first commit of tm4c123bsp, validate on MDK5

2026-10-02 14:23:19 +08:00 · 2020-06-24 19:54:42 +08:00
parent 3408c57d9e
commit aebdcaccbb
149 changed files with 153048 additions and 0 deletions
@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "board/Kconfig"
+
@@ -0,0 +1,123 @@
+# BSP README 模板
+
+## 简介
+
+本文档为ek-tm4c123gxl开发板的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+【此处简单介绍一下开发板】
+
+开发板外观如下图所示：
+
+![](E:\00MyWorkSpace\tm4c123_rtos\tm4c123bsp\figures\board.jpg)
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：TM4C123Gh6PM，主频 80MHz，256KB FLASH ，32KB RAM
+- 外部 RAM：型号，xMB
+- 外部 FLASH：型号，xMB
+- 常用外设
+  - LED：1个三色，（红色，PF1），（蓝色，PF2）,（绿色，PF3）
+  - 按键：2个，SW1（PF4），SW2（兼具唤醒功能，PF0）
+- 常用接口：ICDI（具串口功能）、USB接口
+- 调试接口，ICDI
+
+开发板更多详细信息请参考【TI】 [TM4C123G开发板介绍](https://www.ti.com/tool/EK-TM4C123GXL?DCMP=stellaris-launchpad&HQS=tm4c123g-launchpad)。
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设**      | **支持情况** | **备注**                              |
+| :----------------- | :----------: | :------------------------------------- |
+| USB 转串口        |     支持     |                                       |
+| SPI Flash         |     暂不支持     |                                       |
+| 以太网            |     暂不支持     |                                       |
+| SD卡              |   暂不支持   |                                       |
+| CAN               |   暂不支持   |                                       |
+| **片上外设**      | **支持情况** | **备注**                              |
+| GPIO              |     支持     | PF0, PF1... PF4---> PIN: 0, 1...4 |
+| UART              |     支持     | UART0/1/2/3                        |
+| SPI               |     支持     | SPI0/1/2                            |
+| I2C               |     支持     | 软件 I2C                              |
+| SDIO              |   暂不支持   | 即将支持                              |
+| RTC               |   暂不支持   | 即将支持                              |
+| PWM               |   支持   | PWM0/1/2/3/4/5/6/7             |
+| USB Device        |   暂不支持   | 即将支持                              |
+| USB Host          |   暂不支持   | 即将支持                              |
+| IWG               |   暂不支持   | 即将支持                              |
+| **扩展模块**      | **支持情况** | **备注**                              |
+|     xxx 模块      |   支持   |                                      |
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+    本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+    本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC，打开电源开关。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 ICDI 仿真器下载程序，在通过USB连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，【这里写开发板运行起来之后的现象，如：LED 闪烁等】。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     3.1.1 build Nov 19 2018
+ 2006 - 2018 Copyright by rt-thread team
+msh >
+```
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口0 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
+
+本章节更多详细的介绍请结合 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)学习使用。
+
+## 注意事项
+
+- 本BSP配置片上外设在board/tm4c123gh6pz_config.c/h中进行配置。配置时钟在board.c文件中进行
+
+## 联系人信息
+
+维护人:
+
+-  [AHTYDHD](https://github.com/LYH-ux), 邮箱：<1780328728@qq.com>
@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
@@ -0,0 +1,64 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+# set RTT_ROOT
+#if not os.getenv("RTT_ROOT"): 
+    #RTT_ROOT="rt-thread"
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+tm4c123_library = 'TivaWare_C_series'
+rtconfig.BSP_LIBRARY_TYPE = tm4c123_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, tm4c123_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'Drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+int main(void)
+{
+    int count = 1;
+    /* set LED0 pin mode to output */
+    rt_pin_mode(2, PIN_MODE_OUTPUT);
+
+    while (count++)
+    {
+        rt_pin_write(2, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(2, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+    
+    return RT_EOK;
+}
@@ -0,0 +1,32 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+tm4c123_config.c
+''')
+
+path =  [cwd]
+#path += [cwd + '/CubeMX_Config/Inc']
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += [startup_path_prefix + '/TivaWare_C_series/tm4c123_driverlib/startup/gcc/startup_gcc.c']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += [startup_path_prefix + '/TivaWare_C_series/tm4c123_driverlib/startup/arm/startup_rvmdk.S']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src += [startup_path_prefix + '/TivaWare_C_series/tm4c123_driverlib/startup/iar/startup_rvmdk.S']
+
+
+CPPDEFINES = ['PART_TM4C123GH6PM']
+CPPDEFINES += ['TARGET_IS_TM4C123_RB1']
+CPPDEFINES += ['rvmdk']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+Return('group')
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-07-24     Tanek        the first version
+ * 2018-11-12     Ernest Chen  modify copyright
+ */
+ 
+#include <stdint.h>
+#include <stdbool.h>
+#include "hw_ints.h"
+#include "hw_sysctl.h"
+#include "hw_memmap.h"
+#include "hw_types.h"
+#include "fpu.h"
+#include "debug.h"
+#include "pin_map.h"
+#include "rom.h"
+#include "sysctl.h"
+#include "systick.h"
+#include "hw_ints.h"
+#include "board.h"
+
+// Holds the system core clock, which is the system clock 
+// frequency supplied to the SysTick timer and the processor 
+// core clock.
+uint32_t SystemCoreClock;
+
+
+
+void SystemCoreClockUpdate(void)
+{
+	
+	   FPULazyStackingEnable();
+
+    //
+    // Set the clocking to run directly from the crystal.
+    //
+    SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ |
+                       SYSCTL_OSC_MAIN);
+	
+	  SystemCoreClock = SysCtlClockGet();
+
+}
+
+void SysTickConfig()
+{
+	  SysTickDisable();
+    SysTickPeriodSet(SystemCoreClock/RT_TICK_PER_SECOND);
+    SysTickIntEnable();
+    SysTickEnable();	
+}
+
+/**
+ * This function will initial your board.
+ */
+void rt_hw_board_init()
+{
+    /* System Clock Update */
+    SystemCoreClockUpdate();
+    /* System Tick Configuration */
+    SysTickConfig();
+
+#ifdef RT_USING_SERIAL
+		rt_hw_usart_init();
+#endif
+#ifdef RT_USING_PIN
+	  rt_hw_pin_init();
+#endif
+
+#ifdef RT_USING_PWM
+	  rt_hw_pwm_init();
+#endif
+    /* Call components board initial (use INIT_BOARD_EXPORT()) */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+	
+	  rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+	  
+#endif
+
+
+}
+
+
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+
+
+
+
+
@@ -0,0 +1,47 @@
+#ifndef   _BOARD_H_
+#define   _BOARD_H_
+
+#include <rthw.h>
+#include <rtthread.h>
+
+
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+
+#define TM4C123_SRAM1_START              (0x20000000)      
+#define TM4C123_SRAM1_END                (TM4C123_SRAM1_START + 32 * 1024)   // end address = 0x20000000(base adddress) + 32K(RAM size)
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+extern int Image$$RW_IRAM$$ZI$$Limit;                   // RW_IRAM
+#define HEAP_BEGIN      ((void *)&Image$$RW_IRAM$$ZI$$Limit)
+#endif
+
+#define HEAP_END                       TM4C123_SRAM1_END
+
+#endif
+
+
+
+
+#ifdef RT_USING_PIN
+#include "drv_gpio.h"
+#endif /* RT_USING_PIN */
+
+
+#ifdef RT_USING_SERIAL
+#include "drv_uart.h"
+#endif /* RT_USING_SERIAL */
+
+#ifdef RT_USING_PWM
+#include "drv_pwm.h"
+#endif /* RT_USING_PWM*/
+
+#ifdef RT_USING_SPI
+#include "drv_spi.h"
+#endif /* RT_USING_SPI*/
+
+
+
+
+
+#endif /*_BOARD_H_*/
+
@@ -0,0 +1,78 @@
+//*****************************************************************************
+//
+// hello.icf - Linker configuration file for hello.
+//
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2.1.4.178 of the EK-TM4C123GXL Firmware Package.
+//
+//*****************************************************************************
+
+//
+// Define a memory region that covers the entire 4 GB addressible space of the
+// processor.
+//
+define memory mem with size = 4G;
+
+//
+// Define a region for the on-chip flash.
+//
+define region FLASH = mem:[from 0x00000000 to 0x0003ffff];
+
+//
+// Define a region for the on-chip SRAM.
+//
+define region SRAM = mem:[from 0x20000000 to 0x20007fff];
+
+//
+// Define a block for the heap.  The size should be set to something other
+// than zero if things in the C library that require the heap are used.
+//
+define block HEAP with alignment = 8, size = 0x00000000 { };
+
+//
+// Indicate that the read/write values should be initialized by copying from
+// flash.
+//
+initialize by copy { readwrite };
+
+//
+// Indicate that the noinit values should be left alone.  This includes the
+// stack, which if initialized will destroy the return address from the
+// initialization code, causing the processor to branch to zero and fault.
+//
+do not initialize { section .noinit };
+
+//
+// Place the interrupt vectors at the start of flash.
+//
+place at start of FLASH { readonly section .intvec };
+
+//
+// Place the remainder of the read-only items into flash.
+//
+place in FLASH { readonly };
+
+//
+// Place the RAM vector table at the start of SRAM.
+//
+place at start of SRAM { section VTABLE };
+
+//
+// Place all read/write items into SRAM.
+//
+place in SRAM { readwrite, block HEAP };
@@ -0,0 +1,58 @@
+/******************************************************************************
+ *
+ * hello.ld - Linker configuration file for hello.
+ *
+ * Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
+ * Software License Agreement
+ * 
+ * Texas Instruments (TI) is supplying this software for use solely and
+ * exclusively on TI's microcontroller products. The software is owned by
+ * TI and/or its suppliers, and is protected under applicable copyright
+ * laws. You may not combine this software with "viral" open-source
+ * software in order to form a larger program.
+ * 
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+ * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+ * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+ * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+ * DAMAGES, FOR ANY REASON WHATSOEVER.
+ * 
+ * This is part of revision 2.1.4.178 of the EK-TM4C123GXL Firmware Package.
+ *
+ *****************************************************************************/
+
+MEMORY
+{
+    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
+    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+SECTIONS
+{
+    .text :
+    {
+        _text = .;
+        KEEP(*(.isr_vector))
+        *(.text*)
+        *(.rodata*)
+        _etext = .;
+    } > FLASH
+
+    .data : AT(ADDR(.text) + SIZEOF(.text))
+    {
+        _data = .;
+        _ldata = LOADADDR (.data);
+        *(vtable)
+        *(.data*)
+        _edata = .;
+    } > SRAM
+
+    .bss :
+    {
+        _bss = .;
+        *(.bss*)
+        *(COMMON)
+        _ebss = .;
+    } > SRAM
+}
@@ -0,0 +1,47 @@
+;******************************************************************************
+;
+; hello.sct - Linker configuration file for hello.
+;
+; Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
+; Software License Agreement
+; 
+; Texas Instruments (TI) is supplying this software for use solely and
+; exclusively on TI's microcontroller products. The software is owned by
+; TI and/or its suppliers, and is protected under applicable copyright
+; laws. You may not combine this software with "viral" open-source
+; software in order to form a larger program.
+; 
+; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+; DAMAGES, FOR ANY REASON WHATSOEVER.
+; 
+; This is part of revision 2.1.4.178 of the EK-TM4C123GXL Firmware Package.
+;
+;******************************************************************************
+
+LR_IROM 0x00000000 0x00040000
+{
+    ;
+    ; Specify the Execution Address of the code and the size.
+    ;
+    ER_IROM 0x00000000 0x00040000
+    {
+        *.o (RESET, +First)
+        * (InRoot$$Sections, +RO)
+    }
+
+    ;
+    ; Specify the Execution Address of the data area.
+    ;
+    RW_IRAM 0x20000000 0x00008000
+    {
+        ;
+        ; Uncomment the following line in order to use IntRegister().
+        ;
+        ;* (vtable, +First)
+        * (+RW, +ZI)
+    }
+}
@@ -0,0 +1,77 @@
+#include "stdbool.h"
+#include "stdint.h"
+#include "hw_memmap.h"
+#include "pin_map.h"
+#include "sysctl.h"
+#include "pwm.h"
+#include "gpio.h"
+#include "uart.h"
+#include "adc.h"
+#include "ssi.h"
+
+#include "tm4c123_config.h"
+
+
+
+
+void uart_hw_config(void)
+{
+	  SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
+    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
+	  GPIOPinConfigure(GPIO_PA0_U0RX);
+    GPIOPinConfigure(GPIO_PA1_U0TX);
+    GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
+	
+	  SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);
+    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
+	  GPIOPinConfigure(GPIO_PC4_U1RX);
+    GPIOPinConfigure(GPIO_PC5_U1TX);
+    GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_4 | GPIO_PIN_5);
+	  
+}
+
+
+
+void pwm_hw_config(void)
+{
+	SysCtlPWMClockSet(SYSCTL_PWMDIV_2);
+   //GPIO port D needs to be enabled so these pins can be used.
+	SysCtlPeripheralEnable(SYSCTL_PERIPH_PWM1);
+    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
+
+     // Configure the GPIO pin muxing to select PWM functions for these pins.
+    GPIOPinConfigure(GPIO_PF2_M1PWM6);
+    GPIOPinConfigure(GPIO_PF3_M1PWM7);
+
+     // Configure the GPIO pad for PWM function on pins PF2 and PF3
+    GPIOPinTypePWM(GPIO_PORTF_BASE, GPIO_PIN_2|GPIO_PIN_3);	
+	 
+}
+
+
+void adc_hw_config(void)
+{
+    // The ADC0 peripheral must be enabled for use.
+    //
+    SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
+
+    // GPIO port D needs to be enabled
+    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
+
+    // Select the analog ADC function for these pins.
+    GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3); 
+}
+
+
+void  spi_hw_config(void)
+{
+    SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
+    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
+    GPIOPinConfigure(GPIO_PA2_SSI0CLK);
+    //GPIOPinConfigure(GPIO_PA3_SSI0FSS);
+    GPIOPinConfigure(GPIO_PA4_SSI0RX);
+    GPIOPinConfigure(GPIO_PA5_SSI0TX);
+    GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_2);
+
+}
+
@@ -0,0 +1,23 @@
+#ifndef _TM4C123GH6PZ_CONFIG_H_
+#define _TM4C123GH6PZ_CONFIG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+	
+	
+	
+
+void uart_hw_config(void);	
+void pwm_hw_config(void);	
+void adc_hw_config(void);
+void spi_hw_config(void);	
+	
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /*_TM4C123GH6PZ_CONFIG_H_*/
+
@@ -0,0 +1,101 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+""")
+
+if GetDepend(['RT_USING_PIN']):
+    src += ['drv_gpio.c']
+    
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['drv_uart.c']
+
+if GetDepend(['RT_USING_HWTIMER']):
+    src += ['drv_hwtimer.c']
+
+if GetDepend(['RT_USING_PWM']):
+    src += ['drv_pwm.c']
+
+if GetDepend(['RT_USING_SPI']):
+    src += ['drv_spi.c']
+
+if GetDepend(['RT_USING_QSPI']):
+    src += ['drv_qspi.c']
+
+if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
+    if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'):
+        src += ['drv_soft_i2c.c']
+
+if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']):
+    src += ['drv_eth.c']
+
+if GetDepend(['RT_USING_ADC']):
+    src += Glob('drv_adc.c')
+
+if GetDepend(['RT_USING_CAN']):
+    src += ['drv_can.c']
+
+if GetDepend(['RT_USING_PM', 'SOC_SERIES_STM32L4']):
+    src += ['drv_pm.c']
+    src += ['drv_lptim.c']
+
+if GetDepend('BSP_USING_SDRAM'):
+    src += ['drv_sdram.c']
+
+if GetDepend('BSP_USING_LCD'):
+    src += ['drv_lcd.c']
+
+if GetDepend('BSP_USING_LCD_MIPI'):
+    src += ['drv_lcd_mipi.c']
+
+if GetDepend('BSP_USING_ONCHIP_RTC'):
+    src += ['drv_rtc.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F0']):
+    src += ['drv_flash/drv_flash_f0.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F1']):
+    src += ['drv_flash/drv_flash_f1.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F2']):
+    src += ['drv_flash/drv_flash_f2.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F4']):
+    src += ['drv_flash/drv_flash_f4.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F7']):
+    src += ['drv_flash/drv_flash_f7.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32L4']):
+    src += ['drv_flash/drv_flash_l4.c']
+	
+if GetDepend('RT_USING_HWCRYPTO'):
+    src += ['drv_crypto.c']
+	
+if GetDepend(['BSP_USING_WDT']):
+    src += ['drv_wdt.c']
+
+if GetDepend(['BSP_USING_SDIO']):
+    src += ['drv_sdio.c']
+
+if GetDepend(['BSP_USING_USBD']):
+    src += ['drv_usbd.c']
+
+if GetDepend(['BSP_USING_PULSE_ENCODER']):
+    src += ['drv_pulse_encoder.c']
+
+#src += ['drv_common.c']
+
+path =  [cwd]
+path += [cwd + '/config']
+
+if GetDepend('BSP_USING_ON_CHIP_FLASH'):
+    path += [cwd + '/drv_flash']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')
@@ -0,0 +1,45 @@
+#ifndef _ADC_CONFIG_H_
+#define _ADC_CONFIG_H_
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef BSP_USING_ADC0
+#ifndef ADC0_CONFIG
+#define ADC0_CONFIG                             \
+    {                                           \
+        .name                    ="adc0",       \
+        .adcbase                 = ADC0_BASE,    \
+        .channel                 = 0 ,           \
+		.sequence                = 2 ,           \
+		.trigermode              = ADC_TRIGGER_PROCESSOR,   \
+        .sequencepriority        = 0             \
+    }
+#endif /* ADC0_CONFIG */
+#endif /* BSP_USING_ADC0 */
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                             \
+    {                                           \
+        .name                    = "adc1",       \
+        .adcbase                 = ADC1_BASE,    \
+        .channel                 = 0     ,        \
+		.sequence                = 3     ,        \
+		.syncMode                = ADC_TRIGGER_PROCESSOR,   \
+        .sequencepriority        = 0              \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */		
+				
+	
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /*_ADC_CONFIG_H_*/
@@ -0,0 +1,114 @@
+#ifndef _PWM_CONFIG_H_
+#define _PWM_CONFIG_H_
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+	
+#ifdef BSP_USING_PWM0
+#ifndef PWM0_CONFIG
+#define PWM0_CONFIG                             \
+    {                                           \
+        .name                    = "pwm0",       \
+        .channel                 = 0     ,        \
+		.counterMode             = PWM_GEN_MODE_UP_DOWN , \
+		.syncMode                = PWM_GEN_MODE_NO_SYNC   \
+    }
+#endif /* PWM0_CONFIG */
+#endif /* BSP_USING_PWM0 */
+
+#ifdef BSP_USING_PWM1
+#ifndef PWM1_CONFIG
+#define PWM1_CONFIG                             \
+    {                                           \
+        .name                    = "pwm1",       \
+        .channel                 = 0     ,        \
+		.counterMode             = PWM_GEN_MODE_UP_DOWN , \
+		.syncMode                = PWM_GEN_MODE_NO_SYNC   \
+    }
+#endif /* PWM1_CONFIG */
+#endif /* BSP_USING_PWM1 */		
+	
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+        .name                    = "pwm2",       \
+        .channel                 = 0     ,        \
+		.counterMode             = PWM_GEN_MODE_UP_DOWN , \
+		.syncMode                = PWM_GEN_MODE_NO_SYNC   \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+        .name                    = "pwm3",       \
+        .channel                 = 0     ,        \
+		.counterMode             = PWM_GEN_MODE_UP_DOWN , \
+		.syncMode                = PWM_GEN_MODE_NO_SYNC   \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+        .name                    = "pwm4",       \
+        .channel                 = 0     ,        \
+		.counterMode             = PWM_GEN_MODE_UP_DOWN , \
+		.syncMode                = PWM_GEN_MODE_NO_SYNC   \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+        .name                    = "pwm5",       \
+        .channel                 = 0     ,        \
+		.counterMode             = PWM_GEN_MODE_UP_DOWN , \
+		.syncMode                = PWM_GEN_MODE_NO_SYNC   \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */	
+		
+#ifdef BSP_USING_PWM6
+#ifndef PWM6_CONFIG
+#define PWM6_CONFIG                             \
+    {                                           \
+        .name                    = "pwm6",       \
+        .channel                 = 0    ,         \
+		.counterMode             = PWM_GEN_MODE_UP_DOWN , \
+		.syncMode                = PWM_GEN_MODE_NO_SYNC   \
+    }
+#endif /* PWM6_CONFIG */
+#endif /* BSP_USING_PWM6 */	
+		
+#ifdef BSP_USING_PWM7
+#ifndef PWM7_CONFIG
+#define PWM7_CONFIG                             \
+    {                                           \
+        .name                    = "pwm7",       \
+        .channel                 = 0     ,        \
+		.counterMode             = PWM_GEN_MODE_UP_DOWN , \
+		.syncMode                = PWM_GEN_MODE_NO_SYNC   \
+    }
+#endif /* PWM7_CONFIG */
+#endif /* BSP_USING_PWM7 */	
+	
+			
+	
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /*_PWM_CONFIG_H_*/
+
@@ -0,0 +1,56 @@
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI0
+#ifndef SPI0_BUS_CONFIG
+#define SPI0_BUS_CONFIG                             \
+    {                                               \
+        .base = SSI0_BASE,                           \
+        .bus_name = "spi0",                         \
+    }
+#endif /* SPI0_BUS_CONFIG */
+#endif /* BSP_USING_SPI0 */
+
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .base = SSI1_BASE,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .base = SSI2_BASE,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .base = SSI3_BASE,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
@@ -0,0 +1,67 @@
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(BSP_USING_UART0)
+#ifndef UART0_CONFIG
+#define UART0_CONFIG                                                \
+    {                                                               \
+        .name = "uart0",                                            \
+			  .uartbase = UART0_BASE,                                     \
+			  .baudrate = 115200,                                         \
+			  .mode     = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |     \
+                             UART_CONFIG_PAR_NONE                   \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1*/	
+	
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+			  .uartbase = UART1_BASE,                                     \
+			  .baudrate = 115200,                                         \
+			  .mode     = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |     \
+                             UART_CONFIG_PAR_NONE                   \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1*/
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+				.uartbase = UART2_BASE,                                     \
+			  .baudrate = 115200,                                         \
+			  .mode     = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |     \
+                             UART_CONFIG_PAR_NONE                   \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2*/
+		
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+			  .uartbase = UART3_BASE,                                     \
+			  .baudrate = 115200,                                         \
+			  .mode     = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |     \
+                             UART_CONFIG_PAR_NONE                   \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3*/		
+	
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
@@ -0,0 +1,164 @@
+#include "drv_adc.h"
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+#include "hw_memmap.h"
+#include "adc.h"
+#include "sysctl.h"
+
+
+
+#ifdef  RT_USING_ADC
+
+#include "adc_config.h"
+#include "tm4c123_config.h"
+
+
+#define LOG_TAG             "drv.adc"
+#include <drv_log.h>
+
+static struct tm4c123_adc_config adc_config[] =
+{
+#ifdef BSP_USING_ADC0
+    ADC0_CONFIG,
+#endif
+
+#ifdef BSP_USING_ADC1
+    ADC1_CONFIG,
+#endif
+
+};
+
+struct tm4c123_adc
+{
+    struct tm4c123_adc_config *config;
+    struct rt_adc_device adc_device;
+};
+
+static struct tm4c123_adc   adc_obj[sizeof(adc_config) / sizeof(adc_config[0])]={0};
+
+static rt_err_t tm4c123_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
+{
+    RT_ASSERT(device != RT_NULL);
+    //stm32_adc_handler = device->parent.user_data;
+
+    if (enabled)
+    {
+        ADCSequenceEnable(ADC0_BASE, 2);
+        ADCIntClear(ADC0_BASE, 2);
+    }
+    else
+    {
+        ADCSequenceDisable(ADC0_BASE, 2);
+    }
+
+    return RT_EOK;
+}
+
+
+static rt_err_t tm4c123_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(value != RT_NULL);
+    
+    uint32_t    pui32ADC0Value[4]={0};
+
+    // Trigger the ADC conversion.
+    //
+    ADCProcessorTrigger(ADC0_BASE, 2);
+
+    //
+    // Wait for conversion to be completed.
+    //
+    while(!ADCIntStatus(ADC0_BASE, 2, false))
+    {
+    }
+
+    //
+    // Clear the ADC interrupt flag.
+    //
+    ADCIntClear(ADC0_BASE, 2);
+
+    //
+    // Read ADC Value.
+    //
+    ADCSequenceDataGet(ADC0_BASE, 2, pui32ADC0Value);
+
+
+    /* get ADC value */
+    *value = (rt_uint32_t)pui32ADC0Value[channel];
+
+    return RT_EOK;
+}
+
+static const struct rt_adc_ops tm4c123_adc_ops =
+{
+    .enabled = tm4c123_adc_enabled,
+    .convert = tm4c123_get_adc_value,
+};
+
+
+static rt_err_t tm4c123_hw_adc_init(struct tm4c123_adc *device)
+{
+    
+    uint32_t  adcbase = device->config->adcbase;
+    uint32_t  sequencenum = device->config->sequence;
+
+    ADCSequenceConfigure(adcbase, sequencenum, 
+                        device->config->trigermode, 0); 
+
+    ADCSequenceStepConfigure(ADC0_BASE, 2, 0, ADC_CTL_CH7 );
+    ADCSequenceStepConfigure(ADC0_BASE, 2, 1, ADC_CTL_CH6 | ADC_CTL_IE );
+    ADCSequenceStepConfigure(ADC0_BASE, 2, 2, ADC_CTL_CH5 );
+    //Tell the ADC logic
+    // that this is the last conversion on sequence 3 (ADC_CTL_END).  
+    ADCSequenceStepConfigure(ADC0_BASE, 2, 3, ADC_CTL_CH4 | ADC_CTL_IE |
+                              ADC_CTL_END);
+	  return RT_EOK;
+}
+
+
+static int tm4c123_adc_init(void)
+{
+	  int i = 0;
+	  rt_size_t obj_num = sizeof(adc_obj) / sizeof(struct tm4c123_adc);
+	  rt_err_t result = RT_EOK;
+
+    adc_hw_config(); 
+
+    for (i = 0; i < obj_num; i++)
+    {
+        /* ADC init */
+        adc_obj[i].config = &adc_config[i];
+        
+
+       if(tm4c123_hw_adc_init(&adc_obj[i])!= RT_EOK)
+        {
+            LOG_E("%s init failed", adc_obj[i].config->name);
+            result = -RT_ERROR;
+            return result;
+        }
+        else
+        {
+            LOG_D("%s init success", adc_obj[i].config->name);
+            
+            /* register adc device */
+            if (rt_hw_adc_register(&adc_obj[i].adc_device, adc_obj[i].config->name, &tm4c123_adc_ops,RT_NULL) == RT_EOK)
+            {
+                LOG_D("%s register success", adc_obj[i].config->name);
+            }
+            else
+            {
+                LOG_E("%s register failed", adc_obj[i].config->name);
+                result = -RT_ERROR;
+            }
+        }
+    }
+
+    return result;
+}
+INIT_APP_EXPORT(tm4c123_adc_init);
+
+#endif  /*RT_UING_ADC*/
@@ -0,0 +1,20 @@
+#ifndef _DRV_ADC_H_
+#define _DRV_ADC_H_
+
+#include<stdint.h>
+#include<rtthread.h>
+#include<rtdevice.h>
+#include<rthw.h>
+
+struct tm4c123_adc_config
+{
+        const char  *name;       
+        uint32_t    adcbase;   
+        uint32_t    channel;           
+		uint32_t    sequence;                      
+		uint32_t    trigermode;               
+        uint32_t    sequencepriority;                   
+};
+
+
+#endif /*_DRV_ADC_H_*/
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-5      SummerGift   first version
+ */
+
+#ifndef __DRV_FLASH_H__
+#define __DRV_FLASH_H__
+
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+#include <drv_common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size);
+int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size);
+int stm32_flash_erase(rt_uint32_t addr, size_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __DRV_FLASH_H__ */
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-5      SummerGift   first version
+ */
+
+#include "board.h"
+
+#ifdef BSP_USING_ON_CHIP_FLASH
+#include "drv_config.h"
+#include "drv_flash.h"
+
+#if defined(PKG_USING_FAL)
+#include "fal.h"
+#endif
+
+//#define DRV_DEBUG
+#define LOG_TAG                "drv.flash"
+#include <drv_log.h>
+
+/**
+  * @brief  Gets the page of a given address
+  * @param  Addr: Address of the FLASH Memory
+  * @retval The page of a given address
+  */
+static uint32_t GetPage(uint32_t addr)
+{
+    uint32_t page = 0;
+    page = RT_ALIGN_DOWN(addr, FLASH_PAGE_SIZE);
+    return page;
+}
+
+/**
+ * Read data from flash.
+ * @note This operation's units is word.
+ *
+ * @param addr flash address
+ * @param buf buffer to store read data
+ * @param size read bytes size
+ *
+ * @return result
+ */
+int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
+{
+    size_t i;
+
+    if ((addr + size) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    for (i = 0; i < size; i++, buf++, addr++)
+    {
+        *buf = *(rt_uint8_t *) addr;
+    }
+
+    return size;
+}
+
+/**
+ * Write data to flash.
+ * @note This operation's units is word.
+ * @note This operation must after erase. @see flash_erase.
+ *
+ * @param addr flash address
+ * @param buf the write data buffer
+ * @param size write bytes size
+ *
+ * @return result
+ */
+int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
+{
+    rt_err_t result        = RT_EOK;
+    rt_uint32_t end_addr   = addr + size;
+
+    if (addr % 4 != 0)
+    {
+        LOG_E("write addr must be 4-byte alignment");
+        return -RT_EINVAL;
+    }
+
+    if ((end_addr) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    HAL_FLASH_Unlock();
+
+    while (addr < end_addr)
+    {
+        if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, addr, *((rt_uint32_t *)buf)) == HAL_OK)
+        {
+            if (*(rt_uint32_t *)addr != *(rt_uint32_t *)buf)
+            {
+                result = -RT_ERROR;
+                break;
+            }
+            addr += 4;
+            buf  += 4;
+        }
+        else
+        {
+            result = -RT_ERROR;
+            break;
+        }
+    }
+
+    HAL_FLASH_Lock();
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    return size;
+}
+
+/**
+ * Erase data on flash.
+ * @note This operation is irreversible.
+ * @note This operation's units is different which on many chips.
+ *
+ * @param addr flash address
+ * @param size erase bytes size
+ *
+ * @return result
+ */
+int stm32_flash_erase(rt_uint32_t addr, size_t size)
+{
+    rt_err_t result = RT_EOK;
+    uint32_t PAGEError = 0;
+
+    /*Variable used for Erase procedure*/
+    FLASH_EraseInitTypeDef EraseInitStruct;
+
+    if ((addr + size) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    HAL_FLASH_Unlock();
+
+    /* Fill EraseInit structure*/
+    EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
+    EraseInitStruct.PageAddress = GetPage(addr);
+    EraseInitStruct.NbPages     = (size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE;
+
+    if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK)
+    {
+        result = -RT_ERROR;
+        goto __exit;
+    }
+
+__exit:
+    HAL_FLASH_Lock();
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
+    return size;
+}
+
+#if defined(PKG_USING_FAL)
+
+static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
+static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
+static int fal_flash_erase(long offset, size_t size);
+
+const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, FLASH_PAGE_SIZE, {NULL, fal_flash_read, fal_flash_write, fal_flash_erase} };
+
+static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
+{
+    return stm32_flash_read(stm32_onchip_flash.addr + offset, buf, size);
+}
+
+static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size)
+{
+    return stm32_flash_write(stm32_onchip_flash.addr + offset, buf, size);
+}
+
+static int fal_flash_erase(long offset, size_t size)
+{
+    return stm32_flash_erase(stm32_onchip_flash.addr + offset, size);
+}
+
+#endif
+#endif /* BSP_USING_ON_CHIP_FLASH */
@@ -0,0 +1,199 @@
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "hw_memmap.h"
+#include "sysctl.h"
+#include "gpio.h"
+#include "pin_map.h"
+#include "interrupt.h"
+#include "rom_map.h"
+#include "drv_gpio.h"
+
+
+#ifdef RT_USING_PIN
+
+static const struct pin_index pins[] = 
+{
+    _TM4C_PIN(0 ,F, 0 ),
+    _TM4C_PIN(1 ,F, 1 ),
+    _TM4C_PIN(2 ,F, 2 ),
+    _TM4C_PIN(3 ,F, 3 ),
+    _TM4C_PIN(4 ,F, 4 )
+};
+
+
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL}
+};
+
+
+static uint32_t pin_irq_enable_mask=0;
+
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+	
+	
+static const struct pin_index *get_pin(uint8_t pin)
+{
+    const struct pin_index *index;
+
+    if (pin < ITEM_NUM(pins))
+    {
+        index = &pins[pin];
+        if (index->index == -1)
+            index = RT_NULL;
+    }
+    else
+    {
+        index = RT_NULL;
+    }
+    return index;
+};
+
+
+static void tm4c123_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    const struct pin_index *index;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+				
+		if(mode == PIN_MODE_INPUT)
+		{
+        GPIOPinTypeGPIOInput(index ->gpioBaseAddress, index->pin);
+		}
+		else if(mode == PIN_MODE_OUTPUT)
+		{
+			  GPIOPinTypeGPIOOutput(index->gpioBaseAddress, index->pin);
+		}
+		else if(mode == PIN_MODE_INPUT_PULLUP)
+		{
+				
+    //
+    // Make the pin(s) be inputs.
+    //
+				GPIODirModeSet(index->gpioBaseAddress, index->pin, GPIO_DIR_MODE_IN);
+    //
+    // Set the pad(s) for standard pullup operation.
+    //
+				GPIOPadConfigSet(index->gpioBaseAddress, index->pin, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
+		}
+		else if(mode == PIN_MODE_INPUT_PULLDOWN)
+		{		
+    //
+    // Make the pin(s) be inputs.
+    //
+				GPIODirModeSet(index->gpioBaseAddress, index->pin, GPIO_DIR_MODE_IN);
+    //
+    // Set the pad(s) for standard pulldown operation.
+    //
+				GPIOPadConfigSet(index->gpioBaseAddress, index->pin, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPD);
+		}
+		else if(mode == PIN_MODE_OUTPUT_OD)
+		{
+		//
+		// Set the pad(s) for standard push-pull operation.
+				GPIOPadConfigSet(index->gpioBaseAddress, index->pin, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD);
+		//
+		// Make the pin(s) be outputs.
+				GPIODirModeSet(index->gpioBaseAddress, index->pin, GPIO_DIR_MODE_OUT);
+		}
+		
+}
+
+static void tm4c123_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t ui8Val)
+{
+    const struct pin_index *index;
+	  index = get_pin(pin);
+	  if( index == RT_NULL)
+		{
+			    return;
+		}
+		if(ui8Val)
+		{
+					GPIOPinWrite(index ->gpioBaseAddress, index->pin, index->pin );
+		}
+		else
+		{
+					GPIOPinWrite(index ->gpioBaseAddress, index->pin, 0 );
+		}		
+}
+
+
+static int tm4c123_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    const struct pin_index *index;
+		int value = 0;
+	  
+		index = get_pin(pin);
+	  if( index == RT_NULL)
+		{
+			    return value;
+		}
+	  value = GPIOPinRead(index ->gpioBaseAddress , index ->pin );
+	
+    return value;
+}
+
+static rt_err_t tm4c123_pin_attach_irq(rt_device_t device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args )
+{
+    //const struct pin_index *index;
+	
+    return RT_EOK;
+}
+
+static rt_err_t tm4c123_pin_dettach_irq(rt_device_t device, rt_int32_t pin)
+{
+    //const struct pin_index *index;
+	
+    return RT_EOK;
+}
+
+
+static rt_err_t tm4c123_pin_irq_enable(rt_device_t device, rt_base_t pin,
+                                     rt_uint32_t enabled)
+{
+    //const struct pin_index *index;
+    //const struct pin_irq_map *irqmap;
+    return RT_EOK;
+}
+
+
+const static struct rt_pin_ops _tm4c123_pin_ops =
+{
+    tm4c123_pin_mode,
+    tm4c123_pin_write,
+    tm4c123_pin_read,
+    tm4c123_pin_attach_irq,
+    tm4c123_pin_dettach_irq,
+    tm4c123_pin_irq_enable,
+};
+
+int rt_hw_pin_init(void)
+{
+    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
+    return rt_device_pin_register("pin", &_tm4c123_pin_ops, RT_NULL);
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+#endif   /*RT_USING_PIN*/
@@ -0,0 +1,29 @@
+#ifndef _DRV_GPIO_H_
+#define _DRV_GPIO_H_
+
+#include <stdint.h>
+#include <rtthread.h>
+
+#define _TM4C_PIN(index, gpioport, gpio_index)                          \
+        {                                                               \
+				     index, GPIO_PORT##gpioport##_BASE, GPIO_PIN_##gpio_index   \
+				}
+				
+#define _TM4C_PIN_RESERVE                                              \
+        {                                                               \
+				    -1, 0, 0                                                    \
+				}
+				
+
+/* TM4C123 GPIO driver*/
+struct pin_index
+{
+    int index;
+    uint32_t gpioBaseAddress;
+    uint32_t pin;
+};
+
+extern int rt_hw_pin_init(void);
+
+#endif  /*_DRV_GPIO_H_*/
+
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-15     SummerGift   first version
+ */
+
+/*
+ * NOTE: DO NOT include this file on the header file.
+ */
+
+#ifndef LOG_TAG
+#define DBG_TAG               "drv"
+#else
+#define DBG_TAG               LOG_TAG
+#endif /* LOG_TAG */
+
+#ifdef DRV_DEBUG
+#define DBG_LVL               DBG_LOG
+#else
+#define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+
+#include <rtdbg.h>
@@ -0,0 +1,28 @@
+#ifndef _DRV_PWM_H_
+#define _DRV_PWM_H_
+
+
+#include<rtdevice.h>
+#include<rthw.h>
+
+
+struct tm4c123_pwm
+{
+	struct tm4c123_pwm_config *config;
+	struct rt_device_pwm  pwm_device;
+};
+
+/* tm4c123 config class */
+struct tm4c123_pwm_config
+{
+	rt_uint8_t channel;
+	char *name;
+	uint32_t   counterMode;
+	uint32_t   syncMode;
+};
+
+
+int rt_hw_pwm_init(void);
+
+
+#endif /*_DRV_PWM_H_*/
@@ -0,0 +1,45 @@
+#ifndef __DRV_SPI_H_
+#define __DRV_SPI_H_
+
+#include <rtdevice.h>
+#include <rthw.h>
+#include "drivers/spi.h"
+
+rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint32_t portindex, uint32_t  cs_gpiobase, uint32_t cs_gpio_pin);
+
+struct tm4c123_hw_spi_cs
+{
+    uint32_t portbase;
+    uint32_t GPIO_Pin;
+};
+
+struct tm4c123_spi_config
+{
+    uint32_t   base;
+    char *     bus_name;
+};
+
+/* tm4c123 spi dirver class */
+struct tm4c123_spi
+{
+    struct tm4c123_spi_config *config;
+    struct rt_spi_configuration *cfg;
+
+    struct rt_spi_bus spi_bus;
+};
+
+struct tm4c123_spi_device
+{
+    rt_uint32_t pin;
+    char *bus_name;
+    char *device_name;
+};
+
+#define SPI_USING_RX_DMA_FLAG   (1<<0)
+#define SPI_USING_TX_DMA_FLAG   (1<<1)
+
+#endif /*__DRV_SPI_H_ */
+
+
+
+
@@ -0,0 +1,38 @@
+#ifndef _DRV_UART_H_
+#define _DRV_UART_H_
+
+#include <stdint.h>
+#include <rthw.h>
+#include <rtthread.h>
+#include "rtdevice.h"
+
+/* tm4c123 config class */
+struct tm4c123_uart_config
+{
+    const char *name;
+	  uint32_t    uartbase;
+	  uint32_t    baudrate;
+	  uint32_t    mode;
+    //struct dma_config *dma_rx;
+    //struct dma_config *dma_tx;
+};
+
+
+/* tm4c123 uart dirver class */
+struct tm4c123_uart
+{    
+    struct tm4c123_uart_config *config;
+    uint32_t   uartintbase;	
+    
+#ifdef RT_SERIAL_USING_DMA
+#endif
+	
+    rt_uint16_t uart_dma_flag;
+    struct rt_serial_device serial;
+};
+
+extern int rt_hw_usart_init(void);
+
+#endif /*_DRV_UART_H_*/
+
+
@@ -0,0 +1,73 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+src = Split("""
+tm4c123_driverlib/src/sysctl.c
+tm4c123_driverlib/src/systick.c
+tm4c123_driverlib/src/interrupt.c
+tm4c123_driverlib/src/fpu.c
+tm4c123_driverlib/src/cpu.c
+tm4c123_driverlib/src/gpio.c
+""")
+
+#if GetDepend(['RT_USING_PIN']):
+   
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['tm4c123_driverlib/src/uart.c']
+
+#if GetDepend(['RT_USING_I2C']):
+
+    
+if GetDepend(['RT_USING_SPI']):
+    src += ['tm4c123_driverlib/src/ssi.c']
+
+#if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']):
+
+
+#if GetDepend(['RT_USING_CAN']):
+
+
+#if GetDepend(['RT_USING_HWTIMER']) 
+
+if GetDepend(['RT_USING_PWM']) or GetDepend(['RT_USING_PULSE_ENCODER']):
+    src += ['tm4c123_driverlib/src/pwm.c']    
+
+#if GetDepend(['BSP_USING_ETH']):
+
+
+if GetDepend(['RT_USING_ADC']):
+    src += ['tm4c123_driverlib/src/adc.c']
+
+#if GetDepend(['RT_USING_RTC']):
+
+
+#if GetDepend(['RT_USING_WDT']):
+
+
+#if GetDepend(['RT_USING_SDIO']):
+
+
+#if GetDepend(['RT_USING_AUDIO']):
+
+
+#if GetDepend(['RT_USING_MTD_NOR']):
+
+
+#if GetDepend(['RT_USING_MTD_NAND']):
+
+
+#if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
+
+
+path = [cwd + '/tm4c123_driverlib', 
+    cwd + '/tm4c123_driverlib/driverlib',
+    cwd + '/tm4c123_driverlib/driverlib/inc']
+
+group = DefineGroup('TM4C123_HAL', src, depend = [''], CPPPATH = path)
+
+Return('group')
@@ -0,0 +1,141 @@
+//*****************************************************************************
+//
+// comp.h - Prototypes for the analog comparator driver.
+//
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_COMP_H__
+#define __DRIVERLIB_COMP_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to ComparatorConfigure() as the ui32Config
+// parameter.  For each group (in other words, COMP_TRIG_xxx, COMP_INT_xxx, and
+// so on), one of the values may be selected and combined together with values
+// from the other groups via a logical OR.
+//
+//*****************************************************************************
+#define COMP_TRIG_NONE          0x00000000  // No ADC trigger
+#define COMP_TRIG_HIGH          0x00000880  // Trigger when high
+#define COMP_TRIG_LOW           0x00000800  // Trigger when low
+#define COMP_TRIG_FALL          0x00000820  // Trigger on falling edge
+#define COMP_TRIG_RISE          0x00000840  // Trigger on rising edge
+#define COMP_TRIG_BOTH          0x00000860  // Trigger on both edges
+#define COMP_INT_HIGH           0x00000010  // Interrupt when high
+#define COMP_INT_LOW            0x00000000  // Interrupt when low
+#define COMP_INT_FALL           0x00000004  // Interrupt on falling edge
+#define COMP_INT_RISE           0x00000008  // Interrupt on rising edge
+#define COMP_INT_BOTH           0x0000000C  // Interrupt on both edges
+#define COMP_ASRCP_PIN          0x00000000  // Dedicated Comp+ pin
+#define COMP_ASRCP_PIN0         0x00000200  // Comp0+ pin
+#define COMP_ASRCP_REF          0x00000400  // Internal voltage reference
+#define COMP_OUTPUT_NORMAL      0x00000000  // Comparator output normal
+#define COMP_OUTPUT_INVERT      0x00000002  // Comparator output inverted
+
+//*****************************************************************************
+//
+// Values that can be passed to ComparatorSetRef() as the ui32Ref parameter.
+//
+//*****************************************************************************
+#define COMP_REF_OFF            0x00000000  // Turn off the internal reference
+#define COMP_REF_0V             0x00000300  // Internal reference of 0V
+#define COMP_REF_0_1375V        0x00000301  // Internal reference of 0.1375V
+#define COMP_REF_0_275V         0x00000302  // Internal reference of 0.275V
+#define COMP_REF_0_4125V        0x00000303  // Internal reference of 0.4125V
+#define COMP_REF_0_55V          0x00000304  // Internal reference of 0.55V
+#define COMP_REF_0_6875V        0x00000305  // Internal reference of 0.6875V
+#define COMP_REF_0_825V         0x00000306  // Internal reference of 0.825V
+#define COMP_REF_0_928125V      0x00000201  // Internal reference of 0.928125V
+#define COMP_REF_0_9625V        0x00000307  // Internal reference of 0.9625V
+#define COMP_REF_1_03125V       0x00000202  // Internal reference of 1.03125V
+#define COMP_REF_1_134375V      0x00000203  // Internal reference of 1.134375V
+#define COMP_REF_1_1V           0x00000308  // Internal reference of 1.1V
+#define COMP_REF_1_2375V        0x00000309  // Internal reference of 1.2375V
+#define COMP_REF_1_340625V      0x00000205  // Internal reference of 1.340625V
+#define COMP_REF_1_375V         0x0000030A  // Internal reference of 1.375V
+#define COMP_REF_1_44375V       0x00000206  // Internal reference of 1.44375V
+#define COMP_REF_1_5125V        0x0000030B  // Internal reference of 1.5125V
+#define COMP_REF_1_546875V      0x00000207  // Internal reference of 1.546875V
+#define COMP_REF_1_65V          0x0000030C  // Internal reference of 1.65V
+#define COMP_REF_1_753125V      0x00000209  // Internal reference of 1.753125V
+#define COMP_REF_1_7875V        0x0000030D  // Internal reference of 1.7875V
+#define COMP_REF_1_85625V       0x0000020A  // Internal reference of 1.85625V
+#define COMP_REF_1_925V         0x0000030E  // Internal reference of 1.925V
+#define COMP_REF_1_959375V      0x0000020B  // Internal reference of 1.959375V
+#define COMP_REF_2_0625V        0x0000030F  // Internal reference of 2.0625V
+#define COMP_REF_2_165625V      0x0000020D  // Internal reference of 2.165625V
+#define COMP_REF_2_26875V       0x0000020E  // Internal reference of 2.26875V
+#define COMP_REF_2_371875V      0x0000020F  // Internal reference of 2.371875V
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void ComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp,
+                                uint32_t ui32Config);
+extern void ComparatorRefSet(uint32_t ui32Base, uint32_t ui32Ref);
+extern bool ComparatorValueGet(uint32_t ui32Base, uint32_t ui32Comp);
+extern void ComparatorIntRegister(uint32_t ui32Base, uint32_t ui32Comp,
+                                  void (*pfnHandler)(void));
+extern void ComparatorIntUnregister(uint32_t ui32Base, uint32_t ui32Comp);
+extern void ComparatorIntEnable(uint32_t ui32Base, uint32_t ui32Comp);
+extern void ComparatorIntDisable(uint32_t ui32Base, uint32_t ui32Comp);
+extern bool ComparatorIntStatus(uint32_t ui32Base, uint32_t ui32Comp,
+                                bool bMasked);
+extern void ComparatorIntClear(uint32_t ui32Base, uint32_t ui32Comp);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_COMP_H__
@@ -0,0 +1,75 @@
+//*****************************************************************************
+//
+// cpu.h - Prototypes for the CPU instruction wrapper functions.
+//
+// Copyright (c) 2006-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_CPU_H__
+#define __DRIVERLIB_CPU_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes.
+//
+//*****************************************************************************
+extern uint32_t CPUcpsid(void);
+extern uint32_t CPUcpsie(void);
+extern uint32_t CPUprimask(void);
+extern void CPUwfi(void);
+extern uint32_t CPUbasepriGet(void);
+extern void CPUbasepriSet(uint32_t ui32NewBasepri);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_CPU_H__
@@ -0,0 +1,101 @@
+//*****************************************************************************
+//
+// crc.h - Defines and Macros for CRC module.
+//
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_CRC_H__
+#define __DRIVERLIB_CRC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following defines are used in the ui32Config argument of the
+// ECConfig function.
+//
+//*****************************************************************************
+#define CRC_CFG_INIT_SEED       0x00000000  // Initialize with seed
+#define CRC_CFG_INIT_0          0x00004000  // Initialize to all '0s'
+#define CRC_CFG_INIT_1          0x00006000  // Initialize to all '1s'
+#define CRC_CFG_SIZE_8BIT       0x00001000  // Input Data Size
+#define CRC_CFG_SIZE_32BIT      0x00000000  // Input Data Size
+#define CRC_CFG_RESINV          0x00000200  // Result Inverse Enable
+#define CRC_CFG_OBR             0x00000100  // Output Reverse Enable
+#define CRC_CFG_IBR             0x00000080  // Bit reverse enable
+#define CRC_CFG_ENDIAN_SBHW     0x00000020  // Swap byte in half-word
+#define CRC_CFG_ENDIAN_SHW      0x00000010  // Swap half-word
+#define CRC_CFG_TYPE_P8005      0x00000000  // Polynomial 0x8005
+#define CRC_CFG_TYPE_P1021      0x00000001  // Polynomial 0x1021
+#define CRC_CFG_TYPE_P4C11DB7   0x00000002  // Polynomial 0x4C11DB7
+#define CRC_CFG_TYPE_P1EDC6F41  0x00000003  // Polynomial 0x1EDC6F41
+#define CRC_CFG_TYPE_TCPCHKSUM  0x00000008  // TCP checksum
+
+//*****************************************************************************
+//
+// Function prototypes.
+//
+//*****************************************************************************
+#if 0
+extern void ECClockGatingReqest(uint32_t ui32Base, uint32_t ui32ECIP,
+                                bool bGate);
+#endif
+extern void CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig);
+extern uint32_t CRCDataProcess(uint32_t ui32Base, uint32_t *pui32DataIn,
+                               uint32_t ui32DataLength, bool bPPResult);
+extern void CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data);
+extern uint32_t CRCResultRead(uint32_t ui32Base, bool bPPResult);
+extern void CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_CRC_H__
@@ -0,0 +1,70 @@
+//*****************************************************************************
+//
+// debug.h - Macros for assisting debug of the driver library.
+//
+// Copyright (c) 2006-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_DEBUG_H__
+#define __DRIVERLIB_DEBUG_H__
+
+//*****************************************************************************
+//
+// Prototype for the function that is called when an invalid argument is passed
+// to an API.  This is only used when doing a DEBUG build.
+//
+//*****************************************************************************
+extern void __error__(char *pcFilename, uint32_t ui32Line);
+
+//*****************************************************************************
+//
+// The ASSERT macro, which does the actual assertion checking.  Typically, this
+// will be for procedure arguments.
+//
+//*****************************************************************************
+#ifdef DEBUG
+#define ASSERT(expr) do                                                       \
+                     {                                                        \
+                         if(!(expr))                                          \
+                         {                                                    \
+                             __error__(__FILE__, __LINE__);                   \
+                         }                                                    \
+                     }                                                        \
+                     while(0)
+#else
+#define ASSERT(expr)
+#endif
+
+#endif // __DRIVERLIB_DEBUG_H__
@@ -0,0 +1,140 @@
+//*****************************************************************************
+//
+// des.h - Defines and Macros for the DES module.
+//
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_DES_H__
+#define __DRIVERLIB_DES_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following defines are used to specify the direction with the
+// ui32Config argument in the DESConfig() function.  Only one is permitted.
+//
+//*****************************************************************************
+#define DES_CFG_DIR_DECRYPT     0x00000000
+#define DES_CFG_DIR_ENCRYPT     0x00000004
+
+//*****************************************************************************
+//
+// The following defines are used to specify the operational with the
+// ui32Config argument in the DESConfig() function.  Only one is permitted.
+//
+//*****************************************************************************
+#define DES_CFG_MODE_ECB        0x00000000
+#define DES_CFG_MODE_CBC        0x00000010
+#define DES_CFG_MODE_CFB        0x00000020
+
+//*****************************************************************************
+//
+// The following defines are used to select between single DES and triple DES
+// with the ui32Config argument in the DESConfig() function.  Only one is
+// permitted.
+//
+//*****************************************************************************
+#define DES_CFG_SINGLE          0x00000000
+#define DES_CFG_TRIPLE          0x00000008
+
+//*****************************************************************************
+//
+// The following defines are used with the DESIntEnable(), DESIntDisable() and
+// DESIntStatus() functions.
+//
+//*****************************************************************************
+#define DES_INT_CONTEXT_IN      0x00000001
+#define DES_INT_DATA_IN         0x00000002
+#define DES_INT_DATA_OUT        0x00000004
+#define DES_INT_DMA_CONTEXT_IN  0x00010000
+#define DES_INT_DMA_DATA_IN     0x00020000
+#define DES_INT_DMA_DATA_OUT    0x00040000
+
+//*****************************************************************************
+//
+// The following defines are used with the DESEnableDMA() and DESDisableDMA()
+// functions.
+//
+//*****************************************************************************
+#define DES_DMA_CONTEXT_IN      0x00000080
+#define DES_DMA_DATA_OUT        0x00000040
+#define DES_DMA_DATA_IN         0x00000020
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void DESConfigSet(uint32_t ui32Base, uint32_t ui32Config);
+extern void DESDataRead(uint32_t ui32Base, uint32_t *pui32Dest);
+extern bool DESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest);
+extern bool DESDataProcess(uint32_t ui32Base, uint32_t *pui32Src,
+                           uint32_t *pui32Dest, uint32_t ui32Length);
+extern void DESDataWrite(uint32_t ui32Base, uint32_t *pui32Src);
+extern bool DESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src);
+extern void DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags);
+extern void DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags);
+extern void DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void DESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern uint32_t DESIntStatus(uint32_t ui32Base, bool bMasked);
+extern void DESIntUnregister(uint32_t ui32Base);
+extern bool DESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata);
+extern void DESKeySet(uint32_t ui32Base, uint32_t *pui32Key);
+extern void DESLengthSet(uint32_t ui32Base, uint32_t ui32Length);
+extern void DESReset(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_DES_H__
@@ -0,0 +1,122 @@
+//*****************************************************************************
+//
+// flash.h - Prototypes for the flash driver.
+//
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_FLASH_H__
+#define __DRIVERLIB_FLASH_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to FlashProtectSet(), and returned by
+// FlashProtectGet().
+//
+//*****************************************************************************
+typedef enum
+{
+    FlashReadWrite,                         // Flash can be read and written
+    FlashReadOnly,                          // Flash can only be read
+    FlashExecuteOnly                        // Flash can only be executed
+}
+tFlashProtection;
+
+//*****************************************************************************
+//
+// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and
+// returned from FlashIntStatus().
+//
+//*****************************************************************************
+#define FLASH_INT_PROGRAM     0x00000002 // Programming Interrupt Mask
+#define FLASH_INT_ACCESS      0x00000001 // Access Interrupt Mask
+#define FLASH_INT_EEPROM      0x00000004 // EEPROM Interrupt Mask
+#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask
+#define FLASH_INT_DATA_ERR    0x00000400 // Invalid Data Interrupt Mask
+#define FLASH_INT_ERASE_ERR   0x00000800 // Erase Error Interrupt Mask
+#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern int32_t FlashErase(uint32_t ui32Address);
+extern int32_t FlashProgram(uint32_t *pui32Data, uint32_t ui32Address,
+                            uint32_t ui32Count);
+extern tFlashProtection FlashProtectGet(uint32_t ui32Address);
+extern int32_t FlashProtectSet(uint32_t ui32Address,
+                               tFlashProtection eProtect);
+extern int32_t FlashProtectSave(void);
+extern int32_t FlashUserGet(uint32_t *pui32User0, uint32_t *pui32User1);
+extern int32_t FlashUserSet(uint32_t ui32User0, uint32_t ui32User1);
+extern int32_t FlashAllUserRegisterGet(uint32_t *pui32User0,
+                                       uint32_t *pui32User1,
+                                       uint32_t *pui32User2,
+                                       uint32_t *pui32User3);
+extern int32_t FlashAllUserRegisterSet(uint32_t ui32User0,
+                                       uint32_t ui32User1,
+                                       uint32_t ui32User2,
+                                       uint32_t ui32User3);
+extern int32_t FlashUserSave(void);
+extern int32_t FlashAllUserRegisterSave(void);
+extern void FlashIntRegister(void (*pfnHandler)(void));
+extern void FlashIntUnregister(void);
+extern void FlashIntEnable(uint32_t ui32IntFlags);
+extern void FlashIntDisable(uint32_t ui32IntFlags);
+extern uint32_t FlashIntStatus(bool bMasked);
+extern void FlashIntClear(uint32_t ui32IntFlags);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_FLASH_H__
@@ -0,0 +1,113 @@
+//*****************************************************************************
+//
+// fpu.h - Prototypes for the floatint point manipulation routines.
+//
+// Copyright (c) 2011-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_FPU_H__
+#define __DRIVERLIB_FPU_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to FPUHalfPrecisionSet as the ui32Mode parameter.
+//
+//*****************************************************************************
+#define FPU_HALF_IEEE           0x00000000
+#define FPU_HALF_ALTERNATE      0x04000000
+
+//*****************************************************************************
+//
+// Values that can be passed to FPUNaNModeSet as the ui32Mode parameter.
+//
+//*****************************************************************************
+#define FPU_NAN_PROPAGATE       0x00000000
+#define FPU_NAN_DEFAULT         0x02000000
+
+//*****************************************************************************
+//
+// Values that can be passed to FPUFlushToZeroModeSet as the ui32Mode
+// parameter.
+//
+//*****************************************************************************
+#define FPU_FLUSH_TO_ZERO_DIS   0x00000000
+#define FPU_FLUSH_TO_ZERO_EN    0x01000000
+
+//*****************************************************************************
+//
+// Values that can be passed to FPURoundingModeSet as the ui32Mode parameter.
+//
+//*****************************************************************************
+#define FPU_ROUND_NEAREST       0x00000000
+#define FPU_ROUND_POS_INF       0x00400000
+#define FPU_ROUND_NEG_INF       0x00800000
+#define FPU_ROUND_ZERO          0x00c00000
+
+//*****************************************************************************
+//
+// Prototypes.
+//
+//*****************************************************************************
+extern void FPUEnable(void);
+extern void FPUDisable(void);
+extern void FPUStackingEnable(void);
+extern void FPULazyStackingEnable(void);
+extern void FPUStackingDisable(void);
+extern void FPUHalfPrecisionModeSet(uint32_t ui32Mode);
+extern void FPUNaNModeSet(uint32_t ui32Mode);
+extern void FPUFlushToZeroModeSet(uint32_t ui32Mode);
+extern void FPURoundingModeSet(uint32_t ui32Mode);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_FPU_H__
@@ -0,0 +1,115 @@
+//*****************************************************************************
+//
+// hw_ccm.h - Macros used when accessing the CCM hardware.
+//
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_CCM_H__
+#define __HW_CCM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the EC register offsets.
+//
+//*****************************************************************************
+#define CCM_O_CRCCTRL           0x00000400  // CRC Control
+#define CCM_O_CRCSEED           0x00000410  // CRC SEED/Context
+#define CCM_O_CRCDIN            0x00000414  // CRC Data Input
+#define CCM_O_CRCRSLTPP         0x00000418  // CRC Post Processing Result
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCCTRL register.
+//
+//*****************************************************************************
+#define CCM_CRCCTRL_INIT_M      0x00006000  // CRC Initialization
+#define CCM_CRCCTRL_INIT_SEED   0x00000000  // Use the CRCSEED register context
+                                            // as the starting value
+#define CCM_CRCCTRL_INIT_0      0x00004000  // Initialize to all '0s'
+#define CCM_CRCCTRL_INIT_1      0x00006000  // Initialize to all '1s'
+#define CCM_CRCCTRL_SIZE        0x00001000  // Input Data Size
+#define CCM_CRCCTRL_RESINV      0x00000200  // Result Inverse Enable
+#define CCM_CRCCTRL_OBR         0x00000100  // Output Reverse Enable
+#define CCM_CRCCTRL_BR          0x00000080  // Bit reverse enable
+#define CCM_CRCCTRL_ENDIAN_M    0x00000030  // Endian Control
+#define CCM_CRCCTRL_ENDIAN_SBHW 0x00000000  // Configuration unchanged. (B3,
+                                            // B2, B1, B0)
+#define CCM_CRCCTRL_ENDIAN_SHW  0x00000010  // Bytes are swapped in half-words
+                                            // but half-words are not swapped
+                                            // (B2, B3, B0, B1)
+#define CCM_CRCCTRL_ENDIAN_SHWNB                                              \
+                                0x00000020  // Half-words are swapped but bytes
+                                            // are not swapped in half-word.
+                                            // (B1, B0, B3, B2)
+#define CCM_CRCCTRL_ENDIAN_SBSW 0x00000030  // Bytes are swapped in half-words
+                                            // and half-words are swapped. (B0,
+                                            // B1, B2, B3)
+#define CCM_CRCCTRL_TYPE_M      0x0000000F  // Operation Type
+#define CCM_CRCCTRL_TYPE_P8055  0x00000000  // Polynomial 0x8005
+#define CCM_CRCCTRL_TYPE_P1021  0x00000001  // Polynomial 0x1021
+#define CCM_CRCCTRL_TYPE_P4C11DB7                                             \
+                                0x00000002  // Polynomial 0x4C11DB7
+#define CCM_CRCCTRL_TYPE_P1EDC6F41                                            \
+                                0x00000003  // Polynomial 0x1EDC6F41
+#define CCM_CRCCTRL_TYPE_TCPCHKSUM                                            \
+                                0x00000008  // TCP checksum
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCSEED register.
+//
+//*****************************************************************************
+#define CCM_CRCSEED_SEED_M      0xFFFFFFFF  // SEED/Context Value
+#define CCM_CRCSEED_SEED_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCDIN register.
+//
+//*****************************************************************************
+#define CCM_CRCDIN_DATAIN_M     0xFFFFFFFF  // Data Input
+#define CCM_CRCDIN_DATAIN_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCRSLTPP
+// register.
+//
+//*****************************************************************************
+#define CCM_CRCRSLTPP_RSLTPP_M  0xFFFFFFFF  // Post Processing Result
+#define CCM_CRCRSLTPP_RSLTPP_S  0
+
+#endif // __HW_CCM_H__
@@ -0,0 +1,49 @@
+//*****************************************************************************
+//
+// hw_fan.h - Macros used when accessing the fan control hardware.
+//
+// Copyright (c) 2010-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_FAN_H__
+#define __HW_FAN_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Fan Control register offsets.
+//
+//*****************************************************************************
+
+#endif // __HW_FAN_H__
@@ -0,0 +1,151 @@
+//*****************************************************************************
+//
+// hw_memmap.h - Macros defining the memory map of the device.
+//
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_MEMMAP_H__
+#define __HW_MEMMAP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the base address of the memories and
+// peripherals.
+//
+//*****************************************************************************
+#define FLASH_BASE              0x00000000  // FLASH memory
+#define SRAM_BASE               0x20000000  // SRAM memory
+#define WATCHDOG0_BASE          0x40000000  // Watchdog0
+#define WATCHDOG1_BASE          0x40001000  // Watchdog1
+#define GPIO_PORTA_BASE         0x40004000  // GPIO Port A
+#define GPIO_PORTB_BASE         0x40005000  // GPIO Port B
+#define GPIO_PORTC_BASE         0x40006000  // GPIO Port C
+#define GPIO_PORTD_BASE         0x40007000  // GPIO Port D
+#define SSI0_BASE               0x40008000  // SSI0
+#define SSI1_BASE               0x40009000  // SSI1
+#define SSI2_BASE               0x4000A000  // SSI2
+#define SSI3_BASE               0x4000B000  // SSI3
+#define UART0_BASE              0x4000C000  // UART0
+#define UART1_BASE              0x4000D000  // UART1
+#define UART2_BASE              0x4000E000  // UART2
+#define UART3_BASE              0x4000F000  // UART3
+#define UART4_BASE              0x40010000  // UART4
+#define UART5_BASE              0x40011000  // UART5
+#define UART6_BASE              0x40012000  // UART6
+#define UART7_BASE              0x40013000  // UART7
+#define I2C0_BASE               0x40020000  // I2C0
+#define I2C1_BASE               0x40021000  // I2C1
+#define I2C2_BASE               0x40022000  // I2C2
+#define I2C3_BASE               0x40023000  // I2C3
+#define GPIO_PORTE_BASE         0x40024000  // GPIO Port E
+#define GPIO_PORTF_BASE         0x40025000  // GPIO Port F
+#define GPIO_PORTG_BASE         0x40026000  // GPIO Port G
+#define GPIO_PORTH_BASE         0x40027000  // GPIO Port H
+#define PWM0_BASE               0x40028000  // Pulse Width Modulator (PWM)
+#define PWM1_BASE               0x40029000  // Pulse Width Modulator (PWM)
+#define QEI0_BASE               0x4002C000  // QEI0
+#define QEI1_BASE               0x4002D000  // QEI1
+#define TIMER0_BASE             0x40030000  // Timer0
+#define TIMER1_BASE             0x40031000  // Timer1
+#define TIMER2_BASE             0x40032000  // Timer2
+#define TIMER3_BASE             0x40033000  // Timer3
+#define TIMER4_BASE             0x40034000  // Timer4
+#define TIMER5_BASE             0x40035000  // Timer5
+#define WTIMER0_BASE            0x40036000  // Wide Timer0
+#define WTIMER1_BASE            0x40037000  // Wide Timer1
+#define ADC0_BASE               0x40038000  // ADC0
+#define ADC1_BASE               0x40039000  // ADC1
+#define COMP_BASE               0x4003C000  // Analog comparators
+#define GPIO_PORTJ_BASE         0x4003D000  // GPIO Port J
+#define CAN0_BASE               0x40040000  // CAN0
+#define CAN1_BASE               0x40041000  // CAN1
+#define WTIMER2_BASE            0x4004C000  // Wide Timer2
+#define WTIMER3_BASE            0x4004D000  // Wide Timer3
+#define WTIMER4_BASE            0x4004E000  // Wide Timer4
+#define WTIMER5_BASE            0x4004F000  // Wide Timer5
+#define USB0_BASE               0x40050000  // USB 0 Controller
+#define GPIO_PORTA_AHB_BASE     0x40058000  // GPIO Port A (high speed)
+#define GPIO_PORTB_AHB_BASE     0x40059000  // GPIO Port B (high speed)
+#define GPIO_PORTC_AHB_BASE     0x4005A000  // GPIO Port C (high speed)
+#define GPIO_PORTD_AHB_BASE     0x4005B000  // GPIO Port D (high speed)
+#define GPIO_PORTE_AHB_BASE     0x4005C000  // GPIO Port E (high speed)
+#define GPIO_PORTF_AHB_BASE     0x4005D000  // GPIO Port F (high speed)
+#define GPIO_PORTG_AHB_BASE     0x4005E000  // GPIO Port G (high speed)
+#define GPIO_PORTH_AHB_BASE     0x4005F000  // GPIO Port H (high speed)
+#define GPIO_PORTJ_AHB_BASE     0x40060000  // GPIO Port J (high speed)
+#define GPIO_PORTK_BASE         0x40061000  // GPIO Port K
+#define GPIO_PORTL_BASE         0x40062000  // GPIO Port L
+#define GPIO_PORTM_BASE         0x40063000  // GPIO Port M
+#define GPIO_PORTN_BASE         0x40064000  // GPIO Port N
+#define GPIO_PORTP_BASE         0x40065000  // GPIO Port P
+#define GPIO_PORTQ_BASE         0x40066000  // GPIO Port Q
+#define GPIO_PORTR_BASE         0x40067000  // General-Purpose Input/Outputs
+                                            // (GPIOs)
+#define GPIO_PORTS_BASE         0x40068000  // General-Purpose Input/Outputs
+                                            // (GPIOs)
+#define GPIO_PORTT_BASE         0x40069000  // General-Purpose Input/Outputs
+                                            // (GPIOs)
+#define EEPROM_BASE             0x400AF000  // EEPROM memory
+#define ONEWIRE0_BASE           0x400B6000  // 1-Wire Master Module
+#define I2C8_BASE               0x400B8000  // I2C8
+#define I2C9_BASE               0x400B9000  // I2C9
+#define I2C4_BASE               0x400C0000  // I2C4
+#define I2C5_BASE               0x400C1000  // I2C5
+#define I2C6_BASE               0x400C2000  // I2C6
+#define I2C7_BASE               0x400C3000  // I2C7
+#define EPI0_BASE               0x400D0000  // EPI0
+#define TIMER6_BASE             0x400E0000  // General-Purpose Timers
+#define TIMER7_BASE             0x400E1000  // General-Purpose Timers
+#define EMAC0_BASE              0x400EC000  // Ethernet Controller
+#define SYSEXC_BASE             0x400F9000  // System Exception Module
+#define HIB_BASE                0x400FC000  // Hibernation Module
+#define FLASH_CTRL_BASE         0x400FD000  // FLASH Controller
+#define SYSCTL_BASE             0x400FE000  // System Control
+#define UDMA_BASE               0x400FF000  // uDMA Controller
+#define CCM0_BASE               0x44030000  // Cyclical Redundancy Check (CRC)
+#define SHAMD5_BASE             0x44034000  // SHA/MD5 Accelerator
+#define AES_BASE                0x44036000  // Advance Encryption
+                                            // Hardware-Accelerated Module
+#define DES_BASE                0x44038000  // Data Encryption Standard
+                                            // Accelerator (DES)
+#define LCD0_BASE               0x44050000  // LCD Controller
+#define ITM_BASE                0xE0000000  // Instrumentation Trace Macrocell
+#define DWT_BASE                0xE0001000  // Data Watchpoint and Trace
+#define FPB_BASE                0xE0002000  // FLASH Patch and Breakpoint
+#define NVIC_BASE               0xE000E000  // Nested Vectored Interrupt Ctrl
+#define TPIU_BASE               0xE0040000  // Trace Port Interface Unit
+
+#endif // __HW_MEMMAP_H__
@@ -0,0 +1,178 @@
+//*****************************************************************************
+//
+// hw_qei.h - Macros used when accessing the QEI hardware.
+//
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_QEI_H__
+#define __HW_QEI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the QEI register offsets.
+//
+//*****************************************************************************
+#define QEI_O_CTL               0x00000000  // QEI Control
+#define QEI_O_STAT              0x00000004  // QEI Status
+#define QEI_O_POS               0x00000008  // QEI Position
+#define QEI_O_MAXPOS            0x0000000C  // QEI Maximum Position
+#define QEI_O_LOAD              0x00000010  // QEI Timer Load
+#define QEI_O_TIME              0x00000014  // QEI Timer
+#define QEI_O_COUNT             0x00000018  // QEI Velocity Counter
+#define QEI_O_SPEED             0x0000001C  // QEI Velocity
+#define QEI_O_INTEN             0x00000020  // QEI Interrupt Enable
+#define QEI_O_RIS               0x00000024  // QEI Raw Interrupt Status
+#define QEI_O_ISC               0x00000028  // QEI Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_FILTCNT_M       0x000F0000  // Input Filter Prescale Count
+#define QEI_CTL_FILTEN          0x00002000  // Enable Input Filter
+#define QEI_CTL_STALLEN         0x00001000  // Stall QEI
+#define QEI_CTL_INVI            0x00000800  // Invert Index Pulse
+#define QEI_CTL_INVB            0x00000400  // Invert PhB
+#define QEI_CTL_INVA            0x00000200  // Invert PhA
+#define QEI_CTL_VELDIV_M        0x000001C0  // Predivide Velocity
+#define QEI_CTL_VELDIV_1        0x00000000  // QEI clock /1
+#define QEI_CTL_VELDIV_2        0x00000040  // QEI clock /2
+#define QEI_CTL_VELDIV_4        0x00000080  // QEI clock /4
+#define QEI_CTL_VELDIV_8        0x000000C0  // QEI clock /8
+#define QEI_CTL_VELDIV_16       0x00000100  // QEI clock /16
+#define QEI_CTL_VELDIV_32       0x00000140  // QEI clock /32
+#define QEI_CTL_VELDIV_64       0x00000180  // QEI clock /64
+#define QEI_CTL_VELDIV_128      0x000001C0  // QEI clock /128
+#define QEI_CTL_VELEN           0x00000020  // Capture Velocity
+#define QEI_CTL_RESMODE         0x00000010  // Reset Mode
+#define QEI_CTL_CAPMODE         0x00000008  // Capture Mode
+#define QEI_CTL_SIGMODE         0x00000004  // Signal Mode
+#define QEI_CTL_SWAP            0x00000002  // Swap Signals
+#define QEI_CTL_ENABLE          0x00000001  // Enable QEI
+#define QEI_CTL_FILTCNT_S       16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_STAT register.
+//
+//*****************************************************************************
+#define QEI_STAT_DIRECTION      0x00000002  // Direction of Rotation
+#define QEI_STAT_ERROR          0x00000001  // Error Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_POS register.
+//
+//*****************************************************************************
+#define QEI_POS_M               0xFFFFFFFF  // Current Position Integrator
+                                            // Value
+#define QEI_POS_S               0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_MAXPOS register.
+//
+//*****************************************************************************
+#define QEI_MAXPOS_M            0xFFFFFFFF  // Maximum Position Integrator
+                                            // Value
+#define QEI_MAXPOS_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_LOAD register.
+//
+//*****************************************************************************
+#define QEI_LOAD_M              0xFFFFFFFF  // Velocity Timer Load Value
+#define QEI_LOAD_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_TIME register.
+//
+//*****************************************************************************
+#define QEI_TIME_M              0xFFFFFFFF  // Velocity Timer Current Value
+#define QEI_TIME_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_COUNT register.
+//
+//*****************************************************************************
+#define QEI_COUNT_M             0xFFFFFFFF  // Velocity Pulse Count
+#define QEI_COUNT_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_SPEED register.
+//
+//*****************************************************************************
+#define QEI_SPEED_M             0xFFFFFFFF  // Velocity
+#define QEI_SPEED_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_INTEN register.
+//
+//*****************************************************************************
+#define QEI_INTEN_ERROR         0x00000008  // Phase Error Interrupt Enable
+#define QEI_INTEN_DIR           0x00000004  // Direction Change Interrupt
+                                            // Enable
+#define QEI_INTEN_TIMER         0x00000002  // Timer Expires Interrupt Enable
+#define QEI_INTEN_INDEX         0x00000001  // Index Pulse Detected Interrupt
+                                            // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_RIS register.
+//
+//*****************************************************************************
+#define QEI_RIS_ERROR           0x00000008  // Phase Error Detected
+#define QEI_RIS_DIR             0x00000004  // Direction Change Detected
+#define QEI_RIS_TIMER           0x00000002  // Velocity Timer Expired
+#define QEI_RIS_INDEX           0x00000001  // Index Pulse Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_ISC register.
+//
+//*****************************************************************************
+#define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt
+#define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt
+#define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired Interrupt
+#define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt
+
+#endif // __HW_QEI_H__
@@ -0,0 +1,132 @@
+//*****************************************************************************
+//
+// hw_sysexc.h - Macros used when accessing the system exception module.
+//
+// Copyright (c) 2011-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SYSEXC_H__
+#define __HW_SYSEXC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the System Exception Module register
+// addresses.
+//
+//*****************************************************************************
+#define SYSEXC_RIS              0x400F9000  // System Exception Raw Interrupt
+                                            // Status
+#define SYSEXC_IM               0x400F9004  // System Exception Interrupt Mask
+#define SYSEXC_MIS              0x400F9008  // System Exception Masked
+                                            // Interrupt Status
+#define SYSEXC_IC               0x400F900C  // System Exception Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_RIS register.
+//
+//*****************************************************************************
+#define SYSEXC_RIS_FPIXCRIS     0x00000020  // Floating-Point Inexact Exception
+                                            // Raw Interrupt Status
+#define SYSEXC_RIS_FPOFCRIS     0x00000010  // Floating-Point Overflow
+                                            // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPUFCRIS     0x00000008  // Floating-Point Underflow
+                                            // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIOCRIS     0x00000004  // Floating-Point Invalid Operation
+                                            // Raw Interrupt Status
+#define SYSEXC_RIS_FPDZCRIS     0x00000002  // Floating-Point Divide By 0
+                                            // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIDCRIS     0x00000001  // Floating-Point Input Denormal
+                                            // Exception Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IM register.
+//
+//*****************************************************************************
+#define SYSEXC_IM_FPIXCIM       0x00000020  // Floating-Point Inexact Exception
+                                            // Interrupt Mask
+#define SYSEXC_IM_FPOFCIM       0x00000010  // Floating-Point Overflow
+                                            // Exception Interrupt Mask
+#define SYSEXC_IM_FPUFCIM       0x00000008  // Floating-Point Underflow
+                                            // Exception Interrupt Mask
+#define SYSEXC_IM_FPIOCIM       0x00000004  // Floating-Point Invalid Operation
+                                            // Interrupt Mask
+#define SYSEXC_IM_FPDZCIM       0x00000002  // Floating-Point Divide By 0
+                                            // Exception Interrupt Mask
+#define SYSEXC_IM_FPIDCIM       0x00000001  // Floating-Point Input Denormal
+                                            // Exception Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_MIS register.
+//
+//*****************************************************************************
+#define SYSEXC_MIS_FPIXCMIS     0x00000020  // Floating-Point Inexact Exception
+                                            // Masked Interrupt Status
+#define SYSEXC_MIS_FPOFCMIS     0x00000010  // Floating-Point Overflow
+                                            // Exception Masked Interrupt
+                                            // Status
+#define SYSEXC_MIS_FPUFCMIS     0x00000008  // Floating-Point Underflow
+                                            // Exception Masked Interrupt
+                                            // Status
+#define SYSEXC_MIS_FPIOCMIS     0x00000004  // Floating-Point Invalid Operation
+                                            // Masked Interrupt Status
+#define SYSEXC_MIS_FPDZCMIS     0x00000002  // Floating-Point Divide By 0
+                                            // Exception Masked Interrupt
+                                            // Status
+#define SYSEXC_MIS_FPIDCMIS     0x00000001  // Floating-Point Input Denormal
+                                            // Exception Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IC register.
+//
+//*****************************************************************************
+#define SYSEXC_IC_FPIXCIC       0x00000020  // Floating-Point Inexact Exception
+                                            // Interrupt Clear
+#define SYSEXC_IC_FPOFCIC       0x00000010  // Floating-Point Overflow
+                                            // Exception Interrupt Clear
+#define SYSEXC_IC_FPUFCIC       0x00000008  // Floating-Point Underflow
+                                            // Exception Interrupt Clear
+#define SYSEXC_IC_FPIOCIC       0x00000004  // Floating-Point Invalid Operation
+                                            // Interrupt Clear
+#define SYSEXC_IC_FPDZCIC       0x00000002  // Floating-Point Divide By 0
+                                            // Exception Interrupt Clear
+#define SYSEXC_IC_FPIDCIC       0x00000001  // Floating-Point Input Denormal
+                                            // Exception Interrupt Clear
+
+#endif // __HW_SYSEXC_H__
@@ -0,0 +1,147 @@
+//*****************************************************************************
+//
+// hw_types.h - Common types and macros.
+//
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_TYPES_H__
+#define __HW_TYPES_H__
+
+//*****************************************************************************
+//
+// Macros for hardware access, both direct and via the bit-band region.
+//
+//*****************************************************************************
+#define HWREG(x)                                                              \
+        (*((volatile uint32_t *)(x)))
+#define HWREGH(x)                                                             \
+        (*((volatile uint16_t *)(x)))
+#define HWREGB(x)                                                             \
+        (*((volatile uint8_t *)(x)))
+#define HWREGBITW(x, b)                                                       \
+        HWREG(((uint32_t)(x) & 0xF0000000) | 0x02000000 |                     \
+              (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITH(x, b)                                                       \
+        HWREGH(((uint32_t)(x) & 0xF0000000) | 0x02000000 |                    \
+               (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITB(x, b)                                                       \
+        HWREGB(((uint32_t)(x) & 0xF0000000) | 0x02000000 |                    \
+               (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+
+//*****************************************************************************
+//
+// Helper Macros for determining silicon revisions, etc.
+//
+// These macros will be used by Driverlib at "run-time" to create necessary
+// conditional code blocks that will allow a single version of the Driverlib
+// "binary" code to support multiple(all) Tiva silicon revisions.
+//
+// It is expected that these macros will be used inside of a standard 'C'
+// conditional block of code, e.g.
+//
+//     if(CLASS_IS_TM4C123)
+//     {
+//         do some TM4C123-class specific code here.
+//     }
+//
+// By default, these macros will be defined as run-time checks of the
+// appropriate register(s) to allow creation of run-time conditional code
+// blocks for a common DriverLib across the entire Tiva family.
+//
+// However, if code-space optimization is required, these macros can be "hard-
+// coded" for a specific version of Tiva silicon.  Many compilers will then
+// detect the "hard-coded" conditionals, and appropriately optimize the code
+// blocks, eliminating any "unreachable" code.  This would result in a smaller
+// Driverlib, thus producing a smaller final application size, but at the cost
+// of limiting the Driverlib binary to a specific Tiva silicon revision.
+//
+//*****************************************************************************
+#ifndef CLASS_IS_TM4C123
+#define CLASS_IS_TM4C123                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+         (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TM4C123))
+#endif
+
+#ifndef CLASS_IS_TM4C129
+#define CLASS_IS_TM4C129                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+         (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TM4C129))
+#endif
+
+#ifndef REVISION_IS_A0
+#define REVISION_IS_A0                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_A1
+#define REVISION_IS_A1                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_A2
+#define REVISION_IS_A2                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))
+#endif
+
+#ifndef REVISION_IS_B0
+#define REVISION_IS_B0                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_B1
+#define REVISION_IS_B1                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1))
+#endif
+
+//*****************************************************************************
+//
+// For TivaWare 2.1, we removed all references to Tiva IC codenames from the
+// source.  To ensure that existing customer code doesn't break as a result
+// of this change, make sure that the old definitions are still available at
+// least for the time being.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define CLASS_IS_BLIZZARD CLASS_IS_TM4C123
+#define CLASS_IS_SNOWFLAKE CLASS_IS_TM4C123
+#endif
+
+#endif // __HW_TYPES_H__
@@ -0,0 +1,122 @@
+//*****************************************************************************
+//
+// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
+//
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_WATCHDOG_H__
+#define __HW_WATCHDOG_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Watchdog Timer register offsets.
+//
+//*****************************************************************************
+#define WDT_O_LOAD              0x00000000  // Watchdog Load
+#define WDT_O_VALUE             0x00000004  // Watchdog Value
+#define WDT_O_CTL               0x00000008  // Watchdog Control
+#define WDT_O_ICR               0x0000000C  // Watchdog Interrupt Clear
+#define WDT_O_RIS               0x00000010  // Watchdog Raw Interrupt Status
+#define WDT_O_MIS               0x00000014  // Watchdog Masked Interrupt Status
+#define WDT_O_TEST              0x00000418  // Watchdog Test
+#define WDT_O_LOCK              0x00000C00  // Watchdog Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value
+#define WDT_LOAD_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value
+#define WDT_VALUE_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_WRC             0x80000000  // Write Complete
+#define WDT_CTL_INTTYPE         0x00000004  // Watchdog Interrupt Type
+#define WDT_CTL_RESEN           0x00000002  // Watchdog Reset Enable
+#define WDT_CTL_INTEN           0x00000001  // Watchdog Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear
+#define WDT_ICR_S               0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL          0x00000100  // Watchdog Stall Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock
+#define WDT_LOCK_UNLOCKED       0x00000000  // Unlocked
+#define WDT_LOCK_LOCKED         0x00000001  // Locked
+#define WDT_LOCK_UNLOCK         0x1ACCE551  // Unlocks the watchdog timer
+
+#endif // __HW_WATCHDOG_H__
@@ -0,0 +1,94 @@
+//*****************************************************************************
+//
+// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
+//
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_INTERRUPT_H__
+#define __DRIVERLIB_INTERRUPT_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Macro to generate an interrupt priority mask based on the number of bits
+// of priority supported by the hardware.
+//
+//*****************************************************************************
+#define INT_PRIORITY_MASK       ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern bool IntMasterEnable(void);
+extern bool IntMasterDisable(void);
+extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void));
+extern void IntUnregister(uint32_t ui32Interrupt);
+extern void IntPriorityGroupingSet(uint32_t ui32Bits);
+extern uint32_t IntPriorityGroupingGet(void);
+extern void IntPrioritySet(uint32_t ui32Interrupt,
+                           uint8_t ui8Priority);
+extern int32_t IntPriorityGet(uint32_t ui32Interrupt);
+extern void IntEnable(uint32_t ui32Interrupt);
+extern void IntDisable(uint32_t ui32Interrupt);
+extern uint32_t IntIsEnabled(uint32_t ui32Interrupt);
+extern void IntPendSet(uint32_t ui32Interrupt);
+extern void IntPendClear(uint32_t ui32Interrupt);
+extern void IntPriorityMaskSet(uint32_t ui32PriorityMask);
+extern uint32_t IntPriorityMaskGet(void);
+extern void IntTrigger(uint32_t ui32Interrupt);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_INTERRUPT_H__
@@ -0,0 +1,162 @@
+//*****************************************************************************
+//
+// mpu.h - Defines and Macros for the memory protection unit.
+//
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_MPU_H__
+#define __DRIVERLIB_MPU_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Flags that can be passed to MPUEnable.
+//
+//*****************************************************************************
+#define MPU_CONFIG_PRIV_DEFAULT     4
+#define MPU_CONFIG_HARDFLT_NMI      2
+#define MPU_CONFIG_NONE             0
+
+//*****************************************************************************
+//
+// Flags for the region size to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_RGN_SIZE_32B            (4 << 1)
+#define MPU_RGN_SIZE_64B            (5 << 1)
+#define MPU_RGN_SIZE_128B           (6 << 1)
+#define MPU_RGN_SIZE_256B           (7 << 1)
+#define MPU_RGN_SIZE_512B           (8 << 1)
+
+#define MPU_RGN_SIZE_1K             (9 << 1)
+#define MPU_RGN_SIZE_2K             (10 << 1)
+#define MPU_RGN_SIZE_4K             (11 << 1)
+#define MPU_RGN_SIZE_8K             (12 << 1)
+#define MPU_RGN_SIZE_16K            (13 << 1)
+#define MPU_RGN_SIZE_32K            (14 << 1)
+#define MPU_RGN_SIZE_64K            (15 << 1)
+#define MPU_RGN_SIZE_128K           (16 << 1)
+#define MPU_RGN_SIZE_256K           (17 << 1)
+#define MPU_RGN_SIZE_512K           (18 << 1)
+
+#define MPU_RGN_SIZE_1M             (19 << 1)
+#define MPU_RGN_SIZE_2M             (20 << 1)
+#define MPU_RGN_SIZE_4M             (21 << 1)
+#define MPU_RGN_SIZE_8M             (22 << 1)
+#define MPU_RGN_SIZE_16M            (23 << 1)
+#define MPU_RGN_SIZE_32M            (24 << 1)
+#define MPU_RGN_SIZE_64M            (25 << 1)
+#define MPU_RGN_SIZE_128M           (26 << 1)
+#define MPU_RGN_SIZE_256M           (27 << 1)
+#define MPU_RGN_SIZE_512M           (28 << 1)
+
+#define MPU_RGN_SIZE_1G             (29 << 1)
+#define MPU_RGN_SIZE_2G             (30 << 1)
+#define MPU_RGN_SIZE_4G             (31 << 1)
+
+//*****************************************************************************
+//
+// Flags for the permissions to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_RGN_PERM_EXEC           0x00000000
+#define MPU_RGN_PERM_NOEXEC         0x10000000
+#define MPU_RGN_PERM_PRV_NO_USR_NO  0x00000000
+#define MPU_RGN_PERM_PRV_RW_USR_NO  0x01000000
+#define MPU_RGN_PERM_PRV_RW_USR_RO  0x02000000
+#define MPU_RGN_PERM_PRV_RW_USR_RW  0x03000000
+#define MPU_RGN_PERM_PRV_RO_USR_NO  0x05000000
+#define MPU_RGN_PERM_PRV_RO_USR_RO  0x06000000
+
+//*****************************************************************************
+//
+// Flags for the sub-region to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_SUB_RGN_DISABLE_0       0x00000100
+#define MPU_SUB_RGN_DISABLE_1       0x00000200
+#define MPU_SUB_RGN_DISABLE_2       0x00000400
+#define MPU_SUB_RGN_DISABLE_3       0x00000800
+#define MPU_SUB_RGN_DISABLE_4       0x00001000
+#define MPU_SUB_RGN_DISABLE_5       0x00002000
+#define MPU_SUB_RGN_DISABLE_6       0x00004000
+#define MPU_SUB_RGN_DISABLE_7       0x00008000
+
+//*****************************************************************************
+//
+// Flags to enable or disable a region, to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_RGN_ENABLE              1
+#define MPU_RGN_DISABLE             0
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void MPUEnable(uint32_t ui32MPUConfig);
+extern void MPUDisable(void);
+extern uint32_t MPURegionCountGet(void);
+extern void MPURegionEnable(uint32_t ui32Region);
+extern void MPURegionDisable(uint32_t ui32Region);
+extern void MPURegionSet(uint32_t ui32Region, uint32_t ui32Addr,
+                         uint32_t ui32Flags);
+extern void MPURegionGet(uint32_t ui32Region, uint32_t *pui32Addr,
+                         uint32_t *pui32Flags);
+extern void MPUIntRegister(void (*pfnHandler)(void));
+extern void MPUIntUnregister(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_MPU_H__
@@ -0,0 +1,154 @@
+//*****************************************************************************
+//
+// qei.h - Prototypes for the Quadrature Encoder Driver.
+//
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_QEI_H__
+#define __DRIVERLIB_QEI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to QEIConfigure as the ui32Config paramater.
+//
+//*****************************************************************************
+#define QEI_CONFIG_CAPTURE_A    0x00000000  // Count on ChA edges only
+#define QEI_CONFIG_CAPTURE_A_B  0x00000008  // Count on ChA and ChB edges
+#define QEI_CONFIG_NO_RESET     0x00000000  // Do not reset on index pulse
+#define QEI_CONFIG_RESET_IDX    0x00000010  // Reset position on index pulse
+#define QEI_CONFIG_QUADRATURE   0x00000000  // ChA and ChB are quadrature
+#define QEI_CONFIG_CLOCK_DIR    0x00000004  // ChA and ChB are clock and dir
+#define QEI_CONFIG_NO_SWAP      0x00000000  // Do not swap ChA and ChB
+#define QEI_CONFIG_SWAP         0x00000002  // Swap ChA and ChB
+
+//*****************************************************************************
+//
+// Values that can be passed to QEIFilterConfigure as the ui32PreDiv
+// parameter.
+//
+//*****************************************************************************
+#define QEI_FILTCNT_2           0x00000000  // Filter Count of 2 System Clocks
+#define QEI_FILTCNT_3           0x00010000  // Filter Count of 3 System Clocks
+#define QEI_FILTCNT_4           0x00020000  // Filter Count of 4 System Clocks
+#define QEI_FILTCNT_5           0x00030000  // Filter Count of 5 System Clocks
+#define QEI_FILTCNT_6           0x00040000  // Filter Count of 6 System Clocks
+#define QEI_FILTCNT_7           0x00050000  // Filter Count of 7 System Clocks
+#define QEI_FILTCNT_8           0x00060000  // Filter Count of 8 System Clocks
+#define QEI_FILTCNT_9           0x00070000  // Filter Count of 9 System Clocks
+#define QEI_FILTCNT_10          0x00080000  // Filter Count of 10 System Clocks
+#define QEI_FILTCNT_11          0x00090000  // Filter Count of 11 System Clocks
+#define QEI_FILTCNT_12          0x000A0000  // Filter Count of 12 System Clocks
+#define QEI_FILTCNT_13          0x000B0000  // Filter Count of 13 System Clocks
+#define QEI_FILTCNT_14          0x000C0000  // Filter Count of 14 System Clocks
+#define QEI_FILTCNT_15          0x000D0000  // Filter Count of 15 System Clocks
+#define QEI_FILTCNT_16          0x000E0000  // Filter Count of 16 System Clocks
+#define QEI_FILTCNT_17          0x000F0000  // Filter Count of 17 System Clocks
+
+//*****************************************************************************
+//
+// Values that can be passed to QEIVelocityConfigure as the ui32PreDiv
+// parameter.
+//
+//*****************************************************************************
+#define QEI_VELDIV_1            0x00000000  // Predivide by 1
+#define QEI_VELDIV_2            0x00000040  // Predivide by 2
+#define QEI_VELDIV_4            0x00000080  // Predivide by 4
+#define QEI_VELDIV_8            0x000000C0  // Predivide by 8
+#define QEI_VELDIV_16           0x00000100  // Predivide by 16
+#define QEI_VELDIV_32           0x00000140  // Predivide by 32
+#define QEI_VELDIV_64           0x00000180  // Predivide by 64
+#define QEI_VELDIV_128          0x000001C0  // Predivide by 128
+
+//*****************************************************************************
+//
+// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts
+// as the ui32IntFlags parameter, and returned by QEIGetIntStatus.
+//
+//*****************************************************************************
+#define QEI_INTERROR            0x00000008  // Phase error detected
+#define QEI_INTDIR              0x00000004  // Direction change
+#define QEI_INTTIMER            0x00000002  // Velocity timer expired
+#define QEI_INTINDEX            0x00000001  // Index pulse detected
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void QEIEnable(uint32_t ui32Base);
+extern void QEIDisable(uint32_t ui32Base);
+extern void QEIConfigure(uint32_t ui32Base, uint32_t ui32Config,
+                         uint32_t ui32MaxPosition);
+extern uint32_t QEIPositionGet(uint32_t ui32Base);
+extern void QEIPositionSet(uint32_t ui32Base, uint32_t ui32Position);
+extern int32_t QEIDirectionGet(uint32_t ui32Base);
+extern bool QEIErrorGet(uint32_t ui32Base);
+extern void QEIFilterEnable(uint32_t ui32Base);
+extern void QEIFilterDisable(uint32_t ui32Base);
+extern void QEIFilterConfigure(uint32_t ui32Base, uint32_t ui32FiltCnt);
+extern void QEIVelocityEnable(uint32_t ui32Base);
+extern void QEIVelocityDisable(uint32_t ui32Base);
+extern void QEIVelocityConfigure(uint32_t ui32Base, uint32_t ui32PreDiv,
+                                 uint32_t ui32Period);
+extern uint32_t QEIVelocityGet(uint32_t ui32Base);
+extern void QEIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern void QEIIntUnregister(uint32_t ui32Base);
+extern void QEIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void QEIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern uint32_t QEIIntStatus(uint32_t ui32Base, bool bMasked);
+extern void QEIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_QEI_H__
@@ -0,0 +1,108 @@
+//*****************************************************************************
+//
+// rtos_bindings.h - Macros intended to aid porting of TivaWare modules
+//                   for use with an RTOS.
+//
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_RTOS_BINDINGS_H__
+#define __DRIVERLIB_RTOS_BINDINGS_H__
+
+#ifdef USE_RTOS
+//*****************************************************************************
+//
+// If an RTOS is in use, implement a header file called "tiva_rtos.h"
+// which contains RTOS-specific versions of each of the macros defined below
+// and make sure it appears on the include path set when you build your
+// project.
+//
+// Note that there is no default implementation of this header file included
+// in TivaWare - it is your responsibility to create it specifically for
+// your RTOS.
+//
+//*****************************************************************************
+#include "tiva_rtos.h"
+
+#else
+//*****************************************************************************
+//
+// When no RTOS is in use, the follow macros compile to either nothing or a
+// minimal implementation that works in a bare-metal environment.
+//
+// Each of these macros must be redefined in tiva_rtos.h if you are using
+// TivaWare under an RTOS.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// A simple macro used to yield within polling loops.  In the default, non-RTOS
+// implementation, this compiles to nothing.
+//
+//*****************************************************************************
+#define OS_YIELD()
+
+//*****************************************************************************
+//
+// A simple macro around the SysCtlDelay function.  The parameter is the number
+// of 3 cycle loops to wait before returning (as for SysCtlDelay).  In an RTOS
+// implementation, this could be replaced with an OS delay call with
+// appropriate parameter scaling.
+//
+//*****************************************************************************
+#define OS_DELAY(ul3Cycles) MAP_SysCtlDelay(ul3Cycles)
+
+//*****************************************************************************
+//
+// Wrappers around low level interrupt control functions.  For information
+// on each of these functions, please see the appropriate API documentation
+// for the DriverLib Interrupt driver.
+//
+// The macros defined here represent interrupt-control functions that may be
+// called from within TivaWare code.  It is expected that application
+// code will use RTOS-specific functions to control interrupt priority, to
+// pend interrupts and to perform runtime vector manipulation.  As a result,
+// no macros are defined to wrap any of these functions from interrupt.c.
+//
+//*****************************************************************************
+#define OS_INT_MASTER_ENABLE() MAP_IntMasterEnable()
+#define OS_INT_MASTER_DISABLE() MAP_IntMasterDisable()
+#define OS_INT_DISABLE(ui32IntID) MAP_IntDisable(ui32IntID)
+#define OS_INT_ENABLE(ui32IntID) MAP_IntEnable(ui32IntID)
+
+#endif // USE_RTOS
+
+#endif // __DRIVERLIB_RTOS_BINDINGS_H__
@@ -0,0 +1,127 @@
+//*****************************************************************************
+//
+// shamd5.h - Defines and Macros for the SHA/MD5.
+//
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_SHAMD5_H__
+#define __DRIVERLIB_SHAMD5_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following defines are used to specify the algorithm in use in the
+// SHA/MD5 module.
+//
+//*****************************************************************************
+#define SHAMD5_ALGO_MD5         0x00000018
+#define SHAMD5_ALGO_SHA1        0x0000001a
+#define SHAMD5_ALGO_SHA224      0x0000001c
+#define SHAMD5_ALGO_SHA256      0x0000001e
+#define SHAMD5_ALGO_HMAC_MD5    0x00000000
+#define SHAMD5_ALGO_HMAC_SHA1   0x00000002
+#define SHAMD5_ALGO_HMAC_SHA224 0x00000004
+#define SHAMD5_ALGO_HMAC_SHA256 0x00000006
+
+//*****************************************************************************
+//
+// The following defines are used to represent the different interrupt sources
+// in SHAMD5IntEnable(), SHAMD5IntDisable(), SHAMD5GetIntStatus(), and
+// SHAMD5BlockOnIntStatus() functions.
+//
+//*****************************************************************************
+#define SHAMD5_INT_CONTEXT_READY \
+                                0x00000008
+#define SHAMD5_INT_PARTHASH_READY \
+                                0x00000004
+#define SHAMD5_INT_INPUT_READY  0x00000002
+#define SHAMD5_INT_OUTPUT_READY 0x00000001
+#define SHAMD5_INT_DMA_CONTEXT_IN \
+                                0x00080000
+#define SHAMD5_INT_DMA_DATA_IN  0x00020000
+#define SHAMD5_INT_DMA_CONTEXT_OUT \
+                                0x00010000
+
+//*****************************************************************************
+//
+// Function prototypes
+//
+//*****************************************************************************
+extern void SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32Mode);
+extern void SHAMD5DataProcess(uint32_t ui32Base, uint32_t *pui32DataSrc,
+                              uint32_t ui32DataLength,
+                              uint32_t *pui32HashResult);
+extern void SHAMD5DataWrite(uint32_t ui32Base, uint32_t *pui32Src);
+extern bool SHAMD5DataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src);
+extern void SHAMD5DMADisable(uint32_t ui32Base);
+extern void SHAMD5DMAEnable(uint32_t ui32Base);
+extern void SHAMD5HashLengthSet(uint32_t ui32Base, uint32_t ui32Length);
+extern void SHAMD5HMACKeySet(uint32_t ui32Base, uint32_t *pui32Src);
+extern void SHAMD5HMACPPKeyGenerate(uint32_t ui32Base, uint32_t *pui32Key,
+                                    uint32_t *pui32PPKey);
+extern void SHAMD5HMACPPKeySet(uint32_t ui32Base, uint32_t *pui32Src);
+extern void SHAMD5HMACProcess(uint32_t ui32Base, uint32_t *pui32DataSrc,
+                              uint32_t ui32DataLength,
+                              uint32_t *pui32HashResult);
+extern void SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void SHAMD5IntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern uint32_t SHAMD5IntStatus(uint32_t ui32Base, bool bMasked);
+extern void SHAMD5IntUnregister(uint32_t ui32Base);
+extern void SHAMD5Reset(uint32_t ui32Base);
+extern void SHAMD5ResultRead(uint32_t ui32Base, uint32_t *pui32Dest);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_SHAMD5_H__
@@ -0,0 +1,157 @@
+//*****************************************************************************
+//
+// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
+//
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_SSI_H__
+#define __DRIVERLIB_SSI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
+// as the ui32IntFlags parameter, and returned by SSIIntStatus.
+//
+//*****************************************************************************
+#define SSI_TXEOT               0x00000040  // Transmit FIFO is empty
+#define SSI_DMATX               0x00000020  // DMA Transmit complete
+#define SSI_DMARX               0x00000010  // DMA Receive complete
+#define SSI_TXFF                0x00000008  // TX FIFO half full or less
+#define SSI_RXFF                0x00000004  // RX FIFO half full or more
+#define SSI_RXTO                0x00000002  // RX timeout
+#define SSI_RXOR                0x00000001  // RX overrun
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIConfigSetExpClk.
+//
+//*****************************************************************************
+#define SSI_FRF_MOTO_MODE_0     0x00000000  // Moto fmt, polarity 0, phase 0
+#define SSI_FRF_MOTO_MODE_1     0x00000002  // Moto fmt, polarity 0, phase 1
+#define SSI_FRF_MOTO_MODE_2     0x00000001  // Moto fmt, polarity 1, phase 0
+#define SSI_FRF_MOTO_MODE_3     0x00000003  // Moto fmt, polarity 1, phase 1
+#define SSI_FRF_TI              0x00000010  // TI frame format
+#define SSI_FRF_NMW             0x00000020  // National MicroWire frame format
+
+#define SSI_MODE_MASTER         0x00000000  // SSI master
+#define SSI_MODE_SLAVE          0x00000001  // SSI slave
+#define SSI_MODE_SLAVE_OD       0x00000002  // SSI slave with output disabled
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIDMAEnable() and SSIDMADisable().
+//
+//*****************************************************************************
+#define SSI_DMA_TX              0x00000002  // Enable DMA for transmit
+#define SSI_DMA_RX              0x00000001  // Enable DMA for receive
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIClockSourceSet() or returned from
+// SSIClockSourceGet().
+//
+//*****************************************************************************
+#define SSI_CLOCK_SYSTEM        0x00000000
+#define SSI_CLOCK_PIOSC         0x00000005
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIAdvModeSet().
+//
+//*****************************************************************************
+#define SSI_ADV_MODE_LEGACY     0x00000000
+#define SSI_ADV_MODE_READ_WRITE 0x000001c0
+#define SSI_ADV_MODE_WRITE      0x000000c0
+#define SSI_ADV_MODE_BI_READ    0x00000140
+#define SSI_ADV_MODE_BI_WRITE   0x00000040
+#define SSI_ADV_MODE_QUAD_READ  0x00000180
+#define SSI_ADV_MODE_QUAD_WRITE 0x00000080
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk,
+                               uint32_t ui32Protocol, uint32_t ui32Mode,
+                               uint32_t ui32BitRate,
+                               uint32_t ui32DataWidth);
+extern void SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data);
+extern int32_t SSIDataGetNonBlocking(uint32_t ui32Base,
+                                  uint32_t *pui32Data);
+extern void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data);
+extern int32_t SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data);
+extern void SSIDisable(uint32_t ui32Base);
+extern void SSIEnable(uint32_t ui32Base);
+extern void SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern uint32_t SSIIntStatus(uint32_t ui32Base, bool bMasked);
+extern void SSIIntUnregister(uint32_t ui32Base);
+extern void SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags);
+extern void SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags);
+extern bool SSIBusy(uint32_t ui32Base);
+extern void SSIClockSourceSet(uint32_t ui32Base, uint32_t ui32Source);
+extern uint32_t SSIClockSourceGet(uint32_t ui32Base);
+extern void SSIAdvModeSet(uint32_t ui32Base, uint32_t ui32Mode);
+extern void SSIAdvDataPutFrameEnd(uint32_t ui32Base, uint32_t ui32Data);
+extern int32_t SSIAdvDataPutFrameEndNonBlocking(uint32_t ui32Base,
+                                             uint32_t ui32Data);
+extern void SSIAdvFrameHoldEnable(uint32_t ui32Base);
+extern void SSIAdvFrameHoldDisable(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_SSI_H__
@@ -0,0 +1,78 @@
+//*****************************************************************************
+//
+// sw_crc.h - Prototypes for the software CRC functions.
+//
+// Copyright (c) 2010-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_SW_CRC_H__
+#define __DRIVERLIB_SW_CRC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes for the functions.
+//
+//*****************************************************************************
+extern uint8_t Crc8CCITT(uint8_t ui8Crc, const uint8_t *pui8Data,
+                         uint32_t ui32Count);
+extern uint16_t Crc16(uint16_t ui16Crc, const uint8_t *pui8Data,
+                      uint32_t ui32Count);
+extern uint16_t Crc16Array(uint32_t ui32WordLen, const uint32_t *pui32Data);
+extern void Crc16Array3(uint32_t ui32WordLen, const uint32_t *pui32Data,
+                        uint16_t *pui16Crc3);
+extern uint32_t Crc32(uint32_t ui32Crc, const uint8_t *pui8Data,
+                      uint32_t ui32Count);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_SW_CRC_H__
--- a/Show More
+++ b/Show More