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Merge pull request #5279 from OpenNuvoton/nuvoton

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[Nuvoton] Update drivers.
This commit is contained in:
Bernard Xiong authored and GitHub committed 2021-11-25 20:03:58 +08:00
2 parents 3bc5ffb495 674ded6aa5
commit 1cea0c8c79
43 files changed
+2086 -1525
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bsp/nuvoton/libraries/m031/rtt_port/drv_i2c.c
+29 -13
View File
@@ -72,20 +72,32 @@ static nu_i2c_bus_t nu_i2c1 =
static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg msgs[],
rt_uint32_t num);
static rt_err_t nu_i2c_bus_control(struct rt_i2c_bus_device *bus,
rt_uint32_t u32Cmd,
rt_uint32_t u32Value);
static const struct rt_i2c_bus_device_ops nu_i2c_ops =
{
.master_xfer = nu_i2c_mst_xfer,
.slave_xfer = NULL,
.i2c_bus_control = NULL,
.i2c_bus_control = nu_i2c_bus_control
};
static rt_err_t nu_i2c_configure(nu_i2c_bus_t *bus)
static rt_err_t nu_i2c_bus_control(struct rt_i2c_bus_device *bus, rt_uint32_t u32Cmd, rt_uint32_t u32Value)
{
RT_ASSERT(bus != RT_NULL);
nu_i2c_bus_t *nu_i2c;
bus->parent.ops = &nu_i2c_ops;
I2C_Open(bus->I2C, 100000);
RT_ASSERT(bus != RT_NULL);
nu_i2c = (nu_i2c_bus_t *) bus;
switch (RT_I2C_DEV_CTRL_CLK)
{
case RT_I2C_DEV_CTRL_CLK:
I2C_SetBusClockFreq(nu_i2c->I2C, u32Value);
break;
default:
return -RT_EIO;
}
return RT_EOK;
}
@@ -290,24 +302,28 @@ static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
int rt_hw_i2c_init(void)
{
rt_err_t ret = RT_ERROR;
#if defined(BSP_USING_I2C0)
SYS_UnlockReg();
SYS_ResetModule(I2C0_RST);
SYS_LockReg();
nu_i2c_configure(&nu_i2c0);
#if defined(BSP_USING_I2C0)
I2C_Close(nu_i2c0.I2C);
I2C_Open(nu_i2c0.I2C, 100000);
nu_i2c0.parent.ops = &nu_i2c_ops;
ret = rt_i2c_bus_device_register(&nu_i2c0.parent, nu_i2c0.device_name);
RT_ASSERT(RT_EOK == ret);
#endif /* BSP_USING_I2C0 */
#if defined(BSP_USING_I2C1)
SYS_UnlockReg();
SYS_ResetModule(I2C1_RST);
SYS_LockReg();
nu_i2c_configure(&nu_i2c1);
I2C_Close(nu_i2c1.I2C);
I2C_Open(nu_i2c1.I2C, 100000);
nu_i2c1.parent.ops = &nu_i2c_ops;
ret = rt_i2c_bus_device_register(&nu_i2c1.parent, nu_i2c1.device_name);
RT_ASSERT(RT_EOK == ret);
#endif /* BSP_USING_I2C1 */
SYS_LockReg();
return ret;
}
bsp/nuvoton/libraries/m2354/USBHostLib/src/ohci.c
+7
View File
@@ -1144,6 +1144,9 @@ void USBH_IRQHandler(void)
TD_T *td, *td_prev, *td_next;
uint32_t int_sts;
/* enter interrupt */
rt_interrupt_enter();
int_sts = _ohci->HcInterruptStatus;
//USB_debug("ohci int_sts = 0x%x\n", int_sts);
@@ -1199,6 +1202,10 @@ void USBH_IRQHandler(void)
}
_ohci->HcInterruptStatus = int_sts;
/* leave interrupt */
rt_interrupt_leave();
}
#ifdef ENABLE_DEBUG_MSG
bsp/nuvoton/libraries/m2354/rtt_port/drv_i2c.c
+34 -17
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@@ -81,20 +81,32 @@ static nu_i2c_bus_t nu_i2c2 =
static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg msgs[],
rt_uint32_t num);
static rt_err_t nu_i2c_bus_control(struct rt_i2c_bus_device *bus,
rt_uint32_t u32Cmd,
rt_uint32_t u32Value);
static const struct rt_i2c_bus_device_ops nu_i2c_ops =
{
.master_xfer = nu_i2c_mst_xfer,
.slave_xfer = NULL,
.i2c_bus_control = NULL,
.i2c_bus_control = nu_i2c_bus_control
};
static rt_err_t nu_i2c_configure(nu_i2c_bus_t *bus)
static rt_err_t nu_i2c_bus_control(struct rt_i2c_bus_device *bus, rt_uint32_t u32Cmd, rt_uint32_t u32Value)
{
RT_ASSERT(bus != RT_NULL);
nu_i2c_bus_t *nu_i2c;
bus->parent.ops = &nu_i2c_ops;
I2C_Open(bus->I2C, 100000);
RT_ASSERT(bus != RT_NULL);
nu_i2c = (nu_i2c_bus_t *) bus;
switch (RT_I2C_DEV_CTRL_CLK)
{
case RT_I2C_DEV_CTRL_CLK:
I2C_SetBusClockFreq(nu_i2c->I2C, u32Value);
break;
default:
return -RT_EIO;
}
return RT_EOK;
}
@@ -354,33 +366,38 @@ static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
int rt_hw_i2c_init(void)
{
rt_err_t ret = RT_ERROR;
#if defined(BSP_USING_I2C0)
SYS_UnlockReg();
SYS_ResetModule(I2C0_RST);
SYS_LockReg();
nu_i2c_configure(&nu_i2c0);
#if defined(BSP_USING_I2C0)
I2C_Close(nu_i2c0.I2C);
I2C_Open(nu_i2c0.I2C, 100000);
nu_i2c0.parent.ops = &nu_i2c_ops;
ret = rt_i2c_bus_device_register(&nu_i2c0.parent, nu_i2c0.device_name);
RT_ASSERT(RT_EOK == ret);
#endif /* BSP_USING_I2C0 */
#if defined(BSP_USING_I2C1)
SYS_UnlockReg();
SYS_ResetModule(I2C1_RST);
SYS_LockReg();
nu_i2c_configure(&nu_i2c1);
I2C_Close(nu_i2c1.I2C);
I2C_Open(nu_i2c1.I2C, 100000);
nu_i2c1.parent.ops = &nu_i2c_ops;
ret = rt_i2c_bus_device_register(&nu_i2c1.parent, nu_i2c1.device_name);
RT_ASSERT(RT_EOK == ret);
#endif /* BSP_USING_I2C1 */
#if defined(BSP_USING_I2C2)
SYS_UnlockReg();
SYS_ResetModule(I2C2_RST);
SYS_LockReg();
nu_i2c_configure(&nu_i2c2);
I2C_Close(nu_i2c2.I2C);
I2C_Open(nu_i2c2.I2C, 100000);
nu_i2c2.parent.ops = &nu_i2c_ops;
ret = rt_i2c_bus_device_register(&nu_i2c2.parent, nu_i2c2.device_name);
RT_ASSERT(RT_EOK == ret);
#endif /* BSP_USING_I2C2 */
SYS_LockReg();
return ret;
}
bsp/nuvoton/libraries/m2354/rtt_port/drv_usbhost.c
+368 -330
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File diff suppressed because it is too large. Load diff
bsp/nuvoton/libraries/m480/USBHostLib/src/ehci.c
+6
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@@ -1113,6 +1113,9 @@ void EHCI_IRQHandler(void)
{
uint32_t intsts;
/* enter interrupt */
rt_interrupt_enter();
intsts = _ehci->USTSR;
_ehci->USTSR = intsts; /* clear interrupt status */
@@ -1136,6 +1139,9 @@ void EHCI_IRQHandler(void)
{
iaad_remove_qh();
}
/* leave interrupt */
rt_interrupt_leave();
}
static UDEV_T *ehci_find_device_by_port(int port)
bsp/nuvoton/libraries/m480/USBHostLib/src/ohci.c
+6
View File
@@ -1154,6 +1154,9 @@ void OHCI_IRQHandler(void)
TD_T *td, *td_prev, *td_next;
uint32_t int_sts;
/* enter interrupt */
rt_interrupt_enter();
int_sts = _ohci->HcInterruptStatus;
//USB_debug("ohci int_sts = 0x%x\n", int_sts);
@@ -1209,6 +1212,9 @@ void OHCI_IRQHandler(void)
}
_ohci->HcInterruptStatus = int_sts;
/* leave interrupt */
rt_interrupt_leave();
}
#ifdef ENABLE_DEBUG_MSG
bsp/nuvoton/libraries/m480/rtt_port/drv_i2c.c
+34 -20
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@@ -81,20 +81,32 @@ static nu_i2c_bus_t nu_i2c2 =
static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg msgs[],
rt_uint32_t num);
static rt_err_t nu_i2c_bus_control(struct rt_i2c_bus_device *bus,
rt_uint32_t u32Cmd,
rt_uint32_t u32Value);
static const struct rt_i2c_bus_device_ops nu_i2c_ops =
{
.master_xfer = nu_i2c_mst_xfer,
.slave_xfer = NULL,
.i2c_bus_control = NULL,
.i2c_bus_control = nu_i2c_bus_control
};
static rt_err_t nu_i2c_configure(nu_i2c_bus_t *bus)
static rt_err_t nu_i2c_bus_control(struct rt_i2c_bus_device *bus, rt_uint32_t u32Cmd, rt_uint32_t u32Value)
{
RT_ASSERT(bus != RT_NULL);
nu_i2c_bus_t *nu_i2c;
bus->parent.ops = &nu_i2c_ops;
I2C_Open(bus->I2C, 100000);
RT_ASSERT(bus != RT_NULL);
nu_i2c = (nu_i2c_bus_t *) bus;
switch (RT_I2C_DEV_CTRL_CLK)
{
case RT_I2C_DEV_CTRL_CLK:
I2C_SetBusClockFreq(nu_i2c->I2C, u32Value);
break;
default:
return -RT_EIO;
}
return RT_EOK;
}
@@ -354,36 +366,38 @@ static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
int rt_hw_i2c_init(void)
{
rt_err_t ret = RT_ERROR;
#if defined(BSP_USING_I2C0)
SYS_UnlockReg();
/* Enable I2C0 clock */
SYS_ResetModule(I2C0_RST);
SYS_LockReg();
nu_i2c_configure(&nu_i2c0);
#if defined(BSP_USING_I2C0)
I2C_Close(nu_i2c0.I2C);
I2C_Open(nu_i2c0.I2C, 100000);
nu_i2c0.parent.ops = &nu_i2c_ops;
ret = rt_i2c_bus_device_register(&nu_i2c0.parent, nu_i2c0.device_name);
RT_ASSERT(RT_EOK == ret);
#endif /* BSP_USING_I2C0 */
#if defined(BSP_USING_I2C1)
SYS_UnlockReg();
/* Enable I2C1 clock */
SYS_ResetModule(I2C1_RST);
SYS_LockReg();
nu_i2c_configure(&nu_i2c1);
I2C_Close(nu_i2c1.I2C);
I2C_Open(nu_i2c1.I2C, 100000);
nu_i2c1.parent.ops = &nu_i2c_ops;
ret = rt_i2c_bus_device_register(&nu_i2c1.parent, nu_i2c1.device_name);
RT_ASSERT(RT_EOK == ret);
#endif /* BSP_USING_I2C1 */
#if defined(BSP_USING_I2C2)
SYS_UnlockReg();
/* Enable I2C2 clock */
SYS_ResetModule(I2C2_RST);
SYS_LockReg();
nu_i2c_configure(&nu_i2c2);
I2C_Close(nu_i2c2.I2C);
I2C_Open(nu_i2c2.I2C, 100000);
nu_i2c2.parent.ops = &nu_i2c_ops;
ret = rt_i2c_bus_device_register(&nu_i2c2.parent, nu_i2c2.device_name);
RT_ASSERT(RT_EOK == ret);
#endif /* BSP_USING_I2C2 */
SYS_LockReg();
return ret;
}
bsp/nuvoton/libraries/m480/rtt_port/drv_usbhost.c
+246 -210
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File diff suppressed because it is too large. Load diff
bsp/nuvoton/libraries/n9h30/Driver/Include/nu_sdh.h
+20 -13
View File
@@ -376,6 +376,7 @@ typedef struct
__IO uint32_t BLEN; /*!< [0x0838] SD Block Length Register */
__IO uint32_t TOUT; /*!< [0x083c] SD Response/Data-in Time-out Register */
__IO uint32_t ECTL; /*!< [0x0840] SD Host Extend Control Register */
} SDH_T;
@@ -450,8 +451,8 @@ typedef struct
#define SDH_CTL_CLK8OEN_Pos (6) /*!< SDH_T::CTL: CLK8OEN Position */
#define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) /*!< SDH_T::CTL: CLK8OEN Mask */
#define SDH_CTL_CLKKEEP_Pos (7) /*!< SDH_T::CTL: CLKKEEP Position */
#define SDH_CTL_CLKKEEP_Msk (0x1ul << SDH_CTL_CLKKEEP_Pos) /*!< SDH_T::CTL: CLKKEEP Mask */
#define SDH_CTL_CLKKEEP0_Pos (7) /*!< SDH_T::CTL: CLKKEEP Position */
#define SDH_CTL_CLKKEEP0_Msk (0x1ul << SDH_CTL_CLKKEEP0_Pos) /*!< SDH_T::CTL: CLKKEEP Mask */
#define SDH_CTL_CMDCODE_Pos (8) /*!< SDH_T::CTL: CMDCODE Position */
#define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) /*!< SDH_T::CTL: CMDCODE Mask */
@@ -567,6 +568,12 @@ typedef struct
#define SDH_TOUT_TOUT_Pos (0) /*!< SDH_T::TOUT: TOUT Position */
#define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) /*!< SDH_T::TOUT: TOUT Mask */
#define SDH_ECTL_POWEROFF0_Pos (0) /*!< SDH_T::ECTL: POWEROFF0 Position */
#define SDH_ECTL_POWEROFF0_Msk (0x1ul << SDH_ECTL_POWEROFF0_Pos) /*!< SDH_T::ECTL: POWEROFF0 Mask */
#define SDH_ECTL_POWEROFF1_Pos (1) /*!< SDH_T::ECTL: POWEROFF1 Position */
#define SDH_ECTL_POWEROFF1_Msk (0x1ul << SDH_ECTL_POWEROFF1_Pos) /*!< SDH_T::ECTL: POWEROFF1 Mask */
/**@}*/ /* SDH_CONST */
/**@}*/ /* end of SDH register group */
/**@}*/ /* end of REGISTER group */
@@ -645,7 +652,6 @@ typedef struct SDH_info_t
/*@}*/ /* end of group N9H30_SDH_EXPORTED_TYPEDEF */
/// @cond HIDDEN_SYMBOLS
extern SDH_INFO_T SD0, SD1;
/// @endcond HIDDEN_SYMBOLS
@@ -724,7 +730,7 @@ extern SDH_INFO_T SD0, SD1;
* 0: Card removed.
* \hideinitializer
*/
#define SDH_IS_CARD_PRESENT(sdh) (((sdh) == SDH0)? SD0.IsCardInsert : SD1.IsCardInsert)
//#define SDH_IS_CARD_PRESENT(sdh) (((sdh) == SDH0)? SD0.IsCardInsert : SD1.IsCardInsert)
/**
* @brief Get SD Card capacity.
@@ -734,17 +740,18 @@ extern SDH_INFO_T SD0, SD1;
* @return SD Card capacity. (unit: KByte)
* \hideinitializer
*/
#define SDH_GET_CARD_CAPACITY(sdh) (((sdh) == SDH0)? SD0.diskSize : SD1.diskSize)
//#define SDH_GET_CARD_CAPACITY(sdh) (((sdh) == SDH0)? SD0.diskSize : SD1.diskSize)
void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc);
uint32_t SDH_Probe(SDH_T *sdh);
uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount);
uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount);
uint32_t SDH_CardDetection(SDH_T *sdh);
void SDH_Open_Disk(SDH_T *sdh, uint32_t u32CardDetSrc);
void SDH_Close_Disk(SDH_T *sdh);
void SDH_Open(SDH_T *sdh, SDH_INFO_T *pSD, uint32_t u32CardDetSrc);
uint32_t SDH_Probe(SDH_T *sdh, SDH_INFO_T *pSD, uint32_t card_num);
uint32_t SDH_Read(SDH_T *sdh, SDH_INFO_T *pSD, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount);
uint32_t SDH_Write(SDH_T *sdh, SDH_INFO_T *pSD, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount);
void SDH_CardSelect(SDH_T *sdh, SDH_INFO_T *pSD, uint32_t u32CardSrc);
uint32_t SDH_CardDetection(SDH_T *sdh, SDH_INFO_T *pSD, uint32_t card_num);
void SDH_Open_Disk(SDH_T *sdh, SDH_INFO_T *pSD, uint32_t u32CardDetSrc);
void SDH_Close_Disk(SDH_T *sdh, SDH_INFO_T *pSD);
uint32_t SDH_WhichCardIsSelected(SDH_T *sdh);
/*@}*/ /* end of group N9H30_SDH_EXPORTED_FUNCTIONS */
bsp/nuvoton/libraries/n9h30/Driver/Source/nu_sdh.c
+202 -212
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File diff suppressed because it is too large. Load diff
bsp/nuvoton/libraries/n9h30/UsbHostLib/src/ehci.c
+4 -3
View File
@@ -297,6 +297,8 @@ static int ehci_init(void)
_ehci->UCFGR = 0x1; /* enable port routing to EHCI */
_ehci->UIENR = HSUSBH_UIENR_USBIEN_Msk | HSUSBH_UIENR_UERRIEN_Msk | HSUSBH_UIENR_HSERREN_Msk | HSUSBH_UIENR_IAAEN_Msk;
_ehci->UASSTR = 0xfff;
usbh_delay_ms(1); /* delay 1 ms */
_ehci->UPSCR[0] = HSUSBH_UPSCR_PP_Msk; /* enable port 1 port power */
@@ -905,7 +907,7 @@ static int visit_qtd(qTD_T *qtd)
return 0;
}
static void scan_asynchronous_list()
void scan_asynchronous_list()
{
QH_T *qh, *qh_tmp;
qTD_T *q_pre, *qtd, *qtd_tmp;
@@ -1094,9 +1096,8 @@ void iaad_remove_qh()
//void EHCI_IRQHandler(void)
void nu_ehci_isr(int vector, void *param)
{
uint32_t intsts;
volatile uint32_t intsts = _ehci->USTSR;
intsts = _ehci->USTSR;
_ehci->USTSR = intsts; /* clear interrupt status */
//USB_debug("ehci int_sts = 0x%x\n", intsts);
bsp/nuvoton/libraries/n9h30/UsbHostLib/src/support.c
+61 -103
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File diff suppressed because it is too large. Load diff
bsp/nuvoton/libraries/n9h30/UsbHostLib/src/usb_core.c
+2 -2
View File
@@ -67,7 +67,7 @@ void usbh_core_init()
#ifdef ENABLE_OHCI
//sysInstallISR(IRQ_LEVEL_1, IRQ_OHCI, (PVOID)OHCI_IRQHandler);
rt_hw_interrupt_install(IRQ_OHCI, nu_ohci_isr, NULL, "ohci");
rt_hw_interrupt_set_priority(IRQ_OHCI, IRQ_LEVEL_1);
//rt_hw_interrupt_set_priority(IRQ_OHCI, IRQ_LEVEL_1);
ohci_driver.init();
ENABLE_OHCI_IRQ();
@@ -76,7 +76,7 @@ void usbh_core_init()
#ifdef ENABLE_EHCI
//sysInstallISR(IRQ_LEVEL_1, IRQ_EHCI, (PVOID)EHCI_IRQHandler);
rt_hw_interrupt_install(IRQ_EHCI, nu_ehci_isr, NULL, "ehci");
rt_hw_interrupt_set_priority(IRQ_EHCI, IRQ_LEVEL_1);
//rt_hw_interrupt_set_priority(IRQ_EHCI, IRQ_LEVEL_1);
ehci_driver.init();
ENABLE_EHCI_IRQ();
bsp/nuvoton/libraries/n9h30/rtt_port/Kconfig
+6 -2
View File
@@ -275,11 +275,15 @@ config SOC_SERIES_N9H30
select RT_USING_DFS
if BSP_USING_SDH
config BSP_USING_EMMC
bool "Enable FMI_EMMC"
config BSP_USING_SDH0
bool "Enable SDH0"
bool "Enable SDH_PORT0"
config BSP_USING_SDH1
bool "Enable SDH1"
bool "Enable SDH_PORT1"
config NU_SDH_HOTPLUG
bool "Using HOTPLUG"
bsp/nuvoton/libraries/n9h30/rtt_port/drv_ge2d.c
+1 -1
View File
@@ -12,7 +12,7 @@
#include <drv_sys.h>
//#define DEBUG
//#define DEF_COND_WAIT 1
#define DEF_COND_WAIT 1
static unsigned int GFX_BPP;
static unsigned int GFX_WIDTH;
bsp/nuvoton/libraries/n9h30/rtt_port/drv_i2s.c
+5 -5
View File
@@ -244,6 +244,11 @@ static rt_err_t nu_i2s_dai_setup(nu_i2s_t psNuI2s, struct rt_audio_configure *pc
i2sIoctl(I2S_SET_I2S_FORMAT, I2S_FORMAT_I2S, 0);
if (psNuI2s->AcodecOps->role == NU_ACODEC_ROLE_MASTER)
{
// Set as slave, source clock is XIN (12MHz)
i2sIoctl(I2S_SET_MODE, I2S_MODE_SLAVE, 0);
}
else
{
if (pconfig->samplerate % 11025)
{
@@ -284,11 +289,6 @@ static rt_err_t nu_i2s_dai_setup(nu_i2s_t psNuI2s, struct rt_audio_configure *pc
// Set as master
i2sIoctl(I2S_SET_MODE, I2S_MODE_MASTER, 0);
}
else
{
// Set as slave, source clock is XIN (12MHz)
i2sIoctl(I2S_SET_MODE, I2S_MODE_SLAVE, 0);
}
LOG_I("Open I2S.");
bsp/nuvoton/libraries/n9h30/rtt_port/drv_sdh.c
+221 -32
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File diff suppressed because it is too large. Load diff
bsp/nuvoton/libraries/n9h30/rtt_port/drv_sys.c
+12 -8
View File
@@ -48,19 +48,23 @@ void rt_interrupt_dispatch(rt_uint32_t fiq_irq)
/* Get irq number */
_mIPER = (inpw(REG_AIC_IPER) >> 2) & 0x3f;
_mISNR = inpw(REG_AIC_ISNR) & 0x3f;
if ((_mIPER != _mISNR) || _mISNR == 0)
return;
/* Get interrupt service routine */
isr_func = irq_desc[_mISNR].handler;
param = irq_desc[_mISNR].param;
if (_mISNR != 0)
{
if (_mIPER == _mISNR)
{
/* Get interrupt service routine */
isr_func = irq_desc[_mISNR].handler;
param = irq_desc[_mISNR].param;
#ifdef RT_USING_INTERRUPT_INFO
irq_desc[_mISNR].counter ++;
irq_desc[_mISNR].counter ++;
#endif
/* Turn to interrupt service routine */
isr_func(_mISNR, param);
/* Turn to interrupt service routine */
isr_func(_mISNR, param);
}
}
/* Handled the ISR. */
outpw(REG_AIC_EOSCR, 1);
bsp/nuvoton/libraries/n9h30/rtt_port/drv_usbhost.c
+93 -30
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File diff suppressed because it is too large. Load diff
bsp/nuvoton/libraries/nu_packages/AudioCodec/acodec_nau8822.c
+47 -12
View File
@@ -40,7 +40,7 @@ static rt_err_t nau8822_mixer_query(rt_uint32_t ui32Units, rt_uint32_t *ui32Valu
nu_acodec_ops nu_acodec_ops_nau8822 =
{
.name = "NAU8822",
.role = NU_ACODEC_ROLE_SLAVE,
.role = NU_ACODEC_ROLE_MASTER,
.config = { // Default settings.
.samplerate = 16000,
.channels = 2,
@@ -117,6 +117,20 @@ static int I2C_WriteNAU8822(uint8_t u8addr, uint16_t u16data)
return RT_EOK;
}
static void nau8822_phonejack_set(S_NU_NAU8822_CONFIG *psCodecConfig, int bEnable)
{
rt_pin_mode(psCodecConfig->pin_phonejack_en, PIN_MODE_OUTPUT);
if (bEnable)
{
rt_pin_write(psCodecConfig->pin_phonejack_en, PIN_LOW);
}
else
{
rt_pin_write(psCodecConfig->pin_phonejack_en, PIN_HIGH);
}
}
static rt_err_t nau8822_probe(void)
{
@@ -180,8 +194,6 @@ static rt_err_t nau8822_dsp_config(rt_uint32_t ui32SamplRate, rt_uint8_t u8ChNum
}
u16AudIf = (u16AudIf & 0x19F) | (u8WLEN << 5);
I2C_WriteNAU8822(4, u16AudIf);
if (ui32SamplRate % 11025)
{
I2C_WriteNAU8822(36, 0x008); //12.288Mhz
@@ -189,6 +201,10 @@ static rt_err_t nau8822_dsp_config(rt_uint32_t ui32SamplRate, rt_uint8_t u8ChNum
I2C_WriteNAU8822(38, 0x093);
I2C_WriteNAU8822(39, 0x0E9);
/* FIXME */
if (ui32SamplRate > 48000)
ui32SamplRate = 8000;
mClkDiv = (48000 * 256 * u8ChNum) / (ui32SamplRate * 256);
bClkDiv = (ui32SamplRate * 256) / (ui32SamplRate * u8ChNum * u8SamplBit);
}
@@ -199,6 +215,10 @@ static rt_err_t nau8822_dsp_config(rt_uint32_t ui32SamplRate, rt_uint8_t u8ChNum
I2C_WriteNAU8822(38, 0x161);
I2C_WriteNAU8822(39, 0x026);
/* FIXME */
if (ui32SamplRate > 44100)
ui32SamplRate = 11025;
mClkDiv = (44100 * 256 * u8ChNum) / (ui32SamplRate * 256);
bClkDiv = (ui32SamplRate * 256) / (ui32SamplRate * u8ChNum * u8SamplBit);
}
@@ -258,11 +278,16 @@ static rt_err_t nau8822_dsp_config(rt_uint32_t ui32SamplRate, rt_uint8_t u8ChNum
return -RT_ERROR;
}
u16ClkCtrl = (1 << 8) | (1 << 0); //Use internal PLL, FS/BCLK
if (nu_acodec_ops_nau8822.role == NU_ACODEC_ROLE_MASTER)
{
u16ClkCtrl = (1 << 8) | (1 << 0); //Use internal PLL, FS/BCLK
}
u16ClkCtrl = (u16ClkCtrl & 0x11F) | (mClkDiv << 5);
u16ClkCtrl = (u16ClkCtrl & 0x1E3) | (bClkDiv << 2);
I2C_WriteNAU8822(4, u16AudIf);
I2C_WriteNAU8822(6, u16ClkCtrl);
return RT_EOK;
@@ -271,28 +296,36 @@ static rt_err_t nau8822_dsp_config(rt_uint32_t ui32SamplRate, rt_uint8_t u8ChNum
static rt_err_t nau8822_init(void)
{
//input source is MIC
I2C_WriteNAU8822(1, 0x03F);
if (nu_acodec_ops_nau8822.role == NU_ACODEC_ROLE_MASTER)
{
I2C_WriteNAU8822(1, 0x03F); /* PLLEN, MICBIASEN, ABIASEN, IOBUFEN, REFIMP(3kohm) */
}
else
{
I2C_WriteNAU8822(1, 0x01F); /* MICBIASEN, ABIASEN, IOBUFEN, REFIMP(3kohm) */
}
I2C_WriteNAU8822(2, 0x1BF); /* Enable L/R Headphone, ADC Mix/Boost, ADC */
I2C_WriteNAU8822(3, 0x07F); /* Enable L/R main mixer, DAC */
I2C_WriteNAU8822(4, 0x010); /* 16-bit word length, I2S format, Stereo */
I2C_WriteNAU8822(5, 0x000); /* Companding control and loop back mode (all disable) */
nau8822_delay_ms(30);
if (nu_acodec_ops_nau8822.role == NU_ACODEC_ROLE_SLAVE)
{
I2C_WriteNAU8822(6, 0x1AD); /* Divide by 6, 16K */
I2C_WriteNAU8822(7, 0x006); /* 16K for internal filter coefficients */
}
I2C_WriteNAU8822(6, 0x1AD); /* Divide by 6, 16K */
I2C_WriteNAU8822(7, 0x006); /* 16K for internal filter coefficients */
I2C_WriteNAU8822(10, 0x008); /* DAC soft mute is disabled, DAC oversampling rate is 128x */
I2C_WriteNAU8822(14, 0x108); /* ADC HP filter is disabled, ADC oversampling rate is 128x */
I2C_WriteNAU8822(15, 0x1EF); /* ADC left digital volume control */
I2C_WriteNAU8822(16, 0x1EF); /* ADC right digital volume control */
I2C_WriteNAU8822(44, 0x033); /* LMICN/LMICP is connected to PGA */
I2C_WriteNAU8822(49, 0x042);
I2C_WriteNAU8822(47, 0x100); /* Gain value */
I2C_WriteNAU8822(48, 0x100); /* Gain value */
I2C_WriteNAU8822(50, 0x001); /* Left DAC connected to LMIX */
I2C_WriteNAU8822(51, 0x001); /* Right DAC connected to RMIX */
I2C_WriteNAU8822(0x34, 0x13F);
I2C_WriteNAU8822(0x35, 0x13F);
nu_acodec_ops_nau8822.config.samplerate = 16000;
nu_acodec_ops_nau8822.config.channels = 2;
nu_acodec_ops_nau8822.config.samplebits = 16;
@@ -326,10 +359,12 @@ static rt_err_t nau8822_mixer_control(rt_uint32_t ui32Units, rt_uint32_t ui32Val
if (ui32Value)
{
I2C_WriteNAU8822(10, u16Data | (1 << 6));
nau8822_phonejack_set(g_psCodecConfig, 0);
}
else
{
I2C_WriteNAU8822(10, u16Data & ~(1 << 6));
nau8822_phonejack_set(g_psCodecConfig, 1);
}
}
break;
bsp/nuvoton/libraries/nu_packages/BMX055/sensor_bmx055.c
+1
View File
@@ -14,6 +14,7 @@
#if defined(NU_PKG_USING_BMX055)
#include <sys/time.h>
#include <string.h>
#include "sensor_bmx055.h"
bsp/nuvoton/libraries/nu_packages/Kconfig
+5
View File
@@ -29,6 +29,11 @@ menu "Nuvoton Packages Config"
select BSP_USING_I2C
default n
config NU_PKG_USING_DA9062
bool "DA9062 PMIC."
select BSP_USING_I2C
default n
config NU_PKG_USING_ILI9341
bool "ILI9341 LCD Panel"
select BSP_USING_GPIO
bsp/nuvoton/libraries/nu_packages/MAX31875/sensor_max31875.c
+1
View File
@@ -14,6 +14,7 @@
#if defined(NU_PKG_USING_MAX31875)
#include <sys/time.h>
#include "sensor.h"
#include "max31875_c.h"
bsp/nuvoton/libraries/nu_packages/SPINAND/drv_spinand.c
+2 -1
View File
@@ -498,7 +498,8 @@ rt_err_t rt_hw_mtd_spinand_init(void)
RT_ASSERT(result == RT_EOK);
result = spinand_flash_init(SPINAND_FLASH_QSPI);
RT_ASSERT(result == RT_EOK);
if (result != RT_EOK)
return -RT_ERROR;
for (i = 0; i < MTD_SPINAND_PARTITION_NUM; i++)
{
bsp/nuvoton/libraries/nu_packages/SPINAND/spinand.c
+104 -21
View File
@@ -26,7 +26,48 @@
const struct nu_spinand_info g_spinandflash_list[] =
{
/* Winbond */
{ 0xEFAA21, 2048, 64, 0x6b, 0xff, 0xff, 0xff, 0x1, 1024, 64, 0, "Winbond 128MB: 2048+64@64@1024" }, /* Only tested */
/* Only tested */
{
0xEFAA21, 2048, 64, 0x6b, 0xff, 0xff, 0xff, 0x1, 1024, 64, 0, "Winbond 128MB: 2048+64@64@1024",
#if defined(RT_USING_DFS_UFFS)
{
/* For storing Seal-byte at 0x37. Need 15-Bytes */
0x04, 0x04, 0x14, 0x04, 0x24, 0x04, 0x34, 0x03, 0xFF, 0x00
},
{
/* For storing Seal-byte at 0x37 and not report latest ECC part in Spare-3 */
0x08, 0x08, 0x18, 0x08, 0x28, 0x08, /*0x38, 0x08,*/ 0xFF, 0x00
}
#else
{
0x04, 0x04, 0x14, 0x04, 0x24, 0x04, 0x34, 0x04, 0xFF, 0x00
},
{
0x08, 0x08, 0x18, 0x08, 0x28, 0x08, 0x38, 0x08, 0xFF, 0x00
}
#endif
},
{
0xEFBF22, 2048, 64, 0x6b, 0xff, 0xff, 0xff, 0x1, 2048, 64, 0, "Winbond 256MB: 2048+64@64@2048",
#if defined(RT_USING_DFS_UFFS)
{
/* For storing Seal-byte at 0x39. Need 15-Bytes */
0x08, 0x04, 0x18, 0x04, 0x28, 0x04, 0x38, 0x03, 0xFF, 0x00
},
{
/* For storing Seal-byte at 0x39 and not report latest ECC part in Spare-3 */
0x0C, 0x04, 0x1C, 0x04, 0x2C, 0x04, /*0x3C, 0x04,*/ 0xFF, 0x00
}
#else
{
0x08, 0x04, 0x18, 0x04, 0x28, 0x04, 0x38, 0x04, 0xFF, 0x00
},
{
0x0C, 0x04, 0x1C, 0x04, 0x2C, 0x04, 0x3C, 0x04, 0xFF, 0x00
}
#endif
},
#if 0
{ 0xEFAA22, 2048, 64, 0x6b, 0xff, 0xff, 0xff, 0x1, 2048, 64, 0, "Winbond 256MB: 2048+64@64@1024" },
@@ -61,6 +102,7 @@ const struct nu_spinand_info g_spinandflash_list[] =
/*
========================================================
For 0xEFAA21 description:
Data Area(2048-Byte)
@@ -112,27 +154,66 @@ ECC Spare: ECC for spare 4-D.
| 0 1 2 3 | 4 5 6 7 | 8 9 A B C D | E F |
-----------------------------------------------
| NO ECC | ECC PROTECTED | ECC 34-3D |
========================================================
========================================================
For 0xEFBF22 description:
Data Area(2048-Byte)
-----------------------------
|Sect-0|Sect-1|Sect-2|Sect-3|
|(512B)|(512B)|(512B)|(512B)|
-----------------------------
Spare Area(64-Byte)
---------------------------------
|Spare-0|Spare-1|Spare-2|Spare-3|
| (16B) | (16B) | (16B) | (16B) |
---------------------------------
----------------- Spare-0 -------------------
/ \
-----------------------------------------
| BBM | UD2 | UD1 | ECC UD1 |
| 0 1 | 2 3 4 5 6 7 | 8 9 A B | C D E F |
-----------------------------------------
| NO ECC | ECC PROTECTED |
BBM: Bad block marker.
UD1: User Data 1.
UD2: User Data 2.
ECC UD1: ECC for UD1.
---------------- Spare-1 -------------------
/ \
---------------------------------------
| UD2 | UD1 | ECC UD1 |
| 0 1 2 3 4 5 6 7 | 8 9 A B | C D E F |
---------------------------------------
| NO ECC | ECC PROTECTED |
---------------- Spare-2 -------------------
/ \
---------------------------------------
| UD2 | UD1 | ECC UD1 |
| 0 1 2 3 4 5 6 7 | 8 9 A B | C D E F |
---------------------------------------
| NO ECC | ECC PROTECTED |
---------------- Spare-3 -------------------
/ \
---------------------------------------
| UD2 | UD1 | ECC UD1 |
| 0 1 2 3 4 5 6 7 | 8 9 A B | C D E F |
---------------------------------------
| NO ECC | ECC PROTECTED |
========================================================
*/
rt_uint8_t spinand_flash_data_layout[SPINAND_SPARE_LAYOUT_SIZE] =
{
#if defined(RT_USING_DFS_UFFS)
/* For storing Seal-byte at 0x37. */
0x04, 0x04, 0x14, 0x04, 0x24, 0x04, 0x34, 0x03, 0xFF, 0x00
#else
0x04, 0x04, 0x14, 0x04, 0x24, 0x04, 0x34, 0x04, 0xFF, 0x00
#endif
};
rt_uint8_t spinand_flash_ecc_layout[SPINAND_SPARE_LAYOUT_SIZE] =
{
#if defined(RT_USING_DFS_UFFS)
/* For storing Seal-byte at 0x37 and not report latest ECC part in Spare-3 */
0x08, 0x08, 0x18, 0x08, 0x28, 0x08, /*0x38, 0x08,*/ 0xFF, 0x00
#else
0x08, 0x08, 0x18, 0x08, 0x28, 0x08, 0x38, 0x08, 0xFF, 0x00
#endif
};
rt_uint8_t spinand_flash_data_layout[SPINAND_SPARE_LAYOUT_SIZE];
rt_uint8_t spinand_flash_ecc_layout[SPINAND_SPARE_LAYOUT_SIZE];
static rt_err_t spinand_info_read(struct rt_qspi_device *qspi);
@@ -186,7 +267,6 @@ static rt_err_t spinand_program_dataload(
uint8_t *pu8SpareBuff,
uint32_t u32SpareCount)
{
uint32_t volatile i = 0;
uint8_t u8WECmd = 0x06;
rt_err_t result = RT_EOK;
@@ -667,6 +747,9 @@ static rt_err_t spinand_info_read(struct rt_qspi_device *qspi)
{
if (u32JedecId == g_spinandflash_list[i].u32JEDECID) /* Match JEDECID? */
{
rt_memcpy((void *)&spinand_flash_data_layout[0], (void *)&g_spinandflash_list[i].au8DataLayout[0], SPINAND_SPARE_LAYOUT_SIZE);
rt_memcpy((void *)&spinand_flash_ecc_layout[0], (void *)&g_spinandflash_list[i].au8EccLayout[0], SPINAND_SPARE_LAYOUT_SIZE);
rt_memcpy(SPINAND_FLASH_INFO, &g_spinandflash_list[i], sizeof(struct nu_spinand_info));
LOG_I("Found: [%08X] %s.", u32JedecId, SPINAND_FLASH_DESCRIPTION);
bsp/nuvoton/libraries/nu_packages/SPINAND/spinand.h
+30 -27
View File
@@ -19,24 +19,6 @@
#include "drv_spi.h"
#include <board.h>
/* SPI NAND flash information */
struct nu_spinand_info
{
uint32_t u32JEDECID;
uint16_t u16PageSize;
uint16_t u16OOBSize;
uint8_t u8QuadReadCmdId;
uint8_t u8ReadStatusCmdId;
uint8_t u8WriteStatusCmdid;
uint8_t u8StatusValue;
uint8_t u8DummyByte;
uint32_t u32BlockPerFlash;
uint32_t u32PagePerBlock;
uint8_t u8IsDieSelect;
const char *szDescription;
};
typedef struct nu_spinand_info *nu_spinand_info_t;
struct spinand_ops
{
rt_err_t (*block_erase)(struct rt_qspi_device *qspi, uint8_t u8Addr2, uint8_t u8Addr1, uint8_t u8Addr0);
@@ -53,15 +35,6 @@ struct spinand_ops
};
typedef struct spinand_ops *nu_spinand_ops_t;
struct nu_spinand
{
struct nu_spinand_info info;
struct rt_qspi_device *qspi_device;
nu_spinand_ops_t ops;
struct rt_mutex lock;
};
typedef struct nu_spinand *nu_spinand_t;
#define SPINAND_FLASH_JEDECID g_spinandflash_dev.info.u32JEDECID
#define SPINAND_FLASH_PAGE_SIZE g_spinandflash_dev.info.u16PageSize
#define SPINAND_FLASH_OOB_SIZE g_spinandflash_dev.info.u16OOBSize
@@ -82,6 +55,36 @@ typedef struct nu_spinand *nu_spinand_t;
#define SPINAND_SPARE_LAYOUT_SIZE 16
/* SPI NAND flash information */
struct nu_spinand_info
{
uint32_t u32JEDECID;
uint16_t u16PageSize;
uint16_t u16OOBSize;
uint8_t u8QuadReadCmdId;
uint8_t u8ReadStatusCmdId;
uint8_t u8WriteStatusCmdid;
uint8_t u8StatusValue;
uint8_t u8DummyByte;
uint32_t u32BlockPerFlash;
uint32_t u32PagePerBlock;
uint8_t u8IsDieSelect;
const char *szDescription;
uint8_t au8DataLayout[SPINAND_SPARE_LAYOUT_SIZE];
uint8_t au8EccLayout[SPINAND_SPARE_LAYOUT_SIZE];
};
typedef struct nu_spinand_info *nu_spinand_info_t;
struct nu_spinand
{
struct nu_spinand_info info;
struct rt_qspi_device *qspi_device;
nu_spinand_ops_t ops;
struct rt_mutex lock;
};
typedef struct nu_spinand *nu_spinand_t;
rt_err_t rt_hw_mtd_spinand_register(const char *device_name);
rt_size_t nu_qspi_transfer_message(struct rt_qspi_device *device, struct rt_qspi_message *message);
rt_err_t nu_qspi_send_then_recv(struct rt_qspi_device *device, const void *send_buf, rt_size_t send_length, void *recv_buf, rt_size_t recv_length);
bsp/nuvoton/libraries/nuc980/Driver/Include/nu_emac.h
+6 -3
View File
@@ -30,8 +30,8 @@ extern "C"
*/
#define EMAC_PHY_ADDR 1UL /*!< PHY address, this address is board dependent \hideinitializer */
#define EMAC_RX_DESC_SIZE 64UL /*!< Number of Rx Descriptors, should be 2 at least \hideinitializer */
#define EMAC_TX_DESC_SIZE 32UL /*!< Number of Tx Descriptors, should be 2 at least \hideinitializer */
#define EMAC_RX_DESC_SIZE 128UL /*!< Number of Rx Descriptors, should be 2 at least \hideinitializer */
#define EMAC_TX_DESC_SIZE 64UL /*!< Number of Tx Descriptors, should be 2 at least \hideinitializer */
#define EMAC_CAMENTRY_NB 16UL /*!< Number of CAM \hideinitializer */
#define EMAC_MAX_PKT_SIZE 1536UL /*!< Number of HDR + EXTRA + VLAN_TAG + PAYLOAD + CRC \hideinitializer */
@@ -53,6 +53,8 @@ typedef struct
uint32_t u32Next; /*!< Pointer to next descriptor */
uint32_t u32Backup1; /*!< For backup descriptor fields over written by time stamp */
uint32_t u32Backup2; /*!< For backup descriptor fields over written by time stamp */
uint32_t u32Reserved1; /*!< For Reserved */
uint32_t u32Reserved2; /*!< For Reserved */
} EMAC_DESCRIPTOR_T;
/** Tx/Rx buffer structure */
@@ -379,7 +381,8 @@ int32_t EMAC_FillCamEntry(EMAC_T *EMAC, uint8_t pu8MacAddr[]);
uint8_t *EMAC_ClaimFreeTXBuf(EMAC_MEMMGR_T *psMemMgr);
uint32_t EMAC_GetAvailRXBufSize(EMAC_MEMMGR_T *psMemMgr, uint8_t **ppuDataBuf);
uint32_t EMAC_SendPktWoCopy(EMAC_MEMMGR_T *psMemMgr, uint32_t u32Size);
void EMAC_RecvPktDoneWoRxTrigger(EMAC_MEMMGR_T *psMemMgr);
EMAC_DESCRIPTOR_T * EMAC_RecvPktDoneWoRxTrigger(EMAC_MEMMGR_T *psMemMgr);
void EMAC_RxTrigger(EMAC_MEMMGR_T *psMemMgr, EMAC_DESCRIPTOR_T * rx_desc);
/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */
bsp/nuvoton/libraries/nuc980/Driver/Source/nu_emac.c
+15 -3
View File
@@ -298,7 +298,7 @@ static void EMAC_RxDescInit(EMAC_MEMMGR_T *psMemMgr)
for (i = 0UL; i < psMemMgr->u32RxDescSize; i++)
{
psMemMgr->psRXDescs[i].u32Status1 = EMAC_DESC_OWN_EMAC;
psMemMgr->psRXDescs[i].u32Data = (uint32_t)&psMemMgr->psRXFrames[i] | BIT31;
psMemMgr->psRXDescs[i].u32Data = (uint32_t)&psMemMgr->psRXFrames[i];
psMemMgr->psRXDescs[i].u32Status2 = 0UL;
psMemMgr->psRXDescs[i].u32Next = (uint32_t)(&psMemMgr->psRXDescs[(i + 1UL) % EMAC_RX_DESC_SIZE]) | BIT31;
psMemMgr->psRXDescs[i].u32Backup1 = psMemMgr->psRXDescs[i].u32Data;
@@ -1129,25 +1129,37 @@ uint32_t EMAC_GetAvailRXBufSize(EMAC_MEMMGR_T *psMemMgr, uint8_t **ppuDataBuf)
* @note Application can only call this function once every time \ref EMAC_RecvPkt or \ref EMAC_RecvPktTS returns 1
* @note This function is without doing EMAC_TRIGGER_RX.
*/
void EMAC_RecvPktDoneWoRxTrigger(EMAC_MEMMGR_T *psMemMgr)
EMAC_DESCRIPTOR_T * EMAC_RecvPktDoneWoRxTrigger(EMAC_MEMMGR_T *psMemMgr)
{
/* Get Rx Frame Descriptor */
EMAC_DESCRIPTOR_T *desc = (EMAC_DESCRIPTOR_T *)psMemMgr->psCurrentRxDesc;
EMAC_DESCRIPTOR_T *ret = desc;
/* Restore descriptor link list and data pointer they will be overwrite if time stamp enabled */
desc->u32Data = desc->u32Backup1;
desc->u32Next = desc->u32Backup2;
/* Change ownership to DMA for next use */
desc->u32Status1 |= EMAC_DESC_OWN_EMAC;
// desc->u32Status1 |= EMAC_DESC_OWN_EMAC;
/* Get Next Frame Descriptor pointer to process */
desc = (EMAC_DESCRIPTOR_T *)desc->u32Next;
/* Save last processed Rx descriptor */
psMemMgr->psCurrentRxDesc = desc;
return ret;
}
void EMAC_RxTrigger(EMAC_MEMMGR_T *psMemMgr, EMAC_DESCRIPTOR_T * rx_desc)
{
EMAC_T *EMAC = psMemMgr->psEmac;
rx_desc->u32Status1 |= EMAC_DESC_OWN_EMAC;
/* Trigger EMAC to send the packet */
EMAC_TRIGGER_RX(EMAC);
}
/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */
bsp/nuvoton/libraries/nuc980/Driver/Source/nu_pdma.c
+39 -86
View File
@@ -8,9 +8,6 @@
#include "nuc980.h"
#include "nu_pdma.h"
static uint8_t u32ChSelect[PDMA_CH_MAX];
/** @addtogroup Standard_Driver Standard Driver
@{
*/
@@ -44,7 +41,6 @@ void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask)
if ((1 << i) & u32Mask)
{
pdma->DSCT[i].CTL = 0UL;
u32ChSelect[i] = PDMA_MEM;
}
}
@@ -188,54 +184,27 @@ void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uin
*/
void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
{
u32ChSelect[u32Ch] = u32Peripheral;
switch (u32Ch)
if (u32Ch < PDMA_CH_MAX)
{
case 0ul:
pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral;
break;
case 1ul:
pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos);
break;
case 2ul:
pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos);
break;
case 3ul:
pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos);
break;
case 4ul:
pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral;
break;
case 5ul:
pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos);
break;
case 6ul:
pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos);
break;
case 7ul:
pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos);
break;
case 8ul:
pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC8_Msk) | u32Peripheral;
break;
case 9ul:
pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC9_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC9_Pos);
break;
default:
break;
}
__IO uint32_t *pau32REQSEL = (__IO uint32_t *)&pdma->REQSEL0_3;
uint32_t u32REQSEL_Pos, u32REQSEL_Msk;
if (u32ScatterEn)
{
pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
pdma->DSCT[u32Ch].NEXT = u32DescAddr - (pdma->SCATBA);
}
else
{
pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC;
u32REQSEL_Pos = (u32Ch % 4) * 8 ;
u32REQSEL_Msk = PDMA_REQSEL0_3_REQSRC0_Msk << u32REQSEL_Pos;
pau32REQSEL[u32Ch / 4] = (pau32REQSEL[u32Ch / 4] & ~u32REQSEL_Msk) | (u32Peripheral << u32REQSEL_Pos);
if (u32ScatterEn)
{
pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
pdma->DSCT[u32Ch].NEXT = u32DescAddr - (pdma->SCATBA);
}
else
{
pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC;
}
}
else {}
}
/**
* @brief Set PDMA Burst Type and Size
*
@@ -310,45 +279,21 @@ void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask)
*/
void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
{
switch (u32Ch)
if (u32Ch < PDMA_CH_MAX)
{
case 0ul:
pdma->TOC0_1 = (pdma->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt;
break;
case 1ul:
pdma->TOC0_1 = (pdma->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos);
break;
case 2ul:
pdma->TOC2_3 = (pdma->TOC2_3 & ~PDMA_TOC2_3_TOC2_Msk) | u32TimeOutCnt;
break;
case 3ul:
pdma->TOC2_3 = (pdma->TOC2_3 & ~PDMA_TOC2_3_TOC3_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos);
break;
case 4ul:
pdma->TOC4_5 = (pdma->TOC4_5 & ~PDMA_TOC4_5_TOC4_Msk) | u32TimeOutCnt;
break;
case 5ul:
pdma->TOC4_5 = (pdma->TOC4_5 & ~PDMA_TOC4_5_TOC5_Msk) | (u32TimeOutCnt << PDMA_TOC4_5_TOC5_Pos);
break;
case 6ul:
pdma->TOC6_7 = (pdma->TOC6_7 & ~PDMA_TOC6_7_TOC6_Msk) | u32TimeOutCnt;
break;
case 7ul:
pdma->TOC6_7 = (pdma->TOC6_7 & ~PDMA_TOC6_7_TOC7_Msk) | (u32TimeOutCnt << PDMA_TOC6_7_TOC7_Pos);
break;
case 8ul:
pdma->TOC8_9 = (pdma->TOC8_9 & ~PDMA_TOC8_9_TOC8_Msk) | u32TimeOutCnt;
break;
case 9ul:
pdma->TOC8_9 = (pdma->TOC8_9 & ~PDMA_TOC8_9_TOC9_Msk) | (u32TimeOutCnt << PDMA_TOC8_9_TOC9_Pos);
break;
default:
break;
__IO uint32_t *pau32TOC = (__IO uint32_t *)&pdma->TOC0_1;
uint32_t u32TOC_Pos, u32TOC_Msk;
u32TOC_Pos = (u32Ch % 2) * 16 ;
u32TOC_Msk = PDMA_TOC0_1_TOC0_Msk << u32TOC_Pos;
pau32TOC[u32Ch / 2] = (pau32TOC[u32Ch / 2] & ~u32TOC_Msk) | (u32TimeOutCnt << u32TOC_Pos);
if (u32OnOff)
pdma->TOUTEN |= (1 << u32Ch);
else
pdma->TOUTEN &= ~(1 << u32Ch);
}
if (u32OnOff)
pdma->TOUTEN |= (1 << u32Ch);
else
pdma->TOUTEN &= ~(1 << u32Ch);
else {}
}
/**
@@ -363,7 +308,15 @@ void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u
*/
void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch)
{
if (u32ChSelect[u32Ch] == PDMA_MEM)
__IO uint32_t *pau32REQSEL = (__IO uint32_t *)&pdma->REQSEL0_3;
uint32_t u32REQSEL_Pos, u32REQSEL_Msk, u32ChReq;
u32REQSEL_Pos = (u32Ch % 4) * 8 ;
u32REQSEL_Msk = PDMA_REQSEL0_3_REQSRC0_Msk << u32REQSEL_Pos;
u32ChReq = (pau32REQSEL[u32Ch / 4] & u32REQSEL_Msk) >> u32REQSEL_Pos;
if (u32ChReq == PDMA_MEM)
{
pdma->SWREQ = (1ul << u32Ch);
}
bsp/nuvoton/libraries/nuc980/UsbHostLib/inc/config.h
+2 -2
View File
@@ -33,7 +33,7 @@
#define DISABLE_EHCI_IRQ() rt_hw_interrupt_mask(IRQ_EHCI)
#define IS_EHCI_IRQ_ENABLED() ((inpw(REG_AIC_INTMSK0)>>IRQ_EHCI) & 0x1)
//#define ENABLE_OHCI /* Enable OHCI host controller */
#define ENABLE_OHCI /* Enable OHCI host controller */
#define ENABLE_EHCI /* Enable EHCI host controller */
#define EHCI_PORT_CNT 2 /* Number of EHCI roothub ports */
@@ -50,7 +50,7 @@
unconditionally reclaim iTD/isTD scheduled
in just elapsed EHCI_ISO_RCLM_RANGE ms. */
#define MAX_DESC_BUFF_SIZE 1024 /* To hold the configuration descriptor, USB
#define MAX_DESC_BUFF_SIZE 4096 /* To hold the configuration descriptor, USB
core will allocate a buffer with this size
for each connected device. USB core does
not release it until device disconnected. */
bsp/nuvoton/libraries/nuc980/UsbHostLib/src/ehci.c
+4 -3
View File
@@ -297,6 +297,8 @@ static int ehci_init(void)
_ehci->UCFGR = 0x1; /* enable port routing to EHCI */
_ehci->UIENR = HSUSBH_UIENR_USBIEN_Msk | HSUSBH_UIENR_UERRIEN_Msk | HSUSBH_UIENR_HSERREN_Msk | HSUSBH_UIENR_IAAEN_Msk;
_ehci->UASSTR = 0xfff;
usbh_delay_ms(1); /* delay 1 ms */
_ehci->UPSCR[0] = HSUSBH_UPSCR_PP_Msk; /* enable port 1 port power */
@@ -905,7 +907,7 @@ static int visit_qtd(qTD_T *qtd)
return 0;
}
static void scan_asynchronous_list()
void scan_asynchronous_list()
{
QH_T *qh, *qh_tmp;
qTD_T *q_pre, *qtd, *qtd_tmp;
@@ -1094,9 +1096,8 @@ void iaad_remove_qh()
//void EHCI_IRQHandler(void)
void nu_ehci_isr(int vector, void *param)
{
uint32_t intsts;
volatile uint32_t intsts = _ehci->USTSR;
intsts = _ehci->USTSR;
_ehci->USTSR = intsts; /* clear interrupt status */
//USB_debug("ehci int_sts = 0x%x\n", intsts);
bsp/nuvoton/libraries/nuc980/UsbHostLib/src/support.c
+52 -102
View File
File diff suppressed because it is too large. Load diff
bsp/nuvoton/libraries/nuc980/rtt_port/drv_emac.c
+107 -44
View File
File diff suppressed because it is too large. Load diff
bsp/nuvoton/libraries/nuc980/rtt_port/drv_i2c.c
+22 -7
View File
@@ -100,20 +100,32 @@ static nu_i2c_bus_t nu_i2c_arr [ ] =
static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg msgs[],
rt_uint32_t num);
static rt_err_t nu_i2c_bus_control(struct rt_i2c_bus_device *bus,
rt_uint32_t u32Cmd,
rt_uint32_t u32Value);
static const struct rt_i2c_bus_device_ops nu_i2c_ops =
{
.master_xfer = nu_i2c_mst_xfer,
.slave_xfer = NULL,
.i2c_bus_control = NULL,
.i2c_bus_control = nu_i2c_bus_control
};
static rt_err_t nu_i2c_configure(nu_i2c_bus_t *bus)
static rt_err_t nu_i2c_bus_control(struct rt_i2c_bus_device *bus, rt_uint32_t u32Cmd, rt_uint32_t u32Value)
{
RT_ASSERT(bus != RT_NULL);
nu_i2c_bus_t *nu_i2c;
bus->parent.ops = &nu_i2c_ops;
I2C_Open(bus->I2C, 100000);
RT_ASSERT(bus != RT_NULL);
nu_i2c = (nu_i2c_bus_t *) bus;
switch (RT_I2C_DEV_CTRL_CLK)
{
case RT_I2C_DEV_CTRL_CLK:
I2C_SetBusClockFreq(nu_i2c->I2C, u32Value);
break;
default:
return -RT_EIO;
}
return RT_EOK;
}
@@ -376,11 +388,14 @@ int rt_hw_i2c_init(void)
for (i = (I2C_START + 1); i < I2C_CNT; i++)
{
nu_sys_ipclk_enable(nu_i2c_arr[i].clkidx);
nu_sys_ip_reset(nu_i2c_arr[i].rstidx);
nu_i2c_configure(&nu_i2c_arr[i]);
/* Reset and initial IP engine. */
I2C_Close(nu_i2c_arr[i].I2C);
I2C_Open(nu_i2c_arr[i].I2C, 100000);
nu_i2c_arr[i].parent.ops = &nu_i2c_ops;
ret = rt_i2c_bus_device_register(&nu_i2c_arr[i].parent, nu_i2c_arr[i].device_name);
RT_ASSERT(RT_EOK == ret);
}
bsp/nuvoton/libraries/nuc980/rtt_port/drv_i2s.c
+5 -5
View File
@@ -244,6 +244,11 @@ static rt_err_t nu_i2s_dai_setup(nu_i2s_t psNuI2s, struct rt_audio_configure *pc
i2sIoctl(I2S_SET_I2S_FORMAT, I2S_FORMAT_I2S, 0);
if (psNuI2s->AcodecOps->role == NU_ACODEC_ROLE_MASTER)
{
// Set as slave, source clock is XIN (12MHz)
i2sIoctl(I2S_SET_MODE, I2S_MODE_SLAVE, 0);
}
else
{
if (pconfig->samplerate % 11025)
{
@@ -284,11 +289,6 @@ static rt_err_t nu_i2s_dai_setup(nu_i2s_t psNuI2s, struct rt_audio_configure *pc
// Set as master
i2sIoctl(I2S_SET_MODE, I2S_MODE_MASTER, 0);
}
else
{
// Set as slave, source clock is XIN (12MHz)
i2sIoctl(I2S_SET_MODE, I2S_MODE_SLAVE, 0);
}
LOG_I("Open I2S.");
bsp/nuvoton/libraries/nuc980/rtt_port/drv_sys.c
-1
View File
@@ -302,7 +302,6 @@ E_SYS_USB0_ID nu_sys_usb0_role(void)
#ifdef RT_USING_FINSH
#include <finsh.h>
FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system);
#ifdef FINSH_USING_MSH
int cmd_reset(int argc, char **argv)
bsp/nuvoton/libraries/nuc980/rtt_port/drv_usbhost.c
+93 -30
View File
File diff suppressed because it is too large. Load diff
bsp/nuvoton/nk-980iot/.config
+65 -59
View File
File diff suppressed because it is too large. Load diff
bsp/nuvoton/nk-980iot/board/nu_pin_init.c
+2
View File
@@ -17,8 +17,10 @@ static void nu_pin_uart_init(void)
/* UART0: GPF11, GPF12 */
outpw(REG_SYS_GPF_MFPH, (inpw(REG_SYS_GPF_MFPH) & 0xfff00fff) | 0x11000);
#if !defined(BOARD_USING_LCD_ILI9341)
/* UART1: GPF9, GPF10 */
outpw(REG_SYS_GPF_MFPH, (inpw(REG_SYS_GPF_MFPH) & 0xfffff00f) | 0x00220);
#endif
}
static void nu_pin_emac_init(void)
bsp/nuvoton/nk-n9h30/.config
+29 -51
View File
@@ -7,6 +7,7 @@
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_BIG_ENDIAN is not set
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
@@ -27,6 +28,7 @@ CONFIG_IDLE_THREAD_STACK_SIZE=2048
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_ASM_MEMCPY is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
@@ -72,7 +74,8 @@ CONFIG_RT_USING_INTERRUPT_INFO=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=256
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x40003
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_VER_NUM=0x40004
CONFIG_ARCH_ARM=y
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_ARM_ARM9=y
@@ -95,19 +98,19 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_RT_USING_MSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
# CONFIG_FINSH_USING_MSH_ONLY is not set
CONFIG_FINSH_ARG_MAX=10
#
@@ -141,6 +144,7 @@ CONFIG_RT_DFS_ELM_DRIVES=8
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
@@ -155,6 +159,8 @@ CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=2048
CONFIG_RT_USING_CAN=y
@@ -205,6 +211,7 @@ CONFIG_RT_INPUT_CAPTURE_RB_SIZE=100
#
# Using USB
#
CONFIG_RT_USING_USB=y
CONFIG_RT_USING_USB_HOST=y
CONFIG_RT_USBH_MSTORAGE=y
CONFIG_UDISK_MOUNTPOINT="/mnt/udisk"
@@ -234,14 +241,16 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1"
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
CONFIG_RT_LIBC_USING_TIME=y
# CONFIG_RT_LIBC_USING_FILEIO is not set
# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_RT_USING_PTHREADS is not set
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_POSIX_GETLINE is not set
# CONFIG_RT_USING_POSIX_AIO is not set
# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_FIXED_TIMEZONE=8
#
# Network
@@ -278,6 +287,7 @@ CONFIG_NETDEV_IPV6=0
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP141 is not set
CONFIG_RT_USING_LWIP202=y
# CONFIG_RT_USING_LWIP203 is not set
# CONFIG_RT_USING_LWIP212 is not set
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=4
@@ -349,8 +359,15 @@ CONFIG_RT_LWIP_USING_PING=y
CONFIG_RT_USING_UTEST=y
CONFIG_UTEST_THR_STACK_SIZE=4096
CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_LWP is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# RT-Thread online packages
#
@@ -507,27 +524,6 @@ CONFIG_PKG_NUEMWIN_VER_NUM=0x99999
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
CONFIG_PKG_USING_MEM_SANDBOX=y
CONFIG_PKG_MEM_SANDBOX_PATH="/packages/tools/mem_sandbox"
CONFIG_PKG_USING_MEM_SANDBOX_LATEST_VERSION=y
CONFIG_PKG_MEM_SANDBOX_VER="latest"
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
#
# system packages
@@ -733,27 +729,8 @@ CONFIG_PKG_OPTPARSE_VER="latest"
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
CONFIG_PKG_USING_VI=y
CONFIG_PKG_VI_PATH="/packages/misc/vi"
CONFIG_VI_SANDBOX_SIZE_KB=20
CONFIG_VI_MAX_LEN=4096
# CONFIG_VI_ENABLE_8BIT is not set
CONFIG_VI_ENABLE_COLON=y
CONFIG_VI_ENABLE_COLON_EXPAND=y
CONFIG_VI_ENABLE_YANKMARK=y
CONFIG_VI_ENABLE_SEARCH=y
CONFIG_VI_ENABLE_DOT_CMD=y
CONFIG_VI_ENABLE_READONLY=y
CONFIG_VI_ENABLE_SETOPTS=y
CONFIG_VI_ENABLE_SET=y
# CONFIG_VI_ENABLE_WIN_RESIZE is not set
CONFIG_VI_ENABLE_VI_ASK_TERMINAL=y
CONFIG_VI_ENABLE_UNDO=y
CONFIG_VI_ENABLE_UNDO_QUEUE=y
CONFIG_VI_UNDO_QUEUE_MAX=256
CONFIG_VI_ENABLE_VERBOSE_STATUS=y
CONFIG_PKG_USING_VI_LATEST_VERSION=y
CONFIG_PKG_VI_VER="latest"
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_VI_LATEST_VERSION is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
@@ -783,6 +760,7 @@ CONFIG_NU_PKG_USING_UTILS=y
# CONFIG_NU_PKG_USING_MAX31875 is not set
# CONFIG_NU_PKG_USING_NAU88L25 is not set
CONFIG_NU_PKG_USING_NAU8822=y
# CONFIG_NU_PKG_USING_DA9062 is not set
# CONFIG_NU_PKG_USING_ILI9341 is not set
# CONFIG_NU_PKG_USING_SPINAND is not set
bsp/nuvoton/nk-n9h30/board/Kconfig
+2 -2
View File
@@ -28,9 +28,9 @@ menu "Hardware Drivers Config"
default n
config BOARD_USING_STORAGE_SDCARD
bool "SDCARD supporting(over sdh1)"
bool "SDCARD supporting(over sdh_p0)"
select BSP_USING_SDH
select BSP_USING_SDH1
select BSP_USING_SDH0
default y
config BOARD_USING_STORAGE_SPIFLASH
bsp/nuvoton/nk-rtu980/.config
+95 -64
View File
File diff suppressed because it is too large. Load diff
components/net/at/at_socket/at_socket.c
+1 -1
View File
@@ -1107,7 +1107,7 @@ static uint32_t ipstr_to_u32(char *ipstr)
struct hostent *at_gethostbyname(const char *name)
{
struct at_device *device = RT_NULL;
ip_addr_t addr;
ip_addr_t addr = {0};
char ipstr[16] = { 0 };
/* buffer variables for at_gethostbyname() */
static struct hostent s_hostent;