Prep for 0.4.7 release

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1837 42af7a65-404d-4744-a932-0658087f49c3

ChangeLog

@@ -697,5 +697,60 @@
 	* include/css: Added std header files
 	* libxx: New C++-only directory provides support for minimal C++ applications
 
-0.4.6 2009-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
+0.4.6 2009-05-19 Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Change SPI interface so that is can accomodate interfaces where the
+	  number of bits per word is greater an 8 (such as with many 9-bit display
+	  interfaces). -- this might have broken a few things which will need to
+	  be retested!
+	* arch/arm/src/imx: Added i.MX SPI driver
+	* SPI: Add a method to set the number of bits per word.  Also add an
+	  alternative interface for so that (eventually) I can phase the sndblock
+	  and recvblock methods and replace them with a single exchange method
+	* Build:  objcopy fails with toolchains that use newer GCC and binutils.  The
+	  following arguments need to be included in the objcopy command line "-R .note
+	  -R .note.gnu.build-id -R .comment"  This has bin fixed in arch/arm/src/Makefile,
+	  but other architectures may have the same problem.  Thanks to Dave Marples
+	  for verifying this.
+	* configs/eagle100/ostest: Added support for the MicroMint Eagle100 board. 
+	  This board has a Luminary LM3S6918 Cortex-M3. Added a configuration to build
+	  examples/ostest.
+	* arch/arm/src/lpc214x: Add configuration option to enable fast GPIO (vs.
+	  legacy, "slow" GPIO) for LPC214x.
+	* arch/arm: Restructured the arch/arm directory structure to better suppor ARM
+	  and Cortex-M3.
+	* sched/: pthread_create() must return a (non-negated) errno value on failure.
+	* configs/eagle100/nsh: Add a NuttShell (NSH) configuration for the Eagle-100
+
+0.4.7 2009-05-29 Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* arch/arm/src/lm3s: Added an Ethernet driver for the LM3S6918
+	* configs/eagle100/nettest: Added an examples/nettest configuration for the
+	  Micromint Eagle100 board.
+	* Documentation/NuttxPortingGuide.html: Added a section on NuttX device drivers.
+	* configs/eagle100/httpd: Added an examples/uip configuration for the
+	  Micromint Eagle100 board.
+	* arch/arm/src/lm3s: Added an SSI driver for the LM3S6918
+	* examples/nsh: Added MMC/SD support for the LM3S6918
+	* arch/arm/src/lm3s: Fix logic for setting and clearing output GPIOs (critical
+	  fix!).
+	* drivers/mmcsd: Found numerous errors in current MMC/SD SPI driver.  Bad frequency
+	  calculation based on CSD settings, inappropriate timeouts, odd code that looks like
+	  a bad search and replace.  Also needs support for SDHC ver 2.x.  New MMC/SD is
+	  largely redesigned and probably non-functional in the first check-in.
+	* drivers/mmcsd: Changes verified on 4Gb Kingston microSHDC card and on a 2Gb
+	  SanDisk microSDC card on the Eagle100 platform.
+	* fs/fat: With the 4Gb card, the first tests of FAT32 were (finally) performed.
+	  Found and corrected a problem that prevented use of FAT32: It was not updating
+	  the sector cache before checking the FAT32 FSINFO sector.
+	* configs/eagle100/*/Make.defs:  Added configuration options that should make
+	  it possible to build NuttX for the Eagle100 using CodeSourcery 2009q1 toolchain
+	  and the devkitARM GNU toolchain.
+	* configs/mcu123-lpc214x/src: Corrected some logic in the LPC2148 SPI receive block
+	  logic.  Re-verified SDC ver1.x support with 1Gb Toshiba SDC, 1Gb PNY SDC, and
+	  4Gb Kingston SDHC.  There are CMD0 issues with the 2Gb SanDisk SDC on this board.
+	* fs/fs_mount.c: Corrected error handling that could cause a deadlock on certain
+	  mount() failures.
+
+0.4.8 2009-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
 

Documentation/NuttX.html

@@ -8,7 +8,7 @@
   <tr align="center" bgcolor="#e4e4e4">
     <td>
       <h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
-      <p>Last Updated: April 19, 2009</p>
+      <p>Last Updated: May 29, 2009</p>
     </td>
   </tr>
 </table>
@@ -217,6 +217,22 @@
       Non-restrictive BSD license.
     </p>
 </tr>
+<tr>
+  <td valign="top" width="22"><img height="20" width="20" src="favicon.ico"></td>
+  <td bgcolor="#5eaee1">
+    <b>GNU Toolchains</b>
+  </td>
+</tr>
+<tr>
+  <td><br></td>
+  <td>
+    <p>
+      Compatible GNU toolchains based on <a href="http://buildroot.uclibc.org/">buildroot</a>
+      available for
+      <a href="https://sourceforge.net/project/showfiles.php?group_id=189573&package_id=224585">download</a>
+      to provide a complete development environment for many architectures.
+    </p>
+</tr>
 </table></center>
 
 <p>
@@ -385,7 +401,7 @@
   <td><br></td>
   <td>
     <p>
-      <li>Generic driver for SPI-based MMC/SD cards.</li>
+      <li>Generic driver for SPI-based MMC/SD/SDH cards.</li>
     </p>
 </tr>
 <tr>
@@ -671,8 +687,8 @@
   </tr>
 </table>
 
-<p><b>nuttx-0.4.5</b>.
-  The 37<sup>th</sup> release of NuttX (nuttx-0.4.5) is available for download
+<p><b>nuttx-0.4.7</b>.
+  The 39<sup>th</sup> release of NuttX (nuttx-0.4.7) was made on May 29, 2009 and is available for download
   from the <a href="http://sourceforge.net/project/showfiles.php?group_id=189573">SourceForge</a>
   website.
   The change log associated with the release is available <a href="#currentrelease">here</a>.
@@ -680,26 +696,22 @@
   These unreleased changes are listed <a href="#pendingchanges">here</a>.
 </p>
 <p>
-  This release focuses on a few new features.
+  This release focuses on cleaning up and extending the Eagle100/LM3S6918 port released
+  in nuttx-0.4.6 and on improved MMC/SD support.  New features include:
   <ul>
     <li>
-      The basic port for the FreeScale ARM920T i.MX1 processor on the
-      Freescale MX1ADS board.  Coding is complete for this port, but it is
-      has not yet fully integrated.
+      Improved reliably and additional drivers for the Eagle-100 board (LM3S6918
+      ARM Cortex-M3).  Additional drivers include Ethernet, SSI, and support for
+      the on-board LEDs and microSD cards.
     </li>
     <li>
-      Extended I2C and SPI interface definitions
-    </li>
-    <li>
-      Add basic support for C++ applications.  Very simple C++ applications
-      can now be built against NuttX without any external libraries.  At
-      present, only the most primitive C++ programs are supported, but it
-      is hoped that this support will be extended in future releases.
+      The SPI-based MMC/SD driver was extended to support SDHC Version 2.xx cards.
     </li>
   </ul>
 </p>
 <p>
-  See the Changelog for a detailed description of these changes.
+  In addition, this release includes several important bugfixes for the LM3S6918, the LPC2148,
+  the SPI-based MMC/SD driver, and to FAT32.  See the ChangeLog for details of these bugfixes.
 </p>
 
 <table width ="100%">
@@ -810,8 +822,9 @@
     </p>
     <p>
       <b>STATUS:</b>
-        This port is in progress.  Coding is complete on the basic port (timer, serial console).
-        Verified support for the i.MX1 will be announced in a future release of NuttX.
+        This port is in progress.  Coding is complete on the basic port (timer, serial console, SPI).
+        Verified support for the i.MX1 will be announced in a future release of NuttX (work has
+        been temporarily stopped to support the Luminary LM3S6918).
     </p>
    </td>
 </tr>
@@ -835,10 +848,34 @@
       <b>STATUS:</b>
         The basic port (timer interrupts, serial ports, network, framebuffer, etc.) is complete.
         All implemented features have been verified with the exception of the USB device-side
-        driver; that implementation is complete but completely untested.
+        driver; that implementation is complete but untested.
     </p>
    </td>
 </tr>
+<tr>
+  <td valign="top"><img height="20" width="20" src="favicon.ico"></td>
+  <td bgcolor="#5eaee1">
+    <b>ARM Cortex-M3</b>.
+  </td>
+</tr>
+<tr>
+  <td><br></td>
+  <td>
+    <p>
+      <b>Luminary LM3S6918</b>.
+      This port uses the <a href=" http://www.micromint.com/">Micromint</a> Eagle-100 development
+      board with a GNU arm-elf toolchain* under either Linux or Cygwin.
+    </p>
+    <p>
+      <b>STATUS:</b>
+        The initial, release of this port was included in NuttX  version 0.4.6.
+        The current port includes timer, serial console, Ethernet, SSI, and microSD support.
+        There are working configurations the NuttX OS test, to run the <a href="NuttShell.html">NuttShell
+        (NSH)</a>, the NuttX networking test, and the uIP web server.
+    </p>
+   </td>
+</tr>
+
 <tr>
   <td valign="top"><img height="20" width="20" src="favicon.ico"></td>
   <td bgcolor="#5eaee1">
@@ -1322,21 +1359,35 @@ Other memory:
 </table>
 
 <pre><ul>
-nuttx-0.4.5 2009-04-19 Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
+nuttx-0.4.7 2009-05-29 Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
 
-	* Add an enumeration argument to the SPI chip select and status methods so
-	  that the interface can handle more than one device.
-	* eZ80Acclaim!: Add a generic SPI driver for all eZ80 boards.
-	* Add a setmode() method to the SPI interface to handle parts with differing
-	  mode requirements.
-	* include/nuttx/i2c.h: Defined a standard I2C interface
-	* eZ80Acclaim!: Add an I2C driver.
-	* eZ8Encore!: Add an I2C driver.
-	* Add support for the Freescale i.MX1/L architecture and a configuration for
-	  the Freescale MX1ADS development board.
-	* examples/helloxx: Added a simple C++ hello world example
-	* include/css: Added std header files
-	* libxx: New C++-only directory provides support for minimal C++ applications
+	* arch/arm/src/lm3s: Added an Ethernet driver for the LM3S6918
+	* configs/eagle100/nettest: Added an examples/nettest configuration for the
+	  Micromint Eagle100 board.
+	* Documentation/NuttxPortingGuide.html: Added a section on NuttX device drivers.
+	* configs/eagle100/httpd: Added an examples/uip configuration for the
+	  Micromint Eagle100 board.
+	* arch/arm/src/lm3s: Added an SSI driver for the LM3S6918
+	* examples/nsh: Added MMC/SD support for the LM3S6918
+	* arch/arm/src/lm3s: Fix logic for setting and clearing output GPIOs (critical
+	  fix!).
+	* drivers/mmcsd: Found numerous errors in current MMC/SD SPI driver.  Bad frequency
+	  calculation based on CSD settings, inappropriate timeouts, odd code that looks like
+	  a bad search and replace.  Also needs support for SDHC ver 2.x.  New MMC/SD is
+	  largely redesigned and probably non-functional in the first check-in.
+	* drivers/mmcsd: Changes verified on 4Gb Kingston microSHDC card and on a 2Gb
+	  SanDisk microSDC card on the Eagle100 platform.
+	* fs/fat: With the 4Gb card, the first tests of FAT32 were (finally) performed.
+	  Found and corrected a problem that prevented use of FAT32: It was not updating
+	  the sector cache before checking the FAT32 FSINFO sector.
+	* configs/eagle100/*/Make.defs:  Added configuration options that should make
+	  it possible to build NuttX for the Eagle100 using CodeSourcery 2009q1 toolchain
+	  and the devkitARM GNU toolchain.
+	* configs/mcu123-lpc214x/src: Corrected some logic in the LPC2148 SPI receive block
+	  logic.  Re-verified SDC ver1.x support with 1Gb Toshiba SDC, 1Gb PNY SDC, and
+	  4Gb Kingston SDHC.  There are CMD0 issues with the 2Gb SanDisk SDC on this board.
+	* fs/fs_mount.c: Corrected error handling that could cause a deadlock on certain
+	  mount() failures.
 
 pascal-0.1.2 2008-02-10 Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
 
@@ -1348,14 +1399,14 @@ pascal-0.1.2 2008-02-10 Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
 	  and eliminate a compiler bug
 	* Changes so that runtime compiles with SDCC.
 
-buildroot-0.1.3 2009-02-28 &lt;spudmonkey@racsa.co.cr&gt;
+buildroot-0.1.5 2009-04-25 &lt;spudmonkey@racsa.co.cr&gt;
 
-	* Add support for H8/300 toolchain
-	* Add support for GCC 4.2.4 and binutils 2.19
-	* Various fixes for newer Linux environments
-	* New ARM configuration using  GCC 4.2.4 and binutils 2.19
-	  (Note: this doesn't work with NuttX yet... to nuttx TODO.txt list).
-	* Add Renesas R8C/M16C/M32C configuration using GCC 4.2.4 and binutils 2.19
+	* Replaced config/arm-defconfig-4.2.4 with config/arm920t-defconfig-4.2.4
+	  and config/arm926t-defconfig-4.2.4 because of differences in the
+	  way that soft floating point is handled between these two
+	  architectures.
+	* Add support for gcc-4.3.3 and the ARM Cortex-M3 processor (thumb2)
+	* Add support for binutils 2.19.1
 </pre></ul>
 
 <table width ="100%">
@@ -1367,19 +1418,18 @@ buildroot-0.1.3 2009-02-28 &lt;spudmonkey@racsa.co.cr&gt;
 </table>
 
 <pre><ul>
-nuttx-0.4.6 2009-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
+nuttx-0.4.8 2009-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
 
 pascal-0.1.3 2009-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
 
-buildroot-0.1.4 2009-xx-xx &lt;spudmonkey@racsa.co.cr&gt;
-
-	* Add support for a blackfin toolchain using GCC 4.2.4 and binutils 2.19
-	* GCC 4.2.4 no longer attempts to build libstdc++.  Now we can build g++!
-	* The ARM GCC-4.2.4 configuration was changed so that it now builds g++.
-	* Removed building of initial and final GCC.  that is not necessary because
-	  we do not build a libc.  Now it builds almost twice as fast.
-	* Removed logic to build the target GCC.  That is never used.
+buildroot-0.1.6 2009-xx-xx &lt;spudmonkey@racsa.co.cr&gt;
 
+	* Added config/arm7tdmi-defconfig-4.2.4
+	* Added config/arm920t-defconfig-4.3.3
+	* Correct error in arm-defconfig gcc-3.4.6 build. The gcc-3.4.6 configuration
+	  does not not take --with-abi
+	* Correct error in gcc-3.4.6/gcc/collect.c.  Calls open with O_CREAT but
+	  does not specify mode.  Newer host compilers can error out on this.
 </pre></ul>
 
 <table width ="100%">
@@ -1440,9 +1490,10 @@ buildroot-0.1.4 2009-xx-xx &lt;spudmonkey@racsa.co.cr&gt;
   </tr>
 </table>
 <ul>
-  <li>ARM, ARM7 ARM7TDMI, ARM9, ARM920T, ARM926EJS are trademarks of Advanced RISC Machines, Limited.</li>
+  <li>ARM, ARM7 ARM7TDMI, ARM9, ARM920T, ARM926EJS Cortex-M3 are trademarks of Advanced RISC Machines, Limited.</li>
   <li>Cygwin is a trademark of Red Hat, Incorporated.</li>
   <li>Linux is a registered trademark of Linus Torvalds.</li>
+  <li>Eagle-100 is a trademark of <a href=" http://www.micromint.com/">Micromint USA, LLC</a>.
   <li>LPC2148 is a trademark of NXP Semiconductors.</li>
   <li>TI is a tradename of Texas Instruments Incorporated.</li>
   <li>UNIX is a registered trademark of The Open Group.</li>

Documentation/NuttxUserGuide.html

@@ -13,7 +13,7 @@
       <h1><big><font color="#3c34ec"><i>NuttX Operating System<p>User's Manual</i></font></big></h1>
       <p><small>by</small></p>
       <p>Gregory Nutt<p>
-      <p>Last Updated: March 13, 2009</p>
+      <p>Last Updated: May 22, 2009</p>
     </td>
   </tr>
 </table>
@@ -184,7 +184,7 @@ paragraphs.
   were started from the same parent thread.
 </p>
 <p>
-  The following task control interfaces are provided by Nuttx:
+  The following task control interfaces are provided by NuttX:
 </p>
 <ul>
   <li><a href="#taskcreate">2.1.1 task_create</a></li>
@@ -231,7 +231,7 @@ paragraphs.
    The newly created task does not inherit scheduler characteristics
    from the parent task:  The new task is started at the
    default system priority and with the SCHED_FIFO scheduling
-   policy.  These characteristcs may be modified after the new
+   policy.  These characteristics may be modified after the new
    task has been started.
 </p>
 <p>
@@ -281,7 +281,7 @@ VxWorks provides the following similar interface:
 <ul>
 <li>Interface name
 <li>Various differences in types of arguments
-<li>There is no options arguement.
+<li>There is no options argument.
 <li>A variable number of parameters can be passed to a task (VxWorks supports ten).
 </ul>
 
@@ -472,7 +472,7 @@ VxWorks provides the following similar interface:
 <p>
 <b>Description:</b> This function causes the calling task to cease
 to exist -- its stack and TCB will be deallocated.  exit differs from
-_exit in that it flushs streams, closes file descriptors and will
+_exit in that it flushes streams, closes file descriptors and will
 execute any function registered with atexit().
 <p>
 <b>Input Parameters:</b> 
@@ -491,7 +491,7 @@ execute any function registered with atexit().
 <pre>
     void exit( int code );
 </pre>
-And the unix interface:
+And the UNIX interface:
 <pre>
     void _exit( int code );
 </pre>
@@ -1065,7 +1065,7 @@ on this thread of execution.
 </table>
 
 <p>
-  NuttX supports POSIX named message queues for intertask communication.
+  NuttX supports POSIX named message queues for inter-task communication.
   Any task may send or receive messages on named message queues.
   Interrupt handlers may send messages via named message queues.
 </p>
@@ -1699,7 +1699,7 @@ interface of the same name.
   Proper use of semaphores avoids the issues of <code>sched_lock()</code>.
   However, consider the following example:
   <OL>
-    <li>Some low-priority task, <I>Task C</I>, acquires a semphore in order to
+    <li>Some low-priority task, <I>Task C</I>, acquires a semaphore in order to
       get exclusive access to a protected resource.</li>
     <li><I>Task C</I> is suspended to allow some high-priority task,</li>
       <I>Task A</I>, to execute.</li>
@@ -1727,7 +1727,7 @@ interface of the same name.
   The designer may, as examples:
 </p>
 <ul>
-  <li>Implement all tasks that need the semphore-managed resources at the
+  <li>Implement all tasks that need the semaphore-managed resources at the
     same priority level,</li>
   <li>Boost the priority of the low-priority task before the semaphore is
     acquired, or</li>
@@ -1760,7 +1760,7 @@ interface of the same name.
       The setting <code>CONFIG_SEM_PREALLOCHOLDERS</code> defines the maximum
       number of different threads (minus one per semaphore instance) that can
       take counts on a semaphore with priority inheritance support.
-      This setting defines the size of a single pool of preallocated structures.
+      This setting defines the size of a single pool of pre-allocated structures.
       It may be set to zero if priority inheritance is disabled OR if you
       are only using semaphores as mutexes (only one holder) OR if no more
       than two threads participate using a counting semaphore.
@@ -1797,7 +1797,7 @@ interface of the same name.
     These various structures tie the semaphore implementation more tightly to
     the behavior of the implementation.  For examples, if a thread executes while
     holding counts on a semaphore, or if a thread exits without call <code>sem_destroy()</code>
-    then.  Or what if the thread with the boosted priority reprioritizes itself?
+    then.  Or what if the thread with the boosted priority re-prioritizes itself?
     The NuttX implement of priority inheritance attempts to handle all of these
     types of corner cases, but it is very likely that some are missed.
     The worst case result is that memory could by stranded within the priority
@@ -2022,7 +2022,7 @@ interface of the same name.
 <p>
 <b>Description:</b> This function will remove the semaphore named by the
 input name parameter.  If one or more tasks have the semaphore named by
-name oepn when sem_unlink() is called, destruction of the semaphore will
+name open when sem_unlink() is called, destruction of the semaphore will
 be postponed until all references have been destroyed by calls to
 sem_close().
 <p>
@@ -2326,7 +2326,7 @@ VxWorks provides the following comparable interface:
 Differences from the VxWorks interface include:
 <ul>
 <li>Does not make any checks to see if the watchdog is being used
-before de-allocating it (i.e., never returns ERROR).
+before deallocating it (i.e., never returns ERROR).
 </ul>
 
 <H3><a name="wdstart">2.6.3 wd_start</a></H3>
@@ -2779,7 +2779,7 @@ VxWorks provides the following comparable interface:
 </p>
 <ul>
  <li><code>timerid</code>. The pre-thread timer, previously created by the call to timer_create(), to be be set.</li>
- <li><code>flags</code>. Specifie characteristics of the timer (see above)</li>
+ <li><code>flags</code>. Specify characteristics of the timer (see above)</li>
  <li><code>value</code>. Specifies the timer value to set</li>
  <li><code>ovalue</code>. A location in which to return the time remaining from the previous timer setting (ignored).</li>
 </ul>
@@ -3145,7 +3145,7 @@ action to be associated with the specified signal.  If the argument oact
 is not NULL, the action previously associated with the signal is stored
 in the location pointed to by the argument oact.  If the argument act is
 NULL, signal handling is unchanged by this function call; thus, the call
-can be used to enquire about the current handling of a given signal.
+can be used to inquire about the current handling of a given signal.
 <p>
 When a signal is caught by a signal-catching function installed by the
 sigaction() function, a new signal mask is calculated and installed for
@@ -3384,7 +3384,7 @@ for si_code are defined in signal.h:
   <li><I>SI_USER</I>. Signal sent from kill, raise, or abort
   <li><I>SI_QUEUE</I>. Signal sent from sigqueue
   <li><I>SI_TIMER</I>. Signal is result of timer expiration
-  <li><I>SI_ASYNCIO</I>. Signal is the result of asynch IO completion 
+  <li><I>SI_ASYNCIO</I>. Signal is the result of asynchronous IO completion 
   <li><I>SI_MESGQ</I>. Signal generated by arrival of a message on an empty message queue.
 </ul>
 
@@ -4121,7 +4121,7 @@ Identifies the thread to be canceled.</li>
 <p>
 <b>Returned Values:</b>
 <p>
-If successful, the <I>ptnread_cancel()</I> function will return zero (<I>OK</I>).
+If successful, the <I>pthread_cancel()</I> function will return zero (<I>OK</I>).
 Otherwise, an error number will be returned to indicate the error:
 <p>
 <ul>
@@ -4136,8 +4136,8 @@ interface of the same name.  Except:</p>
 <li>The thread-specific data destructor functions shall be called for thread.
 However, these destructors are not currently supported.</li>
 <li>Cancellation types are not supported.  The thread will be canceled
-at the time that pthread_cancel() is called or, if cancelation is disabled, at
-the time when cancelation is re-enabled.</li>
+at the time that pthread_cancel() is called or, if cancellation is disabled, at
+the time when cancellation is re-enabled.</li>
 <li><tt>pthread_testcancel()</tt> is not supported.</li>
 <li>Thread cancellation at <i>cancellation points</i> is not supported.</li>
 </ul>
@@ -4158,16 +4158,16 @@ state and returns the previous cancelability  state at the location
 referenced by oldstate.
 Legal values for state are PTHREAD_CANCEL_ENABLE and PTHREAD_CANCEL_DISABLE.<.li>
 
-<p>Any pending thread cancelation may occur at the time that the
-cancelation state is set to PTHREAD_CANCEL_ENABLE.</p>
+<p>Any pending thread cancellation may occur at the time that the
+cancellation state is set to PTHREAD_CANCEL_ENABLE.</p>
 
 <b>Input Parameters:</b>
 <p>
 <ul>
 <li><I>state</I> 
-New cancelation state.  One of PTHREAD_CANCEL_ENABLE or PTHREAD_CANCEL_DISABLE.<.li>
+New cancellation state.  One of PTHREAD_CANCEL_ENABLE or PTHREAD_CANCEL_DISABLE.<.li>
 <li><I>oldstate</I>.
-Location to return the previous cancelation state.
+Location to return the previous cancellation state.
 </ul>
 <p>
 <b>Returned Values:</b>
@@ -4682,7 +4682,7 @@ interface of the same name.
 
 <H3><a name="pthreadmutexattrdestroy">2.9.27 pthread_mutexattr_destroy</a></H3>
 <p>
-<b>Function Protoype:</b>
+<b>Function Prototype:</b>
 <p>
 <pre>
     #include &lt;pthread.h&gt;
@@ -4830,15 +4830,15 @@ returned to indicate the error:
   <li><code>type</code>. The mutex type value to set.  The following values are supported:
   <ul>
     <li><code>PTHREAD_MUTEX_NORMAL</code>.  This type of mutex does not detect deadlock. A thread
-      attempting to relock this mutex without first unlocking it will deadlock.
+      attempting to re-lock this mutex without first unlocking it will deadlock.
       Attempting to unlock a mutex locked by a different thread results in undefined
       behavior. Attempting to unlock an unlocked mutex results in undefined behavior. </li>
     <li><code>PTHREAD_MUTEX_ERRORCHECK</code>.  This type of mutex provides error checking.
-      A thread attempting to relock this mutex without first unlocking it will return with an error.
+      A thread attempting to re-lock this mutex without first unlocking it will return with an error.
       A thread attempting to unlock a mutex which another thread has locked will return with an error.
       A thread attempting to unlock an unlocked mutex will return with an error.</li>
-    <li><code>PTHREAD_MUTEX_RECURSIVE</code>.  A thread attempting to relock this mutex without first
-      unlocking it will succeed in locking the mutex. The relocking deadlock which can occur with mutexes
+    <li><code>PTHREAD_MUTEX_RECURSIVE</code>.  A thread attempting to re-lock this mutex without first
+      unlocking it will succeed in locking the mutex. The re-locking deadlock which can occur with mutexes
       of type PTHREAD_MUTEX_NORMAL cannot occur with this type of mutex. Multiple locks of this mutex
       require the same number of unlocks to release the mutex before another thread can acquire the mutex.
       A thread attempting to unlock a mutex which another thread has locked will return with an error.
@@ -4944,7 +4944,7 @@ interface of the same name.
 </p>
 <p>
    If the mutex type is <code>PTHREAD_MUTEX_NORMAL</code>, deadlock detection is not provided.
-   Attempting to relock the mutex causes deadlock. If a thread attempts to unlock
+   Attempting to re-lock the mutex causes deadlock. If a thread attempts to unlock
    a mutex that it has not locked or a mutex which is unlocked, undefined behavior
    results.
 </p>
@@ -4954,14 +4954,14 @@ interface of the same name.
 </p>
 <p>
    If the mutex type is <code>PTHREAD_MUTEX_ERRORCHECK</code>, then error checking is provided.
-   If a thread attempts to relock a mutex that it has already locked, an error
+   If a thread attempts to re-lock a mutex that it has already locked, an error
    will be returned. If a thread attempts to unlock a mutex that it has not
    locked or a mutex which is unlocked, an error will be returned.
 </p>
 <p>
    If the mutex type is <code>PTHREAD_MUTEX_RECURSIVE</code>, then the mutex maintains the concept
    of a lock count. When a thread successfully acquires a mutex for the first time,
-   the lock count is set to one. Every time a thread relocks this mutex, the lock count
+   the lock count is set to one. Every time a thread re-locks this mutex, the lock count
    is incremented by one. Each time the thread unlocks the mutex, the lock count is
    decremented by one. When the lock count reaches zero, the mutex becomes available
    for other threads to acquire. If a thread attempts to unlock a mutex that it has
@@ -5592,7 +5592,7 @@ interface of the same name.
 </pre>
 <p>
   <b>Description:</b>
-  The <code>pthread_barrier_wait()</code> function synchronizse participating
+  The <code>pthread_barrier_wait()</code> function synchronizes participating
   threads at the barrier referenced by <code>barrier</code>.
   The calling thread is blocked until the required number of threads have called
   <code>pthread_barrier_wait()</code> specifying the same <code>barrier</code>.
@@ -5665,7 +5665,7 @@ interface of the same name.
   <li>
     <code>once_control</code>.
     Determines if <code>init_routine()</code> should be called.
-    <code>once_control</code> should be declared and intialized as follows:
+    <code>once_control</code> should be declared and initialized as follows:
     <ul><pre>pthread_once_t once_control = PTHREAD_ONCE_INIT;
     </pre></ul>
     <code>PTHREAD_ONCE_INIT</code> is defined in <code>pthread.h</code>.
@@ -5795,7 +5795,7 @@ interface of the same name.
   <b>Returned Values:</b>
 </p>
 <p>
-  0 (OK) on succes or EINVAL if <code>how</code> is invalid.
+  0 (OK) on success or EINVAL if <code>how</code> is invalid.
 </p>
 <p>
   <b>Assumptions/Limitations:</b>
@@ -5815,7 +5815,7 @@ interface of the same name.
 <p><b>Overview</b>.
   NuttX supports environment variables that can be used to control the behavior of programs.
   In the spirit of NuttX the environment variable behavior attempts to emulate the behavior of
-  environment variables in the mulit-processing OS:
+  environment variables in the multi-processing OS:
 </p>
 <ul>
   <li><b>Task environments</b>.
@@ -5828,10 +5828,10 @@ interface of the same name.
   </li>
   <li><b>Thread environments</b>.
     When a pthread is created using <a href="#pthreadcreate">pthread_create</a>, the child
-    thread also inherits that envirnment of the parent.
-    However, the child does not recieve a copy of the environment but, rather, shares the same
+    thread also inherits that environment of the parent.
+    However, the child does not receive a copy of the environment but, rather, shares the same
     environment.
-    Changes to the environment are visiable to all threads with the same parentage.
+    Changes to the environment are visible to all threads with the same parentage.
   </li>
 </ul>
 <p><b>Programming Interfaces</b>.
@@ -5875,7 +5875,7 @@ interface of the same name.
 </ul>
 <p>
   <b>Returned Values:</b>
-   The value of the valiable (read-only) or NULL on failure.
+   The value of the variable (read-only) or NULL on failure.
 </p>
 
 <h3><a name="putenv">2.10.2 <code>putenv</code></a></h3>
@@ -5906,7 +5906,7 @@ interface of the same name.
 </ul>
 <p>
   <b>Returned Values:</b>
-  Zero on sucess.
+  Zero on success.
 </p>
 
 <h3><a name="clearenv">2.10.3 <code>clearenv</code></a></h3>
@@ -6018,27 +6018,30 @@ interface of the same name.
 
 <p><b>Overview</b>.
   NuttX includes an optional, scalable file system.
-  This file-system may be omitted altogther; NuttX does not depend on the presence
+  This file-system may be omitted altogether; NuttX does not depend on the presence
   of any file system.
 </p>
 
 <p><b>Pseudo Root File System</b>.
-  Or, a simple <i>in-memory</i>, <i>psuedo</i> file system can be enabled.
+  Or, a simple <i>in-memory</i>, <i>pseudo</i> file system can be enabled.
   This simple file system can be enabled setting the CONFIG_NFILE_DESCRIPTORS
   option to a non-zero value.
   This is an <i>in-memory</i> file system because it does not require any
   storage medium or block driver support.
   Rather, file system contents are generated on-the-fly as referenced via
   standard file system operations (open, close, read, write, etc.).
-  In this sense, the file system is <i>psuedo</i> file system (in the
+  In this sense, the file system is <i>pseudo</i> file system (in the
   same sense that the Linux <code>/proc</code> file system is also
-  referred to as a psuedo file system).
+  referred to as a pseudo file system).
 </p>
 
 <p>
-  Any user supplied data or logic can be accessed via the psuedo-file system.
-  Built in support is provided for character and block drivers in the
-  <code>/dev</code> psuedo file system directory.
+  Any user supplied data or logic can be accessed via the pseudo-file system.
+  Built in support is provided for character and block 
+  <a href="NuttxPortingGuide.html#DeviceDrivers">driver</a> <i>nodes</i> in the any
+  pseudo file system directory.
+  (By convention, however, all driver nodes should be in the <code>/dev</code>
+  pseudo file system directory).
 </p>
 
 <p><b>Mounted File Systems</b>
@@ -6046,7 +6049,7 @@ interface of the same name.
   devices that provide access to true file systems backed up via some
   mass storage device.
   NuttX supports the standard <code>mount()</code> command that allows
-  a block driver to be bound to a mountpoint within the psuedo file system
+  a block driver to be bound to a mount-point within the pseudo file system
   and to a a file system.
   At present, NuttX supports only the VFAT file system.
 </p>
@@ -6055,10 +6058,10 @@ interface of the same name.
   From a programming perspective, the NuttX file system appears very similar
   to a Linux file system.
   However, there is a fundamental difference:
-  The NuttX root file system is a psuedo file system and true file systems may be
-  mounted in the psuedo file system.
+  The NuttX root file system is a pseudo file system and true file systems may be
+  mounted in the pseudo file system.
   In the typical Linux installation by comparison, the Linux root file system
-  is a true file system and psuedo file systems may be mounted in the true,
+  is a true file system and pseudo file systems may be mounted in the true,
   root file system.
   The approach selected by NuttX is intended to support greater scalability
   from the very tiny platform to the moderate platform.
@@ -6165,7 +6168,7 @@ interface of the same name.
   <b>Returned Values:</b>
 </p>
 <p>
-  On success, the number of structures that have nonzero <cod>revents</code> fields.
+  On success, the number of structures that have nonzero <code>revents</code> fields.
   A value of 0 indicates that the call timed out and no file descriptors were ready.
   On error, -1 is returned, and <code>errno</code> is set appropriately:
 </p>
@@ -6432,7 +6435,7 @@ struct fat_format_s
           bad FAT size in <code>fmt</code>, bad cluster size in <code>fmt</code>
         </li>
         <li><code>ENOENT</code> - 
-          <code>pathname</code> does not refer to anything in the filesystem.
+          <code>pathname</code> does not refer to anything in the file-system.
         </li>
         <li><code>ENOTBLK</code> -
           <code>pathname</code> does not refer to a block driver
@@ -6454,14 +6457,14 @@ struct fat_format_s
   access media under the following very restrictive conditions:
   <ol>
     <li>
-      The filesystem supports the <code>FIOC_MMAP</code> ioctl command.
+      The file-system supports the <code>FIOC_MMAP</code> ioctl command.
       Any file system that maps files contiguously on the media should support this
       <code>ioctl</code> command.
       By comparison, most file system scatter files over the media in non-contiguous
       sectors.  As of this writing, ROMFS is the only file system that meets this requirement.
     </li>
     <li>
-      The underly block driver supports the <code>BIOC_XIPBASE</code> <code>ioctl</code> command
+      The underlying block driver supports the <code>BIOC_XIPBASE</code> <code>ioctl</code> command
       that maps the underlying media to a randomly accessible address.
        At present, only the RAM/ROM disk driver does this.
     </li>
@@ -6588,7 +6591,7 @@ FAR void *mmap(FAR void *start, size_t length, int prot, int flags, int fd, off_
           contained both of these values.
         </li>
         <li><code>ENODEV</code> -
-          The underlying filesystem of the specified file does not support memory mapping.
+          The underlying file-system of the specified file does not support memory mapping.
         </li>
       </ul>
     </p>
@@ -7172,7 +7175,7 @@ Those socket APIs are discussed in the following paragraphs.</p>
 </pre>
 <p>
   <b>Description:</b>
-  <code>getsockopt()</code> retrieve thse value for the option specified by the
+  <code>getsockopt()</code> retrieve those value for the option specified by the
   <code>option</code> argument for the socket specified by the <code>sockfd</code> argument. If
   the size of the option value is greater than <code>value_len</code>, the value
   stored in the object pointed to by the <code>value</code> argument will be silently

Makefile

@@ -1,7 +1,7 @@
 ############################################################################
 # Makefile
 #
-#   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -101,7 +101,7 @@ LINKLIBS	= sched/libsched$(LIBEXT) $(ARCH_SRC)/libarch$(LIBEXT) mm/libmm$(LIBEXT
 # Add libraries for network support.  CXX, CXXFLAGS, and COMPILEXX must
 # be defined in Make.defs for this to work!
 
-ifneq ($(CXX),)
+ifeq ($(CONFIG_HAVE_CXX),y)
 LINKLIBS	+= libxx/liblibxx$(LIBEXT)
 endif
 
@@ -144,7 +144,7 @@ endif
 BIN		= nuttx$(EXEEXT)
 
 all: $(BIN)
-.PHONY: clean context clean_context distclean
+.PHONY: context clean_context check_context subdir_clean clean subdir_distclean distclean
 
 # Build the mkconfig tool used to create include/nuttx/config.h
 tools/mkconfig:
@@ -203,10 +203,8 @@ sched/libsched$(LIBEXT): context
 lib/liblib$(LIBEXT): context
 	@$(MAKE) -C lib TOPDIR="$(TOPDIR)" liblib$(LIBEXT)
 
-ifneq ($(CXX),)
 libxx/liblibxx$(LIBEXT): context
 	@$(MAKE) -C libxx TOPDIR="$(TOPDIR)" liblibxx$(LIBEXT)
-endif
 
 $(ARCH_SRC)/libarch$(LIBEXT): context
 	@$(MAKE) -C $(ARCH_SRC) TOPDIR="$(TOPDIR)" libarch$(LIBEXT)
@@ -247,13 +245,13 @@ ifeq ($(CONFIG_RRLOAD_BINARY),y)
 	fi
 endif
 ifeq ($(CONFIG_INTELHEX_BINARY),y)
-	@$(OBJCOPY) -O ihex $(TOPDIR)/$@ $(TOPDIR)/$@.ihx
+	@$(OBJCOPY) $(OBJCOPYARGS) -O ihex $(TOPDIR)/$@ $(TOPDIR)/$@.ihx
 endif
 ifeq ($(CONFIG_MOTOROLA_SREC),y)
-	@$(OBJCOPY) -O srec $(TOPDIR)/$@ $(TOPDIR)/$@.srec
+	@$(OBJCOPY) $(OBJCOPYARGS) -O srec $(TOPDIR)/$@ $(TOPDIR)/$@.srec
 endif
 ifeq ($(CONFIG_RAW_BINARY),y)
-	@$(OBJCOPY) -O binary $(TOPDIR)/$@ $(TOPDIR)/$@.bin
+	@$(OBJCOPY) $(OBJCOPYARGS) -O binary $(TOPDIR)/$@ $(TOPDIR)/$@.bin
 endif
 
 depend:

ReleaseNotes

@@ -847,7 +847,7 @@ ZDS-II toolchain in Cygwin-based environment. Please report any errors to me.
 
 This tarball contains a complete CVS snapshot from March 29, 2009.
 
-nuttx-0.4.4
+nuttx-0.4.5
 ^^^^^^^^^^^
 
 This is the 37th release of NuttX.  This release focuses on a few new features.
@@ -863,4 +863,50 @@ This is the 37th release of NuttX.  This release focuses on a few new features.
 
 See the Changelog for a detailed description of these changes.
 
-This tarball contains a complete CVS snapshot from April 19, 2009.
+This tarball contains a complete CVS snapshot from April 19, 2009.
+
+nuttx-0.4.6
+^^^^^^^^^^^
+
+This is the 38th release of NuttX.  The release features support for the Micromint
+Eagle-100 development board.  This board is based around, the Luminary LM3S6918 MCU.
+This is the first ARM Cortex-M3 architecture supported by Nuttx. This initial, basic
+port includes timer and serial console with configurations to execute the NuttX OS
+test and to run the NuttShell (NSH). Work is still underway on this port and current
+plans are to have I2C, SSI, MMC/SD, and and Ethernet driver in the 0.4.7 release.
+
+Additional work was done on the MXADS i.MX1 port, however, that work has been set
+aside until I complete work on the Eagle-100 (I also need to come up with a 3V power
+supply).
+
+Other changes in this release include: Extensions to the SPI interface definition
+in order to handle 9-bit interfaces to displays.  Several bugs were fixed (see the
+ChangeLog for a complete list of changes).
+
+This tarball contains a complete CVS snapshot from May 19, 2009.
+
+nuttx-0.4.7
+^^^^^^^^^^^
+
+This is the 39th release of NuttX.  This release focuses on cleaning up and
+extending the Eagle100/LM3S6918 port released in nuttx-0.4.6 and on improved
+MMC/SD support.  New features include:
+
+  o Improved reliably and additional drivers for the Eagle-100 board (LM3S6918
+    ARM Cortex-M3).  Additional drivers include Ethernet, SSI, and support for
+    the on-board LEDs and microSD cards.
+  o The SPI-based MMC/SD driver was extended to support SDHC Version 2.xx cards.
+
+In addition, this release includes several important bugfixes for the LM3S6918,
+the LPC2148, the SPI-based MMC/SD driver, and to FAT32.  See the ChangeLog for
+details of these bugfixes.
+
+This tarball contains a complete CVS snapshot from May 19, 2009.
+
+
+
+
+
+
+
+

TODO

@@ -10,10 +10,10 @@ NuttX TODO List (Last updated April 12, 2009)
  (12)  Network (net/, netutils/)
   (1)  USB (drivers/usbdev)
   (4)  Libraries (lib/)
-  (6)  File system/Generic drivers (fs/, drivers/)
+  (7)  File system/Generic drivers (fs/, drivers/)
   (2)  Graphics subystem (graphics/)
   (1)  Pascal add-on (pcode/)
-  (2)  Documentation (Documentation/)
+  (0)  Documentation (Documentation/)
   (5)  Build system / Toolchains
   (2)  NuttShell (NSH) (examples/nsh)
   (3)  Other Applications & Tests (examples/)
@@ -21,9 +21,10 @@ NuttX TODO List (Last updated April 12, 2009)
   (2)  ARM (arch/arm/)
   (1)  ARM/C5471 (arch/arm/src/c5471/)
   (3)  ARM/DM320 (arch/arm/src/dm320/)
-  (1)  ARM/i.MX (arch/arm/src/imx/)
-  (6)  ARM/LPC214x (arch/arm/src/lpc214x/)
-  (3)  ARM/STR71x (arch/arm/src/str71x/)
+  (2)  ARM/i.MX (arch/arm/src/imx/)
+  (8)  ARM/LPC214x (arch/arm/src/lpc214x/)
+  (4)  ARM/STR71x (arch/arm/src/str71x/)
+  (1)  ARM/LM3S6918 (arch/arm/src/lm3s/)
   (4)  pjrc-8052 / MCS51 (arch/pjrc-8051/)
   (2)  Hitachi/Renesas SH-1 (arch/sh/src/sh1)
   (4)  Renesas M16C/26 (arch/sh/src/m16c)
@@ -288,11 +289,6 @@ o File system / Generic drivers (fs/, drivers/)
   Priority:    Low.  I have mixed feelings about if NuttX should pay a
                performance penalty for better data integrity.
 
-  Description: FAT: FAT32 is untested -- because I don't have any large
-               enough devices yet to support a FAT32 FS.
-  Status:      Open
-  Priority:    Medium
-
   Description: The simple SPI based MMCS/SD driver in fs/mmcsd does not
                yet handle multiple block transfers.
   Status:      Open
@@ -329,14 +325,6 @@ o Pascal Add-On (pcode/)
 o Documentation (Documentation/)
   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-  Description: Document driver/ logic
-  Status:      Open
-  Priority:    Low
-
-  Description: Document C-library APIs
-  Status:      Open
-  Priority:    Low
-
 o Build system
   ^^^^^^^^^^^^
 
@@ -366,13 +354,6 @@ o Build system
   Status:      Open
   Priority:    Medium-low
 
-  Descripton   I am having trouble using the newer gcc 4.2.4 + binutils 2.19
-               toolchain for ARM.  The problem is in arch/arm/src/Makefile:
-               In the call to objcopy to relocate the .data section, arm-elf-objcopy
-               dies with a 'Floating point exception'  No clue to the cause yet.
-  Status:      Open
-  Priority:    Medium-Low -- workaroung, stick with the 3.4.6 toolchain
-
 o NuttShell (NSH) (examples/nsh)
   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
@@ -483,6 +464,10 @@ o ARM/i.MX (arch/arm/src/imx/)
   Status:      Open (and in work)
   Priority:    Medium (high if you need i.MX1/L support)
 
+  Description: SPI methods are not thread safe.  Needs a semaphore to protect from re-entrancy.
+  Status:      Open
+  Priority:    Medium -- Will be very high if you do SPI access from multiple threads.
+
 o ARM/LPC214x (arch/arm/src/lpc214x/)
   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
@@ -509,9 +494,16 @@ o ARM/LPC214x (arch/arm/src/lpc214x/)
   Priority:    High
 
   Description: At present the SPI driver is polled.  Should it be interrupt driven?
+               Look at arch/arm/src/imx/imx_spi.c -- that is a good example of an
+               interrupt driven SPI driver.  Should be very easy to part that architecture
+               to the LPC.
   Status:      Open
   Priority:    Medium
 
+  Description: SPI methods are not thread safe.  Needs a semaphore to protect from re-entrancy.
+  Status:      Open
+  Priority:    Medium -- Will be very high if you do SPI access from multiple threads.
+
   Description: At present the SPI driver is polled -AND- there is a rather large, arbitrary,
                delay in one of the block access routines.  The purpose of the delay is to
                avoid a race conditions.  This begs for a re-design -OR- at a minimum, some
@@ -519,6 +511,12 @@ o ARM/LPC214x (arch/arm/src/lpc214x/)
   Status:      Open
   Priority:    Medium
 
+  Desription:  I am unable to initialize a 2Gb SanDisk microSD card (in adaptor) on the
+               the mcu123 board.  The card fails to accept CMD0.  Doesn't seem like a software
+               issue, but if anyone else sees the problem, I'd like to know.
+  Status:      Open
+  Priority:    Uncertain
+
 o ARM/STR71x (arch/arm/src/str71x/)
   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
@@ -535,6 +533,23 @@ o ARM/STR71x (arch/arm/src/str71x/)
   Status:      Open
   Priority:    Medium
 
+  Description: SPI methods are not thread safe.  Needs a semaphore to protect from re-entrancy.
+  Status:      Open
+  Priority:    Medium -- Will be very high if you do SPI access from multiple threads.
+
+o ARM/LM3S6918 (arch/arm/src/lm3s/)
+  ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+  Description: Still need to implement I2C
+  Status:      Open
+  Priority:    Low
+
+  Description: Should terminate SSI/SPI transfer if an Rx FIFO overrun occurs.
+               Right now, if an Rx FIFO overrun occurs, the SSI driver hangs.
+  Status:      Open
+  Priority:    Medium, If the transfer is properly tuned, then there should not
+               be any Rx FIFO overruns.
+
 o pjrc-8052 / MCS51 (arch/pjrc-8051/)
   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
@@ -704,6 +719,10 @@ o z80/z8/ez80 (arch/z80)
   Status:      Open
   Priority:    Med
 
+  Description: SPI methods are not thread safe.  Needs a semaphore to protect from re-entrancy.
+  Status:      Open
+  Priority:    Medium -- Will be very high if you do SPI access from multiple threads.
+
   Description: A "generic" I2C driver has been coded for the eZ8Encore!
                However, this remains untested since I have no I2C devices for
                the board (yet).

arch/arm/include/arm/irq.h

@@ -0,0 +1,229 @@
+/****************************************************************************
+ * arch/arm/include/arm/irq.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_ARM_IRQ_H
+#define __ARCH_ARM_INCLUDE_ARM_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/irq.h>
+#include <sys/types.h>
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* IRQ Stack Frame Format:
+ *
+ * Context is always saved/restored in the same way:
+ *
+ *   (1) stmia rx, {r0-r14}
+ *   (2) then the PC and CPSR
+ *
+ * This results in the following set of indices that
+ * can be used to access individual registers in the
+ * xcp.regs array:
+ */
+
+#define REG_R0              (0)
+#define REG_R1              (1)
+#define REG_R2              (2)
+#define REG_R3              (3)
+#define REG_R4              (4)
+#define REG_R5              (5)
+#define REG_R6              (6)
+#define REG_R7              (7)
+#define REG_R8              (8)
+#define REG_R9              (9)
+#define REG_R10             (10)
+#define REG_R11             (11)
+#define REG_R12             (12)
+#define REG_R13             (13)
+#define REG_R14             (14)
+#define REG_R15             (15)
+#define REG_CPSR            (16)
+
+#define XCPTCONTEXT_REGS    (17)
+#define XCPTCONTEXT_SIZE    (4 * XCPTCONTEXT_REGS)
+
+#define REG_A1              REG_R0
+#define REG_A2              REG_R1
+#define REG_A3              REG_R2
+#define REG_A4              REG_R3
+#define REG_V1              REG_R4
+#define REG_V2              REG_R5
+#define REG_V3              REG_R6
+#define REG_V4              REG_R7
+#define REG_V5              REG_R8
+#define REG_V6              REG_R9
+#define REG_V7              REG_R10
+#define REG_SB              REG_R9
+#define REG_SL              REG_R10
+#define REG_FP              REG_R11
+#define REG_IP              REG_R12
+#define REG_SP              REG_R13
+#define REG_LR              REG_R14
+#define REG_PC              REG_R15
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* This struct defines the way the registers are stored.  We
+ * need to save:
+ *
+ *  1	CPSR
+ *  7	Static registers, v1-v7 (aka r4-r10)
+ *  1	Frame pointer, fp (aka r11)
+ *  1	Stack pointer, sp (aka r13)
+ *  1	Return address, lr (aka r14)
+ * ---
+ * 11	(XCPTCONTEXT_USER_REG)
+ *
+ * On interrupts, we also need to save:
+ *  4	Volatile registers, a1-a4 (aka r0-r3)
+ *  1	Scratch Register, ip (aka r12)
+ *---
+ *  5	(XCPTCONTEXT_IRQ_REGS)
+ *
+ * For a total of 17 (XCPTCONTEXT_REGS)
+ */
+
+#ifndef __ASSEMBLY__
+struct xcptcontext
+{
+  /* The following function pointer is non-zero if there
+   * are pending signals to be processed.
+   */
+
+#ifndef CONFIG_DISABLE_SIGNALS
+  void *sigdeliver; /* Actual type is sig_deliver_t */
+
+  /* These are saved copies of LR and CPSR used during
+   * signal processing.
+   */
+
+  uint32 saved_pc;
+  uint32 saved_cpsr;
+#endif
+
+  /* Register save area */
+
+  uint32 regs[XCPTCONTEXT_REGS];
+};
+#endif
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* Save the current interrupt enable state & disable IRQs */
+
+static inline irqstate_t irqsave(void)
+{
+  unsigned int flags;
+  unsigned int temp;
+  __asm__ __volatile__
+    (
+     "\tmrs    %0, cpsr\n"
+     "\torr    %1, %0, #128\n"
+     "\tmsr    cpsr_c, %1"
+     : "=r" (flags), "=r" (temp)
+     :
+     : "memory");
+  return flags;
+}
+
+/* Restore saved IRQ & FIQ state */
+
+static inline void irqrestore(irqstate_t flags)
+{
+  __asm__ __volatile__
+    (
+     "msr    cpsr_c, %0"
+     :
+     : "r" (flags)
+     : "memory");
+}
+
+static inline void system_call(swint_t func, int parm1,
+			       int parm2, int parm3)
+{
+  __asm__ __volatile__
+    (
+     "mov\tr0,%0\n\t"
+     "mov\tr1,%1\n\t"
+     "mov\tr2,%2\n\t"
+     "mov\tr3,%3\n\t"
+     "swi\t0x900001\n\t"
+     :
+     : "r" ((long)(func)),  "r" ((long)(parm1)),
+       "r" ((long)(parm2)), "r" ((long)(parm3))
+     : "r0", "r1", "r2", "r3", "lr");
+}
+#endif /* __ASSEMBLY__ */
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_ARM_IRQ_H */
+

arch/arm/include/cortexm3/irq.h

@@ -0,0 +1,290 @@
+/****************************************************************************
+ * arch/arm/include/cortexm3/irq.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_CORTEXM3_IRQ_H
+#define __ARCH_ARM_INCLUDE_CORTEXM3_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/irq.h>
+#include <sys/types.h>
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* IRQ Stack Frame Format: */
+
+/* On entry into an IRQ, the hardware automatically saves the following
+ * registers on the stack in this (address) order:
+ */
+
+#define REG_XPSR            (17) /* xPSR */
+#define REG_R15             (16) /* R15 = PC */
+#define REG_R14             (15) /* R14 = LR */
+#define REG_R12             (14) /* R12 */
+#define REG_R3              (13) /* R3 */
+#define REG_R2              (12) /* R2 */
+#define REG_R1              (11) /* R1 */
+#define REG_R0              (10) /* R0 */
+
+#define HW_XCPT_REGS        (8)
+#define HW_XCPT_SIZE        (4 * HW_XCPT_REGS)
+
+/* The following additional registers are stored by the interrupt handling
+ * logic.
+ */
+
+#define REG_R11             (9) /* R11 */
+#define REG_R10             (8) /* R10 */
+#define REG_R9              (7) /* R9 */
+#define REG_R8              (6) /* R8 */
+#define REG_R7              (5) /* R7 */
+#define REG_R6              (4) /* R6 */
+#define REG_R5              (3) /* R5 */
+#define REG_R4              (2) /* R4 */
+#define REG_PRIMASK         (1) /* PRIMASK */
+#define REG_R13             (0) /* R13 = SP at time of interrupt */
+
+#define SW_XCPT_REGS        (10)
+#define SW_XCPT_SIZE        (4 * SW_XCPT_REGS)
+
+#define XCPTCONTEXT_REGS    (HW_XCPT_REGS + SW_XCPT_REGS)
+#define XCPTCONTEXT_SIZE    (HW_XCPT_SIZE + SW_XCPT_SIZE)
+
+#define REG_A1              REG_R0
+#define REG_A2              REG_R1
+#define REG_A3              REG_R2
+#define REG_A4              REG_R3
+#define REG_V1              REG_R4
+#define REG_V2              REG_R5
+#define REG_V3              REG_R6
+#define REG_V4              REG_R7
+#define REG_V5              REG_R8
+#define REG_V6              REG_R9
+#define REG_V7              REG_R10
+#define REG_SB              REG_R9
+#define REG_SL              REG_R10
+#define REG_FP              REG_R11
+#define REG_IP              REG_R12
+#define REG_SP              REG_R13
+#define REG_LR              REG_R14
+#define REG_PC              REG_R15
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* The following structure is included in the TCB and defines the complete
+ * state of the thread.
+ */
+
+#ifndef __ASSEMBLY__
+struct xcptcontext
+{
+  /* The following function pointer is non-zero if there
+   * are pending signals to be processed.
+   */
+
+#ifndef CONFIG_DISABLE_SIGNALS
+  void *sigdeliver; /* Actual type is sig_deliver_t */
+
+  /* These are saved copies of LR, PRIMASK, and xPSR used during
+   * signal processing.
+   */
+
+  uint32 saved_pc;
+  uint32 saved_primask;
+  uint32 saved_xpsr;
+#endif
+
+  /* Register save area */
+
+  uint32 regs[XCPTCONTEXT_REGS];
+};
+#endif
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* Save the current primask state & disable IRQs */
+
+static inline irqstate_t irqsave(void)
+{
+  unsigned short primask;
+
+  /* Return the the current value of primask register and set
+   * bit 0 of the primask register to disable interrupts
+   */
+
+  __asm__ __volatile__
+    (
+     "\tmrs    %0, primask\n"
+     "\tcpsid  i\n"
+     : "=r" (primask)
+     :
+     : "memory");
+  return primask;
+}
+
+/* Restore saved primask state */
+
+static inline void irqrestore(irqstate_t primask)
+{
+  /* If bit 0 of the primask is 0, then we need to restore
+   * interupts.
+   */
+
+  __asm__ __volatile__
+    (
+      "\ttst    %0, #1\n"
+      "\tbne    1f\n"
+      "\tcpsie  i\n"
+      "1:\n"
+      :
+      : "r" (primask)
+      : "memory");
+}
+
+/* Get/set the primask register */
+
+static inline ubyte getprimask(void)
+{
+  uint32 primask;
+  __asm__ __volatile__
+    (
+     "\tmrs  %0, primask\n"
+     : "=r" (primask)
+     :
+     : "memory");
+  return (ubyte)primask;
+}
+
+static inline void setprimask(uint32 primask)
+{
+  __asm__ __volatile__
+    (
+      "\tmsr primask, %0\n"
+      :
+      : "r" (primask)
+      : "memory");
+}
+
+/* Get/set the basepri register */
+
+static inline ubyte getbasepri(void)
+{
+  uint32 basepri;
+  __asm__ __volatile__
+    (
+     "\tmrs  %0, basepri\n"
+     : "=r" (basepri)
+     :
+     : "memory");
+  return (ubyte)basepri;
+}
+
+static inline void setbasepri(uint32 basepri)
+{
+  __asm__ __volatile__
+    (
+      "\tmsr basepri, %0\n"
+      :
+      : "r" (basepri)
+      : "memory");
+}
+
+/* Get IPSR */
+
+static inline uint32 getipsr(void)
+{
+  uint32 ipsr;
+  __asm__ __volatile__
+    (
+     "\tmrs  %0, ipsr\n"
+     : "=r" (ipsr)
+     :
+     : "memory");
+  return ipsr;
+}
+
+/* SVC system call */
+
+static inline void svcall(uint32 cmd, uint32 arg)
+{
+  __asm__ __volatile__
+    (
+      "\tmov  r0, %0\n"
+      "\tmov  r1, %1\n"
+      "\tsvc  0\n"
+      :
+      : "r" (cmd), "r" (arg)
+      : "memory");
+}
+#endif /* __ASSEMBLY__ */
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_CORTEXM3_IRQ_H */
+

arch/arm/include/irq.h

@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/include/irq.h
  *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
  *
  ****************************************************************************/
 
-/* This file should never be included directed but, rather,
- * only indirectly through nuttx/irq.h
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
  */
 
 #ifndef __ARCH_ARM_INCLUDE_IRQ_H
@@ -44,165 +44,36 @@
  * Included Files
  ****************************************************************************/
 
+/* Include NuttX-specific IRQ definitions */
+
 #include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
 #include <arch/chip/irq.h>
 
+/* Include ARM architectgure-specific IRQ definitions (including register
+ * save structure and irqsave()/irqrestore() macros
+ */
+
+#ifdef CONFIG_ARCH_CORTEXM3
+# include <arch/cortexm3/irq.h>
+#else
+# include <arch/arm/irq.h>
+#endif
+
 /****************************************************************************
  * Definitions
  ****************************************************************************/
 
-/* IRQ Stack Frame Format:
- *
- * Context is always saved/restored in the same way:
- *
- *   (1) stmia rx, {r0-r14}
- *   (2) then the PC and CPSR
- *
- * This results in the following set of indices that
- * can be used to access individual registers in the
- * xcp.regs array:
- */
-
-#define REG_R0              (0)
-#define REG_R1              (1)
-#define REG_R2              (2)
-#define REG_R3              (3)
-#define REG_R4              (4)
-#define REG_R5              (5)
-#define REG_R6              (6)
-#define REG_R7              (7)
-#define REG_R8              (8)
-#define REG_R9              (9)
-#define REG_R10             (10)
-#define REG_R11             (11)
-#define REG_R12             (12)
-#define REG_R13             (13)
-#define REG_R14             (14)
-#define REG_R15             (15)
-#define REG_CPSR            (16)
-
-#define XCPTCONTEXT_REGS    (17)
-#define XCPTCONTEXT_SIZE    (4 * XCPTCONTEXT_REGS)
-
-#define REG_A1              REG_R0
-#define REG_A2              REG_R1
-#define REG_A3              REG_R2
-#define REG_A4              REG_R3
-#define REG_V1              REG_R4
-#define REG_V2              REG_R5
-#define REG_V3              REG_R6
-#define REG_V4              REG_R7
-#define REG_V5              REG_R8
-#define REG_V6              REG_R9
-#define REG_V7              REG_R10
-#define REG_SB              REG_R9
-#define REG_SL              REG_R10
-#define REG_FP              REG_R11
-#define REG_IP              REG_R12
-#define REG_SP              REG_R13
-#define REG_LR              REG_R14
-#define REG_PC              REG_R15
-
 /****************************************************************************
  * Public Types
  ****************************************************************************/
 
-/* This struct defines the way the registers are stored.  We
- * need to save:
- *
- *  1	CPSR
- *  7	Static registers, v1-v7 (aka r4-r10)
- *  1	Frame pointer, fp (aka r11)
- *  1	Stack pointer, sp (aka r13)
- *  1	Return address, lr (aka r14)
- * ---
- * 11	(XCPTCONTEXT_USER_REG)
- *
- * On interrupts, we also need to save:
- *  4	Volatile registers, a1-a4 (aka r0-r3)
- *  1	Scratch Register, ip (aka r12)
- *---
- *  5	(XCPTCONTEXT_IRQ_REGS)
- *
- * For a total of 17 (XCPTCONTEXT_REGS)
- */
-
-#ifndef __ASSEMBLY__
-struct xcptcontext
-{
-  /* The following function pointer is non-zero if there
-   * are pending signals to be processed.
-   */
-
-#ifndef CONFIG_DISABLE_SIGNALS
-  void *sigdeliver; /* Actual type is sig_deliver_t */
-
-  /* These are saved copies of LR and CPSR used during
-   * signal processing.
-   */
-
-  uint32 saved_pc;
-  uint32 saved_cpsr;
-#endif
-
-  /* Register save area */
-
-  uint32 regs[XCPTCONTEXT_REGS];
-};
-#endif
-
 /****************************************************************************
  * Inline functions
  ****************************************************************************/
 
-#ifndef __ASSEMBLY__
-
-/* Save the current interrupt enable state & disable IRQs */
-
-static inline irqstate_t irqsave(void)
-{
-  unsigned int flags;
-  unsigned int temp;
-  __asm__ __volatile__
-    (
-     "\tmrs    %0, cpsr\n"
-     "\torr    %1, %0, #128\n"
-     "\tmsr    cpsr_c, %1"
-     : "=r" (flags), "=r" (temp)
-     :
-     : "memory");
-  return flags;
-}
-
-/* Restore saved IRQ & FIQ state */
-
-static inline void irqrestore(irqstate_t flags)
-{
-  __asm__ __volatile__
-    (
-     "msr    cpsr_c, %0"
-     :
-     : "r" (flags)
-     : "memory");
-}
-
-static inline void system_call(swint_t func, int parm1,
-			       int parm2, int parm3)
-{
-  __asm__ __volatile__
-    (
-     "mov\tr0,%0\n\t"
-     "mov\tr1,%1\n\t"
-     "mov\tr2,%2\n\t"
-     "mov\tr3,%3\n\t"
-     "swi\t0x900001\n\t"
-     :
-     : "r" ((long)(func)),  "r" ((long)(parm1)),
-       "r" ((long)(parm2)), "r" ((long)(parm3))
-     : "r0", "r1", "r2", "r3", "lr");
-}
-#endif
-
 /****************************************************************************
  * Public Variables
  ****************************************************************************/

arch/arm/include/lm3s/irq.h

@@ -0,0 +1,301 @@
+/************************************************************************************
+ * arch/arm/include/lm3s/irq.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/* This file should never be included directed but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_LM3S_IRQ_H
+#define __ARCH_ARM_INCLUDE_LM3S_IRQ_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <nuttx/irq.h>
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* IRQ numbers.  The IRQ number corresponds vector number and hence map directly to
+ * bits in the NVIC.  This does, however, waste several words of memory in the IRQ
+ * to handle mapping tables.
+ */
+
+/* Processor Exceptions (vectors 0-15) */
+
+#define LM3S_IRQ_RESERVED     (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+                                  /* Vector  0: Reset stack pointer value */
+                                  /* Vector  1: Reset (not handler as an IRQ) */
+#define LM3S_IRQ_NMI          (2) /* Vector  2: Non-Maskable Interrupt (NMI) */
+#define LM3S_IRQ_HARDFAULT    (3) /* Vector  3: Hard fault */
+#define LM3S_IRQ_MPU          (4) /* Vector  4: Memory management (MPU) */
+#define LM3S_IRQ_BUSFAULT     (5) /* Vector  5: Bus fault */
+#define LM3S_IRQ_USAGEFAULT   (6) /* Vector  6: Usage fault */
+#define LM3S_IRQ_SVCALL      (11) /* Vector 11: SVC call */
+#define LM3S_IRQ_DBGMONITOR  (12) /* Vector 12: Debug Monitor */
+                                  /* Vector 13: Reserved */
+#define LM3S_IRQ_PENDSV      (14) /* Vector 14: Pendable system service request */
+#define LM3S_IRQ_SYSTICK     (15) /* Vector 15: System tick */
+
+/* External interrupts (vectors >= 16) */
+
+#define LM3S_IRQ_INTERRUPTS  (16) /* Vector number of the first external interrupt */
+#ifdef CONFIG_ARCH_CHIP_LM3S6918
+
+#  define LM3S_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
+#  define LM3S_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
+#  define LM3S_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
+#  define LM3S_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
+#  define LM3S_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
+#  define LM3S_IRQ_UART0     (21) /* Vector 21: UART 0 */
+#  define LM3S_IRQ_UART1     (22) /* Vector 22: UART 1 */
+#  define LM3S_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
+#  define LM3S_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
+                                  /* Vector 25-29: Reserved */
+#  define LM3S_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
+#  define LM3S_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
+#  define LM3S_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
+#  define LM3S_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
+#  define LM3S_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
+#  define LM3S_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
+#  define LM3S_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
+#  define LM3S_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
+#  define LM3S_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
+#  define LM3S_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
+#  define LM3S_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
+#  define LM3S_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
+#  define LM3S_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
+                                  /* Vector 43: Reserved */
+#  define LM3S_IRQ_SYSCON    (44) /* Vector 44: System Control */
+#  define LM3S_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
+#  define LM3S_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
+#  define LM3S_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
+#  define LM3S_IRQ_GPIOH     (48) /* Vector 48: GPIO Port H */
+                                  /* Vector 49: Reserved */
+#  define LM3S_IRQ_SSI1      (50) /* Vector 50: SSI 1 */
+#  define LM3S_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
+#  define LM3S_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
+#  define LM3S_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
+                                  /* Vectors 54-57: Reserved */
+#  define LM3S_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
+#  define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
+                                  /* Vectors 60-70: Reserved */
+#else
+#  error "IRQ Numbers not specified for this LM3S chip"
+#endif
+
+#define NR_IRQS              (60) /* Really only 43 */
+
+/* GPIO IRQs -- Note that support for individual GPIO ports can
+ * be disabled in order to reduce the size of the implemenation.
+ */
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS
+#  define LM3S_IRQ_GPIOA_0 (NR_IRQS + 0)
+#  define LM3S_IRQ_GPIOA_1 (NR_IRQS + 1)
+#  define LM3S_IRQ_GPIOA_2 (NR_IRQS + 2)
+#  define LM3S_IRQ_GPIOA_3 (NR_IRQS + 3)
+#  define LM3S_IRQ_GPIOA_4 (NR_IRQS + 4)
+#  define LM3S_IRQ_GPIOA_5 (NR_IRQS + 5)
+#  define LM3S_IRQ_GPIOA_6 (NR_IRQS + 6)
+#  define LM3S_IRQ_GPIOA_7 (NR_IRQS + 7)
+#  define _NGPIOAIRQS      (NR_IRQS + 8)
+#else
+#  define _NGPIOAIRQS      NR_IRQS
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS
+#  define LM3S_IRQ_GPIOB_0 (_NGPIOAIRQS + 0)
+#  define LM3S_IRQ_GPIOB_1 (_NGPIOAIRQS + 1)
+#  define LM3S_IRQ_GPIOB_2 (_NGPIOAIRQS + 2)
+#  define LM3S_IRQ_GPIOB_3 (_NGPIOAIRQS + 3)
+#  define LM3S_IRQ_GPIOB_4 (_NGPIOAIRQS + 4)
+#  define LM3S_IRQ_GPIOB_5 (_NGPIOAIRQS + 5)
+#  define LM3S_IRQ_GPIOB_6 (_NGPIOAIRQS + 6)
+#  define LM3S_IRQ_GPIOB_7 (_NGPIOAIRQS + 7)
+#  define _NGPIOBIRQS      (_NGPIOAIRQS + 8)
+#else
+#  define _NGPIOBIRQS      _NGPIOAIRQS
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS
+#  define LM3S_IRQ_GPIOC_0 (_NGPIOBIRQS + 0)
+#  define LM3S_IRQ_GPIOC_1 (_NGPIOBIRQS + 1)
+#  define LM3S_IRQ_GPIOC_2 (_NGPIOBIRQS + 2)
+#  define LM3S_IRQ_GPIOC_3 (_NGPIOBIRQS + 3)
+#  define LM3S_IRQ_GPIOC_4 (_NGPIOBIRQS + 4)
+#  define LM3S_IRQ_GPIOC_5 (_NGPIOBIRQS + 5)
+#  define LM3S_IRQ_GPIOC_6 (_NGPIOBIRQS + 6)
+#  define LM3S_IRQ_GPIOC_7 (_NGPIOBIRQS + 7)
+#  define _NGPIOCIRQS      (_NGPIOBIRQS + 8)
+#else
+#  define _NGPIOCIRQS      _NGPIOBIRQS
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS
+#  define LM3S_IRQ_GPIOD_0 (_NGPIOCIRQS + 0)
+#  define LM3S_IRQ_GPIOD_1 (_NGPIOCIRQS + 1)
+#  define LM3S_IRQ_GPIOD_2 (_NGPIOCIRQS + 2)
+#  define LM3S_IRQ_GPIOD_3 (_NGPIOCIRQS + 3)
+#  define LM3S_IRQ_GPIOD_4 (_NGPIOCIRQS + 4)
+#  define LM3S_IRQ_GPIOD_5 (_NGPIOCIRQS + 5)
+#  define LM3S_IRQ_GPIOD_6 (_NGPIOCIRQS + 6)
+#  define LM3S_IRQ_GPIOD_7 (_NGPIOCIRQS + 7)
+#  define _NGPIODIRQS      (_NGPIOCIRQS + 8)
+#else
+#  define _NGPIODIRQS      _NGPIOCIRQS
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS
+#  define LM3S_IRQ_GPIOE_0 (_NGPIODIRQS + 0)
+#  define LM3S_IRQ_GPIOE_1 (_NGPIODIRQS + 1)
+#  define LM3S_IRQ_GPIOE_2 (_NGPIODIRQS + 2)
+#  define LM3S_IRQ_GPIOE_3 (_NGPIODIRQS + 3)
+#  define LM3S_IRQ_GPIOE_4 (_NGPIODIRQS + 4)
+#  define LM3S_IRQ_GPIOE_5 (_NGPIODIRQS + 5)
+#  define LM3S_IRQ_GPIOE_6 (_NGPIODIRQS + 6)
+#  define LM3S_IRQ_GPIOE_7 (_NGPIODIRQS + 7)
+#  define _NGPIOEIRQS      (_NGPIODIRQS + 8)
+#else
+#  define _NGPIOEIRQS      _NGPIODIRQS
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS
+#  define LM3S_IRQ_GPIOF_0 (_NGPIOEIRQS + 0)
+#  define LM3S_IRQ_GPIOF_1 (_NGPIOEIRQS + 1)
+#  define LM3S_IRQ_GPIOF_2 (_NGPIOEIRQS + 2)
+#  define LM3S_IRQ_GPIOF_3 (_NGPIOEIRQS + 3)
+#  define LM3S_IRQ_GPIOF_4 (_NGPIOEIRQS + 4)
+#  define LM3S_IRQ_GPIOF_5 (_NGPIOEIRQS + 5)
+#  define LM3S_IRQ_GPIOF_6 (_NGPIOEIRQS + 6)
+#  define LM3S_IRQ_GPIOF_7 (_NGPIOEIRQS + 7)
+#  define _NGPIOFIRQS      (_NGPIOEIRQS + 8)
+#else
+#  define _NGPIOFIRQS      _NGPIOEIRQS
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS
+#  define LM3S_IRQ_GPIOG_0 (_NGPIOFIRQS + 0)
+#  define LM3S_IRQ_GPIOG_1 (_NGPIOFIRQS + 1)
+#  define LM3S_IRQ_GPIOG_2 (_NGPIOFIRQS + 2)
+#  define LM3S_IRQ_GPIOG_3 (_NGPIOFIRQS + 3)
+#  define LM3S_IRQ_GPIOG_4 (_NGPIOFIRQS + 4)
+#  define LM3S_IRQ_GPIOG_5 (_NGPIOFIRQS + 5)
+#  define LM3S_IRQ_GPIOG_6 (_NGPIOFIRQS + 6)
+#  define LM3S_IRQ_GPIOG_7 (_NGPIOFIRQS + 7)
+#  define _NGPIOGIRQS      (_NGPIOFIRQS + 8)
+#else
+#  define _NGPIOGIRQS      _NGPIOFIRQS
+#endif
+
+#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS
+#  define LM3S_IRQ_GPIOH_0 (_NGPIOGIRQS + 0)
+#  define LM3S_IRQ_GPIOH_1 (_NGPIOGIRQS + 1)
+#  define LM3S_IRQ_GPIOH_2 (_NGPIOGIRQS + 2)
+#  define LM3S_IRQ_GPIOH_3 (_NGPIOGIRQS + 3)
+#  define LM3S_IRQ_GPIOH_4 (_NGPIOGIRQS + 4)
+#  define LM3S_IRQ_GPIOH_5 (_NGPIOGIRQS + 5)
+#  define LM3S_IRQ_GPIOH_6 (_NGPIOGIRQS + 6)
+#  define LM3S_IRQ_GPIOH_7 (_NGPIOGIRQS + 7)
+#  define _NGPIOHIRQS      (_NGPIOGIRQS + 8)
+#else
+#  define _NGPIOHIRQS      _NGPIOGIRQS
+#endif
+
+#define NR_GPIO_IRQS       (_NGPIOHIRQS - NR_IRQS)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/****************************************************************************
+ * Name: gpio_irqattach
+ *
+ * Description:
+ *   Attach the interrupt handler 'isr' to the GPIO IRQ 'irq'
+ *
+ ****************************************************************************/
+
+EXTERN int gpio_irqattach(int irq, xcpt_t isr);
+#define gpio_irqdetach(isr) gpio_irqattach(isr, NULL)
+
+/****************************************************************************
+ * Name: gpio_irqenable
+ *
+ * Description:
+ *   Enable the GPIO IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+EXTERN void gpio_irqenable(int irq);
+
+/****************************************************************************
+ * Name: gpio_irqdisable
+ *
+ * Description:
+ *   Disable the GPIO IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+EXTERN void gpio_irqdisable(int irq);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_LM3S_IRQ_H */
+

arch/arm/include/types.h

@@ -67,11 +67,16 @@ typedef unsigned int uint32;
 typedef long long sint64;
 typedef unsigned long long uint64;
 
-/* This is the size of the interrupt state save returned by
- * irqsave()
+/* This is the size of the interrupt state save returned by irqsave().  For
+ * ARM, a 32 register value is returned, for the thumb2, Cortex-M3, the 16-bit
+ * primask register value is returned,
  */
 
+#ifdef __thumb2__
+typedef unsigned short irqstate_t;
+#else /* __thumb2__ */
 typedef unsigned int irqstate_t;
+#endif /* __thumb2__ */
 
 #endif /* __ASSEMBLY__ */
 

arch/arm/src/Makefile

@@ -1,7 +1,7 @@
 ############################################################################
 # arch/arm/src/Makefile
 #
-#   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -37,7 +37,14 @@
 -include chip/Make.defs
 
 ARCH_SRCDIR	= $(TOPDIR)/arch/$(CONFIG_ARCH)/src
-CFLAGS		+= -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(TOPDIR)/sched
+ifeq ($(CONFIG_ARCH_CORTEXM3),y)
+ARCH_SUBDIR	= cortexm3
+else
+ARCH_SUBDIR	= arm
+endif
+
+CFLAGS		+= -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common \
+		   -I$(ARCH_SRCDIR)/$(ARCH_SUBDIR) -I$(TOPDIR)/sched
 
 HEAD_AOBJ	= $(HEAD_ASRC:.S=$(OBJEXT))
 
@@ -59,9 +66,9 @@ LDLIBS		= $(patsubst lib%,-l%,$(basename $(notdir $(LINKLIBS))))
 
 BOARDDIR	= $(TOPDIR)/arch/$(CONFIG_ARCH)/src/board
 
-LIBGCC		= ${shell $(CC) -print-libgcc-file-name}
+LIBGCC		= "${shell $(CC) -print-libgcc-file-name}"
 
-VPATH		= chip:common
+VPATH		= chip:common:$(ARCH_SUBDIR)
 
 all: $(HEAD_OBJ) libarch$(LIBEXT)
 
@@ -77,7 +84,7 @@ libarch$(LIBEXT): $(OBJS)
 	done ; )
 
 board/libboard$(LIBEXT):
-	$(MAKE) -C board TOPDIR="$(TOPDIR)" libboard$(LIBEXT)
+	@$(MAKE) -C board TOPDIR="$(TOPDIR)" libboard$(LIBEXT)
 
 nuttx: $(HEAD_AOBJ) board/libboard$(LIBEXT)
 	@echo "LD: nuttx"
@@ -85,7 +92,7 @@ nuttx: $(HEAD_AOBJ) board/libboard$(LIBEXT)
 		--start-group $(LDLIBS) -lboard --end-group $(EXTRA_LIBS) $(LIBGCC)
 ifeq ($(CONFIG_BOOT_RUNFROMFLASH),y)
 	@export flashloc=`$(OBJDUMP) --all-headers $(TOPDIR)/$@ | grep _eronly | cut -d' ' -f1`;  \
-	$(OBJCOPY) --adjust-section-vma=.data=0x$$flashloc $(TOPDIR)/$@ $(TOPDIR)/$@.flashimage
+	$(OBJCOPY) $(OBJCOPYARGS) --adjust-section-vma=.data=0x$$flashloc $(TOPDIR)/$@ $(TOPDIR)/$@.flashimage
 	@mv $(TOPDIR)/$@.flashimage $(TOPDIR)/$@
 endif
 	@$(NM) $(TOPDIR)/$@ | \
@@ -93,7 +100,7 @@ endif
 	sort > $(TOPDIR)/System.map
 	@export vflashstart=`$(OBJDUMP) --all-headers $(TOPDIR)/$@ | grep _vflashstart | cut -d' ' -f1`;  \
 	if [ ! -z "$$vflashstart" ]; then \
-		$(OBJCOPY) --adjust-section-vma=.vector=0x$$vflashstart $(TOPDIR)/$@ $(TOPDIR)/$@.flashimage; \
+		$(OBJCOPY) $(OBJCOPYARGS) --adjust-section-vma=.vector=0x$$vflashstart $(TOPDIR)/$@ $(TOPDIR)/$@.flashimage; \
 		mv $(TOPDIR)/$@.flashimage $(TOPDIR)/$@; \
 	fi
 
@@ -101,7 +108,8 @@ endif
 	@if [ -e board/Makefile ]; then \
 		$(MAKE) -C board TOPDIR="$(TOPDIR)" depend ; \
 	fi
-	@$(MKDEP) --dep-path chip --dep-path common $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
+	@$(MKDEP) --dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR) \
+	 $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
 	@touch $@
 
 depend: .depend

arch/arm/src/arm/arm.h

@@ -1,7 +1,7 @@
 /************************************************************************************
- * arch/arm/src/common/arm.h
+ * arch/arm/src/arm/arm.h
  *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -44,9 +44,9 @@
 # include <sys/types.h>
 #endif
 
-/**************************************************************************
- * Conditional Compilation
- **************************************************************************/
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
 
 #undef CONFIG_ALIGNMENT_TRAP
 #undef CONFIG_DCACHE_WRITETHROUGH
@@ -54,10 +54,6 @@
 #undef CONFIG_DCACHE_DISABLE
 #undef CONFIG_ICACHE_DISABLE
 
-/************************************************************************************
- * Definitions
- ************************************************************************************/
-
 /* ARM9EJS **************************************************************************/
 
 /* PSR bits */

arch/arm/src/arm/up_assert.c

@@ -1,7 +1,7 @@
 /****************************************************************************
- * common/up_assert.c
+ * arch/arm/src/arm/up_assert.c
  *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -132,6 +132,7 @@ static inline void up_registerdump(void)
                  regs, ptr[0], ptr[1], ptr[2], ptr[3],
                  ptr[4], ptr[5], ptr[6], ptr[7]);
         }
+
       lldbg("CPSR: %08x\n", current_regs[REG_CPSR]);
     }
 }

arch/arm/src/arm/up_cache.S

@@ -1,7 +1,7 @@
-/********************************************************************
- * common/up_cache.S
+/****************************************************************************
+ * arch/arm/src/arm/up_cache.S
  *
- *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -14,7 +14,7 @@
  *    notice, this list of conditions and the following disclaimer in
  *    the documentation and/or other materials provided with the
  *    distribution.
- * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ * 3. Neither the name NuttX nor the names of its contributors may be
  *    used to endorse or promote products derived from this software
  *    without specific prior written permission.
  *
@@ -31,29 +31,29 @@
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
- ********************************************************************/
+ ****************************************************************************/
 
-/********************************************************************
+/****************************************************************************
  * Included Files
- ********************************************************************/
+ ****************************************************************************/
 
 #include <nuttx/config.h>
 #include "up_internal.h"
 #include "up_arch.h"
 
-/********************************************************************
+/****************************************************************************
  * Definitions
- ********************************************************************/
+ ****************************************************************************/
 
 #define CACHE_DLINESIZE    32
 
-/********************************************************************
+/****************************************************************************
  * Assembly Macros
- ********************************************************************/
+ ****************************************************************************/
 
-/**************************************************************************
+/****************************************************************************
  * Name: up_flushicache
- **************************************************************************/
+ ****************************************************************************/
 
 /* Esure coherency between the Icache and the Dcache in the region described 
  * by r0=start and r1=end.

arch/arm/src/arm/up_copystate.c

@@ -1,7 +1,7 @@
 /****************************************************************************
- * arch/arm/src/common/up_copystate.c
+ * arch/arm/src/arm/up_copystate.c
  *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -69,6 +69,11 @@
 void up_copystate(uint32 *dest, uint32 *src)
 {
   int i;
+
+  /* In the current ARM model, the state is always copied to and from the
+   * stack and TCB.
+   */
+
   for (i = 0; i < XCPTCONTEXT_REGS; i++)
     {
       *dest++ = *src++;

arch/arm/src/arm/up_dataabort.c

@@ -1,7 +1,7 @@
 /****************************************************************************
- * arch/arm/src/common/up_dataabort.c
+ * arch/arm/src/arm/up_dataabort.c
  *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without

arch/arm/src/arm/up_doirq.c

@@ -1,7 +1,7 @@
 /****************************************************************************
- * arch/arm/src/common/up_doirq.c
+ * arch/arm/src/arm/up_doirq.c
  *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -66,39 +66,40 @@
  * Public Functions
  ****************************************************************************/
 
-void up_doirq(int irq, uint32* regs)
+void up_doirq(int irq, uint32 *regs)
 {
   up_ledon(LED_INIRQ);
 #ifdef CONFIG_SUPPRESS_INTERRUPTS
   PANIC(OSERR_ERREXCEPTION);
 #else
-  if ((unsigned)irq < NR_IRQS)
-    {
-       /* Current regs non-zero indicates that we are processing
-        * an interrupt; current_regs is also used to manage
-        * interrupt level context switches.
-        */
+  /* Nested interrupts are not supported in this implementation.  If you want
+   * implemented nested interrupts, you would have to (1) change the way that
+   * current regs is handled and (2) the design associated with
+   * CONFIG_ARCH_INTERRUPTSTACK.
+   */
 
-       current_regs = regs;
+  /* Current regs non-zero indicates that we are processing an interrupt;
+   * current_regs is also used to manage interrupt level context switches.
+   */
 
-       /* Mask and acknowledge the interrupt */
+  DEBUGASSERT(current_regs == NULL);
+  current_regs = regs;
 
-       up_maskack_irq(irq);
+  /* Mask and acknowledge the interrupt */
 
-       /* Deliver the IRQ */
+  up_maskack_irq(irq);
 
-       irq_dispatch(irq, regs);
+  /* Deliver the IRQ */
 
-       /* Indicate that we are no long in an interrupt handler */
+  irq_dispatch(irq, regs);
 
-       current_regs = NULL;
+  /* Indicate that we are no long in an interrupt handler */
 
-       /* Unmask the last interrupt (global interrupts are still
-        * disabled.
-        */
+  current_regs = NULL;
 
-       up_enable_irq(irq);
-    }
-  up_ledoff(LED_INIRQ);
+  /* Unmask the last interrupt (global interrupts are still disabled) */
+
+  up_enable_irq(irq);
 #endif
+  up_ledoff(LED_INIRQ);
 }

arch/arm/src/arm/up_fullcontextrestore.S

@@ -1,7 +1,7 @@
 /**************************************************************************
- * common/up_fullcontextrestore.S
+ * arch/arm/src/arm/up_fullcontextrestore.S
  *
- *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -14,7 +14,7 @@
  *    notice, this list of conditions and the following disclaimer in
  *    the documentation and/or other materials provided with the
  *    distribution.
- * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ * 3. Neither the name NuttX nor the names of its contributors may be
  *    used to endorse or promote products derived from this software
  *    without specific prior written permission.
  *

arch/arm/src/arm/up_head.S

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/common/up_head.S
+ * arch/arm/src/arm/up_head.S
  *
  *   Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -38,6 +38,8 @@
  ****************************************************************************/
 
 #include <nuttx/config.h>
+
+#include "arm.h"
 #include "up_internal.h"
 #include "up_arch.h"
 

arch/arm/src/arm/up_initialstate.c

@@ -1,7 +1,7 @@
 /****************************************************************************
- *  arch/arm/src/common/up_initialstate.c
+ *  arch/arm/src/arm/up_initialstate.c
  *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -40,7 +40,10 @@
 #include <nuttx/config.h>
 #include <sys/types.h>
 #include <string.h>
+
 #include <nuttx/arch.h>
+
+#include "arm.h"
 #include "up_internal.h"
 #include "up_arch.h"
 
@@ -81,11 +84,21 @@ void up_initial_state(_TCB *tcb)
   /* Initialize the initial exception register context structure */
 
   memset(xcp, 0, sizeof(struct xcptcontext));
-  xcp->regs[REG_SP]   = (uint32)tcb->adj_stack_ptr;
-  xcp->regs[REG_PC]   = (uint32)tcb->start;
-#ifdef CONFIG_SUPPRESS_INTERRUPTS
-  xcp->regs[REG_CPSR] = SVC_MODE | PSR_I_BIT | PSR_F_BIT;
-#else
-  xcp->regs[REG_CPSR] = SVC_MODE | PSR_F_BIT;
-#endif
+
+  /* Save the initial stack pointer */
+
+  xcp->regs[REG_SP]      = (uint32)tcb->adj_stack_ptr;
+
+  /* Save the task entry point */
+
+  xcp->regs[REG_PC]      = (uint32)tcb->start;
+
+  /* Enable or disable interrupts, based on user configuration */
+
+# ifdef CONFIG_SUPPRESS_INTERRUPTS
+  xcp->regs[REG_CPSR]    = SVC_MODE | PSR_I_BIT | PSR_F_BIT;
+# else
+  xcp->regs[REG_CPSR]    = SVC_MODE | PSR_F_BIT;
+# endif
 }
+

arch/arm/src/arm/up_nommuhead.S

@@ -1,7 +1,7 @@
-/********************************************************************
- * common/up_nommuhead.S
+/****************************************************************************
+ * arch/arm/src/arm/up_nommuhead.S
  *
- *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -14,7 +14,7 @@
  *    notice, this list of conditions and the following disclaimer in
  *    the documentation and/or other materials provided with the
  *    distribution.
- * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ * 3. Neither the name NuttX nor the names of its contributors may be
  *    used to endorse or promote products derived from this software
  *    without specific prior written permission.
  *
@@ -31,19 +31,21 @@
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
- ********************************************************************/
+ ****************************************************************************/
 
-/********************************************************************
+/****************************************************************************
  * Included Files
- ********************************************************************/
+ ****************************************************************************/
 
 #include <nuttx/config.h>
+
+#include "arm.h"
 #include "up_internal.h"
 #include "up_arch.h"
 
-/********************************************************************
+/****************************************************************************
  * Macros
- ********************************************************************/
+ ****************************************************************************/
 
 	/* This macro will modify r0, r1, r2 and r14 */
 
@@ -57,9 +59,9 @@
 	.endm
 #endif
 
-/********************************************************************
+/****************************************************************************
  * OS Entry Point
- ********************************************************************/
+ ****************************************************************************/
 
 /* We assume the bootloader has already initialized most of the h/w for
  * us and that only leaves us having to do some os specific things

arch/arm/src/arm/up_prefetchabort.c

@@ -1,7 +1,7 @@
 /****************************************************************************
- *  arch/arm/src/common/up_prefetchabort.c
+ *  arch/arm/src/src/up_prefetchabort.c
  *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without

arch/arm/src/arm/up_saveusercontext.S

@@ -1,7 +1,7 @@
 /**************************************************************************
- * common/up_saveusercontext.S
+ * arch/arm/src/arm/up_saveusercontext.S
  *
- *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -14,7 +14,7 @@
  *    notice, this list of conditions and the following disclaimer in
  *    the documentation and/or other materials provided with the
  *    distribution.
- * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ * 3. Neither the name NuttX nor the names of its contributors may be
  *    used to endorse or promote products derived from this software
  *    without specific prior written permission.
  *

arch/arm/src/arm/up_schedulesigaction.c

@@ -1,7 +1,7 @@
 /****************************************************************************
- * common/up_schedulesigaction.c
+ * arch/arm/src/arm/up_schedulesigaction.c
  *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -45,6 +45,7 @@
 
 #include <nuttx/arch.h>
 
+#include "arm.h"
 #include "os_internal.h"
 #include "up_internal.h"
 #include "up_arch.h"
@@ -137,6 +138,12 @@ void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver)
            * interrupted task is the same as the one that
            * must receive the signal, then we will have to modify
            * the return state as well as the state in the TCB.
+           *
+           * Hmmm... there looks like a latent bug here: The following
+           * logic would fail in the strange case where we are in an
+           * interrupt handler, the thread is signalling itself, but
+           * a context switch to another task has occurred so that
+           * current_regs does not refer to the thread at g_readytorun.head!
            */
 
           else
@@ -146,22 +153,22 @@ void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver)
                * the signals have been delivered.
                */
 
-              tcb->xcp.sigdeliver    = sigdeliver;
-              tcb->xcp.saved_pc      = current_regs[REG_PC];
-              tcb->xcp.saved_cpsr    = current_regs[REG_CPSR];
+              tcb->xcp.sigdeliver       = sigdeliver;
+              tcb->xcp.saved_pc         = current_regs[REG_PC];
+              tcb->xcp.saved_cpsr       = current_regs[REG_CPSR];
 
               /* Then set up to vector to the trampoline with interrupts
                * disabled
                */
 
-              current_regs[REG_PC]    = (uint32)up_sigdeliver;
-              current_regs[REG_CPSR]  = SVC_MODE | PSR_I_BIT | PSR_F_BIT;
+              current_regs[REG_PC]      = (uint32)up_sigdeliver;
+              current_regs[REG_CPSR]    = SVC_MODE | PSR_I_BIT | PSR_F_BIT;
 
               /* And make sure that the saved context in the TCB
                * is the same as the interrupt return context.
                */
 
-              up_copystate(tcb->xcp.regs, current_regs);
+              up_savestate(tcb->xcp.regs);
             }
         }
 
@@ -178,16 +185,16 @@ void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver)
            * the signals have been delivered.
            */
 
-          tcb->xcp.sigdeliver    = sigdeliver;
-          tcb->xcp.saved_pc      = tcb->xcp.regs[REG_PC];
-          tcb->xcp.saved_cpsr    = tcb->xcp.regs[REG_CPSR];
+          tcb->xcp.sigdeliver       = sigdeliver;
+          tcb->xcp.saved_pc         = tcb->xcp.regs[REG_PC];
+          tcb->xcp.saved_cpsr       = tcb->xcp.regs[REG_CPSR];
 
           /* Then set up to vector to the trampoline with interrupts
            * disabled
            */
 
-          tcb->xcp.regs[REG_PC]   = (uint32)up_sigdeliver;
-          tcb->xcp.regs[REG_CPSR] = SVC_MODE | PSR_I_BIT | PSR_F_BIT;
+          tcb->xcp.regs[REG_PC]      = (uint32)up_sigdeliver;
+          tcb->xcp.regs[REG_CPSR]    = SVC_MODE | PSR_I_BIT | PSR_F_BIT;
         }
 
       irqrestore(flags);

arch/arm/src/arm/up_sigdeliver.c

@@ -1,7 +1,7 @@
 /****************************************************************************
- * common/up_sigdeliver.c
+ * arch/arm/src/arm/up_sigdeliver.c
  *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -81,7 +81,6 @@
 
 void up_sigdeliver(void)
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   _TCB  *rtcb = (_TCB*)g_readytorun.head;
   uint32 regs[XCPTCONTEXT_REGS];
   sig_deliver_t sigdeliver;
@@ -102,8 +101,8 @@ void up_sigdeliver(void)
   /* Save the real return state on the stack. */
 
   up_copystate(regs, rtcb->xcp.regs);
-  regs[REG_PC]   = rtcb->xcp.saved_pc;
-  regs[REG_CPSR] = rtcb->xcp.saved_cpsr;
+  regs[REG_PC]         = rtcb->xcp.saved_pc;
+  regs[REG_CPSR]       = rtcb->xcp.saved_cpsr;
 
   /* Get a local copy of the sigdeliver function pointer.
    * we do this so that we can nullify the sigdeliver
@@ -138,7 +137,6 @@ void up_sigdeliver(void)
 
   up_ledoff(LED_SIGNAL);
   up_fullcontextrestore(regs);
-#endif
 }
 
 #endif /* !CONFIG_DISABLE_SIGNALS */

arch/arm/src/arm/up_syscall.c

@@ -1,7 +1,7 @@
 /****************************************************************************
- *  arch/arm/src/common/up_syscall.c
+ *  arch/arm/src/arm/up_syscall.c
  *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without

arch/arm/src/arm/up_undefinedinsn.c

@@ -1,7 +1,7 @@
 /****************************************************************************
- * arch/arm/src/common/up_undefinedinsn.c
+ * arch/arm/src/arm/up_undefinedinsn.c
  *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without

arch/arm/src/arm/up_vectoraddrexcptn.S

@@ -1,7 +1,7 @@
 /************************************************************************************
- * arch/arm/src/common/up_vectoraddrexceptn.S
+ * arch/arm/src/src/up_vectoraddrexceptn.S
  *
- *   Copyright (C) 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without

arch/arm/src/arm/up_vectors.S

@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/common/up_vectors.S
+ * arch/arm/src/arm/up_vectors.S
  *
  *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -40,6 +40,7 @@
 #include <nuttx/config.h>
 #include <nuttx/irq.h>
 
+#include "arm.h"
 #include "up_arch.h"
 
 /************************************************************************************

arch/arm/src/arm/up_vectortab.S

@@ -1,7 +1,7 @@
-/********************************************************************
- * common/up_vectortab.S
+/****************************************************************************
+ * arch/arm/src/arm/up_vectortab.S
  *
- *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -14,7 +14,7 @@
  *    notice, this list of conditions and the following disclaimer in
  *    the documentation and/or other materials provided with the
  *    distribution.
- * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ * 3. Neither the name NuttX nor the names of its contributors may be
  *    used to endorse or promote products derived from this software
  *    without specific prior written permission.
  *
@@ -31,32 +31,32 @@
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
- ********************************************************************/
+ ****************************************************************************/
 
-/********************************************************************
+/****************************************************************************
  * Included Files
- ********************************************************************/
+ ****************************************************************************/
 
 #include <nuttx/config.h>
 
-/********************************************************************
+/****************************************************************************
  * Definitions
- ********************************************************************/
+ ****************************************************************************/
 
-/********************************************************************
+/****************************************************************************
  * Global Data
- ********************************************************************/
+ ****************************************************************************/
 
-/********************************************************************
+/****************************************************************************
  * Assembly Macros
- ********************************************************************/
+ ****************************************************************************/
 
-/********************************************************************
+/****************************************************************************
  * Name: _vector_start
  *
  * Description:
  *   Vector initialization block
- ********************************************************************/
+ ****************************************************************************/
 
 	.globl	_vector_start
 

arch/arm/src/c5471/c5471_irq.c

@@ -1,7 +1,7 @@
-/************************************************************
- * c5471/c5471_irq.c
+/****************************************************************************
+ * arch/arm/src/c5471/c5471_irq.c
  *
- *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -14,7 +14,7 @@
  *    notice, this list of conditions and the following disclaimer in
  *    the documentation and/or other materials provided with the
  *    distribution.
- * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ * 3. Neither the name NuttX nor the names of its contributors may be
  *    used to endorse or promote products derived from this software
  *    without specific prior written permission.
  *
@@ -31,35 +31,38 @@
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
- ************************************************************/
+ ****************************************************************************/
 
-/************************************************************
+/****************************************************************************
  * Included Files
- ************************************************************/
+ ****************************************************************************/
 
 #include <nuttx/config.h>
 #include <sys/types.h>
+
 #include <nuttx/irq.h>
+
+#include "arm.h"
 #include "up_arch.h"
 #include "os_internal.h"
 #include "up_internal.h"
 
-/************************************************************
+/****************************************************************************
  * Definitions
- ************************************************************/
+ ****************************************************************************/
 
 #define ILR_EDGESENSITIVE 0x00000020
 #define ILR_PRIORITY      0x0000001E
 
-/************************************************************
+/****************************************************************************
  * Public Data
- ************************************************************/
+ ****************************************************************************/
 
 uint32 *current_regs;
 
-/************************************************************
+/****************************************************************************
  * Private Data
- ************************************************************/
+ ****************************************************************************/
 
 /* The value of _vflashstart is defined in ld.script.  It
  * could be hard-coded because we know that correct IRAM
@@ -87,11 +90,11 @@ static up_vector_t g_vectorinittab[] =
 };
 #define NVECTORS ((sizeof(g_vectorinittab)) / sizeof(up_vector_t))
 
-/************************************************************
+/****************************************************************************
  * Private Functions
- ************************************************************/
+ ****************************************************************************/
 
-/************************************************************
+/****************************************************************************
  * Name: up_ackirq
  *
  * Description:
@@ -100,7 +103,7 @@ static up_vector_t g_vectorinittab[] =
  *   output. Clear source IRQ register. Enables a new IRQ
  *   generation. Reset by internal logic.
  *
- ************************************************************/
+ ****************************************************************************/
 
 static inline void up_ackirq(unsigned int irq)
 {
@@ -109,7 +112,7 @@ static inline void up_ackirq(unsigned int irq)
   putreg32(reg | 0x00000001, INT_CTRL_REG); /* write the NEW_IRQ_AGR bit. */
 }
 
-/************************************************************
+/****************************************************************************
  * Name: up_ackfiq
  *
  * Description:
@@ -118,7 +121,7 @@ static inline void up_ackirq(unsigned int irq)
  *   output. Clear source FIQ register. Enables a new FIQ
  *   generation. Reset by internal logic.
  *
- ************************************************************/
+ ****************************************************************************/
 
 static inline void up_ackfiq(unsigned int irq)
 {
@@ -127,9 +130,9 @@ static inline void up_ackfiq(unsigned int irq)
   putreg32(reg | 0x00000002, INT_CTRL_REG); /* write the NEW_FIQ_AGR bit. */
 }
 
-/************************************************************
+/****************************************************************************
  * Name: up_vectorinitialize
- ************************************************************/
+ ****************************************************************************/
 
 static inline void up_vectorinitialize(void)
 {
@@ -143,13 +146,13 @@ static inline void up_vectorinitialize(void)
     }
 }
 
-/************************************************************
- * Public Funtions
- ************************************************************/
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
 
-/************************************************************
+/****************************************************************************
  * Name: up_irqinitialize
- ************************************************************/
+ ****************************************************************************/
 
 void up_irqinitialize(void)
 {
@@ -182,13 +185,13 @@ void up_irqinitialize(void)
 #endif
 }
 
-/************************************************************
+/****************************************************************************
  * Name: up_disable_irq
  *
  * Description:
  *   Disable the IRQ specified by 'irq'
  *
- ************************************************************/
+ ****************************************************************************/
 
 void up_disable_irq(int irq)
 {
@@ -199,13 +202,13 @@ void up_disable_irq(int irq)
     }
 }
 
-/************************************************************
+/****************************************************************************
  * Name: up_enable_irq
  *
  * Description:
  *   Enable the IRQ specified by 'irq'
  *
- ************************************************************/
+ ****************************************************************************/
 
 void up_enable_irq(int irq)
 {
@@ -216,13 +219,13 @@ void up_enable_irq(int irq)
     }
 }
 
-/************************************************************
+/****************************************************************************
  * Name: up_maskack_irq
  *
  * Description:
  *   Mask the IRQ and acknowledge it
  *
- ************************************************************/
+ ****************************************************************************/
 
 void up_maskack_irq(int irq)
 {

arch/arm/src/c5471/c5471_vectors.S

@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/src/c5471/c5471_vectors.S
  *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -39,6 +39,8 @@
 
 #include <nuttx/config.h>
 #include <nuttx/irq.h>
+
+#include "arm.h"
 #include "up_arch.h"
 
 /************************************************************************************

arch/arm/src/common/up_arch.h

@@ -45,7 +45,6 @@
 # include <sys/types.h>
 #endif
 
-#include "arm.h"
 #include <arch/board/board.h>
 #include "chip.h"
 
@@ -82,11 +81,28 @@ static inline void putreg16(uint16 val, unsigned int addr)
  __asm__ __volatile__("\tstrh %0, [%1]\n\t": : "r"(val), "r"(addr));
 }
 
-/* Most DM320 registers are 16-bits wide */
-
-#define getreg(a)   getreg16(a)
-#define putreg(v,a) putreg16(v,a)
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
 
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
 #endif
 
+/* Atomic modification of registers */
+
+EXTERN void modifyreg8(unsigned int addr, ubyte clearbits, ubyte setbits);
+EXTERN void modifyreg16(unsigned int addr, uint16 clearbits, uint16 setbits);
+EXTERN void modifyreg32(unsigned int addr, uint32 clearbits, uint32 setbits);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
 #endif  /* ___ARCH_ARM_SRC_COMMON_UP_ARCH_H */

arch/arm/src/common/up_blocktask.c

@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/common/up_blocktask.c
  *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -39,9 +39,12 @@
 
 #include <nuttx/config.h>
 #include <sys/types.h>
+
 #include <sched.h>
 #include <debug.h>
+
 #include <nuttx/arch.h>
+
 #include "os_internal.h"
 #include "up_internal.h"
 
@@ -129,7 +132,7 @@ void up_block_task(_TCB *tcb, tstate_t task_state)
                * Just copy the current_regs into the OLD rtcb.
                */
 
-               up_copystate(rtcb->xcp.regs, current_regs);
+               up_savestate(rtcb->xcp.regs);
 
               /* Restore the exception context of the rtcb at the (new) head 
                * of the g_readytorun task list.
@@ -139,7 +142,7 @@ void up_block_task(_TCB *tcb, tstate_t task_state)
 
               /* Then switch contexts */
 
-              up_copystate(current_regs, rtcb->xcp.regs);
+              up_restorestate(rtcb->xcp.regs);
             }
 
           /* Copy the user C context into the TCB at the (old) head of the

arch/arm/src/common/up_exit.c

@@ -1,7 +1,7 @@
 /****************************************************************************
  * common/up_exit.c
  *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -42,6 +42,7 @@
 #include <sched.h>
 #include <debug.h>
 #include <nuttx/arch.h>
+
 #include "os_internal.h"
 #include "up_internal.h"
 

arch/arm/src/common/up_initialize.c

@@ -52,10 +52,6 @@
  * Definitions
  ****************************************************************************/
 
-/* Define to enable timing loop calibration */
-
-#undef CONFIG_ARM_CALIBRATION
-
 /****************************************************************************
  * Private Types
  ****************************************************************************/
@@ -74,16 +70,16 @@
  *
  ****************************************************************************/
 
-#if defined(CONFIG_ARM_CALIBRATION) & defined(CONFIG_DEBUG)
+#if defined(CONFIG_ARCH_CALIBRATION) && defined(CONFIG_DEBUG)
 static void up_calibratedelay(void)
 {
   int i;
-  slldbg("Beginning 100s delay\n");
+  lldbg("Beginning 100s delay\n");
   for (i = 0; i < 100; i++)
     {
       up_mdelay(1000);
     }
-  slldbg("End 100s delay\n");
+  lldbg("End 100s delay\n");
 }
 #else
 # define up_calibratedelay()

arch/arm/src/common/up_internal.h

@@ -1,7 +1,7 @@
 /****************************************************************************
  * common/up_internal.h
  *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -71,6 +71,20 @@
 # define CONFIG_ARCH_INTERRUPTSTACK 0
 #endif
 
+/* Macros to handle saving and restore interrupt state.  In the current ARM
+ * model, the state is always copied to and from the stack and TCB.  In the
+ * Cortex-M3 model, the state is copied from the stack to the TCB, but only
+ * a referenced is passed to get the the state from the TCB.
+ */
+
+#ifdef CONFIG_ARCH_CORTEXM3
+#  define up_savestate(regs)    up_copystate(regs, current_regs)
+#  define up_restorestate(regs) (current_regs = regs)
+#else
+#  define up_savestate(regs)    up_copystate(regs, current_regs)
+#  define up_restorestate(regs) up_copystate(current_regs, regs)
+#endif
+
 /****************************************************************************
  * Public Types
  ****************************************************************************/
@@ -104,6 +118,26 @@ extern uint32 g_heapbase;
 #if CONFIG_ARCH_INTERRUPTSTACK > 3
 extern uint32 g_userstack;
 #endif
+
+/* These 'addresses' of these values are setup by the linker script.  They are
+ * not actual uint32 storage locations! They are only used meaningfully in the
+ * following way:
+ *
+ *  - The linker script defines, for example, the symbol_sdata.
+ *  - The declareion extern uint32 _sdata; makes C happy.  C will believe
+ *    that the value _sdata is the address of a uint32 variable _data (it is
+ *    not!).
+ *  - We can recoved the linker value then by simply taking the address of
+ *    of _data.  like:  uint32 *pdata = &_sdata;
+ */
+
+extern uint32 _stext;           /* Start of .text */
+extern uint32 _etext;           /* End_1 of .text + .rodata */
+extern const uint32 _eronly;    /* End+1 of read only section (.text + .rodata) */
+extern uint32 _sdata;           /* Start of .data */
+extern uint32 _edata;           /* End+1 of .data */
+extern uint32 _sbss;            /* Start of .bss */
+extern uint32 _ebss;            /* End+1 of .bss */
 #endif
 
 /****************************************************************************
@@ -120,21 +154,28 @@ extern uint32 g_userstack;
 
 extern void up_boot(void);
 extern void up_copystate(uint32 *dest, uint32 *src);
-extern void up_dataabort(uint32 *regs);
 extern void up_decodeirq(uint32 *regs);
-extern void up_doirq(int irq, uint32 *regs);
 extern void up_fullcontextrestore(uint32 *regs) __attribute__ ((noreturn));
 extern void up_irqinitialize(void);
-extern void up_prefetchabort(uint32 *regs);
 extern int  up_saveusercontext(uint32 *regs);
 extern void up_sigdeliver(void);
-extern void up_syscall(uint32 *regs);
 extern int  up_timerisr(int irq, uint32 *regs);
-extern void up_undefinedinsn(uint32 *regs);
 extern void up_lowputc(char ch);
 extern void up_puts(const char *str);
 extern void up_lowputs(const char *str);
 
+#ifdef CONFIG_ARCH_CORTEXM3
+extern uint32 *up_doirq(int irq, uint32 *regs);
+extern int  up_svcall(int irq, FAR void *context);
+extern int  up_hardfault(int irq, FAR void *context);
+#else
+extern void up_doirq(int irq, uint32 *regs);
+extern void up_dataabort(uint32 *regs);
+extern void up_prefetchabort(uint32 *regs);
+extern void up_syscall(uint32 *regs);
+extern void up_undefinedinsn(uint32 *regs);
+#endif
+
 /* Defined in up_vectors.S */
 
 extern void up_vectorundefinsn(void);

arch/arm/src/common/up_modifyreg16.c

@@ -0,0 +1,85 @@
+/****************************************************************************
+ * arch/arm/src/common/up_modifyreg16.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+#include <nuttx/arch.h>
+
+#include "up_arch.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: modifyreg16
+ *
+ * Description:
+ *   Atomically modify the specified bits in a memory mapped register
+ *
+ ****************************************************************************/
+
+void modifyreg16(unsigned int addr, uint16 clearbits, uint16 setbits)
+{
+  irqstate_t flags;
+  uint16     regval;
+
+  flags   = irqsave();
+  regval  = getreg16(addr);
+  regval &= ~clearbits;
+  regval |= setbits;
+  putreg16(regval, addr);
+  irqrestore(flags);
+}

arch/arm/src/common/up_modifyreg32.c

@@ -0,0 +1,85 @@
+/****************************************************************************
+ * arch/arm/src/common/up_modifyreg32.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+#include <nuttx/arch.h>
+
+#include "up_arch.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: modifyreg32
+ *
+ * Description:
+ *   Atomically modify the specified bits in a memory mapped register
+ *
+ ****************************************************************************/
+
+void modifyreg32(unsigned int addr, uint32 clearbits, uint32 setbits)
+{
+  irqstate_t flags;
+  uint32     regval;
+
+  flags   = irqsave();
+  regval  = getreg32(addr);
+  regval &= ~clearbits;
+  regval |= setbits;
+  putreg32(regval, addr);
+  irqrestore(flags);
+}

arch/arm/src/common/up_modifyreg8.c

@@ -0,0 +1,85 @@
+/****************************************************************************
+ * arch/arm/src/common/up_modifyreg8.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+#include <nuttx/arch.h>
+
+#include "up_arch.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: modifyreg8
+ *
+ * Description:
+ *   Atomically modify the specified bits in a memory mapped register
+ *
+ ****************************************************************************/
+
+void modifyreg8(unsigned int addr, ubyte clearbits, ubyte setbits)
+{
+  irqstate_t flags;
+  ubyte      regval;
+
+  flags   = irqsave();
+  regval  = getreg8(addr);
+  regval &= ~clearbits;
+  regval |= setbits;
+  putreg8(regval, addr);
+  irqrestore(flags);
+}

arch/arm/src/common/up_releasepending.c

@@ -1,7 +1,7 @@
 /****************************************************************************
  *  arch/arm/src/common/up_releasepending.c
  *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -94,7 +94,7 @@ void up_release_pending(void)
            * Just copy the current_regs into the OLD rtcb.
            */
 
-           up_copystate(rtcb->xcp.regs, current_regs);
+           up_savestate(rtcb->xcp.regs);
 
           /* Restore the exception context of the rtcb at the (new) head 
            * of the g_readytorun task list.
@@ -105,7 +105,7 @@ void up_release_pending(void)
 
           /* Then switch contexts */
 
-          up_copystate(current_regs, rtcb->xcp.regs);
+          up_restorestate(rtcb->xcp.regs);
         }
 
       /* Copy the exception context into the TCB of the task that

arch/arm/src/common/up_reprioritizertr.c

@@ -142,7 +142,7 @@ void up_reprioritize_rtr(_TCB *tcb, ubyte priority)
                * Just copy the current_regs into the OLD rtcb.
                */
 
-               up_copystate(rtcb->xcp.regs, current_regs);
+               up_savestate(rtcb->xcp.regs);
 
               /* Restore the exception context of the rtcb at the (new) head 
                * of the g_readytorun task list.
@@ -153,7 +153,7 @@ void up_reprioritize_rtr(_TCB *tcb, ubyte priority)
 
               /* Then switch contexts */
 
-              up_copystate(current_regs, rtcb->xcp.regs);
+              up_restorestate(rtcb->xcp.regs);
             }
 
           /* Copy the exception context into the TCB at the (old) head of the

arch/arm/src/common/up_unblocktask.c

@@ -1,7 +1,7 @@
 /****************************************************************************
  *  arch/arm/src/common/up_unblocktask.c
  *
- *   Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -121,7 +121,7 @@ void up_unblock_task(_TCB *tcb)
                * Just copy the current_regs into the OLD rtcb.
                */
 
-               up_copystate(rtcb->xcp.regs, current_regs);
+               up_savestate(rtcb->xcp.regs);
 
               /* Restore the exception context of the rtcb at the (new) head 
                * of the g_readytorun task list.
@@ -131,7 +131,7 @@ void up_unblock_task(_TCB *tcb)
 
               /* Then switch contexts */
 
-              up_copystate(current_regs, rtcb->xcp.regs);
+              up_restorestate(rtcb->xcp.regs);
             }
 
           /* We are not in an interrupt handler.  Copy the user C context

arch/arm/src/cortexm3/nvic.h

@@ -0,0 +1,489 @@
+/************************************************************************************
+ * arch/arm/src/cortexm3/nvic.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_COMMON_CORTEXM3_NVIC_H
+#define __ARCH_ARM_SRC_COMMON_CORTEXM3_NVIC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* NVIC base address ****************************************************************/
+
+#define CORTEXM3_NVIC_BASE              0xe000e000
+
+/* NVIC register offsets ************************************************************/
+
+#define NVIC_INTCTRL_TYPE_OFFSET        0x0004 /* Interrupt controller type */
+#define NVIC_SYSTICK_CTRL_OFFSET        0x0010 /* SysTick control and status register */
+#define NVIC_SYSTICK_RELOAD_OFFSET      0x0014 /* SysTick reload value register */
+#define NVIC_SYSTICK_CURRENT_OFFSET     0x0018 /* SysTick current value register */
+#define NVIC_SYSTICK_CALIB_OFFSET       0x001c /* SysTick calibration value register */
+
+#define NVIC_IRQ_ENABLE_OFFSET(n)       (0x0100 + 4*((n) >> 5))
+#define NVIC_IRQ0_31_ENABLE_OFFSET      0x0100 /* IRQ 0-31 set enable register */
+#define NVIC_IRQ32_63_ENABLE_OFFSET     0x0104 /* IRQ 32-63 set enable register */
+#define NVIC_IRQ64_95_ENABLE_OFFSET     0x0108 /* IRQ 64-95 set enable register */
+#define NVIC_IRQ96_127_ENABLE_OFFSET    0x010c /* IRQ 96-127 set enable register */
+#define NVIC_IRQ128_159_ENABLE_OFFSET   0x0110 /* IRQ 128-159 set enable register */
+#define NVIC_IRQ160_191_ENABLE_OFFSET   0x0114 /* IRQ 160-191 set enable register */
+#define NVIC_IRQ192_223_ENABLE_OFFSET   0x0118 /* IRQ 192-223 set enable register */
+#define NVIC_IRQ224_239_ENABLE_OFFSET   0x011c /* IRQ 224-239 set enable register */
+
+#define NVIC_IRQ_CLEAR_OFFSET(n)        (0x0180 + 4*((n) >> 5))
+#define NVIC_IRQ0_31_CLEAR_OFFSET       0x0180 /* IRQ 0-31 clear enable register */
+#define NVIC_IRQ32_63_CLEAR_OFFSET      0x0184 /* IRQ 32-63 clear enable register */
+#define NVIC_IRQ64_95_CLEAR_OFFSET      0x0188 /* IRQ 64-95 clear enable register */
+#define NVIC_IRQ96_127_CLEAR_OFFSET     0x018c /* IRQ 96-127 clear enable register */
+#define NVIC_IRQ128_159_CLEAR_OFFSET    0x0190 /* IRQ 128-159 clear enable register */
+#define NVIC_IRQ160_191_CLEAR_OFFSET    0x0194 /* IRQ 160-191 clear enable register */
+#define NVIC_IRQ192_223_CLEAR_OFFSET    0x0198 /* IRQ 192-223 clear enable register */
+#define NVIC_IRQ224_239_CLEAR_OFFSET    0x019c /* IRQ 224-2391 clear enable register */
+
+#define NVIC_IRQ_PEND_OFFSET(n)         (0x0200 + 4*((n) >> 5))
+#define NVIC_IRQ0_31_PEND_OFFSET        0x0200 /* IRQ 0-31 set pending register */
+#define NVIC_IRQ32_63_PEND_OFFSET       0x0204 /* IRQ 32-63 set pending register */
+#define NVIC_IRQ64_95_PEND_OFFSET       0x0208 /* IRQ 64-95 set pending register */
+#define NVIC_IRQ96_127_PEND_OFFSET      0x020c /* IRQ 96-127 set pending register */
+#define NVIC_IRQ128_159_PEND_OFFSET     0x0210 /* IRQ 128-159 set pending register */
+#define NVIC_IRQ160_191_PEND_OFFSET     0x0214 /* IRQ 160-191 set pending register */
+#define NVIC_IRQ192_223_PEND_OFFSET     0x0218 /* IRQ 192-2231 set pending register */
+#define NVIC_IRQ224_239_PEND_OFFSET     0x021c /* IRQ 224-2391 set pending register */
+
+#define NVIC_IRQ_CLRPEND_OFFSET(n)      (0x0280 + 4*((n) >> 5))
+#define NVIC_IRQ0_31_CLRPEND_OFFSET     0x0280 /* IRQ 0-31 clear pending register */
+#define NVIC_IRQ32_63_CLRPEND_OFFSET    0x0284 /* IRQ 32-63 clear pending register */
+#define NVIC_IRQ64_95_CLRPEND_OFFSET    0x0288 /* IRQ 64-95 clear pending register */
+#define NVIC_IRQ96_127_CLRPEND_OFFSET   0x028c /* IRQ 96-127 clear pending register */
+#define NVIC_IRQ128_159_CLRPEND_OFFSET  0x0290 /* IRQ 128-159 clear pending register */
+#define NVIC_IRQ160_191_CLRPEND_OFFSET  0x0294 /* IRQ 160-191 clear pending register */
+#define NVIC_IRQ192_223_CLRPEND_OFFSET  0x0298 /* IRQ 192-223 clear pending register */
+#define NVIC_IRQ224_239_CLRPEND_OFFSET  0x029c /* IRQ 224-239 clear pending register */
+
+#define NVIC_IRQ_ACTIVE_OFFSET(n)       (0x0300 + 4*((n) >> 5))
+#define NVIC_IRQ0_31_ACTIVE_OFFSET      0x0300 /* IRQ 0-31 active bit register */
+#define NVIC_IRQ32_63_ACTIVE_OFFSET     0x0304 /* IRQ 32-63 active bit register */
+#define NVIC_IRQ64_95_ACTIVE_OFFSET     0x0308 /* IRQ 64-95 active bit register */
+#define NVIC_IRQ96_127_ACTIVE_OFFSET    0x030c /* IRQ 96-127 active bit register */
+#define NVIC_IRQ128_159_ACTIVE_OFFSET   0x0310 /* IRQ 128-159 active bit register */
+#define NVIC_IRQ160_191_ACTIVE_OFFSET   0x0314 /* IRQ 160-191 active bit register */
+#define NVIC_IRQ192_223_ACTIVE_OFFSET   0x0318 /* IRQ 192-223 active bit register */
+#define NVIC_IRQ224_239_ACTIVE_OFFSET   0x031c /* IRQ 224-239 active bit register */
+
+#define NVIC_IRQ_PRIORITY_OFFSET(n)     (0x0400 + 4*((n) >> 2))
+#define NVIC_IRQ0_3_PRIORITY_OFFSET     0x0400 /* IRQ 0-3 priority register */
+#define NVIC_IRQ4_7_PRIORITY_OFFSET     0x0404 /* IRQ 4-7 priority register */
+#define NVIC_IRQ8_11_PRIORITY_OFFSET    0x0408 /* IRQ 8-11 priority register */
+#define NVIC_IRQ12_15_PRIORITY_OFFSET   0x040c /* IRQ 12-15 priority register */
+#define NVIC_IRQ16_19_PRIORITY_OFFSET   0x0410 /* IRQ 16-19 priority register */
+#define NVIC_IRQ20_23_PRIORITY_OFFSET   0x0414 /* IRQ 20-23 priority register */
+#define NVIC_IRQ24_27_PRIORITY_OFFSET   0x0418 /* IRQ 24-29 priority register */
+#define NVIC_IRQ28_31_PRIORITY_OFFSET   0x041c /* IRQ 28-31 priority register */
+#define NVIC_IRQ32_35_PRIORITY_OFFSET   0x0420 /* IRQ 32-35 priority register */
+#define NVIC_IRQ36_39_PRIORITY_OFFSET   0x0424 /* IRQ 36-39 priority register */
+#define NVIC_IRQ40_43_PRIORITY_OFFSET   0x0428 /* IRQ 40-43 priority register */
+#define NVIC_IRQ44_47_PRIORITY_OFFSET   0x042c /* IRQ 44-47 priority register */
+#define NVIC_IRQ48_51_PRIORITY_OFFSET   0x0430 /* IRQ 48-51 priority register */
+#define NVIC_IRQ52_55_PRIORITY_OFFSET   0x0434 /* IRQ 52-55 priority register */
+#define NVIC_IRQ56_59_PRIORITY_OFFSET   0x0438 /* IRQ 56-59 priority register */
+#define NVIC_IRQ60_63_PRIORITY_OFFSET   0x043c /* IRQ 60-63 priority register */
+#define NVIC_IRQ64_67_PRIORITY_OFFSET   0x0440 /* IRQ 64-67 priority register */
+#define NVIC_IRQ68_71_PRIORITY_OFFSET   0x0444 /* IRQ 68-71 priority register */
+#define NVIC_IRQ72_75_PRIORITY_OFFSET   0x0448 /* IRQ 72-75 priority register */
+#define NVIC_IRQ76_79_PRIORITY_OFFSET   0x044c /* IRQ 76-79 priority register */
+#define NVIC_IRQ80_83_PRIORITY_OFFSET   0x0450 /* IRQ 80-83 priority register */
+#define NVIC_IRQ84_87_PRIORITY_OFFSET   0x0454 /* IRQ 84-87 priority register */
+#define NVIC_IRQ88_91_PRIORITY_OFFSET   0x0458 /* IRQ 88-91 priority register */
+#define NVIC_IRQ92_95_PRIORITY_OFFSET   0x045c /* IRQ 92-95 priority register */
+#define NVIC_IRQ96_99_PRIORITY_OFFSET   0x0460 /* IRQ 96-99 priority register */
+#define NVIC_IRQ100_103_PRIORITY_OFFSET 0x0464 /* IRQ 100-103 priority register */
+#define NVIC_IRQ104_107_PRIORITY_OFFSET 0x0468 /* IRQ 104-107 priority register */
+#define NVIC_IRQ108_111_PRIORITY_OFFSET 0x046c /* IRQ 108-111 priority register */
+#define NVIC_IRQ112_115_PRIORITY_OFFSET 0x0470 /* IRQ 112-115 priority register */
+#define NVIC_IRQ116_119_PRIORITY_OFFSET 0x0474 /* IRQ 116-119 priority register */
+#define NVIC_IRQ120_123_PRIORITY_OFFSET 0x0478 /* IRQ 120-123 priority register */
+#define NVIC_IRQ124_127_PRIORITY_OFFSET 0x047c /* IRQ 124-127 priority register */
+#define NVIC_IRQ128_131_PRIORITY_OFFSET 0x0480 /* IRQ 128-131 priority register */
+#define NVIC_IRQ132_135_PRIORITY_OFFSET 0x0484 /* IRQ 132-135 priority register */
+#define NVIC_IRQ136_139_PRIORITY_OFFSET 0x0488 /* IRQ 136-139 priority register */
+#define NVIC_IRQ140_143_PRIORITY_OFFSET 0x048c /* IRQ 140-143 priority register */
+#define NVIC_IRQ144_147_PRIORITY_OFFSET 0x0490 /* IRQ 144-147 priority register */
+#define NVIC_IRQ148_151_PRIORITY_OFFSET 0x0494 /* IRQ 148-151 priority register */
+#define NVIC_IRQ152_155_PRIORITY_OFFSET 0x0498 /* IRQ 152-155 priority register */
+#define NVIC_IRQ156_159_PRIORITY_OFFSET 0x049c /* IRQ 156-159 priority register */
+#define NVIC_IRQ160_163_PRIORITY_OFFSET 0x04a0 /* IRQ 160-163 priority register */
+#define NVIC_IRQ164_167_PRIORITY_OFFSET 0x04a4 /* IRQ 164-167 priority register */
+#define NVIC_IRQ168_171_PRIORITY_OFFSET 0x04a8 /* IRQ 168-171 priority register */
+#define NVIC_IRQ172_175_PRIORITY_OFFSET 0x04ac /* IRQ 172-175 priority register */
+#define NVIC_IRQ176_179_PRIORITY_OFFSET 0x04b0 /* IRQ 176-179 priority register */
+#define NVIC_IRQ180_183_PRIORITY_OFFSET 0x04b4 /* IRQ 180-183 priority register */
+#define NVIC_IRQ184_187_PRIORITY_OFFSET 0x04b8 /* IRQ 184-187 priority register */
+#define NVIC_IRQ188_191_PRIORITY_OFFSET 0x04bc /* IRQ 188-191 priority register */
+#define NVIC_IRQ192_195_PRIORITY_OFFSET 0x04c0 /* IRQ 192-195 priority register */
+#define NVIC_IRQ196_199_PRIORITY_OFFSET 0x04c4 /* IRQ 196-199 priority register */
+#define NVIC_IRQ200_203_PRIORITY_OFFSET 0x04c8 /* IRQ 200-203 priority register */
+#define NVIC_IRQ204_207_PRIORITY_OFFSET 0x04cc /* IRQ 204-207 priority register */
+#define NVIC_IRQ208_211_PRIORITY_OFFSET 0x04d0 /* IRQ 208-211 priority register */
+#define NVIC_IRQ212_215_PRIORITY_OFFSET 0x04d4 /* IRQ 212-215 priority register */
+#define NVIC_IRQ216_219_PRIORITY_OFFSET 0x04d8 /* IRQ 216-219 priority register */
+#define NVIC_IRQ220_223_PRIORITY_OFFSET 0x04dc /* IRQ 220-223 priority register */
+#define NVIC_IRQ224_227_PRIORITY_OFFSET 0x04e0 /* IRQ 224-227 priority register */
+#define NVIC_IRQ228_231_PRIORITY_OFFSET 0x04e4 /* IRQ 228-231 priority register */
+#define NVIC_IRQ232_235_PRIORITY_OFFSET 0x04e8 /* IRQ 232-235 priority register */
+#define NVIC_IRQ236_239_PRIORITY_OFFSET 0x04ec /* IRQ 236-239 priority register */
+
+#define NVIC_CPUID_BASE_OFFSET          0x0d00 /* CPUID base register */
+#define NVIC_INTCTRL_OFFSET             0x0d04 /* Interrupt control state register */
+#define NVIC_VECTAB_OFFSET              0x0d08 /* Vector table offset register */
+#define NVIC_AIRC_OFFSET                0x0d0c /* Application interrupt/reset contol registr */
+#define NVIC_SYSCON_OFFSET              0x0d10 /* System control register */
+#define NVIC_CFGCON_OFFSET              0x0d14 /* Configuration control register */
+#define NVIC_SYSH_PRIORITY_OFFSET(n)    (0x0d14 + 4*((n) >> 2))
+#define NVIC_SYSH4_7_PRIORITY_OFFSET    0x0d18 /* System handlers 4-7 priority register */
+#define NVIC_SYSH8_11_PRIORITY_OFFSET   0x0d1c /* System handler 8-11 priority register */
+#define NVIC_SYSH12_15_PRIORITY_OFFSET  0x0d20 /* System handler 12-15 priority register */
+#define NVIC_SYSHCON_OFFSET             0x0d24 /* System handler control and state register */
+#define NVIC_CFAULTS_OFFSET             0x0d28 /* Configurable fault status register */
+#define NVIC_HFAULTS_OFFSET             0x0d2c /* Hard fault status register */
+#define NVIC_DFAULTS_OFFSET             0x0d30 /* Debug fault status register */
+#define NVIC_MEMMANAGE_ADDR_OFFSET      0x0d34 /* Mem manage address register */
+#define NVIC_BFAULT_ADDR_OFFSET         0x0d38 /* Bus fault address register */
+#define NVIC_AFAULTS_OFFSET             0x0d3c /* Auxiliary fault status register */
+#define NVIC_PFR0_OFFSET                0x0d40 /* Processor feature register 0 */
+#define NVIC_PFR1_OFFSET                0x0d44 /* Processor feature register 1 */
+#define NVIC_DFR0_OFFSET                0x0d48 /* Debug feature register 0 */
+#define NVIC_AFR0_OFFSET                0x0d4c /* Auxiliary feature register 0 */
+#define NVIC_MMFR0_OFFSET               0x0d50 /* Memory model feature register 0 */
+#define NVIC_MMFR1_OFFSET               0x0d54 /* Memory model feature register 1 */
+#define NVIC_MMFR2_OFFSET               0x0d58 /* Memory model feature register 2 */
+#define NVIC_MMFR3_OFFSET               0x0d5c /* Memory model feature register 3 */
+#define NVIC_ISAR0_OFFSET               0x0d60 /* ISA feature register 0 */
+#define NVIC_ISAR1_OFFSET               0x0d64 /* ISA feature register 1 */
+#define NVIC_ISAR2_OFFSET               0x0d68 /* ISA feature register 2 */
+#define NVIC_ISAR3_OFFSET               0x0d6c /* ISA feature register 3 */
+#define NVIC_ISAR4_OFFSET               0x0d70 /* ISA feature register 4 */
+#define NVIC_STIR_OFFSET                0x0f00 /* Software trigger interrupt register */
+#define NVIC_PID4_OFFSET                0x0fd0 /* Peripheral identification register (PID4) */
+#define NVIC_PID5_OFFSET                0x0fd4 /* Peripheral identification register (PID5) */
+#define NVIC_PID6_OFFSET                0x0fd8 /* Peripheral identification register (PID6) */
+#define NVIC_PID7_OFFSET                0x0fdc /* Peripheral identification register (PID7) */
+#define NVIC_PID0_OFFSET                0x0fe0 /* Peripheral identification register bits 7:0 (PID0) */
+#define NVIC_PID1_OFFSET                0x0fe4 /* Peripheral identification register bits 15:8 (PID1) */
+#define NVIC_PID2_OFFSET                0x0fe8 /* Peripheral identification register bits 23:16 (PID2) */
+#define NVIC_PID3_OFFSET                0x0fec /* Peripheral identification register bits 23:16 (PID3) */
+#define NVIC_CID0_OFFSET                0x0ff0 /* Component identification register bits 7:0 (CID0) */
+#define NVIC_CID1_OFFSET                0x0ff4 /* Component identification register bits 15:8 (CID0) */
+#define NVIC_CID2_OFFSET                0x0ff8 /* Component identification register bits 23:16 (CID0) */
+#define NVIC_CID3_OFFSET                0x0ffc /* Component identification register bits 23:16 (CID0) */
+
+/* NVIC register addresses **********************************************************/
+
+#define NVIC_INTCTRL_TYPE             (CORTEXM3_NVIC_BASE + NVIC_INTCTRL_TYPE_OFFSET)
+#define NVIC_SYSTICK_CTRL             (CORTEXM3_NVIC_BASE + NVIC_SYSTICK_CTRL_OFFSET)
+#define NVIC_SYSTICK_RELOAD           (CORTEXM3_NVIC_BASE + NVIC_SYSTICK_RELOAD_OFFSET)
+#define NVIC_SYSTICK_CURRENT          (CORTEXM3_NVIC_BASE + NVIC_SYSTICK_CURRENT_OFFSET)
+#define NVIC_SYSTICK_CALIB            (CORTEXM3_NVIC_BASE + NVIC_SYSTICK_CALIB_OFFSET)
+
+#define NVIC_IRQ_ENABLE(n)            (CORTEXM3_NVIC_BASE + NVIC_IRQ_ENABLE_OFFSET(n))
+#define NVIC_IRQ0_31_ENABLE           (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_ENABLE_OFFSET)
+#define NVIC_IRQ32_63_ENABLE          (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_ENABLE_OFFSET)
+#define NVIC_IRQ64_95_ENABLE          (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_ENABLE_OFFSET)
+#define NVIC_IRQ96_127_ENABLE         (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_ENABLE_OFFSET)
+#define NVIC_IRQ128_159_ENABLE        (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_ENABLE_OFFSET)
+#define NVIC_IRQ160_191_ENABLE        (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_ENABLE_OFFSET)
+#define NVIC_IRQ192_223_ENABLE        (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_ENABLE_OFFSET)
+#define NVIC_IRQ224_239_ENABLE        (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_ENABLE_OFFSET)
+
+#define NVIC_IRQ_CLEAR(n)             (CORTEXM3_NVIC_BASE + NVIC_IRQ_CLEAR_OFFSET(n))
+#define NVIC_IRQ0_31_CLEAR            (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_CLEAR_OFFSET)
+#define NVIC_IRQ32_63_CLEAR           (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_CLEAR_OFFSET)
+#define NVIC_IRQ64_95_CLEAR           (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_CLEAR_OFFSET)
+#define NVIC_IRQ96_127_CLEAR          (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_CLEAR_OFFSET)
+#define NVIC_IRQ128_159_CLEAR         (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_CLEAR_OFFSET)
+#define NVIC_IRQ160_191_CLEAR         (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_CLEAR_OFFSET)
+#define NVIC_IRQ192_223_CLEAR         (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_CLEAR_OFFSET)
+#define NVIC_IRQ224_239_CLEAR         (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_CLEAR_OFFSET)
+
+#define NVIC_IRQ_PEND(n)              (CORTEXM3_NVIC_BASE + NVIC_IRQ_PEND_OFFSET(n))
+#define NVIC_IRQ0_31_PEND             (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_PEND_OFFSET)
+#define NVIC_IRQ32_63_PEND            (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_PEND_OFFSET)
+#define NVIC_IRQ64_95_PEND            (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_PEND_OFFSET)
+#define NVIC_IRQ96_127_PEND           (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_PEND_OFFSET)
+#define NVIC_IRQ128_159_PEND          (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_PEND_OFFSET)
+#define NVIC_IRQ160_191_PEND          (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_PEND_OFFSET)
+#define NVIC_IRQ192_223_PEND          (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_PEND_OFFSET)
+#define NVIC_IRQ224_239_PEND          (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_PEND_OFFSET)
+
+#define NVIC_IRQ_CLRPEND(n)           (CORTEXM3_NVIC_BASE + NVIC_IRQ_CLRPEND_OFFSET(n))
+#define NVIC_IRQ0_31_CLRPEND          (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_CLRPEND_OFFSET)
+#define NVIC_IRQ32_63_CLRPEND         (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_CLRPEND_OFFSET)
+#define NVIC_IRQ64_95_CLRPEND         (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_CLRPEND_OFFSET)
+#define NVIC_IRQ96_127_CLRPEND        (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_CLRPEND_OFFSET)
+#define NVIC_IRQ128_159_CLRPEND       (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_CLRPEND_OFFSET)
+#define NVIC_IRQ160_191_CLRPEND       (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_CLRPEND_OFFSET)
+#define NVIC_IRQ192_223_CLRPEND       (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_CLRPEND_OFFSET)
+#define NVIC_IRQ224_239_CLRPEND       (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_CLRPEND_OFFSET)
+
+#define NVIC_IRQ_ACTIVE(n)            (CORTEXM3_NVIC_BASE + NVIC_IRQ_ACTIVE_OFFSET(n))
+#define NVIC_IRQ0_31_ACTIVE           (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_ACTIVE_OFFSET)
+#define NVIC_IRQ32_63_ACTIVE          (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_ACTIVE_OFFSET)
+#define NVIC_IRQ64_95_ACTIVE          (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_ACTIVE_OFFSET)
+#define NVIC_IRQ96_127_ACTIVE         (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_ACTIVE_OFFSET)
+#define NVIC_IRQ128_159_ACTIVE        (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_ACTIVE_OFFSET)
+#define NVIC_IRQ160_191_ACTIVE        (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_ACTIVE_OFFSET)
+#define NVIC_IRQ192_223_ACTIVE        (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_ACTIVE_OFFSET)
+#define NVIC_IRQ224_239_ACTIVE        (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_ACTIVE_OFFSET)
+
+#define NVIC_IRQ_PRIORITY(n)          (CORTEXM3_NVIC_BASE + NVIC_IRQ_PRIORITY_OFFSET(n))
+#define NVIC_IRQ0_3_PRIORITY          (CORTEXM3_NVIC_BASE + NVIC_IRQ0_3_PRIORITY_OFFSET)
+#define NVIC_IRQ4_7_PRIORITY          (CORTEXM3_NVIC_BASE + NVIC_IRQ4_7_PRIORITY_OFFSET)
+#define NVIC_IRQ8_11_PRIORITY         (CORTEXM3_NVIC_BASE + NVIC_IRQ8_11_PRIORITY_OFFSET)
+#define NVIC_IRQ12_15_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ12_15_PRIORITY_OFFSET)
+#define NVIC_IRQ16_19_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ16_19_PRIORITY_OFFSET)
+#define NVIC_IRQ20_23_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ20_23_PRIORITY_OFFSET)
+#define NVIC_IRQ24_27_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ24_27_PRIORITY_OFFSET)
+#define NVIC_IRQ28_31_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ28_31_PRIORITY_OFFSET)
+#define NVIC_IRQ32_35_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ32_35_PRIORITY_OFFSET)
+#define NVIC_IRQ36_39_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ36_39_PRIORITY_OFFSET)
+#define NVIC_IRQ40_43_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ40_43_PRIORITY_OFFSET)
+#define NVIC_IRQ44_47_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ44_47_PRIORITY_OFFSET)
+#define NVIC_IRQ48_51_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ48_51_PRIORITY_OFFSET)
+#define NVIC_IRQ52_55_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ52_55_PRIORITY_OFFSET)
+#define NVIC_IRQ56_59_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ56_59_PRIORITY_OFFSET)
+#define NVIC_IRQ60_63_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ60_63_PRIORITY_OFFSET)
+#define NVIC_IRQ64_67_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ64_67_PRIORITY_OFFSET)
+#define NVIC_IRQ68_71_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ68_71_PRIORITY_OFFSET)
+#define NVIC_IRQ72_75_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ72_75_PRIORITY_OFFSET)
+#define NVIC_IRQ76_79_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ76_79_PRIORITY_OFFSET)
+#define NVIC_IRQ80_83_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ80_83_PRIORITY_OFFSET)
+#define NVIC_IRQ84_87_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ84_87_PRIORITY_OFFSET)
+#define NVIC_IRQ88_91_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ88_91_PRIORITY_OFFSET)
+#define NVIC_IRQ92_95_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ92_95_PRIORITY_OFFSET)
+#define NVIC_IRQ96_99_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ96_99_PRIORITY_OFFSET)
+#define NVIC_IRQ100_103_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ100_103_PRIORITY_OFFSET)
+#define NVIC_IRQ104_107_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ104_107_PRIORITY_OFFSET)
+#define NVIC_IRQ108_111_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ108_111_PRIORITY_OFFSET)
+#define NVIC_IRQ112_115_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ112_115_PRIORITY_OFFSET)
+#define NVIC_IRQ116_119_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ116_119_PRIORITY_OFFSET)
+#define NVIC_IRQ120_123_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ120_123_PRIORITY_OFFSET)
+#define NVIC_IRQ124_127_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ124_127_PRIORITY_OFFSET)
+#define NVIC_IRQ128_131_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ128_131_PRIORITY_OFFSET)
+#define NVIC_IRQ132_135_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ132_135_PRIORITY_OFFSET)
+#define NVIC_IRQ136_139_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ136_139_PRIORITY_OFFSET)
+#define NVIC_IRQ140_143_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ140_143_PRIORITY_OFFSET)
+#define NVIC_IRQ144_147_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ144_147_PRIORITY_OFFSET)
+#define NVIC_IRQ148_151_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ148_151_PRIORITY_OFFSET)
+#define NVIC_IRQ152_155_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ152_155_PRIORITY_OFFSET)
+#define NVIC_IRQ156_159_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ156_159_PRIORITY_OFFSET)
+#define NVIC_IRQ160_163_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ160_163_PRIORITY_OFFSET)
+#define NVIC_IRQ164_167_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ164_167_PRIORITY_OFFSET)
+#define NVIC_IRQ168_171_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ168_171_PRIORITY_OFFSET)
+#define NVIC_IRQ172_175_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ172_175_PRIORITY_OFFSET)
+#define NVIC_IRQ176_179_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ176_179_PRIORITY_OFFSET)
+#define NVIC_IRQ180_183_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ180_183_PRIORITY_OFFSET)
+#define NVIC_IRQ184_187_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ184_187_PRIORITY_OFFSET)
+#define NVIC_IRQ188_191_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ188_191_PRIORITY_OFFSET)
+#define NVIC_IRQ192_195_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ192_195_PRIORITY_OFFSET)
+#define NVIC_IRQ196_199_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ196_199_PRIORITY_OFFSET)
+#define NVIC_IRQ200_203_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ200_203_PRIORITY_OFFSET)
+#define NVIC_IRQ204_207_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ204_207_PRIORITY_OFFSET)
+#define NVIC_IRQ208_211_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ208_211_PRIORITY_OFFSET)
+#define NVIC_IRQ212_215_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ212_215_PRIORITY_OFFSET)
+#define NVIC_IRQ216_219_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ216_219_PRIORITY_OFFSET)
+#define NVIC_IRQ220_223_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ220_223_PRIORITY_OFFSET)
+#define NVIC_IRQ224_227_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ224_227_PRIORITY_OFFSET)
+#define NVIC_IRQ228_231_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ228_231_PRIORITY_OFFSET)
+#define NVIC_IRQ232_235_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ232_235_PRIORITY_OFFSET)
+
+#define NVIC_CPUID_BASE               (CORTEXM3_NVIC_BASE + NVIC_CPUID_BASE_OFFSET)
+#define NVIC_INTCTRL                  (CORTEXM3_NVIC_BASE + NVIC_INTCTRL_OFFSET)
+#define NVIC_VECTAB                   (CORTEXM3_NVIC_BASE + NVIC_VECTAB_OFFSET)
+#define NVIC_AIRC                     (CORTEXM3_NVIC_BASE + NVIC_AIRC_OFFSET)
+#define NVIC_SYSCON                   (CORTEXM3_NVIC_BASE + NVIC_SYSCON_OFFSET)
+#define NVIC_CFGCON                   (CORTEXM3_NVIC_BASE + NVIC_CFGCON_OFFSET)
+#define NVIC_SYSH_PRIORITY(n)         (CORTEXM3_NVIC_BASE + NVIC_SYSH_PRIORITY_OFFSET(n))
+#define NVIC_SYSH4_7_PRIORITY         (CORTEXM3_NVIC_BASE + NVIC_SYSH4_7_PRIORITY_OFFSET)
+#define NVIC_SYSH8_11_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_SYSH8_11_PRIORITY_OFFSET)
+#define NVIC_SYSH12_15_PRIORITY       (CORTEXM3_NVIC_BASE + NVIC_SYSH12_15_PRIORITY_OFFSET)
+#define NVIC_SYSHCON                  (CORTEXM3_NVIC_BASE + NVIC_SYSHCON_OFFSET)
+#define NVIC_CFAULTS                  (CORTEXM3_NVIC_BASE + NVIC_CFAULTS_OFFSET)
+#define NVIC_HFAULTS                  (CORTEXM3_NVIC_BASE + NVIC_HFAULTS_OFFSET)
+#define NVIC_DFAULTS                  (CORTEXM3_NVIC_BASE + NVIC_DFAULTS_OFFSET)
+#define NVIC_MEMMANAGE_ADDR           (CORTEXM3_NVIC_BASE + NVIC_MEMMANAGE_ADDR_OFFSET)
+#define NVIC_BFAULT_ADDR              (CORTEXM3_NVIC_BASE + NVIC_BFAULT_ADDR_OFFSET)
+#define NVIC_AFAULTS                  (CORTEXM3_NVIC_BASE + NVIC_AFAULTS_OFFSET)
+#define NVIC_PFR0                     (CORTEXM3_NVIC_BASE + NVIC_PFR0_OFFSET)
+#define NVIC_PFR1                     (CORTEXM3_NVIC_BASE + NVIC_PFR1_OFFSET)
+#define NVIC_DFR0                     (CORTEXM3_NVIC_BASE + NVIC_DFR0_OFFSET)
+#define NVIC_AFR0                     (CORTEXM3_NVIC_BASE + NVIC_AFR0_OFFSET)
+#define NVIC_MMFR0                    (CORTEXM3_NVIC_BASE + NVIC_MMFR0_OFFSET)
+#define NVIC_MMFR1                    (CORTEXM3_NVIC_BASE + NVIC_MMFR1_OFFSET)
+#define NVIC_MMFR2                    (CORTEXM3_NVIC_BASE + NVIC_MMFR2_OFFSET)
+#define NVIC_MMFR3                    (CORTEXM3_NVIC_BASE + NVIC_MMFR3_OFFSET)
+#define NVIC_ISAR0                    (CORTEXM3_NVIC_BASE + NVIC_ISAR0_OFFSET)
+#define NVIC_ISAR1                    (CORTEXM3_NVIC_BASE + NVIC_ISAR1_OFFSET)
+#define NVIC_ISAR2                    (CORTEXM3_NVIC_BASE + NVIC_ISAR2_OFFSET)
+#define NVIC_ISAR3                    (CORTEXM3_NVIC_BASE + NVIC_ISAR3_OFFSET)
+#define NVIC_ISAR4                    (CORTEXM3_NVIC_BASE + NVIC_ISAR4_OFFSET)
+#define NVIC_STIR                     (CORTEXM3_NVIC_BASE + NVIC_STIR_OFFSET)
+#define NVIC_PID4                     (CORTEXM3_NVIC_BASE + NVIC_PID4_OFFSET)
+#define NVIC_PID5                     (CORTEXM3_NVIC_BASE + NVIC_PID5_OFFSET)
+#define NVIC_PID6                     (CORTEXM3_NVIC_BASE + NVIC_PID6_OFFSET)
+#define NVIC_PID7                     (CORTEXM3_NVIC_BASE + NVIC_PID7_OFFSET)
+#define NVIC_PID0                     (CORTEXM3_NVIC_BASE + NVIC_PID0_OFFSET)
+#define NVIC_PID1                     (CORTEXM3_NVIC_BASE + NVIC_PID1_OFFSET)
+#define NVIC_PID2                     (CORTEXM3_NVIC_BASE + NVIC_PID2_OFFSET)
+#define NVIC_PID3                     (CORTEXM3_NVIC_BASE + NVIC_PID3_OFFSET)
+#define NVIC_CID0                     (CORTEXM3_NVIC_BASE + NVIC_CID0_OFFSET)
+#define NVIC_CID1                     (CORTEXM3_NVIC_BASE + NVIC_CID1_OFFSET)
+#define NVIC_CID2                     (CORTEXM3_NVIC_BASE + NVIC_CID2_OFFSET)
+#define NVIC_CID3                     (CORTEXM3_NVIC_BASE + NVIC_CID3_OFFSET)
+
+/* NVIC register bit definitions ****************************************************/
+
+/* Interrrupt controller type (INCTCTL_TYPE) */
+
+#define NVIC_INTCTRL_TYPE_INTLINESNUM_SHIFT 0    /* Bits 4-0: Number of interrupt intputs / 32 */
+#define NVIC_INTCTRL_TYPE_INTLINESNUM_MASK  (0x1f << NVIC_INTCTRL_TYPE_INTLINESNUM_SHIFT)
+
+/* SysTick control and status register (SYSTICK_CTRL) */
+
+#define NVIC_SYSTICK_CTRL_ENABLE       (1 << 0)  /* Bit 0:  Enable */
+#define NVIC_SYSTICK_CTRL_TICKINT      (1 << 1)  /* Bit 1:  Tick interrupt */
+#define NVIC_SYSTICK_CTRL_CLKSOURCE    (1 << 2)  /* Bit 2:  Clock source */
+#define NVIC_SYSTICK_CTRL_COUNTFLAG    (1 << 16) /* Bit 16: Count Flag */
+
+/* SysTick reload value register (SYSTICK_RELOAD) */
+
+#define NVIC_SYSTICK_RELOAD_SHIFT      0         /* Bits 23-0: Timer reload value */
+#define NVIC_SYSTICK_RELOAD_MASK       (0x00ffffff << NVIC_SYSTICK_RELOAD_SHIFT)
+
+/* SysTick current value registe (SYSTICK_CURRENT) */
+
+#define NVIC_SYSTICK_CURRENT_SHIFT     0         /* Bits 23-0: Timer current value */
+#define NVIC_SYSTICK_CURRENT_MASK      (0x00ffffff << NVIC_SYSTICK_RELOAD_SHIFT)
+
+/* SysTick calibration value register (SYSTICK_CALIB) */
+
+#define NVIC_SYSTICK_CALIB_TENMS_SHIFT 0        /* Bits 23-0: Calibration value */
+#define NVIC_SYSTICK_CALIB_TENMS_MASK  (0x00ffffff << NVIC_SYSTICK_CALIB_TENMS_SHIFT)
+#define NVIC_SYSTICK_CALIB_SKEW        (1 << 30) /* Bit 30: Calibration value inexact */
+#define NVIC_SYSTICK_CALIB_NOREF       (1 << 31) /* Bit 31: No external reference clock */
+
+/* Interrupt control state register (INTCTRL) */
+
+#define NVIC_INTCTRL_NMIPENDSET        (1 << 31) /* Bit 31: Set pending NMI bit */
+#define NVIC_INTCTRL_PENDSVSET         (1 << 28) /* Bit 28: Set pending PendSV bit */
+#define NVIC_INTCTRL_PENDSVCLR         (1 << 27) /* Bit 27: Clear pending PendSV bit */
+#define NVIC_INTCTRL_PENDSTSET         (1 << 26) /* Bit 26: Set pending SysTick bit */
+#define NVIC_INTCTRL_PENDSTCLR         (1 << 25) /* Bit 25: Clear pending SysTick bit */
+#define NVIC_INTCTRL_ISPREEMPOT        (1 << 23) /* Bit 23: Pending active next cycle */
+#define NVIC_INTCTRL_ISRPENDING        (1 << 22) /* Bit 22: Interrupt pending flag */
+#define NVIC_INTCTRL_VECTPENDING_SHIFT 12        /* Bits 21-12: Pending ISR number field */
+#define NVIC_INTCTRL_VECTPENDING_MASK  (0x3ff << NVIC_INTCTRL_VECTPENDING_SHIFT)
+#define NVIC_INTCTRL_RETTOBASE         (1 << 11) /* Bit 11: no other exceptions pending */
+#define NVIC_INTCTRL_VECTACTIVE_SHIFT  0         /* Bits 8-0: Active ISR number */
+#define NVIC_INTCTRL_VECTACTIVE_MASK   (0x1ff << NVIC_INTCTRL_VECTACTIVE_SHIFT)
+
+/* System handler 4-7 priority register */
+
+#define NVIC_SYSH_PRIORITY_PR4_SHIFT   0
+#define NVIC_SYSH_PRIORITY_PR4_MASK    (0xff << NVIC_SYSH_PRIORITY_PR4_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR5_SHIFT   8
+#define NVIC_SYSH_PRIORITY_PR5_MASK    (0xff << NVIC_SYSH_PRIORITY_PR5_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR6_SHIFT   16
+#define NVIC_SYSH_PRIORITY_PR6_MASK    (0xff << NVIC_SYSH_PRIORITY_PR6_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR7_SHIFT   24
+#define NVIC_SYSH_PRIORITY_PR7_MASK    (0xff << NVIC_SYSH_PRIORITY_PR7_SHIFT)
+
+/* System handler 8-11 priority register */
+
+#define NVIC_SYSH_PRIORITY_PR8_SHIFT 0
+#define NVIC_SYSH_PRIORITY_PR8_MASK  (0xff << NVIC_SYSH_PRIORITY_PR8_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR9_SHIFT 8
+#define NVIC_SYSH_PRIORITY_PR9_MASK  (0xff << NVIC_SYSH_PRIORITY_PR9_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR10_SHIFT 16
+#define NVIC_SYSH_PRIORITY_PR10_MASK  (0xff << NVIC_SYSH_PRIORITY_PR10_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR11_SHIFT 24
+#define NVIC_SYSH_PRIORITY_PR11_MASK  (0xff << NVIC_SYSH_PRIORITY_PR11_SHIFT)
+
+/* System handler 12-15 priority register */
+
+#define NVIC_SYSH_PRIORITY_PR12_SHIFT 0
+#define NVIC_SYSH_PRIORITY_PR12_MASK  (0xff << NVIC_SYSH_PRIORITY_PR12_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR13_SHIFT 8
+#define NVIC_SYSH_PRIORITY_PR13_MASK  (0xff << NVIC_SYSH_PRIORITY_PR13_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR14_SHIFT 16
+#define NVIC_SYSH_PRIORITY_PR14_MASK  (0xff << NVIC_SYSH_PRIORITY_PR14_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR15_SHIFT 24
+#define NVIC_SYSH_PRIORITY_PR15_MASK  (0xff << NVIC_SYSH_PRIORITY_PR15_SHIFT)
+
+/* System handler control and state register (SYSHCON) */
+
+#define NVIC_SYSHCON_MEMFAULTACT      (1 << 0)  /* Bit 0:  MemManage is active */
+#define NVIC_SYSHCON_BUSFAULTACT      (1 << 1)  /* Bit 1:  BusFault is active */
+#define NVIC_SYSHCON_USGFAULTACT      (1 << 3)  /* Bit 3:  UsageFault is active */
+#define NVIC_SYSHCON_SVCALLACT        (1 << 7)  /* Bit 7:  SVCall is active */
+#define NVIC_SYSHCON_MONITORACT       (1 << 8)  /* Bit 8:  Monitor is active */
+#define NVIC_SYSHCON_PENDSVACT        (1 << 10) /* Bit 10: PendSV is active */
+#define NVIC_SYSHCON_SYSTICKACT       (1 << 11) /* Bit 11: SysTick is active */
+#define NVIC_SYSHCON_USGFAULTPENDED   (1 << 12) /* Bit 12: Usage fault is pended */
+#define NVIC_SYSHCON_MEMFAULTPENDED   (1 << 13) /* Bit 13: MemManage is pended */
+#define NVIC_SYSHCON_BUSFAULTPENDED   (1 << 14) /* Bit 14: BusFault is pended */
+#define NVIC_SYSHCON_SVCALLPENDED     (1 << 15) /* Bit 15: SVCall is pended */
+#define NVIC_SYSHCON_MEMFAULTENA      (1 << 16) /* Bit 16: MemFault enabled */
+#define NVIC_SYSHCON_BUSFAULTENA      (1 << 17) /* Bit 17: BusFault enabled */
+#define NVIC_SYSHCON_USGFAULTENA      (1 << 18) /* Bit 18: UsageFault enabled */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_COMMON_CORTEXM3_NVIC_H */

arch/arm/src/cortexm3/psr.h

@@ -0,0 +1,91 @@
+/************************************************************************************
+ * arch/arm/src/cortexm3/psr.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_COMMON_CORTEXM_PSR_H
+#define __ARCH_ARM_SRC_COMMON_CORTEXM_PSR_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+# include <sys/types.h>
+#endif
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Application Program Status Register (APSR) */
+
+#define CORTEXM3_APSR_Q            (1 << 27) /* Bit 27: Sticky saturation flag */
+#define CORTEXM3_APSR_V            (1 << 28) /* Bit 28: Overflow flag */
+#define CORTEXM3_APSR_C            (1 << 29) /* Bit 29: Carry/borrow flag */
+#define CORTEXM3_APSR_Z            (1 << 30) /* Bit 30: Zero flag */
+#define CORTEXM3_APSR_N            (1 << 31) /* Bit 31: Negative, less than flag */
+
+/* Interrupt Program Status Register (IPSR) */
+
+#define CORTEXM3_IPSR_ISR_SHIFT    0         /* Bits 8-0: ISR number */
+#define CORTEXM3_IPSR_ISR_MASK     (0x1ff << CORTEXM3_IPSR_ISR_SHIFT)
+
+/* Execution PSR Register (EPSR) */
+
+#define CORTEXM3_EPSR_ICIIT1_SHIFT 10        /* Bits 15-10: Interrupt-Continuable-Instruction/If-Then bits */
+#define CORTEXM3_EPSR_ICIIT1_MASK  (3 << CORTEXM3_EPSR_ICIIT1_SHIFT)
+#define CORTEXM3_EPSR_T            (1 << 24) /* Bit 24: T-bit */
+#define CORTEXM3_EPSR_ICIIT2_SHIFT 25        /* Bits 26-25: Interrupt-Continuable-Instruction/If-Then bits */
+#define CORTEXM3_EPSR_ICIIT2_MASK  (3 << CORTEXM3_EPSR_ICIIT2_SHIFT)
+
+/* Save xPSR bits */
+
+#define CORTEXM3_XPSR_ISR_SHIFT    CORTEXM3_IPSR_ISR_SHIFT
+#define CORTEXM3_XPSR_ISR_MASK     CORTEXM3_IPSR_ISR_MASK
+#define CORTEXM3_XPSR_ICIIT1_SHIFT CORTEXM3_EPSR_ICIIT1_SHIFT/
+#define CORTEXM3_XPSR_ICIIT1_MASK  CORTEXM3_EPSR_ICIIT1_MASK
+#define CORTEXM3_XPSR_T            CORTEXM3_EPSR_T
+#define CORTEXM3_XPSR_ICIIT2_SHIFT CORTEXM3_EPSR_ICIIT2_SHIFT
+#define CORTEXM3_XPSR_ICIIT2_MASK  CORTEXM3_EPSR_ICIIT2_MASK
+#define CORTEXM3_XPSR_Q            CORTEXM3_APSR_Q
+#define CORTEXM3_XPSR_V            CORTEXM3_APSR_V
+#define CORTEXM3_XPSR_C            CORTEXM3_APSR_C
+#define CORTEXM3_XPSR_Z            CORTEXM3_APSR_Z
+#define CORTEXM3_XPSR_N            CORTEXM3_APSR_N
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#endif  /* __ARCH_ARM_SRC_COMMON_CORTEXM_PSR_H */

arch/arm/src/cortexm3/up_assert.c

@@ -0,0 +1,311 @@
+/****************************************************************************
+ * arch/arm/src/cortexm3/up_assert.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdlib.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* Output debug info if stack dump is selected -- even if 
+ * debug is not selected.
+ */
+
+#ifdef CONFIG_ARCH_STACKDUMP
+# undef  lldbg
+# define lldbg lib_lowprintf
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_getsp
+ ****************************************************************************/
+
+/* I don't know if the builtin to get SP is enabled */
+
+static inline uint32 up_getsp(void)
+{
+  uint32 sp;
+  __asm__
+  (
+    "\tmov %0, sp\n\t"
+    : "=r"(sp)
+  );
+  return sp;
+}
+
+/****************************************************************************
+ * Name: up_stackdump
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_STACKDUMP
+static void up_stackdump(uint32 sp, uint32 stack_base)
+{
+  uint32 stack ;
+
+  for (stack = sp & ~0x1f; stack < stack_base; stack += 32)
+    {
+      uint32 *ptr = (uint32*)stack;
+      lldbg("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+             stack, ptr[0], ptr[1], ptr[2], ptr[3],
+             ptr[4], ptr[5], ptr[6], ptr[7]);
+    }
+}
+#else
+# define up_stackdump()
+#endif
+
+/****************************************************************************
+ * Name: up_registerdump
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_STACKDUMP
+static inline void up_registerdump(void)
+{
+  /* Are user registers available from interrupt processing? */
+
+  if (current_regs)
+    {
+      /* Yes.. dump the interrupt registers */
+
+      lldbg("R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+            current_regs[REG_R0],  current_regs[REG_R1],
+            current_regs[REG_R2],  current_regs[REG_R3],
+            current_regs[REG_R4],  current_regs[REG_R5],
+            current_regs[REG_R6],  current_regs[REG_R7]);
+      lldbg("R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+            current_regs[REG_R8],  current_regs[REG_R9],
+            current_regs[REG_R10], current_regs[REG_R11],
+            current_regs[REG_R12], current_regs[REG_R13],
+            current_regs[REG_R14], current_regs[REG_R15]);
+      lldbg("xPSR: %08x PRIMASK: %08x\n",
+            current_regs[REG_XPSR],  current_regs[REG_PRIMASK]);
+    }
+}
+#else
+# define up_registerdump()
+#endif
+
+/****************************************************************************
+ * Name: up_dumpstate
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_STACKDUMP
+static void up_dumpstate(void)
+{
+  _TCB *rtcb        = (_TCB*)g_readytorun.head;
+  uint32 sp         = up_getsp();
+  uint32 ustackbase;
+  uint32 ustacksize;
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+  uint32 istackbase;
+  uint32 istacksize;
+#endif
+
+  /* Get the limits on the user stack memory */
+
+  if (rtcb->pid == 0)
+    {
+      ustackbase = g_heapbase - 4;
+      ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
+    }
+  else
+    {
+      ustackbase = (uint32)rtcb->adj_stack_ptr;
+      ustacksize = (uint32)rtcb->adj_stack_size;
+    }
+
+  /* Get the limits on the interrupt stack memory */
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+  istackbase = (uint32)&g_userstack;
+  istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4;
+
+  /* Show interrupt stack info */
+
+  lldbg("sp:     %08x\n", sp);
+  lldbg("IRQ stack:\n");
+  lldbg("  base: %08x\n", istackbase);
+  lldbg("  size: %08x\n", istacksize);
+
+  /* Does the current stack pointer lie within the interrupt
+   * stack?
+   */
+
+  if (sp <= istackbase && sp > istackbase - istacksize)
+    {
+      /* Yes.. dump the interrupt stack */
+
+      up_stackdump(sp, istackbase);
+
+      /* Extract the user stack pointer which should lie
+       * at the base of the interrupt stack.
+       */
+
+      sp = g_userstack;
+      lldbg("sp:     %08x\n", sp);
+    }
+
+  /* Show user stack info */
+
+  lldbg("User stack:\n");
+  lldbg("  base: %08x\n", ustackbase);
+  lldbg("  size: %08x\n", ustacksize);
+#else
+  lldbg("sp:         %08x\n", sp);
+  lldbg("stack base: %08x\n", ustackbase);
+  lldbg("stack size: %08x\n", ustacksize);
+#endif
+
+  /* Dump the user stack if the stack pointer lies within the allocated user
+   * stack memory.
+   */
+
+  if (sp > ustackbase || sp <= ustackbase - ustacksize)
+    {
+#if !defined(CONFIG_ARCH_INTERRUPTSTACK) || CONFIG_ARCH_INTERRUPTSTACK < 4
+      lldbg("ERROR: Stack pointer is not within allocated stack\n");
+#endif
+    }
+  else
+    {
+      up_stackdump(sp, ustackbase);
+    }
+
+  /* Then dump the registers (if available) */
+
+  up_registerdump();
+}
+#else
+# define up_dumpstate()
+#endif
+
+/****************************************************************************
+ * Name: _up_assert
+ ****************************************************************************/
+
+static void _up_assert(int errorcode) /* __attribute__ ((noreturn)) */
+{
+  /* Are we in an interrupt handler or the idle task? */
+
+  if (current_regs || ((_TCB*)g_readytorun.head)->pid == 0)
+    {
+       (void)irqsave();
+        for(;;)
+          {
+#ifdef CONFIG_ARCH_LEDS
+            up_ledon(LED_PANIC);
+            up_mdelay(250);
+            up_ledoff(LED_PANIC);
+            up_mdelay(250);
+#endif
+          }
+    }
+  else
+    {
+      exit(errorcode);
+    }
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_assert
+ ****************************************************************************/
+
+void up_assert(const ubyte *filename, int lineno)
+{
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG)
+  _TCB *rtcb = (_TCB*)g_readytorun.head;
+#endif
+
+  up_ledon(LED_ASSERTION);
+#if CONFIG_TASK_NAME_SIZE > 0
+  lldbg("Assertion failed at file:%s line: %d task: %s\n",
+        filename, lineno, rtcb->name);
+#else
+  lldbg("Assertion failed at file:%s line: %d\n",
+        filename, lineno);
+#endif
+  up_dumpstate();
+  _up_assert(EXIT_FAILURE);
+}
+
+/****************************************************************************
+ * Name: up_assert_code
+ ****************************************************************************/
+
+void up_assert_code(const ubyte *filename, int lineno, int errorcode)
+{
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG)
+  _TCB *rtcb = (_TCB*)g_readytorun.head;
+#endif
+
+  up_ledon(LED_ASSERTION);
+#if CONFIG_TASK_NAME_SIZE > 0
+  lldbg("Assertion failed at file:%s line: %d task: %s error code: %d\n",
+        filename, lineno, rtcb->name, errorcode);
+#else
+  lldbg("Assertion failed at file:%s line: %d error code: %d\n",
+        filename, lineno, errorcode);
+#endif
+  up_dumpstate();
+  _up_assert(errorcode);
+}

arch/arm/src/cortexm3/up_context.S

@@ -0,0 +1,132 @@
+/************************************************************************************
+ * arch/arm/src/cortexm3/up_context.S
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include "nvic.h"
+
+/************************************************************************************
+ * Preprocessor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Global Symbols
+ ************************************************************************************/
+
+	.syntax		unified
+	.thumb
+	.file		"up_context.S"
+
+/************************************************************************************
+ * Macros
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/**************************************************************************
+ * Name: up_saveusercontext
+ *
+ * Description:
+ *   Save the current thread context.  Full prototype is:
+ *
+ *   int  up_saveusercontext(uint32 *regs);
+ *
+ * Return:
+ *   0: Normal return
+ *   1: Context switch return
+ *
+ **************************************************************************/
+
+	.text
+	.thumb_func
+	.globl		up_saveusercontext
+	.type		up_saveusercontext, function
+up_saveusercontext:
+
+	/* Perform the System call with R0=0 and R1=regs */
+
+	mov	r1, r0			/* R1: regs */
+	mov	r0, #0			/* R0: 0 means save context (also return value) */
+	svc	0			/* Force synchronous SVCall (or Hard Fault) */
+
+	/* There are two return conditions.  On the first return, R0 (the
+	 * return value will be zero.  On the second return we need to
+	 * force R0 to be 1.
+	 */
+
+	add	r2, r1, #(4*REG_R0)
+	mov	r3, #1
+	str	r3, [r2, #0]
+	bx	lr			/* "normal" return with r0=0 or
+					 * context switch with r0=1 */
+	.size		up_saveusercontext, .-up_saveusercontext
+
+
+/**************************************************************************
+ * Name: up_fullcontextrestore
+ *
+ * Description:
+ *   Restore the current thread context.  Full prototype is:
+ *
+ *   void up_fullcontextrestore(uint32 *regs) __attribute__ ((noreturn));
+ *
+ * Return:
+ *   None
+ *
+ **************************************************************************/
+
+	.thumb_func
+	.globl		up_fullcontextrestore
+	.type		up_fullcontextrestore, function
+up_fullcontextrestore:
+
+	/* Perform the System call with R0=1 and R1=regs */
+
+	mov	r1, r0			/* R1: regs */
+	mov	r0, #1			/* R0: 1 means restore context */
+	svc	0			/* Force synchronous SVCall (or Hard Fault) */
+
+	/* This call should not return */
+
+	bx	lr			/* Unnecessary ... will not return */
+	.size		up_fullcontextrestore, .-up_fullcontextrestore
+        .end
+

arch/arm/src/cortexm3/up_copystate.c

@@ -0,0 +1,86 @@
+/****************************************************************************
+ * arch/arm/src/cortexm3/up_copystate.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+
+#include "os_internal.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_undefinedinsn
+ ****************************************************************************/
+
+/* A little faster than most memcpy's */
+
+void up_copystate(uint32 *dest, uint32 *src)
+{
+  int i;
+
+  /* In the Cortex-M3 model, the state is copied from the stack to the TCB,
+   * but only a reference is passed to get the state from the TCB.  So the
+   * following check avoids copying the TCB save area onto itself:
+   */
+
+  if (src != dest)
+    {
+      for (i = 0; i < XCPTCONTEXT_REGS; i++)
+        {
+          *dest++ = *src++;
+        }
+    }
+}
+