mirror of
https://github.com/apache/nuttx.git
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Add basic lm3s6918 gpio support
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1778 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -827,7 +827,8 @@
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<p>
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<b>STATUS:</b>
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This port is in progress. Coding is complete on the basic port (timer, serial console, SPI).
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Verified support for the i.MX1 will be announced in a future release of NuttX.
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Verified support for the i.MX1 will be announced in a future release of NuttX (work has
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been temporarily stopped to support the Luminary LM3S6918).
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</p>
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</td>
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</tr>
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@@ -851,10 +852,32 @@
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<b>STATUS:</b>
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The basic port (timer interrupts, serial ports, network, framebuffer, etc.) is complete.
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All implemented features have been verified with the exception of the USB device-side
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driver; that implementation is complete but completely untested.
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driver; that implementation is complete but untested.
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</p>
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</td>
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</tr>
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<tr>
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<td valign="top"><img height="20" width="20" src="favicon.ico"></td>
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<td bgcolor="#5eaee1">
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<b>ARM Cortex-M3</b>.
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</td>
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</tr>
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<tr>
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<td><br></td>
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<td>
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<p>
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<b>Luminary LM3S6918</b>.
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This port uses theMicromint Eagle-10 development board with a GNU arm-elf toolchain*
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under either Linux or Cygwin.
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</p>
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<p>
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<b>STATUS:</b>
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This port is in progress. Coding is complete on the basic port (timer, serial console, SPI).
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Verified support for the Cortex-M3 will be announced in a future release of NuttX.
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</p>
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</td>
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</tr>
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<tr>
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<td valign="top"><img height="20" width="20" src="favicon.ico"></td>
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<td bgcolor="#5eaee1">
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@@ -43,11 +43,11 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
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up_prefetchabort.c up_releasepending.c up_releasestack.c \
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up_reprioritizertr.c up_schedulesigaction.c \
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up_sigdeliver.c up_syscall.c up_unblocktask.c \
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up_undefinedinsn.c up_usestack.c
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up_undefinedinsn.c up_usestack.c up_doirq.c
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CHIP_ASRCS = lm3s_context.S
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CHIP_CSRCS = lm3s_start.c lm3s_syscontrol.c lm3s_irq.c lm3s_pendsv.c \
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lm3s_timerisr.c lm3s_lowputc.c lm3s_serial.c
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lm3s_gpio.c lm3s_timerisr.c lm3s_lowputc.c lm3s_serial.c
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ifdef CONFIG_NET
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CHIP_CSRCS += lm3s_ethernet.c
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@@ -565,14 +565,10 @@ int lm3s_initialize(void)
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/* Enable Port F for Ethernet LEDs: LED0=Bit 3; LED1=Bit 2 */
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#ifdef CONFIG_LM3S_ETHLEDS
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/* Make sure that the GPIOF peripheral is enabled */
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modifyreg32(LM3S_SYSCON_RCGC2_OFFSET, 0, SYSCON_RCGC2_GPIOF);
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/* Configure the pins for the peripheral function */
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lm3s_configgpio(GPIO_FUNC_PERIPHERAL | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD | GPIO_PORTF | 2);
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lm3s_configgpio(GPIO_FUNC_PERIPHERAL | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD | GPIO_PORTF | 3);
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lm3s_configgpio(GPIO_ETHPHY_LED0 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD);
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lm3s_configgpio(GPIO_ETHPHY_LED1 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD);
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#endif
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#warning "Missing logic"
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File diff suppressed because it is too large
Load Diff
@@ -57,12 +57,19 @@
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* The default priority level is set to the middle value
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0x00
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80
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#define NVIC_SYSH_PRIORITY_MAX 0xe0
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#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* All bits set in minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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/* Bit-encoded input to lm3s_configgpio() *******************************************/
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/* Encoding:
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* FFFS SPPP IIIn nnnn nnnn nnnn nVPP PBBB
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*
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* These bits set the primary function of the pin:
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* FFFn nnnn nnnn nnnn nnnn nnnn nnnn nnnn
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*/
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#define GPIO_FUNC_SHIFT 29 /* Bit 31-29: GPIO function */
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#define GPIO_FUNC_MASK (7 << GPIO_FUNC_SHIFT) /* (See table 9-1 in data sheet) */
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#define GPIO_FUNC_INPUT (0 << GPIO_FUNC_SHIFT) /* Digital GPIO input */
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@@ -75,23 +82,21 @@
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#define GPIO_FUNC_PFIO (5 << GPIO_FUNC_SHIFT) /* Digital input/output (SSI, UART) */
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#define GPIO_FUNC_ANINPUT (6 << GPIO_FUNC_SHIFT) /* Analog input (Comparator) */
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#define GPIO_FUNC_INTERRUPT (7 << GPIO_FUNC_SHIFT) /* Interrupt function */
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#define GPIO_FUNC_MAX GPIO_FUNC_INTERRUPT
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#define GPIO_INT_SHIFT 26 /* Bits 28-26: Interrupt type */
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#define GPIO_INT_MASK (7 << GPIO_INT_SHIFT)
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#define GPIO_INT_FALLINGEDGE (0 << GPIO_INT_SHIFT) /* Interrupt on falling edge */
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#define GPIO_INT_RISINGEDGE (1 << GPIO_INT_SHIFT) /* Interrupt on rising edge */
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#define GPIO_INT_BOTHEDGES (2 << GPIO_INT_SHIFT) /* Interrupt on both edges */
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#define GPIO_INT_LOWLEVEL (3 << GPIO_INT_SHIFT) /* Interrupt on low level */
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#define GPIO_INT_HIGHLEVEL (4 << GPIO_INT_SHIFT) /* Interrupt on high level */
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/* That primary may be modified by the following options
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* nnnS SPPP nnnn nnnn nnnn nnnn nnnn nnnn
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*/
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#define GPIO_STRENGTH_SHIFT 24 /* Bits 25-24: Pad drive strength */
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#define GPIO_STRENGTH_SHIFT 27 /* Bits 28-27: Pad drive strength */
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#define GPIO_STRENGTH_MASK (3 << GPIO_STRENGTH_SHIFT)
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#define GPIO_STRENGTH_2MA (0 << GPIO_STRENGTH_SHIFT) /* 2mA pad drive strength */
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#define GPIO_STRENGTH_4MA (1 << GPIO_STRENGTH_SHIFT) /* 4mA pad drive strength */
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#define GPIO_STRENGTH_8MA (2 << GPIO_STRENGTH_SHIFT) /* 8mA pad drive strength */
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#define GPIO_STRENGTH_8MASC (3 << GPIO_STRENGTH_SHIFT) /* 8mA Pad drive with slew rate control */
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#define GPIO_STRENGTH_MAX GPIO_STRENGTH_8MASC
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#define GPIO_PADTYPE_SHIFT 21 /* Bits 21-23: Pad type */
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#define GPIO_PADTYPE_SHIFT 24 /* Bits 26-24: Pad type */
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#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT)
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#define GPIO_PADTYPE_STD (0 << GPIO_PADTYPE_SHIFT) /* Push-pull */
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#define GPIO_PADTYPE_STDWPU (1 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-up */
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@@ -101,11 +106,31 @@
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#define GPIO_PADTYPE_ODWPD (5 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-down */
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#define GPIO_PADTYPE_ANALOG (6 << GPIO_PADTYPE_SHIFT) /* Analog comparator */
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/* If the pin is an interrupt, then the following options apply
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* nnnn nnnn IIIn nnnn nnnn nnnn nnnn nnnn
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*/
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#define GPIO_INT_SHIFT 21 /* Bits 23-21: Interrupt type */
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#define GPIO_INT_MASK (7 << GPIO_INT_SHIFT)
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#define GPIO_INT_FALLINGEDGE (0 << GPIO_INT_SHIFT) /* Interrupt on falling edge */
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#define GPIO_INT_RISINGEDGE (1 << GPIO_INT_SHIFT) /* Interrupt on rising edge */
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#define GPIO_INT_BOTHEDGES (2 << GPIO_INT_SHIFT) /* Interrupt on both edges */
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#define GPIO_INT_LOWLEVEL (3 << GPIO_INT_SHIFT) /* Interrupt on low level */
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#define GPIO_INT_HIGHLEVEL (4 << GPIO_INT_SHIFT) /* Interrupt on high level */
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/* If the pin is an GPIO digital output, then this identifies the initial output value:
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* nnnn nnnn nnnn nnnn nnnn nnnn nVnn nnnn
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*/
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#define GPIO_VALUE_SHIFT 6 /* Bit 6: If output, inital value of output */
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#define GPIO_VALUE_MASK (1 << GPIO_VALUE_SHIFT)
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#define GPIO_VALUE_ZERO (0 << GPIO_VALUE_SHIFT) /* Initial value is zero */
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#define GPIO_VALUE_ONE (1 << GPIO_VALUE_SHIFT) /* Initial value is one */
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/* This identifies the GPIO port
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* nnnn nnnn nnnn nnnn nnnn nnnn nnPP Pnnn
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*/
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#define GPIO_PORT_SHIFT 3 /* Bit 3-5: Port number */
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#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
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#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */
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@@ -117,6 +142,10 @@
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#define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
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#define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */
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/* This identifies the bit in the port:
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* nnnn nnnn nnnn nnnn nnnn nnnn nnnn nBBB
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*/
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#define GPIO_NUMBER_SHIFT 0 /* Bits 0-2: GPIO number: 0-7 */
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#define GPIO_NUMBER_MASK (7 << GPIO_NUMBER_SHIFT)
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@@ -172,24 +201,6 @@
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#ifndef __ASSEMBLY__
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static inline uint32 lm3s_gpiobaseaddress(unsigned int port)
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{
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#ifdef CONFIG_ARCH_CHIP_LM3S6918
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unsigned int portno = (port >> GPIO_PORT_SHIFT) & 7;
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if (portno < 4)
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{
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return LM3S_GPIOA_BASE + 0x1000 * portno;
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}
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else
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{
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return LM3S_GPIOE_BASE + 0x1000 * portno;
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}
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#else
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# error "GPIO register base addresses not known for this LM3S chip"
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return 0;
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#endif
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}
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/************************************************************************************
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* Public Data
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************************************************************************************/
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@@ -249,7 +260,7 @@ EXTERN void up_clockconfig(void);
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*
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****************************************************************************/
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EXTERN int lm3s_configgpio(uint32 bitset);
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EXTERN int lm3s_configgpio(uint32 cfgset);
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/****************************************************************************
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* Name: lm3s_pendsv
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@@ -261,6 +272,26 @@ EXTERN int lm3s_configgpio(uint32 bitset);
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EXTERN int lm3s_pendsv(int irq, FAR void *context);
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/****************************************************************************
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* Name: lm3s_gpiowrite
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*
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* Description:
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* Write one or zero to the selected GPIO pin
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*
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****************************************************************************/
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EXTERN void lm3s_gpiowrite(uint32 pinset, boolean value);
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/****************************************************************************
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* Name: lm3s_gpioread
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*
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* Description:
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* Read one or zero from the selected GPIO pin
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*
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****************************************************************************/
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EXTERN boolean lm3s_gpioread(uint32 pinset, boolean value);
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#undef EXTERN
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#if defined(__cplusplus)
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}
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@@ -40,7 +40,9 @@
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include "up_arch.h"
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#include "os_internal.h"
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@@ -173,13 +175,17 @@ void up_irqinitialize(void)
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current_regs = NULL;
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/* Attach the PendSV exception handler. This is used for performing
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/* Attach the PendSV exception handler and set it to the minimum
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* prioirity. The PendSV exception is used for performing
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* context switches.
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*/
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irq_attach(LMSB_IRQ_PENDSV, lm3s_pendsv);
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#ifdef CONFIG_ARCH_IRQPRIO
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up_prioritize_irq(LMSB_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN);
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#endif
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/* Attach all processor exceptions (except reset and sys tick) */
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/* Attach all other processor exceptions (except reset and sys tick) */
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#ifdef CONFIG_DEBUG
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irq_attach(LMSB_IRQ_NMI, lm3s_nmi);
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@@ -285,7 +291,7 @@ int up_prioritize_irq(int irq, int priority)
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uint32 regval;
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int shift;
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DEBUGASSERT(irq >= LMSB_IRQ_MPU && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MAX);
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DEBUGASSERT(irq >= LMSB_IRQ_MPU && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
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if (irq < LM3S_IRQ_INTERRUPTS)
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{
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@@ -249,22 +249,6 @@ void up_lowsetup(void)
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putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
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#endif
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/* Peripheral clocking to the selected UART modules and to the GPIO
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* modules used for the pin configuration. NOTE: this function is
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* called very early in the boot sequence so we do not need to be
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* concerned about exclusive access to registers.
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*/
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rcgc1 = getreg32(LM3S_SYSCON_RCGC1);
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#if !defined(CONFIG_UART0_DISABLE) && !defined(CONFIG_UART1_DISABLE)
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rcgc1 |= (SYSCON_RCGC1_UART0|SYSCON_RCGC2_GPIOA|SYSCON_RCGC1_UART1|SYSCON_RCGC2_GPIOD);
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#elif !defined(CONFIG_UART0_DISABLE)
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rcgc1 |= (SYSCON_RCGC1_UART0|SYSCON_RCGC2_GPIOA);
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#elif !defined(CONFIG_UART1_DISABLE)
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rcgc1 |= (SYSCON_RCGC1_UART1|SYSCON_RCGC2_GPIOD);
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#endif
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putreg32(rcgc1, LM3S_SYSCON_RCGC1);
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/* Then configure GPIO pins to enable the selected UARTs. NOTE: The
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* serial driver later depends on this pin configuration.
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*/
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@@ -102,7 +102,7 @@ extern void lm3s_vectors(void);
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*
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****************************************************************************/
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void _start(void)
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void __start(void)
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{
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const uint32 *src;
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uint32 *dest;
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@@ -210,6 +210,7 @@
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/* Device Capabilities 4 (DC4), offset 0x01c */
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#define SYSCON_DC4_GPIO(n) (1 << (n))
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#define SYSCON_DC4_GPIOA (1 << 0) /* Bit 0: GPIO Port A Present */
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#define SYSCON_DC4_GPIOB (1 << 1) /* Bit 1: GPIO Port B Present */
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#define SYSCON_DC4_GPIOC (1 << 2) /* Bit 2: GPIO Port C Present */
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@@ -264,6 +265,7 @@
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/* Software Reset Control 2 (SRCR2), offset 0x048 */
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#define SYSCON_SRCR2_GPIO(n) (1 << (n))
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#define SYSCON_SRCR2_GPIOA (1 << 0) /* Bit 0: Port A Reset Control */
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#define SYSCON_SRCR2_GPIOB (1 << 1) /* Bit 1: Port B Reset Control */
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#define SYSCON_SRCR2_GPIOC (1 << 2) /* Bit 2: Port C Reset Control */
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@@ -382,6 +384,7 @@
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/* Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 */
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#define SYSCON_RCGC2_GPIO(n) (1 << (n))
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#define SYSCON_RCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */
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#define SYSCON_RCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */
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#define SYSCON_RCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */
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@@ -418,6 +421,7 @@
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/* Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 */
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#define SYSCON_SCGC2_GPIO(n) (1 << (n))
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#define SYSCON_SCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */
|
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#define SYSCON_SCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */
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#define SYSCON_SCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */
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@@ -454,6 +458,7 @@
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/* Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 */
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#define SYSCON_DCGC2_GPIO(n) (1 << (n))
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#define SYSCON_DCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */
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#define SYSCON_DCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */
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#define SYSCON_DCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */
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@@ -64,6 +64,7 @@
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* Global Symbols
|
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************************************************************************************/
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.globl __start
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.globl dispach_irq
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.syntax unified
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@@ -99,7 +100,7 @@
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lm3s_vectors:
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/* Processor Exceptions */
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.word IDLE_STACK /* Vector 0: Reset stack pointer */
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.word _start /* Vector 1: Reset vector */
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.word __start /* Vector 1: Reset vector */
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.word lm3s_nmi /* Vector 2: Non-Maskable Interrupt (NMI) */
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.word lm3s_hardfault /* Vector 3: Hard fault */
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.word lm3s_mpu /* Vector 4: Memory management (MPU) */
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@@ -474,6 +474,11 @@ configs/c5471evm
|
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NuttX runs on the ARM core and is built with a GNU arm-elf toolchain*.
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This port is complete, verified, and included in the NuttX release.
|
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|
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configs/eagle100
|
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Micromint Eagle-100 Development board. This board is based on the
|
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an ARM Cortex-M3 MCU, the Luminary LM3S6918. This OS is built with the
|
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arm-elf toolchain*. STATUS: This port is currently under development.
|
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|
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configs/ez80f0910200kitg
|
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ez80Acclaim! Microcontroller. This port use the Zilog ez80f0910200kitg
|
||||
development kit, eZ80F091 part, and the Zilog ZDS-II Windows command line
|
||||
@@ -493,6 +498,12 @@ configs/mcu123-lpc214x
|
||||
lpc214x development board. This OS is also built with the arm-elf
|
||||
toolchain*. The port supports serial, timer0, spi, and usb.
|
||||
|
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configs/mx1ads
|
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This is a port to the Motorola MX1ADS development board. That board
|
||||
is based on the Freescale i.MX1 processor. The i.MX1 is an ARM920T.
|
||||
STATUS: This port is nearly code complete but still under development
|
||||
(work is stalled until I devote time to the Micromint Eagle-100)
|
||||
|
||||
configs/ntosd-dm320
|
||||
This port uses the Neuros OSD with a GNU arm-elf toolchain*:
|
||||
see http://wiki.neurostechnology.com/index.php/Developer_Welcome .
|
||||
|
||||
Reference in New Issue
Block a user