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arch/arm/imx9: add i.MX93 Cortex-M33 support.

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Add hardware register headers and driver support for the NXP i.MX93
Cortex-M33 core. All new and modified code is guarded by
ARCH_CHIP_IMX93_M33 preprocessor defines; existing i.MX95-M7 builds
are unaffected.

New drivers:
- imx9_xcache.c - off core cache init and maintenance
- imx9_ccm.c - generic CCM abstraction layer

Signed-off-by: Maarten Zanders <maarten@zanders.be>
This commit is contained in:
Maarten Zanders
2026-02-27 14:22:30 +01:00
committed by Xiang Xiao
parent 461e7bd91f
commit f70d40bca7
29 changed files with 5335 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/include/imx9/imx93_irq.h
+304
View File
@@ -0,0 +1,304 @@
/****************************************************************************
* arch/arm/include/imx9/imx93_irq.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_IMX9_IMX93_IRQ_H
#define __ARCH_ARM_INCLUDE_IMX9_IMX93_IRQ_H
#define IMX9_IRQ_RESERVED32 (IMX9_IRQ_EXTINT + 0) /* Exception condition notification while boot */
#define IMX9_IRQ_RESERVED33 (IMX9_IRQ_EXTINT + 1) /* DAP interrupt */
#define IMX9_IRQ_RESERVED34 (IMX9_IRQ_EXTINT + 2) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED35 (IMX9_IRQ_EXTINT + 3) /* CTI trigger outputs from CM33 platform */
#define IMX9_IRQ_RESERVED36 (IMX9_IRQ_EXTINT + 4) /* CTI trigger outputs from CA55 platform */
#define IMX9_IRQ_RESERVED37 (IMX9_IRQ_EXTINT + 5) /* Performance Unit Interrupts from CA55 platform */
#define IMX9_IRQ_RESERVED38 (IMX9_IRQ_EXTINT + 6) /* ECC error from CA55 platform cache */
#define IMX9_IRQ_RESERVED39 (IMX9_IRQ_EXTINT + 7) /* 1-bit or 2-bit ECC or Parity error from CA55 platform cache */
#define IMX9_IRQ_CAN1 (IMX9_IRQ_EXTINT + 8) /* CAN1 interrupt */
#define IMX9_IRQ_CAN1_ERROR (IMX9_IRQ_EXTINT + 9) /* CAN1 error interrupt */
#define IMX9_IRQ_GPIO1_0 (IMX9_IRQ_EXTINT + 10) /* General Purpose Input/Output 1 interrupt 0 */
#define IMX9_IRQ_GPIO1_1 (IMX9_IRQ_EXTINT + 11) /* General Purpose Input/Output 1 interrupt 1 */
#define IMX9_IRQ_I3C1 (IMX9_IRQ_EXTINT + 12) /* Improved Inter-Integrated Circuit 1 interrupt */
#define IMX9_IRQ_LPI2C1 (IMX9_IRQ_EXTINT + 13) /* Low Power Inter-Integrated Circuit module 1 */
#define IMX9_IRQ_LPI2C2 (IMX9_IRQ_EXTINT + 14) /* Low Power Inter-Integrated Circuit module 2 */
#define IMX9_IRQ_LPIT1 (IMX9_IRQ_EXTINT + 15) /* Low Power Periodic Interrupt Timer 1 */
#define IMX9_IRQ_LPSPI1 (IMX9_IRQ_EXTINT + 16) /* Low Power Serial Peripheral Interface 1 */
#define IMX9_IRQ_LPSPI2 (IMX9_IRQ_EXTINT + 17) /* Low Power Serial Peripheral Interface 2 */
#define IMX9_IRQ_LPTMR1 (IMX9_IRQ_EXTINT + 18) /* Low Power Timer 1 */
#define IMX9_IRQ_LPUART1 (IMX9_IRQ_EXTINT + 19) /* Low Power UART 1 */
#define IMX9_IRQ_LPUART2 (IMX9_IRQ_EXTINT + 20) /* Low Power UART 2 */
#define IMX9_IRQ_MU1_A (IMX9_IRQ_EXTINT + 21) /* Messaging Unit 1 - Side A (to communicate with M7 core) */
#define IMX9_IRQ_MU1_B (IMX9_IRQ_EXTINT + 22) /* Messaging Unit 1 - Side B (to communicate with M33 core) */
#define IMX9_IRQ_MU2_A (IMX9_IRQ_EXTINT + 23) /* Messaging Unit 2 - Side A (to communicate with M7 core) */
#define IMX9_IRQ_MU2_B (IMX9_IRQ_EXTINT + 24) /* Messaging Unit 2 - Side B (to communicate with A55 core) */
#define IMX9_IRQ_RESERVED57 (IMX9_IRQ_EXTINT + 25) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED58 (IMX9_IRQ_EXTINT + 26) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED59 (IMX9_IRQ_EXTINT + 27) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED60 (IMX9_IRQ_EXTINT + 28) /* Edgelock Trust MUA RX full interrupt */
#define IMX9_IRQ_RESERVED61 (IMX9_IRQ_EXTINT + 29) /* Edgelock Trust MUA TX empty interrupt */
#define IMX9_IRQ_RESERVED62 (IMX9_IRQ_EXTINT + 30) /* Edgelock Apps Core MUA RX full interrupt */
#define IMX9_IRQ_RESERVED63 (IMX9_IRQ_EXTINT + 31) /* Edgelock Apps Core MUA TX empty interrupt */
#define IMX9_IRQ_RESERVED64 (IMX9_IRQ_EXTINT + 32) /* Edgelock Realtime Core MUA RX full interrupt */
#define IMX9_IRQ_RESERVED65 (IMX9_IRQ_EXTINT + 33) /* Edgelock Realtime Core MUA TX empty interrupt */
#define IMX9_IRQ_RESERVED66 (IMX9_IRQ_EXTINT + 34) /* Edgelock secure interrupt */
#define IMX9_IRQ_RESERVED67 (IMX9_IRQ_EXTINT + 35) /* Edgelock non-secure interrupt */
#define IMX9_IRQ_TPM1 (IMX9_IRQ_EXTINT + 36) /* Timer PWM module 1 */
#define IMX9_IRQ_TPM2 (IMX9_IRQ_EXTINT + 37) /* Timer PWM module 2 */
#define IMX9_IRQ_WDOG1 (IMX9_IRQ_EXTINT + 38) /* Watchdog 1 Interrupt */
#define IMX9_IRQ_WDOG2 (IMX9_IRQ_EXTINT + 39) /* Watchdog 2 Interrupt */
#define IMX9_IRQ_TRDC (IMX9_IRQ_EXTINT + 40) /* AONMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED73 (IMX9_IRQ_EXTINT + 41) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED74 (IMX9_IRQ_EXTINT + 42) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED75 (IMX9_IRQ_EXTINT + 43) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED76 (IMX9_IRQ_EXTINT + 44) /* Reserved interrupt */
#define IMX9_IRQ_SAI1 (IMX9_IRQ_EXTINT + 45) /* Serial Audio Interface 1 */
#define IMX9_IRQ_RESERVED78 (IMX9_IRQ_EXTINT + 46) /* M33 PS Tag/Data Parity Error */
#define IMX9_IRQ_RESERVED79 (IMX9_IRQ_EXTINT + 47) /* M33 TCM ECC interrupt */
#define IMX9_IRQ_RESERVED80 (IMX9_IRQ_EXTINT + 48) /* M33 TCM Error interrupt */
#define IMX9_IRQ_RESERVED81 (IMX9_IRQ_EXTINT + 49) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED82 (IMX9_IRQ_EXTINT + 50) /* Reserved interrupt */
#define IMX9_IRQ_CAN2 (IMX9_IRQ_EXTINT + 51) /* CAN2 interrupt */
#define IMX9_IRQ_CAN2_ERROR (IMX9_IRQ_EXTINT + 52) /* CAN2 error interrupt */
#define IMX9_IRQ_FLEXIO1 (IMX9_IRQ_EXTINT + 53) /* Flexible IO 1 interrupt */
#define IMX9_IRQ_FLEXIO2 (IMX9_IRQ_EXTINT + 54) /* Flexible IO 2 interrupt */
#define IMX9_IRQ_FLEXSPI1 (IMX9_IRQ_EXTINT + 55) /* FlexSPI controller interface interrupt 1 */
#define IMX9_IRQ_RESERVED88 (IMX9_IRQ_EXTINT + 56) /* Reserved interrupt */
#define IMX9_IRQ_GPIO2_0 (IMX9_IRQ_EXTINT + 57) /* General Purpose Input/Output 2 interrupt 0 */
#define IMX9_IRQ_GPIO2_1 (IMX9_IRQ_EXTINT + 58) /* General Purpose Input/Output 2 interrupt 1 */
#define IMX9_IRQ_GPIO3_0 (IMX9_IRQ_EXTINT + 59) /* General Purpose Input/Output 3 interrupt 0 */
#define IMX9_IRQ_GPIO3_1 (IMX9_IRQ_EXTINT + 60) /* General Purpose Input/Output 3 interrupt 1 */
#define IMX9_IRQ_I3C2 (IMX9_IRQ_EXTINT + 61) /* Improved Inter-Integrated Circuit 2 interrupt */
#define IMX9_IRQ_LPI2C3 (IMX9_IRQ_EXTINT + 62) /* Low Power Inter-Integrated Circuit module 3 */
#define IMX9_IRQ_LPI2C4 (IMX9_IRQ_EXTINT + 63) /* Low Power Inter-Integrated Circuit module 4 */
#define IMX9_IRQ_LPIT2 (IMX9_IRQ_EXTINT + 64) /* Low Power Periodic Interrupt Timer 2 */
#define IMX9_IRQ_LPSPI3 (IMX9_IRQ_EXTINT + 65) /* Low Power Serial Peripheral Interface 3 */
#define IMX9_IRQ_LPSPI4 (IMX9_IRQ_EXTINT + 66) /* Low Power Serial Peripheral Interface 4 */
#define IMX9_IRQ_LPTMR2 (IMX9_IRQ_EXTINT + 67) /* Low Power Timer 2 */
#define IMX9_IRQ_LPUART3 (IMX9_IRQ_EXTINT + 68) /* Low Power UART 3 */
#define IMX9_IRQ_LPUART4 (IMX9_IRQ_EXTINT + 69) /* Low Power UART 4 */
#define IMX9_IRQ_LPUART5 (IMX9_IRQ_EXTINT + 70) /* Low Power UART 5 */
#define IMX9_IRQ_LPUART6 (IMX9_IRQ_EXTINT + 71) /* Low Power UART 6 */
#define IMX9_IRQ_RESERVED104 (IMX9_IRQ_EXTINT + 72) /* MTR Master error interrupt */
#define IMX9_IRQ_RESERVED105 (IMX9_IRQ_EXTINT + 73) /* BBNSM Non-Secure interrupt */
#define IMX9_IRQ_RESERVED106 (IMX9_IRQ_EXTINT + 74) /* System Counter compare interrupt */
#define IMX9_IRQ_TPM3 (IMX9_IRQ_EXTINT + 75) /* Timer PWM module 3 */
#define IMX9_IRQ_TPM4 (IMX9_IRQ_EXTINT + 76) /* Timer PWM module 4 */
#define IMX9_IRQ_TPM5 (IMX9_IRQ_EXTINT + 77) /* Timer PWM module 5 */
#define IMX9_IRQ_TPM6 (IMX9_IRQ_EXTINT + 78) /* Timer PWM module 6 */
#define IMX9_IRQ_WDOG3 (IMX9_IRQ_EXTINT + 79) /* Watchdog 3 Interrupt */
#define IMX9_IRQ_WDOG4 (IMX9_IRQ_EXTINT + 80) /* Watchdog 4 Interrupt */
#define IMX9_IRQ_WDOG5 (IMX9_IRQ_EXTINT + 81) /* Watchdog 5 Interrupt */
#define IMX9_IRQ_RESERVED114 (IMX9_IRQ_EXTINT + 82) /* WAKEUPMIX TRDC transfer error interrupt */
#define IMX9_IRQ_TEMPMON (IMX9_IRQ_EXTINT + 83) /* TempSensor interrupt */
#define IMX9_IRQ_RESERVED116 (IMX9_IRQ_EXTINT + 84) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED117 (IMX9_IRQ_EXTINT + 85) /* Reserved interrupt */
#define IMX9_IRQ_USDHC1 (IMX9_IRQ_EXTINT + 86) /* ultra Secure Digital Host Controller interrupt 1 */
#define IMX9_IRQ_USDHC2 (IMX9_IRQ_EXTINT + 87) /* ultra Secure Digital Host Controller interrupt 2 */
#define IMX9_IRQ_RESERVED120 (IMX9_IRQ_EXTINT + 88) /* MEGAMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED121 (IMX9_IRQ_EXTINT + 89) /* NIC_WRAPPER TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED122 (IMX9_IRQ_EXTINT + 90) /* DRAM controller Performance Monitor Interrupt */
#define IMX9_IRQ_RESERVED123 (IMX9_IRQ_EXTINT + 91) /* DRAM controller Critical Interrupt */
#define IMX9_IRQ_RESERVED124 (IMX9_IRQ_EXTINT + 92) /* DRAM Phy Critical Interrupt */
#define IMX9_IRQ_RESERVED125 (IMX9_IRQ_EXTINT + 93) /* Reserved interrupt */
#define IMX9_IRQ_DMA3_ERROR (IMX9_IRQ_EXTINT + 94) /* eDMA1 error interrupt */
#define IMX9_IRQ_DMA3_0 (IMX9_IRQ_EXTINT + 95) /* eDMA1 channel 0 interrupt */
#define IMX9_IRQ_DMA3_1 (IMX9_IRQ_EXTINT + 96) /* eDMA1 channel 1 interrupt */
#define IMX9_IRQ_DMA3_2 (IMX9_IRQ_EXTINT + 97) /* eDMA1 channel 2 interrupt */
#define IMX9_IRQ_DMA3_3 (IMX9_IRQ_EXTINT + 98) /* eDMA1 channel 3 interrupt */
#define IMX9_IRQ_DMA3_4 (IMX9_IRQ_EXTINT + 99) /* eDMA1 channel 4 interrupt */
#define IMX9_IRQ_DMA3_5 (IMX9_IRQ_EXTINT + 100) /* eDMA1 channel 5 interrupt */
#define IMX9_IRQ_DMA3_6 (IMX9_IRQ_EXTINT + 101) /* eDMA1 channel 6 interrupt */
#define IMX9_IRQ_DMA3_7 (IMX9_IRQ_EXTINT + 102) /* eDMA1 channel 7 interrupt */
#define IMX9_IRQ_DMA3_8 (IMX9_IRQ_EXTINT + 103) /* eDMA1 channel 8 interrupt */
#define IMX9_IRQ_DMA3_9 (IMX9_IRQ_EXTINT + 104) /* eDMA1 channel 9 interrupt */
#define IMX9_IRQ_DMA3_10 (IMX9_IRQ_EXTINT + 105) /* eDMA1 channel 10 interrupt */
#define IMX9_IRQ_DMA3_11 (IMX9_IRQ_EXTINT + 106) /* eDMA1 channel 11 interrupt */
#define IMX9_IRQ_DMA3_12 (IMX9_IRQ_EXTINT + 107) /* eDMA1 channel 12 interrupt */
#define IMX9_IRQ_DMA3_13 (IMX9_IRQ_EXTINT + 108) /* eDMA1 channel 13 interrupt */
#define IMX9_IRQ_DMA3_14 (IMX9_IRQ_EXTINT + 109) /* eDMA1 channel 14 interrupt */
#define IMX9_IRQ_DMA3_15 (IMX9_IRQ_EXTINT + 110) /* eDMA1 channel 15 interrupt */
#define IMX9_IRQ_DMA3_16 (IMX9_IRQ_EXTINT + 111) /* eDMA1 channel 16 interrupt */
#define IMX9_IRQ_DMA3_17 (IMX9_IRQ_EXTINT + 112) /* eDMA1 channel 17 interrupt */
#define IMX9_IRQ_DMA3_18 (IMX9_IRQ_EXTINT + 113) /* eDMA1 channel 18 interrupt */
#define IMX9_IRQ_DMA3_19 (IMX9_IRQ_EXTINT + 114) /* eDMA1 channel 19 interrupt */
#define IMX9_IRQ_DMA3_20 (IMX9_IRQ_EXTINT + 115) /* eDMA1 channel 20 interrupt */
#define IMX9_IRQ_DMA3_21 (IMX9_IRQ_EXTINT + 116) /* eDMA1 channel 21 interrupt */
#define IMX9_IRQ_DMA3_22 (IMX9_IRQ_EXTINT + 117) /* eDMA1 channel 22 interrupt */
#define IMX9_IRQ_DMA3_23 (IMX9_IRQ_EXTINT + 118) /* eDMA1 channel 23 interrupt */
#define IMX9_IRQ_DMA3_24 (IMX9_IRQ_EXTINT + 119) /* eDMA1 channel 24 interrupt */
#define IMX9_IRQ_DMA3_25 (IMX9_IRQ_EXTINT + 120) /* eDMA1 channel 25 interrupt */
#define IMX9_IRQ_DMA3_26 (IMX9_IRQ_EXTINT + 121) /* eDMA1 channel 26 interrupt */
#define IMX9_IRQ_DMA3_27 (IMX9_IRQ_EXTINT + 122) /* eDMA1 channel 27 interrupt */
#define IMX9_IRQ_DMA3_28 (IMX9_IRQ_EXTINT + 123) /* eDMA1 channel 28 interrupt */
#define IMX9_IRQ_DMA3_29 (IMX9_IRQ_EXTINT + 124) /* eDMA1 channel 29 interrupt */
#define IMX9_IRQ_DMA3_30 (IMX9_IRQ_EXTINT + 125) /* eDMA1 channel 30 interrupt */
#define IMX9_IRQ_RESERVED158 (IMX9_IRQ_EXTINT + 126) /* Reserved interrupt */
#define IMX9_IRQ_DMA4_ERROR (IMX9_IRQ_EXTINT + 127) /* eDMA2 error interrupt */
#define IMX9_IRQ_DMA4_0_1 (IMX9_IRQ_EXTINT + 128) /* eDMA2 channel 0/1 interrupt */
#define IMX9_IRQ_DMA4_2_3 (IMX9_IRQ_EXTINT + 129) /* eDMA2 channel 2/3 interrupt */
#define IMX9_IRQ_DMA4_4_5 (IMX9_IRQ_EXTINT + 130) /* eDMA2 channel 4/5 interrupt */
#define IMX9_IRQ_DMA4_6_7 (IMX9_IRQ_EXTINT + 131) /* eDMA2 channel 6/7 interrupt */
#define IMX9_IRQ_DMA4_8_9 (IMX9_IRQ_EXTINT + 132) /* eDMA2 channel 8/9 interrupt */
#define IMX9_IRQ_DMA4_10_11 (IMX9_IRQ_EXTINT + 133) /* eDMA2 channel 10/11 interrupt */
#define IMX9_IRQ_DMA4_12_13 (IMX9_IRQ_EXTINT + 134) /* eDMA2 channel 12/13 interrupt */
#define IMX9_IRQ_DMA4_14_15 (IMX9_IRQ_EXTINT + 135) /* eDMA2 channel 14/15 interrupt */
#define IMX9_IRQ_DMA4_16_17 (IMX9_IRQ_EXTINT + 136) /* eDMA2 channel 16/17 interrupt */
#define IMX9_IRQ_DMA4_18_19 (IMX9_IRQ_EXTINT + 137) /* eDMA2 channel 18/19 interrupt */
#define IMX9_IRQ_DMA4_20_21 (IMX9_IRQ_EXTINT + 138) /* eDMA2 channel 20/21 interrupt */
#define IMX9_IRQ_DMA4_22_23 (IMX9_IRQ_EXTINT + 139) /* eDMA2 channel 22/23 interrupt */
#define IMX9_IRQ_DMA4_24_25 (IMX9_IRQ_EXTINT + 140) /* eDMA2 channel 24/25 interrupt */
#define IMX9_IRQ_DMA4_26_27 (IMX9_IRQ_EXTINT + 141) /* eDMA2 channel 26/27 interrupt */
#define IMX9_IRQ_DMA4_28_29 (IMX9_IRQ_EXTINT + 142) /* eDMA2 channel 28/29 interrupt */
#define IMX9_IRQ_DMA4_30_31 (IMX9_IRQ_EXTINT + 143) /* eDMA2 channel 30/31 interrupt */
#define IMX9_IRQ_DMA4_32_33 (IMX9_IRQ_EXTINT + 144) /* eDMA2 channel 32/33 interrupt */
#define IMX9_IRQ_DMA4_34_35 (IMX9_IRQ_EXTINT + 145) /* eDMA2 channel 34/35 interrupt */
#define IMX9_IRQ_DMA4_36_37 (IMX9_IRQ_EXTINT + 146) /* eDMA2 channel 36/37 interrupt */
#define IMX9_IRQ_DMA4_38_39 (IMX9_IRQ_EXTINT + 147) /* eDMA2 channel 38/39 interrupt */
#define IMX9_IRQ_DMA4_40_41 (IMX9_IRQ_EXTINT + 148) /* eDMA2 channel 40/41 interrupt */
#define IMX9_IRQ_DMA4_42_43 (IMX9_IRQ_EXTINT + 149) /* eDMA2 channel 42/43 interrupt */
#define IMX9_IRQ_DMA4_44_45 (IMX9_IRQ_EXTINT + 150) /* eDMA2 channel 44/45 interrupt */
#define IMX9_IRQ_DMA4_46_47 (IMX9_IRQ_EXTINT + 151) /* eDMA2 channel 46/47 interrupt */
#define IMX9_IRQ_DMA4_48_49 (IMX9_IRQ_EXTINT + 152) /* eDMA2 channel 48/49 interrupt */
#define IMX9_IRQ_DMA4_50_51 (IMX9_IRQ_EXTINT + 153) /* eDMA2 channel 50/51 interrupt */
#define IMX9_IRQ_DMA4_52_53 (IMX9_IRQ_EXTINT + 154) /* eDMA2 channel 52/53 interrupt */
#define IMX9_IRQ_DMA4_54_55 (IMX9_IRQ_EXTINT + 155) /* eDMA2 channel 54/55 interrupt */
#define IMX9_IRQ_DMA4_56_57 (IMX9_IRQ_EXTINT + 156) /* eDMA2 channel 56/57 interrupt */
#define IMX9_IRQ_DMA4_58_59 (IMX9_IRQ_EXTINT + 157) /* eDMA2 channel 58/59 interrupt */
#define IMX9_IRQ_DMA4_60_61 (IMX9_IRQ_EXTINT + 158) /* eDMA2 channel 60/61 interrupt */
#define IMX9_IRQ_DMA4_62_63 (IMX9_IRQ_EXTINT + 159) /* eDMA2 channel 62/63 interrupt */
#define IMX9_IRQ_RESERVED192 (IMX9_IRQ_EXTINT + 160) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED193 (IMX9_IRQ_EXTINT + 161) /* Edgelock Group 1 reset source */
#define IMX9_IRQ_RESERVED194 (IMX9_IRQ_EXTINT + 162) /* Edgelock Group 2 reset source */
#define IMX9_IRQ_RESERVED195 (IMX9_IRQ_EXTINT + 163) /* Edgelock Group 2 reset source */
#define IMX9_IRQ_RESERVED196 (IMX9_IRQ_EXTINT + 164) /* JTAGSW DAP MDM-AP SRC reset source */
#define IMX9_IRQ_RESERVED197 (IMX9_IRQ_EXTINT + 165) /* JTAGC SRC reset source */
#define IMX9_IRQ_RESERVED198 (IMX9_IRQ_EXTINT + 166) /* CM33 SYSREQRST SRC reset source */
#define IMX9_IRQ_RESERVED199 (IMX9_IRQ_EXTINT + 167) /* CM33 LOCKUP SRC reset source */
#define IMX9_IRQ_RESERVED200 (IMX9_IRQ_EXTINT + 168) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED201 (IMX9_IRQ_EXTINT + 169) /* Reserved interrupt */
#define IMX9_IRQ_SAI2 (IMX9_IRQ_EXTINT + 170) /* Serial Audio Interface 2 */
#define IMX9_IRQ_SAI3 (IMX9_IRQ_EXTINT + 171) /* Serial Audio Interface 3 */
#define IMX9_IRQ_ISI (IMX9_IRQ_EXTINT + 172) /* ISI interrupt */
#define IMX9_IRQ_RESERVED205 (IMX9_IRQ_EXTINT + 173) /* PXP interrupt 0 */
#define IMX9_IRQ_RESERVED206 (IMX9_IRQ_EXTINT + 174) /* PXP interrupt 1 */
#define IMX9_IRQ_CSI (IMX9_IRQ_EXTINT + 175) /* CSI interrupt */
#define IMX9_IRQ_RESERVED208 (IMX9_IRQ_EXTINT + 176) /* LCDIF Sync Interrupt */
#define IMX9_IRQ_DSI (IMX9_IRQ_EXTINT + 177) /* MIPI DSI Interrupt Request */
#define IMX9_IRQ_RESERVED210 (IMX9_IRQ_EXTINT + 178) /* Machine learning processor interrupt */
#define IMX9_IRQ_ENET_MAC0_RX_TX_D ONE1 (IMX9_IRQ_EXTINT + 179) /* MAC 0 Receive/ Transmit Frame/ Buffer Done */
#define IMX9_IRQ_ENET_MAC0_RX_TX_D ONE2 (IMX9_IRQ_EXTINT + 180) /* MAC 0 Receive/ Transmit Frame/ Buffer Done */
#define IMX9_IRQ_ENET (IMX9_IRQ_EXTINT + 181) /* MAC 0 IRQ */
#define IMX9_IRQ_ENET_1588 (IMX9_IRQ_EXTINT + 182) /* MAC 0 1588 Timer Interrupt - synchronous */
#define IMX9_IRQ_ENET_QOS_PMT (IMX9_IRQ_EXTINT + 183) /* ENET QOS PMT interrupt */
#define IMX9_IRQ_ENET_QOS (IMX9_IRQ_EXTINT + 184) /* ENET QOS interrupt */
#define IMX9_IRQ_RESERVED217 (IMX9_IRQ_EXTINT + 185) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED218 (IMX9_IRQ_EXTINT + 186) /* Reserved interrupt */
#define IMX9_IRQ_USB1 (IMX9_IRQ_EXTINT + 187) /* USB-1 Wake-up Interrupt */
#define IMX9_IRQ_USB2 (IMX9_IRQ_EXTINT + 188) /* USB-2 Wake-up Interrupt */
#define IMX9_IRQ_GPIO4_0 (IMX9_IRQ_EXTINT + 189) /* General Purpose Input/Output 4 interrupt 0 */
#define IMX9_IRQ_GPIO4_1 (IMX9_IRQ_EXTINT + 190) /* General Purpose Input/Output 4 interrupt 1 */
#define IMX9_IRQ_LPSPI5 (IMX9_IRQ_EXTINT + 191) /* Low Power Serial Peripheral Interface 5 */
#define IMX9_IRQ_LPSPI6 (IMX9_IRQ_EXTINT + 192) /* Low Power Serial Peripheral Interface 6 */
#define IMX9_IRQ_LPSPI7 (IMX9_IRQ_EXTINT + 193) /* Low Power Serial Peripheral Interface 7 */
#define IMX9_IRQ_LPSPI8 (IMX9_IRQ_EXTINT + 194) /* Low Power Serial Peripheral Interface 8 */
#define IMX9_IRQ_LPI2C5 (IMX9_IRQ_EXTINT + 195) /* Low Power Inter-Integrated Circuit module 5 */
#define IMX9_IRQ_LPI2C6 (IMX9_IRQ_EXTINT + 196) /* Low Power Inter-Integrated Circuit module 6 */
#define IMX9_IRQ_LPI2C7 (IMX9_IRQ_EXTINT + 197) /* Low Power Inter-Integrated Circuit module 7 */
#define IMX9_IRQ_LPI2C8 (IMX9_IRQ_EXTINT + 198) /* Low Power Inter-Integrated Circuit module 8 */
#define IMX9_IRQ_PDM_HWVAD_ERROR (IMX9_IRQ_EXTINT + 199) /* PDM interrupt */
#define IMX9_IRQ_PDM_HWVAD_EVENT (IMX9_IRQ_EXTINT + 200) /* PDM interrupt */
#define IMX9_IRQ_PDM_ERROR (IMX9_IRQ_EXTINT + 201) /* PDM interrupt */
#define IMX9_IRQ_PDM_EVENT (IMX9_IRQ_EXTINT + 202) /* PDM interrupt */
#define IMX9_IRQ_RESERVED235 (IMX9_IRQ_EXTINT + 203) /* AUDIO XCVR interrupt */
#define IMX9_IRQ_RESERVED236 (IMX9_IRQ_EXTINT + 204) /* AUDIO XCVR interrupt */
#define IMX9_IRQ_USDHC3 (IMX9_IRQ_EXTINT + 205) /* ultra Secure Digital Host Controller interrupt 3 */
#define IMX9_IRQ_RESERVED238 (IMX9_IRQ_EXTINT + 206) /* OCRAM MECC interrupt */
#define IMX9_IRQ_RESERVED239 (IMX9_IRQ_EXTINT + 207) /* OCRAM MECC interrupt */
#define IMX9_IRQ_RESERVED240 (IMX9_IRQ_EXTINT + 208) /* HSIOMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED241 (IMX9_IRQ_EXTINT + 209) /* MEDIAMIX TRDC transfer error interrupt */
#define IMX9_IRQ_LPUART7 (IMX9_IRQ_EXTINT + 210) /* Low Power UART 7 */
#define IMX9_IRQ_LPUART8 (IMX9_IRQ_EXTINT + 211) /* Low Power UART 8 */
#define IMX9_IRQ_RESERVED244 (IMX9_IRQ_EXTINT + 212) /* CM33 MCM interrupt */
#define IMX9_IRQ_RESERVED245 (IMX9_IRQ_EXTINT + 213) /* SFA interrupt */
#define IMX9_IRQ_RESERVED246 (IMX9_IRQ_EXTINT + 214) /* GIC600 INTERRUPT */
#define IMX9_IRQ_RESERVED247 (IMX9_IRQ_EXTINT + 215) /* GIC600 INTERRUPT */
#define IMX9_IRQ_RESERVED248 (IMX9_IRQ_EXTINT + 216) /* GIC600 INTERRUPT */
#define IMX9_IRQ_RESERVED249 (IMX9_IRQ_EXTINT + 217) /* ADC interrupt */
#define IMX9_IRQ_RESERVED250 (IMX9_IRQ_EXTINT + 218) /* ADC interrupt */
#define IMX9_IRQ_RESERVED251 (IMX9_IRQ_EXTINT + 219) /* ADC interrupt */
#define IMX9_IRQ_RESERVED252 (IMX9_IRQ_EXTINT + 220) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED253 (IMX9_IRQ_EXTINT + 221) /* I3C1 wakeup irq after double sync */
#define IMX9_IRQ_RESERVED254 (IMX9_IRQ_EXTINT + 222) /* I3C2 wakeup irq after double sync */
#define IMX9_IRQ_RESERVED255 (IMX9_IRQ_EXTINT + 223) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED256 (IMX9_IRQ_EXTINT + 224) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED257 (IMX9_IRQ_EXTINT + 225) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED258 (IMX9_IRQ_EXTINT + 226) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED259 (IMX9_IRQ_EXTINT + 227) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED260 (IMX9_IRQ_EXTINT + 228) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED261 (IMX9_IRQ_EXTINT + 229) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED262 (IMX9_IRQ_EXTINT + 230) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED263 (IMX9_IRQ_EXTINT + 231) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED264 (IMX9_IRQ_EXTINT + 232) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED265 (IMX9_IRQ_EXTINT + 233) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED266 (IMX9_IRQ_EXTINT + 234) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED267 (IMX9_IRQ_EXTINT + 235) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED268 (IMX9_IRQ_EXTINT + 236) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED269 (IMX9_IRQ_EXTINT + 237) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED270 (IMX9_IRQ_EXTINT + 238) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED271 (IMX9_IRQ_EXTINT + 239) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED272 (IMX9_IRQ_EXTINT + 240) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED273 (IMX9_IRQ_EXTINT + 241) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED274 (IMX9_IRQ_EXTINT + 242) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED275 (IMX9_IRQ_EXTINT + 243) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED276 (IMX9_IRQ_EXTINT + 244) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED277 (IMX9_IRQ_EXTINT + 245) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED278 (IMX9_IRQ_EXTINT + 246) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED279 (IMX9_IRQ_EXTINT + 247) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED280 (IMX9_IRQ_EXTINT + 248) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED281 (IMX9_IRQ_EXTINT + 249) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED282 (IMX9_IRQ_EXTINT + 250) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED283 (IMX9_IRQ_EXTINT + 251) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED284 (IMX9_IRQ_EXTINT + 252) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED285 (IMX9_IRQ_EXTINT + 253) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED286 (IMX9_IRQ_EXTINT + 254) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED287 (IMX9_IRQ_EXTINT + 255) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED288 (IMX9_IRQ_EXTINT + 256) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED289 (IMX9_IRQ_EXTINT + 257) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED290 (IMX9_IRQ_EXTINT + 258) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED291 (IMX9_IRQ_EXTINT + 259) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED292 (IMX9_IRQ_EXTINT + 260) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED293 (IMX9_IRQ_EXTINT + 261) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED294 (IMX9_IRQ_EXTINT + 262) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED295 (IMX9_IRQ_EXTINT + 263) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED296 (IMX9_IRQ_EXTINT + 264) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED297 (IMX9_IRQ_EXTINT + 265) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED298 (IMX9_IRQ_EXTINT + 266) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED299 (IMX9_IRQ_EXTINT + 267) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED300 (IMX9_IRQ_EXTINT + 268) /* ADC Asynchronous Interrupt */
#define IMX9_IRQ_NEXTINT (268)
/* Total amount of entries in system vector table */
#define NR_IRQS (IMX9_IRQ_EXTINT + IMX9_IRQ_NEXTINT)
#define ARMV8M_PERIPHERAL_INTERRUPTS (IMX9_IRQ_NEXTINT)
#endif /* __ARCH_ARM_INCLUDE_IMX9_IMX93_IRQ_H */
arch/arm/include/imx9/irq.h
+2
View File
@@ -36,6 +36,8 @@
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include <arch/imx9/imx95_irq.h>
#elif defined(CONFIG_ARCH_CHIP_IMX93_M33)
# include <arch/imx9/imx93_irq.h>
#else
# error "Unrecognized i.MX9 architecture"
#endif
arch/arm/src/imx9/CMakeLists.txt
+6
View File
@@ -33,12 +33,18 @@ set(SRCS
if(CONFIG_IMX9_SCMI)
list(APPEND SRCS imx9_scmi.c)
# NXP SDK SCMI interface for pinctrl and clocking
else()
list(APPEND SRCS imx9_ccm.c)
endif()
if(CONFIG_RPTUN)
list(APPEND SRCS imx9_rsctable.c imx9_rptun.c)
endif()
if(CONFIG_IMX9_XCACHE)
list(APPEND SRCS imx9_xcache.c)
endif()
if(CONFIG_IMX9_MU)
list(APPEND SRCS imx9_mu.c)
endif()
arch/arm/src/imx9/Kconfig
+39
View File
@@ -19,6 +19,13 @@ config ARCH_CHIP_IMX95_M7
select ARMV7M_HAVE_DTCM
select IMX9_HAVE_MU
config ARCH_CHIP_IMX93_M33
bool "i.MX93 Cortex-M33 Processor"
select ARCH_CORTEXM33
select ARMV8M_HAVE_ITCM
select ARMV8M_HAVE_DTCM
select IMX9_HAVE_MU
endchoice # i.MX9 Core Selection
config IMX9_HAVE_MU
@@ -30,6 +37,24 @@ config IMX9_SCMI
default y
depends on IMX9_MU5
config IMX9_XCACHE
bool
default n
config IMX9_LPCAC_PC
bool "Low Power Cache - Program Cache (ICACHE)"
default n
depends on ARCH_CHIP_IMX93_M33
select ARCH_ICACHE
select IMX9_XCACHE
config IMX9_LPCAC_PS
bool "Low Power Cache - Peripheral System (DCACHE)"
default n
depends on ARCH_CHIP_IMX93_M33
select ARCH_DCACHE
select IMX9_XCACHE
if IMX9_SCMI
config IMX9_CLK_OVER_SCMI
@@ -996,6 +1021,20 @@ menuconfig IMX9_MU
if IMX9_MU
config IMX9_MU1
bool "MU1 M33 <-> A55"
default y
depends on ARCH_CHIP_IMX93_M33
---help---
Enable mailbox 1 that operates between M33 and A55 cores
config IMX9_MU2
bool "MU2 M33 <-> A55"
default n
depends on ARCH_CHIP_IMX93_M33
---help---
Enable mailbox 2 that operates between M33 and A55 cores
config IMX9_MU5
bool "MU5 M7 <-> M33"
default y
arch/arm/src/imx9/Make.defs
+11 -1
View File
@@ -21,7 +21,11 @@
#
############################################################################
include armv7-m/Make.defs
ifeq ($(CONFIG_ARCH_ARMV7M),y)
include armv7-m/Make.defs
else ifeq ($(CONFIG_ARCH_ARMV8M),y)
include armv8-m/Make.defs
endif
# i.MX9-specific C source files
@@ -30,6 +34,12 @@ CHIP_CSRCS = imx9_allocateheap.c imx9_start.c imx9_clockconfig.c imx9_gpio.c imx
ifeq ($(CONFIG_IMX9_SCMI),y)
CHIP_CSRCS += imx9_scmi.c
# NXP SDK SCMI interface for pinctrl and clocking
else
CHIP_CSRCS += imx9_ccm.c
endif
ifeq ($(CONFIG_IMX9_XCACHE),y)
CHIP_CSRCS += imx9_xcache.c
endif
ifeq ($(CONFIG_RPTUN),y)
arch/arm/src/imx9/hardware/imx93/imx93_ccm.h
+751
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/imx9/hardware/imx93/imx93_clock.h
+549
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/imx9/hardware/imx93/imx93_dmamux.h
+211
View File
@@ -0,0 +1,211 @@
/****************************************************************************
* arch/arm/src/imx9/hardware/imx93/imx93_dmamux.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_DMAMUX_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_DMAMUX_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "imx93_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Identify channel MUX from 9th bit */
#define EDMA3_MUX_ID 0x0000
#define EDMA4_MUX_ID 0x0100
#define EDMA_MUX_ID_MASK 0xff00
#define EDMA_MUX_MASK 0x00ff
/* eDMA3 MUXs */
#define DMA_REQUEST_DISABLED (0) /**< Channel disabled */
#define DMA_REQUEST_MUXCAN1 (1 | EDMA3_MUX_ID) /**< CAN1 */
#define DMA_REQUEST_MUXGPIO1_0 (3 | EDMA3_MUX_ID) /**< GPIO1 channel 0 */
#define DMA_REQUEST_MUXGPIO1_1 (4 | EDMA3_MUX_ID) /**< GPIO1 channel 1 */
#define DMA_REQUEST_MUXI3C1TOBUS (5 | EDMA3_MUX_ID) /**< I3C1 To-bus Request */
#define DMA_REQUEST_MUXI3C1FROMBUS (6 | EDMA3_MUX_ID) /**< I3C1 From-bus Request */
#define DMA_REQUEST_MUXLPI2C1TX (7 | EDMA3_MUX_ID) /**< LPI2C1 */
#define DMA_REQUEST_MUXLPI2C1RX (8 | EDMA3_MUX_ID) /**< LPI2C1 */
#define DMA_REQUEST_MUXLPI2C2TX (9 | EDMA3_MUX_ID) /**< LPI2C2 */
#define DMA_REQUEST_MUXLPI2C2RX (10 | EDMA3_MUX_ID) /**< LPI2C2 */
#define DMA_REQUEST_MUXLPSPI1TX (11 | EDMA3_MUX_ID) /**< LPSPI1 Transmit */
#define DMA_REQUEST_MUXLPSPI1RX (12 | EDMA3_MUX_ID) /**< LPSPI1 Receive */
#define DMA_REQUEST_MUXLPSPI2TX (13 | EDMA3_MUX_ID) /**< LPSPI2 Transmit */
#define DMA_REQUEST_MUXLPSPI2RX (14 | EDMA3_MUX_ID) /**< LPSPI2 Receive */
#define DMA_REQUEST_MUXLPTMR1 (15 | EDMA3_MUX_ID) /**< LPTMR1 Request */
#define DMA_REQUEST_MUXLPUART1TX (16 | EDMA3_MUX_ID) /**< LPUART1 Transmit */
#define DMA_REQUEST_MUXLPUART1RX (17 | EDMA3_MUX_ID) /**< LPUART1 Receive */
#define DMA_REQUEST_MUXLPUART2TX (18 | EDMA3_MUX_ID) /**< LPUART2 Transmit */
#define DMA_REQUEST_MUXLPUART2RX (19 | EDMA3_MUX_ID) /**< LPUART2 Receive */
#define DMA_REQUEST_MUXEDGELOCK (20 | EDMA3_MUX_ID) /**< Edgelock enclave DMA Request */
#define DMA_REQUEST_MUXSAI1TX (21 | EDMA3_MUX_ID) /**< SAI1 Transmit */
#define DMA_REQUEST_MUXSAI1RX (22 | EDMA3_MUX_ID) /**< SAI1 Receive */
#define DMA_REQUEST_MUXTPM1_0_2 (23 | EDMA3_MUX_ID) /**< TPM1 request 0 and request 2 */
#define DMA_REQUEST_MUXTPM1_1_3 (24 | EDMA3_MUX_ID) /**< TPM1 request 1 and request 3 */
#define DMA_REQUEST_MUXTPM1OVERFLOW (25 | EDMA3_MUX_ID) /**< TPM1 Overflow request */
#define DMA_REQUEST_MUXTPM2_0_2 (26 | EDMA3_MUX_ID) /**< TPM2 request 0 and request 2 */
#define DMA_REQUEST_MUXTPM2_1_3 (27 | EDMA3_MUX_ID) /**< TPM2 request 1 and request 3 */
#define DMA_REQUEST_MUXTPM2OVERFLOW (28 | EDMA3_MUX_ID) /**< TPM2 Overflow request */
#define DMA_REQUEST_MUXPDM (29 | EDMA3_MUX_ID) /**< PDM */
#define DMA_REQUEST_MUXADC1 (30 | EDMA3_MUX_ID) /**< ADC1 */
#define DMA3_REQUEST_MUX_COUNT (31)
/* eDMA4 MUXs */
#define DMA_REQUEST_MUXCAN2 (1 | EDMA4_MUX_ID) /**< CAN2 */
#define DMA_REQUEST_MUXGPIO2_0 (2 | EDMA4_MUX_ID) /**< GPIO2 channel 0 */
#define DMA_REQUEST_MUXGPIO2_1 (3 | EDMA4_MUX_ID) /**< GPIO2 channel 1 */
#define DMA_REQUEST_MUXGPIO3_0 (4 | EDMA4_MUX_ID) /**< GPIO3 channel 0 */
#define DMA_REQUEST_MUXGPIO3_1 (5 | EDMA4_MUX_ID) /**< GPIO3 channel 1 */
#define DMA_REQUEST_MUXI3C2TOBUS (6 | EDMA4_MUX_ID) /**< I3C2 To-bus Request */
#define DMA_REQUEST_MUXI3C2FROMBUS (7 | EDMA4_MUX_ID) /**< I3C2 From-bus Request */
#define DMA_REQUEST_MUXLPI2C3TX (8 | EDMA4_MUX_ID) /**< LPI2C3 */
#define DMA_REQUEST_MUXLPI2C3RX (9 | EDMA4_MUX_ID) /**< LPI2C3 */
#define DMA_REQUEST_MUXLPI2C4TX (10 | EDMA4_MUX_ID) /**< LPI2C4 */
#define DMA_REQUEST_MUXLPI2C4RX (11 | EDMA4_MUX_ID) /**< LPI2C4 */
#define DMA_REQUEST_MUXLPSPI3TX (12 | EDMA4_MUX_ID) /**< LPSPI3 Transmit */
#define DMA_REQUEST_MUXLPSPI3RX (13 | EDMA4_MUX_ID) /**< LPSPI3 Receive */
#define DMA_REQUEST_MUXLPSPI4TX (14 | EDMA4_MUX_ID) /**< LPSPI4 Transmit */
#define DMA_REQUEST_MUXLPSPI4RX (15 | EDMA4_MUX_ID) /**< LPSPI4 Receive */
#define DMA_REQUEST_MUXLPTMR2 (16 | EDMA4_MUX_ID) /**< LPTMR2 Request */
#define DMA_REQUEST_MUXLPUART3TX (17 | EDMA4_MUX_ID) /**< LPUART3 Transmit */
#define DMA_REQUEST_MUXLPUART3RX (18 | EDMA4_MUX_ID) /**< LPUART3 Receive */
#define DMA_REQUEST_MUXLPUART4TX (19 | EDMA4_MUX_ID) /**< LPUART4 Transmit */
#define DMA_REQUEST_MUXLPUART4RX (20 | EDMA4_MUX_ID) /**< LPUART4 Receive */
#define DMA_REQUEST_MUXLPUART5TX (21 | EDMA4_MUX_ID) /**< LPUART5 Transmit */
#define DMA_REQUEST_MUXLPUART5RX (22 | EDMA4_MUX_ID) /**< LPUART5 Receive */
#define DMA_REQUEST_MUXLPUART6TX (23 | EDMA4_MUX_ID) /**< LPUART6 Transmit */
#define DMA_REQUEST_MUXLPUART6RX (24 | EDMA4_MUX_ID) /**< LPUART6 Receive */
#define DMA_REQUEST_MUXTPM3_0_2 (25 | EDMA4_MUX_ID) /**< TPM3 request 0 and request 2 */
#define DMA_REQUEST_MUXTPM3_1_3 (26 | EDMA4_MUX_ID) /**< TPM3 request 1 and request 3 */
#define DMA_REQUEST_MUXTPM3OVERFLOW (27 | EDMA4_MUX_ID) /**< TPM3 Overflow request */
#define DMA_REQUEST_MUXTPM4_0_2 (28 | EDMA4_MUX_ID) /**< TPM4 request 0 and request 2 */
#define DMA_REQUEST_MUXTPM4_1_3 (29 | EDMA4_MUX_ID) /**< TPM4 request 1 and request 3 */
#define DMA_REQUEST_MUXTPM4OVERFLOW (30 | EDMA4_MUX_ID) /**< TPM4 Overflow request */
#define DMA_REQUEST_MUXTPM5_0_2 (31 | EDMA4_MUX_ID) /**< TPM5 request 0 and request 2 */
#define DMA_REQUEST_MUXTPM5_1_3 (32 | EDMA4_MUX_ID) /**< TPM5 request 1 and request 3 */
#define DMA_REQUEST_MUXTPM5OVERFLOW (33 | EDMA4_MUX_ID) /**< TPM5 Overflow request */
#define DMA_REQUEST_MUXTPM6_0_2 (34 | EDMA4_MUX_ID) /**< TPM6 request 0 and request 2 */
#define DMA_REQUEST_MUXTPM6_1_3 (35 | EDMA4_MUX_ID) /**< TPM6 request 1 and request 3 */
#define DMA_REQUEST_MUXTPM6OVERFLOW (36 | EDMA4_MUX_ID) /**< TPM6 Overflow request */
#define DMA_REQUEST_MUXFLEXIO1_0 (37 | EDMA4_MUX_ID) /**< FlexIO1 Request0 */
#define DMA_REQUEST_MUXFLEXIO1_1 (38 | EDMA4_MUX_ID) /**< FlexIO1 Request1 */
#define DMA_REQUEST_MUXFLEXIO1_2 (39 | EDMA4_MUX_ID) /**< FlexIO1 Request2 */
#define DMA_REQUEST_MUXFLEXIO1_3 (40 | EDMA4_MUX_ID) /**< FlexIO1 Request3 */
#define DMA_REQUEST_MUXFLEXIO1_4 (41 | EDMA4_MUX_ID) /**< FlexIO1 Request4 */
#define DMA_REQUEST_MUXFLEXIO1_5 (42 | EDMA4_MUX_ID) /**< FlexIO1 Request5 */
#define DMA_REQUEST_MUXFLEXIO1_6 (43 | EDMA4_MUX_ID) /**< FlexIO1 Request6 */
#define DMA_REQUEST_MUXFLEXIO1_7 (44 | EDMA4_MUX_ID) /**< FlexIO1 Request7 */
#define DMA_REQUEST_MUXFLEXIO2_0 (45 | EDMA4_MUX_ID) /**< FlexIO2 Request0 */
#define DMA_REQUEST_MUXFLEXIO2_1 (46 | EDMA4_MUX_ID) /**< FlexIO2 Request1 */
#define DMA_REQUEST_MUXFLEXIO2_2 (47 | EDMA4_MUX_ID) /**< FlexIO2 Request2 */
#define DMA_REQUEST_MUXFLEXIO2_3 (48 | EDMA4_MUX_ID) /**< FlexIO2 Request3 */
#define DMA_REQUEST_MUXFLEXIO2_4 (49 | EDMA4_MUX_ID) /**< FlexIO2 Request4 */
#define DMA_REQUEST_MUXFLEXIO2_5 (50 | EDMA4_MUX_ID) /**< FlexIO2 Request5 */
#define DMA_REQUEST_MUXFLEXIO2_6 (51 | EDMA4_MUX_ID) /**< FlexIO2 Request6 */
#define DMA_REQUEST_MUXFLEXIO2_7 (52 | EDMA4_MUX_ID) /**< FlexIO2 Request7 */
#define DMA_REQUEST_MUXFLEXSPI1TX (53 | EDMA4_MUX_ID) /**< FlexSPI1 Transmit */
#define DMA_REQUEST_MUXFLEXSPI1RX (54 | EDMA4_MUX_ID) /**< FlexSPI1 Receive */
#define DMA_REQUEST_MUXSAI2TX (58 | EDMA4_MUX_ID) /**< SAI2 Transmit */
#define DMA_REQUEST_MUXSAI2RX (59 | EDMA4_MUX_ID) /**< SAI2 Receive */
#define DMA_REQUEST_MUXSAI3TX (60 | EDMA4_MUX_ID) /**< SAI3 Transmit */
#define DMA_REQUEST_MUXSAI3RX (61 | EDMA4_MUX_ID) /**< SAI3 Receive */
#define DMA_REQUEST_MUXGPIO4_0 (62 | EDMA4_MUX_ID) /**< GPIO4 channel 0 */
#define DMA_REQUEST_MUXGPIO4_1 (63 | EDMA4_MUX_ID) /**< GPIO4 channel 1 */
#define DMA_REQUEST_MUXSPDIF (65 | EDMA4_MUX_ID) /**< SPDIF */
#define DMA_REQUEST_MUXSPDIF_1 (66 | EDMA4_MUX_ID) /**< SPDIF */
#define DMA_REQUEST_MUXENET (67 | EDMA4_MUX_ID) /**< ENET */
#define DMA_REQUEST_MUXENET_1 (68 | EDMA4_MUX_ID) /**< ENET */
#define DMA_REQUEST_MUXENET_2 (69 | EDMA4_MUX_ID) /**< ENET */
#define DMA_REQUEST_MUXENET_3 (70 | EDMA4_MUX_ID) /**< ENET */
#define DMA_REQUEST_MUXLPI2C5TX (71 | EDMA4_MUX_ID) /**< LPI2C5 */
#define DMA_REQUEST_MUXLPI2C5RX (72 | EDMA4_MUX_ID) /**< LPI2C5 */
#define DMA_REQUEST_MUXLPI2C6TX (73 | EDMA4_MUX_ID) /**< LPI2C6 */
#define DMA_REQUEST_MUXLPI2C6RX (74 | EDMA4_MUX_ID) /**< LPI2C6 */
#define DMA_REQUEST_MUXLPI2C7TX (75 | EDMA4_MUX_ID) /**< LPI2C7 */
#define DMA_REQUEST_MUXLPI2C7RX (76 | EDMA4_MUX_ID) /**< LPI2C7 */
#define DMA_REQUEST_MUXLPI2C8TX (77 | EDMA4_MUX_ID) /**< LPI2C8 */
#define DMA_REQUEST_MUXLPI2C8RX (78 | EDMA4_MUX_ID) /**< LPI2C8 */
#define DMA_REQUEST_MUXLPSPI5TX (79 | EDMA4_MUX_ID) /**< LPSPI5 Transmit */
#define DMA_REQUEST_MUXLPSPI5RX (80 | EDMA4_MUX_ID) /**< LPSPI5 Receive */
#define DMA_REQUEST_MUXLPSPI6TX (81 | EDMA4_MUX_ID) /**< LPSPI6 Transmit */
#define DMA_REQUEST_MUXLPSPI6RX (82 | EDMA4_MUX_ID) /**< LPSPI6 Receive */
#define DMA_REQUEST_MUXLPSPI7TX (83 | EDMA4_MUX_ID) /**< LPSPI7 Transmit */
#define DMA_REQUEST_MUXLPSPI7RX (84 | EDMA4_MUX_ID) /**< LPSPI7 Receive */
#define DMA_REQUEST_MUXLPSPI8TX (85 | EDMA4_MUX_ID) /**< LPSPI8 Transmit */
#define DMA_REQUEST_MUXLPSPI8RX (86 | EDMA4_MUX_ID) /**< LPSPI8 Receive */
#define DMA_REQUEST_MUXLPUART7TX (87 | EDMA4_MUX_ID) /**< LPUART7 Transmit */
#define DMA_REQUEST_MUXLPUART7RX (88 | EDMA4_MUX_ID) /**< LPUART7 Receive */
#define DMA_REQUEST_MUXLPUART8TX (89 | EDMA4_MUX_ID) /**< LPUART8 Transmit */
#define DMA_REQUEST_MUXLPUART8RX (90 | EDMA4_MUX_ID) /**< LPUART8 Receive */
#define DMA_REQUEST_MUXENET_QOS (91 | EDMA4_MUX_ID) /**< ENET_QOS */
#define DMA_REQUEST_MUXENET_QOS_1 (92 | EDMA4_MUX_ID) /**< ENET_QOS */
#define DMA_REQUEST_MUXENET_QOS_2 (93 | EDMA4_MUX_ID) /**< ENET_QOS */
#define DMA_REQUEST_MUXENET_QOS_3 (94 | EDMA4_MUX_ID) /**< ENET_QOS */
#define DMA4_REQUEST_MUX_COUNT (95)
/* Combined MUX count (eDMA3 and eDMA4) */
#define DMA_REQUEST_MUX_COUNT (DMA3_REQUEST_MUX_COUNT + DMA4_REQUEST_MUX_COUNT)
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_dmamux_get_dmabase
*
* Description:
* Get DMA engine base address from MUX identifier.
*
* Input Parameters:
* dmamux - The DMA MUX identifier.
*
* Returned Value:
* Base address of the associated DMA engine.
*
****************************************************************************/
static inline uintptr_t imx9_dmamux_get_dmabase(uint16_t dmamux)
{
if ((dmamux & EDMA_MUX_ID_MASK) == EDMA3_MUX_ID)
{
return IMX9_DMA3_BASE;
}
else
{
return IMX9_DMA4_BASE;
}
}
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_DMAMUX_H */
arch/arm/src/imx9/hardware/imx93/imx93_edma.h
+438
View File
@@ -0,0 +1,438 @@
/****************************************************************************
* arch/arm/src/imx9/hardware/imx93/imx93_edma.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_EDMA_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_EDMA_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdint.h>
#include "imx93_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* eDMA3 / eDMA4 Register Offsets */
#define IMX9_EDMA_CSR_OFFSET (0x000000) /* Management Page Control Register (CSR) */
#define IMX9_EDMA_ES_OFFSET (0x000004) /* Management Page Error Status Register (ES) */
#define IMX9_EDMA_CH_GRPRI_OFFSET(n) (0x000100 + ((n) << 2)) /* Channel n Arbitration Group Register (CHn_GRPRI) */
/* eDMA3 only */
#define IMX9_EDMA_INT_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT) */
#define IMX9_EDMA_HRS_OFFSET (0x00000c) /* Management Page Hardware Request Status Register (HRS) */
/* eDMA4 only */
#define IMX9_EDMA_INT_LOW_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT_LOW) */
#define IMX9_EDMA_INT_HIGH_OFFSET (0x00000c) /* Management Page Interrupt Request Status Register (INT_HIGH) */
#define IMX9_EDMA_HRS_LOW_OFFSET (0x000010) /* Management Page Hardware Request Status Register (HRS_LOW) */
#define IMX9_EDMA_HRS_HIGH_OFFSET (0x000014) /* Management Page Hardware Request Status Register (HRS_HIGH) */
/* eDMA3 / eDMA4 Register Addresses */
#define IMX9_EDMA_CSR(n) ((n) + IMX9_EDMA_CSR_OFFSET)
#define IMX9_EDMA_ES(n) ((n) + IMX9_EDMA_ES_OFFSET)
#define IMX9_EDMA_CH_GRPRI(n,c) ((n) + IMX9_EDMA_CH_GRPRI_OFFSET(n))
/* eDMA3 only */
#define IMX9_EDMA_INT (IMX9_DMA3_BASE + IMX9_EDMA_INT_OFFSET)
#define IMX9_EDMA_HRS (IMX9_DMA3_BASE + IMX9_EDMA_HRS_OFFSET)
/* eDMA4 only */
#define IMX9_EDMA_INT_LOW (IMX9_DMA4_BASE + IMX9_EDMA_INT_LOW_OFFSET)
#define IMX9_EDMA_INT_HIGH (IMX9_DMA4_BASE + IMX9_EDMA_INT_HIGH_OFFSET)
#define IMX9_EDMA_HRS_LOW (IMX9_DMA4_BASE + IMX9_EDMA_HRS_LOW_OFFSET)
#define IMX9_EDMA_HRS_HIGH (IMX9_DMA4_BASE + IMX9_EDMA_HRS_HIGH_OFFSET)
/* eDMA Transfer Control Descriptor (TCD) Register Offsets */
#define IMX9_EDMA_CH_CSR_OFFSET (0x000000) /* Channel Control and Status Register (CH0_CSR) */
#define IMX9_EDMA_CH_ES_OFFSET (0x000004) /* Channel Error Status Register (CH0_ES) */
#define IMX9_EDMA_CH_INT_OFFSET (0x000008) /* Channel Interrupt Status Register (CH0_INT) */
#define IMX9_EDMA_CH_SBR_OFFSET (0x00000c) /* Channel System Bus Register (CH0_SBR) */
#define IMX9_EDMA_CH_PRI_OFFSET (0x000010) /* Channel Priority Register (CH0_PRI) */
#define IMX9_EDMA_CH_MUX_OFFSET (0x000014) /* Channel Multiplexor Configuration (CH0_MUX) (eDMA4 only) */
#define IMX9_EDMA_CH_MATTR_OFFSET (0x000018) /* Memory Attributes Register (CH0_MATTR) (eDMA4 only) */
#define IMX9_EDMA_TCD_SADDR_OFFSET (0x000020) /* TCD Source Address Register (TCD0_SADDR) */
#define IMX9_EDMA_TCD_SOFF_OFFSET (0x000024) /* TCD Signed Source Address Offset Register (TCD0_SOFF) */
#define IMX9_EDMA_TCD_ATTR_OFFSET (0x000026) /* TCD Transfer Attributes (TCD0_ATTR) */
#define IMX9_EDMA_TCD_NBYTES_OFFSET (0x000028) /* TCD Transfer Size (TCD0_NBYTES) */
#define IMX9_EDMA_TCD_SLAST_SDA_OFFSET (0x00002c) /* TCD Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
#define IMX9_EDMA_TCD_DADDR_OFFSET (0x000030) /* TCD Destination Address Register (TCD0_DADDR) */
#define IMX9_EDMA_TCD_DOFF_OFFSET (0x000034) /* TCD Signed Destination Address Offset Register (TCD0_DOFF) */
#define IMX9_EDMA_TCD_CITER_OFFSET (0x000036) /* TCD Current Major Loop Count Register (TCD0_CITER) */
#define IMX9_EDMA_TCD_DLAST_SGA_OFFSET (0x000038) /* TCD Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
#define IMX9_EDMA_TCD_CSR_OFFSET (0x00003c) /* TCD Control and Status Register (TCD0_CSR) */
#define IMX9_EDMA_TCD_BITER_OFFSET (0x00003e) /* TCD Beginning Major Loop Count Register (TCD0_BITER) */
/* eDMA 3 and eDMA 4 have TCD instance offsets, but same base offset */
#define IMX9_EDMA_TCD_BASE_OFFSET (0x10000) /* Offset to TCD for both eDMA3/4 */
#define IMX9_EDMA3_TCD_INST_OFFSET (0x10000) /* Per instance TCD offset for eDMA3 */
#define IMX9_EDMA4_TCD_INST_OFFSET (0x8000) /* Per instance TCD offset for eDMA4 */
#define IMX9_EDMA_TCD_BASE(n) ((n) + IMX9_EDMA_TCD_BASE_OFFSET)
#define IMX9_EDMA_TCD_INST_OFFSET(n) ((n) == IMX9_DMA3_BASE ? IMX9_EDMA3_TCD_INST_OFFSET : IMX9_EDMA4_TCD_INST_OFFSET)
#define IMX9_EDMA_TCD(n,t) (IMX9_EDMA_TCD_BASE(n) + (t) * IMX9_EDMA_TCD_INST_OFFSET(n))
/* eDMA Transfer Control Descriptor (TCD) Register Addresses ****************/
#define IMX9_EDMA_CH_CSR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_CSR_OFFSET)
#define IMX9_EDMA_CH_ES(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_ES_OFFSET)
#define IMX9_EDMA_CH_INT(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_INT_OFFSET)
#define IMX9_EDMA_CH_SBR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_SBR_OFFSET)
#define IMX9_EDMA_CH_PRI(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_PRI_OFFSET)
#define IMX9_EDMA_CH_MUX(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_MUX_OFFSET)
#define IMX9_EDMA_TCD_SADDR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_SADDR_OFFSET)
#define IMX9_EDMA_TCD_SOFF(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_SOFF_OFFSET)
#define IMX9_EDMA_TCD_ATTR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_ATTR_OFFSET)
#define IMX9_EDMA_TCD_NBYTES(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_NBYTES_OFFSET)
#define IMX9_EDMA_TCD_SLAST_SDA(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_SLAST_SDA_OFFSET)
#define IMX9_EDMA_TCD_DADDR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_DADDR_OFFSET)
#define IMX9_EDMA_TCD_DOFF(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_DOFF_OFFSET)
#define IMX9_EDMA_TCD_CITER(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_CITER_OFFSET)
#define IMX9_EDMA_TCD_DLAST_SGA(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_DLAST_SGA_OFFSET)
#define IMX9_EDMA_TCD_CSR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_CSR_OFFSET)
#define IMX9_EDMA_TCD_BITER(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_BITER_OFFSET)
/* eDMA Register Bitfield Definitions ***************************************/
/* Management Page Control Register (CSR) */
/* Bit 0: Reserved */
#define EDMA_CSR_EDBG (1 << 1) /* Bit 1: Enable Debug (EDBG) */
#define EDMA_CSR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration (ERCA) */
/* Bit 3: Reserved */
#define EDMA_CSR_HAE (1 << 4) /* Bit 4: Halt After Error (HAE) */
#define EDMA_CSR_HALT (1 << 5) /* Bit 5: Halt DMA Operations (HALT) */
#define EDMA_CSR_GCLC (1 << 6) /* Bit 6: Global Channel Linking Control (GCLC) */
#define EDMA_CSR_GMRC (1 << 7) /* Bit 7: Global Master ID Replication Control (GMRC) */
#define EDMA_CSR_ECX (1 << 8) /* Bit 8: Cancel Transfer With Error (ECX) */
#define EDMA_CSR_CX (1 << 9) /* Bit 9: Cancel Transfer (CX) */
/* Bits 10-23: Reserved */
#define EDMA_CSR_ACTIVE_ID_SHIFT (24) /* Bits 24-28: Active Channel ID (ACTIVE_ID) */
#define EDMA_CSR_ACTIVE_ID_MASK (0x1f << EDMA_CSR_ACTIVE_ID_SHIFT)
/* Bits 29-30: Reserved */
#define EDMA_CSR_ACTIVE (1 << 31) /* Bit 31: DMA Active Status (ACTIVE) */
/* Management Page Error Status Register (ES) */
#define EDMA_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
#define EDMA_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
#define EDMA_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
#define EDMA_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
#define EDMA_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
#define EDMA_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
#define EDMA_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
#define EDMA_ES_ECX (1 << 8) /* Bit 8: Transfer Canceled (ECX) */
/* Bits 9-23: Reserved */
#define EDMA_ES_ERRCHN_SHIFT (24) /* Bits 24-28: Error Channel Number or Canceled Channel Number (ERRCHN) */
#define EDMA_ES_ERRCHN_MASK (0x1f << EDMA_ES_ERRCHN_SHIFT)
/* Bits 29-30: Reserved */
#define EDMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status fields (VALID) */
/* Management Page Interrupt Request Status Register (INT) */
#define EDMA_INT(n) (1 << (n)) /* Bit n: Interrupt Request Status (INT) */
/* Management Page Hardware Request Status Register (HRS) */
#define EDMA_HRS(n) (1 << (n)) /* Bit n: Hardware Request Status (HRS) */
/* Channel n Arbitration Group Register (CHn_GRPRI) */
#define EDMA_CH_GRPRI_SHIFT (0) /* Bits 0-4: Arbitration Group For Channel n (GRPRI) */
#define EDMA_CH_GRPRI_MASK (0x1f << EDMA_CH_GRPRI_SHIFT)
/* Bits 5-31: Reserved */
/* eDMA Transfer Control Descriptor (TCD) Bitfield Definitions **************/
/* Channel n Control and Status Register (CHn_CSR) */
#define EDMA_CH_CSR_ERQ (1 << 0) /* Bit 0: Enable DMA Request (ERQ) */
#define EDMA_CH_CSR_EARQ (1 << 1) /* Bit 1: Enable Asynchronous DMA Request in Stop Mode for Channel (EARQ) */
#define EDMA_CH_CSR_EEI (1 << 2) /* Bit 2: Enable Error Interrupt (EEI) */
#define EDMA_CH_CSR_EBW (1 << 3) /* Bit 3: Enable Buffered Writes (EBW) */
/* Bit 4-29: Reserved */
#define EDMA_CH_CSR_DONE (1 << 30) /* Bit 30: Channel Done (DONE) */
#define EDMA_CH_CSR_ACTIVE (1 << 31) /* Bit 31: CHannel Active (ACTIVE) */
/* Channel n Error Status Register (CHn_ES) */
#define EDMA_CH_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
#define EDMA_CH_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
#define EDMA_CH_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
#define EDMA_CH_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
#define EDMA_CH_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
#define EDMA_CH_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
#define EDMA_CH_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
#define EDMA_CH_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
/* Bit 8-30: Reserved */
#define EDMA_CH_ES_ERR (1 << 31) /* Bit 31: Error in this channel (ERR) */
/* Channel n Interrupt Status Register (CHn_INT) */
#define EDMA_CH_INT (1 << 0) /* Bit 0: Interrupt Request (INT) */
/* Bits 1-31: Reserved */
/* Channel n System Bus Register (CHn_SBR) */
#define EDMA_CH_SBR_MID_SHIFT (0) /* Bits 0-3: Master ID (MID) */
#define EDMA_CH_SBR_MID_MASK (0x0f << EDMA_CH_SBR_MID_SHIFT)
/* Bits 4-13: Reserved */
#define EDMA_CH_SBR_SEC (1 << 14) /* Bit 14: Security Level (SEC) */
#define EDMA_CH_SBR_PAL (1 << 15) /* Bit 15: Privileged Access Level (PAL) */
#define EDMA_CH_SBR_EMI (1 << 16) /* Bit 16: Enable Master ID Replication (EMI) */
#define EDMA_CH_SBR_ATTR_SHIFT (17) /* Bits 17-19: Attribute Output (ATTR) */
#define EDMA_CH_SBR_ATTR_MASK (0x07 << EDMA_CH_SBR_ATTR_SHIFT)
/* Bits 20-31: Reserved */
/* Channel n Priority Register (CHn_PRI) */
#define EDMA_CH_PRI_APL_SHIFT (0) /* Bits 0-2: Arbitration Priority Level (APL) */
#define EDMA_CH_PRI_APL_MASK (0x07 << EDMA_CH_PRI_APL_SHIFT)
/* Bits 3-29: Reserved */
#define EDMA_CH_PRI_DPA (1 << 30) /* Bit 30: Disable Preempt Ability (DPA) */
#define EDMA_CH_PRI_ECP (1 << 31) /* Bit 31: Enable Channel Preemption (ECP) */
/* Channel Multiplexor Configuration (CHn_MUX) */
#define EDMA_CH_SRC_SHIFT (0) /* Bits 0-6: Service Request Source */
#define EDMA_CH_SRC_MASK (0x7f << EDMA_CH_SRC_SHIFT)
/* TCDn Source Address Register (TCDn_SADDR) */
#define EDMA_TCD_SADDR_SHIFT (0) /* Bits 0-31: Source Address (SADDR) */
#define EDMA_TCD_SADDR_MASK (0xffffffff << EDMA_TCD_SADDR_SHIFT)
/* TCDn Signed Source Address Offset Register (TCDn_SOFF) */
#define EDMA_TCD_SOFF_SHIFT (0) /* Bits 0-31: Source Address Signed Offset (SOFF) */
#define EDMA_TCD_SOFF_MASK (0xffffffff << EDMA_TCD_SOFF_SHIFT)
/* TCDn Transfer Attributes (TCDn_ATTR) */
#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination Data Transfer Size (DSIZE) */
#define EDMA_TCD_ATTR_DSIZE_MASK (0x07 << EDMA_TCD_ATTR_DSIZE_SHIFT)
#define EDMA_TCD_ATTR_DSIZE(n) (((n) << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK)
#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo (DMOD) */
#define EDMA_TCD_ATTR_DMOD_MASK (0x1f << EDMA_TCD_ATTR_DMOD_SHIFT)
#define EDMA_TCD_ATTR_DMOD(n) (((n) << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK)
#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source Data Transfer Size (SSIZE) */
#define EDMA_TCD_ATTR_SSIZE_MASK (0x07 << EDMA_TCD_ATTR_SSIZE_SHIFT)
#define EDMA_TCD_ATTR_SSIZE(n) (((n) << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK)
# define EDMA_TCD_ATTR_SSIZE_8BIT (0x00 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
# define EDMA_TCD_ATTR_SSIZE_16BIT (0x01 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */
# define EDMA_TCD_ATTR_SSIZE_32BIT (0x02 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */
# define EDMA_TCD_ATTR_SSIZE_64BIT (0x03 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */
# define EDMA_TCD_ATTR_SSIZE_16BYTE (0x04 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-byte */
# define EDMA_TCD_ATTR_SSIZE_32BYTE (0x05 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte */
# define EDMA_TCD_ATTR_SSIZE_64BYTE (0x06 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-byte */
#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo (SMOD) */
#define EDMA_TCD_ATTR_SMOD_MASK (0x1f << EDMA_TCD_ATTR_SMOD_SHIFT)
#define EDMA_TCD_ATTR_SMOD(n) (((n) << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK)
/* TCDn Transfer Size (TCDn_NBYTES) */
#define EDMA_TCD_NBYTES_SHIFT (0) /* Bits 0-29: Number of Bytes to Transfer per Service Request (NBYTES) */
#define EDMA_TCD_NBYTES_MASK (0x3fffffff << EDMA_TCD_NBYTES_SHIFT)
#define EDMA_TCD_NBYTES_MASK_MLOFF (0x03ff << EDMA_TCD_NBYTES_SHIFT)
#define EDMA_TCD_NBYTES_MLOFF_SHIFT (10) /* Bits 10-29: Minor Loop Offset (MLOFF) */
#define EDMA_TCD_NBYTES_MLOFF_MASK (0x0fffff << EDMA_TCD_NBYTES_MLOFF_SHIFT)
#define EDMA_TCD_NBYTES_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset Enable (DMLOE) */
#define EDMA_TCD_NBYTES_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable (SMLOE) */
/* TCDn Last Source Address Adjustment / Store DADDR Address Register
* (TCDn_SLAST_SDA)
*/
#define EDMA_TCD_SLAST_SDA_SHIFT (0) /* Bits 0-31: Last Source Address Adjustment / Store DADDR Address (SLAST_SDA) */
#define EDMA_TCD_SLAST_SDA_MASK (0xffffffff << EDMA_TCD_SLAST_SDA_SHIFT)
/* TCDn Destination Address Register (TCDn_DADDR) */
#define EDMA_TCD_DADDR_SHIFT (0) /* Bits 0-31: Destination Address (DADDR) */
#define EDMA_TCD_DADDR_MASK (0xffffffff << EDMA_TCD_DADDR_SHIFT)
/* TCDn Signed Destination Address Offset Register (TCDn_DOFF) */
#define EDMA_TCD_DOFF_SHIFT (0) /* Bits 0-15: Destination Address Signed Offset (DOFF) */
#define EDMA_TCD_DOFF_MASK (0xffff << EDMA_TCD_DOFF_SHIFT)
/* TCDn Current Major Loop Count Register (TCDn_CITER) */
#define EDMA_TCD_CITER_SHIFT (0) /* Bits 0-14: Current Major Iteration Count (CITER) */
#define EDMA_TCD_CITER_MASK (0x7fff << EDMA_TCD_CITER_SHIFT)
#define EDMA_TCD_CITER_MASK_ELINK (0x01ff << EDMA_TCD_CITER_SHIFT)
#define EDMA_TCD_CITER_LINKCH_SHIFT (9) /* Bits 9-13: Minor Loop Link Channel Number (LINKCH) */
#define EDMA_TCD_CITER_LINKCH_MASK (0x1f << EDMA_TCD_CITER_LINKCH_SHIFT)
#define EDMA_TCD_CITER_LINKCH(n) (((n) << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT)
#define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */
/* TCDn Last Destination Address Adjustment / Scatter Gather Address Register
* (TCDn_DLAST_SGA)
*/
#define EDMA_TCD_DLAST_SGA_SHIFT (0) /* Bits 0-31: Last Destination Address Adjustment / Scatter Gather Address (DLAST_SGA) */
#define EDMA_TCD_DLAST_SGA_MASK (0xffffffff << EDMA_TCD_DLAST_SGA_SHIFT)
/* TCDn Control and Status Register (TCDn_CSR) */
#define EDMA_TCD_CSR_START (1 << 0) /* Bit 0: Channel Start (START) */
#define EDMA_TCD_CSR_INTMAJOR (1 << 1) /* Bit 1: Enable Interrupt if Major count complete (INTMAJOR) */
#define EDMA_TCD_CSR_INTHALF (1 << 2) /* Bit 2: Enable Interrupt if Major Count Half-complete (INTHALF) */
#define EDMA_TCD_CSR_DREQ (1 << 3) /* Bit 3: Disable Request (DREQ) */
#define EDMA_TCD_CSR_ESG (1 << 4) /* Bit 4: Enable Scatter/Gather Processing (ESG) */
#define EDMA_TCD_CSR_MAJORELINK (1 << 5) /* Bit 5: Enable Link When Major Loop Complete (MAJORELINK) */
#define EDMA_TCD_CSR_EEOP (1 << 6) /* Bit 6: Enable End-Of-Packet Processing (EEOP) */
#define EDMA_TCD_CSR_ESDA (1 << 7) /* Bit 7: Enable Store Destination Address (ESDA) */
#define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-12: Major Loop Link Channel Number (MAJORLINKCH) */
#define EDMA_TCD_CSR_MAJORLINKCH_MASK (0x1f << EDMA_TCD_CSR_MAJORLINKCH_SHIFT)
#define EDMA_TCD_CSR_MAJORLINKCH(n) (((n) << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) & EDMA_TCD_CSR_MAJORLINKCH_MASK)
/* Bit 13: Reserved */
#define EDMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth Control (BWC) */
#define EDMA_TCD_CSR_BWC_MASK (0x03 << EDMA_TCD_CSR_BWC_SHIFT)
# define EDMA_TCD_CSR_BWC_NOSTALL (0x00 << EDMA_TCD_CSR_BWC_SHIFT) /* No eDMA engine stalls */
# define EDMA_TCD_CSR_BWC_HPE (0x01 << EDMA_TCD_CSR_BWC_SHIFT) /* Enable eDMA master high-priority elevation (HPE) mode */
# define EDMA_TCD_CSR_BWC_4CYCLES (0x02 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 4 cycles after each R/W */
# define EDMA_TCD_CSR_BWC_8CYCLES (0x03 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 8 cycles after each R/W */
/* TCDn Beginning Major Loop Count Register (TCDn_BITER) */
#define EDMA_TCD_BITER_SHIFT (0) /* Bits 0-14: Starting Major Iteration Count (BITER) */
#define EDMA_TCD_BITER_MASK (0x7fff << EDMA_TCD_BITER_SHIFT)
#define EDMA_TCD_BITER_MASK_ELINK (0x01ff << EDMA_TCD_BITER_SHIFT)
#define EDMA_TCD_BITER_LINKCH_SHIFT (9) /* Bits 9-13: Link Channel Number (LINKCH) */
#define EDMA_TCD_BITER_LINKCH_MASK (0x1f << EDMA_TCD_BITER_LINKCH_SHIFT)
#define EDMA_TCD_BITER_LINKCH(n) (((n) << EDMA_TCD_BITER_LINKCH_SHIFT) & EDMA_TCD_BITER_LINKCH_MASK)
#define EDMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */
/* Amount of channels */
#define DMA3_CHANNEL_COUNT (31)
#define DMA4_CHANNEL_COUNT (64)
#define IMX9_EDMA_NCHANNELS (DMA3_CHANNEL_COUNT + DMA4_CHANNEL_COUNT)
/* Amount of interrupt sources */
#define DMA3_IRQ_COUNT (32) /* Error interrupt not counted */
#define DMA4_IRQ_COUNT (32) /* Error interrupt not counted */
/****************************************************************************
* Public Types
****************************************************************************/
/* In-memory representation of the 32-byte Transfer Control Descriptor
* (TCD)
*/
struct imx9_edmatcd_s
{
uint32_t saddr; /* Offset: 0x0000 TCD Source Address */
uint16_t soff; /* Offset: 0x0004 TCD Signed Source Address Offset */
uint16_t attr; /* Offset: 0x0006 TCD Transfer Attributes */
uint32_t nbytes; /* Offset: 0x0008 TCD Signed Minor Loop Offset / Byte Count */
uint32_t slast; /* Offset: 0x000c TCD Last Source Address Adjustment */
uint32_t daddr; /* Offset: 0x0010 TCD Destination Address */
uint16_t doff; /* Offset: 0x0014 TCD Signed Destination Address Offset */
uint16_t citer; /* Offset: 0x0016 TCD Current Minor Loop Link, Major Loop Count */
uint32_t dlastsga; /* Offset: 0x0018 TCD Last Destination Address Adjustment/Scatter Gather Address */
uint16_t csr; /* Offset: 0x001c TCD Control and Status */
uint16_t biter; /* Offset: 0x001e TCD Beginning Minor Loop Link, Major Loop Count */
};
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_edma_tcdhasmux
*
* Description:
* Check if DMA TCD has TCD.MUX register.
*
* Input Parameters:
* dmabase - The eDMA base.
*
* Returned Value:
* true if TCD.MUX exists; false if not.
*
****************************************************************************/
static inline bool imx9_edma_tcdhasmux(uintptr_t dmabase)
{
/* Only eDMA4 has TCD.MUX register */
return dmabase == IMX9_DMA4_BASE ? true : false;
}
/****************************************************************************
* Name: imx9_edma_choffset
*
* Description:
* Channel offset in global channel list for dma base.
*
* Input Parameters:
* base - The eDMA base.
*
* Returned Value:
* Channel offset.
*
****************************************************************************/
static inline uint32_t imx9_edma_choffset(uintptr_t base)
{
return base == IMX9_DMA3_BASE ? 0 : DMA3_CHANNEL_COUNT;
}
/****************************************************************************
* Name: imx9_edma_chmax
*
* Description:
* Max channel in global channel list for dma base.
*
* Input Parameters:
* base - The eDMA base.
*
* Returned Value:
* Channel max.
*
****************************************************************************/
static inline uint32_t imx9_edma_chmax(uintptr_t base)
{
return base == IMX9_DMA3_BASE ? DMA3_CHANNEL_COUNT : IMX9_EDMA_NCHANNELS;
}
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_EDMA_H */
arch/arm/src/imx9/hardware/imx93/imx93_gpio.h
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx93/imx93_gpio.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_GPIO_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "imx93_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IMX9_GPIO_VERID_OFFSET (0x0000) /* Version ID */
#define IMX9_GPIO_PARAM_OFFSET (0x0004) /* Parameter */
#define IMX9_GPIO_LOCK_OFFSET (0x000c) /* Lock */
#define IMX9_GPIO_PCNS_OFFSET (0x0010) /* Pin Control Nonsecure */
#define IMX9_GPIO_ICNS_OFFSET (0x0014) /* Interrupt Control Nonsecure */
#define IMX9_GPIO_PCNP_OFFSET (0x0018) /* Pin Control Nonprivilege */
#define IMX9_GPIO_ICNP_OFFSET (0x001c) /* Interrupt Control Nonprivilege */
#define IMX9_GPIO_PDOR_OFFSET (0x0040) /* Port Data Output */
#define IMX9_GPIO_PSOR_OFFSET (0x0044) /* Port Set Output */
#define IMX9_GPIO_PCOR_OFFSET (0x0048) /* Port Clear Output */
#define IMX9_GPIO_PTOR_OFFSET (0x004c) /* Port Toggle Output */
#define IMX9_GPIO_PDIR_OFFSET (0x0050) /* Port Data Input */
#define IMX9_GPIO_PDDR_OFFSET (0x0054) /* Port Data Direction */
#define IMX9_GPIO_PIDR_OFFSET (0x0058) /* Port Input Disable */
#define IMX9_GPIO_P0DR_OFFSET (0x0060) /* Pin Data (0-31 at offsets of n * 4h) */
#define IMX9_GPIO_ICR0_OFFSET (0x0080) /* Interrupt Control (0-31 at offsets of n * 4h) */
#define IMX9_GPIO_GICLR_OFFSET (0x0100) /* Global Interrupt Control Low */
#define IMX9_GPIO_GICHR_OFFSET (0x0104) /* Global Interrupt Control High */
#define IMX9_GPIO_ISFR0_OFFSET (0x0120) /* Interrupt Status Flag */
#define IMX9_GPIO_ISFR1_OFFSET (0x0124) /* Interrupt Status Flag */
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_GPIO_H */
arch/arm/src/imx9/hardware/imx93/imx93_iomux.h
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arch/arm/src/imx9/hardware/imx93/imx93_memorymap.h
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx93/imx93_memorymap.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_MEMORYMAP_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_MEMORYMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IMX9_GIC_DISTRIBUTOR_BASE (0x48000000UL)
#define IMX9_GIC_REDISTRIBUTOR_BASE (0x48040000UL)
#define IMX9_ANA_OSC_BASE (0x44480000UL)
#define IMX9_AXBS_BASE (0x44510000UL)
#define IMX9_BBNSM_BASE (0x44440000UL)
#define IMX9_BLK_CTRL_BBSMMIX1_BASE (0x44410000UL)
#define IMX9_BLK_CTRL_MLMIX_BASE (0x4A810000UL)
#define IMX9_BLK_CTRL_NIC_WRAPPER1_BASE (0x49000000UL)
#define IMX9_BLK_CTRL_NS_AONMIX1_BASE (0x44210000UL)
#define IMX9_BLK_CTRL_S_AONMIX2_BASE (0x444F0000UL)
#define IMX9_BLK_CTRL_WAKEUPMIX1_BASE (0x42420000UL)
#define IMX9_CAN1_BASE (0x443A0000UL)
#define IMX9_CAN2_BASE (0x425B0000UL)
#define IMX9_CCM_CTRL_BASE (0x44450000UL)
#define IMX9_CM33_MCM_BASE (0x44420000UL)
#define IMX9_DDR_CTRL_BASE (0x4E300000UL)
#define IMX9_BLK_CTRL_DDRMIX_BASE (0x4E010000UL)
#define IMX9_DMA3_BASE (0x44000000UL)
#define IMX9_DMA4_BASE (0x42000000UL)
#define IMX9_PMRO_BASE (0x44484000UL)
#define IMX9_ENET_BASE (0x42890000UL)
#define IMX9_ENET_QOS_BASE (0x428A0000UL)
#define IMX9_FLEXIO1_BASE (0x425C0000UL)
#define IMX9_FLEXIO2_BASE (0x425D0000UL)
#define IMX9_FLEXSPI_BASE (0x425E0000UL)
#define IMX9_FLEXSPI_ARDF_BASE (0x47420000UL)
#define IMX9_FLEXSPI_ATDF_BASE (0x47430000UL)
#define IMX9_GPC_CTRL_CM33_BASE (0x44470000UL)
#define IMX9_GPC_CTRL_CA55_0_BASE (0x44470800UL)
#define IMX9_GPC_CTRL_CA55_1_BASE (0x44471000UL)
#define IMX9_GPC_CTRL_CA55_CLUSTER_BASE (0x44471800UL)
#define IMX9_SAI1_BASE (0x443B0000UL)
#define IMX9_SAI2_BASE (0x42650000UL)
#define IMX9_SAI3_BASE (0x42660000UL)
#define IMX9_I3C1_BASE (0x44330000UL)
#define IMX9_I3C2_BASE (0x42520000UL)
#define IMX9_IOMUXC_BASE (0x443C0000UL)
#define IMX9_ISI_BASE (0x4AE40000UL)
#define IMX9_LCDIF_BASE (0x4AE30000UL)
#define IMX9_LPI2C1_BASE (0x44340000UL)
#define IMX9_LPI2C2_BASE (0x44350000UL)
#define IMX9_LPI2C3_BASE (0x42530000UL)
#define IMX9_LPI2C4_BASE (0x42540000UL)
#define IMX9_LPI2C5_BASE (0x426B0000UL)
#define IMX9_LPI2C6_BASE (0x426C0000UL)
#define IMX9_LPI2C7_BASE (0x426D0000UL)
#define IMX9_LPI2C8_BASE (0x426E0000UL)
#define IMX9_LPIT1_BASE (0x442F0000UL)
#define IMX9_LPIT2_BASE (0x424C0000UL)
#define IMX9_LPSPI1_BASE (0x44360000UL)
#define IMX9_LPSPI2_BASE (0x44370000UL)
#define IMX9_LPSPI3_BASE (0x42550000UL)
#define IMX9_LPSPI4_BASE (0x42560000UL)
#define IMX9_LPSPI5_BASE (0x426F0000UL)
#define IMX9_LPSPI6_BASE (0x42700000UL)
#define IMX9_LPSPI7_BASE (0x42710000UL)
#define IMX9_LPSPI8_BASE (0x42720000UL)
#define IMX9_LPTMR1_BASE (0x44300000UL)
#define IMX9_LPTMR2_BASE (0x424D0000UL)
#define IMX9_LPUART1_BASE (0x44380000UL)
#define IMX9_LPUART2_BASE (0x44390000UL)
#define IMX9_LPUART3_BASE (0x42570000UL)
#define IMX9_LPUART4_BASE (0x42580000UL)
#define IMX9_LPUART5_BASE (0x42590000UL)
#define IMX9_LPUART6_BASE (0x425A0000UL)
#define IMX9_LPUART7_BASE (0x42690000UL)
#define IMX9_LPUART8_BASE (0x426A0000UL)
#define IMX9_M33_CACHE_MCM_BASE (0x44401000UL)
#define IMX9_BLK_CTRL_MEDIAMIX_BASE (0x4AC10000UL)
#define IMX9_MIPI_CSI_CSR_BASE (0x4AE00000UL)
#define IMX9_MIPI_DSI_BASE (0x4AE10000UL)
#define IMX9_MU1_MUA_BASE (0x44220000UL)
#define IMX9_MU2_MUA_BASE (0x42430000UL)
#define IMX9_S3MUA_BASE (0x47520000UL)
#define IMX9_TRDC_BASE (0x49010000UL)
#define IMX9_NPU_BASE (0x4A900000UL)
#define IMX9_OCOTP_BASE (0x47518000UL)
#define IMX9_OCRAM_MECC1_BASE (0x490A0000UL)
#define IMX9_FLEXSPI_OTFAD1_BASE (0x425E0C00UL)
#define IMX9_PDM_BASE (0x44520000UL)
#define IMX9_ARMPLL_BASE (0x44481000UL)
#define IMX9_AUDIOPLL_BASE (0x44481200UL)
#define IMX9_DRAMPLL_BASE (0x44481300UL)
#define IMX9_SYSPLL_BASE (0x44481100UL)
#define IMX9_VIDEOPLL_BASE (0x44481400UL)
#define IMX9_PXP_BASE (0x4AE20000UL)
#define IMX9_GPIO1_BASE (0x47400000UL)
#define IMX9_GPIO2_BASE (0x43810000UL)
#define IMX9_GPIO3_BASE (0x43820000UL)
#define IMX9_GPIO4_BASE (0x43830000UL)
#define IMX9_ROMCP1_BASE (0x44430000UL)
#define IMX9_ROMCP2_BASE (0x42640000UL)
#define IMX9_ADC1_BASE (0x44530000UL)
#define IMX9_SEMA42_1_BASE (0x44260000UL)
#define IMX9_SEMA42_2_BASE (0x42450000UL)
#define IMX9_SFA_BASE (0x44483000UL)
#define IMX9_SPDIF_BASE (0x42680000UL)
#define IMX9_SRC_GENERAL_REG_BASE (0x44460000UL)
#define IMX9_SRC_SENTINEL_SLICE_BASE (0x44460400UL)
#define IMX9_SRC_AON_SLICE_BASE (0x44460800UL)
#define IMX9_SRC_WKUP_SLICE_BASE (0x44460C00UL)
#define IMX9_SRC_DDR_SLICE_BASE (0x44461000UL)
#define IMX9_SRC_DPHY_SLICE_BASE (0x44461400UL)
#define IMX9_SRC_ML_SLICE_BASE (0x44461800UL)
#define IMX9_SRC_NIC_SLICE_BASE (0x44461C00UL)
#define IMX9_SRC_HSIO_SLICE_BASE (0x44462000UL)
#define IMX9_SRC_MEDIA_SLICE_BASE (0x44462400UL)
#define IMX9_SRC_M33P_SLICE_BASE (0x44462800UL)
#define IMX9_SRC_A55C0_SLICE_BASE (0x44462C00UL)
#define IMX9_SRC_A55C1_SLICE_BASE (0x44463000UL)
#define IMX9_SRC_A55P_SLICE_BASE (0x44463400UL)
#define IMX9_SRC_MEDIA_MEM_BASE (0x44465800UL)
#define IMX9_SRC_ML_MEM_BASE (0x44464800UL)
#define IMX9_M33_PCF1_BASE (0x443E0000UL)
#define IMX9_M33_PSF1_BASE (0x443F0000UL)
#define IMX9_SYS_CTR_COMPARE_BASE (0x442A0000UL)
#define IMX9_SYS_CTR_CONTROL_BASE (0x44290000UL)
#define IMX9_SYS_CTR_READ_BASE (0x442B0000UL)
#define IMX9_TMU_BASE (0x44482000UL)
#define IMX9_TPM1_BASE (0x44310000UL)
#define IMX9_TPM2_BASE (0x44320000UL)
#define IMX9_TPM3_BASE (0x424E0000UL)
#define IMX9_TPM4_BASE (0x424F0000UL)
#define IMX9_TPM5_BASE (0x42500000UL)
#define IMX9_TPM6_BASE (0x42510000UL)
#define IMX9_TRDC1_BASE (0x44270000UL)
#define IMX9_TRDC2_BASE (0x42460000UL)
#define IMX9_TRGMUX_BASE (0x44531000UL)
#define IMX9_TSTMR1_BASE (0x442C0000UL)
#define IMX9_TSTMR2_BASE (0x42480000UL)
#define IMX9_USB_OTG1_BASE (0x4C100000UL)
#define IMX9_USB_OTG2_BASE (0x4C200000UL)
#define IMX9_USBNC_OTG1_BASE (0x4C100200UL)
#define IMX9_USBNC_OTG2_BASE (0x4C200200UL)
#define IMX9_USDHC1_BASE (0x42850000UL)
#define IMX9_USDHC2_BASE (0x42860000UL)
#define IMX9_USDHC3_BASE (0x428B0000UL)
#define IMX9_WDOG1_BASE (0x442D0000UL)
#define IMX9_WDOG2_BASE (0x442E0000UL)
#define IMX9_WDOG3_BASE (0x42490000UL)
#define IMX9_WDOG4_BASE (0x424A0000UL)
#define IMX9_WDOG5_BASE (0x424B0000UL)
#define IMX9_LPCAC_PC_BASE (0x44400000UL)
#define IMX9_LPCAC_PS_BASE (0x44400800UL)
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_MEMORYMAP_H */
arch/arm/src/imx9/hardware/imx93/imx93_pinmux.h
+636
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arch/arm/src/imx9/hardware/imx93/imx93_pll.h
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx93/imx93_pll.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_PLL_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_PLL_H
/* All registers besides STATUS have SET, CLR, TGL and VAL shadow registers */
#define PLL_REG_VAL_OFFSET (0x00)
#define PLL_REG_SET_OFFSET (0x04)
#define PLL_REG_CLR_OFFSET (0x08)
#define PLL_REG_TGL_OFFSET (0x0c)
/* User can access the individual registers via these macros */
#define PLL_VAL(n) ((n) + PLL_REG_VAL_OFFSET) /* Same as the register itself */
#define PLL_SET(n) ((n) + PLL_REG_SET_OFFSET)
#define PLL_CLR(n) ((n) + PLL_REG_CLR_OFFSET)
#define PLL_TGL(n) ((n) + PLL_REG_TGL_OFFSET)
/* Common offsets for all PLL registers, existence depends on the register
* itself
*/
#define PLL_CTRL_OFFSET (0x00) /* PLL Control */
#define PLL_SPREAD_SPECTRUM_OFFSET (0x30) /* Spread Spectrum */
#define PLL_NUMERATOR_OFFSET (0x40) /* Numerator */
#define PLL_DENOMINATOR_OFFSET (0x50) /* Denominator */
#define PLL_DIV_OFFSET (0x60) /* PLL Dividers */
#define PLL_DFS_CTRL_0_OFFSET (0x70) /* DFS Control */
#define PLL_DFS_DIV_0_OFFSET (0x80) /* DFS Division_0 */
#define PLL_DFS_CTRL_1_OFFSET (0x90) /* DFS Control */
#define PLL_DFS_DIV_1_OFFSET (0xa0) /* DFS Division_1 */
#define PLL_DFS_CTRL_2_OFFSET (0xb0) /* DFS Control */
#define PLL_DFS_DIV_2_OFFSET (0xc0) /* DFS Division_2 */
#define PLL_PLL_STATUS_OFFSET (0xf0) /* PLL Status */
#define PLL_DFS_STATUS_OFFSET (0xf4) /* DFS Status */
/* Register addresses */
#define PLL_CTRL(n) ((n) + PLL_CTRL_OFFSET)
#define PLL_SPREAD_SPECTRUM(n) ((n) + PLL_SPREAD_SPECTRUM_OFFSET)
#define PLL_NUMERATOR(n) ((n) + PLL_NUMERATOR_OFFSET)
#define PLL_DENOMINATOR(n) ((n) + PLL_DENOMINATOR_OFFSET)
#define PLL_DIV(n) ((n) + PLL_DIV_OFFSET)
#define PLL_DFS_CTRL_0(n) ((n) + PLL_DFS_CTRL_0_OFFSET)
#define PLL_DFS_DIV_0(n) ((n) + PLL_DFS_DIV_0_OFFSET)
#define PLL_DFS_CTRL_1(n) ((n) + PLL_DFS_CTRL_1_OFFSET)
#define PLL_DFS_DIV_1(n) ((n) + PLL_DFS_DIV_1_OFFSET)
#define PLL_DFS_CTRL_2(n) ((n) + PLL_DFS_CTRL_2_OFFSET)
#define PLL_DFS_DIV_2(n) ((n) + PLL_DFS_DIV_2_OFFSET)
#define PLL_PLL_STATUS(n) ((n) + PLL_PLL_STATUS_OFFSET)
#define PLL_DFS_STATUS(n) ((n) + PLL_DFS_STATUS_OFFSET)
/* SYSPLL registers */
#define SYSPLL_CTRL (IMX9_SYSPLL_BASE + PLL_CTRL_OFFSET)
#define SYSPLL_SPREAD_SPECTRUM (IMX9_SYSPLL_BASE + PLL_SPREAD_SPECTRUM_OFFSET)
#define SYSPLL_NUMERATOR (IMX9_SYSPLL_BASE + PLL_NUMERATOR_OFFSET)
#define SYSPLL_DENOMINATOR (IMX9_SYSPLL_BASE + PLL_DENOMINATOR_OFFSET)
#define SYSPLL_DIV (IMX9_SYSPLL_BASE + PLL_DIV_OFFSET)
#define SYSPLL_DFS_CTRL_0 (IMX9_SYSPLL_BASE + PLL_DFS_CTRL_0_OFFSET)
#define SYSPLL_DFS_DIV_0 (IMX9_SYSPLL_BASE + PLL_DFS_DIV_0_OFFSET)
#define SYSPLL_DFS_CTRL_1 (IMX9_SYSPLL_BASE + PLL_DFS_CTRL_1_OFFSET)
#define SYSPLL_DFS_DIV_1 (IMX9_SYSPLL_BASE + PLL_DFS_DIV_1_OFFSET)
#define SYSPLL_DFS_CTRL_2 (IMX9_SYSPLL_BASE + PLL_DFS_CTRL_2_OFFSET)
#define SYSPLL_DFS_DIV_2 (IMX9_SYSPLL_BASE + PLL_DFS_DIV_2_OFFSET)
#define SYSPLL_PLL_STATUS (IMX9_SYSPLL_BASE + PLL_PLL_STATUS_OFFSET)
#define SYSPLL_DFS_STATUS (IMX9_SYSPLL_BASE + PLL_DFS_STATUS_OFFSET)
/* ARMPLL registers */
#define ARMPLL_CTRL (IMX9_ARMPLL_BASE + PLL_CTRL_OFFSET)
#define ARMPLL_DIV (IMX9_ARMPLL_BASE + PLL_DIV_OFFSET)
#define ARMPLL_PLL_STATUS (IMX9_ARMPLL_BASE + PLL_PLL_STATUS_OFFSET)
/* AUDIOPLL registers */
#define AUDIOPLL_CTRL (IMX9_AUDIOPLL_BASE + PLL_CTRL_OFFSET)
#define AUDIOPLL_SPREAD_SPECTRUM (IMX9_AUDIOPLL_BASE + PLL_SPREAD_SPECTRUM_OFFSET)
#define AUDIOPLL_NUMERATOR (IMX9_AUDIOPLL_BASE + PLL_NUMERATOR_OFFSET)
#define AUDIOPLL_DENOMINATOR (IMX9_AUDIOPLL_BASE + PLL_DENOMINATOR_OFFSET)
#define AUDIOPLL_DIV (IMX9_AUDIOPLL_BASE + PLL_DIV_OFFSET)
#define AUDIOPLL_PLL_STATUS (IMX9_AUDIOPLL_BASE + PLL_PLL_STATUS_OFFSET)
/* DRAMPLL registers */
#define DRAMPLL_CTRL (IMX9_AUDIOPLL_BASE + PLL_CTRL_OFFSET)
#define DRAMPLL_SPREAD_SPECTRUM (IMX9_AUDIOPLL_BASE + PLL_SPREAD_SPECTRUM_OFFSET)
#define DRAMPLL_NUMERATOR (IMX9_AUDIOPLL_BASE + PLL_NUMERATOR_OFFSET)
#define DRAMPLL_DENOMINATOR (IMX9_AUDIOPLL_BASE + PLL_DENOMINATOR_OFFSET)
#define DRAMPLL_DIV (IMX9_AUDIOPLL_BASE + PLL_DIV_OFFSET)
#define DRAMPLL_PLL_STATUS (IMX9_AUDIOPLL_BASE + PLL_PLL_STATUS_OFFSET)
/* VIDEOPLL registers */
#define VIDEOPLL_CTRL (IMX9_VIDEOPLL_BASE + PLL_CTRL_OFFSET)
#define VIDEOPLL_SPREAD_SPECTRUM (IMX9_VIDEOPLL_BASE + PLL_SPREAD_SPECTRUM_OFFSET)
#define VIDEOPLL_NUMERATOR (IMX9_VIDEOPLL_BASE + PLL_NUMERATOR_OFFSET)
#define VIDEOPLL_DENOMINATOR (IMX9_VIDEOPLL_BASE + PLL_DENOMINATOR_OFFSET)
#define VIDEOPLL_DIV (IMX9_VIDEOPLL_BASE + PLL_DIV_OFFSET)
#define VIDEOPLL_PLL_STATUS (IMX9_VIDEOPLL_BASE + PLL_PLL_STATUS_OFFSET)
/* PLL Control (CTRL) */
#define PLL_CTRL_POWERUP (1 << 0) /* Bit 0: Power up PLL */
#define PLL_CTRL_CLKMUX_EN (1 << 1) /* Bit 1: Enable CLKMUX output */
#define PLL_CTRL_CLKMUX_BYPASS (1 << 2) /* Bit 2: Enable CLKMUX bypass */
#define PLL_CTRL_SPREADCTL (1 << 8) /* Bit 8: Modulation Type Select */
#define PLL_CTRL_HW_CTRL_SEL (1 << 16) /* Bit 16: Hardware Control Select */
#define PLL_CTRL_LOCK_BYPASS (1 << 31) /* Bit 31: Lock bypass */
/* Spread Spectrum (SPREAD_SPECTRUM) */
#define PLL_SPREAD_SPECTRUM_STEP_SHIFT (0) /* Bits 14-0: Set spread spectrum step */
#define PLL_SPREAD_SPECTRUM_STEP_MASK (0x7fff << PLL_SPREAD_SPECTRUM_STEP_SHIFT)
#define PLL_SPREAD_SPECTRUM_STEP(n) (((n) << PLL_SPREAD_SPECTRUM_STEP_SHIFT) & PLL_SPREAD_SPECTRUM_STEP_MASK)
#define PLL_SPREAD_SPECTRUM_ENABLE (1 << 15) /* Bit 15: Enable spread spectrum */
#define PLL_SPREAD_SPECTRUM_STOP_SHIFT (16) /* Bits 16-31: Set spread spectrum stop */
#define PLL_SPREAD_SPECTRUM_STOP_MASK (0xffff << PLL_SPREAD_SPECTRUM_STOP_SHIFT)
#define PLL_SPREAD_SPECTRUM_STOP(n) (((n) << PLL_SPREAD_SPECTRUM_STOP_SHIFT) & PLL_SPREAD_SPECTRUM_STOP_MASK)
/* Numerator (NUMERATOR) */
#define PLL_NUMERATOR_MFN_SHIFT (2) /* Bits 2-31: Numerator MFN value */
#define PLL_NUMERATOR_MFN_MASK (0x3fffffff << PLL_NUMERATOR_MFN_SHIFT)
#define PLL_NUMERATOR_MFN(n) (((n) << PLL_NUMERATOR_MFN_SHIFT) & PLL_NUMERATOR_MFN_MASK)
/* Denominator (DENOMINATOR) */
#define PLL_DENOMINATOR_MFD_SHIFT (0) /* Bits 0-29: Denominator MFD value */
#define PLL_DENOMINATOR_MFD_MASK (0x3fffffff << PLL_DENOMINATOR_MFD_SHIFT)
#define PLL_DENOMINATOR_MFD(n) (((n) << PLL_DENOMINATOR_MFD_SHIFT) & PLL_DENOMINATOR_MFD_MASK)
/* PLL Dividers (DIV) */
#define PLL_DIV_ODIV_SHIFT (0) /* Bits 0-7: Output Frequency Divider for Clock Output */
#define PLL_DIV_ODIV_MASK (0xff << PLL_DIV_ODIV_SHIFT)
#define PLL_DIV_ODIV(n) (((n) << PLL_DIV_ODIV_SHIFT) & PLL_DIV_ODIV_MASK)
#define PLL_DIV_RDIV_SHIFT (13) /* Bits 13-15: Input Clock Predivider */
#define PLL_DIV_RDIV_MASK (0x7 << PLL_DIV_RDIV_SHIFT)
#define PLL_DIV_RDIV(n) (((n) << PLL_DIV_RDIV_SHIFT) & PLL_DIV_RDIV_MASK)
#define PLL_DIV_MFI_SHIFT (16) /* Bits 16-24: Integer Portion of Loop Divider */
#define PLL_DIV_MFI_MASK (0x1ff << PLL_DIV_MFI_SHIFT)
#define PLL_DIV_MFI(n) (((n) << PLL_DIV_MFI_SHIFT) & PLL_DIV_MFI_MASK)
/* DFS Control (DFS_CTRL_0 - DFS_CTRL_2) */
#define PLL_DFS_HW_CTRL_SEL (1 << 16) /* Bit 16: Hardware Control Select */
#define PLL_DFS_BYPASS_EN (1 << 23) /* Bit 23: Bypass Enable */
#define PLL_DFS_CLKOUT_DIVBY2_EN (1 << 29) /* Bit 29: DFS Clock Output Divide by 2 Enable */
#define PLL_DFS_CLKOUT_EN (1 << 30) /* Bit 30: DFS Clock Output Enable */
#define PLL_DFS_ENABLE (1 << 31) /* Bit 31: DFS Block Enable */
/* DFS Division_a (DFS_DIV_0 - DFS_DIV_2) */
#define PLL_DFS_MFN_SHIFT (0) /* Bits 0-2: MFN */
#define PLL_DFS_MFN_MASK (0x7 << PLL_DFS_MFN_SHIFT)
#define PLL_DFS_MFN(n) (((n) << PLL_DFS_MFN_SHIFT) & PLL_DFS_MFN_MASK)
#define PLL_DFS_MFI_SHIFT (8) /* Bits 8-15: MFI */
#define PLL_DFS_MFI_MASK (0xff << PLL_DFS_MFI_SHIFT)
#define PLL_DFS_MFI(n) (((n) << PLL_DFS_MFI_SHIFT) & PLL_DFS_MFI_MASK)
/* PLL Dividers (DIV) */
#define PLL_PLL_STATUS_PLL_LOCK (1 << 0) /* Bit 0: PLL is locked */
#define PLL_PLL_STATUS_PLL_LOL (1 << 1) /* Bit 1: PLL lock is lost */
#define PLL_PLL_STATUS_ANA_MFN_SHIFT (2)
#define PLL_PLL_STATUS_ANA_MFN_MASK (0x3fffffff << PLL_PLL_STATUS_ANA_MFN_SHIFT)
#define PLL_PLL_STATUS_ANA_MFN(n) (((n) << PLL_PLL_STATUS_ANA_MFN_SHIFT) & PLL_PLL_STATUS_ANA_MFN_MASK)
/* DFS Status (DFS_STATUS) */
#define PLL_DFS_STATUS_DFS_OK_SHIFT (0) /* Bits 0-2: DFS OK status */
#define PLL_DFS_STATUS_DFS_OK_MASK (0x7 << PLL_DFS_STATUS_DFS_OK_SHIFT)
#define PLL_DFS_STATUS_DFS_OK(n) (((n) << PLL_DFS_STATUS_DFS_OK_SHIFT) & PLL_DFS_STATUS_DFS_OK_MASK)
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_PLL_H_*/
arch/arm/src/imx9/hardware/imx9_ccm.h
+40
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@@ -0,0 +1,40 @@
/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_ccm.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_CCM_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_CCM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imx9_memorymap.h"
#if defined(CONFIG_ARCH_CHIP_IMX93_M33)
# include "hardware/imx93/imx93_ccm.h"
# include "hardware/imx93/imx93_pll.h"
#else
# error Unrecognized i.MX9 architecture
#endif
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_CCM_H_ */
arch/arm/src/imx9/hardware/imx9_clock.h
+2
View File
@@ -33,6 +33,8 @@
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include "hardware/imx95/imx95_clock.h"
#elif defined(CONFIG_ARCH_CHIP_IMX93_M33)
# include "hardware/imx93/imx93_clock.h"
#else
# error Unrecognized i.MX9 architecture
#endif
arch/arm/src/imx9/hardware/imx9_gpio.h
+2
View File
@@ -32,6 +32,8 @@
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include "hardware/imx95/imx95_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_IMX93_M33)
# include "hardware/imx93/imx93_gpio.h"
#else
# error Unrecognized i.MX9 architecture
#endif
arch/arm/src/imx9/hardware/imx9_iomuxc.h
+2
View File
@@ -32,6 +32,8 @@
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include "hardware/imx95/imx95_iomuxc.h"
#elif defined(CONFIG_ARCH_CHIP_IMX93_M33)
# include "hardware/imx93/imx93_iomux.h"
#else
# error Unrecognized i.MX9 architecture
#endif
arch/arm/src/imx9/hardware/imx9_memorymap.h
+2
View File
@@ -32,6 +32,8 @@
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include "hardware/imx95/imx95_memorymap.h"
#elif defined(CONFIG_ARCH_CHIP_IMX93_M33)
# include "hardware/imx93/imx93_memorymap.h"
#else
# error Unrecognized i.MX9 architecture
#endif
arch/arm/src/imx9/hardware/imx9_pinmux.h
+2
View File
@@ -32,6 +32,8 @@
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include "hardware/imx95/imx95_pinmux.h"
#elif defined(CONFIG_ARCH_CHIP_IMX93_M33)
# include "hardware/imx93/imx93_pinmux.h"
#else
# error Unrecognized i.MX9 architecture
#endif
arch/arm/src/imx9/hardware/imx9_rptun.h
+2
View File
@@ -25,6 +25,8 @@
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# define MU_INSTANCE 7
#elif defined(CONFIG_ARCH_CHIP_IMX93_M33)
# define MU_INSTANCE 1
#else
# error Unrecognized i.MX9 architecture
#endif
arch/arm/src/imx9/hardware/imx9_rsctable.h
+3
View File
@@ -26,6 +26,9 @@
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# define VDEV0_VRING_BASE 0x88000000
# define RESOURCE_TABLE_BASE 0x88220000
#elif defined(CONFIG_ARCH_CHIP_IMX93_M33)
# define VDEV0_VRING_BASE 0xA4000000
# define RESOURCE_TABLE_BASE 0x2001E000
#else
# error Unrecognized i.MX9 architecture
#endif
arch/arm/src/imx9/hardware/imx9_xcache.h
+78
View File
@@ -0,0 +1,78 @@
/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_xcache.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2026 Maarten Zanders
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_XCACHE_H
#define __ARCH_ARM_SRC_IMX9_IMX9_XCACHE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imx9_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* XCACHE Register Offsets */
#define IMX9_XCACHE_CCR_OFFSET 0x0000 /* Cache Control Register */
#define IMX9_XCACHE_CLCR_OFFSET 0x0004 /* Cache Line Control Register */
#define IMX9_XCACHE_CSAR_OFFSET 0x0008 /* Cache Search Address Register */
#define IMX9_XCACHE_CCVR_OFFSET 0x000C /* Cache Value Register */
/* Cache Control Register (CCR) */
#define XCACHE_CCR_ENCACHE (1 << 0) /* Enable cache */
#define XCACHE_CCR_INVW0 (1 << 24) /* Invalidate Way 0 */
#define XCACHE_CCR_PUSHW0 (1 << 25) /* Push Way 0 */
#define XCACHE_CCR_INVW1 (1 << 26) /* Invalidate Way 1 */
#define XCACHE_CCR_PUSHW1 (1 << 27) /* Push Way 1 */
#define XCACHE_CCR_GO (1 << 31) /* Initiate command */
/* Cache Line Control Register (CLCR) */
#define XCACHE_CLCR_LGO (1 << 0) /* Line command go */
#define XCACHE_CLCR_CACHEADDR_SHIFT 2
#define XCACHE_CLCR_CACHEADDR_MASK (0x7ff << XCACHE_CLCR_CACHEADDR_SHIFT)
#define XCACHE_CLCR_WSEL (1 << 14) /* Way select */
#define XCACHE_CLCR_TDSEL (1 << 16) /* Tag or data select */
#define XCACHE_CLCR_LCIVB (1 << 20) /* Line command initial valid */
#define XCACHE_CLCR_LCIMB (1 << 21) /* Line command initial modified */
#define XCACHE_CLCR_LCWAY (1 << 22) /* Line command way */
#define XCACHE_CLCR_LADSEL (1 << 26) /* Line Address Select (0: cache, 1: physical) */
#define XCACHE_CLCR_LCMD_SHIFT 24
#define XCACHE_CLCR_LCMD_MASK (0x3 << XCACHE_CLCR_LCMD_SHIFT) /* Line command */
#define XCACHE_CLCR_LCMD(n) ((n << XCACHE_CLCR_LCMD_SHIFT) & XCACHE_CLCR_LCMD_MASK)
#define XCACHE_LCMD_SRCH_RW 0b00
#define XCACHE_LCMD_INVALIDATE 0b01
#define XCACHE_LCMD_PUSH 0b10
#define XCACHE_LCMD_CLEAR 0b11
/* Cache Search Address Register */
#define XCACHE_CSAR_PHYADDR_MASK (0xFFFFFFFD)
#define XCACHE_CSAR_LGO (1 << 0)
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_XCACHE_H */
arch/arm/src/imx9/imx9_ccm.c
+173
View File
@@ -0,0 +1,173 @@
/****************************************************************************
* arch/arm/src/imx9/imx9_ccm.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <sys/param.h>
#include <sys/types.h>
#include <arch/barriers.h>
#include "imx9_ccm.h"
#include "hardware/imx9_ccm.h"
#include "arm_internal.h" /* getreg32(), putreg32() */
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_ccm_configure_root_clock
*
* Description:
* Change root clock source and divider. Leaves the clock running state
* unaltered.
*
* Input Parameters:
* root - The root clock index.
* src - The root clock MUX source.
* div - The root clock divider.
*
* Returned Value:
* Zero (OK) is returned on success. A negated errno value is returned on
* failure.
*
****************************************************************************/
int imx9_ccm_configure_root_clock(int root, int mux, uint32_t div)
{
uint32_t value;
if (root >= CCM_CR_COUNT || div == 0 || div > 255 || mux >= ROOT_MUX_MAX)
{
return -EINVAL;
}
/* Set the new value */
value = CCM_CR_CTRL_MUX_SRCSEL(mux) | CCM_CR_CTRL_DIV(div);
putreg32(value, IMX9_CCM_CR_CTRL(root));
UP_MB();
/* Wait for the clock state change */
while (getreg32(IMX9_CCM_CR_STAT0(root)) & CCM_CR_STAT0_CHANGING);
return OK;
}
/****************************************************************************
* Name: imx9_ccm_root_clock_on
*
* Description:
* Enable / disable root clock.
*
* Input Parameters:
* root - The root clock index.
* enabled - True enables the clock; false disables it.
*
* Returned Value:
* Zero (OK) is returned on success. A negated errno value is returned on
* failure.
*
****************************************************************************/
int imx9_ccm_root_clock_on(int root, bool enabled)
{
if (root >= CCM_CR_COUNT)
{
return -EINVAL;
}
if (enabled)
{
putreg32(CCM_CR_CTRL_OFF, IMX9_CCM_CR_CTRL_CLR(root));
}
else
{
putreg32(CCM_CR_CTRL_OFF, IMX9_CCM_CR_CTRL_SET(root));
}
UP_MB();
/* Wait for the clock state change */
while (getreg32(IMX9_CCM_CR_STAT0(root)) & CCM_CR_STAT0_CHANGING);
return OK;
}
/****************************************************************************
* Name: imx9_ccm_gate_on
*
* Description:
* Enable / disable clock.
*
* Input Parameters:
* gate - The clock gate index.
* enabled - True enables the clock; false disables it.
*
* Returned Value:
* Zero (OK) is returned on success. A negated errno value is returned on
* failure.
*
****************************************************************************/
int imx9_ccm_gate_on(int gate, bool enabled)
{
uint32_t value;
if (gate >= CCM_LPCG_COUNT)
{
return -EINVAL;
}
/* Make sure direct mode is on, which is what we support */
value = getreg32(IMX9_CCM_LPCG_AUTH(gate));
if (value & CCM_LPCG_AUTH_CPULPM)
{
value &= ~CCM_LPCG_AUTH_CPULPM;
putreg32(value, IMX9_CCM_LPCG_AUTH(gate));
UP_MB();
}
value = enabled ? 1 : 0;
putreg32(value, IMX9_CCM_LPCG_DIR(gate));
UP_MB();
/* Wait for the clock state change */
while ((getreg32(IMX9_CCM_LPCG_STAT0(gate)) & CCM_LPCG_STAT0_ON) != value);
return OK;
}
arch/arm/src/imx9/imx9_ccm.h
+90
View File
@@ -0,0 +1,90 @@
/****************************************************************************
* arch/arm/src/imx9/imx9_ccm.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_CCM_H
#define __ARCH_ARM_SRC_IMX9_IMX9_CCM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
/****************************************************************************
* Name: imx9_ccm_configure_root_clock
*
* Description:
* Change root clock source and divider. Leaves the clock running state
* unaltered.
*
* Input Parameters:
* root - The root clock index.
* mux - The root clock MUX source.
* div - The root clock divider.
*
* Returned Value:
* Zero (OK) is returned on success. A negated errno value is returned on
* failure.
*
****************************************************************************/
int imx9_ccm_configure_root_clock(int root, int mux, uint32_t div);
/****************************************************************************
* Name: imx9_ccm_root_clock_on
*
* Description:
* Enable / disable root clock.
*
* Input Parameters:
* root - The root clock index.
* enabled - True enables the clock; false disables it.
*
* Returned Value:
* Zero (OK) is returned on success. A negated errno value is returned on
* failure.
*
****************************************************************************/
int imx9_ccm_root_clock_on(int root, bool enabled);
/****************************************************************************
* Name: imx9_ccm_gate_on
*
* Description:
* Enable / disable clock.
*
* Input Parameters:
* gate - The clock gate index.
* enabled - True enables the clock; false disables it.
*
* Returned Value:
* Zero (OK) is returned on success. A negated errno value is returned on
* failure.
*
****************************************************************************/
int imx9_ccm_gate_on(int gate, bool enabled);
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_CCM_H */
arch/arm/src/imx9/imx9_clockconfig.c
+406 -1
View File
@@ -45,10 +45,96 @@
#include "imx9_clockconfig.h"
#include "imx9_scmi.h"
#include "hardware/imx9_memorymap.h"
#ifndef CONFIG_IMX9_CLK_OVER_SCMI
#include "imx9_ccm.h"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef CONFIG_IMX9_CLK_OVER_SCMI
#define PLL_PARMS(_rdiv, _odiv, _mfi, _mfn, _mfd) \
{ \
.rdiv = (_rdiv), \
.odiv = (_odiv), \
.mfi = (_mfi), \
.mfn = (_mfn), \
.mfd = (_mfd), \
}
#define PLL_CFG(_reg, _frac, _parms) \
{ \
.reg = (_reg), \
.frac = (_frac), \
.parms = _parms, \
}
#define PFD_PARMS(_mfi, _mfn, _div2) \
{ \
.mfi = (_mfi), \
.mfn = (_mfn), \
.divby2_en = (_div2) \
}
#define PFD_CFG(_reg, _pfd, _parms) \
{ \
.reg = (_reg), \
.pfd = (_pfd), \
.parms = _parms, \
}
#endif /* !CONFIG_IMX9_CLK_OVER_SCMI */
/****************************************************************************
* Types
****************************************************************************/
#ifndef CONFIG_IMX9_CLK_OVER_SCMI
struct pll_parms_s
{
/* Integer part (DIV) */
struct
{
uint32_t rdiv; /* Input clock divider */
uint32_t odiv; /* PLL output divider */
uint32_t mfi; /* PLL integer divider */
};
/* Fractional part (NUMERATOR / DENOMINATOR) */
struct
{
uint32_t mfn; /* PLL fractional divider numerator */
uint32_t mfd; /* PLL fractional divider denominator */
};
};
struct pfd_parms_s
{
uint32_t mfi; /* PLL integer divider */
uint32_t mfn; /* PLL fractional divider numerator */
bool divby2_en; /* Enable the divide-by-2 output */
};
struct imx9_pll_cfg_s
{
uintptr_t reg; /* The PLL register base */
bool frac; /* Fractional PLL ? */
struct pll_parms_s parms; /* The PLL parameters */
};
struct imx9_pfd_cfg_s
{
uintptr_t reg; /* The PLL register base */
int pfd; /* The PFD number */
struct pfd_parms_s parms; /* The PFD parameters */
};
#endif /* !CONFIG_IMX9_CLK_OVER_SCMI */
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -180,10 +266,267 @@ static int imx9_sm_getipfreq(sm_clock_t *sm_clk)
return rate.lower;
}
#endif
#else /* !CONFIG_IMX9_CLK_OVER_SCMI */
static uint32_t calculate_vco_freq(const struct pll_parms_s *parm, bool frac)
{
/* Base clock is common for all VCO:s */
if (frac)
{
return (uint64_t)XTAL_FREQ * (parm->mfi * parm->mfd + parm->mfn) /
parm->mfd / parm->rdiv;
}
else
{
return (uint64_t)XTAL_FREQ * parm->mfi / parm->rdiv;
}
}
static uint32_t vco_freq_out(uintptr_t reg, bool frac)
{
struct pll_parms_s parm;
uint32_t ctrl;
uint32_t status;
uint32_t div;
/* Check if the PLL on or off */
ctrl = getreg32(PLL_CTRL(reg));
if ((ctrl & PLL_CTRL_POWERUP) == 0)
{
return 0;
}
/* Check if the PLL is stable */
status = getreg32(PLL_PLL_STATUS(reg));
if ((status & PLL_PLL_STATUS_PLL_LOCK) == 0)
{
return 0;
}
/* Populate the integer and fractional PLL parameters */
div = getreg32(PLL_DIV(reg));
parm.rdiv = (div & PLL_DIV_RDIV_MASK) >> PLL_DIV_RDIV_SHIFT;
parm.mfi = (div & PLL_DIV_MFI_MASK) >> PLL_DIV_MFI_SHIFT;
/* RDIV values 0 and 1 both mean a divisor of 1 */
if (parm.rdiv == 0)
{
parm.rdiv = 1;
}
if (frac)
{
/* Fill the fractional parameters */
parm.mfn = getreg32(PLL_NUMERATOR(reg)) & PLL_NUMERATOR_MFN_MASK;
parm.mfn >>= PLL_NUMERATOR_MFN_SHIFT;
parm.mfd = getreg32(PLL_DENOMINATOR(reg)) & PLL_DENOMINATOR_MFD_MASK;
parm.mfd >>= PLL_DENOMINATOR_MFD_SHIFT;
}
return calculate_vco_freq(&parm, frac);
}
static uint32_t pll_freq_out(uintptr_t reg, bool frac)
{
uint32_t ctrl;
uint32_t div;
uint32_t vco;
/* Read the MUX control register and check if bypass mode is enabled */
ctrl = getreg32(PLL_CTRL(reg));
if (ctrl & PLL_CTRL_CLKMUX_BYPASS)
{
return XTAL_FREQ;
}
/* If the mux is disabled output frequency is 0 */
if ((ctrl & PLL_CTRL_CLKMUX_EN) == 0)
{
return 0;
}
/* Get input VCO frequency */
vco = vco_freq_out(reg, frac);
if (vco == 0)
{
/* The VCO is off or unstable */
return 0;
}
/* Calculate the output clock divider */
div = (getreg32(PLL_DIV(reg)) & PLL_DIV_ODIV_MASK) >> PLL_DIV_ODIV_SHIFT;
/* According to spec, div0 = 2 and div1 = 3 */
if (div == 0)
{
div = 2;
}
else if (div == 1)
{
div = 3;
}
return vco / div;
}
static uint32_t pll_pfd_freq_out(uintptr_t reg, int pfd, int div2)
{
struct pfd_parms_s parm;
uint32_t ctrl;
uint32_t div;
uint32_t vco;
/* Read the correct PFD register set */
switch (pfd)
{
case 0:
ctrl = getreg32(PLL_DFS_CTRL_0(reg));
div = getreg32(PLL_DFS_DIV_0(reg));
break;
case 1:
ctrl = getreg32(PLL_DFS_CTRL_1(reg));
div = getreg32(PLL_DFS_DIV_1(reg));
break;
case 2:
ctrl = getreg32(PLL_DFS_CTRL_2(reg));
div = getreg32(PLL_DFS_DIV_2(reg));
break;
default:
return 0;
}
/* Get input VCO frequency */
vco = vco_freq_out(reg, true);
if (vco == 0)
{
/* The VCO is off or unstable */
return 0;
}
/* If the DFS part is bypassed, the output is the VCO directly */
if (ctrl & PLL_DFS_BYPASS_EN)
{
return vco;
}
/* Check if the DFS part is disabled */
if ((ctrl & PLL_DFS_ENABLE) == 0)
{
return 0;
}
/* Populate the DFS parameters */
parm.mfi = (div & PLL_DFS_MFI_MASK) >> PLL_DFS_MFI_SHIFT;
parm.mfn = (div & PLL_DFS_MFN_MASK) >> PLL_DFS_MFN_SHIFT;
return ((uint64_t)vco * 5) / (parm.mfi * 5 + parm.mfn) / div2;
}
/****************************************************************************
* Name: imx9_get_clock
*
* Description:
* This function returns the clock frequency of the specified functional
* clock.
*
* Input Parameters:
* clkname - Identifies the clock of interest
* frequency - The location where the peripheral clock frequency will be
* returned
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure. -ENODEV is returned if the clock is not enabled or is not
* being clocked.
*
****************************************************************************/
static int imx9_get_clock(int clkname, uint32_t *frequency)
{
switch (clkname)
{
case OSC_24M:
*frequency = XTAL_FREQ;
break;
case ARM_PLL:
*frequency = pll_freq_out(IMX9_ARMPLL_BASE, false);
break;
case SYS_PLL1_IN:
*frequency = pll_freq_out(IMX9_SYSPLL_BASE, false);
break;
case SYS_PLL1PFD0:
*frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 0, 1);
break;
case SYS_PLL1PFD0DIV2:
*frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 0, 2);
break;
case SYS_PLL1PFD1:
*frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 1, 1);
break;
case SYS_PLL1PFD1DIV2:
*frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 1, 2);
break;
case SYS_PLL1PFD2:
*frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 2, 1);
break;
case SYS_PLL1PFD2DIV2:
*frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 2, 2);
break;
case AUDIO_PLL1OUT:
*frequency = pll_freq_out(IMX9_AUDIOPLL_BASE, true);
break;
case DRAM_PLLOUT:
*frequency = pll_freq_out(IMX9_DRAMPLL_BASE, true);
break;
case VIDEO_PLL1OUT:
*frequency = pll_freq_out(IMX9_VIDEOPLL_BASE, true);
break;
default:
return -ENODEV;
}
return OK;
}
#endif /* CONFIG_IMX9_CLK_OVER_SCMI */
int imx9_configure_clock(clock_config_t clk_config, bool enabled)
{
#ifdef CONFIG_IMX9_CLK_OVER_SCMI
sm_clock_t sm_clk = /* clang-format off */
{
0
@@ -205,6 +548,40 @@ int imx9_configure_clock(clock_config_t clk_config, bool enabled)
sm_clk.flags = SCMI_CLOCK_RATE_FLAGS_ROUND(SCMI_CLOCK_ROUND_AUTO);
return imx9_sm_setrootclock(&sm_clk);
#else
int ret;
int root = GET_CLOCK_ROOT(clk_config) + ROOT_CLOCK_OFFSET;
int gate = GET_CLOCK_GATE(clk_config);
ret = imx9_ccm_configure_root_clock(
root,
GET_ROOT_MUX(clk_config),
GET_CLOCK_DIV(clk_config));
if (ret)
{
return ret;
}
ret = imx9_ccm_root_clock_on(root, enabled);
if (ret)
{
return ret;
}
if (gate != CCM_LPCG_NONE)
{
ret = imx9_ccm_gate_on(gate, enabled);
if (ret)
{
return ret;
}
}
return OK;
#endif
}
/****************************************************************************
@@ -228,6 +605,7 @@ int imx9_configure_clock(clock_config_t clk_config, bool enabled)
int imx9_get_rootclock(int clkroot, uint32_t *frequency)
{
#ifdef CONFIG_IMX9_CLK_OVER_SCMI
if (clkroot <= CCM_CR_COUNT)
{
uint32_t ret = 0;
@@ -253,5 +631,32 @@ int imx9_get_rootclock(int clkroot, uint32_t *frequency)
}
}
#else
uint32_t reg;
uint32_t div;
uint32_t mux;
int clk_name;
if (clkroot <= CCM_CR_COUNT)
{
reg = getreg32(IMX9_CCM_CR_CTRL(clkroot));
if ((reg & CCM_CR_CTRL_OFF) == CCM_CR_CTRL_OFF)
{
*frequency = 0;
}
else
{
mux = (reg & CCM_CR_CTRL_MUX_MASK) >> CCM_CR_CTRL_MUX_SHIFT;
clk_name = g_ccm_root_mux[clkroot][mux];
imx9_get_clock(clk_name, frequency);
div = ((reg & CCM_CR_CTRL_DIV_MASK) >> CCM_CR_CTRL_DIV_SHIFT) + 1;
*frequency = *frequency / div;
}
return OK;
}
#endif
return -ENODEV;
}
arch/arm/src/imx9/imx9_irq.c
+17 -1
View File
@@ -287,7 +287,23 @@ static int imx9_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
}
else
#endif
#if IMX9_IRQ_NEXTINT > 218
#if IMX9_IRQ_NEXTINT > 224
if (extint < 256)
{
*regaddr = (NVIC_IRQ_ENABLE(224) + offset);
*bit = 1 << (extint - 224);
}
else
#endif
#if IMX9_IRQ_NEXTINT > 256
if (extint < 288)
{
*regaddr = (NVIC_IRQ_ENABLE(256) + offset);
*bit = 1 << (extint - 256);
}
else
#endif
#if IMX9_IRQ_NEXTINT > 288
# error Missing logic
#endif
{
arch/arm/src/imx9/imx9_mu.c
+32
View File
@@ -61,6 +61,22 @@ struct imx9_mudev_s
* Private Data
****************************************************************************/
#ifdef CONFIG_IMX9_MU1
static struct imx9_mudev_s g_mu1_dev = /* clang-format off */
{
.mubase = IMX9_MU1_MUA_BASE,
.irq = IMX9_IRQ_MU1_A
}; /* clang-format on */
#endif
#ifdef CONFIG_IMX9_MU2
static struct imx9_mudev_s g_mu2_dev = /* clang-format off */
{
.mubase = IMX9_MU2_MUA_BASE,
.irq = IMX9_IRQ_MU2_A
}; /* clang-format on */
#endif
#ifdef CONFIG_IMX9_MU5
static struct imx9_mudev_s g_mu5_dev = /* clang-format off */
{
@@ -149,6 +165,22 @@ struct imx9_mudev_s *imx9_mu_init(int index)
{
struct imx9_mudev_s *priv;
#ifdef CONFIG_IMX9_MU1
if ((index == 1))
{
priv = &g_mu1_dev;
}
else
#endif
#ifdef CONFIG_IMX9_MU2
if ((index == 2))
{
priv = &g_mu2_dev;
}
else
#endif
#ifdef CONFIG_IMX9_MU5
if ((index == 5))
{
arch/arm/src/imx9/imx9_xcache.c
+490
View File
@@ -0,0 +1,490 @@
/****************************************************************************
* arch/arm/src/imx9/imx9_xcache.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/cache.h>
#include <arch/barriers.h>
#include "arm_internal.h"
#include "hardware/imx9_xcache.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define XCACHE_LINESIZE_BYTE 16
#define XCACHE_SIZE (16*1024)
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: xcache_wait_busy
*
* Description:
* Wait for cache command to complete by polling GO bit
*
****************************************************************************/
static inline void xcache_wait_busy(uintptr_t base)
{
while (getreg32(base + IMX9_XCACHE_CCR_OFFSET) & XCACHE_CCR_GO)
{
}
}
/****************************************************************************
* Name: xcache_wait_line_busy
*
* Description:
* Wait for cache line command to complete by polling LGO bit
*
****************************************************************************/
static inline void xcache_wait_line_busy(uintptr_t base)
{
while (getreg32(base + IMX9_XCACHE_CSAR_OFFSET) & XCACHE_CSAR_LGO)
{
}
}
/****************************************************************************
* Name: xcache_invalidate_all
*
* Description:
* Invalidate entire cache (both ways)
*
****************************************************************************/
static void xcache_invalidate_all(uintptr_t base)
{
uint32_t regval;
/* Invalidate all lines in both ways and initiate command */
regval = XCACHE_CCR_INVW0 | XCACHE_CCR_INVW1 | XCACHE_CCR_GO;
putreg32(regval, base + IMX9_XCACHE_CCR_OFFSET);
/* Wait until command completes */
xcache_wait_busy(base);
/* Clear command bits, precaution */
regval = getreg32(base + IMX9_XCACHE_CCR_OFFSET);
regval &= ~(XCACHE_CCR_INVW0 | XCACHE_CCR_INVW1);
putreg32(regval, base + IMX9_XCACHE_CCR_OFFSET);
}
/****************************************************************************
* Name: xcache_clean_all
*
* Description:
* Clean (push) entire cache (both ways)
*
****************************************************************************/
static void xcache_clean_all(uintptr_t base)
{
uint32_t regval;
/* Push all modified lines in both ways */
regval = XCACHE_CCR_PUSHW0 | XCACHE_CCR_PUSHW1 | XCACHE_CCR_GO;
putreg32(regval, base + IMX9_XCACHE_CCR_OFFSET);
/* Wait until command completes */
xcache_wait_busy(base);
/* Clear command bits, precaution */
regval = getreg32(base + IMX9_XCACHE_CCR_OFFSET);
regval &= ~(XCACHE_CCR_PUSHW0 | XCACHE_CCR_PUSHW1);
putreg32(regval, base + IMX9_XCACHE_CCR_OFFSET);
}
/****************************************************************************
* Name: xcache_clean_invalidate_all
*
* Description:
* Clean and invalidate entire cache (both ways)
*
****************************************************************************/
static void xcache_clean_invalidate_all(uintptr_t base)
{
uint32_t regval;
/* Push and invalidate all */
regval = XCACHE_CCR_PUSHW0 | XCACHE_CCR_PUSHW1 |
XCACHE_CCR_INVW0 | XCACHE_CCR_INVW1 | XCACHE_CCR_GO;
putreg32(regval, base + IMX9_XCACHE_CCR_OFFSET);
/* Wait until command completes */
xcache_wait_busy(base);
/* Clear command bits, precaution */
regval = getreg32(base + IMX9_XCACHE_CCR_OFFSET);
regval &= ~(XCACHE_CCR_PUSHW0 | XCACHE_CCR_PUSHW1 |
XCACHE_CCR_INVW0 | XCACHE_CCR_INVW1);
putreg32(regval, base + IMX9_XCACHE_CCR_OFFSET);
}
/****************************************************************************
* Name: xcache_op_by_range
*
* Description:
* Perform cache operation by address range (line by line)
*
* Input Parameters:
* base - XCACHE base address
* start - Start address (will be aligned to cache line)
* end - End address + 1
* lcmd - Line command: 1=invalidate, 2=clean, 3=clean+invalidate
*
****************************************************************************/
static void xcache_op_by_range(uintptr_t base, uintptr_t start,
uintptr_t end, uint32_t lcmd)
{
uint32_t regval;
uintptr_t addr;
if (start >= end)
{
return;
}
/* Align start address to cache line size */
addr = start & ~(XCACHE_LINESIZE_BYTE - 1);
/* Set line command and use physical address */
regval = getreg32(base + IMX9_XCACHE_CLCR_OFFSET);
regval &= ~XCACHE_CLCR_LCMD_MASK;
regval |= XCACHE_CLCR_LCMD(lcmd) | XCACHE_CLCR_LADSEL;
putreg32(regval, base + IMX9_XCACHE_CLCR_OFFSET);
/* Process each cache line */
while (addr < end)
{
/* Set address and initiate line command */
regval = (addr & XCACHE_CSAR_PHYADDR_MASK) | XCACHE_CSAR_LGO;
putreg32(regval, base + IMX9_XCACHE_CSAR_OFFSET);
/* Wait for completion */
xcache_wait_line_busy(base);
addr += XCACHE_LINESIZE_BYTE;
}
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_get_icache_linesize
****************************************************************************/
#ifdef CONFIG_IMX9_LPCAC_PC
size_t up_get_icache_linesize(void)
{
return XCACHE_LINESIZE_BYTE; /* XCACHE line size is 32 bytes */
}
#endif
/****************************************************************************
* Name: up_get_icache_size
****************************************************************************/
#ifdef CONFIG_IMX9_LPCAC_PC
size_t up_get_icache_size(void)
{
return XCACHE_SIZE;
}
#endif
/****************************************************************************
* Name: up_enable_icache
****************************************************************************/
#ifdef CONFIG_IMX9_LPCAC_PC
void up_enable_icache(void)
{
uint32_t regval;
/* Return if already enabled */
regval = getreg32(IMX9_LPCAC_PC_BASE + IMX9_XCACHE_CCR_OFFSET);
if (regval & XCACHE_CCR_ENCACHE)
{
return;
}
/* First, invalidate the entire cache */
xcache_invalidate_all(IMX9_LPCAC_PC_BASE);
/* Now enable the cache */
regval = getreg32(IMX9_LPCAC_PC_BASE + IMX9_XCACHE_CCR_OFFSET);
regval |= XCACHE_CCR_ENCACHE;
putreg32(regval, IMX9_LPCAC_PC_BASE + IMX9_XCACHE_CCR_OFFSET);
UP_ISB();
}
#endif
/****************************************************************************
* Name: up_disable_icache
****************************************************************************/
#ifdef CONFIG_IMX9_LPCAC_PC
void up_disable_icache(void)
{
uint32_t regval;
regval = getreg32(IMX9_LPCAC_PC_BASE + IMX9_XCACHE_CCR_OFFSET);
if (!(regval & XCACHE_CCR_ENCACHE))
{
return;
}
/* Disable the cache */
regval &= ~XCACHE_CCR_ENCACHE;
putreg32(regval, IMX9_LPCAC_PC_BASE + IMX9_XCACHE_CCR_OFFSET);
UP_DSB();
UP_ISB();
}
#endif
/****************************************************************************
* Name: up_invalidate_icache
****************************************************************************/
#ifdef CONFIG_IMX9_LPCAC_PC
void up_invalidate_icache(uintptr_t start, uintptr_t end)
{
xcache_op_by_range(IMX9_LPCAC_PC_BASE, start, end, XCACHE_LCMD_INVALIDATE);
UP_ISB();
}
#endif
/****************************************************************************
* Name: up_invalidate_icache_all
****************************************************************************/
#ifdef CONFIG_IMX9_LPCAC_PC
void up_invalidate_icache_all(void)
{
xcache_invalidate_all(IMX9_LPCAC_PC_BASE);
UP_ISB();
}
#endif
/****************************************************************************
* Name: up_get_dcache_linesize
****************************************************************************/
#ifdef CONFIG_IMX9_LPCAC_PS
size_t up_get_dcache_linesize(void)
{
return XCACHE_LINESIZE_BYTE;
}
#endif
/****************************************************************************
* Name: up_get_dcache_size
****************************************************************************/
#ifdef CONFIG_IMX9_LPCAC_PS
size_t up_get_dcache_size(void)
{
return XCACHE_SIZE;
}
#endif
/****************************************************************************
* Name: up_enable_dcache
****************************************************************************/
#ifdef CONFIG_IMX9_LPCAC_PS
void up_enable_dcache(void)
{
uint32_t regval;
/* Return if already enabled */
regval = getreg32(IMX9_LPCAC_PS_BASE + IMX9_XCACHE_CCR_OFFSET);
if (regval & XCACHE_CCR_ENCACHE)
{
return;
}
/* First, invalidate the entire cache */
xcache_invalidate_all(IMX9_LPCAC_PS_BASE);
/* Now enable the cache */
regval = getreg32(IMX9_LPCAC_PS_BASE + IMX9_XCACHE_CCR_OFFSET);
regval |= XCACHE_CCR_ENCACHE;
putreg32(regval, IMX9_LPCAC_PS_BASE + IMX9_XCACHE_CCR_OFFSET);
UP_DSB();
}
#endif
/****************************************************************************
* Name: up_disable_dcache
****************************************************************************/
#ifdef CONFIG_IMX9_LPCAC_PS
void up_disable_dcache(void)
{
uint32_t regval;
regval = getreg32(IMX9_LPCAC_PS_BASE + IMX9_XCACHE_CCR_OFFSET);
if (!(regval & XCACHE_CCR_ENCACHE))
{
return;
}
/* First, clean any modified contents */
xcache_clean_all(IMX9_LPCAC_PS_BASE);
/* Now disable the cache */
regval &= ~XCACHE_CCR_ENCACHE;
putreg32(regval, IMX9_LPCAC_PS_BASE + IMX9_XCACHE_CCR_OFFSET);
UP_DSB();
}
#endif
/****************************************************************************
* Name: up_invalidate_dcache
****************************************************************************/
#ifdef CONFIG_IMX9_LPCAC_PS
void up_invalidate_dcache(uintptr_t start, uintptr_t end)
{
xcache_op_by_range(IMX9_LPCAC_PS_BASE, start, end, XCACHE_LCMD_INVALIDATE);
UP_DSB();
}
#endif
/****************************************************************************
* Name: up_invalidate_dcache_all
****************************************************************************/
#ifdef CONFIG_IMX9_LPCAC_PS
void up_invalidate_dcache_all(void)
{
xcache_invalidate_all(IMX9_LPCAC_PS_BASE);
UP_DSB();
}
#endif
/****************************************************************************
* Name: up_clean_dcache
****************************************************************************/
#ifdef CONFIG_IMX9_LPCAC_PS
void up_clean_dcache(uintptr_t start, uintptr_t end)
{
xcache_op_by_range(IMX9_LPCAC_PS_BASE, start, end, XCACHE_LCMD_PUSH);
UP_DSB();
}
#endif
/****************************************************************************
* Name: up_clean_dcache_all
****************************************************************************/
#ifdef CONFIG_IMX9_LPCAC_PS
void up_clean_dcache_all(void)
{
xcache_clean_all(IMX9_LPCAC_PS_BASE);
UP_DSB();
}
#endif
/****************************************************************************
* Name: up_flush_dcache
****************************************************************************/
#ifdef CONFIG_IMX9_LPCAC_PS
void up_flush_dcache(uintptr_t start, uintptr_t end)
{
xcache_op_by_range(IMX9_LPCAC_PS_BASE, start, end, XCACHE_LCMD_CLEAR);
UP_DSB();
}
#endif
/****************************************************************************
* Name: up_flush_dcache_all
****************************************************************************/
#ifdef CONFIG_IMX9_LPCAC_PS
void up_flush_dcache_all(void)
{
xcache_clean_invalidate_all(IMX9_LPCAC_PS_BASE);
UP_DSB();
}
#endif
/****************************************************************************
* Name: up_coherent_dcache
****************************************************************************/
#if defined(CONFIG_IMX9_LPCAC_PS)
void up_coherent_dcache(uintptr_t addr, size_t len)
{
/* Clean PS cache and invalidate PC cache for code coherency */
up_clean_dcache(addr, addr + len);
#if defined(CONFIG_IMX9_LPCAC_PC)
up_invalidate_icache(addr, addr + len);
#endif
}
#endif