diff --git a/arch/arm/include/imx9/imx93_irq.h b/arch/arm/include/imx9/imx93_irq.h new file mode 100644 index 00000000000..a6b3ee6bc6e --- /dev/null +++ b/arch/arm/include/imx9/imx93_irq.h @@ -0,0 +1,304 @@ +/**************************************************************************** + * arch/arm/include/imx9/imx93_irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_IMX9_IMX93_IRQ_H +#define __ARCH_ARM_INCLUDE_IMX9_IMX93_IRQ_H + +#define IMX9_IRQ_RESERVED32 (IMX9_IRQ_EXTINT + 0) /* Exception condition notification while boot */ +#define IMX9_IRQ_RESERVED33 (IMX9_IRQ_EXTINT + 1) /* DAP interrupt */ +#define IMX9_IRQ_RESERVED34 (IMX9_IRQ_EXTINT + 2) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED35 (IMX9_IRQ_EXTINT + 3) /* CTI trigger outputs from CM33 platform */ +#define IMX9_IRQ_RESERVED36 (IMX9_IRQ_EXTINT + 4) /* CTI trigger outputs from CA55 platform */ +#define IMX9_IRQ_RESERVED37 (IMX9_IRQ_EXTINT + 5) /* Performance Unit Interrupts from CA55 platform */ +#define IMX9_IRQ_RESERVED38 (IMX9_IRQ_EXTINT + 6) /* ECC error from CA55 platform cache */ +#define IMX9_IRQ_RESERVED39 (IMX9_IRQ_EXTINT + 7) /* 1-bit or 2-bit ECC or Parity error from CA55 platform cache */ +#define IMX9_IRQ_CAN1 (IMX9_IRQ_EXTINT + 8) /* CAN1 interrupt */ +#define IMX9_IRQ_CAN1_ERROR (IMX9_IRQ_EXTINT + 9) /* CAN1 error interrupt */ +#define IMX9_IRQ_GPIO1_0 (IMX9_IRQ_EXTINT + 10) /* General Purpose Input/Output 1 interrupt 0 */ +#define IMX9_IRQ_GPIO1_1 (IMX9_IRQ_EXTINT + 11) /* General Purpose Input/Output 1 interrupt 1 */ +#define IMX9_IRQ_I3C1 (IMX9_IRQ_EXTINT + 12) /* Improved Inter-Integrated Circuit 1 interrupt */ +#define IMX9_IRQ_LPI2C1 (IMX9_IRQ_EXTINT + 13) /* Low Power Inter-Integrated Circuit module 1 */ +#define IMX9_IRQ_LPI2C2 (IMX9_IRQ_EXTINT + 14) /* Low Power Inter-Integrated Circuit module 2 */ +#define IMX9_IRQ_LPIT1 (IMX9_IRQ_EXTINT + 15) /* Low Power Periodic Interrupt Timer 1 */ +#define IMX9_IRQ_LPSPI1 (IMX9_IRQ_EXTINT + 16) /* Low Power Serial Peripheral Interface 1 */ +#define IMX9_IRQ_LPSPI2 (IMX9_IRQ_EXTINT + 17) /* Low Power Serial Peripheral Interface 2 */ +#define IMX9_IRQ_LPTMR1 (IMX9_IRQ_EXTINT + 18) /* Low Power Timer 1 */ +#define IMX9_IRQ_LPUART1 (IMX9_IRQ_EXTINT + 19) /* Low Power UART 1 */ +#define IMX9_IRQ_LPUART2 (IMX9_IRQ_EXTINT + 20) /* Low Power UART 2 */ +#define IMX9_IRQ_MU1_A (IMX9_IRQ_EXTINT + 21) /* Messaging Unit 1 - Side A (to communicate with M7 core) */ +#define IMX9_IRQ_MU1_B (IMX9_IRQ_EXTINT + 22) /* Messaging Unit 1 - Side B (to communicate with M33 core) */ +#define IMX9_IRQ_MU2_A (IMX9_IRQ_EXTINT + 23) /* Messaging Unit 2 - Side A (to communicate with M7 core) */ +#define IMX9_IRQ_MU2_B (IMX9_IRQ_EXTINT + 24) /* Messaging Unit 2 - Side B (to communicate with A55 core) */ +#define IMX9_IRQ_RESERVED57 (IMX9_IRQ_EXTINT + 25) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED58 (IMX9_IRQ_EXTINT + 26) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED59 (IMX9_IRQ_EXTINT + 27) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED60 (IMX9_IRQ_EXTINT + 28) /* Edgelock Trust MUA RX full interrupt */ +#define IMX9_IRQ_RESERVED61 (IMX9_IRQ_EXTINT + 29) /* Edgelock Trust MUA TX empty interrupt */ +#define IMX9_IRQ_RESERVED62 (IMX9_IRQ_EXTINT + 30) /* Edgelock Apps Core MUA RX full interrupt */ +#define IMX9_IRQ_RESERVED63 (IMX9_IRQ_EXTINT + 31) /* Edgelock Apps Core MUA TX empty interrupt */ +#define IMX9_IRQ_RESERVED64 (IMX9_IRQ_EXTINT + 32) /* Edgelock Realtime Core MUA RX full interrupt */ +#define IMX9_IRQ_RESERVED65 (IMX9_IRQ_EXTINT + 33) /* Edgelock Realtime Core MUA TX empty interrupt */ +#define IMX9_IRQ_RESERVED66 (IMX9_IRQ_EXTINT + 34) /* Edgelock secure interrupt */ +#define IMX9_IRQ_RESERVED67 (IMX9_IRQ_EXTINT + 35) /* Edgelock non-secure interrupt */ +#define IMX9_IRQ_TPM1 (IMX9_IRQ_EXTINT + 36) /* Timer PWM module 1 */ +#define IMX9_IRQ_TPM2 (IMX9_IRQ_EXTINT + 37) /* Timer PWM module 2 */ +#define IMX9_IRQ_WDOG1 (IMX9_IRQ_EXTINT + 38) /* Watchdog 1 Interrupt */ +#define IMX9_IRQ_WDOG2 (IMX9_IRQ_EXTINT + 39) /* Watchdog 2 Interrupt */ +#define IMX9_IRQ_TRDC (IMX9_IRQ_EXTINT + 40) /* AONMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED73 (IMX9_IRQ_EXTINT + 41) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED74 (IMX9_IRQ_EXTINT + 42) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED75 (IMX9_IRQ_EXTINT + 43) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED76 (IMX9_IRQ_EXTINT + 44) /* Reserved interrupt */ +#define IMX9_IRQ_SAI1 (IMX9_IRQ_EXTINT + 45) /* Serial Audio Interface 1 */ +#define IMX9_IRQ_RESERVED78 (IMX9_IRQ_EXTINT + 46) /* M33 PS Tag/Data Parity Error */ +#define IMX9_IRQ_RESERVED79 (IMX9_IRQ_EXTINT + 47) /* M33 TCM ECC interrupt */ +#define IMX9_IRQ_RESERVED80 (IMX9_IRQ_EXTINT + 48) /* M33 TCM Error interrupt */ +#define IMX9_IRQ_RESERVED81 (IMX9_IRQ_EXTINT + 49) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED82 (IMX9_IRQ_EXTINT + 50) /* Reserved interrupt */ +#define IMX9_IRQ_CAN2 (IMX9_IRQ_EXTINT + 51) /* CAN2 interrupt */ +#define IMX9_IRQ_CAN2_ERROR (IMX9_IRQ_EXTINT + 52) /* CAN2 error interrupt */ +#define IMX9_IRQ_FLEXIO1 (IMX9_IRQ_EXTINT + 53) /* Flexible IO 1 interrupt */ +#define IMX9_IRQ_FLEXIO2 (IMX9_IRQ_EXTINT + 54) /* Flexible IO 2 interrupt */ +#define IMX9_IRQ_FLEXSPI1 (IMX9_IRQ_EXTINT + 55) /* FlexSPI controller interface interrupt 1 */ +#define IMX9_IRQ_RESERVED88 (IMX9_IRQ_EXTINT + 56) /* Reserved interrupt */ +#define IMX9_IRQ_GPIO2_0 (IMX9_IRQ_EXTINT + 57) /* General Purpose Input/Output 2 interrupt 0 */ +#define IMX9_IRQ_GPIO2_1 (IMX9_IRQ_EXTINT + 58) /* General Purpose Input/Output 2 interrupt 1 */ +#define IMX9_IRQ_GPIO3_0 (IMX9_IRQ_EXTINT + 59) /* General Purpose Input/Output 3 interrupt 0 */ +#define IMX9_IRQ_GPIO3_1 (IMX9_IRQ_EXTINT + 60) /* General Purpose Input/Output 3 interrupt 1 */ +#define IMX9_IRQ_I3C2 (IMX9_IRQ_EXTINT + 61) /* Improved Inter-Integrated Circuit 2 interrupt */ +#define IMX9_IRQ_LPI2C3 (IMX9_IRQ_EXTINT + 62) /* Low Power Inter-Integrated Circuit module 3 */ +#define IMX9_IRQ_LPI2C4 (IMX9_IRQ_EXTINT + 63) /* Low Power Inter-Integrated Circuit module 4 */ +#define IMX9_IRQ_LPIT2 (IMX9_IRQ_EXTINT + 64) /* Low Power Periodic Interrupt Timer 2 */ +#define IMX9_IRQ_LPSPI3 (IMX9_IRQ_EXTINT + 65) /* Low Power Serial Peripheral Interface 3 */ +#define IMX9_IRQ_LPSPI4 (IMX9_IRQ_EXTINT + 66) /* Low Power Serial Peripheral Interface 4 */ +#define IMX9_IRQ_LPTMR2 (IMX9_IRQ_EXTINT + 67) /* Low Power Timer 2 */ +#define IMX9_IRQ_LPUART3 (IMX9_IRQ_EXTINT + 68) /* Low Power UART 3 */ +#define IMX9_IRQ_LPUART4 (IMX9_IRQ_EXTINT + 69) /* Low Power UART 4 */ +#define IMX9_IRQ_LPUART5 (IMX9_IRQ_EXTINT + 70) /* Low Power UART 5 */ +#define IMX9_IRQ_LPUART6 (IMX9_IRQ_EXTINT + 71) /* Low Power UART 6 */ +#define IMX9_IRQ_RESERVED104 (IMX9_IRQ_EXTINT + 72) /* MTR Master error interrupt */ +#define IMX9_IRQ_RESERVED105 (IMX9_IRQ_EXTINT + 73) /* BBNSM Non-Secure interrupt */ +#define IMX9_IRQ_RESERVED106 (IMX9_IRQ_EXTINT + 74) /* System Counter compare interrupt */ +#define IMX9_IRQ_TPM3 (IMX9_IRQ_EXTINT + 75) /* Timer PWM module 3 */ +#define IMX9_IRQ_TPM4 (IMX9_IRQ_EXTINT + 76) /* Timer PWM module 4 */ +#define IMX9_IRQ_TPM5 (IMX9_IRQ_EXTINT + 77) /* Timer PWM module 5 */ +#define IMX9_IRQ_TPM6 (IMX9_IRQ_EXTINT + 78) /* Timer PWM module 6 */ +#define IMX9_IRQ_WDOG3 (IMX9_IRQ_EXTINT + 79) /* Watchdog 3 Interrupt */ +#define IMX9_IRQ_WDOG4 (IMX9_IRQ_EXTINT + 80) /* Watchdog 4 Interrupt */ +#define IMX9_IRQ_WDOG5 (IMX9_IRQ_EXTINT + 81) /* Watchdog 5 Interrupt */ +#define IMX9_IRQ_RESERVED114 (IMX9_IRQ_EXTINT + 82) /* WAKEUPMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_TEMPMON (IMX9_IRQ_EXTINT + 83) /* TempSensor interrupt */ +#define IMX9_IRQ_RESERVED116 (IMX9_IRQ_EXTINT + 84) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED117 (IMX9_IRQ_EXTINT + 85) /* Reserved interrupt */ +#define IMX9_IRQ_USDHC1 (IMX9_IRQ_EXTINT + 86) /* ultra Secure Digital Host Controller interrupt 1 */ +#define IMX9_IRQ_USDHC2 (IMX9_IRQ_EXTINT + 87) /* ultra Secure Digital Host Controller interrupt 2 */ +#define IMX9_IRQ_RESERVED120 (IMX9_IRQ_EXTINT + 88) /* MEGAMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED121 (IMX9_IRQ_EXTINT + 89) /* NIC_WRAPPER TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED122 (IMX9_IRQ_EXTINT + 90) /* DRAM controller Performance Monitor Interrupt */ +#define IMX9_IRQ_RESERVED123 (IMX9_IRQ_EXTINT + 91) /* DRAM controller Critical Interrupt */ +#define IMX9_IRQ_RESERVED124 (IMX9_IRQ_EXTINT + 92) /* DRAM Phy Critical Interrupt */ +#define IMX9_IRQ_RESERVED125 (IMX9_IRQ_EXTINT + 93) /* Reserved interrupt */ +#define IMX9_IRQ_DMA3_ERROR (IMX9_IRQ_EXTINT + 94) /* eDMA1 error interrupt */ +#define IMX9_IRQ_DMA3_0 (IMX9_IRQ_EXTINT + 95) /* eDMA1 channel 0 interrupt */ +#define IMX9_IRQ_DMA3_1 (IMX9_IRQ_EXTINT + 96) /* eDMA1 channel 1 interrupt */ +#define IMX9_IRQ_DMA3_2 (IMX9_IRQ_EXTINT + 97) /* eDMA1 channel 2 interrupt */ +#define IMX9_IRQ_DMA3_3 (IMX9_IRQ_EXTINT + 98) /* eDMA1 channel 3 interrupt */ +#define IMX9_IRQ_DMA3_4 (IMX9_IRQ_EXTINT + 99) /* eDMA1 channel 4 interrupt */ +#define IMX9_IRQ_DMA3_5 (IMX9_IRQ_EXTINT + 100) /* eDMA1 channel 5 interrupt */ +#define IMX9_IRQ_DMA3_6 (IMX9_IRQ_EXTINT + 101) /* eDMA1 channel 6 interrupt */ +#define IMX9_IRQ_DMA3_7 (IMX9_IRQ_EXTINT + 102) /* eDMA1 channel 7 interrupt */ +#define IMX9_IRQ_DMA3_8 (IMX9_IRQ_EXTINT + 103) /* eDMA1 channel 8 interrupt */ +#define IMX9_IRQ_DMA3_9 (IMX9_IRQ_EXTINT + 104) /* eDMA1 channel 9 interrupt */ +#define IMX9_IRQ_DMA3_10 (IMX9_IRQ_EXTINT + 105) /* eDMA1 channel 10 interrupt */ +#define IMX9_IRQ_DMA3_11 (IMX9_IRQ_EXTINT + 106) /* eDMA1 channel 11 interrupt */ +#define IMX9_IRQ_DMA3_12 (IMX9_IRQ_EXTINT + 107) /* eDMA1 channel 12 interrupt */ +#define IMX9_IRQ_DMA3_13 (IMX9_IRQ_EXTINT + 108) /* eDMA1 channel 13 interrupt */ +#define IMX9_IRQ_DMA3_14 (IMX9_IRQ_EXTINT + 109) /* eDMA1 channel 14 interrupt */ +#define IMX9_IRQ_DMA3_15 (IMX9_IRQ_EXTINT + 110) /* eDMA1 channel 15 interrupt */ +#define IMX9_IRQ_DMA3_16 (IMX9_IRQ_EXTINT + 111) /* eDMA1 channel 16 interrupt */ +#define IMX9_IRQ_DMA3_17 (IMX9_IRQ_EXTINT + 112) /* eDMA1 channel 17 interrupt */ +#define IMX9_IRQ_DMA3_18 (IMX9_IRQ_EXTINT + 113) /* eDMA1 channel 18 interrupt */ +#define IMX9_IRQ_DMA3_19 (IMX9_IRQ_EXTINT + 114) /* eDMA1 channel 19 interrupt */ +#define IMX9_IRQ_DMA3_20 (IMX9_IRQ_EXTINT + 115) /* eDMA1 channel 20 interrupt */ +#define IMX9_IRQ_DMA3_21 (IMX9_IRQ_EXTINT + 116) /* eDMA1 channel 21 interrupt */ +#define IMX9_IRQ_DMA3_22 (IMX9_IRQ_EXTINT + 117) /* eDMA1 channel 22 interrupt */ +#define IMX9_IRQ_DMA3_23 (IMX9_IRQ_EXTINT + 118) /* eDMA1 channel 23 interrupt */ +#define IMX9_IRQ_DMA3_24 (IMX9_IRQ_EXTINT + 119) /* eDMA1 channel 24 interrupt */ +#define IMX9_IRQ_DMA3_25 (IMX9_IRQ_EXTINT + 120) /* eDMA1 channel 25 interrupt */ +#define IMX9_IRQ_DMA3_26 (IMX9_IRQ_EXTINT + 121) /* eDMA1 channel 26 interrupt */ +#define IMX9_IRQ_DMA3_27 (IMX9_IRQ_EXTINT + 122) /* eDMA1 channel 27 interrupt */ +#define IMX9_IRQ_DMA3_28 (IMX9_IRQ_EXTINT + 123) /* eDMA1 channel 28 interrupt */ +#define IMX9_IRQ_DMA3_29 (IMX9_IRQ_EXTINT + 124) /* eDMA1 channel 29 interrupt */ +#define IMX9_IRQ_DMA3_30 (IMX9_IRQ_EXTINT + 125) /* eDMA1 channel 30 interrupt */ +#define IMX9_IRQ_RESERVED158 (IMX9_IRQ_EXTINT + 126) /* Reserved interrupt */ +#define IMX9_IRQ_DMA4_ERROR (IMX9_IRQ_EXTINT + 127) /* eDMA2 error interrupt */ +#define IMX9_IRQ_DMA4_0_1 (IMX9_IRQ_EXTINT + 128) /* eDMA2 channel 0/1 interrupt */ +#define IMX9_IRQ_DMA4_2_3 (IMX9_IRQ_EXTINT + 129) /* eDMA2 channel 2/3 interrupt */ +#define IMX9_IRQ_DMA4_4_5 (IMX9_IRQ_EXTINT + 130) /* eDMA2 channel 4/5 interrupt */ +#define IMX9_IRQ_DMA4_6_7 (IMX9_IRQ_EXTINT + 131) /* eDMA2 channel 6/7 interrupt */ +#define IMX9_IRQ_DMA4_8_9 (IMX9_IRQ_EXTINT + 132) /* eDMA2 channel 8/9 interrupt */ +#define IMX9_IRQ_DMA4_10_11 (IMX9_IRQ_EXTINT + 133) /* eDMA2 channel 10/11 interrupt */ +#define IMX9_IRQ_DMA4_12_13 (IMX9_IRQ_EXTINT + 134) /* eDMA2 channel 12/13 interrupt */ +#define IMX9_IRQ_DMA4_14_15 (IMX9_IRQ_EXTINT + 135) /* eDMA2 channel 14/15 interrupt */ +#define IMX9_IRQ_DMA4_16_17 (IMX9_IRQ_EXTINT + 136) /* eDMA2 channel 16/17 interrupt */ +#define IMX9_IRQ_DMA4_18_19 (IMX9_IRQ_EXTINT + 137) /* eDMA2 channel 18/19 interrupt */ +#define IMX9_IRQ_DMA4_20_21 (IMX9_IRQ_EXTINT + 138) /* eDMA2 channel 20/21 interrupt */ +#define IMX9_IRQ_DMA4_22_23 (IMX9_IRQ_EXTINT + 139) /* eDMA2 channel 22/23 interrupt */ +#define IMX9_IRQ_DMA4_24_25 (IMX9_IRQ_EXTINT + 140) /* eDMA2 channel 24/25 interrupt */ +#define IMX9_IRQ_DMA4_26_27 (IMX9_IRQ_EXTINT + 141) /* eDMA2 channel 26/27 interrupt */ +#define IMX9_IRQ_DMA4_28_29 (IMX9_IRQ_EXTINT + 142) /* eDMA2 channel 28/29 interrupt */ +#define IMX9_IRQ_DMA4_30_31 (IMX9_IRQ_EXTINT + 143) /* eDMA2 channel 30/31 interrupt */ +#define IMX9_IRQ_DMA4_32_33 (IMX9_IRQ_EXTINT + 144) /* eDMA2 channel 32/33 interrupt */ +#define IMX9_IRQ_DMA4_34_35 (IMX9_IRQ_EXTINT + 145) /* eDMA2 channel 34/35 interrupt */ +#define IMX9_IRQ_DMA4_36_37 (IMX9_IRQ_EXTINT + 146) /* eDMA2 channel 36/37 interrupt */ +#define IMX9_IRQ_DMA4_38_39 (IMX9_IRQ_EXTINT + 147) /* eDMA2 channel 38/39 interrupt */ +#define IMX9_IRQ_DMA4_40_41 (IMX9_IRQ_EXTINT + 148) /* eDMA2 channel 40/41 interrupt */ +#define IMX9_IRQ_DMA4_42_43 (IMX9_IRQ_EXTINT + 149) /* eDMA2 channel 42/43 interrupt */ +#define IMX9_IRQ_DMA4_44_45 (IMX9_IRQ_EXTINT + 150) /* eDMA2 channel 44/45 interrupt */ +#define IMX9_IRQ_DMA4_46_47 (IMX9_IRQ_EXTINT + 151) /* eDMA2 channel 46/47 interrupt */ +#define IMX9_IRQ_DMA4_48_49 (IMX9_IRQ_EXTINT + 152) /* eDMA2 channel 48/49 interrupt */ +#define IMX9_IRQ_DMA4_50_51 (IMX9_IRQ_EXTINT + 153) /* eDMA2 channel 50/51 interrupt */ +#define IMX9_IRQ_DMA4_52_53 (IMX9_IRQ_EXTINT + 154) /* eDMA2 channel 52/53 interrupt */ +#define IMX9_IRQ_DMA4_54_55 (IMX9_IRQ_EXTINT + 155) /* eDMA2 channel 54/55 interrupt */ +#define IMX9_IRQ_DMA4_56_57 (IMX9_IRQ_EXTINT + 156) /* eDMA2 channel 56/57 interrupt */ +#define IMX9_IRQ_DMA4_58_59 (IMX9_IRQ_EXTINT + 157) /* eDMA2 channel 58/59 interrupt */ +#define IMX9_IRQ_DMA4_60_61 (IMX9_IRQ_EXTINT + 158) /* eDMA2 channel 60/61 interrupt */ +#define IMX9_IRQ_DMA4_62_63 (IMX9_IRQ_EXTINT + 159) /* eDMA2 channel 62/63 interrupt */ +#define IMX9_IRQ_RESERVED192 (IMX9_IRQ_EXTINT + 160) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED193 (IMX9_IRQ_EXTINT + 161) /* Edgelock Group 1 reset source */ +#define IMX9_IRQ_RESERVED194 (IMX9_IRQ_EXTINT + 162) /* Edgelock Group 2 reset source */ +#define IMX9_IRQ_RESERVED195 (IMX9_IRQ_EXTINT + 163) /* Edgelock Group 2 reset source */ +#define IMX9_IRQ_RESERVED196 (IMX9_IRQ_EXTINT + 164) /* JTAGSW DAP MDM-AP SRC reset source */ +#define IMX9_IRQ_RESERVED197 (IMX9_IRQ_EXTINT + 165) /* JTAGC SRC reset source */ +#define IMX9_IRQ_RESERVED198 (IMX9_IRQ_EXTINT + 166) /* CM33 SYSREQRST SRC reset source */ +#define IMX9_IRQ_RESERVED199 (IMX9_IRQ_EXTINT + 167) /* CM33 LOCKUP SRC reset source */ +#define IMX9_IRQ_RESERVED200 (IMX9_IRQ_EXTINT + 168) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED201 (IMX9_IRQ_EXTINT + 169) /* Reserved interrupt */ +#define IMX9_IRQ_SAI2 (IMX9_IRQ_EXTINT + 170) /* Serial Audio Interface 2 */ +#define IMX9_IRQ_SAI3 (IMX9_IRQ_EXTINT + 171) /* Serial Audio Interface 3 */ +#define IMX9_IRQ_ISI (IMX9_IRQ_EXTINT + 172) /* ISI interrupt */ +#define IMX9_IRQ_RESERVED205 (IMX9_IRQ_EXTINT + 173) /* PXP interrupt 0 */ +#define IMX9_IRQ_RESERVED206 (IMX9_IRQ_EXTINT + 174) /* PXP interrupt 1 */ +#define IMX9_IRQ_CSI (IMX9_IRQ_EXTINT + 175) /* CSI interrupt */ +#define IMX9_IRQ_RESERVED208 (IMX9_IRQ_EXTINT + 176) /* LCDIF Sync Interrupt */ +#define IMX9_IRQ_DSI (IMX9_IRQ_EXTINT + 177) /* MIPI DSI Interrupt Request */ +#define IMX9_IRQ_RESERVED210 (IMX9_IRQ_EXTINT + 178) /* Machine learning processor interrupt */ +#define IMX9_IRQ_ENET_MAC0_RX_TX_D ONE1 (IMX9_IRQ_EXTINT + 179) /* MAC 0 Receive/ Transmit Frame/ Buffer Done */ +#define IMX9_IRQ_ENET_MAC0_RX_TX_D ONE2 (IMX9_IRQ_EXTINT + 180) /* MAC 0 Receive/ Transmit Frame/ Buffer Done */ +#define IMX9_IRQ_ENET (IMX9_IRQ_EXTINT + 181) /* MAC 0 IRQ */ +#define IMX9_IRQ_ENET_1588 (IMX9_IRQ_EXTINT + 182) /* MAC 0 1588 Timer Interrupt - synchronous */ +#define IMX9_IRQ_ENET_QOS_PMT (IMX9_IRQ_EXTINT + 183) /* ENET QOS PMT interrupt */ +#define IMX9_IRQ_ENET_QOS (IMX9_IRQ_EXTINT + 184) /* ENET QOS interrupt */ +#define IMX9_IRQ_RESERVED217 (IMX9_IRQ_EXTINT + 185) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED218 (IMX9_IRQ_EXTINT + 186) /* Reserved interrupt */ +#define IMX9_IRQ_USB1 (IMX9_IRQ_EXTINT + 187) /* USB-1 Wake-up Interrupt */ +#define IMX9_IRQ_USB2 (IMX9_IRQ_EXTINT + 188) /* USB-2 Wake-up Interrupt */ +#define IMX9_IRQ_GPIO4_0 (IMX9_IRQ_EXTINT + 189) /* General Purpose Input/Output 4 interrupt 0 */ +#define IMX9_IRQ_GPIO4_1 (IMX9_IRQ_EXTINT + 190) /* General Purpose Input/Output 4 interrupt 1 */ +#define IMX9_IRQ_LPSPI5 (IMX9_IRQ_EXTINT + 191) /* Low Power Serial Peripheral Interface 5 */ +#define IMX9_IRQ_LPSPI6 (IMX9_IRQ_EXTINT + 192) /* Low Power Serial Peripheral Interface 6 */ +#define IMX9_IRQ_LPSPI7 (IMX9_IRQ_EXTINT + 193) /* Low Power Serial Peripheral Interface 7 */ +#define IMX9_IRQ_LPSPI8 (IMX9_IRQ_EXTINT + 194) /* Low Power Serial Peripheral Interface 8 */ +#define IMX9_IRQ_LPI2C5 (IMX9_IRQ_EXTINT + 195) /* Low Power Inter-Integrated Circuit module 5 */ +#define IMX9_IRQ_LPI2C6 (IMX9_IRQ_EXTINT + 196) /* Low Power Inter-Integrated Circuit module 6 */ +#define IMX9_IRQ_LPI2C7 (IMX9_IRQ_EXTINT + 197) /* Low Power Inter-Integrated Circuit module 7 */ +#define IMX9_IRQ_LPI2C8 (IMX9_IRQ_EXTINT + 198) /* Low Power Inter-Integrated Circuit module 8 */ +#define IMX9_IRQ_PDM_HWVAD_ERROR (IMX9_IRQ_EXTINT + 199) /* PDM interrupt */ +#define IMX9_IRQ_PDM_HWVAD_EVENT (IMX9_IRQ_EXTINT + 200) /* PDM interrupt */ +#define IMX9_IRQ_PDM_ERROR (IMX9_IRQ_EXTINT + 201) /* PDM interrupt */ +#define IMX9_IRQ_PDM_EVENT (IMX9_IRQ_EXTINT + 202) /* PDM interrupt */ +#define IMX9_IRQ_RESERVED235 (IMX9_IRQ_EXTINT + 203) /* AUDIO XCVR interrupt */ +#define IMX9_IRQ_RESERVED236 (IMX9_IRQ_EXTINT + 204) /* AUDIO XCVR interrupt */ +#define IMX9_IRQ_USDHC3 (IMX9_IRQ_EXTINT + 205) /* ultra Secure Digital Host Controller interrupt 3 */ +#define IMX9_IRQ_RESERVED238 (IMX9_IRQ_EXTINT + 206) /* OCRAM MECC interrupt */ +#define IMX9_IRQ_RESERVED239 (IMX9_IRQ_EXTINT + 207) /* OCRAM MECC interrupt */ +#define IMX9_IRQ_RESERVED240 (IMX9_IRQ_EXTINT + 208) /* HSIOMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED241 (IMX9_IRQ_EXTINT + 209) /* MEDIAMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_LPUART7 (IMX9_IRQ_EXTINT + 210) /* Low Power UART 7 */ +#define IMX9_IRQ_LPUART8 (IMX9_IRQ_EXTINT + 211) /* Low Power UART 8 */ +#define IMX9_IRQ_RESERVED244 (IMX9_IRQ_EXTINT + 212) /* CM33 MCM interrupt */ +#define IMX9_IRQ_RESERVED245 (IMX9_IRQ_EXTINT + 213) /* SFA interrupt */ +#define IMX9_IRQ_RESERVED246 (IMX9_IRQ_EXTINT + 214) /* GIC600 INTERRUPT */ +#define IMX9_IRQ_RESERVED247 (IMX9_IRQ_EXTINT + 215) /* GIC600 INTERRUPT */ +#define IMX9_IRQ_RESERVED248 (IMX9_IRQ_EXTINT + 216) /* GIC600 INTERRUPT */ +#define IMX9_IRQ_RESERVED249 (IMX9_IRQ_EXTINT + 217) /* ADC interrupt */ +#define IMX9_IRQ_RESERVED250 (IMX9_IRQ_EXTINT + 218) /* ADC interrupt */ +#define IMX9_IRQ_RESERVED251 (IMX9_IRQ_EXTINT + 219) /* ADC interrupt */ +#define IMX9_IRQ_RESERVED252 (IMX9_IRQ_EXTINT + 220) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED253 (IMX9_IRQ_EXTINT + 221) /* I3C1 wakeup irq after double sync */ +#define IMX9_IRQ_RESERVED254 (IMX9_IRQ_EXTINT + 222) /* I3C2 wakeup irq after double sync */ +#define IMX9_IRQ_RESERVED255 (IMX9_IRQ_EXTINT + 223) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED256 (IMX9_IRQ_EXTINT + 224) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED257 (IMX9_IRQ_EXTINT + 225) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED258 (IMX9_IRQ_EXTINT + 226) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED259 (IMX9_IRQ_EXTINT + 227) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED260 (IMX9_IRQ_EXTINT + 228) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED261 (IMX9_IRQ_EXTINT + 229) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED262 (IMX9_IRQ_EXTINT + 230) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED263 (IMX9_IRQ_EXTINT + 231) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED264 (IMX9_IRQ_EXTINT + 232) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED265 (IMX9_IRQ_EXTINT + 233) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED266 (IMX9_IRQ_EXTINT + 234) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED267 (IMX9_IRQ_EXTINT + 235) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED268 (IMX9_IRQ_EXTINT + 236) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED269 (IMX9_IRQ_EXTINT + 237) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED270 (IMX9_IRQ_EXTINT + 238) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED271 (IMX9_IRQ_EXTINT + 239) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED272 (IMX9_IRQ_EXTINT + 240) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED273 (IMX9_IRQ_EXTINT + 241) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED274 (IMX9_IRQ_EXTINT + 242) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED275 (IMX9_IRQ_EXTINT + 243) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED276 (IMX9_IRQ_EXTINT + 244) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED277 (IMX9_IRQ_EXTINT + 245) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED278 (IMX9_IRQ_EXTINT + 246) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED279 (IMX9_IRQ_EXTINT + 247) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED280 (IMX9_IRQ_EXTINT + 248) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED281 (IMX9_IRQ_EXTINT + 249) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED282 (IMX9_IRQ_EXTINT + 250) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED283 (IMX9_IRQ_EXTINT + 251) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED284 (IMX9_IRQ_EXTINT + 252) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED285 (IMX9_IRQ_EXTINT + 253) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED286 (IMX9_IRQ_EXTINT + 254) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED287 (IMX9_IRQ_EXTINT + 255) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED288 (IMX9_IRQ_EXTINT + 256) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED289 (IMX9_IRQ_EXTINT + 257) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED290 (IMX9_IRQ_EXTINT + 258) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED291 (IMX9_IRQ_EXTINT + 259) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED292 (IMX9_IRQ_EXTINT + 260) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED293 (IMX9_IRQ_EXTINT + 261) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED294 (IMX9_IRQ_EXTINT + 262) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED295 (IMX9_IRQ_EXTINT + 263) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED296 (IMX9_IRQ_EXTINT + 264) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED297 (IMX9_IRQ_EXTINT + 265) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED298 (IMX9_IRQ_EXTINT + 266) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED299 (IMX9_IRQ_EXTINT + 267) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED300 (IMX9_IRQ_EXTINT + 268) /* ADC Asynchronous Interrupt */ + +#define IMX9_IRQ_NEXTINT (268) + +/* Total amount of entries in system vector table */ + +#define NR_IRQS (IMX9_IRQ_EXTINT + IMX9_IRQ_NEXTINT) + +#define ARMV8M_PERIPHERAL_INTERRUPTS (IMX9_IRQ_NEXTINT) + +#endif /* __ARCH_ARM_INCLUDE_IMX9_IMX93_IRQ_H */ diff --git a/arch/arm/include/imx9/irq.h b/arch/arm/include/imx9/irq.h index 2af7d08ff72..5128bf8cbf3 100644 --- a/arch/arm/include/imx9/irq.h +++ b/arch/arm/include/imx9/irq.h @@ -36,6 +36,8 @@ #if defined(CONFIG_ARCH_CHIP_IMX95_M7) # include +#elif defined(CONFIG_ARCH_CHIP_IMX93_M33) +# include #else # error "Unrecognized i.MX9 architecture" #endif diff --git a/arch/arm/src/imx9/CMakeLists.txt b/arch/arm/src/imx9/CMakeLists.txt index 46a399cfce3..004d12a39e0 100644 --- a/arch/arm/src/imx9/CMakeLists.txt +++ b/arch/arm/src/imx9/CMakeLists.txt @@ -33,12 +33,18 @@ set(SRCS if(CONFIG_IMX9_SCMI) list(APPEND SRCS imx9_scmi.c) # NXP SDK SCMI interface for pinctrl and clocking +else() + list(APPEND SRCS imx9_ccm.c) endif() if(CONFIG_RPTUN) list(APPEND SRCS imx9_rsctable.c imx9_rptun.c) endif() +if(CONFIG_IMX9_XCACHE) + list(APPEND SRCS imx9_xcache.c) +endif() + if(CONFIG_IMX9_MU) list(APPEND SRCS imx9_mu.c) endif() diff --git a/arch/arm/src/imx9/Kconfig b/arch/arm/src/imx9/Kconfig index 124812d674d..5bd28873e8a 100644 --- a/arch/arm/src/imx9/Kconfig +++ b/arch/arm/src/imx9/Kconfig @@ -19,6 +19,13 @@ config ARCH_CHIP_IMX95_M7 select ARMV7M_HAVE_DTCM select IMX9_HAVE_MU +config ARCH_CHIP_IMX93_M33 + bool "i.MX93 Cortex-M33 Processor" + select ARCH_CORTEXM33 + select ARMV8M_HAVE_ITCM + select ARMV8M_HAVE_DTCM + select IMX9_HAVE_MU + endchoice # i.MX9 Core Selection config IMX9_HAVE_MU @@ -30,6 +37,24 @@ config IMX9_SCMI default y depends on IMX9_MU5 +config IMX9_XCACHE + bool + default n + +config IMX9_LPCAC_PC + bool "Low Power Cache - Program Cache (ICACHE)" + default n + depends on ARCH_CHIP_IMX93_M33 + select ARCH_ICACHE + select IMX9_XCACHE + +config IMX9_LPCAC_PS + bool "Low Power Cache - Peripheral System (DCACHE)" + default n + depends on ARCH_CHIP_IMX93_M33 + select ARCH_DCACHE + select IMX9_XCACHE + if IMX9_SCMI config IMX9_CLK_OVER_SCMI @@ -996,6 +1021,20 @@ menuconfig IMX9_MU if IMX9_MU +config IMX9_MU1 + bool "MU1 M33 <-> A55" + default y + depends on ARCH_CHIP_IMX93_M33 + ---help--- + Enable mailbox 1 that operates between M33 and A55 cores + +config IMX9_MU2 + bool "MU2 M33 <-> A55" + default n + depends on ARCH_CHIP_IMX93_M33 + ---help--- + Enable mailbox 2 that operates between M33 and A55 cores + config IMX9_MU5 bool "MU5 M7 <-> M33" default y diff --git a/arch/arm/src/imx9/Make.defs b/arch/arm/src/imx9/Make.defs index f1d9e369feb..ecc93aa9562 100644 --- a/arch/arm/src/imx9/Make.defs +++ b/arch/arm/src/imx9/Make.defs @@ -21,7 +21,11 @@ # ############################################################################ -include armv7-m/Make.defs +ifeq ($(CONFIG_ARCH_ARMV7M),y) + include armv7-m/Make.defs +else ifeq ($(CONFIG_ARCH_ARMV8M),y) + include armv8-m/Make.defs +endif # i.MX9-specific C source files @@ -30,6 +34,12 @@ CHIP_CSRCS = imx9_allocateheap.c imx9_start.c imx9_clockconfig.c imx9_gpio.c imx ifeq ($(CONFIG_IMX9_SCMI),y) CHIP_CSRCS += imx9_scmi.c # NXP SDK SCMI interface for pinctrl and clocking +else + CHIP_CSRCS += imx9_ccm.c +endif + +ifeq ($(CONFIG_IMX9_XCACHE),y) + CHIP_CSRCS += imx9_xcache.c endif ifeq ($(CONFIG_RPTUN),y) diff --git a/arch/arm/src/imx9/hardware/imx93/imx93_ccm.h b/arch/arm/src/imx9/hardware/imx93/imx93_ccm.h new file mode 100644 index 00000000000..1401039316d --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx93/imx93_ccm.h @@ -0,0 +1,751 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx93/imx93_ccm.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_CCM_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_CCM_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define IMX9_CCM_CR_CTRL_OFFSET(n) (0x0000 + ((n) << 7)) /* Clock root control (CLOCK_ROOTn_CONTROL, n=0..94) */ +#define IMX9_CCM_CR_CTRL_SET_OFFSET(n) (0x0004 + ((n) << 7)) /* Clock root control (CLOCK_ROOTn_CONTROL_SET, n=0..94) */ +#define IMX9_CCM_CR_CTRL_CLR_OFFSET(n) (0x0008 + ((n) << 7)) /* Clock root control (CLOCK_ROOTn_CONTROL_CLR, n=0..94) */ +#define IMX9_CCM_CR_CTRL_TOG_OFFSET(n) (0x000c + ((n) << 7)) /* Clock root control (CLOCK_ROOTn_CONTROL_TOG, n=0..94) */ +#define IMX9_CCM_CR_STAT0_OFFSET(n) (0x0020 + ((n) << 7)) /* Clock root working status (CLOCK_ROOTn_STATUS0, n=0..94) */ +#define IMX9_CCM_CR_AUTH_OFFSET(n) (0x0030 + ((n) << 7)) /* Clock root access control (CLOCK_ROOTn_AUTHEN, n=0..94) */ +#define IMX9_CCM_CR_AUTH_SET_OFFSET(n) (0x0034 + ((n) << 7)) /* Clock root access control (CLOCK_ROOTn_AUTHEN_SET, n=0..94) */ +#define IMX9_CCM_CR_AUTH_CLR_OFFSET(n) (0x0038 + ((n) << 7)) /* Clock root access control (CLOCK_ROOTn_AUTHEN_CLR, n=0..94) */ +#define IMX9_CCM_CR_AUTH_TOG_OFFSET(n) (0x003c + ((n) << 7)) /* Clock root access control (CLOCK_ROOTn_AUTHEN_TOG, n=0..94) */ + +#define IMX9_CCM_GPR_SH_OFFSET(n) (0x4800 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn, n=0..7) */ +#define IMX9_CCM_GPR_SH_SET_OFFSET(n) (0x4804 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_SET, n=0..7) */ +#define IMX9_CCM_GPR_SH_CLR_OFFSET(n) (0x4808 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_CLR, n=0..7) */ +#define IMX9_CCM_GPR_SH_TOG_OFFSET(n) (0x480c + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_TOG, n=0..7) */ +#define IMX9_CCM_GPR_SH_AUTH_OFFSET(n) (0x4810 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_AUTHEN, n=0..7) */ +#define IMX9_CCM_GPR_SH_AUTH_SET_OFFSET(n) (0x4814 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_AUTHEN_SET, n=0..7) */ +#define IMX9_CCM_GPR_SH_AUTH_CLR_OFFSET(n) (0x4818 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_AUTHEN_CLR, n=0..7) */ +#define IMX9_CCM_GPR_SH_AUTH_TOG_OFFSET(n) (0x481c + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_AUTHEN_TOG, n=0..7) */ + +#define IMX9_CCM_GPR_PR_OFFSET(n) (0x4c00 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn, n=1..7) */ +#define IMX9_CCM_GPR_PR_SET_OFFSET(n) (0x4c04 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_SET, n=1..7) */ +#define IMX9_CCM_GPR_PR_CLR_OFFSET(n) (0x4c08 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_CLR, n=1..7) */ +#define IMX9_CCM_GPR_PR_TOG_OFFSET(n) (0x4c0c + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_TOG, n=1..7) */ +#define IMX9_CCM_GPR_PR_AUTH_OFFSET(n) (0x4c10 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_AUTHEN, n=1..7) */ +#define IMX9_CCM_GPR_PR_AUTH_SET_OFFSET(n) (0x4c14 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_AUTHEN_SET, n=1..7) */ +#define IMX9_CCM_GPR_PR_AUTH_CLR_OFFSET(n) (0x4c18 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_AUTHEN_CLR, n=1..7) */ +#define IMX9_CCM_GPR_PR_AUTH_TOG_OFFSET(n) (0x4c1c + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_AUTHEN_TOG, n=1..7) */ + +#define IMX9_CCM_OSCPLL_DIR_OFFSET(n) (0x5000 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */ +#define IMX9_CCM_OSCPLL_LPM_STAT0_OFFSET(n) (0x5004 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */ +#define IMX9_CCM_OSCPLL_LPM_STAT1_OFFSET(n) (0x5008 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */ +#define IMX9_CCM_OSCPLL_LPM0_OFFSET(n) (0x5010 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */ +#define IMX9_CCM_OSCPLL_LPM1_OFFSET(n) (0x5014 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */ +#define IMX9_CCM_OSCPLL_LPM_CUR_OFFSET(n) (0x501C + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */ +#define IMX9_CCM_OSCPLL_STAT0_OFFSET(n) (0x5020 + ((n) << 6)) /* Clock source working status (OSCPLLn_STATUS0, n=0..18) */ +#define IMX9_CCM_OSCPLL_STAT1_OFFSET(n) (0x5024 + ((n) << 6)) /* Clock source low power status (OSCPLLn_STATUS1, n=0..18) */ +#define IMX9_CCM_OSCPLL_AUTH_OFFSET(n) (0x5030 + ((n) << 6)) /* Clock source access control (OSCPLLn_AUTHEN, n=0..18) */ + +#define IMX9_CCM_LPCG_DIR_OFFSET(n) (0x8000 + ((n) << 6)) /* LPCG direct control (LPCGn_DIRECT, n=0..126) */ +#define IMX9_CCM_LPCG_LPM_STAT0_OFFSET(n) (0x8004 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */ +#define IMX9_CCM_LPCG_LPM_STAT1_OFFSET(n) (0x8008 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */ +#define IMX9_CCM_LPCG_LPM0_OFFSET(n) (0x8010 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */ +#define IMX9_CCM_LPCG_LPM1_OFFSET(n) (0x8014 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */ +#define IMX9_CCM_LPCG_LPM_CUR_OFFSET(n) (0x801C + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */ +#define IMX9_CCM_LPCG_STAT0_OFFSET(n) (0x8020 + ((n) << 6)) /* LPCG working status (LPCGn_STATUS0, n=0..126) */ +#define IMX9_CCM_LPCG_STAT1_OFFSET(n) (0x8024 + ((n) << 6)) /* LPCG low power status (LPCGn_STATUS1, n=0..126) */ +#define IMX9_CCM_LPCG_AUTH_OFFSET(n) (0x8030 + ((n) << 6)) /* LPCG access control (LPCGn_AUTHEN, n=0..126) */ + +/* Register addresses *******************************************************/ + +#define IMX9_CCM_CR_CTRL(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_CTRL_OFFSET(n)) +#define IMX9_CCM_CR_CTRL_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_CTRL_SET_OFFSET(n)) +#define IMX9_CCM_CR_CTRL_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_CTRL_CLR_OFFSET(n)) +#define IMX9_CCM_CR_CTRL_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_CTRL_TOG_OFFSET(n)) +#define IMX9_CCM_CR_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_STAT0_OFFSET(n)) +#define IMX9_CCM_CR_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_AUTH_OFFSET(n)) +#define IMX9_CCM_CR_AUTH_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_AUTH_SET_OFFSET(n)) +#define IMX9_CCM_CR_AUTH_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_AUTH_CLR_OFFSET(n)) +#define IMX9_CCM_CR_AUTH_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_AUTH_TOG_OFFSET(n)) + +#define IMX9_CCM_GPR_SH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_OFFSET(n)) +#define IMX9_CCM_GPR_SH_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_SET_OFFSET(n)) +#define IMX9_CCM_GPR_SH_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_CLR_OFFSET(n)) +#define IMX9_CCM_GPR_SH_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_TOG_OFFSET(n)) +#define IMX9_CCM_GPR_SH_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_AUTH_OFFSET(n)) +#define IMX9_CCM_GPR_SH_AUTH_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_AUTH_SET_OFFSET(n)) +#define IMX9_CCM_GPR_SH_AUTH_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_AUTH_CLR_OFFSET(n)) +#define IMX9_CCM_GPR_SH_AUTH_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_AUTH_TOG_OFFSET(n)) + +#define IMX9_CCM_GPR_PR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_OFFSET(n)) +#define IMX9_CCM_GPR_PR_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_SET_OFFSET(n)) +#define IMX9_CCM_GPR_PR_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_CLR_OFFSET(n)) +#define IMX9_CCM_GPR_PR_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_TOG_OFFSET(n)) +#define IMX9_CCM_GPR_PR_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_AUTH_OFFSET(n)) +#define IMX9_CCM_GPR_PR_AUTH_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_AUTH_SET_OFFSET(n)) +#define IMX9_CCM_GPR_PR_AUTH_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_AUTH_CLR_OFFSET(n)) +#define IMX9_CCM_GPR_PR_AUTH_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_AUTH_TOG_OFFSET(n)) + +#define IMX9_CCM_OSCPLL_DIR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_DIR_OFFSET(n)) +#define IMX9_CCM_OSCPLL_LPM_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM_STAT0_OFFSET(n)) +#define IMX9_CCM_OSCPLL_LPM_STAT1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM_STAT1_OFFSET(n)) +#define IMX9_CCM_OSCPLL_LPM0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM0_OFFSET(n)) +#define IMX9_CCM_OSCPLL_LPM1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM1_OFFSET(n)) +#define IMX9_CCM_OSCPLL_LPM_CUR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM1_OFFSET(n)) +#define IMX9_CCM_OSCPLL_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_STAT0_OFFSET(n)) +#define IMX9_CCM_OSCPLL_STAT1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_STAT1_OFFSET(n)) +#define IMX9_CCM_OSCPLL_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_AUTH_OFFSET(n)) + +#define IMX9_CCM_LPCG_DIR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_DIR_OFFSET(n)) +#define IMX9_CCM_LPCG_LPM_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM_STAT0_OFFSET(n)) +#define IMX9_CCM_LPCG_LPM_STAT1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM_STAT1_OFFSET(n)) +#define IMX9_CCM_LPCG_LPM0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM0_OFFSET(n)) +#define IMX9_CCM_LPCG_LPM1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM1_OFFSET(n)) +#define IMX9_CCM_LPCG_LPM_CUR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM1_OFFSET(n)) +#define IMX9_CCM_LPCG_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_STAT0_OFFSET(n)) +#define IMX9_CCM_LPCG_STAT1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_STAT1_OFFSET(n)) +#define IMX9_CCM_LPCG_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_AUTH_OFFSET(n)) + +/* Register bit definitions *************************************************/ + +/* Clock root control (CLOCK_ROOTn_CONTROL, n=0..94) */ + +#define CCM_CR_CTRL_DIV_SHIFT (0) /* Bits 0-7: Divide selected clock by DIV+1 (DIV) */ +#define CCM_CR_CTRL_DIV_MASK (0xff << CCM_CR_CTRL_DIV_SHIFT) +# define CCM_CR_CTRL_DIV(n) (((n)-1) << CCM_CR_CTRL_DIV_SHIFT) /* Divide selected clock by n */ + +#define CCM_CR_CTRL_MUX_SHIFT (8) /* Bits 8-9: Select clock from 8 clock sources (MUX) */ +#define CCM_CR_CTRL_MUX_MASK (0x03 << CCM_CR_CTRL_MUX_SHIFT) +# define CCM_CR_CTRL_MUX_SRCSEL(n) ((n) << CCM_CR_CTRL_MUX_SHIFT) /* Select clock source n */ + + /* Bits 11-23: Reserved */ +#define CCM_CR_CTRL_OFF (1 << 24) /* Bit 24: Shutdown clock root (OFF) */ + /* Bits 25-31: Reserved */ + +/* Clock root working status (CLOCK_ROOTn_STATUS0, n=0..94) */ + +#define CCM_CR_STAT0_DIV_SHIFT (0) /* Bits 0-7: Current clock root DIV setting (DIV) */ +#define CCM_CR_STAT0_DIV_MASK (0xff << CCM_CR_STAT0_DIV_SHIFT) +#define CCM_CR_STAT0_MUX_SHIFT (8) /* Bits 8-9: Current clock root MUX setting (MUX) */ +#define CCM_CR_STAT0_MUX_MASK (0x03 << CCM_CR_STAT0_MUX_SHIFT) + /* Bits 11-23: Reserved */ +#define CCM_CR_STAT0_OFF (1 << 24) /* Bit 24: Current clock root OFF setting (OFF) */ + /* Bits 25-27: Reserved */ +#define CCM_CR_STAT0_SLICE_BUSY (1 << 28) /* Bit 28: Clock generation logic is applying the new setting (SLICE_BUSY) */ +#define CCM_CR_STAT0_CHANGING (1 << 31) /* Bit 31: Clock generation logic is updating currently (CHANGING) */ + +/* Clock root access control (CLOCK_ROOTn_AUTHEN, n=0..94) */ + +#define CCM_CR_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock root can be changed in user mode (TZ_USER) */ +#define CCM_CR_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock root can be changed in non-secure mode (TZ_NS) */ + /* Bit 10: Reserved */ +#define CCM_CR_AUTH_LOCK_TZ (1 << 11) /* Bit 11: Lock TrustZone settings (LOCK_TZ) */ + /* Bits 12-14: Reserved */ +#define CCM_CR_AUTH_LOCK_LIST (1 << 12) /* Bit 15: Lock whitelist settings (LOCK_LIST) */ +#define CCM_CR_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */ +#define CCM_CR_AUTH_WHITE_LIST_MASK (0xffff << CCM_CR_AUTH_WHITE_LIST_SHIFT) + +/* General Purpose Register (GPR_SHAREDn, n=0..7) */ + +#define CCM_GPR_SH_GPR_SHIFT (0) /* Bits 0-31: General purpose register, shared for all CPU domains (GPR) */ +#define CCM_GPR_SH_GPR_MASK (0xffffffff << CCM_GPR_SH_GPR_SHIFT) +#define CCM_GPR_A55_CLK_SEL_SHIFT (0) +#define CCM_GPR_A55_CLK_SEL_MASK (0x01 << CCM_GPR_A55_CLK_SEL_SHIFT) +#define CCM_GPR_A55_CLK_SEL_CCM (0 << 0) +#define CCM_GPR_A55_CLK_SEL_PLL (1 << 0) + +/* General Purpose Register (GPR_SHAREDn_AUTHEN, n=0..7) */ + +#define CCM_GPR_SH_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock root can be changed in user mode (TZ_USER) */ +#define CCM_GPR_SH_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock root can be changed in non-secure mode (TZ_NS) */ + /* Bit 10: Reserved */ +#define CCM_GPR_SH_AUTH_LOCK_TZ (1 << 11) /* Bit 1: Lock TrustZone settings (LOCK_TZ) */ + /* Bits 12-14: Reserved */ +#define CCM_GPR_SH_AUTH_LOCK_LIST (1 << 12) /* Bit 15: Lock whitelist settings (LOCK_LIST) */ +#define CCM_GPR_SH_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */ +#define CCM_GPR_SH_AUTH_WHITE_LIST_MASK (0xffff << CCM_GPR_SH_AUTH_WHITE_LIST_SHIFT) + +/* General Purpose Register (GPR_PRIVATEn, n=1..7) */ + +#define CCM_GPR_PR_GPR_SHIFT (0) /* Bits 0-31: General purpose register, with dedicated bits for each domain (GPR) */ +#define CCM_GPR_PR_GPR_MASK (0xffffffff << CCM_GPR_PR_GPR_SHIFT) + +/* General Purpose Register (GPR_PRIVATEn_AUTHEN, n=1..7) */ + +#define CCM_GPR_PR_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock root can be changed in user mode (TZ_USER) */ +#define CCM_GPR_PR_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock root can be changed in non-secure mode (TZ_NS) */ + /* Bit 10: Reserved */ +#define CCM_GPR_PR_AUTH_LOCK_TZ (1 << 11) /* Bit 1: Lock TrustZone settings (LOCK_TZ) */ + /* Bits 12-14: Reserved */ +#define CCM_GPR_PR_AUTH_LOCK_LIST (1 << 12) /* Bit 15: Lock whitelist settings (LOCK_LIST) */ +#define CCM_GPR_PR_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */ +#define CCM_GPR_PR_AUTH_WHITE_LIST_MASK (0xffff << CCM_CR_AUTH_WHITE_LIST_SHIFT) + +/* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */ + +#define CCM_OSCPLL_DIR_ON (1 << 0) /* Bit 0: Turn on clock source (ON) */ + /* Bits 1-31: Reserved */ + +/* Clock source LPM status (OSCPLLn_LPM_STATUS0/1, n=0..18) */ + +#define CCM_OSCPLL_LPM_STAT_CPU_MODE_SHIFT (0) /* Bits 0-1: Current mode of CPU */ +#define CCM_OSCPLL_LPM_STAT_CPU_MODE_MASK (0x03 << CCM_OSCPLL_LPM_STAT_CPU_MODE_SHIFT) +#define CCM_OSCPLL_LPM_STAT_CPU_TRANS_REQ_SHIFT (2) /* Bit 2: Domain request pending */ +#define CCM_OSCPLL_LPM_STAT_CPU_TRANS_REQ_MASK (0x01 << CCM_OSCPLL_LPM_STAT_CPU_TRANS_REQ_SHIFT) +# define CCM_OSCPLL_LPM_STAT_ON (0) /* CPU is in RUN mode */ +# define CCM_OSCPLL_LPM_STAT_WAIT (1) /* CPU is in WAIT mode */ +# define CCM_OSCPLL_LPM_STAT_STOP (2) /* CPU is in STOP mode */ +# define CCM_OSCPLL_LPM_STAT_SUSPED (3) /* CPU is in SUSPEND mode */ + +/* CPU domain[n] from OSCPLLn_LPM_STATUS0/1 */ + +#define CCM_OSCPLL_LPM_STAT_CPU_DOMAIN_SHIFT (4) +#define CCM_OSCPLL_LPM_STAT_CPU_DOMAIN(n) ((n) * CCM_OSCPLL_LPM_STAT_CPU_DOMAIN_SHIFT) +#define CCM_OSCPLL_LPM_STAT_CPU_MODE_GET(n, v) (((v) >> CCM_OSCPLL_LPM_STAT_CPU_DOMAIN(n)) & CCM_OSCPLL_LPM_STAT_CPU_MODE_MASK) + +/* Clock source LPM mode (OSCPLLn_LPM_0/1 and _CUR, n=0..18) */ + +#define CCM_OSCPLL_LPM_MODE_SHIFT (0) /* Bits 0-2: Current mode of CPU */ +#define CCM_OSCPLL_LPM_MODE_MASK (0x07 << CCM_OSCPLL_LPM_MODE_SHIFT) +# define CCM_OSCPLL_LPM_MODE_OFF (0) /* Clock is off during all modes */ +# define CCM_OSCPLL_LPM_MODE_RUN (1) /* Clock is on in run mode, but off in WAIT and STOP modes */ +# define CCM_OSCPLL_LPM_MODE_RUNWAIT (2) /* Clock is on in run and wait modes, but off in STOP modes */ +# define CCM_OSCPLL_LPM_MODE_RUNWAITSTOP (3) /* Clock is on during all modes, except SUSPEND mode */ +# define CCM_OSCPLL_LPM_MODE_ALL (4) /* Clock is on during all modes */ + +/* CPU domain[n] from OSCPLLn_LPM_0/1 */ + +#define CCM_OSCPLL_LPM_MODE_CPU_DOMAIN_SHIFT (4) +#define CCM_OSCPLL_LPM_MODE_CPU_DOMAIN(n) ((n) * CCM_OSCPLL_LPM_MODE_CPU_DOMAIN_SHIFT) +#define CCM_OSCPLL_LPM_MODE_CPU_MODE_SET(n, v) ((v) & CCM_OSCPLL_LPM_MODE_MASK << CCM_LPCG_LPM_MODE_CPU_DOMAIN(n)) +#define CCM_OSCPLL_LPM_MODE_CPU_MODE_GET(n, v) (((v) >> CCM_LPCG_LPM_STAT_CPU_DOMAIN(n)) & CCM_OSCPLL_LPM_MODE_MASK) + +/* Clock source working status (OSCPLLn_STATUS0, n=0..18) */ + +#define CCM_OSCPLL_STAT0_ON (1 << 0) /* Bit 0: Clock source is turned on (ON) */ + /* Bits 1-3: Reserved */ +#define CCM_OSCPLL_STAT0_STATUS_EARLY (1 << 4) /* Bit 4: Clock source is active (STATUS_EARLY) */ +#define CCM_OSCPLL_STAT0_STATUS_LATE (1 << 5) /* Bit 5: Clock source is ready to use (STATUS_LATE) */ + /* Bits 6-11: Reserved */ +#define CCM_OSCPLL_STAT0_IN_USE (1 << 12) /* Bit 28: Indicates whether the clock source is being used by active clock roots (IN_USE) */ + /* Bits 16-31: Reserved */ + +/* Clock source low power status (OSCPLLn_STATUS1, n=0..18) */ + +#define CCM_OSCPLL_STAT1_DOM_ACTIVE_SHIFT (0) /* Bits 0-15: Domain active */ +#define CCM_OSCPLL_STAT1_DOM_ACTIVE_MASK (0xffff << CCM_OSCPLL_STAT1_DOM_ACTIVE_SHIFT) +#define CCM_OSCPLL_STAT1_DOM_ENABLE_SHIFT (16) /* Bits 16-32: Domain enabled */ +#define CCM_OSCPLL_STAT1_DOM_ENABLE_MASK (0xffff << CCM_OSCPLL_STAT1_DOM_ENABLE_SHIFT) + +/* Clock source access control (OSCPLLn_AUTHEN, n=0..18) */ + +#define CCM_OSCPLL_AUTH_CPULPM (1 << 2) /* Bit 2: CPU Low Power Mode (CPULPM) */ +#define CCM_OSCPLL_AUTH_AUTO_CTRL (1 << 3) /* Bit 2: Auto mode (AUTO_CTRL) */ +#define CCM_OSCPLL_AUTH_LOCK_MODE (1 << 7) /* Bit 7: Lock low power and access mode (LOCK_MODE) */ +#define CCM_OSCPLL_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock source can be changed in user mode (TZ_USER) */ +#define CCM_OSCPLL_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock source can be changed in non-secure mode (TZ_NS) */ + /* Bit 10: Reserved */ +#define CCM_OSCPLL_AUTH_LOCK_TZ (1 << 11) /* Bit 11: Lock TrustZone settings (LOCK_TZ) */ + /* Bits 12-14: Reserved */ +#define CCM_OSCPLL_AUTH_LOCK_LIST (1 << 15) /* Bit 15: Lock whitelist settings (LOCK_LIST) */ +#define CCM_OSCPLL_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */ +#define CCM_OSCPLL_AUTH_WHITE_LIST_MASK (0xffff << CCM_OSCPLL_AUTH_WHITE_LIST_SHIFT) + +/* LPCG direct control (LPCGn_DIRECT, n=0..126) */ + +#define CCM_LPCG_DIR_ON (1 << 0) /* Bit 0: LPCG on (ON) */ + /* Bit 1: Reserved */ +#define CCM_LPCG_ACK_TIMEOUT_EN (1 << 2) /* Bit 2: Ack timeout enable */ + /* Bits 3-31: Reserved */ + +/* Clock source LPM status (LPCGn_LPM_STATUS0/1, n=0..18) */ + +#define CCM_LPCG_LPM_STAT_CPU_MODE_SHIFT (0) /* Bits 0-1: Current mode of CPU */ +#define CCM_LPCG_LPM_STAT_CPU_MODE_MASK (0x03 << CCM_LPCG_LPM_STAT_CPU_MODE_SHIFT) +#define CCM_LPCG_LPM_STAT_CPU_TRANS_REQ_SHIFT (2) /* Bit 2: Domain request pending */ +#define CCM_LPCG_LPM_STAT_CPU_TRANS_REQ_MASK (0x01 << CCM_LPCG_LPM_STAT_CPU_TRANS_REQ_SHIFT) +# define CCM_LPCG_LPM_STAT_ON (0) /* CPU is in RUN mode */ +# define CCM_LPCG_LPM_STAT_WAIT (1) /* CPU is in WAIT mode */ +# define CCM_LPCG_LPM_STAT_STOP (2) /* CPU is in STOP mode */ +# define CCM_LPCG_LPM_STAT_SUSPED (3) /* CPU is in SUSPEND mode */ + +/* CPU domain[n] from OSCPLLn_LPM_STATUS0/1 */ + +#define CCM_LPCG_LPM_STAT_CPU_DOMAIN_SHIFT (4) +#define CCM_LPCG_LPM_STAT_CPU_DOMAIN(n) ((n) * CCM_LPCG_LPM_STAT_CPU_DOMAIN_SHIFT) +#define CCM_LPCG_LPM_STAT_CPU_MODE_GET(n, v) (((v) >> CCM_LPCG_LPM_STAT_CPU_DOMAIN(n)) & CCM_LPCG_LPM_STAT_CPU_MODE_MASK) + +/* Clock source LPM mode (LPCGn_LPM_0/1 and _CUR, n=0..18) */ + +#define CCM_LPCG_LPM_MODE_SHIFT (0) /* Bits 0-2: Current mode of CPU */ +#define CCM_LPCG_LPM_MODE_MASK (0x07 << CCM_LPCG_LPM_MODE_SHIFT) +# define CCM_LPCG_LPM_MODE_OFF (0) /* Clock is off during all modes */ +# define CCM_LPCG_LPM_MODE_RUN (1) /* Clock is on in run mode, but off in WAIT and STOP modes */ +# define CCM_LPCG_LPM_MODE_RUNWAIT (2) /* Clock is on in run and wait modes, but off in STOP modes */ +# define CCM_LPCG_LPM_MODE_RUNWAITSTOP (3) /* Clock is on during all modes, except SUSPEND mode */ +# define CCM_LPCG_LPM_MODE_ALL (4) /* Clock is on during all modes */ + +/* CPU domain[n] from LPCGn_LPM_0/1 */ + +#define CCM_LPCG_LPM_MODE_CPU_DOMAIN_SHIFT (4) +#define CCM_LPCG_LPM_MODE_CPU_DOMAIN(n) ((n) * CCM_LPCG_LPM_MODE_CPU_DOMAIN_SHIFT) +#define CCM_LPCG_LPM_MODE_CPU_MODE_SET(n, v) ((v) & CCM_LPCG_LPM_MODE_MASK << CCM_LPCG_LPM_MODE_CPU_DOMAIN(n)) +#define CCM_LPCG_LPM_MODE_CPU_MODE_GET(n, v) (((v) >> CCM_LPCG_LPM_MODE_CPU_DOMAIN(n)) & CCM_LPCG_LPM_MODE_MASK) + +/* LPCG working status (LPCGn_STATUS0, n=0..126) */ + +#define CCM_LPCG_STAT0_ON (1 << 0) /* Bit 0: Clock source is turned on (ON) */ + /* Bits 1-31 Reserved */ + +/* LPCG low power status (LPCGn_STATUS1, n=0..126) */ + +#define CCM_LPCG_STAT0_ACTIVE_DOMAIN_SHIFT (8) /* Bits 8-11: Domains that own this clock source according to whitelist (ACTIVE_DOMAIN) */ +#define CCM_LPCG_STAT0_ACTIVE_DOMAIN_MASK (0x0f << CCM_LPCG_STAT0_ACTIVE_DOMAIN_SHIFT) +#define CCM_LPCG_STAT0_DOMAIN_ENABLE_SHIFT (8) /* Bits 12-15: Enable status from each domain (DOMAIN_ENABLE) */ +#define CCM_LPCG_STAT0_DOMAIN_ENABLE_MASK (0x0f << CCM_LPCG_STAT0_DOMAIN_ENABLE_SHIFT) + /* Bits 16-31: Reserved */ + +/* LPCG access control (LPCGn_AUTHEN, n=0..126) */ + +#define CCM_LPCG_AUTH_CPULPM (1 << 2) /* Bit 2: CPU Low Power Mode (CPULPM) */ +#define CCM_LPCG_AUTH_LOCK_MODE (1 << 7) /* Bit 7: Lock low power and access mode (LOCK_MODE) */ +#define CCM_LPCG_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock source can be changed in user mode (TZ_USER) */ +#define CCM_LPCG_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock source can be changed in non-secure mode (TZ_NS) */ + /* Bit 10: Reserved */ +#define CCM_LPCG_AUTH_LOCK_TZ (1 << 11) /* Bit 11: Lock TrustZone settings (LOCK_TZ) */ + /* Bits 12-14: Reserved */ +#define CCM_LPCG_AUTH_LOCK_LIST (1 << 15) /* Bit 15: Lock whitelist settings (LOCK_LIST) */ +#define CCM_LPCG_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */ +#define CCM_LPCG_AUTH_WHITE_LIST_MASK (0xffff << CCM_LPCG_AUTH_WHITE_LIST_SHIFT) + +/* Auth access bits */ + +#define CCM_AUTH_TZ_USER(n) ((n) << 8) +#define CCM_AUTH_TZ_NS(n) ((n) << 9) +#define CCM_AUTH_LOCK_TZ(n) ((n) << 11) + +/* Clock roots */ + +#define ROOT_CLOCK_OFFSET 0 + +#define CCM_CR_A55PERIPH 0 /* CLOCK Root Arm A55 Periph. */ +#define CCM_CR_A55MTRBUS 1 /* CLOCK Root Arm A55 MTR BUS. */ +#define CCM_CR_A55 2 /* CLOCK Root Arm A55. */ +#define CCM_CR_M33 3 /* CLOCK Root M33. */ +#define CCM_CR_SENTINEL 4 /* CLOCK Root Sentinel. */ +#define CCM_CR_BUSWAKEUP 5 /* CLOCK Root Bus Wakeup. */ +#define CCM_CR_BUSAON 6 /* CLOCK Root Bus Aon. */ +#define CCM_CR_WAKEUPAXI 7 /* CLOCK Root Wakeup Axi. */ +#define CCM_CR_SWOTRACE 8 /* CLOCK Root Swo Trace. */ +#define CCM_CR_M33SYSTICK 9 /* CLOCK Root M33 Systick. */ +#define CCM_CR_FLEXIO1 10 /* CLOCK Root Flexio1. */ +#define CCM_CR_FLEXIO2 11 /* CLOCK Root Flexio2. */ +#define CCM_CR_LPIT1 12 /* CLOCK Root Lpit1. */ +#define CCM_CR_LPIT2 13 /* CLOCK Root Lpit2. */ +#define CCM_CR_LPTMR1 14 /* CLOCK Root Lptmr1. */ +#define CCM_CR_LPTMR2 15 /* CLOCK Root Lptmr2. */ +#define CCM_CR_TPM1 16 /* CLOCK Root Tpm1. */ +#define CCM_CR_TPM2 17 /* CLOCK Root Tpm2. */ +#define CCM_CR_TPM3 18 /* CLOCK Root Tpm3. */ +#define CCM_CR_TPM4 19 /* CLOCK Root Tpm4. */ +#define CCM_CR_TPM5 20 /* CLOCK Root Tpm5. */ +#define CCM_CR_TPM6 21 /* CLOCK Root Tpm6. */ +#define CCM_CR_FLEXSPI1 22 /* CLOCK Root Flexspi1. */ +#define CCM_CR_CAN1 23 /* CLOCK Root Can1. */ +#define CCM_CR_CAN2 24 /* CLOCK Root Can2. */ +#define CCM_CR_LPUART1 25 /* CLOCK Root Lpuart1. */ +#define CCM_CR_LPUART2 26 /* CLOCK Root Lpuart2. */ +#define CCM_CR_LPUART3 27 /* CLOCK Root Lpuart3. */ +#define CCM_CR_LPUART4 28 /* CLOCK Root Lpuart4. */ +#define CCM_CR_LPUART5 29 /* CLOCK Root Lpuart5. */ +#define CCM_CR_LPUART6 30 /* CLOCK Root Lpuart6. */ +#define CCM_CR_LPUART7 31 /* CLOCK Root Lpuart7. */ +#define CCM_CR_LPUART8 32 /* CLOCK Root Lpuart8. */ +#define CCM_CR_LPI2C1 33 /* CLOCK Root Lpi2c1. */ +#define CCM_CR_LPI2C2 34 /* CLOCK Root Lpi2c2. */ +#define CCM_CR_LPI2C3 35 /* CLOCK Root Lpi2c3. */ +#define CCM_CR_LPI2C4 36 /* CLOCK Root Lpi2c4. */ +#define CCM_CR_LPI2C5 37 /* CLOCK Root Lpi2c5. */ +#define CCM_CR_LPI2C6 38 /* CLOCK Root Lpi2c6. */ +#define CCM_CR_LPI2C7 39 /* CLOCK Root Lpi2c7. */ +#define CCM_CR_LPI2C8 40 /* CLOCK Root Lpi2c8. */ +#define CCM_CR_LPSPI1 41 /* CLOCK Root Lpspi1. */ +#define CCM_CR_LPSPI2 42 /* CLOCK Root Lpspi2. */ +#define CCM_CR_LPSPI3 43 /* CLOCK Root Lpspi3. */ +#define CCM_CR_LPSPI4 44 /* CLOCK Root Lpspi4. */ +#define CCM_CR_LPSPI5 45 /* CLOCK Root Lpspi5. */ +#define CCM_CR_LPSPI6 46 /* CLOCK Root Lpspi6. */ +#define CCM_CR_LPSPI7 47 /* CLOCK Root Lpspi7. */ +#define CCM_CR_LPSPI8 48 /* CLOCK Root Lpspi8. */ +#define CCM_CR_I3C1 49 /* CLOCK Root I3c1. */ +#define CCM_CR_I3C2 50 /* CLOCK Root I3c2. */ +#define CCM_CR_USDHC1 51 /* CLOCK Root Usdhc1. */ +#define CCM_CR_USDHC2 52 /* CLOCK Root Usdhc2. */ +#define CCM_CR_USDHC3 53 /* CLOCK Root Usdhc3. */ +#define CCM_CR_SAI1 54 /* CLOCK Root Sai1. */ +#define CCM_CR_SAI2 55 /* CLOCK Root Sai2. */ +#define CCM_CR_SAI3 56 /* CLOCK Root Sai3. */ +#define CCM_CR_CCMCKO1 57 /* CLOCK Root Ccm Cko1. */ +#define CCM_CR_CCMCKO2 58 /* CLOCK Root Ccm Cko2. */ +#define CCM_CR_CCMCKO3 59 /* CLOCK Root Ccm Cko3. */ +#define CCM_CR_CCMCKO4 60 /* CLOCK Root Ccm Cko4. */ +#define CCM_CR_HSIO 61 /* CLOCK Root Hsio. */ +#define CCM_CR_HSIOUSBTEST60M 62 /* CLOCK Root Hsio Usb Test 60M. */ +#define CCM_CR_HSIOACSCAN80M 63 /* CLOCK Root Hsio Acscan 80M. */ +#define CCM_CR_HSIOACSCAN480M 64 /* CLOCK Root Hsio Acscan 480M. */ +#define CCM_CR_NIC 65 /* CLOCK Root Nic. */ +#define CCM_CR_NICAPB 66 /* CLOCK Root Nic Apb. */ +#define CCM_CR_MLAPB 67 /* CLOCK Root Ml Apb. */ +#define CCM_CR_ML 68 /* CLOCK Root Ml. */ +#define CCM_CR_MEDIAAXI 69 /* CLOCK Root Media Axi. */ +#define CCM_CR_MEDIAAPB 70 /* CLOCK Root Media Apb. */ +#define CCM_CR_MEDIALDB 71 /* CLOCK Root Media Ldb. */ +#define CCM_CR_MEDIADISPPIX 72 /* CLOCK Root Media Disp Pix. */ +#define CCM_CR_CAMPIX 73 /* CLOCK Root Cam Pix. */ +#define CCM_CR_MIPITESTBYTE 74 /* CLOCK Root Mipi Test Byte. */ +#define CCM_CR_MIPIPHYCFG 75 /* CLOCK Root Mipi Phy Cfg. */ +#define CCM_CR_DRAMALT 76 /* CLOCK Root Dram Alt. */ +#define CCM_CR_DRAMAPB 77 /* CLOCK Root Dram Apb. */ +#define CCM_CR_ADC 78 /* CLOCK Root Adc. */ +#define CCM_CR_PDM 79 /* CLOCK Root Pdm. */ +#define CCM_CR_TSTMR1 80 /* CLOCK Root Tstmr1. */ +#define CCM_CR_TSTMR2 81 /* CLOCK Root Tstmr2. */ +#define CCM_CR_MQS1 82 /* CLOCK Root MQS1. */ +#define CCM_CR_MQS2 83 /* CLOCK Root MQS2. */ +#define CCM_CR_AUDIOXCVR 84 /* CLOCK Root Audio XCVR. */ +#define CCM_CR_SPDIF 85 /* CLOCK Root Spdif. */ +#define CCM_CR_ENET 86 /* CLOCK Root Enet. */ +#define CCM_CR_ENETTIMER1 87 /* CLOCK Root Enet Timer1. */ +#define CCM_CR_ENETTIMER2 88 /* CLOCK Root Enet Timer2. */ +#define CCM_CR_ENETREF 89 /* CLOCK Root Enet Ref. */ +#define CCM_CR_ENETREFPHY 90 /* CLOCK Root Enet Ref Phy. */ +#define CCM_CR_I3C1SLOW 91 /* CLOCK Root I3c1Slow. */ +#define CCM_CR_I3C2SLOW 92 /* CLOCK Root I3c2Slow. */ +#define CCM_CR_USBPHYBURUNIN 93 /* CLOCK Root Usb Phy Burunin. */ +#define CCM_CR_PALCAMESCAN 94 /* CLOCK Root Pal Came Scan. */ + +/* Clock gates */ + +#define CCM_LPCG_A55 0 +#define CCM_LPCG_CM33 1 +#define CCM_LPCG_ARM_TROUT 2 +#define CCM_LPCG_SENTINEL 3 +#define CCM_LPCG_SIM_WAKEUP 4 +#define CCM_LPCG_SIM_AON 5 +#define CCM_LPCG_SIM_MEGA 6 +#define CCM_LPCG_ANADIG 7 +#define CCM_LPCG_SRC 8 +#define CCM_LPCG_CCM 9 +#define CCM_LPCG_GPC 10 +#define CCM_LPCG_ADC1 11 +#define CCM_LPCG_WDOG1 12 +#define CCM_LPCG_WDOG2 13 +#define CCM_LPCG_WDOG3 14 +#define CCM_LPCG_WDOG4 15 +#define CCM_LPCG_WDOG5 16 +#define CCM_LPCG_SEMA1 17 +#define CCM_LPCG_SEMA2 18 +#define CCM_LPCG_MU_A 19 +#define CCM_LPCG_MU_B 20 +#define CCM_LPCG_EDMA3 21 +#define CCM_LPCG_EDMA4 22 +#define CCM_LPCG_ROMCP_A55 23 +#define CCM_LPCG_ROMCP_M33 24 +#define CCM_LPCG_FLEXSPI1 25 +#define CCM_LPCG_AON_TRDC 26 +#define CCM_LPCG_WKUP_TRDC 27 +#define CCM_LPCG_OCOTP 28 +#define CCM_LPCG_BBSM_HP 29 +#define CCM_LPCG_BBSM 30 +#define CCM_LPCG_CSTRACE 31 +#define CCM_LPCG_CSSWO 32 +#define CCM_LPCG_IOMUXC 33 +#define CCM_LPCG_GPIO1 34 +#define CCM_LPCG_GPIO2 35 +#define CCM_LPCG_GPIO3 36 +#define CCM_LPCG_GPIO4 37 +#define CCM_LPCG_FLEXIO1 38 +#define CCM_LPCG_FLEXIO2 39 +#define CCM_LPCG_LPIT1 40 +#define CCM_LPCG_LPIT2 41 +#define CCM_LPCG_LPTMR1 42 +#define CCM_LPCG_LPTMR2 43 +#define CCM_LPCG_TPM1 44 +#define CCM_LPCG_TPM2 45 +#define CCM_LPCG_TPM3 46 +#define CCM_LPCG_TPM4 47 +#define CCM_LPCG_TPM5 48 +#define CCM_LPCG_TPM6 49 +#define CCM_LPCG_CAN1 50 +#define CCM_LPCG_CAN2 51 +#define CCM_LPCG_LPUART1 52 +#define CCM_LPCG_LPUART2 53 +#define CCM_LPCG_LPUART3 54 +#define CCM_LPCG_LPUART4 55 +#define CCM_LPCG_LPUART5 56 +#define CCM_LPCG_LPUART6 57 +#define CCM_LPCG_LPUART7 58 +#define CCM_LPCG_LPUART8 59 +#define CCM_LPCG_LPI2C1 60 +#define CCM_LPCG_LPI2C2 61 +#define CCM_LPCG_LPI2C3 62 +#define CCM_LPCG_LPI2C4 63 +#define CCM_LPCG_LPI2C5 64 +#define CCM_LPCG_LPI2C6 65 +#define CCM_LPCG_LPI2C7 66 +#define CCM_LPCG_LPI2C8 67 +#define CCM_LPCG_LPSPI1 68 +#define CCM_LPCG_LPSPI2 69 +#define CCM_LPCG_LPSPI3 70 +#define CCM_LPCG_LPSPI4 71 +#define CCM_LPCG_LPSPI5 72 +#define CCM_LPCG_LPSPI6 73 +#define CCM_LPCG_LPSPI7 74 +#define CCM_LPCG_LPSPI8 75 +#define CCM_LPCG_I3C1 76 +#define CCM_LPCG_I3C2 77 +#define CCM_LPCG_USDHC1 78 +#define CCM_LPCG_USDHC2 79 +#define CCM_LPCG_USDHC3 80 +#define CCM_LPCG_SAI1 81 +#define CCM_LPCG_SAI2 82 +#define CCM_LPCG_SAI3 83 +#define CCM_LPCG_SSI_W2AO 84 +#define CCM_LPCG_SSI_AO2W 85 +#define CCM_LPCG_MIPI_CSI 86 +#define CCM_LPCG_MIPI_DSI 87 +#define CCM_LPCG_LVDS 88 +#define CCM_LPCG_LCDIF 89 +#define CCM_LPCG_PXP 90 +#define CCM_LPCG_ISI 91 +#define CCM_LPCG_NIC_MEDIA 92 +#define CCM_LPCG_DDR_DFI 93 +#define CCM_LPCG_DDR_CTL 94 +#define CCM_LPCG_DDR_DFI_CTL 95 +#define CCM_LPCG_DDR_SSI 96 +#define CCM_LPCG_DDR_BYPASS 97 +#define CCM_LPCG_DDR_APB 98 +#define CCM_LPCG_DDR_DRAMPLL 99 +#define CCM_LPCG_DDR_CLK_CTL 100 +#define CCM_LPCG_NIC_CENTRAL 101 +#define CCM_LPCG_GIC600 102 +#define CCM_LPCG_NIC_APB 103 +#define CCM_LPCG_USB_CONTROLLER 104 +#define CCM_LPCG_USB_TEST_60M 105 +#define CCM_LPCG_HSIO_TROUT_24M 106 +#define CCM_LPCG_PDM 107 +#define CCM_LPCG_MQS1 108 +#define CCM_LPCG_MQS2 109 +#define CCM_LPCG_AUD_XCVR 110 +#define CCM_LPCG_NICMIX_MECC 111 +#define CCM_LPCG_SPDIF 112 +#define CCM_LPCG_SSI_ML2NIC 113 +#define CCM_LPCG_SSI_MED2NIC 114 +#define CCM_LPCG_SSI_HSIO2NIC 115 +#define CCM_LPCG_SSI_W2NIC 116 +#define CCM_LPCG_SSI_NIC2W 117 +#define CCM_LPCG_SSI_NIC2DDR 118 +#define CCM_LPCG_HSIO_32K 119 +#define CCM_LPCG_ENET1 120 +#define CCM_LPCG_ENET_QOS 121 +#define CCM_LPCG_SYS_CNT 122 +#define CCM_LPCG_TSTMR1 123 +#define CCM_LPCG_TSTMR2 124 +#define CCM_LPCG_TMC 125 +#define CCM_LPCG_PMRO 126 + +/* Shared register indices */ + +#define CCM_SHARED_EXT_CLK 0 +#define CCM_SHARED_A55_CLK 1 +#define CCM_SHARED_DRAM_CLK 2 +#define CCM_SHARED_GPR_COUNT 7 + +/* Other parameters */ + +#define ROOT_MUX_MAX 4 /* Count of root clock MUX options */ +#define CCM_CR_COUNT 94 /* Count of clock roots */ +#define CCM_LPCG_COUNT 126 /* Count of clock gates */ +#define CCM_OSCPLL_COUNT 18 /* Count of osc plls */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* NOTE: The PLL input (IN) clocks are not available in clock tree */ + +enum ccm_clock_name_e +{ + OSC_24M = 0, /* 24MHZ OSCILLATOR. */ + ARM_PLL = 1, /* ARM PLL */ + ARM_PLLOUT = 2, /* ARM PLL OUT */ + SYS_PLL1_IN = 3, /* SYSTEM PLL1 IN */ + SYS_PLL1PFD0_IN = 4, /* SYSTEM PLL1 PFD0 IN */ + SYS_PLL1PFD0 = 5, /* SYSTEM PLL1 PFD0 */ + SYS_PLL1PFD0DIV2 = 6, /* SYSTEM PLL1 PFD0 DIV2 */ + SYS_PLL1PFD1_IN = 7, /* SYSTEM PLL1 PFD1 IN */ + SYS_PLL1PFD1 = 8, /* SYSTEM PLL1 PFD1 */ + SYS_PLL1PFD1DIV2 = 9, /* SYSTEM PLL1 PFD1 DIV2 */ + SYS_PLL1PFD2_IN = 10, /* SYSTEM PLL1 PFD2 IN */ + SYS_PLL1PFD2 = 11, /* SYSTEM PLL1 PFD2 */ + SYS_PLL1PFD2DIV2 = 12, /* SYSTEM PLL1 PFD2 DIV2 */ + AUDIO_PLL1 = 13, /* AUDIO PLL1 */ + AUDIO_PLL1OUT = 14, /* AUDIO PLL1 OUT */ + DRAM_PLL = 15, /* DRAM PLL */ + DRAM_PLLOUT = 16, /* DRAM PLL OUT */ + VIDEO_PLL1 = 17, /* VIDEO PLL1 */ + VIDEO_PLL1OUT = 18, /* VIDEO PLL1 OUT */ + EXT = 19, /* EXT */ +}; + +/* This contains a simple LUT to find the corresponding MUX index per root */ + +static const int g_ccm_root_mux[][ROOT_MUX_MAX] = +{ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Arm A55 Periph */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Arm A55 MTR BUS */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Arm A55 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* M33 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Sentinel */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Bus Wakeup */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Bus Aon */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Wakeup Axi */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Swo Trace */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* M33 Systick */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Flexio1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Flexio2 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpit1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpit2 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lptmr1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lptmr2 */ + {OSC_24M, SYS_PLL1PFD0, AUDIO_PLL1OUT, EXT}, /* Tpm1 */ + {OSC_24M, SYS_PLL1PFD0, AUDIO_PLL1OUT, EXT}, /* Tpm2 */ + {OSC_24M, SYS_PLL1PFD0, AUDIO_PLL1OUT, EXT}, /* Tpm3 */ + {OSC_24M, SYS_PLL1PFD0, AUDIO_PLL1OUT, EXT}, /* Tpm4 */ + {OSC_24M, SYS_PLL1PFD0, AUDIO_PLL1OUT, EXT}, /* Tpm5 */ + {OSC_24M, SYS_PLL1PFD0, AUDIO_PLL1OUT, EXT}, /* Tpm6 */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Flexspi1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Can1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Can2 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpuart1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpuart2 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpuart3 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpuart4 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpuart5 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpuart6 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpuart7 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpuart8 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpi2c1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpi2c2 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpi2c3 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpi2c4 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpi2c5 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpi2c6 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpi2c7 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpi2c8 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpspi1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpspi2 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpspi3 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpspi4 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpspi5 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpspi6 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpspi7 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpspi8 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* I3c1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* I3c2 */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Usdhc1 */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Usdhc2 */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Usdhc3 */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, EXT}, /* Sai1 */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, EXT}, /* Sai2 */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, EXT}, /* Sai3 */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, AUDIO_PLL1OUT}, /* Ccm Cko1 */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, VIDEO_PLL1OUT}, /* Ccm Cko2 */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, AUDIO_PLL1OUT}, /* Ccm Cko3 */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, VIDEO_PLL1OUT}, /* Ccm Cko4 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Hsio */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Hsio Usb Test 60M */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Hsio Acscan 80M */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, SYS_PLL1PFD2}, /* Hsio Acscan 480M */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Nic */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Nic Apb */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Ml Apb */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Ml */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Media Axi */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Media Apb */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, SYS_PLL1PFD0}, /* Media Ldb */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, SYS_PLL1PFD0}, /* Media Disp Pix */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, SYS_PLL1PFD0}, /* Cam Pix */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, SYS_PLL1PFD0}, /* Mipi Test Byte */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, SYS_PLL1PFD0}, /* Mipi Phy Cfg */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Dram Alt */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, SYS_PLL1PFD2DIV2}, /* Dram Apb */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Adc */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, EXT}, /* Pdm */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Tstmr1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Tstmr2 */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, EXT}, /* Mqs1 */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, EXT}, /* Mqs2 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, SYS_PLL1PFD2DIV2}, /* Audio XCVR */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, EXT}, /* Spdif */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, SYS_PLL1PFD2DIV2}, /* Enet */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Enet Timer1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Enet Timer2 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, SYS_PLL1PFD2DIV2}, /* Enet Ref */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Enet Ref Phy */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* I3c1 Slow */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* I3c2 Slow */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Usb Phy Burunin */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, SYS_PLL1PFD2}, /* Pal Came Scan */ +}; + +#define CCM_ARM_A55_PERIPH_CLK_ROOT 0 +#define CCM_ARM_A55_MTR_BUS_CLK_ROOT 1 +#define CCM_ARM_A55_CLK_ROOT 2 +#define CCM_M33_CLK_ROOT 3 +#define CCM_ELE_CLK_ROOT 4 +#define CCM_BUS_WAKEUP_CLK_ROOT 5 +#define CCM_BUS_AON_CLK_ROOT 6 +#define CCM_WAKEUP_AXI_CLK_ROOT 7 +#define CCM_SWO_TRACE_CLK_ROOT 8 +#define CCM_M33_SYSTICK_CLK_ROOT 9 +#define CCM_NIC_CLK_ROOT 65 +#define CCM_NIC_APB_CLK_ROOT 66 +#define CCM_DRAM_ALT_CLK_ROOT 76 +#define CCM_DRAM_APB_CLK_ROOT 77 +#define CCM_ENET_TIMER_CLK_ROOT 87 +#define CCM_ENET_REF_CLK_ROOT 89 +#define CCM_CLK_ROOT_NUM 95 + +#define CCM_OSCPLL_END 19 +#define CCM_CCGR_NUM 127 + +#define CCM_SHARED_GPR_DRAM_CLK 2 +#define CCM_SHARED_GPR_DRAM_CLK_SEL_PLL 0 +#define CCM_SHARED_GPR_DRAM_CLK_SEL_CCM BIT(0) +#define CCM_SHARED_GPR_NUM 8 + +#define MHZ(x) ((x) * 1000000UL) + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_CCM_H */ diff --git a/arch/arm/src/imx9/hardware/imx93/imx93_clock.h b/arch/arm/src/imx9/hardware/imx93/imx93_clock.h new file mode 100644 index 00000000000..0066ffa4630 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx93/imx93_clock.h @@ -0,0 +1,549 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx93/imx93_clock.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2025 Maarten Zanders + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX93_CLOCK_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX93_CLOCK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "imx93_ccm.h" +#include "imx93_pll.h" + +#define XTAL_FREQ 24000000u + +typedef uint32_t clock_config_t; + +#define CLOCK_GATE_SHIFT (24) +#define CLOCK_GATE_MASK (0xff << CLOCK_GATE_SHIFT) +#define CLOCK_GATE(n) (((n) << CLOCK_GATE_SHIFT) & CLOCK_GATE_MASK) +#define GET_CLOCK_GATE(n) (((n) & CLOCK_GATE_MASK) >> CLOCK_GATE_SHIFT) + +#define CLOCK_DIV_SHIFT (16) +#define CLOCK_DIV_MASK (0xff << CLOCK_DIV_SHIFT) +#define CLOCK_DIV(n) (((n) << CLOCK_DIV_SHIFT) & CLOCK_DIV_MASK) +#define GET_CLOCK_DIV(n) (((n) & CLOCK_DIV_MASK) >> CLOCK_DIV_SHIFT) + +#define CLOCK_ROOT_SHIFT (8) +#define CLOCK_ROOT_MASK (0x7f << CLOCK_ROOT_SHIFT) +#define CLOCK_ROOT(n) (((n) << CLOCK_ROOT_SHIFT) & CLOCK_ROOT_MASK) +#define GET_CLOCK_ROOT(n) (((n) & CLOCK_ROOT_MASK) >> CLOCK_ROOT_SHIFT) + +#define CLOCK_SOURCE_ID_SHIFT (3) +#define CLOCK_SOURCE_ID_MASK (0x1f << CLOCK_SOURCE_ID_SHIFT) +#define CLOCK_SOURCE_ID(n) (((n) << CLOCK_SOURCE_ID_SHIFT) & CLOCK_SOURCE_ID_MASK) +#define GET_CLOCK_SOURCE_ID(n) (((n) & CLOCK_SOURCE_ID_MASK) >> CLOCK_SOURCE_ID_SHIFT) + +#define ROOT_MUX_SHIFT (0) +#define ROOT_MUX_MASK (0x07 << ROOT_MUX_SHIFT) +#define ROOT_MUX(n) (((n) << ROOT_MUX_SHIFT) & ROOT_MUX_MASK) +#define GET_ROOT_MUX(n) (((n) & ROOT_MUX_MASK) >> ROOT_MUX_SHIFT) + +#define CCM_LPCG_NONE 255 // Special case for clk roots which do not have a gate + +/* Peripheral root clock configurations, divide to be defined! */ +#define CLOCK_ROOT_CONFIG(gate, root, src, mux) \ + (CLOCK_GATE(gate) | CLOCK_ROOT(root) | CLOCK_SOURCE_ID(src) | ROOT_MUX(mux)) + +#define A55PERIPH_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_A55PERIPH, OSC_24M, 0) +#define A55PERIPH_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_A55PERIPH, SYS_PLL1PFD0, 1) +#define A55PERIPH_CLK_ROOT_SYS_PLL1PFD1 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_A55PERIPH, SYS_PLL1PFD1, 2) +#define A55PERIPH_CLK_ROOT_SYS_PLL1PFD2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_A55PERIPH, SYS_PLL1PFD2, 3) + +#define A55MTRBUS_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_A55MTRBUS, OSC_24M, 0) +#define A55MTRBUS_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_A55MTRBUS, SYS_PLL1PFD0DIV2, 1) +#define A55MTRBUS_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_A55MTRBUS, SYS_PLL1PFD1DIV2, 2) +#define A55MTRBUS_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_A55MTRBUS, VIDEO_PLL1OUT, 3) + +#define A55_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_A55, CCM_CR_A55, OSC_24M, 0) +#define A55_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_A55, CCM_CR_A55, SYS_PLL1PFD0, 1) +#define A55_CLK_ROOT_SYS_PLL1PFD1 CLOCK_ROOT_CONFIG(CCM_LPCG_A55, CCM_CR_A55, SYS_PLL1PFD1, 2) +#define A55_CLK_ROOT_SYS_PLL1PFD2 CLOCK_ROOT_CONFIG(CCM_LPCG_A55, CCM_CR_A55, SYS_PLL1PFD2, 3) + +#define M33_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_M33, OSC_24M, 0) +#define M33_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_M33, SYS_PLL1PFD0DIV2, 1) +#define M33_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_M33, SYS_PLL1PFD1DIV2, 2) +#define M33_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_M33, VIDEO_PLL1OUT, 3) + +#define SENTINEL_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_SENTINEL, CCM_CR_SENTINEL, OSC_24M, 0) +#define SENTINEL_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_SENTINEL, CCM_CR_SENTINEL, SYS_PLL1PFD0DIV2, 1) +#define SENTINEL_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_SENTINEL, CCM_CR_SENTINEL, SYS_PLL1PFD1DIV2, 2) +#define SENTINEL_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_SENTINEL, CCM_CR_SENTINEL, VIDEO_PLL1OUT, 3) + +#define BUSWAKEUP_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_BUSWAKEUP, OSC_24M, 0) +#define BUSWAKEUP_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_BUSWAKEUP, SYS_PLL1PFD0DIV2, 1) +#define BUSWAKEUP_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_BUSWAKEUP, SYS_PLL1PFD1DIV2, 2) +#define BUSWAKEUP_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_BUSWAKEUP, VIDEO_PLL1OUT, 3) + +#define BUSAON_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_BUSAON, OSC_24M, 0) +#define BUSAON_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_BUSAON, SYS_PLL1PFD0DIV2, 1) +#define BUSAON_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_BUSAON, SYS_PLL1PFD1DIV2, 2) +#define BUSAON_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_BUSAON, VIDEO_PLL1OUT, 3) + +#define WAKEUPAXI_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_WAKEUPAXI, OSC_24M, 0) +#define WAKEUPAXI_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_WAKEUPAXI, SYS_PLL1PFD0, 1) +#define WAKEUPAXI_CLK_ROOT_SYS_PLL1PFD1 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_WAKEUPAXI, SYS_PLL1PFD1, 2) +#define WAKEUPAXI_CLK_ROOT_SYS_PLL1PFD2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_WAKEUPAXI, SYS_PLL1PFD2, 3) + +#define SWOTRACE_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_SWOTRACE, OSC_24M, 0) +#define SWOTRACE_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_SWOTRACE, SYS_PLL1PFD0DIV2, 1) +#define SWOTRACE_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_SWOTRACE, SYS_PLL1PFD1DIV2, 2) +#define SWOTRACE_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_SWOTRACE, VIDEO_PLL1OUT, 3) + +#define M33SYSTICK_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_M33SYSTICK, OSC_24M, 0) +#define M33SYSTICK_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_M33SYSTICK, SYS_PLL1PFD0DIV2, 1) +#define M33SYSTICK_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_M33SYSTICK, SYS_PLL1PFD1DIV2, 2) +#define M33SYSTICK_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_M33SYSTICK, VIDEO_PLL1OUT, 3) + +#define FLEXIO1_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_FLEXIO1, CCM_CR_FLEXIO1, OSC_24M, 0) +#define FLEXIO1_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_FLEXIO1, CCM_CR_FLEXIO1, SYS_PLL1PFD0DIV2, 1) +#define FLEXIO1_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_FLEXIO1, CCM_CR_FLEXIO1, SYS_PLL1PFD1DIV2, 2) +#define FLEXIO1_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_FLEXIO1, CCM_CR_FLEXIO1, VIDEO_PLL1OUT, 3) + +#define FLEXIO2_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_FLEXIO2, CCM_CR_FLEXIO2, OSC_24M, 0) +#define FLEXIO2_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_FLEXIO2, CCM_CR_FLEXIO2, SYS_PLL1PFD0DIV2, 1) +#define FLEXIO2_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_FLEXIO2, CCM_CR_FLEXIO2, SYS_PLL1PFD1DIV2, 2) +#define FLEXIO2_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_FLEXIO2, CCM_CR_FLEXIO2, VIDEO_PLL1OUT, 3) + +#define LPIT1_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPIT1, CCM_CR_LPIT1, OSC_24M, 0) +#define LPIT1_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPIT1, CCM_CR_LPIT1, SYS_PLL1PFD0DIV2, 1) +#define LPIT1_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPIT1, CCM_CR_LPIT1, SYS_PLL1PFD1DIV2, 2) +#define LPIT1_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPIT1, CCM_CR_LPIT1, VIDEO_PLL1OUT, 3) + +#define LPIT2_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPIT2, CCM_CR_LPIT2, OSC_24M, 0) +#define LPIT2_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPIT2, CCM_CR_LPIT2, SYS_PLL1PFD0DIV2, 1) +#define LPIT2_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPIT2, CCM_CR_LPIT2, SYS_PLL1PFD1DIV2, 2) +#define LPIT2_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPIT2, CCM_CR_LPIT2, VIDEO_PLL1OUT, 3) + +#define LPTMR1_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPTMR1, CCM_CR_LPTMR1, OSC_24M, 0) +#define LPTMR1_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPTMR1, CCM_CR_LPTMR1, SYS_PLL1PFD0DIV2, 1) +#define LPTMR1_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPTMR1, CCM_CR_LPTMR1, SYS_PLL1PFD1DIV2, 2) +#define LPTMR1_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPTMR1, CCM_CR_LPTMR1, VIDEO_PLL1OUT, 3) + +#define LPTMR2_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPTMR2, CCM_CR_LPTMR2, OSC_24M, 0) +#define LPTMR2_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPTMR2, CCM_CR_LPTMR2, SYS_PLL1PFD0DIV2, 1) +#define LPTMR2_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPTMR2, CCM_CR_LPTMR2, SYS_PLL1PFD1DIV2, 2) +#define LPTMR2_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPTMR2, CCM_CR_LPTMR2, VIDEO_PLL1OUT, 3) + +#define TPM1_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_TPM1, CCM_CR_TPM1, OSC_24M, 0) +#define TPM1_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_TPM1, CCM_CR_TPM1, SYS_PLL1PFD0, 1) +#define TPM1_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_TPM1, CCM_CR_TPM1, AUDIO_PLL1OUT, 2) +#define TPM1_CLK_ROOT_EXT CLOCK_ROOT_CONFIG(CCM_LPCG_TPM1, CCM_CR_TPM1, EXT, 3) + +#define TPM2_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_TPM2, CCM_CR_TPM2, OSC_24M, 0) +#define TPM2_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_TPM2, CCM_CR_TPM2, SYS_PLL1PFD0, 1) +#define TPM2_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_TPM2, CCM_CR_TPM2, AUDIO_PLL1OUT, 2) +#define TPM2_CLK_ROOT_EXT CLOCK_ROOT_CONFIG(CCM_LPCG_TPM2, CCM_CR_TPM2, EXT, 3) + +#define TPM3_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_TPM3, CCM_CR_TPM3, OSC_24M, 0) +#define TPM3_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_TPM3, CCM_CR_TPM3, SYS_PLL1PFD0, 1) +#define TPM3_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_TPM3, CCM_CR_TPM3, AUDIO_PLL1OUT, 2) +#define TPM3_CLK_ROOT_EXT CLOCK_ROOT_CONFIG(CCM_LPCG_TPM3, CCM_CR_TPM3, EXT, 3) + +#define TPM4_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_TPM4, CCM_CR_TPM4, OSC_24M, 0) +#define TPM4_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_TPM4, CCM_CR_TPM4, SYS_PLL1PFD0, 1) +#define TPM4_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_TPM4, CCM_CR_TPM4, AUDIO_PLL1OUT, 2) +#define TPM4_CLK_ROOT_EXT CLOCK_ROOT_CONFIG(CCM_LPCG_TPM4, CCM_CR_TPM4, EXT, 3) + +#define TPM5_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_TPM5, CCM_CR_TPM5, OSC_24M, 0) +#define TPM5_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_TPM5, CCM_CR_TPM5, SYS_PLL1PFD0, 1) +#define TPM5_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_TPM5, CCM_CR_TPM5, AUDIO_PLL1OUT, 2) +#define TPM5_CLK_ROOT_EXT CLOCK_ROOT_CONFIG(CCM_LPCG_TPM5, CCM_CR_TPM5, EXT, 3) + +#define TPM6_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_TPM6, CCM_CR_TPM6, OSC_24M, 0) +#define TPM6_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_TPM6, CCM_CR_TPM6, SYS_PLL1PFD0, 1) +#define TPM6_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_TPM6, CCM_CR_TPM6, AUDIO_PLL1OUT, 2) +#define TPM6_CLK_ROOT_EXT CLOCK_ROOT_CONFIG(CCM_LPCG_TPM6, CCM_CR_TPM6, EXT, 3) + +#define FLEXSPI1_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_FLEXSPI1, CCM_CR_FLEXSPI1, OSC_24M, 0) +#define FLEXSPI1_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_FLEXSPI1, CCM_CR_FLEXSPI1, SYS_PLL1PFD0, 1) +#define FLEXSPI1_CLK_ROOT_SYS_PLL1PFD1 CLOCK_ROOT_CONFIG(CCM_LPCG_FLEXSPI1, CCM_CR_FLEXSPI1, SYS_PLL1PFD1, 2) +#define FLEXSPI1_CLK_ROOT_SYS_PLL1PFD2 CLOCK_ROOT_CONFIG(CCM_LPCG_FLEXSPI1, CCM_CR_FLEXSPI1, SYS_PLL1PFD2, 3) + +#define CAN1_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_CAN1, CCM_CR_CAN1, OSC_24M, 0) +#define CAN1_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_CAN1, CCM_CR_CAN1, SYS_PLL1PFD0DIV2, 1) +#define CAN1_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_CAN1, CCM_CR_CAN1, SYS_PLL1PFD1DIV2, 2) +#define CAN1_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_CAN1, CCM_CR_CAN1, VIDEO_PLL1OUT, 3) + +#define CAN2_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_CAN2, CCM_CR_CAN2, OSC_24M, 0) +#define CAN2_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_CAN2, CCM_CR_CAN2, SYS_PLL1PFD0DIV2, 1) +#define CAN2_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_CAN2, CCM_CR_CAN2, SYS_PLL1PFD1DIV2, 2) +#define CAN2_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_CAN2, CCM_CR_CAN2, VIDEO_PLL1OUT, 3) + +#define LPUART1_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART1, CCM_CR_LPUART1, OSC_24M, 0) +#define LPUART1_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART1, CCM_CR_LPUART1, SYS_PLL1PFD0DIV2, 1) +#define LPUART1_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART1, CCM_CR_LPUART1, SYS_PLL1PFD1DIV2, 2) +#define LPUART1_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART1, CCM_CR_LPUART1, VIDEO_PLL1OUT, 3) + +#define LPUART2_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART2, CCM_CR_LPUART2, OSC_24M, 0) +#define LPUART2_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART2, CCM_CR_LPUART2, SYS_PLL1PFD0DIV2, 1) +#define LPUART2_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART2, CCM_CR_LPUART2, SYS_PLL1PFD1DIV2, 2) +#define LPUART2_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART2, CCM_CR_LPUART2, VIDEO_PLL1OUT, 3) + +#define LPUART3_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART3, CCM_CR_LPUART3, OSC_24M, 0) +#define LPUART3_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART3, CCM_CR_LPUART3, SYS_PLL1PFD0DIV2, 1) +#define LPUART3_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART3, CCM_CR_LPUART3, SYS_PLL1PFD1DIV2, 2) +#define LPUART3_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART3, CCM_CR_LPUART3, VIDEO_PLL1OUT, 3) + +#define LPUART4_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART4, CCM_CR_LPUART4, OSC_24M, 0) +#define LPUART4_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART4, CCM_CR_LPUART4, SYS_PLL1PFD0DIV2, 1) +#define LPUART4_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART4, CCM_CR_LPUART4, SYS_PLL1PFD1DIV2, 2) +#define LPUART4_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART4, CCM_CR_LPUART4, VIDEO_PLL1OUT, 3) + +#define LPUART5_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART5, CCM_CR_LPUART5, OSC_24M, 0) +#define LPUART5_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART5, CCM_CR_LPUART5, SYS_PLL1PFD0DIV2, 1) +#define LPUART5_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART5, CCM_CR_LPUART5, SYS_PLL1PFD1DIV2, 2) +#define LPUART5_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART5, CCM_CR_LPUART5, VIDEO_PLL1OUT, 3) + +#define LPUART6_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART6, CCM_CR_LPUART6, OSC_24M, 0) +#define LPUART6_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART6, CCM_CR_LPUART6, SYS_PLL1PFD0DIV2, 1) +#define LPUART6_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART6, CCM_CR_LPUART6, SYS_PLL1PFD1DIV2, 2) +#define LPUART6_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART6, CCM_CR_LPUART6, VIDEO_PLL1OUT, 3) + +#define LPUART7_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART7, CCM_CR_LPUART7, OSC_24M, 0) +#define LPUART7_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART7, CCM_CR_LPUART7, SYS_PLL1PFD0DIV2, 1) +#define LPUART7_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART7, CCM_CR_LPUART7, SYS_PLL1PFD1DIV2, 2) +#define LPUART7_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART7, CCM_CR_LPUART7, VIDEO_PLL1OUT, 3) + +#define LPUART8_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART8, CCM_CR_LPUART8, OSC_24M, 0) +#define LPUART8_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART8, CCM_CR_LPUART8, SYS_PLL1PFD0DIV2, 1) +#define LPUART8_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART8, CCM_CR_LPUART8, SYS_PLL1PFD1DIV2, 2) +#define LPUART8_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPUART8, CCM_CR_LPUART8, VIDEO_PLL1OUT, 3) + +#define LPI2C1_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C1, CCM_CR_LPI2C1, OSC_24M, 0) +#define LPI2C1_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C1, CCM_CR_LPI2C1, SYS_PLL1PFD0DIV2, 1) +#define LPI2C1_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C1, CCM_CR_LPI2C1, SYS_PLL1PFD1DIV2, 2) +#define LPI2C1_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C1, CCM_CR_LPI2C1, VIDEO_PLL1OUT, 3) + +#define LPI2C2_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C2, CCM_CR_LPI2C2, OSC_24M, 0) +#define LPI2C2_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C2, CCM_CR_LPI2C2, SYS_PLL1PFD0DIV2, 1) +#define LPI2C2_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C2, CCM_CR_LPI2C2, SYS_PLL1PFD1DIV2, 2) +#define LPI2C2_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C2, CCM_CR_LPI2C2, VIDEO_PLL1OUT, 3) + +#define LPI2C3_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C3, CCM_CR_LPI2C3, OSC_24M, 0) +#define LPI2C3_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C3, CCM_CR_LPI2C3, SYS_PLL1PFD0DIV2, 1) +#define LPI2C3_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C3, CCM_CR_LPI2C3, SYS_PLL1PFD1DIV2, 2) +#define LPI2C3_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C3, CCM_CR_LPI2C3, VIDEO_PLL1OUT, 3) + +#define LPI2C4_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C4, CCM_CR_LPI2C4, OSC_24M, 0) +#define LPI2C4_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C4, CCM_CR_LPI2C4, SYS_PLL1PFD0DIV2, 1) +#define LPI2C4_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C4, CCM_CR_LPI2C4, SYS_PLL1PFD1DIV2, 2) +#define LPI2C4_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C4, CCM_CR_LPI2C4, VIDEO_PLL1OUT, 3) + +#define LPI2C5_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C5, CCM_CR_LPI2C5, OSC_24M, 0) +#define LPI2C5_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C5, CCM_CR_LPI2C5, SYS_PLL1PFD0DIV2, 1) +#define LPI2C5_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C5, CCM_CR_LPI2C5, SYS_PLL1PFD1DIV2, 2) +#define LPI2C5_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C5, CCM_CR_LPI2C5, VIDEO_PLL1OUT, 3) + +#define LPI2C6_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C6, CCM_CR_LPI2C6, OSC_24M, 0) +#define LPI2C6_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C6, CCM_CR_LPI2C6, SYS_PLL1PFD0DIV2, 1) +#define LPI2C6_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C6, CCM_CR_LPI2C6, SYS_PLL1PFD1DIV2, 2) +#define LPI2C6_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C6, CCM_CR_LPI2C6, VIDEO_PLL1OUT, 3) + +#define LPI2C7_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C7, CCM_CR_LPI2C7, OSC_24M, 0) +#define LPI2C7_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C7, CCM_CR_LPI2C7, SYS_PLL1PFD0DIV2, 1) +#define LPI2C7_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C7, CCM_CR_LPI2C7, SYS_PLL1PFD1DIV2, 2) +#define LPI2C7_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C7, CCM_CR_LPI2C7, VIDEO_PLL1OUT, 3) + +#define LPI2C8_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C8, CCM_CR_LPI2C8, OSC_24M, 0) +#define LPI2C8_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C8, CCM_CR_LPI2C8, SYS_PLL1PFD0DIV2, 1) +#define LPI2C8_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C8, CCM_CR_LPI2C8, SYS_PLL1PFD1DIV2, 2) +#define LPI2C8_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPI2C8, CCM_CR_LPI2C8, VIDEO_PLL1OUT, 3) + +#define LPSPI1_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI1, CCM_CR_LPSPI1, OSC_24M, 0) +#define LPSPI1_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI1, CCM_CR_LPSPI1, SYS_PLL1PFD0DIV2, 1) +#define LPSPI1_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI1, CCM_CR_LPSPI1, SYS_PLL1PFD1DIV2, 2) +#define LPSPI1_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI1, CCM_CR_LPSPI1, VIDEO_PLL1OUT, 3) + +#define LPSPI2_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI2, CCM_CR_LPSPI2, OSC_24M, 0) +#define LPSPI2_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI2, CCM_CR_LPSPI2, SYS_PLL1PFD0DIV2, 1) +#define LPSPI2_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI2, CCM_CR_LPSPI2, SYS_PLL1PFD1DIV2, 2) +#define LPSPI2_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI2, CCM_CR_LPSPI2, VIDEO_PLL1OUT, 3) + +#define LPSPI3_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI3, CCM_CR_LPSPI3, OSC_24M, 0) +#define LPSPI3_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI3, CCM_CR_LPSPI3, SYS_PLL1PFD0DIV2, 1) +#define LPSPI3_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI3, CCM_CR_LPSPI3, SYS_PLL1PFD1DIV2, 2) +#define LPSPI3_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI3, CCM_CR_LPSPI3, VIDEO_PLL1OUT, 3) + +#define LPSPI4_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI4, CCM_CR_LPSPI4, OSC_24M, 0) +#define LPSPI4_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI4, CCM_CR_LPSPI4, SYS_PLL1PFD0DIV2, 1) +#define LPSPI4_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI4, CCM_CR_LPSPI4, SYS_PLL1PFD1DIV2, 2) +#define LPSPI4_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI4, CCM_CR_LPSPI4, VIDEO_PLL1OUT, 3) + +#define LPSPI5_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI5, CCM_CR_LPSPI5, OSC_24M, 0) +#define LPSPI5_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI5, CCM_CR_LPSPI5, SYS_PLL1PFD0DIV2, 1) +#define LPSPI5_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI5, CCM_CR_LPSPI5, SYS_PLL1PFD1DIV2, 2) +#define LPSPI5_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI5, CCM_CR_LPSPI5, VIDEO_PLL1OUT, 3) + +#define LPSPI6_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI6, CCM_CR_LPSPI6, OSC_24M, 0) +#define LPSPI6_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI6, CCM_CR_LPSPI6, SYS_PLL1PFD0DIV2, 1) +#define LPSPI6_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI6, CCM_CR_LPSPI6, SYS_PLL1PFD1DIV2, 2) +#define LPSPI6_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI6, CCM_CR_LPSPI6, VIDEO_PLL1OUT, 3) + +#define LPSPI7_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI7, CCM_CR_LPSPI7, OSC_24M, 0) +#define LPSPI7_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI7, CCM_CR_LPSPI7, SYS_PLL1PFD0DIV2, 1) +#define LPSPI7_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI7, CCM_CR_LPSPI7, SYS_PLL1PFD1DIV2, 2) +#define LPSPI7_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI7, CCM_CR_LPSPI7, VIDEO_PLL1OUT, 3) + +#define LPSPI8_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI8, CCM_CR_LPSPI8, OSC_24M, 0) +#define LPSPI8_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI8, CCM_CR_LPSPI8, SYS_PLL1PFD0DIV2, 1) +#define LPSPI8_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI8, CCM_CR_LPSPI8, SYS_PLL1PFD1DIV2, 2) +#define LPSPI8_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_LPSPI8, CCM_CR_LPSPI8, VIDEO_PLL1OUT, 3) + +#define I3C1_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_I3C1, CCM_CR_I3C1, OSC_24M, 0) +#define I3C1_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_I3C1, CCM_CR_I3C1, SYS_PLL1PFD0DIV2, 1) +#define I3C1_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_I3C1, CCM_CR_I3C1, SYS_PLL1PFD1DIV2, 2) +#define I3C1_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_I3C1, CCM_CR_I3C1, VIDEO_PLL1OUT, 3) + +#define I3C2_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_I3C2, CCM_CR_I3C2, OSC_24M, 0) +#define I3C2_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_I3C2, CCM_CR_I3C2, SYS_PLL1PFD0DIV2, 1) +#define I3C2_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_I3C2, CCM_CR_I3C2, SYS_PLL1PFD1DIV2, 2) +#define I3C2_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_I3C2, CCM_CR_I3C2, VIDEO_PLL1OUT, 3) + +#define USDHC1_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_USDHC1, CCM_CR_USDHC1, OSC_24M, 0) +#define USDHC1_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_USDHC1, CCM_CR_USDHC1, SYS_PLL1PFD0, 1) +#define USDHC1_CLK_ROOT_SYS_PLL1PFD1 CLOCK_ROOT_CONFIG(CCM_LPCG_USDHC1, CCM_CR_USDHC1, SYS_PLL1PFD1, 2) +#define USDHC1_CLK_ROOT_SYS_PLL1PFD2 CLOCK_ROOT_CONFIG(CCM_LPCG_USDHC1, CCM_CR_USDHC1, SYS_PLL1PFD2, 3) + +#define USDHC2_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_USDHC2, CCM_CR_USDHC2, OSC_24M, 0) +#define USDHC2_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_USDHC2, CCM_CR_USDHC2, SYS_PLL1PFD0, 1) +#define USDHC2_CLK_ROOT_SYS_PLL1PFD1 CLOCK_ROOT_CONFIG(CCM_LPCG_USDHC2, CCM_CR_USDHC2, SYS_PLL1PFD1, 2) +#define USDHC2_CLK_ROOT_SYS_PLL1PFD2 CLOCK_ROOT_CONFIG(CCM_LPCG_USDHC2, CCM_CR_USDHC2, SYS_PLL1PFD2, 3) + +#define USDHC3_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_USDHC3, CCM_CR_USDHC3, OSC_24M, 0) +#define USDHC3_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_USDHC3, CCM_CR_USDHC3, SYS_PLL1PFD0, 1) +#define USDHC3_CLK_ROOT_SYS_PLL1PFD1 CLOCK_ROOT_CONFIG(CCM_LPCG_USDHC3, CCM_CR_USDHC3, SYS_PLL1PFD1, 2) +#define USDHC3_CLK_ROOT_SYS_PLL1PFD2 CLOCK_ROOT_CONFIG(CCM_LPCG_USDHC3, CCM_CR_USDHC3, SYS_PLL1PFD2, 3) + +#define SAI1_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_SAI1, CCM_CR_SAI1, OSC_24M, 0) +#define SAI1_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_SAI1, CCM_CR_SAI1, AUDIO_PLL1OUT, 1) +#define SAI1_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_SAI1, CCM_CR_SAI1, VIDEO_PLL1OUT, 2) +#define SAI1_CLK_ROOT_EXT CLOCK_ROOT_CONFIG(CCM_LPCG_SAI1, CCM_CR_SAI1, EXT, 3) + +#define SAI2_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_SAI2, CCM_CR_SAI2, OSC_24M, 0) +#define SAI2_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_SAI2, CCM_CR_SAI2, AUDIO_PLL1OUT, 1) +#define SAI2_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_SAI2, CCM_CR_SAI2, VIDEO_PLL1OUT, 2) +#define SAI2_CLK_ROOT_EXT CLOCK_ROOT_CONFIG(CCM_LPCG_SAI2, CCM_CR_SAI2, EXT, 3) + +#define SAI3_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_SAI3, CCM_CR_SAI3, OSC_24M, 0) +#define SAI3_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_SAI3, CCM_CR_SAI3, AUDIO_PLL1OUT, 1) +#define SAI3_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_SAI3, CCM_CR_SAI3, VIDEO_PLL1OUT, 2) +#define SAI3_CLK_ROOT_EXT CLOCK_ROOT_CONFIG(CCM_LPCG_SAI3, CCM_CR_SAI3, EXT, 3) + +#define CCMCKO1_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CCMCKO1, OSC_24M, 0) +#define CCMCKO1_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CCMCKO1, SYS_PLL1PFD0, 1) +#define CCMCKO1_CLK_ROOT_SYS_PLL1PFD1 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CCMCKO1, SYS_PLL1PFD1, 2) +#define CCMCKO1_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CCMCKO1, AUDIO_PLL1OUT, 3) + +#define CCMCKO2_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CCMCKO2, OSC_24M, 0) +#define CCMCKO2_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CCMCKO2, SYS_PLL1PFD0, 1) +#define CCMCKO2_CLK_ROOT_SYS_PLL1PFD1 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CCMCKO2, SYS_PLL1PFD1, 2) +#define CCMCKO2_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CCMCKO2, VIDEO_PLL1OUT, 3) + +#define CCMCKO3_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CCMCKO3, OSC_24M, 0) +#define CCMCKO3_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CCMCKO3, SYS_PLL1PFD0, 1) +#define CCMCKO3_CLK_ROOT_SYS_PLL1PFD1 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CCMCKO3, SYS_PLL1PFD1, 2) +#define CCMCKO3_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CCMCKO3, AUDIO_PLL1OUT, 3) + +#define CCMCKO4_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CCMCKO4, OSC_24M, 0) +#define CCMCKO4_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CCMCKO4, SYS_PLL1PFD0, 1) +#define CCMCKO4_CLK_ROOT_SYS_PLL1PFD1 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CCMCKO4, SYS_PLL1PFD1, 2) +#define CCMCKO4_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CCMCKO4, VIDEO_PLL1OUT, 3) + +#define HSIO_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_HSIO, OSC_24M, 0) +#define HSIO_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_HSIO, SYS_PLL1PFD0DIV2, 1) +#define HSIO_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_HSIO, SYS_PLL1PFD1DIV2, 2) +#define HSIO_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_HSIO, VIDEO_PLL1OUT, 3) + +#define HSIOUSBTEST60M_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_HSIOUSBTEST60M, OSC_24M, 0) +#define HSIOUSBTEST60M_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_HSIOUSBTEST60M, SYS_PLL1PFD0DIV2, 1) +#define HSIOUSBTEST60M_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_HSIOUSBTEST60M, SYS_PLL1PFD1DIV2, 2) +#define HSIOUSBTEST60M_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_HSIOUSBTEST60M, VIDEO_PLL1OUT, 3) + +#define HSIOACSCAN80M_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_HSIOACSCAN80M, OSC_24M, 0) +#define HSIOACSCAN80M_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_HSIOACSCAN80M, SYS_PLL1PFD0DIV2, 1) +#define HSIOACSCAN80M_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_HSIOACSCAN80M, SYS_PLL1PFD1DIV2, 2) +#define HSIOACSCAN80M_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_HSIOACSCAN80M, VIDEO_PLL1OUT, 3) + +#define HSIOACSCAN480M_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_HSIOACSCAN480M, OSC_24M, 0) +#define HSIOACSCAN480M_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_HSIOACSCAN480M, AUDIO_PLL1OUT, 1) +#define HSIOACSCAN480M_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_HSIOACSCAN480M, VIDEO_PLL1OUT, 2) +#define HSIOACSCAN480M_CLK_ROOT_SYS_PLL1PFD2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_HSIOACSCAN480M, SYS_PLL1PFD2, 3) + +#define NIC_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_NIC, OSC_24M, 0) +#define NIC_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_NIC, SYS_PLL1PFD0, 1) +#define NIC_CLK_ROOT_SYS_PLL1PFD1 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_NIC, SYS_PLL1PFD1, 2) +#define NIC_CLK_ROOT_SYS_PLL1PFD2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_NIC, SYS_PLL1PFD2, 3) + +#define NICAPB_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_NICAPB, OSC_24M, 0) +#define NICAPB_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_NICAPB, SYS_PLL1PFD0DIV2, 1) +#define NICAPB_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_NICAPB, SYS_PLL1PFD1DIV2, 2) +#define NICAPB_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_NICAPB, VIDEO_PLL1OUT, 3) + +#define MLAPB_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MLAPB, OSC_24M, 0) +#define MLAPB_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MLAPB, SYS_PLL1PFD0DIV2, 1) +#define MLAPB_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MLAPB, SYS_PLL1PFD1DIV2, 2) +#define MLAPB_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MLAPB, VIDEO_PLL1OUT, 3) + +#define ML_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ML, OSC_24M, 0) +#define ML_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ML, SYS_PLL1PFD0, 1) +#define ML_CLK_ROOT_SYS_PLL1PFD1 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ML, SYS_PLL1PFD1, 2) +#define ML_CLK_ROOT_SYS_PLL1PFD2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ML, SYS_PLL1PFD2, 3) + +#define MEDIAAXI_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MEDIAAXI, OSC_24M, 0) +#define MEDIAAXI_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MEDIAAXI, SYS_PLL1PFD0, 1) +#define MEDIAAXI_CLK_ROOT_SYS_PLL1PFD1 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MEDIAAXI, SYS_PLL1PFD1, 2) +#define MEDIAAXI_CLK_ROOT_SYS_PLL1PFD2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MEDIAAXI, SYS_PLL1PFD2, 3) + +#define MEDIAAPB_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MEDIAAPB, OSC_24M, 0) +#define MEDIAAPB_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MEDIAAPB, SYS_PLL1PFD0DIV2, 1) +#define MEDIAAPB_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MEDIAAPB, SYS_PLL1PFD1DIV2, 2) +#define MEDIAAPB_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MEDIAAPB, VIDEO_PLL1OUT, 3) + +#define MEDIALDB_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MEDIALDB, OSC_24M, 0) +#define MEDIALDB_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MEDIALDB, AUDIO_PLL1OUT, 1) +#define MEDIALDB_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MEDIALDB, VIDEO_PLL1OUT, 2) +#define MEDIALDB_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MEDIALDB, SYS_PLL1PFD0, 3) + +#define MEDIADISPPIX_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MEDIADISPPIX, OSC_24M, 0) +#define MEDIADISPPIX_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MEDIADISPPIX, AUDIO_PLL1OUT, 1) +#define MEDIADISPPIX_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MEDIADISPPIX, VIDEO_PLL1OUT, 2) +#define MEDIADISPPIX_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MEDIADISPPIX, SYS_PLL1PFD0, 3) + +#define CAMPIX_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CAMPIX, OSC_24M, 0) +#define CAMPIX_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CAMPIX, AUDIO_PLL1OUT, 1) +#define CAMPIX_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CAMPIX, VIDEO_PLL1OUT, 2) +#define CAMPIX_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_CAMPIX, SYS_PLL1PFD0, 3) + +#define MIPITESTBYTE_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MIPITESTBYTE, OSC_24M, 0) +#define MIPITESTBYTE_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MIPITESTBYTE, AUDIO_PLL1OUT, 1) +#define MIPITESTBYTE_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MIPITESTBYTE, VIDEO_PLL1OUT, 2) +#define MIPITESTBYTE_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MIPITESTBYTE, SYS_PLL1PFD0, 3) + +#define MIPIPHYCFG_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MIPIPHYCFG, OSC_24M, 0) +#define MIPIPHYCFG_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MIPIPHYCFG, AUDIO_PLL1OUT, 1) +#define MIPIPHYCFG_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MIPIPHYCFG, VIDEO_PLL1OUT, 2) +#define MIPIPHYCFG_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_MIPIPHYCFG, SYS_PLL1PFD0, 3) + +#define DRAMALT_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_DRAMALT, OSC_24M, 0) +#define DRAMALT_CLK_ROOT_SYS_PLL1PFD0 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_DRAMALT, SYS_PLL1PFD0, 1) +#define DRAMALT_CLK_ROOT_SYS_PLL1PFD1 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_DRAMALT, SYS_PLL1PFD1, 2) +#define DRAMALT_CLK_ROOT_SYS_PLL1PFD2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_DRAMALT, SYS_PLL1PFD2, 3) + +#define DRAMAPB_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_DRAMAPB, OSC_24M, 0) +#define DRAMAPB_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_DRAMAPB, SYS_PLL1PFD0DIV2, 1) +#define DRAMAPB_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_DRAMAPB, SYS_PLL1PFD1DIV2, 2) +#define DRAMAPB_CLK_ROOT_SYS_PLL1PFD2DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_DRAMAPB, SYS_PLL1PFD2DIV2, 3) + +#define ADC_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ADC, OSC_24M, 0) +#define ADC_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ADC, SYS_PLL1PFD0DIV2, 1) +#define ADC_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ADC, SYS_PLL1PFD1DIV2, 2) +#define ADC_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ADC, VIDEO_PLL1OUT, 3) + +#define PDM_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_PDM, CCM_CR_PDM, OSC_24M, 0) +#define PDM_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_PDM, CCM_CR_PDM, AUDIO_PLL1OUT, 1) +#define PDM_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_PDM, CCM_CR_PDM, VIDEO_PLL1OUT, 2) +#define PDM_CLK_ROOT_EXT CLOCK_ROOT_CONFIG(CCM_LPCG_PDM, CCM_CR_PDM, EXT, 3) + +#define TSTMR1_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_TSTMR1, CCM_CR_TSTMR1, OSC_24M, 0) +#define TSTMR1_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_TSTMR1, CCM_CR_TSTMR1, SYS_PLL1PFD0DIV2, 1) +#define TSTMR1_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_TSTMR1, CCM_CR_TSTMR1, SYS_PLL1PFD1DIV2, 2) +#define TSTMR1_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_TSTMR1, CCM_CR_TSTMR1, VIDEO_PLL1OUT, 3) + +#define TSTMR2_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_TSTMR2, CCM_CR_TSTMR2, OSC_24M, 0) +#define TSTMR2_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_TSTMR2, CCM_CR_TSTMR2, SYS_PLL1PFD0DIV2, 1) +#define TSTMR2_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_TSTMR2, CCM_CR_TSTMR2, SYS_PLL1PFD1DIV2, 2) +#define TSTMR2_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_TSTMR2, CCM_CR_TSTMR2, VIDEO_PLL1OUT, 3) + +#define MQS1_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_MQS1, CCM_CR_MQS1, OSC_24M, 0) +#define MQS1_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_MQS1, CCM_CR_MQS1, AUDIO_PLL1OUT, 1) +#define MQS1_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_MQS1, CCM_CR_MQS1, VIDEO_PLL1OUT, 2) +#define MQS1_CLK_ROOT_EXT CLOCK_ROOT_CONFIG(CCM_LPCG_MQS1, CCM_CR_MQS1, EXT, 3) + +#define MQS2_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_MQS2, CCM_CR_MQS2, OSC_24M, 0) +#define MQS2_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_MQS2, CCM_CR_MQS2, AUDIO_PLL1OUT, 1) +#define MQS2_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_MQS2, CCM_CR_MQS2, VIDEO_PLL1OUT, 2) +#define MQS2_CLK_ROOT_EXT CLOCK_ROOT_CONFIG(CCM_LPCG_MQS2, CCM_CR_MQS2, EXT, 3) + +#define AUDIOXCVR_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_AUDIOXCVR, OSC_24M, 0) +#define AUDIOXCVR_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_AUDIOXCVR, SYS_PLL1PFD0DIV2, 1) +#define AUDIOXCVR_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_AUDIOXCVR, SYS_PLL1PFD1DIV2, 2) +#define AUDIOXCVR_CLK_ROOT_SYS_PLL1PFD2DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_AUDIOXCVR, SYS_PLL1PFD2DIV2, 3) + +#define SPDIF_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_SPDIF, CCM_CR_SPDIF, OSC_24M, 0) +#define SPDIF_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_SPDIF, CCM_CR_SPDIF, AUDIO_PLL1OUT, 1) +#define SPDIF_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_SPDIF, CCM_CR_SPDIF, VIDEO_PLL1OUT, 2) +#define SPDIF_CLK_ROOT_EXT CLOCK_ROOT_CONFIG(CCM_LPCG_SPDIF, CCM_CR_SPDIF, EXT, 3) + +#define ENET_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENET, OSC_24M, 0) +#define ENET_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENET, SYS_PLL1PFD0DIV2, 1) +#define ENET_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENET, SYS_PLL1PFD1DIV2, 2) +#define ENET_CLK_ROOT_SYS_PLL1PFD2DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENET, SYS_PLL1PFD2DIV2, 3) + +#define ENETTIMER1_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENETTIMER1, OSC_24M, 0) +#define ENETTIMER1_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENETTIMER1, SYS_PLL1PFD0DIV2, 1) +#define ENETTIMER1_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENETTIMER1, SYS_PLL1PFD1DIV2, 2) +#define ENETTIMER1_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENETTIMER1, VIDEO_PLL1OUT, 3) + +#define ENETTIMER2_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENETTIMER2, OSC_24M, 0) +#define ENETTIMER2_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENETTIMER2, SYS_PLL1PFD0DIV2, 1) +#define ENETTIMER2_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENETTIMER2, SYS_PLL1PFD1DIV2, 2) +#define ENETTIMER2_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENETTIMER2, VIDEO_PLL1OUT, 3) + +#define ENETREF_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENETREF, OSC_24M, 0) +#define ENETREF_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENETREF, SYS_PLL1PFD0DIV2, 1) +#define ENETREF_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENETREF, SYS_PLL1PFD1DIV2, 2) +#define ENETREF_CLK_ROOT_SYS_PLL1PFD2DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENETREF, SYS_PLL1PFD2DIV2, 3) + +#define ENETREFPHY_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENETREFPHY, OSC_24M, 0) +#define ENETREFPHY_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENETREFPHY, SYS_PLL1PFD0DIV2, 1) +#define ENETREFPHY_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENETREFPHY, SYS_PLL1PFD1DIV2, 2) +#define ENETREFPHY_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_ENETREFPHY, VIDEO_PLL1OUT, 3) + +#define I3C1SLOW_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_I3C1SLOW, OSC_24M, 0) +#define I3C1SLOW_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_I3C1SLOW, SYS_PLL1PFD0DIV2, 1) +#define I3C1SLOW_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_I3C1SLOW, SYS_PLL1PFD1DIV2, 2) +#define I3C1SLOW_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_I3C1SLOW, VIDEO_PLL1OUT, 3) + +#define I3C2SLOW_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_I3C2SLOW, OSC_24M, 0) +#define I3C2SLOW_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_I3C2SLOW, SYS_PLL1PFD0DIV2, 1) +#define I3C2SLOW_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_I3C2SLOW, SYS_PLL1PFD1DIV2, 2) +#define I3C2SLOW_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_I3C2SLOW, VIDEO_PLL1OUT, 3) + +#define USBPHYBURUNIN_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_USBPHYBURUNIN, OSC_24M, 0) +#define USBPHYBURUNIN_CLK_ROOT_SYS_PLL1PFD0DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_USBPHYBURUNIN, SYS_PLL1PFD0DIV2, 1) +#define USBPHYBURUNIN_CLK_ROOT_SYS_PLL1PFD1DIV2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_USBPHYBURUNIN, SYS_PLL1PFD1DIV2, 2) +#define USBPHYBURUNIN_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_USBPHYBURUNIN, VIDEO_PLL1OUT, 3) + +#define PALCAMESCAN_CLK_ROOT_OSC_24M CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_PALCAMESCAN, OSC_24M, 0) +#define PALCAMESCAN_CLK_ROOT_AUDIO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_PALCAMESCAN, AUDIO_PLL1OUT, 1) +#define PALCAMESCAN_CLK_ROOT_VIDEO_PLL1OUT CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_PALCAMESCAN, VIDEO_PLL1OUT, 2) +#define PALCAMESCAN_CLK_ROOT_SYS_PLL1PFD2 CLOCK_ROOT_CONFIG(CCM_LPCG_NONE, CCM_CR_PALCAMESCAN, SYS_PLL1PFD2, 3) + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX93_CLOCK_H */ \ No newline at end of file diff --git a/arch/arm/src/imx9/hardware/imx93/imx93_dmamux.h b/arch/arm/src/imx9/hardware/imx93/imx93_dmamux.h new file mode 100644 index 00000000000..5ae9c841612 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx93/imx93_dmamux.h @@ -0,0 +1,211 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx93/imx93_dmamux.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_DMAMUX_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_DMAMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "imx93_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Identify channel MUX from 9th bit */ + +#define EDMA3_MUX_ID 0x0000 +#define EDMA4_MUX_ID 0x0100 +#define EDMA_MUX_ID_MASK 0xff00 +#define EDMA_MUX_MASK 0x00ff + +/* eDMA3 MUXs */ + +#define DMA_REQUEST_DISABLED (0) /**< Channel disabled */ +#define DMA_REQUEST_MUXCAN1 (1 | EDMA3_MUX_ID) /**< CAN1 */ +#define DMA_REQUEST_MUXGPIO1_0 (3 | EDMA3_MUX_ID) /**< GPIO1 channel 0 */ +#define DMA_REQUEST_MUXGPIO1_1 (4 | EDMA3_MUX_ID) /**< GPIO1 channel 1 */ +#define DMA_REQUEST_MUXI3C1TOBUS (5 | EDMA3_MUX_ID) /**< I3C1 To-bus Request */ +#define DMA_REQUEST_MUXI3C1FROMBUS (6 | EDMA3_MUX_ID) /**< I3C1 From-bus Request */ +#define DMA_REQUEST_MUXLPI2C1TX (7 | EDMA3_MUX_ID) /**< LPI2C1 */ +#define DMA_REQUEST_MUXLPI2C1RX (8 | EDMA3_MUX_ID) /**< LPI2C1 */ +#define DMA_REQUEST_MUXLPI2C2TX (9 | EDMA3_MUX_ID) /**< LPI2C2 */ +#define DMA_REQUEST_MUXLPI2C2RX (10 | EDMA3_MUX_ID) /**< LPI2C2 */ +#define DMA_REQUEST_MUXLPSPI1TX (11 | EDMA3_MUX_ID) /**< LPSPI1 Transmit */ +#define DMA_REQUEST_MUXLPSPI1RX (12 | EDMA3_MUX_ID) /**< LPSPI1 Receive */ +#define DMA_REQUEST_MUXLPSPI2TX (13 | EDMA3_MUX_ID) /**< LPSPI2 Transmit */ +#define DMA_REQUEST_MUXLPSPI2RX (14 | EDMA3_MUX_ID) /**< LPSPI2 Receive */ +#define DMA_REQUEST_MUXLPTMR1 (15 | EDMA3_MUX_ID) /**< LPTMR1 Request */ +#define DMA_REQUEST_MUXLPUART1TX (16 | EDMA3_MUX_ID) /**< LPUART1 Transmit */ +#define DMA_REQUEST_MUXLPUART1RX (17 | EDMA3_MUX_ID) /**< LPUART1 Receive */ +#define DMA_REQUEST_MUXLPUART2TX (18 | EDMA3_MUX_ID) /**< LPUART2 Transmit */ +#define DMA_REQUEST_MUXLPUART2RX (19 | EDMA3_MUX_ID) /**< LPUART2 Receive */ +#define DMA_REQUEST_MUXEDGELOCK (20 | EDMA3_MUX_ID) /**< Edgelock enclave DMA Request */ +#define DMA_REQUEST_MUXSAI1TX (21 | EDMA3_MUX_ID) /**< SAI1 Transmit */ +#define DMA_REQUEST_MUXSAI1RX (22 | EDMA3_MUX_ID) /**< SAI1 Receive */ +#define DMA_REQUEST_MUXTPM1_0_2 (23 | EDMA3_MUX_ID) /**< TPM1 request 0 and request 2 */ +#define DMA_REQUEST_MUXTPM1_1_3 (24 | EDMA3_MUX_ID) /**< TPM1 request 1 and request 3 */ +#define DMA_REQUEST_MUXTPM1OVERFLOW (25 | EDMA3_MUX_ID) /**< TPM1 Overflow request */ +#define DMA_REQUEST_MUXTPM2_0_2 (26 | EDMA3_MUX_ID) /**< TPM2 request 0 and request 2 */ +#define DMA_REQUEST_MUXTPM2_1_3 (27 | EDMA3_MUX_ID) /**< TPM2 request 1 and request 3 */ +#define DMA_REQUEST_MUXTPM2OVERFLOW (28 | EDMA3_MUX_ID) /**< TPM2 Overflow request */ +#define DMA_REQUEST_MUXPDM (29 | EDMA3_MUX_ID) /**< PDM */ +#define DMA_REQUEST_MUXADC1 (30 | EDMA3_MUX_ID) /**< ADC1 */ + +#define DMA3_REQUEST_MUX_COUNT (31) + +/* eDMA4 MUXs */ + +#define DMA_REQUEST_MUXCAN2 (1 | EDMA4_MUX_ID) /**< CAN2 */ +#define DMA_REQUEST_MUXGPIO2_0 (2 | EDMA4_MUX_ID) /**< GPIO2 channel 0 */ +#define DMA_REQUEST_MUXGPIO2_1 (3 | EDMA4_MUX_ID) /**< GPIO2 channel 1 */ +#define DMA_REQUEST_MUXGPIO3_0 (4 | EDMA4_MUX_ID) /**< GPIO3 channel 0 */ +#define DMA_REQUEST_MUXGPIO3_1 (5 | EDMA4_MUX_ID) /**< GPIO3 channel 1 */ +#define DMA_REQUEST_MUXI3C2TOBUS (6 | EDMA4_MUX_ID) /**< I3C2 To-bus Request */ +#define DMA_REQUEST_MUXI3C2FROMBUS (7 | EDMA4_MUX_ID) /**< I3C2 From-bus Request */ +#define DMA_REQUEST_MUXLPI2C3TX (8 | EDMA4_MUX_ID) /**< LPI2C3 */ +#define DMA_REQUEST_MUXLPI2C3RX (9 | EDMA4_MUX_ID) /**< LPI2C3 */ +#define DMA_REQUEST_MUXLPI2C4TX (10 | EDMA4_MUX_ID) /**< LPI2C4 */ +#define DMA_REQUEST_MUXLPI2C4RX (11 | EDMA4_MUX_ID) /**< LPI2C4 */ +#define DMA_REQUEST_MUXLPSPI3TX (12 | EDMA4_MUX_ID) /**< LPSPI3 Transmit */ +#define DMA_REQUEST_MUXLPSPI3RX (13 | EDMA4_MUX_ID) /**< LPSPI3 Receive */ +#define DMA_REQUEST_MUXLPSPI4TX (14 | EDMA4_MUX_ID) /**< LPSPI4 Transmit */ +#define DMA_REQUEST_MUXLPSPI4RX (15 | EDMA4_MUX_ID) /**< LPSPI4 Receive */ +#define DMA_REQUEST_MUXLPTMR2 (16 | EDMA4_MUX_ID) /**< LPTMR2 Request */ +#define DMA_REQUEST_MUXLPUART3TX (17 | EDMA4_MUX_ID) /**< LPUART3 Transmit */ +#define DMA_REQUEST_MUXLPUART3RX (18 | EDMA4_MUX_ID) /**< LPUART3 Receive */ +#define DMA_REQUEST_MUXLPUART4TX (19 | EDMA4_MUX_ID) /**< LPUART4 Transmit */ +#define DMA_REQUEST_MUXLPUART4RX (20 | EDMA4_MUX_ID) /**< LPUART4 Receive */ +#define DMA_REQUEST_MUXLPUART5TX (21 | EDMA4_MUX_ID) /**< LPUART5 Transmit */ +#define DMA_REQUEST_MUXLPUART5RX (22 | EDMA4_MUX_ID) /**< LPUART5 Receive */ +#define DMA_REQUEST_MUXLPUART6TX (23 | EDMA4_MUX_ID) /**< LPUART6 Transmit */ +#define DMA_REQUEST_MUXLPUART6RX (24 | EDMA4_MUX_ID) /**< LPUART6 Receive */ +#define DMA_REQUEST_MUXTPM3_0_2 (25 | EDMA4_MUX_ID) /**< TPM3 request 0 and request 2 */ +#define DMA_REQUEST_MUXTPM3_1_3 (26 | EDMA4_MUX_ID) /**< TPM3 request 1 and request 3 */ +#define DMA_REQUEST_MUXTPM3OVERFLOW (27 | EDMA4_MUX_ID) /**< TPM3 Overflow request */ +#define DMA_REQUEST_MUXTPM4_0_2 (28 | EDMA4_MUX_ID) /**< TPM4 request 0 and request 2 */ +#define DMA_REQUEST_MUXTPM4_1_3 (29 | EDMA4_MUX_ID) /**< TPM4 request 1 and request 3 */ +#define DMA_REQUEST_MUXTPM4OVERFLOW (30 | EDMA4_MUX_ID) /**< TPM4 Overflow request */ +#define DMA_REQUEST_MUXTPM5_0_2 (31 | EDMA4_MUX_ID) /**< TPM5 request 0 and request 2 */ +#define DMA_REQUEST_MUXTPM5_1_3 (32 | EDMA4_MUX_ID) /**< TPM5 request 1 and request 3 */ +#define DMA_REQUEST_MUXTPM5OVERFLOW (33 | EDMA4_MUX_ID) /**< TPM5 Overflow request */ +#define DMA_REQUEST_MUXTPM6_0_2 (34 | EDMA4_MUX_ID) /**< TPM6 request 0 and request 2 */ +#define DMA_REQUEST_MUXTPM6_1_3 (35 | EDMA4_MUX_ID) /**< TPM6 request 1 and request 3 */ +#define DMA_REQUEST_MUXTPM6OVERFLOW (36 | EDMA4_MUX_ID) /**< TPM6 Overflow request */ +#define DMA_REQUEST_MUXFLEXIO1_0 (37 | EDMA4_MUX_ID) /**< FlexIO1 Request0 */ +#define DMA_REQUEST_MUXFLEXIO1_1 (38 | EDMA4_MUX_ID) /**< FlexIO1 Request1 */ +#define DMA_REQUEST_MUXFLEXIO1_2 (39 | EDMA4_MUX_ID) /**< FlexIO1 Request2 */ +#define DMA_REQUEST_MUXFLEXIO1_3 (40 | EDMA4_MUX_ID) /**< FlexIO1 Request3 */ +#define DMA_REQUEST_MUXFLEXIO1_4 (41 | EDMA4_MUX_ID) /**< FlexIO1 Request4 */ +#define DMA_REQUEST_MUXFLEXIO1_5 (42 | EDMA4_MUX_ID) /**< FlexIO1 Request5 */ +#define DMA_REQUEST_MUXFLEXIO1_6 (43 | EDMA4_MUX_ID) /**< FlexIO1 Request6 */ +#define DMA_REQUEST_MUXFLEXIO1_7 (44 | EDMA4_MUX_ID) /**< FlexIO1 Request7 */ +#define DMA_REQUEST_MUXFLEXIO2_0 (45 | EDMA4_MUX_ID) /**< FlexIO2 Request0 */ +#define DMA_REQUEST_MUXFLEXIO2_1 (46 | EDMA4_MUX_ID) /**< FlexIO2 Request1 */ +#define DMA_REQUEST_MUXFLEXIO2_2 (47 | EDMA4_MUX_ID) /**< FlexIO2 Request2 */ +#define DMA_REQUEST_MUXFLEXIO2_3 (48 | EDMA4_MUX_ID) /**< FlexIO2 Request3 */ +#define DMA_REQUEST_MUXFLEXIO2_4 (49 | EDMA4_MUX_ID) /**< FlexIO2 Request4 */ +#define DMA_REQUEST_MUXFLEXIO2_5 (50 | EDMA4_MUX_ID) /**< FlexIO2 Request5 */ +#define DMA_REQUEST_MUXFLEXIO2_6 (51 | EDMA4_MUX_ID) /**< FlexIO2 Request6 */ +#define DMA_REQUEST_MUXFLEXIO2_7 (52 | EDMA4_MUX_ID) /**< FlexIO2 Request7 */ +#define DMA_REQUEST_MUXFLEXSPI1TX (53 | EDMA4_MUX_ID) /**< FlexSPI1 Transmit */ +#define DMA_REQUEST_MUXFLEXSPI1RX (54 | EDMA4_MUX_ID) /**< FlexSPI1 Receive */ +#define DMA_REQUEST_MUXSAI2TX (58 | EDMA4_MUX_ID) /**< SAI2 Transmit */ +#define DMA_REQUEST_MUXSAI2RX (59 | EDMA4_MUX_ID) /**< SAI2 Receive */ +#define DMA_REQUEST_MUXSAI3TX (60 | EDMA4_MUX_ID) /**< SAI3 Transmit */ +#define DMA_REQUEST_MUXSAI3RX (61 | EDMA4_MUX_ID) /**< SAI3 Receive */ +#define DMA_REQUEST_MUXGPIO4_0 (62 | EDMA4_MUX_ID) /**< GPIO4 channel 0 */ +#define DMA_REQUEST_MUXGPIO4_1 (63 | EDMA4_MUX_ID) /**< GPIO4 channel 1 */ +#define DMA_REQUEST_MUXSPDIF (65 | EDMA4_MUX_ID) /**< SPDIF */ +#define DMA_REQUEST_MUXSPDIF_1 (66 | EDMA4_MUX_ID) /**< SPDIF */ +#define DMA_REQUEST_MUXENET (67 | EDMA4_MUX_ID) /**< ENET */ +#define DMA_REQUEST_MUXENET_1 (68 | EDMA4_MUX_ID) /**< ENET */ +#define DMA_REQUEST_MUXENET_2 (69 | EDMA4_MUX_ID) /**< ENET */ +#define DMA_REQUEST_MUXENET_3 (70 | EDMA4_MUX_ID) /**< ENET */ +#define DMA_REQUEST_MUXLPI2C5TX (71 | EDMA4_MUX_ID) /**< LPI2C5 */ +#define DMA_REQUEST_MUXLPI2C5RX (72 | EDMA4_MUX_ID) /**< LPI2C5 */ +#define DMA_REQUEST_MUXLPI2C6TX (73 | EDMA4_MUX_ID) /**< LPI2C6 */ +#define DMA_REQUEST_MUXLPI2C6RX (74 | EDMA4_MUX_ID) /**< LPI2C6 */ +#define DMA_REQUEST_MUXLPI2C7TX (75 | EDMA4_MUX_ID) /**< LPI2C7 */ +#define DMA_REQUEST_MUXLPI2C7RX (76 | EDMA4_MUX_ID) /**< LPI2C7 */ +#define DMA_REQUEST_MUXLPI2C8TX (77 | EDMA4_MUX_ID) /**< LPI2C8 */ +#define DMA_REQUEST_MUXLPI2C8RX (78 | EDMA4_MUX_ID) /**< LPI2C8 */ +#define DMA_REQUEST_MUXLPSPI5TX (79 | EDMA4_MUX_ID) /**< LPSPI5 Transmit */ +#define DMA_REQUEST_MUXLPSPI5RX (80 | EDMA4_MUX_ID) /**< LPSPI5 Receive */ +#define DMA_REQUEST_MUXLPSPI6TX (81 | EDMA4_MUX_ID) /**< LPSPI6 Transmit */ +#define DMA_REQUEST_MUXLPSPI6RX (82 | EDMA4_MUX_ID) /**< LPSPI6 Receive */ +#define DMA_REQUEST_MUXLPSPI7TX (83 | EDMA4_MUX_ID) /**< LPSPI7 Transmit */ +#define DMA_REQUEST_MUXLPSPI7RX (84 | EDMA4_MUX_ID) /**< LPSPI7 Receive */ +#define DMA_REQUEST_MUXLPSPI8TX (85 | EDMA4_MUX_ID) /**< LPSPI8 Transmit */ +#define DMA_REQUEST_MUXLPSPI8RX (86 | EDMA4_MUX_ID) /**< LPSPI8 Receive */ +#define DMA_REQUEST_MUXLPUART7TX (87 | EDMA4_MUX_ID) /**< LPUART7 Transmit */ +#define DMA_REQUEST_MUXLPUART7RX (88 | EDMA4_MUX_ID) /**< LPUART7 Receive */ +#define DMA_REQUEST_MUXLPUART8TX (89 | EDMA4_MUX_ID) /**< LPUART8 Transmit */ +#define DMA_REQUEST_MUXLPUART8RX (90 | EDMA4_MUX_ID) /**< LPUART8 Receive */ +#define DMA_REQUEST_MUXENET_QOS (91 | EDMA4_MUX_ID) /**< ENET_QOS */ +#define DMA_REQUEST_MUXENET_QOS_1 (92 | EDMA4_MUX_ID) /**< ENET_QOS */ +#define DMA_REQUEST_MUXENET_QOS_2 (93 | EDMA4_MUX_ID) /**< ENET_QOS */ +#define DMA_REQUEST_MUXENET_QOS_3 (94 | EDMA4_MUX_ID) /**< ENET_QOS */ + +#define DMA4_REQUEST_MUX_COUNT (95) + +/* Combined MUX count (eDMA3 and eDMA4) */ + +#define DMA_REQUEST_MUX_COUNT (DMA3_REQUEST_MUX_COUNT + DMA4_REQUEST_MUX_COUNT) + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_dmamux_get_dmabase + * + * Description: + * Get DMA engine base address from MUX identifier. + * + * Input Parameters: + * dmamux - The DMA MUX identifier. + * + * Returned Value: + * Base address of the associated DMA engine. + * + ****************************************************************************/ + +static inline uintptr_t imx9_dmamux_get_dmabase(uint16_t dmamux) +{ + if ((dmamux & EDMA_MUX_ID_MASK) == EDMA3_MUX_ID) + { + return IMX9_DMA3_BASE; + } + else + { + return IMX9_DMA4_BASE; + } +} + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_DMAMUX_H */ diff --git a/arch/arm/src/imx9/hardware/imx93/imx93_edma.h b/arch/arm/src/imx9/hardware/imx93/imx93_edma.h new file mode 100644 index 00000000000..60e9241b423 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx93/imx93_edma.h @@ -0,0 +1,438 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx93/imx93_edma.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_EDMA_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_EDMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "imx93_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* eDMA3 / eDMA4 Register Offsets */ + +#define IMX9_EDMA_CSR_OFFSET (0x000000) /* Management Page Control Register (CSR) */ +#define IMX9_EDMA_ES_OFFSET (0x000004) /* Management Page Error Status Register (ES) */ +#define IMX9_EDMA_CH_GRPRI_OFFSET(n) (0x000100 + ((n) << 2)) /* Channel n Arbitration Group Register (CHn_GRPRI) */ + +/* eDMA3 only */ + +#define IMX9_EDMA_INT_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT) */ +#define IMX9_EDMA_HRS_OFFSET (0x00000c) /* Management Page Hardware Request Status Register (HRS) */ + +/* eDMA4 only */ + +#define IMX9_EDMA_INT_LOW_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT_LOW) */ +#define IMX9_EDMA_INT_HIGH_OFFSET (0x00000c) /* Management Page Interrupt Request Status Register (INT_HIGH) */ +#define IMX9_EDMA_HRS_LOW_OFFSET (0x000010) /* Management Page Hardware Request Status Register (HRS_LOW) */ +#define IMX9_EDMA_HRS_HIGH_OFFSET (0x000014) /* Management Page Hardware Request Status Register (HRS_HIGH) */ + +/* eDMA3 / eDMA4 Register Addresses */ + +#define IMX9_EDMA_CSR(n) ((n) + IMX9_EDMA_CSR_OFFSET) +#define IMX9_EDMA_ES(n) ((n) + IMX9_EDMA_ES_OFFSET) +#define IMX9_EDMA_CH_GRPRI(n,c) ((n) + IMX9_EDMA_CH_GRPRI_OFFSET(n)) + +/* eDMA3 only */ + +#define IMX9_EDMA_INT (IMX9_DMA3_BASE + IMX9_EDMA_INT_OFFSET) +#define IMX9_EDMA_HRS (IMX9_DMA3_BASE + IMX9_EDMA_HRS_OFFSET) + +/* eDMA4 only */ + +#define IMX9_EDMA_INT_LOW (IMX9_DMA4_BASE + IMX9_EDMA_INT_LOW_OFFSET) +#define IMX9_EDMA_INT_HIGH (IMX9_DMA4_BASE + IMX9_EDMA_INT_HIGH_OFFSET) +#define IMX9_EDMA_HRS_LOW (IMX9_DMA4_BASE + IMX9_EDMA_HRS_LOW_OFFSET) +#define IMX9_EDMA_HRS_HIGH (IMX9_DMA4_BASE + IMX9_EDMA_HRS_HIGH_OFFSET) + +/* eDMA Transfer Control Descriptor (TCD) Register Offsets */ + +#define IMX9_EDMA_CH_CSR_OFFSET (0x000000) /* Channel Control and Status Register (CH0_CSR) */ +#define IMX9_EDMA_CH_ES_OFFSET (0x000004) /* Channel Error Status Register (CH0_ES) */ +#define IMX9_EDMA_CH_INT_OFFSET (0x000008) /* Channel Interrupt Status Register (CH0_INT) */ +#define IMX9_EDMA_CH_SBR_OFFSET (0x00000c) /* Channel System Bus Register (CH0_SBR) */ +#define IMX9_EDMA_CH_PRI_OFFSET (0x000010) /* Channel Priority Register (CH0_PRI) */ +#define IMX9_EDMA_CH_MUX_OFFSET (0x000014) /* Channel Multiplexor Configuration (CH0_MUX) (eDMA4 only) */ +#define IMX9_EDMA_CH_MATTR_OFFSET (0x000018) /* Memory Attributes Register (CH0_MATTR) (eDMA4 only) */ +#define IMX9_EDMA_TCD_SADDR_OFFSET (0x000020) /* TCD Source Address Register (TCD0_SADDR) */ +#define IMX9_EDMA_TCD_SOFF_OFFSET (0x000024) /* TCD Signed Source Address Offset Register (TCD0_SOFF) */ +#define IMX9_EDMA_TCD_ATTR_OFFSET (0x000026) /* TCD Transfer Attributes (TCD0_ATTR) */ +#define IMX9_EDMA_TCD_NBYTES_OFFSET (0x000028) /* TCD Transfer Size (TCD0_NBYTES) */ +#define IMX9_EDMA_TCD_SLAST_SDA_OFFSET (0x00002c) /* TCD Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */ +#define IMX9_EDMA_TCD_DADDR_OFFSET (0x000030) /* TCD Destination Address Register (TCD0_DADDR) */ +#define IMX9_EDMA_TCD_DOFF_OFFSET (0x000034) /* TCD Signed Destination Address Offset Register (TCD0_DOFF) */ +#define IMX9_EDMA_TCD_CITER_OFFSET (0x000036) /* TCD Current Major Loop Count Register (TCD0_CITER) */ +#define IMX9_EDMA_TCD_DLAST_SGA_OFFSET (0x000038) /* TCD Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/ +#define IMX9_EDMA_TCD_CSR_OFFSET (0x00003c) /* TCD Control and Status Register (TCD0_CSR) */ +#define IMX9_EDMA_TCD_BITER_OFFSET (0x00003e) /* TCD Beginning Major Loop Count Register (TCD0_BITER) */ + +/* eDMA 3 and eDMA 4 have TCD instance offsets, but same base offset */ + +#define IMX9_EDMA_TCD_BASE_OFFSET (0x10000) /* Offset to TCD for both eDMA3/4 */ +#define IMX9_EDMA3_TCD_INST_OFFSET (0x10000) /* Per instance TCD offset for eDMA3 */ +#define IMX9_EDMA4_TCD_INST_OFFSET (0x8000) /* Per instance TCD offset for eDMA4 */ +#define IMX9_EDMA_TCD_BASE(n) ((n) + IMX9_EDMA_TCD_BASE_OFFSET) +#define IMX9_EDMA_TCD_INST_OFFSET(n) ((n) == IMX9_DMA3_BASE ? IMX9_EDMA3_TCD_INST_OFFSET : IMX9_EDMA4_TCD_INST_OFFSET) +#define IMX9_EDMA_TCD(n,t) (IMX9_EDMA_TCD_BASE(n) + (t) * IMX9_EDMA_TCD_INST_OFFSET(n)) + +/* eDMA Transfer Control Descriptor (TCD) Register Addresses ****************/ + +#define IMX9_EDMA_CH_CSR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_CSR_OFFSET) +#define IMX9_EDMA_CH_ES(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_ES_OFFSET) +#define IMX9_EDMA_CH_INT(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_INT_OFFSET) +#define IMX9_EDMA_CH_SBR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_SBR_OFFSET) +#define IMX9_EDMA_CH_PRI(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_PRI_OFFSET) +#define IMX9_EDMA_CH_MUX(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_MUX_OFFSET) +#define IMX9_EDMA_TCD_SADDR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_SADDR_OFFSET) +#define IMX9_EDMA_TCD_SOFF(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_SOFF_OFFSET) +#define IMX9_EDMA_TCD_ATTR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_ATTR_OFFSET) +#define IMX9_EDMA_TCD_NBYTES(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_NBYTES_OFFSET) +#define IMX9_EDMA_TCD_SLAST_SDA(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_SLAST_SDA_OFFSET) +#define IMX9_EDMA_TCD_DADDR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_DADDR_OFFSET) +#define IMX9_EDMA_TCD_DOFF(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_DOFF_OFFSET) +#define IMX9_EDMA_TCD_CITER(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_CITER_OFFSET) +#define IMX9_EDMA_TCD_DLAST_SGA(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_DLAST_SGA_OFFSET) +#define IMX9_EDMA_TCD_CSR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_CSR_OFFSET) +#define IMX9_EDMA_TCD_BITER(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_BITER_OFFSET) + +/* eDMA Register Bitfield Definitions ***************************************/ + +/* Management Page Control Register (CSR) */ + + /* Bit 0: Reserved */ +#define EDMA_CSR_EDBG (1 << 1) /* Bit 1: Enable Debug (EDBG) */ +#define EDMA_CSR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration (ERCA) */ + /* Bit 3: Reserved */ +#define EDMA_CSR_HAE (1 << 4) /* Bit 4: Halt After Error (HAE) */ +#define EDMA_CSR_HALT (1 << 5) /* Bit 5: Halt DMA Operations (HALT) */ +#define EDMA_CSR_GCLC (1 << 6) /* Bit 6: Global Channel Linking Control (GCLC) */ +#define EDMA_CSR_GMRC (1 << 7) /* Bit 7: Global Master ID Replication Control (GMRC) */ +#define EDMA_CSR_ECX (1 << 8) /* Bit 8: Cancel Transfer With Error (ECX) */ +#define EDMA_CSR_CX (1 << 9) /* Bit 9: Cancel Transfer (CX) */ + /* Bits 10-23: Reserved */ +#define EDMA_CSR_ACTIVE_ID_SHIFT (24) /* Bits 24-28: Active Channel ID (ACTIVE_ID) */ +#define EDMA_CSR_ACTIVE_ID_MASK (0x1f << EDMA_CSR_ACTIVE_ID_SHIFT) + /* Bits 29-30: Reserved */ +#define EDMA_CSR_ACTIVE (1 << 31) /* Bit 31: DMA Active Status (ACTIVE) */ + +/* Management Page Error Status Register (ES) */ + +#define EDMA_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */ +#define EDMA_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */ +#define EDMA_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */ +#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */ +#define EDMA_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */ +#define EDMA_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */ +#define EDMA_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */ +#define EDMA_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */ +#define EDMA_ES_ECX (1 << 8) /* Bit 8: Transfer Canceled (ECX) */ + /* Bits 9-23: Reserved */ +#define EDMA_ES_ERRCHN_SHIFT (24) /* Bits 24-28: Error Channel Number or Canceled Channel Number (ERRCHN) */ +#define EDMA_ES_ERRCHN_MASK (0x1f << EDMA_ES_ERRCHN_SHIFT) + /* Bits 29-30: Reserved */ +#define EDMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status fields (VALID) */ + +/* Management Page Interrupt Request Status Register (INT) */ + +#define EDMA_INT(n) (1 << (n)) /* Bit n: Interrupt Request Status (INT) */ + +/* Management Page Hardware Request Status Register (HRS) */ + +#define EDMA_HRS(n) (1 << (n)) /* Bit n: Hardware Request Status (HRS) */ + +/* Channel n Arbitration Group Register (CHn_GRPRI) */ + +#define EDMA_CH_GRPRI_SHIFT (0) /* Bits 0-4: Arbitration Group For Channel n (GRPRI) */ +#define EDMA_CH_GRPRI_MASK (0x1f << EDMA_CH_GRPRI_SHIFT) + /* Bits 5-31: Reserved */ + +/* eDMA Transfer Control Descriptor (TCD) Bitfield Definitions **************/ + +/* Channel n Control and Status Register (CHn_CSR) */ + +#define EDMA_CH_CSR_ERQ (1 << 0) /* Bit 0: Enable DMA Request (ERQ) */ +#define EDMA_CH_CSR_EARQ (1 << 1) /* Bit 1: Enable Asynchronous DMA Request in Stop Mode for Channel (EARQ) */ +#define EDMA_CH_CSR_EEI (1 << 2) /* Bit 2: Enable Error Interrupt (EEI) */ +#define EDMA_CH_CSR_EBW (1 << 3) /* Bit 3: Enable Buffered Writes (EBW) */ + /* Bit 4-29: Reserved */ +#define EDMA_CH_CSR_DONE (1 << 30) /* Bit 30: Channel Done (DONE) */ +#define EDMA_CH_CSR_ACTIVE (1 << 31) /* Bit 31: CHannel Active (ACTIVE) */ + +/* Channel n Error Status Register (CHn_ES) */ + +#define EDMA_CH_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */ +#define EDMA_CH_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */ +#define EDMA_CH_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */ +#define EDMA_CH_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */ +#define EDMA_CH_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */ +#define EDMA_CH_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */ +#define EDMA_CH_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */ +#define EDMA_CH_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */ + /* Bit 8-30: Reserved */ +#define EDMA_CH_ES_ERR (1 << 31) /* Bit 31: Error in this channel (ERR) */ + +/* Channel n Interrupt Status Register (CHn_INT) */ + +#define EDMA_CH_INT (1 << 0) /* Bit 0: Interrupt Request (INT) */ + /* Bits 1-31: Reserved */ + +/* Channel n System Bus Register (CHn_SBR) */ + +#define EDMA_CH_SBR_MID_SHIFT (0) /* Bits 0-3: Master ID (MID) */ +#define EDMA_CH_SBR_MID_MASK (0x0f << EDMA_CH_SBR_MID_SHIFT) + /* Bits 4-13: Reserved */ +#define EDMA_CH_SBR_SEC (1 << 14) /* Bit 14: Security Level (SEC) */ +#define EDMA_CH_SBR_PAL (1 << 15) /* Bit 15: Privileged Access Level (PAL) */ +#define EDMA_CH_SBR_EMI (1 << 16) /* Bit 16: Enable Master ID Replication (EMI) */ +#define EDMA_CH_SBR_ATTR_SHIFT (17) /* Bits 17-19: Attribute Output (ATTR) */ +#define EDMA_CH_SBR_ATTR_MASK (0x07 << EDMA_CH_SBR_ATTR_SHIFT) + /* Bits 20-31: Reserved */ + +/* Channel n Priority Register (CHn_PRI) */ + +#define EDMA_CH_PRI_APL_SHIFT (0) /* Bits 0-2: Arbitration Priority Level (APL) */ +#define EDMA_CH_PRI_APL_MASK (0x07 << EDMA_CH_PRI_APL_SHIFT) + /* Bits 3-29: Reserved */ +#define EDMA_CH_PRI_DPA (1 << 30) /* Bit 30: Disable Preempt Ability (DPA) */ +#define EDMA_CH_PRI_ECP (1 << 31) /* Bit 31: Enable Channel Preemption (ECP) */ + +/* Channel Multiplexor Configuration (CHn_MUX) */ + +#define EDMA_CH_SRC_SHIFT (0) /* Bits 0-6: Service Request Source */ +#define EDMA_CH_SRC_MASK (0x7f << EDMA_CH_SRC_SHIFT) + +/* TCDn Source Address Register (TCDn_SADDR) */ + +#define EDMA_TCD_SADDR_SHIFT (0) /* Bits 0-31: Source Address (SADDR) */ +#define EDMA_TCD_SADDR_MASK (0xffffffff << EDMA_TCD_SADDR_SHIFT) + +/* TCDn Signed Source Address Offset Register (TCDn_SOFF) */ + +#define EDMA_TCD_SOFF_SHIFT (0) /* Bits 0-31: Source Address Signed Offset (SOFF) */ +#define EDMA_TCD_SOFF_MASK (0xffffffff << EDMA_TCD_SOFF_SHIFT) + +/* TCDn Transfer Attributes (TCDn_ATTR) */ + +#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination Data Transfer Size (DSIZE) */ +#define EDMA_TCD_ATTR_DSIZE_MASK (0x07 << EDMA_TCD_ATTR_DSIZE_SHIFT) +#define EDMA_TCD_ATTR_DSIZE(n) (((n) << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK) +#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo (DMOD) */ +#define EDMA_TCD_ATTR_DMOD_MASK (0x1f << EDMA_TCD_ATTR_DMOD_SHIFT) +#define EDMA_TCD_ATTR_DMOD(n) (((n) << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK) +#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source Data Transfer Size (SSIZE) */ +#define EDMA_TCD_ATTR_SSIZE_MASK (0x07 << EDMA_TCD_ATTR_SSIZE_SHIFT) +#define EDMA_TCD_ATTR_SSIZE(n) (((n) << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK) +# define EDMA_TCD_ATTR_SSIZE_8BIT (0x00 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */ +# define EDMA_TCD_ATTR_SSIZE_16BIT (0x01 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */ +# define EDMA_TCD_ATTR_SSIZE_32BIT (0x02 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */ +# define EDMA_TCD_ATTR_SSIZE_64BIT (0x03 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */ +# define EDMA_TCD_ATTR_SSIZE_16BYTE (0x04 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-byte */ +# define EDMA_TCD_ATTR_SSIZE_32BYTE (0x05 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte */ +# define EDMA_TCD_ATTR_SSIZE_64BYTE (0x06 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-byte */ + +#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo (SMOD) */ +#define EDMA_TCD_ATTR_SMOD_MASK (0x1f << EDMA_TCD_ATTR_SMOD_SHIFT) +#define EDMA_TCD_ATTR_SMOD(n) (((n) << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK) + +/* TCDn Transfer Size (TCDn_NBYTES) */ + +#define EDMA_TCD_NBYTES_SHIFT (0) /* Bits 0-29: Number of Bytes to Transfer per Service Request (NBYTES) */ +#define EDMA_TCD_NBYTES_MASK (0x3fffffff << EDMA_TCD_NBYTES_SHIFT) +#define EDMA_TCD_NBYTES_MASK_MLOFF (0x03ff << EDMA_TCD_NBYTES_SHIFT) +#define EDMA_TCD_NBYTES_MLOFF_SHIFT (10) /* Bits 10-29: Minor Loop Offset (MLOFF) */ +#define EDMA_TCD_NBYTES_MLOFF_MASK (0x0fffff << EDMA_TCD_NBYTES_MLOFF_SHIFT) +#define EDMA_TCD_NBYTES_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset Enable (DMLOE) */ +#define EDMA_TCD_NBYTES_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable (SMLOE) */ + +/* TCDn Last Source Address Adjustment / Store DADDR Address Register + * (TCDn_SLAST_SDA) + */ + +#define EDMA_TCD_SLAST_SDA_SHIFT (0) /* Bits 0-31: Last Source Address Adjustment / Store DADDR Address (SLAST_SDA) */ +#define EDMA_TCD_SLAST_SDA_MASK (0xffffffff << EDMA_TCD_SLAST_SDA_SHIFT) + +/* TCDn Destination Address Register (TCDn_DADDR) */ + +#define EDMA_TCD_DADDR_SHIFT (0) /* Bits 0-31: Destination Address (DADDR) */ +#define EDMA_TCD_DADDR_MASK (0xffffffff << EDMA_TCD_DADDR_SHIFT) + +/* TCDn Signed Destination Address Offset Register (TCDn_DOFF) */ + +#define EDMA_TCD_DOFF_SHIFT (0) /* Bits 0-15: Destination Address Signed Offset (DOFF) */ +#define EDMA_TCD_DOFF_MASK (0xffff << EDMA_TCD_DOFF_SHIFT) + +/* TCDn Current Major Loop Count Register (TCDn_CITER) */ + +#define EDMA_TCD_CITER_SHIFT (0) /* Bits 0-14: Current Major Iteration Count (CITER) */ +#define EDMA_TCD_CITER_MASK (0x7fff << EDMA_TCD_CITER_SHIFT) +#define EDMA_TCD_CITER_MASK_ELINK (0x01ff << EDMA_TCD_CITER_SHIFT) +#define EDMA_TCD_CITER_LINKCH_SHIFT (9) /* Bits 9-13: Minor Loop Link Channel Number (LINKCH) */ +#define EDMA_TCD_CITER_LINKCH_MASK (0x1f << EDMA_TCD_CITER_LINKCH_SHIFT) +#define EDMA_TCD_CITER_LINKCH(n) (((n) << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT) +#define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */ + +/* TCDn Last Destination Address Adjustment / Scatter Gather Address Register + * (TCDn_DLAST_SGA) + */ + +#define EDMA_TCD_DLAST_SGA_SHIFT (0) /* Bits 0-31: Last Destination Address Adjustment / Scatter Gather Address (DLAST_SGA) */ +#define EDMA_TCD_DLAST_SGA_MASK (0xffffffff << EDMA_TCD_DLAST_SGA_SHIFT) + +/* TCDn Control and Status Register (TCDn_CSR) */ + +#define EDMA_TCD_CSR_START (1 << 0) /* Bit 0: Channel Start (START) */ +#define EDMA_TCD_CSR_INTMAJOR (1 << 1) /* Bit 1: Enable Interrupt if Major count complete (INTMAJOR) */ +#define EDMA_TCD_CSR_INTHALF (1 << 2) /* Bit 2: Enable Interrupt if Major Count Half-complete (INTHALF) */ +#define EDMA_TCD_CSR_DREQ (1 << 3) /* Bit 3: Disable Request (DREQ) */ +#define EDMA_TCD_CSR_ESG (1 << 4) /* Bit 4: Enable Scatter/Gather Processing (ESG) */ +#define EDMA_TCD_CSR_MAJORELINK (1 << 5) /* Bit 5: Enable Link When Major Loop Complete (MAJORELINK) */ +#define EDMA_TCD_CSR_EEOP (1 << 6) /* Bit 6: Enable End-Of-Packet Processing (EEOP) */ +#define EDMA_TCD_CSR_ESDA (1 << 7) /* Bit 7: Enable Store Destination Address (ESDA) */ +#define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-12: Major Loop Link Channel Number (MAJORLINKCH) */ +#define EDMA_TCD_CSR_MAJORLINKCH_MASK (0x1f << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) +#define EDMA_TCD_CSR_MAJORLINKCH(n) (((n) << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) & EDMA_TCD_CSR_MAJORLINKCH_MASK) + /* Bit 13: Reserved */ +#define EDMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth Control (BWC) */ +#define EDMA_TCD_CSR_BWC_MASK (0x03 << EDMA_TCD_CSR_BWC_SHIFT) +# define EDMA_TCD_CSR_BWC_NOSTALL (0x00 << EDMA_TCD_CSR_BWC_SHIFT) /* No eDMA engine stalls */ +# define EDMA_TCD_CSR_BWC_HPE (0x01 << EDMA_TCD_CSR_BWC_SHIFT) /* Enable eDMA master high-priority elevation (HPE) mode */ +# define EDMA_TCD_CSR_BWC_4CYCLES (0x02 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 4 cycles after each R/W */ +# define EDMA_TCD_CSR_BWC_8CYCLES (0x03 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 8 cycles after each R/W */ + +/* TCDn Beginning Major Loop Count Register (TCDn_BITER) */ + +#define EDMA_TCD_BITER_SHIFT (0) /* Bits 0-14: Starting Major Iteration Count (BITER) */ +#define EDMA_TCD_BITER_MASK (0x7fff << EDMA_TCD_BITER_SHIFT) +#define EDMA_TCD_BITER_MASK_ELINK (0x01ff << EDMA_TCD_BITER_SHIFT) +#define EDMA_TCD_BITER_LINKCH_SHIFT (9) /* Bits 9-13: Link Channel Number (LINKCH) */ +#define EDMA_TCD_BITER_LINKCH_MASK (0x1f << EDMA_TCD_BITER_LINKCH_SHIFT) +#define EDMA_TCD_BITER_LINKCH(n) (((n) << EDMA_TCD_BITER_LINKCH_SHIFT) & EDMA_TCD_BITER_LINKCH_MASK) +#define EDMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */ + +/* Amount of channels */ + +#define DMA3_CHANNEL_COUNT (31) +#define DMA4_CHANNEL_COUNT (64) +#define IMX9_EDMA_NCHANNELS (DMA3_CHANNEL_COUNT + DMA4_CHANNEL_COUNT) + +/* Amount of interrupt sources */ + +#define DMA3_IRQ_COUNT (32) /* Error interrupt not counted */ +#define DMA4_IRQ_COUNT (32) /* Error interrupt not counted */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* In-memory representation of the 32-byte Transfer Control Descriptor + * (TCD) + */ + +struct imx9_edmatcd_s +{ + uint32_t saddr; /* Offset: 0x0000 TCD Source Address */ + uint16_t soff; /* Offset: 0x0004 TCD Signed Source Address Offset */ + uint16_t attr; /* Offset: 0x0006 TCD Transfer Attributes */ + uint32_t nbytes; /* Offset: 0x0008 TCD Signed Minor Loop Offset / Byte Count */ + uint32_t slast; /* Offset: 0x000c TCD Last Source Address Adjustment */ + uint32_t daddr; /* Offset: 0x0010 TCD Destination Address */ + uint16_t doff; /* Offset: 0x0014 TCD Signed Destination Address Offset */ + uint16_t citer; /* Offset: 0x0016 TCD Current Minor Loop Link, Major Loop Count */ + uint32_t dlastsga; /* Offset: 0x0018 TCD Last Destination Address Adjustment/Scatter Gather Address */ + uint16_t csr; /* Offset: 0x001c TCD Control and Status */ + uint16_t biter; /* Offset: 0x001e TCD Beginning Minor Loop Link, Major Loop Count */ +}; + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_edma_tcdhasmux + * + * Description: + * Check if DMA TCD has TCD.MUX register. + * + * Input Parameters: + * dmabase - The eDMA base. + * + * Returned Value: + * true if TCD.MUX exists; false if not. + * + ****************************************************************************/ + +static inline bool imx9_edma_tcdhasmux(uintptr_t dmabase) +{ + /* Only eDMA4 has TCD.MUX register */ + + return dmabase == IMX9_DMA4_BASE ? true : false; +} + +/**************************************************************************** + * Name: imx9_edma_choffset + * + * Description: + * Channel offset in global channel list for dma base. + * + * Input Parameters: + * base - The eDMA base. + * + * Returned Value: + * Channel offset. + * + ****************************************************************************/ + +static inline uint32_t imx9_edma_choffset(uintptr_t base) +{ + return base == IMX9_DMA3_BASE ? 0 : DMA3_CHANNEL_COUNT; +} + +/**************************************************************************** + * Name: imx9_edma_chmax + * + * Description: + * Max channel in global channel list for dma base. + * + * Input Parameters: + * base - The eDMA base. + * + * Returned Value: + * Channel max. + * + ****************************************************************************/ + +static inline uint32_t imx9_edma_chmax(uintptr_t base) +{ + return base == IMX9_DMA3_BASE ? DMA3_CHANNEL_COUNT : IMX9_EDMA_NCHANNELS; +} + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_EDMA_H */ diff --git a/arch/arm/src/imx9/hardware/imx93/imx93_gpio.h b/arch/arm/src/imx9/hardware/imx93/imx93_gpio.h new file mode 100644 index 00000000000..0057288bb77 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx93/imx93_gpio.h @@ -0,0 +1,61 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx93/imx93_gpio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_GPIO_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "imx93_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IMX9_GPIO_VERID_OFFSET (0x0000) /* Version ID */ +#define IMX9_GPIO_PARAM_OFFSET (0x0004) /* Parameter */ +#define IMX9_GPIO_LOCK_OFFSET (0x000c) /* Lock */ +#define IMX9_GPIO_PCNS_OFFSET (0x0010) /* Pin Control Nonsecure */ +#define IMX9_GPIO_ICNS_OFFSET (0x0014) /* Interrupt Control Nonsecure */ +#define IMX9_GPIO_PCNP_OFFSET (0x0018) /* Pin Control Nonprivilege */ +#define IMX9_GPIO_ICNP_OFFSET (0x001c) /* Interrupt Control Nonprivilege */ +#define IMX9_GPIO_PDOR_OFFSET (0x0040) /* Port Data Output */ +#define IMX9_GPIO_PSOR_OFFSET (0x0044) /* Port Set Output */ +#define IMX9_GPIO_PCOR_OFFSET (0x0048) /* Port Clear Output */ +#define IMX9_GPIO_PTOR_OFFSET (0x004c) /* Port Toggle Output */ +#define IMX9_GPIO_PDIR_OFFSET (0x0050) /* Port Data Input */ +#define IMX9_GPIO_PDDR_OFFSET (0x0054) /* Port Data Direction */ +#define IMX9_GPIO_PIDR_OFFSET (0x0058) /* Port Input Disable */ +#define IMX9_GPIO_P0DR_OFFSET (0x0060) /* Pin Data (0-31 at offsets of n * 4h) */ +#define IMX9_GPIO_ICR0_OFFSET (0x0080) /* Interrupt Control (0-31 at offsets of n * 4h) */ +#define IMX9_GPIO_GICLR_OFFSET (0x0100) /* Global Interrupt Control Low */ +#define IMX9_GPIO_GICHR_OFFSET (0x0104) /* Global Interrupt Control High */ +#define IMX9_GPIO_ISFR0_OFFSET (0x0120) /* Interrupt Status Flag */ +#define IMX9_GPIO_ISFR1_OFFSET (0x0124) /* Interrupt Status Flag */ + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_GPIO_H */ diff --git a/arch/arm/src/imx9/hardware/imx93/imx93_iomux.h b/arch/arm/src/imx9/hardware/imx93/imx93_iomux.h new file mode 100644 index 00000000000..c0a1d950e64 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx93/imx93_iomux.h @@ -0,0 +1,608 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx93/imx93_iomux.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_IOMUX_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_IOMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets */ + +#define IOMUXC_MUX_CTL_DAP_TDI_OFFSET (0x0000) +#define IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET (0x0004) +#define IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET (0x0008) +#define IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET (0x000C) +#define IOMUXC_MUX_CTL_GPIO_IO00_OFFSET (0x0010) +#define IOMUXC_MUX_CTL_GPIO_IO01_OFFSET (0x0014) +#define IOMUXC_MUX_CTL_GPIO_IO02_OFFSET (0x0018) +#define IOMUXC_MUX_CTL_GPIO_IO03_OFFSET (0x001C) +#define IOMUXC_MUX_CTL_GPIO_IO04_OFFSET (0x0020) +#define IOMUXC_MUX_CTL_GPIO_IO05_OFFSET (0x0024) +#define IOMUXC_MUX_CTL_GPIO_IO06_OFFSET (0x0028) +#define IOMUXC_MUX_CTL_GPIO_IO07_OFFSET (0x002C) +#define IOMUXC_MUX_CTL_GPIO_IO08_OFFSET (0x0030) +#define IOMUXC_MUX_CTL_GPIO_IO09_OFFSET (0x0034) +#define IOMUXC_MUX_CTL_GPIO_IO10_OFFSET (0x0038) +#define IOMUXC_MUX_CTL_GPIO_IO11_OFFSET (0x003C) +#define IOMUXC_MUX_CTL_GPIO_IO12_OFFSET (0x0040) +#define IOMUXC_MUX_CTL_GPIO_IO13_OFFSET (0x0044) +#define IOMUXC_MUX_CTL_GPIO_IO14_OFFSET (0x0048) +#define IOMUXC_MUX_CTL_GPIO_IO15_OFFSET (0x004C) +#define IOMUXC_MUX_CTL_GPIO_IO16_OFFSET (0x0050) +#define IOMUXC_MUX_CTL_GPIO_IO17_OFFSET (0x0054) +#define IOMUXC_MUX_CTL_GPIO_IO18_OFFSET (0x0058) +#define IOMUXC_MUX_CTL_GPIO_IO19_OFFSET (0x005C) +#define IOMUXC_MUX_CTL_GPIO_IO20_OFFSET (0x0060) +#define IOMUXC_MUX_CTL_GPIO_IO21_OFFSET (0x0064) +#define IOMUXC_MUX_CTL_GPIO_IO22_OFFSET (0x0068) +#define IOMUXC_MUX_CTL_GPIO_IO23_OFFSET (0x006C) +#define IOMUXC_MUX_CTL_GPIO_IO24_OFFSET (0x0070) +#define IOMUXC_MUX_CTL_GPIO_IO25_OFFSET (0x0074) +#define IOMUXC_MUX_CTL_GPIO_IO26_OFFSET (0x0078) +#define IOMUXC_MUX_CTL_GPIO_IO27_OFFSET (0x007C) +#define IOMUXC_MUX_CTL_GPIO_IO28_OFFSET (0x0080) +#define IOMUXC_MUX_CTL_GPIO_IO29_OFFSET (0x0084) +#define IOMUXC_MUX_CTL_CCM_CLKO1_OFFSET (0x0088) +#define IOMUXC_MUX_CTL_CCM_CLKO2_OFFSET (0x008C) +#define IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET (0x0090) +#define IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET (0x0094) +#define IOMUXC_MUX_CTL_ENET1_MDC_OFFSET (0x0098) +#define IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET (0x009C) +#define IOMUXC_MUX_CTL_ENET1_TD3_OFFSET (0x00A0) +#define IOMUXC_MUX_CTL_ENET1_TD2_OFFSET (0x00A4) +#define IOMUXC_MUX_CTL_ENET1_TD1_OFFSET (0x00A8) +#define IOMUXC_MUX_CTL_ENET1_TD0_OFFSET (0x00AC) +#define IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET (0x00B0) +#define IOMUXC_MUX_CTL_ENET1_TXC_OFFSET (0x00B4) +#define IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET (0x00B8) +#define IOMUXC_MUX_CTL_ENET1_RXC_OFFSET (0x00BC) +#define IOMUXC_MUX_CTL_ENET1_RD0_OFFSET (0x00C0) +#define IOMUXC_MUX_CTL_ENET1_RD1_OFFSET (0x00C4) +#define IOMUXC_MUX_CTL_ENET1_RD2_OFFSET (0x00C8) +#define IOMUXC_MUX_CTL_ENET1_RD3_OFFSET (0x00CC) +#define IOMUXC_MUX_CTL_ENET2_MDC_OFFSET (0x00D0) +#define IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET (0x00D4) +#define IOMUXC_MUX_CTL_ENET2_TD3_OFFSET (0x00D8) +#define IOMUXC_MUX_CTL_ENET2_TD2_OFFSET (0x00DC) +#define IOMUXC_MUX_CTL_ENET2_TD1_OFFSET (0x00E0) +#define IOMUXC_MUX_CTL_ENET2_TD0_OFFSET (0x00E4) +#define IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET (0x00E8) +#define IOMUXC_MUX_CTL_ENET2_TXC_OFFSET (0x00EC) +#define IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET (0x00F0) +#define IOMUXC_MUX_CTL_ENET2_RXC_OFFSET (0x00F4) +#define IOMUXC_MUX_CTL_ENET2_RD0_OFFSET (0x00F8) +#define IOMUXC_MUX_CTL_ENET2_RD1_OFFSET (0x00FC) +#define IOMUXC_MUX_CTL_ENET2_RD2_OFFSET (0x0100) +#define IOMUXC_MUX_CTL_ENET2_RD3_OFFSET (0x0104) +#define IOMUXC_MUX_CTL_SD1_CLK_OFFSET (0x0108) +#define IOMUXC_MUX_CTL_SD1_CMD_OFFSET (0x010C) +#define IOMUXC_MUX_CTL_SD1_DATA0_OFFSET (0x0110) +#define IOMUXC_MUX_CTL_SD1_DATA1_OFFSET (0x0114) +#define IOMUXC_MUX_CTL_SD1_DATA2_OFFSET (0x0118) +#define IOMUXC_MUX_CTL_SD1_DATA3_OFFSET (0x011C) +#define IOMUXC_MUX_CTL_SD1_DATA4_OFFSET (0x0120) +#define IOMUXC_MUX_CTL_SD1_DATA5_OFFSET (0x0124) +#define IOMUXC_MUX_CTL_SD1_DATA6_OFFSET (0x0128) +#define IOMUXC_MUX_CTL_SD1_DATA7_OFFSET (0x012C) +#define IOMUXC_MUX_CTL_SD1_STROBE_OFFSET (0x0130) +#define IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET (0x0134) +#define IOMUXC_MUX_CTL_SD3_CLK_OFFSET (0x0138) +#define IOMUXC_MUX_CTL_SD3_CMD_OFFSET (0x013C) +#define IOMUXC_MUX_CTL_SD3_DATA0_OFFSET (0x0140) +#define IOMUXC_MUX_CTL_SD3_DATA1_OFFSET (0x0144) +#define IOMUXC_MUX_CTL_SD3_DATA2_OFFSET (0x0148) +#define IOMUXC_MUX_CTL_SD3_DATA3_OFFSET (0x014C) +#define IOMUXC_MUX_CTL_SD2_CD_B_OFFSET (0x0150) +#define IOMUXC_MUX_CTL_SD2_CLK_OFFSET (0x0154) +#define IOMUXC_MUX_CTL_SD2_CMD_OFFSET (0x0158) +#define IOMUXC_MUX_CTL_SD2_DATA0_OFFSET (0x015C) +#define IOMUXC_MUX_CTL_SD2_DATA1_OFFSET (0x0160) +#define IOMUXC_MUX_CTL_SD2_DATA2_OFFSET (0x0164) +#define IOMUXC_MUX_CTL_SD2_DATA3_OFFSET (0x0168) +#define IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET (0x016C) +#define IOMUXC_MUX_CTL_I2C1_SCL_OFFSET (0x0170) +#define IOMUXC_MUX_CTL_I2C1_SDA_OFFSET (0x0174) +#define IOMUXC_MUX_CTL_I2C2_SCL_OFFSET (0x0178) +#define IOMUXC_MUX_CTL_I2C2_SDA_OFFSET (0x017C) +#define IOMUXC_MUX_CTL_UART1_RXD_OFFSET (0x0180) +#define IOMUXC_MUX_CTL_UART1_TXD_OFFSET (0x0184) +#define IOMUXC_MUX_CTL_UART2_RXD_OFFSET (0x0188) +#define IOMUXC_MUX_CTL_UART2_TXD_OFFSET (0x018C) +#define IOMUXC_MUX_CTL_PDM_CLK_OFFSET (0x0190) +#define IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET (0x0194) +#define IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET (0x0198) +#define IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET (0x019C) +#define IOMUXC_MUX_CTL_SAI1_TXC_OFFSET (0x01A0) +#define IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET (0x01A4) +#define IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET (0x01A8) +#define IOMUXC_MUX_CTL_WDOG_ANY_OFFSET (0x01AC) + +#define IOMUXC_MUX_CTL_GPIO_LASTIO_OFFSET (IOMUXC_MUX_CTL_GPIO_IO29_OFFSET) + +#define IOMUXC_PAD_CTL_DAP_TDI_OFFSET (0x01B0) +#define IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET (0x01B4) +#define IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET (0x01B8) +#define IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET (0x01BC) +#define IOMUXC_PAD_CTL_GPIO_IO00_OFFSET (0x01C0) +#define IOMUXC_PAD_CTL_GPIO_IO01_OFFSET (0x01C4) +#define IOMUXC_PAD_CTL_GPIO_IO02_OFFSET (0x01C8) +#define IOMUXC_PAD_CTL_GPIO_IO03_OFFSET (0x01CC) +#define IOMUXC_PAD_CTL_GPIO_IO04_OFFSET (0x01D0) +#define IOMUXC_PAD_CTL_GPIO_IO05_OFFSET (0x01D4) +#define IOMUXC_PAD_CTL_GPIO_IO06_OFFSET (0x01D8) +#define IOMUXC_PAD_CTL_GPIO_IO07_OFFSET (0x01DC) +#define IOMUXC_PAD_CTL_GPIO_IO08_OFFSET (0x01E0) +#define IOMUXC_PAD_CTL_GPIO_IO09_OFFSET (0x01E4) +#define IOMUXC_PAD_CTL_GPIO_IO10_OFFSET (0x01E8) +#define IOMUXC_PAD_CTL_GPIO_IO11_OFFSET (0x01EC) +#define IOMUXC_PAD_CTL_GPIO_IO12_OFFSET (0x01F0) +#define IOMUXC_PAD_CTL_GPIO_IO13_OFFSET (0x01F4) +#define IOMUXC_PAD_CTL_GPIO_IO14_OFFSET (0x01F8) +#define IOMUXC_PAD_CTL_GPIO_IO15_OFFSET (0x01FC) +#define IOMUXC_PAD_CTL_GPIO_IO16_OFFSET (0x0200) +#define IOMUXC_PAD_CTL_GPIO_IO17_OFFSET (0x0204) +#define IOMUXC_PAD_CTL_GPIO_IO18_OFFSET (0x0208) +#define IOMUXC_PAD_CTL_GPIO_IO19_OFFSET (0x020C) +#define IOMUXC_PAD_CTL_GPIO_IO20_OFFSET (0x0210) +#define IOMUXC_PAD_CTL_GPIO_IO21_OFFSET (0x0214) +#define IOMUXC_PAD_CTL_GPIO_IO22_OFFSET (0x0218) +#define IOMUXC_PAD_CTL_GPIO_IO23_OFFSET (0x021C) +#define IOMUXC_PAD_CTL_GPIO_IO24_OFFSET (0x0220) +#define IOMUXC_PAD_CTL_GPIO_IO25_OFFSET (0x0224) +#define IOMUXC_PAD_CTL_GPIO_IO26_OFFSET (0x0228) +#define IOMUXC_PAD_CTL_GPIO_IO27_OFFSET (0x022C) +#define IOMUXC_PAD_CTL_GPIO_IO28_OFFSET (0x0230) +#define IOMUXC_PAD_CTL_GPIO_IO29_OFFSET (0x0234) +#define IOMUXC_PAD_CTL_CCM_CLKO1_OFFSET (0x0238) +#define IOMUXC_PAD_CTL_CCM_CLKO2_OFFSET (0x023C) +#define IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET (0x0240) +#define IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET (0x0244) +#define IOMUXC_PAD_CTL_ENET1_MDC_OFFSET (0x0248) +#define IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET (0x024C) +#define IOMUXC_PAD_CTL_ENET1_TD3_OFFSET (0x0250) +#define IOMUXC_PAD_CTL_ENET1_TD2_OFFSET (0x0254) +#define IOMUXC_PAD_CTL_ENET1_TD1_OFFSET (0x0258) +#define IOMUXC_PAD_CTL_ENET1_TD0_OFFSET (0x025C) +#define IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET (0x0260) +#define IOMUXC_PAD_CTL_ENET1_TXC_OFFSET (0x0264) +#define IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET (0x0268) +#define IOMUXC_PAD_CTL_ENET1_RXC_OFFSET (0x026C) +#define IOMUXC_PAD_CTL_ENET1_RD0_OFFSET (0x0270) +#define IOMUXC_PAD_CTL_ENET1_RD1_OFFSET (0x0274) +#define IOMUXC_PAD_CTL_ENET1_RD2_OFFSET (0x0278) +#define IOMUXC_PAD_CTL_ENET1_RD3_OFFSET (0x027C) +#define IOMUXC_PAD_CTL_ENET2_MDC_OFFSET (0x0280) +#define IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET (0x0284) +#define IOMUXC_PAD_CTL_ENET2_TD3_OFFSET (0x0288) +#define IOMUXC_PAD_CTL_ENET2_TD2_OFFSET (0x028C) +#define IOMUXC_PAD_CTL_ENET2_TD1_OFFSET (0x01B0) +#define IOMUXC_PAD_CTL_ENET2_TD0_OFFSET (0x01B0) +#define IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET (0x01B0) +#define IOMUXC_PAD_CTL_ENET2_TXC_OFFSET (0x029C) +#define IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET (0x02A0) +#define IOMUXC_PAD_CTL_ENET2_RXC_OFFSET (0x02A4) +#define IOMUXC_PAD_CTL_ENET2_RD0_OFFSET (0x02A8) +#define IOMUXC_PAD_CTL_ENET2_RD1_OFFSET (0x02AC) +#define IOMUXC_PAD_CTL_ENET2_RD2_OFFSET (0x02B0) +#define IOMUXC_PAD_CTL_ENET2_RD3_OFFSET (0x02B4) +#define IOMUXC_PAD_CTL_SD1_CLK_OFFSET (0x02B8) +#define IOMUXC_PAD_CTL_SD1_CMD_OFFSET (0x02BC) +#define IOMUXC_PAD_CTL_SD1_DATA0_OFFSET (0x02C0) +#define IOMUXC_PAD_CTL_SD1_DATA1_OFFSET (0x02C4) +#define IOMUXC_PAD_CTL_SD1_DATA2_OFFSET (0x02C8) +#define IOMUXC_PAD_CTL_SD1_DATA3_OFFSET (0x02CC) +#define IOMUXC_PAD_CTL_SD1_DATA4_OFFSET (0x02D0) +#define IOMUXC_PAD_CTL_SD1_DATA5_OFFSET (0x02D4) +#define IOMUXC_PAD_CTL_SD1_DATA6_OFFSET (0x02D8) +#define IOMUXC_PAD_CTL_SD1_DATA7_OFFSET (0x02DC) +#define IOMUXC_PAD_CTL_SD1_STROBE_OFFSET (0x02E0) +#define IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET (0x02E4) +#define IOMUXC_PAD_CTL_SD3_CLK_OFFSET (0x02E8) +#define IOMUXC_PAD_CTL_SD3_CMD_OFFSET (0x02EC) +#define IOMUXC_PAD_CTL_SD3_DATA0_OFFSET (0x02F0) +#define IOMUXC_PAD_CTL_SD3_DATA1_OFFSET (0x02F4) +#define IOMUXC_PAD_CTL_SD3_DATA2_OFFSET (0x02F8) +#define IOMUXC_PAD_CTL_SD3_DATA3_OFFSET (0x02FC) +#define IOMUXC_PAD_CTL_SD2_CD_B_OFFSET (0x0300) +#define IOMUXC_PAD_CTL_SD2_CLK_OFFSET (0x0304) +#define IOMUXC_PAD_CTL_SD2_CMD_OFFSET (0x0308) +#define IOMUXC_PAD_CTL_SD2_DATA0_OFFSET (0x030C) +#define IOMUXC_PAD_CTL_SD2_DATA1_OFFSET (0x0310) +#define IOMUXC_PAD_CTL_SD2_DATA2_OFFSET (0x0314) +#define IOMUXC_PAD_CTL_SD2_DATA3_OFFSET (0x0318) +#define IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET (0x031C) +#define IOMUXC_PAD_CTL_I2C1_SCL_OFFSET (0x0320) +#define IOMUXC_PAD_CTL_I2C1_SDA_OFFSET (0x0324) +#define IOMUXC_PAD_CTL_I2C2_SCL_OFFSET (0x0328) +#define IOMUXC_PAD_CTL_I2C2_SDA_OFFSET (0x032C) +#define IOMUXC_PAD_CTL_UART1_RXD_OFFSET (0x0330) +#define IOMUXC_PAD_CTL_UART1_TXD_OFFSET (0x0334) +#define IOMUXC_PAD_CTL_UART2_RXD_OFFSET (0x0338) +#define IOMUXC_PAD_CTL_UART2_TXD_OFFSET (0x033C) +#define IOMUXC_PAD_CTL_PDM_CLK_OFFSET (0x0340) +#define IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET (0x0344) +#define IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET (0x0348) +#define IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET (0x034C) +#define IOMUXC_PAD_CTL_SAI1_TXC_OFFSET (0x0350) +#define IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET (0x0354) +#define IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET (0x0358) +#define IOMUXC_PAD_CTL_WDOG_ANY_OFFSET (0x035C) + +#define CAN1_IPP_IND_CANRX_SELECT_INPUT_OFFSET (0x0360) +#define CAN2_IPP_IND_CANRX_SELECT_INPUT_OFFSET (0x0364) +#define CCMSRCGPCMIX_EXT1_CLK_SELECT_INPUT_OFFSET (0x0368) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_0_OFFSET (0x036C) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_1_OFFSET (0x0370) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_2_OFFSET (0x0374) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_3_OFFSET (0x0378) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_4_OFFSET (0x037C) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_5_OFFSET (0x0380) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_6_OFFSET (0x0384) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_7_OFFSET (0x0388) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_8_OFFSET (0x038C) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_9_OFFSET (0x0390) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_10_OFFSET (0x0394) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_11_OFFSET (0x0398) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_13_OFFSET (0x039C) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_14_OFFSET (0x03A0) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_15_OFFSET (0x03A4) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_16_OFFSET (0x03A8) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_17_OFFSET (0x03AC) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_18_OFFSET (0x03B0) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_20_OFFSET (0x03B4) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_22_OFFSET (0x03B8) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_23_OFFSET (0x03BC) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_24_OFFSET (0x03C0) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_25_OFFSET (0x03C4) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_27_OFFSET (0x03C8) +#define I3C2_PIN_SCL_IN_SELECT_INPUT_OFFSET (0x03CC) +#define I3C2_PIN_SDA_IN_SELECT_INPUT_OFFSET (0x03D0) +#define JTAG_MUX_TCK_SELECT_INPUT_OFFSET (0x03D4) +#define JTAG_MUX_TDI_SELECT_INPUT_OFFSET (0x03D8) +#define JTAG_MUX_TMS_SELECT_INPUT_OFFSET (0x03DC) +#define LP12C3_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x03E0) +#define LPI12C3_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x03E4) +#define LP12C5_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x03E8) +#define LP12C5_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x03EC) +#define LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x03F0) +#define LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x03F4) +#define LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x03F8) +#define LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x03FC) +#define LPI2C8_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x0400) +#define LPI2C8_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x0404) +#define LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_O_OFFSET (0x0408) +#define LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_1_OFFSET (0x040C) +#define LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_2_OFFSET (0x0410) +#define LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INP_OFFSET (0x0414) +#define LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET (0x0418) +#define LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET (0x041C) +#define LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INP_OFFSET (0x0420) +#define LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET (0x0424) +#define LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET (0x0428) +#define LPUARTS_IPP_IND_LPUART_CTS_N_SELECT_INP_OFFSET (0x042C) +#define LPUARTS_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET (0x0430) +#define LPUARTS_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET (0x0434) +#define SAI1_IPP_IND_SAI_MCLK_SELECT_INPUT_OFFSET (0x0448) +#define SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET (0x044c) +#define SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET (0x0450) +#define SPDIF_SPDIF_I_SELECT_INPUT_OFFSET (0x0454) +#define USDHC3_IPP_CARD_CLK_IN_SELECT_INPUT_OFFSET (0x0458) +#define USDHC3_IPP_CMD_IN_SELECT_INPUT_OFFSET (0x045C) +#define USDHC3_IPP_DATO_IN_SELECT_INPUT_OFFSET (0x0460) +#define USDHC3_IPP_DAT1_IN_SELECT_INPUT_OFFSET (0x0464) +#define USDHC3_IPP_DAT2_IN_SELECT_INPUT_OFFSET (0x0468) +#define USDHC3_IPP_DAT3_IN_SELECT_INPUT_OFFSET (0x046C) + +/* Register addresses */ + +#define IOMUXC_MUX_CTL_DAP_TDI (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TDI_OFFSET) +#define IOMUXC_MUX_CTL_DAP_TMS_SWDIO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET) +#define IOMUXC_MUX_CTL_DAP_TCLK_SWCLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET) +#define IOMUXC_MUX_CTL_DAP_TDO_TRACESWO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO00 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO00_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO01 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO01_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO02 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO02_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO03 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO03_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO04 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO04_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO05 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO05_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO06 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO06_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO07 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO07_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO08 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO08_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO09 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO09_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO10 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO10_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO11 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO11_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO12 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO12_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO13 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO13_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO14 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO14_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO15 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO15_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO16 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO16_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO17 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO17_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO18 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO18_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO19 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO19_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO20 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO20_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO21 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO21_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO22 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO22_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO23 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO23_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO24 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO24_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO25 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO25_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO26 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO26_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO27 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO27_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO28 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO28_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO29 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO29_OFFSET) +#define IOMUXC_MUX_CTL_CCM_CLKO1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO1_OFFSET) +#define IOMUXC_MUX_CTL_CCM_CLKO2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO2_OFFSET) +#define IOMUXC_MUX_CTL_CCM_CLKO3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET) +#define IOMUXC_MUX_CTL_CCM_CLKO4 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_MDC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_MDC_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD3_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD2_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD1_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD0_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TXC_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RXC_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD0_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD1_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD2_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD3_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_MDC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_MDC_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD3_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD2_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD1_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD0_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TXC_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RXC_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD0_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD1_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD2_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD3_OFFSET) +#define IOMUXC_MUX_CTL_SD1_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_CLK_OFFSET) +#define IOMUXC_MUX_CTL_SD1_CMD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_CMD_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA0_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA1_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA2_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA3_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA4 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA4_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA5 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA5_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA6 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA6_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA7 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA7_OFFSET) +#define IOMUXC_MUX_CTL_SD1_STROBE (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_STROBE_OFFSET) +#define IOMUXC_MUX_CTL_SD2_VSELECT (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET) +#define IOMUXC_MUX_CTL_SD3_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_CLK_OFFSET) +#define IOMUXC_MUX_CTL_SD3_CMD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_CMD_OFFSET) +#define IOMUXC_MUX_CTL_SD3_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA0_OFFSET) +#define IOMUXC_MUX_CTL_SD3_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA1_OFFSET) +#define IOMUXC_MUX_CTL_SD3_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA2_OFFSET) +#define IOMUXC_MUX_CTL_SD3_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA3_OFFSET) +#define IOMUXC_MUX_CTL_SD2_CD_B (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_CD_B_OFFSET) +#define IOMUXC_MUX_CTL_SD2_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_CLK_OFFSET) +#define IOMUXC_MUX_CTL_SD2_CMD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_CMD_OFFSET) +#define IOMUXC_MUX_CTL_SD2_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA0_OFFSET) +#define IOMUXC_MUX_CTL_SD2_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA1_OFFSET) +#define IOMUXC_MUX_CTL_SD2_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA2_OFFSET) +#define IOMUXC_MUX_CTL_SD2_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA3_OFFSET) +#define IOMUXC_MUX_CTL_SD2_RESET_B (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET) +#define IOMUXC_MUX_CTL_I2C1_SCL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C1_SCL_OFFSET) +#define IOMUXC_MUX_CTL_I2C1_SDA (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C1_SDA_OFFSET) +#define IOMUXC_MUX_CTL_I2C2_SCL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C2_SCL_OFFSET) +#define IOMUXC_MUX_CTL_I2C2_SDA (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C2_SDA_OFFSET) +#define IOMUXC_MUX_CTL_UART1_RXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART1_RXD_OFFSET) +#define IOMUXC_MUX_CTL_UART1_TXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART1_TXD_OFFSET) +#define IOMUXC_MUX_CTL_UART2_RXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART2_RXD_OFFSET) +#define IOMUXC_MUX_CTL_UART2_TXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART2_TXD_OFFSET) +#define IOMUXC_MUX_CTL_PDM_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_PDM_CLK_OFFSET) +#define IOMUXC_MUX_CTL_PDM_BIT_STREAM0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET) +#define IOMUXC_MUX_CTL_PDM_BIT_STREAM1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET) +#define IOMUXC_MUX_CTL_SAI1_TXFS (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET) +#define IOMUXC_MUX_CTL_SAI1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_TXC_OFFSET) +#define IOMUXC_MUX_CTL_SAI1_TXD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET) +#define IOMUXC_MUX_CTL_SAI1_RXD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET) +#define IOMUXC_MUX_CTL_WDOG_ANY (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_WDOG_ANY_OFFSET) + +#define IOMUXC_PAD_CTL_DAP_TDI (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TDI_OFFSET) +#define IOMUXC_PAD_CTL_DAP_TMS_SWDIO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET) +#define IOMUXC_PAD_CTL_DAP_TCLK_SWCLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET) +#define IOMUXC_PAD_CTL_DAP_TDO_TRACESWO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO00 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO00_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO01 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO01_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO02 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO02_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO03 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO03_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO04 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO04_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO05 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO05_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO06 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO06_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO07 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO07_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO08 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO08_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO09 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO09_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO10 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO10_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO11 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO11_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO12 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO12_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO13 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO13_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO14 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO14_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO15 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO15_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO16 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO16_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO17 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO17_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO18 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO18_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO19 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO19_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO20 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO20_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO21 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO21_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO22 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO22_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO23 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO23_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO24 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO24_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO25 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO25_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO26 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO26_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO27 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO27_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO28 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO28_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO29 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO29_OFFSET) +#define IOMUXC_PAD_CTL_CCM_CLKO1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO1_OFFSET) +#define IOMUXC_PAD_CTL_CCM_CLKO2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO2_OFFSET) +#define IOMUXC_PAD_CTL_CCM_CLKO3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET) +#define IOMUXC_PAD_CTL_CCM_CLKO4 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_MDC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_MDC_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD3_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD2_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD1_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD0_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TXC_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RXC_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD0_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD1_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD2_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD3_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_MDC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_MDC_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD3_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD2_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD1_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD0_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TXC_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RXC_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD0_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD1_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD2_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD3_OFFSET) +#define IOMUXC_PAD_CTL_SD1_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_CLK_OFFSET) +#define IOMUXC_PAD_CTL_SD1_CMD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_CMD_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA0_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA1_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA2_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA3_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA4 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA4_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA5 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA5_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA6 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA6_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA7 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA7_OFFSET) +#define IOMUXC_PAD_CTL_SD1_STROBE (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_STROBE_OFFSET) +#define IOMUXC_PAD_CTL_SD2_VSELECT (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET) +#define IOMUXC_PAD_CTL_SD3_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_CLK_OFFSET) +#define IOMUXC_PAD_CTL_SD3_CMD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_CMD_OFFSET) +#define IOMUXC_PAD_CTL_SD3_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA0_OFFSET) +#define IOMUXC_PAD_CTL_SD3_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA1_OFFSET) +#define IOMUXC_PAD_CTL_SD3_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA2_OFFSET) +#define IOMUXC_PAD_CTL_SD3_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA3_OFFSET) +#define IOMUXC_PAD_CTL_SD2_CD_B (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_CD_B_OFFSET) +#define IOMUXC_PAD_CTL_SD2_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_CLK_OFFSET) +#define IOMUXC_PAD_CTL_SD2_CMD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_CMD_OFFSET) +#define IOMUXC_PAD_CTL_SD2_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA0_OFFSET) +#define IOMUXC_PAD_CTL_SD2_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA1_OFFSET) +#define IOMUXC_PAD_CTL_SD2_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA2_OFFSET) +#define IOMUXC_PAD_CTL_SD2_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA3_OFFSET) +#define IOMUXC_PAD_CTL_SD2_RESET_B (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET) +#define IOMUXC_PAD_CTL_I2C1_SCL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C1_SCL_OFFSET) +#define IOMUXC_PAD_CTL_I2C1_SDA (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C1_SDA_OFFSET) +#define IOMUXC_PAD_CTL_I2C2_SCL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C2_SCL_OFFSET) +#define IOMUXC_PAD_CTL_I2C2_SDA (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C2_SDA_OFFSET) +#define IOMUXC_PAD_CTL_UART1_RXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART1_RXD_OFFSET) +#define IOMUXC_PAD_CTL_UART1_TXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART1_TXD_OFFSET) +#define IOMUXC_PAD_CTL_UART2_RXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART2_RXD_OFFSET) +#define IOMUXC_PAD_CTL_UART2_TXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART2_TXD_OFFSET) +#define IOMUXC_PAD_CTL_PDM_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_PDM_CLK_OFFSET) +#define IOMUXC_PAD_CTL_PDM_BIT_STREAM0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET) +#define IOMUXC_PAD_CTL_PDM_BIT_STREAM1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET) +#define IOMUXC_PAD_CTL_SAI1_TXFS (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET) +#define IOMUXC_PAD_CTL_SAI1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_TXC_OFFSET) +#define IOMUXC_PAD_CTL_SAI1_TXD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET) +#define IOMUXC_PAD_CTL_SAI1_RXD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET) +#define IOMUXC_PAD_CTL_WDOG_ANY (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_WDOG_ANY_OFFSET) + +#define CAN1_IPP_IND_CANRX_SELECT_INPUT (IMX9_IOMUXC1_BASE + CAN1_IPP_IND_CANRX_SELECT_INPUT_OFFSET) +#define CAN2_IPP_IND_CANRX_SELECT_INPUT (IMX9_IOMUXC1_BASE + CAN2_IPP_IND_CANRX_SELECT_INPUT_OFFSET) +#define CCMSRCGPCMIX_EXT1_CLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + CCMSRCGPCMIX_EXT1_CLK_SELECT_INPUT_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_0 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_0_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_1_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_2_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_3 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_3_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_4 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_4_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_5 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_5_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_6 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_6_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_7 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_7_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_8 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_8_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_9 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_9_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_10 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_10_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_11 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_11_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_13 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_13_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_14 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_14_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_15 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_15_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_16 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_16_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_17 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_17_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_18 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_18_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_20 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_20_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_22 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_22_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_23 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_23_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_24 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_24_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_25 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_25_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_27 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_27_OFFSET) +#define I3C2_PIN_SCL_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + 13C2_PIN_SCL_IN_SELECT_INPUT_OFFSET) +#define I3C2_PIN_SDA_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + 13C2_PIN_SDA_IN_SELECT_INPUT_OFFSET) +#define JTAG_MUX_TCK_SELECT_INPUT (IMX9_IOMUXC1_BASE + JTAG_MUX_TCK_SELECT_INPUT_OFFSET) +#define JTAG_MUX_TDI_SELECT_INPUT (IMX9_IOMUXC1_BASE + JTAG_MUX_TDI_SELECT_INPUT_OFFSET) +#define JTAG_MUX_TMS_SELECT_INPUT (IMX9_IOMUXC1_BASE + JTAG_MUX_TMS_SELECT_INPUT_OFFSET) +#define LP12C3_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + LP12C3_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define LPI12C3_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI12C3_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define LP12C5_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + LP12C5_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define LP12C5_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + LP12C5_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define LPI2C8_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI2C8_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define LPI2C8_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI2C8_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_O (IMX9_IOMUXC1_BASE + LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_O_OFFSET) +#define LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_1_OFFSET) +#define LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_2_OFFSET) +#define LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INP (IMX9_IOMUXC1_BASE + LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INP_OFFSET) +#define LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET) +#define LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET) +#define LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INP (IMX9_IOMUXC1_BASE + LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INP_OFFSET) +#define LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET) +#define LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET) +#define LPUARTS_IPP_IND_LPUART_CTS_N_SELECT_INP (IMX9_IOMUXC1_BASE + LPUARTS_IPP_IND_LPUART_CTS_N_SELECT_INP_OFFSET) +#define LPUARTS_IPP_IND_LPUART_RXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPUARTS_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET) +#define LPUARTS_IPP_IND_LPUART_TXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPUARTS_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET) +#define SAI1_IPP_IND_SAI_MCLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + SAI1_IPP_IND_SAI_MCLK_SELECT_INPUT_OFFSET) +#define SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET) +#define SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT (IMX9_IOMUXC1_BASE + SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET) +#define SPDIF_SPDIF_I_SELECT_INPUT (IMX9_IOMUXC1_BASE + SPDIF_SPDIF_I_SELECT_INPUT_OFFSET) +#define USDHC3_IPP_CARD_CLK_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + USDHC3_IPP_CARD_CLK_IN_SELECT_INPUT_OFFSET) +#define USDHC3_IPP_CMD_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + USDHC3_IPP_CMD_IN_SELECT_INPUT_OFFSET) +#define USDHC3_IPP_DATO_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + USDHC3_IPP_DATO_IN_SELECT_INPUT_OFFSET) +#define USDHC3_IPP_DAT1_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + USDHC3_IPP_DAT1_IN_SELECT_INPUT_OFFSET) +#define USDHC3_IPP_DAT2_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + USDHC3_IPP_DAT2_IN_SELECT_INPUT_OFFSET) +#define USDHC3_IPP_DAT3_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + USDHC3_IPP_DAT3_IN_SELECT_INPUT_OFFSET) + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_IOMUX_H */ diff --git a/arch/arm/src/imx9/hardware/imx93/imx93_memorymap.h b/arch/arm/src/imx9/hardware/imx93/imx93_memorymap.h new file mode 100644 index 00000000000..1f757886b01 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx93/imx93_memorymap.h @@ -0,0 +1,181 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx93/imx93_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_MEMORYMAP_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IMX9_GIC_DISTRIBUTOR_BASE (0x48000000UL) +#define IMX9_GIC_REDISTRIBUTOR_BASE (0x48040000UL) +#define IMX9_ANA_OSC_BASE (0x44480000UL) +#define IMX9_AXBS_BASE (0x44510000UL) +#define IMX9_BBNSM_BASE (0x44440000UL) +#define IMX9_BLK_CTRL_BBSMMIX1_BASE (0x44410000UL) +#define IMX9_BLK_CTRL_MLMIX_BASE (0x4A810000UL) +#define IMX9_BLK_CTRL_NIC_WRAPPER1_BASE (0x49000000UL) +#define IMX9_BLK_CTRL_NS_AONMIX1_BASE (0x44210000UL) +#define IMX9_BLK_CTRL_S_AONMIX2_BASE (0x444F0000UL) +#define IMX9_BLK_CTRL_WAKEUPMIX1_BASE (0x42420000UL) +#define IMX9_CAN1_BASE (0x443A0000UL) +#define IMX9_CAN2_BASE (0x425B0000UL) +#define IMX9_CCM_CTRL_BASE (0x44450000UL) +#define IMX9_CM33_MCM_BASE (0x44420000UL) +#define IMX9_DDR_CTRL_BASE (0x4E300000UL) +#define IMX9_BLK_CTRL_DDRMIX_BASE (0x4E010000UL) +#define IMX9_DMA3_BASE (0x44000000UL) +#define IMX9_DMA4_BASE (0x42000000UL) +#define IMX9_PMRO_BASE (0x44484000UL) +#define IMX9_ENET_BASE (0x42890000UL) +#define IMX9_ENET_QOS_BASE (0x428A0000UL) +#define IMX9_FLEXIO1_BASE (0x425C0000UL) +#define IMX9_FLEXIO2_BASE (0x425D0000UL) +#define IMX9_FLEXSPI_BASE (0x425E0000UL) +#define IMX9_FLEXSPI_ARDF_BASE (0x47420000UL) +#define IMX9_FLEXSPI_ATDF_BASE (0x47430000UL) +#define IMX9_GPC_CTRL_CM33_BASE (0x44470000UL) +#define IMX9_GPC_CTRL_CA55_0_BASE (0x44470800UL) +#define IMX9_GPC_CTRL_CA55_1_BASE (0x44471000UL) +#define IMX9_GPC_CTRL_CA55_CLUSTER_BASE (0x44471800UL) +#define IMX9_SAI1_BASE (0x443B0000UL) +#define IMX9_SAI2_BASE (0x42650000UL) +#define IMX9_SAI3_BASE (0x42660000UL) +#define IMX9_I3C1_BASE (0x44330000UL) +#define IMX9_I3C2_BASE (0x42520000UL) +#define IMX9_IOMUXC_BASE (0x443C0000UL) +#define IMX9_ISI_BASE (0x4AE40000UL) +#define IMX9_LCDIF_BASE (0x4AE30000UL) +#define IMX9_LPI2C1_BASE (0x44340000UL) +#define IMX9_LPI2C2_BASE (0x44350000UL) +#define IMX9_LPI2C3_BASE (0x42530000UL) +#define IMX9_LPI2C4_BASE (0x42540000UL) +#define IMX9_LPI2C5_BASE (0x426B0000UL) +#define IMX9_LPI2C6_BASE (0x426C0000UL) +#define IMX9_LPI2C7_BASE (0x426D0000UL) +#define IMX9_LPI2C8_BASE (0x426E0000UL) +#define IMX9_LPIT1_BASE (0x442F0000UL) +#define IMX9_LPIT2_BASE (0x424C0000UL) +#define IMX9_LPSPI1_BASE (0x44360000UL) +#define IMX9_LPSPI2_BASE (0x44370000UL) +#define IMX9_LPSPI3_BASE (0x42550000UL) +#define IMX9_LPSPI4_BASE (0x42560000UL) +#define IMX9_LPSPI5_BASE (0x426F0000UL) +#define IMX9_LPSPI6_BASE (0x42700000UL) +#define IMX9_LPSPI7_BASE (0x42710000UL) +#define IMX9_LPSPI8_BASE (0x42720000UL) +#define IMX9_LPTMR1_BASE (0x44300000UL) +#define IMX9_LPTMR2_BASE (0x424D0000UL) +#define IMX9_LPUART1_BASE (0x44380000UL) +#define IMX9_LPUART2_BASE (0x44390000UL) +#define IMX9_LPUART3_BASE (0x42570000UL) +#define IMX9_LPUART4_BASE (0x42580000UL) +#define IMX9_LPUART5_BASE (0x42590000UL) +#define IMX9_LPUART6_BASE (0x425A0000UL) +#define IMX9_LPUART7_BASE (0x42690000UL) +#define IMX9_LPUART8_BASE (0x426A0000UL) +#define IMX9_M33_CACHE_MCM_BASE (0x44401000UL) +#define IMX9_BLK_CTRL_MEDIAMIX_BASE (0x4AC10000UL) +#define IMX9_MIPI_CSI_CSR_BASE (0x4AE00000UL) +#define IMX9_MIPI_DSI_BASE (0x4AE10000UL) +#define IMX9_MU1_MUA_BASE (0x44220000UL) +#define IMX9_MU2_MUA_BASE (0x42430000UL) +#define IMX9_S3MUA_BASE (0x47520000UL) +#define IMX9_TRDC_BASE (0x49010000UL) +#define IMX9_NPU_BASE (0x4A900000UL) +#define IMX9_OCOTP_BASE (0x47518000UL) +#define IMX9_OCRAM_MECC1_BASE (0x490A0000UL) +#define IMX9_FLEXSPI_OTFAD1_BASE (0x425E0C00UL) +#define IMX9_PDM_BASE (0x44520000UL) +#define IMX9_ARMPLL_BASE (0x44481000UL) +#define IMX9_AUDIOPLL_BASE (0x44481200UL) +#define IMX9_DRAMPLL_BASE (0x44481300UL) +#define IMX9_SYSPLL_BASE (0x44481100UL) +#define IMX9_VIDEOPLL_BASE (0x44481400UL) +#define IMX9_PXP_BASE (0x4AE20000UL) +#define IMX9_GPIO1_BASE (0x47400000UL) +#define IMX9_GPIO2_BASE (0x43810000UL) +#define IMX9_GPIO3_BASE (0x43820000UL) +#define IMX9_GPIO4_BASE (0x43830000UL) +#define IMX9_ROMCP1_BASE (0x44430000UL) +#define IMX9_ROMCP2_BASE (0x42640000UL) +#define IMX9_ADC1_BASE (0x44530000UL) +#define IMX9_SEMA42_1_BASE (0x44260000UL) +#define IMX9_SEMA42_2_BASE (0x42450000UL) +#define IMX9_SFA_BASE (0x44483000UL) +#define IMX9_SPDIF_BASE (0x42680000UL) +#define IMX9_SRC_GENERAL_REG_BASE (0x44460000UL) +#define IMX9_SRC_SENTINEL_SLICE_BASE (0x44460400UL) +#define IMX9_SRC_AON_SLICE_BASE (0x44460800UL) +#define IMX9_SRC_WKUP_SLICE_BASE (0x44460C00UL) +#define IMX9_SRC_DDR_SLICE_BASE (0x44461000UL) +#define IMX9_SRC_DPHY_SLICE_BASE (0x44461400UL) +#define IMX9_SRC_ML_SLICE_BASE (0x44461800UL) +#define IMX9_SRC_NIC_SLICE_BASE (0x44461C00UL) +#define IMX9_SRC_HSIO_SLICE_BASE (0x44462000UL) +#define IMX9_SRC_MEDIA_SLICE_BASE (0x44462400UL) +#define IMX9_SRC_M33P_SLICE_BASE (0x44462800UL) +#define IMX9_SRC_A55C0_SLICE_BASE (0x44462C00UL) +#define IMX9_SRC_A55C1_SLICE_BASE (0x44463000UL) +#define IMX9_SRC_A55P_SLICE_BASE (0x44463400UL) +#define IMX9_SRC_MEDIA_MEM_BASE (0x44465800UL) +#define IMX9_SRC_ML_MEM_BASE (0x44464800UL) +#define IMX9_M33_PCF1_BASE (0x443E0000UL) +#define IMX9_M33_PSF1_BASE (0x443F0000UL) +#define IMX9_SYS_CTR_COMPARE_BASE (0x442A0000UL) +#define IMX9_SYS_CTR_CONTROL_BASE (0x44290000UL) +#define IMX9_SYS_CTR_READ_BASE (0x442B0000UL) +#define IMX9_TMU_BASE (0x44482000UL) +#define IMX9_TPM1_BASE (0x44310000UL) +#define IMX9_TPM2_BASE (0x44320000UL) +#define IMX9_TPM3_BASE (0x424E0000UL) +#define IMX9_TPM4_BASE (0x424F0000UL) +#define IMX9_TPM5_BASE (0x42500000UL) +#define IMX9_TPM6_BASE (0x42510000UL) +#define IMX9_TRDC1_BASE (0x44270000UL) +#define IMX9_TRDC2_BASE (0x42460000UL) +#define IMX9_TRGMUX_BASE (0x44531000UL) +#define IMX9_TSTMR1_BASE (0x442C0000UL) +#define IMX9_TSTMR2_BASE (0x42480000UL) +#define IMX9_USB_OTG1_BASE (0x4C100000UL) +#define IMX9_USB_OTG2_BASE (0x4C200000UL) +#define IMX9_USBNC_OTG1_BASE (0x4C100200UL) +#define IMX9_USBNC_OTG2_BASE (0x4C200200UL) +#define IMX9_USDHC1_BASE (0x42850000UL) +#define IMX9_USDHC2_BASE (0x42860000UL) +#define IMX9_USDHC3_BASE (0x428B0000UL) +#define IMX9_WDOG1_BASE (0x442D0000UL) +#define IMX9_WDOG2_BASE (0x442E0000UL) +#define IMX9_WDOG3_BASE (0x42490000UL) +#define IMX9_WDOG4_BASE (0x424A0000UL) +#define IMX9_WDOG5_BASE (0x424B0000UL) +#define IMX9_LPCAC_PC_BASE (0x44400000UL) +#define IMX9_LPCAC_PS_BASE (0x44400800UL) + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_MEMORYMAP_H */ diff --git a/arch/arm/src/imx9/hardware/imx93/imx93_pinmux.h b/arch/arm/src/imx9/hardware/imx93/imx93_pinmux.h new file mode 100644 index 00000000000..0f1b6758564 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx93/imx93_pinmux.h @@ -0,0 +1,636 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx93/imx93_pinmux.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_PINMUX_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_PINMUX_H + +#define IOMUXC_PAD_DAP_TDI_JTAG_MUX_TDI IOMUX_PADCFG(0x0000, 0x0, 0x03d8, 0x0, 0x01b0) +#define IOMUXC_PAD_DAP_TDI_MQS2_LEFT IOMUX_PADCFG(0x0000, 0x1, 0x0000, 0x0, 0x01b0) +#define IOMUXC_PAD_DAP_TDI_CAN2_TX IOMUX_PADCFG(0x0000, 0x3, 0x0000, 0x0, 0x01b0) +#define IOMUXC_PAD_DAP_TDI_FLEXIO2_FLEXIO30 IOMUX_PADCFG(0x0000, 0x4, 0x0000, 0x0, 0x01b0) +#define IOMUXC_PAD_DAP_TDI_GPIO3_IO28 IOMUX_PADCFG(0x0000, 0x5, 0x0000, 0x0, 0x01b0) +#define IOMUXC_PAD_DAP_TDI_LPUART5_RX IOMUX_PADCFG(0x0000, 0x6, 0x0430, 0x0, 0x01b0) +#define IOMUXC_PAD_DAP_TMS_SWDIO_JTAG_MUX_TMS IOMUX_PADCFG(0x0004, 0x0, 0x03dc, 0x0, 0x01b4) +#define IOMUXC_PAD_DAP_TMS_SWDIO_FLEXIO2_FLEXIO31 IOMUX_PADCFG(0x0004, 0x4, 0x0000, 0x0, 0x01b4) +#define IOMUXC_PAD_DAP_TMS_SWDIO_GPIO3_IO29 IOMUX_PADCFG(0x0004, 0x5, 0x0000, 0x0, 0x01b4) +#define IOMUXC_PAD_DAP_TMS_SWDIO_LPUART5_RTS_B IOMUX_PADCFG(0x0004, 0x6, 0x0000, 0x0, 0x01b4) +#define IOMUXC_PAD_DAP_TCLK_SWCLK_JTAG_MUX_TCK IOMUX_PADCFG(0x0008, 0x0, 0x03d4, 0x0, 0x01b8) +#define IOMUXC_PAD_DAP_TCLK_SWCLK_FLEXIO1_FLEXIO30 IOMUX_PADCFG(0x0008, 0x4, 0x0000, 0x0, 0x01b8) +#define IOMUXC_PAD_DAP_TCLK_SWCLK_GPIO3_IO30 IOMUX_PADCFG(0x0008, 0x5, 0x0000, 0x0, 0x01b8) +#define IOMUXC_PAD_DAP_TCLK_SWCLK_LPUART5_CTS_B IOMUX_PADCFG(0x0008, 0x6, 0x042c, 0x0, 0x01b8) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_JTAG_MUX_TDO IOMUX_PADCFG(0x000c, 0x0, 0x0000, 0x0, 0x01bc) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_MQS2_RIGHT IOMUX_PADCFG(0x000c, 0x1, 0x0000, 0x0, 0x01bc) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_CAN2_RX IOMUX_PADCFG(0x000c, 0x3, 0x0364, 0x0, 0x01bc) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_FLEXIO1_FLEXIO31 IOMUX_PADCFG(0x000c, 0x4, 0x0000, 0x0, 0x01bc) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_GPIO3_IO31 IOMUX_PADCFG(0x000c, 0x5, 0x0000, 0x0, 0x01bc) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_LPUART5_TX IOMUX_PADCFG(0x000c, 0x6, 0x0434, 0x0, 0x01bc) +#define IOMUXC_PAD_GPIO_IO00_GPIO2_IO00 IOMUX_PADCFG(0x0010, 0x0, 0x0000, 0x0, 0x01c0) +#define IOMUXC_PAD_GPIO_IO00_LPI2C3_SDA IOMUX_PADCFG(0x0010, 0x1, 0x03e4, 0x0, 0x01c0) +#define IOMUXC_PAD_GPIO_IO00_MEDIAMIX_CAM_CLK IOMUX_PADCFG(0x0010, 0x2, 0x0000, 0x0, 0x01c0) +#define IOMUXC_PAD_GPIO_IO00_MEDIAMIX_DISP_CLK IOMUX_PADCFG(0x0010, 0x3, 0x0000, 0x0, 0x01c0) +#define IOMUXC_PAD_GPIO_IO00_LPSPI6_PCS0 IOMUX_PADCFG(0x0010, 0x4, 0x0000, 0x0, 0x01c0) +#define IOMUXC_PAD_GPIO_IO00_LPUART5_TX IOMUX_PADCFG(0x0010, 0x5, 0x0434, 0x1, 0x01c0) +#define IOMUXC_PAD_GPIO_IO00_LPI2C5_SDA IOMUX_PADCFG(0x0010, 0x6, 0x03ec, 0x0, 0x01c0) +#define IOMUXC_PAD_GPIO_IO00_FLEXIO1_FLEXIO00 IOMUX_PADCFG(0x0010, 0x7, 0x036c, 0x0, 0x01c0) +#define IOMUXC_PAD_GPIO_IO01_GPIO2_IO01 IOMUX_PADCFG(0x0014, 0x0, 0x0000, 0x0, 0x01c4) +#define IOMUXC_PAD_GPIO_IO01_LPI2C3_SCL IOMUX_PADCFG(0x0014, 0x1, 0x03e0, 0x0, 0x01c4) +#define IOMUXC_PAD_GPIO_IO01_MEDIAMIX_CAM_DATA00 IOMUX_PADCFG(0x0014, 0x2, 0x0000, 0x0, 0x01c4) +#define IOMUXC_PAD_GPIO_IO01_MEDIAMIX_DISP_DE IOMUX_PADCFG(0x0014, 0x3, 0x0000, 0x0, 0x01c4) +#define IOMUXC_PAD_GPIO_IO01_LPSPI6_SIN IOMUX_PADCFG(0x0014, 0x4, 0x0000, 0x0, 0x01c4) +#define IOMUXC_PAD_GPIO_IO01_LPUART5_RX IOMUX_PADCFG(0x0014, 0x5, 0x0430, 0x1, 0x01c4) +#define IOMUXC_PAD_GPIO_IO01_LPI2C5_SCL IOMUX_PADCFG(0x0014, 0x6, 0x03e8, 0x0, 0x01c4) +#define IOMUXC_PAD_GPIO_IO01_FLEXIO1_FLEXIO01 IOMUX_PADCFG(0x0014, 0x7, 0x0370, 0x0, 0x01c4) +#define IOMUXC_PAD_GPIO_IO02_GPIO2_IO02 IOMUX_PADCFG(0x0018, 0x0, 0x0000, 0x0, 0x01c8) +#define IOMUXC_PAD_GPIO_IO02_LPI2C4_SDA IOMUX_PADCFG(0x0018, 0x1, 0x0000, 0x0, 0x01c8) +#define IOMUXC_PAD_GPIO_IO02_MEDIAMIX_CAM_VSYNC IOMUX_PADCFG(0x0018, 0x2, 0x0000, 0x0, 0x01c8) +#define IOMUXC_PAD_GPIO_IO02_MEDIAMIX_DISP_VSYNC IOMUX_PADCFG(0x0018, 0x3, 0x0000, 0x0, 0x01c8) +#define IOMUXC_PAD_GPIO_IO02_LPSPI6_SOUT IOMUX_PADCFG(0x0018, 0x4, 0x0000, 0x0, 0x01c8) +#define IOMUXC_PAD_GPIO_IO02_LPUART5_CTS_B IOMUX_PADCFG(0x0018, 0x5, 0x042c, 0x1, 0x01c8) +#define IOMUXC_PAD_GPIO_IO02_LPI2C6_SDA IOMUX_PADCFG(0x0018, 0x6, 0x03f4, 0x0, 0x01c8) +#define IOMUXC_PAD_GPIO_IO02_FLEXIO1_FLEXIO02 IOMUX_PADCFG(0x0018, 0x7, 0x0374, 0x0, 0x01c8) +#define IOMUXC_PAD_GPIO_IO03_GPIO2_IO03 IOMUX_PADCFG(0x001c, 0x0, 0x0000, 0x0, 0x01cc) +#define IOMUXC_PAD_GPIO_IO03_LPI2C4_SCL IOMUX_PADCFG(0x001c, 0x1, 0x0000, 0x0, 0x01cc) +#define IOMUXC_PAD_GPIO_IO03_MEDIAMIX_CAM_HSYNC IOMUX_PADCFG(0x001c, 0x2, 0x0000, 0x0, 0x01cc) +#define IOMUXC_PAD_GPIO_IO03_MEDIAMIX_DISP_HSYNC IOMUX_PADCFG(0x001c, 0x3, 0x0000, 0x0, 0x01cc) +#define IOMUXC_PAD_GPIO_IO03_LPSPI6_SCK IOMUX_PADCFG(0x001c, 0x4, 0x0000, 0x0, 0x01cc) +#define IOMUXC_PAD_GPIO_IO03_LPUART5_RTS_B IOMUX_PADCFG(0x001c, 0x5, 0x0000, 0x0, 0x01cc) +#define IOMUXC_PAD_GPIO_IO03_LPI2C6_SCL IOMUX_PADCFG(0x001c, 0x6, 0x03f0, 0x0, 0x01cc) +#define IOMUXC_PAD_GPIO_IO03_FLEXIO1_FLEXIO03 IOMUX_PADCFG(0x001c, 0x7, 0x0378, 0x0, 0x01cc) +#define IOMUXC_PAD_GPIO_IO04_GPIO2_IO04 IOMUX_PADCFG(0x0020, 0x0, 0x0000, 0x0, 0x01d0) +#define IOMUXC_PAD_GPIO_IO04_TPM3_CH0 IOMUX_PADCFG(0x0020, 0x1, 0x0000, 0x0, 0x01d0) +#define IOMUXC_PAD_GPIO_IO04_PDM_CLK IOMUX_PADCFG(0x0020, 0x2, 0x0000, 0x0, 0x01d0) +#define IOMUXC_PAD_GPIO_IO04_MEDIAMIX_DISP_DATA00 IOMUX_PADCFG(0x0020, 0x3, 0x0000, 0x0, 0x01d0) +#define IOMUXC_PAD_GPIO_IO04_LPSPI7_PCS0 IOMUX_PADCFG(0x0020, 0x4, 0x0000, 0x0, 0x01d0) +#define IOMUXC_PAD_GPIO_IO04_LPUART6_TX IOMUX_PADCFG(0x0020, 0x5, 0x0000, 0x0, 0x01d0) +#define IOMUXC_PAD_GPIO_IO04_LPI2C6_SDA IOMUX_PADCFG(0x0020, 0x6, 0x03f4, 0x1, 0x01d0) +#define IOMUXC_PAD_GPIO_IO04_FLEXIO1_FLEXIO04 IOMUX_PADCFG(0x0020, 0x7, 0x037c, 0x0, 0x01d0) +#define IOMUXC_PAD_GPIO_IO05_GPIO2_IO05 IOMUX_PADCFG(0x0024, 0x0, 0x0000, 0x0, 0x01d4) +#define IOMUXC_PAD_GPIO_IO05_TPM4_CH0 IOMUX_PADCFG(0x0024, 0x1, 0x0000, 0x0, 0x01d4) +#define IOMUXC_PAD_GPIO_IO05_PDM_BIT_STREAM00 IOMUX_PADCFG(0x0024, 0x2, 0x0438, 0x0, 0x01d4) +#define IOMUXC_PAD_GPIO_IO05_MEDIAMIX_DISP_DATA01 IOMUX_PADCFG(0x0024, 0x3, 0x0000, 0x0, 0x01d4) +#define IOMUXC_PAD_GPIO_IO05_LPSPI7_SIN IOMUX_PADCFG(0x0024, 0x4, 0x0000, 0x0, 0x01d4) +#define IOMUXC_PAD_GPIO_IO05_LPUART6_RX IOMUX_PADCFG(0x0024, 0x5, 0x0000, 0x0, 0x01d4) +#define IOMUXC_PAD_GPIO_IO05_LPI2C6_SCL IOMUX_PADCFG(0x0024, 0x6, 0x03f0, 0x1, 0x01d4) +#define IOMUXC_PAD_GPIO_IO05_FLEXIO1_FLEXIO05 IOMUX_PADCFG(0x0024, 0x7, 0x0380, 0x0, 0x01d4) +#define IOMUXC_PAD_GPIO_IO06_GPIO2_IO06 IOMUX_PADCFG(0x0028, 0x0, 0x0000, 0x0, 0x01d8) +#define IOMUXC_PAD_GPIO_IO06_TPM5_CH0 IOMUX_PADCFG(0x0028, 0x1, 0x0000, 0x0, 0x01d8) +#define IOMUXC_PAD_GPIO_IO06_PDM_BIT_STREAM01 IOMUX_PADCFG(0x0028, 0x2, 0x043c, 0x0, 0x01d8) +#define IOMUXC_PAD_GPIO_IO06_MEDIAMIX_DISP_DATA02 IOMUX_PADCFG(0x0028, 0x3, 0x0000, 0x0, 0x01d8) +#define IOMUXC_PAD_GPIO_IO06_LPSPI7_SOUT IOMUX_PADCFG(0x0028, 0x4, 0x0000, 0x0, 0x01d8) +#define IOMUXC_PAD_GPIO_IO06_LPUART6_CTS_B IOMUX_PADCFG(0x0028, 0x5, 0x0000, 0x0, 0x01d8) +#define IOMUXC_PAD_GPIO_IO06_LPI2C7_SDA IOMUX_PADCFG(0x0028, 0x6, 0x03fc, 0x0, 0x01d8) +#define IOMUXC_PAD_GPIO_IO06_FLEXIO1_FLEXIO06 IOMUX_PADCFG(0x0028, 0x7, 0x0384, 0x0, 0x01d8) +#define IOMUXC_PAD_GPIO_IO07_GPIO2_IO07 IOMUX_PADCFG(0x002c, 0x0, 0x0000, 0x0, 0x01dc) +#define IOMUXC_PAD_GPIO_IO07_LPSPI3_PCS1 IOMUX_PADCFG(0x002c, 0x1, 0x0000, 0x0, 0x01dc) +#define IOMUXC_PAD_GPIO_IO07_MEDIAMIX_CAM_DATA01 IOMUX_PADCFG(0x002c, 0x2, 0x0000, 0x0, 0x01dc) +#define IOMUXC_PAD_GPIO_IO07_MEDIAMIX_DISP_DATA03 IOMUX_PADCFG(0x002c, 0x3, 0x0000, 0x0, 0x01dc) +#define IOMUXC_PAD_GPIO_IO07_LPSPI7_SCK IOMUX_PADCFG(0x002c, 0x4, 0x0000, 0x0, 0x01dc) +#define IOMUXC_PAD_GPIO_IO07_LPUART6_RTS_B IOMUX_PADCFG(0x002c, 0x5, 0x0000, 0x0, 0x01dc) +#define IOMUXC_PAD_GPIO_IO07_LPI2C7_SCL IOMUX_PADCFG(0x002c, 0x6, 0x03f8, 0x0, 0x01dc) +#define IOMUXC_PAD_GPIO_IO07_FLEXIO1_FLEXIO07 IOMUX_PADCFG(0x002c, 0x7, 0x0388, 0x0, 0x01dc) +#define IOMUXC_PAD_GPIO_IO08_GPIO2_IO08 IOMUX_PADCFG(0x0030, 0x0, 0x0000, 0x0, 0x01e0) +#define IOMUXC_PAD_GPIO_IO08_LPSPI3_PCS0 IOMUX_PADCFG(0x0030, 0x1, 0x0000, 0x0, 0x01e0) +#define IOMUXC_PAD_GPIO_IO08_MEDIAMIX_CAM_DATA02 IOMUX_PADCFG(0x0030, 0x2, 0x0000, 0x0, 0x01e0) +#define IOMUXC_PAD_GPIO_IO08_MEDIAMIX_DISP_DATA04 IOMUX_PADCFG(0x0030, 0x3, 0x0000, 0x0, 0x01e0) +#define IOMUXC_PAD_GPIO_IO08_TPM6_CH0 IOMUX_PADCFG(0x0030, 0x4, 0x0000, 0x0, 0x01e0) +#define IOMUXC_PAD_GPIO_IO08_LPUART7_TX IOMUX_PADCFG(0x0030, 0x5, 0x0000, 0x0, 0x01e0) +#define IOMUXC_PAD_GPIO_IO08_LPI2C7_SDA IOMUX_PADCFG(0x0030, 0x6, 0x03fc, 0x1, 0x01e0) +#define IOMUXC_PAD_GPIO_IO08_FLEXIO1_FLEXIO08 IOMUX_PADCFG(0x0030, 0x7, 0x038c, 0x0, 0x01e0) +#define IOMUXC_PAD_GPIO_IO09_GPIO2_IO09 IOMUX_PADCFG(0x0034, 0x0, 0x0000, 0x0, 0x01e4) +#define IOMUXC_PAD_GPIO_IO09_LPSPI3_SIN IOMUX_PADCFG(0x0034, 0x1, 0x0000, 0x0, 0x01e4) +#define IOMUXC_PAD_GPIO_IO09_MEDIAMIX_CAM_DATA03 IOMUX_PADCFG(0x0034, 0x2, 0x0000, 0x0, 0x01e4) +#define IOMUXC_PAD_GPIO_IO09_MEDIAMIX_DISP_DATA05 IOMUX_PADCFG(0x0034, 0x3, 0x0000, 0x0, 0x01e4) +#define IOMUXC_PAD_GPIO_IO09_TPM3_EXTCLK IOMUX_PADCFG(0x0034, 0x4, 0x0000, 0x0, 0x01e4) +#define IOMUXC_PAD_GPIO_IO09_LPUART7_RX IOMUX_PADCFG(0x0034, 0x5, 0x0000, 0x0, 0x01e4) +#define IOMUXC_PAD_GPIO_IO09_LPI2C7_SCL IOMUX_PADCFG(0x0034, 0x6, 0x03f8, 0x1, 0x01e4) +#define IOMUXC_PAD_GPIO_IO09_FLEXIO1_FLEXIO09 IOMUX_PADCFG(0x0034, 0x7, 0x0390, 0x0, 0x01e4) +#define IOMUXC_PAD_GPIO_IO10_GPIO2_IO10 IOMUX_PADCFG(0x0038, 0x0, 0x0000, 0x0, 0x01e8) +#define IOMUXC_PAD_GPIO_IO10_LPSPI3_SOUT IOMUX_PADCFG(0x0038, 0x1, 0x0000, 0x0, 0x01e8) +#define IOMUXC_PAD_GPIO_IO10_MEDIAMIX_CAM_DATA04 IOMUX_PADCFG(0x0038, 0x2, 0x0000, 0x0, 0x01e8) +#define IOMUXC_PAD_GPIO_IO10_MEDIAMIX_DISP_DATA06 IOMUX_PADCFG(0x0038, 0x3, 0x0000, 0x0, 0x01e8) +#define IOMUXC_PAD_GPIO_IO10_TPM4_EXTCLK IOMUX_PADCFG(0x0038, 0x4, 0x0000, 0x0, 0x01e8) +#define IOMUXC_PAD_GPIO_IO10_LPUART7_CTS_B IOMUX_PADCFG(0x0038, 0x5, 0x0000, 0x0, 0x01e8) +#define IOMUXC_PAD_GPIO_IO10_LPI2C8_SDA IOMUX_PADCFG(0x0038, 0x6, 0x0404, 0x0, 0x01e8) +#define IOMUXC_PAD_GPIO_IO10_FLEXIO1_FLEXIO10 IOMUX_PADCFG(0x0038, 0x7, 0x0394, 0x0, 0x01e8) +#define IOMUXC_PAD_GPIO_IO11_GPIO2_IO11 IOMUX_PADCFG(0x003c, 0x0, 0x0000, 0x0, 0x01ec) +#define IOMUXC_PAD_GPIO_IO11_LPSPI3_SCK IOMUX_PADCFG(0x003c, 0x1, 0x0000, 0x0, 0x01ec) +#define IOMUXC_PAD_GPIO_IO11_MEDIAMIX_CAM_DATA05 IOMUX_PADCFG(0x003c, 0x2, 0x0000, 0x0, 0x01ec) +#define IOMUXC_PAD_GPIO_IO11_MEDIAMIX_DISP_DATA07 IOMUX_PADCFG(0x003c, 0x3, 0x0000, 0x0, 0x01ec) +#define IOMUXC_PAD_GPIO_IO11_TPM5_EXTCLK IOMUX_PADCFG(0x003c, 0x4, 0x0000, 0x0, 0x01ec) +#define IOMUXC_PAD_GPIO_IO11_LPUART7_RTS_B IOMUX_PADCFG(0x003c, 0x5, 0x0000, 0x0, 0x01ec) +#define IOMUXC_PAD_GPIO_IO11_LPI2C8_SCL IOMUX_PADCFG(0x003c, 0x6, 0x0400, 0x0, 0x01ec) +#define IOMUXC_PAD_GPIO_IO11_FLEXIO1_FLEXIO11 IOMUX_PADCFG(0x003c, 0x7, 0x0398, 0x0, 0x01ec) +#define IOMUXC_PAD_GPIO_IO12_GPIO2_IO12 IOMUX_PADCFG(0x0040, 0x0, 0x0000, 0x0, 0x01f0) +#define IOMUXC_PAD_GPIO_IO12_TPM3_CH2 IOMUX_PADCFG(0x0040, 0x1, 0x0000, 0x0, 0x01f0) +#define IOMUXC_PAD_GPIO_IO12_PDM_BIT_STREAM02 IOMUX_PADCFG(0x0040, 0x2, 0x0440, 0x0, 0x01f0) +#define IOMUXC_PAD_GPIO_IO12_MEDIAMIX_DISP_DATA08 IOMUX_PADCFG(0x0040, 0x3, 0x0000, 0x0, 0x01f0) +#define IOMUXC_PAD_GPIO_IO12_LPSPI8_PCS0 IOMUX_PADCFG(0x0040, 0x4, 0x0000, 0x0, 0x01f0) +#define IOMUXC_PAD_GPIO_IO12_LPUART8_TX IOMUX_PADCFG(0x0040, 0x5, 0x0000, 0x0, 0x01f0) +#define IOMUXC_PAD_GPIO_IO12_LPI2C8_SDA IOMUX_PADCFG(0x0040, 0x6, 0x0404, 0x1, 0x01f0) +#define IOMUXC_PAD_GPIO_IO12_SAI3_RX_SYNC IOMUX_PADCFG(0x0040, 0x7, 0x0450, 0x0, 0x01f0) +#define IOMUXC_PAD_GPIO_IO13_GPIO2_IO13 IOMUX_PADCFG(0x0044, 0x0, 0x0000, 0x0, 0x01f4) +#define IOMUXC_PAD_GPIO_IO13_TPM4_CH2 IOMUX_PADCFG(0x0044, 0x1, 0x0000, 0x0, 0x01f4) +#define IOMUXC_PAD_GPIO_IO13_PDM_BIT_STREAM03 IOMUX_PADCFG(0x0044, 0x2, 0x0444, 0x0, 0x01f4) +#define IOMUXC_PAD_GPIO_IO13_MEDIAMIX_DISP_DATA09 IOMUX_PADCFG(0x0044, 0x3, 0x0000, 0x0, 0x01f4) +#define IOMUXC_PAD_GPIO_IO13_LPSPI8_SIN IOMUX_PADCFG(0x0044, 0x4, 0x0000, 0x0, 0x01f4) +#define IOMUXC_PAD_GPIO_IO13_LPUART8_RX IOMUX_PADCFG(0x0044, 0x5, 0x0000, 0x0, 0x01f4) +#define IOMUXC_PAD_GPIO_IO13_LPI2C8_SCL IOMUX_PADCFG(0x0044, 0x6, 0x0400, 0x1, 0x01f4) +#define IOMUXC_PAD_GPIO_IO13_FLEXIO1_FLEXIO13 IOMUX_PADCFG(0x0044, 0x7, 0x039c, 0x0, 0x01f4) +#define IOMUXC_PAD_GPIO_IO14_GPIO2_IO14 IOMUX_PADCFG(0x0048, 0x0, 0x0000, 0x0, 0x01f8) +#define IOMUXC_PAD_GPIO_IO14_LPUART3_TX IOMUX_PADCFG(0x0048, 0x1, 0x041c, 0x0, 0x01f8) +#define IOMUXC_PAD_GPIO_IO14_MEDIAMIX_CAM_DATA06 IOMUX_PADCFG(0x0048, 0x2, 0x0000, 0x0, 0x01f8) +#define IOMUXC_PAD_GPIO_IO14_MEDIAMIX_DISP_DATA10 IOMUX_PADCFG(0x0048, 0x3, 0x0000, 0x0, 0x01f8) +#define IOMUXC_PAD_GPIO_IO14_LPSPI8_SOUT IOMUX_PADCFG(0x0048, 0x4, 0x0000, 0x0, 0x01f8) +#define IOMUXC_PAD_GPIO_IO14_LPUART8_CTS_B IOMUX_PADCFG(0x0048, 0x5, 0x0000, 0x0, 0x01f8) +#define IOMUXC_PAD_GPIO_IO14_LPUART4_TX IOMUX_PADCFG(0x0048, 0x6, 0x0428, 0x0, 0x01f8) +#define IOMUXC_PAD_GPIO_IO14_FLEXIO1_FLEXIO14 IOMUX_PADCFG(0x0048, 0x7, 0x03a0, 0x0, 0x01f8) +#define IOMUXC_PAD_GPIO_IO15_GPIO2_IO15 IOMUX_PADCFG(0x004c, 0x0, 0x0000, 0x0, 0x01fc) +#define IOMUXC_PAD_GPIO_IO15_LPUART3_RX IOMUX_PADCFG(0x004c, 0x1, 0x0418, 0x0, 0x01fc) +#define IOMUXC_PAD_GPIO_IO15_MEDIAMIX_CAM_DATA07 IOMUX_PADCFG(0x004c, 0x2, 0x0000, 0x0, 0x01fc) +#define IOMUXC_PAD_GPIO_IO15_MEDIAMIX_DISP_DATA11 IOMUX_PADCFG(0x004c, 0x3, 0x0000, 0x0, 0x01fc) +#define IOMUXC_PAD_GPIO_IO15_LPSPI8_SCK IOMUX_PADCFG(0x004c, 0x4, 0x0000, 0x0, 0x01fc) +#define IOMUXC_PAD_GPIO_IO15_LPUART8_RTS_B IOMUX_PADCFG(0x004c, 0x5, 0x0000, 0x0, 0x01fc) +#define IOMUXC_PAD_GPIO_IO15_LPUART4_RX IOMUX_PADCFG(0x004c, 0x6, 0x0424, 0x0, 0x01fc) +#define IOMUXC_PAD_GPIO_IO15_FLEXIO1_FLEXIO15 IOMUX_PADCFG(0x004c, 0x7, 0x03a4, 0x0, 0x01fc) +#define IOMUXC_PAD_GPIO_IO16_GPIO2_IO16 IOMUX_PADCFG(0x0050, 0x0, 0x0000, 0x0, 0x0200) +#define IOMUXC_PAD_GPIO_IO16_SAI3_TX_BCLK IOMUX_PADCFG(0x0050, 0x1, 0x0000, 0x0, 0x0200) +#define IOMUXC_PAD_GPIO_IO16_PDM_BIT_STREAM02 IOMUX_PADCFG(0x0050, 0x2, 0x0440, 0x1, 0x0200) +#define IOMUXC_PAD_GPIO_IO16_MEDIAMIX_DISP_DATA12 IOMUX_PADCFG(0x0050, 0x3, 0x0000, 0x0, 0x0200) +#define IOMUXC_PAD_GPIO_IO16_LPUART3_CTS_B IOMUX_PADCFG(0x0050, 0x4, 0x0414, 0x0, 0x0200) +#define IOMUXC_PAD_GPIO_IO16_LPSPI4_PCS2 IOMUX_PADCFG(0x0050, 0x5, 0x0000, 0x0, 0x0200) +#define IOMUXC_PAD_GPIO_IO16_LPUART4_CTS_B IOMUX_PADCFG(0x0050, 0x6, 0x0420, 0x0, 0x0200) +#define IOMUXC_PAD_GPIO_IO16_FLEXIO1_FLEXIO16 IOMUX_PADCFG(0x0050, 0x7, 0x03a8, 0x0, 0x0200) +#define IOMUXC_PAD_GPIO_IO17_GPIO2_IO17 IOMUX_PADCFG(0x0054, 0x0, 0x0000, 0x0, 0x0204) +#define IOMUXC_PAD_GPIO_IO17_SAI3_MCLK IOMUX_PADCFG(0x0054, 0x1, 0x0000, 0x0, 0x0204) +#define IOMUXC_PAD_GPIO_IO17_MEDIAMIX_CAM_DATA08 IOMUX_PADCFG(0x0054, 0x2, 0x0000, 0x0, 0x0204) +#define IOMUXC_PAD_GPIO_IO17_MEDIAMIX_DISP_DATA13 IOMUX_PADCFG(0x0054, 0x3, 0x0000, 0x0, 0x0204) +#define IOMUXC_PAD_GPIO_IO17_LPUART3_RTS_B IOMUX_PADCFG(0x0054, 0x4, 0x0000, 0x0, 0x0204) +#define IOMUXC_PAD_GPIO_IO17_LPSPI4_PCS1 IOMUX_PADCFG(0x0054, 0x5, 0x0000, 0x0, 0x0204) +#define IOMUXC_PAD_GPIO_IO17_LPUART4_RTS_B IOMUX_PADCFG(0x0054, 0x6, 0x0000, 0x0, 0x0204) +#define IOMUXC_PAD_GPIO_IO17_FLEXIO1_FLEXIO17 IOMUX_PADCFG(0x0054, 0x7, 0x03ac, 0x0, 0x0204) +#define IOMUXC_PAD_GPIO_IO18_GPIO2_IO18 IOMUX_PADCFG(0x0058, 0x0, 0x0000, 0x0, 0x0208) +#define IOMUXC_PAD_GPIO_IO18_SAI3_RX_BCLK IOMUX_PADCFG(0x0058, 0x1, 0x044c, 0x0, 0x0208) +#define IOMUXC_PAD_GPIO_IO18_MEDIAMIX_CAM_DATA09 IOMUX_PADCFG(0x0058, 0x2, 0x0000, 0x0, 0x0208) +#define IOMUXC_PAD_GPIO_IO18_MEDIAMIX_DISP_DATA14 IOMUX_PADCFG(0x0058, 0x3, 0x0000, 0x0, 0x0208) +#define IOMUXC_PAD_GPIO_IO18_LPSPI5_PCS0 IOMUX_PADCFG(0x0058, 0x4, 0x0000, 0x0, 0x0208) +#define IOMUXC_PAD_GPIO_IO18_LPSPI4_PCS0 IOMUX_PADCFG(0x0058, 0x5, 0x0000, 0x0, 0x0208) +#define IOMUXC_PAD_GPIO_IO18_TPM5_CH2 IOMUX_PADCFG(0x0058, 0x6, 0x0000, 0x0, 0x0208) +#define IOMUXC_PAD_GPIO_IO18_FLEXIO1_FLEXIO18 IOMUX_PADCFG(0x0058, 0x7, 0x03b0, 0x0, 0x0208) +#define IOMUXC_PAD_GPIO_IO19_GPIO2_IO19 IOMUX_PADCFG(0x005c, 0x0, 0x0000, 0x0, 0x020c) +#define IOMUXC_PAD_GPIO_IO19_SAI3_RX_SYNC IOMUX_PADCFG(0x005c, 0x1, 0x0450, 0x1, 0x020c) +#define IOMUXC_PAD_GPIO_IO19_PDM_BIT_STREAM03 IOMUX_PADCFG(0x005c, 0x2, 0x0444, 0x1, 0x020c) +#define IOMUXC_PAD_GPIO_IO19_MEDIAMIX_DISP_DATA15 IOMUX_PADCFG(0x005c, 0x3, 0x0000, 0x0, 0x020c) +#define IOMUXC_PAD_GPIO_IO19_LPSPI5_SIN IOMUX_PADCFG(0x005c, 0x4, 0x0000, 0x0, 0x020c) +#define IOMUXC_PAD_GPIO_IO19_LPSPI4_SIN IOMUX_PADCFG(0x005c, 0x5, 0x0000, 0x0, 0x020c) +#define IOMUXC_PAD_GPIO_IO19_TPM6_CH2 IOMUX_PADCFG(0x005c, 0x6, 0x0000, 0x0, 0x020c) +#define IOMUXC_PAD_GPIO_IO19_SAI3_TX_DATA00 IOMUX_PADCFG(0x005c, 0x7, 0x0000, 0x0, 0x020c) +#define IOMUXC_PAD_GPIO_IO20_GPIO2_IO20 IOMUX_PADCFG(0x0060, 0x0, 0x0000, 0x0, 0x0210) +#define IOMUXC_PAD_GPIO_IO20_SAI3_RX_DATA00 IOMUX_PADCFG(0x0060, 0x1, 0x0000, 0x0, 0x0210) +#define IOMUXC_PAD_GPIO_IO20_PDM_BIT_STREAM00 IOMUX_PADCFG(0x0060, 0x2, 0x0438, 0x1, 0x0210) +#define IOMUXC_PAD_GPIO_IO20_MEDIAMIX_DISP_DATA16 IOMUX_PADCFG(0x0060, 0x3, 0x0000, 0x0, 0x0210) +#define IOMUXC_PAD_GPIO_IO20_LPSPI5_SOUT IOMUX_PADCFG(0x0060, 0x4, 0x0000, 0x0, 0x0210) +#define IOMUXC_PAD_GPIO_IO20_LPSPI4_SOUT IOMUX_PADCFG(0x0060, 0x5, 0x0000, 0x0, 0x0210) +#define IOMUXC_PAD_GPIO_IO20_TPM3_CH1 IOMUX_PADCFG(0x0060, 0x6, 0x0000, 0x0, 0x0210) +#define IOMUXC_PAD_GPIO_IO20_FLEXIO1_FLEXIO20 IOMUX_PADCFG(0x0060, 0x7, 0x03b4, 0x0, 0x0210) +#define IOMUXC_PAD_GPIO_IO21_GPIO2_IO21 IOMUX_PADCFG(0x0064, 0x0, 0x0000, 0x0, 0x0214) +#define IOMUXC_PAD_GPIO_IO21_SAI3_TX_DATA00 IOMUX_PADCFG(0x0064, 0x1, 0x0000, 0x0, 0x0214) +#define IOMUXC_PAD_GPIO_IO21_PDM_CLK IOMUX_PADCFG(0x0064, 0x2, 0x0000, 0x0, 0x0214) +#define IOMUXC_PAD_GPIO_IO21_MEDIAMIX_DISP_DATA17 IOMUX_PADCFG(0x0064, 0x3, 0x0000, 0x0, 0x0214) +#define IOMUXC_PAD_GPIO_IO21_LPSPI5_SCK IOMUX_PADCFG(0x0064, 0x4, 0x0000, 0x0, 0x0214) +#define IOMUXC_PAD_GPIO_IO21_LPSPI4_SCK IOMUX_PADCFG(0x0064, 0x5, 0x0000, 0x0, 0x0214) +#define IOMUXC_PAD_GPIO_IO21_TPM4_CH1 IOMUX_PADCFG(0x0064, 0x6, 0x0000, 0x0, 0x0214) +#define IOMUXC_PAD_GPIO_IO21_SAI3_RX_BCLK IOMUX_PADCFG(0x0064, 0x7, 0x044c, 0x1, 0x0214) +#define IOMUXC_PAD_GPIO_IO22_GPIO2_IO22 IOMUX_PADCFG(0x0068, 0x0, 0x0000, 0x0, 0x0218) +#define IOMUXC_PAD_GPIO_IO22_USDHC3_CLK IOMUX_PADCFG(0x0068, 0x1, 0x0458, 0x0, 0x0218) +#define IOMUXC_PAD_GPIO_IO22_SPDIF_IN IOMUX_PADCFG(0x0068, 0x2, 0x0454, 0x0, 0x0218) +#define IOMUXC_PAD_GPIO_IO22_MEDIAMIX_DISP_DATA18 IOMUX_PADCFG(0x0068, 0x3, 0x0000, 0x0, 0x0218) +#define IOMUXC_PAD_GPIO_IO22_TPM5_CH1 IOMUX_PADCFG(0x0068, 0x4, 0x0000, 0x0, 0x0218) +#define IOMUXC_PAD_GPIO_IO22_TPM6_EXTCLK IOMUX_PADCFG(0x0068, 0x5, 0x0000, 0x0, 0x0218) +#define IOMUXC_PAD_GPIO_IO22_LPI2C5_SDA IOMUX_PADCFG(0x0068, 0x6, 0x03ec, 0x1, 0x0218) +#define IOMUXC_PAD_GPIO_IO22_FLEXIO1_FLEXIO22 IOMUX_PADCFG(0x0068, 0x7, 0x03b8, 0x0, 0x0218) +#define IOMUXC_PAD_GPIO_IO23_GPIO2_IO23 IOMUX_PADCFG(0x006c, 0x0, 0x0000, 0x0, 0x021c) +#define IOMUXC_PAD_GPIO_IO23_USDHC3_CMD IOMUX_PADCFG(0x006c, 0x1, 0x045c, 0x0, 0x021c) +#define IOMUXC_PAD_GPIO_IO23_SPDIF_OUT IOMUX_PADCFG(0x006c, 0x2, 0x0000, 0x0, 0x021c) +#define IOMUXC_PAD_GPIO_IO23_MEDIAMIX_DISP_DATA19 IOMUX_PADCFG(0x006c, 0x3, 0x0000, 0x0, 0x021c) +#define IOMUXC_PAD_GPIO_IO23_TPM6_CH1 IOMUX_PADCFG(0x006c, 0x4, 0x0000, 0x0, 0x021c) +#define IOMUXC_PAD_GPIO_IO23_LPI2C5_SCL IOMUX_PADCFG(0x006c, 0x6, 0x03e8, 0x1, 0x021c) +#define IOMUXC_PAD_GPIO_IO23_FLEXIO1_FLEXIO23 IOMUX_PADCFG(0x006c, 0x7, 0x03bc, 0x0, 0x021c) +#define IOMUXC_PAD_GPIO_IO24_GPIO2_IO24 IOMUX_PADCFG(0x0070, 0x0, 0x0000, 0x0, 0x0220) +#define IOMUXC_PAD_GPIO_IO24_USDHC3_DATA0 IOMUX_PADCFG(0x0070, 0x1, 0x0460, 0x0, 0x0220) +#define IOMUXC_PAD_GPIO_IO24_MEDIAMIX_DISP_DATA20 IOMUX_PADCFG(0x0070, 0x3, 0x0000, 0x0, 0x0220) +#define IOMUXC_PAD_GPIO_IO24_TPM3_CH3 IOMUX_PADCFG(0x0070, 0x4, 0x0000, 0x0, 0x0220) +#define IOMUXC_PAD_GPIO_IO24_JTAG_MUX_TDO IOMUX_PADCFG(0x0070, 0x5, 0x0000, 0x0, 0x0220) +#define IOMUXC_PAD_GPIO_IO24_LPSPI6_PCS1 IOMUX_PADCFG(0x0070, 0x6, 0x0000, 0x0, 0x0220) +#define IOMUXC_PAD_GPIO_IO24_FLEXIO1_FLEXIO24 IOMUX_PADCFG(0x0070, 0x7, 0x03c0, 0x0, 0x0220) +#define IOMUXC_PAD_GPIO_IO25_GPIO2_IO25 IOMUX_PADCFG(0x0074, 0x0, 0x0000, 0x0, 0x0224) +#define IOMUXC_PAD_GPIO_IO25_USDHC3_DATA1 IOMUX_PADCFG(0x0074, 0x1, 0x0464, 0x0, 0x0224) +#define IOMUXC_PAD_GPIO_IO25_CAN2_TX IOMUX_PADCFG(0x0074, 0x2, 0x0000, 0x0, 0x0224) +#define IOMUXC_PAD_GPIO_IO25_MEDIAMIX_DISP_DATA21 IOMUX_PADCFG(0x0074, 0x3, 0x0000, 0x0, 0x0224) +#define IOMUXC_PAD_GPIO_IO25_TPM4_CH3 IOMUX_PADCFG(0x0074, 0x4, 0x0000, 0x0, 0x0224) +#define IOMUXC_PAD_GPIO_IO25_JTAG_MUX_TCK IOMUX_PADCFG(0x0074, 0x5, 0x03d4, 0x1, 0x0224) +#define IOMUXC_PAD_GPIO_IO25_LPSPI7_PCS1 IOMUX_PADCFG(0x0074, 0x6, 0x0000, 0x0, 0x0224) +#define IOMUXC_PAD_GPIO_IO25_FLEXIO1_FLEXIO25 IOMUX_PADCFG(0x0074, 0x7, 0x03c4, 0x0, 0x0224) +#define IOMUXC_PAD_GPIO_IO26_GPIO2_IO26 IOMUX_PADCFG(0x0078, 0x0, 0x0000, 0x0, 0x0228) +#define IOMUXC_PAD_GPIO_IO26_USDHC3_DATA2 IOMUX_PADCFG(0x0078, 0x1, 0x0468, 0x0, 0x0228) +#define IOMUXC_PAD_GPIO_IO26_PDM_BIT_STREAM01 IOMUX_PADCFG(0x0078, 0x2, 0x043c, 0x1, 0x0228) +#define IOMUXC_PAD_GPIO_IO26_MEDIAMIX_DISP_DATA22 IOMUX_PADCFG(0x0078, 0x3, 0x0000, 0x0, 0x0228) +#define IOMUXC_PAD_GPIO_IO26_TPM5_CH3 IOMUX_PADCFG(0x0078, 0x4, 0x0000, 0x0, 0x0228) +#define IOMUXC_PAD_GPIO_IO26_JTAG_MUX_TDI IOMUX_PADCFG(0x0078, 0x5, 0x03d8, 0x1, 0x0228) +#define IOMUXC_PAD_GPIO_IO26_LPSPI8_PCS1 IOMUX_PADCFG(0x0078, 0x6, 0x0000, 0x0, 0x0228) +#define IOMUXC_PAD_GPIO_IO26_SAI3_TX_SYNC IOMUX_PADCFG(0x0078, 0x7, 0x0000, 0x0, 0x0228) +#define IOMUXC_PAD_GPIO_IO27_GPIO2_IO27 IOMUX_PADCFG(0x007c, 0x0, 0x0000, 0x0, 0x022c) +#define IOMUXC_PAD_GPIO_IO27_USDHC3_DATA3 IOMUX_PADCFG(0x007c, 0x1, 0x046c, 0x0, 0x022c) +#define IOMUXC_PAD_GPIO_IO27_CAN2_RX IOMUX_PADCFG(0x007c, 0x2, 0x0364, 0x1, 0x022c) +#define IOMUXC_PAD_GPIO_IO27_MEDIAMIX_DISP_DATA23 IOMUX_PADCFG(0x007c, 0x3, 0x0000, 0x0, 0x022c) +#define IOMUXC_PAD_GPIO_IO27_TPM6_CH3 IOMUX_PADCFG(0x007c, 0x4, 0x0000, 0x0, 0x022c) +#define IOMUXC_PAD_GPIO_IO27_JTAG_MUX_TMS IOMUX_PADCFG(0x007c, 0x5, 0x03dc, 0x1, 0x022c) +#define IOMUXC_PAD_GPIO_IO27_LPSPI5_PCS1 IOMUX_PADCFG(0x007c, 0x6, 0x0000, 0x0, 0x022c) +#define IOMUXC_PAD_GPIO_IO27_FLEXIO1_FLEXIO27 IOMUX_PADCFG(0x007c, 0x7, 0x03c8, 0x0, 0x022c) +#define IOMUXC_PAD_GPIO_IO28_GPIO2_IO28 IOMUX_PADCFG(0x0080, 0x0, 0x0000, 0x0, 0x0230) +#define IOMUXC_PAD_GPIO_IO28_LPI2C3_SDA IOMUX_PADCFG(0x0080, 0x1, 0x03e4, 0x1, 0x0230) +#define IOMUXC_PAD_GPIO_IO28_FLEXIO1_FLEXIO28 IOMUX_PADCFG(0x0080, 0x7, 0x0000, 0x0, 0x0230) +#define IOMUXC_PAD_GPIO_IO29_GPIO2_IO29 IOMUX_PADCFG(0x0084, 0x0, 0x0000, 0x0, 0x0234) +#define IOMUXC_PAD_GPIO_IO29_LPI2C3_SCL IOMUX_PADCFG(0x0084, 0x1, 0x03e0, 0x1, 0x0234) +#define IOMUXC_PAD_GPIO_IO29_FLEXIO1_FLEXIO29 IOMUX_PADCFG(0x0084, 0x7, 0x0000, 0x0, 0x0234) +#define IOMUXC_PAD_CCM_CLKO1_CCMSRCGPCMIX_CLKO1 IOMUX_PADCFG(0x0088, 0x0, 0x0000, 0x0, 0x0238) +#define IOMUXC_PAD_CCM_CLKO1_FLEXIO1_FLEXIO26 IOMUX_PADCFG(0x0088, 0x4, 0x0000, 0x0, 0x0238) +#define IOMUXC_PAD_CCM_CLKO1_GPIO3_IO26 IOMUX_PADCFG(0x0088, 0x5, 0x0000, 0x0, 0x0238) +#define IOMUXC_PAD_CCM_CLKO2_GPIO3_IO27 IOMUX_PADCFG(0x008c, 0x5, 0x0000, 0x0, 0x023c) +#define IOMUXC_PAD_CCM_CLKO2_CCMSRCGPCMIX_CLKO2 IOMUX_PADCFG(0x008c, 0x0, 0x0000, 0x0, 0x023c) +#define IOMUXC_PAD_CCM_CLKO2_FLEXIO1_FLEXIO27 IOMUX_PADCFG(0x008c, 0x4, 0x03c8, 0x1, 0x023c) +#define IOMUXC_PAD_CCM_CLKO3_CCMSRCGPCMIX_CLKO3 IOMUX_PADCFG(0x0090, 0x0, 0x0000, 0x0, 0x0240) +#define IOMUXC_PAD_CCM_CLKO3_FLEXIO2_FLEXIO28 IOMUX_PADCFG(0x0090, 0x4, 0x0000, 0x0, 0x0240) +#define IOMUXC_PAD_CCM_CLKO3_GPIO4_IO28 IOMUX_PADCFG(0x0090, 0x5, 0x0000, 0x0, 0x0240) +#define IOMUXC_PAD_CCM_CLKO4_CCMSRCGPCMIX_CLKO4 IOMUX_PADCFG(0x0094, 0x0, 0x0000, 0x0, 0x0244) +#define IOMUXC_PAD_CCM_CLKO4_FLEXIO2_FLEXIO29 IOMUX_PADCFG(0x0094, 0x4, 0x0000, 0x0, 0x0244) +#define IOMUXC_PAD_CCM_CLKO4_GPIO4_IO29 IOMUX_PADCFG(0x0094, 0x5, 0x0000, 0x0, 0x0244) +#define IOMUXC_PAD_ENET1_MDC_ENET_QOS_MDC IOMUX_PADCFG(0x0098, 0x0, 0x0000, 0x0, 0x0248) +#define IOMUXC_PAD_ENET1_MDC_LPUART3_DCB_B IOMUX_PADCFG(0x0098, 0x1, 0x0000, 0x0, 0x0248) +#define IOMUXC_PAD_ENET1_MDC_I3C2_SCL IOMUX_PADCFG(0x0098, 0x2, 0x03cc, 0x0, 0x0248) +#define IOMUXC_PAD_ENET1_MDC_HSIOMIX_OTG_ID1 IOMUX_PADCFG(0x0098, 0x3, 0x0000, 0x0, 0x0248) +#define IOMUXC_PAD_ENET1_MDC_FLEXIO2_FLEXIO00 IOMUX_PADCFG(0x0098, 0x4, 0x0000, 0x0, 0x0248) +#define IOMUXC_PAD_ENET1_MDC_GPIO4_IO00 IOMUX_PADCFG(0x0098, 0x5, 0x0000, 0x0, 0x0248) +#define IOMUXC_PAD_ENET1_MDIO_ENET_QOS_MDIO IOMUX_PADCFG(0x009c, 0x0, 0x0000, 0x0, 0x024c) +#define IOMUXC_PAD_ENET1_MDIO_LPUART3_RIN_B IOMUX_PADCFG(0x009c, 0x1, 0x0000, 0x0, 0x024c) +#define IOMUXC_PAD_ENET1_MDIO_I3C2_SDA IOMUX_PADCFG(0x009c, 0x2, 0x03d0, 0x0, 0x024c) +#define IOMUXC_PAD_ENET1_MDIO_HSIOMIX_OTG_PWR1 IOMUX_PADCFG(0x009c, 0x3, 0x0000, 0x0, 0x024c) +#define IOMUXC_PAD_ENET1_MDIO_FLEXIO2_FLEXIO01 IOMUX_PADCFG(0x009c, 0x4, 0x0000, 0x0, 0x024c) +#define IOMUXC_PAD_ENET1_MDIO_GPIO4_IO01 IOMUX_PADCFG(0x009c, 0x5, 0x0000, 0x0, 0x024c) +#define IOMUXC_PAD_ENET1_TD3_ENET_QOS_RGMII_TD3 IOMUX_PADCFG(0x00a0, 0x0, 0x0000, 0x0, 0x0250) +#define IOMUXC_PAD_ENET1_TD3_CAN2_TX IOMUX_PADCFG(0x00a0, 0x2, 0x0000, 0x0, 0x0250) +#define IOMUXC_PAD_ENET1_TD3_HSIOMIX_OTG_ID2 IOMUX_PADCFG(0x00a0, 0x3, 0x0000, 0x0, 0x0250) +#define IOMUXC_PAD_ENET1_TD3_FLEXIO2_FLEXIO02 IOMUX_PADCFG(0x00a0, 0x4, 0x0000, 0x0, 0x0250) +#define IOMUXC_PAD_ENET1_TD3_GPIO4_IO02 IOMUX_PADCFG(0x00a0, 0x5, 0x0000, 0x0, 0x0250) +#define IOMUXC_PAD_ENET1_TD2_ENET_QOS_RGMII_TD2 IOMUX_PADCFG(0x00a4, 0x0, 0x0000, 0x0, 0x0254) +#define IOMUXC_PAD_ENET1_TD2_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK IOMUX_PADCFG(0x00a4, 0x1, 0x0000, 0x0, 0x0254) +#define IOMUXC_PAD_ENET1_TD2_CAN2_RX IOMUX_PADCFG(0x00a4, 0x2, 0x0364, 0x2, 0x0254) +#define IOMUXC_PAD_ENET1_TD2_HSIOMIX_OTG_OC2 IOMUX_PADCFG(0x00a4, 0x3, 0x0000, 0x0, 0x0254) +#define IOMUXC_PAD_ENET1_TD2_FLEXIO2_FLEXIO03 IOMUX_PADCFG(0x00a4, 0x4, 0x0000, 0x0, 0x0254) +#define IOMUXC_PAD_ENET1_TD2_GPIO4_IO03 IOMUX_PADCFG(0x00a4, 0x5, 0x0000, 0x0, 0x0254) +#define IOMUXC_PAD_ENET1_TD1_ENET_QOS_RGMII_TD1 IOMUX_PADCFG(0x00a8, 0x0, 0x0000, 0x0, 0x0258) +#define IOMUXC_PAD_ENET1_TD1_LPUART3_RTS_B IOMUX_PADCFG(0x00a8, 0x1, 0x0000, 0x0, 0x0258) +#define IOMUXC_PAD_ENET1_TD1_I3C2_PUR IOMUX_PADCFG(0x00a8, 0x2, 0x0000, 0x0, 0x0258) +#define IOMUXC_PAD_ENET1_TD1_HSIOMIX_OTG_OC1 IOMUX_PADCFG(0x00a8, 0x3, 0x0000, 0x0, 0x0258) +#define IOMUXC_PAD_ENET1_TD1_FLEXIO2_FLEXIO04 IOMUX_PADCFG(0x00a8, 0x4, 0x0000, 0x0, 0x0258) +#define IOMUXC_PAD_ENET1_TD1_GPIO4_IO04 IOMUX_PADCFG(0x00a8, 0x5, 0x0000, 0x0, 0x0258) +#define IOMUXC_PAD_ENET1_TD1_I3C2_PUR_B IOMUX_PADCFG(0x00a8, 0x6, 0x0000, 0x0, 0x0258) +#define IOMUXC_PAD_ENET1_TD0_ENET_QOS_RGMII_TD0 IOMUX_PADCFG(0x00ac, 0x0, 0x0000, 0x0, 0x025c) +#define IOMUXC_PAD_ENET1_TD0_LPUART3_TX IOMUX_PADCFG(0x00ac, 0x1, 0x041c, 0x1, 0x025c) +#define IOMUXC_PAD_ENET1_TD0_FLEXIO2_FLEXIO05 IOMUX_PADCFG(0x00ac, 0x4, 0x0000, 0x0, 0x025c) +#define IOMUXC_PAD_ENET1_TD0_GPIO4_IO05 IOMUX_PADCFG(0x00ac, 0x5, 0x0000, 0x0, 0x025c) +#define IOMUXC_PAD_ENET1_TX_CTL_ENET_QOS_RGMII_TX_CTL IOMUX_PADCFG(0x00b0, 0x0, 0x0000, 0x0, 0x0260) +#define IOMUXC_PAD_ENET1_TX_CTL_LPUART3_DTR_B IOMUX_PADCFG(0x00b0, 0x1, 0x0000, 0x0, 0x0260) +#define IOMUXC_PAD_ENET1_TX_CTL_FLEXIO2_FLEXIO06 IOMUX_PADCFG(0x00b0, 0x4, 0x0000, 0x0, 0x0260) +#define IOMUXC_PAD_ENET1_TX_CTL_GPIO4_IO06 IOMUX_PADCFG(0x00b0, 0x5, 0x0000, 0x0, 0x0260) +#define IOMUXC_PAD_ENET1_TXC_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK IOMUX_PADCFG(0x00b4, 0x0, 0x0000, 0x0, 0x0264) +#define IOMUXC_PAD_ENET1_TXC_ENET_QOS_TX_ER IOMUX_PADCFG(0x00b4, 0x1, 0x0000, 0x0, 0x0264) +#define IOMUXC_PAD_ENET1_TXC_FLEXIO2_FLEXIO07 IOMUX_PADCFG(0x00b4, 0x4, 0x0000, 0x0, 0x0264) +#define IOMUXC_PAD_ENET1_TXC_GPIO4_IO07 IOMUX_PADCFG(0x00b4, 0x5, 0x0000, 0x0, 0x0264) +#define IOMUXC_PAD_ENET1_RX_CTL_ENET_QOS_RGMII_RX_CTL IOMUX_PADCFG(0x00b8, 0x0, 0x0000, 0x0, 0x0268) +#define IOMUXC_PAD_ENET1_RX_CTL_LPUART3_DSR_B IOMUX_PADCFG(0x00b8, 0x1, 0x0000, 0x0, 0x0268) +#define IOMUXC_PAD_ENET1_RX_CTL_HSIOMIX_OTG_PWR2 IOMUX_PADCFG(0x00b8, 0x3, 0x0000, 0x0, 0x0268) +#define IOMUXC_PAD_ENET1_RX_CTL_FLEXIO2_FLEXIO08 IOMUX_PADCFG(0x00b8, 0x4, 0x0000, 0x0, 0x0268) +#define IOMUXC_PAD_ENET1_RX_CTL_GPIO4_IO08 IOMUX_PADCFG(0x00b8, 0x5, 0x0000, 0x0, 0x0268) +#define IOMUXC_PAD_ENET1_RXC_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK IOMUX_PADCFG(0x00bc, 0x0, 0x0000, 0x0, 0x026c) +#define IOMUXC_PAD_ENET1_RXC_ENET_QOS_RX_ER IOMUX_PADCFG(0x00bc, 0x1, 0x0000, 0x0, 0x026c) +#define IOMUXC_PAD_ENET1_RXC_FLEXIO2_FLEXIO09 IOMUX_PADCFG(0x00bc, 0x4, 0x0000, 0x0, 0x026c) +#define IOMUXC_PAD_ENET1_RXC_GPIO4_IO09 IOMUX_PADCFG(0x00bc, 0x5, 0x0000, 0x0, 0x026c) +#define IOMUXC_PAD_ENET1_RD0_ENET_QOS_RGMII_RD0 IOMUX_PADCFG(0x00c0, 0x0, 0x0000, 0x0, 0x0270) +#define IOMUXC_PAD_ENET1_RD0_LPUART3_RX IOMUX_PADCFG(0x00c0, 0x1, 0x0418, 0x1, 0x0270) +#define IOMUXC_PAD_ENET1_RD0_FLEXIO2_FLEXIO10 IOMUX_PADCFG(0x00c0, 0x4, 0x0000, 0x0, 0x0270) +#define IOMUXC_PAD_ENET1_RD0_GPIO4_IO10 IOMUX_PADCFG(0x00c0, 0x5, 0x0000, 0x0, 0x0270) +#define IOMUXC_PAD_ENET1_RD1_ENET_QOS_RGMII_RD1 IOMUX_PADCFG(0x00c4, 0x0, 0x0000, 0x0, 0x0274) +#define IOMUXC_PAD_ENET1_RD1_LPUART3_CTS_B IOMUX_PADCFG(0x00c4, 0x1, 0x0414, 0x1, 0x0274) +#define IOMUXC_PAD_ENET1_RD1_LPTMR2_ALT1 IOMUX_PADCFG(0x00c4, 0x3, 0x0408, 0x0, 0x0274) +#define IOMUXC_PAD_ENET1_RD1_FLEXIO2_FLEXIO11 IOMUX_PADCFG(0x00c4, 0x4, 0x0000, 0x0, 0x0274) +#define IOMUXC_PAD_ENET1_RD1_GPIO4_IO11 IOMUX_PADCFG(0x00c4, 0x5, 0x0000, 0x0, 0x0274) +#define IOMUXC_PAD_ENET1_RD2_ENET_QOS_RGMII_RD2 IOMUX_PADCFG(0x00c8, 0x0, 0x0000, 0x0, 0x0278) +#define IOMUXC_PAD_ENET1_RD2_LPTMR2_ALT2 IOMUX_PADCFG(0x00c8, 0x3, 0x040c, 0x0, 0x0278) +#define IOMUXC_PAD_ENET1_RD2_FLEXIO2_FLEXIO12 IOMUX_PADCFG(0x00c8, 0x4, 0x0000, 0x0, 0x0278) +#define IOMUXC_PAD_ENET1_RD2_GPIO4_IO12 IOMUX_PADCFG(0x00c8, 0x5, 0x0000, 0x0, 0x0278) +#define IOMUXC_PAD_ENET1_RD3_ENET_QOS_RGMII_RD3 IOMUX_PADCFG(0x00cc, 0x0, 0x0000, 0x0, 0x027c) +#define IOMUXC_PAD_ENET1_RD3_FLEXSPI1_TESTER_TRIGGER IOMUX_PADCFG(0x00cc, 0x2, 0x0000, 0x0, 0x027c) +#define IOMUXC_PAD_ENET1_RD3_LPTMR2_ALT3 IOMUX_PADCFG(0x00cc, 0x3, 0x0410, 0x0, 0x027c) +#define IOMUXC_PAD_ENET1_RD3_FLEXIO2_FLEXIO13 IOMUX_PADCFG(0x00cc, 0x4, 0x0000, 0x0, 0x027c) +#define IOMUXC_PAD_ENET1_RD3_GPIO4_IO13 IOMUX_PADCFG(0x00cc, 0x5, 0x0000, 0x0, 0x027c) +#define IOMUXC_PAD_ENET2_MDC_ENET1_MDC IOMUX_PADCFG(0x00d0, 0x0, 0x0000, 0x0, 0x0280) +#define IOMUXC_PAD_ENET2_MDC_LPUART4_DCB_B IOMUX_PADCFG(0x00d0, 0x1, 0x0000, 0x0, 0x0280) +#define IOMUXC_PAD_ENET2_MDC_SAI2_RX_SYNC IOMUX_PADCFG(0x00d0, 0x2, 0x0000, 0x0, 0x0280) +#define IOMUXC_PAD_ENET2_MDC_FLEXIO2_FLEXIO14 IOMUX_PADCFG(0x00d0, 0x4, 0x0000, 0x0, 0x0280) +#define IOMUXC_PAD_ENET2_MDC_GPIO4_IO14 IOMUX_PADCFG(0x00d0, 0x5, 0x0000, 0x0, 0x0280) +#define IOMUXC_PAD_ENET2_MDIO_ENET1_MDIO IOMUX_PADCFG(0x00d4, 0x0, 0x0000, 0x0, 0x0284) +#define IOMUXC_PAD_ENET2_MDIO_LPUART4_RIN_B IOMUX_PADCFG(0x00d4, 0x1, 0x0000, 0x0, 0x0284) +#define IOMUXC_PAD_ENET2_MDIO_SAI2_RX_BCLK IOMUX_PADCFG(0x00d4, 0x2, 0x0000, 0x0, 0x0284) +#define IOMUXC_PAD_ENET2_MDIO_FLEXIO2_FLEXIO15 IOMUX_PADCFG(0x00d4, 0x4, 0x0000, 0x0, 0x0284) +#define IOMUXC_PAD_ENET2_MDIO_GPIO4_IO15 IOMUX_PADCFG(0x00d4, 0x5, 0x0000, 0x0, 0x0284) +#define IOMUXC_PAD_ENET2_TD3_SAI2_RX_DATA00 IOMUX_PADCFG(0x00d8, 0x2, 0x0000, 0x0, 0x0288) +#define IOMUXC_PAD_ENET2_TD3_FLEXIO2_FLEXIO16 IOMUX_PADCFG(0x00d8, 0x4, 0x0000, 0x0, 0x0288) +#define IOMUXC_PAD_ENET2_TD3_GPIO4_IO16 IOMUX_PADCFG(0x00d8, 0x5, 0x0000, 0x0, 0x0288) +#define IOMUXC_PAD_ENET2_TD3_ENET1_RGMII_TD3 IOMUX_PADCFG(0x00d8, 0x0, 0x0000, 0x0, 0x0288) +#define IOMUXC_PAD_ENET2_TD2_ENET1_RGMII_TD2 IOMUX_PADCFG(0x00dc, 0x0, 0x0000, 0x0, 0x028c) +#define IOMUXC_PAD_ENET2_TD2_ENET1_TX_CLK IOMUX_PADCFG(0x00dc, 0x1, 0x0000, 0x0, 0x028c) +#define IOMUXC_PAD_ENET2_TD2_SAI2_RX_DATA01 IOMUX_PADCFG(0x00dc, 0x2, 0x0000, 0x0, 0x028c) +#define IOMUXC_PAD_ENET2_TD2_FLEXIO2_FLEXIO17 IOMUX_PADCFG(0x00dc, 0x4, 0x0000, 0x0, 0x028c) +#define IOMUXC_PAD_ENET2_TD2_GPIO4_IO17 IOMUX_PADCFG(0x00dc, 0x5, 0x0000, 0x0, 0x028c) +#define IOMUXC_PAD_ENET2_TD1_ENET1_RGMII_TD1 IOMUX_PADCFG(0x00e0, 0x0, 0x0000, 0x0, 0x0290) +#define IOMUXC_PAD_ENET2_TD1_LPUART4_RTS_B IOMUX_PADCFG(0x00e0, 0x1, 0x0000, 0x0, 0x0290) +#define IOMUXC_PAD_ENET2_TD1_SAI2_RX_DATA02 IOMUX_PADCFG(0x00e0, 0x2, 0x0000, 0x0, 0x0290) +#define IOMUXC_PAD_ENET2_TD1_FLEXIO2_FLEXIO18 IOMUX_PADCFG(0x00e0, 0x4, 0x0000, 0x0, 0x0290) +#define IOMUXC_PAD_ENET2_TD1_GPIO4_IO18 IOMUX_PADCFG(0x00e0, 0x5, 0x0000, 0x0, 0x0290) +#define IOMUXC_PAD_ENET2_TD0_ENET1_RGMII_TD0 IOMUX_PADCFG(0x00e4, 0x0, 0x0000, 0x0, 0x0294) +#define IOMUXC_PAD_ENET2_TD0_LPUART4_TX IOMUX_PADCFG(0x00e4, 0x1, 0x0428, 0x1, 0x0294) +#define IOMUXC_PAD_ENET2_TD0_SAI2_RX_DATA03 IOMUX_PADCFG(0x00e4, 0x2, 0x0000, 0x0, 0x0294) +#define IOMUXC_PAD_ENET2_TD0_FLEXIO2_FLEXIO19 IOMUX_PADCFG(0x00e4, 0x4, 0x0000, 0x0, 0x0294) +#define IOMUXC_PAD_ENET2_TD0_GPIO4_IO19 IOMUX_PADCFG(0x00e4, 0x5, 0x0000, 0x0, 0x0294) +#define IOMUXC_PAD_ENET2_TX_CTL_ENET1_RGMII_TX_CTL IOMUX_PADCFG(0x00e8, 0x0, 0x0000, 0x0, 0x0298) +#define IOMUXC_PAD_ENET2_TX_CTL_LPUART4_DTR_B IOMUX_PADCFG(0x00e8, 0x1, 0x0000, 0x0, 0x0298) +#define IOMUXC_PAD_ENET2_TX_CTL_SAI2_TX_SYNC IOMUX_PADCFG(0x00e8, 0x2, 0x0000, 0x0, 0x0298) +#define IOMUXC_PAD_ENET2_TX_CTL_FLEXIO2_FLEXIO20 IOMUX_PADCFG(0x00e8, 0x4, 0x0000, 0x0, 0x0298) +#define IOMUXC_PAD_ENET2_TX_CTL_GPIO4_IO20 IOMUX_PADCFG(0x00e8, 0x5, 0x0000, 0x0, 0x0298) +#define IOMUXC_PAD_ENET2_TXC_ENET1_RGMII_TXC IOMUX_PADCFG(0x00ec, 0x0, 0x0000, 0x0, 0x029c) +#define IOMUXC_PAD_ENET2_TXC_ENET1_TX_ER IOMUX_PADCFG(0x00ec, 0x1, 0x0000, 0x0, 0x029c) +#define IOMUXC_PAD_ENET2_TXC_SAI2_TX_BCLK IOMUX_PADCFG(0x00ec, 0x2, 0x0000, 0x0, 0x029c) +#define IOMUXC_PAD_ENET2_TXC_FLEXIO2_FLEXIO21 IOMUX_PADCFG(0x00ec, 0x4, 0x0000, 0x0, 0x029c) +#define IOMUXC_PAD_ENET2_TXC_GPIO4_IO21 IOMUX_PADCFG(0x00ec, 0x5, 0x0000, 0x0, 0x029c) +#define IOMUXC_PAD_ENET2_RX_CTL_ENET1_RGMII_RX_CTL IOMUX_PADCFG(0x00f0, 0x0, 0x0000, 0x0, 0x02a0) +#define IOMUXC_PAD_ENET2_RX_CTL_LPUART4_DSR_B IOMUX_PADCFG(0x00f0, 0x1, 0x0000, 0x0, 0x02a0) +#define IOMUXC_PAD_ENET2_RX_CTL_SAI2_TX_DATA00 IOMUX_PADCFG(0x00f0, 0x2, 0x0000, 0x0, 0x02a0) +#define IOMUXC_PAD_ENET2_RX_CTL_FLEXIO2_FLEXIO22 IOMUX_PADCFG(0x00f0, 0x4, 0x0000, 0x0, 0x02a0) +#define IOMUXC_PAD_ENET2_RX_CTL_GPIO4_IO22 IOMUX_PADCFG(0x00f0, 0x5, 0x0000, 0x0, 0x02a0) +#define IOMUXC_PAD_ENET2_RXC_ENET1_RGMII_RXC IOMUX_PADCFG(0x00f4, 0x0, 0x0000, 0x0, 0x02a4) +#define IOMUXC_PAD_ENET2_RXC_ENET1_RX_ER IOMUX_PADCFG(0x00f4, 0x1, 0x0000, 0x0, 0x02a4) +#define IOMUXC_PAD_ENET2_RXC_SAI2_TX_DATA01 IOMUX_PADCFG(0x00f4, 0x2, 0x0000, 0x0, 0x02a4) +#define IOMUXC_PAD_ENET2_RXC_FLEXIO2_FLEXIO23 IOMUX_PADCFG(0x00f4, 0x4, 0x0000, 0x0, 0x02a4) +#define IOMUXC_PAD_ENET2_RXC_GPIO4_IO23 IOMUX_PADCFG(0x00f4, 0x5, 0x0000, 0x0, 0x02a4) +#define IOMUXC_PAD_ENET2_RD0_ENET1_RGMII_RD0 IOMUX_PADCFG(0x00f8, 0x0, 0x0000, 0x0, 0x02a8) +#define IOMUXC_PAD_ENET2_RD0_LPUART4_RX IOMUX_PADCFG(0x00f8, 0x1, 0x0424, 0x1, 0x02a8) +#define IOMUXC_PAD_ENET2_RD0_SAI2_TX_DATA02 IOMUX_PADCFG(0x00f8, 0x2, 0x0000, 0x0, 0x02a8) +#define IOMUXC_PAD_ENET2_RD0_FLEXIO2_FLEXIO24 IOMUX_PADCFG(0x00f8, 0x4, 0x0000, 0x0, 0x02a8) +#define IOMUXC_PAD_ENET2_RD0_GPIO4_IO24 IOMUX_PADCFG(0x00f8, 0x5, 0x0000, 0x0, 0x02a8) +#define IOMUXC_PAD_ENET2_RD1_ENET1_RGMII_RD1 IOMUX_PADCFG(0x00fc, 0x0, 0x0000, 0x0, 0x02ac) +#define IOMUXC_PAD_ENET2_RD1_SPDIF_IN IOMUX_PADCFG(0x00fc, 0x1, 0x0454, 0x1, 0x02ac) +#define IOMUXC_PAD_ENET2_RD1_SAI2_TX_DATA03 IOMUX_PADCFG(0x00fc, 0x2, 0x0000, 0x0, 0x02ac) +#define IOMUXC_PAD_ENET2_RD1_FLEXIO2_FLEXIO25 IOMUX_PADCFG(0x00fc, 0x4, 0x0000, 0x0, 0x02ac) +#define IOMUXC_PAD_ENET2_RD1_GPIO4_IO25 IOMUX_PADCFG(0x00fc, 0x5, 0x0000, 0x0, 0x02ac) +#define IOMUXC_PAD_ENET2_RD2_ENET1_RGMII_RD2 IOMUX_PADCFG(0x0100, 0x0, 0x0000, 0x0, 0x02b0) +#define IOMUXC_PAD_ENET2_RD2_LPUART4_CTS_B IOMUX_PADCFG(0x0100, 0x1, 0x0420, 0x1, 0x02b0) +#define IOMUXC_PAD_ENET2_RD2_SAI2_MCLK IOMUX_PADCFG(0x0100, 0x2, 0x0000, 0x0, 0x02b0) +#define IOMUXC_PAD_ENET2_RD2_MQS2_RIGHT IOMUX_PADCFG(0x0100, 0x3, 0x0000, 0x0, 0x02b0) +#define IOMUXC_PAD_ENET2_RD2_FLEXIO2_FLEXIO26 IOMUX_PADCFG(0x0100, 0x4, 0x0000, 0x0, 0x02b0) +#define IOMUXC_PAD_ENET2_RD2_GPIO4_IO26 IOMUX_PADCFG(0x0100, 0x5, 0x0000, 0x0, 0x02b0) +#define IOMUXC_PAD_ENET2_RD3_ENET1_RGMII_RD3 IOMUX_PADCFG(0x0104, 0x0, 0x0000, 0x0, 0x02b4) +#define IOMUXC_PAD_ENET2_RD3_SPDIF_OUT IOMUX_PADCFG(0x0104, 0x1, 0x0000, 0x0, 0x02b4) +#define IOMUXC_PAD_ENET2_RD3_SPDIF_IN IOMUX_PADCFG(0x0104, 0x2, 0x0454, 0x2, 0x02b4) +#define IOMUXC_PAD_ENET2_RD3_MQS2_LEFT IOMUX_PADCFG(0x0104, 0x3, 0x0000, 0x0, 0x02b4) +#define IOMUXC_PAD_ENET2_RD3_FLEXIO2_FLEXIO27 IOMUX_PADCFG(0x0104, 0x4, 0x0000, 0x0, 0x02b4) +#define IOMUXC_PAD_ENET2_RD3_GPIO4_IO27 IOMUX_PADCFG(0x0104, 0x5, 0x0000, 0x0, 0x02b4) +#define IOMUXC_PAD_SD1_CLK_FLEXIO1_FLEXIO08 IOMUX_PADCFG(0x0108, 0x4, 0x038c, 0x1, 0x02b8) +#define IOMUXC_PAD_SD1_CLK_GPIO3_IO08 IOMUX_PADCFG(0x0108, 0x5, 0x0000, 0x0, 0x02b8) +#define IOMUXC_PAD_SD1_CLK_USDHC1_CLK IOMUX_PADCFG(0x0108, 0x0, 0x0000, 0x0, 0x02b8) +#define IOMUXC_PAD_SD1_CMD_USDHC1_CMD IOMUX_PADCFG(0x010c, 0x0, 0x0000, 0x0, 0x02bc) +#define IOMUXC_PAD_SD1_CMD_FLEXIO1_FLEXIO09 IOMUX_PADCFG(0x010c, 0x4, 0x0390, 0x1, 0x02bc) +#define IOMUXC_PAD_SD1_CMD_GPIO3_IO09 IOMUX_PADCFG(0x010c, 0x5, 0x0000, 0x0, 0x02bc) +#define IOMUXC_PAD_SD1_DATA0_USDHC1_DATA0 IOMUX_PADCFG(0x0110, 0x0, 0x0000, 0x0, 0x02c0) +#define IOMUXC_PAD_SD1_DATA0_FLEXIO1_FLEXIO10 IOMUX_PADCFG(0x0110, 0x4, 0x0394, 0x1, 0x02c0) +#define IOMUXC_PAD_SD1_DATA0_GPIO3_IO10 IOMUX_PADCFG(0x0110, 0x5, 0x0000, 0x0, 0x02c0) +#define IOMUXC_PAD_SD1_DATA1_USDHC1_DATA1 IOMUX_PADCFG(0x0114, 0x0, 0x0000, 0x0, 0x02c4) +#define IOMUXC_PAD_SD1_DATA1_FLEXIO1_FLEXIO11 IOMUX_PADCFG(0x0114, 0x4, 0x0398, 0x1, 0x02c4) +#define IOMUXC_PAD_SD1_DATA1_GPIO3_IO11 IOMUX_PADCFG(0x0114, 0x5, 0x0000, 0x0, 0x02c4) +#define IOMUXC_PAD_SD1_DATA1_CCMSRCGPCMIX_INT_BOOT IOMUX_PADCFG(0x0114, 0x6, 0x0000, 0x0, 0x02c4) +#define IOMUXC_PAD_SD1_DATA2_USDHC1_DATA2 IOMUX_PADCFG(0x0118, 0x0, 0x0000, 0x0, 0x02c8) +#define IOMUXC_PAD_SD1_DATA2_FLEXIO1_FLEXIO12 IOMUX_PADCFG(0x0118, 0x4, 0x0000, 0x0, 0x02c8) +#define IOMUXC_PAD_SD1_DATA2_GPIO3_IO12 IOMUX_PADCFG(0x0118, 0x5, 0x0000, 0x0, 0x02c8) +#define IOMUXC_PAD_SD1_DATA2_CCMSRCGPCMIX_PMIC_READY IOMUX_PADCFG(0x0118, 0x6, 0x0000, 0x0, 0x02c8) +#define IOMUXC_PAD_SD1_DATA3_USDHC1_DATA3 IOMUX_PADCFG(0x011c, 0x0, 0x0000, 0x0, 0x02cc) +#define IOMUXC_PAD_SD1_DATA3_FLEXSPI1_A_SS1_B IOMUX_PADCFG(0x011c, 0x1, 0x0000, 0x0, 0x02cc) +#define IOMUXC_PAD_SD1_DATA3_FLEXIO1_FLEXIO13 IOMUX_PADCFG(0x011c, 0x4, 0x039c, 0x1, 0x02cc) +#define IOMUXC_PAD_SD1_DATA3_GPIO3_IO13 IOMUX_PADCFG(0x011c, 0x5, 0x0000, 0x0, 0x02cc) +#define IOMUXC_PAD_SD1_DATA4_USDHC1_DATA4 IOMUX_PADCFG(0x0120, 0x0, 0x0000, 0x0, 0x02d0) +#define IOMUXC_PAD_SD1_DATA4_FLEXSPI1_A_DATA04 IOMUX_PADCFG(0x0120, 0x1, 0x0000, 0x0, 0x02d0) +#define IOMUXC_PAD_SD1_DATA4_FLEXIO1_FLEXIO14 IOMUX_PADCFG(0x0120, 0x4, 0x03a0, 0x1, 0x02d0) +#define IOMUXC_PAD_SD1_DATA4_GPIO3_IO14 IOMUX_PADCFG(0x0120, 0x5, 0x0000, 0x0, 0x02d0) +#define IOMUXC_PAD_SD1_DATA5_USDHC1_DATA5 IOMUX_PADCFG(0x0124, 0x0, 0x0000, 0x0, 0x02d4) +#define IOMUXC_PAD_SD1_DATA5_FLEXSPI1_A_DATA05 IOMUX_PADCFG(0x0124, 0x1, 0x0000, 0x0, 0x02d4) +#define IOMUXC_PAD_SD1_DATA5_USDHC1_RESET_B IOMUX_PADCFG(0x0124, 0x2, 0x0000, 0x0, 0x02d4) +#define IOMUXC_PAD_SD1_DATA5_FLEXIO1_FLEXIO15 IOMUX_PADCFG(0x0124, 0x4, 0x03a4, 0x1, 0x02d4) +#define IOMUXC_PAD_SD1_DATA5_GPIO3_IO15 IOMUX_PADCFG(0x0124, 0x5, 0x0000, 0x0, 0x02d4) +#define IOMUXC_PAD_SD1_DATA6_USDHC1_DATA6 IOMUX_PADCFG(0x0128, 0x0, 0x0000, 0x0, 0x02d8) +#define IOMUXC_PAD_SD1_DATA6_FLEXSPI1_A_DATA06 IOMUX_PADCFG(0x0128, 0x1, 0x0000, 0x0, 0x02d8) +#define IOMUXC_PAD_SD1_DATA6_USDHC1_CD_B IOMUX_PADCFG(0x0128, 0x2, 0x0000, 0x0, 0x02d8) +#define IOMUXC_PAD_SD1_DATA6_FLEXIO1_FLEXIO16 IOMUX_PADCFG(0x0128, 0x4, 0x03a8, 0x1, 0x02d8) +#define IOMUXC_PAD_SD1_DATA6_GPIO3_IO16 IOMUX_PADCFG(0x0128, 0x5, 0x0000, 0x0, 0x02d8) +#define IOMUXC_PAD_SD1_DATA7_USDHC1_DATA7 IOMUX_PADCFG(0x012c, 0x0, 0x0000, 0x0, 0x02dc) +#define IOMUXC_PAD_SD1_DATA7_FLEXSPI1_A_DATA07 IOMUX_PADCFG(0x012c, 0x1, 0x0000, 0x0, 0x02dc) +#define IOMUXC_PAD_SD1_DATA7_USDHC1_WP IOMUX_PADCFG(0x012c, 0x2, 0x0000, 0x0, 0x02dc) +#define IOMUXC_PAD_SD1_DATA7_FLEXIO1_FLEXIO17 IOMUX_PADCFG(0x012c, 0x4, 0x03ac, 0x1, 0x02dc) +#define IOMUXC_PAD_SD1_DATA7_GPIO3_IO17 IOMUX_PADCFG(0x012c, 0x5, 0x0000, 0x0, 0x02dc) +#define IOMUXC_PAD_SD1_STROBE_USDHC1_STROBE IOMUX_PADCFG(0x0130, 0x0, 0x0000, 0x0, 0x02e0) +#define IOMUXC_PAD_SD1_STROBE_FLEXSPI1_A_DQS IOMUX_PADCFG(0x0130, 0x1, 0x0000, 0x0, 0x02e0) +#define IOMUXC_PAD_SD1_STROBE_FLEXIO1_FLEXIO18 IOMUX_PADCFG(0x0130, 0x4, 0x03b0, 0x1, 0x02e0) +#define IOMUXC_PAD_SD1_STROBE_GPIO3_IO18 IOMUX_PADCFG(0x0130, 0x5, 0x0000, 0x0, 0x02e0) +#define IOMUXC_PAD_SD2_VSELECT_USDHC2_VSELECT IOMUX_PADCFG(0x0134, 0x0, 0x0000, 0x0, 0x02e4) +#define IOMUXC_PAD_SD2_VSELECT_USDHC2_WP IOMUX_PADCFG(0x0134, 0x1, 0x0000, 0x0, 0x02e4) +#define IOMUXC_PAD_SD2_VSELECT_LPTMR2_ALT3 IOMUX_PADCFG(0x0134, 0x2, 0x0410, 0x1, 0x02e4) +#define IOMUXC_PAD_SD2_VSELECT_FLEXIO1_FLEXIO19 IOMUX_PADCFG(0x0134, 0x4, 0x0000, 0x0, 0x02e4) +#define IOMUXC_PAD_SD2_VSELECT_GPIO3_IO19 IOMUX_PADCFG(0x0134, 0x5, 0x0000, 0x0, 0x02e4) +#define IOMUXC_PAD_SD2_VSELECT_CCMSRCGPCMIX_EXT_CLK1 IOMUX_PADCFG(0x0134, 0x6, 0x0368, 0x0, 0x02e4) +#define IOMUXC_PAD_SD3_CLK_USDHC3_CLK IOMUX_PADCFG(0x0138, 0x0, 0x0458, 0x1, 0x02e8) +#define IOMUXC_PAD_SD3_CLK_FLEXSPI1_A_SCLK IOMUX_PADCFG(0x0138, 0x1, 0x0000, 0x0, 0x02e8) +#define IOMUXC_PAD_SD3_CLK_FLEXIO1_FLEXIO20 IOMUX_PADCFG(0x0138, 0x4, 0x03b4, 0x1, 0x02e8) +#define IOMUXC_PAD_SD3_CLK_GPIO3_IO20 IOMUX_PADCFG(0x0138, 0x5, 0x0000, 0x0, 0x02e8) +#define IOMUXC_PAD_SD3_CMD_USDHC3_CMD IOMUX_PADCFG(0x013c, 0x0, 0x045c, 0x1, 0x02ec) +#define IOMUXC_PAD_SD3_CMD_FLEXSPI1_A_SS0_B IOMUX_PADCFG(0x013c, 0x1, 0x0000, 0x0, 0x02ec) +#define IOMUXC_PAD_SD3_CMD_FLEXIO1_FLEXIO21 IOMUX_PADCFG(0x013c, 0x4, 0x0000, 0x0, 0x02ec) +#define IOMUXC_PAD_SD3_CMD_GPIO3_IO21 IOMUX_PADCFG(0x013c, 0x5, 0x0000, 0x0, 0x02ec) +#define IOMUXC_PAD_SD3_DATA0_USDHC3_DATA0 IOMUX_PADCFG(0x0140, 0x0, 0x0460, 0x1, 0x02f0) +#define IOMUXC_PAD_SD3_DATA0_FLEXSPI1_A_DATA00 IOMUX_PADCFG(0x0140, 0x1, 0x0000, 0x0, 0x02f0) +#define IOMUXC_PAD_SD3_DATA0_FLEXIO1_FLEXIO22 IOMUX_PADCFG(0x0140, 0x4, 0x03b8, 0x1, 0x02f0) +#define IOMUXC_PAD_SD3_DATA0_GPIO3_IO22 IOMUX_PADCFG(0x0140, 0x5, 0x0000, 0x0, 0x02f0) +#define IOMUXC_PAD_SD3_DATA1_USDHC3_DATA1 IOMUX_PADCFG(0x0144, 0x0, 0x0464, 0x1, 0x02f4) +#define IOMUXC_PAD_SD3_DATA1_FLEXSPI1_A_DATA01 IOMUX_PADCFG(0x0144, 0x1, 0x0000, 0x0, 0x02f4) +#define IOMUXC_PAD_SD3_DATA1_FLEXIO1_FLEXIO23 IOMUX_PADCFG(0x0144, 0x4, 0x03bc, 0x1, 0x02f4) +#define IOMUXC_PAD_SD3_DATA1_GPIO3_IO23 IOMUX_PADCFG(0x0144, 0x5, 0x0000, 0x0, 0x02f4) +#define IOMUXC_PAD_SD3_DATA2_USDHC3_DATA2 IOMUX_PADCFG(0x0148, 0x0, 0x0468, 0x1, 0x02f8) +#define IOMUXC_PAD_SD3_DATA2_FLEXSPI1_A_DATA02 IOMUX_PADCFG(0x0148, 0x1, 0x0000, 0x0, 0x02f8) +#define IOMUXC_PAD_SD3_DATA2_FLEXIO1_FLEXIO24 IOMUX_PADCFG(0x0148, 0x4, 0x03c0, 0x1, 0x02f8) +#define IOMUXC_PAD_SD3_DATA2_GPIO3_IO24 IOMUX_PADCFG(0x0148, 0x5, 0x0000, 0x0, 0x02f8) +#define IOMUXC_PAD_SD3_DATA3_USDHC3_DATA3 IOMUX_PADCFG(0x014c, 0x0, 0x046c, 0x1, 0x02fc) +#define IOMUXC_PAD_SD3_DATA3_FLEXSPI1_A_DATA03 IOMUX_PADCFG(0x014c, 0x1, 0x0000, 0x0, 0x02fc) +#define IOMUXC_PAD_SD3_DATA3_FLEXIO1_FLEXIO25 IOMUX_PADCFG(0x014c, 0x4, 0x03c4, 0x1, 0x02fc) +#define IOMUXC_PAD_SD3_DATA3_GPIO3_IO25 IOMUX_PADCFG(0x014c, 0x5, 0x0000, 0x0, 0x02fc) +#define IOMUXC_PAD_SD2_CD_B_USDHC2_CD_B IOMUX_PADCFG(0x0150, 0x0, 0x0000, 0x0, 0x0300) +#define IOMUXC_PAD_SD2_CD_B_ENET_QOS_1588_EVENT0_IN IOMUX_PADCFG(0x0150, 0x1, 0x0000, 0x0, 0x0300) +#define IOMUXC_PAD_SD2_CD_B_I3C2_SCL IOMUX_PADCFG(0x0150, 0x2, 0x03cc, 0x1, 0x0300) +#define IOMUXC_PAD_SD2_CD_B_FLEXIO1_FLEXIO00 IOMUX_PADCFG(0x0150, 0x4, 0x036c, 0x1, 0x0300) +#define IOMUXC_PAD_SD2_CD_B_GPIO3_IO00 IOMUX_PADCFG(0x0150, 0x5, 0x0000, 0x0, 0x0300) +#define IOMUXC_PAD_SD2_CLK_USDHC2_CLK IOMUX_PADCFG(0x0154, 0x0, 0x0000, 0x0, 0x0304) +#define IOMUXC_PAD_SD2_CLK_ENET_QOS_1588_EVENT0_OUT IOMUX_PADCFG(0x0154, 0x1, 0x0000, 0x0, 0x0304) +#define IOMUXC_PAD_SD2_CLK_I3C2_SDA IOMUX_PADCFG(0x0154, 0x2, 0x03d0, 0x1, 0x0304) +#define IOMUXC_PAD_SD2_CLK_FLEXIO1_FLEXIO01 IOMUX_PADCFG(0x0154, 0x4, 0x0370, 0x1, 0x0304) +#define IOMUXC_PAD_SD2_CLK_GPIO3_IO01 IOMUX_PADCFG(0x0154, 0x5, 0x0000, 0x0, 0x0304) +#define IOMUXC_PAD_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 IOMUX_PADCFG(0x0154, 0x6, 0x0000, 0x0, 0x0304) +#define IOMUXC_PAD_SD2_CMD_USDHC2_CMD IOMUX_PADCFG(0x0158, 0x0, 0x0000, 0x0, 0x0308) +#define IOMUXC_PAD_SD2_CMD_ENET1_1588_EVENT0_IN IOMUX_PADCFG(0x0158, 0x1, 0x0000, 0x0, 0x0308) +#define IOMUXC_PAD_SD2_CMD_I3C2_PUR IOMUX_PADCFG(0x0158, 0x2, 0x0000, 0x0, 0x0308) +#define IOMUXC_PAD_SD2_CMD_I3C2_PUR_B IOMUX_PADCFG(0x0158, 0x3, 0x0000, 0x0, 0x0308) +#define IOMUXC_PAD_SD2_CMD_FLEXIO1_FLEXIO02 IOMUX_PADCFG(0x0158, 0x4, 0x0374, 0x1, 0x0308) +#define IOMUXC_PAD_SD2_CMD_GPIO3_IO02 IOMUX_PADCFG(0x0158, 0x5, 0x0000, 0x0, 0x0308) +#define IOMUXC_PAD_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 IOMUX_PADCFG(0x0158, 0x6, 0x0000, 0x0, 0x0308) +#define IOMUXC_PAD_SD2_DATA0_USDHC2_DATA0 IOMUX_PADCFG(0x015c, 0x0, 0x0000, 0x0, 0x030c) +#define IOMUXC_PAD_SD2_DATA0_ENET1_1588_EVENT0_OUT IOMUX_PADCFG(0x015c, 0x1, 0x0000, 0x0, 0x030c) +#define IOMUXC_PAD_SD2_DATA0_CAN2_TX IOMUX_PADCFG(0x015c, 0x2, 0x0000, 0x0, 0x030c) +#define IOMUXC_PAD_SD2_DATA0_FLEXIO1_FLEXIO03 IOMUX_PADCFG(0x015c, 0x4, 0x0378, 0x1, 0x030c) +#define IOMUXC_PAD_SD2_DATA0_GPIO3_IO03 IOMUX_PADCFG(0x015c, 0x5, 0x0000, 0x0, 0x030c) +#define IOMUXC_PAD_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 IOMUX_PADCFG(0x015c, 0x6, 0x0000, 0x0, 0x030c) +#define IOMUXC_PAD_SD2_DATA1_USDHC2_DATA1 IOMUX_PADCFG(0x0160, 0x0, 0x0000, 0x0, 0x0310) +#define IOMUXC_PAD_SD2_DATA1_ENET1_1588_EVENT1_IN IOMUX_PADCFG(0x0160, 0x1, 0x0000, 0x0, 0x0310) +#define IOMUXC_PAD_SD2_DATA1_CAN2_RX IOMUX_PADCFG(0x0160, 0x2, 0x0364, 0x3, 0x0310) +#define IOMUXC_PAD_SD2_DATA1_FLEXIO1_FLEXIO04 IOMUX_PADCFG(0x0160, 0x4, 0x037c, 0x1, 0x0310) +#define IOMUXC_PAD_SD2_DATA1_GPIO3_IO04 IOMUX_PADCFG(0x0160, 0x5, 0x0000, 0x0, 0x0310) +#define IOMUXC_PAD_SD2_DATA1_CCMSRCGPCMIX_WAIT IOMUX_PADCFG(0x0160, 0x6, 0x0000, 0x0, 0x0310) +#define IOMUXC_PAD_SD2_DATA2_USDHC2_DATA2 IOMUX_PADCFG(0x0164, 0x0, 0x0000, 0x0, 0x0314) +#define IOMUXC_PAD_SD2_DATA2_ENET1_1588_EVENT1_OUT IOMUX_PADCFG(0x0164, 0x1, 0x0000, 0x0, 0x0314) +#define IOMUXC_PAD_SD2_DATA2_MQS2_RIGHT IOMUX_PADCFG(0x0164, 0x2, 0x0000, 0x0, 0x0314) +#define IOMUXC_PAD_SD2_DATA2_FLEXIO1_FLEXIO05 IOMUX_PADCFG(0x0164, 0x4, 0x0380, 0x1, 0x0314) +#define IOMUXC_PAD_SD2_DATA2_GPIO3_IO05 IOMUX_PADCFG(0x0164, 0x5, 0x0000, 0x0, 0x0314) +#define IOMUXC_PAD_SD2_DATA2_CCMSRCGPCMIX_STOP IOMUX_PADCFG(0x0164, 0x6, 0x0000, 0x0, 0x0314) +#define IOMUXC_PAD_SD2_DATA3_USDHC2_DATA3 IOMUX_PADCFG(0x0168, 0x0, 0x0000, 0x0, 0x0318) +#define IOMUXC_PAD_SD2_DATA3_LPTMR2_ALT1 IOMUX_PADCFG(0x0168, 0x1, 0x0408, 0x1, 0x0318) +#define IOMUXC_PAD_SD2_DATA3_MQS2_LEFT IOMUX_PADCFG(0x0168, 0x2, 0x0000, 0x0, 0x0318) +#define IOMUXC_PAD_SD2_DATA3_FLEXIO1_FLEXIO06 IOMUX_PADCFG(0x0168, 0x4, 0x0384, 0x1, 0x0318) +#define IOMUXC_PAD_SD2_DATA3_GPIO3_IO06 IOMUX_PADCFG(0x0168, 0x5, 0x0000, 0x0, 0x0318) +#define IOMUXC_PAD_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET IOMUX_PADCFG(0x0168, 0x6, 0x0000, 0x0, 0x0318) +#define IOMUXC_PAD_SD2_RESET_B_USDHC2_RESET_B IOMUX_PADCFG(0x016c, 0x0, 0x0000, 0x0, 0x031c) +#define IOMUXC_PAD_SD2_RESET_B_LPTMR2_ALT2 IOMUX_PADCFG(0x016c, 0x1, 0x040c, 0x1, 0x031c) +#define IOMUXC_PAD_SD2_RESET_B_FLEXIO1_FLEXIO07 IOMUX_PADCFG(0x016c, 0x4, 0x0388, 0x1, 0x031c) +#define IOMUXC_PAD_SD2_RESET_B_GPIO3_IO07 IOMUX_PADCFG(0x016c, 0x5, 0x0000, 0x0, 0x031c) +#define IOMUXC_PAD_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET IOMUX_PADCFG(0x016c, 0x6, 0x0000, 0x0, 0x031c) +#define IOMUXC_PAD_I2C1_SCL_LPI2C1_SCL IOMUX_PADCFG(0x0170, 0x0, 0x0000, 0x0, 0x0320) +#define IOMUXC_PAD_I2C1_SCL_I3C1_SCL IOMUX_PADCFG(0x0170, 0x1, 0x0000, 0x0, 0x0320) +#define IOMUXC_PAD_I2C1_SCL_LPUART1_DCB_B IOMUX_PADCFG(0x0170, 0x2, 0x0000, 0x0, 0x0320) +#define IOMUXC_PAD_I2C1_SCL_TPM2_CH0 IOMUX_PADCFG(0x0170, 0x3, 0x0000, 0x0, 0x0320) +#define IOMUXC_PAD_I2C1_SCL_GPIO1_IO00 IOMUX_PADCFG(0x0170, 0x5, 0x0000, 0x0, 0x0320) +#define IOMUXC_PAD_I2C1_SDA_LPI2C1_SDA IOMUX_PADCFG(0x0174, 0x0, 0x0000, 0x0, 0x0324) +#define IOMUXC_PAD_I2C1_SDA_I3C1_SDA IOMUX_PADCFG(0x0174, 0x1, 0x0000, 0x0, 0x0324) +#define IOMUXC_PAD_I2C1_SDA_LPUART1_RIN_B IOMUX_PADCFG(0x0174, 0x2, 0x0000, 0x0, 0x0324) +#define IOMUXC_PAD_I2C1_SDA_TPM2_CH1 IOMUX_PADCFG(0x0174, 0x3, 0x0000, 0x0, 0x0324) +#define IOMUXC_PAD_I2C1_SDA_GPIO1_IO01 IOMUX_PADCFG(0x0174, 0x5, 0x0000, 0x0, 0x0324) +#define IOMUXC_PAD_I2C2_SCL_LPI2C2_SCL IOMUX_PADCFG(0x0178, 0x0, 0x0000, 0x0, 0x0328) +#define IOMUXC_PAD_I2C2_SCL_I3C1_PUR IOMUX_PADCFG(0x0178, 0x1, 0x0000, 0x0, 0x0328) +#define IOMUXC_PAD_I2C2_SCL_LPUART2_DCB_B IOMUX_PADCFG(0x0178, 0x2, 0x0000, 0x0, 0x0328) +#define IOMUXC_PAD_I2C2_SCL_TPM2_CH2 IOMUX_PADCFG(0x0178, 0x3, 0x0000, 0x0, 0x0328) +#define IOMUXC_PAD_I2C2_SCL_SAI1_RX_SYNC IOMUX_PADCFG(0x0178, 0x4, 0x0000, 0x0, 0x0328) +#define IOMUXC_PAD_I2C2_SCL_GPIO1_IO02 IOMUX_PADCFG(0x0178, 0x5, 0x0000, 0x0, 0x0328) +#define IOMUXC_PAD_I2C2_SCL_I3C1_PUR_B IOMUX_PADCFG(0x0178, 0x6, 0x0000, 0x0, 0x0328) +#define IOMUXC_PAD_I2C2_SDA_LPI2C2_SDA IOMUX_PADCFG(0x017c, 0x0, 0x0000, 0x0, 0x032c) +#define IOMUXC_PAD_I2C2_SDA_LPUART2_RIN_B IOMUX_PADCFG(0x017c, 0x2, 0x0000, 0x0, 0x032c) +#define IOMUXC_PAD_I2C2_SDA_TPM2_CH3 IOMUX_PADCFG(0x017c, 0x3, 0x0000, 0x0, 0x032c) +#define IOMUXC_PAD_I2C2_SDA_SAI1_RX_BCLK IOMUX_PADCFG(0x017c, 0x4, 0x0000, 0x0, 0x032c) +#define IOMUXC_PAD_I2C2_SDA_GPIO1_IO03 IOMUX_PADCFG(0x017c, 0x5, 0x0000, 0x0, 0x032c) +#define IOMUXC_PAD_UART1_RXD_LPUART1_RX IOMUX_PADCFG(0x0180, 0x0, 0x0000, 0x0, 0x0330) +#define IOMUXC_PAD_UART1_RXD_S400_UART_RX IOMUX_PADCFG(0x0180, 0x1, 0x0000, 0x0, 0x0330) +#define IOMUXC_PAD_UART1_RXD_LPSPI2_SIN IOMUX_PADCFG(0x0180, 0x2, 0x0000, 0x0, 0x0330) +#define IOMUXC_PAD_UART1_RXD_TPM1_CH0 IOMUX_PADCFG(0x0180, 0x3, 0x0000, 0x0, 0x0330) +#define IOMUXC_PAD_UART1_RXD_GPIO1_IO04 IOMUX_PADCFG(0x0180, 0x5, 0x0000, 0x0, 0x0330) +#define IOMUXC_PAD_UART1_TXD_LPUART1_TX IOMUX_PADCFG(0x0184, 0x0, 0x0000, 0x0, 0x0334) +#define IOMUXC_PAD_UART1_TXD_S400_UART_TX IOMUX_PADCFG(0x0184, 0x1, 0x0000, 0x0, 0x0334) +#define IOMUXC_PAD_UART1_TXD_LPSPI2_PCS0 IOMUX_PADCFG(0x0184, 0x2, 0x0000, 0x0, 0x0334) +#define IOMUXC_PAD_UART1_TXD_TPM1_CH1 IOMUX_PADCFG(0x0184, 0x3, 0x0000, 0x0, 0x0334) +#define IOMUXC_PAD_UART1_TXD_GPIO1_IO05 IOMUX_PADCFG(0x0184, 0x5, 0x0000, 0x0, 0x0334) +#define IOMUXC_PAD_UART2_RXD_LPUART2_RX IOMUX_PADCFG(0x0188, 0x0, 0x0000, 0x0, 0x0338) +#define IOMUXC_PAD_UART2_RXD_LPUART1_CTS_B IOMUX_PADCFG(0x0188, 0x1, 0x0000, 0x0, 0x0338) +#define IOMUXC_PAD_UART2_RXD_LPSPI2_SOUT IOMUX_PADCFG(0x0188, 0x2, 0x0000, 0x0, 0x0338) +#define IOMUXC_PAD_UART2_RXD_TPM1_CH2 IOMUX_PADCFG(0x0188, 0x3, 0x0000, 0x0, 0x0338) +#define IOMUXC_PAD_UART2_RXD_SAI1_MCLK IOMUX_PADCFG(0x0188, 0x4, 0x0448, 0x0, 0x0338) +#define IOMUXC_PAD_UART2_RXD_GPIO1_IO06 IOMUX_PADCFG(0x0188, 0x5, 0x0000, 0x0, 0x0338) +#define IOMUXC_PAD_UART2_TXD_LPUART2_TX IOMUX_PADCFG(0x018c, 0x0, 0x0000, 0x0, 0x033c) +#define IOMUXC_PAD_UART2_TXD_LPUART1_RTS_B IOMUX_PADCFG(0x018c, 0x1, 0x0000, 0x0, 0x033c) +#define IOMUXC_PAD_UART2_TXD_LPSPI2_SCK IOMUX_PADCFG(0x018c, 0x2, 0x0000, 0x0, 0x033c) +#define IOMUXC_PAD_UART2_TXD_TPM1_CH3 IOMUX_PADCFG(0x018c, 0x3, 0x0000, 0x0, 0x033c) +#define IOMUXC_PAD_UART2_TXD_GPIO1_IO07 IOMUX_PADCFG(0x018c, 0x5, 0x0000, 0x0, 0x033c) +#define IOMUXC_PAD_PDM_CLK_PDM_CLK IOMUX_PADCFG(0x0190, 0x0, 0x0000, 0x0, 0x0340) +#define IOMUXC_PAD_PDM_CLK_MQS1_LEFT IOMUX_PADCFG(0x0190, 0x1, 0x0000, 0x0, 0x0340) +#define IOMUXC_PAD_PDM_CLK_LPTMR1_ALT1 IOMUX_PADCFG(0x0190, 0x4, 0x0000, 0x0, 0x0340) +#define IOMUXC_PAD_PDM_CLK_GPIO1_IO08 IOMUX_PADCFG(0x0190, 0x5, 0x0000, 0x0, 0x0340) +#define IOMUXC_PAD_PDM_CLK_CAN1_TX IOMUX_PADCFG(0x0190, 0x6, 0x0000, 0x0, 0x0340) +#define IOMUXC_PAD_PDM_BIT_STREAM0_PDM_BIT_STREAM00 IOMUX_PADCFG(0x0194, 0x0, 0x0438, 0x2, 0x0344) +#define IOMUXC_PAD_PDM_BIT_STREAM0_MQS1_RIGHT IOMUX_PADCFG(0x0194, 0x1, 0x0000, 0x0, 0x0344) +#define IOMUXC_PAD_PDM_BIT_STREAM0_LPSPI1_PCS1 IOMUX_PADCFG(0x0194, 0x2, 0x0000, 0x0, 0x0344) +#define IOMUXC_PAD_PDM_BIT_STREAM0_TPM1_EXTCLK IOMUX_PADCFG(0x0194, 0x3, 0x0000, 0x0, 0x0344) +#define IOMUXC_PAD_PDM_BIT_STREAM0_LPTMR1_ALT2 IOMUX_PADCFG(0x0194, 0x4, 0x0000, 0x0, 0x0344) +#define IOMUXC_PAD_PDM_BIT_STREAM0_GPIO1_IO09 IOMUX_PADCFG(0x0194, 0x5, 0x0000, 0x0, 0x0344) +#define IOMUXC_PAD_PDM_BIT_STREAM0_CAN1_RX IOMUX_PADCFG(0x0194, 0x6, 0x0360, 0x0, 0x0344) +#define IOMUXC_PAD_PDM_BIT_STREAM1_PDM_BIT_STREAM01 IOMUX_PADCFG(0x0198, 0x0, 0x043c, 0x2, 0x0348) +#define IOMUXC_PAD_PDM_BIT_STREAM1_NMI_GLUE_NMI IOMUX_PADCFG(0x0198, 0x1, 0x0000, 0x0, 0x0348) +#define IOMUXC_PAD_PDM_BIT_STREAM1_LPSPI2_PCS1 IOMUX_PADCFG(0x0198, 0x2, 0x0000, 0x0, 0x0348) +#define IOMUXC_PAD_PDM_BIT_STREAM1_TPM2_EXTCLK IOMUX_PADCFG(0x0198, 0x3, 0x0000, 0x0, 0x0348) +#define IOMUXC_PAD_PDM_BIT_STREAM1_LPTMR1_ALT3 IOMUX_PADCFG(0x0198, 0x4, 0x0000, 0x0, 0x0348) +#define IOMUXC_PAD_PDM_BIT_STREAM1_GPIO1_IO10 IOMUX_PADCFG(0x0198, 0x5, 0x0000, 0x0, 0x0348) +#define IOMUXC_PAD_PDM_BIT_STREAM1_CCMSRCGPCMIX_EXT_CLK1 IOMUX_PADCFG(0x0198, 0x6, 0x0368, 0x1, 0x0348) +#define IOMUXC_PAD_SAI1_TXFS_SAI1_TX_SYNC IOMUX_PADCFG(0x019c, 0x0, 0x0000, 0x0, 0x034c) +#define IOMUXC_PAD_SAI1_TXFS_SAI1_TX_DATA01 IOMUX_PADCFG(0x019c, 0x1, 0x0000, 0x0, 0x034c) +#define IOMUXC_PAD_SAI1_TXFS_LPSPI1_PCS0 IOMUX_PADCFG(0x019c, 0x2, 0x0000, 0x0, 0x034c) +#define IOMUXC_PAD_SAI1_TXFS_LPUART2_DTR_B IOMUX_PADCFG(0x019c, 0x3, 0x0000, 0x0, 0x034c) +#define IOMUXC_PAD_SAI1_TXFS_MQS1_LEFT IOMUX_PADCFG(0x019c, 0x4, 0x0000, 0x0, 0x034c) +#define IOMUXC_PAD_SAI1_TXFS_GPIO1_IO11 IOMUX_PADCFG(0x019c, 0x5, 0x0000, 0x0, 0x034c) +#define IOMUXC_PAD_SAI1_TXC_SAI1_TX_BCLK IOMUX_PADCFG(0x01a0, 0x0, 0x0000, 0x0, 0x0350) +#define IOMUXC_PAD_SAI1_TXC_LPUART2_CTS_B IOMUX_PADCFG(0x01a0, 0x1, 0x0000, 0x0, 0x0350) +#define IOMUXC_PAD_SAI1_TXC_LPSPI1_SIN IOMUX_PADCFG(0x01a0, 0x2, 0x0000, 0x0, 0x0350) +#define IOMUXC_PAD_SAI1_TXC_LPUART1_DSR_B IOMUX_PADCFG(0x01a0, 0x3, 0x0000, 0x0, 0x0350) +#define IOMUXC_PAD_SAI1_TXC_CAN1_RX IOMUX_PADCFG(0x01a0, 0x4, 0x0360, 0x1, 0x0350) +#define IOMUXC_PAD_SAI1_TXC_GPIO1_IO12 IOMUX_PADCFG(0x01a0, 0x5, 0x0000, 0x0, 0x0350) +#define IOMUXC_PAD_SAI1_TXD0_SAI1_TX_DATA00 IOMUX_PADCFG(0x01a4, 0x0, 0x0000, 0x0, 0x0354) +#define IOMUXC_PAD_SAI1_TXD0_LPUART2_RTS_B IOMUX_PADCFG(0x01a4, 0x1, 0x0000, 0x0, 0x0354) +#define IOMUXC_PAD_SAI1_TXD0_LPSPI1_SCK IOMUX_PADCFG(0x01a4, 0x2, 0x0000, 0x0, 0x0354) +#define IOMUXC_PAD_SAI1_TXD0_LPUART1_DTR_B IOMUX_PADCFG(0x01a4, 0x3, 0x0000, 0x0, 0x0354) +#define IOMUXC_PAD_SAI1_TXD0_CAN1_TX IOMUX_PADCFG(0x01a4, 0x4, 0x0000, 0x0, 0x0354) +#define IOMUXC_PAD_SAI1_TXD0_GPIO1_IO13 IOMUX_PADCFG(0x01a4, 0x5, 0x0000, 0x0, 0x0354) +#define IOMUXC_PAD_SAI1_RXD0_SAI1_RX_DATA00 IOMUX_PADCFG(0x01a8, 0x0, 0x0000, 0x0, 0x0358) +#define IOMUXC_PAD_SAI1_RXD0_SAI1_MCLK IOMUX_PADCFG(0x01a8, 0x1, 0x0448, 0x1, 0x0358) +#define IOMUXC_PAD_SAI1_RXD0_LPSPI1_SOUT IOMUX_PADCFG(0x01a8, 0x2, 0x0000, 0x0, 0x0358) +#define IOMUXC_PAD_SAI1_RXD0_LPUART2_DSR_B IOMUX_PADCFG(0x01a8, 0x3, 0x0000, 0x0, 0x0358) +#define IOMUXC_PAD_SAI1_RXD0_MQS1_RIGHT IOMUX_PADCFG(0x01a8, 0x4, 0x0000, 0x0, 0x0358) +#define IOMUXC_PAD_SAI1_RXD0_GPIO1_IO14 IOMUX_PADCFG(0x01a8, 0x5, 0x0000, 0x0, 0x0358) +#define IOMUXC_PAD_WDOG_ANY_WDOG1_WDOG_ANY IOMUX_PADCFG(0x01ac, 0x0, 0x0000, 0x0, 0x035c) +#define IOMUXC_PAD_WDOG_ANY_GPIO1_IO15 IOMUX_PADCFG(0x01ac, 0x5, 0x0000, 0x0, 0x035c) + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_PINMUX_H */ diff --git a/arch/arm/src/imx9/hardware/imx93/imx93_pll.h b/arch/arm/src/imx9/hardware/imx93/imx93_pll.h new file mode 100644 index 00000000000..7dc212aecc2 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx93/imx93_pll.h @@ -0,0 +1,197 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx93/imx93_pll.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_PLL_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_PLL_H + +/* All registers besides STATUS have SET, CLR, TGL and VAL shadow registers */ + +#define PLL_REG_VAL_OFFSET (0x00) +#define PLL_REG_SET_OFFSET (0x04) +#define PLL_REG_CLR_OFFSET (0x08) +#define PLL_REG_TGL_OFFSET (0x0c) + +/* User can access the individual registers via these macros */ + +#define PLL_VAL(n) ((n) + PLL_REG_VAL_OFFSET) /* Same as the register itself */ +#define PLL_SET(n) ((n) + PLL_REG_SET_OFFSET) +#define PLL_CLR(n) ((n) + PLL_REG_CLR_OFFSET) +#define PLL_TGL(n) ((n) + PLL_REG_TGL_OFFSET) + +/* Common offsets for all PLL registers, existence depends on the register + * itself + */ + +#define PLL_CTRL_OFFSET (0x00) /* PLL Control */ +#define PLL_SPREAD_SPECTRUM_OFFSET (0x30) /* Spread Spectrum */ +#define PLL_NUMERATOR_OFFSET (0x40) /* Numerator */ +#define PLL_DENOMINATOR_OFFSET (0x50) /* Denominator */ +#define PLL_DIV_OFFSET (0x60) /* PLL Dividers */ +#define PLL_DFS_CTRL_0_OFFSET (0x70) /* DFS Control */ +#define PLL_DFS_DIV_0_OFFSET (0x80) /* DFS Division_0 */ +#define PLL_DFS_CTRL_1_OFFSET (0x90) /* DFS Control */ +#define PLL_DFS_DIV_1_OFFSET (0xa0) /* DFS Division_1 */ +#define PLL_DFS_CTRL_2_OFFSET (0xb0) /* DFS Control */ +#define PLL_DFS_DIV_2_OFFSET (0xc0) /* DFS Division_2 */ +#define PLL_PLL_STATUS_OFFSET (0xf0) /* PLL Status */ +#define PLL_DFS_STATUS_OFFSET (0xf4) /* DFS Status */ + +/* Register addresses */ + +#define PLL_CTRL(n) ((n) + PLL_CTRL_OFFSET) +#define PLL_SPREAD_SPECTRUM(n) ((n) + PLL_SPREAD_SPECTRUM_OFFSET) +#define PLL_NUMERATOR(n) ((n) + PLL_NUMERATOR_OFFSET) +#define PLL_DENOMINATOR(n) ((n) + PLL_DENOMINATOR_OFFSET) +#define PLL_DIV(n) ((n) + PLL_DIV_OFFSET) +#define PLL_DFS_CTRL_0(n) ((n) + PLL_DFS_CTRL_0_OFFSET) +#define PLL_DFS_DIV_0(n) ((n) + PLL_DFS_DIV_0_OFFSET) +#define PLL_DFS_CTRL_1(n) ((n) + PLL_DFS_CTRL_1_OFFSET) +#define PLL_DFS_DIV_1(n) ((n) + PLL_DFS_DIV_1_OFFSET) +#define PLL_DFS_CTRL_2(n) ((n) + PLL_DFS_CTRL_2_OFFSET) +#define PLL_DFS_DIV_2(n) ((n) + PLL_DFS_DIV_2_OFFSET) +#define PLL_PLL_STATUS(n) ((n) + PLL_PLL_STATUS_OFFSET) +#define PLL_DFS_STATUS(n) ((n) + PLL_DFS_STATUS_OFFSET) + +/* SYSPLL registers */ + +#define SYSPLL_CTRL (IMX9_SYSPLL_BASE + PLL_CTRL_OFFSET) +#define SYSPLL_SPREAD_SPECTRUM (IMX9_SYSPLL_BASE + PLL_SPREAD_SPECTRUM_OFFSET) +#define SYSPLL_NUMERATOR (IMX9_SYSPLL_BASE + PLL_NUMERATOR_OFFSET) +#define SYSPLL_DENOMINATOR (IMX9_SYSPLL_BASE + PLL_DENOMINATOR_OFFSET) +#define SYSPLL_DIV (IMX9_SYSPLL_BASE + PLL_DIV_OFFSET) +#define SYSPLL_DFS_CTRL_0 (IMX9_SYSPLL_BASE + PLL_DFS_CTRL_0_OFFSET) +#define SYSPLL_DFS_DIV_0 (IMX9_SYSPLL_BASE + PLL_DFS_DIV_0_OFFSET) +#define SYSPLL_DFS_CTRL_1 (IMX9_SYSPLL_BASE + PLL_DFS_CTRL_1_OFFSET) +#define SYSPLL_DFS_DIV_1 (IMX9_SYSPLL_BASE + PLL_DFS_DIV_1_OFFSET) +#define SYSPLL_DFS_CTRL_2 (IMX9_SYSPLL_BASE + PLL_DFS_CTRL_2_OFFSET) +#define SYSPLL_DFS_DIV_2 (IMX9_SYSPLL_BASE + PLL_DFS_DIV_2_OFFSET) +#define SYSPLL_PLL_STATUS (IMX9_SYSPLL_BASE + PLL_PLL_STATUS_OFFSET) +#define SYSPLL_DFS_STATUS (IMX9_SYSPLL_BASE + PLL_DFS_STATUS_OFFSET) + +/* ARMPLL registers */ + +#define ARMPLL_CTRL (IMX9_ARMPLL_BASE + PLL_CTRL_OFFSET) +#define ARMPLL_DIV (IMX9_ARMPLL_BASE + PLL_DIV_OFFSET) +#define ARMPLL_PLL_STATUS (IMX9_ARMPLL_BASE + PLL_PLL_STATUS_OFFSET) + +/* AUDIOPLL registers */ + +#define AUDIOPLL_CTRL (IMX9_AUDIOPLL_BASE + PLL_CTRL_OFFSET) +#define AUDIOPLL_SPREAD_SPECTRUM (IMX9_AUDIOPLL_BASE + PLL_SPREAD_SPECTRUM_OFFSET) +#define AUDIOPLL_NUMERATOR (IMX9_AUDIOPLL_BASE + PLL_NUMERATOR_OFFSET) +#define AUDIOPLL_DENOMINATOR (IMX9_AUDIOPLL_BASE + PLL_DENOMINATOR_OFFSET) +#define AUDIOPLL_DIV (IMX9_AUDIOPLL_BASE + PLL_DIV_OFFSET) +#define AUDIOPLL_PLL_STATUS (IMX9_AUDIOPLL_BASE + PLL_PLL_STATUS_OFFSET) + +/* DRAMPLL registers */ + +#define DRAMPLL_CTRL (IMX9_AUDIOPLL_BASE + PLL_CTRL_OFFSET) +#define DRAMPLL_SPREAD_SPECTRUM (IMX9_AUDIOPLL_BASE + PLL_SPREAD_SPECTRUM_OFFSET) +#define DRAMPLL_NUMERATOR (IMX9_AUDIOPLL_BASE + PLL_NUMERATOR_OFFSET) +#define DRAMPLL_DENOMINATOR (IMX9_AUDIOPLL_BASE + PLL_DENOMINATOR_OFFSET) +#define DRAMPLL_DIV (IMX9_AUDIOPLL_BASE + PLL_DIV_OFFSET) +#define DRAMPLL_PLL_STATUS (IMX9_AUDIOPLL_BASE + PLL_PLL_STATUS_OFFSET) + +/* VIDEOPLL registers */ + +#define VIDEOPLL_CTRL (IMX9_VIDEOPLL_BASE + PLL_CTRL_OFFSET) +#define VIDEOPLL_SPREAD_SPECTRUM (IMX9_VIDEOPLL_BASE + PLL_SPREAD_SPECTRUM_OFFSET) +#define VIDEOPLL_NUMERATOR (IMX9_VIDEOPLL_BASE + PLL_NUMERATOR_OFFSET) +#define VIDEOPLL_DENOMINATOR (IMX9_VIDEOPLL_BASE + PLL_DENOMINATOR_OFFSET) +#define VIDEOPLL_DIV (IMX9_VIDEOPLL_BASE + PLL_DIV_OFFSET) +#define VIDEOPLL_PLL_STATUS (IMX9_VIDEOPLL_BASE + PLL_PLL_STATUS_OFFSET) + +/* PLL Control (CTRL) */ + +#define PLL_CTRL_POWERUP (1 << 0) /* Bit 0: Power up PLL */ +#define PLL_CTRL_CLKMUX_EN (1 << 1) /* Bit 1: Enable CLKMUX output */ +#define PLL_CTRL_CLKMUX_BYPASS (1 << 2) /* Bit 2: Enable CLKMUX bypass */ +#define PLL_CTRL_SPREADCTL (1 << 8) /* Bit 8: Modulation Type Select */ +#define PLL_CTRL_HW_CTRL_SEL (1 << 16) /* Bit 16: Hardware Control Select */ +#define PLL_CTRL_LOCK_BYPASS (1 << 31) /* Bit 31: Lock bypass */ + +/* Spread Spectrum (SPREAD_SPECTRUM) */ + +#define PLL_SPREAD_SPECTRUM_STEP_SHIFT (0) /* Bits 14-0: Set spread spectrum step */ +#define PLL_SPREAD_SPECTRUM_STEP_MASK (0x7fff << PLL_SPREAD_SPECTRUM_STEP_SHIFT) +#define PLL_SPREAD_SPECTRUM_STEP(n) (((n) << PLL_SPREAD_SPECTRUM_STEP_SHIFT) & PLL_SPREAD_SPECTRUM_STEP_MASK) +#define PLL_SPREAD_SPECTRUM_ENABLE (1 << 15) /* Bit 15: Enable spread spectrum */ +#define PLL_SPREAD_SPECTRUM_STOP_SHIFT (16) /* Bits 16-31: Set spread spectrum stop */ +#define PLL_SPREAD_SPECTRUM_STOP_MASK (0xffff << PLL_SPREAD_SPECTRUM_STOP_SHIFT) +#define PLL_SPREAD_SPECTRUM_STOP(n) (((n) << PLL_SPREAD_SPECTRUM_STOP_SHIFT) & PLL_SPREAD_SPECTRUM_STOP_MASK) + +/* Numerator (NUMERATOR) */ + +#define PLL_NUMERATOR_MFN_SHIFT (2) /* Bits 2-31: Numerator MFN value */ +#define PLL_NUMERATOR_MFN_MASK (0x3fffffff << PLL_NUMERATOR_MFN_SHIFT) +#define PLL_NUMERATOR_MFN(n) (((n) << PLL_NUMERATOR_MFN_SHIFT) & PLL_NUMERATOR_MFN_MASK) + +/* Denominator (DENOMINATOR) */ + +#define PLL_DENOMINATOR_MFD_SHIFT (0) /* Bits 0-29: Denominator MFD value */ +#define PLL_DENOMINATOR_MFD_MASK (0x3fffffff << PLL_DENOMINATOR_MFD_SHIFT) +#define PLL_DENOMINATOR_MFD(n) (((n) << PLL_DENOMINATOR_MFD_SHIFT) & PLL_DENOMINATOR_MFD_MASK) + +/* PLL Dividers (DIV) */ + +#define PLL_DIV_ODIV_SHIFT (0) /* Bits 0-7: Output Frequency Divider for Clock Output */ +#define PLL_DIV_ODIV_MASK (0xff << PLL_DIV_ODIV_SHIFT) +#define PLL_DIV_ODIV(n) (((n) << PLL_DIV_ODIV_SHIFT) & PLL_DIV_ODIV_MASK) +#define PLL_DIV_RDIV_SHIFT (13) /* Bits 13-15: Input Clock Predivider */ +#define PLL_DIV_RDIV_MASK (0x7 << PLL_DIV_RDIV_SHIFT) +#define PLL_DIV_RDIV(n) (((n) << PLL_DIV_RDIV_SHIFT) & PLL_DIV_RDIV_MASK) +#define PLL_DIV_MFI_SHIFT (16) /* Bits 16-24: Integer Portion of Loop Divider */ +#define PLL_DIV_MFI_MASK (0x1ff << PLL_DIV_MFI_SHIFT) +#define PLL_DIV_MFI(n) (((n) << PLL_DIV_MFI_SHIFT) & PLL_DIV_MFI_MASK) + +/* DFS Control (DFS_CTRL_0 - DFS_CTRL_2) */ + +#define PLL_DFS_HW_CTRL_SEL (1 << 16) /* Bit 16: Hardware Control Select */ +#define PLL_DFS_BYPASS_EN (1 << 23) /* Bit 23: Bypass Enable */ +#define PLL_DFS_CLKOUT_DIVBY2_EN (1 << 29) /* Bit 29: DFS Clock Output Divide by 2 Enable */ +#define PLL_DFS_CLKOUT_EN (1 << 30) /* Bit 30: DFS Clock Output Enable */ +#define PLL_DFS_ENABLE (1 << 31) /* Bit 31: DFS Block Enable */ + +/* DFS Division_a (DFS_DIV_0 - DFS_DIV_2) */ + +#define PLL_DFS_MFN_SHIFT (0) /* Bits 0-2: MFN */ +#define PLL_DFS_MFN_MASK (0x7 << PLL_DFS_MFN_SHIFT) +#define PLL_DFS_MFN(n) (((n) << PLL_DFS_MFN_SHIFT) & PLL_DFS_MFN_MASK) +#define PLL_DFS_MFI_SHIFT (8) /* Bits 8-15: MFI */ +#define PLL_DFS_MFI_MASK (0xff << PLL_DFS_MFI_SHIFT) +#define PLL_DFS_MFI(n) (((n) << PLL_DFS_MFI_SHIFT) & PLL_DFS_MFI_MASK) + +/* PLL Dividers (DIV) */ + +#define PLL_PLL_STATUS_PLL_LOCK (1 << 0) /* Bit 0: PLL is locked */ +#define PLL_PLL_STATUS_PLL_LOL (1 << 1) /* Bit 1: PLL lock is lost */ +#define PLL_PLL_STATUS_ANA_MFN_SHIFT (2) +#define PLL_PLL_STATUS_ANA_MFN_MASK (0x3fffffff << PLL_PLL_STATUS_ANA_MFN_SHIFT) +#define PLL_PLL_STATUS_ANA_MFN(n) (((n) << PLL_PLL_STATUS_ANA_MFN_SHIFT) & PLL_PLL_STATUS_ANA_MFN_MASK) + +/* DFS Status (DFS_STATUS) */ + +#define PLL_DFS_STATUS_DFS_OK_SHIFT (0) /* Bits 0-2: DFS OK status */ +#define PLL_DFS_STATUS_DFS_OK_MASK (0x7 << PLL_DFS_STATUS_DFS_OK_SHIFT) +#define PLL_DFS_STATUS_DFS_OK(n) (((n) << PLL_DFS_STATUS_DFS_OK_SHIFT) & PLL_DFS_STATUS_DFS_OK_MASK) + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_PLL_H_*/ diff --git a/arch/arm/src/imx9/hardware/imx9_ccm.h b/arch/arm/src/imx9/hardware/imx9_ccm.h new file mode 100644 index 00000000000..92745fe2441 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx9_ccm.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx9_ccm.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_CCM_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_CCM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/imx9_memorymap.h" + +#if defined(CONFIG_ARCH_CHIP_IMX93_M33) +# include "hardware/imx93/imx93_ccm.h" +# include "hardware/imx93/imx93_pll.h" +#else +# error Unrecognized i.MX9 architecture +#endif + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_CCM_H_ */ diff --git a/arch/arm/src/imx9/hardware/imx9_clock.h b/arch/arm/src/imx9/hardware/imx9_clock.h index 141cdb45071..9f1d737f6fb 100644 --- a/arch/arm/src/imx9/hardware/imx9_clock.h +++ b/arch/arm/src/imx9/hardware/imx9_clock.h @@ -33,6 +33,8 @@ #if defined(CONFIG_ARCH_CHIP_IMX95_M7) # include "hardware/imx95/imx95_clock.h" +#elif defined(CONFIG_ARCH_CHIP_IMX93_M33) +# include "hardware/imx93/imx93_clock.h" #else # error Unrecognized i.MX9 architecture #endif diff --git a/arch/arm/src/imx9/hardware/imx9_gpio.h b/arch/arm/src/imx9/hardware/imx9_gpio.h index 6c8f76a9419..945bbf93832 100644 --- a/arch/arm/src/imx9/hardware/imx9_gpio.h +++ b/arch/arm/src/imx9/hardware/imx9_gpio.h @@ -32,6 +32,8 @@ #if defined(CONFIG_ARCH_CHIP_IMX95_M7) # include "hardware/imx95/imx95_gpio.h" +#elif defined(CONFIG_ARCH_CHIP_IMX93_M33) +# include "hardware/imx93/imx93_gpio.h" #else # error Unrecognized i.MX9 architecture #endif diff --git a/arch/arm/src/imx9/hardware/imx9_iomuxc.h b/arch/arm/src/imx9/hardware/imx9_iomuxc.h index 3b4ccc12822..40ed23dcd12 100644 --- a/arch/arm/src/imx9/hardware/imx9_iomuxc.h +++ b/arch/arm/src/imx9/hardware/imx9_iomuxc.h @@ -32,6 +32,8 @@ #if defined(CONFIG_ARCH_CHIP_IMX95_M7) # include "hardware/imx95/imx95_iomuxc.h" +#elif defined(CONFIG_ARCH_CHIP_IMX93_M33) +# include "hardware/imx93/imx93_iomux.h" #else # error Unrecognized i.MX9 architecture #endif diff --git a/arch/arm/src/imx9/hardware/imx9_memorymap.h b/arch/arm/src/imx9/hardware/imx9_memorymap.h index f500ae69399..bcdde41f29b 100644 --- a/arch/arm/src/imx9/hardware/imx9_memorymap.h +++ b/arch/arm/src/imx9/hardware/imx9_memorymap.h @@ -32,6 +32,8 @@ #if defined(CONFIG_ARCH_CHIP_IMX95_M7) # include "hardware/imx95/imx95_memorymap.h" +#elif defined(CONFIG_ARCH_CHIP_IMX93_M33) +# include "hardware/imx93/imx93_memorymap.h" #else # error Unrecognized i.MX9 architecture #endif diff --git a/arch/arm/src/imx9/hardware/imx9_pinmux.h b/arch/arm/src/imx9/hardware/imx9_pinmux.h index d93dd907866..32a7097640b 100644 --- a/arch/arm/src/imx9/hardware/imx9_pinmux.h +++ b/arch/arm/src/imx9/hardware/imx9_pinmux.h @@ -32,6 +32,8 @@ #if defined(CONFIG_ARCH_CHIP_IMX95_M7) # include "hardware/imx95/imx95_pinmux.h" +#elif defined(CONFIG_ARCH_CHIP_IMX93_M33) +# include "hardware/imx93/imx93_pinmux.h" #else # error Unrecognized i.MX9 architecture #endif diff --git a/arch/arm/src/imx9/hardware/imx9_rptun.h b/arch/arm/src/imx9/hardware/imx9_rptun.h index bef157b5c90..57c3f0ae81f 100644 --- a/arch/arm/src/imx9/hardware/imx9_rptun.h +++ b/arch/arm/src/imx9/hardware/imx9_rptun.h @@ -25,6 +25,8 @@ #if defined(CONFIG_ARCH_CHIP_IMX95_M7) # define MU_INSTANCE 7 +#elif defined(CONFIG_ARCH_CHIP_IMX93_M33) +# define MU_INSTANCE 1 #else # error Unrecognized i.MX9 architecture #endif diff --git a/arch/arm/src/imx9/hardware/imx9_rsctable.h b/arch/arm/src/imx9/hardware/imx9_rsctable.h index 626d8617077..4cba6b94cd2 100644 --- a/arch/arm/src/imx9/hardware/imx9_rsctable.h +++ b/arch/arm/src/imx9/hardware/imx9_rsctable.h @@ -26,6 +26,9 @@ #if defined(CONFIG_ARCH_CHIP_IMX95_M7) # define VDEV0_VRING_BASE 0x88000000 # define RESOURCE_TABLE_BASE 0x88220000 +#elif defined(CONFIG_ARCH_CHIP_IMX93_M33) +# define VDEV0_VRING_BASE 0xA4000000 +# define RESOURCE_TABLE_BASE 0x2001E000 #else # error Unrecognized i.MX9 architecture #endif diff --git a/arch/arm/src/imx9/hardware/imx9_xcache.h b/arch/arm/src/imx9/hardware/imx9_xcache.h new file mode 100644 index 00000000000..7f54817e6c6 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx9_xcache.h @@ -0,0 +1,78 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx9_xcache.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2026 Maarten Zanders + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_XCACHE_H +#define __ARCH_ARM_SRC_IMX9_IMX9_XCACHE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/imx9_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* XCACHE Register Offsets */ + +#define IMX9_XCACHE_CCR_OFFSET 0x0000 /* Cache Control Register */ +#define IMX9_XCACHE_CLCR_OFFSET 0x0004 /* Cache Line Control Register */ +#define IMX9_XCACHE_CSAR_OFFSET 0x0008 /* Cache Search Address Register */ +#define IMX9_XCACHE_CCVR_OFFSET 0x000C /* Cache Value Register */ + +/* Cache Control Register (CCR) */ + +#define XCACHE_CCR_ENCACHE (1 << 0) /* Enable cache */ +#define XCACHE_CCR_INVW0 (1 << 24) /* Invalidate Way 0 */ +#define XCACHE_CCR_PUSHW0 (1 << 25) /* Push Way 0 */ +#define XCACHE_CCR_INVW1 (1 << 26) /* Invalidate Way 1 */ +#define XCACHE_CCR_PUSHW1 (1 << 27) /* Push Way 1 */ +#define XCACHE_CCR_GO (1 << 31) /* Initiate command */ + +/* Cache Line Control Register (CLCR) */ + +#define XCACHE_CLCR_LGO (1 << 0) /* Line command go */ +#define XCACHE_CLCR_CACHEADDR_SHIFT 2 +#define XCACHE_CLCR_CACHEADDR_MASK (0x7ff << XCACHE_CLCR_CACHEADDR_SHIFT) +#define XCACHE_CLCR_WSEL (1 << 14) /* Way select */ +#define XCACHE_CLCR_TDSEL (1 << 16) /* Tag or data select */ +#define XCACHE_CLCR_LCIVB (1 << 20) /* Line command initial valid */ +#define XCACHE_CLCR_LCIMB (1 << 21) /* Line command initial modified */ +#define XCACHE_CLCR_LCWAY (1 << 22) /* Line command way */ +#define XCACHE_CLCR_LADSEL (1 << 26) /* Line Address Select (0: cache, 1: physical) */ +#define XCACHE_CLCR_LCMD_SHIFT 24 +#define XCACHE_CLCR_LCMD_MASK (0x3 << XCACHE_CLCR_LCMD_SHIFT) /* Line command */ +#define XCACHE_CLCR_LCMD(n) ((n << XCACHE_CLCR_LCMD_SHIFT) & XCACHE_CLCR_LCMD_MASK) + +#define XCACHE_LCMD_SRCH_RW 0b00 +#define XCACHE_LCMD_INVALIDATE 0b01 +#define XCACHE_LCMD_PUSH 0b10 +#define XCACHE_LCMD_CLEAR 0b11 + +/* Cache Search Address Register */ +#define XCACHE_CSAR_PHYADDR_MASK (0xFFFFFFFD) +#define XCACHE_CSAR_LGO (1 << 0) + +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_XCACHE_H */ diff --git a/arch/arm/src/imx9/imx9_ccm.c b/arch/arm/src/imx9/imx9_ccm.c new file mode 100644 index 00000000000..6adef244fae --- /dev/null +++ b/arch/arm/src/imx9/imx9_ccm.c @@ -0,0 +1,173 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_ccm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include + +#include "imx9_ccm.h" + +#include "hardware/imx9_ccm.h" + +#include "arm_internal.h" /* getreg32(), putreg32() */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_ccm_configure_root_clock + * + * Description: + * Change root clock source and divider. Leaves the clock running state + * unaltered. + * + * Input Parameters: + * root - The root clock index. + * src - The root clock MUX source. + * div - The root clock divider. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int imx9_ccm_configure_root_clock(int root, int mux, uint32_t div) +{ + uint32_t value; + + if (root >= CCM_CR_COUNT || div == 0 || div > 255 || mux >= ROOT_MUX_MAX) + { + return -EINVAL; + } + + /* Set the new value */ + + value = CCM_CR_CTRL_MUX_SRCSEL(mux) | CCM_CR_CTRL_DIV(div); + putreg32(value, IMX9_CCM_CR_CTRL(root)); + UP_MB(); + + /* Wait for the clock state change */ + + while (getreg32(IMX9_CCM_CR_STAT0(root)) & CCM_CR_STAT0_CHANGING); + + return OK; +} + +/**************************************************************************** + * Name: imx9_ccm_root_clock_on + * + * Description: + * Enable / disable root clock. + * + * Input Parameters: + * root - The root clock index. + * enabled - True enables the clock; false disables it. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int imx9_ccm_root_clock_on(int root, bool enabled) +{ + if (root >= CCM_CR_COUNT) + { + return -EINVAL; + } + + if (enabled) + { + putreg32(CCM_CR_CTRL_OFF, IMX9_CCM_CR_CTRL_CLR(root)); + } + else + { + putreg32(CCM_CR_CTRL_OFF, IMX9_CCM_CR_CTRL_SET(root)); + } + + UP_MB(); + + /* Wait for the clock state change */ + + while (getreg32(IMX9_CCM_CR_STAT0(root)) & CCM_CR_STAT0_CHANGING); + + return OK; +} + +/**************************************************************************** + * Name: imx9_ccm_gate_on + * + * Description: + * Enable / disable clock. + * + * Input Parameters: + * gate - The clock gate index. + * enabled - True enables the clock; false disables it. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int imx9_ccm_gate_on(int gate, bool enabled) +{ + uint32_t value; + + if (gate >= CCM_LPCG_COUNT) + { + return -EINVAL; + } + + /* Make sure direct mode is on, which is what we support */ + + value = getreg32(IMX9_CCM_LPCG_AUTH(gate)); + if (value & CCM_LPCG_AUTH_CPULPM) + { + value &= ~CCM_LPCG_AUTH_CPULPM; + putreg32(value, IMX9_CCM_LPCG_AUTH(gate)); + UP_MB(); + } + + value = enabled ? 1 : 0; + putreg32(value, IMX9_CCM_LPCG_DIR(gate)); + UP_MB(); + + /* Wait for the clock state change */ + + while ((getreg32(IMX9_CCM_LPCG_STAT0(gate)) & CCM_LPCG_STAT0_ON) != value); + + return OK; +} diff --git a/arch/arm/src/imx9/imx9_ccm.h b/arch/arm/src/imx9/imx9_ccm.h new file mode 100644 index 00000000000..f30a9baf81b --- /dev/null +++ b/arch/arm/src/imx9/imx9_ccm.h @@ -0,0 +1,90 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_ccm.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_CCM_H +#define __ARCH_ARM_SRC_IMX9_IMX9_CCM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Name: imx9_ccm_configure_root_clock + * + * Description: + * Change root clock source and divider. Leaves the clock running state + * unaltered. + * + * Input Parameters: + * root - The root clock index. + * mux - The root clock MUX source. + * div - The root clock divider. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int imx9_ccm_configure_root_clock(int root, int mux, uint32_t div); + +/**************************************************************************** + * Name: imx9_ccm_root_clock_on + * + * Description: + * Enable / disable root clock. + * + * Input Parameters: + * root - The root clock index. + * enabled - True enables the clock; false disables it. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int imx9_ccm_root_clock_on(int root, bool enabled); + +/**************************************************************************** + * Name: imx9_ccm_gate_on + * + * Description: + * Enable / disable clock. + * + * Input Parameters: + * gate - The clock gate index. + * enabled - True enables the clock; false disables it. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int imx9_ccm_gate_on(int gate, bool enabled); + +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_CCM_H */ diff --git a/arch/arm/src/imx9/imx9_clockconfig.c b/arch/arm/src/imx9/imx9_clockconfig.c index 54a430c4771..c9f15869d59 100644 --- a/arch/arm/src/imx9/imx9_clockconfig.c +++ b/arch/arm/src/imx9/imx9_clockconfig.c @@ -45,10 +45,96 @@ #include "imx9_clockconfig.h" #include "imx9_scmi.h" +#include "hardware/imx9_memorymap.h" + +#ifndef CONFIG_IMX9_CLK_OVER_SCMI +#include "imx9_ccm.h" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +#ifndef CONFIG_IMX9_CLK_OVER_SCMI +#define PLL_PARMS(_rdiv, _odiv, _mfi, _mfn, _mfd) \ + { \ + .rdiv = (_rdiv), \ + .odiv = (_odiv), \ + .mfi = (_mfi), \ + .mfn = (_mfn), \ + .mfd = (_mfd), \ + } + +#define PLL_CFG(_reg, _frac, _parms) \ + { \ + .reg = (_reg), \ + .frac = (_frac), \ + .parms = _parms, \ + } + +#define PFD_PARMS(_mfi, _mfn, _div2) \ + { \ + .mfi = (_mfi), \ + .mfn = (_mfn), \ + .divby2_en = (_div2) \ + } + +#define PFD_CFG(_reg, _pfd, _parms) \ + { \ + .reg = (_reg), \ + .pfd = (_pfd), \ + .parms = _parms, \ + } + +#endif /* !CONFIG_IMX9_CLK_OVER_SCMI */ + +/**************************************************************************** + * Types + ****************************************************************************/ + +#ifndef CONFIG_IMX9_CLK_OVER_SCMI +struct pll_parms_s +{ + /* Integer part (DIV) */ + + struct + { + uint32_t rdiv; /* Input clock divider */ + uint32_t odiv; /* PLL output divider */ + uint32_t mfi; /* PLL integer divider */ + }; + + /* Fractional part (NUMERATOR / DENOMINATOR) */ + + struct + { + uint32_t mfn; /* PLL fractional divider numerator */ + uint32_t mfd; /* PLL fractional divider denominator */ + }; +}; + +struct pfd_parms_s +{ + uint32_t mfi; /* PLL integer divider */ + uint32_t mfn; /* PLL fractional divider numerator */ + bool divby2_en; /* Enable the divide-by-2 output */ +}; + +struct imx9_pll_cfg_s +{ + uintptr_t reg; /* The PLL register base */ + bool frac; /* Fractional PLL ? */ + struct pll_parms_s parms; /* The PLL parameters */ +}; + +struct imx9_pfd_cfg_s +{ + uintptr_t reg; /* The PLL register base */ + int pfd; /* The PFD number */ + struct pfd_parms_s parms; /* The PFD parameters */ +}; +#endif /* !CONFIG_IMX9_CLK_OVER_SCMI */ + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -180,10 +266,267 @@ static int imx9_sm_getipfreq(sm_clock_t *sm_clk) return rate.lower; } -#endif + +#else /* !CONFIG_IMX9_CLK_OVER_SCMI */ + +static uint32_t calculate_vco_freq(const struct pll_parms_s *parm, bool frac) +{ + /* Base clock is common for all VCO:s */ + + if (frac) + { + return (uint64_t)XTAL_FREQ * (parm->mfi * parm->mfd + parm->mfn) / + parm->mfd / parm->rdiv; + } + else + { + return (uint64_t)XTAL_FREQ * parm->mfi / parm->rdiv; + } +} + +static uint32_t vco_freq_out(uintptr_t reg, bool frac) +{ + struct pll_parms_s parm; + uint32_t ctrl; + uint32_t status; + uint32_t div; + + /* Check if the PLL on or off */ + + ctrl = getreg32(PLL_CTRL(reg)); + if ((ctrl & PLL_CTRL_POWERUP) == 0) + { + return 0; + } + + /* Check if the PLL is stable */ + + status = getreg32(PLL_PLL_STATUS(reg)); + if ((status & PLL_PLL_STATUS_PLL_LOCK) == 0) + { + return 0; + } + + /* Populate the integer and fractional PLL parameters */ + + div = getreg32(PLL_DIV(reg)); + parm.rdiv = (div & PLL_DIV_RDIV_MASK) >> PLL_DIV_RDIV_SHIFT; + parm.mfi = (div & PLL_DIV_MFI_MASK) >> PLL_DIV_MFI_SHIFT; + + /* RDIV values 0 and 1 both mean a divisor of 1 */ + + if (parm.rdiv == 0) + { + parm.rdiv = 1; + } + + if (frac) + { + /* Fill the fractional parameters */ + + parm.mfn = getreg32(PLL_NUMERATOR(reg)) & PLL_NUMERATOR_MFN_MASK; + parm.mfn >>= PLL_NUMERATOR_MFN_SHIFT; + parm.mfd = getreg32(PLL_DENOMINATOR(reg)) & PLL_DENOMINATOR_MFD_MASK; + parm.mfd >>= PLL_DENOMINATOR_MFD_SHIFT; + } + + return calculate_vco_freq(&parm, frac); +} + +static uint32_t pll_freq_out(uintptr_t reg, bool frac) +{ + uint32_t ctrl; + uint32_t div; + uint32_t vco; + + /* Read the MUX control register and check if bypass mode is enabled */ + + ctrl = getreg32(PLL_CTRL(reg)); + if (ctrl & PLL_CTRL_CLKMUX_BYPASS) + { + return XTAL_FREQ; + } + + /* If the mux is disabled output frequency is 0 */ + + if ((ctrl & PLL_CTRL_CLKMUX_EN) == 0) + { + return 0; + } + + /* Get input VCO frequency */ + + vco = vco_freq_out(reg, frac); + if (vco == 0) + { + /* The VCO is off or unstable */ + + return 0; + } + + /* Calculate the output clock divider */ + + div = (getreg32(PLL_DIV(reg)) & PLL_DIV_ODIV_MASK) >> PLL_DIV_ODIV_SHIFT; + + /* According to spec, div0 = 2 and div1 = 3 */ + + if (div == 0) + { + div = 2; + } + else if (div == 1) + { + div = 3; + } + + return vco / div; +} + +static uint32_t pll_pfd_freq_out(uintptr_t reg, int pfd, int div2) +{ + struct pfd_parms_s parm; + uint32_t ctrl; + uint32_t div; + uint32_t vco; + + /* Read the correct PFD register set */ + + switch (pfd) + { + case 0: + ctrl = getreg32(PLL_DFS_CTRL_0(reg)); + div = getreg32(PLL_DFS_DIV_0(reg)); + break; + + case 1: + ctrl = getreg32(PLL_DFS_CTRL_1(reg)); + div = getreg32(PLL_DFS_DIV_1(reg)); + break; + + case 2: + ctrl = getreg32(PLL_DFS_CTRL_2(reg)); + div = getreg32(PLL_DFS_DIV_2(reg)); + break; + + default: + return 0; + } + + /* Get input VCO frequency */ + + vco = vco_freq_out(reg, true); + if (vco == 0) + { + /* The VCO is off or unstable */ + + return 0; + } + + /* If the DFS part is bypassed, the output is the VCO directly */ + + if (ctrl & PLL_DFS_BYPASS_EN) + { + return vco; + } + + /* Check if the DFS part is disabled */ + + if ((ctrl & PLL_DFS_ENABLE) == 0) + { + return 0; + } + + /* Populate the DFS parameters */ + + parm.mfi = (div & PLL_DFS_MFI_MASK) >> PLL_DFS_MFI_SHIFT; + parm.mfn = (div & PLL_DFS_MFN_MASK) >> PLL_DFS_MFN_SHIFT; + + return ((uint64_t)vco * 5) / (parm.mfi * 5 + parm.mfn) / div2; +} + +/**************************************************************************** + * Name: imx9_get_clock + * + * Description: + * This function returns the clock frequency of the specified functional + * clock. + * + * Input Parameters: + * clkname - Identifies the clock of interest + * frequency - The location where the peripheral clock frequency will be + * returned + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. -ENODEV is returned if the clock is not enabled or is not + * being clocked. + * + ****************************************************************************/ + +static int imx9_get_clock(int clkname, uint32_t *frequency) +{ + switch (clkname) + { + case OSC_24M: + *frequency = XTAL_FREQ; + break; + + case ARM_PLL: + *frequency = pll_freq_out(IMX9_ARMPLL_BASE, false); + break; + + case SYS_PLL1_IN: + *frequency = pll_freq_out(IMX9_SYSPLL_BASE, false); + break; + + case SYS_PLL1PFD0: + *frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 0, 1); + break; + + case SYS_PLL1PFD0DIV2: + *frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 0, 2); + break; + + case SYS_PLL1PFD1: + *frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 1, 1); + break; + + case SYS_PLL1PFD1DIV2: + *frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 1, 2); + break; + + case SYS_PLL1PFD2: + *frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 2, 1); + break; + + case SYS_PLL1PFD2DIV2: + *frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 2, 2); + break; + + case AUDIO_PLL1OUT: + *frequency = pll_freq_out(IMX9_AUDIOPLL_BASE, true); + break; + + case DRAM_PLLOUT: + *frequency = pll_freq_out(IMX9_DRAMPLL_BASE, true); + break; + + case VIDEO_PLL1OUT: + *frequency = pll_freq_out(IMX9_VIDEOPLL_BASE, true); + break; + + default: + return -ENODEV; + } + + return OK; +} + +#endif /* CONFIG_IMX9_CLK_OVER_SCMI */ int imx9_configure_clock(clock_config_t clk_config, bool enabled) { +#ifdef CONFIG_IMX9_CLK_OVER_SCMI sm_clock_t sm_clk = /* clang-format off */ { 0 @@ -205,6 +548,40 @@ int imx9_configure_clock(clock_config_t clk_config, bool enabled) sm_clk.flags = SCMI_CLOCK_RATE_FLAGS_ROUND(SCMI_CLOCK_ROUND_AUTO); return imx9_sm_setrootclock(&sm_clk); + +#else + + int ret; + int root = GET_CLOCK_ROOT(clk_config) + ROOT_CLOCK_OFFSET; + int gate = GET_CLOCK_GATE(clk_config); + + ret = imx9_ccm_configure_root_clock( + root, + GET_ROOT_MUX(clk_config), + GET_CLOCK_DIV(clk_config)); + if (ret) + { + return ret; + } + + ret = imx9_ccm_root_clock_on(root, enabled); + if (ret) + { + return ret; + } + + if (gate != CCM_LPCG_NONE) + { + ret = imx9_ccm_gate_on(gate, enabled); + if (ret) + { + return ret; + } + } + + return OK; + +#endif } /**************************************************************************** @@ -228,6 +605,7 @@ int imx9_configure_clock(clock_config_t clk_config, bool enabled) int imx9_get_rootclock(int clkroot, uint32_t *frequency) { +#ifdef CONFIG_IMX9_CLK_OVER_SCMI if (clkroot <= CCM_CR_COUNT) { uint32_t ret = 0; @@ -253,5 +631,32 @@ int imx9_get_rootclock(int clkroot, uint32_t *frequency) } } +#else + uint32_t reg; + uint32_t div; + uint32_t mux; + int clk_name; + + if (clkroot <= CCM_CR_COUNT) + { + reg = getreg32(IMX9_CCM_CR_CTRL(clkroot)); + + if ((reg & CCM_CR_CTRL_OFF) == CCM_CR_CTRL_OFF) + { + *frequency = 0; + } + else + { + mux = (reg & CCM_CR_CTRL_MUX_MASK) >> CCM_CR_CTRL_MUX_SHIFT; + clk_name = g_ccm_root_mux[clkroot][mux]; + imx9_get_clock(clk_name, frequency); + div = ((reg & CCM_CR_CTRL_DIV_MASK) >> CCM_CR_CTRL_DIV_SHIFT) + 1; + *frequency = *frequency / div; + } + + return OK; + } + +#endif return -ENODEV; } diff --git a/arch/arm/src/imx9/imx9_irq.c b/arch/arm/src/imx9/imx9_irq.c index b76e288f8f7..8afb558be79 100644 --- a/arch/arm/src/imx9/imx9_irq.c +++ b/arch/arm/src/imx9/imx9_irq.c @@ -287,7 +287,23 @@ static int imx9_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, } else #endif -#if IMX9_IRQ_NEXTINT > 218 +#if IMX9_IRQ_NEXTINT > 224 + if (extint < 256) + { + *regaddr = (NVIC_IRQ_ENABLE(224) + offset); + *bit = 1 << (extint - 224); + } + else +#endif +#if IMX9_IRQ_NEXTINT > 256 + if (extint < 288) + { + *regaddr = (NVIC_IRQ_ENABLE(256) + offset); + *bit = 1 << (extint - 256); + } + else +#endif +#if IMX9_IRQ_NEXTINT > 288 # error Missing logic #endif { diff --git a/arch/arm/src/imx9/imx9_mu.c b/arch/arm/src/imx9/imx9_mu.c index eecf765ff79..3a7b8eed77a 100644 --- a/arch/arm/src/imx9/imx9_mu.c +++ b/arch/arm/src/imx9/imx9_mu.c @@ -61,6 +61,22 @@ struct imx9_mudev_s * Private Data ****************************************************************************/ +#ifdef CONFIG_IMX9_MU1 +static struct imx9_mudev_s g_mu1_dev = /* clang-format off */ +{ + .mubase = IMX9_MU1_MUA_BASE, + .irq = IMX9_IRQ_MU1_A +}; /* clang-format on */ +#endif + +#ifdef CONFIG_IMX9_MU2 +static struct imx9_mudev_s g_mu2_dev = /* clang-format off */ +{ + .mubase = IMX9_MU2_MUA_BASE, + .irq = IMX9_IRQ_MU2_A +}; /* clang-format on */ +#endif + #ifdef CONFIG_IMX9_MU5 static struct imx9_mudev_s g_mu5_dev = /* clang-format off */ { @@ -149,6 +165,22 @@ struct imx9_mudev_s *imx9_mu_init(int index) { struct imx9_mudev_s *priv; +#ifdef CONFIG_IMX9_MU1 + if ((index == 1)) + { + priv = &g_mu1_dev; + } + + else +#endif +#ifdef CONFIG_IMX9_MU2 + if ((index == 2)) + { + priv = &g_mu2_dev; + } + + else +#endif #ifdef CONFIG_IMX9_MU5 if ((index == 5)) { diff --git a/arch/arm/src/imx9/imx9_xcache.c b/arch/arm/src/imx9/imx9_xcache.c new file mode 100644 index 00000000000..ccaa62d015a --- /dev/null +++ b/arch/arm/src/imx9/imx9_xcache.c @@ -0,0 +1,490 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_xcache.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "arm_internal.h" +#include "hardware/imx9_xcache.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +#define XCACHE_LINESIZE_BYTE 16 +#define XCACHE_SIZE (16*1024) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xcache_wait_busy + * + * Description: + * Wait for cache command to complete by polling GO bit + * + ****************************************************************************/ + +static inline void xcache_wait_busy(uintptr_t base) +{ + while (getreg32(base + IMX9_XCACHE_CCR_OFFSET) & XCACHE_CCR_GO) + { + } +} + +/**************************************************************************** + * Name: xcache_wait_line_busy + * + * Description: + * Wait for cache line command to complete by polling LGO bit + * + ****************************************************************************/ + +static inline void xcache_wait_line_busy(uintptr_t base) +{ + while (getreg32(base + IMX9_XCACHE_CSAR_OFFSET) & XCACHE_CSAR_LGO) + { + } +} + +/**************************************************************************** + * Name: xcache_invalidate_all + * + * Description: + * Invalidate entire cache (both ways) + * + ****************************************************************************/ + +static void xcache_invalidate_all(uintptr_t base) +{ + uint32_t regval; + + /* Invalidate all lines in both ways and initiate command */ + + regval = XCACHE_CCR_INVW0 | XCACHE_CCR_INVW1 | XCACHE_CCR_GO; + putreg32(regval, base + IMX9_XCACHE_CCR_OFFSET); + + /* Wait until command completes */ + + xcache_wait_busy(base); + + /* Clear command bits, precaution */ + + regval = getreg32(base + IMX9_XCACHE_CCR_OFFSET); + regval &= ~(XCACHE_CCR_INVW0 | XCACHE_CCR_INVW1); + putreg32(regval, base + IMX9_XCACHE_CCR_OFFSET); +} + +/**************************************************************************** + * Name: xcache_clean_all + * + * Description: + * Clean (push) entire cache (both ways) + * + ****************************************************************************/ + +static void xcache_clean_all(uintptr_t base) +{ + uint32_t regval; + + /* Push all modified lines in both ways */ + + regval = XCACHE_CCR_PUSHW0 | XCACHE_CCR_PUSHW1 | XCACHE_CCR_GO; + putreg32(regval, base + IMX9_XCACHE_CCR_OFFSET); + + /* Wait until command completes */ + + xcache_wait_busy(base); + + /* Clear command bits, precaution */ + + regval = getreg32(base + IMX9_XCACHE_CCR_OFFSET); + regval &= ~(XCACHE_CCR_PUSHW0 | XCACHE_CCR_PUSHW1); + putreg32(regval, base + IMX9_XCACHE_CCR_OFFSET); +} + +/**************************************************************************** + * Name: xcache_clean_invalidate_all + * + * Description: + * Clean and invalidate entire cache (both ways) + * + ****************************************************************************/ + +static void xcache_clean_invalidate_all(uintptr_t base) +{ + uint32_t regval; + + /* Push and invalidate all */ + + regval = XCACHE_CCR_PUSHW0 | XCACHE_CCR_PUSHW1 | + XCACHE_CCR_INVW0 | XCACHE_CCR_INVW1 | XCACHE_CCR_GO; + putreg32(regval, base + IMX9_XCACHE_CCR_OFFSET); + + /* Wait until command completes */ + + xcache_wait_busy(base); + + /* Clear command bits, precaution */ + + regval = getreg32(base + IMX9_XCACHE_CCR_OFFSET); + regval &= ~(XCACHE_CCR_PUSHW0 | XCACHE_CCR_PUSHW1 | + XCACHE_CCR_INVW0 | XCACHE_CCR_INVW1); + putreg32(regval, base + IMX9_XCACHE_CCR_OFFSET); +} + +/**************************************************************************** + * Name: xcache_op_by_range + * + * Description: + * Perform cache operation by address range (line by line) + * + * Input Parameters: + * base - XCACHE base address + * start - Start address (will be aligned to cache line) + * end - End address + 1 + * lcmd - Line command: 1=invalidate, 2=clean, 3=clean+invalidate + * + ****************************************************************************/ + +static void xcache_op_by_range(uintptr_t base, uintptr_t start, + uintptr_t end, uint32_t lcmd) +{ + uint32_t regval; + uintptr_t addr; + + if (start >= end) + { + return; + } + + /* Align start address to cache line size */ + + addr = start & ~(XCACHE_LINESIZE_BYTE - 1); + + /* Set line command and use physical address */ + + regval = getreg32(base + IMX9_XCACHE_CLCR_OFFSET); + regval &= ~XCACHE_CLCR_LCMD_MASK; + regval |= XCACHE_CLCR_LCMD(lcmd) | XCACHE_CLCR_LADSEL; + putreg32(regval, base + IMX9_XCACHE_CLCR_OFFSET); + + /* Process each cache line */ + + while (addr < end) + { + /* Set address and initiate line command */ + + regval = (addr & XCACHE_CSAR_PHYADDR_MASK) | XCACHE_CSAR_LGO; + putreg32(regval, base + IMX9_XCACHE_CSAR_OFFSET); + + /* Wait for completion */ + + xcache_wait_line_busy(base); + + addr += XCACHE_LINESIZE_BYTE; + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_get_icache_linesize + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPCAC_PC +size_t up_get_icache_linesize(void) +{ + return XCACHE_LINESIZE_BYTE; /* XCACHE line size is 32 bytes */ +} +#endif + +/**************************************************************************** + * Name: up_get_icache_size + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPCAC_PC +size_t up_get_icache_size(void) +{ + return XCACHE_SIZE; +} +#endif + +/**************************************************************************** + * Name: up_enable_icache + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPCAC_PC +void up_enable_icache(void) +{ + uint32_t regval; + + /* Return if already enabled */ + + regval = getreg32(IMX9_LPCAC_PC_BASE + IMX9_XCACHE_CCR_OFFSET); + if (regval & XCACHE_CCR_ENCACHE) + { + return; + } + + /* First, invalidate the entire cache */ + + xcache_invalidate_all(IMX9_LPCAC_PC_BASE); + + /* Now enable the cache */ + + regval = getreg32(IMX9_LPCAC_PC_BASE + IMX9_XCACHE_CCR_OFFSET); + regval |= XCACHE_CCR_ENCACHE; + putreg32(regval, IMX9_LPCAC_PC_BASE + IMX9_XCACHE_CCR_OFFSET); + + UP_ISB(); +} +#endif + +/**************************************************************************** + * Name: up_disable_icache + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPCAC_PC +void up_disable_icache(void) +{ + uint32_t regval; + + regval = getreg32(IMX9_LPCAC_PC_BASE + IMX9_XCACHE_CCR_OFFSET); + if (!(regval & XCACHE_CCR_ENCACHE)) + { + return; + } + + /* Disable the cache */ + + regval &= ~XCACHE_CCR_ENCACHE; + putreg32(regval, IMX9_LPCAC_PC_BASE + IMX9_XCACHE_CCR_OFFSET); + + UP_DSB(); + UP_ISB(); +} +#endif + +/**************************************************************************** + * Name: up_invalidate_icache + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPCAC_PC +void up_invalidate_icache(uintptr_t start, uintptr_t end) +{ + xcache_op_by_range(IMX9_LPCAC_PC_BASE, start, end, XCACHE_LCMD_INVALIDATE); + UP_ISB(); +} +#endif + +/**************************************************************************** + * Name: up_invalidate_icache_all + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPCAC_PC +void up_invalidate_icache_all(void) +{ + xcache_invalidate_all(IMX9_LPCAC_PC_BASE); + UP_ISB(); +} +#endif + +/**************************************************************************** + * Name: up_get_dcache_linesize + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPCAC_PS +size_t up_get_dcache_linesize(void) +{ + return XCACHE_LINESIZE_BYTE; +} +#endif + +/**************************************************************************** + * Name: up_get_dcache_size + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPCAC_PS +size_t up_get_dcache_size(void) +{ + return XCACHE_SIZE; +} +#endif + +/**************************************************************************** + * Name: up_enable_dcache + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPCAC_PS +void up_enable_dcache(void) +{ + uint32_t regval; + + /* Return if already enabled */ + + regval = getreg32(IMX9_LPCAC_PS_BASE + IMX9_XCACHE_CCR_OFFSET); + if (regval & XCACHE_CCR_ENCACHE) + { + return; + } + + /* First, invalidate the entire cache */ + + xcache_invalidate_all(IMX9_LPCAC_PS_BASE); + + /* Now enable the cache */ + + regval = getreg32(IMX9_LPCAC_PS_BASE + IMX9_XCACHE_CCR_OFFSET); + regval |= XCACHE_CCR_ENCACHE; + putreg32(regval, IMX9_LPCAC_PS_BASE + IMX9_XCACHE_CCR_OFFSET); + + UP_DSB(); +} +#endif + +/**************************************************************************** + * Name: up_disable_dcache + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPCAC_PS +void up_disable_dcache(void) +{ + uint32_t regval; + + regval = getreg32(IMX9_LPCAC_PS_BASE + IMX9_XCACHE_CCR_OFFSET); + if (!(regval & XCACHE_CCR_ENCACHE)) + { + return; + } + + /* First, clean any modified contents */ + + xcache_clean_all(IMX9_LPCAC_PS_BASE); + + /* Now disable the cache */ + + regval &= ~XCACHE_CCR_ENCACHE; + putreg32(regval, IMX9_LPCAC_PS_BASE + IMX9_XCACHE_CCR_OFFSET); + + UP_DSB(); +} +#endif + +/**************************************************************************** + * Name: up_invalidate_dcache + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPCAC_PS +void up_invalidate_dcache(uintptr_t start, uintptr_t end) +{ + xcache_op_by_range(IMX9_LPCAC_PS_BASE, start, end, XCACHE_LCMD_INVALIDATE); + UP_DSB(); +} +#endif + +/**************************************************************************** + * Name: up_invalidate_dcache_all + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPCAC_PS +void up_invalidate_dcache_all(void) +{ + xcache_invalidate_all(IMX9_LPCAC_PS_BASE); + UP_DSB(); +} +#endif + +/**************************************************************************** + * Name: up_clean_dcache + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPCAC_PS +void up_clean_dcache(uintptr_t start, uintptr_t end) +{ + xcache_op_by_range(IMX9_LPCAC_PS_BASE, start, end, XCACHE_LCMD_PUSH); + UP_DSB(); +} +#endif + +/**************************************************************************** + * Name: up_clean_dcache_all + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPCAC_PS +void up_clean_dcache_all(void) +{ + xcache_clean_all(IMX9_LPCAC_PS_BASE); + UP_DSB(); +} +#endif + +/**************************************************************************** + * Name: up_flush_dcache + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPCAC_PS +void up_flush_dcache(uintptr_t start, uintptr_t end) +{ + xcache_op_by_range(IMX9_LPCAC_PS_BASE, start, end, XCACHE_LCMD_CLEAR); + UP_DSB(); +} +#endif + +/**************************************************************************** + * Name: up_flush_dcache_all + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPCAC_PS +void up_flush_dcache_all(void) +{ + xcache_clean_invalidate_all(IMX9_LPCAC_PS_BASE); + UP_DSB(); +} +#endif + +/**************************************************************************** + * Name: up_coherent_dcache + ****************************************************************************/ + +#if defined(CONFIG_IMX9_LPCAC_PS) +void up_coherent_dcache(uintptr_t addr, size_t len) +{ + /* Clean PS cache and invalidate PC cache for code coherency */ + + up_clean_dcache(addr, addr + len); +#if defined(CONFIG_IMX9_LPCAC_PC) + up_invalidate_icache(addr, addr + len); +#endif +} +#endif \ No newline at end of file