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Merged in raiden00/nuttx_pe (pull request #877)
Improvements for STM32 PWM arch/arm/src/stm32/stm32_pwm: add support for all PWM modes arch/arm/src/stm32/stm32_pwm: add interface to change PWM mode arch/arm/src/stm32/stm32_pwm: refactor pwm_mode_configure() arch/arm/src/stm32/stm32_pwm: STM32_PWM_CHANx corresponds to the timer channel and STM32_PWM_OUTx corresponds to the timer channel output arch/arm/src/stm32/stm32_pwm: add CHAN5 and CHAN6 to PWM_TIMx_NCHANNELS arch/arm/src/stm32/stm32_pwm: calculate the PWM_TIMx_NCHANNELS if CONFIG_STM32_PWM_MULTICHAN is selected Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
raiden00pl
Gregory Nutt
+218
-247
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Load Diff
+172
-233
File diff suppressed because it is too large
Load Diff
@@ -123,11 +123,9 @@
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#include <arch/board/board.h>
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#include "hardware/stm32_tim.h"
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/* Configuration needed by upper-half PWM driver */
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/* PWM driver channels configuration */
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#ifdef CONFIG_PWM
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#ifdef CONFIG_PWM_MULTICHAN
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#ifdef CONFIG_STM32_PWM_MULTICHAN
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#ifdef CONFIG_STM32_TIM1_CHANNEL1
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# define PWM_TIM1_CHANNEL1 1
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@@ -149,8 +147,19 @@
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#else
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# define PWM_TIM1_CHANNEL4 0
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#endif
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#ifdef CONFIG_STM32_TIM1_CHANNEL5
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# define PWM_TIM1_CHANNEL5 1
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#else
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# define PWM_TIM1_CHANNEL5 0
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#endif
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#ifdef CONFIG_STM32_TIM1_CHANNEL6
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# define PWM_TIM1_CHANNEL6 1
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#else
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# define PWM_TIM1_CHANNEL6 0
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#endif
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#define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \
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PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4)
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PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \
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PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6)
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#ifdef CONFIG_STM32_TIM2_CHANNEL1
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# define PWM_TIM2_CHANNEL1 1
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@@ -264,8 +273,19 @@
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#else
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# define PWM_TIM8_CHANNEL4 0
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#endif
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#ifdef CONFIG_STM32_TIM8_CHANNEL5
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# define PWM_TIM8_CHANNEL5 1
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#else
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# define PWM_TIM8_CHANNEL5 0
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#endif
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#ifdef CONFIG_STM32_TIM8_CHANNEL6
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# define PWM_TIM8_CHANNEL6 1
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#else
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# define PWM_TIM8_CHANNEL6 0
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#endif
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#define PWM_TIM8_NCHANNELS (PWM_TIM8_CHANNEL1 + PWM_TIM8_CHANNEL2 + \
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PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4)
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PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \
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PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6)
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#ifdef CONFIG_STM32_TIM9_CHANNEL1
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# define PWM_TIM9_CHANNEL1 1
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@@ -603,9 +623,7 @@
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# define PWM_TIM17_NCHANNELS 1
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#endif
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#endif /* CONFIG_PWM_MULTICHAN */
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#endif /* CONFIG_PWM */
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#endif /* CONFIG_STM32_PWM_MULTICHAN */
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#ifdef CONFIG_STM32_TIM1_CH1OUT
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# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
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@@ -876,6 +894,8 @@
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/* Low-level ops helpers ************************************************************/
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#ifdef CONFIG_STM32_PWM_LL_OPS
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/* NOTE: low-level ops accept pwm_lowerhalf_s as first argument, but llops access
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* can be found in stm32_pwm_dev_s
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*/
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@@ -886,6 +906,8 @@
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(dev)->ops->shutdown((FAR struct pwm_lowerhalf_s *)dev)
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#define PWM_CCR_UPDATE(dev, index, ccr) \
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(dev)->llops->ccr_update((FAR struct pwm_lowerhalf_s *)dev, index, ccr)
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#define PWM_MODE_UPDATE(dev, index, mode) \
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(dev)->llops->mode_update((FAR struct pwm_lowerhalf_s *)dev, index, mode)
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#define PWM_CCR_GET(dev, index) \
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(dev)->llops->ccr_get((FAR struct pwm_lowerhalf_s *)dev, index)
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#define PWM_ARR_UPDATE(dev, arr) \
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@@ -913,6 +935,8 @@
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#define PWM_DT_UPDATE(dev, dt) \
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(dev)->llops->dt_update((FAR struct pwm_lowerhalf_s *)dev, dt)
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#endif
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/************************************************************************************
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* Public Types
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************************************************************************************/
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@@ -946,37 +970,57 @@ enum stm32_pwm_idle_e
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/* PWM channel mode */
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enum stm32_chan_mode_e
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enum stm32_pwm_chanmode_e
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{
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STM32_CHANMODE_PWM1 = 0,
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STM32_CHANMODE_PWM2 = 1,
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STM32_CHANMODE_FRZN = 0, /* CCRx matches has no effects on outputs */
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STM32_CHANMODE_CHACT = 1, /* OCxREF active on match */
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STM32_CHANMODE_CHINACT = 2, /* OCxREF inactive on match */
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STM32_CHANMODE_OCREFTOG = 3, /* OCxREF toggles when TIMy_CNT=TIMyCCRx */
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STM32_CHANMODE_OCREFLO = 4, /* OCxREF is forced low */
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STM32_CHANMODE_OCREFHI = 5, /* OCxREF is forced high */
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STM32_CHANMODE_PWM1 = 6, /* PWM mode 1 */
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STM32_CHANMODE_PWM2 = 7, /* PWM mode 2 */
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#ifdef HAVE_IP_TIMERS_V2
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STM32_CHANMODE_COMBINED1 = 2,
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STM32_CHANMODE_COMBINED2 = 3,
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STM32_CHANMODE_ASYMMETRIC1 = 4,
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STM32_CHANMODE_ASYMMETRIC2 = 5
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STM32_CHANMODE_COMBINED1 = 8, /* Combined PWM mode 1 */
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STM32_CHANMODE_COMBINED2 = 9, /* Combined PWM mode 2 */
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STM32_CHANMODE_ASYMMETRIC1 = 10, /* Asymmetric PWM mode 1 */
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STM32_CHANMODE_ASYMMETRIC2 = 11, /* Asymmetric PWM mode 2 */
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#endif
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};
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/* Timer channel */
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/* PWM timer channel */
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enum stm32_chan_e
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enum stm32_pwm_chan_e
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{
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STM32_CHAN1 = (1 << 0),
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STM32_CHAN1N = (1 << 1),
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STM32_CHAN2 = (1 << 2),
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STM32_CHAN2N = (1 << 3),
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STM32_CHAN3 = (1 << 4),
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STM32_CHAN3N = (1 << 5),
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STM32_CHAN4 = (1 << 6),
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/* No complementary output for CH4 */
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STM32_PWM_CHAN1 = 1,
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STM32_PWM_CHAN2 = 2,
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STM32_PWM_CHAN3 = 3,
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STM32_PWM_CHAN4 = 4,
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#ifdef HAVE_IP_TIMERS_V2
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STM32_PWM_CHAN5 = 5,
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STM32_PWM_CHAN6 = 6,
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#endif
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};
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/* PWM timer channel output */
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enum stm32_pwm_output_e
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{
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STM32_PWM_OUT1 = (1 << 0),
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STM32_PWM_OUT1N = (1 << 1),
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STM32_PWM_OUT2 = (1 << 2),
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STM32_PWM_OUT2N = (1 << 3),
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STM32_PWM_OUT3 = (1 << 4),
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STM32_PWM_OUT3N = (1 << 5),
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STM32_PWM_OUT4 = (1 << 6),
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/* 1 << 7 reserved - no complementary output for CH4 */
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#ifdef HAVE_IP_TIMERS_V2
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/* Only available inside micro */
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STM32_CHAN5 = (1 << 7),
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/* 1<<8 reserved */
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STM32_CHAN6 = (1 << 9),
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/* 1<<10 reserved */
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STM32_PWM_OUT5 = (1 << 8),
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/* 1 << 9 reserved - no complementary output for CH5 */
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STM32_PWM_OUT6 = (1 << 10),
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/* 1 << 11 reserved - no complementary output for CH6 */
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#endif
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};
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@@ -1010,6 +1054,10 @@ struct stm32_pwm_ops_s
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int (*ccr_update)(FAR struct pwm_lowerhalf_s *dev, uint8_t index, uint32_t ccr);
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/* Update PWM mode */
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int (*mode_update)(FAR struct pwm_lowerhalf_s *dev, uint8_t index, uint32_t mode);
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/* Get CCR register */
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uint32_t (*ccr_get)(FAR struct pwm_lowerhalf_s *dev, uint8_t index);
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@@ -405,9 +405,9 @@ int highpri_main(int argc, char *argv[])
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PWM_CCR_UPDATE(pwm1, 1, 0x0f00);
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/* Enable TIM1 CHAN1 */
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/* Enable TIM1 OUT1 */
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PWM_OUTPUTS_ENABLE(pwm1, STM32_CHAN1, true);
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PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true);
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#else
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# error T1CC1 only supported for now
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#endif
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@@ -284,8 +284,6 @@
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/* TIM1 PWM configuration ***************************************************/
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# define PWM_TIM1_NCHANNELS 4
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# define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_1 /* TIM1 CH1 - PA8 */
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# define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_3 /* TIM1 CH1N - PA7 */
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/* TIM1 CH2 - PA9 */
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@@ -441,9 +441,9 @@ int highpri_main(int argc, char *argv[])
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PWM_CCR_UPDATE(pwm1, 1, 0x0f00);
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/* Enable TIM1 CHAN1 */
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/* Enable TIM1 OUT1 */
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PWM_OUTPUTS_ENABLE(pwm1, STM32_CHAN1, true);
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PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true);
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#else
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# error T1CC1 only supported for now
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#endif
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@@ -389,9 +389,9 @@ int highpri_main(int argc, char *argv[])
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PWM_CCR_UPDATE(pwm1, 1, 0x0f00);
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/* Enable TIM1 CHAN1 */
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/* Enable TIM1 OUT1 */
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PWM_OUTPUTS_ENABLE(pwm1, STM32_CHAN1, true);
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PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true);
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#else
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# error T1CC1 only supported for now
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#endif
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