diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 4f59da57a6b..92da8204150 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -3230,11 +3230,11 @@ if STM32_TIM1_CHANNEL1 config STM32_TIM1_CH1MODE int "TIM1 Channel 1 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM1_CH1OUT bool "TIM1 Channel 1 Output" @@ -3260,11 +3260,11 @@ if STM32_TIM1_CHANNEL2 config STM32_TIM1_CH2MODE int "TIM1 Channel 2 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM1_CH2OUT bool "TIM1 Channel 2 Output" @@ -3290,11 +3290,11 @@ if STM32_TIM1_CHANNEL3 config STM32_TIM1_CH3MODE int "TIM1 Channel 3 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM1_CH3OUT bool "TIM1 Channel 3 Output" @@ -3320,11 +3320,11 @@ if STM32_TIM1_CHANNEL4 config STM32_TIM1_CH4MODE int "TIM1 Channel 4 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM1_CH4OUT bool "TIM1 Channel 4 Output" @@ -3345,10 +3345,10 @@ if STM32_TIM1_CHANNEL5 config STM32_TIM1_CH5MODE int "TIM1 Channel 5 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM1_CH5OUT bool "TIM1 Channel 5 Output" @@ -3369,10 +3369,10 @@ if STM32_TIM1_CHANNEL6 config STM32_TIM1_CH6MODE int "TIM1 Channel 6 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM1_CH6OUT bool "TIM1 Channel 6 Output" @@ -3454,11 +3454,11 @@ endif # STM32_TIM1_CHANNEL = 4 config STM32_TIM1_CHMODE int "TIM1 Channel Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32_PWM_MULTICHAN @@ -3499,11 +3499,11 @@ if STM32_TIM2_CHANNEL1 config STM32_TIM2_CH1MODE int "TIM2 Channel 1 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM2_CH1OUT bool "TIM2 Channel 1 Output" @@ -3523,11 +3523,11 @@ if STM32_TIM2_CHANNEL2 config STM32_TIM2_CH2MODE int "TIM2 Channel 2 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM2_CH2OUT bool "TIM2 Channel 2 Output" @@ -3547,11 +3547,11 @@ if STM32_TIM2_CHANNEL3 config STM32_TIM2_CH3MODE int "TIM2 Channel 3 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM2_CH3OUT bool "TIM2 Channel 3 Output" @@ -3571,11 +3571,11 @@ if STM32_TIM2_CHANNEL4 config STM32_TIM2_CH4MODE int "TIM2 Channel 4 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM2_CH4OUT bool "TIM2 Channel 4 Output" @@ -3639,11 +3639,11 @@ endif # STM32_TIM2_CHANNEL = 4 config STM32_TIM2_CHMODE int "TIM2 Channel Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32_PWM_MULTICHAN @@ -3684,11 +3684,11 @@ if STM32_TIM3_CHANNEL1 config STM32_TIM3_CH1MODE int "TIM3 Channel 1 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM3_CH1OUT bool "TIM3 Channel 1 Output" @@ -3708,11 +3708,11 @@ if STM32_TIM3_CHANNEL2 config STM32_TIM3_CH2MODE int "TIM3 Channel 2 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM3_CH2OUT bool "TIM3 Channel 2 Output" @@ -3732,11 +3732,11 @@ if STM32_TIM3_CHANNEL3 config STM32_TIM3_CH3MODE int "TIM3 Channel 3 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM3_CH3OUT bool "TIM3 Channel 3 Output" @@ -3756,11 +3756,11 @@ if STM32_TIM3_CHANNEL4 config STM32_TIM3_CH4MODE int "TIM3 Channel 4 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM3_CH4OUT bool "TIM3 Channel 4 Output" @@ -3824,11 +3824,11 @@ endif # STM32_TIM3_CHANNEL = 4 config STM32_TIM3_CHMODE int "TIM3 Channel Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32_PWM_MULTICHAN @@ -3869,11 +3869,11 @@ if STM32_TIM4_CHANNEL1 config STM32_TIM4_CH1MODE int "TIM4 Channel 1 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM4_CH1OUT bool "TIM4 Channel 1 Output" @@ -3893,11 +3893,11 @@ if STM32_TIM4_CHANNEL2 config STM32_TIM4_CH2MODE int "TIM4 Channel 2 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM4_CH2OUT bool "TIM4 Channel 2 Output" @@ -3917,11 +3917,11 @@ if STM32_TIM4_CHANNEL3 config STM32_TIM4_CH3MODE int "TIM4 Channel 3 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM4_CH3OUT bool "TIM4 Channel 3 Output" @@ -3941,11 +3941,11 @@ if STM32_TIM4_CHANNEL4 config STM32_TIM4_CH4MODE int "TIM4 Channel 4 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM4_CH4OUT bool "TIM4 Channel 4 Output" @@ -4009,11 +4009,11 @@ endif # STM32_TIM4_CHANNEL = 4 config STM32_TIM4_CHMODE int "TIM4 Channel Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32_PWM_MULTICHAN @@ -4054,11 +4054,11 @@ if STM32_TIM5_CHANNEL1 config STM32_TIM5_CH1MODE int "TIM5 Channel 1 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM5_CH1OUT bool "TIM5 Channel 1 Output" @@ -4078,11 +4078,11 @@ if STM32_TIM5_CHANNEL2 config STM32_TIM5_CH2MODE int "TIM5 Channel 2 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM5_CH2OUT bool "TIM5 Channel 2 Output" @@ -4102,11 +4102,11 @@ if STM32_TIM5_CHANNEL3 config STM32_TIM5_CH3MODE int "TIM5 Channel 3 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM5_CH3OUT bool "TIM5 Channel 3 Output" @@ -4126,11 +4126,11 @@ if STM32_TIM5_CHANNEL4 config STM32_TIM5_CH4MODE int "TIM5 Channel 4 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM5_CH4OUT bool "TIM5 Channel 4 Output" @@ -4194,11 +4194,11 @@ endif # STM32_TIM5_CHANNEL = 4 config STM32_TIM5_CHMODE int "TIM5 Channel Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32_PWM_MULTICHAN @@ -4260,11 +4260,11 @@ if STM32_TIM8_CHANNEL1 config STM32_TIM8_CH1MODE int "TIM8 Channel 1 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM8_CH1OUT bool "TIM8 Channel 1 Output" @@ -4290,11 +4290,11 @@ if STM32_TIM8_CHANNEL2 config STM32_TIM8_CH2MODE int "TIM8 Channel 2 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM8_CH2OUT bool "TIM8 Channel 2 Output" @@ -4320,11 +4320,11 @@ if STM32_TIM8_CHANNEL3 config STM32_TIM8_CH3MODE int "TIM8 Channel 3 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM8_CH3OUT bool "TIM8 Channel 3 Output" @@ -4350,11 +4350,11 @@ if STM32_TIM8_CHANNEL4 config STM32_TIM8_CH4MODE int "TIM8 Channel 4 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM8_CH4OUT bool "TIM8 Channel 4 Output" @@ -4375,10 +4375,10 @@ if STM32_TIM8_CHANNEL5 config STM32_TIM8_CH5MODE int "TIM8 Channel 5 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM8_CH5OUT bool "TIM8 Channel 5 Output" @@ -4399,10 +4399,10 @@ if STM32_TIM8_CHANNEL6 config STM32_TIM8_CH6MODE int "TIM8 Channel 6 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM8_CH6OUT bool "TIM8 Channel 6 Output" @@ -4484,11 +4484,11 @@ endif # STM32_TIM8_CHANNEL = 4 config STM32_TIM8_CHMODE int "TIM8 Channel Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32_PWM_MULTICHAN @@ -4522,11 +4522,11 @@ if STM32_TIM9_CHANNEL1 config STM32_TIM9_CH1MODE int "TIM9 Channel 1 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM9_CH1OUT bool "TIM9 Channel 1 Output" @@ -4546,11 +4546,11 @@ if STM32_TIM9_CHANNEL2 config STM32_TIM9_CH2MODE int "TIM9 Channel 2 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM9_CH2OUT bool "TIM9 Channel 2 Output" @@ -4594,11 +4594,11 @@ endif # STM32_TIM9_CHANNEL = 2 config STM32_TIM9_CHMODE int "TIM9 Channel Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32_PWM_MULTICHAN @@ -4632,11 +4632,11 @@ if STM32_TIM10_CHANNEL1 config STM32_TIM10_CH1MODE int "TIM10 Channel 1 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM10_CH1OUT bool "TIM10 Channel 1 Output" @@ -4670,11 +4670,11 @@ endif # STM32_TIM10_CHANNEL = 1 config STM32_TIM10_CHMODE int "TIM10 Channel Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32_PWM_MULTICHAN @@ -4708,11 +4708,11 @@ if STM32_TIM11_CHANNEL1 config STM32_TIM11_CH1MODE int "TIM11 Channel 1 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM11_CH1OUT bool "TIM11 Channel 1 Output" @@ -4746,11 +4746,11 @@ endif # STM32_TIM11_CHANNEL = 1 config STM32_TIM11_CHMODE int "TIM11 Channel Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32_PWM_MULTICHAN @@ -4784,11 +4784,11 @@ if STM32_TIM12_CHANNEL1 config STM32_TIM12_CH1MODE int "TIM12 Channel 1 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM12_CH1OUT bool "TIM12 Channel 1 Output" @@ -4808,11 +4808,11 @@ if STM32_TIM12_CHANNEL2 config STM32_TIM12_CH2MODE int "TIM12 Channel 2 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM12_CH2OUT bool "TIM12 Channel 2 Output" @@ -4856,11 +4856,11 @@ endif # STM32_TIM12_CHANNEL = 2 config STM32_TIM12_CHMODE int "TIM12 Channel Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32_PWM_MULTICHAN @@ -4894,11 +4894,11 @@ if STM32_TIM13_CHANNEL1 config STM32_TIM13_CH1MODE int "TIM13 Channel 1 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM13_CH1OUT bool "TIM13 Channel 1 Output" @@ -4932,11 +4932,11 @@ endif # STM32_TIM13_CHANNEL = 1 config STM32_TIM13_CHMODE int "TIM13 Channel Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32_PWM_MULTICHAN @@ -4970,11 +4970,11 @@ if STM32_TIM14_CHANNEL1 config STM32_TIM14_CH1MODE int "TIM14 Channel 1 Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM14_CH1OUT bool "TIM14 Channel 1 Output" @@ -5008,11 +5008,11 @@ endif # STM32_TIM14_CHANNEL = 1 config STM32_TIM14_CHMODE int "TIM14 Channel Mode" - default 0 - range 0 5 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32_PWM_MULTICHAN @@ -5066,11 +5066,11 @@ if STM32_TIM15_CHANNEL1 config STM32_TIM15_CH1MODE int "TIM15 Channel 1 Mode" - default 0 - range 0 3 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 9 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM15_CH1OUT bool "TIM15 Channel 1 Output" @@ -5096,11 +5096,11 @@ if STM32_TIM15_CHANNEL2 config STM32_TIM15_CH2MODE int "TIM15 Channel 2 Mode" - default 0 - range 0 3 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 9 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM15_CH2OUT bool "TIM15 Channel 2 Output" @@ -5156,11 +5156,11 @@ endif # STM32_TIM15_CHANNEL = 2 config STM32_TIM15_CHMODE int "TIM15 Channel Mode" - default 0 - range 0 3 if STM32_HAVE_IP_TIMERS_V2 - range 0 1 if !STM32_HAVE_IP_TIMERS_V2 + default 6 + range 0 9 if STM32_HAVE_IP_TIMERS_V2 + range 0 7 if !STM32_HAVE_IP_TIMERS_V2 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32_PWM_MULTICHAN @@ -5214,10 +5214,10 @@ if STM32_TIM16_CHANNEL1 config STM32_TIM16_CH1MODE int "TIM16 Channel 1 Mode" - default 0 - range 0 1 + default 6 + range 0 7 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM16_CH1OUT bool "TIM16 Channel 1 Output" @@ -5251,10 +5251,10 @@ endif # STM32_TIM16_CHANNEL = 1 config STM32_TIM16_CHMODE int "TIM16 Channel Mode" - default 0 - range 0 1 + default 6 + range 0 7 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32_PWM_MULTICHAN @@ -5308,10 +5308,10 @@ if STM32_TIM17_CHANNEL1 config STM32_TIM17_CH1MODE int "TIM17 Channel 1 Mode" - default 0 - range 0 1 + default 6 + range 0 7 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32_TIM17_CH1OUT bool "TIM17 Channel 1 Output" @@ -5345,10 +5345,10 @@ endif # STM32_TIM17_CHANNEL = 1 config STM32_TIM17_CHMODE int "TIM17 Channel Mode" - default 0 - range 0 1 + default 6 + range 0 7 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32_PWM_MULTICHAN @@ -5370,38 +5370,6 @@ config STM32_PWM_TRGO ---help--- Enable TRGO support for PWM driver -config STM32_TIM1_PWM_ADC - bool "TIM1 PWM ADC " - default n - depends on STM32_TIM1 && STM32_ADC && STM32_TIM1_PWM - ---help--- - ADC trigger with TIM1 configured as PWM source - -choice - prompt "Select TIM1 PWM ADC channel" - default STM32_TIM1_PWM_ADC1 - depends on STM32_TIM1_PWM_ADC - -config STM32_TIM1_PWM_ADC1 - bool "TIM1 PWM ADC1" - depends on STM32_ADC1 - ---help--- - Trigger ADC1 with PWM configured TIM1 - -config STM32_TIM1_PWM_ADC2 - bool "TIM1 PWM ADC2" - depends on STM32_ADC2 - ---help--- - Trigger ADC2 with PWM configured TIM1 - -config STM32_TIM1_PWM_ADC3 - bool "TIM1 PWM ADC3" - depends on STM32_ADC3 - ---help--- - Trigger ADC3 with PWM configured TIM1 - -endchoice - config STM32_TIM1_ADC bool "TIM1 ADC" default n @@ -5663,6 +5631,9 @@ config STM32_HAVE_ADC2_TIMER config STM32_HAVE_ADC3_TIMER bool +config STM32_HAVE_ADC4_TIMER + bool + config STM32_ADC1_SAMPLE_FREQUENCY int "ADC1 Sampling Frequency" default 100 @@ -5674,7 +5645,7 @@ config STM32_ADC1_TIMTRIG int "ADC1 Timer Trigger" default 0 range 0 4 - depends on STM32_HAVE_ADC1_TIMER || STM32_TIM1_PWM_ADC1 + depends on STM32_HAVE_ADC1_TIMER ---help--- Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO @@ -5689,7 +5660,7 @@ config STM32_ADC2_TIMTRIG int "ADC2 Timer Trigger" default 0 range 0 4 - depends on STM32_HAVE_ADC2_TIMER || STM32_TIM1_PWM_ADC2 + depends on STM32_HAVE_ADC2_TIMER ---help--- Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO @@ -5704,7 +5675,7 @@ config STM32_ADC3_TIMTRIG int "ADC3 Timer Trigger" default 0 range 0 4 - depends on STM32_HAVE_ADC3_TIMER || STM32_TIM1_PWM_ADC3 + depends on STM32_HAVE_ADC3_TIMER ---help--- Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c index 9761653c6d6..5031aec1d56 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/stm32/stm32_pwm.c @@ -369,7 +369,7 @@ struct stm32_pwm_break_s struct stm32_pwmchan_s { uint8_t channel:4; /* Timer output channel: {1,..4} */ - uint8_t mode:4; /* PWM channel mode (see stm32_chan_mode_e) */ + uint8_t mode:4; /* PWM channel mode (see stm32_pwm_chanmode_e) */ struct stm32_pwm_out_s out1; /* PWM output configuration */ #ifdef HAVE_BREAK struct stm32_pwm_break_s brk; /* PWM break configuration */ @@ -442,7 +442,7 @@ static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg); static int pwm_frequency_update(FAR struct pwm_lowerhalf_s *dev, uint32_t frequency); -static int pwm_mode_configure(FAR struct stm32_pwmtimer_s *priv, +static int pwm_mode_configure(FAR struct pwm_lowerhalf_s *dev, uint8_t channel, uint32_t mode); static int pwm_timer_configure(FAR struct stm32_pwmtimer_s *priv); static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv, @@ -537,6 +537,7 @@ static const struct stm32_pwm_ops_s g_llpwmops = .configure = pwm_configure, .soft_break = pwm_soft_break, .ccr_update = pwm_ccr_update, + .mode_update = pwm_mode_configure, .ccr_get = pwm_ccr_get, .arr_update = pwm_arr_update, .arr_get = pwm_arr_get, @@ -2119,38 +2120,38 @@ static int pwm_ccr_update(FAR struct pwm_lowerhalf_s *dev, uint8_t index, switch (index) { - case 1: + case STM32_PWM_CHAN1: { offset = STM32_GTIM_CCR1_OFFSET; break; } - case 2: + case STM32_PWM_CHAN2: { offset = STM32_GTIM_CCR2_OFFSET; break; } - case 3: + case STM32_PWM_CHAN3: { offset = STM32_GTIM_CCR3_OFFSET; break; } - case 4: + case STM32_PWM_CHAN4: { offset = STM32_GTIM_CCR4_OFFSET; break; } #ifdef HAVE_IP_TIMERS_V2 - case 5: + case STM32_PWM_CHAN5: { offset = STM32_ATIM_CCR5_OFFSET; break; } - case 6: + case STM32_PWM_CHAN6: { offset = STM32_ATIM_CCR6_OFFSET; break; @@ -2183,38 +2184,38 @@ static uint32_t pwm_ccr_get(FAR struct pwm_lowerhalf_s *dev, uint8_t index) switch (index) { - case 1: + case STM32_PWM_CHAN1: { offset = STM32_GTIM_CCR1_OFFSET; break; } - case 2: + case STM32_PWM_CHAN2: { offset = STM32_GTIM_CCR2_OFFSET; break; } - case 3: + case STM32_PWM_CHAN3: { offset = STM32_GTIM_CCR3_OFFSET; break; } - case 4: + case STM32_PWM_CHAN4: { offset = STM32_GTIM_CCR4_OFFSET; break; } #ifdef HAVE_IP_TIMERS_V2 - case 5: + case STM32_PWM_CHAN5: { offset = STM32_ATIM_CCR5_OFFSET; break; } - case 6: + case STM32_PWM_CHAN6: { offset = STM32_ATIM_CCR6_OFFSET; break; @@ -2533,18 +2534,16 @@ errout: * ****************************************************************************/ -static int pwm_mode_configure(FAR struct stm32_pwmtimer_s *priv, +static int pwm_mode_configure(FAR struct pwm_lowerhalf_s *dev, uint8_t channel, uint32_t mode) { + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; uint32_t chanmode = 0; - uint32_t ocmode1 = 0; - uint32_t ocmode2 = 0; - uint32_t ccmr1 = 0; - uint32_t ccmr2 = 0; + uint32_t ocmode = 0; + uint32_t ccmr = 0; + uint32_t offset = 0; int ret = OK; #ifdef HAVE_IP_TIMERS_V2 - uint32_t ccmr3 = 0; - uint32_t ocmode3 = 0; bool ocmbit = false; #endif @@ -2565,6 +2564,42 @@ static int pwm_mode_configure(FAR struct stm32_pwmtimer_s *priv, switch (mode) { + case STM32_CHANMODE_FRZN: + { + chanmode = GTIM_CCMR_MODE_FRZN; + break; + } + + case STM32_CHANMODE_CHACT: + { + chanmode = GTIM_CCMR_MODE_CHACT; + break; + } + + case STM32_CHANMODE_CHINACT: + { + chanmode = GTIM_CCMR_MODE_CHINACT; + break; + } + + case STM32_CHANMODE_OCREFTOG: + { + chanmode = GTIM_CCMR_MODE_OCREFTOG; + break; + } + + case STM32_CHANMODE_OCREFLO: + { + chanmode = GTIM_CCMR_MODE_OCREFLO; + break; + } + + case STM32_CHANMODE_OCREFHI: + { + chanmode = GTIM_CCMR_MODE_OCREFHI; + break; + } + case STM32_CHANMODE_PWM1: { chanmode = ATIM_CCMR_MODE_PWM1; @@ -2615,207 +2650,29 @@ static int pwm_mode_configure(FAR struct stm32_pwmtimer_s *priv, } } - /* Get current registers */ - - ccmr1 = pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr2 = pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET); -#ifdef HAVE_IP_TIMERS_V2 - if (priv->timtype == TIMTYPE_ADVANCED) - { - ccmr3 = pwm_getreg(priv, STM32_ATIM_CCMR3_OFFSET); - } -#endif + /* Get CCMR offset */ switch (channel) { - case 1: /* PWM Mode configuration: Channel 1 */ + case STM32_PWM_CHAN1: + case STM32_PWM_CHAN2: { - /* Reset current channel 1 mode configuration */ - - ccmr1 &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | - ATIM_CCMR1_OC1PE); - - /* Configure CC1 as output */ - - ocmode1 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT); - - /* Configure Compare 1 mode */ - - ocmode1 |= (chanmode << ATIM_CCMR1_OC1M_SHIFT); - - /* Enable CCR2 preload */ - - ocmode1 |= ATIM_CCMR1_OC1PE; - -#ifdef HAVE_IP_TIMERS_V2 - /* Reset current OC bit */ - - ccmr1 &= ~(ATIM_CCMR1_OC1M); - - /* Set an additional OC1M bit */ - - if (ocmbit) - { - ocmode1 |= ATIM_CCMR1_OC1M; - } -#endif + offset = STM32_GTIM_CCMR1_OFFSET; break; } - case 2: /* PWM Mode configuration: Channel 2 */ + case STM32_PWM_CHAN3: + case STM32_PWM_CHAN4: { - /* Reset current channel 2 mode configuration */ - - ccmr1 &= ~(ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | - ATIM_CCMR1_OC2PE); - - /* Configure CC2 as output */ - - ocmode1 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT); - - /* Configure Compare 2 mode */ - - ocmode1 |= (chanmode << ATIM_CCMR1_OC2M_SHIFT); - - /* Enable CCR2 preload */ - - ocmode1 |= ATIM_CCMR1_OC2PE; - -#ifdef HAVE_IP_TIMERS_V2 - /* Reset current OC bit */ - - ccmr1 &= ~(ATIM_CCMR1_OC2M); - - /* Set an additional OC2M bit */ - - if (ocmbit) - { - ocmode1 |= ATIM_CCMR1_OC2M; - } -#endif - break; - } - - case 3: /* PWM Mode configuration: Channel 3 */ - { - /* Reset current channel 3 mode configuration */ - - ccmr2 &= ~(ATIM_CCMR2_CC3S_MASK | ATIM_CCMR2_OC3M_MASK | - ATIM_CCMR2_OC3PE); - - /* Configure CC3 as output */ - - ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT); - - /* Configure Compare 3 mode */ - - ocmode2 |= (chanmode << ATIM_CCMR2_OC3M_SHIFT); - - /* Enable CCR3 preload */ - - ocmode2 |= ATIM_CCMR2_OC3PE; - -#ifdef HAVE_IP_TIMERS_V2 - /* Reset current OC bit */ - - ccmr2 &= ~(ATIM_CCMR2_OC3M); - - /* Set an additional OC3M bit */ - - if (ocmbit) - { - ocmode2 |= ATIM_CCMR2_OC3M; - } -#endif - break; - } - - case 4: /* PWM Mode configuration: Channel 4 */ - { - /* Reset current channel 4 mode configuration */ - - ccmr2 &= ~(ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | - ATIM_CCMR2_OC4PE); - - /* Configure Compare 4 mode */ - - ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT); - - /* Enable CCR4 preload */ - - ocmode2 |= (chanmode << ATIM_CCMR2_OC4M_SHIFT); - - /* Enable CCR4 preload */ - - ocmode2 |= ATIM_CCMR2_OC4PE; - -#ifdef HAVE_IP_TIMERS_V2 - /* Reset current OC bit */ - - ccmr2 &= ~(ATIM_CCMR2_OC4M); - - /* Set an additional OC4M bit */ - - if (ocmbit) - { - ocmode2 |= ATIM_CCMR2_OC4M; - } -#endif + offset = STM32_GTIM_CCMR2_OFFSET; break; } #ifdef HAVE_IP_TIMERS_V2 - case 5: /* PWM Mode configuration: Channel 5 */ + case STM32_PWM_CHAN5: + case STM32_PWM_CHAN6: { - /* Reset current channel 5 mode configuration */ - - ccmr3 &= ~(ATIM_CCMR3_OC5M_MASK | ATIM_CCMR3_OC5PE); - - /* Enable CCR5 preload */ - - ocmode3 |= (chanmode << ATIM_CCMR3_OC5M_SHIFT); - - /* Enable CCR5 preload */ - - ocmode3 |= ATIM_CCMR3_OC5PE; - - /* Reset current OC bit */ - - ccmr3 &= ~(ATIM_CCMR3_OC5M); - - /* Set an additional OC5M bit */ - - if (ocmbit) - { - ocmode3 |= ATIM_CCMR3_OC5M; - } - break; - } - - case 6: /* PWM Mode configuration: Channel 6 */ - { - /* Reset current channel 6 mode configuration */ - - ccmr3 &= ~(ATIM_CCMR3_OC6M_MASK | ATIM_CCMR3_OC6PE); - - /* Enable CCR6 preload */ - - ocmode3 |= (chanmode << ATIM_CCMR3_OC6M_SHIFT); - - /* Enable CCR6 preload */ - - ocmode3 |= ATIM_CCMR3_OC6PE; - - /* Reset current OC bit */ - - ccmr3 &= ~(ATIM_CCMR3_OC6M); - - /* Set an additional OC6M bit */ - - if (ocmbit) - { - ocmode3 |= ATIM_CCMR3_OC6M; - } + offset = STM32_ATIM_CCMR3_OFFSET; break; } #endif @@ -2828,22 +2685,104 @@ static int pwm_mode_configure(FAR struct stm32_pwmtimer_s *priv, } } + /* Get current registers */ + + ccmr = pwm_getreg(priv, offset); + + /* PWM mode configuration. + * NOTE: The CCMRx registers are identical if the channels are outputs. + */ + + switch (channel) + { + /* Configure channel 1/3/5 */ + + case STM32_PWM_CHAN1: + case STM32_PWM_CHAN3: +#ifdef HAVE_IP_TIMERS_V2 + case STM32_PWM_CHAN5: +#endif + { + /* Reset current channel 1/3/5 mode configuration */ + + ccmr &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | + ATIM_CCMR1_OC1PE); + + /* Configure CC1/3/5 as output */ + + ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT); + + /* Configure Compare 1/3/5 mode */ + + ocmode |= (chanmode << ATIM_CCMR1_OC1M_SHIFT); + + /* Enable CCR1/3/5 preload */ + + ocmode |= ATIM_CCMR1_OC1PE; + +#ifdef HAVE_IP_TIMERS_V2 + /* Reset current OC bit */ + + ccmr &= ~(ATIM_CCMR1_OC1M); + + /* Set an additional OC1/3/5M bit */ + + if (ocmbit) + { + ocmode |= ATIM_CCMR1_OC1M; + } +#endif + break; + } + + /* Configure channel 2/4/6 */ + + case STM32_PWM_CHAN2: + case STM32_PWM_CHAN4: +#ifdef HAVE_IP_TIMERS_V2 + case STM32_PWM_CHAN6: +#endif + { + /* Reset current channel 2/4/6 mode configuration */ + + ccmr &= ~(ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | + ATIM_CCMR1_OC2PE); + + /* Configure CC2/4/6 as output */ + + ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT); + + /* Configure Compare 2/4/6 mode */ + + ocmode |= (chanmode << ATIM_CCMR1_OC2M_SHIFT); + + /* Enable CCR2/4/6 preload */ + + ocmode |= ATIM_CCMR1_OC2PE; + +#ifdef HAVE_IP_TIMERS_V2 + /* Reset current OC bit */ + + ccmr &= ~(ATIM_CCMR1_OC2M); + + /* Set an additioneal OC2/4/6M bit */ + + if (ocmbit) + { + ocmode |= ATIM_CCMR1_OC2M; + } +#endif + break; + } + } + /* Set the selected output compare mode */ - ccmr1 |= ocmode1; - ccmr2 |= ocmode2; + ccmr |= ocmode; /* Write CCMRx registers */ - pwm_putreg(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - pwm_putreg(priv, STM32_GTIM_CCMR2_OFFSET, ccmr2); -#ifdef HAVE_IP_TIMERS_V2 - if (priv->timtype == TIMTYPE_ADVANCED) - { - ccmr3 |= ocmode3; - pwm_putreg(priv, STM32_ATIM_CCMR3_OFFSET, ccmr3); - } -#endif + pwm_putreg(priv, offset, ccmr); errout: return ret; @@ -2985,19 +2924,19 @@ static int pwm_outputs_enable(FAR struct pwm_lowerhalf_s *dev, /* Get outputs configuration */ - regval |= ((outputs & STM32_CHAN1) ? ATIM_CCER_CC1E : 0); - regval |= ((outputs & STM32_CHAN1N) ? ATIM_CCER_CC1NE : 0); - regval |= ((outputs & STM32_CHAN2) ? ATIM_CCER_CC2E : 0); - regval |= ((outputs & STM32_CHAN2N) ? ATIM_CCER_CC2NE : 0); - regval |= ((outputs & STM32_CHAN3) ? ATIM_CCER_CC3E : 0); - regval |= ((outputs & STM32_CHAN3N) ? ATIM_CCER_CC3NE : 0); - regval |= ((outputs & STM32_CHAN4) ? ATIM_CCER_CC4E : 0); + regval |= ((outputs & STM32_PWM_OUT1) ? ATIM_CCER_CC1E : 0); + regval |= ((outputs & STM32_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0); + regval |= ((outputs & STM32_PWM_OUT2) ? ATIM_CCER_CC2E : 0); + regval |= ((outputs & STM32_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0); + regval |= ((outputs & STM32_PWM_OUT3) ? ATIM_CCER_CC3E : 0); + regval |= ((outputs & STM32_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0); + regval |= ((outputs & STM32_PWM_OUT4) ? ATIM_CCER_CC4E : 0); /* NOTE: CC4N does not exist, but some docs show configuration bits for it */ #ifdef HAVE_IP_TIMERS_V2 - regval |= ((outputs & STM32_CHAN5) ? ATIM_CCER_CC5E : 0); - regval |= ((outputs & STM32_CHAN6) ? ATIM_CCER_CC6E : 0); + regval |= ((outputs & STM32_PWM_OUT5) ? ATIM_CCER_CC5E : 0); + regval |= ((outputs & STM32_PWM_OUT6) ? ATIM_CCER_CC6E : 0); #endif if (state == true) @@ -3170,7 +3109,7 @@ static uint16_t pwm_outputs_from_channels(FAR struct stm32_pwmtimer_s *priv) if (priv->channels[i].out1.in_use == 1) { - outputs |= (STM32_CHAN1 << ((channel-1)*2)); + outputs |= (STM32_PWM_OUT1 << ((channel-1)*2)); } #ifdef HAVE_PWM_COMPLEMENTARY @@ -3178,7 +3117,7 @@ static uint16_t pwm_outputs_from_channels(FAR struct stm32_pwmtimer_s *priv) if (priv->channels[i].out2.in_use == 1) { - outputs |= (STM32_CHAN1N << ((channel-1)*2)); + outputs |= (STM32_PWM_OUT1N << ((channel-1)*2)); } #endif } @@ -3352,7 +3291,7 @@ static int pwm_pulsecount_configure(FAR struct pwm_lowerhalf_s *dev) { /* Update PWM mode */ - pwm_mode_configure(priv, priv->channels[j].channel, + pwm_mode_configure(dev, priv->channels[j].channel, priv->channels[j].mode); /* PWM outputs configuration */ @@ -3597,7 +3536,7 @@ static int pwm_configure(FAR struct pwm_lowerhalf_s *dev) { /* Update PWM mode */ - ret = pwm_mode_configure(priv, priv->channels[j].channel, + ret = pwm_mode_configure(dev, priv->channels[j].channel, priv->channels[j].mode); if (ret < 0) { diff --git a/arch/arm/src/stm32/stm32_pwm.h b/arch/arm/src/stm32/stm32_pwm.h index 85b70ab51a0..c12e95f1385 100644 --- a/arch/arm/src/stm32/stm32_pwm.h +++ b/arch/arm/src/stm32/stm32_pwm.h @@ -123,11 +123,9 @@ #include #include "hardware/stm32_tim.h" -/* Configuration needed by upper-half PWM driver */ +/* PWM driver channels configuration */ -#ifdef CONFIG_PWM - -#ifdef CONFIG_PWM_MULTICHAN +#ifdef CONFIG_STM32_PWM_MULTICHAN #ifdef CONFIG_STM32_TIM1_CHANNEL1 # define PWM_TIM1_CHANNEL1 1 @@ -149,8 +147,19 @@ #else # define PWM_TIM1_CHANNEL4 0 #endif +#ifdef CONFIG_STM32_TIM1_CHANNEL5 +# define PWM_TIM1_CHANNEL5 1 +#else +# define PWM_TIM1_CHANNEL5 0 +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL6 +# define PWM_TIM1_CHANNEL6 1 +#else +# define PWM_TIM1_CHANNEL6 0 +#endif #define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \ - PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4) + PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \ + PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6) #ifdef CONFIG_STM32_TIM2_CHANNEL1 # define PWM_TIM2_CHANNEL1 1 @@ -264,8 +273,19 @@ #else # define PWM_TIM8_CHANNEL4 0 #endif +#ifdef CONFIG_STM32_TIM8_CHANNEL5 +# define PWM_TIM8_CHANNEL5 1 +#else +# define PWM_TIM8_CHANNEL5 0 +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL6 +# define PWM_TIM8_CHANNEL6 1 +#else +# define PWM_TIM8_CHANNEL6 0 +#endif #define PWM_TIM8_NCHANNELS (PWM_TIM8_CHANNEL1 + PWM_TIM8_CHANNEL2 + \ - PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4) + PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \ + PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6) #ifdef CONFIG_STM32_TIM9_CHANNEL1 # define PWM_TIM9_CHANNEL1 1 @@ -603,9 +623,7 @@ # define PWM_TIM17_NCHANNELS 1 #endif -#endif /* CONFIG_PWM_MULTICHAN */ - -#endif /* CONFIG_PWM */ +#endif /* CONFIG_STM32_PWM_MULTICHAN */ #ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT @@ -876,6 +894,8 @@ /* Low-level ops helpers ************************************************************/ +#ifdef CONFIG_STM32_PWM_LL_OPS + /* NOTE: low-level ops accept pwm_lowerhalf_s as first argument, but llops access * can be found in stm32_pwm_dev_s */ @@ -886,6 +906,8 @@ (dev)->ops->shutdown((FAR struct pwm_lowerhalf_s *)dev) #define PWM_CCR_UPDATE(dev, index, ccr) \ (dev)->llops->ccr_update((FAR struct pwm_lowerhalf_s *)dev, index, ccr) +#define PWM_MODE_UPDATE(dev, index, mode) \ + (dev)->llops->mode_update((FAR struct pwm_lowerhalf_s *)dev, index, mode) #define PWM_CCR_GET(dev, index) \ (dev)->llops->ccr_get((FAR struct pwm_lowerhalf_s *)dev, index) #define PWM_ARR_UPDATE(dev, arr) \ @@ -913,6 +935,8 @@ #define PWM_DT_UPDATE(dev, dt) \ (dev)->llops->dt_update((FAR struct pwm_lowerhalf_s *)dev, dt) +#endif + /************************************************************************************ * Public Types ************************************************************************************/ @@ -946,37 +970,57 @@ enum stm32_pwm_idle_e /* PWM channel mode */ -enum stm32_chan_mode_e +enum stm32_pwm_chanmode_e { - STM32_CHANMODE_PWM1 = 0, - STM32_CHANMODE_PWM2 = 1, + STM32_CHANMODE_FRZN = 0, /* CCRx matches has no effects on outputs */ + STM32_CHANMODE_CHACT = 1, /* OCxREF active on match */ + STM32_CHANMODE_CHINACT = 2, /* OCxREF inactive on match */ + STM32_CHANMODE_OCREFTOG = 3, /* OCxREF toggles when TIMy_CNT=TIMyCCRx */ + STM32_CHANMODE_OCREFLO = 4, /* OCxREF is forced low */ + STM32_CHANMODE_OCREFHI = 5, /* OCxREF is forced high */ + STM32_CHANMODE_PWM1 = 6, /* PWM mode 1 */ + STM32_CHANMODE_PWM2 = 7, /* PWM mode 2 */ #ifdef HAVE_IP_TIMERS_V2 - STM32_CHANMODE_COMBINED1 = 2, - STM32_CHANMODE_COMBINED2 = 3, - STM32_CHANMODE_ASYMMETRIC1 = 4, - STM32_CHANMODE_ASYMMETRIC2 = 5 + STM32_CHANMODE_COMBINED1 = 8, /* Combined PWM mode 1 */ + STM32_CHANMODE_COMBINED2 = 9, /* Combined PWM mode 2 */ + STM32_CHANMODE_ASYMMETRIC1 = 10, /* Asymmetric PWM mode 1 */ + STM32_CHANMODE_ASYMMETRIC2 = 11, /* Asymmetric PWM mode 2 */ #endif }; -/* Timer channel */ +/* PWM timer channel */ -enum stm32_chan_e +enum stm32_pwm_chan_e { - STM32_CHAN1 = (1 << 0), - STM32_CHAN1N = (1 << 1), - STM32_CHAN2 = (1 << 2), - STM32_CHAN2N = (1 << 3), - STM32_CHAN3 = (1 << 4), - STM32_CHAN3N = (1 << 5), - STM32_CHAN4 = (1 << 6), - /* No complementary output for CH4 */ + STM32_PWM_CHAN1 = 1, + STM32_PWM_CHAN2 = 2, + STM32_PWM_CHAN3 = 3, + STM32_PWM_CHAN4 = 4, +#ifdef HAVE_IP_TIMERS_V2 + STM32_PWM_CHAN5 = 5, + STM32_PWM_CHAN6 = 6, +#endif +}; + +/* PWM timer channel output */ + +enum stm32_pwm_output_e +{ + STM32_PWM_OUT1 = (1 << 0), + STM32_PWM_OUT1N = (1 << 1), + STM32_PWM_OUT2 = (1 << 2), + STM32_PWM_OUT2N = (1 << 3), + STM32_PWM_OUT3 = (1 << 4), + STM32_PWM_OUT3N = (1 << 5), + STM32_PWM_OUT4 = (1 << 6), + /* 1 << 7 reserved - no complementary output for CH4 */ #ifdef HAVE_IP_TIMERS_V2 /* Only available inside micro */ - STM32_CHAN5 = (1 << 7), - /* 1<<8 reserved */ - STM32_CHAN6 = (1 << 9), - /* 1<<10 reserved */ + STM32_PWM_OUT5 = (1 << 8), + /* 1 << 9 reserved - no complementary output for CH5 */ + STM32_PWM_OUT6 = (1 << 10), + /* 1 << 11 reserved - no complementary output for CH6 */ #endif }; @@ -1010,6 +1054,10 @@ struct stm32_pwm_ops_s int (*ccr_update)(FAR struct pwm_lowerhalf_s *dev, uint8_t index, uint32_t ccr); + /* Update PWM mode */ + + int (*mode_update)(FAR struct pwm_lowerhalf_s *dev, uint8_t index, uint32_t mode); + /* Get CCR register */ uint32_t (*ccr_get)(FAR struct pwm_lowerhalf_s *dev, uint8_t index); diff --git a/configs/nucleo-f302r8/src/stm32_highpri.c b/configs/nucleo-f302r8/src/stm32_highpri.c index 93fe9c859d8..8ea02f9a957 100644 --- a/configs/nucleo-f302r8/src/stm32_highpri.c +++ b/configs/nucleo-f302r8/src/stm32_highpri.c @@ -405,9 +405,9 @@ int highpri_main(int argc, char *argv[]) PWM_CCR_UPDATE(pwm1, 1, 0x0f00); - /* Enable TIM1 CHAN1 */ + /* Enable TIM1 OUT1 */ - PWM_OUTPUTS_ENABLE(pwm1, STM32_CHAN1, true); + PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true); #else # error T1CC1 only supported for now #endif diff --git a/configs/nucleo-f334r8/include/board.h b/configs/nucleo-f334r8/include/board.h index 227d6e93136..99c7def0bbb 100644 --- a/configs/nucleo-f334r8/include/board.h +++ b/configs/nucleo-f334r8/include/board.h @@ -284,8 +284,6 @@ /* TIM1 PWM configuration ***************************************************/ -# define PWM_TIM1_NCHANNELS 4 - # define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_1 /* TIM1 CH1 - PA8 */ # define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_3 /* TIM1 CH1N - PA7 */ /* TIM1 CH2 - PA9 */ diff --git a/configs/nucleo-f334r8/src/stm32_highpri.c b/configs/nucleo-f334r8/src/stm32_highpri.c index c3c041b0cf6..b1af05426e4 100644 --- a/configs/nucleo-f334r8/src/stm32_highpri.c +++ b/configs/nucleo-f334r8/src/stm32_highpri.c @@ -441,9 +441,9 @@ int highpri_main(int argc, char *argv[]) PWM_CCR_UPDATE(pwm1, 1, 0x0f00); - /* Enable TIM1 CHAN1 */ + /* Enable TIM1 OUT1 */ - PWM_OUTPUTS_ENABLE(pwm1, STM32_CHAN1, true); + PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true); #else # error T1CC1 only supported for now #endif diff --git a/configs/stm32f429i-disco/src/stm32_highpri.c b/configs/stm32f429i-disco/src/stm32_highpri.c index 434a643e0c7..30fe72c3147 100644 --- a/configs/stm32f429i-disco/src/stm32_highpri.c +++ b/configs/stm32f429i-disco/src/stm32_highpri.c @@ -389,9 +389,9 @@ int highpri_main(int argc, char *argv[]) PWM_CCR_UPDATE(pwm1, 1, 0x0f00); - /* Enable TIM1 CHAN1 */ + /* Enable TIM1 OUT1 */ - PWM_OUTPUTS_ENABLE(pwm1, STM32_CHAN1, true); + PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true); #else # error T1CC1 only supported for now #endif