configs/misoc: Add a sample directory containing generated sources. This is really only useful for performing test builds. You really must generate the Misoc architecture for a real-life build.

2026-09-23 16:22:23 +08:00 · 2016-11-28 13:30:46 -06:00
parent f9a7898bd4
commit f3e6264654
7 changed files with 800 additions and 2 deletions
@@ -66,7 +66,16 @@ Buildroot Toolchain
 configs/misoc/include/generated
 ===============================

-  In order to build this configuration, you must provide this directory.
-  It contains the generated Misoc files.  The base configurtion will NOT
+  In order to build this configuration, you must provide the
+  configs/misoc/include/generated directory.  It contains the generated
+  Misoc files and may be a symbolic link.  The base configurtion will NOT
  build without this directory!

+  There is a sample generated directory at configs/misoc/include/generated-sample.
+  If you want to do a test build without generating the architecture, then
+  you can simply link this sample directory like:
+
+    $ ln -s configs/misoc/include/generated-sample configs/misoc/include/generated
+
+  That should permit a test build.
+
@@ -0,0 +1,16 @@
+#ifndef __GENERATED_MEM_H
+#define __GENERATED_MEM_H
+
+#define ROM_BASE 0x00000000
+#define ROM_SIZE 0x00008000
+
+#define SRAM_BASE 0x10000000
+#define SRAM_SIZE 0x00008000
+
+#define MAIN_RAM_BASE 0x40000000
+#define MAIN_RAM_SIZE 0x10000000
+
+#define ETHMAC_BASE 0xb0000000
+#define ETHMAC_SIZE 0x00002000
+
+#endif
@@ -0,0 +1 @@
+OUTPUT_FORMAT("elf32-lm32")
@@ -0,0 +1,6 @@
+MEMORY {
+	rom : ORIGIN = 0x00000000, LENGTH = 0x00008000
+	sram : ORIGIN = 0x10000000, LENGTH = 0x00008000
+	main_ram : ORIGIN = 0x40000000, LENGTH = 0x10000000
+	ethmac : ORIGIN = 0xb0000000, LENGTH = 0x00002000
+}
@@ -0,0 +1,102 @@
+#ifndef __GENERATED_SDRAM_PHY_H
+#define __GENERATED_SDRAM_PHY_H
+#include <hw/common.h>
+#include <generated/csr.h>
+#include <hw/flags.h>
+
+#define DFII_NPHASES 4
+
+static void cdelay(int i);
+
+static void command_p0(int cmd)
+{
+    sdram_dfii_pi0_command_write(cmd);
+    sdram_dfii_pi0_command_issue_write(1);
+}
+static void command_p1(int cmd)
+{
+    sdram_dfii_pi1_command_write(cmd);
+    sdram_dfii_pi1_command_issue_write(1);
+}
+static void command_p2(int cmd)
+{
+    sdram_dfii_pi2_command_write(cmd);
+    sdram_dfii_pi2_command_issue_write(1);
+}
+static void command_p3(int cmd)
+{
+    sdram_dfii_pi3_command_write(cmd);
+    sdram_dfii_pi3_command_issue_write(1);
+}
+
+
+#define sdram_dfii_pird_address_write(X) sdram_dfii_pi0_address_write(X)
+#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi2_address_write(X)
+
+#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi0_baddress_write(X)
+#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi2_baddress_write(X)
+
+#define command_prd(X) command_p0(X)
+#define command_pwr(X) command_p2(X)
+
+#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
+
+const unsigned int sdram_dfii_pix_wrdata_addr[4] = {
+    CSR_SDRAM_DFII_PI0_WRDATA_ADDR,
+	CSR_SDRAM_DFII_PI1_WRDATA_ADDR,
+	CSR_SDRAM_DFII_PI2_WRDATA_ADDR,
+	CSR_SDRAM_DFII_PI3_WRDATA_ADDR
+};
+
+const unsigned int sdram_dfii_pix_rddata_addr[4] = {
+    CSR_SDRAM_DFII_PI0_RDDATA_ADDR,
+	CSR_SDRAM_DFII_PI1_RDDATA_ADDR,
+	CSR_SDRAM_DFII_PI2_RDDATA_ADDR,
+	CSR_SDRAM_DFII_PI3_RDDATA_ADDR
+};
+
+#define DDR3_MR1 6
+
+static void init_sequence(void)
+{
+	/* Release reset */
+	sdram_dfii_pi0_address_write(0x0);
+	sdram_dfii_pi0_baddress_write(0);
+	sdram_dfii_control_write(DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
+	cdelay(50000);
+
+	/* Bring CKE high */
+	sdram_dfii_pi0_address_write(0x0);
+	sdram_dfii_pi0_baddress_write(0);
+	sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
+	cdelay(10000);
+
+	/* Load Mode Register 2 */
+	sdram_dfii_pi0_address_write(0x408);
+	sdram_dfii_pi0_baddress_write(2);
+	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
+
+	/* Load Mode Register 3 */
+	sdram_dfii_pi0_address_write(0x0);
+	sdram_dfii_pi0_baddress_write(3);
+	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
+
+	/* Load Mode Register 1 */
+	sdram_dfii_pi0_address_write(0x6);
+	sdram_dfii_pi0_baddress_write(1);
+	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
+
+	/* Load Mode Register 0, CL=7, BL=8 */
+	sdram_dfii_pi0_address_write(0x930);
+	sdram_dfii_pi0_baddress_write(0);
+	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
+	cdelay(200);
+
+	/* ZQ Calibration */
+	sdram_dfii_pi0_address_write(0x400);
+	sdram_dfii_pi0_baddress_write(0);
+	command_p0(DFII_COMMAND_WE|DFII_COMMAND_CS);
+	cdelay(200);
+
+}
+#endif
@@ -0,0 +1,11 @@
+TRIPLE=lm32-elf
+CPU=lm32
+CPUFLAGS=-mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled
+CPUENDIANNESS=big
+CLANG=0
+SOC_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc
+BUILDINC_DIRECTORY=/home/lenovo/fpga/arty-soc/build/software/include
+LIBBASE_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/libbase
+LIBCOMPILER_RT_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/libcompiler_rt
+LIBNET_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/libnet
+BIOS_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/bios