From f3e6264654c110562a981ce5294a9df062104672 Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Mon, 28 Nov 2016 13:30:46 -0600 Subject: [PATCH] configs/misoc: Add a sample directory containing generated sources. This is really only useful for performing test builds. You really must generate the Misoc architecture for a real-life build. --- configs/misoc/README.txt | 13 +- configs/misoc/include/generated-sample/csr.h | 653 ++++++++++++++++++ configs/misoc/include/generated-sample/mem.h | 16 + .../include/generated-sample/output_format.ld | 1 + .../misoc/include/generated-sample/regions.ld | 6 + .../include/generated-sample/sdram_phy.h | 102 +++ .../include/generated-sample/variables.mak | 11 + 7 files changed, 800 insertions(+), 2 deletions(-) create mode 100644 configs/misoc/include/generated-sample/csr.h create mode 100644 configs/misoc/include/generated-sample/mem.h create mode 100644 configs/misoc/include/generated-sample/output_format.ld create mode 100644 configs/misoc/include/generated-sample/regions.ld create mode 100644 configs/misoc/include/generated-sample/sdram_phy.h create mode 100644 configs/misoc/include/generated-sample/variables.mak diff --git a/configs/misoc/README.txt b/configs/misoc/README.txt index 094ec1acdb1..a241aba6b6a 100644 --- a/configs/misoc/README.txt +++ b/configs/misoc/README.txt @@ -66,7 +66,16 @@ Buildroot Toolchain configs/misoc/include/generated =============================== - In order to build this configuration, you must provide this directory. - It contains the generated Misoc files. The base configurtion will NOT + In order to build this configuration, you must provide the + configs/misoc/include/generated directory. It contains the generated + Misoc files and may be a symbolic link. The base configurtion will NOT build without this directory! + There is a sample generated directory at configs/misoc/include/generated-sample. + If you want to do a test build without generating the architecture, then + you can simply link this sample directory like: + + $ ln -s configs/misoc/include/generated-sample configs/misoc/include/generated + + That should permit a test build. + diff --git a/configs/misoc/include/generated-sample/csr.h b/configs/misoc/include/generated-sample/csr.h new file mode 100644 index 00000000000..e58b0e0bf4f --- /dev/null +++ b/configs/misoc/include/generated-sample/csr.h @@ -0,0 +1,653 @@ +#ifndef __GENERATED_CSR_H +#define __GENERATED_CSR_H +#include + +/* ddrphy */ +#define CSR_DDRPHY_BASE 0xe0008800 +#define CSR_DDRPHY_DLY_SEL_ADDR 0xe0008800 +#define CSR_DDRPHY_DLY_SEL_SIZE 1 +static inline unsigned char ddrphy_dly_sel_read(void) { + unsigned char r = MMPTR(0xe0008800); + return r; +} +static inline void ddrphy_dly_sel_write(unsigned char value) { + MMPTR(0xe0008800) = value; +} +#define CSR_DDRPHY_RDLY_DQ_RST_ADDR 0xe0008804 +#define CSR_DDRPHY_RDLY_DQ_RST_SIZE 1 +static inline unsigned char ddrphy_rdly_dq_rst_read(void) { + unsigned char r = MMPTR(0xe0008804); + return r; +} +static inline void ddrphy_rdly_dq_rst_write(unsigned char value) { + MMPTR(0xe0008804) = value; +} +#define CSR_DDRPHY_RDLY_DQ_INC_ADDR 0xe0008808 +#define CSR_DDRPHY_RDLY_DQ_INC_SIZE 1 +static inline unsigned char ddrphy_rdly_dq_inc_read(void) { + unsigned char r = MMPTR(0xe0008808); + return r; +} +static inline void ddrphy_rdly_dq_inc_write(unsigned char value) { + MMPTR(0xe0008808) = value; +} +#define CSR_DDRPHY_RDLY_DQ_BITSLIP_ADDR 0xe000880c +#define CSR_DDRPHY_RDLY_DQ_BITSLIP_SIZE 1 +static inline unsigned char ddrphy_rdly_dq_bitslip_read(void) { + unsigned char r = MMPTR(0xe000880c); + return r; +} +static inline void ddrphy_rdly_dq_bitslip_write(unsigned char value) { + MMPTR(0xe000880c) = value; +} + +/* ethmac */ +#define CSR_ETHMAC_BASE 0xe000f800 +#define CSR_ETHMAC_SRAM_WRITER_SLOT_ADDR 0xe000f800 +#define CSR_ETHMAC_SRAM_WRITER_SLOT_SIZE 1 +static inline unsigned char ethmac_sram_writer_slot_read(void) { + unsigned char r = MMPTR(0xe000f800); + return r; +} +#define CSR_ETHMAC_SRAM_WRITER_LENGTH_ADDR 0xe000f804 +#define CSR_ETHMAC_SRAM_WRITER_LENGTH_SIZE 4 +static inline unsigned int ethmac_sram_writer_length_read(void) { + unsigned int r = MMPTR(0xe000f804); + r <<= 8; + r |= MMPTR(0xe000f808); + r <<= 8; + r |= MMPTR(0xe000f80c); + r <<= 8; + r |= MMPTR(0xe000f810); + return r; +} +#define CSR_ETHMAC_SRAM_WRITER_EV_STATUS_ADDR 0xe000f814 +#define CSR_ETHMAC_SRAM_WRITER_EV_STATUS_SIZE 1 +static inline unsigned char ethmac_sram_writer_ev_status_read(void) { + unsigned char r = MMPTR(0xe000f814); + return r; +} +static inline void ethmac_sram_writer_ev_status_write(unsigned char value) { + MMPTR(0xe000f814) = value; +} +#define CSR_ETHMAC_SRAM_WRITER_EV_PENDING_ADDR 0xe000f818 +#define CSR_ETHMAC_SRAM_WRITER_EV_PENDING_SIZE 1 +static inline unsigned char ethmac_sram_writer_ev_pending_read(void) { + unsigned char r = MMPTR(0xe000f818); + return r; +} +static inline void ethmac_sram_writer_ev_pending_write(unsigned char value) { + MMPTR(0xe000f818) = value; +} +#define CSR_ETHMAC_SRAM_WRITER_EV_ENABLE_ADDR 0xe000f81c +#define CSR_ETHMAC_SRAM_WRITER_EV_ENABLE_SIZE 1 +static inline unsigned char ethmac_sram_writer_ev_enable_read(void) { + unsigned char r = MMPTR(0xe000f81c); + return r; +} +static inline void ethmac_sram_writer_ev_enable_write(unsigned char value) { + MMPTR(0xe000f81c) = value; +} +#define CSR_ETHMAC_SRAM_READER_START_ADDR 0xe000f820 +#define CSR_ETHMAC_SRAM_READER_START_SIZE 1 +static inline unsigned char ethmac_sram_reader_start_read(void) { + unsigned char r = MMPTR(0xe000f820); + return r; +} +static inline void ethmac_sram_reader_start_write(unsigned char value) { + MMPTR(0xe000f820) = value; +} +#define CSR_ETHMAC_SRAM_READER_READY_ADDR 0xe000f824 +#define CSR_ETHMAC_SRAM_READER_READY_SIZE 1 +static inline unsigned char ethmac_sram_reader_ready_read(void) { + unsigned char r = MMPTR(0xe000f824); + return r; +} +#define CSR_ETHMAC_SRAM_READER_SLOT_ADDR 0xe000f828 +#define CSR_ETHMAC_SRAM_READER_SLOT_SIZE 1 +static inline unsigned char ethmac_sram_reader_slot_read(void) { + unsigned char r = MMPTR(0xe000f828); + return r; +} +static inline void ethmac_sram_reader_slot_write(unsigned char value) { + MMPTR(0xe000f828) = value; +} +#define CSR_ETHMAC_SRAM_READER_LENGTH_ADDR 0xe000f82c +#define CSR_ETHMAC_SRAM_READER_LENGTH_SIZE 2 +static inline unsigned short int ethmac_sram_reader_length_read(void) { + unsigned short int r = MMPTR(0xe000f82c); + r <<= 8; + r |= MMPTR(0xe000f830); + return r; +} +static inline void ethmac_sram_reader_length_write(unsigned short int value) { + MMPTR(0xe000f82c) = value >> 8; + MMPTR(0xe000f830) = value; +} +#define CSR_ETHMAC_SRAM_READER_EV_STATUS_ADDR 0xe000f834 +#define CSR_ETHMAC_SRAM_READER_EV_STATUS_SIZE 1 +static inline unsigned char ethmac_sram_reader_ev_status_read(void) { + unsigned char r = MMPTR(0xe000f834); + return r; +} +static inline void ethmac_sram_reader_ev_status_write(unsigned char value) { + MMPTR(0xe000f834) = value; +} +#define CSR_ETHMAC_SRAM_READER_EV_PENDING_ADDR 0xe000f838 +#define CSR_ETHMAC_SRAM_READER_EV_PENDING_SIZE 1 +static inline unsigned char ethmac_sram_reader_ev_pending_read(void) { + unsigned char r = MMPTR(0xe000f838); + return r; +} +static inline void ethmac_sram_reader_ev_pending_write(unsigned char value) { + MMPTR(0xe000f838) = value; +} +#define CSR_ETHMAC_SRAM_READER_EV_ENABLE_ADDR 0xe000f83c +#define CSR_ETHMAC_SRAM_READER_EV_ENABLE_SIZE 1 +static inline unsigned char ethmac_sram_reader_ev_enable_read(void) { + unsigned char r = MMPTR(0xe000f83c); + return r; +} +static inline void ethmac_sram_reader_ev_enable_write(unsigned char value) { + MMPTR(0xe000f83c) = value; +} +#define CSR_ETHMAC_PREAMBLE_CRC_ADDR 0xe000f840 +#define CSR_ETHMAC_PREAMBLE_CRC_SIZE 1 +static inline unsigned char ethmac_preamble_crc_read(void) { + unsigned char r = MMPTR(0xe000f840); + return r; +} + +/* ethphy */ +#define CSR_ETHPHY_BASE 0xe000f000 +#define CSR_ETHPHY_CRG_RESET_ADDR 0xe000f000 +#define CSR_ETHPHY_CRG_RESET_SIZE 1 +static inline unsigned char ethphy_crg_reset_read(void) { + unsigned char r = MMPTR(0xe000f000); + return r; +} +static inline void ethphy_crg_reset_write(unsigned char value) { + MMPTR(0xe000f000) = value; +} +#define CSR_ETHPHY_MDIO_W_ADDR 0xe000f004 +#define CSR_ETHPHY_MDIO_W_SIZE 1 +static inline unsigned char ethphy_mdio_w_read(void) { + unsigned char r = MMPTR(0xe000f004); + return r; +} +static inline void ethphy_mdio_w_write(unsigned char value) { + MMPTR(0xe000f004) = value; +} +#define CSR_ETHPHY_MDIO_R_ADDR 0xe000f008 +#define CSR_ETHPHY_MDIO_R_SIZE 1 +static inline unsigned char ethphy_mdio_r_read(void) { + unsigned char r = MMPTR(0xe000f008); + return r; +} + +/* sdram */ +#define CSR_SDRAM_BASE 0xe0004000 +#define CSR_SDRAM_DFII_CONTROL_ADDR 0xe0004000 +#define CSR_SDRAM_DFII_CONTROL_SIZE 1 +static inline unsigned char sdram_dfii_control_read(void) { + unsigned char r = MMPTR(0xe0004000); + return r; +} +static inline void sdram_dfii_control_write(unsigned char value) { + MMPTR(0xe0004000) = value; +} +#define CSR_SDRAM_DFII_PI0_COMMAND_ADDR 0xe0004004 +#define CSR_SDRAM_DFII_PI0_COMMAND_SIZE 1 +static inline unsigned char sdram_dfii_pi0_command_read(void) { + unsigned char r = MMPTR(0xe0004004); + return r; +} +static inline void sdram_dfii_pi0_command_write(unsigned char value) { + MMPTR(0xe0004004) = value; +} +#define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_ADDR 0xe0004008 +#define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_SIZE 1 +static inline unsigned char sdram_dfii_pi0_command_issue_read(void) { + unsigned char r = MMPTR(0xe0004008); + return r; +} +static inline void sdram_dfii_pi0_command_issue_write(unsigned char value) { + MMPTR(0xe0004008) = value; +} +#define CSR_SDRAM_DFII_PI0_ADDRESS_ADDR 0xe000400c +#define CSR_SDRAM_DFII_PI0_ADDRESS_SIZE 2 +static inline unsigned short int sdram_dfii_pi0_address_read(void) { + unsigned short int r = MMPTR(0xe000400c); + r <<= 8; + r |= MMPTR(0xe0004010); + return r; +} +static inline void sdram_dfii_pi0_address_write(unsigned short int value) { + MMPTR(0xe000400c) = value >> 8; + MMPTR(0xe0004010) = value; +} +#define CSR_SDRAM_DFII_PI0_BADDRESS_ADDR 0xe0004014 +#define CSR_SDRAM_DFII_PI0_BADDRESS_SIZE 1 +static inline unsigned char sdram_dfii_pi0_baddress_read(void) { + unsigned char r = MMPTR(0xe0004014); + return r; +} +static inline void sdram_dfii_pi0_baddress_write(unsigned char value) { + MMPTR(0xe0004014) = value; +} +#define CSR_SDRAM_DFII_PI0_WRDATA_ADDR 0xe0004018 +#define CSR_SDRAM_DFII_PI0_WRDATA_SIZE 4 +static inline unsigned int sdram_dfii_pi0_wrdata_read(void) { + unsigned int r = MMPTR(0xe0004018); + r <<= 8; + r |= MMPTR(0xe000401c); + r <<= 8; + r |= MMPTR(0xe0004020); + r <<= 8; + r |= MMPTR(0xe0004024); + return r; +} +static inline void sdram_dfii_pi0_wrdata_write(unsigned int value) { + MMPTR(0xe0004018) = value >> 24; + MMPTR(0xe000401c) = value >> 16; + MMPTR(0xe0004020) = value >> 8; + MMPTR(0xe0004024) = value; +} +#define CSR_SDRAM_DFII_PI0_RDDATA_ADDR 0xe0004028 +#define CSR_SDRAM_DFII_PI0_RDDATA_SIZE 4 +static inline unsigned int sdram_dfii_pi0_rddata_read(void) { + unsigned int r = MMPTR(0xe0004028); + r <<= 8; + r |= MMPTR(0xe000402c); + r <<= 8; + r |= MMPTR(0xe0004030); + r <<= 8; + r |= MMPTR(0xe0004034); + return r; +} +#define CSR_SDRAM_DFII_PI1_COMMAND_ADDR 0xe0004038 +#define CSR_SDRAM_DFII_PI1_COMMAND_SIZE 1 +static inline unsigned char sdram_dfii_pi1_command_read(void) { + unsigned char r = MMPTR(0xe0004038); + return r; +} +static inline void sdram_dfii_pi1_command_write(unsigned char value) { + MMPTR(0xe0004038) = value; +} +#define CSR_SDRAM_DFII_PI1_COMMAND_ISSUE_ADDR 0xe000403c +#define CSR_SDRAM_DFII_PI1_COMMAND_ISSUE_SIZE 1 +static inline unsigned char sdram_dfii_pi1_command_issue_read(void) { + unsigned char r = MMPTR(0xe000403c); + return r; +} +static inline void sdram_dfii_pi1_command_issue_write(unsigned char value) { + MMPTR(0xe000403c) = value; +} +#define CSR_SDRAM_DFII_PI1_ADDRESS_ADDR 0xe0004040 +#define CSR_SDRAM_DFII_PI1_ADDRESS_SIZE 2 +static inline unsigned short int sdram_dfii_pi1_address_read(void) { + unsigned short int r = MMPTR(0xe0004040); + r <<= 8; + r |= MMPTR(0xe0004044); + return r; +} +static inline void sdram_dfii_pi1_address_write(unsigned short int value) { + MMPTR(0xe0004040) = value >> 8; + MMPTR(0xe0004044) = value; +} +#define CSR_SDRAM_DFII_PI1_BADDRESS_ADDR 0xe0004048 +#define CSR_SDRAM_DFII_PI1_BADDRESS_SIZE 1 +static inline unsigned char sdram_dfii_pi1_baddress_read(void) { + unsigned char r = MMPTR(0xe0004048); + return r; +} +static inline void sdram_dfii_pi1_baddress_write(unsigned char value) { + MMPTR(0xe0004048) = value; +} +#define CSR_SDRAM_DFII_PI1_WRDATA_ADDR 0xe000404c +#define CSR_SDRAM_DFII_PI1_WRDATA_SIZE 4 +static inline unsigned int sdram_dfii_pi1_wrdata_read(void) { + unsigned int r = MMPTR(0xe000404c); + r <<= 8; + r |= MMPTR(0xe0004050); + r <<= 8; + r |= MMPTR(0xe0004054); + r <<= 8; + r |= MMPTR(0xe0004058); + return r; +} +static inline void sdram_dfii_pi1_wrdata_write(unsigned int value) { + MMPTR(0xe000404c) = value >> 24; + MMPTR(0xe0004050) = value >> 16; + MMPTR(0xe0004054) = value >> 8; + MMPTR(0xe0004058) = value; +} +#define CSR_SDRAM_DFII_PI1_RDDATA_ADDR 0xe000405c +#define CSR_SDRAM_DFII_PI1_RDDATA_SIZE 4 +static inline unsigned int sdram_dfii_pi1_rddata_read(void) { + unsigned int r = MMPTR(0xe000405c); + r <<= 8; + r |= MMPTR(0xe0004060); + r <<= 8; + r |= MMPTR(0xe0004064); + r <<= 8; + r |= MMPTR(0xe0004068); + return r; +} +#define CSR_SDRAM_DFII_PI2_COMMAND_ADDR 0xe000406c +#define CSR_SDRAM_DFII_PI2_COMMAND_SIZE 1 +static inline unsigned char sdram_dfii_pi2_command_read(void) { + unsigned char r = MMPTR(0xe000406c); + return r; +} +static inline void sdram_dfii_pi2_command_write(unsigned char value) { + MMPTR(0xe000406c) = value; +} +#define CSR_SDRAM_DFII_PI2_COMMAND_ISSUE_ADDR 0xe0004070 +#define CSR_SDRAM_DFII_PI2_COMMAND_ISSUE_SIZE 1 +static inline unsigned char sdram_dfii_pi2_command_issue_read(void) { + unsigned char r = MMPTR(0xe0004070); + return r; +} +static inline void sdram_dfii_pi2_command_issue_write(unsigned char value) { + MMPTR(0xe0004070) = value; +} +#define CSR_SDRAM_DFII_PI2_ADDRESS_ADDR 0xe0004074 +#define CSR_SDRAM_DFII_PI2_ADDRESS_SIZE 2 +static inline unsigned short int sdram_dfii_pi2_address_read(void) { + unsigned short int r = MMPTR(0xe0004074); + r <<= 8; + r |= MMPTR(0xe0004078); + return r; +} +static inline void sdram_dfii_pi2_address_write(unsigned short int value) { + MMPTR(0xe0004074) = value >> 8; + MMPTR(0xe0004078) = value; +} +#define CSR_SDRAM_DFII_PI2_BADDRESS_ADDR 0xe000407c +#define CSR_SDRAM_DFII_PI2_BADDRESS_SIZE 1 +static inline unsigned char sdram_dfii_pi2_baddress_read(void) { + unsigned char r = MMPTR(0xe000407c); + return r; +} +static inline void sdram_dfii_pi2_baddress_write(unsigned char value) { + MMPTR(0xe000407c) = value; +} +#define CSR_SDRAM_DFII_PI2_WRDATA_ADDR 0xe0004080 +#define CSR_SDRAM_DFII_PI2_WRDATA_SIZE 4 +static inline unsigned int sdram_dfii_pi2_wrdata_read(void) { + unsigned int r = MMPTR(0xe0004080); + r <<= 8; + r |= MMPTR(0xe0004084); + r <<= 8; + r |= MMPTR(0xe0004088); + r <<= 8; + r |= MMPTR(0xe000408c); + return r; +} +static inline void sdram_dfii_pi2_wrdata_write(unsigned int value) { + MMPTR(0xe0004080) = value >> 24; + MMPTR(0xe0004084) = value >> 16; + MMPTR(0xe0004088) = value >> 8; + MMPTR(0xe000408c) = value; +} +#define CSR_SDRAM_DFII_PI2_RDDATA_ADDR 0xe0004090 +#define CSR_SDRAM_DFII_PI2_RDDATA_SIZE 4 +static inline unsigned int sdram_dfii_pi2_rddata_read(void) { + unsigned int r = MMPTR(0xe0004090); + r <<= 8; + r |= MMPTR(0xe0004094); + r <<= 8; + r |= MMPTR(0xe0004098); + r <<= 8; + r |= MMPTR(0xe000409c); + return r; +} +#define CSR_SDRAM_DFII_PI3_COMMAND_ADDR 0xe00040a0 +#define CSR_SDRAM_DFII_PI3_COMMAND_SIZE 1 +static inline unsigned char sdram_dfii_pi3_command_read(void) { + unsigned char r = MMPTR(0xe00040a0); + return r; +} +static inline void sdram_dfii_pi3_command_write(unsigned char value) { + MMPTR(0xe00040a0) = value; +} +#define CSR_SDRAM_DFII_PI3_COMMAND_ISSUE_ADDR 0xe00040a4 +#define CSR_SDRAM_DFII_PI3_COMMAND_ISSUE_SIZE 1 +static inline unsigned char sdram_dfii_pi3_command_issue_read(void) { + unsigned char r = MMPTR(0xe00040a4); + return r; +} +static inline void sdram_dfii_pi3_command_issue_write(unsigned char value) { + MMPTR(0xe00040a4) = value; +} +#define CSR_SDRAM_DFII_PI3_ADDRESS_ADDR 0xe00040a8 +#define CSR_SDRAM_DFII_PI3_ADDRESS_SIZE 2 +static inline unsigned short int sdram_dfii_pi3_address_read(void) { + unsigned short int r = MMPTR(0xe00040a8); + r <<= 8; + r |= MMPTR(0xe00040ac); + return r; +} +static inline void sdram_dfii_pi3_address_write(unsigned short int value) { + MMPTR(0xe00040a8) = value >> 8; + MMPTR(0xe00040ac) = value; +} +#define CSR_SDRAM_DFII_PI3_BADDRESS_ADDR 0xe00040b0 +#define CSR_SDRAM_DFII_PI3_BADDRESS_SIZE 1 +static inline unsigned char sdram_dfii_pi3_baddress_read(void) { + unsigned char r = MMPTR(0xe00040b0); + return r; +} +static inline void sdram_dfii_pi3_baddress_write(unsigned char value) { + MMPTR(0xe00040b0) = value; +} +#define CSR_SDRAM_DFII_PI3_WRDATA_ADDR 0xe00040b4 +#define CSR_SDRAM_DFII_PI3_WRDATA_SIZE 4 +static inline unsigned int sdram_dfii_pi3_wrdata_read(void) { + unsigned int r = MMPTR(0xe00040b4); + r <<= 8; + r |= MMPTR(0xe00040b8); + r <<= 8; + r |= MMPTR(0xe00040bc); + r <<= 8; + r |= MMPTR(0xe00040c0); + return r; +} +static inline void sdram_dfii_pi3_wrdata_write(unsigned int value) { + MMPTR(0xe00040b4) = value >> 24; + MMPTR(0xe00040b8) = value >> 16; + MMPTR(0xe00040bc) = value >> 8; + MMPTR(0xe00040c0) = value; +} +#define CSR_SDRAM_DFII_PI3_RDDATA_ADDR 0xe00040c4 +#define CSR_SDRAM_DFII_PI3_RDDATA_SIZE 4 +static inline unsigned int sdram_dfii_pi3_rddata_read(void) { + unsigned int r = MMPTR(0xe00040c4); + r <<= 8; + r |= MMPTR(0xe00040c8); + r <<= 8; + r |= MMPTR(0xe00040cc); + r <<= 8; + r |= MMPTR(0xe00040d0); + return r; +} + +/* timer0 */ +#define CSR_TIMER0_BASE 0xe0002000 +#define CSR_TIMER0_LOAD_ADDR 0xe0002000 +#define CSR_TIMER0_LOAD_SIZE 4 +static inline unsigned int timer0_load_read(void) { + unsigned int r = MMPTR(0xe0002000); + r <<= 8; + r |= MMPTR(0xe0002004); + r <<= 8; + r |= MMPTR(0xe0002008); + r <<= 8; + r |= MMPTR(0xe000200c); + return r; +} +static inline void timer0_load_write(unsigned int value) { + MMPTR(0xe0002000) = value >> 24; + MMPTR(0xe0002004) = value >> 16; + MMPTR(0xe0002008) = value >> 8; + MMPTR(0xe000200c) = value; +} +#define CSR_TIMER0_RELOAD_ADDR 0xe0002010 +#define CSR_TIMER0_RELOAD_SIZE 4 +static inline unsigned int timer0_reload_read(void) { + unsigned int r = MMPTR(0xe0002010); + r <<= 8; + r |= MMPTR(0xe0002014); + r <<= 8; + r |= MMPTR(0xe0002018); + r <<= 8; + r |= MMPTR(0xe000201c); + return r; +} +static inline void timer0_reload_write(unsigned int value) { + MMPTR(0xe0002010) = value >> 24; + MMPTR(0xe0002014) = value >> 16; + MMPTR(0xe0002018) = value >> 8; + MMPTR(0xe000201c) = value; +} +#define CSR_TIMER0_EN_ADDR 0xe0002020 +#define CSR_TIMER0_EN_SIZE 1 +static inline unsigned char timer0_en_read(void) { + unsigned char r = MMPTR(0xe0002020); + return r; +} +static inline void timer0_en_write(unsigned char value) { + MMPTR(0xe0002020) = value; +} +#define CSR_TIMER0_UPDATE_VALUE_ADDR 0xe0002024 +#define CSR_TIMER0_UPDATE_VALUE_SIZE 1 +static inline unsigned char timer0_update_value_read(void) { + unsigned char r = MMPTR(0xe0002024); + return r; +} +static inline void timer0_update_value_write(unsigned char value) { + MMPTR(0xe0002024) = value; +} +#define CSR_TIMER0_VALUE_ADDR 0xe0002028 +#define CSR_TIMER0_VALUE_SIZE 4 +static inline unsigned int timer0_value_read(void) { + unsigned int r = MMPTR(0xe0002028); + r <<= 8; + r |= MMPTR(0xe000202c); + r <<= 8; + r |= MMPTR(0xe0002030); + r <<= 8; + r |= MMPTR(0xe0002034); + return r; +} +#define CSR_TIMER0_EV_STATUS_ADDR 0xe0002038 +#define CSR_TIMER0_EV_STATUS_SIZE 1 +static inline unsigned char timer0_ev_status_read(void) { + unsigned char r = MMPTR(0xe0002038); + return r; +} +static inline void timer0_ev_status_write(unsigned char value) { + MMPTR(0xe0002038) = value; +} +#define CSR_TIMER0_EV_PENDING_ADDR 0xe000203c +#define CSR_TIMER0_EV_PENDING_SIZE 1 +static inline unsigned char timer0_ev_pending_read(void) { + unsigned char r = MMPTR(0xe000203c); + return r; +} +static inline void timer0_ev_pending_write(unsigned char value) { + MMPTR(0xe000203c) = value; +} +#define CSR_TIMER0_EV_ENABLE_ADDR 0xe0002040 +#define CSR_TIMER0_EV_ENABLE_SIZE 1 +static inline unsigned char timer0_ev_enable_read(void) { + unsigned char r = MMPTR(0xe0002040); + return r; +} +static inline void timer0_ev_enable_write(unsigned char value) { + MMPTR(0xe0002040) = value; +} + +/* uart */ +#define CSR_UART_BASE 0xe0001000 +#define CSR_UART_RXTX_ADDR 0xe0001000 +#define CSR_UART_RXTX_SIZE 1 +static inline unsigned char uart_rxtx_read(void) { + unsigned char r = MMPTR(0xe0001000); + return r; +} +static inline void uart_rxtx_write(unsigned char value) { + MMPTR(0xe0001000) = value; +} +#define CSR_UART_TXFULL_ADDR 0xe0001004 +#define CSR_UART_TXFULL_SIZE 1 +static inline unsigned char uart_txfull_read(void) { + unsigned char r = MMPTR(0xe0001004); + return r; +} +#define CSR_UART_RXEMPTY_ADDR 0xe0001008 +#define CSR_UART_RXEMPTY_SIZE 1 +static inline unsigned char uart_rxempty_read(void) { + unsigned char r = MMPTR(0xe0001008); + return r; +} +#define CSR_UART_EV_STATUS_ADDR 0xe000100c +#define CSR_UART_EV_STATUS_SIZE 1 +static inline unsigned char uart_ev_status_read(void) { + unsigned char r = MMPTR(0xe000100c); + return r; +} +static inline void uart_ev_status_write(unsigned char value) { + MMPTR(0xe000100c) = value; +} +#define CSR_UART_EV_PENDING_ADDR 0xe0001010 +#define CSR_UART_EV_PENDING_SIZE 1 +static inline unsigned char uart_ev_pending_read(void) { + unsigned char r = MMPTR(0xe0001010); + return r; +} +static inline void uart_ev_pending_write(unsigned char value) { + MMPTR(0xe0001010) = value; +} +#define CSR_UART_EV_ENABLE_ADDR 0xe0001014 +#define CSR_UART_EV_ENABLE_SIZE 1 +static inline unsigned char uart_ev_enable_read(void) { + unsigned char r = MMPTR(0xe0001014); + return r; +} +static inline void uart_ev_enable_write(unsigned char value) { + MMPTR(0xe0001014) = value; +} + +/* uart_phy */ +#define CSR_UART_PHY_BASE 0xe0000800 +#define CSR_UART_PHY_TUNING_WORD_ADDR 0xe0000800 +#define CSR_UART_PHY_TUNING_WORD_SIZE 4 +static inline unsigned int uart_phy_tuning_word_read(void) { + unsigned int r = MMPTR(0xe0000800); + r <<= 8; + r |= MMPTR(0xe0000804); + r <<= 8; + r |= MMPTR(0xe0000808); + r <<= 8; + r |= MMPTR(0xe000080c); + return r; +} +static inline void uart_phy_tuning_word_write(unsigned int value) { + MMPTR(0xe0000800) = value >> 24; + MMPTR(0xe0000804) = value >> 16; + MMPTR(0xe0000808) = value >> 8; + MMPTR(0xe000080c) = value; +} + +/* constants */ +#define UART_INTERRUPT 0 +#define TIMER0_INTERRUPT 1 +#define ETHMAC_INTERRUPT 2 +#define SYSTEM_CLOCK_FREQUENCY 100000000 +#define A7DDRPHY_BITSLIP 2 +#define A7DDRPHY_DELAY 6 +#define L2_SIZE 8192 + +#endif diff --git a/configs/misoc/include/generated-sample/mem.h b/configs/misoc/include/generated-sample/mem.h new file mode 100644 index 00000000000..f4a9c9c6435 --- /dev/null +++ b/configs/misoc/include/generated-sample/mem.h @@ -0,0 +1,16 @@ +#ifndef __GENERATED_MEM_H +#define __GENERATED_MEM_H + +#define ROM_BASE 0x00000000 +#define ROM_SIZE 0x00008000 + +#define SRAM_BASE 0x10000000 +#define SRAM_SIZE 0x00008000 + +#define MAIN_RAM_BASE 0x40000000 +#define MAIN_RAM_SIZE 0x10000000 + +#define ETHMAC_BASE 0xb0000000 +#define ETHMAC_SIZE 0x00002000 + +#endif diff --git a/configs/misoc/include/generated-sample/output_format.ld b/configs/misoc/include/generated-sample/output_format.ld new file mode 100644 index 00000000000..72acc74d0f7 --- /dev/null +++ b/configs/misoc/include/generated-sample/output_format.ld @@ -0,0 +1 @@ +OUTPUT_FORMAT("elf32-lm32") diff --git a/configs/misoc/include/generated-sample/regions.ld b/configs/misoc/include/generated-sample/regions.ld new file mode 100644 index 00000000000..1708c3a309a --- /dev/null +++ b/configs/misoc/include/generated-sample/regions.ld @@ -0,0 +1,6 @@ +MEMORY { + rom : ORIGIN = 0x00000000, LENGTH = 0x00008000 + sram : ORIGIN = 0x10000000, LENGTH = 0x00008000 + main_ram : ORIGIN = 0x40000000, LENGTH = 0x10000000 + ethmac : ORIGIN = 0xb0000000, LENGTH = 0x00002000 +} diff --git a/configs/misoc/include/generated-sample/sdram_phy.h b/configs/misoc/include/generated-sample/sdram_phy.h new file mode 100644 index 00000000000..646cf7009ad --- /dev/null +++ b/configs/misoc/include/generated-sample/sdram_phy.h @@ -0,0 +1,102 @@ +#ifndef __GENERATED_SDRAM_PHY_H +#define __GENERATED_SDRAM_PHY_H +#include +#include +#include + +#define DFII_NPHASES 4 + +static void cdelay(int i); + +static void command_p0(int cmd) +{ + sdram_dfii_pi0_command_write(cmd); + sdram_dfii_pi0_command_issue_write(1); +} +static void command_p1(int cmd) +{ + sdram_dfii_pi1_command_write(cmd); + sdram_dfii_pi1_command_issue_write(1); +} +static void command_p2(int cmd) +{ + sdram_dfii_pi2_command_write(cmd); + sdram_dfii_pi2_command_issue_write(1); +} +static void command_p3(int cmd) +{ + sdram_dfii_pi3_command_write(cmd); + sdram_dfii_pi3_command_issue_write(1); +} + + +#define sdram_dfii_pird_address_write(X) sdram_dfii_pi0_address_write(X) +#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi2_address_write(X) + +#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi0_baddress_write(X) +#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi2_baddress_write(X) + +#define command_prd(X) command_p0(X) +#define command_pwr(X) command_p2(X) + +#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE + +const unsigned int sdram_dfii_pix_wrdata_addr[4] = { + CSR_SDRAM_DFII_PI0_WRDATA_ADDR, + CSR_SDRAM_DFII_PI1_WRDATA_ADDR, + CSR_SDRAM_DFII_PI2_WRDATA_ADDR, + CSR_SDRAM_DFII_PI3_WRDATA_ADDR +}; + +const unsigned int sdram_dfii_pix_rddata_addr[4] = { + CSR_SDRAM_DFII_PI0_RDDATA_ADDR, + CSR_SDRAM_DFII_PI1_RDDATA_ADDR, + CSR_SDRAM_DFII_PI2_RDDATA_ADDR, + CSR_SDRAM_DFII_PI3_RDDATA_ADDR +}; + +#define DDR3_MR1 6 + +static void init_sequence(void) +{ + /* Release reset */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + sdram_dfii_control_write(DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + cdelay(50000); + + /* Bring CKE high */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + cdelay(10000); + + /* Load Mode Register 2 */ + sdram_dfii_pi0_address_write(0x408); + sdram_dfii_pi0_baddress_write(2); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 3 */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(3); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 1 */ + sdram_dfii_pi0_address_write(0x6); + sdram_dfii_pi0_baddress_write(1); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 0, CL=7, BL=8 */ + sdram_dfii_pi0_address_write(0x930); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); + + /* ZQ Calibration */ + sdram_dfii_pi0_address_write(0x400); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); + +} +#endif diff --git a/configs/misoc/include/generated-sample/variables.mak b/configs/misoc/include/generated-sample/variables.mak new file mode 100644 index 00000000000..2bd0474215a --- /dev/null +++ b/configs/misoc/include/generated-sample/variables.mak @@ -0,0 +1,11 @@ +TRIPLE=lm32-elf +CPU=lm32 +CPUFLAGS=-mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled +CPUENDIANNESS=big +CLANG=0 +SOC_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc +BUILDINC_DIRECTORY=/home/lenovo/fpga/arty-soc/build/software/include +LIBBASE_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/libbase +LIBCOMPILER_RT_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/libcompiler_rt +LIBNET_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/libnet +BIOS_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/bios