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arch: arm: fixes for nxstyle errors

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Nxstyle error fixes to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea
2021-03-21 15:41:45 +01:00
committed by Xiang Xiao
parent e8606942eb
commit ee0861ae7a
95 changed files with 3104 additions and 1757 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/imxrt/hardware/imxrt_flexpwm.h
+125 -59
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File diff suppressed because it is too large Load Diff
arch/arm/src/imxrt/hardware/imxrt_gpt.h
+15 -9
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imxrt/hardware/imxrt_gpt.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,23 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_GPT_H
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_GPT_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imxrt_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define IMXRT_GPT_CR_OFFSET 0x0000 /* GPT Control Register */
#define IMXRT_GPT_PR_OFFSET 0x0004 /* GPT Prescaler Register */
@@ -45,7 +45,7 @@
#define IMXRT_GPT_ICR2_OFFSET 0x0020 /* GPT Input Capture Register 2 */
#define IMXRT_GPT_CNT_OFFSET 0x0024 /* GPT Counter Register */
/* Register addresses ***********************************************************************/
/* Register addresses *******************************************************/
#define IMXRT_GPT1_CR (IMXRT_GPT1_BASE + IMXRT_GPT1_CR_OFFSET) /* GPT 1 Control Register */
#define IMXRT_GPT1_PR (IMXRT_GPT1_BASE + IMXRT_GPT1_PR_OFFSET) /* GPT 1 Prescaler Register */
@@ -70,7 +70,7 @@
/* GPT Control Register */
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
#define GPT_CR_EN (1 << 0) /* Bit: 0 GPT Enable. */
#define GPT_CR_ENMOD (1 << 1) /* Bit: 1 GPT Enable mode. */
@@ -87,6 +87,7 @@
# define GPT_CR_CLKSRC_EXT (3 << GPT_CR_CLKSRC_SHIFT) /* External Clock */
# define GPT_CR_CLKSRC_IPG_LFR (4 << GPT_CR_CLKSRC_SHIFT) /* Low Frequency Reference Clock (ipg_clk_32k) */
# define GPT_CR_CLKSRC_IPG_24M (5 << GPT_CR_CLKSRC_SHIFT) /* Crystal oscillator as Reference Clock (ipg_clk_24M) */
#define GPT_CR_FRR (1 << 9) /* Bit: 9 Free-Run or Restart mode. */
#define GPT_CR_EN_24M (1 << 10) /* Bit: 10 Enable 24 MHz clock input from crystal. */
/* Bits: 11-14 Reserved */
@@ -98,6 +99,7 @@
# define GPT_CR_IM1_RISING (1 << GPT_CR_IM1_SHIFT) /* Capture on rising edge */
# define GPT_CR_IM1_FALLING (2 << GPT_CR_IM1_SHIFT) /* Capture on falling edge */
# define GPT_CR_IM1_BOTH (3 << GPT_CR_IM1_SHIFT) /* Capture on both edges */
#define GPT_CR_IM2_SHIFT (18) /* Bits: 18-19 IM2 (bits 19-18, Input Capture Channel 2 operating mode) */
#define GPT_CR_IM2_MASK (3 << GPT_CR_IM2_SHIFT)
# define GPT_CR_IM2(n) ((uint32_t)(n) << GPT_CR_IM2_SHIFT)
@@ -105,6 +107,7 @@
# define GPT_CR_IM2_RISING (1 << GPT_CR_IM2_SHIFT) /* Capture on rising edge */
# define GPT_CR_IM2_FALLING (2 << GPT_CR_IM2_SHIFT) /* Capture on falling edge */
# define GPT_CR_IM2_BOTH (3 << GPT_CR_IM2_SHIFT) /* Capture on both edges */
#define GPT_CR_OM1_SHIFT (20) /* Bits: 20-22 See OM3 */
#define GPT_CR_OM1_MASK (7 << GPT_CR_OM1_SHIFT)
# define GPT_CR_OM1(n) ((uint32_t)(n) << GPT_CR_OM1_SHIFT)
@@ -113,6 +116,7 @@
# define GPT_CR_OM1_CLEAR (2 << GPT_CR_OM1_SHIFT) /* Clear output pin */
# define GPT_CR_OM1_SET (3 << GPT_CR_OM1_SHIFT) /* Set output pin */
# define GPT_CR_OM1_PULSE (4 << GPT_CR_OM1_SHIFT) /* Generate an active low pulse */
#define GPT_CR_OM2_SHIFT (23) /* Bits: 23-25 See OM3 */
#define GPT_CR_OM2_MASK (7 << GPT_CR_OM2_SHIFT)
# define GPT_CR_OM2(n) ((uint32_t)(n) << GPT_CR_OM2_SHIFT)
@@ -121,6 +125,7 @@
# define GPT_CR_OM2_CLEAR (2 << GPT_CR_OM2_SHIFT) /* Clear output pin */
# define GPT_CR_OM2_SET (3 << GPT_CR_OM2_SHIFT) /* Set output pin */
# define GPT_CR_OM2_PULSE (4 << GPT_CR_OM2_SHIFT) /* Generate an active low pulse */
#define GPT_CR_OM3_SHIFT (26) /* Bits: 26-28 OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode. */
#define GPT_CR_OM3_MASK (7 << GPT_CR_OM3_SHIFT)
# define GPT_CR_OM3(n) ((uint32_t)(n) << GPT_CR_OM3_SHIFT)
@@ -129,6 +134,7 @@
# define GPT_CR_OM3_CLEAR (2 << GPT_CR_OM3_SHIFT) /* Clear output pin */
# define GPT_CR_OM3_SET (3 << GPT_CR_OM3_SHIFT) /* Set output pin */
# define GPT_CR_OM3_PULSE (4 << GPT_CR_OM3_SHIFT) /* Generate an active low pulse */
#define GPT_CR_FO1 (1 << 29) /* Bit: 29 See F03 */
#define GPT_CR_FO2 (1 << 30) /* Bit: 30 See F03 */
#define GPT_CR_FO3 (1 << 31) /* Bit: 31 FO3 Force Output Compare Channel 3 */
arch/arm/src/imxrt/hardware/imxrt_ocotp.h
+11 -11
View File
@@ -1,4 +1,4 @@
/************************************************************************************************************************************
/****************************************************************************
* arch/arm/src/imxrt/hardware/imxrt_ocotp.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,7 +16,7 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_OCOTP_H
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_OCOTP_H
@@ -27,18 +27,18 @@
* OTP, OCOTP Indexes are used.
*/
/************************************************************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imxrt_memorymap.h"
/************************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define IMXRT_OCOTP_CTRL_OFFSET 0x0000 /* OTP Controller Control Register */
#define IMXRT_OCOTP_CTRL_SET_OFFSET 0x0004 /* OTP Controller Control Register */
@@ -58,7 +58,7 @@
#define IMXRT_OCOTP_VERSION_OFFSET 0x0090 /* OTP Controller Version Register */
#define IMXRT_OCOTP_TIMING2_OFFSET 0x0100 /* OTP Controller Timing Register */
/* OCOTP Shadow Offsets *************************************************************/
/* OCOTP Shadow Offsets *****************************************************/
#define IMXRT_OCOTP_LOCK_OFFSET 0x0400 /* Value of OTP Bank0 Word0 (Lock controls) */
#define IMXRT_OCOTP_CFG0_OFFSET 0x0410 /* Value of OTP Bank0 Word1 (Configuration and Manufacturing */
@@ -124,7 +124,7 @@
#define IMXRT_OCOTP_GP42_OFFSET 0x08e0 /* Value of OTP Bank7 Word6 (GP4) */
#define IMXRT_OCOTP_GP43_OFFSET 0x08f0 /* Value of OTP Bank7 Word7 (GP4) */
/* OCOTP Indexes *****************************************************************/
/* OCOTP Indexes ************************************************************/
#define IMXRT_OCOTP_O2I(offset) (((offset) - IMXRT_OCOTP_LOCK_OFFSET) >> 4)
@@ -194,7 +194,7 @@
#define IMXRT_OCOTP_GP42_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP42_OFFSET) /* Value of OTP Bank7 Word6 (GP4) */
#define IMXRT_OCOTP_GP43_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP43_OFFSET) /* Value of OTP Bank7 Word7 (GP4) */
/* Register addresses ***********************************************************************************************************************/
/* Register addresses *******************************************************/
#define IMXRT_OCOTP_CTRL (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CTRL_OFFSET) /* OTP Controller Control Register */
#define IMXRT_OCOTP_CTRL_SET (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CTRL_SET_OFFSET) /* OTP Controller Control Register */
@@ -276,7 +276,7 @@
#define IMXRT_OCOTP_GP42 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP42_OFFSET) /* Value of OTP Bank7 Word6 (GP4) */
#define IMXRT_OCOTP_GP43 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP43_OFFSET) /* Value of OTP Bank7 Word7 (GP4) */
/* Register Bit Definitions *********************************************************************************************************/
/* Register Bit Definitions *************************************************/
/* OTP Controller Control Register */
arch/arm/src/imxrt/hardware/imxrt_pit.h
+2 -1
View File
@@ -85,6 +85,7 @@
/* Bits 2-31: Reserved */
/* Timer Load Value Register (32-bit Timer Start Value Bits) */
/* Current Timer Value Register (32-bit Current Timer Value) */
/* Timer Control Register */
@@ -109,7 +110,7 @@
************************************************************************************/
/************************************************************************************
* Public Functions
* Public Functions Prototypes
************************************************************************************/
#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_PIT_H */
arch/arm/src/imxrt/hardware/imxrt_tmr.h
+22 -15
View File
@@ -1,4 +1,4 @@
/********************************************************************************************************************************************
/****************************************************************************
* arch/arm/src/imxrt/hardware/imxrt_tmr.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,23 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_TMR_H
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_TMR_H
/********************************************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imxrt_memorymap.h"
/********************************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************************************/
****************************************************************************/
/* Register Offsets *************************************************************************************************************************/
/* Register Offsets *********************************************************/
#define IMXRT_TMR_COMP1_OFFSET 0x0000 /* Timer Channel Compare Register 1 */
#define IMXRT_TMR_COMP2_OFFSET 0x0002 /* Timer Channel Compare Register 2 */
@@ -279,7 +279,7 @@
#define IMXRT_TMR4_FILT3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_FILT_OFFSET) /* Timer Channel Input Filter Register */
#define IMXRT_TMR4_DMA3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_DMA_OFFSET) /* Timer Channel DMA Enable Register */
/* Register addresses *******************************************************************************************************************************/
/* Register addresses *******************************************************/
#define IMXRT_TMR1_COMP10 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_COMP10_OFFSET) /* Timer Channel Compare Register 1 */
#define IMXRT_TMR1_COMP20 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_COMP20_OFFSET) /* Timer Channel Compare Register 2 */
@@ -494,7 +494,7 @@
#define IMXRT_TMR4_FILT3 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_FILT3_OFFSET) /* Timer Channel Input Filter Register */
#define IMXRT_TMR4_DMA3 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_DMA3_OFFSET) /* Timer Channel DMA Enable Register */
/* Register Bit Definitions *****************************************************************************************************************/
/* Register Bit Definitions *************************************************/
/* Timer Channel Control Register */
@@ -509,6 +509,7 @@
# define TMR_CTRL_OUTMODE_SET_CLR (5 << TMR_CTRL_OUTMODE_SHIFT) /* Set on compare, cleared on secondary source input edge */
# define TMR_CTRL_OUTMODE_SET_CLR_ROL (6 << TMR_CTRL_OUTMODE_SHIFT) /* Set on compare, cleared on counter rollover */
# define TMR_CTRL_OUTMODE_GATED (7 << TMR_CTRL_OUTMODE_SHIFT) /* Enable gated clock output while counter is active */
#define TMR_CTRL_COINIT (1 << 3) /* Bit: 3 Co-Channel Initialization */
#define TMR_CTRL_DIR (1 << 4) /* Bit: 4 Count Direction */
#define TMR_CTRL_LENGTH (1 << 5) /* Bit: 5 Count Length */
@@ -520,6 +521,7 @@
# define TMR_CTRL_SCS_CNTR1 (1 << TMR_CTRL_SCS_SHIFT) /* Counter 1 input pin */
# define TMR_CTRL_SCS_CNTR2 (2 << TMR_CTRL_SCS_SHIFT) /* Counter 2 input pin */
# define TMR_CTRL_SCS_CNTR3 (3 << TMR_CTRL_SCS_SHIFT) /* Counter 3 input pin */
#define TMR_CTRL_PCS_SHIFT (9) /* Bits: 9-12 Primary Count Source */
#define TMR_CTRL_PCS_MASK (15 << TMR_CTRL_PCS_SHIFT)
# define TMR_CTRL_PCS(n) ((uint32_t)(n) << TMR_CTRL_PCS_SHIFT)
@@ -533,12 +535,13 @@
# define TMR_CTRL_PCS_OUT3 (7 << TMR_CTRL_PCS_SHIFT) /* Counter 3 output */
# define TMR_CTRL_PCS_DIV1 (8 << TMR_CTRL_PCS_SHIFT) /* IP bus clock divide by 1 prescaler */
# define TMR_CTRL_PCS_DIV2 (9 << TMR_CTRL_PCS_SHIFT) /* IP bus clock divide by 2 prescaler */
# define TMR_CTRL_PCS_DIV4 (10 << TMR_CTRL_PCS_SHIFT) /*IP bus clock divide by 4 prescaler */
# define TMR_CTRL_PCS_DIV8 (11 << TMR_CTRL_PCS_SHIFT) /*IP bus clock divide by 8 prescaler */
# define TMR_CTRL_PCS_DIV16 (12 << TMR_CTRL_PCS_SHIFT) /*IP bus clock divide by 16 prescaler */
# define TMR_CTRL_PCS_DIV32 (13 << TMR_CTRL_PCS_SHIFT) /*IP bus clock divide by 32 prescaler */
# define TMR_CTRL_PCS_DIV64 (14 << TMR_CTRL_PCS_SHIFT) /*IP bus clock divide by 64 prescaler */
# define TMR_CTRL_PCS_DIV128 (15 << TMR_CTRL_PCS_SHIFT) /*IP bus clock divide by 128 prescaler */
# define TMR_CTRL_PCS_DIV4 (10 << TMR_CTRL_PCS_SHIFT) /* IP bus clock divide by 4 prescaler */
# define TMR_CTRL_PCS_DIV8 (11 << TMR_CTRL_PCS_SHIFT) /* IP bus clock divide by 8 prescaler */
# define TMR_CTRL_PCS_DIV16 (12 << TMR_CTRL_PCS_SHIFT) /* IP bus clock divide by 16 prescaler */
# define TMR_CTRL_PCS_DIV32 (13 << TMR_CTRL_PCS_SHIFT) /* IP bus clock divide by 32 prescaler */
# define TMR_CTRL_PCS_DIV64 (14 << TMR_CTRL_PCS_SHIFT) /* IP bus clock divide by 64 prescaler */
# define TMR_CTRL_PCS_DIV128 (15 << TMR_CTRL_PCS_SHIFT) /* IP bus clock divide by 128 prescaler */
#define TMR_CTRL_CM_SHIFT (13) /* Bits: 13-15 Count Mode */
#define TMR_CTRL_CM_MASK (7 << TMR_CTRL_CM_SHIFT)
# define TMR_CTRL_CM(n) ((uint32_t)(n) << TMR_CTRL_CM_SHIFT)
@@ -566,6 +569,7 @@
# define TMR_SCTRL_CAPTURE_RISING (1 << TMR_SCTRL_CAPTURE_MODE_SHIFT) /* Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input */
# define TMR_SCTRL_CAPTURE_FALLING (2 << TMR_SCTRL_CAPTURE_MODE_SHIFT) /* Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input */
# define TMR_SCTRL_CAPTURE_BOTH (3 << TMR_SCTRL_CAPTURE_MODE_SHIFT) /* Load capture register on both edges of input */
#define TMR_SCTRL_INPUT (1 << 8) /* Bit: 8 External Input Signal */
#define TMR_SCTRL_IPS (1 << 9) /* Bit: 9 Input Polarity Select */
#define TMR_SCTRL_IEFIE (1 << 10) /* Bit: 10 Input Edge Flag Interrupt Enable */
@@ -583,12 +587,14 @@
# define TMR_CSCTRL_CL1_DIS (0 << TMR_CSCTRL_CL1_SHIFT) /* Never preload */
# define TMR_CSCTRL_CL1_COMP1 (1 << TMR_CSCTRL_CL1_SHIFT) /* Load upon successful compare with the value in COMP1 */
# define TMR_CSCTRL_CL1_COMP2 (2 << TMR_CSCTRL_CL1_SHIFT) /* Load upon successful compare with the value in COMP2 */
#define TMR_CSCTRL_CL2_SHIFT (2) /* Bits: 2-3 Compare Load Control 2 */
#define TMR_CSCTRL_CL2_MASK (3 << TMR_CSCTRL_CL2_SHIFT)
# define TMR_CSCTRL_CL2(n) ((uint32_t)(n) << TMR_CSCTRL_CL2_SHIFT)
# define TMR_CSCTRL_CL2_DIS (0 << TMR_CSCTRL_CL2_SHIFT) /* Never preload */
# define TMR_CSCTRL_CL2_COMP1 (1 << TMR_CSCTRL_CL2_SHIFT) /* Load upon successful compare with the value in COMP1 */
# define TMR_CSCTRL_CL2_COMP2 (2 << TMR_CSCTRL_CL2_SHIFT) /* Load upon successful compare with the value in COMP2 */
#define TMR_CSCTRL_TCF1 (1 << 4) /* Bit: 4 Timer Compare 1 Interrupt Flag */
#define TMR_CSCTRL_TCF2 (1 << 5) /* Bit: 5 Timer Compare 2 Interrupt Flag */
#define TMR_CSCTRL_TCF1EN (1 << 6) /* Bit: 6 Timer Compare 1 Interrupt Enable */
@@ -641,6 +647,7 @@
# define TMR_ENBL_CHN1 (2 << TMR_ENBL_ENBL_SHIFT) /* Channel 1 enable */
# define TMR_ENBL_CHN3 (4 << TMR_ENBL_ENBL_SHIFT) /* Channel 2 enable */
# define TMR_ENBL_CHN4 (8 << TMR_ENBL_ENBL_SHIFT) /* Channel 3 enable */
/* Bits: 4-15 Reserved */
#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_TMR_H */
arch/arm/src/imxrt/hardware/imxrt_usb_analog.h
+14 -11
View File
@@ -1,4 +1,4 @@
/************************************************************************************************************************************
/****************************************************************************
* arch/arm/src/imxrt/hardware/imxrt_usb_analog.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,23 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USB_ANALOG_H
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USB_ANALOG_H
/************************************************************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imxrt_memorymap.h"
/************************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************************************************************/
/* Register Offsets *********************************************************/
#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_OFFSET 0x01a0 /* USB VBUS Detect Register */
#define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_SET_OFFSET 0x01a4 /* USB VBUS Detect Set Register */
@@ -64,7 +64,7 @@
#define IMXRT_USB_ANALOG_USB2_MISC_TOG_OFFSET 0x025c /* USB Misc Toggle Register */
#define IMXRT_USB_ANALOG_DIGPROG_OFFSET 0x0260 /* Chip Silicon Version */
/* Register addresses ***********************************************************************************************************************/
/* Register addresses *******************************************************/
/* Analog USB1 Register Addresses */
@@ -130,7 +130,7 @@
#define IMXRT_USB_ANALOG_USB2_MISC_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_MISC_TOG_OFFSET) /* USB_ANALOG2 USB Misc Toggle Register */
#define IMXRT_USB_ANALOG_DIGPROG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_DIGPROG_OFFSET) /* USB_ANALOG2 Chip Silicon Version */
/* Register Bit Definitions *********************************************************************************************************/
/* Register Bit Definitions *************************************************/
/* USB VBUS Detect Register */
@@ -145,7 +145,9 @@
# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V5 (5 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V5 — 4.5V */
# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V6 (6 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V6 — 4.6V */
# define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V7 (7 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V7 — 4.7V */
/* Bits: 3-19 Reserved */
/* Bits: 3-19 Reserved */
#define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_PWRUP_CMPS (1 << 20) /* Bit: 20 Powers up comparators for vbus_valid detector. */
/* Bits: 21-25 Reserved */
#define USB_ANALOG_USB_VBUS_DETECT_DISCHARGE_VBUS (1 << 26) /* Bit: 26 USB OTG discharge VBUS. */
@@ -154,7 +156,8 @@
/* USB Charger Detect Register */
/* Bits: 0-17 Reserved */
/* Bits: 0-17 Reserved */
#define USB_ANALOG_USB_CHRG_DETECT_CHK_CONTACT (1 << 18) /* Bit: 18 Check the contact of USB plug */
#define USB_ANALOG_USB_CHRG_DETECT_CHK_CHRG_B (1 << 19) /* Bit: 19 Check the charger connection */
#define USB_ANALOG_USB_CHRG_DETECT_EN_B (1 << 20) /* Bit: 20 Control the charger detector. */
arch/arm/src/imxrt/hardware/imxrt_xbar.h
-1
View File
@@ -39,7 +39,6 @@
# error Unrecognized i.MX RT architecture
#endif
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h
+1
View File
@@ -77,6 +77,7 @@
#define IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET 0x000c /* SNVC GPR3 General Purpose Register */
/* Pad Mux Registers */
/* Pad Mux Register Indices (used by software for table lookups) */
#define IMXRT_PADMUX_GPIO_EMC_00_INDEX 0
arch/arm/src/imxrt/hardware/rt106x/imxrt106x_iomuxc.h
+1
View File
@@ -86,6 +86,7 @@
#define IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET 0x000c /* SNVC GPR3 General Purpose Register */
/* Pad Mux Registers */
/* Pad Mux Register Indices (used by software for table lookups) */
#define IMXRT_PADMUX_GPIO_EMC_00_INDEX 0
arch/arm/src/imxrt/hardware/rt106x/imxrt106x_memorymap.h
+133 -7
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imxrt/hardware/rt106x/imxrt106x_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,58 +16,86 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_MEMORYMAP_H
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_MEMORYMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* System memory map */
#define IMXRT_ITCM_BASE 0x00000000 /* 512KB ITCM */
/* 0x00080000 512KB ITCM Reserved */
/* 0x00100000 1MB ITCM Reserved */
#define IMXRT_ROMCP_BASE 0x00200000 /* 128KB ROMCP */
/* 0x00220000 384KB ROMCP Reserved */
/* 0x00280000 1536KB Reserved */
/* 0x00400000 124MB Reserved */
#define IMXRT_FLEXSPI_BASE 0x08000000 /* 128MB FlexSPI (Aliased) */
#define IMXRT_SEMCA_BASE 0x10000000 /* 256MB SEMC (Aliased) */
#define IMXRT_DTCM_BASE 0x20000000 /* 512KB DTCM */
/* 0x20080000 512KB DTCM Reserved */
/* 0x20100000 1MB Reserved */
#define IMXRT_OCRAM2_BASE 0x20200000 /* 512KB OCRAM2 */
#define IMXRT_OCRAM_BASE 0x20280000 /* 512KB OCRAM FlexRAM */
/* 0x20300000 512KB OCRAM Reserved */
/* 0x20400000 252MB Reserved */
/* 0x30000000 256MB Reserved */
#define IMXRT_AIPS1_BASE 0x40000000 /* 1MB AIPS-1 */
#define IMXRT_AIPS2_BASE 0x40100000 /* 1MB AIPS-2 */
#define IMXRT_AIPS3_BASE 0x40200000 /* 1MB AIPS-3 */
#define IMXRT_AIPS4_BASE 0x40300000 /* 1MB AIPS-4 */
/* 40400000 12MB Reserved */
#define IMXRT_MAINCNF_BASE 0x41000000 /* 1MB "main" configuration port */
#define IMXRT_MCNF_BASE 0x41100000 /* 1MB "m" configuration port */
/* 41200000 1MB Reserved for "per" GPV */
/* 41300000 1MB Reserved for "ems" GPV */
#define IMXRT_CPUCNF_BASE 0x41400000 /* 1MB "cpu" configuration port */
/* 0x41500000 1MB GPV Reserved */
/* 0x41600000 1MB GPV Reserved */
/* 0x41700000 1MB GPV Reserved */
/* 0x41800000 8MB Reserved */
#define IMXRT_AIPS5_BASE 0x42000000 /* 1MB AIPS-5 */
/* 0x42100000 31MB Reserved */
/* 0x44000000 64MB Reserved */
/* 0x48000000 384MB Reserved */
#define IMXRT_FLEXCIPHER_BASE 0x60000000 /* 256MB FlexSPI/ FlexSPI ciphertext */
#define IMXRT_FLEX2CIPHER_BASE 0x70000000 /* 240MB FlexSPI2/ FlexSPI ciphertext */
#define IMXRT_FLEXSPI2TX_BASE 0x7f000000 /* 4MB FlexSPI2 TX FIFO */
@@ -76,22 +104,32 @@
#define IMXRT_FLEXSPIRX_BASE 0x7fc00000 /* 4MB FlexSPI RX FIFO */
#define IMXRT_EXTMEM_BASE 0x80000000 /* 1.5GB SEMC external memories shared memory space */
#define IMXRT_CM7_BASE 0xe0000000 /* 1MB CM7 PPB */
/* 0xe0100000 511MB Reserved */
/* AIPS-1 memory map */
/* 0x40000000 256KB Reserved */
/* 0x40040000 240KB Reserved */
#define IMXRT_AIPS1CNF_BASE 0x4007c000 /* 6KB AIPS-1 Configuration */
#define IMXRT_DCDC_BASE 0x40080000 /* 16KB DCDC */
#define IMXRT_PIT_BASE 0x40084000 /* 16KB PIT */
/* 0x40088000 16KB Reserved */
/* 0x4008c000 16KB Reserved */
#define IMXRT_MTR_BASE 0x40090000 /* 16KB MTR */
#define IMXRT_ACMP_BASE 0x40094000 /* 16KB ACMP */
/* 0x40098000 16KB Reserved */
/* 0x4009c000 16KB Reserved */
/* 0x400a0000 16KB Reserved */
#define IMXRT_IOMUXCSNVSGPR_BASE 0x400a4000 /* 16KB IOMUXC_SNVS_GPR */
#define IMXRT_IOMUXCSNVS_BASE 0x400a8000 /* 16KB IOMUXC_SNVS */
#define IMXRT_IOMUXCGPR_BASE 0x400ac000 /* 16KB IOMUXC_GPR */
@@ -107,11 +145,16 @@
#define IMXRT_SNVSHP_BASE 0x400d4000 /* 16KB SNVS_HP */
#define IMXRT_ANATOP_BASE 0x400d8000 /* 16KB ANATOP */
#define IMXRT_CSU_BASE 0x400dc000 /* 16KB CSU */
/* 0x400e0000 16KB Reserved */
/* 0x400e4000 16KB Reserved */
#define IMXRT_EDMA_BASE 0x400e8000 /* 16KB EDMA */
#define IMXRT_DMAMUX_BASE 0x400ec000 /* 16KB DMA_CH_MUX */
/* 400f0000 16KB Reserved */
#define IMXRT_GPC_BASE 0x400f4000 /* 16KB GPC */
#define IMXRT_SRC_BASE 0x400f8000 /* 16KB SRC */
#define IMXRT_CCM_BASE 0x400fc000 /* 16KB CCM */
@@ -119,7 +162,9 @@
/* AIPS-2 memory map */
/* 0x40100000 256KB Reserved */
/* 0x40140000 240KB Reserved */
#define IMXRT_AIPS2CNF_BASE 0x4017c000 /* 16KB AIPS-2 Configuration */
#define IMXRT_ROMCPC_BASE 0x40180000 /* 16KB ROMCP controller*/
#define IMXRT_LPUART1_BASE 0x40184000 /* 16KB LPUART1 */
@@ -130,17 +175,25 @@
#define IMXRT_LPUART6_BASE 0x40198000 /* 16KB LPUART6 */
#define IMXRT_LPUART7_BASE 0x4019c000 /* 16KB LPUART7 */
#define IMXRT_LPUART8_BASE 0x401a0000 /* 16KB LPUART8 */
/* 0x401a4000 16KB Reserved */
/* 0x401a8000 16KB Reserved */
#define IMXRT_FLEXIO1_BASE 0x401ac000 /* 16KB FlexIO1 */
#define IMXRT_FLEXIO2_BASE 0x401b0000 /* 16KB FlexIO2 */
/* 0x401b4000 16KB Reserved */
#define IMXRT_GPIO1_BASE 0x401b8000 /* 16KB GPIO1 */
#define IMXRT_GPIO2_BASE 0x401bc000 /* 16KB GPIO2 */
#define IMXRT_GPIO3_BASE 0x401c0000 /* 16KB GPIO3 */
#define IMXRT_GPIO4_BASE 0x401c4000 /* 16KB GPIO4 */
/* 0x401c8000 16KB Reserved */
/* 0x401cc000 16KB Reserved */
#define IMXRT_CAN1_BASE 0x401d0000 /* 16KB CAN1 */
#define IMXRT_CAN2_BASE 0x401d4000 /* 16KB CAN2 */
#define IMXRT_CAN3_BASE 0x401d8000 /* 16KB CAN3 */
@@ -157,59 +210,94 @@
/* AIPS-3 memory map */
/* 0x40200000 256KB Reserved */
/* 0x40240000 240KB Reserved */
#define IMXRT_AIOS3CNF_BASE 0x4027c000 /* 16KB AIPS-3 Configuration */
/* 0x40280000 16KB Reserved */
/* 0x40284000 16KB Reserved */
/* 0x40288000 16KB Reserved */
/* 0x4028c000 16KB Reserved */
/* 0x40290000 16KB Reserved */
/* 0x40294000 16KB Reserved */
/* 0x40298000 16KB Reserved */
/* 0x4029c000 16KB Reserved */
/* 0x402a0000 16KB Reserved */
#define IMXRT_FLEXSPI2C_BASE 0x402a4000 /* 16KB FlexSPI2 */
#define IMXRT_FLEXSPIC_BASE 0x402a8000 /* 16KB FlexSPI */
/* 0x402ac000 16KB Reserved */
/* 0x402b0000 16KB Reserved */
#define IMXRT_PXP_BASE 0x402b4000 /* 16KB PXP */
#define IMXRT_LCDIF_BASE 0x402b8000 /* 16KB LCDIF */
#define IMXRT_CSI_BASE 0x402bc000 /* 16KB CSI */
#define IMXRT_USDHC1_BASE 0x402c0000 /* 16KB USDHC1 */
#define IMXRT_USDHC2_BASE 0x402c4000 /* 16KB USDHC2 */
/* 0x402c8000 16KB Reserved */
/* 0x402cc000 16KB Reserved */
/* 0x402d0000 16KB Reserved */
/* 0x402d4000 16KB Reserved */
#define IMXRT_ENET2_BASE 0x402d4000 /* 16KB ENET2 */
#define IMXRT_ENET_BASE 0x402d8000 /* 16KB ENET */
#define IMXRT_USBPL301_BASE 0x402dc000 /* 16KB USB(PL301) */
#define IMXRT_USB_BASE 0x402e0000 /* 16KB USB(USB) */
/* 0x402e4000 16KB Reserved */
/* 0x402e8000 16KB Reserved */
/* 0x402ec000 16KB Reserved */
#define IMXRT_SEMC_BASE 0x402f0000 /* 16KB SEMC */
/* 0x402f4000 16KB Reserved */
/* 0x402f8000 16KB Reserved */
#define IMXRT_DCP_BASE 0x402fc000 /* 16KB DCP */
/* AIPS-4 memory map */
/* 0x40300000 256KB Reserved */
/* 0x40340000 240KB Reserved */
#define IMXRT_AIPS4CNF_BASE 0x4037c000 /* 16KB AIPS-4 Configuration */
#define IMXRT_SPDIF_BASE 0x40380000 /* 16KB SPDIF */
#define IMXRT_SAI1_BASE 0x40384000 /* 16KB SAI1 */
#define IMXRT_SAI2_BASE 0x40388000 /* 16KB SAI2 */
#define IMXRT_SAI3_BASE 0x4038c000 /* 16KB SAI3 */
/* 0x40390000 16KB Reserved */
#define IMXRT_LPSPI1_BASE 0x40394000 /* 16KB LPSPI1 */
#define IMXRT_LPSPI2_BASE 0x40398000 /* 16KB LPSPI2 */
#define IMXRT_LPSPI3_BASE 0x4039c000 /* 16KB LPSPI3 */
#define IMXRT_LPSPI4_BASE 0x403a0000 /* 16KB LPSPI4 */
/* 0x403a4000 16KB Reserved */
/* 0x403a8000 16KB Reserved */
/* 0x403ac000 16KB Reserved */
#define IMXRT_ADCETC_BASE 0x403b0000 /* 16KB ADC_ETC */
#define IMXRT_AOI1_BASE 0x403b4000 /* 16KB AOI1 */
#define IMXRT_AOI2_BASE 0x403b8000 /* 16KB AOI2 */
@@ -220,7 +308,9 @@
#define IMXRT_ENC2_BASE 0x403cc000 /* 16KB ENC2 */
#define IMXRT_ENC3_BASE 0x403d0000 /* 16KB ENC3 */
#define IMXRT_ENC4_BASE 0x403d4000 /* 16KB ENC4 */
/* 0x403d8000 16KB Reserved */
#define IMXRT_FLEXPWM1_BASE 0x403dc000 /* 16KB FLEXPWM1 */
#define IMXRT_FLEXPWM2_BASE 0x403e0000 /* 16KB FLEXPWM2 */
#define IMXRT_FLEXPWM3_BASE 0x403e4000 /* 16KB FLEXPWM3 */
@@ -237,35 +327,66 @@
#define IMXRT_GPIO7_BASE 0x42004000 /* 16KB GPIO7 */
#define IMXRT_GPIO8_BASE 0x42008000 /* 16KB GPIO8 */
#define IMXRT_GPIO9_BASE 0x4200c000 /* 16KB GPIO9 */
/* 0x42010000 16KB Reserved */
/* 0x42014000 16KB Reserved */
/* 0x42018000 16KB Reserved */
/* 0x4201c000 16KB Reserved */
#define IMXRT_FLEXIO3_BASE 0x42020000 /* 16KB FlexIO3 */
/* 0x42024000 16KB Reserved */
/* 0x42028000 16KB Reserved */
/* 0x4202c000 16KB Reserved */
/* 0x42030000 16KB Reserved */
/* 0x42034000 16KB Reserved */
/* 0x42038000 16KB Reserved */
/* 0x4203c000 16KB Reserved */
/* 0x42040000 16KB Reserved */
/* 0x42044000 16KB Reserved */
/* 0x42048000 16KB Reserved */
/* 0x4204c000 16KB Reserved */
/* 0x42050000 16KB Reserved */
/* 0x42054000 16KB Reserved */
/* 0x42058000 16KB Reserved */
/* 0x4205c000 16KB Reserved */
/* 0x42060000 16KB Reserved */
/* 0x42064000 16KB Reserved */
/* 0x42068000 16KB Reserved */
/* 0x4206c000 16KB Reserved */
/* 0x42070000 16KB Reserved */
/* 0x42074000 16KB Reserved */
/* 0x42078000 16KB Reserved */
/* 0x4207c000 16KB Reserved */
/* 0x42080000 512KB Reserved Off Platform */
/* 0x42080000 512KB Reserved */
/* Off Platform */
/* PPB memory map */
@@ -274,10 +395,15 @@
#define IMXRT_CTI_BASE 0xe0042000 /* 4KB CTI */
#define IMXRT_TSGEN_BASE 0xe0043000 /* 4KB TSGEN */
#define IMXRT_PPBRES_BASE 0xe0044000 /* 4KB PPB RES */
/* 0xe0045000 236KB PPB Reserved */
#define IMXRT_MCM_BASE 0xe0080000 /* 4KB MCM */
/* 0xe0081000 444KB PPB Reserved */
/* 0xe00f0000 52KB PPB Reserved */
#define IMXRT_SYSROM_BASE 0xe00fd000 /* 4KB SYS ROM */
#define IMXRT_PROCROM_BASE 0xe00fe000 /* 4KB Processor ROM */
#define IMXRT_PPBROM_BASE 0xe00ff000 /* 4KB PPB ROM */
arch/arm/src/imxrt/imxrt105x_daisy.c
+613 -304
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/imxrt/imxrt106x_daisy.c
+635 -278
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/imxrt/imxrt_xbar.c
+5 -2
View File
@@ -89,14 +89,17 @@ int imxrt_xbar_connect(uint16_t mux_index_out, uint16_t mux_index_input)
* 4) Input index is input.
*/
if (xbar_index < sizeof(g_xbars_addresses) / sizeof(g_xbars_addresses[0]) &&
if (xbar_index < sizeof(g_xbars_addresses) /
sizeof(g_xbars_addresses[0]) &&
(mux_index_out & XBAR_OUTPUT) == XBAR_OUTPUT &&
(mux_index_input & XBAR_INPUT) == XBAR_INPUT)
{
address = g_xbars_addresses[xbar_index];
address += (mux_select / IMXRT_SEL_PER_REG) * sizeof(uint16_t);
/* There are 2 selects per Register LSB is even selects and MSB is odd */
/* There are 2 selects per Register LSB is even selects and
* MSB is odd
*/
if (mux_select & 1)
{
arch/arm/src/imxrt/imxrt_xbar.h
+39 -37
View File
@@ -1,4 +1,4 @@
/**************************************************************************************************************************************************
/****************************************************************************
* arch/arm/src/imxrt/imxrt_xbar.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,27 @@
* License for the specific language governing permissions and limitations
* under the License.
*
**************************************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_XBAR_H
#define __ARCH_ARM_SRC_IMXRT_IMXRT_XBAR_H
/**************************************************************************************************************************************************
/****************************************************************************
* Included Files
**************************************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "hardware/imxrt_xbar.h"
#include "hardware/imxrt_memorymap.h"
/**************************************************************************************************************************************************
/* Collect correct XBAR definitions from chip file */
#include "hardware/imxrt_xbar.h"
/****************************************************************************
* Pre-processor Definitions
**************************************************************************************************************************************************/
****************************************************************************/
/* Cross Bars
*
@@ -48,7 +52,8 @@
* Therefore there are M select fields that will be written to I values.
* The M fields are know as SELn, there are 2 selects fields per register.
*
* A Input is wired to an output with a call to imxrt_xbar_connect(output, input)
* A Input is wired to an output with a call to imxrt_xbar_connect(output,
* input)
*
*/
@@ -57,52 +62,49 @@
* v vvvv +++++++---- Index of input or output index
* 000s xxxx nnnnnnnn
*
* Where side is used to parameter check the passed value in output is an output
* XBAR is the index of the XBAR
* Where side is used to parameter check the passed value in output is an
* output XBAR is the index of the XBAR
* input|output index - the index of the M mux (output) or I.
*
*/
/* Input and Output Indexes */
#define IMXRT_XBARA_IO_INDEX_SHIFTS 0
#define IMXRT_XBARA_IO_INDEX_MASK (0xff << IMXRT_XBARA_IO_INDEX_SHIFTS)
#define IMXRT_XBARA_IO_INDEX_SHIFTS 0
#define IMXRT_XBARA_IO_INDEX_MASK (0xff << IMXRT_XBARA_IO_INDEX_SHIFTS)
/* Index for xbar addresses */
#define IMXRT_XBARA_INDEX_SHIFTS 8
#define IMXRT_XBARA_INDEX_MASK (0xf << IMXRT_XBARA_INDEX_SHIFTS)
# define IMXRT_XBARA1_INDEX (0 << IMXRT_XBARA_INDEX_SHIFTS)
# define IMXRT_XBARA2_INDEX (1 << IMXRT_XBARA_INDEX_SHIFTS)
# define IMXRT_XBARA3_INDEX (2 << IMXRT_XBARA_INDEX_SHIFTS)
#define IMXRT_XBARA_INDEX_SHIFTS 8
#define IMXRT_XBARA_INDEX_MASK (0xf << IMXRT_XBARA_INDEX_SHIFTS)
# define IMXRT_XBARA1_INDEX (0 << IMXRT_XBARA_INDEX_SHIFTS)
# define IMXRT_XBARA2_INDEX (1 << IMXRT_XBARA_INDEX_SHIFTS)
# define IMXRT_XBARA3_INDEX (2 << IMXRT_XBARA_INDEX_SHIFTS)
/* Side of xbar */
#define IMXRT_XBARA_SIDE_SHIFTS 12
#define IMXRT_XBARA_SIDE_MASK (0x1 << IMXRT_XBARA_SIDE_SHIFTS)
#define IMXRT_XBARA_SIDE_SHIFTS 12
#define IMXRT_XBARA_SIDE_MASK (0x1 << IMXRT_XBARA_SIDE_SHIFTS)
#define XBAR_OUTPUT (0x1 << IMXRT_XBARA_SIDE_SHIFTS)
#define XBAR_INPUT (0x0 << IMXRT_XBARA_SIDE_SHIFTS)
#define XBAR_OUTPUT (0x1 << IMXRT_XBARA_SIDE_SHIFTS)
#define XBAR_INPUT (0x0 << IMXRT_XBARA_SIDE_SHIFTS)
/* xbar helpers */
#define IMXRT_XBARA1(side, select) ((uint16_t)((side) | IMXRT_XBARA1_INDEX | \
((select) & 0xff) << IMXRT_XBARA_IO_INDEX_SHIFTS))
#define IMXRT_XBARA2(side, select) ((uint16_t)((side) | IMXRT_XBARA2_INDEX | \
((select) & 0xff) << IMXRT_XBARA_IO_INDEX_SHIFTS))
#define IMXRT_XBARA3(side, select) ((uint16_t)((side) | IMXRT_XBARA3_INDEX | \
((select) & 0xff) << IMXRT_XBARA_IO_INDEX_SHIFTS))
#define IMXRT_XBARA1(side, select) ((uint16_t)((side) | IMXRT_XBARA1_INDEX | \
((select) & 0xff) << IMXRT_XBARA_IO_INDEX_SHIFTS))
#define IMXRT_XBARA2(side, select) ((uint16_t)((side) | IMXRT_XBARA2_INDEX | \
((select) & 0xff) << IMXRT_XBARA_IO_INDEX_SHIFTS))
#define IMXRT_XBARA3(side, select) ((uint16_t)((side) | IMXRT_XBARA3_INDEX | \
((select) & 0xff) << IMXRT_XBARA_IO_INDEX_SHIFTS))
#define IMXRT_SEL(six) ((six) & IMXRT_XBARA_IO_INDEX_MASK) >> IMXRT_XBARA_IO_INDEX_SHIFTS
#define IMXRT_XBAR(six) ((six) & IMXRT_XBARA_INDEX_MASK) >> IMXRT_XBARA_INDEX_SHIFTS
#define IMXRT_SIDE(six) ((six) & IMXRT_XBARA_SIDE_MASK) >> IMXRT_XBARA_SIDE_SHIFTS
#define IMXRT_SEL(six) ((six) & IMXRT_XBARA_IO_INDEX_MASK) >> IMXRT_XBARA_IO_INDEX_SHIFTS
#define IMXRT_XBAR(six) ((six) & IMXRT_XBARA_INDEX_MASK) >> IMXRT_XBARA_INDEX_SHIFTS
#define IMXRT_SIDE(six) ((six) & IMXRT_XBARA_SIDE_MASK) >> IMXRT_XBARA_SIDE_SHIFTS
/* Collect correct XBAR definitions from chip file */
#include "hardware/imxrt_xbar.h"
/**************************************************************************************************************************************************
* Public Functions
**************************************************************************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
@@ -115,7 +117,7 @@ extern "C"
#define EXTERN extern
#endif
/******************************************************************************************************************************************
/****************************************************************************
* Name: imxrt_xbar_connect
*
* Description:
@@ -128,7 +130,7 @@ extern "C"
* Returned Value:
* OK on success; Negated errno on failure.
*
******************************************************************************************************************************************/
****************************************************************************/
int imxrt_xbar_connect(uint16_t mux_out, uint16_t mux_input);
arch/arm/src/kl/hardware/kl_tsi.h
+19 -16
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kl/hardware/kl_tsi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,38 +16,39 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KL_HARDWARE_KL_TSI_H
#define __ARCH_ARM_SRC_KL_HARDWARE_KL_TSI_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KL_TSI_GENCS_OFFSET 0x0000 /* General Control and Status Register */
#define KL_TSI_DATA_OFFSET 0x0004 /* SCAN control register */
#define KL_TSI_TSHD_OFFSET 0x0008 /* Pin enable register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KL_TSI_GENCS (KL_TSI_BASE+KL_TSI_GENCS_OFFSET)
#define KL_TSI_DATA (KL_TSI_BASE+KL_TSI_DATA_OFFSET)
#define KL_TSI_TSHD (KL_TSI_BASE+KL_TSI_TSHD_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* General Control and Status Register */
/* Bit 0: Reserved */
#define TSI_GENCS_CURSW (1 << 1) /* Bit 1: Current sources for oscillators swapped */
#define TSI_GENCS_EOSF (1 << 2) /* Bit 2: End of scan flag */
@@ -59,6 +60,7 @@
#define TSI_GENCS_NSCN_SHIFT (8) /* Bits 8-12: Electrode oscillator count used in a scan */
#define TSI_GENCS_NSCN_MASK (31 << TSI_GENCS_NSCN_SHIFT)
# define TSI_GENCS_NSCN_TIMES(n) (((n)-1) << TSI_GENCS_NSCN_SHIFT) /* n times per electrode,n=1..32 */
#define TSI_GENCS_PS_SHIFT (13) /* Bits 13-15: Prescaler value */
#define TSI_GENCS_PS_MASK (7 << TSI_GENCS_PS_SHIFT)
# define TSI_GENCS_PS_DIV1 (0 << TSI_GENCS_PS_SHIFT) /* Electrode oscillator / 1 */
@@ -69,6 +71,7 @@
# define TSI_GENCS_PS_DIV32 (5 << TSI_GENCS_PS_SHIFT) /* Electrode oscillator / 32 */
# define TSI_GENCS_PS_DIV64 (6 << TSI_GENCS_PS_SHIFT) /* Electrode oscillator / 64 */
# define TSI_GENCS_PS_DIV128 (7 << TSI_GENCS_PS_SHIFT) /* Electrode oscillator / 128 */
#define TSI_GENCS_EXTCHRG_SHIFT (16) /* Bits 16-18: Electrode Osc charge/discharge value */
#define TSI_GENCS_EXTCHRG_MASK (7 << TSI_GENCS_EXTCHRG_SHIFT)
# define TSI_GENCS_EXTCHRG_500NA (0 << TSI_GENCS_EXTCHRG_SHIFT)
@@ -124,16 +127,16 @@
#define TSI_THRESHLD_LTHH_SHIFT (16) /* Bits 16-31: Low threshold value */
#define TSI_THRESHLD_LTHH_MASK (0xffff << TSI_THRESHLD_LTHH_SHIFT)
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KL_HARDWARE_KL_TSI_H */
arch/arm/src/kl/kl_clockconfig.c
+16 -8
View File
@@ -93,10 +93,13 @@ void kl_pllconfig(void)
* settings in the board.h header file.
*/
regval32 = (SIM_CLKDIV1_OUTDIV1(BOARD_OUTDIV1) | SIM_CLKDIV1_OUTDIV4(BOARD_OUTDIV4));
regval32 = (SIM_CLKDIV1_OUTDIV1(BOARD_OUTDIV1) |
SIM_CLKDIV1_OUTDIV4(BOARD_OUTDIV4));
putreg32(regval32, KL_SIM_CLKDIV1);
/* System oscillator drives 32 kHz clock for various peripherals (OSC32KSEL=0) */
/* System oscillator drives 32 kHz clock for various peripherals
* (OSC32KSEL=0)
*/
regval32 = getreg32(KL_SIM_SOPT1);
regval32 &= ~(SIM_SOPT1_OSC32KSEL_MASK);
@@ -110,10 +113,12 @@ void kl_pllconfig(void)
regval32 |= SIM_SOPT2_PLLFLLSEL;
putreg32(regval32, KL_SIM_SOPT2);
regval32 = (regval32 & ~(SIM_SOPT2_TPMSRC_OCSERCLK)) | SIM_SOPT2_TPMSRC_MCGCLK;
regval32 = (regval32 & ~(SIM_SOPT2_TPMSRC_OCSERCLK)) |
SIM_SOPT2_TPMSRC_MCGCLK;
putreg32(regval32, KL_SIM_SOPT2);
/* PORTA_PCR18: ISF=0, MUX=0 */
/* PORTA_PCR19: ISF=0, MUX=0 */
regval32 = getreg32(KL_PORTA_PCR18);
@@ -125,7 +130,10 @@ void kl_pllconfig(void)
putreg32(regval32, KL_PORTA_PCR19);
/* Switch to FBE Mode */
/* OSC0_CR: ERCLKEN=0, ??=0, EREFSTEN=0, ??=0, SC2P=0, SC4P=0, SC8P=0, SC16P=0 */
/* OSC0_CR: ERCLKEN=0,
* ??=0, EREFSTEN=0, ??=0, SC2P=0, SC4P=0, SC8P=0, SC16P=0
*/
putreg8(0, KL_OSC_CR);
@@ -191,8 +199,7 @@ void kl_pllconfig(void)
/* Wait until PLL output */
while ((getreg8(KL_MCG_S) & MCG_S_CLKST_MASK) != 0x0C)
;
while ((getreg8(KL_MCG_S) & MCG_S_CLKST_MASK) != 0x0c);
}
/****************************************************************************
@@ -223,6 +230,7 @@ void kl_clockconfig(void)
* the FlexBus clock.
*/
//kl_traceconfig();
//kl_fbconfig();
/* kl_traceconfig(); */
/* kl_fbconfig(); */
}
arch/arm/src/kl/kl_pwm.h
+36 -27
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kl/kl_pwm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,27 +16,39 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KL_KINETIS_PWM_H
#define __ARCH_ARM_SRC_KL_KINETIS_PWM_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/* Check if PWM support for any channel is enabled. */
#if defined(CONFIG_KL_TPM0_PWM) || defined(CONFIG_KL_TPM1_PWM) || \
defined(CONFIG_KL_TPM2_PWM)
#include <arch/board/board.h>
#include "hardware/kl_pinmux.h"
#endif
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
****************************************************************************/
/* Configuration ************************************************************/
/* Timer devices may be used for different purposes. One special purpose is
* to generate modulated outputs for such things as motor control. If CONFIG_KL_TPMn
* is defined then the CONFIG_KL_TPMn_PWM must also be defined to indicate that
* timer "n" is intended to be used for pulsed output signal generation.
* to generate modulated outputs for such things as motor control.
* If CONFIG_KL_TPMn is defined then the CONFIG_KL_TPMn_PWM must also be
* defined to indicate that timer "n" is intended to be used for pulsed
* output signal generation.
*/
#ifndef CONFIG_KL_TPM0
@@ -54,16 +66,13 @@
#if defined(CONFIG_KL_TPM0_PWM) || defined(CONFIG_KL_TPM1_PWM) || \
defined(CONFIG_KL_TPM2_PWM)
#include <arch/board/board.h>
#include "hardware/kl_pinmux.h"
/* For each timer that is enabled for PWM usage, we need the following additional
* configuration settings:
/* For each timer that is enabled for PWM usage, we need the following
* additional configuration settings:
*
* CONFIG_KL_TPMx_CHANNEL - Specifies the timer output channel {1,..,4}
* PWM_TPMx_CHn - One of the values defined in chip/kl*_pinmap.h. In the case
* where there are multiple pin selections, the correct setting must be provided
* in the arch/board/board.h file.
* PWM_TPMx_CHn - One of the values defined in chip/kl*_pinmap.h. In the
* case where there are multiple pin selections, the correct setting must
* be provided in the arch/board/board.h file.
*/
#ifdef CONFIG_KL_TPM0_PWM
@@ -126,13 +135,13 @@
# endif
#endif
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
@@ -145,11 +154,11 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: kl_pwminitialize
*
* Description:
@@ -162,7 +171,7 @@ extern "C"
* On success, a pointer to the KL lower half PWM driver is returned.
* NULL is returned on any failure.
*
************************************************************************************/
****************************************************************************/
FAR struct pwm_lowerhalf_s *kl_pwminitialize(int timer);
arch/arm/src/lpc43xx/lpc43_timer.h
+1 -1
View File
@@ -49,7 +49,7 @@ extern "C"
#endif
/****************************************************************************
* Public Functions
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
arch/arm/src/nrf52/hardware/nrf52_nvmc.h
+9 -9
View File
@@ -1,4 +1,4 @@
/***************************************************************************************************
/****************************************************************************
* arch/arm/src/nrf52/hardware/nrf52_nvmc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,23 @@
* License for the specific language governing permissions and limitations
* under the License.
*
***************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_NVMC_H
#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_NVMC_H
/***************************************************************************************************
/****************************************************************************
* Included Files
***************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/nrf52_memorymap.h"
/***************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
***************************************************************************************************/
****************************************************************************/
/* NVMC Register Offsets ****************************************************************************/
/* NVMC Register Offsets ****************************************************/
/* Registers for the NVMC */
@@ -47,7 +47,7 @@
#define NRF52_NVMC_IHIT_OFFSET 0x548 /* I-Code cache hit counter. */
#define NRF52_NVMC_IMISS_OFFSET 0x54c /* I-Code cache miss counter */
/* NVMC Register Addresses **************************************************************************/
/* NVMC Register Addresses **************************************************/
#define NRF52_NVMC_READY (NRF52_NVMC_BASE + NRF52_NVMC_READY_OFFSET)
#define NRF52_NVMC_CONFIG (NRF52_NVMC_BASE + NRF52_NVMC_CONFIG_OFFSET)
@@ -60,7 +60,7 @@
#define NRF52_NVMC_IHIT (NRF52_NVMC_BASE + NRF52_NVMC_IHIT_OFFSET)
#define NRF52_NVMC_IMISS (NRF52_NVMC_BASE + NRF52_NVMC_IMISS_OFFSET)
/* NVMC Register Bitfield Definitions **************************************************************/
/* NVMC Register Bitfield Definitions ***************************************/
/* READY Register */
arch/arm/src/samv7/sam_systemreset.c
+2 -2
View File
@@ -37,7 +37,7 @@
#ifdef CONFIG_SAMV7_SYSTEMRESET
/****************************************************************************
* Public functions
* Public Functions
****************************************************************************/
/****************************************************************************
@@ -62,7 +62,7 @@ void up_systemreset(void)
rstmr = getreg32(SAM_RSTC_MR);
rstmr &= ~RSTC_MR_ERSTL_MASK;
rstmr &= RSTC_MR_ERSTL(CONFIG_SAMV7_EXTRESET_ERST-1) | RSTC_MR_KEY;
rstmr &= RSTC_MR_ERSTL(CONFIG_SAMV7_EXTRESET_ERST - 1) | RSTC_MR_KEY;
putreg32(rstmr, SAM_RSTC_MR);
#endif
arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h
+27 -22
View File
@@ -1,4 +1,4 @@
/********************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H
/********************************************************************************
/****************************************************************************
* Included Files
********************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -32,7 +32,8 @@
/* STM32 M0 ADC driver:
* - no injected channels
* - no offset registers
* - the F0/L0 family support one sampling time configuration for all channels
* - the F0/L0 family support one sampling time configuration for all
* channels
* - the G0 family support two sampling time configurations
*/
@@ -70,24 +71,24 @@
#undef ADC_HAVE_INJECTED
/********************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************/
****************************************************************************/
#define STM32_ADC1_OFFSET 0x0000
#define STM32_ADC2_OFFSET 0x0100
#define STM32_ADC3_OFFSET 0x0000
#define STM32_ADC4_OFFSET 0x0100
#define STM32_ADCCMN_OFFSET 0x0300
#define STM32_ADC1_OFFSET 0x0000
#define STM32_ADC2_OFFSET 0x0100
#define STM32_ADC3_OFFSET 0x0000
#define STM32_ADC4_OFFSET 0x0100
#define STM32_ADCCMN_OFFSET 0x0300
#define STM32_ADC1_BASE (STM32_ADC1_OFFSET+STM32_ADC12_BASE) /* ADC1 Master ADC */
#define STM32_ADC2_BASE (STM32_ADC2_OFFSET+STM32_ADC12_BASE) /* ADC2 Slave ADC */
#define STM32_ADC3_BASE (STM32_ADC3_OFFSET+STM32_ADC34_BASE) /* ADC3 Master ADC */
#define STM32_ADC4_BASE (STM32_ADC4_OFFSET+STM32_ADC34_BASE) /* ADC4 Slave ADC */
#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET+STM32_ADC12_BASE) /* ADC1, ADC2 common */
#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET+STM32_ADC34_BASE) /* ADC3, ADC4 common */
#define STM32_ADC1_BASE (STM32_ADC1_OFFSET+STM32_ADC12_BASE) /* ADC1 Master ADC */
#define STM32_ADC2_BASE (STM32_ADC2_OFFSET+STM32_ADC12_BASE) /* ADC2 Slave ADC */
#define STM32_ADC3_BASE (STM32_ADC3_OFFSET+STM32_ADC34_BASE) /* ADC3 Master ADC */
#define STM32_ADC4_BASE (STM32_ADC4_OFFSET+STM32_ADC34_BASE) /* ADC4 Slave ADC */
#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET+STM32_ADC12_BASE) /* ADC1, ADC2 common */
#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET+STM32_ADC34_BASE) /* ADC3, ADC4 common */
/* Register Offsets *********************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */
#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */
@@ -103,7 +104,7 @@
#define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */
/* Register Addresses *******************************************************************************/
/* Register Addresses *******************************************************/
#define STM32_ADC1_ISR (STM32_ADC1_BASE + STM32_ADC_ISR_OFFSET)
#define STM32_ADC1_IER (STM32_ADC1_BASE + STM32_ADC_IER_OFFSET)
@@ -116,9 +117,11 @@
#define STM32_ADC1_DR (STM32_ADC1_BASE + STM32_ADC_DR_OFFSET)
#define STM32_ADC1_CCR (STM32_ADC1_BASE + STM32_ADC_CCR_OFFSET)
/* Register Bitfield Definitions ************************************************/
/* Register Bitfield Definitions ********************************************/
/* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */
/* ADC interrupt and status register (ISR) and
* ADC interrupt enable register (IER)
*/
#define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */
#define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */
@@ -147,6 +150,7 @@
# define ADC_CFGR1_RES_10BIT (1 << ADC_CFGR1_RES_SHIFT) /* 13 ADCCLK clyes */
# define ADC_CFGR1_RES_8BIT (2 << ADC_CFGR1_RES_SHIFT) /* 11 ADCCLK clyes */
# define ADC_CFGR1_RES_6BIT (3 << ADC_CFGR1_RES_SHIFT) /* 9 ADCCLK clyes */
#define ADC_CFGR1_ALIGN (1 << 5) /* Bit 5: Data Alignment */
#define ADC_CFGR1_EXTSEL_SHIFT (6) /* Bits 6-8: External trigger selection */
#define ADC_CFGR1_EXTSEL_MASK (7 << ADC_CFGR1_EXTSEL_SHIFT)
@@ -164,6 +168,7 @@
# define ADC_CFGR1_EXTEN_RISING (1 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the rising edge */
# define ADC_CFGR1_EXTEN_FALLING (2 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the falling edge */
# define ADC_CFGR1_EXTEN_BOTH (3 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on both edges */
#define ADC_CFGR1_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */
#define ADC_CFGR1_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */
#define ADC_CFGR1_WAIT (1 << 14) /* Bit 14: Wait conversion mode */
arch/arm/src/stm32f0l0g0/hardware/stm32_can.h
+10 -9
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_can.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,22 +16,22 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* 3 TX mailboxes */
@@ -48,7 +48,7 @@
#define CAN_NFILTERS 14
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
/* CAN control and status registers */
@@ -121,7 +121,7 @@
#define STM32_CAN_FIR_OFFSET(f,i) (0x240 + ((f) << 3)+(((i) - 1) << 2))
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#if STM32_NCAN > 0
# define STM32_CAN1_MCR (STM32_CAN1_BASE + STM32_CAN_MCR_OFFSET)
@@ -231,7 +231,7 @@
# define STM32_CAN2_FIR(b,i) (STM32_CAN2_BASE + STM32_CAN_FIR_OFFSET(b,i))
#endif
/* Register Bitfield Definitions ****************************************************/
/* Register Bitfield Definitions ********************************************/
/* CAN master control register */
@@ -324,6 +324,7 @@
# define CAN_ESR_BDOMERROR (5 << CAN_ESR_LEC_SHIFT) /* 101: Bit dominant Error */
# define CAN_ESR_CRCERRPR (6 << CAN_ESR_LEC_SHIFT) /* 110: CRC Error */
# define CAN_ESR_SWERROR (7 << CAN_ESR_LEC_SHIFT) /* 111: Set by software */
#define CAN_ESR_TEC_SHIFT (16) /* Bits 23-16: LS byte of the 9-bit Transmit Error Counter */
#define CAN_ESR_TEC_MASK (0xff << CAN_ESR_TEC_SHIF)
#define CAN_ESR_REC_SHIFT (24) /* Bits 31-24: Receive Error Counter */
arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h
+15 -9
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,23 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define STM32_CRC_DR_OFFSET 0x0000 /* Data register */
#define STM32_CRC_IDR_OFFSET 0x0004 /* Independent Data register */
@@ -40,7 +40,7 @@
#define STM32_CRC_INIT_OFFSET 0x0010 /* Initial CRC value register */
#define STM32_CRC_POL_OFFSET 0x0014 /* CRC polynomial register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define STM32_CRC_DR (STM32_CRC_BASE + STM32_CRC_DR_OFFSET)
#define STM32_CRC_IDR (STM32_CRC_BASE + STM32_CRC_IDR_OFFSET)
@@ -48,7 +48,7 @@
#define STM32_CRC_INIT (STM32_CRC_BASE + STM32_CRC_INIT_OFFSET)
#define STM32_CRC_POL (STM32_CRC_BASE + STM32_CRC_POL_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* Register Bitfield Definitions ********************************************/
/* CRC independent data register */
@@ -63,12 +63,18 @@
# define CRC_CR_POLYSIZE_16 (1 << CRC_CR_POLYSIZE_SHIFT) /* 01: 16 bit polynomial */
# define CRC_CR_POLYSIZE_8 (2 << CRC_CR_POLYSIZE_SHIFT) /* 10: 8 bit polynomial */
# define CRC_CR_POLYSIZE_7 (3 << CRC_CR_POLYSIZE_SHIFT) /* 10: 8 bit polynomial */
#define CRC_CR_REVIN_SHIFT 5 /* Bits 5-6: These bits ontrol the reversal of the bit order of the input data */
#define CRC_CR_REVIN_MASK (3 << CRC_CR_REVIN_SHIFT)
# define CRC_CR_REVIN_NONE (0 << CRC_CR_REVIN_SHIFT) /* 00: bit order is not affected */
# define CRC_CR_REVIN_BYTE (1 << CRC_CR_REVIN_SHIFT) /* 01: reversal done by byte */
# define CRC_CR_REVIN_HWORD (2 << CRC_CR_REVIN_SHIFT) /* 10: reversal done by half-word */
# define CRC_CR_REVIN_WORD (3 << CRC_CR_REVIN_SHIFT) /* 11: reversal done by word */
#define CRC_CR_REVOUT (1 << 7) /* This bit controls the reversal of the bit order of the output data */
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H */
arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h
+9 -7
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,30 +16,30 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define STM32_CRS_CR_OFFSET 0x0000 /* CRS control register */
#define STM32_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */
#define STM32_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */
#define STM32_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define STM32_CRS_CR (STM32_CRS_BASE + STM32_CRS_CR_OFFSET)
#define STM32_CRS_CFGR (STM32_CRS_BASE + STM32_CRS_CFGR_OFFSET)
#define STM32_CRS_ISR (STM32_CRS_BASE + STM32_CRS_ISR_OFFSET)
#define STM32_CRS_ICR (STM32_CRS_BASE + STM32_CRS_ICR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* Register Bitfield Definitions ********************************************/
/* CRS control register */
@@ -69,11 +69,13 @@
# define CRS_CFGR_SYNCDIV_d32 (5 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 32 */
# define CRS_CFGR_SYNCDIV_d64 (6 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 64 */
# define CRS_CFGR_SYNCDIV_d128 (7 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 128 */
#define CRS_CFGR_SYNCSRC_SHIFT 28 /* Bits 28-29: SYNC signal source selection */
#define CRS_CFGR_SYNCSRC_MASK (3 << CRS_CFGR_SYNCSRC_SHIFT)
# define CRS_CFGR_SYNCSRC_GPIO (0 << CRS_CFGR_SYNCSRC_SHIFT) /* GPIO as SYNC signal source */
# define CRS_CFGR_SYNCSRC_LSE (1 << CRS_CFGR_SYNCSRC_SHIFT) /* LSE as SYNC signal source */
# define CRS_CFGR_SYNCSRC_USBSOF (2 << CRS_CFGR_SYNCSRC_SHIFT) /* USB SOF as SYNC signal source */
#define CRS_CFGR_SYNCPOL (1 << 31) /* SYNC polarity selection */
/* CRS interrupt and status register */
arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h
+17 -10
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,23 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */
#define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */
@@ -49,7 +49,7 @@
#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */
#define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
/* DAC */
@@ -68,9 +68,10 @@
#define STM32_DAC1_DOR2 (STM32_DAC1_BASE + STM32_DAC_DOR2_OFFSET)
#define STM32_DAC1_SR (STM32_DAC1_BASE + STM32_DAC_SR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* Register Bitfield Definitions ********************************************/
/* DAC control register */
/* These definitions may be used with the full, 32-bit register */
#define DAC_CR_EN1 (1 << 0) /* Bit 0: DAC channel 1 enable */
@@ -85,11 +86,13 @@
# define DAC_CR_TSEL1_TIM2 (4 << DAC_CR_TSEL1_SHIFT) /* Timer 2 TRGO event */
# define DAC_CR_TSEL1_EXT9 (6 << DAC_CR_TSEL1_SHIFT) /* External line9 */
# define DAC_CR_TSEL1_SW (7 << DAC_CR_TSEL1_SHIFT) /* Software trigger */
#define DAC_CR_WAVE1_SHIFT (6) /* Bits 6-7: DAC channel 1 noise/triangle wave generation */
#define DAC_CR_WAVE1_MASK (3 << DAC_CR_WAVE1_SHIFT)
# define DAC_CR_WAVE1_DISABLED (0 << DAC_CR_WAVE1_SHIFT) /* Wave generation disabled */
# define DAC_CR_WAVE1_NOISE (1 << DAC_CR_WAVE1_SHIFT) /* Noise wave generation enabled */
# define DAC_CR_WAVE1_TRIANGLE (2 << DAC_CR_WAVE1_SHIFT) /* Triangle wave generation enabled */
#define DAC_CR_MAMP1_SHIFT (8) /* Bits 8-11: DAC channel 1 mask/amplitude selector */
#define DAC_CR_MAMP1_MASK (15 << DAC_CR_MAMP1_SHIFT)
# define DAC_CR_MAMP1_AMP1 (0 << DAC_CR_MAMP1_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */
@@ -104,13 +107,14 @@
# define DAC_CR_MAMP1_AMP1023 (9 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */
# define DAC_CR_MAMP1_AMP2047 (10 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */
# define DAC_CR_MAMP1_AMP4095 (11 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */
#define DAC_CR_DMAEN1 (1 << 12) /* Bit 12: DAC channel 1 DMA enable */
#define DAC_CR_DMAUDRIE1 (1 << 13) /* Bit 13: DAC channel 1 DMA Underrun Interrupt enable */
#define DAC_CR_EN2 (1 << 16) /* Bit 16: DAC channel 2 enable */
#define DAC_CR_BOFF2 (1 << 17) /* Bit 17: DAC channel 2 output buffer disable */
#define DAC_CR_TEN2 (1 << 18) /* Bit 18: DAC channel 2 trigger enable */
#define DAC_CR_TSEL2_SHIFT (19) /* Bits 19-21: DAC channel 2 trigger selection */
#define DAC_CR_TSEL2_SHIFT (19) /* Bits 19-21: DAC channel 2 trigger selection */
#define DAC_CR_TSEL2_MASK (7 << DAC_CR_TSEL2_SHIFT)
# define DAC_CR_TSEL2_TIM6 (0 << DAC_CR_TSEL2_SHIFT) /* Timer 6 TRGO event */
# define DAC_CR_TSEL2_TIM3 (1 << DAC_CR_TSEL2_SHIFT) /* Timer 3 TRGO event */
@@ -119,11 +123,13 @@
# define DAC_CR_TSEL2_TIM2 (4 << DAC_CR_TSEL2_SHIFT) /* Timer 2 TRGO event */
# define DAC_CR_TSEL2_EXT9 (6 << DAC_CR_TSEL2_SHIFT) /* External line9 */
# define DAC_CR_TSEL2_SW (7 << DAC_CR_TSEL2_SHIFT) /* Software trigger */
#define DAC_CR_WAVE2_SHIFT (22) /* Bit 22-23: DAC channel 2 noise/triangle wave generation enable */
#define DAC_CR_WAVE2_MASK (3 << DAC_CR_WAVE2_SHIFT)
# define DAC_CR_WAVE2_DISABLED (0 << DAC_CR_WAVE2_SHIFT) /* Wave generation disabled */
# define DAC_CR_WAVE2_NOISE (1 << DAC_CR_WAVE2_SHIFT) /* Noise wave generation enabled */
# define DAC_CR_WAVE2_TRIANGLE (2 << DAC_CR_WAVE2_SHIFT) /* Triangle wave generation enabled */
#define DAC_CR_MAMP2_SHIFT (24) /* Bit 24-27: DAC channel 2 mask/amplitude selector */
#define DAC_CR_MAMP2_MASK (15 << DAC_CR_MAMP2_SHIFT)
# define DAC_CR_MAMP2_AMP1 (0 << DAC_CR_MAMP2_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */
@@ -138,6 +144,7 @@
# define DAC_CR_MAMP2_AMP1023 (9 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */
# define DAC_CR_MAMP2_AMP2047 (10 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */
# define DAC_CR_MAMP2_AMP4095 (11 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */
#define DAC_CR_DMAEN2 (1 << 28) /* Bit 28: DAC channel 2 DMA enable */
#define DAC_CR_DMAUDRIE2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun interrupt enable */
arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h
+10 -7
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,16 +16,16 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */
#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */
@@ -39,7 +39,7 @@
#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */
#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#if STM32_NI2C > 0
# define STM32_I2C1_CR1 (STM32_I2C1_BASE + STM32_I2C_CR1_OFFSET)
@@ -69,7 +69,7 @@
# define STM32_I2C2_TXDR (STM32_I2C2_BASE + STM32_I2C_TXDR_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/
/* Register Bitfield Definitions ********************************************/
/* Control register 1 */
@@ -85,6 +85,7 @@
#define I2C_CR1_DNF_MASK (15 << I2C_CR1_DNF_SHIFT)
# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT)
# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */
#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */
#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */
#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */
@@ -138,6 +139,7 @@
# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */
# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */
# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */
#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */
/* Timing register */
@@ -175,6 +177,7 @@
#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */
/* Interrupt and Status register and interrupt clear register */
/* Common interrupt bits */
#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */
arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h
+12 -8
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,16 +16,16 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */
#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */
@@ -51,7 +51,7 @@
#define STM32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */
#define STM32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define STM32_RTC_TR (STM32_RTC_BASE + STM32_RTC_TR_OFFSET)
#define STM32_RTC_DR (STM32_RTC_BASE + STM32_RTC_DR_OFFSET)
@@ -79,7 +79,7 @@
#define STM32_RTC_BKCOUNT 5
/* Register Bitfield Definitions ****************************************************/
/* Register Bitfield Definitions ********************************************/
/* RTC time register */
@@ -132,6 +132,7 @@
# define RTC_CR_WUCKSEL_RTCDIV2 (3 << RTC_CR_WUCKSEL_SHIFT) /* 011: RTC/2 clock is selected */
# define RTC_CR_WUCKSEL_CKSPRE (4 << RTC_CR_WUCKSEL_SHIFT) /* 10x: ck_spre clock is selected */
# define RTC_CR_WUCKSEL_CKSPREADD (6 << RTC_CR_WUCKSEL_SHIFT) /* 11x: ck_spr clock and 216 added WUT counter */
#define RTC_CR_TSEDGE (1 << 3) /* Bit 3: Timestamp event active edge */
#define RTC_CR_REFCKON (1 << 4) /* Bit 4: Reference clock detection enable (50 or 60 Hz) */
#define RTC_CR_BYPSHAD (1 << 5) /* Bit 5: Bypass the shadow registers */
@@ -153,6 +154,7 @@
# define RTC_CR_OSEL_ALRMA (1 << RTC_CR_OSEL_SHIFT) /* 01: Alarm A output enabled */
# define RTC_CR_OSEL_ALRMB (2 << RTC_CR_OSEL_SHIFT) /* 10: Alarm B output enabled */
# define RTC_CR_OSEL_WUT (3 << RTC_CR_OSEL_SHIFT) /* 11: Wakeup output enabled */
#define RTC_CR_COE (1 << 23) /* Bit 23: Calibration output enable */
/* RTC initialization and status register */
@@ -272,7 +274,7 @@
#define RTC_TAFCR_TAMP3E (1 << 5) /* Bit 5: RTC_TAMP3 detection enable */
#define RTC_TAFCR_TAMP3TRG (1 << 6) /* Bit 6: Active level for RTC_TAMP3 input */
#define RTC_TAFCR_TAMPTS (1 << 7) /* Bit 7: Activate timestamp on tamper detection event */
#define RTC_TAFCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */
#define RTC_TAFCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */
#define RTC_TAFCR_TAMPFREQ_MASK (7 << RTC_TAFCR_TAMPFREQ_SHIFT)
# define RTC_TAFCR_TAMPFREQ_DIV32768 (0 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 32768 (1 Hz) */
# define RTC_TAFCR_TAMPFREQ_DIV16384 (1 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 16384 (2 Hz) */
@@ -282,6 +284,7 @@
# define RTC_TAFCR_TAMPFREQ_DIV1024 (5 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 1024 (32 Hz) */
# define RTC_TAFCR_TAMPFREQ_DIV512 (6 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 512 (64 Hz) */
# define RTC_TAFCR_TAMPFREQ_DIV256 (7 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 256 (128 Hz) */
#define RTC_TAFCR_TAMPFLT_SHIFT (11) /* Bits 11-12: RTC_TAMPx filter count */
#define RTC_TAFCR_TAMPFLT_MASK (3 << RTC_TAFCR_TAMPFLT_SHIFT)
#define RTC_TAFCR_TAMPPRCH_SHIFT (13) /* Bits 13-14: RTC_TAMPx precharge duration */
@@ -290,6 +293,7 @@
# define RTC_TAFCR_TAMPPRCH_2CYCLES (1 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 2 RTCCLK cycles */
# define RTC_TAFCR_TAMPPRCH_4CYCLES (2 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 4 RTCCLK cycles */
# define RTC_TAFCR_TAMPPRCH_5CYCLES (3 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 8 RTCCLK cycles */
#define RTC_TAFCR_TAMPPUDIS (1 << 15) /* Bit 15: RTC_TAMPx pull-up disable */
#define RTC_TAFCR_PC13VALUE (1 << 18) /* Bit 18: RTC_ALARM output type/PC13 value */
#define RTC_TAFCR_PC13MODE (1 << 19) /* Bit 19: PC13 mode */
arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h
+10 -9
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,23 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_UART_V1_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_UART_V1_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */
#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */
@@ -46,7 +46,7 @@
#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */
#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#if STM32_NUSART > 0
# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET)
@@ -118,7 +118,7 @@
# define STM32_USART5_TDR (STM32_USART5_BASE + STM32_USART_TDR_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/
/* Register Bitfield Definitions ********************************************/
/* Control register 1 */
@@ -216,6 +216,7 @@
#define USART_CR3_WUS_ADDRESS (0 << USART_CR3_WUS_SHIFT) /* 00: WUF active on address match */
#define USART_CR3_WUS_START (2 << USART_CR3_WUS_SHIFT) /* 10: WUF active on Start bit detection */
#define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* 11: WUF active on RXNE */
#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */
/* Baud Rate Register */
arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h
+10 -9
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */
#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */
@@ -45,7 +45,7 @@
#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */
#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define STM32_IWDG_KR (STM32_IWDG_BASE + STM32_IWDG_KR_OFFSET)
#define STM32_IWDG_PR (STM32_IWDG_BASE + STM32_IWDG_PR_OFFSET)
@@ -57,7 +57,7 @@
#define STM32_WWDG_CFR (STM32_WWDG_BASE + STM32_WWDG_CFR_OFFSET)
#define STM32_WWDG_SR (STM32_WWDG_BASE + STM32_WWDG_SR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* Register Bitfield Definitions ********************************************/
/* Key register (32-bit) */
@@ -117,6 +117,7 @@
# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */
# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */
# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */
#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */
/* Status register (32-bit) */
arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h
+18 -16
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,16 +16,16 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F03X_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F03X_MEMORYMAP_H
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* ST32F05XF07X Address Blocks ******************************************************/
/* ST32F05XF07X Address Blocks **********************************************/
#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
@@ -36,7 +36,7 @@
#define STM32_REGION_MASK 0xf0000000
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
/* Code Base Addresses **************************************************************/
/* Code Base Addresses ******************************************************/
#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
/* 0x00100000-0x07ffffff: Reserved */
@@ -49,7 +49,7 @@
#define STM32_OPTION_BASE 0x1ffff800 /* 0x1fffc000-0x1fffc007: Option bytes */
/* 0x1fffc008-0x1fffffff: Reserved */
/* System Memory Addresses **********************************************************/
/* System Memory Addresses **************************************************/
#define STM32_SYSMEM_UID 0x1ffff7ac /* The 96-bit unique device identifier */
#define STM32_SYSMEM_FSIZE 0x1ffff7cc /* This bitfield indicates the size of
@@ -58,7 +58,7 @@
* to 64 Kbytes
*/
/* Peripheral Base Addresses ********************************************************/
/* Peripheral Base Addresses ************************************************/
#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40009fff: APB1 */
/* 0x4000a000-0x4000ffff: Reserved */
@@ -70,9 +70,10 @@
/* 0x48001800-0x4fffFfff: Reserved */
#define STM32_AHB3_BASE 0x50000000 /* 0x50000000-0x500007ff: AHB3 */
/* APB1 Base Addresses **************************************************************/
/* APB1 Base Addresses ******************************************************/
/* 0x40000000-0x400003ff Reserved */
/* 0x40000000-0x400003ff Reserved */
#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */
#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */
#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */
@@ -91,7 +92,7 @@
#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */
/* 0x40007400-0x400077ff Reserved */
/* APB2 Base Addresses **************************************************************/
/* APB2 Base Addresses ******************************************************/
#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103ff SYSCFG + COMP + OPAMP */
#define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107ff EXTI */
@@ -107,7 +108,7 @@
#define STM32_TIM17_BASE 0x40014800 /* 0x40014800-0x40014bff TIM17 */
#define STM32_DBGMCU_BASE 0x40015800 /* 0x40015800-0x40015bff DBGMCU */
/* AHB1 Base Addresses **************************************************************/
/* AHB1 Base Addresses ******************************************************/
#define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */
/* 0x40020400-0x400207ff: Reserved */
@@ -116,7 +117,7 @@
#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */
/* 0x40024000-0x400243ff: Reserved */
/* AHB2 Base Addresses **************************************************************/
/* AHB2 Base Addresses ******************************************************/
#define STM32_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */
#define STM32_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */
@@ -125,9 +126,10 @@
/* 0x48001000-0x480013ff: Reserved */
#define STM32_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */
/* Cortex-M4 Base Addresses *********************************************************/
/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this
* address range
/* Cortex-M4 Base Addresses *************************************************/
/* Other registers --
* see armv7-m/nvic.h for standard Cortex-M4 registers in this address range
*/
#define STM32_SCS_BASE 0xe000e000
arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h
+16 -14
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,39 +16,41 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_PINMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "stm32_gpio.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Alternate Pin Functions.
*
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
* Drivers, however, will use the pin selection without the numeric suffix.
* Alternative pin selections are provided with a numeric suffix like _1, _2,
* etc. Drivers, however, will use the pin selection without the numeric
* suffix.
* Additional definitions are required in the board.h file. For example, if
* CAN1_RX connects vis PD0 on some board, then the following definition should
* appear in the board.h header file for that board:
* CAN1_RX connects vis PD0 on some board, then the following definition
* should appear in the board.h header file for that board:
*
* #define GPIO_CAN1_RX GPIO_CAN1_RX_1
*
* The driver will then automatically configure PD0 as the CAN1 RX pin.
*/
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in this file.
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as
* frequency, open-drain/push-pull, and pull-up/down! Just the basics are
* defined for most pins in this file.
*/
/* ADC 1 */
arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h
+16 -15
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,16 +16,16 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* ST32F05XF07X Address Blocks ******************************************************/
/* ST32F05XF07X Address Blocks **********************************************/
#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
@@ -36,7 +36,7 @@
#define STM32_REGION_MASK 0xf0000000
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
/* Code Base Addresses **************************************************************/
/* Code Base Addresses ******************************************************/
#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
/* 0x00100000-0x07ffffff: Reserved */
@@ -49,7 +49,7 @@
#define STM32_OPTION_BASE 0x1ffff800 /* 0x1fffc000-0x1fffc007: Option bytes */
/* 0x1fffc008-0x1fffffff: Reserved */
/* System Memory Addresses **********************************************************/
/* System Memory Addresses **************************************************/
#define STM32_SYSMEM_UID 0x1ffff7ac /* The 96-bit unique device identifier */
#define STM32_SYSMEM_FSIZE 0x1ffff7cc /* This bitfield indicates the size of
@@ -58,7 +58,7 @@
* to 64 Kbytes
*/
/* Peripheral Base Addresses ********************************************************/
/* Peripheral Base Addresses ************************************************/
#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40009fff: APB1 */
/* 0x4000a000-0x4000ffff: Reserved */
@@ -70,7 +70,7 @@
/* 0x48001800-0x4fffFfff: Reserved */
#define STM32_AHB3_BASE 0x50000000 /* 0x50000000-0x500007ff: AHB3 */
/* APB1 Base Addresses **************************************************************/
/* APB1 Base Addresses ******************************************************/
#define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff TIM2 */
#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */
@@ -96,7 +96,7 @@
#define STM32_DAC1_BASE 0x40007400 /* 0x40007400-0x400077ff DAC 1 */
#define STM32_CEC_BASE 0x40007800 /* 0x40007800-0x40007bff HDMI CEC */
/* APB2 Base Addresses **************************************************************/
/* APB2 Base Addresses ******************************************************/
#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103ff SYSCFG + COMP + OPAMP */
#define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107ff EXTI */
@@ -112,7 +112,7 @@
#define STM32_TIM17_BASE 0x40014800 /* 0x40014800-0x40014bff TIM17 */
#define STM32_DBGMCU_BASE 0x40015800 /* 0x40015800-0x40015bff DBGMCU */
/* AHB1 Base Addresses **************************************************************/
/* AHB1 Base Addresses ******************************************************/
#define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */
#define STM32_DMA2_BASE 0x40020400 /* 0x40020400-0x400207ff: DMA2 */
@@ -121,7 +121,7 @@
#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */
#define STM32_TSC_BASE 0x40024000 /* 0x40024000-0x400243ff: TSC */
/* AHB2 Base Addresses **************************************************************/
/* AHB2 Base Addresses ******************************************************/
#define STM32_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */
#define STM32_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */
@@ -130,9 +130,10 @@
#define STM32_GPIOE_BASE 0x48001000 /* 0x48001000-0x480013ff: GPIO Port E */
#define STM32_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */
/* Cortex-M4 Base Addresses *********************************************************/
/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this
* address range
/* Cortex-M4 Base Addresses *************************************************/
/* Other registers --
* see armv7-m/nvic.h for standard Cortex-M4 registers in this address range
*/
#define STM32_SCS_BASE 0xe000e000
arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h
+16 -14
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,39 +16,41 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "stm32_gpio.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Alternate Pin Functions.
*
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
* Drivers, however, will use the pin selection without the numeric suffix.
* Alternative pin selections are provided with a numeric suffix like _1, _2,
* etc. Drivers, however, will use the pin selection without the numeric
* suffix.
* Additional definitions are required in the board.h file. For example, if
* CAN1_RX connects vis PD0 on some board, then the following definition should
* appear in the board.h header file for that board:
* CAN1_RX connects vis PD0 on some board, then the following definition
* should appear in the board.h header file for that board:
*
* #define GPIO_CAN1_RX GPIO_CAN1_RX_1
*
* The driver will then automatically configure PD0 as the CAN1 RX pin.
*/
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in this file.
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as
* frequency, open-drain/push-pull, and pull-up/down! Just the basics are
* defined for most pins in this file.
*/
/* ADC 1 */
arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h
+16 -15
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,39 +16,40 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "stm32_gpio.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Alternate Pin Functions.
*
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
* Drivers, however, will use the pin selection without the numeric suffix.
* Additional definitions are required in the board.h file. For example, if
* CAN1_RX connects vis PD0 on some board, then the following definition should
* appear in the board.h header file for that board:
* Alternative pin selections are provided with a numeric suffix like _1, _2,
* etc. Drivers, however, will use the pin selection without the numeric
* suffix. Additional definitions are required in the board.h file. For
* example, if CAN1_RX connects vis PD0 on some board, then the following
* definition should appear in the board.h header file for that board:
*
* #define GPIO_CAN1_RX GPIO_CAN1_RX_1
*
* The driver will then automatically configure PD0 as the CAN1 RX pin.
*/
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in this file.
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as
* frequency, open-drain/push-pull, and pull-up/down!
* Just the basics are defined for most pins in this file.
*/
/* ADC 1 */
arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h
+11 -11
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,28 +16,28 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
#define STM32_NEXTI 31
#define STM32_EXTI_MASK 0xffffffff
#define STM32_EXTI_BIT(n) (1 << (n))
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define STM32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */
#define STM32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */
@@ -46,7 +46,7 @@
#define STM32_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */
#define STM32_EXTI_PR_OFFSET 0x0014 /* Pending register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define STM32_EXTI_IMR (STM32_EXTI_BASE + STM32_EXTI_IMR_OFFSET)
#define STM32_EXTI_EMR (STM32_EXTI_BASE + STM32_EXTI_EMR_OFFSET)
@@ -55,7 +55,7 @@
#define STM32_EXTI_SWIER (STM32_EXTI_BASE + STM32_EXTI_SWIER_OFFSET)
#define STM32_EXTI_PR (STM32_EXTI_BASE + STM32_EXTI_PR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* Register Bitfield Definitions ********************************************/
/* EXTI lines > 15 are associated with internal devices: */
@@ -79,13 +79,13 @@
/* Interrupt mask register */
#define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Interrupt request from line x is not masked */
#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
#define EXTI_IMR_MASK STM32_EXTI_MASK
/* Event mask register */
#define EXTI_EMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Event request from line x is not mask */
#define EXTI_EMR_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
#define EXTI_EMR_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
#define EXTI_EMR_MASK STM32_EXTI_MASK
/* Rising Trigger selection register */
arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h
+10 -9
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,36 +16,36 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
#undef HAVE_PWR_WKUP2
#undef HAVE_PWR_WKUP3
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define STM32_PWR_CR_OFFSET 0x0000 /* Power control register */
#define STM32_PWR_CSR_OFFSET 0x0004 /* Power control/status register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define STM32_PWR_CR (STM32_PWR_BASE + STM32_PWR_CR_OFFSET)
#define STM32_PWR_CSR (STM32_PWR_BASE + STM32_PWR_CSR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* Register Bitfield Definitions ********************************************/
/* Power control register */
@@ -64,6 +64,7 @@
# define PWR_CR_2p7V (5 << PWR_CR_PLS_SHIFT) /* 101: 2.7V */
# define PWR_CR_2p8V (6 << PWR_CR_PLS_SHIFT) /* 110: 2.8V */
# define PWR_CR_2p9V (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */
#define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */
/* Power control/status register */
arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h
+24 -12
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,16 +16,16 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */
#define STM32_RCC_CFGR_OFFSET 0x0004 /* Clock configuration register */
@@ -42,7 +42,7 @@
#define STM32_RCC_CFGR3_OFFSET 0x0030 /* Clock configuration register 3 */
#define STM32_RCC_CR2_OFFSET 0x0034 /* Clock control register 2 */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
@@ -59,7 +59,7 @@
#define STM32_RCC_CFGR3 (STM32_RCC_BASE+STM32_RCC_CFGR3_OFFSET)
#define STM32_RCC_CR2 (STM32_RCC_BASE+STM32_RCC_CR2_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* Register Bitfield Definitions ********************************************/
/* Clock control register */
@@ -84,23 +84,26 @@
# define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */
# define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */
# define RCC_CFGR_SW_HSI48 (3 << RCC_CFGR_SW_SHIFT) /* 11: HSI48 selected as system clock */
#define RCC_CFGR_SWS_SHIFT (2) /* Bits 3-2: System Clock Switch Status */
#define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT)
# define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */
# define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */
# define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */
# define RCC_CFGR_SWS_HSI48 (3 << RCC_CFGR_SWS_SHIFT) /* 11: HSI48 used as system clock */
#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 7-4: AHB prescaler */
#define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT)
# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */
# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */
# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */
# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */
# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */
# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */
# define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */
# define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */
# define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */
# define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */
# define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */
# define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */
#define RCC_CFGR_PPRE1_SHIFT (8) /* Bits 10-8: APB Low speed prescaler (APB1) */
#define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT)
# define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */
@@ -108,7 +111,11 @@
# define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */
# define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */
# define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */
/* Bits 13-11: Reserve. Keep the reset value */
/* Bits 13-11: Reserve.
* Keep the reset value
*/
#define RCC_CFGR_ADCPRE (1 << 14) /* Bit 14: ADC prescaler, Obsolete use ADC_CFGR2 */
#define RCC_CFGR_PLLSRC_SHIFT (15) /* Bit 15: PLL input clock source */
#define RCC_CFGR_PLLSRC_MASK (3 << RCC_CFGR_PLLSRC_SHIFT)
@@ -116,6 +123,7 @@
# define RCC_CFGR_PLLSRC_HS1_PREDIV (1 << RCC_CFGR_PLLSRC_SHIFT) /* 01: HSE/PREDIV as PLL input clock */
# define RCC_CFGR_PLLSRC_HSE_PREDIV (2 << RCC_CFGR_PLLSRC_SHIFT) /* 10: HSE/PREDIV as PLL input clock */
# define RCC_CFGR_PLLSRC_HSI48_PREDIV (3 << RCC_CFGR_PLLSRC_SHIFT) /* 11: HSI48/PREDIV as PLL input clock */
#define RCC_CFGR_PLLXTPRE_MASK (1 << 17) /* Bit 17: HSE divider for PLL entry */
# define RCC_CFGR_PLLXTPRE_DIV1 (0 << 17) /* 0=No divistion */
# define RCC_CFGR_PLLXTPRE_DIV2 (1 << 17) /* 1=Divide by two */
@@ -136,7 +144,9 @@
# define RCC_CFGR_PLLMUL_CLKx14 (12 << RCC_CFGR_PLLMUL_SHIFT) /* 1100: PLL input clock x 14 */
# define RCC_CFGR_PLLMUL_CLKx15 (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1101: PLL input clock x 15 */
# define RCC_CFGR_PLLMUL_CLKx16 (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */
/* Bit 22-23: Reserved */
#define RCC_CFGR_MCO_SHIFT (24) /* Bits 27-24: Microcontroller Clock Output */
#define RCC_CFGR_MCO_MASK (15 << RCC_CFGR_MCO_SHIFT)
# define RCC_CFGR_NOCLK (0 << RCC_CFGR_MCO_SHIFT) /* 0000: No clock */
@@ -161,7 +171,6 @@
# define RCC_CFGR_MCOPRE_DIV64 (6 << RCC_CFGR_MCOPRE_SHIFT) /* 110: MCO is divided by 64 */
# define RCC_CFGR_MCOPRE_DIV128 (7 << RCC_CFGR_MCOPRE_SHIFT) /* 111: MCO is divided by 128 */
/* Clock interrupt register */
#define RCC_CIR_LSIRDYF (1 << 0) /* Bit 0: LSI Ready Interrupt flag */
@@ -289,6 +298,7 @@
# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */
# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */
# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */
#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */
#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */
@@ -345,6 +355,7 @@
# define RCC_CFGR3_USART1SW_SYSCLK (1 << RCC_CFGR3_USART1SW_SHIFT) /* SYSCLK is USART1 clock */
# define RCC_CFGR3_USART1SW_LSE (2 << RCC_CFGR3_USART1SW_SHIFT) /* LSE is USART1 clock */
# define RCC_CFGR3_USART1SW_HSI (3 << RCC_CFGR3_USART1SW_SHIFT) /* HSI is USART1 clock */
#define RCC_CFGR3_CECSW (1 << 6) /* Bit 6: HDMI CEC clock source selection */
#define RCC_CFGR3_USBSW (1 << 7) /* Bit 7: USB clock source selection */
#define RCC_CFGR3_CLK48_HSI48 0
@@ -356,6 +367,7 @@
# define RCC_CFGR3_USART2SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT) /* SYSCLK is USART2 clock */
# define RCC_CFGR3_USART2SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT) /* LSE is USART2 clock */
# define RCC_CFGR3_USART2SW_HSI (3 << RCC_CFGR3_USART2SW_SHIFT) /* HSI is USART2 clock */
#define RCC_CFGR3_USART3SW_SHIFT (18) /* Bits 18-19: USART3 clock source selection */
#define RCC_CFGR3_USART3SW_MASK (3 << RCC_CFGR3_USART3SW_SHIFT)
# define RCC_CFGR3_USART3SW_PCLK (0 << RCC_CFGR3_USART3SW_SHIFT) /* PCLK is USART3 clock source */
arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h
+13 -9
View File
@@ -1,4 +1,4 @@
/****************************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,26 +16,28 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H
/****************************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_SYSCFG_CFGR1_OFFSET 0x0000 /* SYSCFG configuration register 1 */
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
@@ -73,7 +75,7 @@
#define STM32_SYSCFG_ITLINE29_OFFSET 0x00f4 /* SYSCFG interrupt line 29 status register (STM32F09x) */
#define STM32_SYSCFG_ITLINE30_OFFSET 0x00f8 /* SYSCFG interrupt line 30 status register (STM32F09x) */
/* Register Addresses *******************************************************************************/
/* Register Addresses *******************************************************/
#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET)
@@ -117,7 +119,7 @@
#define STM32_SYSCFG_ITLINE29 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE29_OFFSET)
#define STM32_SYSCFG_ITLINE30 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE30_OFFSET)
/* Register Bitfield Definitions ********************************************************************/
/* Register Bitfield Definitions ********************************************/
/* SYSCFG memory remap register */
@@ -126,12 +128,14 @@
# define SYSCFG_CFGR1_MEMMODE_FLASH (0 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 00: Main Flash at 0x00000000 */
# define SYSCFG_CFGR1_MEMMODE_SYSTEM (1 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 01: System Flash at 0x00000000 */
# define SYSCFG_CFGR1_MEMMODE_SRAM (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 11: Embedded SRAM at 0x00000000 */
#define SYSCFG_CFGR1_PA11_PA12_RMP (1 << 4) /* Bit 4: PA11 and PA12 remapping bit for small packages */
#define SYSCFG_CFGR1_IRMOD_SHIFT (6) /* Bits 6-7: IR Modulation Envelope signal selection */
#define SYSCFG_CFGR1_IRMOD_MASK (3 << SYSCFG_CFGR1_IRMOD_SHIFT)
# define SYSCFG_CFGR1_IRMOD_TIM16 (0 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 00: TIM16 selected */
# define SYSCFG_CFGR1_IRMOD_USART1 (1 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 01: USART1 selected */
# define SYSCFG_CFGR1_IRMOD_USART4 (2 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 10: USART1 selected */
#define SYSCFG_CFGR1_ADC_DMARMP (1 << 8) /* Bit 8: ADC DMA remapping bit. Only STM32F03x/F04x/F05x/F07x */
#define SYSCFG_CFGR1_USART1_TXDMARMP (1 << 9) /* Bit 9: USART1_TX_DMA request remapping bit. Only STM32F03x/F04x/F05x/F07x */
#define SYSCFG_CFGR1_USART1_RXDMARMP (1 << 10) /* Bit 10: USART1_TX_DMA request remapping bit. Only STM32F03x/F04x/F05x/F07x */
arch/arm/src/stm32f0l0g0/stm32_gpio.c
+15 -11
View File
@@ -47,6 +47,7 @@
/****************************************************************************
* Public Data
****************************************************************************/
/* Base addresses for each GPIO block */
const uint32_t g_gpiobase[STM32_NPORTS] =
@@ -58,7 +59,7 @@ const uint32_t g_gpiobase[STM32_NPORTS] =
STM32_GPIOB_BASE, /* Two GPIO ports, GPIOA-B */
#endif
#if STM32_NPORTS > 2
STM32_GPIOC_BASE, /* Three GPIO ports, GPIOA-C*/
STM32_GPIOC_BASE, /* Three GPIO ports, GPIOA-C */
#endif
#if STM32_NPORTS > 3
STM32_GPIOD_BASE, /* Four GPIO ports, GPIOA-D */
@@ -154,7 +155,8 @@ int stm32_configgpio(uint32_t cfgset)
break;
case GPIO_OUTPUT: /* General purpose output mode */
stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */
stm32_gpiowrite(cfgset,
(cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */
pinmode = GPIO_MODER_OUTPUT;
break;
@@ -298,7 +300,9 @@ int stm32_configgpio(uint32_t cfgset)
putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET);
/* Otherwise, it is an input pin. Should it configured as an EXTI interrupt? */
/* Otherwise, it is an input pin.
* Should it configured as an EXTI interrupt?
*/
if ((cfgset & GPIO_EXTI) != 0)
{
@@ -338,14 +342,15 @@ int stm32_configgpio(uint32_t cfgset)
* Name: stm32_unconfiggpio
*
* Description:
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set it
* into default HiZ state (and possibly mark it's unused) and unlock it whether
* it was previsouly selected as alternative function (GPIO_ALT|GPIO_CNF_AFPP|...).
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set
* it into default HiZ state (and possibly mark it's unused) and unlock it
* whether it was previsouly selected as alternative function
* (GPIO_ALT|GPIO_CNF_AFPP|...).
*
* This is a safety function and prevents hardware from schocks, as unexpected
* write to the Timer Channel Output GPIO to fixed '1' or '0' while it should
* operate in PWM mode could produce excessive on-board currents and trigger
* over-current/alarm function.
* This is a safety function and prevents hardware from schocks, as
* unexpected write to the Timer Channel Output GPIO to fixed '1' or '0'
* while it should operate in PWM mode could produce excessive on-board
* currents and trigger over-current/alarm function.
*
* Returned Value:
* OK on success
@@ -404,7 +409,6 @@ void stm32_gpiowrite(uint32_t pinset, bool value)
}
putreg32(bit, base + STM32_GPIO_BSRR_OFFSET);
}
}
arch/arm/src/stm32f0l0g0/stm32_hsi48.h
+9 -9
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/stm32_hsi48.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,22 +16,22 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#ifdef CONFIG_STM32F0L0G0_HAVE_HSI48
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
enum syncsrc_e
{
@@ -41,9 +41,9 @@ enum syncsrc_e
SYNCSRC_USB, /* USB SOF selected as SYNC signal source */
};
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_enable_hsi48
arch/arm/src/stm32f0l0g0/stm32_irq.c
+1 -1
View File
@@ -35,7 +35,7 @@
#include "arm_arch.h"
#include "arm_internal.h"
//#include "stm32_irq.h"
/* #include "stm32_irq.h" */
/****************************************************************************
* Pre-processor Definitions
arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c
+9 -5
View File
@@ -199,7 +199,7 @@
# define STM32_USARTDIV16 \
((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
/* Use oversamply by 8 only if the divisor is small. But what is small? */
/* Use oversamply by 8 only if the divisor is small. But what is small? */
# if STM32_USARTDIV8 > 100
# define STM32_BRR_VALUE STM32_USARTDIV16
@@ -228,9 +228,11 @@ void arm_lowputc(char ch)
#ifdef HAVE_CONSOLE
/* Wait until the TX data register is empty */
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0);
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) &
USART_ISR_TXE) == 0);
#ifdef STM32_CONSOLE_RS485_DIR
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY);
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR,
STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
/* Then send the character */
@@ -238,8 +240,10 @@ void arm_lowputc(char ch)
putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET);
#ifdef STM32_CONSOLE_RS485_DIR
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0);
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) &
USART_ISR_TC) == 0);
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR,
!STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
#endif /* HAVE_CONSOLE */
arch/arm/src/stm32f0l0g0/stm32_serial.c
+4 -4
View File
@@ -25,10 +25,6 @@
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/* This file is only a thin shell that includes the correct serial
* implementation for the selected STM32 IP core:
* - STM32 UART IP version 1 - F0, L0
@@ -42,3 +38,7 @@
#else
# error "Unsupported STM32 M0 serial"
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
arch/arm/src/stm32f0l0g0/stm32_timerisr.c
+4 -2
View File
@@ -137,8 +137,10 @@ void up_timer_initialize(void)
*/
#ifdef CONFIG_STM32F0L0G0_SYSTICK_CORECLK
putreg32((SYSTICK_CSR_CLKSOURCE | SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE),
ARMV6M_SYSTICK_CSR);
putreg32((SYSTICK_CSR_CLKSOURCE |
SYSTICK_CSR_TICKINT |
SYSTICK_CSR_ENABLE),
ARMV6M_SYSTICK_CSR);
#else
putreg32((SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), ARMV6M_SYSTICK_CSR);
#endif
arch/arm/src/stm32f0l0g0/stm32_uart.h
+23 -20
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f0l0g0/stm32_uart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -31,9 +31,10 @@
#include "hardware/stm32_uart.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Make sure that we have not enabled more U[S]ARTs than are supported by the
* device.
*/
@@ -284,7 +285,9 @@
# undef HAVE_CONSOLE
#endif
/* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX configuration */
/* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX
* configuration
*/
#if !defined(HAVE_SERIALDRIVER) || !defined(CONFIG_ARCH_DMA)
# undef CONFIG_USART1_RXDMA
@@ -398,13 +401,13 @@
# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE)
#endif
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
@@ -417,22 +420,22 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: stm32_serial_dma_poll
*
* Description:
* Must be called periodically if any STM32 USART is configured for DMA. The DMA
* callback is triggered for each fifo size/2 bytes, but this can result in some
* bytes being transferred but not collected if the incoming data is not a whole
* multiple of half the FIFO size.
* Must be called periodically if any STM32 USART is configured for DMA.
* The DMA callback is triggered for each fifo size/2 bytes, but this can
* result in some bytes being transferred but not collected if the incoming
* data is not a whole multiple of half the FIFO size.
*
* May be safely called from either interrupt or thread context.
*
************************************************************************************/
****************************************************************************/
#ifdef SERIAL_HAVE_RXDMA
void stm32_serial_dma_poll(void);
arch/arm/src/stm32f0l0g0/stm32f0_rcc.c
+8 -4
View File
@@ -79,10 +79,11 @@ static inline void rcc_enableio(void)
uint32_t regval = 0;
/* Enable basic peripheral support */
/* Enable all GPIO modules */
regval = getreg32(STM32_RCC_AHBENR);
regval |= RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPBEN | RCC_AHBENR_IOPCEN |\
regval |= RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPBEN | RCC_AHBENR_IOPCEN |
RCC_AHBENR_IOPDEN | RCC_AHBENR_IOPEEN | RCC_AHBENR_IOPFEN;
putreg32(regval, STM32_RCC_AHBENR);
}
@@ -432,7 +433,8 @@ static void stm32_stdclockconfig(void)
regval &= ~RCC_CFGR_SW_MASK;
putreg32(regval, STM32_RCC_CFGR);
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_HSI);
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_HSI);
}
/* Disable the PLL */
@@ -469,8 +471,10 @@ static void stm32_stdclockconfig(void)
* 3. Use multiplier from board.h
*/
regval &= ~(RCC_CFGR_PLLSRC_MASK | RCC_CFGR_PLLXTPRE_MASK | RCC_CFGR_PLLMUL_MASK);
regval |= (RCC_CFGR_PLLSRC_HSId2 | RCC_CFGR_PLLXTPRE_DIV1 | STM32_CFGR_PLLMUL);
regval &= ~(RCC_CFGR_PLLSRC_MASK | RCC_CFGR_PLLXTPRE_MASK |
RCC_CFGR_PLLMUL_MASK);
regval |= (RCC_CFGR_PLLSRC_HSId2 | RCC_CFGR_PLLXTPRE_DIV1 |
STM32_CFGR_PLLMUL);
putreg32(regval, STM32_RCC_CFGR);
/* Enable the PLL */
arch/arm/src/stm32f7/hardware/stm32_ethernet.h
+73 -24
View File
@@ -1,4 +1,4 @@
/****************************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f7/hardware/stm32_ethernet.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_ETHERNET_H
#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_ETHERNET_H
/****************************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -34,10 +34,12 @@
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
/****************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* Register Offsets *********************************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************/
/* MAC Registers */
#define STM32_ETH_MACCR_OFFSET 0x0000 /* Ethernet MAC configuration register */
@@ -106,7 +108,8 @@
#define STM32_ETH_DMACHTBAR_OFFSET 0x1050 /* Ethernet DMA current host transmit buffer address register */
#define STM32_ETH_DMACHRBAR_OFFSET 0x1054 /* Ethernet DMA current host receive buffer address register */
/* Register Base Addresses **************************************************************************/
/* Register Base Addresses **************************************************/
/* MAC Registers */
#define STM32_ETH_MACCR (STM32_ETHMAC_BASE+STM32_ETH_MACCR_OFFSET)
@@ -175,7 +178,8 @@
#define STM32_ETH_DMACHTBAR (STM32_ETHMAC_BASE+STM32_ETH_DMACHTBAR_OFFSET)
#define STM32_ETH_DMACHRBAR (STM32_ETHMAC_BASE+STM32_ETH_DMACHRBAR_OFFSET)
/* Register Bit-Field Definitions *******************************************************************/
/* Register Bit-Field Definitions *******************************************/
/* MAC Registers */
/* Ethernet MAC configuration register */
@@ -189,6 +193,7 @@
# define ETH_MACCR_BL_8 (1 << ETH_MACCR_BL_SHIFT) /* 01: k = min (n, 8) */
# define ETH_MACCR_BL_4 (2 << ETH_MACCR_BL_SHIFT) /* 10: k = min (n, 4) */
# define ETH_MACCR_BL_1 (3 << ETH_MACCR_BL_SHIFT) /* 11: k = min (n, 1) */
#define ETH_MACCR_APCS (1 << 7) /* Bit 7: Automatic pad/CRC stripping */
#define ETH_MACCR_RD (1 << 9) /* Bit 9: Retry disable */
#define ETH_MACCR_IPCO (1 << 10) /* Bit 10: IPv4 checksum offload */
@@ -200,6 +205,7 @@
#define ETH_MACCR_IFG_SHIFT (17) /* Bits 17-19: Interframe gap */
#define ETH_MACCR_IFG_MASK (7 << ETH_MACCR_IFG_SHIFT)
# define ETH_MACCR_IFG(n) ((12-((n) >> 3)) << ETH_MACCR_IFG_SHIFT) /* n bit times, n=40,48,..96 */
#define ETH_MACCR_JD (1 << 22) /* Bit 22: Jabber disable */
#define ETH_MACCR_WD (1 << 23) /* Bit 23: Watchdog disable */
#define ETH_MACCR_CSTF (1 << 25) /* Bits 25: CRC stripping for Type frames */
@@ -218,6 +224,7 @@
# define ETH_MACFFR_PCF_PAUSE (1 << ETH_MACFFR_PCF_SHIFT) /* Prevents all except Pause control frames */
# define ETH_MACFFR_PCF_ALL (2 << ETH_MACFFR_PCF_SHIFT) /* Forwards all control frames */
# define ETH_MACFFR_PCF_FILTER (3 << ETH_MACFFR_PCF_SHIFT) /* Forwards all that pass address filter */
#define ETH_MACFFR_SAIF (1 << 8) /* Bit 8: Source address inverse filtering */
#define ETH_MACFFR_SAF (1 << 9) /* Bit 9: Source address filter */
#define ETH_MACFFR_HPF (1 << 10) /* Bit 10: Hash or perfect filter */
@@ -236,6 +243,7 @@
# define ETH_MACMIIAR_CR_DIV16 (2 << ETH_MACMIIAR_CR_SHIFT) /* 20-35 MHz HCLK/16 */
# define ETH_MACMIIAR_CR_DIV26 (3 << ETH_MACMIIAR_CR_SHIFT) /* 35-60 MHz HCLK/26 */
# define ETH_MACMIIAR_CR_DIV102 (4 << ETH_MACMIIAR_CR_SHIFT) /* 150-216 MHz HCLK/102 */
#define ETH_MACMIIAR_MR_SHIFT (6) /* Bits 6-10: MII register */
#define ETH_MACMIIAR_MR_MASK (31 << ETH_MACMIIAR_MR_SHIFT)
# define ETH_MACMIIAR_MR(n) ((uint32_t)(n) << ETH_MACMIIAR_MR_SHIFT)
@@ -259,6 +267,7 @@
# define ETH_MACFCR_PLT_M28 (1 << ETH_MACFCR_PLT_SHIFT) /* 01 Pause - 28 slot times */
# define ETH_MACFCR_PLT_M144 (2 << ETH_MACFCR_PLT_SHIFT) /* 10 Pause - 144 slot times */
# define ETH_MACFCR_PLT_M256 (3 << ETH_MACFCR_PLT_SHIFT) /* 11 Pause -s 256 slot times */
#define ETH_MACFCR_ZQPD (1 << 7) /* Bit 7: Zero-quanta pause disable */
#define ETH_MACFCR_PT_SHIFT (16) /* Bits 16-31: Pause time */
#define ETH_MACFCR_PT_MASK (0xffff << ETH_MACFCR_PT_SHIFT)
@@ -270,8 +279,8 @@
# define ETH_MACVLANTR_VLANTI(n) ((uint32_t)(n) << ETH_MACVLANTR_VLANTI_SHIFT)
#define ETH_MACVLANTR_VLANTC (1 << 16) /* Bit 16: 12-bit VLAN tag comparison */
/* Ethernet MAC remote wakeup frame filter reg. Provides 32-bit access to remote
* remote wake-up filters.
/* Ethernet MAC remote wakeup frame filter reg.
* Provides 32-bit access to remote remote wake-up filters.
*/
/* Ethernet MAC PMT control and status register */
@@ -296,12 +305,14 @@
# define ETH_MACDBGR_RFRCS_RFRAME (1 << ETH_MACDBGR_RFRCS_SHIFT) /* 01: Reading frame data */
# define ETH_MACDBGR_RFRCS_RSTATUS (2 << ETH_MACDBGR_RFRCS_SHIFT) /* 10: Reading frame status (or time-stamp) */
# define ETH_MACDBGR_RFRCS_FLUSHING (3 << ETH_MACDBGR_RFRCS_SHIFT) /* 11: Flushing the frame data and status */
#define ETH_MACDBGR_RFFL_SHIFT (8) /* Bits 8-9: Rx FIFO fill level */
#define ETH_MACDBGR_RFFL_MASK (3 << ETH_MACDBGR_RFFL_SHIFT)
# define ETH_MACDBGR_RFFL_EMPTY (0 << ETH_MACDBGR_RFFL_SHIFT) /* 00: RxFIFO empty */
# define ETH_MACDBGR_RFFL_DEACT (1 << ETH_MACDBGR_RFFL_SHIFT) /* 01: RxFIFO fill-level below flow-control de-activate threshold */
# define ETH_MACDBGR_RFFL_ACTIV (2 << ETH_MACDBGR_RFFL_SHIFT) /* 10: RxFIFO fill-level above flow-control activate threshold */
# define ETH_MACDBGR_RFFL_FULL (3 << ETH_MACDBGR_RFFL_SHIFT) /* 11: RxFIFO full */
#define ETH_MACDBGR_MMTEA (1 << 16) /* Bit 16: MAC MII transmit engine active */
#define ETH_MACDBGR_MTFCS_SHIFT (17) /* Bits 17-18: MAC transmit frame controller status */
#define ETH_MACDBGR_MTFCS_MASK (3 << ETH_MACDBGR_MTFCS_SHIFT)
@@ -309,6 +320,7 @@
# define ETH_MACDBGR_MTFCS_WAITING (1 << ETH_MACDBGR_MTFCS_SHIFT) /* 01: Waiting for Status of previous frame or IFG/backoff period to be over */
# define ETH_MACDBGR_MTFCS_PAUSE (2 << ETH_MACDBGR_MTFCS_SHIFT) /* 10: Generating and transmitting a Pause control frame */
# define ETH_MACDBGR_MTFCS_FRAME (3 << ETH_MACDBGR_MTFCS_SHIFT) /* 11: Transferring input frame for transmission */
#define ETH_MACDBGR_MTP (1 << 19) /* Bit 19: MAC transmitter in pause */
#define ETH_MACDBGR_TFRS_SHIFT (20) /* Bits 20-21: Tx FIFO read status */
#define ETH_MACDBGR_TFRS_MASK (3 << ETH_MACDBGR_TFRS_SHIFT)
@@ -316,6 +328,7 @@
# define ETH_MACDBGR_TFRS_READ (1 << ETH_MACDBGR_TFRS_SHIFT) /* 01: Read state */
# define ETH_MACDBGR_TFRS_WAITING (2 << ETH_MACDBGR_TFRS_SHIFT) /* 10: Waiting for TxStatus from MAC transmitter */
# define ETH_MACDBGR_TFRS_WRITING (3 << ETH_MACDBGR_TFRS_SHIFT) /* 11: Writing the received TxStatus or flushing the TxFIFO */
#define ETH_MACDBGR_TFWA (1 << 22) /* Bit 22: Tx FIFO write active */
#define ETH_MACDBGR_TFNE (1 << 24) /* Bit 24: Tx FIFO not empty */
#define ETH_MACDBGR_TFF (1 << 25) /* Bit 25: Tx FIFO full */
@@ -356,6 +369,7 @@
# define ETH_MACA1HR_MBC_16_23 (0x04 << ETH_MACA1HR_MBC_SHIFT) /* Bit 26: ETH_MACA1LR [16-23] */
# define ETH_MACA1HR_MBC_8_15 (0x02 << ETH_MACA1HR_MBC_SHIFT) /* Bit 25: ETH_MACA1LR [8-15] */
# define ETH_MACA1HR_MBC_0_7 (0x01 << ETH_MACA1HR_MBC_SHIFT) /* Bit 24: ETH_MACA1LR [0-7] */
#define ETH_MACA1HR_SA (1 << 30) /* Bit 30: Source address */
#define ETH_MACA1HR_AE (1 << 31) /* Bit 31: Address enable */
@@ -374,6 +388,7 @@
# define ETH_MACA2HR_MBC_16_23 (0x04 << ETH_MACA2HR_MBC_SHIFT) /* Bit 26: ETH_MACA2LR [16-23] */
# define ETH_MACA2HR_MBC_8_15 (0x02 << ETH_MACA2HR_MBC_SHIFT) /* Bit 25: ETH_MACA2LR [8-15] */
# define ETH_MACA2HR_MBC_0_7 (0x01 << ETH_MACA2HR_MBC_SHIFT) /* Bit 24: ETH_MACA2LR [0-7] */
#define ETH_MACA2HR_SA (1 << 30) /* Bit 30: Source address */
#define ETH_MACA2HR_AE (1 << 31) /* Bit 31: Address enable */
@@ -392,6 +407,7 @@
# define ETH_MACA3HR_MBC_16_23 (0x04 << ETH_MACA3HR_MBC_SHIFT) /* Bit 26: ETH_MACA3LR [16-23] */
# define ETH_MACA3HR_MBC_8_15 (0x02 << ETH_MACA3HR_MBC_SHIFT) /* Bit 25: ETH_MACA3LR [8-15] */
# define ETH_MACA3HR_MBC_0_7 (0x01 << ETH_MACA3HR_MBC_SHIFT) /* Bit 24: ETH_MACA3LR [0-7] */
#define ETH_MACA3HR_SA (1 << 30) /* Bit 30: Source address */
#define ETH_MACA3HR_AE (1 << 31) /* Bit 31: Address enable */
@@ -454,6 +470,7 @@
# define ETH_PTPTSCR_TSCNT_BOUNDARY (1 << ETH_PTPTSCR_TSCNT_SHIFT) /* 01: Boundary clock */
# define ETH_PTPTSCR_TSCNT_E2E (2 << ETH_PTPTSCR_TSCNT_SHIFT) /* 10: End-to-end transparent clock */
# define ETH_PTPTSCR_TSCNT_P2P (3 << ETH_PTPTSCR_TSCNT_SHIFT) /* 11: Peer-to-peer transparent clock */
#define ETH_PTPTSCR_TSPFFMAE (1 << 18) /* Bit 18: Time stamp PTP frame filtering MAC address enable */
/* Ethernet PTP subsecond increment register */
@@ -475,7 +492,9 @@
#define ETH_PTPTSLU_MASK (0x7fffffff) /* Bits 0-30: Time stamp update subsecond */
/* Ethernet PTP time stamp addend register (32-bit) */
/* Ethernet PTP target time high register (32-bit) */
/* Ethernet PTP target time low register (32-bit) */
/* Ethernet PTP time stamp status register */
@@ -496,28 +515,34 @@
#define ETH_DMABMR_PBL_SHIFT (8) /* Bits 8-13: Programmable burst length */
#define ETH_DMABMR_PBL_MASK (0x3f << ETH_DMABMR_PBL_SHIFT)
# define ETH_DMABMR_PBL(n) ((n) << ETH_DMABMR_PBL_SHIFT) /* n=1, 2, 4, 8, 16, 32 */
#define ETH_DMABMR_PM_SHIFT (14) /* Bits 14-15: Rx Tx priority ratio */
#define ETH_DMABMR_PM_MASK (3 << ETH_DMABMR_PM_SHIFT)
# define ETH_DMABMR_RTPR_1TO1 (0 << ETH_DMABMR_PM_SHIFT) /* 00: 1:1 */
# define ETH_DMABMR_RTPR_2TO1 (1 << ETH_DMABMR_PM_SHIFT) /* 01: 2:1 */
# define ETH_DMABMR_RTPR_3TO1 (2 << ETH_DMABMR_PM_SHIFT) /* 10: 3:1 */
# define ETH_DMABMR_RTPR_4TO1 (3 << ETH_DMABMR_PM_SHIFT) /* 11: 4:1 */
#define ETH_DMABMR_FB (1 << 16) /* Bit 16: Fixed burst */
#define ETH_DMABMR_RDP_SHIFT (17) /* Bits 17-22: Rx DMA PBL */
#define ETH_DMABMR_RDP_MASK (0x3f << ETH_DMABMR_RDP_SHIFT)
# define ETH_DMABMR_RDP(n) ((n) << ETH_DMABMR_RDP_SHIFT) /* n=1, 2, 4, 8, 16, 32 */
#define ETH_DMABMR_USP (1 << 23) /* Bit 23: Use separate PBL */
#define ETH_DMABMR_FPM (1 << 24) /* Bit 24: 4xPBL mode */
#define ETH_DMABMR_AAB (1 << 25) /* Bit 25: Address-aligned beats */
#define ETH_DMABMR_MB (1 << 26) /* Bit 26: Mixed burst */
/* Ethernet DMA transmit poll demand register (32-bit) */
/* Ethernet DMA receive poll demand register (32-bit) */
/* Ethernet DMA receive descriptor list address register (32-bit address) */
/* Ethernet DMA transmit descriptor list address register (32-bit address) */
/* Interrupt bit definitions common between the DMA status register (DMASR) and
* the DMA interrupt enable register (DMAIER).
/* Interrupt bit definitions common between the DMA status register (DMASR)
* and the DMA interrupt enable register (DMAIER).
*/
#define ETH_DMAINT_TI (1 << 0) /* Bit 0: Transmit interrupt */
@@ -546,6 +571,7 @@
# define ETH_DMASR_RPS_SUSPENDED (4 << ETH_DMASR_RPS_SHIFT) /* 100: Suspended: Receive descriptor unavailable */
# define ETH_DMASR_RPS_CLOSING (5 << ETH_DMASR_RPS_SHIFT) /* 101: Running: Closing receive descriptor */
# define ETH_DMASR_RPS_TRANSFER (7 << ETH_DMASR_RPS_SHIFT) /* 111: Running: Transferring the receive data to memory */
#define ETH_DMASR_TPS_SHIFT (20) /* Bits 20-22: Transmit process state */
#define ETH_DMASR_TPS_MASK (7 << ETH_DMASR_TPS_SHIFT)
# define ETH_DMASR_TPS_STOPPED (0 << ETH_DMASR_TPS_SHIFT) /* 000: Stopped; Reset or Stop Transmit Command issued */
@@ -554,11 +580,13 @@
# define ETH_DMASR_TPS_TRANSFER (3 << ETH_DMASR_TPS_SHIFT) /* 011: Running; Reading data and queuing to transmit (TxFIFO) */
# define ETH_DMASR_TPS_SUSPENDED (6 << ETH_DMASR_TPS_SHIFT) /* 110: Suspended; Transmit descriptor unavailable or buffer underflow */
# define ETH_DMASR_TPS_CLOSING (7 << ETH_DMASR_TPS_SHIFT) /* 111: Running; Closing transmit descriptor */
#define ETH_DMASR_EBS_SHIFT (23) /* Bits 23-25: Error bits status */
#define ETH_DMASR_EBS_MASK (7 << ETH_DMASR_EBS_SHIFT)
# define ETH_DMASR_EBS_TXDMS (1 << ETH_DMASR_EBS_SHIFT) /* Bit 23 1 Error during data transfer by TxDMA */
# define ETH_DMASR_EBS_READ (2 << ETH_DMASR_EBS_SHIFT) /* Bit 24 1 Error during read transfer */
# define ETH_DMASR_EBS_DESC (4 << ETH_DMASR_EBS_SHIFT) /* Bit 25 1 Error during descriptor access */
#define ETH_DMASR_MMCS (1 << 27) /* Bit 27: MMC status */
#define ETH_DMASR_PMTS (1 << 28) /* Bit 28: PMT status */
#define ETH_DMASR_TSTS (1 << 29) /* Bit 29: Time stamp trigger status */
@@ -607,12 +635,24 @@
#define ETH_DMARSWTR_MASK (0xff)
/* Ethernet DMA current host transmit descriptor register (32-bit address) */
/* Ethernet DMA current host receive descriptor register (32-bit address) */
/* Ethernet DMA current host transmit buffer address register (32-bit address) */
/* Ethernet DMA current host receive buffer address register (32-bit address) */
/* Ethernet DMA current host transmit descriptor register
* (32-bit address)
*/
/* Ethernet DMA current host receive descriptor register
* (32-bit address)
*/
/* Ethernet DMA current host transmit buffer address register
* (32-bit address)
*/
/* Ethernet DMA current host receive buffer address register
* (32-bit address)
*/
/* DMA Descriptors **********************************************************/
/* DMA Descriptors **********************************************************************************/
/* TDES0: Transmit descriptor Word0 */
#define ETH_TDES0_DB (1 << 0) /* Bit 0: Deferred bit */
@@ -640,6 +680,7 @@
# define ETH_TDES0_CIC_IH (1 << ETH_TDES0_CIC_SHIFT) /* IP header checksum enabled */
# define ETH_TDES0_CIC_IHPL (2 << ETH_TDES0_CIC_SHIFT) /* IP header and payload checksum enabled */
# define ETH_TDES0_CIC_ALL (3 << ETH_TDES0_CIC_SHIFT) /* IP Header, payload, and pseudo-header checksum enabled */
#define ETH_TDES0_TTSE (1 << 25) /* Bit 25: Transmit time stamp enable */
#define ETH_TDES0_DP (1 << 26) /* Bit 26: Disable pad */
#define ETH_TDES0_DC (1 << 27) /* Bit 27: Disable CRC */
@@ -653,13 +694,16 @@
#define ETH_TDES1_TBS1_SHIFT (0) /* Bits 0-12: Transmit buffer 1 size */
#define ETH_TDES1_TBS1_MASK (0x1fff << ETH_TDES1_TBS1_SHIFT)
# define ETH_TDES1_TBS1(n) ((uint32_t)(n) << ETH_TDES1_TBS1_SHIFT)
#define ETH_TDES1_TBS2_SHIFT (16) /* Bits 16-28: Transmit buffer 2 size */
#define ETH_TDES1_TBS2_SHIFT (16) /* Bits 16-28: Transmit buffer 2 size */
#define ETH_TDES1_TBS2_MASK (0x1fff << ETH_TDES1_TBS2_SHIFT)
# define ETH_TDES1_TBS2(n) ((uint32_t)(n) << ETH_TDES1_TBS2_SHIFT)
/* TDES2: Transmit descriptor Word2 (32-bit address) */
/* TDES3: Transmit descriptor Word3 (32-bit address) */
/* TDES6: Transmit descriptor Word6 (32-bit time stamp) */
/* TDES7: Transmit descriptor Word7 (32-bit time stamp) */
/* RDES0: Receive descriptor Word0 */
@@ -701,6 +745,7 @@
#define ETH_RDES1_DIC (1 << 31) /* Bit 31: Disable interrupt on completion */
/* RDES2: Receive descriptor Word2 (32-bit address) */
/* RDES3: Receive descriptor Word3 (32-bit address) */
/* RDES4: Receive descriptor Word4 */
@@ -711,6 +756,7 @@
# define ETH_RDES4_IPPT_UDP (1 << ETH_RDES4_IPPT_SHIFT) /* UDP payload in IP datagram */
# define ETH_RDES4_IPPT_TCP (2 << ETH_RDES4_IPPT_SHIFT) /* TCP payload in IP datagram */
# define ETH_RDES4_IPPT_ICMP (3 << ETH_RDES4_IPPT_SHIFT) /* ICMP payload in IP datagram */
#define ETH_RDES4_IPHE (1 << 3) /* Bit 3: IP header error */
#define ETH_RDES4_IPPE (1 << 4) /* Bit 4: IP payload error */
#define ETH_RDES4_IPCB (1 << 5) /* Bit 5: IP checksum bypassed */
@@ -733,16 +779,19 @@
* peer-to-peer transparent clock) or
* Signaling (for ordinary or boundary
* clock) */
#define ETH_RDES4_PFT (1 << 12) /* Bit 12: PTP frame type */
#define ETH_RDES4_PV (1 << 13) /* Bit 13: PTP version */
/* RDES5: Receive descriptor Word5 - Reserved */
/* RDES6: Receive descriptor Word6 (32-bit time stamp) */
/* RDES7: Receive descriptor Word7 (32-bit time stamp) */
/****************************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
@@ -786,9 +835,9 @@ struct eth_rxdesc_s
#endif
};
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
arch/arm/src/stm32f7/hardware/stm32_rtcc.h
+13 -9
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f7/hardware/stm32_rtcc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,16 +16,16 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_RTCC_H
#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_RTCC_H
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */
#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */
@@ -81,7 +81,7 @@
#define STM32_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */
#define STM32_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define STM32_RTC_TR (STM32_RTC_BASE+STM32_RTC_TR_OFFSET)
#define STM32_RTC_DR (STM32_RTC_BASE+STM32_RTC_DR_OFFSET)
@@ -138,7 +138,7 @@
#define STM32_RTC_BKCOUNT 32
/* Register Bitfield Definitions ****************************************************/
/* Register Bitfield Definitions ********************************************/
/* RTC time register */
@@ -191,6 +191,7 @@
# define RTC_CR_WUCKSEL_RTCDIV2 (3 << RTC_CR_WUCKSEL_SHIFT) /* 011: RTC/2 clock is selected */
# define RTC_CR_WUCKSEL_CKSPRE (4 << RTC_CR_WUCKSEL_SHIFT) /* 10x: ck_spre clock is selected */
# define RTC_CR_WUCKSEL_CKSPREADD (6 << RTC_CR_WUCKSEL_SHIFT) /* 11x: ck_spr clock and 216 added WUT counter */
#define RTC_CR_TSEDGE (1 << 3) /* Bit 3: Timestamp event active edge */
#define RTC_CR_REFCKON (1 << 4) /* Bit 4: Reference clock detection enable (50 or 60 Hz) */
#define RTC_CR_BYPSHAD (1 << 5) /* Bit 5: Bypass the shadow registers */
@@ -214,6 +215,7 @@
# define RTC_CR_OSEL_ALRMA (1 << RTC_CR_OSEL_SHIFT) /* 01: Alarm A output enabled */
# define RTC_CR_OSEL_ALRMB (2 << RTC_CR_OSEL_SHIFT) /* 10: Alarm B output enabled */
# define RTC_CR_OSEL_WUT (3 << RTC_CR_OSEL_SHIFT) /* 11: Wakeup output enabled */
#define RTC_CR_COE (1 << 23) /* Bit 23: Calibration output enable */
#define RTC_CR_ITSE (1 << 24) /* Bit 24: Timestamp on internal event enable */
@@ -339,7 +341,7 @@
#define RTC_TAMPCR_TAMP3E (1 << 5) /* Bit 5: RTC_TAMP3 detection enable */
#define RTC_TAMPCR_TAMP3TRG (1 << 6) /* Bit 6: Active level for RTC_TAMP3 input */
#define RTC_TAMPCR_TAMPTS (1 << 7) /* Bit 7: Activate timestamp on tamper detection event */
#define RTC_TAMPCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */
#define RTC_TAMPCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */
#define RTC_TAMPCR_TAMPFREQ_MASK (7 << RTC_TAMPCR_TAMPFREQ_SHIFT)
# define RTC_TAMPCR_TAMPFREQ_DIV32768 (0 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 32768 (1 Hz) */
# define RTC_TAMPCR_TAMPFREQ_DIV16384 (1 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 16384 (2 Hz) */
@@ -349,6 +351,7 @@
# define RTC_TAMPCR_TAMPFREQ_DIV1024 (5 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 1024 (32 Hz) */
# define RTC_TAMPCR_TAMPFREQ_DIV512 (6 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 512 (64 Hz) */
# define RTC_TAMPCR_TAMPFREQ_DIV256 (7 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 256 (128 Hz) */
#define RTC_TAMPCR_TAMPFLT_SHIFT (11) /* Bits 11-12: RTC_TAMPx filter count */
#define RTC_TAMPCR_TAMPFLT_MASK (3 << RTC_TAMPCR_TAMPFLT_SHIFT)
#define RTC_TAMPCR_TAMPPRCH_SHIFT (13) /* Bits 13-14: RTC_TAMPx precharge duration */
@@ -357,6 +360,7 @@
# define RTC_TAMPCR_TAMPPRCH_2CYCLES (1 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 2 RTCCLK cycles */
# define RTC_TAMPCR_TAMPPRCH_4CYCLES (2 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 4 RTCCLK cycles */
# define RTC_TAMPCR_TAMPPRCH_5CYCLES (3 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 8 RTCCLK cycles */
#define RTC_TAMPCR_TAMPPUDIS (1 << 15) /* Bit 15: RTC_TAMPx pull-up disable */
#define RTC_TAMPCR_TAMP1IE (1 << 16) /* Bit 16: Tamper 1 interrupt enable */
#define RTC_TAMPCR_TAMP1NOERASE (1 << 17) /* Bit 17: Tamper 1 no erase */
@@ -383,7 +387,7 @@
# define RTC_OR_PI8 (1 << RTC_OR_TSINSEL_SHIFT) /* TIMESTAMP is mapped on PI8 */
# define RTC_OR_PC1 (2 << RTC_OR_TSINSEL_SHIFT) /* TIMESTAMP is mapped on PC1 */
# define RTC_OR_PC1_1 (3 << RTC_OR_TSINSEL_SHIFT) /* TIMESTAMP is mapped on PC1 */
#define RTC_OR_RTC_ALARM_TYPE (1 << 3) /* RTC_ALARM on PC13 output type */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_RTCC_H */
arch/arm/src/stm32f7/hardware/stm32_tim.h
+4 -4
View File
@@ -1,4 +1,4 @@
/****************************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f7/hardware/stm32_tim.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_TIM_H
#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_TIM_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h
+15 -9
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,20 +16,21 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM327_CHIP_STM32F74XX75XX_FLASH_H
#define __ARCH_ARM_SRC_STM327_CHIP_STM32F74XX75XX_FLASH_H
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Flash size is known from the chip selection:
*
* When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the
* CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on the chip
* part number. This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x
* CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on
* the chip part number.
* This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x
*
* Parts STM32F74xxE have 512Kb of FLASH
* Parts STM32F74xxG have 1024Kb of FLASH
@@ -80,7 +81,7 @@
#endif
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define STM32_FLASH_ACR_OFFSET 0x0000
#define STM32_FLASH_KEYR_OFFSET 0x0004
@@ -90,7 +91,7 @@
#define STM32_FLASH_OPTCR_OFFSET 0x0014
#define STM32_FLASH_OPTCR1_OFFSET 0x0018
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET)
#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
@@ -100,7 +101,8 @@
#define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET)
#define STM32_FLASH_OPTCR1 (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR1_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* Register Bitfield Definitions ********************************************/
/* Flash Access Control Register (ACR) */
#define FLASH_ACR_LATENCY_SHIFT (0) /* Bits 0-1: Latency */
@@ -114,6 +116,7 @@
# define FLASH_ACR_LATENCY_5 (5 << FLASH_ACR_LATENCY_SHIFT) /* 101: Five wait states */
# define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 110: Six wait states */
# define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 111: Seven wait states */
#define FLASH_ACR_PRFTEN (1 << 8) /* FLASH prefetch enable */
#define FLASH_ACR_ARTEN (1 << 9) /* Bit 9: ART Accelerator Enable */
#define FLASH_ACR_ARTRST (1 << 11) /* Bit 11: ART Accelerator reset */
@@ -136,12 +139,14 @@
#define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */
#define FLASH_CR_SNB_MASK (0xf << FLASH_CR_SNB_SHIFT)
# define FLASH_CR_SNB(n) (((uint32_t)((n) % 8) << FLASH_CR_SNB_SHIFT) | ((n / 8) << 6)) /* Sector n, n=0..23 */
#define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */
#define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT)
# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* Program x8 */
# define FLASH_CR_PSIZE_X16 (1 << FLASH_CR_PSIZE_SHIFT) /* Program x16 */
# define FLASH_CR_PSIZE_X32 (2 << FLASH_CR_PSIZE_SHIFT) /* Program x32 */
# define FLASH_CR_PSIZE_X64 (3 << FLASH_CR_PSIZE_SHIFT) /* Program x64 */
#define FLASH_CR_STRT (1 << 16) /* Bit 16: Start Erase */
#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */
#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */
@@ -157,6 +162,7 @@
# define FLASH_OPTCR_VBOR2 (1 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 2 */
# define FLASH_OPTCR_VBOR1 (2 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 1 */
# define FLASH_OPTCR_VBOR0 (3 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR off */
#define FLASH_OPTCR_USER_SHIFT (4) /* Bits 5-7: User option bytes */
#define FLASH_OPTCR_USER_MASK (15 << FLASH_OPTCR_USER_SHIFT)
# define FLASH_OPTCR_WWDG_SW (1 << 4) /* Bit 4: WWDG_SW */

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