From ee0861ae7a3920c3126e22cdece871029833ea47 Mon Sep 17 00:00:00 2001 From: Alin Jerpelea Date: Sun, 21 Mar 2021 15:41:45 +0100 Subject: [PATCH] arch: arm: fixes for nxstyle errors Nxstyle error fixes to pass CI Signed-off-by: Alin Jerpelea --- arch/arm/src/imxrt/hardware/imxrt_flexpwm.h | 184 ++-- arch/arm/src/imxrt/hardware/imxrt_gpt.h | 24 +- arch/arm/src/imxrt/hardware/imxrt_ocotp.h | 22 +- arch/arm/src/imxrt/hardware/imxrt_pit.h | 3 +- arch/arm/src/imxrt/hardware/imxrt_tmr.h | 37 +- .../arm/src/imxrt/hardware/imxrt_usb_analog.h | 25 +- arch/arm/src/imxrt/hardware/imxrt_xbar.h | 1 - .../imxrt/hardware/rt105x/imxrt105x_iomuxc.h | 1 + .../imxrt/hardware/rt106x/imxrt106x_iomuxc.h | 1 + .../hardware/rt106x/imxrt106x_memorymap.h | 140 ++- arch/arm/src/imxrt/imxrt105x_daisy.c | 917 ++++++++++++------ arch/arm/src/imxrt/imxrt106x_daisy.c | 913 +++++++++++------ arch/arm/src/imxrt/imxrt_xbar.c | 7 +- arch/arm/src/imxrt/imxrt_xbar.h | 76 +- arch/arm/src/kl/hardware/kl_tsi.h | 35 +- arch/arm/src/kl/kl_clockconfig.c | 24 +- arch/arm/src/kl/kl_pwm.h | 63 +- arch/arm/src/lpc43xx/lpc43_timer.h | 2 +- arch/arm/src/nrf52/hardware/nrf52_nvmc.h | 18 +- arch/arm/src/samv7/sam_systemreset.c | 4 +- arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h | 49 +- arch/arm/src/stm32f0l0g0/hardware/stm32_can.h | 19 +- arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h | 24 +- arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h | 16 +- arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h | 27 +- arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h | 17 +- .../arm/src/stm32f0l0g0/hardware/stm32_rtcc.h | 20 +- .../src/stm32f0l0g0/hardware/stm32_uart_v1.h | 19 +- arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h | 19 +- .../hardware/stm32f03x_memorymap.h | 34 +- .../stm32f0l0g0/hardware/stm32f03x_pinmap.h | 30 +- .../hardware/stm32f05xf07xf09x_memorymap.h | 31 +- .../stm32f0l0g0/hardware/stm32f07x_pinmap.h | 30 +- .../stm32f0l0g0/hardware/stm32f09x_pinmap.h | 31 +- .../src/stm32f0l0g0/hardware/stm32f0_exti.h | 22 +- .../src/stm32f0l0g0/hardware/stm32f0_pwr.h | 19 +- .../src/stm32f0l0g0/hardware/stm32f0_rcc.h | 36 +- .../src/stm32f0l0g0/hardware/stm32f0_syscfg.h | 22 +- arch/arm/src/stm32f0l0g0/stm32_gpio.c | 26 +- arch/arm/src/stm32f0l0g0/stm32_hsi48.h | 18 +- arch/arm/src/stm32f0l0g0/stm32_irq.c | 2 +- arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c | 14 +- arch/arm/src/stm32f0l0g0/stm32_serial.c | 8 +- arch/arm/src/stm32f0l0g0/stm32_timerisr.c | 6 +- arch/arm/src/stm32f0l0g0/stm32_uart.h | 43 +- arch/arm/src/stm32f0l0g0/stm32f0_rcc.c | 12 +- .../arm/src/stm32f7/hardware/stm32_ethernet.h | 97 +- arch/arm/src/stm32f7/hardware/stm32_rtcc.h | 22 +- arch/arm/src/stm32f7/hardware/stm32_tim.h | 8 +- .../stm32f7/hardware/stm32f74xx75xx_flash.h | 24 +- .../hardware/stm32f74xx75xx_memorymap.h | 39 +- .../src/stm32f7/hardware/stm32f74xx75xx_pwr.h | 20 +- .../src/stm32f7/hardware/stm32f74xx75xx_rcc.h | 55 +- .../src/stm32f7/hardware/stm32f74xx75xx_tim.h | 108 ++- .../src/stm32f7/hardware/stm32f74xx77xx_adc.h | 59 +- .../src/stm32f7/hardware/stm32f74xx77xx_i2c.h | 18 +- .../stm32f7/hardware/stm32f74xx77xx_sdmmc.h | 16 +- .../src/stm32f7/hardware/stm32f74xx77xx_spi.h | 27 +- .../stm32f7/hardware/stm32f74xx77xx_uart.h | 21 +- .../stm32f7/hardware/stm32f76xx77xx_flash.h | 24 +- .../hardware/stm32f76xx77xx_memorymap.h | 40 +- .../stm32f7/hardware/stm32f76xx77xx_pinmap.h | 39 +- .../src/stm32f7/hardware/stm32f76xx77xx_pwr.h | 20 +- .../src/stm32f7/hardware/stm32f76xx77xx_rcc.h | 59 +- .../stm32f7/hardware/stm32f76xx77xx_syscfg.h | 19 +- .../src/stm32f7/hardware/stm32f76xx77xx_tim.h | 96 +- arch/arm/src/stm32h7/hardware/stm32_axi.h | 18 +- arch/arm/src/stm32h7/hardware/stm32_rtcc.h | 20 +- arch/arm/src/stm32h7/hardware/stm32_tim.h | 85 +- .../src/stm32h7/hardware/stm32h7x3xx_i2c.h | 18 +- .../src/stm32h7/hardware/stm32h7x3xx_syscfg.h | 23 +- arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c | 13 +- arch/arm/src/stm32l4/hardware/stm32l4_can.h | 43 +- arch/arm/src/stm32l4/hardware/stm32l4_crs.h | 16 +- .../src/stm32l4/hardware/stm32l4x5xx_rcc.h | 61 +- .../src/stm32l4/hardware/stm32l4x6xx_rcc.h | 43 +- arch/arm/src/stm32l4/stm32l4_can.h | 29 +- arch/arm/src/stm32l4/stm32l4_dumpgpio.c | 1 + arch/arm/src/stm32l4/stm32l4_firewall.h | 29 +- arch/arm/src/stm32l4/stm32l4_gpio.h | 81 +- arch/arm/src/stm32l4/stm32l4_hsi48.h | 2 +- arch/arm/src/stm32l4/stm32l4_rcc.c | 99 +- arch/arm/src/stm32l4/stm32l4x5xx_rcc.c | 4 +- .../arm/imxrt/imxrt1060-evk/src/imxrt_boot.c | 7 +- .../arm/stm32/olimexino-stm32/include/board.h | 17 +- .../stm32/olimexino-stm32/src/stm32_boot.c | 17 +- .../olimexino-stm32/src/stm32_composite.c | 24 +- .../arm/stm32/olimexino-stm32/src/stm32_spi.c | 42 +- .../stm32/olimexino-stm32/src/stm32_usbdev.c | 26 +- .../stm32/olimexino-stm32/src/stm32_usbmsc.c | 13 +- .../arm/stm32f7/nucleo-144/src/stm32_boot.c | 24 +- boards/arm/stm32f7/nucleo-144/src/stm32_spi.c | 91 +- .../arm/stm32h7/nucleo-h743zi/src/stm32_adc.c | 10 +- .../stm32l4/nucleo-l496zg/src/stm32_boot.c | 24 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_spi.c | 79 +- 95 files changed, 3104 insertions(+), 1757 deletions(-) diff --git a/arch/arm/src/imxrt/hardware/imxrt_flexpwm.h b/arch/arm/src/imxrt/hardware/imxrt_flexpwm.h index 1d752c40ecd..9e6b39fe50c 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_flexpwm.h +++ b/arch/arm/src/imxrt/hardware/imxrt_flexpwm.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_flexpwm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_FLEXPWM_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_FLEXPWM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define IMXRT_FLEXPWM_SM0CNT_OFFSET 0x0000 /* Counter Register */ #define IMXRT_FLEXPWM_SM0INIT_OFFSET 0x0002 /* Initial Count Register */ @@ -219,7 +219,7 @@ #define IMXRT_FLEXPWM_FTST0_OFFSET 0x0192 /* Fault Test Register */ #define IMXRT_FLEXPWM_FCTRL20_OFFSET 0x0194 /* Fault Control 2 Register */ -/* Register addresses ***********************************************************************/ +/* Register addresses *******************************************************/ /* FLEXPWM1 Register Addresses */ @@ -969,7 +969,7 @@ #define IMXRT_FLEXPWM4_FTST0 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_FTST0_OFFSET) /* FLEXPWM4 Fault Test Register */ #define IMXRT_FLEXPWM4_FCTRL20 (IMXRT_FLEXPWM4_BASE + IMXRT_FLEXPWM_FCTRL20_OFFSET) /* FLEXPWM4 Fault Control 2 Register */ -/* Register Bit Definitions ********************************************************* +/* Register Bit Definitions ************************************************* * * A single FLEXPWM[n] module (where n is 1..4) has submodules 0 - 3 * FLEXPWM module Base addresses are spaced every 0x4000 bytes starting at @@ -978,41 +978,42 @@ * * Each submodule instance is 0x60 bytes. * - * The address of a register is the sum of a base address and an address offset. - * The base address is defined as the module IMXRT_FLEXPWMn_BASE (n=1..4), and - * the address offset is defined at the module level. Each PWM module has a set - * of registers for each PWM submodule, for the configuration logic, and - * for each fault channel. While the registers are 16-bits wide, they can be - * accessed in pairs as 32-bit registers. + * The address of a register is the sum of a base address and an address + * offset. The base address is defined as the module IMXRT_FLEXPWMn_BASE + * (n=1..4), and the address offset is defined at the module level. Each + * PWM module has a set of registers for each PWM submodule, for the + * configuration logic, and for each fault channel. While the registers are + * 16-bits wide, they can be accessed in pairs as 32-bit registers. * - * Submodule registers are repeated for each PWM submodule. To designate which - * submodule they are in, register names are prefixed with SM0, SM1, SM2, and SM3 - * Since all these register definitions are identical the defines herein drops the - * number 0-3 from the prefix. + * Submodule registers are repeated for each PWM submodule. To designate + * which submodule they are in, register names are prefixed with SM0, SM1, + * SM2, and SM3 Since all these register definitions are identical the + * defines herein drops the number 0-3 from the prefix. * * For example the 'Status Register' appears 4 times per module - * (IMXRT_FLEXPWMn_BASE) as IMXRT_FLEXPWM_SM0STS_OFFSET, IMXRT_FLEXPWM_SM1STS_OFFSET, - * IMXRT_FLEXPWM_SM2STS_OFFSET and IMXRT_FLEXPWM_SM3STS_OFFSET. But the bit - * definitions for the 'Status Register' are defined as SMSTS_xxxxx (with the number - * dropped. + * (IMXRT_FLEXPWMn_BASE) as IMXRT_FLEXPWM_SM0STS_OFFSET, + * IMXRT_FLEXPWM_SM1STS_OFFSET, IMXRT_FLEXPWM_SM2STS_OFFSET and + * IMXRT_FLEXPWM_SM3STS_OFFSET. But the bit definitions for the 'Status + * Register' are defined as SMSTS_xxxxx (with the number dropped. * - * The base address of submodule 0 is the same as the base address for the PWM - * module as a whole. The base address of submodule 1 is offset 0x60 from the base - * address for the PWM module as a whole. This 0x60 offset is based on the number - * of registers in a submodule. The base address of submodule 2 is equal to the - * base address of submodule 1 plus this same 0x60 offset. The pattern repeats for - * the base address of submodule 3 - * . - * The base address of the module configuration registers is equal to the base - * address of the PWM module as a whole plus an offset of 0x180. + * The base address of submodule 0 is the same as the base address for the + * PWM module as a whole. The base address of submodule 1 is offset 0x60 from + * the base address for the PWM module as a whole. This 0x60 offset is based + * on the number of registers in a submodule. The base address of submodule + * 2 is equal to the base address of submodule 1 plus this same 0x60 offset. + * The pattern repeats for the base address of submodule 3. * - * Fault channel registers are repeated for each fault channel. To designate - * which fault channel they are in, register names are prefixed with F0 and F1. The - * base address of fault channel 0 is equal to the base address of the PWM module - * as a whole plus an offset of 0x18C. The base address of fault channel 1 is the - * base address of fault channel 0 + 4. This 4 offset is based on the number of - * registers in a fault channel. Each of the four fields in the fault channel - * registers corresponds to fault inputs 3-0. + * The base address of the module configuration registers is equal to the + * base address of the PWM module as a whole plus an offset of 0x180. + * + * Fault channel registers are repeated for each fault channel. To + * designate which fault channel they are in, register names are prefixed + * with F0 and F1. The base address of fault channel 0 is equal to the base + * address of the PWM module as a whole plus an offset of 0x18C. The base + * address of fault channel 1 is the base address of fault channel 0 + 4. + * This 4 offset is based on the number of registers in a fault channel. + * Each of the four fields in the fault channel registers corresponds to + * fault inputs 3-0. */ /* Control 2 Register */ @@ -1023,6 +1024,7 @@ # define SMCTRL2_CLK_SEL_IPG_CLK (0 << SMCTRL2_CLK_SEL_SHIFT) /* The IPBus clock is used as the clock for the local prescaler and counter. */ # define SMCTRL2_CLK_SEL_EXT_CLK (1 << SMCTRL2_CLK_SEL_SHIFT) /* EXT_CLK is used as the clock for the local prescaler and counter. */ # define SMCTRL2_CLK_SEL_AUX_CLK (2 << SMCTRL2_CLK_SEL_SHIFT) /* Submodule 0’s clock (AUX_CLK) is used as the source clock for the local prescaler and counter. */ + #define SMCTRL2_RELOAD_SEL (1 << 2) /* Bit: 2 Reload Source Select */ # define SMCTRL2_RELOAD_SEL_LOCAL (0 << 2) /* Reload Source is local */ # define SMCTRL2_RELOAD_SEL_SM0 (1 << 2) /* Reload Source is submodule 0 */ @@ -1037,6 +1039,7 @@ # define SMCTRL2_FORCE_SEL_SM0_SYNC (5 << SMCTRL2_FORCE_SEL_SHIFT) /* The master sync signal from submodule0 is used to force updates. */ # define SMCTRL2_FORCE_SEL_EXT_FORCE (6 << SMCTRL2_FORCE_SEL_SHIFT) /* The external force signal, EXT_FORCE, from outside the PWM module causes updates. */ # define SMCTRL2_FORCE_SEL_EXT_SYNC (7 << SMCTRL2_FORCE_SEL_SHIFT) /* The external sync signal, EXT_SYNC, from outside the PWM module causes updates */ + #define SMCTRL2_FORCE (1 << 6) /* Bit: 6 Force Initialization */ #define SMCTRL2_FRCEN (1 << 7) /* Bit: 7 FRCEN */ #define SMCTRL2_INIT_SEL_SHIFT (8) /* Bits: 8-9 Initialization Control Select */ @@ -1046,6 +1049,7 @@ # define SMCTRL2_INIT_SEL_SM0 (1 << SMCTRL2_INIT_SEL_SHIFT) /* Master reload from submodule 0 causes initialization. */ # define SMCTRL2_INIT_SEL_SM0_SYNC (2 << SMCTRL2_INIT_SEL_SHIFT) /* Master sync from submodule 0 causes initialization. */ # define SMCTRL2_INIT_SEL_EXT_SYNC (3 << SMCTRL2_INIT_SEL_SHIFT) /* EXT_SYNC causes initialization. */ + #define SMCTRL2_PWMX_INIT (1 << 10) /* Bit: 10 PWM_X Initial Value */ #define SMCTRL2_PWM45_INIT (1 << 11) /* Bit: 11 PWM45 Initial Value */ #define SMCTRL2_PWM23_INIT (1 << 12) /* Bit: 12 PWM23 Initial Value */ @@ -1070,12 +1074,14 @@ # define SMCTRL_PRSC_DIV32 (5 << SMCTRL_PRSC_SHIFT) /* PWM clock frequency = fclk/32 */ # define SMCTRL_PRSC_DIV64 (6 << SMCTRL_PRSC_SHIFT) /* PWM clock frequency = fclk/64 */ # define SMCTRL_PRSC_DIV128 (7 << SMCTRL_PRSC_SHIFT) /* PWM clock frequency = fclk/128*/ + #define SMCTRL_COMPMODE (1 << 7) /* Bit: 7 Compare Mode */ #define SMCTRL_DT_SHIFT (8) /* Bits: 8-9 Deadtime */ #define SMCTRL_DT_MASK (3 << SMCTRL_DT_SHIFT) # define SMCTRL_DT(n) ((uint32_t)(n) << SMCTRL_DT_SHIFT) # define SMCTRL_DT0 (1 << SMCTRL_DT_SHIFT) /* Read Only. These read only bits reflect the sampled values of the PWM_X input */ # define SMCTRL_DT1 (2 << SMCTRL_DT_SHIFT) /* Sampling occurs at the end of deadtime 0 for DT[0] and the end of deadtime 1 for DT[1]. */ + #define SMCTRL_FULL (1 << 10) /* Bit: 10 Full Cycle Reload */ #define SMCTRL_HALF (1 << 11) /* Bit: 11 Half Cycle Reload */ #define SMCTRL_LDFQ_SHIFT (12) /* Bits: 12-15 Load Frequency */ @@ -1091,12 +1097,12 @@ # define SMCTRL_LDFQ_EVERY8 (7 << SMCTRL_LDFQ_SHIFT) /* Every 8 PWM opportunities */ # define SMCTRL_LDFQ_EVERY9 (8 << SMCTRL_LDFQ_SHIFT) /* Every 9 PWM opportunities */ # define SMCTRL_LDFQ_EVERY10 (9 << SMCTRL_LDFQ_SHIFT) /* Every 10 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY11 (10 << SMCTRL_LDFQ_SHIFT) /* Every 11 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY12 (11 << SMCTRL_LDFQ_SHIFT) /* Every 12 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY13 (12 << SMCTRL_LDFQ_SHIFT) /* Every 13 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY14 (13 << SMCTRL_LDFQ_SHIFT) /* Every 14 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY15 (14 << SMCTRL_LDFQ_SHIFT) /* Every 15 PWM opportunities */ -# define SMCTRL_LDFQ_EVERY16 (0xf << SMCTRL_LDFQ_SHIFT) /* Every 16 PWM opportunities */ +# define SMCTRL_LDFQ_EVERY11 (10 << SMCTRL_LDFQ_SHIFT) /* Every 11 PWM opportunities */ +# define SMCTRL_LDFQ_EVERY12 (11 << SMCTRL_LDFQ_SHIFT) /* Every 12 PWM opportunities */ +# define SMCTRL_LDFQ_EVERY13 (12 << SMCTRL_LDFQ_SHIFT) /* Every 13 PWM opportunities */ +# define SMCTRL_LDFQ_EVERY14 (13 << SMCTRL_LDFQ_SHIFT) /* Every 14 PWM opportunities */ +# define SMCTRL_LDFQ_EVERY15 (14 << SMCTRL_LDFQ_SHIFT) /* Every 15 PWM opportunities */ +# define SMCTRL_LDFQ_EVERY16 (0xf << SMCTRL_LDFQ_SHIFT) /* Every 16 PWM opportunities */ /* Fractional Value Register 1 */ @@ -1148,19 +1154,23 @@ # define SMOCTRL_PWMXFS_0 (0 << SMOCTRL_PWMXFS_SHIFT) /* Output is forced to logic 0 state prior to consideration of output polarity control. */ # define SMOCTRL_PWMXFS_1 (1 << SMOCTRL_PWMXFS_SHIFT) /* Output is forced to logic 1 state prior to consideration of output polarity control. */ # define SMOCTRL_PWMXFS_TRISTATE (2 << SMOCTRL_PWMXFS_SHIFT) /* Output is tristated. */ + #define SMOCTRL_PWMBFS_SHIFT (2) /* Bits: 2-3 PWM_B Fault State */ #define SMOCTRL_PWMBFS_MASK (3 << SMOCTRL_PWMBFS_SHIFT) # define SMOCTRL_PWMBFS(n) ((uint32_t)(n) << SMOCTRL_PWMBFS_SHIFT) # define SMOCTRL_PWMBFS_0 (0 << SMOCTRL_PWMBFS_SHIFT) /* Output is forced to logic 0 state prior to consideration of output polarity control. */ # define SMOCTRL_PWMBFS_1 (1 << SMOCTRL_PWMBFS_SHIFT) /* Output is forced to logic 1 state prior to consideration of output polarity control. */ # define SMOCTRL_PWMBFS_TRISTATE (2 << SMOCTRL_PWMBFS_SHIFT) /* Output is tristated. */ + #define SMOCTRL_PWMAFS_SHIFT (4) /* Bits: 4-5 PWM_A Fault State */ #define SMOCTRL_PWMAFS_MASK (3 << SMOCTRL_PWMAFS_SHIFT) # define SMOCTRL_PWMAFS(n) ((uint32_t)(n) << SMOCTRL_PWMAFS_SHIFT) # define SMOCTRL_PWMAFS_0 (0 << SMOCTRL_PWMAFS_SHIFT) /* Output is forced to logic 0 state prior to consideration of output polarity control. */ # define SMOCTRL_PWMAFS_1 (1 << SMOCTRL_PWMAFS_SHIFT) /* Output is forced to logic 1 state prior to consideration of output polarity control. */ # define SMOCTRL_PWMAFS_TRISTATE (2 << SMOCTRL_PWMAFS_SHIFT) /* Output is tristated. */ - /* Bits: 6-7 Reserved */ + + /* Bits: 6-7 Reserved */ + #define SMOCTRL_POLX (1 << 8) /* Bit: 8 PWM_X Output Polarity */ #define SMOCTRL_POLB (1 << 9) /* Bit: 9 PWM_B Output Polarity */ #define SMOCTRL_POLA (1 << 10) /* Bit: 10 PWM_A Output Polarity */ @@ -1180,6 +1190,7 @@ # define SMSTS_CMPF_VAL3 (8 << SMSTS_CMPF_SHIFT) /* A compare event has occurred for VAL3 value */ # define SMSTS_CMPF_VAL4 (16 << SMSTS_CMPF_SHIFT) /* A compare event has occurred for VAL4 value */ # define SMSTS_CMPF_VAL5 (32 << SMSTS_CMPF_SHIFT) /* A compare event has occurred for VAL5 value */ + #define SMSTS_CFX0 (1 << 6) /* Bit: 6 Capture Flag X0 */ #define SMSTS_CFX1 (1 << 7) /* Bit: 7 Capture Flag X1 */ #define SMSTS_CFB0 (1 << 8) /* Bit: 8 Capture Flag B0 */ @@ -1188,8 +1199,10 @@ #define SMSTS_CFA1 (1 << 11) /* Bit: 11 Capture Flag A1 */ #define SMSTS_RF (1 << 12) /* Bit: 12 Reload Flag */ #define SMSTS_REF (1 << 13) /* Bit: 13 Reload Error Flag */ -#define SMSTS_RUF (1 << 14) /* Bit: 14 This read-only flag is set when one of the INIT, VALx,FRACVALx, or CTRL[PRSC] is written */ - /* Bit: 15 Reserved */ +#define SMSTS_RUF (1 << 14) /* Bit: 14 This read-only flag is set when one of the INIT, + * VALx,FRACVALx, or CTRL[PRSC] is written */ + + /* Bit: 15 Reserved */ /* Interrupt Enable Register */ @@ -1200,8 +1213,9 @@ # define SMINTEN_CMPIE_VAL1 (2 << SMINTEN_CMPIE_SHIFT) /* A compare event for VAL1 value will generate an interrupt */ # define SMINTEN_CMPIE_VAL2 (4 << SMINTEN_CMPIE_SHIFT) /* A compare event for VAL2 value will generate an interrupt */ # define SMINTEN_CMPIE_VAL3 (8 << SMINTEN_CMPIE_SHIFT) /* A compare event for VAL3 value will generate an interrupt */ -# define SMINTEN_CMPIE_VAL4 (16 << SMINTEN_CMPIE_SHIFT) /* A compare event for VAL4 value will generate an interrupt */ -# define SMINTEN_CMPIE_VAL5 (32 << SMINTEN_CMPIE_SHIFT) /* A compare event for VAL5 value will generate an interrupt */ +# define SMINTEN_CMPIE_VAL4 (16 << SMINTEN_CMPIE_SHIFT) /* A compare event for VAL4 value will generate an interrupt */ +# define SMINTEN_CMPIE_VAL5 (32 << SMINTEN_CMPIE_SHIFT) /* A compare event for VAL5 value will generate an interrupt */ + #define SMINTEN_CX0IE (1 << 6) /* Bit: 6 Capture X 0 Interrupt Enable */ #define SMINTEN_CX1IE (1 << 7) /* Bit: 7 Capture X 1 Interrupt Enable */ #define SMINTEN_CB0IE (1 << 8) /* Bit: 8 Capture B 0 Interrupt Enable */ @@ -1210,7 +1224,8 @@ #define SMINTEN_CA1IE (1 << 11) /* Bit: 11 Capture A 1 Interrupt Enable */ #define SMINTEN_RIE (1 << 12) /* Bit: 12 Reload Interrupt Enable */ #define SMINTEN_REIE (1 << 13) /* Bit: 13 Reload Error Interrupt Enable */ - /* Bits: 14-15 Reserved */ + + /* Bits: 14-15 Reserved */ /* DMA Enable Register */ @@ -1227,9 +1242,11 @@ # define SMDMAEN_CAPTDE_WMT (1 << SMDMAEN_CAPTDE_SHIFT) /* Exceeding a FIFO watermark sets the DMA read request. */ # define SMDMAEN_CAPTDE_SYNC (2 << SMDMAEN_CAPTDE_SHIFT) /* A local sync (VAL1 matches counter) sets the read DMA request. */ # define SMDMAEN_CAPTDE_RELOAD (3 << SMDMAEN_CAPTDE_SHIFT) /* A local reload (STS[RF] being set) sets the read DMA request. */ + #define SMDMAEN_FAND (1 << 8) /* Bit: 8 FIFO Watermark AND Control */ #define SMDMAEN_VALDE (1 << 9) /* Bit: 9 Value Registers DMA Enable */ - /* Bits: 10-15 Reserved */ + + /* Bits: 10-15 Reserved */ /* Output Trigger Control Register */ @@ -1242,7 +1259,9 @@ # define SMT_OUT_TRIG_EN_VAL3 (8 << SMT_OUT_TRIG_EN_SHIFT) /* PWM_OUT_TRIGx will set when the counter value matches the VAL3 value */ # define SMT_OUT_TRIG_EN_VAL4 (16 << SMT_OUT_TRIG_EN_SHIFT) /* PWM_OUT_TRIGx will set when the counter value matches the VAL4 value */ # define SMT_OUT_TRIG_EN_VAL5 (32 << SMT_OUT_TRIG_EN_SHIFT) /* PWM_OUT_TRIGx will set when the counter value matches the VAL5 value */ - /* Bits: 6-11 Reserved */ + + /* Bits: 6-11 Reserved */ + #define SMT_TRGFRQ (1 << 12) /* Bit: 12 Trigger frequency */ /* Bit: 13 Reserved */ #define SMT_PWBOT1 (1 << 14) /* Bit: 14 Output Trigger 1 Source Select */ @@ -1261,6 +1280,7 @@ # define SMD_DIS0A_FAULT1 (2 << SMD_DIS0A_SHIFT) /* FAULT1 inputs of fault channel 0. */ # define SMD_DIS0A_FAULT2 (4 << SMD_DIS0A_SHIFT) /* FAULT2 inputs of fault channel 0. */ # define SMD_DIS0A_FAULT3 (8 << SMD_DIS0A_SHIFT) /* FAULT3 inputs of fault channel 0. */ + #define SMD_DIS0B_SHIFT (4) /* Bits: 4-7 PWM_B Fault Disable Mask 0 */ #define SMD_DIS0B_MASK (0xf << SMD_DIS0B_SHIFT) # define SMD_DIS0B(n) ((uint32_t)(n) << SMD_DIS0B_SHIFT) @@ -1268,6 +1288,7 @@ # define SMD_DIS0B_FAULT1 (2 << SMD_DIS0B_SHIFT) /* FAULT1 inputs of fault channel 0. */ # define SMD_DIS0B_FAULT2 (4 << SMD_DIS0B_SHIFT) /* FAULT2 inputs of fault channel 0. */ # define SMD_DIS0B_FAULT3 (8 << SMD_DIS0B_SHIFT) /* FAULT3 inputs of fault channel 0. */ + #define SMD_DIS0X_SHIFT (8) /* Bits: 8-11 PWM_X Fault Disable Mask 0 */ #define SMD_DIS0X_MASK (0xf << SMD_DIS0X_SHIFT) # define SMD_DIS0X(n) ((uint32_t)(n) << SMD_DIS0X_SHIFT) @@ -1275,7 +1296,8 @@ # define SMD_DIS0X_FAULT1 (2 << SMD_DIS0X_SHIFT) /* FAULT1 inputs of fault channel 0. */ # define SMD_DIS0X_FAULT2 (4 << SMD_DIS0X_SHIFT) /* FAULT2 inputs of fault channel 0. */ # define SMD_DIS0X_FAULT3 (8 << SMD_DIS0X_SHIFT) /* FAULT3 inputs of fault channel 0. */ - /* Bits: 12-15 Reserved */ + + /* Bits: 12-15 Reserved */ /* Fault Disable Mapping Register 1 */ @@ -1286,6 +1308,7 @@ # define SMD_DIS1A_FAULT1 (2 << SMD_DIS1A_SHIFT) /* FAULT1 inputs of fault channel 1. */ # define SMD_DIS1A_FAULT2 (4 << SMD_DIS1A_SHIFT) /* FAULT2 inputs of fault channel 1. */ # define SMD_DIS1A_FAULT3 (8 << SMD_DIS1A_SHIFT) /* FAULT3 inputs of fault channel 1. */ + #define SMD_DIS1B_SHIFT (4) /* Bits: 4-7 PWM_B Fault Disable Mask 1 */ #define SMD_DIS1B_MASK (0xf << SMD_DIS1B_SHIFT) # define SMD_DIS1B(n) ((uint32_t)(n) << SMD_DIS1B_SHIFT) @@ -1293,6 +1316,7 @@ # define SMD_DIS1B_FAULT1 (2 << SMD_DIS1B_SHIFT) /* FAULT1 inputs of fault channel 1. */ # define SMD_DIS1B_FAULT2 (4 << SMD_DIS1B_SHIFT) /* FAULT2 inputs of fault channel 1. */ # define SMD_DIS1B_FAULT3 (8 << SMD_DIS1B_SHIFT) /* FAULT3 inputs of fault channel 1. */ + #define SMD_DIS1X_SHIFT (8) /* Bits: 8-11 PWM_X Fault Disable Mask 1 */ #define SMD_DIS1X_MASK (0xf << SMD_DIS1X_SHIFT) # define SMD_DIS1X(n) ((uint32_t)(n) << SMD_DIS1X_SHIFT) @@ -1300,7 +1324,8 @@ # define SMD_DIS1X_FAULT1 (2 << SMD_DIS1X_SHIFT) /* FAULT1 inputs of fault channel 1. */ # define SMD_DIS1X_FAULT2 (4 << SMD_DIS1X_SHIFT) /* FAULT2 inputs of fault channel 1. */ # define SMD_DIS1X_FAULT3 (8 << SMD_DIS1X_SHIFT) /* FAULT3 inputs of fault channel 1. */ - /* Bits: 12-15 Reserved */ + + /* Bits: 12-15 Reserved */ /* Capture Control A Register */ @@ -1313,6 +1338,7 @@ # define SMC_EDGA0_FALLING (1 << SMC_EDGA0_SHIFT) /* Capture falling edges */ # define SMC_EDGA0_RISING (2 << SMC_EDGA0_SHIFT) /* Capture rising edges */ # define SMC_EDGA0_BOTH (3 << SMC_EDGA0_SHIFT) /* Capture any edge */ + #define SMC_EDGA1_SHIFT (4) /* Bits: 4-5 Edge A 1 */ #define SMC_EDGA1_MASK (3 << SMC_EDGA1_SHIFT) # define SMC_EDGA1(n) ((uint32_t)(n) << SMC_EDGA1_SHIFT) @@ -1320,6 +1346,7 @@ # define SMC_EDGA1_FALLING (1 << SMC_EDGA1_SHIFT) /* Capture falling edges */ # define SMC_EDGA1_RISING (2 << SMC_EDGA1_SHIFT) /* Capture rising edges */ # define SMC_EDGA1_BOTH (3 << SMC_EDGA1_SHIFT) /* Capture any edge */ + #define SMC_INP_SELA (1 << 6) /* Bit: 6 Input Select A */ #define SMC_EDGCNTA_EN (1 << 7) /* Bit: 7 Edge Counter A Enable */ #define SMC_CFAWM_SHIFT (8) /* Bits: 8-9 Capture A FIFOs Water Mark */ @@ -1329,6 +1356,7 @@ # define SMC_CFAWM_2 (1 << SMC_CFAWM_SHIFT) /* Water mark level of 2 for capture A FIFOs */ # define SMC_CFAWM_3 (2 << SMC_CFAWM_SHIFT) /* Water mark level of 3 for capture A FIFOs */ # define SMC_CFAWM_4 (3 << SMC_CFAWM_SHIFT) /* Water mark level of 4 for capture A FIFOs */ + #define SMC_CA0CNT_SHIFT (10) /* Bits: 10-12 Capture A0 FIFO Word Count */ #define SMC_CA0CNT_MASK (7 << SMC_CA0CNT_SHIFT) # define SMC_CA0CNT(n) ((uint32_t)(n) << SMC_CA0CNT_SHIFT) @@ -1340,6 +1368,7 @@ # define SMC_CA0CNT_05 (5 << SMC_CA0CNT_SHIFT) /* 5 words in the Capture A0 FIFO. */ # define SMC_CA0CNT_06 (6 << SMC_CA0CNT_SHIFT) /* 6 words in the Capture A0 FIFO. */ # define SMC_CA0CNT_07 (7 << SMC_CA0CNT_SHIFT) /* 7 words in the Capture A0 FIFO. */ + #define SMC_CA1CNT_SHIFT (13) /* Bits: 13-15 Capture A1 FIFO Word Count */ #define SMC_CA1CNT_MASK (7 << SMC_CA1CNT_SHIFT) # define SMC_CA1CNT(n) ((uint32_t)(n) << SMC_CA1CNT_SHIFT) @@ -1372,6 +1401,7 @@ # define SMC_EDGB0_FALLING (1 << SMC_EDGB0_SHIFT) /* Capture falling edges */ # define SMC_EDGB0_RISING (2 << SMC_EDGB0_SHIFT) /* Capture rising edges */ # define SMC_EDGB0_BOTH (3 << SMC_EDGB0_SHIFT) /* Capture any edge */ + #define SMC_EDGB1_SHIFT (4) /* Bits: 4-5 Edge B 1 */ #define SMC_EDGB1_MASK (3 << SMC_EDGB1_SHIFT) # define SMC_EDGB1(n) ((uint32_t)(n) << SMC_EDGB1_SHIFT) @@ -1379,6 +1409,7 @@ # define SMC_EDGB1_FALLING (1 << SMC_EDGB1_SHIFT) /* Capture falling edges */ # define SMC_EDGB1_RISING (2 << SMC_EDGB1_SHIFT) /* Capture rising edges */ # define SMC_EDGB1_BOTH (3 << SMC_EDGB1_SHIFT) /* Capture any edge */ + #define SMC_INP_SELB (1 << 6) /* Bit: 6 Input Select B */ #define SMC_EDGCNTB_EN (1 << 7) /* Bit: 7 Edge Counter B Enable */ #define SMC_CFBWM_SHIFT (8) /* Bits: 8-9 Capture B FIFOs Water Mark */ @@ -1388,6 +1419,7 @@ # define SMC_CFBWM_1 (1 << SMC_CFBWM_SHIFT) /* Water mark level of 2 for capture B FIFOs */ # define SMC_CFBWM_2 (2 << SMC_CFBWM_SHIFT) /* Water mark level of 3 for capture B FIFOs */ # define SMC_CFBWM_3 (3 << SMC_CFBWM_SHIFT) /* Water mark level of 4 for capture B FIFOs */ + #define SMC_CB0CNT_SHIFT (10) /* Bits: 10-12 Capture B0 FIFO Word Count */ #define SMC_CB0CNT_MASK (7 << SMC_CB0CNT_SHIFT) # define SMC_CB0CNT(n) ((uint32_t)(n) << SMC_CB0CNT_SHIFT) @@ -1399,6 +1431,7 @@ # define SMC_CB0CNT_05 (5 << SMC_CB0CNT_SHIFT) /* 5 words in the Capture B0 FIFO. */ # define SMC_CB0CNT_06 (6 << SMC_CB0CNT_SHIFT) /* 6 words in the Capture B0 FIFO. */ # define SMC_CB0CNT_07 (7 << SMC_CB0CNT_SHIFT) /* 7 words in the Capture B0 FIFO. */ + #define SMC_CB1CNT_SHIFT (13) /* Bits: 13-15 Capture B1 FIFO Word Count */ #define SMC_CB1CNT_MASK (7 << SMC_CB1CNT_SHIFT) # define SMC_CB1CNT(n) ((uint32_t)(n) << SMC_CB1CNT_SHIFT) @@ -1431,6 +1464,7 @@ # define SMC_EDGX0_FALLING (1 << SMC_EDGX0_SHIFT) /* Capture falling edges */ # define SMC_EDGX0_RISING (2 << SMC_EDGX0_SHIFT) /* Capture rising edges */ # define SMC_EDGX0_BOTH (3 << SMC_EDGX0_SHIFT) /* Capture any edge */ + #define SMC_EDGX1_SHIFT (4) /* Bits: 4-5 Edge X 1 */ #define SMC_EDGX1_MASK (3 << SMC_EDGX1_SHIFT) # define SMC_EDGX1(n) ((uint32_t)(n) << SMC_EDGX1_SHIFT) @@ -1438,6 +1472,7 @@ # define SMC_EDGX1_FALLING (1 << SMC_EDGX1_SHIFT) /* Capture falling edges */ # define SMC_EDGX1_RISING (2 << SMC_EDGX1_SHIFT) /* Capture rising edges */ # define SMC_EDGX1_BOTH (3 << SMC_EDGX1_SHIFT) /* Capture any edge */ + #define SMC_INP_SELX (1 << 6) /* Bit: 6 Input Select X */ #define SMC_EDGCNTX_EN (1 << 7) /* Bit: 7 Edge Counter X Enable */ #define SMC_CFXWM_SHIFT (8) /* Bits: 8-9 Capture X FIFOs Water Mark */ @@ -1447,6 +1482,7 @@ # define SMC_CFXWM_2 (1 << SMC_CFXWM_SHIFT) /* Water mark level of 2 for capture X FIFOs */ # define SMC_CFXWM_3 (2 << SMC_CFXWM_SHIFT) /* Water mark level of 3 for capture X FIFOs */ # define SMC_CFXWM_4 (3 << SMC_CFXWM_SHIFT) /* Water mark level of 4 for capture X FIFOs */ + #define SMC_CX0CNT_SHIFT (10) /* Bits: 10-12 Capture X0 FIFO Word Count */ #define SMC_CX0CNT_MASK (7 << SMC_CX0CNT_SHIFT) # define SMC_CX0CNT(n) ((uint32_t)(n) << SMC_CX0CNT_SHIFT) @@ -1458,6 +1494,7 @@ # define SMC_CX0CNT_05 (5 << SMC_CX0CNT_SHIFT) /* 5 words in the Capture X0 FIFO. */ # define SMC_CX0CNT_06 (6 << SMC_CX0CNT_SHIFT) /* 6 words in the Capture X0 FIFO. */ # define SMC_CX0CNT_07 (7 << SMC_CX0CNT_SHIFT) /* 7 words in the Capture X0 FIFO. */ + #define SMC_CX1CNT_SHIFT (13) /* Bits: 13-15 Capture X1 FIFO Word Count */ #define SMC_CX1CNT_MASK (7 << SMC_CX1CNT_SHIFT) # define SMC_CX1CNT(n) ((uint32_t)(n) << SMC_CX1CNT_SHIFT) @@ -1525,7 +1562,9 @@ # define OUTEN_PWMX_EN_SM1 (2 << OUTEN_PWMX_EN_SHIFT) /* Enable the PWM_X outputs of submodules 1 */ # define OUTEN_PWMX_EN_SM2 (4 << OUTEN_PWMX_EN_SHIFT) /* Enable the PWM_X outputs of submodules 2 */ # define OUTEN_PWMX_EN_SM3 (8 << OUTEN_PWMX_EN_SHIFT) /* Enable the PWM_X outputs of submodules 3 */ + # define OUTEN_PWMX_EN_ALL (0xf << OUTEN_PWMX_EN_SHIFT) /* All enabled */ + #define OUTEN_PWMB_EN_SHIFT (4) /* Bits: 4-7 PWM_B Output Enables */ #define OUTEN_PWMB_EN_MASK (0xf << OUTEN_PWMB_EN_SHIFT) # define OUTEN_PWMB_EN(n) ((uint32_t)(n) << OUTEN_PWMB_EN_SHIFT) @@ -1534,7 +1573,9 @@ # define OUTEN_PWMB_EN_SM1 (2 << OUTEN_PWMB_EN_SHIFT) /* Enable the PWM_B outputs of submodules 1 */ # define OUTEN_PWMB_EN_SM2 (4 << OUTEN_PWMB_EN_SHIFT) /* Enable the PWM_B outputs of submodules 2 */ # define OUTEN_PWMB_EN_SM3 (8 << OUTEN_PWMB_EN_SHIFT) /* Enable the PWM_B outputs of submodules 3 */ + # define OUTEN_PWMB_EN_ALL (0xf << OUTEN_PWMB_EN_SHIFT) /* All enabled */ + #define OUTEN_PWMA_EN_SHIFT (8) /* Bits: 8-11 PWM_A Output Enables */ #define OUTEN_PWMA_EN_MASK (0xf << OUTEN_PWMA_EN_SHIFT) # define OUTEN_PWMA_EN(n) ((uint32_t)(n) << OUTEN_PWMA_EN_SHIFT) @@ -1543,8 +1584,10 @@ # define OUTEN_PWMA_EN_SM1 (2 << OUTEN_PWMA_EN_SHIFT) /* Enable the PWM_A outputs of submodules 1 */ # define OUTEN_PWMA_EN_SM2 (4 << OUTEN_PWMA_EN_SHIFT) /* Enable the PWM_A outputs of submodules 2 */ # define OUTEN_PWMA_EN_SM3 (8 << OUTEN_PWMA_EN_SHIFT) /* Enable the PWM_A outputs of submodules 3 */ + # define OUTEN_PWMA_EN_ALL (0xf << OUTEN_PWMA_EN_SHIFT) /* All enabled */ - /* Bits: 12-15 Reserved */ + + /* Bits: 12-15 Reserved */ /* Mask Register */ @@ -1555,6 +1598,7 @@ # define MASK_MASKX_SM1 (2 << MASK_MASKX_SHIFT) /* Mask the PWM_X outputs of submodules 1 (forces output to 0) */ # define MASK_MASKX_SM2 (4 << MASK_MASKX_SHIFT) /* Mask the PWM_X outputs of submodules 2 (forces output to 0) */ # define MASK_MASKX_SM3 (8 << MASK_MASKX_SHIFT) /* Mask the PWM_X outputs of submodules 3 (forces output to 0) */ + #define MASK_MASKB_SHIFT (4) /* Bits: 4-7 PWM_B Masks */ #define MASK_MASKB_MASK (0xf << MASK_MASKB_SHIFT) # define MASK_MASKB(n) ((uint32_t)(n) << MASK_MASKB_SHIFT) @@ -1562,6 +1606,7 @@ # define MASK_MASKB_SM1 (2 << MASK_MASKB_SHIFT) /* Mask the PWM_B outputs of submodules 1 (forces output to 0) */ # define MASK_MASKB_SM2 (4 << MASK_MASKB_SHIFT) /* Mask the PWM_B outputs of submodules 2 (forces output to 0) */ # define MASK_MASKB_SM3 (8 << MASK_MASKB_SHIFT) /* Mask the PWM_B outputs of submodules 3 (forces output to 0) */ + #define MASK_MASKA_SHIFT (8) /* Bits: 8-11 PWM_A Masks */ #define MASK_MASKA_MASK (0xf << MASK_MASKB_SHIFT) # define MASK_MASKA(n) ((uint32_t)(n) << MASK_MASKA_SHIFT) @@ -1569,6 +1614,7 @@ # define MASK_MASKA_SM1 (2 << MASK_MASKA_SHIFT) /* Mask the PWM_A outputs of submodules 1 (forces output to 0) */ # define MASK_MASKA_SM2 (4 << MASK_MASKA_SHIFT) /* Mask the PWM_A outputs of submodules 2 (forces output to 0) */ # define MASK_MASKA_SM3 (8 << MASK_MASKA_SHIFT) /* Mask the PWM_A outputs of submodules 3 (forces output to 0) */ + #define MASK_UPDATE_MASK_SHIFT (12) /* Bits: 12-15 Update Mask Bits Immediately */ #define MASK_UPDATE_MASK_MASK (0xf << MASK_UPDATE_MASK_SHIFT) # define MASK_UPDATE_MASK(n) ((uint32_t)(n) << MASK_UPDATE_MASK_SHIFT) @@ -1591,7 +1637,7 @@ /* PWM Source Select Register */ -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ #define DTSRCSEL_SM0SEL45_SHIFT (0) /* Bits: 0-1 Submodule 0 PWM45 Control Select */ #define DTSRCSEL_SM0SEL45_MASK (3 << DTSRCSEL_SM0SEL45_SHIFT) @@ -1600,6 +1646,7 @@ # define DTSRCSEL_SM0SEL45_INVERT (1 << DTSRCSEL_SM0SEL45_SHIFT) /* Inverted generated SM0PWM45 signal is used by the deadtime logic. */ # define DTSRCSEL_SM0SEL45_SWCOUT (2 << DTSRCSEL_SM0SEL45_SHIFT) /* SWCOUT[SM0OUT45] is used by the deadtime logic. */ # define DTSRCSEL_SM0SEL45_PWM0_EXTB (3 << DTSRCSEL_SM0SEL45_SHIFT) /* PWM0_EXTB signal is used by the deadtime logic. */ + #define DTSRCSEL_SM0SEL23_SHIFT (2) /* Bits: 2-3 Submodule 0 PWM23 Control Select */ #define DTSRCSEL_SM0SEL23_MASK (3 << DTSRCSEL_SM0SEL23_SHIFT) # define DTSRCSEL_SM0SEL23(n) ((uint32_t)(n) << DTSRCSEL_SM0SEL23_SHIFT) @@ -1607,6 +1654,7 @@ # define DTSRCSEL_SM0SEL23_INVERT (1 << DTSRCSEL_SM0SEL23_SHIFT) /* Inverted generated SM0PWM23 signal is used by the deadtime logic. */ # define DTSRCSEL_SM0SEL23_SWCOUT (2 << DTSRCSEL_SM0SEL23_SHIFT) /* SWCOUT[SM0OUT23] is used by the deadtime logic. */ # define DTSRCSEL_SM0SEL23_PWM0_EXTA (3 << DTSRCSEL_SM0SEL23_SHIFT) /* PWM0_EXTA signal is used by the deadtime logic. */ + #define DTSRCSEL_SM1SEL45_SHIFT (4) /* Bits: 4-5 Submodule 1 PWM45 Control Select */ #define DTSRCSEL_SM1SEL45_MASK (3 << DTSRCSEL_SM1SEL45_SHIFT) # define DTSRCSEL_SM1SEL45(n) ((uint32_t)(n) << DTSRCSEL_SM1SEL45_SHIFT) @@ -1614,6 +1662,7 @@ # define DTSRCSEL_SM1SEL45_INVERT (1 << DTSRCSEL_SM1SEL45_SHIFT) /* Inverted generated SM1PWM45 signal is used by the deadtime logic. */ # define DTSRCSEL_SM1SEL45_SWCOUT (2 << DTSRCSEL_SM1SEL45_SHIFT) /* SWCOUT[SM1OUT45] is used by the deadtime logic. */ # define DTSRCSEL_SM1SEL45_PWM1_EXTB (3 << DTSRCSEL_SM1SEL45_SHIFT) /* PWM1_EXTB signal is used by the deadtime logic. */ + #define DTSRCSEL_SM1SEL23_SHIFT (6) /* Bits: 6-7 Submodule 1 PWM23 Control Select */ #define DTSRCSEL_SM1SEL23_MASK (3 << DTSRCSEL_SM1SEL23_SHIFT) # define DTSRCSEL_SM1SEL23(n) ((uint32_t)(n) << DTSRCSEL_SM1SEL23_SHIFT) @@ -1621,6 +1670,7 @@ # define DTSRCSEL_SM1SEL23_INVERT (1 << DTSRCSEL_SM1SEL23_SHIFT) /* Inverted generated SM1PWM23 signal is used by the deadtime logic. */ # define DTSRCSEL_SM1SEL23_SWCOUT (2 << DTSRCSEL_SM1SEL23_SHIFT) /* SWCOUT[SM1OUT23] is used by the deadtime logic. */ # define DTSRCSEL_SM1SEL23_PWM1_EXTA (3 << DTSRCSEL_SM1SEL23_SHIFT) /* PWM1_EXTA signal is used by the deadtime logic */ + #define DTSRCSEL_SM2SEL45_SHIFT (8) /* Bits: 8-9 Submodule 2 PWM45 Control Select */ #define DTSRCSEL_SM2SEL45_MASK (3 << DTSRCSEL_SM2SEL45_SHIFT) # define DTSRCSEL_SM2SEL45(n) ((uint32_t)(n) << DTSRCSEL_SM2SEL45_SHIFT) @@ -1628,6 +1678,7 @@ # define DTSRCSEL_SM2SEL45_INVERT (1 << DTSRCSEL_SM2SEL45_SHIFT) /* Inverted generated SM2PWM45 signal is used by the deadtime logic. */ # define DTSRCSEL_SM2SEL45_SWCOUT (2 << DTSRCSEL_SM2SEL45_SHIFT) /* SWCOUT[SM2OUT45] is used by the deadtime logic. */ # define DTSRCSEL_SM2SEL45_PWM2_EXTB (3 << DTSRCSEL_SM2SEL45_SHIFT) /* PWM2_EXTB signal is used by the deadtime logic. */ + #define DTSRCSEL_SM2SEL23_SHIFT (10) /* Bits: 10-11 Submodule 2 PWM23 Control Select */ #define DTSRCSEL_SM2SEL23_MASK (3 << DTSRCSEL_SM2SEL23_SHIFT) # define DTSRCSEL_SM2SEL23(n) ((uint32_t)(n) << DTSRCSEL_SM2SEL23_SHIFT) @@ -1635,6 +1686,7 @@ # define DTSRCSEL_SM2SEL23_INVERT (1 << DTSRCSEL_SM2SEL23_SHIFT) /* Inverted generated SM2PWM23 signal is used by the deadtime logic. */ # define DTSRCSEL_SM2SEL23_SWCOUT (2 << DTSRCSEL_SM2SEL23_SHIFT) /* SWCOUT[SM2OUT23] is used by the deadtime logic. */ # define DTSRCSEL_SM2SEL23_PWM2_EXTA (3 << DTSRCSEL_SM2SEL23_SHIFT) /* PWM2_EXTA signal is used by the deadtime logic */ + #define DTSRCSEL_SM3SEL45_SHIFT (12) /* Bits: 12-13 Submodule 3 PWM45 Control Select */ #define DTSRCSEL_SM3SEL45_MASK (3 << DTSRCSEL_SM3SEL45_SHIFT) # define DTSRCSEL_SM3SEL45(n) ((uint32_t)(n) << DTSRCSEL_SM3SEL45_SHIFT) @@ -1642,6 +1694,7 @@ # define DTSRCSEL_SM3SEL45_INVERT (1 << DTSRCSEL_SM3SEL45_SHIFT) /* Inverted generated SM3PWM45 signal is used by the deadtime logic. */ # define DTSRCSEL_SM3SEL45_SWCOUT (2 << DTSRCSEL_SM3SEL45_SHIFT) /* SWCOUT[SM3OUT45] is used by the deadtime logic. */ # define DTSRCSEL_SM3SEL45_PWM3_EXTB (3 << DTSRCSEL_SM3SEL45_SHIFT) /* PWM3_EXTB signal is used by the deadtime logic. */ + #define DTSRCSEL_SM3SEL23_SHIFT (14) /* Bits: 14-15 Submodule 3 PWM23 Control Select */ #define DTSRCSEL_SM3SEL23_MASK (3 << DTSRCSEL_SM3SEL23_SHIFT) # define DTSRCSEL_SM3SEL23(n) ((uint32_t)(n) << DTSRCSEL_SM3SEL23_SHIFT) @@ -1659,6 +1712,7 @@ # define MCTRL_LDOK_SM1 (2 << MCTRL_LDOK_SHIFT) /* Load prescaler, modulus, and PWM values of submodule 1 */ # define MCTRL_LDOK_SM2 (4 << MCTRL_LDOK_SHIFT) /* Load prescaler, modulus, and PWM values of submodule 2 */ # define MCTRL_LDOK_SM3 (8 << MCTRL_LDOK_SHIFT) /* Load prescaler, modulus, and PWM values of submodule 3 */ + #define MCTRL_CLDOK_SHIFT (4) /* Bits: 4-7 Clear Load Okay */ #define MCTRL_CLDOK_MASK (15 << MCTRL_CLDOK_SHIFT) # define MCTRL_CLDOK(n) ((uint32_t)(n) << MCTRL_CLDOK_SHIFT) @@ -1666,6 +1720,7 @@ # define MCTRL_CLDOK_SM1 (2 << MCTRL_CLDOK_SHIFT) /* Clear Load Okay of submodule 1 */ # define MCTRL_CLDOK_SM2 (4 << MCTRL_CLDOK_SHIFT) /* Clear Load Okay of submodule 2 */ # define MCTRL_CLDOK_SM3 (8 << MCTRL_CLDOK_SHIFT) /* Clear Load Okay of submodule 3 */ + #define MCTRL_RUN_SHIFT (8) /* Bits: 8-11 Run */ #define MCTRL_RUN_MASK (15 << MCTRL_RUN_SHIFT) # define MCTRL_RUN(n) ((uint32_t)(n) << MCTRL_RUN_SHIFT) @@ -1673,6 +1728,7 @@ # define MCTRL_RUN_SM1 (2 << MCTRL_RUN_SHIFT) /* Enable PWM generator of submodules 1 */ # define MCTRL_RUN_SM2 (4 << MCTRL_RUN_SHIFT) /* Enable PWM generator of submodules 2 */ # define MCTRL_RUN_SM3 (8 << MCTRL_RUN_SHIFT) /* Enable PWM generator of submodules 3 */ + #define MCTRL_IPOL_SHIFT (12) /* Bits: 12-15 Current Polarity */ #define MCTRL_IPOL_MASK (15 << MCTRL_IPOL_SHIFT) # define MCTRL_IPOL(n) ((uint32_t)(n) << MCTRL_IPOL_SHIFT) @@ -1683,7 +1739,7 @@ /* Master Control 2 Register */ -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ #define MCTRL2_MONPLL_SHIFT (0) /* Bits: 0-1 Monitor PLL State */ #define MCTRL2_MONPLL_MASK (3 << MCTRL2_MONPLL_SHIFT) @@ -1703,6 +1759,7 @@ # define FCTRL_FIE_FAULT1 (2 << FCTRL_FIE_SHIFT) /* FAULT1 Safe mode. PWM outputs disabled by this fault */ # define FCTRL_FIE_FAULT2 (4 << FCTRL_FIE_SHIFT) /* FAULT2 Safe mode. PWM outputs disabled by this fault */ # define FCTRL_FIE_FAULT3 (8 << FCTRL_FIE_SHIFT) /* FAULT3 Safe mode. PWM outputs disabled by this fault */ + #define FCTRL0_FSAFE_SHIFT (4) /* Bits: 4-7 Fault Safety Mode */ #define FCTRL0_FSAFE_MASK (15 << FCTRL0_FSAFE_SHIFT) # define FCTRL0_FSAFE(n) ((uint32_t)(n) << FCTRL0_FSAFE_SHIFT) @@ -1711,6 +1768,7 @@ # define FCTRL0_FSAFE_FAULT1 (2 << FCTRL0_FSAFE_SHIFT) /* FAULT1 CPU interrupt requests enabled */ # define FCTRL0_FSAFE_FAULT2 (4 << FCTRL0_FSAFE_SHIFT) /* FAULT2 CPU interrupt requests enabled */ # define FCTRL0_FSAFE_FAULT3 (8 << FCTRL0_FSAFE_SHIFT) /* FAULT3 CPU interrupt requests enabled */ + #define FCTRL0_FAUTO_SHIFT (8) /* Bits: 8-11 Automatic Fault Clearing */ #define FCTRL0_FAUTO_MASK (15 << FCTRL0_FAUTO_SHIFT) # define FCTRL0_FAUTO(n) ((uint32_t)(n) << FCTRL0_FAUTO_SHIFT) @@ -1719,6 +1777,7 @@ # define FCTRL0_FAUTO_FAULT1 (2 << FCTRL0_FAUTO_SHIFT) /* FAULT1 Automatic fault clearing. */ # define FCTRL0_FAUTO_FAULT2 (4 << FCTRL0_FAUTO_SHIFT) /* FAULT2 Automatic fault clearing. */ # define FCTRL0_FAUTO_FAULT3 (8 << FCTRL0_FAUTO_SHIFT) /* FAULT3 Automatic fault clearing. */ + #define FCTRL0_FLVL_SHIFT (12) /* Bits: 12-15 Fault Level */ #define FCTRL0_FLVL_MASK (15 << FCTRL0_FLVL_SHIFT) # define FCTRL0_FLVL(n) ((uint32_t)(n) << FCTRL0_FLVL_SHIFT) @@ -1738,6 +1797,7 @@ # define FSTS_FFLAG_FAULT1 (2 << FSTS_FFLAG_SHIFT) /* Fault on the FAULT1 pin */ # define FSTS_FFLAG_FAULT2 (4 << FSTS_FFLAG_SHIFT) /* Fault on the FAULT2 pin */ # define FSTS_FFLAG_FAULT3 (8 << FSTS_FFLAG_SHIFT) /* Fault on the FAULT3 pin */ + #define FSTS_FFULL_SHIFT (4) /* Bits: 4-7 Full Cycle */ #define FSTS_FFULL_MASK (15 << FSTS_FFULL_SHIFT) # define FSTS_FFULL(n) ((uint32_t)(n) << FSTS_FFULL_SHIFT) @@ -1746,6 +1806,7 @@ # define FSTS_FFULL_SM1 (2 << FSTS_FFULL_SHIFT) /* SM1 PWM output is re-enabled at the start of a full cycle */ # define FSTS_FFULL_SM2 (4 << FSTS_FFULL_SHIFT) /* SM2 PWM output is re-enabled at the start of a full cycle */ # define FSTS_FFULL_SM3 (8 << FSTS_FFULL_SHIFT) /* SM3 PWM output is re-enabled at the start of a full cycle */ + #define FSTS_FFPIN_SHIFT (8) /* Bits: 8-11 Filtered Fault Pins */ #define FSTS_FFPIN_MASK (15 << FSTS_FFPIN_SHIFT) # define FSTS_FFPIN(n) ((uint32_t)(n) << FSTS_FFPIN_SHIFT) @@ -1754,6 +1815,7 @@ # define FSTS_FFPIN_FAULT1 (2 << FSTS_FFPIN_SHIFT) /* This read-only bit reflect the current state of the filtered FAULT1 pin */ # define FSTS_FFPIN_FAULT2 (4 << FSTS_FFPIN_SHIFT) /* This read-only bit reflect the current state of the filtered FAULT2 pin */ # define FSTS_FFPIN_FAULT3 (8 << FSTS_FFPIN_SHIFT) /* This read-only bit reflect the current state of the filtered FAULT3 pin */ + #define FSTS_FHALF_SHIFT (12) /* Bits: 12-15 Half Cycle Fault Recovery */ #define FSTS_FHALF_MASK (15 << FSTS_FHALF_SHIFT) # define FSTS_FHALF(n) ((uint32_t)(n) << FSTS_FHALF_SHIFT) @@ -1769,6 +1831,7 @@ #define FFILT_FILT_PER_MASK (0xff << FFILT_FILT_PER_SHIFT) # define FFILT_FILT_PER(n) ((uint32_t)(n) << FFILT_FILT_PER_SHIFT) #define FFILT_FILT_CNT_SHIFT (8) /* Bits: 8-10 Fault Filter Count */ + #define FFILT_FILT_CNT_MASK (7 << FFILT_FILT_CNT_SHIFT) # define FFILT_FILT_CNT(n) ((uint32_t)(n) << FFILT_FILT_CNT_SHIFT) # define FFILT_FILT_CNT_3 (0 << FFILT_FILT_CNT_SHIFT) /* */ @@ -1779,7 +1842,9 @@ # define FFILT_FILT_CNT_8 (5 << FFILT_FILT_CNT_SHIFT) /* */ # define FFILT_FILT_CNT_9 (6 << FFILT_FILT_CNT_SHIFT) /* */ # define FFILT_FILT_CNT_10 (7 << FFILT_FILT_CNT_SHIFT) /* */ - /* Bits: 11-14 Reserved */ + + /* Bits: 11-14 Reserved */ + #define FFILT_GSTR (1 << 15) /* Bit: 15 Fault Glitch Stretch Enable */ /* Fault Test Register */ @@ -1790,6 +1855,7 @@ /* Fault Control 2 Register */ #define FCTRL20_NOCOMB_SHIFT (0) /* Bits: 0-3 No Combinational Path From Fault Input To PWM Output */ + #define FCTRL20_NOCOMB_MASK (0xf << FCTRL20_NOCOMB_SHIFT) # define FCTRL20_NOCOMB(n) ((uint32_t)(n) << FCTRL20_NOCOMB_SHIFT) # define FCTRL20_NOCOMB_ALL_ENABLED (0 << FCTRL20_NOCOMB_SHIFT) /* All combinational link from the fault inputs to the PWM outputs are enabled */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_gpt.h b/arch/arm/src/imxrt/hardware/imxrt_gpt.h index 5dbae3cba0c..314d12e8f91 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_gpt.h +++ b/arch/arm/src/imxrt/hardware/imxrt_gpt.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_gpt.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_GPT_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_GPT_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define IMXRT_GPT_CR_OFFSET 0x0000 /* GPT Control Register */ #define IMXRT_GPT_PR_OFFSET 0x0004 /* GPT Prescaler Register */ @@ -45,7 +45,7 @@ #define IMXRT_GPT_ICR2_OFFSET 0x0020 /* GPT Input Capture Register 2 */ #define IMXRT_GPT_CNT_OFFSET 0x0024 /* GPT Counter Register */ -/* Register addresses ***********************************************************************/ +/* Register addresses *******************************************************/ #define IMXRT_GPT1_CR (IMXRT_GPT1_BASE + IMXRT_GPT1_CR_OFFSET) /* GPT 1 Control Register */ #define IMXRT_GPT1_PR (IMXRT_GPT1_BASE + IMXRT_GPT1_PR_OFFSET) /* GPT 1 Prescaler Register */ @@ -70,7 +70,7 @@ /* GPT Control Register */ -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ #define GPT_CR_EN (1 << 0) /* Bit: 0 GPT Enable. */ #define GPT_CR_ENMOD (1 << 1) /* Bit: 1 GPT Enable mode. */ @@ -87,6 +87,7 @@ # define GPT_CR_CLKSRC_EXT (3 << GPT_CR_CLKSRC_SHIFT) /* External Clock */ # define GPT_CR_CLKSRC_IPG_LFR (4 << GPT_CR_CLKSRC_SHIFT) /* Low Frequency Reference Clock (ipg_clk_32k) */ # define GPT_CR_CLKSRC_IPG_24M (5 << GPT_CR_CLKSRC_SHIFT) /* Crystal oscillator as Reference Clock (ipg_clk_24M) */ + #define GPT_CR_FRR (1 << 9) /* Bit: 9 Free-Run or Restart mode. */ #define GPT_CR_EN_24M (1 << 10) /* Bit: 10 Enable 24 MHz clock input from crystal. */ /* Bits: 11-14 Reserved */ @@ -98,6 +99,7 @@ # define GPT_CR_IM1_RISING (1 << GPT_CR_IM1_SHIFT) /* Capture on rising edge */ # define GPT_CR_IM1_FALLING (2 << GPT_CR_IM1_SHIFT) /* Capture on falling edge */ # define GPT_CR_IM1_BOTH (3 << GPT_CR_IM1_SHIFT) /* Capture on both edges */ + #define GPT_CR_IM2_SHIFT (18) /* Bits: 18-19 IM2 (bits 19-18, Input Capture Channel 2 operating mode) */ #define GPT_CR_IM2_MASK (3 << GPT_CR_IM2_SHIFT) # define GPT_CR_IM2(n) ((uint32_t)(n) << GPT_CR_IM2_SHIFT) @@ -105,6 +107,7 @@ # define GPT_CR_IM2_RISING (1 << GPT_CR_IM2_SHIFT) /* Capture on rising edge */ # define GPT_CR_IM2_FALLING (2 << GPT_CR_IM2_SHIFT) /* Capture on falling edge */ # define GPT_CR_IM2_BOTH (3 << GPT_CR_IM2_SHIFT) /* Capture on both edges */ + #define GPT_CR_OM1_SHIFT (20) /* Bits: 20-22 See OM3 */ #define GPT_CR_OM1_MASK (7 << GPT_CR_OM1_SHIFT) # define GPT_CR_OM1(n) ((uint32_t)(n) << GPT_CR_OM1_SHIFT) @@ -113,6 +116,7 @@ # define GPT_CR_OM1_CLEAR (2 << GPT_CR_OM1_SHIFT) /* Clear output pin */ # define GPT_CR_OM1_SET (3 << GPT_CR_OM1_SHIFT) /* Set output pin */ # define GPT_CR_OM1_PULSE (4 << GPT_CR_OM1_SHIFT) /* Generate an active low pulse */ + #define GPT_CR_OM2_SHIFT (23) /* Bits: 23-25 See OM3 */ #define GPT_CR_OM2_MASK (7 << GPT_CR_OM2_SHIFT) # define GPT_CR_OM2(n) ((uint32_t)(n) << GPT_CR_OM2_SHIFT) @@ -121,6 +125,7 @@ # define GPT_CR_OM2_CLEAR (2 << GPT_CR_OM2_SHIFT) /* Clear output pin */ # define GPT_CR_OM2_SET (3 << GPT_CR_OM2_SHIFT) /* Set output pin */ # define GPT_CR_OM2_PULSE (4 << GPT_CR_OM2_SHIFT) /* Generate an active low pulse */ + #define GPT_CR_OM3_SHIFT (26) /* Bits: 26-28 OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode. */ #define GPT_CR_OM3_MASK (7 << GPT_CR_OM3_SHIFT) # define GPT_CR_OM3(n) ((uint32_t)(n) << GPT_CR_OM3_SHIFT) @@ -129,6 +134,7 @@ # define GPT_CR_OM3_CLEAR (2 << GPT_CR_OM3_SHIFT) /* Clear output pin */ # define GPT_CR_OM3_SET (3 << GPT_CR_OM3_SHIFT) /* Set output pin */ # define GPT_CR_OM3_PULSE (4 << GPT_CR_OM3_SHIFT) /* Generate an active low pulse */ + #define GPT_CR_FO1 (1 << 29) /* Bit: 29 See F03 */ #define GPT_CR_FO2 (1 << 30) /* Bit: 30 See F03 */ #define GPT_CR_FO3 (1 << 31) /* Bit: 31 FO3 Force Output Compare Channel 3 */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_ocotp.h b/arch/arm/src/imxrt/hardware/imxrt_ocotp.h index 4810dfe40f3..270d245d4e5 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_ocotp.h +++ b/arch/arm/src/imxrt/hardware/imxrt_ocotp.h @@ -1,4 +1,4 @@ -/************************************************************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_ocotp.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_OCOTP_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_OCOTP_H @@ -27,18 +27,18 @@ * OTP, OCOTP Indexes are used. */ -/************************************************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/************************************************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define IMXRT_OCOTP_CTRL_OFFSET 0x0000 /* OTP Controller Control Register */ #define IMXRT_OCOTP_CTRL_SET_OFFSET 0x0004 /* OTP Controller Control Register */ @@ -58,7 +58,7 @@ #define IMXRT_OCOTP_VERSION_OFFSET 0x0090 /* OTP Controller Version Register */ #define IMXRT_OCOTP_TIMING2_OFFSET 0x0100 /* OTP Controller Timing Register */ -/* OCOTP Shadow Offsets *************************************************************/ +/* OCOTP Shadow Offsets *****************************************************/ #define IMXRT_OCOTP_LOCK_OFFSET 0x0400 /* Value of OTP Bank0 Word0 (Lock controls) */ #define IMXRT_OCOTP_CFG0_OFFSET 0x0410 /* Value of OTP Bank0 Word1 (Configuration and Manufacturing */ @@ -124,7 +124,7 @@ #define IMXRT_OCOTP_GP42_OFFSET 0x08e0 /* Value of OTP Bank7 Word6 (GP4) */ #define IMXRT_OCOTP_GP43_OFFSET 0x08f0 /* Value of OTP Bank7 Word7 (GP4) */ -/* OCOTP Indexes *****************************************************************/ +/* OCOTP Indexes ************************************************************/ #define IMXRT_OCOTP_O2I(offset) (((offset) - IMXRT_OCOTP_LOCK_OFFSET) >> 4) @@ -194,7 +194,7 @@ #define IMXRT_OCOTP_GP42_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP42_OFFSET) /* Value of OTP Bank7 Word6 (GP4) */ #define IMXRT_OCOTP_GP43_INDEX IMXRT_OCOTP_O2IP(IMXRT_OCOTP_GP43_OFFSET) /* Value of OTP Bank7 Word7 (GP4) */ -/* Register addresses ***********************************************************************************************************************/ +/* Register addresses *******************************************************/ #define IMXRT_OCOTP_CTRL (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CTRL_OFFSET) /* OTP Controller Control Register */ #define IMXRT_OCOTP_CTRL_SET (IMXRT_OCOTP_BASE + IMXRT_OCOTP_CTRL_SET_OFFSET) /* OTP Controller Control Register */ @@ -276,7 +276,7 @@ #define IMXRT_OCOTP_GP42 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP42_OFFSET) /* Value of OTP Bank7 Word6 (GP4) */ #define IMXRT_OCOTP_GP43 (IMXRT_OCOTP_BASE + IMXRT_OCOTP_GP43_OFFSET) /* Value of OTP Bank7 Word7 (GP4) */ -/* Register Bit Definitions *********************************************************************************************************/ +/* Register Bit Definitions *************************************************/ /* OTP Controller Control Register */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_pit.h b/arch/arm/src/imxrt/hardware/imxrt_pit.h index bde67c3aee7..36ba4d0ecc4 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_pit.h +++ b/arch/arm/src/imxrt/hardware/imxrt_pit.h @@ -85,6 +85,7 @@ /* Bits 2-31: Reserved */ /* Timer Load Value Register (32-bit Timer Start Value Bits) */ + /* Current Timer Value Register (32-bit Current Timer Value) */ /* Timer Control Register */ @@ -109,7 +110,7 @@ ************************************************************************************/ /************************************************************************************ - * Public Functions + * Public Functions Prototypes ************************************************************************************/ #endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_PIT_H */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_tmr.h b/arch/arm/src/imxrt/hardware/imxrt_tmr.h index dbadfd806b0..cb868f0c258 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_tmr.h +++ b/arch/arm/src/imxrt/hardware/imxrt_tmr.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_tmr.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_TMR_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_TMR_H -/******************************************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/******************************************************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *************************************************************************************************************************/ +/* Register Offsets *********************************************************/ #define IMXRT_TMR_COMP1_OFFSET 0x0000 /* Timer Channel Compare Register 1 */ #define IMXRT_TMR_COMP2_OFFSET 0x0002 /* Timer Channel Compare Register 2 */ @@ -279,7 +279,7 @@ #define IMXRT_TMR4_FILT3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_FILT_OFFSET) /* Timer Channel Input Filter Register */ #define IMXRT_TMR4_DMA3_OFFSET IMXRT_TMR_OFFSET(IMXRT_TMR_CH3, IMXRT_TMR_DMA_OFFSET) /* Timer Channel DMA Enable Register */ -/* Register addresses *******************************************************************************************************************************/ +/* Register addresses *******************************************************/ #define IMXRT_TMR1_COMP10 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_COMP10_OFFSET) /* Timer Channel Compare Register 1 */ #define IMXRT_TMR1_COMP20 (IMXRT_QTIMER1_BASE + IMXRT_TMR1_COMP20_OFFSET) /* Timer Channel Compare Register 2 */ @@ -494,7 +494,7 @@ #define IMXRT_TMR4_FILT3 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_FILT3_OFFSET) /* Timer Channel Input Filter Register */ #define IMXRT_TMR4_DMA3 (IMXRT_QTIMER4_BASE + IMXRT_TMR4_DMA3_OFFSET) /* Timer Channel DMA Enable Register */ -/* Register Bit Definitions *****************************************************************************************************************/ +/* Register Bit Definitions *************************************************/ /* Timer Channel Control Register */ @@ -509,6 +509,7 @@ # define TMR_CTRL_OUTMODE_SET_CLR (5 << TMR_CTRL_OUTMODE_SHIFT) /* Set on compare, cleared on secondary source input edge */ # define TMR_CTRL_OUTMODE_SET_CLR_ROL (6 << TMR_CTRL_OUTMODE_SHIFT) /* Set on compare, cleared on counter rollover */ # define TMR_CTRL_OUTMODE_GATED (7 << TMR_CTRL_OUTMODE_SHIFT) /* Enable gated clock output while counter is active */ + #define TMR_CTRL_COINIT (1 << 3) /* Bit: 3 Co-Channel Initialization */ #define TMR_CTRL_DIR (1 << 4) /* Bit: 4 Count Direction */ #define TMR_CTRL_LENGTH (1 << 5) /* Bit: 5 Count Length */ @@ -520,6 +521,7 @@ # define TMR_CTRL_SCS_CNTR1 (1 << TMR_CTRL_SCS_SHIFT) /* Counter 1 input pin */ # define TMR_CTRL_SCS_CNTR2 (2 << TMR_CTRL_SCS_SHIFT) /* Counter 2 input pin */ # define TMR_CTRL_SCS_CNTR3 (3 << TMR_CTRL_SCS_SHIFT) /* Counter 3 input pin */ + #define TMR_CTRL_PCS_SHIFT (9) /* Bits: 9-12 Primary Count Source */ #define TMR_CTRL_PCS_MASK (15 << TMR_CTRL_PCS_SHIFT) # define TMR_CTRL_PCS(n) ((uint32_t)(n) << TMR_CTRL_PCS_SHIFT) @@ -533,12 +535,13 @@ # define TMR_CTRL_PCS_OUT3 (7 << TMR_CTRL_PCS_SHIFT) /* Counter 3 output */ # define TMR_CTRL_PCS_DIV1 (8 << TMR_CTRL_PCS_SHIFT) /* IP bus clock divide by 1 prescaler */ # define TMR_CTRL_PCS_DIV2 (9 << TMR_CTRL_PCS_SHIFT) /* IP bus clock divide by 2 prescaler */ -# define TMR_CTRL_PCS_DIV4 (10 << TMR_CTRL_PCS_SHIFT) /*IP bus clock divide by 4 prescaler */ -# define TMR_CTRL_PCS_DIV8 (11 << TMR_CTRL_PCS_SHIFT) /*IP bus clock divide by 8 prescaler */ -# define TMR_CTRL_PCS_DIV16 (12 << TMR_CTRL_PCS_SHIFT) /*IP bus clock divide by 16 prescaler */ -# define TMR_CTRL_PCS_DIV32 (13 << TMR_CTRL_PCS_SHIFT) /*IP bus clock divide by 32 prescaler */ -# define TMR_CTRL_PCS_DIV64 (14 << TMR_CTRL_PCS_SHIFT) /*IP bus clock divide by 64 prescaler */ -# define TMR_CTRL_PCS_DIV128 (15 << TMR_CTRL_PCS_SHIFT) /*IP bus clock divide by 128 prescaler */ +# define TMR_CTRL_PCS_DIV4 (10 << TMR_CTRL_PCS_SHIFT) /* IP bus clock divide by 4 prescaler */ +# define TMR_CTRL_PCS_DIV8 (11 << TMR_CTRL_PCS_SHIFT) /* IP bus clock divide by 8 prescaler */ +# define TMR_CTRL_PCS_DIV16 (12 << TMR_CTRL_PCS_SHIFT) /* IP bus clock divide by 16 prescaler */ +# define TMR_CTRL_PCS_DIV32 (13 << TMR_CTRL_PCS_SHIFT) /* IP bus clock divide by 32 prescaler */ +# define TMR_CTRL_PCS_DIV64 (14 << TMR_CTRL_PCS_SHIFT) /* IP bus clock divide by 64 prescaler */ +# define TMR_CTRL_PCS_DIV128 (15 << TMR_CTRL_PCS_SHIFT) /* IP bus clock divide by 128 prescaler */ + #define TMR_CTRL_CM_SHIFT (13) /* Bits: 13-15 Count Mode */ #define TMR_CTRL_CM_MASK (7 << TMR_CTRL_CM_SHIFT) # define TMR_CTRL_CM(n) ((uint32_t)(n) << TMR_CTRL_CM_SHIFT) @@ -566,6 +569,7 @@ # define TMR_SCTRL_CAPTURE_RISING (1 << TMR_SCTRL_CAPTURE_MODE_SHIFT) /* Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input */ # define TMR_SCTRL_CAPTURE_FALLING (2 << TMR_SCTRL_CAPTURE_MODE_SHIFT) /* Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input */ # define TMR_SCTRL_CAPTURE_BOTH (3 << TMR_SCTRL_CAPTURE_MODE_SHIFT) /* Load capture register on both edges of input */ + #define TMR_SCTRL_INPUT (1 << 8) /* Bit: 8 External Input Signal */ #define TMR_SCTRL_IPS (1 << 9) /* Bit: 9 Input Polarity Select */ #define TMR_SCTRL_IEFIE (1 << 10) /* Bit: 10 Input Edge Flag Interrupt Enable */ @@ -583,12 +587,14 @@ # define TMR_CSCTRL_CL1_DIS (0 << TMR_CSCTRL_CL1_SHIFT) /* Never preload */ # define TMR_CSCTRL_CL1_COMP1 (1 << TMR_CSCTRL_CL1_SHIFT) /* Load upon successful compare with the value in COMP1 */ # define TMR_CSCTRL_CL1_COMP2 (2 << TMR_CSCTRL_CL1_SHIFT) /* Load upon successful compare with the value in COMP2 */ + #define TMR_CSCTRL_CL2_SHIFT (2) /* Bits: 2-3 Compare Load Control 2 */ #define TMR_CSCTRL_CL2_MASK (3 << TMR_CSCTRL_CL2_SHIFT) # define TMR_CSCTRL_CL2(n) ((uint32_t)(n) << TMR_CSCTRL_CL2_SHIFT) # define TMR_CSCTRL_CL2_DIS (0 << TMR_CSCTRL_CL2_SHIFT) /* Never preload */ # define TMR_CSCTRL_CL2_COMP1 (1 << TMR_CSCTRL_CL2_SHIFT) /* Load upon successful compare with the value in COMP1 */ # define TMR_CSCTRL_CL2_COMP2 (2 << TMR_CSCTRL_CL2_SHIFT) /* Load upon successful compare with the value in COMP2 */ + #define TMR_CSCTRL_TCF1 (1 << 4) /* Bit: 4 Timer Compare 1 Interrupt Flag */ #define TMR_CSCTRL_TCF2 (1 << 5) /* Bit: 5 Timer Compare 2 Interrupt Flag */ #define TMR_CSCTRL_TCF1EN (1 << 6) /* Bit: 6 Timer Compare 1 Interrupt Enable */ @@ -641,6 +647,7 @@ # define TMR_ENBL_CHN1 (2 << TMR_ENBL_ENBL_SHIFT) /* Channel 1 enable */ # define TMR_ENBL_CHN3 (4 << TMR_ENBL_ENBL_SHIFT) /* Channel 2 enable */ # define TMR_ENBL_CHN4 (8 << TMR_ENBL_ENBL_SHIFT) /* Channel 3 enable */ + /* Bits: 4-15 Reserved */ #endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_TMR_H */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_usb_analog.h b/arch/arm/src/imxrt/hardware/imxrt_usb_analog.h index a87db5abcd2..f840a749fe0 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_usb_analog.h +++ b/arch/arm/src/imxrt/hardware/imxrt_usb_analog.h @@ -1,4 +1,4 @@ -/************************************************************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_usb_analog.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USB_ANALOG_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USB_ANALOG_H -/************************************************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/************************************************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************************************************************/ +/* Register Offsets *********************************************************/ #define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_OFFSET 0x01a0 /* USB VBUS Detect Register */ #define IMXRT_USB_ANALOG_USB1_VBUS_DETECT_SET_OFFSET 0x01a4 /* USB VBUS Detect Set Register */ @@ -64,7 +64,7 @@ #define IMXRT_USB_ANALOG_USB2_MISC_TOG_OFFSET 0x025c /* USB Misc Toggle Register */ #define IMXRT_USB_ANALOG_DIGPROG_OFFSET 0x0260 /* Chip Silicon Version */ -/* Register addresses ***********************************************************************************************************************/ +/* Register addresses *******************************************************/ /* Analog USB1 Register Addresses */ @@ -130,7 +130,7 @@ #define IMXRT_USB_ANALOG_USB2_MISC_TOG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_USB2_MISC_TOG_OFFSET) /* USB_ANALOG2 USB Misc Toggle Register */ #define IMXRT_USB_ANALOG_DIGPROG (IMXRT_ANATOP_BASE + IMXRT_USB_ANALOG_DIGPROG_OFFSET) /* USB_ANALOG2 Chip Silicon Version */ -/* Register Bit Definitions *********************************************************************************************************/ +/* Register Bit Definitions *************************************************/ /* USB VBUS Detect Register */ @@ -145,7 +145,9 @@ # define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V5 (5 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V5 — 4.5V */ # define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V6 (6 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V6 — 4.6V */ # define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_4V7 (7 << USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_THRESH_SHIFT) /* 4V7 — 4.7V */ - /* Bits: 3-19 Reserved */ + + /* Bits: 3-19 Reserved */ + #define USB_ANALOG_USB_VBUS_DETECT_VBUSVALID_PWRUP_CMPS (1 << 20) /* Bit: 20 Powers up comparators for vbus_valid detector. */ /* Bits: 21-25 Reserved */ #define USB_ANALOG_USB_VBUS_DETECT_DISCHARGE_VBUS (1 << 26) /* Bit: 26 USB OTG discharge VBUS. */ @@ -154,7 +156,8 @@ /* USB Charger Detect Register */ - /* Bits: 0-17 Reserved */ + /* Bits: 0-17 Reserved */ + #define USB_ANALOG_USB_CHRG_DETECT_CHK_CONTACT (1 << 18) /* Bit: 18 Check the contact of USB plug */ #define USB_ANALOG_USB_CHRG_DETECT_CHK_CHRG_B (1 << 19) /* Bit: 19 Check the charger connection */ #define USB_ANALOG_USB_CHRG_DETECT_EN_B (1 << 20) /* Bit: 20 Control the charger detector. */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_xbar.h b/arch/arm/src/imxrt/hardware/imxrt_xbar.h index e0f39b78dbf..86ce4ad3fa0 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_xbar.h +++ b/arch/arm/src/imxrt/hardware/imxrt_xbar.h @@ -39,7 +39,6 @@ # error Unrecognized i.MX RT architecture #endif - /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ diff --git a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h index 35446d8ae87..e389cb1fbb0 100644 --- a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h +++ b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h @@ -77,6 +77,7 @@ #define IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET 0x000c /* SNVC GPR3 General Purpose Register */ /* Pad Mux Registers */ + /* Pad Mux Register Indices (used by software for table lookups) */ #define IMXRT_PADMUX_GPIO_EMC_00_INDEX 0 diff --git a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_iomuxc.h b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_iomuxc.h index 12e6e2fd284..08cd65169ac 100644 --- a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_iomuxc.h +++ b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_iomuxc.h @@ -86,6 +86,7 @@ #define IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET 0x000c /* SNVC GPR3 General Purpose Register */ /* Pad Mux Registers */ + /* Pad Mux Register Indices (used by software for table lookups) */ #define IMXRT_PADMUX_GPIO_EMC_00_INDEX 0 diff --git a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_memorymap.h b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_memorymap.h index 44d49c1066b..ce169e007af 100644 --- a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_memorymap.h +++ b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/rt106x/imxrt106x_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,58 +16,86 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_MEMORYMAP_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* System memory map */ #define IMXRT_ITCM_BASE 0x00000000 /* 512KB ITCM */ + /* 0x00080000 512KB ITCM Reserved */ + /* 0x00100000 1MB ITCM Reserved */ + #define IMXRT_ROMCP_BASE 0x00200000 /* 128KB ROMCP */ + /* 0x00220000 384KB ROMCP Reserved */ + /* 0x00280000 1536KB Reserved */ + /* 0x00400000 124MB Reserved */ + #define IMXRT_FLEXSPI_BASE 0x08000000 /* 128MB FlexSPI (Aliased) */ #define IMXRT_SEMCA_BASE 0x10000000 /* 256MB SEMC (Aliased) */ #define IMXRT_DTCM_BASE 0x20000000 /* 512KB DTCM */ + /* 0x20080000 512KB DTCM Reserved */ + /* 0x20100000 1MB Reserved */ + #define IMXRT_OCRAM2_BASE 0x20200000 /* 512KB OCRAM2 */ #define IMXRT_OCRAM_BASE 0x20280000 /* 512KB OCRAM FlexRAM */ + /* 0x20300000 512KB OCRAM Reserved */ + /* 0x20400000 252MB Reserved */ + /* 0x30000000 256MB Reserved */ + #define IMXRT_AIPS1_BASE 0x40000000 /* 1MB AIPS-1 */ #define IMXRT_AIPS2_BASE 0x40100000 /* 1MB AIPS-2 */ #define IMXRT_AIPS3_BASE 0x40200000 /* 1MB AIPS-3 */ #define IMXRT_AIPS4_BASE 0x40300000 /* 1MB AIPS-4 */ + /* 40400000 12MB Reserved */ + #define IMXRT_MAINCNF_BASE 0x41000000 /* 1MB "main" configuration port */ #define IMXRT_MCNF_BASE 0x41100000 /* 1MB "m" configuration port */ + /* 41200000 1MB Reserved for "per" GPV */ + /* 41300000 1MB Reserved for "ems" GPV */ + #define IMXRT_CPUCNF_BASE 0x41400000 /* 1MB "cpu" configuration port */ + /* 0x41500000 1MB GPV Reserved */ + /* 0x41600000 1MB GPV Reserved */ + /* 0x41700000 1MB GPV Reserved */ + /* 0x41800000 8MB Reserved */ + #define IMXRT_AIPS5_BASE 0x42000000 /* 1MB AIPS-5 */ + /* 0x42100000 31MB Reserved */ + /* 0x44000000 64MB Reserved */ + /* 0x48000000 384MB Reserved */ + #define IMXRT_FLEXCIPHER_BASE 0x60000000 /* 256MB FlexSPI/ FlexSPI ciphertext */ #define IMXRT_FLEX2CIPHER_BASE 0x70000000 /* 240MB FlexSPI2/ FlexSPI ciphertext */ #define IMXRT_FLEXSPI2TX_BASE 0x7f000000 /* 4MB FlexSPI2 TX FIFO */ @@ -76,22 +104,32 @@ #define IMXRT_FLEXSPIRX_BASE 0x7fc00000 /* 4MB FlexSPI RX FIFO */ #define IMXRT_EXTMEM_BASE 0x80000000 /* 1.5GB SEMC external memories shared memory space */ #define IMXRT_CM7_BASE 0xe0000000 /* 1MB CM7 PPB */ + /* 0xe0100000 511MB Reserved */ /* AIPS-1 memory map */ /* 0x40000000 256KB Reserved */ + /* 0x40040000 240KB Reserved */ + #define IMXRT_AIPS1CNF_BASE 0x4007c000 /* 6KB AIPS-1 Configuration */ #define IMXRT_DCDC_BASE 0x40080000 /* 16KB DCDC */ #define IMXRT_PIT_BASE 0x40084000 /* 16KB PIT */ + /* 0x40088000 16KB Reserved */ + /* 0x4008c000 16KB Reserved */ + #define IMXRT_MTR_BASE 0x40090000 /* 16KB MTR */ #define IMXRT_ACMP_BASE 0x40094000 /* 16KB ACMP */ + /* 0x40098000 16KB Reserved */ + /* 0x4009c000 16KB Reserved */ + /* 0x400a0000 16KB Reserved */ + #define IMXRT_IOMUXCSNVSGPR_BASE 0x400a4000 /* 16KB IOMUXC_SNVS_GPR */ #define IMXRT_IOMUXCSNVS_BASE 0x400a8000 /* 16KB IOMUXC_SNVS */ #define IMXRT_IOMUXCGPR_BASE 0x400ac000 /* 16KB IOMUXC_GPR */ @@ -107,11 +145,16 @@ #define IMXRT_SNVSHP_BASE 0x400d4000 /* 16KB SNVS_HP */ #define IMXRT_ANATOP_BASE 0x400d8000 /* 16KB ANATOP */ #define IMXRT_CSU_BASE 0x400dc000 /* 16KB CSU */ + /* 0x400e0000 16KB Reserved */ + /* 0x400e4000 16KB Reserved */ + #define IMXRT_EDMA_BASE 0x400e8000 /* 16KB EDMA */ #define IMXRT_DMAMUX_BASE 0x400ec000 /* 16KB DMA_CH_MUX */ + /* 400f0000 16KB Reserved */ + #define IMXRT_GPC_BASE 0x400f4000 /* 16KB GPC */ #define IMXRT_SRC_BASE 0x400f8000 /* 16KB SRC */ #define IMXRT_CCM_BASE 0x400fc000 /* 16KB CCM */ @@ -119,7 +162,9 @@ /* AIPS-2 memory map */ /* 0x40100000 256KB Reserved */ + /* 0x40140000 240KB Reserved */ + #define IMXRT_AIPS2CNF_BASE 0x4017c000 /* 16KB AIPS-2 Configuration */ #define IMXRT_ROMCPC_BASE 0x40180000 /* 16KB ROMCP controller*/ #define IMXRT_LPUART1_BASE 0x40184000 /* 16KB LPUART1 */ @@ -130,17 +175,25 @@ #define IMXRT_LPUART6_BASE 0x40198000 /* 16KB LPUART6 */ #define IMXRT_LPUART7_BASE 0x4019c000 /* 16KB LPUART7 */ #define IMXRT_LPUART8_BASE 0x401a0000 /* 16KB LPUART8 */ + /* 0x401a4000 16KB Reserved */ + /* 0x401a8000 16KB Reserved */ + #define IMXRT_FLEXIO1_BASE 0x401ac000 /* 16KB FlexIO1 */ #define IMXRT_FLEXIO2_BASE 0x401b0000 /* 16KB FlexIO2 */ + /* 0x401b4000 16KB Reserved */ + #define IMXRT_GPIO1_BASE 0x401b8000 /* 16KB GPIO1 */ #define IMXRT_GPIO2_BASE 0x401bc000 /* 16KB GPIO2 */ #define IMXRT_GPIO3_BASE 0x401c0000 /* 16KB GPIO3 */ #define IMXRT_GPIO4_BASE 0x401c4000 /* 16KB GPIO4 */ + /* 0x401c8000 16KB Reserved */ + /* 0x401cc000 16KB Reserved */ + #define IMXRT_CAN1_BASE 0x401d0000 /* 16KB CAN1 */ #define IMXRT_CAN2_BASE 0x401d4000 /* 16KB CAN2 */ #define IMXRT_CAN3_BASE 0x401d8000 /* 16KB CAN3 */ @@ -157,59 +210,94 @@ /* AIPS-3 memory map */ /* 0x40200000 256KB Reserved */ + /* 0x40240000 240KB Reserved */ + #define IMXRT_AIOS3CNF_BASE 0x4027c000 /* 16KB AIPS-3 Configuration */ + /* 0x40280000 16KB Reserved */ + /* 0x40284000 16KB Reserved */ + /* 0x40288000 16KB Reserved */ + /* 0x4028c000 16KB Reserved */ + /* 0x40290000 16KB Reserved */ + /* 0x40294000 16KB Reserved */ + /* 0x40298000 16KB Reserved */ + /* 0x4029c000 16KB Reserved */ + /* 0x402a0000 16KB Reserved */ + #define IMXRT_FLEXSPI2C_BASE 0x402a4000 /* 16KB FlexSPI2 */ #define IMXRT_FLEXSPIC_BASE 0x402a8000 /* 16KB FlexSPI */ + /* 0x402ac000 16KB Reserved */ + /* 0x402b0000 16KB Reserved */ + #define IMXRT_PXP_BASE 0x402b4000 /* 16KB PXP */ #define IMXRT_LCDIF_BASE 0x402b8000 /* 16KB LCDIF */ #define IMXRT_CSI_BASE 0x402bc000 /* 16KB CSI */ #define IMXRT_USDHC1_BASE 0x402c0000 /* 16KB USDHC1 */ #define IMXRT_USDHC2_BASE 0x402c4000 /* 16KB USDHC2 */ + /* 0x402c8000 16KB Reserved */ + /* 0x402cc000 16KB Reserved */ + /* 0x402d0000 16KB Reserved */ + /* 0x402d4000 16KB Reserved */ + #define IMXRT_ENET2_BASE 0x402d4000 /* 16KB ENET2 */ #define IMXRT_ENET_BASE 0x402d8000 /* 16KB ENET */ #define IMXRT_USBPL301_BASE 0x402dc000 /* 16KB USB(PL301) */ #define IMXRT_USB_BASE 0x402e0000 /* 16KB USB(USB) */ + /* 0x402e4000 16KB Reserved */ + /* 0x402e8000 16KB Reserved */ + /* 0x402ec000 16KB Reserved */ + #define IMXRT_SEMC_BASE 0x402f0000 /* 16KB SEMC */ + /* 0x402f4000 16KB Reserved */ + /* 0x402f8000 16KB Reserved */ + #define IMXRT_DCP_BASE 0x402fc000 /* 16KB DCP */ /* AIPS-4 memory map */ /* 0x40300000 256KB Reserved */ + /* 0x40340000 240KB Reserved */ + #define IMXRT_AIPS4CNF_BASE 0x4037c000 /* 16KB AIPS-4 Configuration */ #define IMXRT_SPDIF_BASE 0x40380000 /* 16KB SPDIF */ #define IMXRT_SAI1_BASE 0x40384000 /* 16KB SAI1 */ #define IMXRT_SAI2_BASE 0x40388000 /* 16KB SAI2 */ #define IMXRT_SAI3_BASE 0x4038c000 /* 16KB SAI3 */ + /* 0x40390000 16KB Reserved */ + #define IMXRT_LPSPI1_BASE 0x40394000 /* 16KB LPSPI1 */ #define IMXRT_LPSPI2_BASE 0x40398000 /* 16KB LPSPI2 */ #define IMXRT_LPSPI3_BASE 0x4039c000 /* 16KB LPSPI3 */ #define IMXRT_LPSPI4_BASE 0x403a0000 /* 16KB LPSPI4 */ + /* 0x403a4000 16KB Reserved */ + /* 0x403a8000 16KB Reserved */ + /* 0x403ac000 16KB Reserved */ + #define IMXRT_ADCETC_BASE 0x403b0000 /* 16KB ADC_ETC */ #define IMXRT_AOI1_BASE 0x403b4000 /* 16KB AOI1 */ #define IMXRT_AOI2_BASE 0x403b8000 /* 16KB AOI2 */ @@ -220,7 +308,9 @@ #define IMXRT_ENC2_BASE 0x403cc000 /* 16KB ENC2 */ #define IMXRT_ENC3_BASE 0x403d0000 /* 16KB ENC3 */ #define IMXRT_ENC4_BASE 0x403d4000 /* 16KB ENC4 */ + /* 0x403d8000 16KB Reserved */ + #define IMXRT_FLEXPWM1_BASE 0x403dc000 /* 16KB FLEXPWM1 */ #define IMXRT_FLEXPWM2_BASE 0x403e0000 /* 16KB FLEXPWM2 */ #define IMXRT_FLEXPWM3_BASE 0x403e4000 /* 16KB FLEXPWM3 */ @@ -237,35 +327,66 @@ #define IMXRT_GPIO7_BASE 0x42004000 /* 16KB GPIO7 */ #define IMXRT_GPIO8_BASE 0x42008000 /* 16KB GPIO8 */ #define IMXRT_GPIO9_BASE 0x4200c000 /* 16KB GPIO9 */ + /* 0x42010000 16KB Reserved */ + /* 0x42014000 16KB Reserved */ + /* 0x42018000 16KB Reserved */ + /* 0x4201c000 16KB Reserved */ + #define IMXRT_FLEXIO3_BASE 0x42020000 /* 16KB FlexIO3 */ + /* 0x42024000 16KB Reserved */ + /* 0x42028000 16KB Reserved */ + /* 0x4202c000 16KB Reserved */ + /* 0x42030000 16KB Reserved */ + /* 0x42034000 16KB Reserved */ + /* 0x42038000 16KB Reserved */ + /* 0x4203c000 16KB Reserved */ + /* 0x42040000 16KB Reserved */ + /* 0x42044000 16KB Reserved */ + /* 0x42048000 16KB Reserved */ + /* 0x4204c000 16KB Reserved */ + /* 0x42050000 16KB Reserved */ + /* 0x42054000 16KB Reserved */ + /* 0x42058000 16KB Reserved */ + /* 0x4205c000 16KB Reserved */ + /* 0x42060000 16KB Reserved */ + /* 0x42064000 16KB Reserved */ + /* 0x42068000 16KB Reserved */ + /* 0x4206c000 16KB Reserved */ + /* 0x42070000 16KB Reserved */ + /* 0x42074000 16KB Reserved */ + /* 0x42078000 16KB Reserved */ + /* 0x4207c000 16KB Reserved */ - /* 0x42080000 512KB Reserved Off Platform */ + + /* 0x42080000 512KB Reserved */ + + /* Off Platform */ /* PPB memory map */ @@ -274,10 +395,15 @@ #define IMXRT_CTI_BASE 0xe0042000 /* 4KB CTI */ #define IMXRT_TSGEN_BASE 0xe0043000 /* 4KB TSGEN */ #define IMXRT_PPBRES_BASE 0xe0044000 /* 4KB PPB RES */ + /* 0xe0045000 236KB PPB Reserved */ + #define IMXRT_MCM_BASE 0xe0080000 /* 4KB MCM */ + /* 0xe0081000 444KB PPB Reserved */ + /* 0xe00f0000 52KB PPB Reserved */ + #define IMXRT_SYSROM_BASE 0xe00fd000 /* 4KB SYS ROM */ #define IMXRT_PROCROM_BASE 0xe00fe000 /* 4KB Processor ROM */ #define IMXRT_PPBROM_BASE 0xe00ff000 /* 4KB PPB ROM */ diff --git a/arch/arm/src/imxrt/imxrt105x_daisy.c b/arch/arm/src/imxrt/imxrt105x_daisy.c index d9664deffbe..ff839026fac 100644 --- a/arch/arm/src/imxrt/imxrt105x_daisy.c +++ b/arch/arm/src/imxrt/imxrt105x_daisy.c @@ -37,7 +37,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:0 Alt:1 GPIO EMC 00 FLEXPWM4 PWMA00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET), [ALT1].sel = 0, /* Index:0 Alt:2 GPIO EMC 00 LPSPI2 SCK */ @@ -98,7 +99,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:1 Alt:2 GPIO EMC 01 LPSPI2 PCS0 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_PCS0_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_PCS0_OFFSET), [ALT2].sel = 1, /* Index:1 Alt:3 GPIO EMC 01 XBAR1 IN03 */ @@ -149,7 +151,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:2 Alt:1 GPIO EMC 02 FLEXPWM4 PWMA01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET), [ALT1].sel = 0, /* Index:2 Alt:2 GPIO EMC 02 LPSPI2 SDO */ @@ -261,7 +264,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:4 Alt:1 GPIO EMC 04 FLEXPWM4 PWMA02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET), [ALT1].sel = 0, /* Index:4 Alt:2 No input selection */ @@ -322,7 +326,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:5 Alt:2 GPIO EMC 05 SAI2 TX SYNC */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_SYNC_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_SYNC_OFFSET), [ALT2].sel = 0, /* Index:5 Alt:3 GPIO EMC 05 XBAR1 INOUT07 */ @@ -373,12 +378,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:6 Alt:1 GPIO EMC 06 FLEXPWM2 PWMA00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET), [ALT1].sel = 0, /* Index:6 Alt:2 GPIO EMC 06 SAI2 TX BCLK */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_BCLK_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_BCLK_OFFSET), [ALT2].sel = 0, /* Index:6 Alt:3 GPIO EMC 06 XBAR1 INOUT08 */ @@ -429,7 +436,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:7 Alt:1 GPIO EMC 07 FLEXPWM2 PWMB00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET), [ALT1].sel = 0, /* Index:7 Alt:2 GPIO EMC 07 SAI2 MCLK */ @@ -485,12 +493,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:8 Alt:1 GPIO EMC 08 FLEXPWM2 PWMA01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET), [ALT1].sel = 0, /* Index:8 Alt:2 GPIO EMC 08 SAI2 RX DATA */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_DATA0_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_DATA0_OFFSET), [ALT2].sel = 0, /* Index:8 Alt:3 GPIO EMC 08 XBAR1 INOUT17 */ @@ -541,12 +551,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:9 Alt:1 GPIO EMC 09 FLEXPWM2 PWMB01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET), [ALT1].sel = 0, /* Index:9 Alt:2 GPIO EMC 09 SAI2 RX SYNC */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_SYNC_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_SYNC_OFFSET), [ALT2].sel = 0, /* Index:9 Alt:3 No input selection */ @@ -597,17 +609,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:10 Alt:1 GPIO EMC 10 FLEXPWM2 PWMA02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET), [ALT1].sel = 0, /* Index:10 Alt:2 GPIO EMC 10 SAI2 RX BCLK */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_BCLK_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_BCLK_OFFSET), [ALT2].sel = 0, /* Index:10 Alt:3 GPIO EMC 10 FLEXCAN2 RX */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), [ALT3].sel = 0, /* Index:10 Alt:4 No input selection */ @@ -653,7 +668,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:11 Alt:1 GPIO EMC 11 FLEXPWM2 PWMB02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET), [ALT1].sel = 0, /* Index:11 Alt:2 GPIO EMC 11 LPI2C4 SDA */ @@ -724,7 +740,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:12 Alt:4 GPIO EMC 12 FLEXPWM1 PWMA03 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), [ALT4].sel = 1, /* Index:12 Alt:5 No input selection */ @@ -780,7 +797,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:13 Alt:4 GPIO EMC 13 FLEXPWM1 PWMB03 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), [ALT4].sel = 1, /* Index:13 Alt:5 No input selection */ @@ -877,12 +895,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:15 Alt:1 GPIO EMC 15 XBAR1 IN20 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN20_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN20_OFFSET), [ALT1].sel = 0, /* Index:15 Alt:2 GPIO EMC 15 LPUART3 CTS B */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_CTS_B_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_CTS_B_OFFSET), [ALT2].sel = 0, /* Index:15 Alt:3 No input selection */ @@ -892,7 +912,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:15 Alt:4 GPIO EMC 15 QTIMER3 TIMER0 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER0_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER0_OFFSET), [ALT4].sel = 0, /* Index:15 Alt:5 No input selection */ @@ -933,7 +954,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:16 Alt:1 GPIO EMC 16 XBAR1 IN21 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN21_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN21_OFFSET), [ALT1].sel = 0, /* Index:16 Alt:2 No input selection */ @@ -943,12 +965,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:16 Alt:3 GPIO EMC 16 SPDIF IN */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SPDIF_IN_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SPDIF_IN_OFFSET), [ALT3].sel = 1, /* Index:16 Alt:4 GPIO EMC 16 QTIMER3 TIMER1 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER1_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER1_OFFSET), [ALT4].sel = 1, /* Index:16 Alt:5 No input selection */ @@ -989,7 +1013,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:17 Alt:1 GPIO EMC 17 FLEXPWM4 PWMA03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET), [ALT1].sel = 0, /* Index:17 Alt:2 No input selection */ @@ -1004,7 +1029,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:17 Alt:4 GPIO EMC 17 QTIMER3 TIMER2 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER2_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER2_OFFSET), [ALT4].sel = 0, /* Index:17 Alt:5 No input selection */ @@ -1055,12 +1081,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:18 Alt:3 GPIO EMC 18 FLEXCAN1 RX */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), [ALT3].sel = 1, /* Index:18 Alt:4 GPIO EMC 18 QTIMER3 TIMER3 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER3_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER3_OFFSET), [ALT4].sel = 0, /* Index:18 Alt:5 No input selection */ @@ -1101,22 +1129,26 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:19 Alt:1 GPIO EMC 19 FLEXPWM2 PWMA03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), [ALT1].sel = 1, /* Index:19 Alt:2 GPIO EMC 19 LPUART4 TX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_TX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_TX_OFFSET), [ALT2].sel = 1, /* Index:19 Alt:3 GPIO EMC 19 ENET RDATA01 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET1_RXDATA_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET1_RXDATA_OFFSET), [ALT3].sel = 0, /* Index:19 Alt:4 GPIO EMC 19 QTIMER2 TIMER0 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER0_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER0_OFFSET), [ALT4].sel = 0, /* Index:19 Alt:5 No input selection */ @@ -1157,7 +1189,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:20 Alt:1 GPIO EMC 20 FLEXPWM2 PWMB03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET), [ALT1].sel = 1, /* Index:20 Alt:2 GPIO EMC 20 LPUART4 RX */ @@ -1167,12 +1200,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:20 Alt:3 GPIO EMC 20 ENET RDATA00 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_RXDATA_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_RXDATA_OFFSET), [ALT3].sel = 0, /* Index:20 Alt:4 GPIO EMC 20 QTIMER2 TIMER1 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER1_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER1_OFFSET), [ALT4].sel = 0, /* Index:20 Alt:5 No input selection */ @@ -1228,7 +1263,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:21 Alt:4 GPIO EMC 21 QTIMER2 TIMER2 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER2_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER2_OFFSET), [ALT4].sel = 0, /* Index:21 Alt:5 No input selection */ @@ -1284,7 +1320,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:22 Alt:4 GPIO EMC 22 QTIMER2 TIMER3 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER3_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER3_OFFSET), [ALT4].sel = 0, /* Index:22 Alt:5 No input selection */ @@ -1325,7 +1362,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:23 Alt:1 GPIO EMC 23 FLEXPWM1 PWMA00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET), [ALT1].sel = 0, /* Index:23 Alt:2 GPIO EMC 23 LPUART5 TX */ @@ -1381,7 +1419,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:24 Alt:1 GPIO EMC 24 FLEXPWM1 PWMB00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET), [ALT1].sel = 0, /* Index:24 Alt:2 GPIO EMC 24 LPUART5 RX */ @@ -1437,7 +1476,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:25 Alt:1 GPIO EMC 25 FLEXPWM1 PWMA01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET), [ALT1].sel = 0, /* Index:25 Alt:2 GPIO EMC 25 LPUART6 TX */ @@ -1452,7 +1492,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:25 Alt:4 GPIO EMC 25 ENET REF CLK */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET), [ALT4].sel = 0, /* Index:25 Alt:5 No input selection */ @@ -1493,7 +1534,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:26 Alt:1 GPIO EMC 26 FLEXPWM1 PWMB01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET), [ALT1].sel = 0, /* Index:26 Alt:2 GPIO EMC 26 LPUART6 RX */ @@ -1503,7 +1545,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:26 Alt:3 GPIO EMC 26 ENET RX ER */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXERR_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXERR_OFFSET), [ALT3].sel = 0, /* Index:26 Alt:4 No input selection */ @@ -1549,7 +1592,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:27 Alt:1 GPIO EMC 27 FLEXPWM1 PWMA02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET), [ALT1].sel = 0, /* Index:27 Alt:2 No input selection */ @@ -1605,7 +1649,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:28 Alt:1 GPIO EMC 28 FLEXPWM1 PWMB02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET), [ALT1].sel = 0, /* Index:28 Alt:2 No input selection */ @@ -1727,7 +1772,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:30 Alt:3 GPIO EMC 30 LPSPI1 PCS0 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_PCS0_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_PCS0_OFFSET), [ALT3].sel = 1, /* Index:30 Alt:4 No input selection */ @@ -1834,12 +1880,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:32 Alt:2 GPIO EMC 32 LPUART7 RX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART7_RX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART7_RX_OFFSET), [ALT2].sel = 1, /* Index:32 Alt:3 GPIO EMC 32 CCM PMIC RDY */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), [ALT3].sel = 4, /* Index:32 Alt:4 No input selection */ @@ -2022,7 +2070,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:35 Alt:6 GPIO EMC 35 USDHC1 CD B */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET), [ALT6].sel = 0, /* Index:35 Alt:7 No input selection */ @@ -2109,7 +2158,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:37 Alt:1 GPIO EMC 37 XBAR1 IN23 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN23_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN23_OFFSET), [ALT1].sel = 0, /* Index:37 Alt:2 No input selection */ @@ -2134,7 +2184,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:37 Alt:6 GPIO EMC 37 USDHC2 WP */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_WP_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_WP_OFFSET), [ALT6].sel = 0, /* Index:37 Alt:7 No input selection */ @@ -2165,12 +2216,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:38 Alt:1 GPIO EMC 38 FLEXPWM1 PWMA03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), [ALT1].sel = 2, /* Index:38 Alt:2 GPIO EMC 38 LPUART8 TX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_TX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_TX_OFFSET), [ALT2].sel = 2, /* Index:38 Alt:3 No input selection */ @@ -2221,12 +2274,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:39 Alt:1 GPIO EMC 39 FLEXPWM1 PWMB03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), [ALT1].sel = 2, /* Index:39 Alt:2 GPIO EMC 39 LPUART8 RX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_RX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_RX_OFFSET), [ALT2].sel = 2, /* Index:39 Alt:3 No input selection */ @@ -2246,7 +2301,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:39 Alt:6 GPIO EMC 39 USDHC2 CD B */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CD_B_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CD_B_OFFSET), [ALT6].sel = 1, /* Index:39 Alt:7 No input selection */ @@ -2287,7 +2343,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:40 Alt:3 GPIO EMC 40 USB OTG2 OC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG2_OC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG2_OC_OFFSET), [ALT3].sel = 1, /* Index:40 Alt:4 No input selection */ @@ -2384,12 +2441,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:42 Alt:0 GPIO AD B0 00 FLEXPWM2 PWMA03 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), [ALT0].sel = 2, /* Index:42 Alt:1 GPIO AD B0 00 XBAR1 INOUT14 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN14_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN14_OFFSET), [ALT1].sel = 0, /* Index:42 Alt:2 No input selection */ @@ -2399,7 +2458,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:42 Alt:3 GPIO AD B0 00 USB OTG2 ID */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET), [ALT3].sel = 0, /* Index:42 Alt:4 No input selection */ @@ -2419,7 +2479,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:42 Alt:7 GPIO AD B0 00 LPSPI3 SCK */ - [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI3_SCK_OFFSET), + [ALT7].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI3_SCK_OFFSET), [ALT7].sel = 0, /* Index:42 Alt:8 No input selection */ @@ -2440,12 +2501,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:43 Alt:0 GPIO AD B0 01 FLEXPWM2 PWMB03 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET), [ALT0].sel = 2, /* Index:43 Alt:1 GPIO AD B0 01 XBAR1 INOUT15 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN15_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN15_OFFSET), [ALT1].sel = 0, /* Index:43 Alt:2 No input selection */ @@ -2455,7 +2518,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:43 Alt:3 GPIO AD B0 01 USB OTG1 ID */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET), [ALT3].sel = 0, /* Index:43 Alt:4 No input selection */ @@ -2475,7 +2539,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:43 Alt:7 GPIO AD B0 01 LPSPI3 SDO */ - [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI3_SDO_OFFSET), + [ALT7].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI3_SDO_OFFSET), [ALT7].sel = 0, /* Index:43 Alt:8 No input selection */ @@ -2501,12 +2566,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:44 Alt:1 GPIO AD B0 02 XBAR1 INOUT16 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN16_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN16_OFFSET), [ALT1].sel = 0, /* Index:44 Alt:2 GPIO AD B0 02 LPUART6 TX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART6_TX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART6_TX_OFFSET), [ALT2].sel = 1, /* Index:44 Alt:3 No input selection */ @@ -2531,7 +2598,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:44 Alt:7 GPIO AD B0 02 LPSPI3 SDI */ - [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI3_SDI_OFFSET), + [ALT7].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI3_SDI_OFFSET), [ALT7].sel = 0, /* Index:44 Alt:8 No input selection */ @@ -2552,22 +2620,26 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:45 Alt:0 GPIO AD B0 03 FLEXCAN2 RX */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), [ALT0].sel = 1, /* Index:45 Alt:1 GPIO AD B0 03 XBAR1 INOUT17 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN17_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN17_OFFSET), [ALT1].sel = 1, /* Index:45 Alt:2 GPIO AD B0 03 LPUART6 RX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART6_RX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART6_RX_OFFSET), [ALT2].sel = 1, /* Index:45 Alt:3 GPIO AD B0 03 USB OTG1 OC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG1_OC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG1_OC_OFFSET), [ALT3].sel = 0, /* Index:45 Alt:4 No input selection */ @@ -2587,7 +2659,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:45 Alt:7 GPIO AD B0 03 LPSPI3 PCS0 */ - [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI3_PCS0_OFFSET), + [ALT7].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI3_PCS0_OFFSET), [ALT7].sel = 0, /* Index:45 Alt:8 No input selection */ @@ -2623,12 +2696,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:46 Alt:3 GPIO AD B0 04 SAI2 TX SYNC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_SYNC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_SYNC_OFFSET), [ALT3].sel = 1, /* Index:46 Alt:4 GPIO AD B0 04 CSI DATA09 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA09_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA09_OFFSET), [ALT4].sel = 1, /* Index:46 Alt:5 No input selection */ @@ -2679,12 +2754,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:47 Alt:3 GPIO AD B0 05 SAI2 TX BCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_BCLK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_BCLK_OFFSET), [ALT3].sel = 1, /* Index:47 Alt:4 GPIO AD B0 05 CSI DATA08 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA08_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA08_OFFSET), [ALT4].sel = 1, /* Index:47 Alt:5 No input selection */ @@ -2694,7 +2771,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:47 Alt:6 GPIO AD B0 05 XBAR1 INOUT17 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN17_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN17_OFFSET), [ALT6].sel = 2, /* Index:47 Alt:7 No input selection */ @@ -2735,12 +2813,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:48 Alt:3 GPIO AD B0 06 SAI2 RX BCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_BCLK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_BCLK_OFFSET), [ALT3].sel = 1, /* Index:48 Alt:4 GPIO AD B0 06 CSI DATA07 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA07_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA07_OFFSET), [ALT4].sel = 1, /* Index:48 Alt:5 No input selection */ @@ -2750,7 +2830,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:48 Alt:6 GPIO AD B0 06 XBAR1 INOUT18 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN18_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN18_OFFSET), [ALT6].sel = 1, /* Index:48 Alt:7 No input selection */ @@ -2791,12 +2872,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:49 Alt:3 GPIO AD B0 07 SAI2 RX SYNC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_SYNC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_SYNC_OFFSET), [ALT3].sel = 1, /* Index:49 Alt:4 GPIO AD B0 07 CSI DATA06 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA06_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA06_OFFSET), [ALT4].sel = 1, /* Index:49 Alt:5 No input selection */ @@ -2806,7 +2889,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:49 Alt:6 GPIO AD B0 07 XBAR1 INOUT19 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN19_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN19_OFFSET), [ALT6].sel = 1, /* Index:49 Alt:7 No input selection */ @@ -2847,12 +2931,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:50 Alt:3 GPIO AD B0 08 SAI2 RX DATA */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_DATA0_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_DATA0_OFFSET), [ALT3].sel = 1, /* Index:50 Alt:4 GPIO AD B0 08 CSI DATA05 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA05_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA05_OFFSET), [ALT4].sel = 1, /* Index:50 Alt:5 No input selection */ @@ -2862,7 +2948,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:50 Alt:6 GPIO AD B0 08 XBAR1 IN20 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN20_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN20_OFFSET), [ALT6].sel = 1, /* Index:50 Alt:7 No input selection */ @@ -2893,7 +2980,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:51 Alt:1 GPIO AD B0 09 FLEXPWM2 PWMA03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), [ALT1].sel = 3, /* Index:51 Alt:2 No input selection */ @@ -2908,7 +2996,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:51 Alt:4 GPIO AD B0 09 CSI DATA04 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA04_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA04_OFFSET), [ALT4].sel = 1, /* Index:51 Alt:5 No input selection */ @@ -2918,7 +3007,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:51 Alt:6 GPIO AD B0 09 XBAR1 IN21 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN21_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN21_OFFSET), [ALT6].sel = 1, /* Index:51 Alt:7 No input selection */ @@ -2949,7 +3039,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:52 Alt:1 GPIO AD B0 10 FLEXPWM1 PWMA03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), [ALT1].sel = 3, /* Index:52 Alt:2 No input selection */ @@ -2959,12 +3050,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:52 Alt:3 GPIO AD B0 10 SAI2 MCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_MCLK2_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_MCLK2_OFFSET), [ALT3].sel = 1, /* Index:52 Alt:4 GPIO AD B0 10 CSI DATA03 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA03_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA03_OFFSET), [ALT4].sel = 1, /* Index:52 Alt:5 No input selection */ @@ -2974,7 +3067,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:52 Alt:6 GPIO AD B0 10 XBAR1 IN22 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN22_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN22_OFFSET), [ALT6].sel = 1, /* Index:52 Alt:7 No input selection */ @@ -3005,7 +3099,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:53 Alt:1 GPIO AD B0 11 FLEXPWM1 PWMB03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), [ALT1].sel = 3, /* Index:53 Alt:2 No input selection */ @@ -3020,7 +3115,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:53 Alt:4 GPIO AD B0 11 CSI DATA02 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA02_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA02_OFFSET), [ALT4].sel = 1, /* Index:53 Alt:5 No input selection */ @@ -3030,12 +3126,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:53 Alt:6 GPIO AD B0 11 XBAR1 IN23 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN23_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN23_OFFSET), [ALT6].sel = 1, /* Index:53 Alt:7 GPIO AD B0 11 ENET 1588 EVENT0 IN */ - [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_TIMER_OFFSET), + [ALT7].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_TIMER_OFFSET), [ALT7].sel = 1, /* Index:53 Alt:8 No input selection */ @@ -3056,12 +3154,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:54 Alt:0 GPIO AD B0 12 LPI2C4 SCL */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C4_SCL_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C4_SCL_OFFSET), [ALT0].sel = 1, /* Index:54 Alt:1 GPIO AD B0 12 CCM PMIC READY */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), [ALT1].sel = 1, /* Index:54 Alt:2 No input selection */ @@ -3091,7 +3191,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:54 Alt:7 GPIO AD B0 12 NMI GLUE NMI */ - [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_NMI_GLUE_NMI_OFFSET), + [ALT7].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_NMI_GLUE_NMI_OFFSET), [ALT7].sel = 0, /* Index:54 Alt:8 No input selection */ @@ -3112,7 +3213,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:55 Alt:0 GPIO AD B0 13 LPI2C4 SDA */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C4_SDA_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C4_SDA_OFFSET), [ALT0].sel = 1, /* Index:55 Alt:1 No input selection */ @@ -3168,12 +3270,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:56 Alt:0 GPIO AD B0 14 USB OTG2 OC */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG2_OC_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG2_OC_OFFSET), [ALT0].sel = 0, /* Index:56 Alt:1 GPIO AD B0 14 XBAR1 IN24 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN24_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN24_OFFSET), [ALT1].sel = 1, /* Index:56 Alt:2 No input selection */ @@ -3188,7 +3292,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:56 Alt:4 GPIO AD B0 14 CSI VSYNC */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_VSYNC_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_VSYNC_OFFSET), [ALT4].sel = 0, /* Index:56 Alt:5 No input selection */ @@ -3229,7 +3334,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:57 Alt:1 GPIO AD B0 15 XBAR1 IN25 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN25_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN25_OFFSET), [ALT1].sel = 0, /* Index:57 Alt:2 No input selection */ @@ -3239,12 +3345,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:57 Alt:3 GPIO AD B0 15 ENET 1588 EVENT0 IN */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_TIMER_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_TIMER_OFFSET), [ALT3].sel = 0, /* Index:57 Alt:4 GPIO AD B0 15 CSI HSYNC */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_HSYNC_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_HSYNC_OFFSET), [ALT4].sel = 0, /* Index:57 Alt:5 No input selection */ @@ -3254,7 +3362,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:57 Alt:6 GPIO AD B0 15 FLEXCAN2 RX */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), [ALT6].sel = 2, /* Index:57 Alt:7 No input selection */ @@ -3280,12 +3389,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:58 Alt:0 GPIO AD B1 00 USB OTG2 ID */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET), [ALT0].sel = 1, /* Index:58 Alt:1 GPIO AD B1 00 QTIMER3 TIMER0 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER0_OFFSET), [ALT1].sel = 1, /* Index:58 Alt:2 No input selection */ @@ -3295,7 +3406,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:58 Alt:3 GPIO AD B1 00 LPI2C1 SCL */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C1_SCL_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C1_SCL_OFFSET), [ALT3].sel = 1, /* Index:58 Alt:4 No input selection */ @@ -3310,7 +3422,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:58 Alt:6 GPIO AD B1 00 USDHC1 WP */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_WP_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_WP_OFFSET), [ALT6].sel = 2, /* Index:58 Alt:7 No input selection */ @@ -3341,7 +3454,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:59 Alt:1 GPIO AD B1 01 QTIMER3 TIMER1 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER1_OFFSET), [ALT1].sel = 0, /* Index:59 Alt:2 No input selection */ @@ -3351,12 +3465,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:59 Alt:3 GPIO AD B1 01 LPI2C1 SDA */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C1_SDA_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C1_SDA_OFFSET), [ALT3].sel = 1, /* Index:59 Alt:4 GPIO AD B1 01 CCM PMIC READY */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), [ALT4].sel = 2, /* Index:59 Alt:5 No input selection */ @@ -3392,17 +3508,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:60 Alt:0 GPIO AD B1 02 USB OTG1 ID */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET), [ALT0].sel = 1, /* Index:60 Alt:1 GPIO AD B1 02 QTIMER3 TIMER2 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER2_OFFSET), [ALT1].sel = 1, /* Index:60 Alt:2 GPIO AD B1 02 LPUART2 TX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART2_TX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART2_TX_OFFSET), [ALT2].sel = 1, /* Index:60 Alt:3 No input selection */ @@ -3422,7 +3541,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:60 Alt:6 GPIO AD B1 02 USDHC1 CD B */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET), [ALT6].sel = 1, /* Index:60 Alt:7 No input selection */ @@ -3448,22 +3568,26 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:61 Alt:0 GPIO AD B1 03 USB OTG1 OC */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG1_OC_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG1_OC_OFFSET), [ALT0].sel = 1, /* Index:61 Alt:1 GPIO AD B1 03 QTIMER3 TIMER3 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER3_OFFSET), [ALT1].sel = 1, /* Index:61 Alt:2 GPIO AD B1 03 LPUART2 RX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART2_RX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART2_RX_OFFSET), [ALT2].sel = 1, /* Index:61 Alt:3 GPIO AD B1 03 SPDIF IN */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SPDIF_IN_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SPDIF_IN_OFFSET), [ALT3].sel = 0, /* Index:61 Alt:4 No input selection */ @@ -3478,7 +3602,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:61 Alt:6 GPIO AD B1 03 USDHC2 CD B */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CD_B_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CD_B_OFFSET), [ALT6].sel = 0, /* Index:61 Alt:7 No input selection */ @@ -3504,7 +3629,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:62 Alt:0 GPIO AD B1 04 FLEXSPIB DATA03 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET), [ALT0].sel = 1, /* Index:62 Alt:1 No input selection */ @@ -3514,7 +3640,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:62 Alt:2 GPIO AD B1 04 LPUART3 CTS B */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_CTS_B_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_CTS_B_OFFSET), [ALT2].sel = 1, /* Index:62 Alt:3 No input selection */ @@ -3524,7 +3651,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:62 Alt:4 GPIO AD B1 04 CSI PIXCLK */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_PIXCLK_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_PIXCLK_OFFSET), [ALT4].sel = 0, /* Index:62 Alt:5 No input selection */ @@ -3534,7 +3662,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:62 Alt:6 GPIO AD B1 04 USDHC2 DATA0 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA0_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA0_OFFSET), [ALT6].sel = 1, /* Index:62 Alt:7 No input selection */ @@ -3560,12 +3689,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:63 Alt:0 GPIO AD B1 05 FLEXSPIB DATA02 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET), [ALT0].sel = 1, /* Index:63 Alt:1 GPIO AD B1 05 ENET MDIO */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_MDIO_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_MDIO_OFFSET), [ALT1].sel = 0, /* Index:63 Alt:2 No input selection */ @@ -3590,7 +3721,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:63 Alt:6 GPIO AD B1 05 USDHC2 DATA1 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA1_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA1_OFFSET), [ALT6].sel = 1, /* Index:63 Alt:7 No input selection */ @@ -3616,17 +3748,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:64 Alt:0 GPIO AD B1 06 FLEXSPIB DATA01 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET), [ALT0].sel = 1, /* Index:64 Alt:1 GPIO AD B1 06 LPI2C3 SDA */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C3_SDA_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C3_SDA_OFFSET), [ALT1].sel = 2, /* Index:64 Alt:2 GPIO AD B1 06 LPUART3 TX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_TX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_TX_OFFSET), [ALT2].sel = 0, /* Index:64 Alt:3 No input selection */ @@ -3636,7 +3771,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:64 Alt:4 GPIO AD B1 06 CSI VSYNC */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_VSYNC_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_VSYNC_OFFSET), [ALT4].sel = 1, /* Index:64 Alt:5 No input selection */ @@ -3646,7 +3782,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:64 Alt:6 GPIO AD B1 06 USDHC2 DATA2 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA2_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA2_OFFSET), [ALT6].sel = 1, /* Index:64 Alt:7 No input selection */ @@ -3672,17 +3809,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:65 Alt:0 GPIO AD B1 07 FLEXSPIB DATA00 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET), [ALT0].sel = 1, /* Index:65 Alt:1 GPIO AD B1 07 LPI2C3 SCL */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C3_SCL_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C3_SCL_OFFSET), [ALT1].sel = 2, /* Index:65 Alt:2 GPIO AD B1 07 LPUART3 RX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_RX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_RX_OFFSET), [ALT2].sel = 0, /* Index:65 Alt:3 No input selection */ @@ -3692,7 +3832,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:65 Alt:4 GPIO AD B1 07 CSI HSYNC */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_HSYNC_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_HSYNC_OFFSET), [ALT4].sel = 1, /* Index:65 Alt:5 No input selection */ @@ -3702,7 +3843,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:65 Alt:6 GPIO AD B1 07 USDHC2 DATA3 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA3_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA3_OFFSET), [ALT6].sel = 1, /* Index:65 Alt:7 No input selection */ @@ -3733,7 +3875,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:66 Alt:1 GPIO AD B1 08 FLEXPWM4 PWMA00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET), [ALT1].sel = 1, /* Index:66 Alt:2 No input selection */ @@ -3743,12 +3886,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:66 Alt:3 GPIO AD B1 08 CCM PMIC READY */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), [ALT3].sel = 3, /* Index:66 Alt:4 GPIO AD B1 08 CSI DATA09 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA09_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA09_OFFSET), [ALT4].sel = 0, /* Index:66 Alt:5 No input selection */ @@ -3758,7 +3903,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:66 Alt:6 GPIO AD B1 08 USDHC2 CMD */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CMD_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CMD_OFFSET), [ALT6].sel = 1, /* Index:66 Alt:7 No input selection */ @@ -3784,27 +3930,32 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:67 Alt:0 GPIO AD B1 09 FLEXSPIA DQS */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DQS_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DQS_OFFSET), [ALT0].sel = 1, /* Index:67 Alt:1 GPIO AD B1 09 FLEXPWM4 PWMA01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET), [ALT1].sel = 1, /* Index:67 Alt:2 GPIO AD B1 09 FLEXCAN1 RX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), [ALT2].sel = 2, /* Index:67 Alt:3 GPIO AD B1 09 SAI1 MCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_MCLK2_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_MCLK2_OFFSET), [ALT3].sel = 1, /* Index:67 Alt:4 GPIO AD B1 09 CSI DATA08 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA08_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA08_OFFSET), [ALT4].sel = 0, /* Index:67 Alt:5 No input selection */ @@ -3814,7 +3965,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:67 Alt:6 GPIO AD B1 09 USDHC2 CLK */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CLK_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CLK_OFFSET), [ALT6].sel = 1, /* Index:67 Alt:7 No input selection */ @@ -3840,7 +3992,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:68 Alt:0 GPIO AD B1 10 FLEXSPIA DATA03 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET), [ALT0].sel = 1, /* Index:68 Alt:1 No input selection */ @@ -3850,17 +4003,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:68 Alt:2 GPIO AD B1 10 LPUART8 TX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_TX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_TX_OFFSET), [ALT2].sel = 1, /* Index:68 Alt:3 GPIO AD B1 10 SAI1 RX SYNC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_SYNC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_SYNC_OFFSET), [ALT3].sel = 1, /* Index:68 Alt:4 GPIO AD B1 10 CSI DATA07 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA07_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA07_OFFSET), [ALT4].sel = 0, /* Index:68 Alt:5 No input selection */ @@ -3870,7 +4026,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:68 Alt:6 GPIO AD B1 10 USDHC2 WP */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_WP_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_WP_OFFSET), [ALT6].sel = 1, /* Index:68 Alt:7 No input selection */ @@ -3896,7 +4053,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:69 Alt:0 GPIO AD B1 11 FLEXSPIA DATA02 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET), [ALT0].sel = 1, /* Index:69 Alt:1 No input selection */ @@ -3906,17 +4064,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:69 Alt:2 GPIO AD B1 11 LPUART8 RX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_RX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_RX_OFFSET), [ALT2].sel = 1, /* Index:69 Alt:3 GPIO AD B1 11 SAI1 RX BCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_BCLK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_BCLK_OFFSET), [ALT3].sel = 1, /* Index:69 Alt:4 GPIO AD B1 11 CSI DATA06 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA06_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA06_OFFSET), [ALT4].sel = 0, /* Index:69 Alt:5 No input selection */ @@ -3952,7 +4113,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:70 Alt:0 GPIO AD B1 12 FLEXSPIA DATA01 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET), [ALT0].sel = 1, /* Index:70 Alt:1 No input selection */ @@ -3962,17 +4124,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:70 Alt:2 GPIO AD B1 12 LPSPI3 PCS0 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI3_PCS0_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI3_PCS0_OFFSET), [ALT2].sel = 1, /* Index:70 Alt:3 GPIO AD B1 12 SAI1 RX DATA00 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA0_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA0_OFFSET), [ALT3].sel = 1, /* Index:70 Alt:4 GPIO AD B1 12 CSI DATA05 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA05_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA05_OFFSET), [ALT4].sel = 0, /* Index:70 Alt:5 No input selection */ @@ -3982,7 +4147,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:70 Alt:6 GPIO AD B1 12 USDHC2 DATA4 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA4_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA4_OFFSET), [ALT6].sel = 1, /* Index:70 Alt:7 No input selection */ @@ -4008,7 +4174,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:71 Alt:0 GPIO AD B1 13 FLEXSPIA DATA00 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET), [ALT0].sel = 1, /* Index:71 Alt:1 No input selection */ @@ -4018,7 +4185,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:71 Alt:2 GPIO AD B1 13 LPSPI3 SDI */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI3_SDI_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI3_SDI_OFFSET), [ALT2].sel = 1, /* Index:71 Alt:3 No input selection */ @@ -4028,7 +4196,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:71 Alt:4 GPIO AD B1 13 CSI DATA04 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA04_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA04_OFFSET), [ALT4].sel = 0, /* Index:71 Alt:5 No input selection */ @@ -4038,7 +4207,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:71 Alt:6 GPIO AD B1 13 USDHC2 DATA5 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA5_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA5_OFFSET), [ALT6].sel = 1, /* Index:71 Alt:7 No input selection */ @@ -4064,7 +4234,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:72 Alt:0 GPIO AD B1 14 FLEXSPIA SCLK */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_SCK_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_SCK_OFFSET), [ALT0].sel = 1, /* Index:72 Alt:1 No input selection */ @@ -4074,17 +4245,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:72 Alt:2 GPIO AD B1 14 LPSPI3 SDO */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI3_SDO_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI3_SDO_OFFSET), [ALT2].sel = 1, /* Index:72 Alt:3 GPIO AD B1 14 SAI1 TX BCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_BCLK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_BCLK_OFFSET), [ALT3].sel = 1, /* Index:72 Alt:4 GPIO AD B1 14 CSI DATA03 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA03_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA03_OFFSET), [ALT4].sel = 0, /* Index:72 Alt:5 No input selection */ @@ -4094,7 +4268,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:72 Alt:6 GPIO AD B1 14 USDHC2 DATA6 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA6_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA6_OFFSET), [ALT6].sel = 1, /* Index:72 Alt:7 No input selection */ @@ -4135,12 +4310,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:73 Alt:3 GPIO AD B1 15 SAI1 TX SYNC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_SYNC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_SYNC_OFFSET), [ALT3].sel = 1, /* Index:73 Alt:4 GPIO AD B1 15 CSI DATA02 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA02_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA02_OFFSET), [ALT4].sel = 0, /* Index:73 Alt:5 No input selection */ @@ -4150,7 +4327,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:73 Alt:6 GPIO AD B1 15 USDHC2 DATA7 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA7_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA7_OFFSET), [ALT6].sel = 1, /* Index:73 Alt:7 No input selection */ @@ -4191,7 +4369,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:74 Alt:3 GPIO B0 00 LPSPI4 PCS0 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_PCS0_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_PCS0_OFFSET), [ALT3].sel = 0, /* Index:74 Alt:4 No input selection */ @@ -4247,7 +4426,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:75 Alt:3 GPIO B0 01 LPSPI4 SDI */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SDI_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SDI_OFFSET), [ALT3].sel = 0, /* Index:75 Alt:4 No input selection */ @@ -4303,7 +4483,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:76 Alt:3 GPIO B0 02 LPSPI4 SDO */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SDO_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SDO_OFFSET), [ALT3].sel = 0, /* Index:76 Alt:4 No input selection */ @@ -4349,17 +4530,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:77 Alt:1 GPIO B0 03 QTIMER2 TIMER0 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER0_OFFSET), [ALT1].sel = 1, /* Index:77 Alt:2 GPIO B0 03 FLEXCAN1 RX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), [ALT2].sel = 3, /* Index:77 Alt:3 GPIO B0 03 LPSPI4 SCK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SCK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SCK_OFFSET), [ALT3].sel = 0, /* Index:77 Alt:4 No input selection */ @@ -4405,12 +4589,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:78 Alt:1 GPIO B0 04 QTIMER2 TIMER1 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER1_OFFSET), [ALT1].sel = 1, /* Index:78 Alt:2 GPIO B0 04 LPI2C2 SCL */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C2_SCL_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C2_SCL_OFFSET), [ALT2].sel = 1, /* Index:78 Alt:3 No input selection */ @@ -4461,12 +4647,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:79 Alt:1 GPIO B0 05 QTIMER2 TIMER2 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER2_OFFSET), [ALT1].sel = 1, /* Index:79 Alt:2 GPIO B0 05 LPI2C2 SDA */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C2_SDA_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C2_SDA_OFFSET), [ALT2].sel = 1, /* Index:79 Alt:3 No input selection */ @@ -4517,12 +4705,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:80 Alt:1 GPIO B0 06 QTIMER3 TIMER0 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER0_OFFSET), [ALT1].sel = 2, /* Index:80 Alt:2 GPIO B0 06 FLEXPWM2 PWMA00 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET), [ALT2].sel = 1, /* Index:80 Alt:3 No input selection */ @@ -4573,12 +4763,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:81 Alt:1 GPIO B0 07 QTIMER3 TIMER1 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER1_OFFSET), [ALT1].sel = 2, /* Index:81 Alt:2 GPIO B0 07 FLEXPWM2 PWMB00 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET), [ALT2].sel = 1, /* Index:81 Alt:3 No input selection */ @@ -4629,17 +4821,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:82 Alt:1 GPIO B0 08 QTIMER3 TIMER2 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER2_OFFSET), [ALT1].sel = 2, /* Index:82 Alt:2 GPIO B0 08 FLEXPWM2 PWMA01 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET), [ALT2].sel = 1, /* Index:82 Alt:3 GPIO B0 08 LPUART3 TX */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_TX_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_TX_OFFSET), [ALT3].sel = 2, /* Index:82 Alt:4 No input selection */ @@ -4690,12 +4885,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:83 Alt:2 GPIO B0 09 FLEXPWM2 PWMB01 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET), [ALT2].sel = 1, /* Index:83 Alt:3 GPIO B0 09 LPUART3 RX */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_RX_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_RX_OFFSET), [ALT3].sel = 2, /* Index:83 Alt:4 No input selection */ @@ -4746,12 +4943,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:84 Alt:2 GPIO B0 10 FLEXPWM2 PWMA02 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET), [ALT2].sel = 1, /* Index:84 Alt:3 GPIO B0 10 SAI1 TX DATA03 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA1_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA1_OFFSET), [ALT3].sel = 1, /* Index:84 Alt:4 No input selection */ @@ -4802,12 +5001,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:85 Alt:2 GPIO B0 11 FLEXPWM2 PWMB02 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET), [ALT2].sel = 1, /* Index:85 Alt:3 GPIO B0 11 SAI1 TX DATA02 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA2_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA2_OFFSET), [ALT3].sel = 1, /* Index:85 Alt:4 No input selection */ @@ -4863,7 +5064,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:86 Alt:3 GPIO B0 12 SAI1 TX DATA01 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA3_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA3_OFFSET), [ALT3].sel = 1, /* Index:86 Alt:4 No input selection */ @@ -4919,7 +5121,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:87 Alt:3 GPIO B0 13 SAI1 MCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_MCLK2_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_MCLK2_OFFSET), [ALT3].sel = 2, /* Index:87 Alt:4 No input selection */ @@ -4975,7 +5178,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:88 Alt:3 GPIO B0 14 SAI1 RX SYNC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_SYNC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_SYNC_OFFSET), [ALT3].sel = 2, /* Index:88 Alt:4 No input selection */ @@ -5031,7 +5235,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:89 Alt:3 GPIO B0 15 SAI1 RX BCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_BCLK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_BCLK_OFFSET), [ALT3].sel = 2, /* Index:89 Alt:4 No input selection */ @@ -5077,17 +5282,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:90 Alt:1 GPIO B1 00 XBAR1 INOUT14 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN14_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN14_OFFSET), [ALT1].sel = 1, /* Index:90 Alt:2 GPIO B1 00 LPUART4 TX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_TX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_TX_OFFSET), [ALT2].sel = 2, /* Index:90 Alt:3 GPIO B1 00 SAI1 RX DATA00 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA0_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA0_OFFSET), [ALT3].sel = 2, /* Index:90 Alt:4 No input selection */ @@ -5102,7 +5310,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:90 Alt:6 GPIO B1 00 FLEXPWM1 PWMA03 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), [ALT6].sel = 4, /* Index:90 Alt:7 No input selection */ @@ -5133,12 +5342,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:91 Alt:1 GPIO B1 01 XBAR1 INOUT15 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN15_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN15_OFFSET), [ALT1].sel = 1, /* Index:91 Alt:2 GPIO B1 01 LPUART4 RX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_RX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_RX_OFFSET), [ALT2].sel = 2, /* Index:91 Alt:3 No input selection */ @@ -5158,7 +5369,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:91 Alt:6 GPIO B1 01 FLEXPWM1 PWMB03 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), [ALT6].sel = 4, /* Index:91 Alt:7 No input selection */ @@ -5189,7 +5401,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:92 Alt:1 GPIO B1 02 XBAR1 INOUT16 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN16_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN16_OFFSET), [ALT1].sel = 1, /* Index:92 Alt:2 No input selection */ @@ -5199,7 +5412,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:92 Alt:3 GPIO B1 02 SAI1 TX BCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_BCLK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_BCLK_OFFSET), [ALT3].sel = 2, /* Index:92 Alt:4 No input selection */ @@ -5214,7 +5428,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:92 Alt:6 GPIO B1 02 FLEXPWM2 PWMA03 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), [ALT6].sel = 4, /* Index:92 Alt:7 No input selection */ @@ -5245,7 +5460,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:93 Alt:1 GPIO B1 03 XBAR1 INOUT17 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN17_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN17_OFFSET), [ALT1].sel = 3, /* Index:93 Alt:2 No input selection */ @@ -5255,7 +5471,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:93 Alt:3 GPIO B1 03 SAI1 TX SYNC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_SYNC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_SYNC_OFFSET), [ALT3].sel = 2, /* Index:93 Alt:4 No input selection */ @@ -5270,7 +5487,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:93 Alt:6 GPIO B1 03 FLEXPWM2 PWMB03 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET), [ALT6].sel = 3, /* Index:93 Alt:7 No input selection */ @@ -5301,7 +5519,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:94 Alt:1 GPIO B1 04 LPSPI4 PCS0 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_PCS0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_PCS0_OFFSET), [ALT1].sel = 1, /* Index:94 Alt:2 No input selection */ @@ -5311,7 +5530,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:94 Alt:3 GPIO B1 04 ENET RX DATA00 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_RXDATA_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_RXDATA_OFFSET), [ALT3].sel = 1, /* Index:94 Alt:4 No input selection */ @@ -5357,7 +5577,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:95 Alt:1 GPIO B1 05 LPSPI4 SDI */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SDI_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SDI_OFFSET), [ALT1].sel = 1, /* Index:95 Alt:2 No input selection */ @@ -5367,7 +5588,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:95 Alt:3 GPIO B1 05 ENET RX DATA01 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET1_RXDATA_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET1_RXDATA_OFFSET), [ALT3].sel = 1, /* Index:95 Alt:4 No input selection */ @@ -5413,7 +5635,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:96 Alt:1 GPIO B1 06 LPSPI4 SDO */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SDO_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SDO_OFFSET), [ALT1].sel = 1, /* Index:96 Alt:2 No input selection */ @@ -5423,7 +5646,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:96 Alt:3 GPIO B1 06 ENET RX EN */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXEN_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXEN_OFFSET), [ALT3].sel = 1, /* Index:96 Alt:4 No input selection */ @@ -5469,7 +5693,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:97 Alt:1 GPIO B1 07 LPSPI4 SCK */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SCK_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SCK_OFFSET), [ALT1].sel = 1, /* Index:97 Alt:2 No input selection */ @@ -5581,7 +5806,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:99 Alt:1 GPIO B1 09 QTIMER2 TIMER3 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER3_OFFSET), [ALT1].sel = 1, /* Index:99 Alt:2 No input selection */ @@ -5606,7 +5832,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:99 Alt:6 GPIO B1 09 FLEXCAN2 RX */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), [ALT6].sel = 3, /* Index:99 Alt:7 No input selection */ @@ -5637,7 +5864,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:100 Alt:1 GPIO B1 10 QTIMER3 TIMER3 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER3_OFFSET), [ALT1].sel = 2, /* Index:100 Alt:2 No input selection */ @@ -5647,7 +5875,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:100 Alt:3 GPIO B1 10 ENET TX CLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_TXCLK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_TXCLK_OFFSET), [ALT3].sel = 1, /* Index:100 Alt:4 No input selection */ @@ -5662,7 +5891,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:100 Alt:6 GPIO B1 10 ENET REF CLK */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET), [ALT6].sel = 1, /* Index:100 Alt:7 No input selection */ @@ -5703,7 +5933,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:101 Alt:3 GPIO B1 11 ENET RX ER */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXERR_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXERR_OFFSET), [ALT3].sel = 1, /* Index:101 Alt:4 No input selection */ @@ -5749,17 +5980,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:102 Alt:1 GPIO B1 12 LPUART5 TX */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART5_TX_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART5_TX_OFFSET), [ALT1].sel = 1, /* Index:102 Alt:2 GPIO B1 12 CSI PIXCLK */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_PIXCLK_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_PIXCLK_OFFSET), [ALT2].sel = 1, /* Index:102 Alt:3 GPIO B1 12 ENET 1588 EVENT0 IN */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_TIMER_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_TIMER_OFFSET), [ALT3].sel = 2, /* Index:102 Alt:4 No input selection */ @@ -5774,7 +6008,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:102 Alt:6 GPIO B1 12 USDHC1 CD B */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET), [ALT6].sel = 2, /* Index:102 Alt:7 No input selection */ @@ -5805,12 +6040,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:103 Alt:1 GPIO B1 13 LPUART5 RX */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART5_RX_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART5_RX_OFFSET), [ALT1].sel = 1, /* Index:103 Alt:2 GPIO B1 13 CSI VSYNC */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_VSYNC_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_VSYNC_OFFSET), [ALT2].sel = 2, /* Index:103 Alt:3 No input selection */ @@ -5830,7 +6067,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:103 Alt:6 GPIO B1 13 USDHC1 WP */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_WP_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_WP_OFFSET), [ALT6].sel = 3, /* Index:103 Alt:7 No input selection */ @@ -5861,17 +6099,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:104 Alt:1 GPIO B1 14 FLEXPWM4 PWMA02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET), [ALT1].sel = 1, /* Index:104 Alt:2 GPIO B1 14 CSI HSYNC */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_HSYNC_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_HSYNC_OFFSET), [ALT2].sel = 2, /* Index:104 Alt:3 GPIO B1 14 XBAR1 IN02 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN02_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN02_OFFSET), [ALT3].sel = 1, /* Index:104 Alt:4 No input selection */ @@ -5912,12 +6153,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:105 Alt:0 GPIO B1 15 ENET MDIO */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_MDIO_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_MDIO_OFFSET), [ALT0].sel = 2, /* Index:105 Alt:1 GPIO B1 15 FLEXPWM4 PWMA03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET), [ALT1].sel = 1, /* Index:105 Alt:2 No input selection */ @@ -5927,7 +6170,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:105 Alt:3 GPIO B1 15 XBAR1 IN03 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN03_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN03_OFFSET), [ALT3].sel = 1, /* Index:105 Alt:4 No input selection */ @@ -5973,22 +6217,26 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:106 Alt:1 GPIO SD B0 00 FLEXPWM1 PWMA00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET), [ALT1].sel = 1, /* Index:106 Alt:2 GPIO SD B0 00 LPI2C3 SCL */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C3_SCL_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C3_SCL_OFFSET), [ALT2].sel = 1, /* Index:106 Alt:3 GPIO SD B0 00 XBAR1 INOUT04 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN04_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN04_OFFSET), [ALT3].sel = 1, /* Index:106 Alt:4 GPIO SD B0 00 LPSPI1 SCK */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_SCK_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_SCK_OFFSET), [ALT4].sel = 1, /* Index:106 Alt:5 No input selection */ @@ -6029,22 +6277,26 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:107 Alt:1 GPIO SD B0 01 FLEXPWM1 PWMB00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET), [ALT1].sel = 1, /* Index:107 Alt:2 GPIO SD B0 01 LPI2C3 SDA */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C3_SDA_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C3_SDA_OFFSET), [ALT2].sel = 1, /* Index:107 Alt:3 GPIO SD B0 01 XBAR1 INOUT05 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN05_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN05_OFFSET), [ALT3].sel = 1, /* Index:107 Alt:4 GPIO SD B0 01 LPSPI1 PCS0 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_PCS0_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_PCS0_OFFSET), [ALT4].sel = 0, /* Index:107 Alt:5 No input selection */ @@ -6085,7 +6337,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:108 Alt:1 GPIO SD B0 02 FLEXPWM1 PWMA01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET), [ALT1].sel = 1, /* Index:108 Alt:2 No input selection */ @@ -6095,12 +6348,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:108 Alt:3 GPIO SD B0 02 XBAR1 INOUT06 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN06_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN06_OFFSET), [ALT3].sel = 1, /* Index:108 Alt:4 GPIO SD B0 02 LPSPI1 SDO */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_SDO_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_SDO_OFFSET), [ALT4].sel = 1, /* Index:108 Alt:5 No input selection */ @@ -6141,7 +6396,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:109 Alt:1 GPIO SD B0 03 FLEXPWM1 PWMB01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET), [ALT1].sel = 1, /* Index:109 Alt:2 No input selection */ @@ -6151,12 +6407,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:109 Alt:3 GPIO SD B0 03 XBAR1 INOUT07 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN07_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN07_OFFSET), [ALT3].sel = 1, /* Index:109 Alt:4 GPIO SD B0 03 LPSPI1 SDI */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_SDI_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_SDI_OFFSET), [ALT4].sel = 1, /* Index:109 Alt:5 No input selection */ @@ -6197,17 +6455,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:110 Alt:1 GPIO SD B0 04 FLEXPWM1 PWMA02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET), [ALT1].sel = 1, /* Index:110 Alt:2 GPIO SD B0 04 LPUART8 TX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_TX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_TX_OFFSET), [ALT2].sel = 0, /* Index:110 Alt:3 GPIO SD B0 04 XBAR1 INOUT08 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN08_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN08_OFFSET), [ALT3].sel = 1, /* Index:110 Alt:4 No input selection */ @@ -6253,17 +6514,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:111 Alt:1 GPIO SD B0 05 FLEXPWM1 PWMB02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET), [ALT1].sel = 1, /* Index:111 Alt:2 GPIO SD B0 05 LPUART8 RX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_RX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_RX_OFFSET), [ALT2].sel = 0, /* Index:111 Alt:3 GPIO SD B0 05 XBAR1 INOUT09 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN09_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN09_OFFSET), [ALT3].sel = 1, /* Index:111 Alt:4 No input selection */ @@ -6304,27 +6568,32 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:112 Alt:0 GPIO SD B1 00 USDHC2 DATA3 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA3_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA3_OFFSET), [ALT0].sel = 0, /* Index:112 Alt:1 GPIO SD B1 00 FLEXSPIB DATA03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET), [ALT1].sel = 0, /* Index:112 Alt:2 GPIO SD B1 00 FLEXPWM1 PWMA03 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), [ALT2].sel = 0, /* Index:112 Alt:3 GPIO SD B1 00 SAI1 TX DATA03 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA1_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA1_OFFSET), [ALT3].sel = 0, /* Index:112 Alt:4 GPIO SD B1 00 LPUART4 TX */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_TX_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_TX_OFFSET), [ALT4].sel = 0, /* Index:112 Alt:5 No input selection */ @@ -6360,22 +6629,26 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:113 Alt:0 GPIO SD B1 01 USDHC2 DATA2 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA2_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA2_OFFSET), [ALT0].sel = 0, /* Index:113 Alt:1 GPIO SD B1 01 FLEXSPIB DATA02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET), [ALT1].sel = 0, /* Index:113 Alt:2 GPIO SD B1 01 FLEXPWM1 PWMB03 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), [ALT2].sel = 0, /* Index:113 Alt:3 GPIO SD B1 01 SAI1 TX DATA02 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA2_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA2_OFFSET), [ALT3].sel = 0, /* Index:113 Alt:4 GPIO SD B1 01 LPUART4 RX */ @@ -6416,22 +6689,26 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:114 Alt:0 GPIO SD B1 02 USDHC2 DATA1 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA1_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA1_OFFSET), [ALT0].sel = 0, /* Index:114 Alt:1 GPIO SD B1 02 FLEXSPIB DATA01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET), [ALT1].sel = 0, /* Index:114 Alt:2 GPIO SD B1 02 FLEXPWM2 PWMA03 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), [ALT2].sel = 0, /* Index:114 Alt:3 GPIO SD B1 02 SAI1 TX DATA01 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA3_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA3_OFFSET), [ALT3].sel = 0, /* Index:114 Alt:4 No input selection */ @@ -6472,17 +6749,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:115 Alt:0 GPIO SD B1 03 USDHC2 DATA0 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA0_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA0_OFFSET), [ALT0].sel = 0, /* Index:115 Alt:1 GPIO SD B1 03 FLEXSPIB DATA00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET), [ALT1].sel = 0, /* Index:115 Alt:2 GPIO SD B1 03 FLEXPWM2 PWMB03 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET), [ALT2].sel = 0, /* Index:115 Alt:3 GPIO SD B1 03 SAI1 MCLK */ @@ -6492,7 +6772,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:115 Alt:4 GPIO SD B1 03 FLEXCAN1 RX */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), [ALT4].sel = 0, /* Index:115 Alt:5 No input selection */ @@ -6502,7 +6783,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:115 Alt:6 GPIO SD B1 03 CCM PMIC READY */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), [ALT6].sel = 0, /* Index:115 Alt:7 No input selection */ @@ -6528,7 +6810,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:116 Alt:0 GPIO SD B1 04 USDHC2 CLK */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CLK_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CLK_OFFSET), [ALT0].sel = 0, /* Index:116 Alt:1 No input selection */ @@ -6543,7 +6826,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:116 Alt:3 GPIO SD B1 04 SAI1 RX SYNC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_SYNC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_SYNC_OFFSET), [ALT3].sel = 0, /* Index:116 Alt:4 No input selection */ @@ -6584,22 +6868,26 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:117 Alt:0 GPIO SD B1 05 USDHC2 CMD */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CMD_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CMD_OFFSET), [ALT0].sel = 0, /* Index:117 Alt:1 GPIO SD B1 05 FLEXSPIA DQS */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DQS_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DQS_OFFSET), [ALT1].sel = 0, /* Index:117 Alt:2 GPIO SD B1 05 LPI2C1 SDA */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C1_SDA_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C1_SDA_OFFSET), [ALT2].sel = 0, /* Index:117 Alt:3 GPIO SD B1 05 SAI1 RX BCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_BCLK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_BCLK_OFFSET), [ALT3].sel = 0, /* Index:117 Alt:4 No input selection */ @@ -6655,12 +6943,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:118 Alt:3 GPIO SD B1 06 SAI1 RX DATA00 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA0_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA0_OFFSET), [ALT3].sel = 0, /* Index:118 Alt:4 GPIO SD B1 06 LPSPI2 PCS0 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_PCS0_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_PCS0_OFFSET), [ALT4].sel = 0, /* Index:118 Alt:5 No input selection */ @@ -6701,7 +6991,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:119 Alt:1 GPIO SD B1 07 FLEXSPIA SCLK */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_SCK_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_SCK_OFFSET), [ALT1].sel = 0, /* Index:119 Alt:2 No input selection */ @@ -6716,7 +7007,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:119 Alt:4 GPIO SD B1 07 LPSPI2 SCK */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_SCK_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_SCK_OFFSET), [ALT4].sel = 0, /* Index:119 Alt:5 No input selection */ @@ -6752,12 +7044,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:120 Alt:0 GPIO SD B1 08 USDHC2 DATA4 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA4_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA4_OFFSET), [ALT0].sel = 0, /* Index:120 Alt:1 GPIO SD B1 08 FLEXSPIA DATA00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET), [ALT1].sel = 0, /* Index:120 Alt:2 GPIO SD B1 08 LPUART7 TX */ @@ -6767,7 +7061,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:120 Alt:3 GPIO SD B1 08 SAI1 TX BCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_BCLK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_BCLK_OFFSET), [ALT3].sel = 0, /* Index:120 Alt:4 GPIO SD B1 08 LPSPI2 SD0 */ @@ -6808,22 +7103,26 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:121 Alt:0 GPIO SD B1 09 USDHC2 DATA5 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA5_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA5_OFFSET), [ALT0].sel = 0, /* Index:121 Alt:1 GPIO SD B1 09 FLEXSPIA DATA01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET), [ALT1].sel = 0, /* Index:121 Alt:2 GPIO SD B1 09 LPUART7 RX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART7_RX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART7_RX_OFFSET), [ALT2].sel = 0, /* Index:121 Alt:3 GPIO SD B1 09 SAI1 TX SYNC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_SYNC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_SYNC_OFFSET), [ALT3].sel = 0, /* Index:121 Alt:4 GPIO SD B1 09 LPSPI2 SDI */ @@ -6864,12 +7163,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:122 Alt:0 GPIO SD B1 10 USDHC2 DATA6 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA6_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA6_OFFSET), [ALT0].sel = 0, /* Index:122 Alt:1 GPIO SD B1 10 FLEXSPIA DATA02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET), [ALT1].sel = 0, /* Index:122 Alt:2 GPIO SD B1 10 LPUART2 RX */ @@ -6920,12 +7221,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:123 Alt:0 GPIO SD B1 11 USDHC2 DATA7 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA7_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA7_OFFSET), [ALT0].sel = 0, /* Index:123 Alt:1 GPIO SD B1 11 FLEXSPIA DATA03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET), [ALT1].sel = 0, /* Index:123 Alt:2 GPIO SD B1 11 LPUART2 TX */ @@ -7011,7 +7314,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:124 Alt:7 SNVS WAKEUP NMI GLUE NMI */ - [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_NMI_GLUE_NMI_OFFSET), + [ALT7].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_NMI_GLUE_NMI_OFFSET), [ALT7].sel = 1, /* Index:124 Alt:8 No input selection */ @@ -7082,3 +7386,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = }, }, }; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + diff --git a/arch/arm/src/imxrt/imxrt106x_daisy.c b/arch/arm/src/imxrt/imxrt106x_daisy.c index 5813ef7879f..05e7d84bb99 100644 --- a/arch/arm/src/imxrt/imxrt106x_daisy.c +++ b/arch/arm/src/imxrt/imxrt106x_daisy.c @@ -37,7 +37,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:0 Alt:1 GPIO EMC 00 FLEXPWM4 PWMA00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET), [ALT1].sel = 0, /* Index:0 Alt:2 GPIO EMC 00 LPSPI2 SCK */ @@ -98,7 +99,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:1 Alt:2 GPIO EMC 01 LPSPI2 PCS0 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_PCS0_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_PCS0_OFFSET), [ALT2].sel = 1, /* Index:1 Alt:3 GPIO EMC 01 XBAR1 IN03 */ @@ -149,7 +151,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:2 Alt:1 GPIO EMC 02 FLEXPWM4 PWMA01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET), [ALT1].sel = 0, /* Index:2 Alt:2 GPIO EMC 02 LPSPI2 SDO */ @@ -261,7 +264,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:4 Alt:1 GPIO EMC 04 FLEXPWM4 PWMA02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET), [ALT1].sel = 0, /* Index:4 Alt:2 No input selection */ @@ -322,7 +326,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:5 Alt:2 GPIO EMC 05 SAI2 TX SYNC */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_SYNC_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_SYNC_OFFSET), [ALT2].sel = 0, /* Index:5 Alt:3 GPIO EMC 05 XBAR1 INOUT07 */ @@ -373,12 +378,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:6 Alt:1 GPIO EMC 06 FLEXPWM2 PWMA00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET), [ALT1].sel = 0, /* Index:6 Alt:2 GPIO EMC 06 SAI2 TX BCLK */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_BCLK_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_BCLK_OFFSET), [ALT2].sel = 0, /* Index:6 Alt:3 GPIO EMC 06 XBAR1 INOUT08 */ @@ -429,7 +436,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:7 Alt:1 GPIO EMC 07 FLEXPWM2 PWMB00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET), [ALT1].sel = 0, /* Index:7 Alt:2 GPIO EMC 07 SAI2 MCLK */ @@ -485,12 +493,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:8 Alt:1 GPIO EMC 08 FLEXPWM2 PWMA01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET), [ALT1].sel = 0, /* Index:8 Alt:2 GPIO EMC 08 SAI2 RX DATA */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_DATA0_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_DATA0_OFFSET), [ALT2].sel = 0, /* Index:8 Alt:3 GPIO EMC 08 XBAR1 INOUT17 */ @@ -541,12 +551,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:9 Alt:1 GPIO EMC 09 FLEXPWM2 PWMB01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET), [ALT1].sel = 0, /* Index:9 Alt:2 GPIO EMC 09 SAI2 RX SYNC */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_SYNC_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_SYNC_OFFSET), [ALT2].sel = 0, /* Index:9 Alt:3 No input selection */ @@ -597,17 +609,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:10 Alt:1 GPIO EMC 10 FLEXPWM2 PWMA02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET), [ALT1].sel = 0, /* Index:10 Alt:2 GPIO EMC 10 SAI2 RX BCLK */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_BCLK_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_BCLK_OFFSET), [ALT2].sel = 0, /* Index:10 Alt:3 GPIO EMC 10 FLEXCAN2 RX */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), [ALT3].sel = 0, /* Index:10 Alt:4 No input selection */ @@ -653,7 +668,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:11 Alt:1 GPIO EMC 11 FLEXPWM2 PWMB02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET), [ALT1].sel = 0, /* Index:11 Alt:2 GPIO EMC 11 LPI2C4 SDA */ @@ -724,7 +740,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:12 Alt:4 GPIO EMC 12 FLEXPWM1 PWMA03 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), [ALT4].sel = 1, /* Index:12 Alt:5 No input selection */ @@ -744,7 +761,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:12 Alt:8 GPIO EMC 12 FLEXSPI2 B SCLK */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FB_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FB_OFFSET), [ALT8].sel = 0, /* Index:12 Alt:9 No input selection */ @@ -780,7 +799,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:13 Alt:4 GPIO EMC 13 FLEXPWM1 PWMB03 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), [ALT4].sel = 1, /* Index:13 Alt:5 No input selection */ @@ -800,7 +820,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:13 Alt:8 GPIO EMC 13 FLEXSPI2 B DATA00 */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT0_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT0_OFFSET), [ALT8].sel = 0, /* Index:13 Alt:9 No input selection */ @@ -856,7 +878,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:14 Alt:8 GPIO EMC 14 FLEXSPI2 B DATA01 */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT1_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT1_OFFSET), [ALT8].sel = 0, /* Index:14 Alt:9 No input selection */ @@ -882,7 +906,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:15 Alt:2 GPIO EMC 15 LPUART3 CTS B */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_CTS_B_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_CTS_B_OFFSET), [ALT2].sel = 0, /* Index:15 Alt:3 No input selection */ @@ -892,7 +917,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:15 Alt:4 GPIO EMC 15 QTIMER3 TIMER0 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER0_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER0_OFFSET), [ALT4].sel = 0, /* Index:15 Alt:5 No input selection */ @@ -912,7 +938,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:15 Alt:8 GPIO EMC 15 FLEXSPI2 B DATA02 */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT2_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT2_OFFSET), [ALT8].sel = 0, /* Index:15 Alt:9 No input selection */ @@ -948,7 +976,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:16 Alt:4 GPIO EMC 16 QTIMER3 TIMER1 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER1_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER1_OFFSET), [ALT4].sel = 1, /* Index:16 Alt:5 No input selection */ @@ -968,7 +997,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:16 Alt:8 GPIO EMC 16 FLEXSPI2 B DATA03 */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT3_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT3_OFFSET), [ALT8].sel = 0, /* Index:16 Alt:9 No input selection */ @@ -989,7 +1020,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:17 Alt:1 GPIO EMC 17 FLEXPWM4 PWMA03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET), [ALT1].sel = 0, /* Index:17 Alt:2 No input selection */ @@ -1004,7 +1036,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:17 Alt:4 GPIO EMC 17 QTIMER3 TIMER2 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER2_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER2_OFFSET), [ALT4].sel = 0, /* Index:17 Alt:5 No input selection */ @@ -1055,12 +1088,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:18 Alt:3 GPIO EMC 18 FLEXCAN1 RX */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), [ALT3].sel = 1, /* Index:18 Alt:4 GPIO EMC 18 QTIMER3 TIMER3 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER3_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER3_OFFSET), [ALT4].sel = 0, /* Index:18 Alt:5 No input selection */ @@ -1101,7 +1136,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:19 Alt:1 GPIO EMC 19 FLEXPWM2 PWMA03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), [ALT1].sel = 1, /* Index:19 Alt:2 GPIO EMC 19 LPUART4 TX */ @@ -1111,12 +1147,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:19 Alt:3 GPIO EMC 19 ENET RDATA01 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET1_RXDATA_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET1_RXDATA_OFFSET), [ALT3].sel = 0, /* Index:19 Alt:4 GPIO EMC 19 QTIMER2 TIMER0 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER0_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER0_OFFSET), [ALT4].sel = 0, /* Index:19 Alt:5 No input selection */ @@ -1157,22 +1195,26 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:20 Alt:1 GPIO EMC 20 FLEXPWM2 PWMB03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET), [ALT1].sel = 1, /* Index:20 Alt:2 GPIO EMC 20 LPUART4 RX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_RX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_RX_OFFSET), [ALT2].sel = 1, /* Index:20 Alt:3 GPIO EMC 20 ENET RDATA00 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_RXDATA_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_RXDATA_OFFSET), [ALT3].sel = 0, /* Index:20 Alt:4 GPIO EMC 20 QTIMER2 TIMER1 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER1_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER1_OFFSET), [ALT4].sel = 0, /* Index:20 Alt:5 No input selection */ @@ -1228,7 +1270,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:21 Alt:4 GPIO EMC 21 QTIMER2 TIMER2 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER2_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER2_OFFSET), [ALT4].sel = 0, /* Index:21 Alt:5 No input selection */ @@ -1284,7 +1327,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:22 Alt:4 GPIO EMC 22 QTIMER2 TIMER3 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER3_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER3_OFFSET), [ALT4].sel = 0, /* Index:22 Alt:5 No input selection */ @@ -1325,7 +1369,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:23 Alt:1 GPIO EMC 23 FLEXPWM1 PWMA00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET), [ALT1].sel = 0, /* Index:23 Alt:2 GPIO EMC 23 LPUART5 TX */ @@ -1340,7 +1385,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:23 Alt:4 GPIO EMC 23 GPT1 CAPTURE2 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_GPT1_IPP_IND_CAPIN2_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_GPT1_IPP_IND_CAPIN2_OFFSET), [ALT4].sel = 0, /* Index:23 Alt:5 No input selection */ @@ -1360,7 +1407,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:23 Alt:8 GPIO EMC 23 FLEXSPI2 A DQS */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_DQS_FA_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_DQS_FA_OFFSET), [ALT8].sel = 1, /* Index:23 Alt:9 No input selection */ @@ -1381,7 +1430,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:24 Alt:1 GPIO EMC 24 FLEXPWM1 PWMB00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET), [ALT1].sel = 0, /* Index:24 Alt:2 GPIO EMC 24 LPUART5 RX */ @@ -1396,7 +1446,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:24 Alt:4 GPIO EMC 24 GPT1 CAPTURE1 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_GPT1_IPP_IND_CAPIN1_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_GPT1_IPP_IND_CAPIN1_OFFSET), [ALT4].sel = 0, /* Index:24 Alt:5 No input selection */ @@ -1437,7 +1489,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:25 Alt:1 GPIO EMC 25 FLEXPWM1 PWMA01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET), [ALT1].sel = 0, /* Index:25 Alt:2 GPIO EMC 25 LPUART6 TX */ @@ -1452,7 +1505,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:25 Alt:4 GPIO EMC 25 ENET REF CLK */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET), [ALT4].sel = 0, /* Index:25 Alt:5 No input selection */ @@ -1472,7 +1526,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:25 Alt:8 GPIO EMC 25 FLEXSPI2 A SCLK */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FA_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FA_OFFSET), [ALT8].sel = 1, /* Index:25 Alt:9 No input selection */ @@ -1493,7 +1549,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:26 Alt:1 GPIO EMC 26 FLEXPWM1 PWMB01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET), [ALT1].sel = 0, /* Index:26 Alt:2 GPIO EMC 26 LPUART6 RX */ @@ -1528,7 +1585,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:26 Alt:8 GPIO EMC 26 FLEXSPI2 A DATA00 */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT0_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT0_OFFSET), [ALT8].sel = 1, /* Index:26 Alt:9 No input selection */ @@ -1549,7 +1608,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:27 Alt:1 GPIO EMC 27 FLEXPWM1 PWMA02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET), [ALT1].sel = 0, /* Index:27 Alt:2 No input selection */ @@ -1584,7 +1644,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:27 Alt:8 GPIO EMC 27 FLEXSPI2 A DATA01 */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT1_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT1_OFFSET), [ALT8].sel = 1, /* Index:27 Alt:9 No input selection */ @@ -1605,7 +1667,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:28 Alt:1 GPIO EMC 28 FLEXPWM1 PWMB02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET), [ALT1].sel = 0, /* Index:28 Alt:2 No input selection */ @@ -1640,7 +1703,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:28 Alt:8 GPIO EMC 28 FLEXSPI2 A DATA02 */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT2_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT2_OFFSET), [ALT8].sel = 1, /* Index:28 Alt:9 No input selection */ @@ -1696,7 +1761,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:29 Alt:8 GPIO EMC 29 FLEXSPI2 A DATA03 */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT3_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT3_OFFSET), [ALT8].sel = 1, /* Index:29 Alt:9 No input selection */ @@ -1727,7 +1794,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:30 Alt:3 GPIO EMC 30 LPSPI1 PCS0 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_PCS0_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_PCS0_OFFSET), [ALT3].sel = 1, /* Index:30 Alt:4 No input selection */ @@ -1839,7 +1907,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:32 Alt:3 GPIO EMC 32 CCM PMIC RDY */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), [ALT3].sel = 4, /* Index:32 Alt:4 No input selection */ @@ -1895,7 +1964,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:33 Alt:3 GPIO EMC 33 SAI3 RX DATA */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_IPP_IND_SAI_RXDATA_0_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_SAI3_IPP_IND_SAI_RXDATA_0_OFFSET), [ALT3].sel = 0, /* Index:33 Alt:4 No input selection */ @@ -1920,12 +1991,15 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:33 Alt:8 GPIO EMC 33 ENET2 TX CLK */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPP_IND_MAC0_TXCLK_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_ENET2_IPP_IND_MAC0_TXCLK_OFFSET), [ALT8].sel = 0, /* Index:33 Alt:9 GPIO EMC 33 ENET2 REF CLK2 */ - [ALT9].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPG_CLK_RMII_OFFSET), + [ALT9].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPG_CLK_RMII_OFFSET), [ALT9].sel = 0, }, }, @@ -1951,7 +2025,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:34 Alt:3 GPIO EMC 34 SAI3 RX SYNC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_IPP_IND_SAI_RXSYNC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_SAI3_IPP_IND_SAI_RXSYNC_OFFSET), [ALT3].sel = 0, /* Index:34 Alt:4 No input selection */ @@ -1976,7 +2052,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:34 Alt:8 GPIO EMC 34 ENET2 RX ER */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXERR_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXERR_OFFSET), [ALT8].sel = 0, /* Index:34 Alt:9 No input selection */ @@ -2007,7 +2085,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:35 Alt:3 GPIO EMC 35 SAI3 RX BCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_IPP_IND_SAI_RXBCLK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_SAI3_IPP_IND_SAI_RXBCLK_OFFSET), [ALT3].sel = 0, /* Index:35 Alt:4 No input selection */ @@ -2022,7 +2102,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:35 Alt:6 GPIO EMC 35 USDHC1 CD B */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET), [ALT6].sel = 0, /* Index:35 Alt:7 No input selection */ @@ -2032,7 +2113,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:35 Alt:8 GPIO EMC 35 ENET2 RDATA00 */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_0_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_0_OFFSET), [ALT8].sel = 0, /* Index:35 Alt:9 No input selection */ @@ -2088,7 +2171,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:36 Alt:8 GPIO EMC 36 ENET2 RDATA01 */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_1_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_1_OFFSET), [ALT8].sel = 0, /* Index:36 Alt:9 No input selection */ @@ -2119,7 +2204,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:37 Alt:3 GPIO EMC 37 SAI3 MCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_IPG_CLK_SAI_MCLK_2_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_SAI3_IPG_CLK_SAI_MCLK_2_OFFSET), [ALT3].sel = 0, /* Index:37 Alt:4 No input selection */ @@ -2144,12 +2231,16 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:37 Alt:8 GPIO EMC 37 ENET2 RX EN */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXEN_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXEN_OFFSET), [ALT8].sel = 0, /* Index:37 Alt:9 GPIO EMC 37 FLEXCAN3 RX */ - [ALT9].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CANFD_IPP_IND_CANRX_OFFSET), + [ALT9].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_CANFD_IPP_IND_CANRX_OFFSET), [ALT9].sel = 0, }, }, @@ -2165,7 +2256,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:38 Alt:1 GPIO EMC 38 FLEXPWM1 PWMA03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), [ALT1].sel = 2, /* Index:38 Alt:2 GPIO EMC 38 LPUART8 TX */ @@ -2175,7 +2267,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:38 Alt:3 GPIO EMC 38 SAI3 TX BCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_IPP_IND_SAI_TXBCLK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_SAI3_IPP_IND_SAI_TXBCLK_OFFSET), [ALT3].sel = 0, /* Index:38 Alt:4 No input selection */ @@ -2221,7 +2315,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:39 Alt:1 GPIO EMC 39 FLEXPWM1 PWMB03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), [ALT1].sel = 2, /* Index:39 Alt:2 GPIO EMC 39 LPUART8 RX */ @@ -2231,7 +2326,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:39 Alt:3 GPIO EMC 39 SAI3 TX SYNC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_IPP_IND_SAI_TXSYNC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_SAI3_IPP_IND_SAI_TXSYNC_OFFSET), [ALT3].sel = 0, /* Index:39 Alt:4 No input selection */ @@ -2246,7 +2343,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:39 Alt:6 GPIO EMC 39 USDHC2 CD B */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CD_B_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CD_B_OFFSET), [ALT6].sel = 1, /* Index:39 Alt:7 No input selection */ @@ -2256,12 +2354,16 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:39 Alt:8 GPIO EMC 39 ENET2 MDIO */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPP_IND_MAC0_MDIO_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_ENET2_IPP_IND_MAC0_MDIO_OFFSET), [ALT8].sel = 0, /* Index:39 Alt:9 GPIO EMC 39 SEMC DQS4 */ - [ALT9].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SEMC_I_IPP_IND_DQS4_OFFSET), + [ALT9].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_SEMC_I_IPP_IND_DQS4_OFFSET), [ALT9].sel = 1, }, }, @@ -2277,7 +2379,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:40 Alt:1 GPIO EMC 40 GPT2 CAPTURE2 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_GPT2_IPP_IND_CAPIN2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_GPT2_IPP_IND_CAPIN2_OFFSET), [ALT1].sel = 0, /* Index:40 Alt:2 No input selection */ @@ -2287,7 +2391,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:40 Alt:3 GPIO EMC 40 USB OTG2 OC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG2_OC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG2_OC_OFFSET), [ALT3].sel = 1, /* Index:40 Alt:4 No input selection */ @@ -2333,7 +2438,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:41 Alt:1 GPIO EMC 41 GPT2 CAPTURE1 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_GPT2_IPP_IND_CAPIN1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_GPT2_IPP_IND_CAPIN1_OFFSET), [ALT1].sel = 0, /* Index:41 Alt:2 No input selection */ @@ -2384,7 +2491,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:42 Alt:0 GPIO AD B0 00 FLEXPWM2 PWMA03 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), [ALT0].sel = 2, /* Index:42 Alt:1 GPIO AD B0 00 XBAR1 INOUT14 */ @@ -2399,7 +2507,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:42 Alt:3 GPIO AD B0 00 USB OTG2 ID */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET), [ALT3].sel = 0, /* Index:42 Alt:4 No input selection */ @@ -2440,7 +2549,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:43 Alt:0 GPIO AD B0 01 FLEXPWM2 PWMB03 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET), [ALT0].sel = 2, /* Index:43 Alt:1 GPIO AD B0 01 XBAR1 INOUT15 */ @@ -2455,7 +2565,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:43 Alt:3 GPIO AD B0 01 USB OTG1 ID */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET), [ALT3].sel = 0, /* Index:43 Alt:4 No input selection */ @@ -2552,7 +2663,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:45 Alt:0 GPIO AD B0 03 FLEXCAN2 RX */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), [ALT0].sel = 1, /* Index:45 Alt:1 GPIO AD B0 03 XBAR1 INOUT17 */ @@ -2567,7 +2679,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:45 Alt:3 GPIO AD B0 03 USB OTG1 OC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG1_OC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG1_OC_OFFSET), [ALT3].sel = 0, /* Index:45 Alt:4 No input selection */ @@ -2587,7 +2700,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:45 Alt:7 GPIO AD B0 03 LPSPI3 PCS0 */ - [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI3_PCS0_OFFSET), + [ALT7].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI3_PCS0_OFFSET), [ALT7].sel = 0, /* Index:45 Alt:8 No input selection */ @@ -2623,7 +2737,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:46 Alt:3 GPIO AD B0 04 SAI2 TX SYNC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_SYNC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_SYNC_OFFSET), [ALT3].sel = 1, /* Index:46 Alt:4 GPIO AD B0 04 CSI DATA09 */ @@ -2679,7 +2794,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:47 Alt:3 GPIO AD B0 05 SAI2 TX BCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_BCLK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_BCLK_OFFSET), [ALT3].sel = 1, /* Index:47 Alt:4 GPIO AD B0 05 CSI DATA08 */ @@ -2735,7 +2851,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:48 Alt:3 GPIO AD B0 06 SAI2 RX BCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_BCLK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_BCLK_OFFSET), [ALT3].sel = 1, /* Index:48 Alt:4 GPIO AD B0 06 CSI DATA07 */ @@ -2791,7 +2908,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:49 Alt:3 GPIO AD B0 07 SAI2 RX SYNC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_SYNC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_SYNC_OFFSET), [ALT3].sel = 1, /* Index:49 Alt:4 GPIO AD B0 07 CSI DATA06 */ @@ -2847,7 +2965,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:50 Alt:3 GPIO AD B0 08 SAI2 RX DATA */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_DATA0_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_DATA0_OFFSET), [ALT3].sel = 1, /* Index:50 Alt:4 GPIO AD B0 08 CSI DATA05 */ @@ -2893,7 +3012,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:51 Alt:1 GPIO AD B0 09 FLEXPWM2 PWMA03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), [ALT1].sel = 3, /* Index:51 Alt:2 No input selection */ @@ -2923,7 +3043,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:51 Alt:7 GPIO AD B0 09 GPT2 CLK */ - [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_GPT2_IPP_IND_CLKIN_OFFSET), + [ALT7].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_GPT2_IPP_IND_CLKIN_OFFSET), [ALT7].sel = 0, /* Index:51 Alt:8 No input selection */ @@ -2933,7 +3054,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:51 Alt:9 GPIO AD B0 09 SEMC DQS4 */ - [ALT9].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SEMC_I_IPP_IND_DQS4_OFFSET), + [ALT9].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_SEMC_I_IPP_IND_DQS4_OFFSET), [ALT9].sel = 2, }, }, @@ -2949,7 +3072,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:52 Alt:1 GPIO AD B0 10 FLEXPWM1 PWMA03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), [ALT1].sel = 3, /* Index:52 Alt:2 No input selection */ @@ -3005,7 +3129,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:53 Alt:1 GPIO AD B0 11 FLEXPWM1 PWMB03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), [ALT1].sel = 3, /* Index:53 Alt:2 No input selection */ @@ -3020,7 +3145,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:53 Alt:4 GPIO AD B0 11 CSI DATA02 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA02_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CSI_DATA02_OFFSET), [ALT4].sel = 1, /* Index:53 Alt:5 No input selection */ @@ -3030,17 +3156,21 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:53 Alt:6 GPIO AD B0 11 XBAR1 IN23 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN23_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN23_OFFSET), [ALT6].sel = 1, /* Index:53 Alt:7 GPIO AD B0 11 ENET 1588 EVENT0 IN */ - [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_TIMER_OFFSET), + [ALT7].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_TIMER_OFFSET), [ALT7].sel = 1, /* Index:53 Alt:8 GPIO AD B0 11 FLEXCAN3 RX */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CANFD_IPP_IND_CANRX_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_CANFD_IPP_IND_CANRX_OFFSET), [ALT8].sel = 2, /* Index:53 Alt:9 No input selection */ @@ -3056,12 +3186,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:54 Alt:0 GPIO AD B0 12 LPI2C4 SCL */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C4_SCL_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C4_SCL_OFFSET), [ALT0].sel = 1, /* Index:54 Alt:1 GPIO AD B0 12 CCM PMIC READY */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), [ALT1].sel = 1, /* Index:54 Alt:2 No input selection */ @@ -3091,7 +3223,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:54 Alt:7 GPIO AD B0 12 NMI GLUE NMI */ - [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_NMI_GLUE_NMI_OFFSET), + [ALT7].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_NMI_GLUE_NMI_OFFSET), [ALT7].sel = 0, /* Index:54 Alt:8 No input selection */ @@ -3117,7 +3250,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:55 Alt:1 GPIO AD B0 13 GPT1 CLK */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_GPT1_IPP_IND_CLKIN_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_GPT1_IPP_IND_CLKIN_OFFSET), [ALT1].sel = 0, /* Index:55 Alt:2 No input selection */ @@ -3168,12 +3302,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:56 Alt:0 GPIO AD B0 14 USB OTG2 OC */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG2_OC_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG2_OC_OFFSET), [ALT0].sel = 0, /* Index:56 Alt:1 GPIO AD B0 14 XBAR1 IN24 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN24_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN24_OFFSET), [ALT1].sel = 1, /* Index:56 Alt:2 No input selection */ @@ -3239,7 +3375,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:57 Alt:3 GPIO AD B0 15 ENET 1588 EVENT0 IN */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_TIMER_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_TIMER_OFFSET), [ALT3].sel = 0, /* Index:57 Alt:4 GPIO AD B0 15 CSI HSYNC */ @@ -3254,7 +3391,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:57 Alt:6 GPIO AD B0 15 FLEXCAN2 RX */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), [ALT6].sel = 2, /* Index:57 Alt:7 No input selection */ @@ -3264,7 +3402,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:57 Alt:8 GPIO AD B0 15 FLEXCAN3 RX */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CANFD_IPP_IND_CANRX_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_CANFD_IPP_IND_CANRX_OFFSET), [ALT8].sel = 1, /* Index:57 Alt:9 No input selection */ @@ -3280,12 +3420,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:58 Alt:0 GPIO AD B1 00 USB OTG2 ID */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET), [ALT0].sel = 1, /* Index:58 Alt:1 GPIO AD B1 00 QTIMER3 TIMER0 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER0_OFFSET), [ALT1].sel = 1, /* Index:58 Alt:2 No input selection */ @@ -3341,7 +3483,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:59 Alt:1 GPIO AD B1 01 QTIMER3 TIMER1 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER1_OFFSET), [ALT1].sel = 0, /* Index:59 Alt:2 No input selection */ @@ -3356,7 +3499,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:59 Alt:4 GPIO AD B1 01 CCM PMIC READY */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), [ALT4].sel = 2, /* Index:59 Alt:5 No input selection */ @@ -3376,7 +3520,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:59 Alt:8 GPIO AD B1 01 ENET2 1588 EVENT0 IN */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPP_IND_MAC0_TIMER_0_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_ENET2_IPP_IND_MAC0_TIMER_0_OFFSET), [ALT8].sel = 0, /* Index:59 Alt:9 No input selection */ @@ -3392,17 +3538,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:60 Alt:0 GPIO AD B1 02 USB OTG1 ID */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET), [ALT0].sel = 1, /* Index:60 Alt:1 GPIO AD B1 02 QTIMER3 TIMER2 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER2_OFFSET), [ALT1].sel = 1, /* Index:60 Alt:2 GPIO AD B1 02 LPUART2 TX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART2_TX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART2_TX_OFFSET), [ALT2].sel = 1, /* Index:60 Alt:3 No input selection */ @@ -3422,7 +3571,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:60 Alt:6 GPIO AD B1 02 USDHC1 CD B */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET), [ALT6].sel = 1, /* Index:60 Alt:7 No input selection */ @@ -3432,7 +3582,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:60 Alt:8 GPIO AD B1 02 GPT2 CLK */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_GPT2_IPP_IND_CLKIN_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_GPT2_IPP_IND_CLKIN_OFFSET), [ALT8].sel = 1, /* Index:60 Alt:9 No input selection */ @@ -3448,12 +3599,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:61 Alt:0 GPIO AD B1 03 USB OTG1 OC */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG1_OC_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG1_OC_OFFSET), [ALT0].sel = 1, /* Index:61 Alt:1 GPIO AD B1 03 QTIMER3 TIMER3 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER3_OFFSET), [ALT1].sel = 1, /* Index:61 Alt:2 GPIO AD B1 03 LPUART2 RX */ @@ -3478,7 +3631,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:61 Alt:6 GPIO AD B1 03 USDHC2 CD B */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CD_B_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CD_B_OFFSET), [ALT6].sel = 0, /* Index:61 Alt:7 No input selection */ @@ -3488,7 +3642,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:61 Alt:8 GPIO AD B1 03 GPT2 CAPTURE1 */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_GPT2_IPP_IND_CAPIN1_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_GPT2_IPP_IND_CAPIN1_OFFSET), [ALT8].sel = 1, /* Index:61 Alt:9 No input selection */ @@ -3504,7 +3660,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:62 Alt:0 GPIO AD B1 04 FLEXSPIB DATA03 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET), [ALT0].sel = 1, /* Index:62 Alt:1 No input selection */ @@ -3514,7 +3671,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:62 Alt:2 GPIO AD B1 04 LPUART3 CTS B */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_CTS_B_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_CTS_B_OFFSET), [ALT2].sel = 1, /* Index:62 Alt:3 No input selection */ @@ -3534,7 +3692,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:62 Alt:6 GPIO AD B1 04 USDHC2 DATA0 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA0_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA0_OFFSET), [ALT6].sel = 1, /* Index:62 Alt:7 No input selection */ @@ -3544,7 +3703,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:62 Alt:8 GPIO AD B1 04 GPT2 CAPTURE2 */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_GPT2_IPP_IND_CAPIN2_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_GPT2_IPP_IND_CAPIN2_OFFSET), [ALT8].sel = 1, /* Index:62 Alt:9 No input selection */ @@ -3560,7 +3721,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:63 Alt:0 GPIO AD B1 05 FLEXSPIB DATA02 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET), [ALT0].sel = 1, /* Index:63 Alt:1 GPIO AD B1 05 ENET MDIO */ @@ -3590,7 +3752,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:63 Alt:6 GPIO AD B1 05 USDHC2 DATA1 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA1_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA1_OFFSET), [ALT6].sel = 1, /* Index:63 Alt:7 No input selection */ @@ -3616,7 +3779,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:64 Alt:0 GPIO AD B1 06 FLEXSPIB DATA01 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET), [ALT0].sel = 1, /* Index:64 Alt:1 GPIO AD B1 06 LPI2C3 SDA */ @@ -3626,7 +3790,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:64 Alt:2 GPIO AD B1 06 LPUART3 TX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_TX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_TX_OFFSET), [ALT2].sel = 0, /* Index:64 Alt:3 No input selection */ @@ -3646,7 +3811,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:64 Alt:6 GPIO AD B1 06 USDHC2 DATA2 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA2_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA2_OFFSET), [ALT6].sel = 1, /* Index:64 Alt:7 No input selection */ @@ -3672,7 +3838,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:65 Alt:0 GPIO AD B1 07 FLEXSPIB DATA00 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET), [ALT0].sel = 1, /* Index:65 Alt:1 GPIO AD B1 07 LPI2C3 SCL */ @@ -3702,7 +3869,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:65 Alt:6 GPIO AD B1 07 USDHC2 DATA3 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA3_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA3_OFFSET), [ALT6].sel = 1, /* Index:65 Alt:7 No input selection */ @@ -3733,7 +3901,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:66 Alt:1 GPIO AD B1 08 FLEXPWM4 PWMA00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET), [ALT1].sel = 1, /* Index:66 Alt:2 No input selection */ @@ -3743,7 +3912,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:66 Alt:3 GPIO AD B1 08 CCM PMIC READY */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), [ALT3].sel = 3, /* Index:66 Alt:4 GPIO AD B1 08 CSI DATA09 */ @@ -3784,17 +3954,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:67 Alt:0 GPIO AD B1 09 FLEXSPIA DQS */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DQS_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DQS_OFFSET), [ALT0].sel = 1, /* Index:67 Alt:1 GPIO AD B1 09 FLEXPWM4 PWMA01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET), [ALT1].sel = 1, /* Index:67 Alt:2 GPIO AD B1 09 FLEXCAN1 RX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), [ALT2].sel = 2, /* Index:67 Alt:3 GPIO AD B1 09 SAI1 MCLK */ @@ -3840,7 +4013,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:68 Alt:0 GPIO AD B1 10 FLEXSPIA DATA03 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET), [ALT0].sel = 1, /* Index:68 Alt:1 No input selection */ @@ -3855,7 +4029,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:68 Alt:3 GPIO AD B1 10 SAI1 RX SYNC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_SYNC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_SYNC_OFFSET), [ALT3].sel = 1, /* Index:68 Alt:4 GPIO AD B1 10 CSI DATA07 */ @@ -3896,7 +4071,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:69 Alt:0 GPIO AD B1 11 FLEXSPIA DATA02 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET), [ALT0].sel = 1, /* Index:69 Alt:1 No input selection */ @@ -3911,7 +4087,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:69 Alt:3 GPIO AD B1 11 SAI1 RX BCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_BCLK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_BCLK_OFFSET), [ALT3].sel = 1, /* Index:69 Alt:4 GPIO AD B1 11 CSI DATA06 */ @@ -3952,7 +4129,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:70 Alt:0 GPIO AD B1 12 FLEXSPIA DATA01 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET), [ALT0].sel = 1, /* Index:70 Alt:1 No input selection */ @@ -3962,12 +4140,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:70 Alt:2 GPIO AD B1 12 LPSPI3 PCS0 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI3_PCS0_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI3_PCS0_OFFSET), [ALT2].sel = 1, /* Index:70 Alt:3 GPIO AD B1 12 SAI1 RX DATA00 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA0_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA0_OFFSET), [ALT3].sel = 1, /* Index:70 Alt:4 GPIO AD B1 12 CSI DATA05 */ @@ -3982,7 +4162,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:70 Alt:6 GPIO AD B1 12 USDHC2 DATA4 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA4_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA4_OFFSET), [ALT6].sel = 1, /* Index:70 Alt:7 No input selection */ @@ -4008,7 +4189,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:71 Alt:0 GPIO AD B1 13 FLEXSPIA DATA00 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET), [ALT0].sel = 1, /* Index:71 Alt:1 No input selection */ @@ -4038,7 +4220,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:71 Alt:6 GPIO AD B1 13 USDHC2 DATA5 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA5_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA5_OFFSET), [ALT6].sel = 1, /* Index:71 Alt:7 No input selection */ @@ -4064,7 +4247,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:72 Alt:0 GPIO AD B1 14 FLEXSPIA SCLK */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_SCK_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_SCK_OFFSET), [ALT0].sel = 1, /* Index:72 Alt:1 No input selection */ @@ -4079,7 +4263,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:72 Alt:3 GPIO AD B1 14 SAI1 TX BCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_BCLK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_BCLK_OFFSET), [ALT3].sel = 1, /* Index:72 Alt:4 GPIO AD B1 14 CSI DATA03 */ @@ -4094,7 +4279,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:72 Alt:6 GPIO AD B1 14 USDHC2 DATA6 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA6_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA6_OFFSET), [ALT6].sel = 1, /* Index:72 Alt:7 No input selection */ @@ -4135,7 +4321,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:73 Alt:3 GPIO AD B1 15 SAI1 TX SYNC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_SYNC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_SYNC_OFFSET), [ALT3].sel = 1, /* Index:73 Alt:4 GPIO AD B1 15 CSI DATA02 */ @@ -4150,7 +4337,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:73 Alt:6 GPIO AD B1 15 USDHC2 DATA7 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA7_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA7_OFFSET), [ALT6].sel = 1, /* Index:73 Alt:7 No input selection */ @@ -4191,7 +4379,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:74 Alt:3 GPIO B0 00 LPSPI4 PCS0 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_PCS0_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_PCS0_OFFSET), [ALT3].sel = 0, /* Index:74 Alt:4 No input selection */ @@ -4272,7 +4461,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:75 Alt:8 GPIO B0 01 ENET2 MDIO */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPP_IND_MAC0_MDIO_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_ENET2_IPP_IND_MAC0_MDIO_OFFSET), [ALT8].sel = 1, /* Index:75 Alt:9 No input selection */ @@ -4349,12 +4540,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:77 Alt:1 GPIO B0 03 QTIMER2 TIMER0 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER0_OFFSET), [ALT1].sel = 1, /* Index:77 Alt:2 GPIO B0 03 FLEXCAN1 RX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), [ALT2].sel = 3, /* Index:77 Alt:3 GPIO B0 03 LPSPI4 SCK */ @@ -4384,7 +4577,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:77 Alt:8 GPIO B0 03 ENET2 1588 EVENT0 IN */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPP_IND_MAC0_TIMER_0_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_ENET2_IPP_IND_MAC0_TIMER_0_OFFSET), [ALT8].sel = 1, /* Index:77 Alt:9 No input selection */ @@ -4405,7 +4600,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:78 Alt:1 GPIO B0 04 QTIMER2 TIMER1 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER1_OFFSET), [ALT1].sel = 1, /* Index:78 Alt:2 GPIO B0 04 LPI2C2 SCL */ @@ -4461,12 +4657,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:79 Alt:1 GPIO B0 05 QTIMER2 TIMER2 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER2_OFFSET), [ALT1].sel = 1, /* Index:79 Alt:2 GPIO B0 05 LPI2C2 SDA */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C2_SDA_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C2_SDA_OFFSET), [ALT2].sel = 1, /* Index:79 Alt:3 No input selection */ @@ -4517,12 +4715,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:80 Alt:1 GPIO B0 06 QTIMER3 TIMER0 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER0_OFFSET), [ALT1].sel = 2, /* Index:80 Alt:2 GPIO B0 06 FLEXPWM2 PWMA00 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET), [ALT2].sel = 1, /* Index:80 Alt:3 No input selection */ @@ -4573,12 +4773,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:81 Alt:1 GPIO B0 07 QTIMER3 TIMER1 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER1_OFFSET), [ALT1].sel = 2, /* Index:81 Alt:2 GPIO B0 07 FLEXPWM2 PWMB00 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET), [ALT2].sel = 1, /* Index:81 Alt:3 No input selection */ @@ -4629,12 +4831,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:82 Alt:1 GPIO B0 08 QTIMER3 TIMER2 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER2_OFFSET), [ALT1].sel = 2, /* Index:82 Alt:2 GPIO B0 08 FLEXPWM2 PWMA01 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET), [ALT2].sel = 1, /* Index:82 Alt:3 GPIO B0 08 LPUART3 TX */ @@ -4690,7 +4894,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:83 Alt:2 GPIO B0 09 FLEXPWM2 PWMB01 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET), [ALT2].sel = 1, /* Index:83 Alt:3 GPIO B0 09 LPUART3 RX */ @@ -4746,12 +4951,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:84 Alt:2 GPIO B0 10 FLEXPWM2 PWMA02 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET), [ALT2].sel = 1, /* Index:84 Alt:3 GPIO B0 10 SAI1 TX DATA03 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA1_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA1_OFFSET), [ALT3].sel = 1, /* Index:84 Alt:4 No input selection */ @@ -4802,12 +5009,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:85 Alt:2 GPIO B0 11 FLEXPWM2 PWMB02 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET), [ALT2].sel = 1, /* Index:85 Alt:3 GPIO B0 11 SAI1 TX DATA02 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA2_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA2_OFFSET), [ALT3].sel = 1, /* Index:85 Alt:4 No input selection */ @@ -4863,7 +5072,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:86 Alt:3 GPIO B0 12 SAI1 TX DATA01 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA3_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA3_OFFSET), [ALT3].sel = 1, /* Index:86 Alt:4 No input selection */ @@ -4975,7 +5185,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:88 Alt:3 GPIO B0 14 SAI1 RX SYNC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_SYNC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_SYNC_OFFSET), [ALT3].sel = 2, /* Index:88 Alt:4 No input selection */ @@ -5031,7 +5242,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:89 Alt:3 GPIO B0 15 SAI1 RX BCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_BCLK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_BCLK_OFFSET), [ALT3].sel = 2, /* Index:89 Alt:4 No input selection */ @@ -5056,12 +5268,15 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:89 Alt:8 GPIO B0 15 ENET2 TX CLK */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPP_IND_MAC0_TXCLK_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_ENET2_IPP_IND_MAC0_TXCLK_OFFSET), [ALT8].sel = 2, /* Index:89 Alt:9 GPIO B0 15 ENET2 REF CLK2 */ - [ALT9].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPG_CLK_RMII_OFFSET), + [ALT9].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPG_CLK_RMII_OFFSET), [ALT9].sel = 2, }, }, @@ -5087,7 +5302,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:90 Alt:3 GPIO B1 00 SAI1 RX DATA00 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA0_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA0_OFFSET), [ALT3].sel = 2, /* Index:90 Alt:4 No input selection */ @@ -5102,7 +5318,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:90 Alt:6 GPIO B1 00 FLEXPWM1 PWMA03 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), [ALT6].sel = 4, /* Index:90 Alt:7 No input selection */ @@ -5112,7 +5329,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:90 Alt:8 GPIO B1 00 ENET2 RX ER */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXERR_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXERR_OFFSET), [ALT8].sel = 2, /* Index:90 Alt:9 No input selection */ @@ -5158,7 +5377,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:91 Alt:6 GPIO B1 01 FLEXPWM1 PWMB03 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), [ALT6].sel = 4, /* Index:91 Alt:7 No input selection */ @@ -5168,7 +5388,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:91 Alt:8 GPIO B1 01 ENET2 RDATA00 */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_0_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_0_OFFSET), [ALT8].sel = 2, /* Index:91 Alt:9 No input selection */ @@ -5199,7 +5421,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:92 Alt:3 GPIO B1 02 SAI1 TX BCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_BCLK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_BCLK_OFFSET), [ALT3].sel = 2, /* Index:92 Alt:4 No input selection */ @@ -5214,7 +5437,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:92 Alt:6 GPIO B1 02 FLEXPWM2 PWMA03 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), [ALT6].sel = 4, /* Index:92 Alt:7 No input selection */ @@ -5224,7 +5448,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:92 Alt:8 GPIO B1 02 ENET2 RDATA01 */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_1_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_1_OFFSET), [ALT8].sel = 2, /* Index:92 Alt:9 No input selection */ @@ -5245,7 +5471,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:93 Alt:1 GPIO B1 03 XBAR1 INOUT17 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN17_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN17_OFFSET), [ALT1].sel = 3, /* Index:93 Alt:2 No input selection */ @@ -5255,7 +5482,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:93 Alt:3 GPIO B1 03 SAI1 TX SYNC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_SYNC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_SYNC_OFFSET), [ALT3].sel = 2, /* Index:93 Alt:4 No input selection */ @@ -5270,7 +5498,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:93 Alt:6 GPIO B1 03 FLEXPWM2 PWMB03 */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET), [ALT6].sel = 3, /* Index:93 Alt:7 No input selection */ @@ -5280,7 +5509,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:93 Alt:8 GPIO B1 03 ENET2 RX EN */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXEN_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXEN_OFFSET), [ALT8].sel = 2, /* Index:93 Alt:9 No input selection */ @@ -5301,7 +5532,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:94 Alt:1 GPIO B1 04 LPSPI4 PCS0 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_PCS0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_PCS0_OFFSET), [ALT1].sel = 1, /* Index:94 Alt:2 No input selection */ @@ -5311,7 +5543,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:94 Alt:3 GPIO B1 04 ENET RX DATA00 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_RXDATA_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_RXDATA_OFFSET), [ALT3].sel = 1, /* Index:94 Alt:4 No input selection */ @@ -5336,7 +5569,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:94 Alt:8 GPIO B1 04 GPT1 CLK */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_GPT1_IPP_IND_CLKIN_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_GPT1_IPP_IND_CLKIN_OFFSET), [ALT8].sel = 1, /* Index:94 Alt:9 No input selection */ @@ -5367,7 +5601,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:95 Alt:3 GPIO B1 05 ENET RX DATA01 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET1_RXDATA_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET1_RXDATA_OFFSET), [ALT3].sel = 1, /* Index:95 Alt:4 No input selection */ @@ -5392,7 +5627,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:95 Alt:8 GPIO B1 05 GPT1 CAPTURE1 */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_GPT1_IPP_IND_CAPIN1_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_GPT1_IPP_IND_CAPIN1_OFFSET), [ALT8].sel = 1, /* Index:95 Alt:9 No input selection */ @@ -5448,7 +5685,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:96 Alt:8 GPIO B1 06 GPT1 CAPTURE2 */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_GPT1_IPP_IND_CAPIN2_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_GPT1_IPP_IND_CAPIN2_OFFSET), [ALT8].sel = 1, /* Index:96 Alt:9 No input selection */ @@ -5581,7 +5820,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:99 Alt:1 GPIO B1 09 QTIMER2 TIMER3 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER3_OFFSET), [ALT1].sel = 1, /* Index:99 Alt:2 No input selection */ @@ -5606,7 +5846,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:99 Alt:6 GPIO B1 09 FLEXCAN2 RX */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), [ALT6].sel = 3, /* Index:99 Alt:7 No input selection */ @@ -5637,7 +5878,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:100 Alt:1 GPIO B1 10 QTIMER3 TIMER3 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER3_TIMER3_OFFSET), [ALT1].sel = 2, /* Index:100 Alt:2 No input selection */ @@ -5662,7 +5904,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:100 Alt:6 GPIO B1 10 ENET REF CLK */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET), [ALT6].sel = 1, /* Index:100 Alt:7 No input selection */ @@ -5759,7 +6002,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:102 Alt:3 GPIO B1 12 ENET 1588 EVENT0 IN */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_TIMER_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET0_TIMER_OFFSET), [ALT3].sel = 2, /* Index:102 Alt:4 No input selection */ @@ -5774,7 +6018,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:102 Alt:6 GPIO B1 12 USDHC1 CD B */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET), [ALT6].sel = 2, /* Index:102 Alt:7 No input selection */ @@ -5840,7 +6085,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:103 Alt:8 GPIO B1 13 SEMC DQS4 */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SEMC_I_IPP_IND_DQS4_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_SEMC_I_IPP_IND_DQS4_OFFSET), [ALT8].sel = 3, /* Index:103 Alt:9 No input selection */ @@ -5861,7 +6108,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:104 Alt:1 GPIO B1 14 FLEXPWM4 PWMA02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET), [ALT1].sel = 1, /* Index:104 Alt:2 GPIO B1 14 CSI HSYNC */ @@ -5917,7 +6165,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:105 Alt:1 GPIO B1 15 FLEXPWM4 PWMA03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET), [ALT1].sel = 1, /* Index:105 Alt:2 No input selection */ @@ -5973,7 +6222,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:106 Alt:1 GPIO SD B0 00 FLEXPWM1 PWMA00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET), [ALT1].sel = 1, /* Index:106 Alt:2 GPIO SD B0 00 LPI2C3 SCL */ @@ -6013,7 +6263,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:106 Alt:9 GPIO SD B0 00 SEMC DQS4 */ - [ALT9].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SEMC_I_IPP_IND_DQS4_OFFSET), + [ALT9].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_SEMC_I_IPP_IND_DQS4_OFFSET), [ALT9].sel = 0, }, }, @@ -6029,7 +6281,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:107 Alt:1 GPIO SD B0 01 FLEXPWM1 PWMB00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET), [ALT1].sel = 1, /* Index:107 Alt:2 GPIO SD B0 01 LPI2C3 SDA */ @@ -6044,7 +6297,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:107 Alt:4 GPIO SD B0 01 LPSPI1 PCS0 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_PCS0_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_PCS0_OFFSET), [ALT4].sel = 0, /* Index:107 Alt:5 No input selection */ @@ -6064,12 +6318,15 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:107 Alt:8 GPIO SD B0 01 ENET2 TX CLK */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPP_IND_MAC0_TXCLK_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_ENET2_IPP_IND_MAC0_TXCLK_OFFSET), [ALT8].sel = 1, /* Index:107 Alt:9 GPIO SD B0 01 ENET2 REF CLK2 */ - [ALT9].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPG_CLK_RMII_OFFSET), + [ALT9].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPG_CLK_RMII_OFFSET), [ALT9].sel = 1, }, }, @@ -6085,7 +6342,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:108 Alt:1 GPIO SD B0 02 FLEXPWM1 PWMA01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET), [ALT1].sel = 1, /* Index:108 Alt:2 No input selection */ @@ -6120,7 +6378,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:108 Alt:8 GPIO SD B0 02 ENET2 RX ER */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXERR_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXERR_OFFSET), [ALT8].sel = 1, /* Index:108 Alt:9 No input selection */ @@ -6141,7 +6401,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:109 Alt:1 GPIO SD B0 03 FLEXPWM1 PWMB01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET), [ALT1].sel = 1, /* Index:109 Alt:2 No input selection */ @@ -6176,7 +6438,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:109 Alt:8 GPIO SD B0 03 ENET2 RDATA00 */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_0_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_0_OFFSET), [ALT8].sel = 1, /* Index:109 Alt:9 No input selection */ @@ -6197,7 +6461,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:110 Alt:1 GPIO SD B0 04 FLEXPWM1 PWMA02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET), [ALT1].sel = 1, /* Index:110 Alt:2 GPIO SD B0 04 LPUART8 TX */ @@ -6232,7 +6497,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:110 Alt:8 GPIO SD B0 04 ENET2 RDATA01 */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_1_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_1_OFFSET), [ALT8].sel = 1, /* Index:110 Alt:9 No input selection */ @@ -6253,7 +6520,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:111 Alt:1 GPIO SD B0 05 FLEXPWM1 PWMB02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET), [ALT1].sel = 1, /* Index:111 Alt:2 GPIO SD B0 05 LPUART8 RX */ @@ -6288,7 +6556,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:111 Alt:8 GPIO SD B0 05 ENET2 RX EN */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXEN_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXEN_OFFSET), [ALT8].sel = 1, /* Index:111 Alt:9 No input selection */ @@ -6304,22 +6574,26 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:112 Alt:0 GPIO SD B1 00 USDHC2 DATA3 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA3_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA3_OFFSET), [ALT0].sel = 0, /* Index:112 Alt:1 GPIO SD B1 00 FLEXSPIB DATA03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET), [ALT1].sel = 0, /* Index:112 Alt:2 GPIO SD B1 00 FLEXPWM1 PWMA03 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), [ALT2].sel = 0, /* Index:112 Alt:3 GPIO SD B1 00 SAI1 TX DATA03 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA1_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA1_OFFSET), [ALT3].sel = 0, /* Index:112 Alt:4 GPIO SD B1 00 LPUART4 TX */ @@ -6344,7 +6618,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:112 Alt:8 GPIO SD B1 00 SAI3 RX DATA */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_IPP_IND_SAI_RXDATA_0_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_SAI3_IPP_IND_SAI_RXDATA_0_OFFSET), [ALT8].sel = 1, /* Index:112 Alt:9 No input selection */ @@ -6360,27 +6636,32 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:113 Alt:0 GPIO SD B1 01 USDHC2 DATA2 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA2_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA2_OFFSET), [ALT0].sel = 0, /* Index:113 Alt:1 GPIO SD B1 01 FLEXSPIB DATA02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET), [ALT1].sel = 0, /* Index:113 Alt:2 GPIO SD B1 01 FLEXPWM1 PWMB03 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), [ALT2].sel = 0, /* Index:113 Alt:3 GPIO SD B1 01 SAI1 TX DATA02 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA2_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA2_OFFSET), [ALT3].sel = 0, /* Index:113 Alt:4 GPIO SD B1 01 LPUART4 RX */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_RX_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_RX_OFFSET), [ALT4].sel = 0, /* Index:113 Alt:5 No input selection */ @@ -6416,22 +6697,26 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:114 Alt:0 GPIO SD B1 02 USDHC2 DATA1 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA1_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA1_OFFSET), [ALT0].sel = 0, /* Index:114 Alt:1 GPIO SD B1 02 FLEXSPIB DATA01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET), [ALT1].sel = 0, /* Index:114 Alt:2 GPIO SD B1 02 FLEXPWM2 PWMA03 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), [ALT2].sel = 0, /* Index:114 Alt:3 GPIO SD B1 02 SAI1 TX DATA01 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA3_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA3_OFFSET), [ALT3].sel = 0, /* Index:114 Alt:4 No input selection */ @@ -6456,7 +6741,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:114 Alt:8 GPIO SD B1 02 SAI3 TX SYNC */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_IPP_IND_SAI_TXSYNC_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_SAI3_IPP_IND_SAI_TXSYNC_OFFSET), [ALT8].sel = 1, /* Index:114 Alt:9 No input selection */ @@ -6472,17 +6759,20 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:115 Alt:0 GPIO SD B1 03 USDHC2 DATA0 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA0_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA0_OFFSET), [ALT0].sel = 0, /* Index:115 Alt:1 GPIO SD B1 03 FLEXSPIB DATA00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET), [ALT1].sel = 0, /* Index:115 Alt:2 GPIO SD B1 03 FLEXPWM2 PWMB03 */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET), [ALT2].sel = 0, /* Index:115 Alt:3 GPIO SD B1 03 SAI1 MCLK */ @@ -6492,7 +6782,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:115 Alt:4 GPIO SD B1 03 FLEXCAN1 RX */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), [ALT4].sel = 0, /* Index:115 Alt:5 No input selection */ @@ -6502,7 +6793,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:115 Alt:6 GPIO SD B1 03 CCM PMIC READY */ - [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), + [ALT6].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), [ALT6].sel = 0, /* Index:115 Alt:7 No input selection */ @@ -6512,7 +6804,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:115 Alt:8 GPIO SD B1 03 SAI3 TX BCLK */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_IPP_IND_SAI_TXBCLK_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_SAI3_IPP_IND_SAI_TXBCLK_OFFSET), [ALT8].sel = 1, /* Index:115 Alt:9 No input selection */ @@ -6543,7 +6837,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:116 Alt:3 GPIO SD B1 04 SAI1 RX SYNC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_SYNC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_SYNC_OFFSET), [ALT3].sel = 0, /* Index:116 Alt:4 No input selection */ @@ -6568,7 +6863,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:116 Alt:8 GPIO SD B1 04 SAI3 MCLK */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_IPG_CLK_SAI_MCLK_2_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_SAI3_IPG_CLK_SAI_MCLK_2_OFFSET), [ALT8].sel = 1, /* Index:116 Alt:9 No input selection */ @@ -6589,7 +6886,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:117 Alt:1 GPIO SD B1 05 FLEXSPIA DQS */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DQS_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DQS_OFFSET), [ALT1].sel = 0, /* Index:117 Alt:2 GPIO SD B1 05 LPI2C1 SDA */ @@ -6599,7 +6897,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:117 Alt:3 GPIO SD B1 05 SAI1 RX BCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_BCLK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_BCLK_OFFSET), [ALT3].sel = 0, /* Index:117 Alt:4 No input selection */ @@ -6624,7 +6923,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:117 Alt:8 GPIO SD B1 05 SAI3 RX SYNC */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_IPP_IND_SAI_RXSYNC_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_SAI3_IPP_IND_SAI_RXSYNC_OFFSET), [ALT8].sel = 1, /* Index:117 Alt:9 No input selection */ @@ -6655,12 +6956,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:118 Alt:3 GPIO SD B1 06 SAI1 RX DATA00 */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA0_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA0_OFFSET), [ALT3].sel = 0, /* Index:118 Alt:4 GPIO SD B1 06 LPSPI2 PCS0 */ - [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_PCS0_OFFSET), + [ALT4].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_PCS0_OFFSET), [ALT4].sel = 0, /* Index:118 Alt:5 No input selection */ @@ -6680,7 +6983,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:118 Alt:8 GPIO SD B1 06 SAI3 RX BCLK */ - [ALT8].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_IPP_IND_SAI_RXBCLK_OFFSET), + [ALT8].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_SAI3_IPP_IND_SAI_RXBCLK_OFFSET), [ALT8].sel = 1, /* Index:118 Alt:9 No input selection */ @@ -6701,7 +7006,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:119 Alt:1 GPIO SD B1 07 FLEXSPIA SCLK */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_SCK_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_SCK_OFFSET), [ALT1].sel = 0, /* Index:119 Alt:2 No input selection */ @@ -6752,12 +7058,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:120 Alt:0 GPIO SD B1 08 USDHC2 DATA4 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA4_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA4_OFFSET), [ALT0].sel = 0, /* Index:120 Alt:1 GPIO SD B1 08 FLEXSPIA DATA00 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET), [ALT1].sel = 0, /* Index:120 Alt:2 GPIO SD B1 08 LPUART7 TX */ @@ -6767,7 +7075,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:120 Alt:3 GPIO SD B1 08 SAI1 TX BCLK */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_BCLK_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_BCLK_OFFSET), [ALT3].sel = 0, /* Index:120 Alt:4 GPIO SD B1 08 LPSPI2 SD0 */ @@ -6808,12 +7117,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:121 Alt:0 GPIO SD B1 09 USDHC2 DATA5 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA5_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA5_OFFSET), [ALT0].sel = 0, /* Index:121 Alt:1 GPIO SD B1 09 FLEXSPIA DATA01 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET), [ALT1].sel = 0, /* Index:121 Alt:2 GPIO SD B1 09 LPUART7 RX */ @@ -6823,7 +7134,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:121 Alt:3 GPIO SD B1 09 SAI1 TX SYNC */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_SYNC_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_SYNC_OFFSET), [ALT3].sel = 0, /* Index:121 Alt:4 GPIO SD B1 09 LPSPI2 SDI */ @@ -6864,12 +7176,14 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:122 Alt:0 GPIO SD B1 10 USDHC2 DATA6 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA6_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA6_OFFSET), [ALT0].sel = 0, /* Index:122 Alt:1 GPIO SD B1 10 FLEXSPIA DATA02 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET), [ALT1].sel = 0, /* Index:122 Alt:2 GPIO SD B1 10 LPUART2 RX */ @@ -6920,22 +7234,26 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:123 Alt:0 GPIO SD B1 11 USDHC2 DATA7 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA7_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_DATA7_OFFSET), [ALT0].sel = 0, /* Index:123 Alt:1 GPIO SD B1 11 FLEXSPIA DATA03 */ - [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET), + [ALT1].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET), [ALT1].sel = 0, /* Index:123 Alt:2 GPIO SD B1 11 LPUART2 TX */ - [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART2_TX_OFFSET), + [ALT2].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART2_TX_OFFSET), [ALT2].sel = 0, /* Index:123 Alt:3 GPIO SD B1 11 LPI2C2 SCL */ - [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C2_SCL_OFFSET), + [ALT3].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C2_SCL_OFFSET), [ALT3].sel = 0, /* Index:123 Alt:4 No input selection */ @@ -7011,7 +7329,8 @@ static const struct imxrt_daisy_t g_daisy_select[] = /* Index:124 Alt:7 SNVS WAKEUP NMI GLUE NMI */ - [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_NMI_GLUE_NMI_OFFSET), + [ALT7].index = + IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_NMI_GLUE_NMI_OFFSET), [ALT7].sel = 1, /* Index:124 Alt:8 No input selection */ @@ -7200,7 +7519,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:128 Alt:0 GPIO SPI B0 01 FLEXSPI2 B SCLK */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FB_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FB_OFFSET), [ALT0].sel = 1, /* Index:128 Alt:1 No input selection */ @@ -7256,7 +7577,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:129 Alt:0 GPIO SPI B0 02 FLEXSPI2 A DATA00 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT0_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT0_OFFSET), [ALT0].sel = 2, /* Index:129 Alt:1 No input selection */ @@ -7312,7 +7635,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:130 Alt:0 GPIO SPI B0 03 FLEXSPI2 B DATA02 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT2_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT2_OFFSET), [ALT0].sel = 1, /* Index:130 Alt:1 No input selection */ @@ -7368,7 +7693,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:131 Alt:0 GPIO SPI B0 04 FLEXSPI2 B DATA03 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT3_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT3_OFFSET), [ALT0].sel = 1, /* Index:131 Alt:1 No input selection */ @@ -7480,7 +7807,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:133 Alt:0 GPIO SPI B0 06 FLEXSPI2 A DATA02 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT2_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT2_OFFSET), [ALT0].sel = 2, /* Index:133 Alt:1 No input selection */ @@ -7536,7 +7865,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:134 Alt:0 GPIO SPI B0 07 FLEXSPI2 B DATA01 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT1_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT1_OFFSET), [ALT0].sel = 1, /* Index:134 Alt:1 No input selection */ @@ -7592,7 +7923,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:135 Alt:0 GPIO SPI B0 08 FLEXSPI2 A SCLK */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FA_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FA_OFFSET), [ALT0].sel = 2, /* Index:135 Alt:1 No input selection */ @@ -7648,7 +7981,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:136 Alt:0 GPIO SPI B0 09 FLEXSPI2 A DQS */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_DQS_FA_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_DQS_FA_OFFSET), [ALT0].sel = 2, /* Index:136 Alt:1 No input selection */ @@ -7704,7 +8039,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:137 Alt:0 GPIO SPI B0 10 FLEXSPI2 A DATA03 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT3_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT3_OFFSET), [ALT0].sel = 2, /* Index:137 Alt:1 No input selection */ @@ -7760,7 +8097,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:138 Alt:0 GPIO SPI B0 11 FLEXSPI2 B DATA00 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT0_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT0_OFFSET), [ALT0].sel = 1, /* Index:138 Alt:1 No input selection */ @@ -7816,7 +8155,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:139 Alt:0 GPIO SPI B0 12 FLEXSPI2 A DATA01 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT1_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT1_OFFSET), [ALT0].sel = 2, /* Index:139 Alt:1 No input selection */ @@ -7928,7 +8269,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:141 Alt:0 GPIO SPI B1 00 FLEXSPI2 A DQS */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_DQS_FA_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_DQS_FA_OFFSET), [ALT0].sel = 0, /* Index:141 Alt:1 No input selection */ @@ -7984,7 +8327,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:142 Alt:0 GPIO SPI B1 01 FLEXSPI2 A DATA03 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT3_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT3_OFFSET), [ALT0].sel = 0, /* Index:142 Alt:1 No input selection */ @@ -8040,7 +8385,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:143 Alt:0 GPIO SPI B1 02 FLEXSPI2 A DATA02 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT2_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT2_OFFSET), [ALT0].sel = 0, /* Index:143 Alt:1 No input selection */ @@ -8096,7 +8443,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:144 Alt:0 GPIO SPI B1 03 FLEXSPI2 A DATA01 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT1_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT1_OFFSET), [ALT0].sel = 0, /* Index:144 Alt:1 No input selection */ @@ -8152,7 +8501,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:145 Alt:0 GPIO SPI B1 04 FLEXSPI2 A DATA00 */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT0_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT0_OFFSET), [ALT0].sel = 0, /* Index:145 Alt:1 No input selection */ @@ -8208,7 +8559,9 @@ static const struct imxrt_daisy_t g_daisy_select[] = { /* Index:146 Alt:0 GPIO SPI B1 05 FLEXSPI2 A SCLK */ - [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FA_OFFSET), + [ALT0].index = + IMXRT_INPUT_OFFSET2INDEX( + IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FA_OFFSET), [ALT0].sel = 0, /* Index:146 Alt:1 No input selection */ @@ -8370,3 +8723,7 @@ static const struct imxrt_daisy_t g_daisy_select[] = }, }, }; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/imxrt/imxrt_xbar.c b/arch/arm/src/imxrt/imxrt_xbar.c index 1039b7a9ce8..df97ae4299a 100644 --- a/arch/arm/src/imxrt/imxrt_xbar.c +++ b/arch/arm/src/imxrt/imxrt_xbar.c @@ -89,14 +89,17 @@ int imxrt_xbar_connect(uint16_t mux_index_out, uint16_t mux_index_input) * 4) Input index is input. */ - if (xbar_index < sizeof(g_xbars_addresses) / sizeof(g_xbars_addresses[0]) && + if (xbar_index < sizeof(g_xbars_addresses) / + sizeof(g_xbars_addresses[0]) && (mux_index_out & XBAR_OUTPUT) == XBAR_OUTPUT && (mux_index_input & XBAR_INPUT) == XBAR_INPUT) { address = g_xbars_addresses[xbar_index]; address += (mux_select / IMXRT_SEL_PER_REG) * sizeof(uint16_t); - /* There are 2 selects per Register LSB is even selects and MSB is odd */ + /* There are 2 selects per Register LSB is even selects and + * MSB is odd + */ if (mux_select & 1) { diff --git a/arch/arm/src/imxrt/imxrt_xbar.h b/arch/arm/src/imxrt/imxrt_xbar.h index cda7fce8dc8..f974856e34b 100644 --- a/arch/arm/src/imxrt/imxrt_xbar.h +++ b/arch/arm/src/imxrt/imxrt_xbar.h @@ -1,4 +1,4 @@ -/************************************************************************************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/imxrt_xbar.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,27 @@ * License for the specific language governing permissions and limitations * under the License. * - **************************************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_XBAR_H #define __ARCH_ARM_SRC_IMXRT_IMXRT_XBAR_H -/************************************************************************************************************************************************** +/**************************************************************************** * Included Files - **************************************************************************************************************************************************/ + ****************************************************************************/ #include #include #include "hardware/imxrt_xbar.h" #include "hardware/imxrt_memorymap.h" -/************************************************************************************************************************************************** +/* Collect correct XBAR definitions from chip file */ + +#include "hardware/imxrt_xbar.h" + +/**************************************************************************** * Pre-processor Definitions - **************************************************************************************************************************************************/ + ****************************************************************************/ /* Cross Bars * @@ -48,7 +52,8 @@ * Therefore there are M select fields that will be written to I values. * The M fields are know as SELn, there are 2 selects fields per register. * - * A Input is wired to an output with a call to imxrt_xbar_connect(output, input) + * A Input is wired to an output with a call to imxrt_xbar_connect(output, + * input) * */ @@ -57,52 +62,49 @@ * v vvvv +++++++---- Index of input or output index * 000s xxxx nnnnnnnn * - * Where side is used to parameter check the passed value in output is an output - * XBAR is the index of the XBAR + * Where side is used to parameter check the passed value in output is an + * output XBAR is the index of the XBAR * input|output index - the index of the M mux (output) or I. * */ /* Input and Output Indexes */ -#define IMXRT_XBARA_IO_INDEX_SHIFTS 0 -#define IMXRT_XBARA_IO_INDEX_MASK (0xff << IMXRT_XBARA_IO_INDEX_SHIFTS) +#define IMXRT_XBARA_IO_INDEX_SHIFTS 0 +#define IMXRT_XBARA_IO_INDEX_MASK (0xff << IMXRT_XBARA_IO_INDEX_SHIFTS) /* Index for xbar addresses */ -#define IMXRT_XBARA_INDEX_SHIFTS 8 -#define IMXRT_XBARA_INDEX_MASK (0xf << IMXRT_XBARA_INDEX_SHIFTS) -# define IMXRT_XBARA1_INDEX (0 << IMXRT_XBARA_INDEX_SHIFTS) -# define IMXRT_XBARA2_INDEX (1 << IMXRT_XBARA_INDEX_SHIFTS) -# define IMXRT_XBARA3_INDEX (2 << IMXRT_XBARA_INDEX_SHIFTS) +#define IMXRT_XBARA_INDEX_SHIFTS 8 +#define IMXRT_XBARA_INDEX_MASK (0xf << IMXRT_XBARA_INDEX_SHIFTS) +# define IMXRT_XBARA1_INDEX (0 << IMXRT_XBARA_INDEX_SHIFTS) +# define IMXRT_XBARA2_INDEX (1 << IMXRT_XBARA_INDEX_SHIFTS) +# define IMXRT_XBARA3_INDEX (2 << IMXRT_XBARA_INDEX_SHIFTS) /* Side of xbar */ -#define IMXRT_XBARA_SIDE_SHIFTS 12 -#define IMXRT_XBARA_SIDE_MASK (0x1 << IMXRT_XBARA_SIDE_SHIFTS) +#define IMXRT_XBARA_SIDE_SHIFTS 12 +#define IMXRT_XBARA_SIDE_MASK (0x1 << IMXRT_XBARA_SIDE_SHIFTS) -#define XBAR_OUTPUT (0x1 << IMXRT_XBARA_SIDE_SHIFTS) -#define XBAR_INPUT (0x0 << IMXRT_XBARA_SIDE_SHIFTS) +#define XBAR_OUTPUT (0x1 << IMXRT_XBARA_SIDE_SHIFTS) +#define XBAR_INPUT (0x0 << IMXRT_XBARA_SIDE_SHIFTS) /* xbar helpers */ -#define IMXRT_XBARA1(side, select) ((uint16_t)((side) | IMXRT_XBARA1_INDEX | \ - ((select) & 0xff) << IMXRT_XBARA_IO_INDEX_SHIFTS)) -#define IMXRT_XBARA2(side, select) ((uint16_t)((side) | IMXRT_XBARA2_INDEX | \ - ((select) & 0xff) << IMXRT_XBARA_IO_INDEX_SHIFTS)) -#define IMXRT_XBARA3(side, select) ((uint16_t)((side) | IMXRT_XBARA3_INDEX | \ - ((select) & 0xff) << IMXRT_XBARA_IO_INDEX_SHIFTS)) +#define IMXRT_XBARA1(side, select) ((uint16_t)((side) | IMXRT_XBARA1_INDEX | \ + ((select) & 0xff) << IMXRT_XBARA_IO_INDEX_SHIFTS)) +#define IMXRT_XBARA2(side, select) ((uint16_t)((side) | IMXRT_XBARA2_INDEX | \ + ((select) & 0xff) << IMXRT_XBARA_IO_INDEX_SHIFTS)) +#define IMXRT_XBARA3(side, select) ((uint16_t)((side) | IMXRT_XBARA3_INDEX | \ + ((select) & 0xff) << IMXRT_XBARA_IO_INDEX_SHIFTS)) -#define IMXRT_SEL(six) ((six) & IMXRT_XBARA_IO_INDEX_MASK) >> IMXRT_XBARA_IO_INDEX_SHIFTS -#define IMXRT_XBAR(six) ((six) & IMXRT_XBARA_INDEX_MASK) >> IMXRT_XBARA_INDEX_SHIFTS -#define IMXRT_SIDE(six) ((six) & IMXRT_XBARA_SIDE_MASK) >> IMXRT_XBARA_SIDE_SHIFTS +#define IMXRT_SEL(six) ((six) & IMXRT_XBARA_IO_INDEX_MASK) >> IMXRT_XBARA_IO_INDEX_SHIFTS +#define IMXRT_XBAR(six) ((six) & IMXRT_XBARA_INDEX_MASK) >> IMXRT_XBARA_INDEX_SHIFTS +#define IMXRT_SIDE(six) ((six) & IMXRT_XBARA_SIDE_MASK) >> IMXRT_XBARA_SIDE_SHIFTS -/* Collect correct XBAR definitions from chip file */ -#include "hardware/imxrt_xbar.h" - -/************************************************************************************************************************************************** - * Public Functions - **************************************************************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -115,7 +117,7 @@ extern "C" #define EXTERN extern #endif -/****************************************************************************************************************************************** +/**************************************************************************** * Name: imxrt_xbar_connect * * Description: @@ -128,7 +130,7 @@ extern "C" * Returned Value: * OK on success; Negated errno on failure. * - ******************************************************************************************************************************************/ + ****************************************************************************/ int imxrt_xbar_connect(uint16_t mux_out, uint16_t mux_input); diff --git a/arch/arm/src/kl/hardware/kl_tsi.h b/arch/arm/src/kl/hardware/kl_tsi.h index 95d70050b21..8fc88e1b286 100644 --- a/arch/arm/src/kl/hardware/kl_tsi.h +++ b/arch/arm/src/kl/hardware/kl_tsi.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kl/hardware/kl_tsi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,38 +16,39 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KL_HARDWARE_KL_TSI_H #define __ARCH_ARM_SRC_KL_HARDWARE_KL_TSI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KL_TSI_GENCS_OFFSET 0x0000 /* General Control and Status Register */ #define KL_TSI_DATA_OFFSET 0x0004 /* SCAN control register */ #define KL_TSI_TSHD_OFFSET 0x0008 /* Pin enable register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KL_TSI_GENCS (KL_TSI_BASE+KL_TSI_GENCS_OFFSET) #define KL_TSI_DATA (KL_TSI_BASE+KL_TSI_DATA_OFFSET) #define KL_TSI_TSHD (KL_TSI_BASE+KL_TSI_TSHD_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* General Control and Status Register */ + /* Bit 0: Reserved */ #define TSI_GENCS_CURSW (1 << 1) /* Bit 1: Current sources for oscillators swapped */ #define TSI_GENCS_EOSF (1 << 2) /* Bit 2: End of scan flag */ @@ -59,6 +60,7 @@ #define TSI_GENCS_NSCN_SHIFT (8) /* Bits 8-12: Electrode oscillator count used in a scan */ #define TSI_GENCS_NSCN_MASK (31 << TSI_GENCS_NSCN_SHIFT) # define TSI_GENCS_NSCN_TIMES(n) (((n)-1) << TSI_GENCS_NSCN_SHIFT) /* n times per electrode,n=1..32 */ + #define TSI_GENCS_PS_SHIFT (13) /* Bits 13-15: Prescaler value */ #define TSI_GENCS_PS_MASK (7 << TSI_GENCS_PS_SHIFT) # define TSI_GENCS_PS_DIV1 (0 << TSI_GENCS_PS_SHIFT) /* Electrode oscillator / 1 */ @@ -69,6 +71,7 @@ # define TSI_GENCS_PS_DIV32 (5 << TSI_GENCS_PS_SHIFT) /* Electrode oscillator / 32 */ # define TSI_GENCS_PS_DIV64 (6 << TSI_GENCS_PS_SHIFT) /* Electrode oscillator / 64 */ # define TSI_GENCS_PS_DIV128 (7 << TSI_GENCS_PS_SHIFT) /* Electrode oscillator / 128 */ + #define TSI_GENCS_EXTCHRG_SHIFT (16) /* Bits 16-18: Electrode Osc charge/discharge value */ #define TSI_GENCS_EXTCHRG_MASK (7 << TSI_GENCS_EXTCHRG_SHIFT) # define TSI_GENCS_EXTCHRG_500NA (0 << TSI_GENCS_EXTCHRG_SHIFT) @@ -124,16 +127,16 @@ #define TSI_THRESHLD_LTHH_SHIFT (16) /* Bits 16-31: Low threshold value */ #define TSI_THRESHLD_LTHH_MASK (0xffff << TSI_THRESHLD_LTHH_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KL_HARDWARE_KL_TSI_H */ diff --git a/arch/arm/src/kl/kl_clockconfig.c b/arch/arm/src/kl/kl_clockconfig.c index 47109dccbe2..a38e6f13849 100644 --- a/arch/arm/src/kl/kl_clockconfig.c +++ b/arch/arm/src/kl/kl_clockconfig.c @@ -93,10 +93,13 @@ void kl_pllconfig(void) * settings in the board.h header file. */ - regval32 = (SIM_CLKDIV1_OUTDIV1(BOARD_OUTDIV1) | SIM_CLKDIV1_OUTDIV4(BOARD_OUTDIV4)); + regval32 = (SIM_CLKDIV1_OUTDIV1(BOARD_OUTDIV1) | + SIM_CLKDIV1_OUTDIV4(BOARD_OUTDIV4)); putreg32(regval32, KL_SIM_CLKDIV1); - /* System oscillator drives 32 kHz clock for various peripherals (OSC32KSEL=0) */ + /* System oscillator drives 32 kHz clock for various peripherals + * (OSC32KSEL=0) + */ regval32 = getreg32(KL_SIM_SOPT1); regval32 &= ~(SIM_SOPT1_OSC32KSEL_MASK); @@ -110,10 +113,12 @@ void kl_pllconfig(void) regval32 |= SIM_SOPT2_PLLFLLSEL; putreg32(regval32, KL_SIM_SOPT2); - regval32 = (regval32 & ~(SIM_SOPT2_TPMSRC_OCSERCLK)) | SIM_SOPT2_TPMSRC_MCGCLK; + regval32 = (regval32 & ~(SIM_SOPT2_TPMSRC_OCSERCLK)) | + SIM_SOPT2_TPMSRC_MCGCLK; putreg32(regval32, KL_SIM_SOPT2); /* PORTA_PCR18: ISF=0, MUX=0 */ + /* PORTA_PCR19: ISF=0, MUX=0 */ regval32 = getreg32(KL_PORTA_PCR18); @@ -125,7 +130,10 @@ void kl_pllconfig(void) putreg32(regval32, KL_PORTA_PCR19); /* Switch to FBE Mode */ - /* OSC0_CR: ERCLKEN=0, ??=0, EREFSTEN=0, ??=0, SC2P=0, SC4P=0, SC8P=0, SC16P=0 */ + + /* OSC0_CR: ERCLKEN=0, + * ??=0, EREFSTEN=0, ??=0, SC2P=0, SC4P=0, SC8P=0, SC16P=0 + */ putreg8(0, KL_OSC_CR); @@ -191,8 +199,7 @@ void kl_pllconfig(void) /* Wait until PLL output */ - while ((getreg8(KL_MCG_S) & MCG_S_CLKST_MASK) != 0x0C) - ; + while ((getreg8(KL_MCG_S) & MCG_S_CLKST_MASK) != 0x0c); } /**************************************************************************** @@ -223,6 +230,7 @@ void kl_clockconfig(void) * the FlexBus clock. */ - //kl_traceconfig(); - //kl_fbconfig(); + /* kl_traceconfig(); */ + + /* kl_fbconfig(); */ } diff --git a/arch/arm/src/kl/kl_pwm.h b/arch/arm/src/kl/kl_pwm.h index c2332679790..913817fac59 100644 --- a/arch/arm/src/kl/kl_pwm.h +++ b/arch/arm/src/kl/kl_pwm.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kl/kl_pwm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,27 +16,39 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KL_KINETIS_PWM_H #define __ARCH_ARM_SRC_KL_KINETIS_PWM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/* Check if PWM support for any channel is enabled. */ + +#if defined(CONFIG_KL_TPM0_PWM) || defined(CONFIG_KL_TPM1_PWM) || \ + defined(CONFIG_KL_TPM2_PWM) + +#include +#include "hardware/kl_pinmux.h" +#endif + +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ + /* Timer devices may be used for different purposes. One special purpose is - * to generate modulated outputs for such things as motor control. If CONFIG_KL_TPMn - * is defined then the CONFIG_KL_TPMn_PWM must also be defined to indicate that - * timer "n" is intended to be used for pulsed output signal generation. + * to generate modulated outputs for such things as motor control. + * If CONFIG_KL_TPMn is defined then the CONFIG_KL_TPMn_PWM must also be + * defined to indicate that timer "n" is intended to be used for pulsed + * output signal generation. */ #ifndef CONFIG_KL_TPM0 @@ -54,16 +66,13 @@ #if defined(CONFIG_KL_TPM0_PWM) || defined(CONFIG_KL_TPM1_PWM) || \ defined(CONFIG_KL_TPM2_PWM) -#include -#include "hardware/kl_pinmux.h" - -/* For each timer that is enabled for PWM usage, we need the following additional - * configuration settings: +/* For each timer that is enabled for PWM usage, we need the following + * additional configuration settings: * * CONFIG_KL_TPMx_CHANNEL - Specifies the timer output channel {1,..,4} - * PWM_TPMx_CHn - One of the values defined in chip/kl*_pinmap.h. In the case - * where there are multiple pin selections, the correct setting must be provided - * in the arch/board/board.h file. + * PWM_TPMx_CHn - One of the values defined in chip/kl*_pinmap.h. In the + * case where there are multiple pin selections, the correct setting must + * be provided in the arch/board/board.h file. */ #ifdef CONFIG_KL_TPM0_PWM @@ -126,13 +135,13 @@ # endif #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -145,11 +154,11 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: kl_pwminitialize * * Description: @@ -162,7 +171,7 @@ extern "C" * On success, a pointer to the KL lower half PWM driver is returned. * NULL is returned on any failure. * - ************************************************************************************/ + ****************************************************************************/ FAR struct pwm_lowerhalf_s *kl_pwminitialize(int timer); diff --git a/arch/arm/src/lpc43xx/lpc43_timer.h b/arch/arm/src/lpc43xx/lpc43_timer.h index 3181d764195..120990d5938 100644 --- a/arch/arm/src/lpc43xx/lpc43_timer.h +++ b/arch/arm/src/lpc43xx/lpc43_timer.h @@ -49,7 +49,7 @@ extern "C" #endif /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ /**************************************************************************** diff --git a/arch/arm/src/nrf52/hardware/nrf52_nvmc.h b/arch/arm/src/nrf52/hardware/nrf52_nvmc.h index 77143d85a53..bb622bc6680 100644 --- a/arch/arm/src/nrf52/hardware/nrf52_nvmc.h +++ b/arch/arm/src/nrf52/hardware/nrf52_nvmc.h @@ -1,4 +1,4 @@ -/*************************************************************************************************** +/**************************************************************************** * arch/arm/src/nrf52/hardware/nrf52_nvmc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ***************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_NVMC_H #define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_NVMC_H -/*************************************************************************************************** +/**************************************************************************** * Included Files - ***************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/nrf52_memorymap.h" -/*************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ***************************************************************************************************/ + ****************************************************************************/ -/* NVMC Register Offsets ****************************************************************************/ +/* NVMC Register Offsets ****************************************************/ /* Registers for the NVMC */ @@ -47,7 +47,7 @@ #define NRF52_NVMC_IHIT_OFFSET 0x548 /* I-Code cache hit counter. */ #define NRF52_NVMC_IMISS_OFFSET 0x54c /* I-Code cache miss counter */ -/* NVMC Register Addresses **************************************************************************/ +/* NVMC Register Addresses **************************************************/ #define NRF52_NVMC_READY (NRF52_NVMC_BASE + NRF52_NVMC_READY_OFFSET) #define NRF52_NVMC_CONFIG (NRF52_NVMC_BASE + NRF52_NVMC_CONFIG_OFFSET) @@ -60,7 +60,7 @@ #define NRF52_NVMC_IHIT (NRF52_NVMC_BASE + NRF52_NVMC_IHIT_OFFSET) #define NRF52_NVMC_IMISS (NRF52_NVMC_BASE + NRF52_NVMC_IMISS_OFFSET) -/* NVMC Register Bitfield Definitions **************************************************************/ +/* NVMC Register Bitfield Definitions ***************************************/ /* READY Register */ diff --git a/arch/arm/src/samv7/sam_systemreset.c b/arch/arm/src/samv7/sam_systemreset.c index a1ffe58816c..f5513b2dc92 100644 --- a/arch/arm/src/samv7/sam_systemreset.c +++ b/arch/arm/src/samv7/sam_systemreset.c @@ -37,7 +37,7 @@ #ifdef CONFIG_SAMV7_SYSTEMRESET /**************************************************************************** - * Public functions + * Public Functions ****************************************************************************/ /**************************************************************************** @@ -62,7 +62,7 @@ void up_systemreset(void) rstmr = getreg32(SAM_RSTC_MR); rstmr &= ~RSTC_MR_ERSTL_MASK; - rstmr &= RSTC_MR_ERSTL(CONFIG_SAMV7_EXTRESET_ERST-1) | RSTC_MR_KEY; + rstmr &= RSTC_MR_ERSTL(CONFIG_SAMV7_EXTRESET_ERST - 1) | RSTC_MR_KEY; putreg32(rstmr, SAM_RSTC_MR); #endif diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h index ec5d3d7da68..c746dfa8421 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h @@ -1,4 +1,4 @@ -/******************************************************************************** +/**************************************************************************** * arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H #define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H -/******************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************/ + ****************************************************************************/ #include @@ -32,7 +32,8 @@ /* STM32 M0 ADC driver: * - no injected channels * - no offset registers - * - the F0/L0 family support one sampling time configuration for all channels + * - the F0/L0 family support one sampling time configuration for all + * channels * - the G0 family support two sampling time configurations */ @@ -70,24 +71,24 @@ #undef ADC_HAVE_INJECTED -/******************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************/ + ****************************************************************************/ -#define STM32_ADC1_OFFSET 0x0000 -#define STM32_ADC2_OFFSET 0x0100 -#define STM32_ADC3_OFFSET 0x0000 -#define STM32_ADC4_OFFSET 0x0100 -#define STM32_ADCCMN_OFFSET 0x0300 +#define STM32_ADC1_OFFSET 0x0000 +#define STM32_ADC2_OFFSET 0x0100 +#define STM32_ADC3_OFFSET 0x0000 +#define STM32_ADC4_OFFSET 0x0100 +#define STM32_ADCCMN_OFFSET 0x0300 -#define STM32_ADC1_BASE (STM32_ADC1_OFFSET+STM32_ADC12_BASE) /* ADC1 Master ADC */ -#define STM32_ADC2_BASE (STM32_ADC2_OFFSET+STM32_ADC12_BASE) /* ADC2 Slave ADC */ -#define STM32_ADC3_BASE (STM32_ADC3_OFFSET+STM32_ADC34_BASE) /* ADC3 Master ADC */ -#define STM32_ADC4_BASE (STM32_ADC4_OFFSET+STM32_ADC34_BASE) /* ADC4 Slave ADC */ -#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET+STM32_ADC12_BASE) /* ADC1, ADC2 common */ -#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET+STM32_ADC34_BASE) /* ADC3, ADC4 common */ +#define STM32_ADC1_BASE (STM32_ADC1_OFFSET+STM32_ADC12_BASE) /* ADC1 Master ADC */ +#define STM32_ADC2_BASE (STM32_ADC2_OFFSET+STM32_ADC12_BASE) /* ADC2 Slave ADC */ +#define STM32_ADC3_BASE (STM32_ADC3_OFFSET+STM32_ADC34_BASE) /* ADC3 Master ADC */ +#define STM32_ADC4_BASE (STM32_ADC4_OFFSET+STM32_ADC34_BASE) /* ADC4 Slave ADC */ +#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET+STM32_ADC12_BASE) /* ADC1, ADC2 common */ +#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET+STM32_ADC34_BASE) /* ADC3, ADC4 common */ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */ #define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */ @@ -103,7 +104,7 @@ #define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_ADC1_ISR (STM32_ADC1_BASE + STM32_ADC_ISR_OFFSET) #define STM32_ADC1_IER (STM32_ADC1_BASE + STM32_ADC_IER_OFFSET) @@ -116,9 +117,11 @@ #define STM32_ADC1_DR (STM32_ADC1_BASE + STM32_ADC_DR_OFFSET) #define STM32_ADC1_CCR (STM32_ADC1_BASE + STM32_ADC_CCR_OFFSET) -/* Register Bitfield Definitions ************************************************/ +/* Register Bitfield Definitions ********************************************/ -/* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */ +/* ADC interrupt and status register (ISR) and + * ADC interrupt enable register (IER) + */ #define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */ #define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */ @@ -147,6 +150,7 @@ # define ADC_CFGR1_RES_10BIT (1 << ADC_CFGR1_RES_SHIFT) /* 13 ADCCLK clyes */ # define ADC_CFGR1_RES_8BIT (2 << ADC_CFGR1_RES_SHIFT) /* 11 ADCCLK clyes */ # define ADC_CFGR1_RES_6BIT (3 << ADC_CFGR1_RES_SHIFT) /* 9 ADCCLK clyes */ + #define ADC_CFGR1_ALIGN (1 << 5) /* Bit 5: Data Alignment */ #define ADC_CFGR1_EXTSEL_SHIFT (6) /* Bits 6-8: External trigger selection */ #define ADC_CFGR1_EXTSEL_MASK (7 << ADC_CFGR1_EXTSEL_SHIFT) @@ -164,6 +168,7 @@ # define ADC_CFGR1_EXTEN_RISING (1 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the rising edge */ # define ADC_CFGR1_EXTEN_FALLING (2 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the falling edge */ # define ADC_CFGR1_EXTEN_BOTH (3 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on both edges */ + #define ADC_CFGR1_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */ #define ADC_CFGR1_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */ #define ADC_CFGR1_WAIT (1 << 14) /* Bit 14: Wait conversion mode */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_can.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_can.h index 5b530f28000..d4d07058b9f 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_can.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_can.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f0l0g0/hardware/stm32_can.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H #define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* 3 TX mailboxes */ @@ -48,7 +48,7 @@ #define CAN_NFILTERS 14 -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ /* CAN control and status registers */ @@ -121,7 +121,7 @@ #define STM32_CAN_FIR_OFFSET(f,i) (0x240 + ((f) << 3)+(((i) - 1) << 2)) -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #if STM32_NCAN > 0 # define STM32_CAN1_MCR (STM32_CAN1_BASE + STM32_CAN_MCR_OFFSET) @@ -231,7 +231,7 @@ # define STM32_CAN2_FIR(b,i) (STM32_CAN2_BASE + STM32_CAN_FIR_OFFSET(b,i)) #endif -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* CAN master control register */ @@ -324,6 +324,7 @@ # define CAN_ESR_BDOMERROR (5 << CAN_ESR_LEC_SHIFT) /* 101: Bit dominant Error */ # define CAN_ESR_CRCERRPR (6 << CAN_ESR_LEC_SHIFT) /* 110: CRC Error */ # define CAN_ESR_SWERROR (7 << CAN_ESR_LEC_SHIFT) /* 111: Set by software */ + #define CAN_ESR_TEC_SHIFT (16) /* Bits 23-16: LS byte of the 9-bit Transmit Error Counter */ #define CAN_ESR_TEC_MASK (0xff << CAN_ESR_TEC_SHIF) #define CAN_ESR_REC_SHIFT (24) /* Bits 31-24: Receive Error Counter */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h index 9cfac4d3146..a09ef6ad244 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H #define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_CRC_DR_OFFSET 0x0000 /* Data register */ #define STM32_CRC_IDR_OFFSET 0x0004 /* Independent Data register */ @@ -40,7 +40,7 @@ #define STM32_CRC_INIT_OFFSET 0x0010 /* Initial CRC value register */ #define STM32_CRC_POL_OFFSET 0x0014 /* CRC polynomial register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_CRC_DR (STM32_CRC_BASE + STM32_CRC_DR_OFFSET) #define STM32_CRC_IDR (STM32_CRC_BASE + STM32_CRC_IDR_OFFSET) @@ -48,7 +48,7 @@ #define STM32_CRC_INIT (STM32_CRC_BASE + STM32_CRC_INIT_OFFSET) #define STM32_CRC_POL (STM32_CRC_BASE + STM32_CRC_POL_OFFSET) -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* CRC independent data register */ @@ -63,12 +63,18 @@ # define CRC_CR_POLYSIZE_16 (1 << CRC_CR_POLYSIZE_SHIFT) /* 01: 16 bit polynomial */ # define CRC_CR_POLYSIZE_8 (2 << CRC_CR_POLYSIZE_SHIFT) /* 10: 8 bit polynomial */ # define CRC_CR_POLYSIZE_7 (3 << CRC_CR_POLYSIZE_SHIFT) /* 10: 8 bit polynomial */ + #define CRC_CR_REVIN_SHIFT 5 /* Bits 5-6: These bits ontrol the reversal of the bit order of the input data */ #define CRC_CR_REVIN_MASK (3 << CRC_CR_REVIN_SHIFT) # define CRC_CR_REVIN_NONE (0 << CRC_CR_REVIN_SHIFT) /* 00: bit order is not affected */ # define CRC_CR_REVIN_BYTE (1 << CRC_CR_REVIN_SHIFT) /* 01: reversal done by byte */ # define CRC_CR_REVIN_HWORD (2 << CRC_CR_REVIN_SHIFT) /* 10: reversal done by half-word */ # define CRC_CR_REVIN_WORD (3 << CRC_CR_REVIN_SHIFT) /* 11: reversal done by word */ + #define CRC_CR_REVOUT (1 << 7) /* This bit controls the reversal of the bit order of the output data */ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + #endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h index fb11b786b2b..437a361c05a 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,30 +16,30 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H #define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_CRS_CR_OFFSET 0x0000 /* CRS control register */ #define STM32_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ #define STM32_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ #define STM32_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_CRS_CR (STM32_CRS_BASE + STM32_CRS_CR_OFFSET) #define STM32_CRS_CFGR (STM32_CRS_BASE + STM32_CRS_CFGR_OFFSET) #define STM32_CRS_ISR (STM32_CRS_BASE + STM32_CRS_ISR_OFFSET) #define STM32_CRS_ICR (STM32_CRS_BASE + STM32_CRS_ICR_OFFSET) -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* CRS control register */ @@ -69,11 +69,13 @@ # define CRS_CFGR_SYNCDIV_d32 (5 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 32 */ # define CRS_CFGR_SYNCDIV_d64 (6 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 64 */ # define CRS_CFGR_SYNCDIV_d128 (7 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 128 */ + #define CRS_CFGR_SYNCSRC_SHIFT 28 /* Bits 28-29: SYNC signal source selection */ #define CRS_CFGR_SYNCSRC_MASK (3 << CRS_CFGR_SYNCSRC_SHIFT) # define CRS_CFGR_SYNCSRC_GPIO (0 << CRS_CFGR_SYNCSRC_SHIFT) /* GPIO as SYNC signal source */ # define CRS_CFGR_SYNCSRC_LSE (1 << CRS_CFGR_SYNCSRC_SHIFT) /* LSE as SYNC signal source */ # define CRS_CFGR_SYNCSRC_USBSOF (2 << CRS_CFGR_SYNCSRC_SHIFT) /* USB SOF as SYNC signal source */ + #define CRS_CFGR_SYNCPOL (1 << 31) /* SYNC polarity selection */ /* CRS interrupt and status register */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h index c287645ae07..9f580e2d0e5 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H #define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */ #define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ @@ -49,7 +49,7 @@ #define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ #define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ /* DAC */ @@ -68,9 +68,10 @@ #define STM32_DAC1_DOR2 (STM32_DAC1_BASE + STM32_DAC_DOR2_OFFSET) #define STM32_DAC1_SR (STM32_DAC1_BASE + STM32_DAC_SR_OFFSET) -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* DAC control register */ + /* These definitions may be used with the full, 32-bit register */ #define DAC_CR_EN1 (1 << 0) /* Bit 0: DAC channel 1 enable */ @@ -85,11 +86,13 @@ # define DAC_CR_TSEL1_TIM2 (4 << DAC_CR_TSEL1_SHIFT) /* Timer 2 TRGO event */ # define DAC_CR_TSEL1_EXT9 (6 << DAC_CR_TSEL1_SHIFT) /* External line9 */ # define DAC_CR_TSEL1_SW (7 << DAC_CR_TSEL1_SHIFT) /* Software trigger */ + #define DAC_CR_WAVE1_SHIFT (6) /* Bits 6-7: DAC channel 1 noise/triangle wave generation */ #define DAC_CR_WAVE1_MASK (3 << DAC_CR_WAVE1_SHIFT) # define DAC_CR_WAVE1_DISABLED (0 << DAC_CR_WAVE1_SHIFT) /* Wave generation disabled */ # define DAC_CR_WAVE1_NOISE (1 << DAC_CR_WAVE1_SHIFT) /* Noise wave generation enabled */ # define DAC_CR_WAVE1_TRIANGLE (2 << DAC_CR_WAVE1_SHIFT) /* Triangle wave generation enabled */ + #define DAC_CR_MAMP1_SHIFT (8) /* Bits 8-11: DAC channel 1 mask/amplitude selector */ #define DAC_CR_MAMP1_MASK (15 << DAC_CR_MAMP1_SHIFT) # define DAC_CR_MAMP1_AMP1 (0 << DAC_CR_MAMP1_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */ @@ -104,13 +107,14 @@ # define DAC_CR_MAMP1_AMP1023 (9 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */ # define DAC_CR_MAMP1_AMP2047 (10 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */ # define DAC_CR_MAMP1_AMP4095 (11 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */ + #define DAC_CR_DMAEN1 (1 << 12) /* Bit 12: DAC channel 1 DMA enable */ #define DAC_CR_DMAUDRIE1 (1 << 13) /* Bit 13: DAC channel 1 DMA Underrun Interrupt enable */ #define DAC_CR_EN2 (1 << 16) /* Bit 16: DAC channel 2 enable */ #define DAC_CR_BOFF2 (1 << 17) /* Bit 17: DAC channel 2 output buffer disable */ #define DAC_CR_TEN2 (1 << 18) /* Bit 18: DAC channel 2 trigger enable */ -#define DAC_CR_TSEL2_SHIFT (19) /* Bits 19-21: DAC channel 2 trigger selection */ +#define DAC_CR_TSEL2_SHIFT (19) /* Bits 19-21: DAC channel 2 trigger selection */ #define DAC_CR_TSEL2_MASK (7 << DAC_CR_TSEL2_SHIFT) # define DAC_CR_TSEL2_TIM6 (0 << DAC_CR_TSEL2_SHIFT) /* Timer 6 TRGO event */ # define DAC_CR_TSEL2_TIM3 (1 << DAC_CR_TSEL2_SHIFT) /* Timer 3 TRGO event */ @@ -119,11 +123,13 @@ # define DAC_CR_TSEL2_TIM2 (4 << DAC_CR_TSEL2_SHIFT) /* Timer 2 TRGO event */ # define DAC_CR_TSEL2_EXT9 (6 << DAC_CR_TSEL2_SHIFT) /* External line9 */ # define DAC_CR_TSEL2_SW (7 << DAC_CR_TSEL2_SHIFT) /* Software trigger */ + #define DAC_CR_WAVE2_SHIFT (22) /* Bit 22-23: DAC channel 2 noise/triangle wave generation enable */ #define DAC_CR_WAVE2_MASK (3 << DAC_CR_WAVE2_SHIFT) # define DAC_CR_WAVE2_DISABLED (0 << DAC_CR_WAVE2_SHIFT) /* Wave generation disabled */ # define DAC_CR_WAVE2_NOISE (1 << DAC_CR_WAVE2_SHIFT) /* Noise wave generation enabled */ # define DAC_CR_WAVE2_TRIANGLE (2 << DAC_CR_WAVE2_SHIFT) /* Triangle wave generation enabled */ + #define DAC_CR_MAMP2_SHIFT (24) /* Bit 24-27: DAC channel 2 mask/amplitude selector */ #define DAC_CR_MAMP2_MASK (15 << DAC_CR_MAMP2_SHIFT) # define DAC_CR_MAMP2_AMP1 (0 << DAC_CR_MAMP2_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */ @@ -138,6 +144,7 @@ # define DAC_CR_MAMP2_AMP1023 (9 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */ # define DAC_CR_MAMP2_AMP2047 (10 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */ # define DAC_CR_MAMP2_AMP4095 (11 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */ + #define DAC_CR_DMAEN2 (1 << 28) /* Bit 28: DAC channel 2 DMA enable */ #define DAC_CR_DMAUDRIE2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun interrupt enable */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h index 25071bc2320..cc35608246a 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,16 +16,16 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H #define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ #define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ @@ -39,7 +39,7 @@ #define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ #define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #if STM32_NI2C > 0 # define STM32_I2C1_CR1 (STM32_I2C1_BASE + STM32_I2C_CR1_OFFSET) @@ -69,7 +69,7 @@ # define STM32_I2C2_TXDR (STM32_I2C2_BASE + STM32_I2C_TXDR_OFFSET) #endif -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* Control register 1 */ @@ -85,6 +85,7 @@ #define I2C_CR1_DNF_MASK (15 << I2C_CR1_DNF_SHIFT) # define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT) # define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */ + #define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */ #define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */ #define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */ @@ -138,6 +139,7 @@ # define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */ # define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */ # define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */ + #define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */ /* Timing register */ @@ -175,6 +177,7 @@ #define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */ /* Interrupt and Status register and interrupt clear register */ + /* Common interrupt bits */ #define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h index b829df1e08d..4be76b2e40d 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,16 +16,16 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H #define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */ #define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */ @@ -51,7 +51,7 @@ #define STM32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */ #define STM32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_RTC_TR (STM32_RTC_BASE + STM32_RTC_TR_OFFSET) #define STM32_RTC_DR (STM32_RTC_BASE + STM32_RTC_DR_OFFSET) @@ -79,7 +79,7 @@ #define STM32_RTC_BKCOUNT 5 -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* RTC time register */ @@ -132,6 +132,7 @@ # define RTC_CR_WUCKSEL_RTCDIV2 (3 << RTC_CR_WUCKSEL_SHIFT) /* 011: RTC/2 clock is selected */ # define RTC_CR_WUCKSEL_CKSPRE (4 << RTC_CR_WUCKSEL_SHIFT) /* 10x: ck_spre clock is selected */ # define RTC_CR_WUCKSEL_CKSPREADD (6 << RTC_CR_WUCKSEL_SHIFT) /* 11x: ck_spr clock and 216 added WUT counter */ + #define RTC_CR_TSEDGE (1 << 3) /* Bit 3: Timestamp event active edge */ #define RTC_CR_REFCKON (1 << 4) /* Bit 4: Reference clock detection enable (50 or 60 Hz) */ #define RTC_CR_BYPSHAD (1 << 5) /* Bit 5: Bypass the shadow registers */ @@ -153,6 +154,7 @@ # define RTC_CR_OSEL_ALRMA (1 << RTC_CR_OSEL_SHIFT) /* 01: Alarm A output enabled */ # define RTC_CR_OSEL_ALRMB (2 << RTC_CR_OSEL_SHIFT) /* 10: Alarm B output enabled */ # define RTC_CR_OSEL_WUT (3 << RTC_CR_OSEL_SHIFT) /* 11: Wakeup output enabled */ + #define RTC_CR_COE (1 << 23) /* Bit 23: Calibration output enable */ /* RTC initialization and status register */ @@ -272,7 +274,7 @@ #define RTC_TAFCR_TAMP3E (1 << 5) /* Bit 5: RTC_TAMP3 detection enable */ #define RTC_TAFCR_TAMP3TRG (1 << 6) /* Bit 6: Active level for RTC_TAMP3 input */ #define RTC_TAFCR_TAMPTS (1 << 7) /* Bit 7: Activate timestamp on tamper detection event */ -#define RTC_TAFCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */ +#define RTC_TAFCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */ #define RTC_TAFCR_TAMPFREQ_MASK (7 << RTC_TAFCR_TAMPFREQ_SHIFT) # define RTC_TAFCR_TAMPFREQ_DIV32768 (0 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 32768 (1 Hz) */ # define RTC_TAFCR_TAMPFREQ_DIV16384 (1 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 16384 (2 Hz) */ @@ -282,6 +284,7 @@ # define RTC_TAFCR_TAMPFREQ_DIV1024 (5 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 1024 (32 Hz) */ # define RTC_TAFCR_TAMPFREQ_DIV512 (6 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 512 (64 Hz) */ # define RTC_TAFCR_TAMPFREQ_DIV256 (7 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 256 (128 Hz) */ + #define RTC_TAFCR_TAMPFLT_SHIFT (11) /* Bits 11-12: RTC_TAMPx filter count */ #define RTC_TAFCR_TAMPFLT_MASK (3 << RTC_TAFCR_TAMPFLT_SHIFT) #define RTC_TAFCR_TAMPPRCH_SHIFT (13) /* Bits 13-14: RTC_TAMPx precharge duration */ @@ -290,6 +293,7 @@ # define RTC_TAFCR_TAMPPRCH_2CYCLES (1 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 2 RTCCLK cycles */ # define RTC_TAFCR_TAMPPRCH_4CYCLES (2 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 4 RTCCLK cycles */ # define RTC_TAFCR_TAMPPRCH_5CYCLES (3 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 8 RTCCLK cycles */ + #define RTC_TAFCR_TAMPPUDIS (1 << 15) /* Bit 15: RTC_TAMPx pull-up disable */ #define RTC_TAFCR_PC13VALUE (1 << 18) /* Bit 18: RTC_ALARM output type/PC13 value */ #define RTC_TAFCR_PC13MODE (1 << 19) /* Bit 19: PC13 mode */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h index 5c8ab9ce730..1b02d36efff 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_UART_V1_H #define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_UART_V1_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ #define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ @@ -46,7 +46,7 @@ #define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */ #define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) @@ -118,7 +118,7 @@ # define STM32_USART5_TDR (STM32_USART5_BASE + STM32_USART_TDR_OFFSET) #endif -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* Control register 1 */ @@ -216,6 +216,7 @@ #define USART_CR3_WUS_ADDRESS (0 << USART_CR3_WUS_SHIFT) /* 00: WUF active on address match */ #define USART_CR3_WUS_START (2 << USART_CR3_WUS_SHIFT) /* 10: WUF active on Start bit detection */ #define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* 11: WUF active on RXNE */ + #define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */ /* Baud Rate Register */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h index 0169a2bb41b..1521ccaf9de 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H #define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */ #define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */ @@ -45,7 +45,7 @@ #define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */ #define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_IWDG_KR (STM32_IWDG_BASE + STM32_IWDG_KR_OFFSET) #define STM32_IWDG_PR (STM32_IWDG_BASE + STM32_IWDG_PR_OFFSET) @@ -57,7 +57,7 @@ #define STM32_WWDG_CFR (STM32_WWDG_BASE + STM32_WWDG_CFR_OFFSET) #define STM32_WWDG_SR (STM32_WWDG_BASE + STM32_WWDG_SR_OFFSET) -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* Key register (32-bit) */ @@ -117,6 +117,7 @@ # define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */ # define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */ # define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */ + #define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */ /* Status register (32-bit) */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h index c852cbcd90e..8fa84ef38fd 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,16 +16,16 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F03X_MEMORYMAP_H #define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F03X_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* ST32F05XF07X Address Blocks ******************************************************/ +/* ST32F05XF07X Address Blocks **********************************************/ #define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ #define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ @@ -36,7 +36,7 @@ #define STM32_REGION_MASK 0xf0000000 #define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) -/* Code Base Addresses **************************************************************/ +/* Code Base Addresses ******************************************************/ #define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ /* 0x00100000-0x07ffffff: Reserved */ @@ -49,7 +49,7 @@ #define STM32_OPTION_BASE 0x1ffff800 /* 0x1fffc000-0x1fffc007: Option bytes */ /* 0x1fffc008-0x1fffffff: Reserved */ -/* System Memory Addresses **********************************************************/ +/* System Memory Addresses **************************************************/ #define STM32_SYSMEM_UID 0x1ffff7ac /* The 96-bit unique device identifier */ #define STM32_SYSMEM_FSIZE 0x1ffff7cc /* This bitfield indicates the size of @@ -58,7 +58,7 @@ * to 64 Kbytes */ -/* Peripheral Base Addresses ********************************************************/ +/* Peripheral Base Addresses ************************************************/ #define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40009fff: APB1 */ /* 0x4000a000-0x4000ffff: Reserved */ @@ -70,9 +70,10 @@ /* 0x48001800-0x4fffFfff: Reserved */ #define STM32_AHB3_BASE 0x50000000 /* 0x50000000-0x500007ff: AHB3 */ -/* APB1 Base Addresses **************************************************************/ +/* APB1 Base Addresses ******************************************************/ + +/* 0x40000000-0x400003ff Reserved */ - /* 0x40000000-0x400003ff Reserved */ #define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */ #define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */ #define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */ @@ -91,7 +92,7 @@ #define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */ /* 0x40007400-0x400077ff Reserved */ -/* APB2 Base Addresses **************************************************************/ +/* APB2 Base Addresses ******************************************************/ #define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103ff SYSCFG + COMP + OPAMP */ #define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107ff EXTI */ @@ -107,7 +108,7 @@ #define STM32_TIM17_BASE 0x40014800 /* 0x40014800-0x40014bff TIM17 */ #define STM32_DBGMCU_BASE 0x40015800 /* 0x40015800-0x40015bff DBGMCU */ -/* AHB1 Base Addresses **************************************************************/ +/* AHB1 Base Addresses ******************************************************/ #define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */ /* 0x40020400-0x400207ff: Reserved */ @@ -116,7 +117,7 @@ #define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */ /* 0x40024000-0x400243ff: Reserved */ -/* AHB2 Base Addresses **************************************************************/ +/* AHB2 Base Addresses ******************************************************/ #define STM32_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */ #define STM32_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */ @@ -125,9 +126,10 @@ /* 0x48001000-0x480013ff: Reserved */ #define STM32_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */ -/* Cortex-M4 Base Addresses *********************************************************/ -/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this - * address range +/* Cortex-M4 Base Addresses *************************************************/ + +/* Other registers -- + * see armv7-m/nvic.h for standard Cortex-M4 registers in this address range */ #define STM32_SCS_BASE 0xe000e000 diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h index 16eb82c0c9b..fd64ab8db98 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,39 +16,41 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_PINMAP_H #define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "stm32_gpio.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* Alternate Pin Functions. * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. - * Drivers, however, will use the pin selection without the numeric suffix. + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. * Additional definitions are required in the board.h file. For example, if - * CAN1_RX connects vis PD0 on some board, then the following definition should - * appear in the board.h header file for that board: + * CAN1_RX connects vis PD0 on some board, then the following definition + * should appear in the board.h header file for that board: * * #define GPIO_CAN1_RX GPIO_CAN1_RX_1 * * The driver will then automatically configure PD0 as the CAN1 RX pin. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * open-drain/push-pull, and pull-up/down! Just the basics are defined for most - * pins in this file. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file. */ /* ADC 1 */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h index 958643585c1..1e5c59b3b3f 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,16 +16,16 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H #define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* ST32F05XF07X Address Blocks ******************************************************/ +/* ST32F05XF07X Address Blocks **********************************************/ #define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ #define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ @@ -36,7 +36,7 @@ #define STM32_REGION_MASK 0xf0000000 #define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) -/* Code Base Addresses **************************************************************/ +/* Code Base Addresses ******************************************************/ #define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ /* 0x00100000-0x07ffffff: Reserved */ @@ -49,7 +49,7 @@ #define STM32_OPTION_BASE 0x1ffff800 /* 0x1fffc000-0x1fffc007: Option bytes */ /* 0x1fffc008-0x1fffffff: Reserved */ -/* System Memory Addresses **********************************************************/ +/* System Memory Addresses **************************************************/ #define STM32_SYSMEM_UID 0x1ffff7ac /* The 96-bit unique device identifier */ #define STM32_SYSMEM_FSIZE 0x1ffff7cc /* This bitfield indicates the size of @@ -58,7 +58,7 @@ * to 64 Kbytes */ -/* Peripheral Base Addresses ********************************************************/ +/* Peripheral Base Addresses ************************************************/ #define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40009fff: APB1 */ /* 0x4000a000-0x4000ffff: Reserved */ @@ -70,7 +70,7 @@ /* 0x48001800-0x4fffFfff: Reserved */ #define STM32_AHB3_BASE 0x50000000 /* 0x50000000-0x500007ff: AHB3 */ -/* APB1 Base Addresses **************************************************************/ +/* APB1 Base Addresses ******************************************************/ #define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff TIM2 */ #define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */ @@ -96,7 +96,7 @@ #define STM32_DAC1_BASE 0x40007400 /* 0x40007400-0x400077ff DAC 1 */ #define STM32_CEC_BASE 0x40007800 /* 0x40007800-0x40007bff HDMI CEC */ -/* APB2 Base Addresses **************************************************************/ +/* APB2 Base Addresses ******************************************************/ #define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103ff SYSCFG + COMP + OPAMP */ #define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107ff EXTI */ @@ -112,7 +112,7 @@ #define STM32_TIM17_BASE 0x40014800 /* 0x40014800-0x40014bff TIM17 */ #define STM32_DBGMCU_BASE 0x40015800 /* 0x40015800-0x40015bff DBGMCU */ -/* AHB1 Base Addresses **************************************************************/ +/* AHB1 Base Addresses ******************************************************/ #define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */ #define STM32_DMA2_BASE 0x40020400 /* 0x40020400-0x400207ff: DMA2 */ @@ -121,7 +121,7 @@ #define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */ #define STM32_TSC_BASE 0x40024000 /* 0x40024000-0x400243ff: TSC */ -/* AHB2 Base Addresses **************************************************************/ +/* AHB2 Base Addresses ******************************************************/ #define STM32_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */ #define STM32_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */ @@ -130,9 +130,10 @@ #define STM32_GPIOE_BASE 0x48001000 /* 0x48001000-0x480013ff: GPIO Port E */ #define STM32_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */ -/* Cortex-M4 Base Addresses *********************************************************/ -/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this - * address range +/* Cortex-M4 Base Addresses *************************************************/ + +/* Other registers -- + * see armv7-m/nvic.h for standard Cortex-M4 registers in this address range */ #define STM32_SCS_BASE 0xe000e000 diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h index 8c22034abff..298ca8acd75 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,39 +16,41 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H #define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "stm32_gpio.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* Alternate Pin Functions. * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. - * Drivers, however, will use the pin selection without the numeric suffix. + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. * Additional definitions are required in the board.h file. For example, if - * CAN1_RX connects vis PD0 on some board, then the following definition should - * appear in the board.h header file for that board: + * CAN1_RX connects vis PD0 on some board, then the following definition + * should appear in the board.h header file for that board: * * #define GPIO_CAN1_RX GPIO_CAN1_RX_1 * * The driver will then automatically configure PD0 as the CAN1 RX pin. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * open-drain/push-pull, and pull-up/down! Just the basics are defined for most - * pins in this file. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file. */ /* ADC 1 */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h index d3ce2c5b737..9d620b5ee71 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,39 +16,40 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H #define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "stm32_gpio.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* Alternate Pin Functions. * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. - * Drivers, however, will use the pin selection without the numeric suffix. - * Additional definitions are required in the board.h file. For example, if - * CAN1_RX connects vis PD0 on some board, then the following definition should - * appear in the board.h header file for that board: + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. For + * example, if CAN1_RX connects vis PD0 on some board, then the following + * definition should appear in the board.h header file for that board: * * #define GPIO_CAN1_RX GPIO_CAN1_RX_1 * * The driver will then automatically configure PD0 as the CAN1 RX pin. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * open-drain/push-pull, and pull-up/down! Just the basics are defined for most - * pins in this file. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! + * Just the basics are defined for most pins in this file. */ /* ADC 1 */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h index a4e6371798f..72185c11614 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,28 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H #define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #define STM32_NEXTI 31 #define STM32_EXTI_MASK 0xffffffff #define STM32_EXTI_BIT(n) (1 << (n)) -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */ #define STM32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */ @@ -46,7 +46,7 @@ #define STM32_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */ #define STM32_EXTI_PR_OFFSET 0x0014 /* Pending register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_EXTI_IMR (STM32_EXTI_BASE + STM32_EXTI_IMR_OFFSET) #define STM32_EXTI_EMR (STM32_EXTI_BASE + STM32_EXTI_EMR_OFFSET) @@ -55,7 +55,7 @@ #define STM32_EXTI_SWIER (STM32_EXTI_BASE + STM32_EXTI_SWIER_OFFSET) #define STM32_EXTI_PR (STM32_EXTI_BASE + STM32_EXTI_PR_OFFSET) -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* EXTI lines > 15 are associated with internal devices: */ @@ -79,13 +79,13 @@ /* Interrupt mask register */ #define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Interrupt request from line x is not masked */ -#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */ +#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */ #define EXTI_IMR_MASK STM32_EXTI_MASK /* Event mask register */ #define EXTI_EMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Event request from line x is not mask */ -#define EXTI_EMR_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */ +#define EXTI_EMR_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */ #define EXTI_EMR_MASK STM32_EXTI_MASK /* Rising Trigger selection register */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h index 07a82d345eb..4561fb8135a 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,36 +16,36 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H #define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #undef HAVE_PWR_WKUP2 #undef HAVE_PWR_WKUP3 -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_PWR_CR_OFFSET 0x0000 /* Power control register */ #define STM32_PWR_CSR_OFFSET 0x0004 /* Power control/status register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_PWR_CR (STM32_PWR_BASE + STM32_PWR_CR_OFFSET) #define STM32_PWR_CSR (STM32_PWR_BASE + STM32_PWR_CSR_OFFSET) -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* Power control register */ @@ -64,6 +64,7 @@ # define PWR_CR_2p7V (5 << PWR_CR_PLS_SHIFT) /* 101: 2.7V */ # define PWR_CR_2p8V (6 << PWR_CR_PLS_SHIFT) /* 110: 2.8V */ # define PWR_CR_2p9V (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */ + #define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ /* Power control/status register */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h index 6a58a3542dc..69328307202 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,16 +16,16 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H #define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ #define STM32_RCC_CFGR_OFFSET 0x0004 /* Clock configuration register */ @@ -42,7 +42,7 @@ #define STM32_RCC_CFGR3_OFFSET 0x0030 /* Clock configuration register 3 */ #define STM32_RCC_CR2_OFFSET 0x0034 /* Clock control register 2 */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) #define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) @@ -59,7 +59,7 @@ #define STM32_RCC_CFGR3 (STM32_RCC_BASE+STM32_RCC_CFGR3_OFFSET) #define STM32_RCC_CR2 (STM32_RCC_BASE+STM32_RCC_CR2_OFFSET) -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* Clock control register */ @@ -84,23 +84,26 @@ # define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */ # define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */ # define RCC_CFGR_SW_HSI48 (3 << RCC_CFGR_SW_SHIFT) /* 11: HSI48 selected as system clock */ + #define RCC_CFGR_SWS_SHIFT (2) /* Bits 3-2: System Clock Switch Status */ #define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT) # define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */ # define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */ # define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */ # define RCC_CFGR_SWS_HSI48 (3 << RCC_CFGR_SWS_SHIFT) /* 11: HSI48 used as system clock */ + #define RCC_CFGR_HPRE_SHIFT (4) /* Bits 7-4: AHB prescaler */ #define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT) -# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ -# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ -# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ +# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ +# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ +# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ # define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */ # define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */ # define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */ # define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */ # define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */ # define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */ + #define RCC_CFGR_PPRE1_SHIFT (8) /* Bits 10-8: APB Low speed prescaler (APB1) */ #define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT) # define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */ @@ -108,7 +111,11 @@ # define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */ # define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */ # define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */ - /* Bits 13-11: Reserve. Keep the reset value */ + + /* Bits 13-11: Reserve. + * Keep the reset value + */ + #define RCC_CFGR_ADCPRE (1 << 14) /* Bit 14: ADC prescaler, Obsolete use ADC_CFGR2 */ #define RCC_CFGR_PLLSRC_SHIFT (15) /* Bit 15: PLL input clock source */ #define RCC_CFGR_PLLSRC_MASK (3 << RCC_CFGR_PLLSRC_SHIFT) @@ -116,6 +123,7 @@ # define RCC_CFGR_PLLSRC_HS1_PREDIV (1 << RCC_CFGR_PLLSRC_SHIFT) /* 01: HSE/PREDIV as PLL input clock */ # define RCC_CFGR_PLLSRC_HSE_PREDIV (2 << RCC_CFGR_PLLSRC_SHIFT) /* 10: HSE/PREDIV as PLL input clock */ # define RCC_CFGR_PLLSRC_HSI48_PREDIV (3 << RCC_CFGR_PLLSRC_SHIFT) /* 11: HSI48/PREDIV as PLL input clock */ + #define RCC_CFGR_PLLXTPRE_MASK (1 << 17) /* Bit 17: HSE divider for PLL entry */ # define RCC_CFGR_PLLXTPRE_DIV1 (0 << 17) /* 0=No divistion */ # define RCC_CFGR_PLLXTPRE_DIV2 (1 << 17) /* 1=Divide by two */ @@ -136,7 +144,9 @@ # define RCC_CFGR_PLLMUL_CLKx14 (12 << RCC_CFGR_PLLMUL_SHIFT) /* 1100: PLL input clock x 14 */ # define RCC_CFGR_PLLMUL_CLKx15 (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1101: PLL input clock x 15 */ # define RCC_CFGR_PLLMUL_CLKx16 (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */ + /* Bit 22-23: Reserved */ + #define RCC_CFGR_MCO_SHIFT (24) /* Bits 27-24: Microcontroller Clock Output */ #define RCC_CFGR_MCO_MASK (15 << RCC_CFGR_MCO_SHIFT) # define RCC_CFGR_NOCLK (0 << RCC_CFGR_MCO_SHIFT) /* 0000: No clock */ @@ -161,7 +171,6 @@ # define RCC_CFGR_MCOPRE_DIV64 (6 << RCC_CFGR_MCOPRE_SHIFT) /* 110: MCO is divided by 64 */ # define RCC_CFGR_MCOPRE_DIV128 (7 << RCC_CFGR_MCOPRE_SHIFT) /* 111: MCO is divided by 128 */ - /* Clock interrupt register */ #define RCC_CIR_LSIRDYF (1 << 0) /* Bit 0: LSI Ready Interrupt flag */ @@ -289,6 +298,7 @@ # define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ # define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ # define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */ + #define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ #define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */ @@ -345,6 +355,7 @@ # define RCC_CFGR3_USART1SW_SYSCLK (1 << RCC_CFGR3_USART1SW_SHIFT) /* SYSCLK is USART1 clock */ # define RCC_CFGR3_USART1SW_LSE (2 << RCC_CFGR3_USART1SW_SHIFT) /* LSE is USART1 clock */ # define RCC_CFGR3_USART1SW_HSI (3 << RCC_CFGR3_USART1SW_SHIFT) /* HSI is USART1 clock */ + #define RCC_CFGR3_CECSW (1 << 6) /* Bit 6: HDMI CEC clock source selection */ #define RCC_CFGR3_USBSW (1 << 7) /* Bit 7: USB clock source selection */ #define RCC_CFGR3_CLK48_HSI48 0 @@ -356,6 +367,7 @@ # define RCC_CFGR3_USART2SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT) /* SYSCLK is USART2 clock */ # define RCC_CFGR3_USART2SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT) /* LSE is USART2 clock */ # define RCC_CFGR3_USART2SW_HSI (3 << RCC_CFGR3_USART2SW_SHIFT) /* HSI is USART2 clock */ + #define RCC_CFGR3_USART3SW_SHIFT (18) /* Bits 18-19: USART3 clock source selection */ #define RCC_CFGR3_USART3SW_MASK (3 << RCC_CFGR3_USART3SW_SHIFT) # define RCC_CFGR3_USART3SW_PCLK (0 << RCC_CFGR3_USART3SW_SHIFT) /* PCLK is USART3 clock source */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h index 89e886827a6..89f18b46968 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,26 +16,28 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H #define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_SYSCFG_CFGR1_OFFSET 0x0000 /* SYSCFG configuration register 1 */ + #define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ + #define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ #define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ #define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ @@ -73,7 +75,7 @@ #define STM32_SYSCFG_ITLINE29_OFFSET 0x00f4 /* SYSCFG interrupt line 29 status register (STM32F09x) */ #define STM32_SYSCFG_ITLINE30_OFFSET 0x00f8 /* SYSCFG interrupt line 30 status register (STM32F09x) */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET) @@ -117,7 +119,7 @@ #define STM32_SYSCFG_ITLINE29 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE29_OFFSET) #define STM32_SYSCFG_ITLINE30 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE30_OFFSET) -/* Register Bitfield Definitions ********************************************************************/ +/* Register Bitfield Definitions ********************************************/ /* SYSCFG memory remap register */ @@ -126,12 +128,14 @@ # define SYSCFG_CFGR1_MEMMODE_FLASH (0 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 00: Main Flash at 0x00000000 */ # define SYSCFG_CFGR1_MEMMODE_SYSTEM (1 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 01: System Flash at 0x00000000 */ # define SYSCFG_CFGR1_MEMMODE_SRAM (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 11: Embedded SRAM at 0x00000000 */ + #define SYSCFG_CFGR1_PA11_PA12_RMP (1 << 4) /* Bit 4: PA11 and PA12 remapping bit for small packages */ #define SYSCFG_CFGR1_IRMOD_SHIFT (6) /* Bits 6-7: IR Modulation Envelope signal selection */ #define SYSCFG_CFGR1_IRMOD_MASK (3 << SYSCFG_CFGR1_IRMOD_SHIFT) # define SYSCFG_CFGR1_IRMOD_TIM16 (0 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 00: TIM16 selected */ # define SYSCFG_CFGR1_IRMOD_USART1 (1 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 01: USART1 selected */ # define SYSCFG_CFGR1_IRMOD_USART4 (2 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 10: USART1 selected */ + #define SYSCFG_CFGR1_ADC_DMARMP (1 << 8) /* Bit 8: ADC DMA remapping bit. Only STM32F03x/F04x/F05x/F07x */ #define SYSCFG_CFGR1_USART1_TXDMARMP (1 << 9) /* Bit 9: USART1_TX_DMA request remapping bit. Only STM32F03x/F04x/F05x/F07x */ #define SYSCFG_CFGR1_USART1_RXDMARMP (1 << 10) /* Bit 10: USART1_TX_DMA request remapping bit. Only STM32F03x/F04x/F05x/F07x */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_gpio.c b/arch/arm/src/stm32f0l0g0/stm32_gpio.c index dbf3c44e624..bb9fe52b586 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_gpio.c +++ b/arch/arm/src/stm32f0l0g0/stm32_gpio.c @@ -47,6 +47,7 @@ /**************************************************************************** * Public Data ****************************************************************************/ + /* Base addresses for each GPIO block */ const uint32_t g_gpiobase[STM32_NPORTS] = @@ -58,7 +59,7 @@ const uint32_t g_gpiobase[STM32_NPORTS] = STM32_GPIOB_BASE, /* Two GPIO ports, GPIOA-B */ #endif #if STM32_NPORTS > 2 - STM32_GPIOC_BASE, /* Three GPIO ports, GPIOA-C*/ + STM32_GPIOC_BASE, /* Three GPIO ports, GPIOA-C */ #endif #if STM32_NPORTS > 3 STM32_GPIOD_BASE, /* Four GPIO ports, GPIOA-D */ @@ -154,7 +155,8 @@ int stm32_configgpio(uint32_t cfgset) break; case GPIO_OUTPUT: /* General purpose output mode */ - stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */ + stm32_gpiowrite(cfgset, + (cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */ pinmode = GPIO_MODER_OUTPUT; break; @@ -298,7 +300,9 @@ int stm32_configgpio(uint32_t cfgset) putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); - /* Otherwise, it is an input pin. Should it configured as an EXTI interrupt? */ + /* Otherwise, it is an input pin. + * Should it configured as an EXTI interrupt? + */ if ((cfgset & GPIO_EXTI) != 0) { @@ -338,14 +342,15 @@ int stm32_configgpio(uint32_t cfgset) * Name: stm32_unconfiggpio * * Description: - * Unconfigure a GPIO pin based on bit-encoded description of the pin, set it - * into default HiZ state (and possibly mark it's unused) and unlock it whether - * it was previsouly selected as alternative function (GPIO_ALT|GPIO_CNF_AFPP|...). + * Unconfigure a GPIO pin based on bit-encoded description of the pin, set + * it into default HiZ state (and possibly mark it's unused) and unlock it + * whether it was previsouly selected as alternative function + * (GPIO_ALT|GPIO_CNF_AFPP|...). * - * This is a safety function and prevents hardware from schocks, as unexpected - * write to the Timer Channel Output GPIO to fixed '1' or '0' while it should - * operate in PWM mode could produce excessive on-board currents and trigger - * over-current/alarm function. + * This is a safety function and prevents hardware from schocks, as + * unexpected write to the Timer Channel Output GPIO to fixed '1' or '0' + * while it should operate in PWM mode could produce excessive on-board + * currents and trigger over-current/alarm function. * * Returned Value: * OK on success @@ -404,7 +409,6 @@ void stm32_gpiowrite(uint32_t pinset, bool value) } putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); - } } diff --git a/arch/arm/src/stm32f0l0g0/stm32_hsi48.h b/arch/arm/src/stm32f0l0g0/stm32_hsi48.h index 66a7fa7fb11..1631ad239d7 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_hsi48.h +++ b/arch/arm/src/stm32f0l0g0/stm32_hsi48.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f0l0g0/stm32_hsi48.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H #define __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #ifdef CONFIG_STM32F0L0G0_HAVE_HSI48 -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ enum syncsrc_e { @@ -41,9 +41,9 @@ enum syncsrc_e SYNCSRC_USB, /* USB SOF selected as SYNC signal source */ }; -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ /**************************************************************************** * Name: stm32_enable_hsi48 diff --git a/arch/arm/src/stm32f0l0g0/stm32_irq.c b/arch/arm/src/stm32f0l0g0/stm32_irq.c index e8af818dd64..e522271e54e 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_irq.c +++ b/arch/arm/src/stm32f0l0g0/stm32_irq.c @@ -35,7 +35,7 @@ #include "arm_arch.h" #include "arm_internal.h" -//#include "stm32_irq.h" +/* #include "stm32_irq.h" */ /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c b/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c index c089d8db63b..3b3b01f82eb 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c +++ b/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c @@ -199,7 +199,7 @@ # define STM32_USARTDIV16 \ ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) - /* Use oversamply by 8 only if the divisor is small. But what is small? */ +/* Use oversamply by 8 only if the divisor is small. But what is small? */ # if STM32_USARTDIV8 > 100 # define STM32_BRR_VALUE STM32_USARTDIV16 @@ -228,9 +228,11 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & + USART_ISR_TXE) == 0); #ifdef STM32_CONSOLE_RS485_DIR - stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ @@ -238,8 +240,10 @@ void arm_lowputc(char ch) putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); #ifdef STM32_CONSOLE_RS485_DIR - while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & + USART_ISR_TC) == 0); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial.c b/arch/arm/src/stm32f0l0g0/stm32_serial.c index 344cd8e738c..99ef5f78141 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial.c +++ b/arch/arm/src/stm32f0l0g0/stm32_serial.c @@ -25,10 +25,6 @@ #include #include "chip.h" -/**************************************************************************** - * Public Functions - ****************************************************************************/ - /* This file is only a thin shell that includes the correct serial * implementation for the selected STM32 IP core: * - STM32 UART IP version 1 - F0, L0 @@ -42,3 +38,7 @@ #else # error "Unsupported STM32 M0 serial" #endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/stm32f0l0g0/stm32_timerisr.c b/arch/arm/src/stm32f0l0g0/stm32_timerisr.c index 0551e5dc8fa..17630f6e0dc 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_timerisr.c +++ b/arch/arm/src/stm32f0l0g0/stm32_timerisr.c @@ -137,8 +137,10 @@ void up_timer_initialize(void) */ #ifdef CONFIG_STM32F0L0G0_SYSTICK_CORECLK - putreg32((SYSTICK_CSR_CLKSOURCE | SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), - ARMV6M_SYSTICK_CSR); + putreg32((SYSTICK_CSR_CLKSOURCE | + SYSTICK_CSR_TICKINT | + SYSTICK_CSR_ENABLE), + ARMV6M_SYSTICK_CSR); #else putreg32((SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), ARMV6M_SYSTICK_CSR); #endif diff --git a/arch/arm/src/stm32f0l0g0/stm32_uart.h b/arch/arm/src/stm32f0l0g0/stm32_uart.h index 33cbefc2d0c..163c89e8ea6 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_uart.h +++ b/arch/arm/src/stm32f0l0g0/stm32_uart.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f0l0g0/stm32_uart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H #define __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,9 +31,10 @@ #include "hardware/stm32_uart.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* Make sure that we have not enabled more U[S]ARTs than are supported by the * device. */ @@ -284,7 +285,9 @@ # undef HAVE_CONSOLE #endif -/* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX configuration */ +/* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX + * configuration + */ #if !defined(HAVE_SERIALDRIVER) || !defined(CONFIG_ARCH_DMA) # undef CONFIG_USART1_RXDMA @@ -398,13 +401,13 @@ # define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE) #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -417,22 +420,22 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: stm32_serial_dma_poll * * Description: - * Must be called periodically if any STM32 USART is configured for DMA. The DMA - * callback is triggered for each fifo size/2 bytes, but this can result in some - * bytes being transferred but not collected if the incoming data is not a whole - * multiple of half the FIFO size. + * Must be called periodically if any STM32 USART is configured for DMA. + * The DMA callback is triggered for each fifo size/2 bytes, but this can + * result in some bytes being transferred but not collected if the incoming + * data is not a whole multiple of half the FIFO size. * * May be safely called from either interrupt or thread context. * - ************************************************************************************/ + ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA void stm32_serial_dma_poll(void); diff --git a/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c index 2d56a86809d..6c41d10ebfa 100644 --- a/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c +++ b/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c @@ -79,10 +79,11 @@ static inline void rcc_enableio(void) uint32_t regval = 0; /* Enable basic peripheral support */ + /* Enable all GPIO modules */ regval = getreg32(STM32_RCC_AHBENR); - regval |= RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPBEN | RCC_AHBENR_IOPCEN |\ + regval |= RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPBEN | RCC_AHBENR_IOPCEN | RCC_AHBENR_IOPDEN | RCC_AHBENR_IOPEEN | RCC_AHBENR_IOPFEN; putreg32(regval, STM32_RCC_AHBENR); } @@ -432,7 +433,8 @@ static void stm32_stdclockconfig(void) regval &= ~RCC_CFGR_SW_MASK; putreg32(regval, STM32_RCC_CFGR); - while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_HSI); + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + RCC_CFGR_SWS_HSI); } /* Disable the PLL */ @@ -469,8 +471,10 @@ static void stm32_stdclockconfig(void) * 3. Use multiplier from board.h */ - regval &= ~(RCC_CFGR_PLLSRC_MASK | RCC_CFGR_PLLXTPRE_MASK | RCC_CFGR_PLLMUL_MASK); - regval |= (RCC_CFGR_PLLSRC_HSId2 | RCC_CFGR_PLLXTPRE_DIV1 | STM32_CFGR_PLLMUL); + regval &= ~(RCC_CFGR_PLLSRC_MASK | RCC_CFGR_PLLXTPRE_MASK | + RCC_CFGR_PLLMUL_MASK); + regval |= (RCC_CFGR_PLLSRC_HSId2 | RCC_CFGR_PLLXTPRE_DIV1 | + STM32_CFGR_PLLMUL); putreg32(regval, STM32_RCC_CFGR); /* Enable the PLL */ diff --git a/arch/arm/src/stm32f7/hardware/stm32_ethernet.h b/arch/arm/src/stm32f7/hardware/stm32_ethernet.h index 1fcb1a9e294..f477b2aeda5 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_ethernet.h +++ b/arch/arm/src/stm32f7/hardware/stm32_ethernet.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32_ethernet.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_ETHERNET_H #define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_ETHERNET_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include @@ -34,10 +34,12 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ -/* Register Offsets *********************************************************************************/ + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + /* MAC Registers */ #define STM32_ETH_MACCR_OFFSET 0x0000 /* Ethernet MAC configuration register */ @@ -106,7 +108,8 @@ #define STM32_ETH_DMACHTBAR_OFFSET 0x1050 /* Ethernet DMA current host transmit buffer address register */ #define STM32_ETH_DMACHRBAR_OFFSET 0x1054 /* Ethernet DMA current host receive buffer address register */ -/* Register Base Addresses **************************************************************************/ +/* Register Base Addresses **************************************************/ + /* MAC Registers */ #define STM32_ETH_MACCR (STM32_ETHMAC_BASE+STM32_ETH_MACCR_OFFSET) @@ -175,7 +178,8 @@ #define STM32_ETH_DMACHTBAR (STM32_ETHMAC_BASE+STM32_ETH_DMACHTBAR_OFFSET) #define STM32_ETH_DMACHRBAR (STM32_ETHMAC_BASE+STM32_ETH_DMACHRBAR_OFFSET) -/* Register Bit-Field Definitions *******************************************************************/ +/* Register Bit-Field Definitions *******************************************/ + /* MAC Registers */ /* Ethernet MAC configuration register */ @@ -189,6 +193,7 @@ # define ETH_MACCR_BL_8 (1 << ETH_MACCR_BL_SHIFT) /* 01: k = min (n, 8) */ # define ETH_MACCR_BL_4 (2 << ETH_MACCR_BL_SHIFT) /* 10: k = min (n, 4) */ # define ETH_MACCR_BL_1 (3 << ETH_MACCR_BL_SHIFT) /* 11: k = min (n, 1) */ + #define ETH_MACCR_APCS (1 << 7) /* Bit 7: Automatic pad/CRC stripping */ #define ETH_MACCR_RD (1 << 9) /* Bit 9: Retry disable */ #define ETH_MACCR_IPCO (1 << 10) /* Bit 10: IPv4 checksum offload */ @@ -200,6 +205,7 @@ #define ETH_MACCR_IFG_SHIFT (17) /* Bits 17-19: Interframe gap */ #define ETH_MACCR_IFG_MASK (7 << ETH_MACCR_IFG_SHIFT) # define ETH_MACCR_IFG(n) ((12-((n) >> 3)) << ETH_MACCR_IFG_SHIFT) /* n bit times, n=40,48,..96 */ + #define ETH_MACCR_JD (1 << 22) /* Bit 22: Jabber disable */ #define ETH_MACCR_WD (1 << 23) /* Bit 23: Watchdog disable */ #define ETH_MACCR_CSTF (1 << 25) /* Bits 25: CRC stripping for Type frames */ @@ -218,6 +224,7 @@ # define ETH_MACFFR_PCF_PAUSE (1 << ETH_MACFFR_PCF_SHIFT) /* Prevents all except Pause control frames */ # define ETH_MACFFR_PCF_ALL (2 << ETH_MACFFR_PCF_SHIFT) /* Forwards all control frames */ # define ETH_MACFFR_PCF_FILTER (3 << ETH_MACFFR_PCF_SHIFT) /* Forwards all that pass address filter */ + #define ETH_MACFFR_SAIF (1 << 8) /* Bit 8: Source address inverse filtering */ #define ETH_MACFFR_SAF (1 << 9) /* Bit 9: Source address filter */ #define ETH_MACFFR_HPF (1 << 10) /* Bit 10: Hash or perfect filter */ @@ -236,6 +243,7 @@ # define ETH_MACMIIAR_CR_DIV16 (2 << ETH_MACMIIAR_CR_SHIFT) /* 20-35 MHz HCLK/16 */ # define ETH_MACMIIAR_CR_DIV26 (3 << ETH_MACMIIAR_CR_SHIFT) /* 35-60 MHz HCLK/26 */ # define ETH_MACMIIAR_CR_DIV102 (4 << ETH_MACMIIAR_CR_SHIFT) /* 150-216 MHz HCLK/102 */ + #define ETH_MACMIIAR_MR_SHIFT (6) /* Bits 6-10: MII register */ #define ETH_MACMIIAR_MR_MASK (31 << ETH_MACMIIAR_MR_SHIFT) # define ETH_MACMIIAR_MR(n) ((uint32_t)(n) << ETH_MACMIIAR_MR_SHIFT) @@ -259,6 +267,7 @@ # define ETH_MACFCR_PLT_M28 (1 << ETH_MACFCR_PLT_SHIFT) /* 01 Pause - 28 slot times */ # define ETH_MACFCR_PLT_M144 (2 << ETH_MACFCR_PLT_SHIFT) /* 10 Pause - 144 slot times */ # define ETH_MACFCR_PLT_M256 (3 << ETH_MACFCR_PLT_SHIFT) /* 11 Pause -s 256 slot times */ + #define ETH_MACFCR_ZQPD (1 << 7) /* Bit 7: Zero-quanta pause disable */ #define ETH_MACFCR_PT_SHIFT (16) /* Bits 16-31: Pause time */ #define ETH_MACFCR_PT_MASK (0xffff << ETH_MACFCR_PT_SHIFT) @@ -270,8 +279,8 @@ # define ETH_MACVLANTR_VLANTI(n) ((uint32_t)(n) << ETH_MACVLANTR_VLANTI_SHIFT) #define ETH_MACVLANTR_VLANTC (1 << 16) /* Bit 16: 12-bit VLAN tag comparison */ -/* Ethernet MAC remote wakeup frame filter reg. Provides 32-bit access to remote - * remote wake-up filters. +/* Ethernet MAC remote wakeup frame filter reg. + * Provides 32-bit access to remote remote wake-up filters. */ /* Ethernet MAC PMT control and status register */ @@ -296,12 +305,14 @@ # define ETH_MACDBGR_RFRCS_RFRAME (1 << ETH_MACDBGR_RFRCS_SHIFT) /* 01: Reading frame data */ # define ETH_MACDBGR_RFRCS_RSTATUS (2 << ETH_MACDBGR_RFRCS_SHIFT) /* 10: Reading frame status (or time-stamp) */ # define ETH_MACDBGR_RFRCS_FLUSHING (3 << ETH_MACDBGR_RFRCS_SHIFT) /* 11: Flushing the frame data and status */ + #define ETH_MACDBGR_RFFL_SHIFT (8) /* Bits 8-9: Rx FIFO fill level */ #define ETH_MACDBGR_RFFL_MASK (3 << ETH_MACDBGR_RFFL_SHIFT) # define ETH_MACDBGR_RFFL_EMPTY (0 << ETH_MACDBGR_RFFL_SHIFT) /* 00: RxFIFO empty */ # define ETH_MACDBGR_RFFL_DEACT (1 << ETH_MACDBGR_RFFL_SHIFT) /* 01: RxFIFO fill-level below flow-control de-activate threshold */ # define ETH_MACDBGR_RFFL_ACTIV (2 << ETH_MACDBGR_RFFL_SHIFT) /* 10: RxFIFO fill-level above flow-control activate threshold */ # define ETH_MACDBGR_RFFL_FULL (3 << ETH_MACDBGR_RFFL_SHIFT) /* 11: RxFIFO full */ + #define ETH_MACDBGR_MMTEA (1 << 16) /* Bit 16: MAC MII transmit engine active */ #define ETH_MACDBGR_MTFCS_SHIFT (17) /* Bits 17-18: MAC transmit frame controller status */ #define ETH_MACDBGR_MTFCS_MASK (3 << ETH_MACDBGR_MTFCS_SHIFT) @@ -309,6 +320,7 @@ # define ETH_MACDBGR_MTFCS_WAITING (1 << ETH_MACDBGR_MTFCS_SHIFT) /* 01: Waiting for Status of previous frame or IFG/backoff period to be over */ # define ETH_MACDBGR_MTFCS_PAUSE (2 << ETH_MACDBGR_MTFCS_SHIFT) /* 10: Generating and transmitting a Pause control frame */ # define ETH_MACDBGR_MTFCS_FRAME (3 << ETH_MACDBGR_MTFCS_SHIFT) /* 11: Transferring input frame for transmission */ + #define ETH_MACDBGR_MTP (1 << 19) /* Bit 19: MAC transmitter in pause */ #define ETH_MACDBGR_TFRS_SHIFT (20) /* Bits 20-21: Tx FIFO read status */ #define ETH_MACDBGR_TFRS_MASK (3 << ETH_MACDBGR_TFRS_SHIFT) @@ -316,6 +328,7 @@ # define ETH_MACDBGR_TFRS_READ (1 << ETH_MACDBGR_TFRS_SHIFT) /* 01: Read state */ # define ETH_MACDBGR_TFRS_WAITING (2 << ETH_MACDBGR_TFRS_SHIFT) /* 10: Waiting for TxStatus from MAC transmitter */ # define ETH_MACDBGR_TFRS_WRITING (3 << ETH_MACDBGR_TFRS_SHIFT) /* 11: Writing the received TxStatus or flushing the TxFIFO */ + #define ETH_MACDBGR_TFWA (1 << 22) /* Bit 22: Tx FIFO write active */ #define ETH_MACDBGR_TFNE (1 << 24) /* Bit 24: Tx FIFO not empty */ #define ETH_MACDBGR_TFF (1 << 25) /* Bit 25: Tx FIFO full */ @@ -356,6 +369,7 @@ # define ETH_MACA1HR_MBC_16_23 (0x04 << ETH_MACA1HR_MBC_SHIFT) /* Bit 26: ETH_MACA1LR [16-23] */ # define ETH_MACA1HR_MBC_8_15 (0x02 << ETH_MACA1HR_MBC_SHIFT) /* Bit 25: ETH_MACA1LR [8-15] */ # define ETH_MACA1HR_MBC_0_7 (0x01 << ETH_MACA1HR_MBC_SHIFT) /* Bit 24: ETH_MACA1LR [0-7] */ + #define ETH_MACA1HR_SA (1 << 30) /* Bit 30: Source address */ #define ETH_MACA1HR_AE (1 << 31) /* Bit 31: Address enable */ @@ -374,6 +388,7 @@ # define ETH_MACA2HR_MBC_16_23 (0x04 << ETH_MACA2HR_MBC_SHIFT) /* Bit 26: ETH_MACA2LR [16-23] */ # define ETH_MACA2HR_MBC_8_15 (0x02 << ETH_MACA2HR_MBC_SHIFT) /* Bit 25: ETH_MACA2LR [8-15] */ # define ETH_MACA2HR_MBC_0_7 (0x01 << ETH_MACA2HR_MBC_SHIFT) /* Bit 24: ETH_MACA2LR [0-7] */ + #define ETH_MACA2HR_SA (1 << 30) /* Bit 30: Source address */ #define ETH_MACA2HR_AE (1 << 31) /* Bit 31: Address enable */ @@ -392,6 +407,7 @@ # define ETH_MACA3HR_MBC_16_23 (0x04 << ETH_MACA3HR_MBC_SHIFT) /* Bit 26: ETH_MACA3LR [16-23] */ # define ETH_MACA3HR_MBC_8_15 (0x02 << ETH_MACA3HR_MBC_SHIFT) /* Bit 25: ETH_MACA3LR [8-15] */ # define ETH_MACA3HR_MBC_0_7 (0x01 << ETH_MACA3HR_MBC_SHIFT) /* Bit 24: ETH_MACA3LR [0-7] */ + #define ETH_MACA3HR_SA (1 << 30) /* Bit 30: Source address */ #define ETH_MACA3HR_AE (1 << 31) /* Bit 31: Address enable */ @@ -454,6 +470,7 @@ # define ETH_PTPTSCR_TSCNT_BOUNDARY (1 << ETH_PTPTSCR_TSCNT_SHIFT) /* 01: Boundary clock */ # define ETH_PTPTSCR_TSCNT_E2E (2 << ETH_PTPTSCR_TSCNT_SHIFT) /* 10: End-to-end transparent clock */ # define ETH_PTPTSCR_TSCNT_P2P (3 << ETH_PTPTSCR_TSCNT_SHIFT) /* 11: Peer-to-peer transparent clock */ + #define ETH_PTPTSCR_TSPFFMAE (1 << 18) /* Bit 18: Time stamp PTP frame filtering MAC address enable */ /* Ethernet PTP subsecond increment register */ @@ -475,7 +492,9 @@ #define ETH_PTPTSLU_MASK (0x7fffffff) /* Bits 0-30: Time stamp update subsecond */ /* Ethernet PTP time stamp addend register (32-bit) */ + /* Ethernet PTP target time high register (32-bit) */ + /* Ethernet PTP target time low register (32-bit) */ /* Ethernet PTP time stamp status register */ @@ -496,28 +515,34 @@ #define ETH_DMABMR_PBL_SHIFT (8) /* Bits 8-13: Programmable burst length */ #define ETH_DMABMR_PBL_MASK (0x3f << ETH_DMABMR_PBL_SHIFT) # define ETH_DMABMR_PBL(n) ((n) << ETH_DMABMR_PBL_SHIFT) /* n=1, 2, 4, 8, 16, 32 */ + #define ETH_DMABMR_PM_SHIFT (14) /* Bits 14-15: Rx Tx priority ratio */ #define ETH_DMABMR_PM_MASK (3 << ETH_DMABMR_PM_SHIFT) # define ETH_DMABMR_RTPR_1TO1 (0 << ETH_DMABMR_PM_SHIFT) /* 00: 1:1 */ # define ETH_DMABMR_RTPR_2TO1 (1 << ETH_DMABMR_PM_SHIFT) /* 01: 2:1 */ # define ETH_DMABMR_RTPR_3TO1 (2 << ETH_DMABMR_PM_SHIFT) /* 10: 3:1 */ # define ETH_DMABMR_RTPR_4TO1 (3 << ETH_DMABMR_PM_SHIFT) /* 11: 4:1 */ + #define ETH_DMABMR_FB (1 << 16) /* Bit 16: Fixed burst */ #define ETH_DMABMR_RDP_SHIFT (17) /* Bits 17-22: Rx DMA PBL */ #define ETH_DMABMR_RDP_MASK (0x3f << ETH_DMABMR_RDP_SHIFT) # define ETH_DMABMR_RDP(n) ((n) << ETH_DMABMR_RDP_SHIFT) /* n=1, 2, 4, 8, 16, 32 */ + #define ETH_DMABMR_USP (1 << 23) /* Bit 23: Use separate PBL */ #define ETH_DMABMR_FPM (1 << 24) /* Bit 24: 4xPBL mode */ #define ETH_DMABMR_AAB (1 << 25) /* Bit 25: Address-aligned beats */ #define ETH_DMABMR_MB (1 << 26) /* Bit 26: Mixed burst */ /* Ethernet DMA transmit poll demand register (32-bit) */ + /* Ethernet DMA receive poll demand register (32-bit) */ + /* Ethernet DMA receive descriptor list address register (32-bit address) */ + /* Ethernet DMA transmit descriptor list address register (32-bit address) */ -/* Interrupt bit definitions common between the DMA status register (DMASR) and - * the DMA interrupt enable register (DMAIER). +/* Interrupt bit definitions common between the DMA status register (DMASR) + * and the DMA interrupt enable register (DMAIER). */ #define ETH_DMAINT_TI (1 << 0) /* Bit 0: Transmit interrupt */ @@ -546,6 +571,7 @@ # define ETH_DMASR_RPS_SUSPENDED (4 << ETH_DMASR_RPS_SHIFT) /* 100: Suspended: Receive descriptor unavailable */ # define ETH_DMASR_RPS_CLOSING (5 << ETH_DMASR_RPS_SHIFT) /* 101: Running: Closing receive descriptor */ # define ETH_DMASR_RPS_TRANSFER (7 << ETH_DMASR_RPS_SHIFT) /* 111: Running: Transferring the receive data to memory */ + #define ETH_DMASR_TPS_SHIFT (20) /* Bits 20-22: Transmit process state */ #define ETH_DMASR_TPS_MASK (7 << ETH_DMASR_TPS_SHIFT) # define ETH_DMASR_TPS_STOPPED (0 << ETH_DMASR_TPS_SHIFT) /* 000: Stopped; Reset or Stop Transmit Command issued */ @@ -554,11 +580,13 @@ # define ETH_DMASR_TPS_TRANSFER (3 << ETH_DMASR_TPS_SHIFT) /* 011: Running; Reading data and queuing to transmit (TxFIFO) */ # define ETH_DMASR_TPS_SUSPENDED (6 << ETH_DMASR_TPS_SHIFT) /* 110: Suspended; Transmit descriptor unavailable or buffer underflow */ # define ETH_DMASR_TPS_CLOSING (7 << ETH_DMASR_TPS_SHIFT) /* 111: Running; Closing transmit descriptor */ + #define ETH_DMASR_EBS_SHIFT (23) /* Bits 23-25: Error bits status */ #define ETH_DMASR_EBS_MASK (7 << ETH_DMASR_EBS_SHIFT) # define ETH_DMASR_EBS_TXDMS (1 << ETH_DMASR_EBS_SHIFT) /* Bit 23 1 Error during data transfer by TxDMA */ # define ETH_DMASR_EBS_READ (2 << ETH_DMASR_EBS_SHIFT) /* Bit 24 1 Error during read transfer */ # define ETH_DMASR_EBS_DESC (4 << ETH_DMASR_EBS_SHIFT) /* Bit 25 1 Error during descriptor access */ + #define ETH_DMASR_MMCS (1 << 27) /* Bit 27: MMC status */ #define ETH_DMASR_PMTS (1 << 28) /* Bit 28: PMT status */ #define ETH_DMASR_TSTS (1 << 29) /* Bit 29: Time stamp trigger status */ @@ -607,12 +635,24 @@ #define ETH_DMARSWTR_MASK (0xff) -/* Ethernet DMA current host transmit descriptor register (32-bit address) */ -/* Ethernet DMA current host receive descriptor register (32-bit address) */ -/* Ethernet DMA current host transmit buffer address register (32-bit address) */ -/* Ethernet DMA current host receive buffer address register (32-bit address) */ +/* Ethernet DMA current host transmit descriptor register + * (32-bit address) + */ + +/* Ethernet DMA current host receive descriptor register + * (32-bit address) + */ + +/* Ethernet DMA current host transmit buffer address register + * (32-bit address) + */ + +/* Ethernet DMA current host receive buffer address register + * (32-bit address) + */ + +/* DMA Descriptors **********************************************************/ -/* DMA Descriptors **********************************************************************************/ /* TDES0: Transmit descriptor Word0 */ #define ETH_TDES0_DB (1 << 0) /* Bit 0: Deferred bit */ @@ -640,6 +680,7 @@ # define ETH_TDES0_CIC_IH (1 << ETH_TDES0_CIC_SHIFT) /* IP header checksum enabled */ # define ETH_TDES0_CIC_IHPL (2 << ETH_TDES0_CIC_SHIFT) /* IP header and payload checksum enabled */ # define ETH_TDES0_CIC_ALL (3 << ETH_TDES0_CIC_SHIFT) /* IP Header, payload, and pseudo-header checksum enabled */ + #define ETH_TDES0_TTSE (1 << 25) /* Bit 25: Transmit time stamp enable */ #define ETH_TDES0_DP (1 << 26) /* Bit 26: Disable pad */ #define ETH_TDES0_DC (1 << 27) /* Bit 27: Disable CRC */ @@ -653,13 +694,16 @@ #define ETH_TDES1_TBS1_SHIFT (0) /* Bits 0-12: Transmit buffer 1 size */ #define ETH_TDES1_TBS1_MASK (0x1fff << ETH_TDES1_TBS1_SHIFT) # define ETH_TDES1_TBS1(n) ((uint32_t)(n) << ETH_TDES1_TBS1_SHIFT) -#define ETH_TDES1_TBS2_SHIFT (16) /* Bits 16-28: Transmit buffer 2 size */ +#define ETH_TDES1_TBS2_SHIFT (16) /* Bits 16-28: Transmit buffer 2 size */ #define ETH_TDES1_TBS2_MASK (0x1fff << ETH_TDES1_TBS2_SHIFT) # define ETH_TDES1_TBS2(n) ((uint32_t)(n) << ETH_TDES1_TBS2_SHIFT) /* TDES2: Transmit descriptor Word2 (32-bit address) */ + /* TDES3: Transmit descriptor Word3 (32-bit address) */ + /* TDES6: Transmit descriptor Word6 (32-bit time stamp) */ + /* TDES7: Transmit descriptor Word7 (32-bit time stamp) */ /* RDES0: Receive descriptor Word0 */ @@ -701,6 +745,7 @@ #define ETH_RDES1_DIC (1 << 31) /* Bit 31: Disable interrupt on completion */ /* RDES2: Receive descriptor Word2 (32-bit address) */ + /* RDES3: Receive descriptor Word3 (32-bit address) */ /* RDES4: Receive descriptor Word4 */ @@ -711,6 +756,7 @@ # define ETH_RDES4_IPPT_UDP (1 << ETH_RDES4_IPPT_SHIFT) /* UDP payload in IP datagram */ # define ETH_RDES4_IPPT_TCP (2 << ETH_RDES4_IPPT_SHIFT) /* TCP payload in IP datagram */ # define ETH_RDES4_IPPT_ICMP (3 << ETH_RDES4_IPPT_SHIFT) /* ICMP payload in IP datagram */ + #define ETH_RDES4_IPHE (1 << 3) /* Bit 3: IP header error */ #define ETH_RDES4_IPPE (1 << 4) /* Bit 4: IP payload error */ #define ETH_RDES4_IPCB (1 << 5) /* Bit 5: IP checksum bypassed */ @@ -733,16 +779,19 @@ * peer-to-peer transparent clock) or * Signaling (for ordinary or boundary * clock) */ + #define ETH_RDES4_PFT (1 << 12) /* Bit 12: PTP frame type */ #define ETH_RDES4_PV (1 << 13) /* Bit 13: PTP version */ /* RDES5: Receive descriptor Word5 - Reserved */ + /* RDES6: Receive descriptor Word6 (32-bit time stamp) */ + /* RDES7: Receive descriptor Word7 (32-bit time stamp) */ -/**************************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -786,9 +835,9 @@ struct eth_rxdesc_s #endif }; -/**************************************************************************************************** - * Public Functions - ****************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ diff --git a/arch/arm/src/stm32f7/hardware/stm32_rtcc.h b/arch/arm/src/stm32f7/hardware/stm32_rtcc.h index 505f246b558..b7beda6a56f 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_rtcc.h +++ b/arch/arm/src/stm32f7/hardware/stm32_rtcc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32_rtcc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,16 +16,16 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_RTCC_H #define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_RTCC_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */ #define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */ @@ -81,7 +81,7 @@ #define STM32_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */ #define STM32_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_RTC_TR (STM32_RTC_BASE+STM32_RTC_TR_OFFSET) #define STM32_RTC_DR (STM32_RTC_BASE+STM32_RTC_DR_OFFSET) @@ -138,7 +138,7 @@ #define STM32_RTC_BKCOUNT 32 -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* RTC time register */ @@ -191,6 +191,7 @@ # define RTC_CR_WUCKSEL_RTCDIV2 (3 << RTC_CR_WUCKSEL_SHIFT) /* 011: RTC/2 clock is selected */ # define RTC_CR_WUCKSEL_CKSPRE (4 << RTC_CR_WUCKSEL_SHIFT) /* 10x: ck_spre clock is selected */ # define RTC_CR_WUCKSEL_CKSPREADD (6 << RTC_CR_WUCKSEL_SHIFT) /* 11x: ck_spr clock and 216 added WUT counter */ + #define RTC_CR_TSEDGE (1 << 3) /* Bit 3: Timestamp event active edge */ #define RTC_CR_REFCKON (1 << 4) /* Bit 4: Reference clock detection enable (50 or 60 Hz) */ #define RTC_CR_BYPSHAD (1 << 5) /* Bit 5: Bypass the shadow registers */ @@ -214,6 +215,7 @@ # define RTC_CR_OSEL_ALRMA (1 << RTC_CR_OSEL_SHIFT) /* 01: Alarm A output enabled */ # define RTC_CR_OSEL_ALRMB (2 << RTC_CR_OSEL_SHIFT) /* 10: Alarm B output enabled */ # define RTC_CR_OSEL_WUT (3 << RTC_CR_OSEL_SHIFT) /* 11: Wakeup output enabled */ + #define RTC_CR_COE (1 << 23) /* Bit 23: Calibration output enable */ #define RTC_CR_ITSE (1 << 24) /* Bit 24: Timestamp on internal event enable */ @@ -339,7 +341,7 @@ #define RTC_TAMPCR_TAMP3E (1 << 5) /* Bit 5: RTC_TAMP3 detection enable */ #define RTC_TAMPCR_TAMP3TRG (1 << 6) /* Bit 6: Active level for RTC_TAMP3 input */ #define RTC_TAMPCR_TAMPTS (1 << 7) /* Bit 7: Activate timestamp on tamper detection event */ -#define RTC_TAMPCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */ +#define RTC_TAMPCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */ #define RTC_TAMPCR_TAMPFREQ_MASK (7 << RTC_TAMPCR_TAMPFREQ_SHIFT) # define RTC_TAMPCR_TAMPFREQ_DIV32768 (0 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 32768 (1 Hz) */ # define RTC_TAMPCR_TAMPFREQ_DIV16384 (1 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 16384 (2 Hz) */ @@ -349,6 +351,7 @@ # define RTC_TAMPCR_TAMPFREQ_DIV1024 (5 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 1024 (32 Hz) */ # define RTC_TAMPCR_TAMPFREQ_DIV512 (6 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 512 (64 Hz) */ # define RTC_TAMPCR_TAMPFREQ_DIV256 (7 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 256 (128 Hz) */ + #define RTC_TAMPCR_TAMPFLT_SHIFT (11) /* Bits 11-12: RTC_TAMPx filter count */ #define RTC_TAMPCR_TAMPFLT_MASK (3 << RTC_TAMPCR_TAMPFLT_SHIFT) #define RTC_TAMPCR_TAMPPRCH_SHIFT (13) /* Bits 13-14: RTC_TAMPx precharge duration */ @@ -357,6 +360,7 @@ # define RTC_TAMPCR_TAMPPRCH_2CYCLES (1 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 2 RTCCLK cycles */ # define RTC_TAMPCR_TAMPPRCH_4CYCLES (2 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 4 RTCCLK cycles */ # define RTC_TAMPCR_TAMPPRCH_5CYCLES (3 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 8 RTCCLK cycles */ + #define RTC_TAMPCR_TAMPPUDIS (1 << 15) /* Bit 15: RTC_TAMPx pull-up disable */ #define RTC_TAMPCR_TAMP1IE (1 << 16) /* Bit 16: Tamper 1 interrupt enable */ #define RTC_TAMPCR_TAMP1NOERASE (1 << 17) /* Bit 17: Tamper 1 no erase */ @@ -383,7 +387,7 @@ # define RTC_OR_PI8 (1 << RTC_OR_TSINSEL_SHIFT) /* TIMESTAMP is mapped on PI8 */ # define RTC_OR_PC1 (2 << RTC_OR_TSINSEL_SHIFT) /* TIMESTAMP is mapped on PC1 */ # define RTC_OR_PC1_1 (3 << RTC_OR_TSINSEL_SHIFT) /* TIMESTAMP is mapped on PC1 */ + #define RTC_OR_RTC_ALARM_TYPE (1 << 3) /* RTC_ALARM on PC13 output type */ - #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_RTCC_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32_tim.h b/arch/arm/src/stm32f7/hardware/stm32_tim.h index 58137663fa8..07af33f2742 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32_tim.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32_tim.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_TIM_H #define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_TIM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h index ce52c455170..df6d3ce8b10 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM327_CHIP_STM32F74XX75XX_FLASH_H #define __ARCH_ARM_SRC_STM327_CHIP_STM32F74XX75XX_FLASH_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Flash size is known from the chip selection: * * When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on the chip - * part number. This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x + * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on + * the chip part number. + * This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x * * Parts STM32F74xxE have 512Kb of FLASH * Parts STM32F74xxG have 1024Kb of FLASH @@ -80,7 +81,7 @@ #endif -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_FLASH_ACR_OFFSET 0x0000 #define STM32_FLASH_KEYR_OFFSET 0x0004 @@ -90,7 +91,7 @@ #define STM32_FLASH_OPTCR_OFFSET 0x0014 #define STM32_FLASH_OPTCR1_OFFSET 0x0018 -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) #define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) @@ -100,7 +101,8 @@ #define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET) #define STM32_FLASH_OPTCR1 (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR1_OFFSET) -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ + /* Flash Access Control Register (ACR) */ #define FLASH_ACR_LATENCY_SHIFT (0) /* Bits 0-1: Latency */ @@ -114,6 +116,7 @@ # define FLASH_ACR_LATENCY_5 (5 << FLASH_ACR_LATENCY_SHIFT) /* 101: Five wait states */ # define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 110: Six wait states */ # define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 111: Seven wait states */ + #define FLASH_ACR_PRFTEN (1 << 8) /* FLASH prefetch enable */ #define FLASH_ACR_ARTEN (1 << 9) /* Bit 9: ART Accelerator Enable */ #define FLASH_ACR_ARTRST (1 << 11) /* Bit 11: ART Accelerator reset */ @@ -136,12 +139,14 @@ #define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */ #define FLASH_CR_SNB_MASK (0xf << FLASH_CR_SNB_SHIFT) # define FLASH_CR_SNB(n) (((uint32_t)((n) % 8) << FLASH_CR_SNB_SHIFT) | ((n / 8) << 6)) /* Sector n, n=0..23 */ + #define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */ #define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT) # define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* Program x8 */ # define FLASH_CR_PSIZE_X16 (1 << FLASH_CR_PSIZE_SHIFT) /* Program x16 */ # define FLASH_CR_PSIZE_X32 (2 << FLASH_CR_PSIZE_SHIFT) /* Program x32 */ # define FLASH_CR_PSIZE_X64 (3 << FLASH_CR_PSIZE_SHIFT) /* Program x64 */ + #define FLASH_CR_STRT (1 << 16) /* Bit 16: Start Erase */ #define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */ #define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */ @@ -157,6 +162,7 @@ # define FLASH_OPTCR_VBOR2 (1 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 2 */ # define FLASH_OPTCR_VBOR1 (2 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 1 */ # define FLASH_OPTCR_VBOR0 (3 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR off */ + #define FLASH_OPTCR_USER_SHIFT (4) /* Bits 5-7: User option bytes */ #define FLASH_OPTCR_USER_MASK (15 << FLASH_OPTCR_USER_SHIFT) # define FLASH_OPTCR_WWDG_SW (1 << 4) /* Bit 4: WWDG_SW */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h index 60c09aa73e1..adda9347a18 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XXX75XXX_MEMORYMAP_H #define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XXX75XXX_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* STM32F7XXXX STM32F75XXX Address Blocks *******************************************/ +/* STM32F7XXXX STM32F75XXX Address Blocks ***********************************/ #define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ #define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ @@ -52,7 +52,7 @@ #define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) #define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FMC_BANK1) -/* Code Base Addresses **************************************************************/ +/* Code Base Addresses ******************************************************/ #define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ #define STM32_INSTRAM_BASE 0x00000000 /* 0x00000000-0x00003fff: Instruction RAM (ITCM-RAM) */ @@ -63,7 +63,7 @@ #define STM32_FLASH_BASE STM32_FLASH_AXIM #define STM32_OPTIONS_BASE 0x1fff0000 /* 0x1ff00000-0x1fff001f: Option bytes (AXIM) */ -/* Information Addresses ************************************************************/ +/* Information Addresses ****************************************************/ #define STM32_SYSMEM_AXIM 0x1ff00000 /* 0x1ff00000-0x1ff0edbf: System memory (AXIM) */ #define STM32_SYSMEM_UID 0x1ff0f420 /* The 96-bit unique device identifier */ @@ -72,13 +72,13 @@ #define STM32_OPT_BASE STM32_OTP_AXIM #define STM32_OPT_SIZE 1056 -/* SRAM Base Addresses **************************************************************/ +/* SRAM Base Addresses ******************************************************/ #define STM32_DTCRAM_BASE 0x20000000 /* 0x20000000-0x2000ffff: DTCM-RAM on TCM interface */ #define STM32_SRAM1_BASE 0x20010000 /* 0x20010000-0x2004bfff: System SRAM1 */ #define STM32_SRAM2_BASE 0x2004c000 /* 0x2004c000-0x2004ffff: System SRAM2 */ -/* Peripheral Base Addresses ********************************************************/ +/* Peripheral Base Addresses ************************************************/ #define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40007fff: APB1 */ #define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40016bff: APB2 */ @@ -86,7 +86,7 @@ #define STM32_AHB2_BASE 0x50000000 /* 0x50000000-0x5003ffff: AHB2 */ #define STM32_AHB3_BASE 0x60000000 /* 0x60000000-0xdfffffff: AHB3 */ -/* APB1 Base Addresses **************************************************************/ +/* APB1 Base Addresses ******************************************************/ #define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff: TIM2 */ #define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff: TIM3 */ @@ -122,7 +122,7 @@ #define STM32_UART7_BASE 0x40007800 /* 0x40007800-0x40007bff: UART7 */ #define STM32_UART8_BASE 0x40007c00 /* 0x40007c00-0x40007fff: UART8 */ -/* APB2 Base Addresses **************************************************************/ +/* APB2 Base Addresses ******************************************************/ #define STM32_TIM1_BASE 0x40010000 /* 0x40010000-0x400103ff: TIM1 */ #define STM32_TIM8_BASE 0x40010400 /* 0x40010400-0x400107ff: TIM8 */ @@ -147,7 +147,7 @@ #define STM32_SAI2_BASE 0x40015c00 /* 0x40015c00-0x40015fff: SAI2 */ #define STM32_LTDC_BASE 0x40016800 /* 0x40016800-0x40016bff: LCD-TFT */ -/* AHB1 Base Addresses **************************************************************/ +/* AHB1 Base Addresses ******************************************************/ #define STM32_GPIOA_BASE 0x40020000 /* 0x40020000-0x400203ff: GPIOA */ #define STM32_GPIOB_BASE 0x40020400 /* 0x40020400-0x400207ff: GPIOB */ @@ -170,7 +170,7 @@ #define STM32_DMA2D_BASE 0x4002b000 /* 0x4002b000-0x4002Bbff: Chrom-ART (DMA2D) */ #define STM32_USBOTGHS_BASE 0x40040000 /* 0x40040000-0x4007ffff: USB OTG HS */ -/* AHB2 Base Addresses **************************************************************/ +/* AHB2 Base Addresses ******************************************************/ #define STM32_USBOTGFS_BASE 0x50000000 /* 0x50000000-0x5003ffff: USB OTG FS */ #define STM32_DCMI_BASE 0x50050000 /* 0x50050000-0x500503ff: DCMI */ @@ -178,7 +178,7 @@ #define STM32_HASH_BASE 0x50060400 /* 0x50060400-0x500607ff: HASH */ #define STM32_RNG_BASE 0x50060800 /* 0x50060800-0x50060bff: RNG */ -/* AHB3 Base Addresses **************************************************************/ +/* AHB3 Base Addresses ******************************************************/ #define STM32_FMCBANK1_BASE 0x60000000 /* 0x60000000-0x6fffffff: FMC bank 1 */ #define STM32_FMCBANK2_BASE 0x70000000 /* 0x70000000-0x7fffffff: FMC bank 2 */ @@ -189,9 +189,10 @@ #define STM32_FMCBANK5_BASE 0xc0000000 /* 0xc0000000-0xcfffffff: FMC bank 5 */ #define STM32_FMCBANK6_BASE 0xd0000000 /* 0xd0000000-0xdfffffff: FMC bank 6 */ -/* Cortex-M7 Base Addresses *********************************************************/ -/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this - * address range +/* Cortex-M7 Base Addresses *************************************************/ + +/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in + * this address range */ #define STM32_DEBUGMCU_BASE 0xe0042000 diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h index 6328da23a35..46b02a7096b 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,38 +16,38 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_PWR_H #define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_PWR_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ #define STM32_PWR_CSR1_OFFSET 0x0004 /* Power control/status register 1 */ #define STM32_PWR_CR2_OFFSET 0x0008 /* Power control register 1 */ #define STM32_PWR_CSR2_OFFSET 0x000c /* Power control/status register 1 */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET) #define STM32_PWR_CSR1 (STM32_PWR_BASE+STM32_PWR_CSR1_OFFSET) #define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET) #define STM32_PWR_CSR2 (STM32_PWR_BASE+STM32_PWR_CSR2_OFFSET) -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* Power control register 1 */ @@ -65,6 +65,7 @@ # define PWR_CR1_2p7V (5 << PWR_CR1_PLS_SHIFT) /* 101: 2.7V */ # define PWR_CR1_2p8V (6 << PWR_CR1_PLS_SHIFT) /* 110: 2.8V */ # define PWR_CR1_2p9V (7 << PWR_CR1_PLS_SHIFT) /* 111: 2.9V */ + #define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ #define PWR_CR1_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */ #define PWR_CR1_LPUDS (1 << 10) /* Bit 10: Low-power regulator in deepsleep under-drive mode */ @@ -75,6 +76,7 @@ # define PWR_CR1_VOS_SCALE_3 (1 << PWR_CR1_VOS_SHIFT) /* Fmax = 144MHz */ # define PWR_CR1_VOS_SCALE_2 (2 << PWR_CR1_VOS_SHIFT) /* Fmax = 168/180MHz */ # define PWR_CR1_VOS_SCALE_1 (3 << PWR_CR1_VOS_SHIFT) /* Fmax = 180/216MHz */ + #define PWR_CR1_ODEN (1 << 16) /* Bit 16: Over Drive enable */ #define PWR_CR1_ODSWEN (1 << 17) /* Bit 17: Over Drive switch enabled */ #define PWR_CR1_UDEN_SHIFT (18) /* Bits 18-19: Under-drive enable in stop mode */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h index c530163e8c0..916b180d9a8 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_RCC_H #define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_RCC_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ #define STM32_RCC_PLLCFG_OFFSET 0x0004 /* PLL configuration register */ @@ -62,7 +62,7 @@ #define STM32_RCC_DCKCFGR1_OFFSET 0x008c /* Dedicated clocks configuration register 1 */ #define STM32_RCC_DCKCFGR2_OFFSET 0x0090 /* Dedicated clocks configuration register 2 */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) #define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) @@ -91,7 +91,7 @@ #define STM32_RCC_DCKCFGR1 (STM32_RCC_BASE+STM32_RCC_DCKCFGR1_OFFSET) #define STM32_RCC_DCKCFGR2 (STM32_RCC_BASE+STM32_RCC_DCKCFGR2_OFFSET) -/* Register Bitfield Definitions ********************************************************************/ +/* Register Bitfield Definitions ********************************************/ /* Clock control register */ @@ -118,16 +118,20 @@ * input clock divider */ #define RCC_PLLCFG_PLLM_MASK (0x3f << RCC_PLLCFG_PLLM_SHIFT) # define RCC_PLLCFG_PLLM(n) ((n) << RCC_PLLCFG_PLLM_SHIFT) /* n = 2..63 */ + #define RCC_PLLCFG_PLLN_SHIFT (6) /* Bits 6-14: Main PLL (PLL) VCO multiplier */ #define RCC_PLLCFG_PLLN_MASK (0x1ff << RCC_PLLCFG_PLLN_SHIFT) # define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 2..432 */ + #define RCC_PLLCFG_PLLP_SHIFT (16) /* Bits 16-17: Main PLL (PLL) main system clock divider */ #define RCC_PLLCFG_PLLP_MASK (3 << RCC_PLLCFG_PLLP_SHIFT) # define RCC_PLLCFG_PLLP(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLP_SHIFT) /* n=2,4,6,8 */ + # define RCC_PLLCFG_PLLP_2 (0 << RCC_PLLCFG_PLLP_SHIFT) /* 00: PLLP = 2 */ # define RCC_PLLCFG_PLLP_4 (1 << RCC_PLLCFG_PLLP_SHIFT) /* 01: PLLP = 4 */ # define RCC_PLLCFG_PLLP_6 (2 << RCC_PLLCFG_PLLP_SHIFT) /* 10: PLLP = 6 */ # define RCC_PLLCFG_PLLP_8 (3 << RCC_PLLCFG_PLLP_SHIFT) /* 11: PLLP = 8 */ + #define RCC_PLLCFG_PLLSRC (1 << 22) /* Bit 22: Main PLL(PLL) and audio PLL (PLLI2S) * entry clock source */ # define RCC_PLLCFG_PLLSRC_HSI (0) @@ -146,22 +150,25 @@ # define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 00: HSI selected as system clock */ # define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */ # define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */ + #define RCC_CFGR_SWS_SHIFT (2) /* Bits 2-3: System Clock Switch Status */ #define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT) # define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */ # define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */ # define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */ + #define RCC_CFGR_HPRE_SHIFT (4) /* Bits 4-7: AHB prescaler */ #define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT) -# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ -# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ -# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ +# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ +# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ +# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ # define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */ # define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */ # define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */ # define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */ # define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */ # define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */ + #define RCC_CFGR_PPRE1_SHIFT (10) /* Bits 10-12: APB Low speed prescaler (APB1) */ #define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT) # define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */ @@ -169,6 +176,7 @@ # define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */ # define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */ # define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */ + #define RCC_CFGR_PPRE2_SHIFT (13) /* Bits 13-15: APB High speed prescaler (APB2) */ #define RCC_CFGR_PPRE2_MASK (7 << RCC_CFGR_PPRE2_SHIFT) # define RCC_CFGR_PPRE2_HCLK (0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK not divided */ @@ -176,15 +184,18 @@ # define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */ # define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */ # define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */ + #define RCC_CFGR_RTCPRE_SHIFT (16) /* Bits 16-20: APB High speed prescaler (APB2) */ #define RCC_CFGR_RTCPRE_MASK (31 << RCC_CFGR_RTCPRE_SHIFT) # define RCC_CFGR_RTCPRE(n) ((n) << RCC_CFGR_RTCPRE_SHIFT) /* HSE/n, n=1..31 */ + #define RCC_CFGR_MCO1_SHIFT (21) /* Bits 21-22: Microcontroller Clock Output */ #define RCC_CFGR_MCO1_MASK (3 << RCC_CFGR_MCO1_SHIFT) # define RCC_CFGR_MCO1_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 00: HSI clock selected */ # define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 01: LSE oscillator selected */ # define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 10: HSE oscillator clock selected */ # define RCC_CFGR_MCO1_PLL (3 << RCC_CFGR_MCO1_SHIFT) /* 11: PLL clock selected */ + #define RCC_CFGR_I2SSRC (1 << 23) /* Bit 23: I2S clock selection */ #define RCC_CFGR_MCO1PRE_SHIFT (24) /* Bits 24-26: MCO1 prescaler */ #define RCC_CFGR_MCO1PRE_MASK (7 << RCC_CFGR_MCO1PRE_SHIFT) @@ -193,6 +204,7 @@ # define RCC_CFGR_MCO1PRE_DIV3 (5 << RCC_CFGR_MCO1PRE_SHIFT) /* 101: division by 3 */ # define RCC_CFGR_MCO1PRE_DIV4 (6 << RCC_CFGR_MCO1PRE_SHIFT) /* 110: division by 4 */ # define RCC_CFGR_MCO1PRE_DIV5 (7 << RCC_CFGR_MCO1PRE_SHIFT) /* 111: division by 5 */ + #define RCC_CFGR_MCO2PRE_SHIFT (27) /* Bits 27-29: MCO2 prescaler */ #define RCC_CFGR_MCO2PRE_MASK (7 << RCC_CFGR_MCO2PRE_SHIFT) # define RCC_CFGR_MCO2PRE_NONE (0 << RCC_CFGR_MCO2PRE_SHIFT) /* 0xx: no division */ @@ -200,6 +212,7 @@ # define RCC_CFGR_MCO2PRE_DIV3 (5 << RCC_CFGR_MCO2PRE_SHIFT) /* 101: division by 3 */ # define RCC_CFGR_MCO2PRE_DIV4 (6 << RCC_CFGR_MCO2PRE_SHIFT) /* 110: division by 4 */ # define RCC_CFGR_MCO2PRE_DIV5 (7 << RCC_CFGR_MCO2PRE_SHIFT) /* 111: division by 5 */ + #define RCC_CFGR_MCO2_SHIFT (30) /* Bits 30-31: Microcontroller clock output 2 */ #define RCC_CFGR_MCO2_MASK (3 << RCC_CFGR_MCO2_SHIFT) # define RCC_CFGR_MCO2_SYSCLK (0 << RCC_CFGR_MCO2_SHIFT) /* 00: System clock (SYSCLK) selected */ @@ -524,12 +537,14 @@ # define RCC_BDCR_LSEDRV_MEDHI (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01 :Medium high driving capability */ # define RCC_BDCR_LSEDRV_MEDLO (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium low driving capability */ # define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: High driving capability */ + #define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ #define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) # define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ # define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ # define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ # define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */ + #define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ #define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */ @@ -617,76 +632,90 @@ # define RCC_DCKCFGR2_USART1SEL_SYSCLK (1 << RCC_DCKCFGR2_USART1SEL_SHIFT) /* System clock is selected as USART 1 clock */ # define RCC_DCKCFGR2_USART1SEL_HSI (2 << RCC_DCKCFGR2_USART1SEL_SHIFT) /* HSI clock is selected as USART 1 clock */ # define RCC_DCKCFGR2_USART1SEL_LSE (3 << RCC_DCKCFGR2_USART1SEL_SHIFT) /* LSE clock is selected as USART 1 clock */ + #define RCC_DCKCFGR2_USART2SEL_SHIFT (2) /* Bits 2-3: USART 2 clock source selection */ #define RCC_DCKCFGR2_USART2SEL_MASK (3 << RCC_DCKCFGR2_USART2SEL_SHIFT) # define RCC_DCKCFGR2_USART2SEL_APB (0 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* APB1 clock (PCLK1) is selected as USART 2 clock */ # define RCC_DCKCFGR2_USART2SEL_SYSCLK (1 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* System clock is selected as USART 2 clock */ # define RCC_DCKCFGR2_USART2SEL_HSI (2 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* HSI clock is selected as USART 2 clock */ # define RCC_DCKCFGR2_USART2SEL_LSE (3 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* LSE clock is selected as USART 2 clock */ + #define RCC_DCKCFGR2_UART4SEL_SHIFT (6) /* Bits 6-7: UART 4 clock source selection */ #define RCC_DCKCFGR2_UART4SEL_MASK (3 << RCC_DCKCFGR2_UART4SEL_SHIFT) # define RCC_DCKCFGR2_UART4SEL_APB (0 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 4 clock */ # define RCC_DCKCFGR2_UART4SEL_SYSCLK (1 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* System clock is selected as UART 4 clock */ # define RCC_DCKCFGR2_UART4SEL_HSI (2 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* HSI clock is selected as UART 4 clock */ # define RCC_DCKCFGR2_UART4SEL_LSE (3 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* LSE clock is selected as UART 4 clock */ + #define RCC_DCKCFGR2_UART5SEL_SHIFT (8) /* Bits 8-9: UART 5 clock source selection */ #define RCC_DCKCFGR2_UART5SEL_MASK (3 << RCC_DCKCFGR2_UART5SEL_SHIFT) # define RCC_DCKCFGR2_UART5SEL_APB (0 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 5 clock */ # define RCC_DCKCFGR2_UART5SEL_SYSCLK (1 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* System clock is selected as UART 5 clock */ # define RCC_DCKCFGR2_UART5SEL_HSI (2 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* HSI clock is selected as UART 5 clock */ # define RCC_DCKCFGR2_UART5SEL_LSE (3 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* LSE clock is selected as UART 5 clock */ + #define RCC_DCKCFGR2_USART6SEL_SHIFT (10) /* Bits 10-11: USART 6 clock source selection */ #define RCC_DCKCFGR2_USART6SEL_MASK (3 << RCC_DCKCFGR2_USART6SEL_SHIFT) # define RCC_DCKCFGR2_USART6SEL_APB (0 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* APB2 clock (PCLK2) is selected as USART 6 clock */ # define RCC_DCKCFGR2_USART6SEL_SYSCLK (1 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* System clock is selected as USART 6 clock */ # define RCC_DCKCFGR2_USART6SEL_HSI (2 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* HSI clock is selected as USART 6 clock */ # define RCC_DCKCFGR2_USART6SEL_LSE (3 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* LSE clock is selected as USART 6 clock */ + #define RCC_DCKCFGR2_UART7SEL_SHIFT (12) /* Bits 12-13: UART 7 clock source selection */ #define RCC_DCKCFGR2_UART7SEL_MASK (3 << RCC_DCKCFGR2_UART7SEL_SHIFT) # define RCC_DCKCFGR2_UART7SEL_APB (0 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 7 clock */ # define RCC_DCKCFGR2_UART7SEL_SYSCLK (1 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* System clock is selected as UART 7 clock */ # define RCC_DCKCFGR2_UART7SEL_HSI (2 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* HSI clock is selected as UART 7 clock */ # define RCC_DCKCFGR2_UART7SEL_LSE (3 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* LSE clock is selected as UART 7 clock */ + #define RCC_DCKCFGR2_UART8SEL_SHIFT (14) /* Bits 14-15: UART 8 clock source selection */ #define RCC_DCKCFGR2_UART8SEL_MASK (3 << RCC_DCKCFGR2_UART8SEL_SHIFT) # define RCC_DCKCFGR2_UART8SEL_APB (0 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 8 clock */ # define RCC_DCKCFGR2_UART8SEL_SYSCLK (1 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* System clock is selected as UART 8 clock */ # define RCC_DCKCFGR2_UART8SEL_HSI (2 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* HSI clock is selected as UART 8 clock */ # define RCC_DCKCFGR2_UART8SEL_LSE (3 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* LSE clock is selected as UART 8 clock */ + #define RCC_DCKCFGR2_I2C1SEL_SHIFT (16) /* Bits 16-17: I2C1 clock source selection */ #define RCC_DCKCFGR2_I2C1SEL_MASK (3 << RCC_DCKCFGR2_I2C1SEL_SHIFT) # define RCC_DCKCFGR2_I2C1SEL_APB (0 << RCC_DCKCFGR2_I2C1SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 1 clock */ # define RCC_DCKCFGR2_I2C1SEL_SYSCLK (1 << RCC_DCKCFGR2_I2C1SEL_SHIFT) /* System clock is selected as I2C 1 clock */ # define RCC_DCKCFGR2_I2C1SEL_HSI (2 << RCC_DCKCFGR2_I2C1SEL_SHIFT) /* HSI clock is selected as I2C 1 clock */ + #define RCC_DCKCFGR2_I2C2SEL_SHIFT (18) /* Bits 18-19: I2C2 clock source selection */ #define RCC_DCKCFGR2_I2C2SEL_MASK (3 << RCC_DCKCFGR2_I2C2SEL_SHIFT) # define RCC_DCKCFGR2_I2C2SEL_APB (0 << RCC_DCKCFGR2_I2C2SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 2 clock */ # define RCC_DCKCFGR2_I2C2SEL_SYSCLK (1 << RCC_DCKCFGR2_I2C2SEL_SHIFT) /* System clock is selected as I2C 2 clock */ # define RCC_DCKCFGR2_I2C2SEL_HSI (2 << RCC_DCKCFGR2_I2C2SEL_SHIFT) /* HSI clock is selected as I2C 2 clock */ + #define RCC_DCKCFGR2_I2C3SEL_SHIFT (20) /* Bits 20-21: I2C3 clock source selection */ #define RCC_DCKCFGR2_I2C3SEL_MASK (3 << RCC_DCKCFGR2_I2C3SEL_SHIFT) # define RCC_DCKCFGR2_I2C3SEL_APB (0 << RCC_DCKCFGR2_I2C3SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 3 clock */ # define RCC_DCKCFGR2_I2C3SEL_SYSCLK (1 << RCC_DCKCFGR2_I2C3SEL_SHIFT) /* System clock is selected as I2C 3 clock */ # define RCC_DCKCFGR2_I2C3SEL_HSI (2 << RCC_DCKCFGR2_I2C3SEL_SHIFT) /* HSI clock is selected as I2C 3 clock */ + #define RCC_DCKCFGR2_I2C4SEL_SHIFT (22) /* Bits 22-23: I2C4 clock source selection */ #define RCC_DCKCFGR2_I2C4SEL_MASK (3 << RCC_DCKCFGR2_I2C4SEL_SHIFT) # define RCC_DCKCFGR2_I2C4SEL_APB (0 << RCC_DCKCFGR2_I2C4SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 4 clock */ # define RCC_DCKCFGR2_I2C4SEL_SYSCLK (1 << RCC_DCKCFGR2_I2C4SEL_SHIFT) /* System clock is selected as I2C 4 clock */ # define RCC_DCKCFGR2_I2C4SEL_HSI (2 << RCC_DCKCFGR2_I2C4SEL_SHIFT) /* HSI clock is selected as I2C 4 clock */ + #define RCC_DCKCFGR2_LPTIM1SEL_SHIFT (24) /* Bits 24-25: Low power timer 1 clock source selection */ #define RCC_DCKCFGR2_LPTIM1SEL_MASK (3 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) # define RCC_DCKCFGR2_LPTIM1SEL_APB (0 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* APB1 clock (PCLK1) is selected as LPTIM 1 clock */ # define RCC_DCKCFGR2_LPTIM1SEL_SYSCLK (1 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* System clock is selected as LPTIM 1 clock */ # define RCC_DCKCFGR2_LPTIM1SEL_HSI (2 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* HSI clock is selected as LPTIM 1 clock */ # define RCC_DCKCFGR2_LPTIM1SEL_LSE (3 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* LSE clock is selected as LPTIM 1 clock */ + #define RCC_DCKCFGR2_CECSEL_SHIFT (26) /* Bit 26: HDMI-CEC clock source selection */ #define RCC_DCKCFGR2_CECSEL_MASK (1 << RCC_DCKCFGR2_CECSEL_SHIFT) # define RCC_DCKCFGR2_CECSEL_LSE (0 << RCC_DCKCFGR2_CECSEL_SHIFT) /* LSE clock is selected as HDMI-CEC clock */ # define RCC_DCKCFGR2_CECSEL_HSI (1 << RCC_DCKCFGR2_CECSEL_SHIFT) /* HSI clock is selected as HDMI-CEC clock */ + #define RCC_DCKCFGR2_CK48MSEL_SHIFT (27) /* Bit 27: 48MHz clock source selection */ #define RCC_DCKCFGR2_CK48MSEL_MASK (1 << RCC_DCKCFGR2_CK48MSEL_SHIFT) # define RCC_DCKCFGR2_CK48MSEL_PLL (0 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /* 48MHz clock from PLL is selected */ -# define RCC_DCKCFGR2_CK48MSEL_PLLSAI (1 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /*48MHz clock from PLLSAI is selected */ +# define RCC_DCKCFGR2_CK48MSEL_PLLSAI (1 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /* 48MHz clock from PLLSAI is selected */ + #define RCC_DCKCFGR2_SDMMCSEL_SHIFT (28) /* Bit 28: SDMMC clock source selection */ #define RCC_DCKCFGR2_SDMMCSEL_MASK (1 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) # define RCC_DCKCFGR2_SDMMCSEL_48MHZ (0 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h index 035fbffcff0..46e89338df2 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,16 +16,16 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_TIM_H #define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_TIM_H -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ /* Basic Timers - TIM6 and TIM7 */ @@ -39,7 +39,8 @@ #define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5 - * 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 + * 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, + * and TIM14 * timers are 16-bit except for TIM2 and 5 are 32-bit * timers TIM9 and 12 are different then TIM10, TIM11, TIM13, and TIM14 */ @@ -67,14 +68,14 @@ /* Advanced Timers - TIM1 and TIM8 */ #define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (32-bit*) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ #define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (32 -bit) */ #define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (32-bit*) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (32-bit) */ #define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit*) */ -#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit*) */ -#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (32-bit*) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (32-bit) */ #define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (32-bit cnt in lower 16 bit ) */ #define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ #define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ @@ -83,14 +84,14 @@ #define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ #define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ #define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (32-bit*) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (32-bit) */ #define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ #define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ #define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ #define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (32-bit) */ #define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 6 (16-bit) */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ @@ -236,7 +237,6 @@ # define STM32_TIM5_OR (STM32_TIM5_BASE+STM32_GTIM_OR_OFFSET) #endif - /* 16-bit General Timers - TIM9-14 without DMA. Note that (1) these timers * support only a subset of the general timer registers are supported, and * (2) TIM9 and TIM12 differ from the others. @@ -349,7 +349,7 @@ # define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET) #endif -/* Register Bitfield Definitions ********************************************************************/ +/* Register Bitfield Definitions ********************************************/ /* Control register 1 */ @@ -364,12 +364,14 @@ # define ATIM_CR1_CENTER1 (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ # define ATIM_CR1_CENTER2 (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ # define ATIM_CR1_CENTER3 (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ + #define ATIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ #define ATIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock division */ #define ATIM_CR1_CKD_MASK (3 << ATIM_CR1_CKD_SHIFT) # define ATIM_CR1_TCKINT (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ # define ATIM_CR1_2TCKINT (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ # define ATIM_CR1_4TCKINT (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ + #define ATIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ /* Control register 2 */ @@ -387,6 +389,7 @@ # define ATIM_CR2_MMS_OC2REF (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */ # define ATIM_CR2_MMS_OC3REF (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */ # define ATIM_CR2_MMS_OC4REF (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */ + #define ATIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ #define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ #define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ @@ -428,6 +431,7 @@ # define ATIM_SMCR_GATED (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ # define ATIM_SMCR_TRIGGER (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ # define ATIM_SMCR_EXTCLK1 (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ + #define ATIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */ #define ATIM_SMCR_TS_MASK (7 << ATIM_SMCR_TS_SHIFT) # define ATIM_SMCR_ITR0 (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */ @@ -438,31 +442,34 @@ # define ATIM_SMCR_TI1FP1 (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ # define ATIM_SMCR_T12FP2 (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ # define ATIM_SMCR_ETRF (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ + #define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ #define ATIM_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ #define ATIM_SMCR_ETF_MASK (0x0f << ATIM_SMCR_ETF_SHIFT) -# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ -# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define ATIM_SMCR_FCKINT4 (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define ATIM_SMCR_FCKINT8 (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define ATIM_SMCR_FDTSd26 (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define ATIM_SMCR_FDTSd28 (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define ATIM_SMCR_FDTSd46 (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define ATIM_SMCR_FDTSd48 (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define ATIM_SMCR_FDTSd86 (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define ATIM_SMCR_FDTSd88 (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ +# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_SMCR_FCKINT4 (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_SMCR_FCKINT8 (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_SMCR_FDTSd26 (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_SMCR_FDTSd28 (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_SMCR_FDTSd46 (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_SMCR_FDTSd48 (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_SMCR_FDTSd86 (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_SMCR_FDTSd88 (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ # define ATIM_SMCR_FDTSd165 (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ # define ATIM_SMCR_FDTSd166 (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ # define ATIM_SMCR_FDTSd168 (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ # define ATIM_SMCR_FDTSd325 (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ # define ATIM_SMCR_FDTSd326 (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ # define ATIM_SMCR_FDTSd328 (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ + #define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ #define ATIM_SMCR_ETPS_MASK (3 << ATIM_SMCR_ETPS_SHIFT) # define ATIM_SMCR_PSCOFF (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ # define ATIM_SMCR_ETRPd2 (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ # define ATIM_SMCR_ETRPd4 (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ # define ATIM_SMCR_ETRPd8 (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ + #define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ #define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ #define ATIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ @@ -538,7 +545,6 @@ #define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ #define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ - /* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ #define ATIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ @@ -565,7 +571,10 @@ /* Capture/compare mode register 1 -- Input capture mode */ - /* Bits 1-0:(same as output compare mode) */ +/* Bits 1-0: + * (same as output compare mode) + */ + #define ATIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ #define ATIM_CCMR1_IC1PSC_MASK (3 << ATIM_CCMR1_IC1PSC_SHIFT) /* (See common (unshifted) bit field definitions below) */ @@ -631,7 +640,10 @@ /* Capture/compare mode register 2 - Input Capture Mode */ - /* Bits 1-0:(same as output compare mode) */ +/* Bits 1-0: + * (same as output compare mode) + */ + #define ATIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ #define ATIM_CCMR1_IC3PSC_MASK (3 << ATIM_CCMR2_IC3PSC_SHIFT) /* (See common (unshifted) bit field definitions above) */ @@ -663,7 +675,6 @@ #define ATIM_CCMR3_OC5M (1 << 16) /* Bit 16: Output Compare 5 mode - bit 3 */ #define ATIM_CCMR3_OC6M (1 << 24) /* Bit 24: Output Compare 6 mode - bit 3 */ - /* Capture/compare enable register */ #define ATIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ @@ -686,7 +697,6 @@ #define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ #define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ - /* 16-bit counter register */ #define ATIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ @@ -717,6 +727,7 @@ # define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ # define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ # define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */ + #define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ #define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ #define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ @@ -741,6 +752,7 @@ # define ATIM_BDTR_BKF_FDTSd325 (13 << ATIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ # define ATIM_BDTR_BKF_FDTSd326 (14 << ATIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ # define ATIM_BDTR_BKF_FDTSd328 (15 << ATIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ + #define ATIM_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ #define ATIM_BDTR_BK2F_MASK (0xf << ATIM_BDTR_BK2F_SHIFT) # define ATIM_BDTR_BK2F_NOFILT (0 << ATIM_BDTR_BK2F_SHIFT) /* 0000: No filter, BRK 2 acts asynchronously */ @@ -759,9 +771,9 @@ # define ATIM_BDTR_BK2F_FDTSd325 (13 << ATIM_BDTR_BK2F_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ # define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ # define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ -#define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ -#define ATIM_BDTR_BK2P (1 << 1525 /* Bit 25:Break 2 polarity */ +#define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ +#define ATIM_BDTR_BK2P (1 << 1525 /* Bit 25:Break 2 polarity */ /* DMA control register */ @@ -784,12 +796,14 @@ # define GTIM_CR1_CENTER1 (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ # define GTIM_CR1_CENTER2 (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ # define GTIM_CR1_CENTER3 (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ + #define GTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ #define GTIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock Division */ #define GTIM_CR1_CKD_MASK (3 << GTIM_CR1_CKD_SHIFT) # define GTIM_CR1_TCKINT (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */ # define GTIM_CR1_2TCKINT (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */ # define GTIM_CR1_4TCKINT (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */ + #define GTIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ /* Control register 2 (TIM2-5, TIM9-12) */ @@ -807,6 +821,7 @@ # define GTIM_CR2_MMS_OC2REF (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */ # define GTIM_CR2_MMS_OC3REF (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ # define GTIM_CR2_MMS_OC4REF (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ + #define GTIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection (not TIM16) */ #define GTIM_CR2_OIS1 (1 << 8) /* Bit 8: COutput Idle state 1 (OC1 output) (TIM15-17 only) */ #define GTIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) (TIM15-17 only) */ @@ -824,6 +839,7 @@ # define GTIM_SMCR_GATED (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ # define GTIM_SMCR_TRIGGER (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ # define GTIM_SMCR_EXTCLK1 (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ + #define GTIM_SMCR_TS_SHIFT (4) /* Bits 6-4: Trigger Selection */ #define GTIM_SMCR_TS_MASK (7 << GTIM_SMCR_TS_SHIFT) # define GTIM_SMCR_ITR0 (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). TIM1 */ @@ -834,6 +850,7 @@ # define GTIM_SMCR_TI1FP1 (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ # define GTIM_SMCR_TI2FP2 (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ # define GTIM_SMCR_ETRF (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ + #define GTIM_SMCR_MSM (1 << 7) /* Bit 7: Master/Slave mode */ #define GTIM_SMCR_ETF_SHIFT (8) /* Bits 11-8: External Trigger Filter (not TIM15) */ #define GTIM_SMCR_ETF_MASK (0x0f << GTIM_SMCR_ETF_SHIFT) @@ -853,12 +870,14 @@ # define GTIM_SMCR_FDTSd325 (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ # define GTIM_SMCR_FDTSd326 (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ # define GTIM_SMCR_FDTSd328 (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ + #define GTIM_SMCR_ETPS_SHIFT (12) /* Bits 13-12: External Trigger Prescaler (not TIM15) */ #define GTIM_SMCR_ETPS_MASK (3 << GTIM_SMCR_ETPS_SHIFT) # define GTIM_SMCR_PSCOFF (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ # define GTIM_SMCR_ETRPd2 (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ # define GTIM_SMCR_ETRPd4 (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ # define GTIM_SMCR_ETRPd8 (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ + #define GTIM_SMCR_ECE (1 << 14) /* Bit 14: External Clock enable */ #define GTIM_SMCR_ETP (1 << 15) /* Bit 15: External Trigger Polarity */ #define GTIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ @@ -907,7 +926,9 @@ #define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger generation (TIM2-5,9,12&16-17 only) */ #define GTIM_EGR_BG (1 << 7) /* Bit 7: Break generation (TIM15-17 only) */ -/* Capture/compare mode register 1 - Output compare mode (TIM2-5 and TIM9-14) */ +/* Capture/compare mode register + * 1 - Output compare mode (TIM2-5 and TIM9-14) + */ #define GTIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ #define GTIM_CCMR1_CC1S_MASK (3 << GTIM_CCMR1_CC1S_SHIFT) @@ -948,9 +969,14 @@ #define GTIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ #define GTIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ -/* Capture/compare mode register 1 - Input capture mode (TIM2-5 and TIM9-14) */ +/* Capture/compare mode register + * 1 - Input capture mode (TIM2-5 and TIM9-14) + */ + +/* Bits 1-0 + * (Same as Output Compare Mode) + */ - /* Bits 1-0 (Same as Output Compare Mode) */ #define GTIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ #define GTIM_CCMR1_IC1PSC_MASK (3 << GTIM_CCMR1_IC1PSC_SHIFT) /* (See common CCMR Input Capture Prescaler definitions below) */ @@ -1014,7 +1040,10 @@ /* Capture/compare mode register 2 - Input capture mode (TIM2-5 only) */ - /* Bits 1-0 (Same as Output Compare Mode) */ +/* Bits 1-0 + * (Same as Output Compare Mode) + */ + #define GTIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ #define GTIM_CCMR2_IC3PSC_MASK (3 << GTIM_CCMR2_IC3PSC_SHIFT) /* (See common CCMR Input Capture Prescaler definitions below) */ @@ -1064,9 +1093,9 @@ #define TIM2_OR_ITR1_RMP_SHIFT (10) /* Bits 10-11: Internal trigger 1 remap */ #define TIM2_OR_ITR1_RMP_MASK (3 << TIM2_OR_ITR1_RMP_SHIFT) # define TIM2_OR_ITR1_TIM8_TRGOUT (0 << TIM2_OR_ITR1_RMP_SHIFT) /* 00: TIM2_ITR1 input connected to TIM8_TRGOUT */ -# define TIM2_OR_ITR1_PTP (1 << TIM2_OR_ITR1_RMP_SHIFT) /* 01: TIM2_ITR1 input connected to PTP trigger output */ -# define TIM2_OR_ITR1_OTGFSSOF (2 << TIM2_OR_ITR1_RMP_SHIFT) /* 10: TIM2_ITR1 input connected to OTG FS SOF */ -# define TIM2_OR_ITR1_OTGHSSOF (3 << TIM2_OR_ITR1_RMP_SHIFT) /* 11: TIM2_ITR1 input connected to OTG HS SOF */ +# define TIM2_OR_ITR1_PTP (1 << TIM2_OR_ITR1_RMP_SHIFT) /* 01: TIM2_ITR1 input connected to PTP trigger output */ +# define TIM2_OR_ITR1_OTGFSSOF (2 << TIM2_OR_ITR1_RMP_SHIFT) /* 10: TIM2_ITR1 input connected to OTG FS SOF */ +# define TIM2_OR_ITR1_OTGHSSOF (3 << TIM2_OR_ITR1_RMP_SHIFT) /* 11: TIM2_ITR1 input connected to OTG HS SOF */ #define TIM5_OR_TI4_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */ #define TIM5_OR_TI4_RMP_MASK (3 << TIM5_OR_TI4_RMP_SHIFT) @@ -1080,7 +1109,6 @@ # define TIM11_OR_TI1_GPIO (0 << TIM11_OR_TI1_RMP_SHIFT) /* 00-11: TIM11_CH1 input connected to GPIO */ # define TIM11_OR_TI1_HSERTC (3 << TIM11_OR_TI1_RMP_SHIFT) /* 11: TIM11_CH1 input connected to HSE_RTC clock */ - /* Control register 1 */ #define BTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h index b340c002147..2ec4d963b89 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_ADC_H #define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_ADC_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */ #define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */ @@ -56,12 +56,11 @@ #define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */ #define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */ - #define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ #define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */ #define STM32_ADC_CDR_OFFSET 0x0008 /* Data register for dual and triple modes */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #if STM32F7_NADC > 0 # define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET) @@ -136,7 +135,7 @@ #define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET) #define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET) -/* Register Bitfield Definitions ********************************************************************/ +/* Register Bitfield Definitions ********************************************/ /* ADC status register */ @@ -169,6 +168,7 @@ #define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK cycles. For STM32L15XX: 11 ADCCLK cycles */ #define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles. For STM32L15XX: 9 ADCCLK cycles */ #define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles. For STM32L15XX: 7 ADCCLK cycles */ + #define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */ /* ADC control register 2 */ @@ -198,12 +198,14 @@ #define ADC_CR2_JEXTSEL_T3CC1 (0x0d << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 3 CC1 event */ #define ADC_CR2_JEXTSEL_T6TRGO (0x0e << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 6 TRGO event */ /* 1111: Reserved */ + #define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */ #define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT) #define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ #define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ #define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ #define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ + #define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */ /* Bit 23: Reserved, must be kept at reset value. */ #define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */ @@ -224,6 +226,7 @@ #define ADC_CR2_EXTSEL_T6TRGO (0x0d << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 6 TRGO event */ /* 1110: NA */ #define ADC_CR2_EXTSEL_EXTI11 (0x0f << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */ + #define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */ #define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT) #define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */ @@ -262,7 +265,6 @@ #define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ #define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP18_SHIFT) - /* ADC sample time register 2 */ #define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */ @@ -286,7 +288,6 @@ #define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */ #define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT) - /* ADC injected channel data offset register 1-4 */ #define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */ @@ -426,11 +427,19 @@ # define ADC_CCR_MULTI_RSM3 (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */ # define ADC_CCR_MULTI_IM3 (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */ # define ADC_CCR_MULTI_ATM3 (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */ - /* Bits 5-7: Reserved, must be kept at reset value. */ + +/* Bit 5-7 Reserved, + * must be kept at reset value. + */ + # define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ # define ADC_CCR_DELAY_MASK (0xf << ADC_CCR_DELAY_SHIFT) # define ADC_CCR_DELAY(n) (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */ - /* Bit 12 Reserved, must be kept at reset value. */ + +/* Bit 12 Reserved, + * must be kept at reset value. + */ + # define ADC_CCR_DDS (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */ # define ADC_CCR_DMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for multi ADC mode */ @@ -446,23 +455,29 @@ # define ADC_CCR_ADCPRE_DIV4 (1 << ADC_CCR_ADCPRE_SHIFT) /* 01: PCLK2 divided by 4 */ # define ADC_CCR_ADCPRE_DIV6 (2 << ADC_CCR_ADCPRE_SHIFT) /* 10: PCLK2 divided by 6 */ # define ADC_CCR_ADCPRE_DIV8 (3 << ADC_CCR_ADCPRE_SHIFT) /* 11: PCLK2 divided by 8 */ - /* Bits 18-21: Reserved, must be kept at reset value. */ + +/* Bit 18-21 Reserved, + * must be kept at reset value. + */ + # define ADC_CCR_VBATE (1 << 22) /* Bit 22: VBAT enable */ # define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */ /* Bits 24-31 Reserved, must be kept at reset value. */ -/* Data register for dual and triple modes (32-bit data with no named fields) */ +/* Data register for dual and triple modes + * (32-bit data with no named fields) + */ -/**************************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************************** +/**************************************************************************** * Public Function Prototypes - ****************************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_ADC_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h index 9094cd982a4..8b843239232 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,16 +16,16 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F7_STM32F74XX77XX_I2C_H #define __ARCH_ARM_SRC_STM32F7_STM32F74XX77XX_I2C_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ #define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ @@ -39,7 +39,7 @@ #define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ #define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #if STM32F7_NI2C > 0 # define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) @@ -97,7 +97,7 @@ # define STM32_I2C4_TXDR (STM32_I2C4_BASE+STM32_I2C_TXDR_OFFSET) #endif -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* Control register 1 */ @@ -113,6 +113,7 @@ #define I2C_CR1_DNF_MASK (0xf << I2C_CR1_DNF_SHIFT) # define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT) # define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */ + #define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */ #define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */ #define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */ @@ -165,6 +166,7 @@ # define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */ # define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */ # define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */ + #define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */ /* Timing register */ @@ -201,7 +203,6 @@ # define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT) #define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */ - /* Fields unique to the Interrupt and Status register */ #define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */ @@ -215,6 +216,7 @@ #define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT) /* Interrupt and Status register and interrupt clear register */ + /* Common interrupt bits */ #define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_sdmmc.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_sdmmc.h index 9518159ddc8..1a3d56785c2 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_sdmmc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_sdmmc.h @@ -1,4 +1,5 @@ - /* arch/arm/src/stm32f7/hardware/stm32f74xx77xx_sdmmc.h +/**************************************************************************** + * arch/arm/src/stm32f7/hardware/stm32f74xx77xx_sdmmc.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -15,16 +16,16 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_SDMMC_H #define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_SDMMC_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_SDMMC_POWER_OFFSET 0x0000 /* SDMMC power control register */ #define STM32_SDMMC_CLKCR_OFFSET 0x0004 /* SDMMC clock control register */ @@ -46,8 +47,7 @@ #define STM32_SDMMC_FIFOCNT_OFFSET 0x0048 /* SDMMC FIFO counter register */ #define STM32_SDMMC_FIFO_OFFSET 0x0080 /* SDMMC data FIFO register */ - -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ #define STM32_SDMMC_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */ #define STM32_SDMMC_POWER_PWRCTRL_MASK (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) @@ -67,6 +67,7 @@ # define STM32_SDMMC_CLKCR_WIDBUS_D1 (0 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 00: Default (STM32_SDMMC_D0) */ # define STM32_SDMMC_CLKCR_WIDBUS_D4 (1 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (STM32_SDMMC_D[3:0]) */ # define STM32_SDMMC_CLKCR_WIDBUS_D8 (2 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (STM32_SDMMC_D[7:0]) */ + #define STM32_SDMMC_CLKCR_NEGEDGE (1 << 13) /* Bit 13: STM32_SDMMC_CK dephasing selection bit */ #define STM32_SDMMC_CLKCR_HWFC_EN (1 << 14) /* Bit 14: HW Flow Control enable */ @@ -81,6 +82,7 @@ # define STM32_SDMMC_CMD_NORESPONSE (0 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 00/10: No response */ # define STM32_SDMMC_CMD_SHORTRESPONSE (1 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 01: Short response */ # define STM32_SDMMC_CMD_LONGRESPONSE (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 11: Long response */ + #define STM32_SDMMC_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */ #define STM32_SDMMC_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */ #define STM32_SDMMC_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h index 00a18452338..2e9dd52df82 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_SPI_H #define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_SPI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Maximum allowed speed as per data sheet for all SPIs (both pclk1 and pclk2)*/ +/* Maximum allowed speed as per data sheet for all SPIs + * (both pclk1 and pclk2) + */ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # define STM32_SPI_CLK_MAX 50000000UL @@ -40,7 +42,7 @@ # define STM32_SPI_CLK_MAX 54000000UL #endif -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ #define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ @@ -52,7 +54,7 @@ #define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ #define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #if STM32F7_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) @@ -124,7 +126,7 @@ # define STM32_SPI6_I2SPR (STM32_SPI6_BASE+STM32_SPI_I2SPR_OFFSET) #endif -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* SPI Control Register 1 */ @@ -141,6 +143,7 @@ # define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */ # define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */ # define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */ + #define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */ #define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */ #define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */ @@ -199,6 +202,7 @@ # define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */ # define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */ # define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */ + #define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */ #define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT) # define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */ @@ -214,6 +218,7 @@ # define SPI_I2SCFGR_DATLEN_16BIT (0 << SPI_I2SCFGR_DATLEN_SHIFT) /* 00: 16-bit data length */ # define SPI_I2SCFGR_DATLEN_8BIT (1 << SPI_I2SCFGR_DATLEN_SHIFT) /* 01: 24-bit data length */ # define SPI_I2SCFGR_DATLEN_32BIT (2 << SPI_I2SCFGR_DATLEN_SHIFT) /* 10: 32-bit data length */ + #define SPI_I2SCFGR_CKPOL (1 << 3) /* Bit 3: Steady state clock polarity */ #define SPI_I2SCFGR_I2SSTD_SHIFT (4) /* Bit 4-5: I2S standard selection */ #define SPI_I2SCFGR_I2SSTD_MASK (3 << SPI_I2SCFGR_I2SSTD_SHIFT) @@ -221,6 +226,7 @@ # define SPI_I2SCFGR_I2SSTD_MSB (1 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */ # define SPI_I2SCFGR_I2SSTD_LSB (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */ # define SPI_I2SCFGR_I2SSTD_PCM (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */ + #define SPI_I2SCFGR_PCMSYNC (1 << 7) /* Bit 7: PCM frame synchronization */ #define SPI_I2SCFGR_I2SCFG_SHIFT (8) /* Bit 8-9: I2S configuration mode */ #define SPI_I2SCFGR_I2SCFG_MASK (3 << SPI_I2SCFGR_I2SCFG_SHIFT) @@ -228,6 +234,7 @@ # define SPI_I2SCFGR_I2SCFG_SRX (1 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 01: Slave - receive */ # define SPI_I2SCFGR_I2SCFG_MTX (2 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 10: Master - transmit */ # define SPI_I2SCFGR_I2SCFG_MRX (3 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 11: Master - receive */ + #define SPI_I2SCFGR_I2SE (1 << 10) /* Bit 10: I2S Enable */ #define SPI_I2SCFGR_I2SMOD (1 << 11) /* Bit 11: I2S mode selection */ #define SPI_I2SCFGR_ASTRTEN (1 << 12) /* Bit 12: Asynchronous start enable */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h index babd32e3f14..be3e801f0c3 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_UART_H #define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_UART_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ #define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ @@ -48,7 +48,7 @@ #define STM32_USART_RDR_OFFSET 0x0024 /* Receive data register */ #define STM32_USART_TDR_OFFSET 0x0028 /* Transmit data register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #if STM32F7_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) @@ -170,7 +170,7 @@ # define STM32_UART8_TDR (STM32_UART8_BASE+STM32_USART_TDR_OFFSET) #endif -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* Control register 1 */ @@ -217,6 +217,7 @@ # define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ # define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ # define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ + #define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ #define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */ #define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */ @@ -230,6 +231,7 @@ # define USART_CR2_ABRMOD_FALL (1 << USART_CR2_ABRMOD_SHIFT) /* Falling edge measurement */ # define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 0x7F frame detection */ # define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 0x55 frame detection */ + #define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */ #define USART_CR2_ADD4L_SHIFT (24) /* Bits 24-27: Address[3:0]:of the USART node */ #define USART_CR2_ADD4L_MASK (15 << USART_CR2_ADD4L_SHIFT) @@ -291,6 +293,7 @@ # define USART_RTOR_RTO(n) ((uint32_t)(n) << USART_RTOR_RTO_SHIFT) #define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block Length */ #define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT) + # define USART_RTOR_BLEN(n) ((uint32_t)(n) << USART_RTOR_BLEN_SHIFT) /* Request register */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h index aed912138ce..1d65d2feddd 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM327_CHIP_STM32F74XX75XX_FLASH_H #define __ARCH_ARM_SRC_STM327_CHIP_STM32F74XX75XX_FLASH_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Flash size is known from the chip selection: * * When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on the chip - * part number. This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x + * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on + * the chip part number. + * This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x * * Parts STM32F74xxE have 512Kb of FLASH * Parts STM32F74xxG have 1024Kb of FLASH @@ -94,7 +95,7 @@ _K(256), _K(256), _K(256), _K(256)} #endif -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_FLASH_ACR_OFFSET 0x0000 #define STM32_FLASH_KEYR_OFFSET 0x0004 @@ -104,7 +105,7 @@ #define STM32_FLASH_OPTCR_OFFSET 0x0014 #define STM32_FLASH_OPTCR1_OFFSET 0x0018 -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) #define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) @@ -114,7 +115,8 @@ #define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET) #define STM32_FLASH_OPTCR1 (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR1_OFFSET) -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ + /* Flash Access Control Register (ACR) */ #define FLASH_ACR_LATENCY_SHIFT (0) /* Bits 0-1: Latency */ @@ -128,6 +130,7 @@ # define FLASH_ACR_LATENCY_5 (5 << FLASH_ACR_LATENCY_SHIFT) /* 101: Five wait states */ # define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 110: Six wait states */ # define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 111: Seven wait states */ + #define FLASH_ACR_PRFTEN (1 << 8) /* FLASH prefetch enable */ #define FLASH_ACR_ARTEN (1 << 9) /* Bit 9: ART Accelerator Enable */ #define FLASH_ACR_ARTRST (1 << 11) /* Bit 11: ART Accelerator reset */ @@ -150,12 +153,14 @@ #define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */ #define FLASH_CR_SNB_MASK (0x1f << FLASH_CR_SNB_SHIFT) # define FLASH_CR_SNB(n) (((uint32_t)((n) % 12) << FLASH_CR_SNB_SHIFT) | ((n / 12) << 7)) /* Sector n, n=0..23 */ + #define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */ #define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT) # define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* Program x8 */ # define FLASH_CR_PSIZE_X16 (1 << FLASH_CR_PSIZE_SHIFT) /* Program x16 */ # define FLASH_CR_PSIZE_X32 (2 << FLASH_CR_PSIZE_SHIFT) /* Program x32 */ # define FLASH_CR_PSIZE_X64 (3 << FLASH_CR_PSIZE_SHIFT) /* Program x64 */ + #define FLASH_CR_STRT (1 << 16) /* Bit 16: Start Erase */ #define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */ #define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */ @@ -172,6 +177,7 @@ # define FLASH_OPTCR_VBOR2 (1 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 2 */ # define FLASH_OPTCR_VBOR1 (2 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 1 */ # define FLASH_OPTCR_VBOR0 (3 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR off */ + #define FLASH_OPTCR_USER_SHIFT (4) /* Bits 5-7: User option bytes */ #define FLASH_OPTCR_USER_MASK (15 << FLASH_OPTCR_USER_SHIFT) # define FLASH_OPTCR_WWDG_SW (1 << 4) /* Bit 4: WWDG_SW */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h index b270f2b5673..6bef5b110c7 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XXX77XXX_MEMORYMAP_H #define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XXX77XXX_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* STM32F76XXX STM32F77XXX Address Blocks *******************************************/ +/* STM32F76XXX STM32F77XXX Address Blocks ***********************************/ #define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ #define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ @@ -52,7 +52,7 @@ #define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) #define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FMC_BANK1) -/* Code Base Addresses **************************************************************/ +/* Code Base Addresses ******************************************************/ #define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ #define STM32_INSTRAM_BASE 0x00000000 /* 0x00000000-0x00003fff: Instruction RAM (ITCM-RAM) */ @@ -63,8 +63,7 @@ #define STM32_FLASH_BASE STM32_FLASH_AXIM #define STM32_OPTIONS_BASE 0x1fff0000 /* 0x1ff00000-0x1fff001f: Option bytes (AXIM) */ -/* Information Addresses ************************************************************/ - +/* Information Addresses ****************************************************/ #define STM32_SYSMEM_AXIM 0x1ff00000 /* 0x1ff00000-0x1ff0edbf: System memory (AXIM) */ #define STM32_SYSMEM_UID 0x1ff0f420 /* The 96-bit unique device identifier */ @@ -73,13 +72,13 @@ #define STM32_OPT_BASE STM32_OTP_AXIM #define STM32_OPT_SIZE 1056 -/* SRAM Base Addresses **************************************************************/ +/* SRAM Base Addresses ******************************************************/ #define STM32_DTCRAM_BASE 0x20000000 /* 0x20000000-0x2001ffff: DTCM-RAM on TCM interface */ #define STM32_SRAM1_BASE 0x20020000 /* 0x20020000-0x2007bfff: System SRAM1 */ #define STM32_SRAM2_BASE 0x2007c000 /* 0x2007c000-0x2007ffff: System SRAM2 */ -/* Peripheral Base Addresses ********************************************************/ +/* Peripheral Base Addresses ************************************************/ #define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40007fff: APB1 */ #define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40016bff: APB2 */ @@ -87,7 +86,7 @@ #define STM32_AHB2_BASE 0x50000000 /* 0x50000000-0x5003ffff: AHB2 */ #define STM32_AHB3_BASE 0x60000000 /* 0x60000000-0xdfffffff: AHB3 */ -/* APB1 Base Addresses **************************************************************/ +/* APB1 Base Addresses ******************************************************/ #define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff: TIM2 */ #define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff: TIM3 */ @@ -124,7 +123,7 @@ #define STM32_UART7_BASE 0x40007800 /* 0x40007800-0x40007bff: UART7 */ #define STM32_UART8_BASE 0x40007c00 /* 0x40007c00-0x40007fff: UART8 */ -/* APB2 Base Addresses **************************************************************/ +/* APB2 Base Addresses ******************************************************/ #define STM32_TIM1_BASE 0x40010000 /* 0x40010000-0x400103ff: TIM1 */ #define STM32_TIM8_BASE 0x40010400 /* 0x40010400-0x400107ff: TIM8 */ @@ -153,7 +152,7 @@ #define STM32_DFSDM1_BASE 0x40017400 /* 0x40017400-0x400174ff: DFSDM1 */ #define STM32_MDIOS_BASE 0x40017800 /* 0x40017800-0x40017bff: MDIOS */ -/* AHB1 Base Addresses **************************************************************/ +/* AHB1 Base Addresses ******************************************************/ #define STM32_GPIOA_BASE 0x40020000 /* 0x40020000-0x400203ff: GPIOA */ #define STM32_GPIOB_BASE 0x40020400 /* 0x40020400-0x400207ff: GPIOB */ @@ -176,7 +175,7 @@ #define STM32_DMA2D_BASE 0x4002b000 /* 0x4002b000-0x4002Bbff: Chrom-ART (DMA2D) */ #define STM32_USBOTGHS_BASE 0x40040000 /* 0x40040000-0x4007ffff: USB OTG HS */ -/* AHB2 Base Addresses **************************************************************/ +/* AHB2 Base Addresses ******************************************************/ #define STM32_USBOTGFS_BASE 0x50000000 /* 0x50000000-0x5003ffff: USB OTG FS */ #define STM32_DCMI_BASE 0x50050000 /* 0x50050000-0x500503ff: DCMI */ @@ -185,7 +184,7 @@ #define STM32_HASH_BASE 0x50060400 /* 0x50060400-0x500607ff: HASH */ #define STM32_RNG_BASE 0x50060800 /* 0x50060800-0x50060bff: RNG */ -/* AHB3 Base Addresses **************************************************************/ +/* AHB3 Base Addresses ******************************************************/ #define STM32_FMCBANK1_BASE 0x60000000 /* 0x60000000-0x6fffffff: FMC bank 1 */ #define STM32_FMCBANK2_BASE 0x70000000 /* 0x70000000-0x7fffffff: FMC bank 2 */ @@ -196,9 +195,10 @@ #define STM32_FMCBANK5_BASE 0xc0000000 /* 0xc0000000-0xcfffffff: FMC bank 5 */ #define STM32_FMCBANK6_BASE 0xd0000000 /* 0xd0000000-0xdfffffff: FMC bank 6 */ -/* Cortex-M7 Base Addresses *********************************************************/ -/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this - * address range +/* Cortex-M7 Base Addresses *************************************************/ + +/* Other registers -- + * see armv7-m/nvic.h for standard Cortex-M3 registers in this address range */ #define STM32_DEBUGMCU_BASE 0xe0042000 diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h index b46013a0c05..bfdab02a292 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PINMAP_H #define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,28 +31,30 @@ #if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Alternate Pin Functions. All members of the STM32F76|7xxx family share the same - * pin multiplexing (although they may differ in the pins physically available). +/* Alternate Pin Functions. + * All members of the STM32F76|7xxx family share the same pin multiplexing + *(although they may differ in the pins physically available). * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. - * Drivers, however, will use the pin selection without the numeric suffix. + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. * Additional definitions are required in the board.h file. For example, if - * CAN1_RX connects vis PA11 on some board, then the following definitions should - * appear in the board.h header file for that board: + * CAN1_RX connects vis PA11 on some board, then the following definitions + * should should appear in the board.h header file for that board: * * #define GPIO_CAN1_RX GPIO_CAN1_RX_1 * * The driver will then automatically configure PA11 as the CAN1 RX pin. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * open-drain/push-pull, and pull-up/down! Just the basics are defined for most - * pins in this file. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! + * Just the basics are defined for most pins in this file. */ /* ADC */ @@ -914,8 +916,8 @@ /* SD/MMC * * Note that the below configures GPIO_SPEED_50MHz I/O, that means for using - * the SDIO that you must enable I/O Compensation via the configuration option - * CONFIG_STM32F7_SYSCFG_IOCOMPENSATION=y. + * the SDIO that you must enable I/O Compensation via the configuration + * option CONFIG_STM32F7_SYSCFG_IOCOMPENSATION=y. */ #define GPIO_SDMMC1_CK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN12) @@ -944,7 +946,6 @@ #define GPIO_SDMMC2_D6 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) #define GPIO_SDMMC2_D7 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) - /* SPDIFRX */ #define GPIO_SPDIFRX_IN0_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTG|GPIO_PIN11) diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h index 2044eb9c50e..5aff08e16ab 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,38 +16,38 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PWR_H #define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PWR_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ #define STM32_PWR_CSR1_OFFSET 0x0004 /* Power control/status register 1 */ #define STM32_PWR_CR2_OFFSET 0x0008 /* Power control register 1 */ #define STM32_PWR_CSR2_OFFSET 0x000c /* Power control/status register 1 */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET) #define STM32_PWR_CSR1 (STM32_PWR_BASE+STM32_PWR_CSR1_OFFSET) #define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET) #define STM32_PWR_CSR2 (STM32_PWR_BASE+STM32_PWR_CSR2_OFFSET) -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* Power control register 1 */ @@ -65,6 +65,7 @@ # define PWR_CR1_2p7V (5 << PWR_CR1_PLS_SHIFT) /* 101: 2.7V */ # define PWR_CR1_2p8V (6 << PWR_CR1_PLS_SHIFT) /* 110: 2.8V */ # define PWR_CR1_2p9V (7 << PWR_CR1_PLS_SHIFT) /* 111: 2.9V */ + #define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ #define PWR_CR1_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */ #define PWR_CR1_LPUDS (1 << 10) /* Bit 10: Low-power regulator in deepsleep under-drive mode */ @@ -75,6 +76,7 @@ # define PWR_CR1_VOS_SCALE_3 (1 << PWR_CR1_VOS_SHIFT) /* Fmax = 144MHz */ # define PWR_CR1_VOS_SCALE_2 (2 << PWR_CR1_VOS_SHIFT) /* Fmax = 168/180MHz */ # define PWR_CR1_VOS_SCALE_1 (3 << PWR_CR1_VOS_SHIFT) /* Fmax = 180/216MHz */ + #define PWR_CR1_ODEN (1 << 16) /* Bit 16: Over Drive enable */ #define PWR_CR1_ODSWEN (1 << 17) /* Bit 17: Over Drive switch enabled */ #define PWR_CR1_UDEN_SHIFT (18) /* Bits 18-19: Under-drive enable in stop mode */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h index 5eae7de154a..9e8b7c2ba3a 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_RCC_H #define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_RCC_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ #define STM32_RCC_PLLCFG_OFFSET 0x0004 /* PLL configuration register */ @@ -62,7 +62,7 @@ #define STM32_RCC_DCKCFGR1_OFFSET 0x008c /* Dedicated clocks configuration register 1 */ #define STM32_RCC_DCKCFGR2_OFFSET 0x0090 /* Dedicated clocks configuration register 2 */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) #define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) @@ -91,7 +91,7 @@ #define STM32_RCC_DCKCFGR1 (STM32_RCC_BASE+STM32_RCC_DCKCFGR1_OFFSET) #define STM32_RCC_DCKCFGR2 (STM32_RCC_BASE+STM32_RCC_DCKCFGR2_OFFSET) -/* Register Bitfield Definitions ********************************************************************/ +/* Register Bitfield Definitions ********************************************/ /* Clock control register */ @@ -118,16 +118,20 @@ * input clock divider */ #define RCC_PLLCFG_PLLM_MASK (0x3f << RCC_PLLCFG_PLLM_SHIFT) # define RCC_PLLCFG_PLLM(n) ((n) << RCC_PLLCFG_PLLM_SHIFT) /* n = 2..63 */ + #define RCC_PLLCFG_PLLN_SHIFT (6) /* Bits 6-14: Main PLL (PLL) VCO multiplier */ #define RCC_PLLCFG_PLLN_MASK (0x1ff << RCC_PLLCFG_PLLN_SHIFT) # define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 2..432 */ + #define RCC_PLLCFG_PLLP_SHIFT (16) /* Bits 16-17: Main PLL (PLL) main system clock divider */ #define RCC_PLLCFG_PLLP_MASK (3 << RCC_PLLCFG_PLLP_SHIFT) # define RCC_PLLCFG_PLLP(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLP_SHIFT) /* n=2,4,6,8 */ + # define RCC_PLLCFG_PLLP_2 (0 << RCC_PLLCFG_PLLP_SHIFT) /* 00: PLLP = 2 */ # define RCC_PLLCFG_PLLP_4 (1 << RCC_PLLCFG_PLLP_SHIFT) /* 01: PLLP = 4 */ # define RCC_PLLCFG_PLLP_6 (2 << RCC_PLLCFG_PLLP_SHIFT) /* 10: PLLP = 6 */ # define RCC_PLLCFG_PLLP_8 (3 << RCC_PLLCFG_PLLP_SHIFT) /* 11: PLLP = 8 */ + #define RCC_PLLCFG_PLLSRC (1 << 22) /* Bit 22: Main PLL(PLL) and audio PLL (PLLI2S) * entry clock source */ # define RCC_PLLCFG_PLLSRC_HSI (0) @@ -150,22 +154,25 @@ # define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 00: HSI selected as system clock */ # define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */ # define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */ + #define RCC_CFGR_SWS_SHIFT (2) /* Bits 2-3: System Clock Switch Status */ #define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT) # define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */ # define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */ # define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */ + #define RCC_CFGR_HPRE_SHIFT (4) /* Bits 4-7: AHB prescaler */ #define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT) -# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ -# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ -# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ +# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ +# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ +# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ # define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */ # define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */ # define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */ # define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */ # define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */ # define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */ + #define RCC_CFGR_PPRE1_SHIFT (10) /* Bits 10-12: APB Low speed prescaler (APB1) */ #define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT) # define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */ @@ -173,6 +180,7 @@ # define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */ # define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */ # define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */ + #define RCC_CFGR_PPRE2_SHIFT (13) /* Bits 13-15: APB High speed prescaler (APB2) */ #define RCC_CFGR_PPRE2_MASK (7 << RCC_CFGR_PPRE2_SHIFT) # define RCC_CFGR_PPRE2_HCLK (0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK not divided */ @@ -180,15 +188,18 @@ # define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */ # define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */ # define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */ + #define RCC_CFGR_RTCPRE_SHIFT (16) /* Bits 16-20: APB High speed prescaler (APB2) */ #define RCC_CFGR_RTCPRE_MASK (31 << RCC_CFGR_RTCPRE_SHIFT) # define RCC_CFGR_RTCPRE(n) ((n) << RCC_CFGR_RTCPRE_SHIFT) /* HSE/n, n=1..31 */ + #define RCC_CFGR_MCO1_SHIFT (21) /* Bits 21-22: Microcontroller Clock Output */ #define RCC_CFGR_MCO1_MASK (3 << RCC_CFGR_MCO1_SHIFT) # define RCC_CFGR_MCO1_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 00: HSI clock selected */ # define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 01: LSE oscillator selected */ # define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 10: HSE oscillator clock selected */ # define RCC_CFGR_MCO1_PLL (3 << RCC_CFGR_MCO1_SHIFT) /* 11: PLL clock selected */ + #define RCC_CFGR_I2SSRC (1 << 23) /* Bit 23: I2S clock selection */ #define RCC_CFGR_MCO1PRE_SHIFT (24) /* Bits 24-26: MCO1 prescaler */ #define RCC_CFGR_MCO1PRE_MASK (7 << RCC_CFGR_MCO1PRE_SHIFT) @@ -197,6 +208,7 @@ # define RCC_CFGR_MCO1PRE_DIV3 (5 << RCC_CFGR_MCO1PRE_SHIFT) /* 101: division by 3 */ # define RCC_CFGR_MCO1PRE_DIV4 (6 << RCC_CFGR_MCO1PRE_SHIFT) /* 110: division by 4 */ # define RCC_CFGR_MCO1PRE_DIV5 (7 << RCC_CFGR_MCO1PRE_SHIFT) /* 111: division by 5 */ + #define RCC_CFGR_MCO2PRE_SHIFT (27) /* Bits 27-29: MCO2 prescaler */ #define RCC_CFGR_MCO2PRE_MASK (7 << RCC_CFGR_MCO2PRE_SHIFT) # define RCC_CFGR_MCO2PRE_NONE (0 << RCC_CFGR_MCO2PRE_SHIFT) /* 0xx: no division */ @@ -204,6 +216,7 @@ # define RCC_CFGR_MCO2PRE_DIV3 (5 << RCC_CFGR_MCO2PRE_SHIFT) /* 101: division by 3 */ # define RCC_CFGR_MCO2PRE_DIV4 (6 << RCC_CFGR_MCO2PRE_SHIFT) /* 110: division by 4 */ # define RCC_CFGR_MCO2PRE_DIV5 (7 << RCC_CFGR_MCO2PRE_SHIFT) /* 111: division by 5 */ + #define RCC_CFGR_MCO2_SHIFT (30) /* Bits 30-31: Microcontroller clock output 2 */ #define RCC_CFGR_MCO2_MASK (3 << RCC_CFGR_MCO2_SHIFT) # define RCC_CFGR_MCO2_SYSCLK (0 << RCC_CFGR_MCO2_SHIFT) /* 00: System clock (SYSCLK) selected */ @@ -366,7 +379,7 @@ /* AHB3 Peripheral Clock enable register */ -#define RCC_AHB3ENR_FMCEN (1 << 0) /* Bit 0: Flexible static memory controller module clock enable */ +#define RCC_AHB3ENR_FMCEN (1 << 0) /* Bit 0: Flexible static memory controller module clock enable */ #define RCC_AHB3ENR_QSPIEN (1 << 1) /* Bit 1: Quad SPI memory controller clock enable */ /* APB1 Peripheral Clock enable register */ @@ -545,12 +558,14 @@ # define RCC_BDCR_LSEDRV_MEDHI (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium high driving capability */ # define RCC_BDCR_LSEDRV_MEDLO (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium low driving capability */ # define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: High driving capability */ + #define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ #define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) # define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ # define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ # define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ # define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */ + #define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ #define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */ @@ -640,84 +655,100 @@ # define RCC_DCKCFGR2_USART1SEL_SYSCLK (1 << RCC_DCKCFGR2_USART1SEL_SHIFT) /* System clock is selected as USART 1 clock */ # define RCC_DCKCFGR2_USART1SEL_HSI (2 << RCC_DCKCFGR2_USART1SEL_SHIFT) /* HSI clock is selected as USART 1 clock */ # define RCC_DCKCFGR2_USART1SEL_LSE (3 << RCC_DCKCFGR2_USART1SEL_SHIFT) /* LSE clock is selected as USART 1 clock */ + #define RCC_DCKCFGR2_USART2SEL_SHIFT (2) /* Bits 2-3: USART 2 clock source selection */ #define RCC_DCKCFGR2_USART2SEL_MASK (3 << RCC_DCKCFGR2_USART2SEL_SHIFT) # define RCC_DCKCFGR2_USART2SEL_APB (0 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* APB1 clock (PCLK1) is selected as USART 2 clock */ # define RCC_DCKCFGR2_USART2SEL_SYSCLK (1 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* System clock is selected as USART 2 clock */ # define RCC_DCKCFGR2_USART2SEL_HSI (2 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* HSI clock is selected as USART 2 clock */ # define RCC_DCKCFGR2_USART2SEL_LSE (3 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* LSE clock is selected as USART 2 clock */ + #define RCC_DCKCFGR2_UART4SEL_SHIFT (6) /* Bits 6-7: UART 4 clock source selection */ #define RCC_DCKCFGR2_UART4SEL_MASK (3 << RCC_DCKCFGR2_UART4SEL_SHIFT) # define RCC_DCKCFGR2_UART4SEL_APB (0 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 4 clock */ # define RCC_DCKCFGR2_UART4SEL_SYSCLK (1 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* System clock is selected as UART 4 clock */ # define RCC_DCKCFGR2_UART4SEL_HSI (2 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* HSI clock is selected as UART 4 clock */ # define RCC_DCKCFGR2_UART4SEL_LSE (3 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* LSE clock is selected as UART 4 clock */ + #define RCC_DCKCFGR2_UART5SEL_SHIFT (8) /* Bits 8-9: UART 5 clock source selection */ #define RCC_DCKCFGR2_UART5SEL_MASK (3 << RCC_DCKCFGR2_UART5SEL_SHIFT) # define RCC_DCKCFGR2_UART5SEL_APB (0 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 5 clock */ # define RCC_DCKCFGR2_UART5SEL_SYSCLK (1 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* System clock is selected as UART 5 clock */ # define RCC_DCKCFGR2_UART5SEL_HSI (2 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* HSI clock is selected as UART 5 clock */ # define RCC_DCKCFGR2_UART5SEL_LSE (3 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* LSE clock is selected as UART 5 clock */ + #define RCC_DCKCFGR2_USART6SEL_SHIFT (10) /* Bits 10-11: USART 6 clock source selection */ #define RCC_DCKCFGR2_USART6SEL_MASK (3 << RCC_DCKCFGR2_USART6SEL_SHIFT) # define RCC_DCKCFGR2_USART6SEL_APB (0 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* APB2 clock (PCLK2) is selected as USART 6 clock */ # define RCC_DCKCFGR2_USART6SEL_SYSCLK (1 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* System clock is selected as USART 6 clock */ # define RCC_DCKCFGR2_USART6SEL_HSI (2 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* HSI clock is selected as USART 6 clock */ # define RCC_DCKCFGR2_USART6SEL_LSE (3 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* LSE clock is selected as USART 6 clock */ + #define RCC_DCKCFGR2_UART7SEL_SHIFT (12) /* Bits 12-13: UART 7 clock source selection */ #define RCC_DCKCFGR2_UART7SEL_MASK (3 << RCC_DCKCFGR2_UART7SEL_SHIFT) # define RCC_DCKCFGR2_UART7SEL_APB (0 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 7 clock */ # define RCC_DCKCFGR2_UART7SEL_SYSCLK (1 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* System clock is selected as UART 7 clock */ # define RCC_DCKCFGR2_UART7SEL_HSI (2 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* HSI clock is selected as UART 7 clock */ # define RCC_DCKCFGR2_UART7SEL_LSE (3 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* LSE clock is selected as UART 7 clock */ + #define RCC_DCKCFGR2_UART8SEL_SHIFT (14) /* Bits 14-15: UART 8 clock source selection */ #define RCC_DCKCFGR2_UART8SEL_MASK (3 << RCC_DCKCFGR2_UART8SEL_SHIFT) # define RCC_DCKCFGR2_UART8SEL_APB (0 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 8 clock */ # define RCC_DCKCFGR2_UART8SEL_SYSCLK (1 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* System clock is selected as UART 8 clock */ # define RCC_DCKCFGR2_UART8SEL_HSI (2 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* HSI clock is selected as UART 8 clock */ # define RCC_DCKCFGR2_UART8SEL_LSE (3 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* LSE clock is selected as UART 8 clock */ + #define RCC_DCKCFGR2_I2C1SEL_SHIFT (16) /* Bits 16-17: I2C1 clock source selection */ #define RCC_DCKCFGR2_I2C1SEL_MASK (3 << RCC_DCKCFGR2_I2C1SEL_SHIFT) # define RCC_DCKCFGR2_I2C1SEL_APB (0 << RCC_DCKCFGR2_I2C1SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 1 clock */ # define RCC_DCKCFGR2_I2C1SEL_SYSCLK (1 << RCC_DCKCFGR2_I2C1SEL_SHIFT) /* System clock is selected as I2C 1 clock */ # define RCC_DCKCFGR2_I2C1SEL_HSI (2 << RCC_DCKCFGR2_I2C1SEL_SHIFT) /* HSI clock is selected as I2C 1 clock */ + #define RCC_DCKCFGR2_I2C2SEL_SHIFT (18) /* Bits 18-19: I2C2 clock source selection */ #define RCC_DCKCFGR2_I2C2SEL_MASK (3 << RCC_DCKCFGR2_I2C2SEL_SHIFT) # define RCC_DCKCFGR2_I2C2SEL_APB (0 << RCC_DCKCFGR2_I2C2SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 2 clock */ # define RCC_DCKCFGR2_I2C2SEL_SYSCLK (1 << RCC_DCKCFGR2_I2C2SEL_SHIFT) /* System clock is selected as I2C 2 clock */ # define RCC_DCKCFGR2_I2C2SEL_HSI (2 << RCC_DCKCFGR2_I2C2SEL_SHIFT) /* HSI clock is selected as I2C 2 clock */ + #define RCC_DCKCFGR2_I2C3SEL_SHIFT (20) /* Bits 20-21: I2C3 clock source selection */ #define RCC_DCKCFGR2_I2C3SEL_MASK (3 << RCC_DCKCFGR2_I2C3SEL_SHIFT) # define RCC_DCKCFGR2_I2C3SEL_APB (0 << RCC_DCKCFGR2_I2C3SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 3 clock */ # define RCC_DCKCFGR2_I2C3SEL_SYSCLK (1 << RCC_DCKCFGR2_I2C3SEL_SHIFT) /* System clock is selected as I2C 3 clock */ # define RCC_DCKCFGR2_I2C3SEL_HSI (2 << RCC_DCKCFGR2_I2C3SEL_SHIFT) /* HSI clock is selected as I2C 3 clock */ + #define RCC_DCKCFGR2_I2C4SEL_SHIFT (22) /* Bits 22-23: I2C4 clock source selection */ #define RCC_DCKCFGR2_I2C4SEL_MASK (3 << RCC_DCKCFGR2_I2C4SEL_SHIFT) # define RCC_DCKCFGR2_I2C4SEL_APB (0 << RCC_DCKCFGR2_I2C4SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 4 clock */ # define RCC_DCKCFGR2_I2C4SEL_SYSCLK (1 << RCC_DCKCFGR2_I2C4SEL_SHIFT) /* System clock is selected as I2C 4 clock */ # define RCC_DCKCFGR2_I2C4SEL_HSI (2 << RCC_DCKCFGR2_I2C4SEL_SHIFT) /* HSI clock is selected as I2C 4 clock */ + #define RCC_DCKCFGR2_LPTIM1SEL_SHIFT (24) /* Bits 24-25: Low power timer 1 clock source selection */ #define RCC_DCKCFGR2_LPTIM1SEL_MASK (3 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) # define RCC_DCKCFGR2_LPTIM1SEL_APB (0 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* APB1 clock (PCLK1) is selected as LPTIM 1 clock */ # define RCC_DCKCFGR2_LPTIM1SEL_SYSCLK (1 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* System clock is selected as LPTIM 1 clock */ # define RCC_DCKCFGR2_LPTIM1SEL_HSI (2 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* HSI clock is selected as LPTIM 1 clock */ # define RCC_DCKCFGR2_LPTIM1SEL_LSE (3 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* LSE clock is selected as LPTIM 1 clock */ + #define RCC_DCKCFGR2_CECSEL_SHIFT (26) /* Bit 26: HDMI-CEC clock source selection */ #define RCC_DCKCFGR2_CECSEL_MASK (1 << RCC_DCKCFGR2_CECSEL_SHIFT) # define RCC_DCKCFGR2_CECSEL_LSE (0 << RCC_DCKCFGR2_CECSEL_SHIFT) /* LSE clock is selected as HDMI-CEC clock */ # define RCC_DCKCFGR2_CECSEL_HSI (1 << RCC_DCKCFGR2_CECSEL_SHIFT) /* HSI clock is selected as HDMI-CEC clock */ + #define RCC_DCKCFGR2_CK48MSEL_SHIFT (27) /* Bit 27: 48MHz clock source selection */ #define RCC_DCKCFGR2_CK48MSEL_MASK (1 << RCC_DCKCFGR2_CK48MSEL_SHIFT) # define RCC_DCKCFGR2_CK48MSEL_PLL (0 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /* 48MHz clock from PLL is selected */ -# define RCC_DCKCFGR2_CK48MSEL_PLLSAI (1 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /*48MHz clock from PLLSAI is selected */ +# define RCC_DCKCFGR2_CK48MSEL_PLLSAI (1 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /* 48MHz clock from PLLSAI is selected */ + #define RCC_DCKCFGR2_SDMMCSEL_SHIFT (28) /* Bit 28: SDMMC clock source selection */ #define RCC_DCKCFGR2_SDMMCSEL_MASK (1 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) # define RCC_DCKCFGR2_SDMMCSEL_48MHZ (0 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */ # define RCC_DCKCFGR2_SDMMCSEL_SYSCLK (1 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) /* System clock is selected as SDMMC clock */ + #define RCC_DCKCFGR2_SDMMC2SEL_SHIFT (29) /* Bit 29: SDMMC 2 clock source selection */ #define RCC_DCKCFGR2_SDMMC2SEL_MASK (1 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) # define RCC_DCKCFGR2_SDMMC2SEL_48MHZ (0 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) /* 48 MHz clock is selected as SDMMC 2 clock */ # define RCC_DCKCFGR2_SDMMC2SEL_SYSCLK (1 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) /* System clock is selected as SDMMC 2 clock */ + #define RCC_DCKCFGR2_DSISEL_SHIFT (30) /* Bit 30: DSI clock source selection */ #define RCC_DCKCFGR2_DSISEL_MASK (1 << RCC_DCKCFGR2_DSISEL_SHIFT) # define RCC_DCKCFGR2_DSISEL_PHY (0 << RCC_DCKCFGR2_DSISEL_SHIFT) /* DSI PHY sources DSI clock */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h index de4fddc8dc4..7549eb9963f 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,30 +16,31 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_SYSCFG_H #define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_SYSCFG_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ #define STM32_SYSCFG_PMC_OFFSET 0x0004 /* SYSCFG peripheral mode configuration register */ #define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ + #define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ #define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ #define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ @@ -48,7 +49,7 @@ #define STM32_SYSCFG_CBR_OFFSET 0x001c /* Class B register */ #define STM32_SYSCFG_CMPCR_OFFSET 0x0020 /* Compensation cell control register */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) #define STM32_SYSCFG_PMC (STM32_SYSCFG_BASE+STM32_SYSCFG_PMC_OFFSET) @@ -62,7 +63,7 @@ #define STM32_SYSCFG_CBR (STM32_SYSCFG_BASE+STM32_SYSCFG_CBR_OFFSET) #define STM32_SYSCFG_CMPCR (STM32_SYSCFG_BASE+STM32_SYSCFG_CMPCR_OFFSET) -/* Register Bitfield Definitions ********************************************************************/ +/* Register Bitfield Definitions ********************************************/ /* SYSCFG memory remap register */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h index 700c4a28182..c701d1353cf 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,16 +16,16 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_TIM_H #define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_TIM_H -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ /* Basic Timers - TIM6 and TIM7 */ @@ -39,7 +39,8 @@ #define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5 - * 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 + * 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, + * and TIM14 * timers are 16-bit except for TIM2 and 5 are 32-bit * timers TIM9 and 12 are different then TIM10, TIM11, TIM13, and TIM14 */ @@ -92,7 +93,7 @@ #define STM32_ATIM_AF1_OFFSET 0x0060 /* Alternate function option register 1 (16-bit) */ #define STM32_ATIM_AF2_OFFSET 0x0064 /* Alternate function option register 2 (16-bit) */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ @@ -242,7 +243,6 @@ # define STM32_TIM5_OR (STM32_TIM5_BASE+STM32_GTIM_OR_OFFSET) #endif - /* 16-bit General Timers - TIM9-14 without DMA. Note that (1) these timers * support only a subset of the general timer registers are supported, and * (2) TIM9 and TIM12 differ from the others. @@ -355,7 +355,7 @@ # define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET) #endif -/* Register Bitfield Definitions ********************************************************************/ +/* Register Bitfield Definitions ********************************************/ /* Control register 1 */ @@ -370,12 +370,14 @@ # define ATIM_CR1_CENTER1 (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ # define ATIM_CR1_CENTER2 (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ # define ATIM_CR1_CENTER3 (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ + #define ATIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ #define ATIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock division */ #define ATIM_CR1_CKD_MASK (3 << ATIM_CR1_CKD_SHIFT) # define ATIM_CR1_TCKINT (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ # define ATIM_CR1_2TCKINT (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ # define ATIM_CR1_4TCKINT (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ + #define ATIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ /* Control register 2 */ @@ -393,6 +395,7 @@ # define ATIM_CR2_MMS_OC2REF (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */ # define ATIM_CR2_MMS_OC3REF (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */ # define ATIM_CR2_MMS_OC4REF (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */ + #define ATIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ #define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ #define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ @@ -434,6 +437,7 @@ # define ATIM_SMCR_GATED (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ # define ATIM_SMCR_TRIGGER (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ # define ATIM_SMCR_EXTCLK1 (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ + #define ATIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */ #define ATIM_SMCR_TS_MASK (7 << ATIM_SMCR_TS_SHIFT) # define ATIM_SMCR_ITR0 (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */ @@ -444,31 +448,34 @@ # define ATIM_SMCR_TI1FP1 (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ # define ATIM_SMCR_T12FP2 (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ # define ATIM_SMCR_ETRF (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ + #define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ #define ATIM_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ #define ATIM_SMCR_ETF_MASK (0x0f << ATIM_SMCR_ETF_SHIFT) -# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ -# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define ATIM_SMCR_FCKINT4 (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define ATIM_SMCR_FCKINT8 (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define ATIM_SMCR_FDTSd26 (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define ATIM_SMCR_FDTSd28 (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define ATIM_SMCR_FDTSd46 (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define ATIM_SMCR_FDTSd48 (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define ATIM_SMCR_FDTSd86 (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define ATIM_SMCR_FDTSd88 (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ +# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_SMCR_FCKINT4 (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_SMCR_FCKINT8 (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_SMCR_FDTSd26 (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_SMCR_FDTSd28 (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_SMCR_FDTSd46 (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_SMCR_FDTSd48 (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_SMCR_FDTSd86 (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_SMCR_FDTSd88 (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ # define ATIM_SMCR_FDTSd165 (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ # define ATIM_SMCR_FDTSd166 (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ # define ATIM_SMCR_FDTSd168 (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ # define ATIM_SMCR_FDTSd325 (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ # define ATIM_SMCR_FDTSd326 (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ # define ATIM_SMCR_FDTSd328 (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ + #define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ #define ATIM_SMCR_ETPS_MASK (3 << ATIM_SMCR_ETPS_SHIFT) # define ATIM_SMCR_PSCOFF (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ # define ATIM_SMCR_ETRPd2 (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ # define ATIM_SMCR_ETRPd4 (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ # define ATIM_SMCR_ETRPd8 (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ + #define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ #define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ #define ATIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ @@ -544,7 +551,6 @@ #define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ #define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ - /* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ #define ATIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ @@ -571,7 +577,10 @@ /* Capture/compare mode register 1 -- Input capture mode */ - /* Bits 1-0:(same as output compare mode) */ +/* Bits 1-0: + * (same as output compare mode) + */ + #define ATIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ #define ATIM_CCMR1_IC1PSC_MASK (3 << ATIM_CCMR1_IC1PSC_SHIFT) /* (See common (unshifted) bit field definitions below) */ @@ -637,7 +646,10 @@ /* Capture/compare mode register 2 - Input Capture Mode */ - /* Bits 1-0:(same as output compare mode) */ +/* Bits 1-0: + * (same as output compare mode) + */ + #define ATIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ #define ATIM_CCMR1_IC3PSC_MASK (3 << ATIM_CCMR2_IC3PSC_SHIFT) /* (See common (unshifted) bit field definitions above) */ @@ -669,7 +681,6 @@ #define ATIM_CCMR3_OC5M (1 << 16) /* Bit 16: Output Compare 5 mode - bit 3 */ #define ATIM_CCMR3_OC6M (1 << 24) /* Bit 24: Output Compare 6 mode - bit 3 */ - /* Capture/compare enable register */ #define ATIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ @@ -692,7 +703,6 @@ #define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ #define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ - /* 16-bit counter register */ #define ATIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ @@ -735,6 +745,7 @@ # define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ # define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ # define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */ + #define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ #define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ #define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ @@ -759,6 +770,7 @@ # define ATIM_BDTR_BKF_FDTSd325 (13 << ATIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ # define ATIM_BDTR_BKF_FDTSd326 (14 << ATIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ # define ATIM_BDTR_BKF_FDTSd328 (15 << ATIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ + #define ATIM_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ #define ATIM_BDTR_BK2F_MASK (0xf << ATIM_BDTR_BK2F_SHIFT) # define ATIM_BDTR_BK2F_NOFILT (0 << ATIM_BDTR_BK2F_SHIFT) /* 0000: No filter, BRK 2 acts asynchronously */ @@ -777,9 +789,9 @@ # define ATIM_BDTR_BK2F_FDTSd325 (13 << ATIM_BDTR_BK2F_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ # define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ # define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ -#define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ -#define ATIM_BDTR_BK2P (1 << 1525 /* Bit 25:Break 2 polarity */ +#define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ +#define ATIM_BDTR_BK2P (1 << 1525 /* Bit 25:Break 2 polarity */ /* DMA control register */ @@ -802,12 +814,14 @@ # define GTIM_CR1_CENTER1 (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ # define GTIM_CR1_CENTER2 (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ # define GTIM_CR1_CENTER3 (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ + #define GTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ #define GTIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock Division */ #define GTIM_CR1_CKD_MASK (3 << GTIM_CR1_CKD_SHIFT) # define GTIM_CR1_TCKINT (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */ # define GTIM_CR1_2TCKINT (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */ # define GTIM_CR1_4TCKINT (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */ + #define GTIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ /* Control register 2 (TIM2-5, TIM9-12) */ @@ -825,6 +839,7 @@ # define GTIM_CR2_MMS_OC2REF (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */ # define GTIM_CR2_MMS_OC3REF (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ # define GTIM_CR2_MMS_OC4REF (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ + #define GTIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection (not TIM16) */ #define GTIM_CR2_OIS1 (1 << 8) /* Bit 8: COutput Idle state 1 (OC1 output) (TIM15-17 only) */ #define GTIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) (TIM15-17 only) */ @@ -842,6 +857,7 @@ # define GTIM_SMCR_GATED (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ # define GTIM_SMCR_TRIGGER (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ # define GTIM_SMCR_EXTCLK1 (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ + #define GTIM_SMCR_TS_SHIFT (4) /* Bits 6-4: Trigger Selection */ #define GTIM_SMCR_TS_MASK (7 << GTIM_SMCR_TS_SHIFT) # define GTIM_SMCR_ITR0 (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). TIM1 */ @@ -852,6 +868,7 @@ # define GTIM_SMCR_TI1FP1 (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ # define GTIM_SMCR_TI2FP2 (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ # define GTIM_SMCR_ETRF (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ + #define GTIM_SMCR_MSM (1 << 7) /* Bit 7: Master/Slave mode */ #define GTIM_SMCR_ETF_SHIFT (8) /* Bits 11-8: External Trigger Filter (not TIM15) */ #define GTIM_SMCR_ETF_MASK (0x0f << GTIM_SMCR_ETF_SHIFT) @@ -871,12 +888,14 @@ # define GTIM_SMCR_FDTSd325 (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ # define GTIM_SMCR_FDTSd326 (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ # define GTIM_SMCR_FDTSd328 (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ + #define GTIM_SMCR_ETPS_SHIFT (12) /* Bits 13-12: External Trigger Prescaler (not TIM15) */ #define GTIM_SMCR_ETPS_MASK (3 << GTIM_SMCR_ETPS_SHIFT) # define GTIM_SMCR_PSCOFF (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ # define GTIM_SMCR_ETRPd2 (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ # define GTIM_SMCR_ETRPd4 (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ # define GTIM_SMCR_ETRPd8 (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ + #define GTIM_SMCR_ECE (1 << 14) /* Bit 14: External Clock enable */ #define GTIM_SMCR_ETP (1 << 15) /* Bit 15: External Trigger Polarity */ #define GTIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ @@ -925,7 +944,9 @@ #define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger generation (TIM2-5,9,12&16-17 only) */ #define GTIM_EGR_BG (1 << 7) /* Bit 7: Break generation (TIM15-17 only) */ -/* Capture/compare mode register 1 - Output compare mode (TIM2-5 and TIM9-14) */ +/* Capture/compare mode register 1 - + * Output compare mode (TIM2-5 and TIM9-14) + */ #define GTIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ #define GTIM_CCMR1_CC1S_MASK (3 << GTIM_CCMR1_CC1S_SHIFT) @@ -966,9 +987,14 @@ #define GTIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ #define GTIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ -/* Capture/compare mode register 1 - Input capture mode (TIM2-5 and TIM9-14) */ +/* Capture/compare mode register 1 - + * Input capture mode (TIM2-5 and TIM9-14) + */ + +/* Bits 1-0 + * (Same as Output Compare Mode) + */ - /* Bits 1-0 (Same as Output Compare Mode) */ #define GTIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ #define GTIM_CCMR1_IC1PSC_MASK (3 << GTIM_CCMR1_IC1PSC_SHIFT) /* (See common CCMR Input Capture Prescaler definitions below) */ @@ -1032,7 +1058,10 @@ /* Capture/compare mode register 2 - Input capture mode (TIM2-5 only) */ - /* Bits 1-0 (Same as Output Compare Mode) */ +/* Bits 1-0 + * (Same as Output Compare Mode) + */ + #define GTIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ #define GTIM_CCMR2_IC3PSC_MASK (3 << GTIM_CCMR2_IC3PSC_SHIFT) /* (See common CCMR Input Capture Prescaler definitions below) */ @@ -1082,9 +1111,9 @@ #define TIM2_OR_ITR1_RMP_SHIFT (10) /* Bits 10-11: Internal trigger 1 remap */ #define TIM2_OR_ITR1_RMP_MASK (3 << TIM2_OR_ITR1_RMP_SHIFT) # define TIM2_OR_ITR1_TIM8_TRGOUT (0 << TIM2_OR_ITR1_RMP_SHIFT) /* 00: TIM2_ITR1 input connected to TIM8_TRGOUT */ -# define TIM2_OR_ITR1_PTP (1 << TIM2_OR_ITR1_RMP_SHIFT) /* 01: TIM2_ITR1 input connected to PTP trigger output */ -# define TIM2_OR_ITR1_OTGFSSOF (2 << TIM2_OR_ITR1_RMP_SHIFT) /* 10: TIM2_ITR1 input connected to OTG FS SOF */ -# define TIM2_OR_ITR1_OTGHSSOF (3 << TIM2_OR_ITR1_RMP_SHIFT) /* 11: TIM2_ITR1 input connected to OTG HS SOF */ +# define TIM2_OR_ITR1_PTP (1 << TIM2_OR_ITR1_RMP_SHIFT) /* 01: TIM2_ITR1 input connected to PTP trigger output */ +# define TIM2_OR_ITR1_OTGFSSOF (2 << TIM2_OR_ITR1_RMP_SHIFT) /* 10: TIM2_ITR1 input connected to OTG FS SOF */ +# define TIM2_OR_ITR1_OTGHSSOF (3 << TIM2_OR_ITR1_RMP_SHIFT) /* 11: TIM2_ITR1 input connected to OTG HS SOF */ #define TIM5_OR_TI4_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */ #define TIM5_OR_TI4_RMP_MASK (3 << TIM5_OR_TI4_RMP_SHIFT) @@ -1098,7 +1127,6 @@ # define TIM11_OR_TI1_GPIO (0 << TIM11_OR_TI1_RMP_SHIFT) /* 00-11: TIM11_CH1 input connected to GPIO */ # define TIM11_OR_TI1_HSERTC (3 << TIM11_OR_TI1_RMP_SHIFT) /* 11: TIM11_CH1 input connected to HSE_RTC clock */ - /* Control register 1 */ #define BTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ diff --git a/arch/arm/src/stm32h7/hardware/stm32_axi.h b/arch/arm/src/stm32h7/hardware/stm32_axi.h index 69c633e332c..fb4ce52c5e4 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_axi.h +++ b/arch/arm/src/stm32h7/hardware/stm32_axi.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32h7/hardware/stm32_axi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_AXI_H #define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_AXI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_AXI_PERIPH_ID_4_OFFSET 0x01fd0 /* AXI interconnect peripheral ID4 register */ #define STM32_AXI_PERIPH_ID_0_OFFSET 0x01fe0 /* AXI interconnect peripheral ID0 register */ @@ -82,7 +82,7 @@ #define STM32_AXI_INI5_FN_MOD_OFFSET 0x46108 /* AXI interconnect INI 5 issuing functionality modification register */ #define STM32_AXI_INI6_FN_MOD_OFFSET 0x47108 /* AXI interconnect INI 6 issuing functionality modification register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_AXI_PERIPH_ID_4 (STM32_GPV_BASE + STM32_AXI_PERIPH_ID_4_OFFSET) #define STM32_AXI_PERIPH_ID_0 (STM32_GPV_BASE + STM32_AXI_PERIPH_ID_0_OFFSET) @@ -131,7 +131,7 @@ #define STM32_AXI_INI5_FN_MOD (STM32_GPV_BASE + STM32_AXI_INI5_FN_MOD_OFFSET) #define STM32_AXI_INI6_FN_MOD (STM32_GPV_BASE + STM32_AXI_INI6_FN_MOD_OFFSET) -/* AXI Register Bitfield Definitions *********************************************************/ +/* AXI Register Bitfield Definitions ****************************************/ /* TARG x bus matrix issuing functionality Register */ diff --git a/arch/arm/src/stm32h7/hardware/stm32_rtcc.h b/arch/arm/src/stm32h7/hardware/stm32_rtcc.h index 52884348a63..9dda495cab1 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_rtcc.h +++ b/arch/arm/src/stm32h7/hardware/stm32_rtcc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32h7/hardware/stm32_rtcc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,16 +16,16 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_RTCC_H #define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_RTCC_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */ #define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */ @@ -81,7 +81,7 @@ #define STM32_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */ #define STM32_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_RTC_TR (STM32_RTC_BASE+STM32_RTC_TR_OFFSET) #define STM32_RTC_DR (STM32_RTC_BASE+STM32_RTC_DR_OFFSET) @@ -138,7 +138,7 @@ #define STM32_RTC_BKCOUNT 32 -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* RTC time register */ @@ -191,6 +191,7 @@ # define RTC_CR_WUCKSEL_RTCDIV2 (3 << RTC_CR_WUCKSEL_SHIFT) /* 011: RTC/2 clock is selected */ # define RTC_CR_WUCKSEL_CKSPRE (4 << RTC_CR_WUCKSEL_SHIFT) /* 10x: ck_spre clock is selected */ # define RTC_CR_WUCKSEL_CKSPREADD (6 << RTC_CR_WUCKSEL_SHIFT) /* 11x: ck_spr clock and 216 added WUT counter */ + #define RTC_CR_TSEDGE (1 << 3) /* Bit 3: Timestamp event active edge */ #define RTC_CR_REFCKON (1 << 4) /* Bit 4: Reference clock detection enable (50 or 60 Hz) */ #define RTC_CR_BYPSHAD (1 << 5) /* Bit 5: Bypass the shadow registers */ @@ -214,6 +215,7 @@ # define RTC_CR_OSEL_ALRMA (1 << RTC_CR_OSEL_SHIFT) /* 01: Alarm A output enabled */ # define RTC_CR_OSEL_ALRMB (2 << RTC_CR_OSEL_SHIFT) /* 10: Alarm B output enabled */ # define RTC_CR_OSEL_WUT (3 << RTC_CR_OSEL_SHIFT) /* 11: Wakeup output enabled */ + #define RTC_CR_COE (1 << 23) /* Bit 23: Calibration output enable */ #define RTC_CR_ITSE (1 << 24) /* Bit 24: Timestamp on internal event enable */ @@ -339,7 +341,7 @@ #define RTC_TAMPCR_TAMP3E (1 << 5) /* Bit 5: RTC_TAMP3 detection enable */ #define RTC_TAMPCR_TAMP3TRG (1 << 6) /* Bit 6: Active level for RTC_TAMP3 input */ #define RTC_TAMPCR_TAMPTS (1 << 7) /* Bit 7: Activate timestamp on tamper detection event */ -#define RTC_TAMPCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */ +#define RTC_TAMPCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */ #define RTC_TAMPCR_TAMPFREQ_MASK (7 << RTC_TAMPCR_TAMPFREQ_SHIFT) # define RTC_TAMPCR_TAMPFREQ_DIV32768 (0 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 32768 (1 Hz) */ # define RTC_TAMPCR_TAMPFREQ_DIV16384 (1 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 16384 (2 Hz) */ @@ -349,6 +351,7 @@ # define RTC_TAMPCR_TAMPFREQ_DIV1024 (5 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 1024 (32 Hz) */ # define RTC_TAMPCR_TAMPFREQ_DIV512 (6 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 512 (64 Hz) */ # define RTC_TAMPCR_TAMPFREQ_DIV256 (7 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 256 (128 Hz) */ + #define RTC_TAMPCR_TAMPFLT_SHIFT (11) /* Bits 11-12: RTC_TAMPx filter count */ #define RTC_TAMPCR_TAMPFLT_MASK (3 << RTC_TAMPCR_TAMPFLT_SHIFT) #define RTC_TAMPCR_TAMPPRCH_SHIFT (13) /* Bits 13-14: RTC_TAMPx precharge duration */ @@ -357,6 +360,7 @@ # define RTC_TAMPCR_TAMPPRCH_2CYCLES (1 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 2 RTCCLK cycles */ # define RTC_TAMPCR_TAMPPRCH_4CYCLES (2 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 4 RTCCLK cycles */ # define RTC_TAMPCR_TAMPPRCH_5CYCLES (3 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 8 RTCCLK cycles */ + #define RTC_TAMPCR_TAMPPUDIS (1 << 15) /* Bit 15: RTC_TAMPx pull-up disable */ #define RTC_TAMPCR_TAMP1IE (1 << 16) /* Bit 16: Tamper 1 interrupt enable */ #define RTC_TAMPCR_TAMP1NOERASE (1 << 17) /* Bit 17: Tamper 1 no erase */ diff --git a/arch/arm/src/stm32h7/hardware/stm32_tim.h b/arch/arm/src/stm32h7/hardware/stm32_tim.h index e9e6f008ed7..51cf921f112 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_tim.h +++ b/arch/arm/src/stm32h7/hardware/stm32_tim.h @@ -28,15 +28,15 @@ #include #include "chip.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ /* The STM32H7 family uses STM32 TIMER IP version 2 */ #define HAVE_IP_TIMERS_V2 1 -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ /* Basic Timers - TIM6 and TIM7 */ @@ -50,7 +50,8 @@ #define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5 - * 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 + * 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, + * and TIM14 * timers are 16-bit except for TIM2 and 5 are 32-bit * timers TIM9 and 12 are different then TIM10, TIM11, TIM13, and TIM14 */ @@ -103,7 +104,7 @@ #define STM32_ATIM_AF2_OFFSET 0x0064 /* Alternate function option register 2 (16-bit) */ #define STM32_ATIM_TISEL_OFFSET 0x0068 /* Timer input selection register (32-bit) */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ @@ -371,7 +372,7 @@ # define STM32_TIM7_PSC (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET) # define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET) -/* Register Bitfield Definitions ********************************************************************/ +/* Register Bitfield Definitions ********************************************/ /* Control register 1 */ @@ -386,12 +387,14 @@ # define ATIM_CR1_CENTER1 (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ # define ATIM_CR1_CENTER2 (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ # define ATIM_CR1_CENTER3 (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ + #define ATIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ #define ATIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock division */ #define ATIM_CR1_CKD_MASK (3 << ATIM_CR1_CKD_SHIFT) # define ATIM_CR1_TCKINT (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ # define ATIM_CR1_2TCKINT (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ # define ATIM_CR1_4TCKINT (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ + #define ATIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ /* Control register 2 */ @@ -409,6 +412,7 @@ # define ATIM_CR2_MMS_OC2REF (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */ # define ATIM_CR2_MMS_OC3REF (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */ # define ATIM_CR2_MMS_OC4REF (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */ + #define ATIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ #define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ #define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ @@ -450,6 +454,7 @@ # define ATIM_SMCR_GATED (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ # define ATIM_SMCR_TRIGGER (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ # define ATIM_SMCR_EXTCLK1 (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ + #define ATIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */ #define ATIM_SMCR_TS_MASK (7 << ATIM_SMCR_TS_SHIFT) # define ATIM_SMCR_ITR0 (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */ @@ -460,31 +465,34 @@ # define ATIM_SMCR_TI1FP1 (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ # define ATIM_SMCR_T12FP2 (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ # define ATIM_SMCR_ETRF (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ + #define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ #define ATIM_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ #define ATIM_SMCR_ETF_MASK (0x0f << ATIM_SMCR_ETF_SHIFT) -# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ -# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define ATIM_SMCR_FCKINT4 (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define ATIM_SMCR_FCKINT8 (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define ATIM_SMCR_FDTSd26 (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define ATIM_SMCR_FDTSd28 (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define ATIM_SMCR_FDTSd46 (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define ATIM_SMCR_FDTSd48 (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define ATIM_SMCR_FDTSd86 (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define ATIM_SMCR_FDTSd88 (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ +# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_SMCR_FCKINT4 (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_SMCR_FCKINT8 (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_SMCR_FDTSd26 (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_SMCR_FDTSd28 (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_SMCR_FDTSd46 (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_SMCR_FDTSd48 (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_SMCR_FDTSd86 (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_SMCR_FDTSd88 (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ # define ATIM_SMCR_FDTSd165 (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ # define ATIM_SMCR_FDTSd166 (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ # define ATIM_SMCR_FDTSd168 (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ # define ATIM_SMCR_FDTSd325 (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ # define ATIM_SMCR_FDTSd326 (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ # define ATIM_SMCR_FDTSd328 (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ + #define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ #define ATIM_SMCR_ETPS_MASK (3 << ATIM_SMCR_ETPS_SHIFT) # define ATIM_SMCR_PSCOFF (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ # define ATIM_SMCR_ETRPd2 (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ # define ATIM_SMCR_ETRPd4 (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ # define ATIM_SMCR_ETRPd8 (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ + #define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ #define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ #define ATIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ @@ -586,7 +594,10 @@ /* Capture/compare mode register 1 -- Input capture mode */ - /* Bits 1-0:(same as output compare mode) */ +/* Bits 1-0: + * (same as output compare mode) + */ + #define ATIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ #define ATIM_CCMR1_IC1PSC_MASK (3 << ATIM_CCMR1_IC1PSC_SHIFT) /* (See common (unshifted) bit field definitions below) */ @@ -652,7 +663,10 @@ /* Capture/compare mode register 2 - Input Capture Mode */ - /* Bits 1-0:(same as output compare mode) */ +/* Bits 1-0: + * (same as output compare mode) + */ + #define ATIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ #define ATIM_CCMR1_IC3PSC_MASK (3 << ATIM_CCMR2_IC3PSC_SHIFT) /* (See common (unshifted) bit field definitions above) */ @@ -742,12 +756,14 @@ #define ATIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ #define ATIM_BDTR_DTG_MASK (0xff << ATIM_BDTR_DTG_SHIFT) + #define ATIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ #define ATIM_BDTR_LOCK_MASK (3 << ATIM_BDTR_LOCK_SHIFT) # define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ # define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ # define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ # define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */ + #define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ #define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ #define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ @@ -772,6 +788,7 @@ # define ATIM_BDTR_BKF_FDTSd325 (13 << ATIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ # define ATIM_BDTR_BKF_FDTSd326 (14 << ATIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ # define ATIM_BDTR_BKF_FDTSd328 (15 << ATIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ + #define ATIM_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ #define ATIM_BDTR_BK2F_MASK (0xf << ATIM_BDTR_BK2F_SHIFT) # define ATIM_BDTR_BK2F_NOFILT (0 << ATIM_BDTR_BK2F_SHIFT) /* 0000: No filter, BRK 2 acts asynchronously */ @@ -790,6 +807,7 @@ # define ATIM_BDTR_BK2F_FDTSd325 (13 << ATIM_BDTR_BK2F_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ # define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ # define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ + #define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ #define ATIM_BDTR_BK2P (1 << 25) /* Bit 25: Break 2 polarity */ @@ -814,12 +832,14 @@ # define GTIM_CR1_CENTER1 (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ # define GTIM_CR1_CENTER2 (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ # define GTIM_CR1_CENTER3 (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ + #define GTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ #define GTIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock Division */ #define GTIM_CR1_CKD_MASK (3 << GTIM_CR1_CKD_SHIFT) # define GTIM_CR1_TCKINT (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */ # define GTIM_CR1_2TCKINT (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */ # define GTIM_CR1_4TCKINT (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */ + #define GTIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ /* Control register 2 (TIM2-5, TIM9-12) */ @@ -837,6 +857,7 @@ # define GTIM_CR2_MMS_OC2REF (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */ # define GTIM_CR2_MMS_OC3REF (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ # define GTIM_CR2_MMS_OC4REF (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ + #define GTIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection (not TIM16) */ #define GTIM_CR2_OIS1 (1 << 8) /* Bit 8: COutput Idle state 1 (OC1 output) (TIM15-17 only) */ #define GTIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) (TIM15-17 only) */ @@ -854,6 +875,7 @@ # define GTIM_SMCR_GATED (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ # define GTIM_SMCR_TRIGGER (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ # define GTIM_SMCR_EXTCLK1 (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ + #define GTIM_SMCR_TS_SHIFT (4) /* Bits 6-4: Trigger Selection */ #define GTIM_SMCR_TS_MASK (7 << GTIM_SMCR_TS_SHIFT) # define GTIM_SMCR_ITR0 (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). TIM1 */ @@ -864,6 +886,7 @@ # define GTIM_SMCR_TI1FP1 (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ # define GTIM_SMCR_TI2FP2 (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ # define GTIM_SMCR_ETRF (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ + #define GTIM_SMCR_MSM (1 << 7) /* Bit 7: Master/Slave mode */ #define GTIM_SMCR_ETF_SHIFT (8) /* Bits 11-8: External Trigger Filter (not TIM15) */ #define GTIM_SMCR_ETF_MASK (0x0f << GTIM_SMCR_ETF_SHIFT) @@ -883,12 +906,14 @@ # define GTIM_SMCR_FDTSd325 (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ # define GTIM_SMCR_FDTSd326 (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ # define GTIM_SMCR_FDTSd328 (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ + #define GTIM_SMCR_ETPS_SHIFT (12) /* Bits 13-12: External Trigger Prescaler (not TIM15) */ #define GTIM_SMCR_ETPS_MASK (3 << GTIM_SMCR_ETPS_SHIFT) # define GTIM_SMCR_PSCOFF (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ # define GTIM_SMCR_ETRPd2 (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ # define GTIM_SMCR_ETRPd4 (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ # define GTIM_SMCR_ETRPd8 (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ + #define GTIM_SMCR_ECE (1 << 14) /* Bit 14: External Clock enable */ #define GTIM_SMCR_ETP (1 << 15) /* Bit 15: External Trigger Polarity */ #define GTIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ @@ -937,7 +962,9 @@ #define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger generation (TIM2-5,9,12&16-17 only) */ #define GTIM_EGR_BG (1 << 7) /* Bit 7: Break generation (TIM15-17 only) */ -/* Capture/compare mode register 1 - Output compare mode (TIM2-5 and TIM9-14) */ +/* Capture/compare mode register 1 - + * Output compare mode (TIM2-5 and TIM9-14) + */ #define GTIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ #define GTIM_CCMR1_CC1S_MASK (3 << GTIM_CCMR1_CC1S_SHIFT) @@ -978,9 +1005,14 @@ #define GTIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ #define GTIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ -/* Capture/compare mode register 1 - Input capture mode (TIM2-5 and TIM9-14) */ +/* Capture/compare mode register 1 - + * Input capture mode (TIM2-5 and TIM9-14) + */ + +/* Bits 1-0 + * (Same as Output Compare Mode) + */ - /* Bits 1-0 (Same as Output Compare Mode) */ #define GTIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ #define GTIM_CCMR1_IC1PSC_MASK (3 << GTIM_CCMR1_IC1PSC_SHIFT) /* (See common CCMR Input Capture Prescaler definitions below) */ @@ -1044,7 +1076,10 @@ /* Capture/compare mode register 2 - Input capture mode (TIM2-5 only) */ - /* Bits 1-0 (Same as Output Compare Mode) */ +/* Bits 1-0 + * (Same as Output Compare Mode) + */ + #define GTIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ #define GTIM_CCMR2_IC3PSC_MASK (3 << GTIM_CCMR2_IC3PSC_SHIFT) /* (See common CCMR Input Capture Prescaler definitions below) */ @@ -1094,9 +1129,9 @@ #define TIM2_OR_ITR1_RMP_SHIFT (10) /* Bits 10-11: Internal trigger 1 remap */ #define TIM2_OR_ITR1_RMP_MASK (3 << TIM2_OR_ITR1_RMP_SHIFT) # define TIM2_OR_ITR1_TIM8_TRGOUT (0 << TIM2_OR_ITR1_RMP_SHIFT) /* 00: TIM2_ITR1 input connected to TIM8_TRGOUT */ -# define TIM2_OR_ITR1_PTP (1 << TIM2_OR_ITR1_RMP_SHIFT) /* 01: TIM2_ITR1 input connected to PTP trigger output */ -# define TIM2_OR_ITR1_OTGFSSOF (2 << TIM2_OR_ITR1_RMP_SHIFT) /* 10: TIM2_ITR1 input connected to OTG FS SOF */ -# define TIM2_OR_ITR1_OTGHSSOF (3 << TIM2_OR_ITR1_RMP_SHIFT) /* 11: TIM2_ITR1 input connected to OTG HS SOF */ +# define TIM2_OR_ITR1_PTP (1 << TIM2_OR_ITR1_RMP_SHIFT) /* 01: TIM2_ITR1 input connected to PTP trigger output */ +# define TIM2_OR_ITR1_OTGFSSOF (2 << TIM2_OR_ITR1_RMP_SHIFT) /* 10: TIM2_ITR1 input connected to OTG FS SOF */ +# define TIM2_OR_ITR1_OTGHSSOF (3 << TIM2_OR_ITR1_RMP_SHIFT) /* 11: TIM2_ITR1 input connected to OTG HS SOF */ #define TIM5_OR_TI4_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */ #define TIM5_OR_TI4_RMP_MASK (3 << TIM5_OR_TI4_RMP_SHIFT) diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h index e5f596393b2..7408e9055f7 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,16 +16,16 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32H7_STM32H7X3XX_I2C_H #define __ARCH_ARM_SRC_STM32H7_STM32H7X3XX_I2C_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ #define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ @@ -39,7 +39,7 @@ #define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ #define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #if STM32H7_NI2C > 0 # define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) @@ -97,7 +97,7 @@ # define STM32_I2C4_TXDR (STM32_I2C4_BASE+STM32_I2C_TXDR_OFFSET) #endif -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* Control register 1 */ @@ -113,6 +113,7 @@ #define I2C_CR1_DNF_MASK (0xf << I2C_CR1_DNF_SHIFT) # define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT) # define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */ + #define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */ #define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */ #define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */ @@ -165,6 +166,7 @@ # define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */ # define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */ # define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */ + #define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */ /* Timing register */ @@ -201,7 +203,6 @@ # define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT) #define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */ - /* Fields unique to the Interrupt and Status register */ #define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */ @@ -215,6 +216,7 @@ #define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT) /* Interrupt and Status register and interrupt clear register */ + /* Common interrupt bits */ #define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h index 8d2a5ed099d..89b6fad6203 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,29 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_SYSCFG_H #define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_SYSCFG_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/stm32_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define STM32_SYSCFG_PMC_OFFSET 0x0004 /* SYSCFG peripheral mode configuration register */ #define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ + #define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ #define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ #define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ @@ -69,7 +70,7 @@ #define STM32_SYSCFG_UR16_OFFSET 0x0340 /* User register 16 */ #define STM32_SYSCFG_UR17_OFFSET 0x0344 /* User register 17 */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define STM32_SYSCFG_PMC (STM32_SYSCFG_BASE + STM32_SYSCFG_PMC_OFFSET) @@ -84,7 +85,7 @@ #define STM32_SYSCFG_CCCR (STM32_SYSCFG_BASE + STM32_SYSCFG_CCCR_OFFSET) #define STM32_SYSCFG_PWRCR (STM32_SYSCFG_BASE + STM32_SYSCFG_PWRCR_OFFSET) -/* Register Bitfield Definitions ********************************************************************/ +/* Register Bitfield Definitions ********************************************/ /* SYSCFG peripheral mode configuration register */ @@ -162,16 +163,19 @@ #define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT) /* Compensation cell control/status register */ + /* REVISIT: Missing bitfield definitions */ #define SYSCFG_CCSR_ /* Compensation cell value register */ + /* REVISIT: Missing bitfield definitions */ #define SYSCFG_CCVR_ /* Compensation cell code register */ + /* REVISIT: Missing bitfield definitions */ #define SYSCFG_CCCR_ @@ -181,6 +185,7 @@ #define SYSCFG_PWRCR_ODEN (1 << 0) /* Bit 0: Overdrive enable, this bit allows to activate the LDO regulator overdrive mode */ /* User registers 0-17 */ + /* REVISIT: Missing bitfield definitions */ #define SYSCFG_UR0_ diff --git a/arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c b/arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c index 958ef1bde5e..528e11dbcd3 100644 --- a/arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c +++ b/arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c @@ -104,8 +104,9 @@ static bool stm32_havesettime(FAR struct rtc_lowerhalf_s *lower); #ifdef CONFIG_RTC_ALARM static int stm32_setalarm(FAR struct rtc_lowerhalf_s *lower, FAR const struct lower_setalarm_s *alarminfo); -static int stm32_setrelative(FAR struct rtc_lowerhalf_s *lower, - FAR const struct lower_setrelative_s *alarminfo); +static int +stm32_setrelative(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setrelative_s *alarminfo); static int stm32_cancelalarm(FAR struct rtc_lowerhalf_s *lower, int alarmid); static int stm32_rdalarm(FAR struct rtc_lowerhalf_s *lower, @@ -113,9 +114,11 @@ static int stm32_rdalarm(FAR struct rtc_lowerhalf_s *lower, #endif #ifdef CONFIG_RTC_PERIODIC -static int stm32_setperiodic(FAR struct rtc_lowerhalf_s *lower, - FAR const struct lower_setperiodic_s *alarminfo); -static int stm32_cancelperiodic(FAR struct rtc_lowerhalf_s *lower, int id); +static int +stm32_setperiodic(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setperiodic_s *alarminfo); +static int +stm32_cancelperiodic(FAR struct rtc_lowerhalf_s *lower, int id); #endif /**************************************************************************** diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_can.h b/arch/arm/src/stm32l4/hardware/stm32l4_can.h index 80325926dbf..83bd2d2ffd0 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_can.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_can.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4_can.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CAN_H #define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CAN_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* 3 TX mailboxes */ @@ -48,7 +48,7 @@ #define CAN_NFILTERS 14 -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ /* CAN control and status registers */ @@ -119,7 +119,7 @@ #define STM32L4_CAN_FIR_OFFSET(f,i) (0x240+((f)<<3)+(((i)-1)<<2)) -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #if STM32L4_NCAN > 0 # define STM32L4_CAN1_MCR (STM32L4_CAN1_BASE+STM32L4_CAN_MCR_OFFSET) @@ -176,7 +176,7 @@ # define STM32L4_CAN1_FIR(b,i) (STM32L4_CAN1_BASE+STM32L4_CAN_FIR_OFFSET(b,i)) #endif -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* CAN master control register */ @@ -269,6 +269,7 @@ # define CAN_ESR_BDOMERROR (5 << CAN_ESR_LEC_SHIFT) /* 101: Bit dominant Error */ # define CAN_ESR_CRCERRPR (6 << CAN_ESR_LEC_SHIFT) /* 110: CRC Error */ # define CAN_ESR_SWERROR (7 << CAN_ESR_LEC_SHIFT) /* 111: Set by software */ + #define CAN_ESR_TEC_SHIFT (16) /* Bits 23-16: LS byte of the 9-bit Transmit Error Counter */ #define CAN_ESR_TEC_MASK (0xff << CAN_ESR_TEC_SHIF) #define CAN_ESR_REC_SHIFT (24) /* Bits 31-24: Receive Error Counter */ @@ -276,15 +277,15 @@ /* CAN bit timing register */ -#define CAN_BTR_BRP_SHIFT (0) /* Bits 9-0: Baud Rate Prescaler */ +#define CAN_BTR_BRP_SHIFT (0) /* Bits 9-0: Baud Rate Prescaler */ #define CAN_BTR_BRP_MASK (0x03ff << CAN_BTR_BRP_SHIFT) -#define CAN_BTR_TS1_SHIFT (16) /* Bits 19-16: Time Segment 1 */ +#define CAN_BTR_TS1_SHIFT (16) /* Bits 19-16: Time Segment 1 */ #define CAN_BTR_TS1_MASK (0x0f << CAN_BTR_TS1_SHIFT) -#define CAN_BTR_TS2_SHIFT (20) /* Bits 22-20: Time Segment 2 */ +#define CAN_BTR_TS2_SHIFT (20) /* Bits 22-20: Time Segment 2 */ #define CAN_BTR_TS2_MASK (7 << CAN_BTR_TS2_SHIFT) -#define CAN_BTR_SJW_SHIFT (24) /* Bits 25-24: Resynchronization Jump Width */ +#define CAN_BTR_SJW_SHIFT (24) /* Bits 25-24: Resynchronization Jump Width */ #define CAN_BTR_SJW_MASK (3 << CAN_BTR_SJW_SHIFT) -#define CAN_BTR_LBKM (1 << 30) /* Bit 30: Loop Back Mode (Debug) */ +#define CAN_BTR_LBKM (1 << 30) /* Bit 30: Loop Back Mode (Debug) */ #define CAN_BTR_SILM (1ul << 31) /* Bit 31: Silent Mode (Debug) */ #define CAN_BTR_BRP_MAX (1024) /* Maximum BTR value (without decrement) */ @@ -395,16 +396,16 @@ #define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */ #define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CAN_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_crs.h b/arch/arm/src/stm32l4/hardware/stm32l4_crs.h index 50249d38442..55c87331d7e 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_crs.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_crs.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4_crs.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,30 +16,30 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CRS_H #define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CRS_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define STM32L4_CRS_CR_OFFSET 0x0000 /* CRS control register */ #define STM32L4_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ #define STM32L4_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ #define STM32L4_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define STM32L4_CRS_CR (STM32L4_CRS_BASE + STM32L4_CRS_CR_OFFSET) #define STM32L4_CRS_CFGR (STM32L4_CRS_BASE + STM32L4_CRS_CFGR_OFFSET) #define STM32L4_CRS_ISR (STM32L4_CRS_BASE + STM32L4_CRS_ISR_OFFSET) #define STM32L4_CRS_ICR (STM32L4_CRS_BASE + STM32L4_CRS_ICR_OFFSET) -/* Register Bitfield Definitions ****************************************************/ +/* Register Bitfield Definitions ********************************************/ /* CRS control register */ @@ -69,11 +69,13 @@ # define CRS_CFGR_SYNCDIV_d32 (5 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 32 */ # define CRS_CFGR_SYNCDIV_d64 (6 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 64 */ # define CRS_CFGR_SYNCDIV_d128 (7 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 128 */ + #define CRS_CFGR_SYNCSRC_SHIFT 28 /* Bits 28-29: SYNC signal source selection */ #define CRS_CFGR_SYNCSRC_MASK (3 << CRS_CFGR_SYNCSRC_SHIFT) # define CRS_CFGR_SYNCSRC_GPIO (0 << CRS_CFGR_SYNCSRC_SHIFT) /* GPIO as SYNC signal source */ # define CRS_CFGR_SYNCSRC_LSE (1 << CRS_CFGR_SYNCSRC_SHIFT) /* LSE as SYNC signal source */ # define CRS_CFGR_SYNCSRC_USBSOF (2 << CRS_CFGR_SYNCSRC_SHIFT) /* USB SOF as SYNC signal source */ + #define CRS_CFGR_SYNCPOL (1 << 31) /* SYNC polarity selection */ /* CRS interrupt and status register */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h index 2fae30530c5..1b2f4ed91d6 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_RCC_H #define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_RCC_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #if defined(CONFIG_STM32L4_STM32L4X5) -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */ #define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ @@ -66,7 +66,7 @@ #define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ #define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET) #define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET) @@ -99,7 +99,7 @@ #define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET) #define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET) -/* Register Bitfield Definitions ********************************************************************/ +/* Register Bitfield Definitions ********************************************/ /* Clock control register */ @@ -121,6 +121,7 @@ # define RCC_CR_MSIRANGE_24M (9 << RCC_CR_MSIRANGE_SHIFT) /* 1001: around 24 MHz */ # define RCC_CR_MSIRANGE_32M (10 << RCC_CR_MSIRANGE_SHIFT) /* 1010: around 32 MHz */ # define RCC_CR_MSIRANGE_48M (11 << RCC_CR_MSIRANGE_SHIFT) /* 1011: around 48 MHz */ + #define RCC_CR_HSION (1 << 8) /* Bit 8: Internal High Speed clock enable */ #define RCC_CR_HSIKERON (1 << 9) /* Bit 9: HSI16 always enable for peripheral kernels */ #define RCC_CR_HSIRDY (1 << 10) /* Bit 10: Internal High Speed clock ready flag */ @@ -155,23 +156,26 @@ # define RCC_CFGR_SW_HSI (1 << RCC_CFGR_SW_SHIFT) /* 00: HSI selected as system clock */ # define RCC_CFGR_SW_HSE (2 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */ # define RCC_CFGR_SW_PLL (3 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */ + #define RCC_CFGR_SWS_SHIFT (2) /* Bits 2-3: System Clock Switch Status */ #define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT) # define RCC_CFGR_SWS_MSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */ # define RCC_CFGR_SWS_HSI (1 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */ # define RCC_CFGR_SWS_HSE (2 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */ # define RCC_CFGR_SWS_PLL (3 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */ + #define RCC_CFGR_HPRE_SHIFT (4) /* Bits 4-7: AHB prescaler */ #define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT) -# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ -# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ -# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ +# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ +# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ +# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ # define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */ # define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */ # define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */ # define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */ # define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */ # define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */ + #define RCC_CFGR_PPRE1_SHIFT (8) /* Bits 8-10: APB Low speed prescaler (APB1) */ #define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT) # define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */ @@ -179,6 +183,7 @@ # define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */ # define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */ # define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */ + #define RCC_CFGR_PPRE2_SHIFT (11) /* Bits 11-13: APB High speed prescaler (APB2) */ #define RCC_CFGR_PPRE2_MASK (7 << RCC_CFGR_PPRE2_SHIFT) # define RCC_CFGR_PPRE2_HCLK (0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK not divided */ @@ -186,6 +191,7 @@ # define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */ # define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */ # define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */ + #define RCC_CFGR_STOPWUCK (1 << 15) /* Bit 15: Wakeup from Stop and CSS backup clock selection */ # define RCC_CFGR_STOPWUCK_MSI (0 << 15) /* 0: MSI */ # define RCC_CFGR_STOPWUCK_HSI (1 << 15) /* 0: HSI */ @@ -199,6 +205,7 @@ # define RCC_CFGR_MCO_PLL (5 << RCC_CFGR_MCO_SHIFT) /* 101: Main PLL selected */ # define RCC_CFGR_MCO_LSI (6 << RCC_CFGR_MCO_SHIFT) /* 110: LSI clock selected */ # define RCC_CFGR_MCO_LSE (7 << RCC_CFGR_MCO_SHIFT) /* 111: LSE clock selected */ + #define RCC_CFGR_MCOPRE_SHIFT (28) /* Bits 28-30: MCO prescaler */ #define RCC_CFGR_MCOPRE_MASK (7 << RCC_CFGR_MCOPRE_SHIFT) # define RCC_CFGR_MCOPRE_NONE (0 << RCC_CFGR_MCOPRE_SHIFT) /* 000: no division */ @@ -216,28 +223,36 @@ # define RCC_PLLCFG_PLLSRC_MSI (1 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: MSI selected as PLL source */ # define RCC_PLLCFG_PLLSRC_HSI (2 << RCC_PLLCFG_PLLSRC_SHIFT) /* 010: HSI selected as PLL source */ # define RCC_PLLCFG_PLLSRC_HSE (3 << RCC_PLLCFG_PLLSRC_SHIFT) /* 011: HSE selected as PLL source */ + #define RCC_PLLCFG_PLLM_SHIFT (4) /* Bits 4-6: Main PLL (PLL) input clock divider */ #define RCC_PLLCFG_PLLM_MASK (0x07 << RCC_PLLCFG_PLLM_SHIFT) # define RCC_PLLCFG_PLLM(n) ((n-1) << RCC_PLLCFG_PLLM_SHIFT) /* m = 1..8 */ + #define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 8-14: Main PLL (PLL) VCO multiplier */ #define RCC_PLLCFG_PLLN_MASK (0x7f << RCC_PLLCFG_PLLN_SHIFT) # define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 8..86 */ + #define RCC_PLLCFG_PLLPEN (1 << 16) /* Bit 16: Main PLL PLLSAI3CLK output enable */ #define RCC_PLLCFG_PLLP (1 << 17) /* Bit 17: Main PLL div factor for PLLSAI3CLK */ + # define RCC_PLLCFG_PLLP_7 0 /* 0: PLLP = 7 */ # define RCC_PLLCFG_PLLP_17 RCC_PLLCFG_PLLP /* 1: PLLP = 17 */ + #define RCC_PLLCFG_PLLQEN (1 << 20) /* Bit 20: Main PLL PLL48M1CLK output enable */ #define RCC_PLLCFG_PLLQ_SHIFT (21) #define RCC_PLLCFG_PLLQ_MASK (3 << RCC_PLLCFG_PLLQ_SHIFT) # define RCC_PLLCFG_PLLQ(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLQ_SHIFT) /* n=2,4,6,8 */ + # define RCC_PLLCFG_PLLQ_2 (0 << RCC_PLLCFG_PLLQ_SHIFT) /* 00: PLLQ = 2 */ # define RCC_PLLCFG_PLLQ_4 (1 << RCC_PLLCFG_PLLQ_SHIFT) /* 01: PLLQ = 4 */ # define RCC_PLLCFG_PLLQ_6 (2 << RCC_PLLCFG_PLLQ_SHIFT) /* 10: PLLQ = 6 */ # define RCC_PLLCFG_PLLQ_8 (3 << RCC_PLLCFG_PLLQ_SHIFT) /* 11: PLLQ = 8 */ + #define RCC_PLLCFG_PLLREN (1 << 24) /* Bit 24: Main PLL PLLCLK output enable */ #define RCC_PLLCFG_PLLR_SHIFT (25) #define RCC_PLLCFG_PLLR_MASK (3 << RCC_PLLCFG_PLLR_SHIFT) # define RCC_PLLCFG_PLLR(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLR_SHIFT) /* n=2,4,6,8 */ + # define RCC_PLLCFG_PLLR_2 (0 << RCC_PLLCFG_PLLR_SHIFT) /* 00: PLLR = 2 */ # define RCC_PLLCFG_PLLR_4 (1 << RCC_PLLCFG_PLLR_SHIFT) /* 01: PLLR = 4 */ # define RCC_PLLCFG_PLLR_6 (2 << RCC_PLLCFG_PLLR_SHIFT) /* 10: PLLR = 6 */ @@ -250,22 +265,28 @@ #define RCC_PLLSAI1CFG_PLLN_SHIFT (8) /* Bits 6-14: SAI1 PLL (PLLSAI1) VCO multiplier */ #define RCC_PLLSAI1CFG_PLLN_MASK (0x7f << RCC_PLLSAI1CFG_PLLN_SHIFT) # define RCC_PLLSAI1CFG_PLLN(n) ((n) << RCC_PLLSAI1CFG_PLLN_SHIFT) /* n = 8..86 */ + #define RCC_PLLSAI1CFG_PLLPEN (1 << 16) /* Bit 16: SAI1 PLL PLLSAI1CLK output enable */ #define RCC_PLLSAI1CFG_PLLP (1 << 17) /* Bit 17: Main PLL div factor for PLLSAI1CLK */ -# define RCC_PLLSAI1CFG_PLLP_7 0 /* 0: PLLP = 7 */ + +# define RCC_PLLSAI1CFG_PLLP_7 0 /* 0: PLLP = 7 */ # define RCC_PLLSAI1CFG_PLLP_17 RCC_PLLSAI1CFG_PLLP /* 1: PLLP = 17 */ + #define RCC_PLLSAI1CFG_PLLQEN (1 << 20) /* Bit 20: Main PLL PLL48M2CLK output enable */ #define RCC_PLLSAI1CFG_PLLQ_SHIFT (21) #define RCC_PLLSAI1CFG_PLLQ_MASK (3 << RCC_PLLSAI1CFG_PLLQ_SHIFT) # define RCC_PLLSAI1CFG_PLLQ(n) ((((n)>>1)-1)<< RCC_PLLSAI1CFG_PLLQ_SHIFT) /* n=2,4,6,8 */ + # define RCC_PLLSAI1CFG_PLLQ_2 (0 << RCC_PLLSAI1CFG_PLLQ_SHIFT) /* 00: PLLQ = 2 */ # define RCC_PLLSAI1CFG_PLLQ_4 (1 << RCC_PLLSAI1CFG_PLLQ_SHIFT) /* 01: PLLQ = 4 */ # define RCC_PLLSAI1CFG_PLLQ_6 (2 << RCC_PLLSAI1CFG_PLLQ_SHIFT) /* 10: PLLQ = 6 */ # define RCC_PLLSAI1CFG_PLLQ_8 (3 << RCC_PLLSAI1CFG_PLLQ_SHIFT) /* 11: PLLQ = 8 */ + #define RCC_PLLSAI1CFG_PLLREN (1 << 24) /* Bit 24: SAI1 PLL PLLADC1CLK output enable */ #define RCC_PLLSAI1CFG_PLLR_SHIFT (25) #define RCC_PLLSAI1CFG_PLLR_MASK (3 << RCC_PLLSAI1CFG_PLLR_SHIFT) # define RCC_PLLSAI1CFG_PLLR(n) ((((n)>>1)-1)<< RCC_PLLSAI1CFG_PLLR_SHIFT) /* n=2,4,6,8 */ + # define RCC_PLLSAI1CFG_PLLR_2 (0 << RCC_PLLSAI1CFG_PLLR_SHIFT) /* 00: PLLR = 2 */ # define RCC_PLLSAI1CFG_PLLR_4 (1 << RCC_PLLSAI1CFG_PLLR_SHIFT) /* 01: PLLR = 4 */ # define RCC_PLLSAI1CFG_PLLR_6 (2 << RCC_PLLSAI1CFG_PLLR_SHIFT) /* 10: PLLR = 6 */ @@ -276,14 +297,18 @@ #define RCC_PLLSAI2CFG_PLLN_SHIFT (8) /* Bits 6-14: SAI2 PLL (PLLSAI2) VCO multiplier */ #define RCC_PLLSAI2CFG_PLLN_MASK (0x7f << RCC_PLLSAI2CFG_PLLN_SHIFT) # define RCC_PLLSAI2CFG_PLLN(n) ((n) << RCC_PLLSAI2CFG_PLLN_SHIFT) /* n = 8..86 */ + #define RCC_PLLSAI2CFG_PLLPEN (1 << 16) /* Bit 16: SAI1 PLL PLLSAI2CLK output enable */ #define RCC_PLLSAI2CFG_PLLP (1 << 17) /* Bit 17: Main PLL div factor for PLLSAI2CLK */ -# define RCC_PLLSAI2CFG_PLLP_7 0 /* 0: PLLP = 7 */ + +# define RCC_PLLSAI2CFG_PLLP_7 0 /* 0: PLLP = 7 */ # define RCC_PLLSAI2CFG_PLLP_17 RCC_PLLSAI2CFG_PLLP /* 1: PLLP = 17 */ + #define RCC_PLLSAI2CFG_PLLREN (1 << 24) /* Bit 24: SAI2 PLL PLLADC2CLK output enable */ #define RCC_PLLSAI2CFG_PLLR_SHIFT (25) #define RCC_PLLSAI2CFG_PLLR_MASK (3 << RCC_PLLSAI2CFG_PLLR_SHIFT) # define RCC_PLLSAI2CFG_PLLR(n) ((((n)>>1)-1)<< RCC_PLLSAI2CFG_PLLR_SHIFT) /* n=2,4,6,8 */ + # define RCC_PLLSAI2CFG_PLLR_2 (0 << RCC_PLLSAI2CFG_PLLR_SHIFT) /* 00: PLLR = 2 */ # define RCC_PLLSAI2CFG_PLLR_4 (1 << RCC_PLLSAI2CFG_PLLR_SHIFT) /* 01: PLLR = 4 */ # define RCC_PLLSAI2CFG_PLLR_6 (2 << RCC_PLLSAI2CFG_PLLR_SHIFT) /* 10: PLLR = 6 */ @@ -655,19 +680,22 @@ # define RCC_BDCR_LSEDRV_MEDLO (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium Low driving capability */ # define RCC_BDCR_LSEDRV_MEDHI (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium High driving capability*/ # define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: Higher driving capability */ + #define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: CSS on LSE enable */ #define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: CSS on LSE failure Detection */ -#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ +#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ #define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) # define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ # define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ # define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ # define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 32 used as RTC clock */ + #define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ #define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */ #define RCC_BDCR_LSCOEN (1 << 24) /* Bit 24: Low speed clock output enable */ #define RCC_BDCR_LSCOSEL (1 << 25) /* Bit 25: Low speed clock output selection */ -# define RCC_BCDR_LSCOSEL_LSI 0 /* LSI selected */ + +# define RCC_BCDR_LSCOSEL_LSI 0 /* LSI selected */ # define RCC_BDCR_LSCOSEL_LSE RCC_BDCR_LSCOSEL /* LSE selected */ /* Control/status register */ @@ -680,6 +708,7 @@ # define RCC_CSR_MSISRANGE_2M (5 << RCC_CSR_MSISRANGE_SHIFT) /* 0101: around 2 MHz */ # define RCC_CSR_MSISRANGE_4M (6 << RCC_CSR_MSISRANGE_SHIFT) /* 0110: around 4 MHz */ # define RCC_CSR_MSISRANGE_8M (7 << RCC_CSR_MSISRANGE_SHIFT) /* 0111: around 8 MHz */ + #define RCC_CSR_RMVF (1 << 23) /* Bit 23: Remove reset flag */ #define RCC_CSR_FWRSTF (1 << 24) /* Bit 24: Firewall reset flag */ #define RCC_CSR_OBLRSTF (1 << 25) /* Bit 25: Option byte loader reset flag */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h index 504a3f1da6e..45a0c7fdb20 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_RCC_H #define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_RCC_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #if defined(CONFIG_STM32L4_STM32L4X6) -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */ #define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ @@ -68,7 +68,7 @@ #define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ #define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET) #define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET) @@ -103,7 +103,7 @@ #define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET) #define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET) -/* Register Bitfield Definitions ********************************************************************/ +/* Register Bitfield Definitions ********************************************/ /* Clock control register */ @@ -171,9 +171,9 @@ #define RCC_CFGR_HPRE_SHIFT (4) /* Bits 4-7: AHB prescaler */ #define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT) -# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ -# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ -# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ +# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ +# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ +# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ # define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */ # define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */ # define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */ @@ -241,6 +241,7 @@ #define RCC_PLLCFG_PLLPEN (1 << 16) /* Bit 16: Main PLL PLLSAI3CLK output enable */ #define RCC_PLLCFG_PLLP (1 << 17) /* Bit 17: Main PLL div factor for PLLSAI3CLK */ + # define RCC_PLLCFG_PLLP_7 0 /* 0: PLLP = 7 */ # define RCC_PLLCFG_PLLP_17 RCC_PLLCFG_PLLP /* 1: PLLP = 17 */ @@ -249,6 +250,7 @@ #define RCC_PLLCFG_PLLQ_SHIFT (21) /* Bits 21-22: Main PLL division factor for PLL48M1CLK (48 MHz clock) */ #define RCC_PLLCFG_PLLQ_MASK (3 << RCC_PLLCFG_PLLQ_SHIFT) # define RCC_PLLCFG_PLLQ(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLQ_SHIFT) /* n=2,4,6,8 */ + # define RCC_PLLCFG_PLLQ_2 (0 << RCC_PLLCFG_PLLQ_SHIFT) /* 00: PLLQ = 2 */ # define RCC_PLLCFG_PLLQ_4 (1 << RCC_PLLCFG_PLLQ_SHIFT) /* 01: PLLQ = 4 */ # define RCC_PLLCFG_PLLQ_6 (2 << RCC_PLLCFG_PLLQ_SHIFT) /* 10: PLLQ = 6 */ @@ -259,6 +261,7 @@ #define RCC_PLLCFG_PLLR_SHIFT (25) /* Bits 25-26: Main PLL division factor for PLLCLK (system clock) */ #define RCC_PLLCFG_PLLR_MASK (3 << RCC_PLLCFG_PLLR_SHIFT) # define RCC_PLLCFG_PLLR(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLR_SHIFT) /* n=2,4,6,8 */ + # define RCC_PLLCFG_PLLR_2 (0 << RCC_PLLCFG_PLLR_SHIFT) /* 00: PLLR = 2 */ # define RCC_PLLCFG_PLLR_4 (1 << RCC_PLLCFG_PLLR_SHIFT) /* 01: PLLR = 4 */ # define RCC_PLLCFG_PLLR_6 (2 << RCC_PLLCFG_PLLR_SHIFT) /* 10: PLLR = 6 */ @@ -275,7 +278,8 @@ #define RCC_PLLSAI1CFG_PLLPEN (1 << 16) /* Bit 16: SAI1 PLL PLLSAI1CLK output enable */ #define RCC_PLLSAI1CFG_PLLP (1 << 17) /* Bit 17: Main PLL div factor for PLLSAI1CLK */ -# define RCC_PLLSAI1CFG_PLLP_7 0 /* 0: PLLP = 7 */ + +# define RCC_PLLSAI1CFG_PLLP_7 0 /* 0: PLLP = 7 */ # define RCC_PLLSAI1CFG_PLLP_17 RCC_PLLSAI1CFG_PLLP /* 1: PLLP = 17 */ #define RCC_PLLSAI1CFG_PLLQEN (1 << 20) /* Bit 20: Main PLL PLL48M2CLK output enable */ @@ -283,6 +287,7 @@ #define RCC_PLLSAI1CFG_PLLQ_SHIFT (21) #define RCC_PLLSAI1CFG_PLLQ_MASK (3 << RCC_PLLSAI1CFG_PLLQ_SHIFT) # define RCC_PLLSAI1CFG_PLLQ(n) ((((n)>>1)-1)<< RCC_PLLSAI1CFG_PLLQ_SHIFT) /* n=2,4,6,8 */ + # define RCC_PLLSAI1CFG_PLLQ_2 (0 << RCC_PLLSAI1CFG_PLLQ_SHIFT) /* 00: PLLQ = 2 */ # define RCC_PLLSAI1CFG_PLLQ_4 (1 << RCC_PLLSAI1CFG_PLLQ_SHIFT) /* 01: PLLQ = 4 */ # define RCC_PLLSAI1CFG_PLLQ_6 (2 << RCC_PLLSAI1CFG_PLLQ_SHIFT) /* 10: PLLQ = 6 */ @@ -293,6 +298,7 @@ #define RCC_PLLSAI1CFG_PLLR_SHIFT (25) #define RCC_PLLSAI1CFG_PLLR_MASK (3 << RCC_PLLSAI1CFG_PLLR_SHIFT) # define RCC_PLLSAI1CFG_PLLR(n) ((((n)>>1)-1)<< RCC_PLLSAI1CFG_PLLR_SHIFT) /* n=2,4,6,8 */ + # define RCC_PLLSAI1CFG_PLLR_2 (0 << RCC_PLLSAI1CFG_PLLR_SHIFT) /* 00: PLLR = 2 */ # define RCC_PLLSAI1CFG_PLLR_4 (1 << RCC_PLLSAI1CFG_PLLR_SHIFT) /* 01: PLLR = 4 */ # define RCC_PLLSAI1CFG_PLLR_6 (2 << RCC_PLLSAI1CFG_PLLR_SHIFT) /* 10: PLLR = 6 */ @@ -307,7 +313,8 @@ #define RCC_PLLSAI2CFG_PLLPEN (1 << 16) /* Bit 16: SAI1 PLL PLLSAI2CLK output enable */ #define RCC_PLLSAI2CFG_PLLP (1 << 17) /* Bit 17: Main PLL div factor for PLLSAI2CLK */ -# define RCC_PLLSAI2CFG_PLLP_7 0 /* 0: PLLP = 7 */ + +# define RCC_PLLSAI2CFG_PLLP_7 0 /* 0: PLLP = 7 */ # define RCC_PLLSAI2CFG_PLLP_17 RCC_PLLSAI2CFG_PLLP /* 1: PLLP = 17 */ #define RCC_PLLSAI2CFG_PLLREN (1 << 24) /* Bit 24: SAI2 PLL PLLADC2CLK output enable */ @@ -315,6 +322,7 @@ #define RCC_PLLSAI2CFG_PLLR_SHIFT (25) #define RCC_PLLSAI2CFG_PLLR_MASK (3 << RCC_PLLSAI2CFG_PLLR_SHIFT) # define RCC_PLLSAI2CFG_PLLR(n) ((((n)>>1)-1)<< RCC_PLLSAI2CFG_PLLR_SHIFT) /* n=2,4,6,8 */ + # define RCC_PLLSAI2CFG_PLLR_2 (0 << RCC_PLLSAI2CFG_PLLR_SHIFT) /* 00: PLLR = 2 */ # define RCC_PLLSAI2CFG_PLLR_4 (1 << RCC_PLLSAI2CFG_PLLR_SHIFT) /* 01: PLLR = 4 */ # define RCC_PLLSAI2CFG_PLLR_6 (2 << RCC_PLLSAI2CFG_PLLR_SHIFT) /* 10: PLLR = 6 */ @@ -753,7 +761,8 @@ #define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */ #define RCC_BDCR_LSCOEN (1 << 24) /* Bit 24: Low speed clock output enable */ #define RCC_BDCR_LSCOSEL (1 << 25) /* Bit 25: Low speed clock output selection */ -# define RCC_BCDR_LSCOSEL_LSI 0 /* LSI selected */ + +# define RCC_BCDR_LSCOSEL_LSI 0 /* LSI selected */ # define RCC_BDCR_LSCOSEL_LSE RCC_BDCR_LSCOSEL /* LSE selected */ /* Control/status register */ @@ -786,7 +795,9 @@ #define RCC_CRRCR_HSI48ON (1 << 0) /* Bit 0: HSI48 clock enable */ #define RCC_CRRCR_HSI48RDY (1 << 1) /* Bit 1: HSI48 clock ready flag */ -/* Peripheral Independent Clock Configuration 2 register (only on STM32L496xx/4A6xx) */ +/* Peripheral Independent Clock Configuration 2 register + * (only on STM32L496xx/4A6xx) + */ #define RCC_CCIPR2_I2C4SEL_SHIFT (0) /* Bits 0-1: I2C4 clock source selection */ #define RCC_CCIPR2_I2C4SEL_MASK (3 << RCC_CCIPR2_I2C4SEL_SHIFT) diff --git a/arch/arm/src/stm32l4/stm32l4_can.h b/arch/arm/src/stm32l4/stm32l4_can.h index 72517990ffd..eff59d7285c 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.h +++ b/arch/arm/src/stm32l4/stm32l4_can.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32l4/stm32l4_can.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_CAN_H #define __ARCH_ARM_SRC_STM32L4_STM32L4_CAN_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -32,11 +32,12 @@ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ -/* Configuration ********************************************************************/ /* Up to 1 CAN interfaces are supported */ #if STM32L4_NCAN < 1 @@ -74,15 +75,15 @@ # error "CONFIG_STM32L4_CAN_TSEG2 is out of range" #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -93,9 +94,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ /**************************************************************************** * Name: stm32l4can_initialize diff --git a/arch/arm/src/stm32l4/stm32l4_dumpgpio.c b/arch/arm/src/stm32l4/stm32l4_dumpgpio.c index 9eb596d14c4..c0d6426481d 100644 --- a/arch/arm/src/stm32l4/stm32l4_dumpgpio.c +++ b/arch/arm/src/stm32l4/stm32l4_dumpgpio.c @@ -44,6 +44,7 @@ /**************************************************************************** * Private Data ****************************************************************************/ + /* Port letters for prettier debug output */ static const char g_portchar[STM32L4_NPORTS] = diff --git a/arch/arm/src/stm32l4/stm32l4_firewall.h b/arch/arm/src/stm32l4/stm32l4_firewall.h index 011f55ec1d7..51902ba6302 100644 --- a/arch/arm/src/stm32l4/stm32l4_firewall.h +++ b/arch/arm/src/stm32l4/stm32l4_firewall.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32l4/stm32l4_firewall.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_FIREWALL_H #define __ARCH_ARM_SRC_STM32L4_STM32L4_FIREWALL_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include "chip.h" -/* Include the correct firewall register definitions for this STM32L4 family */ +/* Include the correct firewall register definitions for this STM32L4 + * family + */ #if defined(CONFIG_STM32L4_STM32L4X3) # include "hardware/stm32l4x3xx_firewall.h" @@ -44,9 +46,9 @@ # error "Unsupported STM32L4 chip" #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ struct stm32l4_firewall_t { @@ -60,9 +62,9 @@ struct stm32l4_firewall_t uint8_t dataexec : 1; }; -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -75,9 +77,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ /**************************************************************************** * Name: stm32l4_firewallsetup @@ -86,7 +88,8 @@ extern "C" * Configure the STM32L4 firewall. After this, protected code will only * be accessible via the "entry gate". * Once enabled, the firewall cannot be enabled until the next reset. - * Returns 0 when OK, -1 when addresses and length are not properly aligned. + * Returns 0 when OK, -1 when addresses and length are not properly + * aligned. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.h b/arch/arm/src/stm32l4/stm32l4_gpio.h index a12866343dd..d90f63fb892 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.h +++ b/arch/arm/src/stm32l4/stm32l4_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32l4/stm32l4_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_GPIO_H #define __ARCH_ARM_SRC_STM32L4_STM32L4_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -44,14 +44,14 @@ # error "Unsupported STM32L4 chip" #endif -/************************************************************************************ +/**************************************************************************** * Pre-Processor Declarations - ************************************************************************************/ + ****************************************************************************/ /* Bit-encoded input to stm32l4_configgpio() */ -/* Each port bit of the general-purpose I/O (GPIO) ports can be individually configured - * by software in several modes: +/* Each port bit of the general-purpose I/O (GPIO) ports can be individually + * configured by software in several modes: * * - Input floating * - Input pull-up @@ -154,9 +154,10 @@ #define GPIO_OPENDRAIN (1 << 9) /* Bit9: 1=Open-drain output */ #define GPIO_PUSHPULL (0) /* Bit9: 0=Push-pull output */ -/* If the pin is a GPIO digital output, then this identifies the initial output value. - * If the pin is an input, this bit is overloaded to provide the qualifier to - * distinguish input pull-up and -down: +/* If the pin is a GPIO digital output, then this identifies the initial + * output value. + * If the pin is an input, this bit is overloaded to provide the + * qualifier to distinguish input pull-up and -down: * * 1111 1111 1100 0000 0000 * 9876 5432 1098 7654 3210 @@ -224,9 +225,9 @@ # define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) # define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -243,69 +244,71 @@ extern "C" EXTERN const uint32_t g_gpiobase[STM32L4_NPORTS]; -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: stm32l4_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) * function, it must be unconfigured with stm32l4_unconfiggpio() with - * the same cfgset first before it can be set to non-alternative function. + * the same cfgset first before it can be set to non-alternative + * function. * * Returned Value: * OK on success * ERROR on invalid port, or when pin is locked as ALT function. * - ************************************************************************************/ + ****************************************************************************/ int stm32l4_configgpio(uint32_t cfgset); -/************************************************************************************ +/**************************************************************************** * Name: stm32l4_unconfiggpio * * Description: - * Unconfigure a GPIO pin based on bit-encoded description of the pin, set it - * into default HiZ state (and possibly mark it's unused) and unlock it whether - * it was previsouly selected as alternative function (GPIO_ALT|GPIO_CNF_AFPP|...). + * Unconfigure a GPIO pin based on bit-encoded description of the pin, set + * it into default HiZ state (and possibly mark it's unused) and unlock it + * whether it was previsouly selected as alternative function + * (GPIO_ALT|GPIO_CNF_AFPP|...). * - * This is a safety function and prevents hardware from schocks, as unexpected - * write to the Timer Channel Output GPIO to fixed '1' or '0' while it should - * operate in PWM mode could produce excessive on-board currents and trigger - * over-current/alarm function. + * This is a safety function and prevents hardware from schocks, as + * unexpected write to the Timer Channel Output GPIO to fixed '1' or '0' + * while it should operate in PWM mode could produce excessive on-board + * currents and trigger over-current/alarm function. * * Returned Value: * OK on success * ERROR on invalid port * - ************************************************************************************/ + ****************************************************************************/ int stm32l4_unconfiggpio(uint32_t cfgset); -/************************************************************************************ +/**************************************************************************** * Name: stm32l4_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * - ************************************************************************************/ + ****************************************************************************/ void stm32l4_gpiowrite(uint32_t pinset, bool value); -/************************************************************************************ +/**************************************************************************** * Name: stm32l4_gpioread * * Description: * Read one or zero from the selected GPIO pin * - ************************************************************************************/ + ****************************************************************************/ bool stm32l4_gpioread(uint32_t pinset); -/************************************************************************************ +/**************************************************************************** * Name: stm32l4_gpiosetevent * * Description: @@ -320,21 +323,21 @@ bool stm32l4_gpioread(uint32_t pinset); * arg - Argument passed to the interrupt callback * * Returned Value: - * Zero (OK) is returned on success, otherwise a negated errno value is returned - * to indicate the nature of the failure. + * Zero (OK) is returned on success, otherwise a negated errno value is + * returned to indicate the nature of the failure. * - ************************************************************************************/ + ****************************************************************************/ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); -/************************************************************************************ +/**************************************************************************** * Function: stm32l4_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES int stm32l4_dumpgpio(uint32_t pinset, const char *msg); @@ -342,7 +345,7 @@ int stm32l4_dumpgpio(uint32_t pinset, const char *msg); # define stm32l4_dumpgpio(p,m) #endif -/************************************************************************************ +/**************************************************************************** * Function: stm32l4_gpioinit * * Description: @@ -351,7 +354,7 @@ int stm32l4_dumpgpio(uint32_t pinset, const char *msg); * * Typically called from stm32l4_start(). * - ************************************************************************************/ + ****************************************************************************/ void stm32l4_gpioinit(void); diff --git a/arch/arm/src/stm32l4/stm32l4_hsi48.h b/arch/arm/src/stm32l4/stm32l4_hsi48.h index 8d7df4bc674..ecc600709f6 100644 --- a/arch/arm/src/stm32l4/stm32l4_hsi48.h +++ b/arch/arm/src/stm32l4/stm32l4_hsi48.h @@ -42,7 +42,7 @@ enum syncsrc_e }; /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ /**************************************************************************** diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.c b/arch/arm/src/stm32l4/stm32l4_rcc.c index 928fbfff18e..2ee735fe335 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rcc.c @@ -41,6 +41,20 @@ #include "stm32l4_waste.h" #include "stm32l4_rtc.h" +/* Include chip-specific clocking initialization logic */ + +#if defined(CONFIG_STM32L4_STM32L4X3) +# include "stm32l4x3xx_rcc.c" +#elif defined(CONFIG_STM32L4_STM32L4X5) +# include "stm32l4x5xx_rcc.c" +#elif defined(CONFIG_STM32L4_STM32L4X6) +# include "stm32l4x6xx_rcc.c" +#elif defined(CONFIG_STM32L4_STM32L4XR) +# include "stm32l4xrxx_rcc.c" +#else +# error "Unsupported STM32L4 chip" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -60,20 +74,6 @@ * Private Functions ****************************************************************************/ -/* Include chip-specific clocking initialization logic */ - -#if defined(CONFIG_STM32L4_STM32L4X3) -# include "stm32l4x3xx_rcc.c" -#elif defined(CONFIG_STM32L4_STM32L4X5) -# include "stm32l4x5xx_rcc.c" -#elif defined(CONFIG_STM32L4_STM32L4X6) -# include "stm32l4x6xx_rcc.c" -#elif defined(CONFIG_STM32L4_STM32L4XR) -# include "stm32l4xrxx_rcc.c" -#else -# error "Unsupported STM32L4 chip" -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -83,9 +83,9 @@ * * Description: * The RTC needs to reset the Backup Domain to change RTCSEL and resetting - * the Backup Domain renders to disabling the LSE as consequence. In order - * to avoid resetting the Backup Domain when we already configured LSE we - * will reset the Backup Domain early (here). + * the Backup Domain renders to disabling the LSE as consequence. In + * order to avoid resetting the Backup Domain when we already configured + * LSE we will reset the Backup Domain early (here). * * Input Parameters: * None @@ -115,9 +115,9 @@ static inline void rcc_resetbkp(void) bkregs[i] = getreg32(STM32L4_RTC_BKR(i)); } - /* Enable write access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - */ + /* Enable write access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + */ stm32l4_pwr_enablebkp(true); @@ -125,22 +125,22 @@ static inline void rcc_resetbkp(void) * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_BDRST, 0); - /* Restore backup-registers, except RTC related. */ + /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32L4_RTC_BKCOUNT; i++) - { - if (RTC_MAGIC_REG == STM32L4_RTC_BKR(i)) - { - continue; - } + for (i = 0; i < STM32L4_RTC_BKCOUNT; i++) + { + if (RTC_MAGIC_REG == STM32L4_RTC_BKR(i)) + { + continue; + } putreg32(bkregs[i], STM32L4_RTC_BKR(i)); - } + } - stm32l4_pwr_enablebkp(false); + stm32l4_pwr_enablebkp(false); } } #else @@ -160,9 +160,9 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then clocking - * will be enabled by an externally provided, board-specific function called - * stm32l4_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32l4_board_clockconfig(). * * Input Parameters: * None @@ -190,7 +190,9 @@ void stm32l4_clockconfig(void) #else - /* Invoke standard, fixed clock configuration based on definitions in board.h */ + /* Invoke standard, fixed clock configuration based on definitions in + * board.h + */ stm32l4_stdclockconfig(); @@ -201,22 +203,23 @@ void stm32l4_clockconfig(void) rcc_enableperipherals(); } -/************************************************************************************ +/**************************************************************************** * Name: stm32l4_clockenable * * Description: - * Re-enable the clock and restore the clock settings based on settings in board.h. - * This function is only available to support low-power modes of operation: When - * re-awakening from deep-sleep modes, it is necessary to re-enable/re-start the - * PLL + * Re-enable the clock and restore the clock settings based on settings in + * board.h. + * This function is only available to support low-power modes of operation: + * When re-awakening from deep-sleep modes, it is necessary to + * re-enable/re-start the PLL * * This functional performs a subset of the operations performed by - * stm32l4_clockconfig(): It does not reset any devices, and it does not reset the - * currently enabled peripheral clocks. + * stm32l4_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then clocking will - * be enabled by an externally provided, board-specific function called - * stm32l4_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32l4_board_clockconfig(). * * Input Parameters: * None @@ -224,7 +227,7 @@ void stm32l4_clockconfig(void) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_PM void stm32l4_clockenable(void) @@ -237,7 +240,9 @@ void stm32l4_clockenable(void) #else - /* Invoke standard, fixed clock configuration based on definitions in board.h */ + /* Invoke standard, fixed clock configuration based on definitions in + * board.h + */ stm32l4_stdclockconfig(); diff --git a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c index d302dff04a3..8b2178ebf82 100644 --- a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c @@ -847,7 +847,9 @@ static void stm32l4_stdclockconfig(void) } #endif - /* Enable FLASH prefetch, instruction cache, data cache, and 4 wait states */ + /* Enable FLASH prefetch, instruction cache, data cache, + * and 4 wait states + */ #ifdef CONFIG_STM32L4_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | diff --git a/boards/arm/imxrt/imxrt1060-evk/src/imxrt_boot.c b/boards/arm/imxrt/imxrt1060-evk/src/imxrt_boot.c index 9228a9c3bc1..5d6485da5a8 100644 --- a/boards/arm/imxrt/imxrt1060-evk/src/imxrt_boot.c +++ b/boards/arm/imxrt/imxrt1060-evk/src/imxrt_boot.c @@ -64,9 +64,10 @@ void imxrt_ocram_initialize(void) regval = getreg32(IMXRT_IOMUXC_GPR_GPR16); putreg32(regval | GPR_GPR16_FLEXRAM_BANK_CFG_SELF, IMXRT_IOMUXC_GPR_GPR16); - for (src = (uint32_t *)(LOCATE_IN_SRC(g_boot_data.start) + g_boot_data.size), + for (src = (uint32_t *)(LOCATE_IN_SRC(g_boot_data.start) + + g_boot_data.size), dest = (uint32_t *)(g_boot_data.start + g_boot_data.size); - dest < (uint32_t *) &_etext;) + dest < (uint32_t *) &_etext; ) { *dest++ = *src++; } @@ -98,7 +99,7 @@ void imxrt_boardinitialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be + * function called board_late_initialize(). board_late_initialize() will be * called immediately after up_intitialize() is called and just before the * initial application is started. This additional initialization phase * may be used, for example, to initialize board-specific device drivers. diff --git a/boards/arm/stm32/olimexino-stm32/include/board.h b/boards/arm/stm32/olimexino-stm32/include/board.h index fecfd4611d5..95df7d6f0a6 100644 --- a/boards/arm/stm32/olimexino-stm32/include/board.h +++ b/boards/arm/stm32/olimexino-stm32/include/board.h @@ -53,7 +53,10 @@ #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL #define STM32_LSE_FREQUENCY 32768 -/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ +/* PLL source is HSE/1, + * PLL multipler is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC #define STM32_CFGR_PLLXTPRE 0 @@ -102,7 +105,8 @@ /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 */ + * Note: TIM1,8 are on APB2, others on APB1 + */ #define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY @@ -113,12 +117,12 @@ #define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY -/* Buttons *************************************************************************/ +/* Buttons ******************************************************************/ #define BUTTON_BOOT0_BIT (0) #define BUTTON_BOOT0_MASK (1<