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NX style fixes

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This commit is contained in:
Peter van der Perk
2022-07-22 20:23:16 +02:00
committed by Xiang Xiao
parent eae3f77673
commit ec118743ea
9 changed files with 435 additions and 436 deletions
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arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h
-36
View File
@@ -1160,42 +1160,6 @@
#define S32K3XX_EDMA_TCD31_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_CSR_OFFSET)
#define S32K3XX_EDMA_TCD31_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_BITER_OFFSET)
uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
{
S32K3XX_EDMA_CH0_CSR,
S32K3XX_EDMA_CH1_CSR,
S32K3XX_EDMA_CH2_CSR,
S32K3XX_EDMA_CH3_CSR,
S32K3XX_EDMA_CH4_CSR,
S32K3XX_EDMA_CH5_CSR,
S32K3XX_EDMA_CH6_CSR,
S32K3XX_EDMA_CH7_CSR,
S32K3XX_EDMA_CH8_CSR,
S32K3XX_EDMA_CH9_CSR,
S32K3XX_EDMA_CH10_CSR,
S32K3XX_EDMA_CH11_CSR,
S32K3XX_EDMA_CH12_CSR,
S32K3XX_EDMA_CH13_CSR,
S32K3XX_EDMA_CH14_CSR,
S32K3XX_EDMA_CH15_CSR,
S32K3XX_EDMA_CH16_CSR,
S32K3XX_EDMA_CH17_CSR,
S32K3XX_EDMA_CH18_CSR,
S32K3XX_EDMA_CH19_CSR,
S32K3XX_EDMA_CH20_CSR,
S32K3XX_EDMA_CH21_CSR,
S32K3XX_EDMA_CH22_CSR,
S32K3XX_EDMA_CH23_CSR,
S32K3XX_EDMA_CH24_CSR,
S32K3XX_EDMA_CH25_CSR,
S32K3XX_EDMA_CH26_CSR,
S32K3XX_EDMA_CH27_CSR,
S32K3XX_EDMA_CH28_CSR,
S32K3XX_EDMA_CH29_CSR,
S32K3XX_EDMA_CH30_CSR,
S32K3XX_EDMA_CH31_CSR
};
/* eDMA Register Bitfield Definitions ***************************************/
/* Management Page Control Register (CSR) */
arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h
+289 -289
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File diff suppressed because it is too large Load Diff
arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h
+29 -29
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@@ -132,32 +132,32 @@
/* Output Update Disable Register (OUDIS) */
#define EMIOS_OUDIS_OU0 (1 << 0) /* Bit 0: Channel 0 Output Update Disable (OU0) */
#define EMIOS_OUDIS_OU1 (1 << 1) /* Bit 1: Channel 1 Output Update Disable (OU1) */
#define EMIOS_OUDIS_OU2 (1 << 2) /* Bit 2: Channel 2 Output Update Disable (OU2) */
#define EMIOS_OUDIS_OU3 (1 << 3) /* Bit 3: Channel 3 Output Update Disable (OU3) */
#define EMIOS_OUDIS_OU4 (1 << 4) /* Bit 4: Channel 4 Output Update Disable (OU4) */
#define EMIOS_OUDIS_OU5 (1 << 5) /* Bit 5: Channel 5 Output Update Disable (OU5) */
#define EMIOS_OUDIS_OU6 (1 << 6) /* Bit 6: Channel 6 Output Update Disable (OU6) */
#define EMIOS_OUDIS_OU7 (1 << 7) /* Bit 7: Channel 7 Output Update Disable (OU7) */
#define EMIOS_OUDIS_OU8 (1 << 8) /* Bit 8: Channel 8 Output Update Disable (OU8) */
#define EMIOS_OUDIS_OU9 (1 << 9) /* Bit 9: Channel 9 Output Update Disable (OU9) */
#define EMIOS_OUDIS_OU10 (1 << 10) /* Bit 10: Channel 10 Output Update Disable (OU10) */
#define EMIOS_OUDIS_OU11 (1 << 11) /* Bit 11: Channel 11 Output Update Disable (OU11) */
#define EMIOS_OUDIS_OU12 (1 << 12) /* Bit 12: Channel 12 Output Update Disable (OU12) */
#define EMIOS_OUDIS_OU13 (1 << 13) /* Bit 13: Channel 13 Output Update Disable (OU13) */
#define EMIOS_OUDIS_OU14 (1 << 14) /* Bit 14: Channel 14 Output Update Disable (OU14) */
#define EMIOS_OUDIS_OU15 (1 << 15) /* Bit 15: Channel 15 Output Update Disable (OU15) */
#define EMIOS_OUDIS_OU16 (1 << 16) /* Bit 16: Channel 16 Output Update Disable (OU16) */
#define EMIOS_OUDIS_OU17 (1 << 17) /* Bit 17: Channel 17 Output Update Disable (OU17) */
#define EMIOS_OUDIS_OU18 (1 << 18) /* Bit 18: Channel 18 Output Update Disable (OU18) */
#define EMIOS_OUDIS_OU19 (1 << 19) /* Bit 19: Channel 19 Output Update Disable (OU19) */
#define EMIOS_OUDIS_OU20 (1 << 20) /* Bit 20: Channel 20 Output Update Disable (OU20) */
#define EMIOS_OUDIS_OU21 (1 << 21) /* Bit 21: Channel 21 Output Update Disable (OU21) */
#define EMIOS_OUDIS_OU22 (1 << 22) /* Bit 22: Channel 22 Output Update Disable (OU22) */
#define EMIOS_OUDIS_OU23 (1 << 23) /* Bit 23: Channel 23 Output Update Disable (OU23) */
#define EMIOS_OUDIS_OU(n) (1 << n) /* Bit n: Channel n Output Update Disable (OU23) */
/* Bits 24-31: Reserved */
#define EMIOS_OUDIS_OU0 (1 << 0) /* Bit 0: Channel 0 Output Update Disable (OU0) */
#define EMIOS_OUDIS_OU1 (1 << 1) /* Bit 1: Channel 1 Output Update Disable (OU1) */
#define EMIOS_OUDIS_OU2 (1 << 2) /* Bit 2: Channel 2 Output Update Disable (OU2) */
#define EMIOS_OUDIS_OU3 (1 << 3) /* Bit 3: Channel 3 Output Update Disable (OU3) */
#define EMIOS_OUDIS_OU4 (1 << 4) /* Bit 4: Channel 4 Output Update Disable (OU4) */
#define EMIOS_OUDIS_OU5 (1 << 5) /* Bit 5: Channel 5 Output Update Disable (OU5) */
#define EMIOS_OUDIS_OU6 (1 << 6) /* Bit 6: Channel 6 Output Update Disable (OU6) */
#define EMIOS_OUDIS_OU7 (1 << 7) /* Bit 7: Channel 7 Output Update Disable (OU7) */
#define EMIOS_OUDIS_OU8 (1 << 8) /* Bit 8: Channel 8 Output Update Disable (OU8) */
#define EMIOS_OUDIS_OU9 (1 << 9) /* Bit 9: Channel 9 Output Update Disable (OU9) */
#define EMIOS_OUDIS_OU10 (1 << 10) /* Bit 10: Channel 10 Output Update Disable (OU10) */
#define EMIOS_OUDIS_OU11 (1 << 11) /* Bit 11: Channel 11 Output Update Disable (OU11) */
#define EMIOS_OUDIS_OU12 (1 << 12) /* Bit 12: Channel 12 Output Update Disable (OU12) */
#define EMIOS_OUDIS_OU13 (1 << 13) /* Bit 13: Channel 13 Output Update Disable (OU13) */
#define EMIOS_OUDIS_OU14 (1 << 14) /* Bit 14: Channel 14 Output Update Disable (OU14) */
#define EMIOS_OUDIS_OU15 (1 << 15) /* Bit 15: Channel 15 Output Update Disable (OU15) */
#define EMIOS_OUDIS_OU16 (1 << 16) /* Bit 16: Channel 16 Output Update Disable (OU16) */
#define EMIOS_OUDIS_OU17 (1 << 17) /* Bit 17: Channel 17 Output Update Disable (OU17) */
#define EMIOS_OUDIS_OU18 (1 << 18) /* Bit 18: Channel 18 Output Update Disable (OU18) */
#define EMIOS_OUDIS_OU19 (1 << 19) /* Bit 19: Channel 19 Output Update Disable (OU19) */
#define EMIOS_OUDIS_OU20 (1 << 20) /* Bit 20: Channel 20 Output Update Disable (OU20) */
#define EMIOS_OUDIS_OU21 (1 << 21) /* Bit 21: Channel 21 Output Update Disable (OU21) */
#define EMIOS_OUDIS_OU22 (1 << 22) /* Bit 22: Channel 22 Output Update Disable (OU22) */
#define EMIOS_OUDIS_OU23 (1 << 23) /* Bit 23: Channel 23 Output Update Disable (OU23) */
#define EMIOS_OUDIS_OU(n) (1 << (n)) /* Bit n: Channel n Output Update Disable (OU23) */
/* Bits 24-31: Reserved */
/* Disable Channel Register (UCDIS) */
@@ -191,14 +191,14 @@
#define EMIOS_A_SHIFT (0) /* Bits 0-15: A */
#define EMIOS_A_MASK (0xffff << EMIOS_A_SHIFT)
#define EMIOS_A(n) ((n << EMIOS_A_SHIFT) & EMIOS_A_MASK)
#define EMIOS_A(n) (((n) << EMIOS_A_SHIFT) & EMIOS_A_MASK)
/* Bits 16-31: Reserved */
/* UC B n (Bn) */
#define EMIOS_B_SHIFT (0) /* Bits 0-15: B */
#define EMIOS_B_MASK (0xffff << EMIOS_B_SHIFT)
#define EMIOS_B(n) ((n << EMIOS_B_SHIFT) & EMIOS_B_MASK)
#define EMIOS_B(n) (((n) << EMIOS_B_SHIFT) & EMIOS_B_MASK)
/* Bits 16-31: Reserved */
/* UC Counter n (CNTn) */
@@ -314,7 +314,7 @@
/* Bit 15: Reserved */
#define EMIOS_C2_UCEXTPRE_SHIFT (16) /* Bits 16-19: Extended Prescaler (UCEXTPRE) */
#define EMIOS_C2_UCEXTPRE_MASK (0x0f << EMIOS_C2_UCEXTPRE_SHIFT)
#define EMIOS_C2_UCEXTPRE(n) ((n << EMIOS_C2_UCEXTPRE_SHIFT) & EMIOS_C2_UCEXTPRE_MASK)
#define EMIOS_C2_UCEXTPRE(n) (((n) << EMIOS_C2_UCEXTPRE_SHIFT) & EMIOS_C2_UCEXTPRE_MASK)
/* Bits 20-31: Reserved */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EMIOS_H */
arch/arm/src/s32k3xx/hardware/s32k3xx_flexcan.h
+4 -4
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@@ -2669,7 +2669,7 @@
/* Bit 13: Reserved */
#define CAN_CTRL1_ERRMSK (1 << 14) /* Bit 14: Error Interrupt Mask (ERRMSK) */
#define CAN_CTRL1_BOFFMSK (1 << 15) /* Bit 15: Bus Off Interrupt Mask (BOFFMSK) */
#define CAN_CTRL1_TIMINGMSK (0xFFFF << 16)
#define CAN_CTRL1_TIMINGMSK (0xffff << 16)
#define CAN_CTRL1_PSEG2_SHIFT (16) /* Bits 16-18: Phase Segment 2 (PSEG2) */
#define CAN_CTRL1_PSEG2_MASK (0x07 << CAN_CTRL1_PSEG2_SHIFT)
#define CAN_CTRL1_PSEG2(x) (((x) << CAN_CTRL1_PSEG2_SHIFT) & CAN_CTRL1_PSEG2_MASK)
@@ -3121,10 +3121,10 @@
/* CAN MB TX codes */
#define CAN_TXMB_INACTIVE 0x8 /* MB is not active. */
#define CAN_TXMB_ABORT 0x9 /* MB is aborted. */
#define CAN_TXMB_DATAORREMOTE 0xC /* MB is a TX Data Frame(when MB RTR = 0) or */
#define CAN_TXMB_DATAORREMOTE 0xc /* MB is a TX Data Frame(when MB RTR = 0) or */
/* MB is a TX Remote Request Frame (when MB RTR = 1). */
#define CAN_TXMB_TANSWER 0xE /* MB is a TX Response Request Frame from */
#define CAN_TXMB_TANSWER 0xe /* MB is a TX Response Request Frame from */
/* an incoming Remote Request Frame. */
#define CAN_TXMB_NOTUSED 0xF /* Not used.*/
#define CAN_TXMB_NOTUSED 0xf /* Not used.*/
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_CAN_H */
arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h
+38 -38
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@@ -31,7 +31,7 @@
#define FS26_M_FS (1 << 31) /* Bit 31: Main or Fail-safe register selection (M/FS) */
#define FS26_REG_ADDR_SHIFT (25) /* Bits 25-31: Register Address + M/FS */
#define FS26_REG_ADDR_MASK (0x7F << FS26_REG_ADDR_SHIFT)
#define FS26_REG_ADDR_MASK (0x7f << FS26_REG_ADDR_SHIFT)
#define FS26_REG_ADDR(n) (((n) << FS26_REG_ADDR_SHIFT) & FS26_REG_ADDR_MASK)
#define FS26_RW (1 << 24) /* Bit 24: Read/Write (reading Bit 24 = 0) */
@@ -49,17 +49,17 @@
/* FS26 Data encoding********************************************************/
#define FS26_DATA_LSB_SHIFT (8) /* Bits 8-15: DATA_LSB */
#define FS26_DATA_LSB_MASK (0xFF << FS26_DATA_LSB_SHIFT)
#define FS26_DATA_LSB_MASK (0xff << FS26_DATA_LSB_SHIFT)
#define FS26_DATA_LSB(n) (((n) << FS26_DATA_LSB_SHIFT) & FS26_DATA_LSB_MASK)
#define FS26_DATA_MSB_SHIFT (16) /* Bits 16-23: DATA_MSB */
#define FS26_DATA_MSB_MASK (0xFF << FS26_DATA_MSB_SHIFT)
#define FS26_DATA_MSB_MASK (0xff << FS26_DATA_MSB_SHIFT)
#define FS26_DATA_MSB(n) (((n) << FS26_DATA_MSB_SHIFT) & FS26_DATA_MSB_MASK)
#define FS26_DATA_SHIFT (8) /* Bits 8-23: DATA_MSB */
#define FS26_DATA_MASK (0xFFFF << FS26_DATA_SHIFT)
#define FS26_DATA_MASK (0xffff << FS26_DATA_SHIFT)
#define FS26_SET_DATA(n) (((n) << FS26_DATA_SHIFT) & FS26_DATA_MASK)
#define FS26_GET_DATA(n) (((n) & FS26_DATA_MASK) >> FS26_DATA_SHIFT)
#define FS26_CRC_SHIFT (0) /* Bits 0-7: CRC */
#define FS26_CRC_MASK (0xFF << FS26_CRC_SHIFT)
#define FS26_CRC_MASK (0xff << FS26_CRC_SHIFT)
#define FS26_CRC(n) (((n) << FS26_CRC_SHIFT) & FS26_CRC_MASK)
/* FS26 SPI register map */
@@ -74,12 +74,12 @@
#define FS26_M_VSUP_FLG (0x7) /* */
#define FS26_M_VSUP_MSK (0x8) /* */
#define FS26_M_WIO_FLG (0x9) /* */
#define FS26_M_WIO_MSK (0xA) /* */
#define FS26_M_COM_FLG (0xB) /* */
#define FS26_M_COM_MSK (0xC) /* */
#define FS26_M_SYS_CFG (0xD) /* */
#define FS26_M_TSD_CFG (0xE) /* */
#define FS26_M_REG_CFG (0xF) /* */
#define FS26_M_WIO_MSK (0xa) /* */
#define FS26_M_COM_FLG (0xb) /* */
#define FS26_M_COM_MSK (0xc) /* */
#define FS26_M_SYS_CFG (0xd) /* */
#define FS26_M_TSD_CFG (0xe) /* */
#define FS26_M_REG_CFG (0xf) /* */
#define FS26_M_WIO_CFG (0x10) /* */
#define FS26_M_REG_CTRL1 (0x11) /* */
#define FS26_M_REG_CTRL2 (0x12) /* */
@@ -102,12 +102,12 @@
#define FS26_FS_I_SAFE_INPUTS (0x47) /* */
#define FS26_FS_I_NOT_SAFE_INPUTS (0x48) /* */
#define FS26_FS_I_FSSM (0x49) /* */
#define FS26_FS_I_NOT_FSSM (0x4A) /* */
#define FS26_FS_WDW_DURATION (0x4B) /* */
#define FS26_FS_NOT_WDW_DURATION (0x4C) /* */
#define FS26_FS_WD_ANSWER (0x4D) /* */
#define FS26_FS_WD_TOKEN (0x4E) /* */
#define FS26_FS_ABIST_ON_DEMAND (0x4F) /* */
#define FS26_FS_I_NOT_FSSM (0x4a) /* */
#define FS26_FS_WDW_DURATION (0x4b) /* */
#define FS26_FS_NOT_WDW_DURATION (0x4c) /* */
#define FS26_FS_WD_ANSWER (0x4d) /* */
#define FS26_FS_WD_TOKEN (0x4e) /* */
#define FS26_FS_ABIST_ON_DEMAND (0x4f) /* */
#define FS26_FS_OVUV_REG_STATUS (0x50) /* */
#define FS26_FS_RELEASE_FS0B_FS1B (0x51) /* */
#define FS26_FS_SAFE_IOS_1 (0x52) /* */
@@ -243,11 +243,11 @@
#define WD_RFR_CNT_SHIFT (8) /* Reflect the value of the Watchdog Refresh Counter */
#define WD_RFR_CNT_MASK (0x7 << WD_RFR_CNT_SHIFT)
#define WD_RFR_CNT(n) (n & (0x7 << WD_RFR_CNT_SHIFT))
#define WD_RFR_CNT(n) ((n) & (0x7 << WD_RFR_CNT_SHIFT))
#define WD_ERR_CNT_SHIFT (0) /* Reflect the value of the Watchdog Error Counter */
#define WD_ERR_CNT_MASK (0xF << WD_ERR_CNT_SHIFT)
#define WD_ERR_CNT(n) ((n & (0x7 << WD_RFR_CNT_SHIFT)) > 11) ? (11) : ((n & (0x7 << WD_RFR_CNT_SHIFT)))
#define WD_ERR_CNT_MASK (0xf << WD_ERR_CNT_SHIFT)
#define WD_ERR_CNT(n) (((n) & (0x7 << WD_RFR_CNT_SHIFT)) > 11) ? (11) : (((n) & (0x7 << WD_RFR_CNT_SHIFT)))
/* FS26_FS_I_SAFE_INPUTS register */
@@ -349,13 +349,13 @@
#define DIS8S DIS8S_MASK
#define FLT_ERR_CNT_SHIFT (0) /* Reflect the value of the Watchdog Error Counter */
#define FLT_ERR_CNT_MASK (0xF << FLT_ERR_CNT_SHIFT)
#define FLT_ERR_CNT_MASK (0xf << FLT_ERR_CNT_SHIFT)
#define FLT_ERR_CNT(n) ((n & (0x7 << FLT_ERR_CNT_SHIFT)) > 12) ? (12) : ((n & (0x7 << FLT_ERR_CNT_SHIFT)))
/* FS26_FS_WDW_DURATION register */
#define WDW_PERIOD_SHIFT (12) /* Watchdog window period */
#define WDW_PERIOD_MASK (0xF << WDW_PERIOD_SHIFT)
#define WDW_PERIOD_MASK (0xf << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_DISABLE (0x0 << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_1MS (0x1 << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_2MS (0x2 << WDW_PERIOD_SHIFT)
@@ -366,12 +366,12 @@
# define WDW_PERIOD_12MS (0x7 << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_16MS (0x8 << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_24MS (0x9 << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_32MS (0xA << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_64MS (0xB << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_128MS (0xC << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_256MS (0xD << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_512MS (0xE << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_1024MS (0xF << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_32MS (0xa << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_64MS (0xb << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_128MS (0xc << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_256MS (0xd << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_512MS (0xe << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_1024MS (0xf << WDW_PERIOD_SHIFT)
#define WDW_DC_SHIFT (6) /* Watchdog window duty cycle */
#define WDW_DC_MASK (0x7 << WDW_DC_SHIFT)
@@ -382,7 +382,7 @@
# define WDW_DC_68_31 (0x4 << WDW_PERIOD_SHIFT)
#define WDW_RECOVERY_SHIFT (0) /* Watchdog window period */
#define WDW_RECOVERY_MASK (0xF << WDW_RECOVERY_SHIFT)
#define WDW_RECOVERY_MASK (0xf << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_DISABLE (0x0 << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_1MS (0x1 << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_2MS (0x2 << WDW_RECOVERY_SHIFT)
@@ -393,12 +393,12 @@
# define WDW_RECOVERY_12MS (0x7 << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_16MS (0x8 << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_24MS (0x9 << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_32MS (0xA << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_64MS (0xB << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_128MS (0xC << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_256MS (0xD << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_512MS (0xE << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_1024MS (0xF << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_32MS (0xa << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_64MS (0xb << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_128MS (0xc << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_256MS (0xd << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_512MS (0xe << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_1024MS (0xf << WDW_RECOVERY_SHIFT)
/* FS26_FS_DIAG_SAFETY1 register */
@@ -465,14 +465,14 @@
#define REG_CORRUPT REG_CORRUPT_MASK
#define FS_STATES_SHIFT (0) /* LBIST STATUS */
#define FS_STATES_MASK (0x1F << FS_STATES_SHIFT)
#define FS_STATES_MASK (0x1f << FS_STATES_SHIFT)
#define FS_STATES FS_STATES_MASK
# define FS_STATES_DEBUG_ENTRY (0x4 << FS_STATES_SHIFT)
# define FS_STATES_ENABLE_MON (0x6 << FS_STATES_SHIFT)
# define FS_STATES_RSTB_RELEASE (0x8 << FS_STATES_SHIFT)
# define FS_STATES_INIT_FS (0x9 << FS_STATES_SHIFT)
# define FS_STATES_SAFETY_OUT_NOT (0xA << FS_STATES_SHIFT)
# define FS_STATES_NORMAL (0xB << FS_STATES_SHIFT)
# define FS_STATES_SAFETY_OUT_NOT (0xa << FS_STATES_SHIFT)
# define FS_STATES_NORMAL (0xb << FS_STATES_SHIFT)
/* FS26_FS_GRL_FLAGS register */
arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h
+1 -1
View File
@@ -72,7 +72,7 @@
/* Bits 8-15: Reserved */
#define FXOSC_CTRL_EOCV_SHIFT (16) /* Bits 16-23: End of count value (EOCV) */
#define FXOSC_CTRL_EOCV_MASK (0xff << FXOSC_CTRL_EOCV_SHIFT)
#define FXOSC_CTRL_EOCV(n) ((n << FXOSC_CTRL_EOCV_SHIFT) & FXOSC_CTRL_EOCV_MASK)
#define FXOSC_CTRL_EOCV(n) (((n) << FXOSC_CTRL_EOCV_SHIFT) & FXOSC_CTRL_EOCV_MASK)
#define FXOSC_CTRL_COMP_EN (1 << 24) /* Bit 24: Comparator enable (COMP_EN) */
# define FXOSC_CTRL_COMP_DIS (0 << 24) /* Comparator disable */
/* Bits 25-30: Reserved */
arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h
+35 -36
View File
@@ -403,7 +403,7 @@
#define QSPI_LUTKEY_KEY_SHIFT (0) /* Bits 0-31: Key to lock or unlock the LUT (KEY) */
#define QSPI_LUTKEY_KEY_MASK (0xffffffff << QSPI_LUTKEY_KEY_SHIFT)
#define QSPI_LUTKEY_KEY (0x5AF05AF0UL)
#define QSPI_LUTKEY_KEY (0x5AF05AF0ul)
/* LUT Lock Configuration Register (LKCR) */
@@ -447,59 +447,58 @@
typedef enum
{
QSPI_SIDE_A1 = 0x00u, /* Serial flash connected on side A1 */
QSPI_SIDE_A2 = 0x01u, /* Serial flash connected on side A2 */
QSPI_SIDE_B1 = 0x02u, /* Serial flash connected on side B1 */
QSPI_SIDE_B2 = 0x03u, /* Serial flash connected on side B2 */
QSPI_SIDE_A1 = 0x00u, /* Serial flash connected on side A1 */
QSPI_SIDE_A2 = 0x01u, /* Serial flash connected on side A2 */
QSPI_SIDE_B1 = 0x02u, /* Serial flash connected on side B1 */
QSPI_SIDE_B2 = 0x03u, /* Serial flash connected on side B2 */
} s32k3xx_qspi_connectiontype;
/* flash operation type */
typedef enum
{
QSPI_OP_TYPE_CMD = 0x00u, /* Simple command */
QSPI_OP_TYPE_WRITE_REG = 0x01u, /* Write value in external flash register */
QSPI_OP_TYPE_RMW_REG = 0x02u, /* RMW command on external flash register */
QSPI_OP_TYPE_READ_REG = 0x03u, /* Read external flash register until expected value is read */
QSPI_OP_TYPE_QSPI_CFG = 0x04u, /* Re-configure QSPI controller */
QSPI_OP_TYPE_CMD = 0x00u, /* Simple command */
QSPI_OP_TYPE_WRITE_REG = 0x01u, /* Write value in external flash register */
QSPI_OP_TYPE_RMW_REG = 0x02u, /* RMW command on external flash register */
QSPI_OP_TYPE_READ_REG = 0x03u, /* Read external flash register until expected value is read */
QSPI_OP_TYPE_QSPI_CFG = 0x04u, /* Re-configure QSPI controller */
} s32k3xx_qspi_optype;
/* Lut commands */
typedef enum
{
QSPI_LUT_INSTR_STOP = (0U << 10U), /* End of sequence */
QSPI_LUT_INSTR_CMD = (1U << 10U), /* Command */
QSPI_LUT_INSTR_ADDR = (2U << 10U), /* Address */
QSPI_LUT_INSTR_DUMMY = (3U << 10U), /* Dummy cycles */
QSPI_LUT_INSTR_MODE = (4U << 10U), /* 8-bit mode */
QSPI_LUT_INSTR_MODE2 = (5U << 10U), /* 2-bit mode */
QSPI_LUT_INSTR_MODE4 = (6U << 10U), /* 4-bit mode */
QSPI_LUT_INSTR_READ = (7U << 10U), /* Read data */
QSPI_LUT_INSTR_WRITE = (8U << 10U), /* Write data */
QSPI_LUT_INSTR_JMP_ON_CS = (9U << 10U), /* Jump on chip select deassert and stop */
QSPI_LUT_INSTR_ADDR_DDR = (10U << 10U), /* Address - DDR mode */
QSPI_LUT_INSTR_MODE_DDR = (11U << 10U), /* 8-bit mode - DDR mode */
QSPI_LUT_INSTR_MODE2_DDR = (12U << 10U), /* 2-bit mode - DDR mode */
QSPI_LUT_INSTR_MODE4_DDR = (13U << 10U), /* 4-bit mode - DDR mode */
QSPI_LUT_INSTR_READ_DDR = (14U << 10U), /* Read data - DDR mode */
QSPI_LUT_INSTR_WRITE_DDR = (15U << 10U), /* Write data - DDR mode */
QSPI_LUT_INSTR_DATA_LEARN = (16U << 10U), /* Data learning pattern */
QSPI_LUT_INSTR_CMD_DDR = (17U << 10U), /* Command - DDR mode */
QSPI_LUT_INSTR_CADDR = (18U << 10U), /* Column address */
QSPI_LUT_INSTR_CADDR_DDR = (19U << 10U), /* Column address - DDR mode */
QSPI_LUT_INSTR_JMP_TO_SEQ = (20U << 10U), /* Jump on chip select deassert and continue */
QSPI_LUT_INSTR_STOP = (0u << 10u), /* End of sequence */
QSPI_LUT_INSTR_CMD = (1u << 10u), /* Command */
QSPI_LUT_INSTR_ADDR = (2u << 10u), /* Address */
QSPI_LUT_INSTR_DUMMY = (3u << 10u), /* Dummy cycles */
QSPI_LUT_INSTR_MODE = (4u << 10u), /* 8-bit mode */
QSPI_LUT_INSTR_MODE2 = (5u << 10u), /* 2-bit mode */
QSPI_LUT_INSTR_MODE4 = (6u << 10u), /* 4-bit mode */
QSPI_LUT_INSTR_READ = (7u << 10u), /* Read data */
QSPI_LUT_INSTR_WRITE = (8u << 10u), /* Write data */
QSPI_LUT_INSTR_JMP_ON_CS = (9u << 10u), /* Jump on chip select deassert and stop */
QSPI_LUT_INSTR_ADDR_DDR = (10u << 10u), /* Address - DDR mode */
QSPI_LUT_INSTR_MODE_DDR = (11u << 10u), /* 8-bit mode - DDR mode */
QSPI_LUT_INSTR_MODE2_DDR = (12u << 10u), /* 2-bit mode - DDR mode */
QSPI_LUT_INSTR_MODE4_DDR = (13u << 10u), /* 4-bit mode - DDR mode */
QSPI_LUT_INSTR_READ_DDR = (14u << 10u), /* Read data - DDR mode */
QSPI_LUT_INSTR_WRITE_DDR = (15u << 10u), /* Write data - DDR mode */
QSPI_LUT_INSTR_DATA_LEARN = (16u << 10u), /* Data learning pattern */
QSPI_LUT_INSTR_CMD_DDR = (17u << 10u), /* Command - DDR mode */
QSPI_LUT_INSTR_CADDR = (18u << 10u), /* Column address */
QSPI_LUT_INSTR_CADDR_DDR = (19u << 10u), /* Column address - DDR mode */
QSPI_LUT_INSTR_JMP_TO_SEQ = (20u << 10u), /* Jump on chip select deassert and continue */
} s32k3xx_qspi_lutcommandstype;
/* Lut pad options */
typedef enum
{
QSPI_LUT_PADS_1 = (0U << 8U), /* 1 Pad */
QSPI_LUT_PADS_2 = (1U << 8U), /* 2 Pads */
QSPI_LUT_PADS_4 = (2U << 8U), /* 4 Pads */
QSPI_LUT_PADS_8 = (3U << 8U), /* 8 Pads */
QSPI_LUT_PADS_1 = (0u << 8u), /* 1 Pad */
QSPI_LUT_PADS_2 = (1u << 8u), /* 2 Pads */
QSPI_LUT_PADS_4 = (2u << 8u), /* 4 Pads */
QSPI_LUT_PADS_8 = (3u << 8u), /* 8 Pads */
} s32k3xx_qspi_lutpadstype;
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H */
arch/arm/src/s32k3xx/hardware/s32k3xx_virtwrapper.h
+2 -2
View File
@@ -198,7 +198,7 @@
/* Parameter_n Register (REG_D1055_1040) */
/* Bits 0-29: Reserved */
#define VIRTWRAPPER_REG_D_REG_GCR_SHIFT (30) /* Bits 30-31: GCR REgister Of REG_PROT (REG_GCR) */
#define VIRTWRAPPER_REG_D_REG_GCR_SHIFT (30) /* Bits 30-31: GCR Register Of REG_PROT (REG_GCR) */
#define VIRTWRAPPER_REG_D_REG_GCR_MASK (0x03 << VIRTWRAPPER_REG_D_REG_GCR_SHIFT)
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_VIRTWRAPPER_H */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_VIRTWRAPPER_H */
arch/arm/src/s32k3xx/s32k3xx_edma.c
+37 -1
View File
@@ -94,7 +94,7 @@
/* Align to the cache line size which we assume is >= 8 */
# define EDMA_ALIGN ARMV7M_DCACHE_LINESIZE
# define EDMA_ALIGN_MASK (EDMA_ALIGN-1)
# define EDMA_ALIGN_MASK (EDMA_ALIGN - 1)
# define EDMA_ALIGN_UP(n) (((n) + EDMA_ALIGN_MASK) & ~EDMA_ALIGN_MASK)
#else
@@ -164,6 +164,42 @@ struct s32k3xx_edma_s
* Private Data
****************************************************************************/
uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
{
S32K3XX_EDMA_CH0_CSR,
S32K3XX_EDMA_CH1_CSR,
S32K3XX_EDMA_CH2_CSR,
S32K3XX_EDMA_CH3_CSR,
S32K3XX_EDMA_CH4_CSR,
S32K3XX_EDMA_CH5_CSR,
S32K3XX_EDMA_CH6_CSR,
S32K3XX_EDMA_CH7_CSR,
S32K3XX_EDMA_CH8_CSR,
S32K3XX_EDMA_CH9_CSR,
S32K3XX_EDMA_CH10_CSR,
S32K3XX_EDMA_CH11_CSR,
S32K3XX_EDMA_CH12_CSR,
S32K3XX_EDMA_CH13_CSR,
S32K3XX_EDMA_CH14_CSR,
S32K3XX_EDMA_CH15_CSR,
S32K3XX_EDMA_CH16_CSR,
S32K3XX_EDMA_CH17_CSR,
S32K3XX_EDMA_CH18_CSR,
S32K3XX_EDMA_CH19_CSR,
S32K3XX_EDMA_CH20_CSR,
S32K3XX_EDMA_CH21_CSR,
S32K3XX_EDMA_CH22_CSR,
S32K3XX_EDMA_CH23_CSR,
S32K3XX_EDMA_CH24_CSR,
S32K3XX_EDMA_CH25_CSR,
S32K3XX_EDMA_CH26_CSR,
S32K3XX_EDMA_CH27_CSR,
S32K3XX_EDMA_CH28_CSR,
S32K3XX_EDMA_CH29_CSR,
S32K3XX_EDMA_CH30_CSR,
S32K3XX_EDMA_CH31_CSR
};
/* The state of the eDMA */
static struct s32k3xx_edma_s g_edma;