diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h index cb39c54d5ec..7f2978c3b11 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h @@ -1160,42 +1160,6 @@ #define S32K3XX_EDMA_TCD31_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_CSR_OFFSET) #define S32K3XX_EDMA_TCD31_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_BITER_OFFSET) -uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] = -{ - S32K3XX_EDMA_CH0_CSR, - S32K3XX_EDMA_CH1_CSR, - S32K3XX_EDMA_CH2_CSR, - S32K3XX_EDMA_CH3_CSR, - S32K3XX_EDMA_CH4_CSR, - S32K3XX_EDMA_CH5_CSR, - S32K3XX_EDMA_CH6_CSR, - S32K3XX_EDMA_CH7_CSR, - S32K3XX_EDMA_CH8_CSR, - S32K3XX_EDMA_CH9_CSR, - S32K3XX_EDMA_CH10_CSR, - S32K3XX_EDMA_CH11_CSR, - S32K3XX_EDMA_CH12_CSR, - S32K3XX_EDMA_CH13_CSR, - S32K3XX_EDMA_CH14_CSR, - S32K3XX_EDMA_CH15_CSR, - S32K3XX_EDMA_CH16_CSR, - S32K3XX_EDMA_CH17_CSR, - S32K3XX_EDMA_CH18_CSR, - S32K3XX_EDMA_CH19_CSR, - S32K3XX_EDMA_CH20_CSR, - S32K3XX_EDMA_CH21_CSR, - S32K3XX_EDMA_CH22_CSR, - S32K3XX_EDMA_CH23_CSR, - S32K3XX_EDMA_CH24_CSR, - S32K3XX_EDMA_CH25_CSR, - S32K3XX_EDMA_CH26_CSR, - S32K3XX_EDMA_CH27_CSR, - S32K3XX_EDMA_CH28_CSR, - S32K3XX_EDMA_CH29_CSR, - S32K3XX_EDMA_CH30_CSR, - S32K3XX_EDMA_CH31_CSR -}; - /* eDMA Register Bitfield Definitions ***************************************/ /* Management Page Control Register (CSR) */ diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h index b53f34ef87c..1ac45a4380e 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h @@ -624,7 +624,7 @@ /* MAC Extended Configuration (MAC_EXT_CONFIGURATION) */ #define EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT (0) /* Bits 0-14: Giant Packet Size Limit */ -#define EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFF << EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT) +#define EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3fff << EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT) #define EMAC_MAC_EXT_CONFIGURATION_GPSL(n) (((n) << EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT) & EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK) #define EMAC_MAC_EXT_CONFIGURATION_DCRCC (1 << 16) /* Bit 16: Disable CRC Checking For Received Packets */ #define EMAC_MAC_EXT_CONFIGURATION_SPEN (1 << 17) /* Bit 17: Slow Protocol Detection Enable */ @@ -632,7 +632,7 @@ #define EMAC_MAC_EXT_CONFIGURATION_PDC (1 << 19) /* Bit 19: Packet Duplication Control */ #define EMAC_MAC_EXT_CONFIGURATION_EIPGEN (1 << 24) /* Bit 24: Extended Inter-Packet Gap Enable */ #define EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT (25) /* Bits 25-30: Extended Inter-Packet Gap */ -#define EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK (0x1F << EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT) +#define EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK (0x1f << EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT) #define EMAC_MAC_EXT_CONFIGURATION_EIPG(n) (((n) << EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT) & EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK) /* MAC Packet Filter (MAC_PACKET_FILTER) */ @@ -655,23 +655,23 @@ /* MAC Watchdog Timeout (MAC_WATCHDOG_TIMEOUT) */ #define EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT (0) /* Bits 0-4: Watchdog Timeout */ -#define EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK (0xF << EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT) +#define EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK (0xf << EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT) #define EMAC_MAC_WATCHDOG_TIMEOUT_WTO(n) (((n) << EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT) & EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK) #define EMAC_MAC_WATCHDOG_TIMEOUT_PWE (1 << 8) /* Bit 8: Programmable Watchdog Enable */ /* MAC Hash Table First 32 Bits (MAC_HASH_TABLE_REG0) */ #define EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT (0) /* Bits 0-32: MAC Hash Table First 32 Bits */ -#define EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xFFFFFFFF << EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT) +#define EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xffffffff << EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT) #define EMAC_MAC_HASH_TABLE_REG0_HT31T0(n) (((n) << EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT) & EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK) /* MAC Hash Table Second 32 Bits (MAC_HASH_TABLE_REG1) */ #define EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT (0) /* Bits 0-32: MAC Hash Table Second 32 Bits */ -#define EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xFFFFFFFF << EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT) +#define EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xffffffff << EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT) #define EMAC_MAC_HASH_TABLE_REG1_HT63T32(n) (((n) << EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT) & EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK) /* MAC VLAN Tag (MAC_VLAN_TAG) */ #define EMAC_MAC_VLAN_TAG_VL_SHIFT (0) /* Bits 0-16: VLAN Tag Identifier for Receive Packets */ -#define EMAC_MAC_VLAN_TAG_VL_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_VL_SHIFT) +#define EMAC_MAC_VLAN_TAG_VL_MASK (0xffff << EMAC_MAC_VLAN_TAG_VL_SHIFT) #define EMAC_MAC_VLAN_TAG_VL(n) (((n) << EMAC_MAC_VLAN_TAG_VL_SHIFT) & EMAC_MAC_VLAN_TAG_VL_MASK) #define EMAC_MAC_VLAN_TAG_ETV (1 << 16) /* Bit 16: Enable Tag For VLAN */ #define EMAC_MAC_VLAN_TAG_VTIM (1 << 17) /* Bit 17: VLAN Tag Inverse Match Enable */ @@ -715,7 +715,7 @@ /* MAC VLAN Tag Data (MAC_VLAN_TAG_DATA) */ #define EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */ -#define EMAC_MAC_VLAN_TAG_DATA_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT) +#define EMAC_MAC_VLAN_TAG_DATA_VID_MASK (0xffff << EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT) #define EMAC_MAC_VLAN_TAG_DATA_VID(n) (((n) << EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT) & EMAC_MAC_VLAN_TAG_DATA_VID_MASK) #define EMAC_MAC_VLAN_TAG_DATA_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */ #define EMAC_MAC_VLAN_TAG_DATA_ETV (1 << 17) /* Bit 17: VLAN Comparison */ @@ -727,7 +727,7 @@ /* MAC VLAN Tag Filter 0 (MAC_VLAN_TAG_FILTER0) */ #define EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */ -#define EMAC_MAC_VLAN_TAG_FILTER0_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT) +#define EMAC_MAC_VLAN_TAG_FILTER0_VID_MASK (0xffff << EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT) #define EMAC_MAC_VLAN_TAG_FILTER0_VID(n) (((n) << EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER0_VID_MASK) #define EMAC_MAC_VLAN_TAG_FILTER0_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */ #define EMAC_MAC_VLAN_TAG_FILTER0_ETV (1 << 17) /* Bit 17: VLAN Comparison */ @@ -739,7 +739,7 @@ /* MAC VLAN Tag Filter 1 (MAC_VLAN_TAG_FILTER1) */ #define EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */ -#define EMAC_MAC_VLAN_TAG_FILTER1_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT) +#define EMAC_MAC_VLAN_TAG_FILTER1_VID_MASK (0xffff << EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT) #define EMAC_MAC_VLAN_TAG_FILTER1_VID(n) (((n) << EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER1_VID_MASK) #define EMAC_MAC_VLAN_TAG_FILTER1_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */ #define EMAC_MAC_VLAN_TAG_FILTER1_ETV (1 << 17) /* Bit 17: VLAN Comparison */ @@ -751,7 +751,7 @@ /* MAC VLAN Tag Filter 2 (MAC_VLAN_TAG_FILTER2) */ #define EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */ -#define EMAC_MAC_VLAN_TAG_FILTER2_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT) +#define EMAC_MAC_VLAN_TAG_FILTER2_VID_MASK (0xffff << EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT) #define EMAC_MAC_VLAN_TAG_FILTER2_VID(n) (((n) << EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER2_VID_MASK) #define EMAC_MAC_VLAN_TAG_FILTER2_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */ #define EMAC_MAC_VLAN_TAG_FILTER2_ETV (1 << 17) /* Bit 17: VLAN Comparison */ @@ -763,7 +763,7 @@ /* MAC VLAN Tag Filter 3 (MAC_VLAN_TAG_FILTER3) */ #define EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */ -#define EMAC_MAC_VLAN_TAG_FILTER3_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT) +#define EMAC_MAC_VLAN_TAG_FILTER3_VID_MASK (0xffff << EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT) #define EMAC_MAC_VLAN_TAG_FILTER3_VID(n) (((n) << EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER3_VID_MASK) #define EMAC_MAC_VLAN_TAG_FILTER3_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */ #define EMAC_MAC_VLAN_TAG_FILTER3_ETV (1 << 17) /* Bit 17: VLAN Comparison */ @@ -775,12 +775,12 @@ /* MAC VLAN Hash Table (MAC_VLAN_HASH_TABLE) */ #define EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT (0) /* Bits 0-16: VLAN Hash Table */ -#define EMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK (0xFFFF << EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT) +#define EMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK (0xffff << EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT) #define EMAC_MAC_VLAN_HASH_TABLE_VLHT(n) (((n) << EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT) & EMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK) /* MAC VLAN Inclusion Or Replacement (MAC_VLAN_INCL) */ #define EMAC_MAC_VLAN_INCL_VLT_SHIFT (0) /* Bits 0-16: VLAN Tag For Transmit Packets */ -#define EMAC_MAC_VLAN_INCL_VLT_MASK (0xFFFF << EMAC_MAC_VLAN_INCL_VLT_SHIFT) +#define EMAC_MAC_VLAN_INCL_VLT_MASK (0xffff << EMAC_MAC_VLAN_INCL_VLT_SHIFT) #define EMAC_MAC_VLAN_INCL_VLT(n) (((n) << EMAC_MAC_VLAN_INCL_VLT_SHIFT) & EMAC_MAC_VLAN_INCL_VLT_MASK) #define EMAC_MAC_VLAN_INCL_VLC_SHIFT (16) /* Bits 16-18: VLAN Tag Control */ #define EMAC_MAC_VLAN_INCL_VLC_MASK (0x3 << EMAC_MAC_VLAN_INCL_VLC_SHIFT) @@ -795,7 +795,7 @@ /* Inner VLAN Tag Inclusion Or Replacement (MAC_INNER_VLAN_INCL) */ #define EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT (0) /* Bits 0-16: VLAN Tag For Transmit Packets */ -#define EMAC_MAC_INNER_VLAN_INCL_VLT_MASK (0xFFFF << EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT) +#define EMAC_MAC_INNER_VLAN_INCL_VLT_MASK (0xffff << EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT) #define EMAC_MAC_INNER_VLAN_INCL_VLT(n) (((n) << EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT) & EMAC_MAC_INNER_VLAN_INCL_VLT_MASK) #define EMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT (16) /* Bits 16-18: VLAN Tag Control in Transmit Packets */ #define EMAC_MAC_INNER_VLAN_INCL_VLC_MASK (0x3 << EMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT) @@ -812,7 +812,7 @@ #define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT(n) (((n) << EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT) & EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK) #define EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ (1 << 7) /* Bit 7: Disable Zero-Quanta Pause */ #define EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT (16) /* Bits 16-32: Pause Time */ -#define EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK (0xFFFF << EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT) +#define EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK (0xffff << EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT) #define EMAC_MAC_Q0_TX_FLOW_CTRL_PT(n) (((n) << EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT) & EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK) /* MAC Receive Flow Control (MAC_RX_FLOW_CTRL) */ @@ -865,10 +865,10 @@ /* MAC RxQ Control 2 (MAC_RXQ_CTRL2) */ #define EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT (0) /* Bits 0-8: Priorities Selected In Receive Queue 0 */ -#define EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK (0xFF << EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT) +#define EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK (0xff << EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT) #define EMAC_MAC_RXQ_CTRL2_PSRQ0(n) (((n) << EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT) & EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK) #define EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT (8) /* Bits 8-16: Priorities Selected In Receive Queue 1 */ -#define EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK (0xFF << EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT) +#define EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK (0xff << EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT) #define EMAC_MAC_RXQ_CTRL2_PSRQ1(n) (((n) << EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT) & EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK) /* MAC Interrupt Status (MAC_INTERRUPT_STATUS) */ @@ -903,10 +903,10 @@ /* MAC Version (MAC_VERSION) */ #define EMAC_MAC_VERSION_IPVER_SHIFT (0) /* Bits 0-8: IP Version */ -#define EMAC_MAC_VERSION_IPVER_MASK (0xFF << EMAC_MAC_VERSION_IPVER_SHIFT) +#define EMAC_MAC_VERSION_IPVER_MASK (0xff << EMAC_MAC_VERSION_IPVER_SHIFT) #define EMAC_MAC_VERSION_IPVER(n) (((n) << EMAC_MAC_VERSION_IPVER_SHIFT) & EMAC_MAC_VERSION_IPVER_MASK) #define EMAC_MAC_VERSION_CFGVER_SHIFT (8) /* Bits 8-16: IP Configuration Version */ -#define EMAC_MAC_VERSION_CFGVER_MASK (0xFF << EMAC_MAC_VERSION_CFGVER_SHIFT) +#define EMAC_MAC_VERSION_CFGVER_MASK (0xff << EMAC_MAC_VERSION_CFGVER_SHIFT) #define EMAC_MAC_VERSION_CFGVER(n) (((n) << EMAC_MAC_VERSION_CFGVER_SHIFT) & EMAC_MAC_VERSION_CFGVER_MASK) /* MAC Debug (MAC_DEBUG) */ @@ -935,7 +935,7 @@ #define EMAC_MAC_HW_FEATURE0_TXCOESEL (1 << 14) /* Bit 14: Transmit Checksum Offload Feature */ #define EMAC_MAC_HW_FEATURE0_RXCOESEL (1 << 16) /* Bit 16: Receive Checksum Offload Feature */ #define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT (18) /* Bits 18-23: MAC Addresses 1-31 */ -#define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK (0x1F << EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT) +#define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK (0x1f << EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT) #define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL(n) (((n) << EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT) & EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK) #define EMAC_MAC_HW_FEATURE0_MACADR32SEL (1 << 23) /* Bit 23: MAC Addresses 32-63 */ #define EMAC_MAC_HW_FEATURE0_MACADR64SEL (1 << 24) /* Bit 24: MAC Addresses 64-127 */ @@ -949,11 +949,11 @@ /* MAC Hardware Feature 1 (MAC_HW_FEATURE1) */ #define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT (0) /* Bits 0-5: MTL Receive FIFO Size Feature */ -#define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK (0x1F << EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) +#define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK (0x1f << EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) #define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE(n) (((n) << EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) & EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK) #define EMAC_MAC_HW_FEATURE1_SPRAM (1 << 5) /* Bit 5: Single Port RAM Feature */ #define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT (6) /* Bits 6-11: MTL Transmit FIFO Size Feature */ -#define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK (0x1F << EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) +#define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK (0x1f << EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) #define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE(n) (((n) << EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) & EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK) #define EMAC_MAC_HW_FEATURE1_OSTEN (1 << 11) /* Bit 11: One-Step Timestamping Enable Feature */ #define EMAC_MAC_HW_FEATURE1_PTOEN (1 << 12) /* Bit 12: PTP Offload Enable Feature */ @@ -972,21 +972,21 @@ #define EMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK (0x3 << EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT) #define EMAC_MAC_HW_FEATURE1_HASHTBLSZ(n) (((n) << EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT) & EMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK) #define EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT (27) /* Bits 27-31: L3 Or L4 Filter Number */ -#define EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK (0xF << EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT) +#define EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK (0xf << EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT) #define EMAC_MAC_HW_FEATURE1_L3L4FNUM(n) (((n) << EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT) & EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK) /* MAC Hardware Feature 2 (MAC_HW_FEATURE2) */ #define EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT (0) /* Bits 0-4: Number Of MTL Receive Queues */ -#define EMAC_MAC_HW_FEATURE2_RXQCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT) +#define EMAC_MAC_HW_FEATURE2_RXQCNT_MASK (0xf << EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT) #define EMAC_MAC_HW_FEATURE2_RXQCNT(n) (((n) << EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_RXQCNT_MASK) #define EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT (6) /* Bits 6-10: Number Of MTL Transmit Queues */ -#define EMAC_MAC_HW_FEATURE2_TXQCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT) +#define EMAC_MAC_HW_FEATURE2_TXQCNT_MASK (0xf << EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT) #define EMAC_MAC_HW_FEATURE2_TXQCNT(n) (((n) << EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_TXQCNT_MASK) #define EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT (12) /* Bits 12-16: Number Of DMA Receive Channels */ -#define EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT) +#define EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK (0xf << EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT) #define EMAC_MAC_HW_FEATURE2_RXCHCNT(n) (((n) << EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK) #define EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT (18) /* Bits 18-22: Number Of DMA Transmit Channels */ -#define EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT) +#define EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK (0xf << EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT) #define EMAC_MAC_HW_FEATURE2_TXCHCNT(n) (((n) << EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK) #define EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT (24) /* Bits 24-27: Number Of PPS Outputs */ #define EMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK (0x7 << EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT) @@ -1052,18 +1052,18 @@ /* MAC FSM ACT Timer (MAC_FSM_ACT_TIMER) */ #define EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT (0) /* Bits 0-10: CSR Clocks For 1 us Tic */ -#define EMAC_MAC_FSM_ACT_TIMER_TMR_MASK (0x3FF << EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT) +#define EMAC_MAC_FSM_ACT_TIMER_TMR_MASK (0x3ff << EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT) #define EMAC_MAC_FSM_ACT_TIMER_TMR(n) (((n) << EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_TMR_MASK) #define EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT (16) /* Bits 16-20: Normal Mode Timeout Value */ -#define EMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK (0xF << EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT) +#define EMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK (0xf << EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT) #define EMAC_MAC_FSM_ACT_TIMER_NTMRMD(n) (((n) << EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK) #define EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT (20) /* Bits 20-24: Large Mode Timeout Value */ -#define EMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK (0xF << EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT) +#define EMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK (0xf << EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT) #define EMAC_MAC_FSM_ACT_TIMER_LTMRMD(n) (((n) << EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK) /* SCS_REG 1 (SCS_REG1) */ #define EMAC_SCS_REG1_MAC_SCS1_SHIFT (0) /* Bits 0-32: MAC SCS 1 */ -#define EMAC_SCS_REG1_MAC_SCS1_MASK (0xFFFFFFFF << EMAC_SCS_REG1_MAC_SCS1_SHIFT) +#define EMAC_SCS_REG1_MAC_SCS1_MASK (0xffffffff << EMAC_SCS_REG1_MAC_SCS1_SHIFT) #define EMAC_SCS_REG1_MAC_SCS1(n) (((n) << EMAC_SCS_REG1_MAC_SCS1_SHIFT) & EMAC_SCS_REG1_MAC_SCS1_MASK) /* MAC MDIO Address (MAC_MDIO_ADDRESS) */ @@ -1073,26 +1073,26 @@ #define EMAC_MAC_MDIO_ADDRESS_GOC_1 (1 << 3) /* Bit 3: GMII Operation Command 1 */ #define EMAC_MAC_MDIO_ADDRESS_SKAP (1 << 4) /* Bit 4: Skip Address Packet */ #define EMAC_MAC_MDIO_ADDRESS_CR_SHIFT (8) /* Bits 8-12: CSR Clock Range */ -#define EMAC_MAC_MDIO_ADDRESS_CR_MASK (0xF << EMAC_MAC_MDIO_ADDRESS_CR_SHIFT) +#define EMAC_MAC_MDIO_ADDRESS_CR_MASK (0xf << EMAC_MAC_MDIO_ADDRESS_CR_SHIFT) #define EMAC_MAC_MDIO_ADDRESS_CR(n) (((n) << EMAC_MAC_MDIO_ADDRESS_CR_SHIFT) & EMAC_MAC_MDIO_ADDRESS_CR_MASK) #define EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT (12) /* Bits 12-15: Number Of Trailing Clocks */ #define EMAC_MAC_MDIO_ADDRESS_NTC_MASK (0x7 << EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT) #define EMAC_MAC_MDIO_ADDRESS_NTC(n) (((n) << EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT) & EMAC_MAC_MDIO_ADDRESS_NTC_MASK) #define EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT (16) /* Bits 16-21: Register Or Device Address */ -#define EMAC_MAC_MDIO_ADDRESS_RDA_MASK (0x1F << EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) +#define EMAC_MAC_MDIO_ADDRESS_RDA_MASK (0x1f << EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) #define EMAC_MAC_MDIO_ADDRESS_RDA(n) (((n) << EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) & EMAC_MAC_MDIO_ADDRESS_RDA_MASK) #define EMAC_MAC_MDIO_ADDRESS_PA_SHIFT (21) /* Bits 21-26: Physical Layer Address */ -#define EMAC_MAC_MDIO_ADDRESS_PA_MASK (0x1F << EMAC_MAC_MDIO_ADDRESS_PA_SHIFT) +#define EMAC_MAC_MDIO_ADDRESS_PA_MASK (0x1f << EMAC_MAC_MDIO_ADDRESS_PA_SHIFT) #define EMAC_MAC_MDIO_ADDRESS_PA(n) (((n) << EMAC_MAC_MDIO_ADDRESS_PA_SHIFT) & EMAC_MAC_MDIO_ADDRESS_PA_MASK) #define EMAC_MAC_MDIO_ADDRESS_BTB (1 << 26) /* Bit 26: Back-To-Back Transactions */ #define EMAC_MAC_MDIO_ADDRESS_PSE (1 << 27) /* Bit 27: Preamble Suppression Enable */ /* MAC MDIO Data (MAC_MDIO_DATA) */ #define EMAC_MAC_MDIO_DATA_GD_SHIFT (0) /* Bits 0-16: GMII Data */ -#define EMAC_MAC_MDIO_DATA_GD_MASK (0xFFFF << EMAC_MAC_MDIO_DATA_GD_SHIFT) +#define EMAC_MAC_MDIO_DATA_GD_MASK (0xffff << EMAC_MAC_MDIO_DATA_GD_SHIFT) #define EMAC_MAC_MDIO_DATA_GD(n) (((n) << EMAC_MAC_MDIO_DATA_GD_SHIFT) & EMAC_MAC_MDIO_DATA_GD_MASK) #define EMAC_MAC_MDIO_DATA_RA_SHIFT (16) /* Bits 16-32: Register Address */ -#define EMAC_MAC_MDIO_DATA_RA_MASK (0xFFFF << EMAC_MAC_MDIO_DATA_RA_SHIFT) +#define EMAC_MAC_MDIO_DATA_RA_MASK (0xffff << EMAC_MAC_MDIO_DATA_RA_SHIFT) #define EMAC_MAC_MDIO_DATA_RA(n) (((n) << EMAC_MAC_MDIO_DATA_RA_SHIFT) & EMAC_MAC_MDIO_DATA_RA_MASK) /* MAC CSR Software Control (MAC_CSR_SW_CTRL) */ @@ -1111,17 +1111,17 @@ /* MAC Presentation Time (MAC_PRESN_TIME_NS) */ #define EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT (0) /* Bits 0-32: MAC 1722 Presentation Time (In Nanoseconds) */ -#define EMAC_MAC_PRESN_TIME_NS_MPTN_MASK (0xFFFFFFFF << EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT) +#define EMAC_MAC_PRESN_TIME_NS_MPTN_MASK (0xffffffff << EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT) #define EMAC_MAC_PRESN_TIME_NS_MPTN(n) (((n) << EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT) & EMAC_MAC_PRESN_TIME_NS_MPTN_MASK) /* MAC Presentation Time Update (MAC_PRESN_TIME_UPDT) */ #define EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT (0) /* Bits 0-32: MAC 1722 Presentation Time Update */ -#define EMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK (0xFFFFFFFF << EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT) +#define EMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK (0xffffffff << EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT) #define EMAC_MAC_PRESN_TIME_UPDT_MPTU(n) (((n) << EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT) & EMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK) /* MAC Address 0 High (MAC_ADDRESS0_HIGH) */ #define EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT (0) /* Bits 0-16: MAC Address 0 [47:32] */ -#define EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK (0xFFFF << EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT) +#define EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK (0xffff << EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT) #define EMAC_MAC_ADDRESS0_HIGH_ADDRHI(n) (((n) << EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK) #define EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT (16) /* Bits 16-18: DMA Channel Select */ #define EMAC_MAC_ADDRESS0_HIGH_DCS_MASK (0x3 << EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT) @@ -1130,43 +1130,43 @@ /* MAC Address 0 Low (MAC_ADDRESS0_LOW) */ #define EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT (0) /* Bits 0-32: MAC Address 0 [31:0] */ -#define EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK (0xFFFFFFFF << EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT) +#define EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK (0xffffffff << EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT) #define EMAC_MAC_ADDRESS0_LOW_ADDRLO(n) (((n) << EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK) /* MAC Address 1 High (MAC_ADDRESS1_HIGH) */ #define EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT (0) /* Bits 0-16: MAC Address 1 [47:32] */ -#define EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK (0xFFFF << EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT) +#define EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK (0xffff << EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT) #define EMAC_MAC_ADDRESS1_HIGH_ADDRHI(n) (((n) << EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK) #define EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT (16) /* Bits 16-18: DMA Channel Select */ #define EMAC_MAC_ADDRESS1_HIGH_DCS_MASK (0x3 << EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT) #define EMAC_MAC_ADDRESS1_HIGH_DCS(n) (((n) << EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_DCS_MASK) #define EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT (24) /* Bits 24-30: Mask Byte Control */ -#define EMAC_MAC_ADDRESS1_HIGH_MBC_MASK (0x3F << EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT) +#define EMAC_MAC_ADDRESS1_HIGH_MBC_MASK (0x3f << EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT) #define EMAC_MAC_ADDRESS1_HIGH_MBC(n) (((n) << EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_MBC_MASK) #define EMAC_MAC_ADDRESS1_HIGH_SA (1 << 30) /* Bit 30: Source Address */ #define EMAC_MAC_ADDRESS1_HIGH_AE (1 << 31) /* Bit 31: Address Enable */ /* MAC Address 1 Low (MAC_ADDRESS1_LOW) */ #define EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT (0) /* Bits 0-32: MAC Address 1 [31:0] */ -#define EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK (0xFFFFFFFF << EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT) +#define EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK (0xffffffff << EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT) #define EMAC_MAC_ADDRESS1_LOW_ADDRLO(n) (((n) << EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK) /* MAC Address 2 High (MAC_ADDRESS2_HIGH) */ #define EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT (0) /* Bits 0-16: MAC Address 1 [47:32] */ -#define EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK (0xFFFF << EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT) +#define EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK (0xffff << EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT) #define EMAC_MAC_ADDRESS2_HIGH_ADDRHI(n) (((n) << EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK) #define EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT (16) /* Bits 16-18: DMA Channel Select */ #define EMAC_MAC_ADDRESS2_HIGH_DCS_MASK (0x3 << EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT) #define EMAC_MAC_ADDRESS2_HIGH_DCS(n) (((n) << EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_DCS_MASK) #define EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT (24) /* Bits 24-30: Mask Byte Control */ -#define EMAC_MAC_ADDRESS2_HIGH_MBC_MASK (0x3F << EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT) +#define EMAC_MAC_ADDRESS2_HIGH_MBC_MASK (0x3f << EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT) #define EMAC_MAC_ADDRESS2_HIGH_MBC(n) (((n) << EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_MBC_MASK) #define EMAC_MAC_ADDRESS2_HIGH_SA (1 << 30) /* Bit 30: Source Address */ #define EMAC_MAC_ADDRESS2_HIGH_AE (1 << 31) /* Bit 31: Address Enable */ /* MAC Address 2 Low (MAC_ADDRESS2_LOW) */ #define EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT (0) /* Bits 0-32: MAC Address 1 [31:0] */ -#define EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK (0xFFFFFFFF << EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT) +#define EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK (0xffffffff << EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT) #define EMAC_MAC_ADDRESS2_LOW_ADDRLO(n) (((n) << EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK) /* MMC Control (MMC_CONTROL) */ @@ -1292,27 +1292,27 @@ /* Transmit Octet Count Good Bad (TX_OCTET_COUNT_GOOD_BAD) */ #define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT (0) /* Bits 0-32: Transmit Octet Count Good Bad */ -#define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK (0xFFFFFFFF << EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT) +#define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK (0xffffffff << EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT) #define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(n) (((n) << EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT) & EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK) /* Transmit Packet Count Good Bad (TX_PACKET_COUNT_GOOD_BAD) */ #define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT (0) /* Bits 0-32: Transmit Packet Count Good Bad */ -#define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK (0xFFFFFFFF << EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT) +#define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK (0xffffffff << EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT) #define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(n) (((n) << EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT) & EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK) /* Transmit Broadcast Packets Good (TX_BROADCAST_PACKETS_GOOD) */ #define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT (0) /* Bits 0-32: Transmit Broadcast Packets Good */ -#define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK (0xFFFFFFFF << EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT) +#define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK (0xffffffff << EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT) #define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(n) (((n) << EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT) & EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK) /* Transmit Multicast Packets Good (TX_MULTICAST_PACKETS_GOOD) */ #define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT (0) /* Bits 0-32: Transmit Multicast Packets Good */ -#define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK (0xFFFFFFFF << EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT) +#define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK (0xffffffff << EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT) #define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(n) (((n) << EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT) & EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK) /* Transmit 64-Octet Packets Good Bad (TX_64OCTETS_PACKETS_GOOD_BAD) */ #define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT (0) /* Bits 0-32: Transmit 64-Octet Packets Good Bad */ -#define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK (0xFFFFFFFF << EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT) +#define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK (0xffffffff << EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT) #define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(n) (((n) << EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT) & EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK) /* Transmit 65 To 127 Octet Packets Good Bad @@ -1320,7 +1320,7 @@ */ #define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT (0) /* Bits 0-32: Transmit 65 To 127 Octet Packets Good Bad */ -#define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK (0xFFFFFFFF << EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT) +#define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK (0xffffffff << EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT) #define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(n) (((n) << EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT) & EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK) /* Transmit 128 To 255 Octet Packets Good Bad @@ -1328,7 +1328,7 @@ */ #define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT (0) /* Bits 0-32: Transmit 128 To 255 Octet Packets Good Bad */ -#define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK (0xFFFFFFFF << EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT) +#define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK (0xffffffff << EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT) #define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(n) (((n) << EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT) & EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK) /* Transmit 256 To 511 Octet Packets Good Bad @@ -1336,7 +1336,7 @@ */ #define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT (0) /* Bits 0-32: Transmit 256 To 511 Octet Packets Good Bad */ -#define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK (0xFFFFFFFF << EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT) +#define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK (0xffffffff << EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT) #define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(n) (((n) << EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT) & EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK) /* Transmit 512 To 1023 Octet Packets Good Bad @@ -1344,7 +1344,7 @@ */ #define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT (0) /* Bits 0-32: Transmit 512 To 1023 Octet Packets Good Bad */ -#define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK (0xFFFFFFFF << EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT) +#define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK (0xffffffff << EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT) #define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(n) (((n) << EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT) & EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK) /* Transmit 1024 To Max Octet Packets Good Bad @@ -1352,7 +1352,7 @@ */ #define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT (0) /* Bits 0-32: Transmit 1024 To Max Octet Packets Good Bad */ -#define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK (0xFFFFFFFF << EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT) +#define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK (0xffffffff << EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT) #define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(n) (((n) << EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT) & EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK) /* Transmit Unicast Packets Good Bad @@ -1360,22 +1360,22 @@ */ #define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT (0) /* Bits 0-32: Transmit Unicast Packets Good Bad */ -#define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK (0xFFFFFFFF << EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT) +#define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK (0xffffffff << EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT) #define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(n) (((n) << EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT) & EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK) /* Transmit Multicast Packets Good Bad (TX_MULTICAST_PACKETS_GOOD_BAD) */ #define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT (0) /* Bits 0-32: Transmit Multicast Packets Good Bad */ -#define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK (0xFFFFFFFF << EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT) +#define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK (0xffffffff << EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT) #define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(n) (((n) << EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT) & EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK) /* Transmit Broadcast Packets Good Bad (TX_BROADCAST_PACKETS_GOOD_BAD) */ #define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT (0) /* Bits 0-32: Transmit Broadcast Packets Good Bad */ -#define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK (0xFFFFFFFF << EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT) +#define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK (0xffffffff << EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT) #define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(n) (((n) << EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT) & EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK) /* Transmit Underflow Error Packets (TX_UNDERFLOW_ERROR_PACKETS) */ #define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT (0) /* Bits 0-32: Transmit Underflow Error Packets */ -#define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK (0xFFFFFFFF << EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT) +#define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK (0xffffffff << EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT) #define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(n) (((n) << EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT) & EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK) /* Transmit Single Collision Good Packets @@ -1383,7 +1383,7 @@ */ #define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT (0) /* Bits 0-32: Transmit Single Collision Good Packets */ -#define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK (0xFFFFFFFF << EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT) +#define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK (0xffffffff << EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT) #define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(n) (((n) << EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT) & EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK) /* Transmit Multiple Collision Good Packets @@ -1391,117 +1391,117 @@ */ #define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT (0) /* Bits 0-32: Transmit Multiple Collision Good Packets */ -#define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK (0xFFFFFFFF << EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT) +#define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK (0xffffffff << EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT) #define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(n) (((n) << EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT) & EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK) /* Transmit Deferred Packets (TX_DEFERRED_PACKETS) */ #define EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT (0) /* Bits 0-32: Transmit Deferred Packets */ -#define EMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK (0xFFFFFFFF << EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT) +#define EMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK (0xffffffff << EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT) #define EMAC_TX_DEFERRED_PACKETS_TXDEFRD(n) (((n) << EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT) & EMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK) /* Transmit Late Collision Packets (TX_LATE_COLLISION_PACKETS) */ #define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT (0) /* Bits 0-32: Transmit Late Collision Packets */ -#define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK (0xFFFFFFFF << EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT) +#define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK (0xffffffff << EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT) #define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(n) (((n) << EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT) & EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK) /* Transmit Excessive Collision Packets (TX_EXCESSIVE_COLLISION_PACKETS) */ #define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT (0) /* Bits 0-32: Transmit Excessive Collision Packets */ -#define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK (0xFFFFFFFF << EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT) +#define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK (0xffffffff << EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT) #define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(n) (((n) << EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT) & EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK) /* Transmit Carrier Error Packets (TX_CARRIER_ERROR_PACKETS) */ #define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT (0) /* Bits 0-32: Transmit Carrier Error Packets */ -#define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK (0xFFFFFFFF << EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT) +#define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK (0xffffffff << EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT) #define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR(n) (((n) << EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT) & EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK) /* Transmit Octet Count Good (TX_OCTET_COUNT_GOOD) */ #define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT (0) /* Bits 0-32: Transmit Octet Count Good */ -#define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK (0xFFFFFFFF << EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT) +#define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK (0xffffffff << EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT) #define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG(n) (((n) << EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT) & EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK) /* Transmit Packet Count Good (TX_PACKET_COUNT_GOOD) */ #define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT (0) /* Bits 0-32: Transmit Packet Count Good */ -#define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK (0xFFFFFFFF << EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT) +#define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK (0xffffffff << EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT) #define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG(n) (((n) << EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT) & EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK) /* Transmit Excessive Deferral Error (TX_EXCESSIVE_DEFERRAL_ERROR) */ #define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT (0) /* Bits 0-32: Transmit Excessive Deferral Error */ -#define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK (0xFFFFFFFF << EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT) +#define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK (0xffffffff << EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT) #define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(n) (((n) << EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT) & EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK) /* Transmit Pause Packets (TX_PAUSE_PACKETS) */ #define EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT (0) /* Bits 0-32: Transmit Pause Packets */ -#define EMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK (0xFFFFFFFF << EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT) +#define EMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK (0xffffffff << EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT) #define EMAC_TX_PAUSE_PACKETS_TXPAUSE(n) (((n) << EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT) & EMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK) /* Transmit VLAN Packets Good (TX_VLAN_PACKETS_GOOD) */ #define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT (0) /* Bits 0-32: Transmit VLAN Packets Good */ -#define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK (0xFFFFFFFF << EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT) +#define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK (0xffffffff << EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT) #define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG(n) (((n) << EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT) & EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK) /* Transmit O Size Packets Good (TX_OSIZE_PACKETS_GOOD) */ #define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT (0) /* Bits 0-32: Transmit O Size Packets Good */ -#define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK (0xFFFFFFFF << EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT) +#define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK (0xffffffff << EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT) #define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(n) (((n) << EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT) & EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK) /* Receive Packets Count Good Bad (RX_PACKETS_COUNT_GOOD_BAD) */ #define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT (0) /* Bits 0-32: Receive Packets Count Good Bad */ -#define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK (0xFFFFFFFF << EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT) +#define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK (0xffffffff << EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT) #define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(n) (((n) << EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT) & EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK) /* Receive Octet Count Good Bad (RX_OCTET_COUNT_GOOD_BAD) */ #define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT (0) /* Bits 0-32: Receive Octet Count Good Bad */ -#define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK (0xFFFFFFFF << EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT) +#define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK (0xffffffff << EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT) #define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(n) (((n) << EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT) & EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK) /* Receive Octet Count Good (RX_OCTET_COUNT_GOOD) */ #define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT (0) /* Bits 0-32: Receive Octet Count Good */ -#define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK (0xFFFFFFFF << EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT) +#define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK (0xffffffff << EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT) #define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG(n) (((n) << EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT) & EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK) /* Receive Broadcast Packets Good (RX_BROADCAST_PACKETS_GOOD) */ #define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT (0) /* Bits 0-32: Receive Broadcast Packets Good */ -#define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK (0xFFFFFFFF << EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT) +#define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK (0xffffffff << EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT) #define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(n) (((n) << EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT) & EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK) /* Receive Multicast Packets Good (RX_MULTICAST_PACKETS_GOOD) */ #define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT (0) /* Bits 0-32: Receive Multicast Packets Good */ -#define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK (0xFFFFFFFF << EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT) +#define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK (0xffffffff << EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT) #define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(n) (((n) << EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT) & EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK) /* Receive CRC Error Packets (RX_CRC_ERROR_PACKETS) */ #define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT (0) /* Bits 0-32: Receive CRC Error Packets */ -#define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK (0xFFFFFFFF << EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT) +#define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK (0xffffffff << EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT) #define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR(n) (((n) << EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT) & EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK) /* Receive Alignment Error Packets (RX_ALIGNMENT_ERROR_PACKETS) */ #define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT (0) /* Bits 0-32: Receive Alignment Error Packets */ -#define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK (0xFFFFFFFF << EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT) +#define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK (0xffffffff << EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT) #define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(n) (((n) << EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT) & EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK) /* Receive Runt Error Packets (RX_RUNT_ERROR_PACKETS) */ #define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT (0) /* Bits 0-32: Receive Runt Error Packets */ -#define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK (0xFFFFFFFF << EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT) +#define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK (0xffffffff << EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT) #define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(n) (((n) << EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT) & EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK) /* Receive Jabber Error Packets (RX_JABBER_ERROR_PACKETS) */ #define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT (0) /* Bits 0-32: Receive Jabber Error Packets */ -#define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK (0xFFFFFFFF << EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT) +#define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK (0xffffffff << EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT) #define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR(n) (((n) << EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT) & EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK) /* Receive Undersize Packets Good (RX_UNDERSIZE_PACKETS_GOOD) */ #define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT (0) /* Bits 0-32: Receive Undersize Packets Good */ -#define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK (0xFFFFFFFF << EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT) +#define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK (0xffffffff << EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT) #define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(n) (((n) << EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT) & EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK) /* Receive Oversize Packets Good (RX_OVERSIZE_PACKETS_GOOD) */ #define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT (0) /* Bits 0-32: Receive Oversize Packets Good */ -#define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK (0xFFFFFFFF << EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT) +#define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK (0xffffffff << EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT) #define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(n) (((n) << EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT) & EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK) /* Receive 64 Octets Packets Good Bad (RX_64OCTETS_PACKETS_GOOD_BAD) */ #define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT (0) /* Bits 0-32: Receive 64 Octets Packets Good Bad */ -#define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK (0xFFFFFFFF << EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT) +#define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK (0xffffffff << EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT) #define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(n) (((n) << EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT) & EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK) /* Receive 65-127 Octets Packets Good Bad @@ -1509,7 +1509,7 @@ */ #define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT (0) /* Bits 0-32: Receive 65-127 Octets Packets Good Bad */ -#define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK (0xFFFFFFFF << EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT) +#define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK (0xffffffff << EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT) #define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(n) (((n) << EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT) & EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK) /* Receive 128-255 Octets Packets Good Bad @@ -1517,7 +1517,7 @@ */ #define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT (0) /* Bits 0-32: Receive 128-255 Octets Packets Good Bad */ -#define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK (0xFFFFFFFF << EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT) +#define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK (0xffffffff << EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT) #define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(n) (((n) << EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT) & EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK) /* Receive 256-511 Octets Packets Good Bad @@ -1525,7 +1525,7 @@ */ #define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT (0) /* Bits 0-32: Receive 256-511 Octets Packets Good Bad */ -#define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK (0xFFFFFFFF << EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT) +#define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK (0xffffffff << EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT) #define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(n) (((n) << EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT) & EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK) /* Receive 512-1023 Octets Packets Good Bad @@ -1533,7 +1533,7 @@ */ #define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT (0) /* Bits 0-32: Receive 512-1023 Octets Packets Good Bad */ -#define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK (0xFFFFFFFF << EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT) +#define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK (0xffffffff << EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT) #define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(n) (((n) << EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT) & EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK) /* Receive 1024 To Max Octets Good Bad @@ -1541,52 +1541,52 @@ */ #define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT (0) /* Bits 0-32: Receive 1024-Max Octets Good Bad */ -#define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK (0xFFFFFFFF << EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT) +#define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK (0xffffffff << EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT) #define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(n) (((n) << EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT) & EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK) /* Receive Unicast Packets Good (RX_UNICAST_PACKETS_GOOD) */ #define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT (0) /* Bits 0-32: Receive Unicast Packets Good */ -#define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK (0xFFFFFFFF << EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT) +#define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK (0xffffffff << EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT) #define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(n) (((n) << EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT) & EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK) /* Receive Length Error Packets (RX_LENGTH_ERROR_PACKETS) */ #define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT (0) /* Bits 0-32: Receive Length Error Packets */ -#define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK (0xFFFFFFFF << EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT) +#define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK (0xffffffff << EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT) #define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(n) (((n) << EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT) & EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK) /* Receive Out of Range Type Packet (RX_OUT_OF_RANGE_TYPE_PACKETS) */ #define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT (0) /* Bits 0-32: Receive Out of Range Type Packet */ -#define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK (0xFFFFFFFF << EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT) +#define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK (0xffffffff << EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT) #define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(n) (((n) << EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT) & EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK) /* Receive Pause Packets (RX_PAUSE_PACKETS) */ #define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT (0) /* Bits 0-32: Receive Pause Packets */ -#define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK (0xFFFFFFFF << EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT) +#define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK (0xffffffff << EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT) #define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT(n) (((n) << EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT) & EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK) /* Receive FIFO Overflow Packets (RX_FIFO_OVERFLOW_PACKETS) */ #define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT (0) /* Bits 0-32: Receive FIFO Overflow Packets */ -#define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK (0xFFFFFFFF << EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT) +#define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK (0xffffffff << EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT) #define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(n) (((n) << EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT) & EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK) /* Receive VLAN Packets Good Bad (RX_VLAN_PACKETS_GOOD_BAD) */ #define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT (0) /* Bits 0-32: Receive VLAN Packets Good Bad */ -#define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK (0xFFFFFFFF << EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT) +#define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK (0xffffffff << EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT) #define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(n) (((n) << EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT) & EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK) /* Receive Watchdog Error Packets (RX_WATCHDOG_ERROR_PACKETS) */ #define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT (0) /* Bits 0-32: Receive Watchdog Error Packets */ -#define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK (0xFFFFFFFF << EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT) +#define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK (0xffffffff << EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT) #define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(n) (((n) << EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT) & EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK) /* Receive Receive Error Packets (RX_RECEIVE_ERROR_PACKETS) */ #define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT (0) /* Bits 0-32: Receive Receive Error Packets */ -#define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK (0xFFFFFFFF << EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT) +#define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK (0xffffffff << EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT) #define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(n) (((n) << EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT) & EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK) /* Receive Control Packets Good (RX_CONTROL_PACKETS_GOOD) */ #define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT (0) /* Bits 0-32: Receive Control Packets Good */ -#define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK (0xFFFFFFFF << EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT) +#define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK (0xffffffff << EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT) #define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(n) (((n) << EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT) & EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK) /* MMC Transmit FPE Fragment Counter Interrupt Status @@ -1602,12 +1602,12 @@ /* Transmit FPE Fragment Counter (MMC_TX_FPE_FRAGMENT_CNTR) */ #define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT (0) /* Bits 0-32: Transmit FPE Fragment Counter */ -#define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK (0xFFFFFFFF << EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT) +#define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK (0xffffffff << EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT) #define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC(n) (((n) << EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT) & EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK) /* Transmit Hold Request Counter (MMC_TX_HOLD_REQ_CNTR) */ #define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT (0) /* Bits 0-32: Transmit Hold Request Counter */ -#define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK (0xFFFFFFFF << EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT) +#define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK (0xffffffff << EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT) #define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC(n) (((n) << EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT) & EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK) /* MMC Receive Packet Assembly Error Counter Interrupt Status @@ -1630,22 +1630,22 @@ */ #define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT (0) /* Bits 0-32: Packet Assembly Error Counter */ -#define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK (0xFFFFFFFF << EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT) +#define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK (0xffffffff << EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT) #define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC(n) (((n) << EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT) & EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK) /* MMC Receive Packet SMD Error Counter (MMC_RX_PACKET_SMD_ERR_CNTR) */ #define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT (0) /* Bits 0-32: Packet SMD Error Counter */ -#define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK (0xFFFFFFFF << EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT) +#define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK (0xffffffff << EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT) #define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC(n) (((n) << EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT) & EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK) /* MMC Receive Packet Assembly OK Counter (MMC_RX_PACKET_ASSEMBLY_OK_CNTR) */ #define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT (0) /* Bits 0-32: Packet Assembly OK Counter */ -#define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK (0xFFFFFFFF << EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT) +#define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK (0xffffffff << EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT) #define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC(n) (((n) << EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT) & EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK) /* MMC Receive FPE Fragment Counter (MMC_RX_FPE_FRAGMENT_CNTR) */ #define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT (0) /* Bits 0-32: FPE Fragment Counter */ -#define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK (0xFFFFFFFF << EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT) +#define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK (0xffffffff << EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT) #define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC(n) (((n) << EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT) & EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK) /* MAC Layer 3 Layer 4 Control 0 (MAC_L3_L4_CONTROL0) */ @@ -1655,10 +1655,10 @@ #define EMAC_MAC_L3_L4_CONTROL0_L3DAM0 (1 << 4) /* Bit 4: Layer 3 IP DA Match Enable */ #define EMAC_MAC_L3_L4_CONTROL0_L3DAIM0 (1 << 5) /* Bit 5: Layer 3 IP DA Inverse Match Enable */ #define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT (6) /* Bits 6-11: Layer 3 IP SA Higher Bits Match */ -#define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT) +#define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_MASK (0x1f << EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT) #define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0(n) (((n) << EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT) & EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_MASK) #define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT (11) /* Bits 11-16: Layer 3 IP DA Higher Bits Match */ -#define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT) +#define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_MASK (0x1f << EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT) #define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0(n) (((n) << EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT) & EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_MASK) #define EMAC_MAC_L3_L4_CONTROL0_L4PEN0 (1 << 16) /* Bit 16: Layer 4 Protocol Enable */ #define EMAC_MAC_L3_L4_CONTROL0_L4SPM0 (1 << 18) /* Bit 18: Layer 4 Source Port Match Enable */ @@ -1670,30 +1670,30 @@ /* MAC Layer 4 Address 0 (MAC_LAYER4_ADDRESS0) */ #define EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT (0) /* Bits 0-16: Layer 4 Source Port Number */ -#define EMAC_MAC_LAYER4_ADDRESS0_L4SP0_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT) +#define EMAC_MAC_LAYER4_ADDRESS0_L4SP0_MASK (0xffff << EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT) #define EMAC_MAC_LAYER4_ADDRESS0_L4SP0(n) (((n) << EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT) & EMAC_MAC_LAYER4_ADDRESS0_L4SP0_MASK) #define EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT (16) /* Bits 16-32: Layer 4 Destination Port Number */ -#define EMAC_MAC_LAYER4_ADDRESS0_L4DP0_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT) +#define EMAC_MAC_LAYER4_ADDRESS0_L4DP0_MASK (0xffff << EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT) #define EMAC_MAC_LAYER4_ADDRESS0_L4DP0(n) (((n) << EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT) & EMAC_MAC_LAYER4_ADDRESS0_L4DP0_MASK) /* MAC Layer 3 Address 0 Reg 0 (MAC_LAYER3_ADDR0_REG0) */ #define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT (0) /* Bits 0-32: Layer 3 Address 0 */ -#define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT) +#define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT) #define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00(n) (((n) << EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_MASK) /* MAC Layer 3 Address 1 Reg 0 (MAC_LAYER3_ADDR1_REG0) */ #define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT (0) /* Bits 0-32: Layer 3 Address 1 */ -#define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT) +#define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT) #define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10(n) (((n) << EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_MASK) /* MAC Layer 3 Address 2 Reg 0 (MAC_LAYER3_ADDR2_REG0) */ #define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT (0) /* Bits 0-32: Layer 3 Address 2 */ -#define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT) +#define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT) #define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20(n) (((n) << EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_MASK) /* MAC Layer 3 Address 3 Reg 0 (MAC_LAYER3_ADDR3_REG0) */ #define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT (0) /* Bits 0-32: Layer 3 Address 3 */ -#define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT) +#define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT) #define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30(n) (((n) << EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_MASK) /* MAC L3 L4 Control 1 (MAC_L3_L4_CONTROL1) */ @@ -1703,10 +1703,10 @@ #define EMAC_MAC_L3_L4_CONTROL1_L3DAM1 (1 << 4) /* Bit 4: Layer 3 IP DA Match Enable 1 */ #define EMAC_MAC_L3_L4_CONTROL1_L3DAIM1 (1 << 5) /* Bit 5: Layer 3 IP DA Inverse Match Enable 1 */ #define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT (6) /* Bits 6-11: Layer 3 IP SA Higher Bits Match 1 */ -#define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT) +#define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_MASK (0x1f << EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT) #define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1(n) (((n) << EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT) & EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_MASK) #define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT (11) /* Bits 11-16: Layer 3 IP DA Higher Bits Match 1 */ -#define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT) +#define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_MASK (0x1f << EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT) #define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1(n) (((n) << EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT) & EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_MASK) #define EMAC_MAC_L3_L4_CONTROL1_L4PEN1 (1 << 16) /* Bit 16: Layer 4 Protocol Enable 1 */ #define EMAC_MAC_L3_L4_CONTROL1_L4SPM1 (1 << 18) /* Bit 18: Layer 4 Source Port Match Enable 1 */ @@ -1718,30 +1718,30 @@ /* MAC Layer 4 Address 1 (MAC_LAYER4_ADDRESS1) */ #define EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT (0) /* Bits 0-16: Layer 4 Source Port Number 1 */ -#define EMAC_MAC_LAYER4_ADDRESS1_L4SP1_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT) +#define EMAC_MAC_LAYER4_ADDRESS1_L4SP1_MASK (0xffff << EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT) #define EMAC_MAC_LAYER4_ADDRESS1_L4SP1(n) (((n) << EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT) & EMAC_MAC_LAYER4_ADDRESS1_L4SP1_MASK) #define EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT (16) /* Bits 16-32: Layer 4 Destination Port Number 1 */ -#define EMAC_MAC_LAYER4_ADDRESS1_L4DP1_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT) +#define EMAC_MAC_LAYER4_ADDRESS1_L4DP1_MASK (0xffff << EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT) #define EMAC_MAC_LAYER4_ADDRESS1_L4DP1(n) (((n) << EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT) & EMAC_MAC_LAYER4_ADDRESS1_L4DP1_MASK) /* MAC Layer 3 Address 0 Reg 1 (MAC_LAYER3_ADDR0_REG1) */ #define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT (0) /* Bits 0-32: Layer 3 Address 0 */ -#define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT) +#define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT) #define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01(n) (((n) << EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_MASK) /* MAC Layer 3 Address 1 Reg 1 (MAC_LAYER3_ADDR1_REG1) */ #define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT (0) /* Bits 0-32: Layer 3 Address 1 */ -#define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT) +#define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT) #define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11(n) (((n) << EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_MASK) /* MAC Layer 3 Address 2 Reg 1 (MAC_LAYER3_ADDR2_REG1) */ #define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT (0) /* Bits 0-32: Layer 3 Address 2 */ -#define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT) +#define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT) #define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21(n) (((n) << EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_MASK) /* MAC Layer 3 Address 3 Reg 1 (MAC_LAYER3_ADDR3_REG1) */ #define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT (0) /* Bits 0-32: Layer 3 Address 3 */ -#define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT) +#define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT) #define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31(n) (((n) << EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_MASK) /* MAC L3 L4 Control 2 (MAC_L3_L4_CONTROL2) */ @@ -1751,10 +1751,10 @@ #define EMAC_MAC_L3_L4_CONTROL2_L3DAM2 (1 << 4) /* Bit 4: Layer 3 IP DA Match Enable 2 */ #define EMAC_MAC_L3_L4_CONTROL2_L3DAIM2 (1 << 5) /* Bit 5: Layer 3 IP DA Inverse Match Enable 2 */ #define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT (6) /* Bits 6-11: Layer 3 IP SA Higher Bits Match 2 */ -#define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT) +#define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_MASK (0x1f << EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT) #define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2(n) (((n) << EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT) & EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_MASK) #define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT (11) /* Bits 11-16: Layer 3 IP DA Higher Bits Match 2 */ -#define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT) +#define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_MASK (0x1f << EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT) #define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2(n) (((n) << EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT) & EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_MASK) #define EMAC_MAC_L3_L4_CONTROL2_L4PEN2 (1 << 16) /* Bit 16: Layer 4 Protocol Enable 2 */ #define EMAC_MAC_L3_L4_CONTROL2_L4SPM2 (1 << 18) /* Bit 18: Layer 4 Source Port Match Enable 2 */ @@ -1766,30 +1766,30 @@ /* MAC Layer 4 Address 2 (MAC_LAYER4_ADDRESS2) */ #define EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT (0) /* Bits 0-16: Layer 4 Source Port Number 2 */ -#define EMAC_MAC_LAYER4_ADDRESS2_L4SP2_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT) +#define EMAC_MAC_LAYER4_ADDRESS2_L4SP2_MASK (0xffff << EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT) #define EMAC_MAC_LAYER4_ADDRESS2_L4SP2(n) (((n) << EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT) & EMAC_MAC_LAYER4_ADDRESS2_L4SP2_MASK) #define EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT (16) /* Bits 16-32: Layer 4 Destination Port Number 2 */ -#define EMAC_MAC_LAYER4_ADDRESS2_L4DP2_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT) +#define EMAC_MAC_LAYER4_ADDRESS2_L4DP2_MASK (0xffff << EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT) #define EMAC_MAC_LAYER4_ADDRESS2_L4DP2(n) (((n) << EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT) & EMAC_MAC_LAYER4_ADDRESS2_L4DP2_MASK) /* MAC Layer 3 Address 0 Reg 2 (MAC_LAYER3_ADDR0_REG2) */ #define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT (0) /* Bits 0-32: Layer 3 Address 0 */ -#define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT) +#define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT) #define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02(n) (((n) << EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_MASK) /* MAC Layer 3 Address 1 Reg 2 (MAC_LAYER3_ADDR1_REG2) */ #define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT (0) /* Bits 0-32: Layer 3 Address 1 */ -#define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT) +#define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT) #define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12(n) (((n) << EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_MASK) /* MAC Layer 3 Address 2 Reg 2 (MAC_LAYER3_ADDR2_REG2) */ #define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT (0) /* Bits 0-32: Layer 3 Address 2 */ -#define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT) +#define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT) #define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22(n) (((n) << EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_MASK) /* MAC Layer 3 Address 3 Reg 2 (MAC_LAYER3_ADDR3_REG2) */ #define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT (0) /* Bits 0-32: Layer 3 Address 3 */ -#define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT) +#define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT) #define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32(n) (((n) << EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_MASK) /* MAC L3 L4 Control 3 (MAC_L3_L4_CONTROL3) */ @@ -1799,10 +1799,10 @@ #define EMAC_MAC_L3_L4_CONTROL3_L3DAM3 (1 << 4) /* Bit 4: Layer 3 IP DA Match Enable 3 */ #define EMAC_MAC_L3_L4_CONTROL3_L3DAIM3 (1 << 5) /* Bit 5: Layer 3 IP DA Inverse Match Enable 3 */ #define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT (6) /* Bits 6-11: Layer 3 IP SA Higher Bits Match 3 */ -#define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT) +#define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_MASK (0x1f << EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT) #define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3(n) (((n) << EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT) & EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_MASK) #define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT (11) /* Bits 11-16: Layer 3 IP DA Higher Bits Match 3 */ -#define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT) +#define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_MASK (0x1f << EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT) #define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3(n) (((n) << EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT) & EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_MASK) #define EMAC_MAC_L3_L4_CONTROL3_L4PEN3 (1 << 16) /* Bit 16: Layer 4 Protocol Enable 3 */ #define EMAC_MAC_L3_L4_CONTROL3_L4SPM3 (1 << 18) /* Bit 18: Layer 4 Source Port Match Enable 3 */ @@ -1814,30 +1814,30 @@ /* MAC Layer 4 Address 3 (MAC_LAYER4_ADDRESS3) */ #define EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT (0) /* Bits 0-16: Layer 4 Source Port Number 3 */ -#define EMAC_MAC_LAYER4_ADDRESS3_L4SP3_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT) +#define EMAC_MAC_LAYER4_ADDRESS3_L4SP3_MASK (0xffff << EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT) #define EMAC_MAC_LAYER4_ADDRESS3_L4SP3(n) (((n) << EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT) & EMAC_MAC_LAYER4_ADDRESS3_L4SP3_MASK) #define EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT (16) /* Bits 16-32: Layer 4 Destination Port Number 3 */ -#define EMAC_MAC_LAYER4_ADDRESS3_L4DP3_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT) +#define EMAC_MAC_LAYER4_ADDRESS3_L4DP3_MASK (0xffff << EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT) #define EMAC_MAC_LAYER4_ADDRESS3_L4DP3(n) (((n) << EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT) & EMAC_MAC_LAYER4_ADDRESS3_L4DP3_MASK) /* MAC Layer 3 Address 0 Reg 3 (MAC_LAYER3_ADDR0_REG3) */ #define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT (0) /* Bits 0-32: Layer 3 Address 0 */ -#define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT) +#define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT) #define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03(n) (((n) << EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_MASK) /* MAC Layer 3 Address 1 Reg 3 (MAC_LAYER3_ADDR1_REG3) */ #define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT (0) /* Bits 0-32: Layer 3 Address 1 */ -#define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT) +#define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT) #define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13(n) (((n) << EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_MASK) /* MAC Layer 3 Address 2 Reg 3 (MAC_LAYER3_ADDR2_REG3) */ #define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT (0) /* Bits 0-32: Layer 3 Address 2 */ -#define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT) +#define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT) #define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23(n) (((n) << EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_MASK) /* MAC Layer 3 Address 3 Reg 3 (MAC_LAYER3_ADDR3_REG3) */ #define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT (0) /* Bits 0-32: Layer 3 Address 3 */ -#define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT) +#define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT) #define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33(n) (((n) << EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_MASK) /* MAC Timestamp Control (MAC_TIMESTAMP_CONTROL) */ @@ -1865,36 +1865,36 @@ /* MAC Sub Second Increment (MAC_SUB_SECOND_INCREMENT) */ #define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT (8) /* Bits 8-16: Sub-Nanosecond Increment Value */ -#define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK (0xFF << EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT) +#define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK (0xff << EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT) #define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC(n) (((n) << EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT) & EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK) #define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT (16) /* Bits 16-24: Sub-Second Increment Value */ -#define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK (0xFF << EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT) +#define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK (0xff << EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT) #define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC(n) (((n) << EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT) & EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK) /* MAC System Time In Seconds (MAC_SYSTEM_TIME_SECONDS) */ #define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT (0) /* Bits 0-32: Timestamp Second */ -#define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_MASK (0xFFFFFFFF << EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT) +#define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_MASK (0xffffffff << EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT) #define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS(n) (((n) << EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_MASK) /* MAC System Time In Nanoseconds (MAC_SYSTEM_TIME_NANOSECONDS) */ #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT (0) /* Bits 0-31: Timestamp Sub Seconds */ -#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK (0x7FFFFFFF << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT) +#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK (0x7fffffff << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT) #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(n) (((n) << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK) /* MAC System Time Seconds Update (MAC_SYSTEM_TIME_SECONDS_UPDATE) */ #define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT (0) /* Bits 0-32: Timestamp Seconds */ -#define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK (0xFFFFFFFF << EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT) +#define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK (0xffffffff << EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT) #define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(n) (((n) << EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK) /* MAC System Time Nanoseconds Update (MAC_SYSTEM_TIME_NANOSECONDS_UPDATE) */ #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT (0) /* Bits 0-31: Timestamp Subseconds */ -#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK (0x7FFFFFFF << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT) +#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK (0x7fffffff << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT) #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(n) (((n) << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK) #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB (1 << 31) /* Bit 31: Add Or Subtract Time */ /* MAC Timestamp Addend (MAC_TIMESTAMP_ADDEND) */ #define EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT (0) /* Bits 0-32: Timestamp Addend Register */ -#define EMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT) +#define EMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK (0xffffffff << EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT) #define EMAC_MAC_TIMESTAMP_ADDEND_TSAR(n) (((n) << EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT) & EMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK) /* MAC System Time Higher Word In Seconds @@ -1902,7 +1902,7 @@ */ #define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT (0) /* Bits 0-16: Timestamp Higher Word Register */ -#define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK (0xFFFF << EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT) +#define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK (0xffff << EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT) #define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(n) (((n) << EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT) & EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK) /* MAC Timestamp Status (MAC_TIMESTAMP_STATUS) */ @@ -1922,7 +1922,7 @@ */ #define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT (0) /* Bits 0-31: Transmit Timestamp Status Low */ -#define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK (0x7FFFFFFF << EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT) +#define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK (0x7fffffff << EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT) #define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(n) (((n) << EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT) & EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK) #define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS (1 << 31) /* Bit 31: Transmit Timestamp Status Missed */ @@ -1931,7 +1931,7 @@ */ #define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT (0) /* Bits 0-32: Transmit Timestamp Status High */ -#define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK (0xFFFFFFFF << EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT) +#define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK (0xffffffff << EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT) #define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(n) (((n) << EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT) & EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK) /* MAC Timestamp Ingress Asymmetry Correction @@ -1939,7 +1939,7 @@ */ #define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT (0) /* Bits 0-32: One-Step Timestamp Ingress Asymmetry Correction */ -#define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT) +#define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK (0xffffffff << EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT) #define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK) /* MAC Timestamp Egress Asymmetry Correction @@ -1947,7 +1947,7 @@ */ #define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT (0) /* Bits 0-32: One-Step Timestamp Egress Asymmetry Correction */ -#define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT) +#define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK (0xffffffff << EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT) #define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK) /* MAC Timestamp Ingress Correction In Nanoseconds @@ -1955,7 +1955,7 @@ */ #define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0) /* Bits 0-32: Timestamp Ingress Correction */ -#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT) +#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xffffffff << EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT) #define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK) /* MAC Timestamp Egress Correction In Nanoseconds @@ -1963,7 +1963,7 @@ */ #define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0) /* Bits 0-32: Timestamp Egress Correction */ -#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT) +#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xffffffff << EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT) #define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK) /* MAC Timestamp Ingress Correction In Subnanoseconds @@ -1971,7 +1971,7 @@ */ #define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT (8) /* Bits 8-16: Timestamp Ingress Correction In Sub-Nanoseconds */ -#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK (0xFF << EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT) +#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK (0xff << EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT) #define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK) /* MAC Timestamp Engress Correction In Subnanoseconds @@ -1979,28 +1979,28 @@ */ #define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT (8) /* Bits 8-16: Timestamp Egress Correction In Sub-Nanoseconds */ -#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK (0xFF << EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT) +#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK (0xff << EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT) #define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK) /* MAC Timestamp Ingress Latency (MAC_TIMESTAMP_INGRESS_LATENCY) */ #define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT (8) /* Bits 8-16: Ingress Timestamp Latency In Nanoseconds */ -#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK (0xFF << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT) +#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK (0xff << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT) #define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK) #define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT (16) /* Bits 16-28: Ingress Timestamp Latency In Sub-Nanoseconds */ -#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK (0xFFF << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT) +#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK (0xfff << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT) #define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK) /* MAC Timestamp Egress Latecy (MAC_TIMESTAMP_EGRESS_LATENCY) */ #define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT (8) /* Bits 8-16: Egress Timestamp Latency In Sub-Nanoseconds */ -#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK (0xFF << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT) +#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK (0xff << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT) #define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK) #define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT (16) /* Bits 16-28: Egress Timestamp Latency In Nanoseconds */ -#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK (0xFFF << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT) +#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK (0xfff << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT) #define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK) /* MAC PPS Control (MAC_PPS_CONTROL) */ #define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT (0) /* Bits 0-4: PPS Output Frequency Control */ -#define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xF << EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT) +#define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xf << EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT) #define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(n) (((n) << EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK) #define EMAC_MAC_PPS_CONTROL_PPSEN0 (1 << 4) /* Bit 4: Flexible PPS Output Mode Enable 0 */ #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT (5) /* Bits 5-7: Target Time Register Mode For PPS0 Output */ @@ -2008,21 +2008,21 @@ #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL0(n) (((n) << EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_MASK) #define EMAC_MAC_PPS_CONTROL_MCGREN0 (1 << 7) /* Bit 7: MCGR Mode Enable For PPS0 Output */ #define EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT (8) /* Bits 8-12: Flexible PPS1 Output Control */ -#define EMAC_MAC_PPS_CONTROL_PPSCMD1_MASK (0xF << EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT) +#define EMAC_MAC_PPS_CONTROL_PPSCMD1_MASK (0xf << EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT) #define EMAC_MAC_PPS_CONTROL_PPSCMD1(n) (((n) << EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCMD1_MASK) #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT (13) /* Bits 13-15: Target Time Register Mode For PPS1 Output */ #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_MASK (0x3 << EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT) #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL1(n) (((n) << EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_MASK) #define EMAC_MAC_PPS_CONTROL_MCGREN1 (1 << 15) /* Bit 15: MCGR Mode Enable For PPS1 Output */ #define EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT (16) /* Bits 16-20: Flexible PPS2 Output Control */ -#define EMAC_MAC_PPS_CONTROL_PPSCMD2_MASK (0xF << EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT) +#define EMAC_MAC_PPS_CONTROL_PPSCMD2_MASK (0xf << EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT) #define EMAC_MAC_PPS_CONTROL_PPSCMD2(n) (((n) << EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCMD2_MASK) #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT (21) /* Bits 21-23: Target Time Register Mode For PPS2 Output */ #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_MASK (0x3 << EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT) #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL2(n) (((n) << EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_MASK) #define EMAC_MAC_PPS_CONTROL_MCGREN2 (1 << 23) /* Bit 23: MCGR Mode Enable For PPS2 Output */ #define EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT (24) /* Bits 24-28: Flexible PPS3 Output Control */ -#define EMAC_MAC_PPS_CONTROL_PPSCMD3_MASK (0xF << EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT) +#define EMAC_MAC_PPS_CONTROL_PPSCMD3_MASK (0xf << EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT) #define EMAC_MAC_PPS_CONTROL_PPSCMD3(n) (((n) << EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCMD3_MASK) #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT (29) /* Bits 29-31: Target Time Register Mode For PPS3 Output */ #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_MASK (0x3 << EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT) @@ -2031,86 +2031,86 @@ /* MAC PPS0 Target Time In Seconds (MAC_PPS0_TARGET_TIME_SECONDS) */ #define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT (0) /* Bits 0-32: PPS Target Time In Seconds Register */ -#define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK (0xFFFFFFFF << EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT) +#define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK (0xffffffff << EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT) #define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0(n) (((n) << EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT) & EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK) /* MAC PPS0 Target Time In Nanoseconds (MAC_PPS0_TARGET_TIME_NANOSECONDS) */ #define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT (0) /* Bits 0-31: Target Time Low For PPS0 */ -#define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK (0x7FFFFFFF << EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT) +#define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK (0x7fffffff << EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT) #define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(n) (((n) << EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT) & EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK) #define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0 (1 << 31) /* Bit 31: PPS Target Time Busy Status 0 */ /* MAC PPS0 Interval (MAC_PPS0_INTERVAL) */ #define EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT (0) /* Bits 0-32: PPS Output Signal Interval 0 */ -#define EMAC_MAC_PPS0_INTERVAL_PPSINT0_MASK (0xFFFFFFFF << EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT) +#define EMAC_MAC_PPS0_INTERVAL_PPSINT0_MASK (0xffffffff << EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT) #define EMAC_MAC_PPS0_INTERVAL_PPSINT0(n) (((n) << EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT) & EMAC_MAC_PPS0_INTERVAL_PPSINT0_MASK) /* MAC PPS0 Width (MAC_PPS0_WIDTH) */ #define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT (0) /* Bits 0-32: PPS Output Signal Width 0 */ -#define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_MASK (0xFFFFFFFF << EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT) +#define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_MASK (0xffffffff << EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT) #define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0(n) (((n) << EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT) & EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_MASK) /* MAC PPS1 Target Time In Seconds (MAC_PPS1_TARGET_TIME_SECONDS) */ #define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT (0) /* Bits 0-32: PPS Target Time In Seconds 1 */ -#define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK (0xFFFFFFFF << EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT) +#define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK (0xffffffff << EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT) #define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1(n) (((n) << EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT) & EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK) /* MAC PPS1 Target Time In Nanoseconds (MAC_PPS1_TARGET_TIME_NANOSECONDS) */ #define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT (0) /* Bits 0-31: Target Time Low For PPS1 */ -#define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK (0x7FFFFFFF << EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT) +#define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK (0x7fffffff << EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT) #define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(n) (((n) << EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT) & EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK) #define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1 (1 << 31) /* Bit 31: PPS Target Time Busy Status 1 */ /* MAC PPS1 Interval (MAC_PPS1_INTERVAL) */ #define EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT (0) /* Bits 0-32: PPS Output Signal Interval 1 */ -#define EMAC_MAC_PPS1_INTERVAL_PPSINT1_MASK (0xFFFFFFFF << EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT) +#define EMAC_MAC_PPS1_INTERVAL_PPSINT1_MASK (0xffffffff << EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT) #define EMAC_MAC_PPS1_INTERVAL_PPSINT1(n) (((n) << EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT) & EMAC_MAC_PPS1_INTERVAL_PPSINT1_MASK) /* MAC PPS1 Width (MAC_PPS1_WIDTH) */ #define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT (0) /* Bits 0-32: PPS Output Signal Width 1 */ -#define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK (0xFFFFFFFF << EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT) +#define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK (0xffffffff << EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT) #define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1(n) (((n) << EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT) & EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK) /* MAC PPS2 Taget Time In Seconds (MAC_PPS2_TARGET_TIME_SECONDS) */ #define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT (0) /* Bits 0-32: PPS Target Time In Seconds 2 */ -#define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK (0xFFFFFFFF << EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT) +#define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK (0xffffffff << EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT) #define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(n) (((n) << EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT) & EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK) /* MAC PPS2 Target Time In Nanoseconds (MAC_PPS2_TARGET_TIME_NANOSECONDS) */ #define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT (0) /* Bits 0-31: Target Time Low For PPS2 */ -#define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK (0x7FFFFFFF << EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT) +#define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK (0x7fffffff << EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT) #define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(n) (((n) << EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT) & EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK) #define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2 (1 << 31) /* Bit 31: PPS Target Time Busy Status 2 */ /* MAC PPS2 Interval (MAC_PPS2_INTERVAL) */ #define EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT (0) /* Bits 0-32: PPS Output Signal Interval 2 */ -#define EMAC_MAC_PPS2_INTERVAL_PPSINT2_MASK (0xFFFFFFFF << EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT) +#define EMAC_MAC_PPS2_INTERVAL_PPSINT2_MASK (0xffffffff << EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT) #define EMAC_MAC_PPS2_INTERVAL_PPSINT2(n) (((n) << EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT) & EMAC_MAC_PPS2_INTERVAL_PPSINT2_MASK) /* MAC PPS2 Width (MAC_PPS2_WIDTH) */ #define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT (0) /* Bits 0-32: PPS Output Signal Width 2 */ -#define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_MASK (0xFFFFFFFF << EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT) +#define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_MASK (0xffffffff << EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT) #define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2(n) (((n) << EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT) & EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_MASK) /* MAC PPS3 Target Time In Seconds (MAC_PPS3_TARGET_TIME_SECONDS) */ #define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT (0) /* Bits 0-32: PPS Target Time In Seconds 3 */ -#define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK (0xFFFFFFFF << EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT) +#define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK (0xffffffff << EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT) #define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3(n) (((n) << EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT) & EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK) /* MAC PPS3 Target Time In Nanoseconds (MAC_PPS3_TARGET_TIME_NANOSECONDS) */ #define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT (0) /* Bits 0-31: Target Time Low For PPS3 */ -#define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK (0x7FFFFFFF << EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT) +#define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK (0x7fffffff << EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT) #define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(n) (((n) << EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT) & EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK) #define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3 (1 << 31) /* Bit 31: PPS Target Time Register Busy 3 */ /* MAC PPS3 Interval (MAC_PPS3_INTERVAL) */ #define EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT (0) /* Bits 0-32: PPS Output Signal Interval */ -#define EMAC_MAC_PPS3_INTERVAL_PPSINT3_MASK (0xFFFFFFFF << EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT) +#define EMAC_MAC_PPS3_INTERVAL_PPSINT3_MASK (0xffffffff << EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT) #define EMAC_MAC_PPS3_INTERVAL_PPSINT3(n) (((n) << EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT) & EMAC_MAC_PPS3_INTERVAL_PPSINT3_MASK) /* MAC PPS3 Width (MAC_PPS3_WIDTH) */ #define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT (0) /* Bits 0-32: PPS Output Signal Width 3 */ -#define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_MASK (0xFFFFFFFF << EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT) +#define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_MASK (0xffffffff << EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT) #define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3(n) (((n) << EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT) & EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_MASK) /* MTL Operation Mode (MTL_OPERATION_MODE) */ @@ -2161,12 +2161,12 @@ #define EMAC_MTL_DBG_STS_PKTI (1 << 8) /* Bit 8: Receive Packet Available Interrupt Status */ #define EMAC_MTL_DBG_STS_STSI (1 << 9) /* Bit 9: Transmit Status Available Interrupt Status */ #define EMAC_MTL_DBG_STS_LOCR_SHIFT (15) /* Bits 15-32: Remaining Locations In FIFO */ -#define EMAC_MTL_DBG_STS_LOCR_MASK (0x1FFFF << EMAC_MTL_DBG_STS_LOCR_SHIFT) +#define EMAC_MTL_DBG_STS_LOCR_MASK (0x1fFFF << EMAC_MTL_DBG_STS_LOCR_SHIFT) #define EMAC_MTL_DBG_STS_LOCR(n) (((n) << EMAC_MTL_DBG_STS_LOCR_SHIFT) & EMAC_MTL_DBG_STS_LOCR_MASK) /* MTL FIFO Debug Data (MTL_FIFO_DEBUG_DATA) */ #define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT (0) /* Bits 0-32: FIFO Debug Data */ -#define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK (0xFFFFFFFF << EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT) +#define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK (0xffffffff << EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT) #define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA(n) (((n) << EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT) & EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK) /* MTL Interrupt Status (MTL_INTERRUPT_STATUS) */ @@ -2189,7 +2189,7 @@ #define EMAC_MTL_TBS_CTRL_LEGOS_MASK (0x7 << EMAC_MTL_TBS_CTRL_LEGOS_SHIFT) #define EMAC_MTL_TBS_CTRL_LEGOS(n) (((n) << EMAC_MTL_TBS_CTRL_LEGOS_SHIFT) & EMAC_MTL_TBS_CTRL_LEGOS_MASK) #define EMAC_MTL_TBS_CTRL_LEOS_SHIFT (8) /* Bits 8-32: Launch Expiry Offset */ -#define EMAC_MTL_TBS_CTRL_LEOS_MASK (0xFFFFFF << EMAC_MTL_TBS_CTRL_LEOS_SHIFT) +#define EMAC_MTL_TBS_CTRL_LEOS_MASK (0xffffff << EMAC_MTL_TBS_CTRL_LEOS_SHIFT) #define EMAC_MTL_TBS_CTRL_LEOS(n) (((n) << EMAC_MTL_TBS_CTRL_LEOS_SHIFT) & EMAC_MTL_TBS_CTRL_LEOS_MASK) /* MTL EST Control (MTL_EST_CONTROL) */ @@ -2204,10 +2204,10 @@ #define EMAC_MTL_EST_CONTROL_TILS_MASK (0x7 << EMAC_MTL_EST_CONTROL_TILS_SHIFT) #define EMAC_MTL_EST_CONTROL_TILS(n) (((n) << EMAC_MTL_EST_CONTROL_TILS_SHIFT) & EMAC_MTL_EST_CONTROL_TILS_MASK) #define EMAC_MTL_EST_CONTROL_CTOV_SHIFT (12) /* Bits 12-24: Current Time Offset Value */ -#define EMAC_MTL_EST_CONTROL_CTOV_MASK (0xFFF << EMAC_MTL_EST_CONTROL_CTOV_SHIFT) +#define EMAC_MTL_EST_CONTROL_CTOV_MASK (0xfff << EMAC_MTL_EST_CONTROL_CTOV_SHIFT) #define EMAC_MTL_EST_CONTROL_CTOV(n) (((n) << EMAC_MTL_EST_CONTROL_CTOV_SHIFT) & EMAC_MTL_EST_CONTROL_CTOV_MASK) #define EMAC_MTL_EST_CONTROL_PTOV_SHIFT (24) /* Bits 24-32: PTP Time Offset Value */ -#define EMAC_MTL_EST_CONTROL_PTOV_MASK (0xFF << EMAC_MTL_EST_CONTROL_PTOV_SHIFT) +#define EMAC_MTL_EST_CONTROL_PTOV_MASK (0xff << EMAC_MTL_EST_CONTROL_PTOV_SHIFT) #define EMAC_MTL_EST_CONTROL_PTOV(n) (((n) << EMAC_MTL_EST_CONTROL_PTOV_SHIFT) & EMAC_MTL_EST_CONTROL_PTOV_MASK) /* MTL EST Status (MTL_EST_STATUS) */ @@ -2218,10 +2218,10 @@ #define EMAC_MTL_EST_STATUS_CGCE (1 << 4) /* Bit 4: Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the Cycle Time (CTR) is less than or equal to the programmed Time Interval (TI) value after the optional Left Shifting */ #define EMAC_MTL_EST_STATUS_SWOL (1 << 7) /* Bit 7: S/W owned list When '0' indicates Gate control list number "0" is owned by software and when "1" indicates the Gate Control list "1" is owned by the software */ #define EMAC_MTL_EST_STATUS_BTRL_SHIFT (8) /* Bits 8-12: BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time =< New BTR + ((n) * New Cycle Time) becomes true */ -#define EMAC_MTL_EST_STATUS_BTRL_MASK (0xF << EMAC_MTL_EST_STATUS_BTRL_SHIFT) +#define EMAC_MTL_EST_STATUS_BTRL_MASK (0xf << EMAC_MTL_EST_STATUS_BTRL_SHIFT) #define EMAC_MTL_EST_STATUS_BTRL(n) (((n) << EMAC_MTL_EST_STATUS_BTRL_SHIFT) & EMAC_MTL_EST_STATUS_BTRL_MASK) #define EMAC_MTL_EST_STATUS_CGSN_SHIFT (16) /* Bits 16-20: Current GCL Slot Number Indicates the slot number of the GCL list */ -#define EMAC_MTL_EST_STATUS_CGSN_MASK (0xF << EMAC_MTL_EST_STATUS_CGSN_SHIFT) +#define EMAC_MTL_EST_STATUS_CGSN_MASK (0xf << EMAC_MTL_EST_STATUS_CGSN_SHIFT) #define EMAC_MTL_EST_STATUS_CGSN(n) (((n) << EMAC_MTL_EST_STATUS_CGSN_SHIFT) & EMAC_MTL_EST_STATUS_CGSN_MASK) /* MTL EST Scheduling Error (MTL_EST_SCH_ERROR) */ @@ -2236,7 +2236,7 @@ /* MTL EST Frame Size Capture (MTL_EST_FRM_SIZE_CAPTURE) */ #define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT (0) /* Bits 0-15: Frame Size of HLBF */ -#define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK (0x7FFF << EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT) +#define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK (0x7ffF << EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT) #define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS(n) (((n) << EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT) & EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK) #define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ (1 << 16) /* Bit 16: Queue Number of HLBF */ @@ -2254,7 +2254,7 @@ #define EMAC_MTL_EST_GCL_CONTROL_DBGM (1 << 4) /* Bit 4: Debug Mode */ #define EMAC_MTL_EST_GCL_CONTROL_DBGB (1 << 5) /* Bit 5: Debug Mode Bank Select */ #define EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT (8) /* Bits 8-16: Gate Control List Address: (GCLA when GCRR is "0") */ -#define EMAC_MTL_EST_GCL_CONTROL_ADDR_MASK (0xFF << EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT) +#define EMAC_MTL_EST_GCL_CONTROL_ADDR_MASK (0xff << EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT) #define EMAC_MTL_EST_GCL_CONTROL_ADDR(n) (((n) << EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT) & EMAC_MTL_EST_GCL_CONTROL_ADDR_MASK) #define EMAC_MTL_EST_GCL_CONTROL_ERR0 (1 << 20) /* Bit 20: If this field is 1, it indicates that when the software writes to GCL the last write operation was aborted and when MTL_EST_Control[SSWL] is 1, GCL registers are prohibited */ #define EMAC_MTL_EST_GCL_CONTROL_ESTEIEE (1 << 21) /* Bit 21: EST ECC Inject Error Enable */ @@ -2264,7 +2264,7 @@ /* MTL EST GCL Data (MTL_EST_GCL_DATA) */ #define EMAC_MTL_EST_GCL_DATA_GCD_SHIFT (0) /* Bits 0-32: Gate Control Data */ -#define EMAC_MTL_EST_GCL_DATA_GCD_MASK (0xFFFFFFFF << EMAC_MTL_EST_GCL_DATA_GCD_SHIFT) +#define EMAC_MTL_EST_GCL_DATA_GCD_MASK (0xffffffff << EMAC_MTL_EST_GCL_DATA_GCD_SHIFT) #define EMAC_MTL_EST_GCL_DATA_GCD(n) (((n) << EMAC_MTL_EST_GCL_DATA_GCD_SHIFT) & EMAC_MTL_EST_GCL_DATA_GCD_MASK) /* MTL FPE Control Status (MTL_FPE_CTRL_STS) */ @@ -2278,19 +2278,19 @@ /* MTL FPE Advance (MTL_FPE_ADVANCE) */ #define EMAC_MTL_FPE_ADVANCE_HADV_SHIFT (0) /* Bits 0-16: Hold Advance */ -#define EMAC_MTL_FPE_ADVANCE_HADV_MASK (0xFFFF << EMAC_MTL_FPE_ADVANCE_HADV_SHIFT) +#define EMAC_MTL_FPE_ADVANCE_HADV_MASK (0xffff << EMAC_MTL_FPE_ADVANCE_HADV_SHIFT) #define EMAC_MTL_FPE_ADVANCE_HADV(n) (((n) << EMAC_MTL_FPE_ADVANCE_HADV_SHIFT) & EMAC_MTL_FPE_ADVANCE_HADV_MASK) #define EMAC_MTL_FPE_ADVANCE_RADV_SHIFT (16) /* Bits 16-32: Release Advance */ -#define EMAC_MTL_FPE_ADVANCE_RADV_MASK (0xFFFF << EMAC_MTL_FPE_ADVANCE_RADV_SHIFT) +#define EMAC_MTL_FPE_ADVANCE_RADV_MASK (0xffff << EMAC_MTL_FPE_ADVANCE_RADV_SHIFT) #define EMAC_MTL_FPE_ADVANCE_RADV(n) (((n) << EMAC_MTL_FPE_ADVANCE_RADV_SHIFT) & EMAC_MTL_FPE_ADVANCE_RADV_MASK) /* MTL Rx Parser Control Status (MTL_RXP_CONTROL_STATUS) */ #define EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT (0) /* Bits 0-6: Number Of Valid Entry Address Or Index In The Instruction Table */ -#define EMAC_MTL_RXP_CONTROL_STATUS_NVE_MASK (0x3F << EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT) +#define EMAC_MTL_RXP_CONTROL_STATUS_NVE_MASK (0x3f << EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT) #define EMAC_MTL_RXP_CONTROL_STATUS_NVE(n) (((n) << EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT) & EMAC_MTL_RXP_CONTROL_STATUS_NVE_MASK) #define EMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1 (1 << 15) /* Bit 15: MTL_SCS1 */ #define EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT (16) /* Bits 16-22: Number of parsable entries in the Instruction table */ -#define EMAC_MTL_RXP_CONTROL_STATUS_NPE_MASK (0x3F << EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT) +#define EMAC_MTL_RXP_CONTROL_STATUS_NPE_MASK (0x3f << EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT) #define EMAC_MTL_RXP_CONTROL_STATUS_NPE(n) (((n) << EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT) & EMAC_MTL_RXP_CONTROL_STATUS_NPE_MASK) #define EMAC_MTL_RXP_CONTROL_STATUS_RXPI (1 << 31) /* Bit 31: RX Parser in Idle State */ @@ -2309,13 +2309,13 @@ /* MTL Rx Parser Drop Count (MTL_RXP_DROP_CNT) */ #define EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT (0) /* Bits 0-31: Rx Parser Drop Count */ -#define EMAC_MTL_RXP_DROP_CNT_RXPDC_MASK (0x7FFFFFFF << EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT) +#define EMAC_MTL_RXP_DROP_CNT_RXPDC_MASK (0x7fffffff << EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT) #define EMAC_MTL_RXP_DROP_CNT_RXPDC(n) (((n) << EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT) & EMAC_MTL_RXP_DROP_CNT_RXPDC_MASK) #define EMAC_MTL_RXP_DROP_CNT_RXPDCOVF (1 << 31) /* Bit 31: Rx Parser Drop Counter Overflow Bit */ /* MTL Rx Parser Error Count (MTL_RXP_ERROR_CNT) */ #define EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT (0) /* Bits 0-31: Rx Parser Error Count */ -#define EMAC_MTL_RXP_ERROR_CNT_RXPEC_MASK (0x7FFFFFFF << EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT) +#define EMAC_MTL_RXP_ERROR_CNT_RXPEC_MASK (0x7fffffff << EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT) #define EMAC_MTL_RXP_ERROR_CNT_RXPEC(n) (((n) << EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT) & EMAC_MTL_RXP_ERROR_CNT_RXPEC_MASK) #define EMAC_MTL_RXP_ERROR_CNT_RXPECOVF (1 << 31) /* Bit 31: Rx Parser Error Counter Overflow Bit */ @@ -2324,7 +2324,7 @@ */ #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT (0) /* Bits 0-8: FRP Instruction Table Offset Address */ -#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK (0xFF << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT) +#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK (0xff << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT) #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(n) (((n) << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT) & EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK) #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN (1 << 16) /* Bit 16: Read Write Control */ #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE (1 << 20) /* Bit 20: ECC Inject Error Enable for Rx Parser Memory */ @@ -2335,7 +2335,7 @@ /* MTL Rx Parser Indirect Access Data (MTL_RXP_INDIRECT_ACC_DATA) */ #define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT (0) /* Bits 0-32: FRP Instruction Table Write/Read Data */ -#define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK (0xFFFFFFFF << EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT) +#define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK (0xffffffff << EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT) #define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA(n) (((n) << EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT) & EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK) /* MTL ECC Control (MTL_ECC_CONTROL) */ @@ -2379,18 +2379,18 @@ /* MTL ECC Error Adress Status (MTL_ECC_ERR_ADDR_STATUS) */ #define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT (0) /* Bits 0-16: MTL ECC Correctable Error Address Status */ -#define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK (0xFFFF << EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT) +#define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK (0xffff << EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT) #define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS(n) (((n) << EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT) & EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK) #define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT (16) /* Bits 16-32: MTL ECC Uncorrectable Error Address Status */ -#define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_MASK (0xFFFF << EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT) +#define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_MASK (0xffff << EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT) #define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS(n) (((n) << EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT) & EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_MASK) /* MTL ECC Error Control Status (MTL_ECC_ERR_CNTR_STATUS) */ #define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT (0) /* Bits 0-8: MTL ECC Correctable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register, this field holds the respective memory's correctable error count value */ -#define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_MASK (0xFF << EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT) +#define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_MASK (0xff << EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT) #define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS(n) (((n) << EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT) & EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_MASK) #define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT (16) /* Bits 16-20: MTL ECC Uncorrectable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register, this field holds the respective memory's uncorrectable error count value */ -#define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_MASK (0xF << EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT) +#define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_MASK (0xf << EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT) #define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS(n) (((n) << EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT) & EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_MASK) /* MTL DPP Control (MTL_DPP_CONTROL) */ @@ -2417,12 +2417,12 @@ #define EMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK (0x7 << EMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT) #define EMAC_MTL_TXQ0_OPERATION_MODE_TTC(n) (((n) << EMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT) & EMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK) #define EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT (16) /* Bits 16-21: Transmit Queue Size */ -#define EMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK (0x1F << EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT) +#define EMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK (0x1f << EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT) #define EMAC_MTL_TXQ0_OPERATION_MODE_TQS(n) (((n) << EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT) & EMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK) /* MTL Tx Queue 0 Underflow (MTL_TXQ0_UNDERFLOW) */ #define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT (0) /* Bits 0-11: Underflow Packet Counter */ -#define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK (0x7FF << EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT) +#define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK (0x7ff << EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT) #define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT(n) (((n) << EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT) & EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK) #define EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF (1 << 11) /* Bit 11: Overflow Bit for Underflow Packet Counter */ @@ -2443,12 +2443,12 @@ /* MTL Tx Queue 0 ETS Status (MTL_TXQ0_ETS_STATUS) */ #define EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT (0) /* Bits 0-24: Average Bits per Slot */ -#define EMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK (0xFFFFFF << EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT) +#define EMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK (0xffffff << EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT) #define EMAC_MTL_TXQ0_ETS_STATUS_ABS(n) (((n) << EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT) & EMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK) /* MTL Tx Queue Quantum Weight (MTL_TXQ0_QUANTUM_WEIGHT) */ #define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT (0) /* Bits 0-21: Quantum or Weights */ -#define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK (0x1FFFFF << EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT) +#define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK (0x1fffff << EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT) #define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW(n) (((n) << EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT) & EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK) /* MTL Queue 0 Interrupt Control Status (MTL_Q0_INTERRUPT_CONTROL_STATUS) */ @@ -2469,13 +2469,13 @@ #define EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF (1 << 6) /* Bit 6: Disable Dropping of TCP/IP Checksum Error Packets */ #define EMAC_MTL_RXQ0_OPERATION_MODE_EHFC (1 << 7) /* Bit 7: Enable Hardware Flow Control */ #define EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT (8) /* Bits 8-12: Threshold for Activating Flow Control (in half-duplex and full-duplex) */ -#define EMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK (0xF << EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT) +#define EMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK (0xf << EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT) #define EMAC_MTL_RXQ0_OPERATION_MODE_RFA(n) (((n) << EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK) #define EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT (14) /* Bits 14-18: Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */ -#define EMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK (0xF << EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) +#define EMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK (0xf << EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) #define EMAC_MTL_RXQ0_OPERATION_MODE_RFD(n) (((n) << EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK) #define EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT (20) /* Bits 20-25: Receive Queue Size */ -#define EMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK (0x1F << EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT) +#define EMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK (0x1f << EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT) #define EMAC_MTL_RXQ0_OPERATION_MODE_RQS(n) (((n) << EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK) /* MTL Rx Queue Missed Packet Overflow Count @@ -2483,11 +2483,11 @@ */ #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT (0) /* Bits 0-11: Overflow Packet Counter */ -#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK (0x7FF << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT) +#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK (0x7ff << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT) #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(n) (((n) << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK) #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF (1 << 11) /* Bit 11: Overflow Counter Overflow Bit */ #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT (16) /* Bits 16-27: Missed Packet Counter */ -#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK (0x7FF << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT) +#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK (0x7ff << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT) #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(n) (((n) << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK) #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF (1 << 27) /* Bit 27: Missed Packet Counter Overflow Bit */ @@ -2500,7 +2500,7 @@ #define EMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK (0x3 << EMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) #define EMAC_MTL_RXQ0_DEBUG_RXQSTS(n) (((n) << EMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) & EMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK) #define EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT (16) /* Bits 16-30: Number of Packets in Receive Queue */ -#define EMAC_MTL_RXQ0_DEBUG_PRXQ_MASK (0x3FFF << EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT) +#define EMAC_MTL_RXQ0_DEBUG_PRXQ_MASK (0x3fff << EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT) #define EMAC_MTL_RXQ0_DEBUG_PRXQ(n) (((n) << EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT) & EMAC_MTL_RXQ0_DEBUG_PRXQ_MASK) /* MTL Rx Queue 0 Control 0 (MTL_RXQ0_CONTROL) */ @@ -2519,12 +2519,12 @@ #define EMAC_MTL_TXQ1_OPERATION_MODE_TTC_MASK (0x7 << EMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT) #define EMAC_MTL_TXQ1_OPERATION_MODE_TTC(n) (((n) << EMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT) & EMAC_MTL_TXQ1_OPERATION_MODE_TTC_MASK) #define EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT (16) /* Bits 16-21: Transmit Queue Size */ -#define EMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK (0x1F << EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT) +#define EMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK (0x1f << EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT) #define EMAC_MTL_TXQ1_OPERATION_MODE_TQS(n) (((n) << EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT) & EMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK) /* MTL Tx Queue 1 Underflow (MTL_TXQ1_UNDERFLOW) */ #define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT (0) /* Bits 0-11: Underflow Packet Counter */ -#define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK (0x7FF << EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT) +#define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK (0x7ff << EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT) #define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT(n) (((n) << EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT) & EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK) #define EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF (1 << 11) /* Bit 11: Overflow Bit for Underflow Packet Counter */ @@ -2552,27 +2552,27 @@ /* MTL Tx Queue 1 ETS Status (MTL_TXQ1_ETS_STATUS) */ #define EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT (0) /* Bits 0-24: Average Bits per Slot */ -#define EMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK (0xFFFFFF << EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT) +#define EMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK (0xffffff << EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT) #define EMAC_MTL_TXQ1_ETS_STATUS_ABS(n) (((n) << EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT) & EMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK) /* MTL Tx Queue 1 Quantum Weight (MTL_TXQ1_QUANTUM_WEIGHT) */ #define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT (0) /* Bits 0-21: idleSlopeCredit, Quantum or Weights */ -#define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK (0x1FFFFF << EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT) +#define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK (0x1fffff << EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT) #define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW(n) (((n) << EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT) & EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK) /* MTL Tx Queue 1 Sendslope Credit (MTL_TXQ1_SENDSLOPECREDIT) */ #define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT (0) /* Bits 0-14: sendSlopeCredit Value */ -#define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK (0x3FFF << EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT) +#define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK (0x3fff << EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT) #define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC(n) (((n) << EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT) & EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK) /* MTL Tx Queue 1 HiCredit (MTL_TXQ1_HICREDIT) */ #define EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT (0) /* Bits 0-29: hiCredit Value */ -#define EMAC_MTL_TXQ1_HICREDIT_HC_MASK (0x1FFFFFFF << EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT) +#define EMAC_MTL_TXQ1_HICREDIT_HC_MASK (0x1fffffff << EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT) #define EMAC_MTL_TXQ1_HICREDIT_HC(n) (((n) << EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT) & EMAC_MTL_TXQ1_HICREDIT_HC_MASK) /* MTL Tx Queue 1 LoCredit (MTL_TXQ1_LOCREDIT) */ #define EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT (0) /* Bits 0-29: loCredit Value */ -#define EMAC_MTL_TXQ1_LOCREDIT_LC_MASK (0x1FFFFFFF << EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT) +#define EMAC_MTL_TXQ1_LOCREDIT_LC_MASK (0x1fffffff << EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT) #define EMAC_MTL_TXQ1_LOCREDIT_LC(n) (((n) << EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT) & EMAC_MTL_TXQ1_LOCREDIT_LC_MASK) /* MTL Queue 1 Interrupt Control Status (MTL_Q1_INTERRUPT_CONTROL_STATUS) */ @@ -2593,13 +2593,13 @@ #define EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF (1 << 6) /* Bit 6: Disable Dropping of TCP or IP Checksum Error Packets */ #define EMAC_MTL_RXQ1_OPERATION_MODE_EHFC (1 << 7) /* Bit 7: Enable Hardware Flow Control */ #define EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT (8) /* Bits 8-12: Threshold for Activating Flow Control (in half-duplex and full-duplex */ -#define EMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK (0xF << EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT) +#define EMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK (0xf << EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT) #define EMAC_MTL_RXQ1_OPERATION_MODE_RFA(n) (((n) << EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK) #define EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT (14) /* Bits 14-18: Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */ -#define EMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK (0xF << EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT) +#define EMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK (0xf << EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT) #define EMAC_MTL_RXQ1_OPERATION_MODE_RFD(n) (((n) << EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK) #define EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT (20) /* Bits 20-25: Receive Queue Size */ -#define EMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK (0x1F << EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT) +#define EMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK (0x1f << EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT) #define EMAC_MTL_RXQ1_OPERATION_MODE_RQS(n) (((n) << EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK) /* MTL Rx Queue 1 Missed Packet Overflow Counter @@ -2607,11 +2607,11 @@ */ #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT (0) /* Bits 0-11: Overflow Packet Counter */ -#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK (0x7FF << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT) +#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK (0x7ff << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT) #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(n) (((n) << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK) #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF (1 << 11) /* Bit 11: Overflow Counter Overflow Bit */ #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT (16) /* Bits 16-27: Missed Packet Counter */ -#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK (0x7FF << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT) +#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK (0x7ff << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT) #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(n) (((n) << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK) #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF (1 << 27) /* Bit 27: Missed Packet Counter Overflow Bit */ @@ -2624,7 +2624,7 @@ #define EMAC_MTL_RXQ1_DEBUG_RXQSTS_MASK (0x3 << EMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT) #define EMAC_MTL_RXQ1_DEBUG_RXQSTS(n) (((n) << EMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT) & EMAC_MTL_RXQ1_DEBUG_RXQSTS_MASK) #define EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT (16) /* Bits 16-30: Number of Packets in Receive Queue */ -#define EMAC_MTL_RXQ1_DEBUG_PRXQ_MASK (0x3FFF << EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT) +#define EMAC_MTL_RXQ1_DEBUG_PRXQ_MASK (0x3fff << EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT) #define EMAC_MTL_RXQ1_DEBUG_PRXQ(n) (((n) << EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT) & EMAC_MTL_RXQ1_DEBUG_PRXQ_MASK) /* MTL Rx Queue 1 Control (MTL_RXQ1_CONTROL) */ @@ -2663,16 +2663,16 @@ /* DMA Debug Status 0 (DMA_DEBUG_STATUS0) */ #define EMAC_DMA_DEBUG_STATUS0_AXWHSTS (1 << 0) /* Bit 0: AHB Master Status */ #define EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT (8) /* Bits 8-12: DMA Channel 0 Receive Process State */ -#define EMAC_DMA_DEBUG_STATUS0_RPS0_MASK (0xF << EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT) +#define EMAC_DMA_DEBUG_STATUS0_RPS0_MASK (0xf << EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT) #define EMAC_DMA_DEBUG_STATUS0_RPS0(n) (((n) << EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT) & EMAC_DMA_DEBUG_STATUS0_RPS0_MASK) #define EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT (12) /* Bits 12-16: DMA Channel 0 Transmit Process State */ -#define EMAC_DMA_DEBUG_STATUS0_TPS0_MASK (0xF << EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT) +#define EMAC_DMA_DEBUG_STATUS0_TPS0_MASK (0xf << EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT) #define EMAC_DMA_DEBUG_STATUS0_TPS0(n) (((n) << EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT) & EMAC_DMA_DEBUG_STATUS0_TPS0_MASK) #define EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT (16) /* Bits 16-20: DMA Channel 1 Receive Process State */ -#define EMAC_DMA_DEBUG_STATUS0_RPS1_MASK (0xF << EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT) +#define EMAC_DMA_DEBUG_STATUS0_RPS1_MASK (0xf << EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT) #define EMAC_DMA_DEBUG_STATUS0_RPS1(n) (((n) << EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT) & EMAC_DMA_DEBUG_STATUS0_RPS1_MASK) #define EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT (20) /* Bits 20-24: DMA Channel 1 Transmit Process State */ -#define EMAC_DMA_DEBUG_STATUS0_TPS1_MASK (0xF << EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT) +#define EMAC_DMA_DEBUG_STATUS0_TPS1_MASK (0xf << EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT) #define EMAC_DMA_DEBUG_STATUS0_TPS1(n) (((n) << EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT) & EMAC_DMA_DEBUG_STATUS0_TPS1_MASK) /* DMA TBS Control (DMA_TBS_CTRL) */ @@ -2681,7 +2681,7 @@ #define EMAC_DMA_TBS_CTRL_FGOS_MASK (0x7 << EMAC_DMA_TBS_CTRL_FGOS_SHIFT) #define EMAC_DMA_TBS_CTRL_FGOS(n) (((n) << EMAC_DMA_TBS_CTRL_FGOS_SHIFT) & EMAC_DMA_TBS_CTRL_FGOS_MASK) #define EMAC_DMA_TBS_CTRL_FTOS_SHIFT (8) /* Bits 8-32: Fetch Time Offset */ -#define EMAC_DMA_TBS_CTRL_FTOS_MASK (0xFFFFFF << EMAC_DMA_TBS_CTRL_FTOS_SHIFT) +#define EMAC_DMA_TBS_CTRL_FTOS_MASK (0xffffff << EMAC_DMA_TBS_CTRL_FTOS_SHIFT) #define EMAC_DMA_TBS_CTRL_FTOS(n) (((n) << EMAC_DMA_TBS_CTRL_FTOS_SHIFT) & EMAC_DMA_TBS_CTRL_FTOS_MASK) /* DMA Safety Interrupt Status (DMA_SAFETY_INTERRUPT_STATUS) */ @@ -2704,7 +2704,7 @@ #define EMAC_DMA_CH0_TX_CONTROL_TCW(n) (((n) << EMAC_DMA_CH0_TX_CONTROL_TCW_SHIFT) & EMAC_DMA_CH0_TX_CONTROL_TCW_MASK) #define EMAC_DMA_CH0_TX_CONTROL_OSF (1 << 4) /* Bit 4: Operate on Second Packet */ #define EMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT (16) /* Bits 16-22: Transmit Programmable Burst Length */ -#define EMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK (0x3F << EMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT) +#define EMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK (0x3f << EMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT) #define EMAC_DMA_CH0_TX_CONTROL_TXPBL(n) (((n) << EMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT) & EMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK) #define EMAC_DMA_CH0_TX_CONTROL_ETIC (1 << 22) /* Bit 22: Early Transmit Interrupt Control */ #define EMAC_DMA_CH0_TX_CONTROL_EDSE (1 << 28) /* Bit 28: Enhanced Descriptor Enable */ @@ -2715,42 +2715,42 @@ #define EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_MASK (0x3 << EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_SHIFT) #define EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0(n) (((n) << EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_SHIFT) & EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_MASK) #define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT (3) /* Bits 3-15: Receive Buffer size High */ -#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_MASK (0xFFF << EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT) +#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_MASK (0xfff << EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT) #define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y(n) (((n) << EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT) & EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_MASK) #define EMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT (16) /* Bits 16-22: Receive Programmable Burst Length */ -#define EMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK (0x3F << EMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT) +#define EMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK (0x3f << EMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT) #define EMAC_DMA_CH0_RX_CONTROL_RXPBL(n) (((n) << EMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT) & EMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK) #define EMAC_DMA_CH0_RX_CONTROL_ERIC (1 << 22) /* Bit 22: Early Receive Interrupt Control */ #define EMAC_DMA_CH0_RX_CONTROL_RPF (1 << 31) /* Bit 31: Rx Packet Flush */ /* DMA Channel 0 Tx Descriptor List Address (DMA_CH0_TXDESC_LIST_ADDRESS) */ #define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT (2) /* Bits 2-32: Start of Transmit List */ -#define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK (0x3FFFFFFF << EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) +#define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK (0x3fffffff << EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) #define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA(n) (((n) << EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) & EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK) /* DMA Channel 0 Rx Descriptor List Address (DMA_CH0_RXDESC_LIST_ADDRESS) */ #define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT (2) /* Bits 2-32: Start of Receive List */ -#define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK (0x3FFFFFFF << EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) +#define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK (0x3fffffff << EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) #define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA(n) (((n) << EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) & EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK) /* DMA Channel 0 Tx Descriptor Tail Pointer (DMA_CH0_TXDESC_TAIL_POINTER) */ #define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT (2) /* Bits 2-32: Transmit Descriptor Tail Pointer */ -#define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK (0x3FFFFFFF << EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT) +#define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK (0x3fffffff << EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT) #define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP(n) (((n) << EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT) & EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK) /* DMA Channeli 0 Rx Descriptor List Pointer (DMA_CH0_RXDESC_TAIL_POINTER) */ #define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT (2) /* Bits 2-32: Receive Descriptor Tail Pointer */ -#define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK (0x3FFFFFFF << EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT) +#define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK (0x3fffffff << EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT) #define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP(n) (((n) << EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT) & EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK) /* DMA Channel 0 Tx Descriptor Ring Length (DMA_CH0_TXDESC_RING_LENGTH) */ #define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT (0) /* Bits 0-10: Transmit Descriptor Ring Length */ -#define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK (0x3FF << EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT) +#define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK (0x3ff << EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT) #define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL(n) (((n) << EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT) & EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK) /* DMA Channel 0 Rx Descriptor Ring Length (DMA_CH0_RXDESC_RING_LENGTH) */ #define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT (0) /* Bits 0-10: Receive Descriptor Ring Length */ -#define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK (0x3FF << EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT) +#define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK (0x3ff << EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT) #define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL(n) (((n) << EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT) & EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK) /* DMA Channel 0 Interrupt Enable (DMA_CH0_INTERRUPT_ENABLE) */ @@ -2773,7 +2773,7 @@ */ #define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT (0) /* Bits 0-8: Receive Interrupt Watchdog Timer Count */ -#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK (0xFF << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) +#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK (0xff << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) #define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT(n) (((n) << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) & EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK) #define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT (16) /* Bits 16-18: Receive Interrupt Watchdog Timer Count Units */ #define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK (0x3 << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT) @@ -2786,10 +2786,10 @@ #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC (1 << 0) /* Bit 0: Enable Slot Comparison */ #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC (1 << 1) /* Bit 1: Advance Slot Check */ #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT (4) /* Bits 4-16: Slot Interval Value */ -#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK (0xFFF << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT) +#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK (0xfff << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT) #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV(n) (((n) << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK) #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT (16) /* Bits 16-20: Reference Slot Number */ -#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK (0xF << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT) +#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK (0xf << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT) #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN(n) (((n) << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK) /* DMA Channel 0 Current Application Transmit Descriptor @@ -2797,7 +2797,7 @@ */ #define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT (0) /* Bits 0-32: Application Transmit Descriptor Address Pointer */ -#define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) +#define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK (0xffffffff << EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) #define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR(n) (((n) << EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK) /* DMA Channel 0 Current Application Receive Descriptor @@ -2805,7 +2805,7 @@ */ #define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT (0) /* Bits 0-32: Application Receive Descriptor Address Pointer */ -#define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) +#define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK (0xffffffff << EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) #define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR(n) (((n) << EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK) /* DMA Channel 0 Current Application Transmit Descriptor @@ -2813,7 +2813,7 @@ */ #define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT (0) /* Bits 0-32: Application Transmit Buffer Address Pointer */ -#define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) +#define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK (0xffffffff << EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) #define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR(n) (((n) << EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK) /* DMA Channel 0 Current Application Receive Buffer @@ -2821,7 +2821,7 @@ */ #define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT (0) /* Bits 0-32: Application Receive Buffer Address Pointer */ -#define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) +#define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK (0xffffffff << EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) #define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR(n) (((n) << EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK) /* DMA Channel 0 Status (DMA_CH0_STATUS) */ @@ -2847,19 +2847,19 @@ /* DMA Channel 0 Miss Frame Counter (DMA_CH0_MISS_FRAME_CNT) */ #define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT (0) /* Bits 0-11: Dropped Packet Counters Indicates the number of packet counters that DMA drops either because of bus error or because of programing RPF field in DMA_CH${i}_Rx_Control register */ -#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK (0x7FF << EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT) +#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK (0x7ff << EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT) #define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC(n) (((n) << EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT) & EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK) #define EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO (1 << 15) /* Bit 15: Overflow status of the MFC Counter */ /* DMA Channel 0 Rx Parser Accept Count (DMA_CH0_RXP_ACCEPT_CNT) */ #define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT (0) /* Bits 0-31: Rx Parser Accept Counter */ -#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFF << EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT) +#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK (0x7fffffff << EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT) #define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC(n) (((n) << EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT) & EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK) #define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF (1 << 31) /* Bit 31: Rx Parser Accept Counter Overflow Bit */ /* DMA Channel 0 Rx ERI Count (DMA_CH0_RX_ERI_CNT) */ #define EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT (0) /* Bits 0-12: ERI Counter */ -#define EMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK (0xFFF << EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT) +#define EMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK (0xfff << EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT) #define EMAC_DMA_CH0_RX_ERI_CNT_ECNT(n) (((n) << EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT) & EMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK) /* DMA Channel 1 Control (DMA_CH1_CONTROL) */ @@ -2875,7 +2875,7 @@ #define EMAC_DMA_CH1_TX_CONTROL_TCW(n) (((n) << EMAC_DMA_CH1_TX_CONTROL_TCW_SHIFT) & EMAC_DMA_CH1_TX_CONTROL_TCW_MASK) #define EMAC_DMA_CH1_TX_CONTROL_OSF (1 << 4) /* Bit 4: Operate on Second Packet */ #define EMAC_DMA_CH1_TX_CONTROL_TXPBL_SHIFT (16) /* Bits 16-22: Transmit Programmable Burst Length */ -#define EMAC_DMA_CH1_TX_CONTROL_TXPBL_MASK (0x3F << EMAC_DMA_CH1_TX_CONTROL_TXPBL_SHIFT) +#define EMAC_DMA_CH1_TX_CONTROL_TXPBL_MASK (0x3f << EMAC_DMA_CH1_TX_CONTROL_TXPBL_SHIFT) #define EMAC_DMA_CH1_TX_CONTROL_TXPBL(n) (((n) << EMAC_DMA_CH1_TX_CONTROL_TXPBL_SHIFT) & EMAC_DMA_CH1_TX_CONTROL_TXPBL_MASK) #define EMAC_DMA_CH1_TX_CONTROL_ETIC (1 << 22) /* Bit 22: Early Transmit Interrupt Control */ #define EMAC_DMA_CH1_TX_CONTROL_EDSE (1 << 28) /* Bit 28: Enhanced Descriptor Enable */ @@ -2886,42 +2886,42 @@ #define EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_MASK (0x3 << EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_SHIFT) #define EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0(n) (((n) << EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_SHIFT) & EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_MASK) #define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_SHIFT (3) /* Bits 3-15: Receive Buffer size High */ -#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_MASK (0xFFF << EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_SHIFT) +#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_MASK (0xfff << EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_SHIFT) #define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y(n) (((n) << EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_SHIFT) & EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_MASK) #define EMAC_DMA_CH1_RX_CONTROL_RXPBL_SHIFT (16) /* Bits 16-22: Receive Programmable Burst Length */ -#define EMAC_DMA_CH1_RX_CONTROL_RXPBL_MASK (0x3F << EMAC_DMA_CH1_RX_CONTROL_RXPBL_SHIFT) +#define EMAC_DMA_CH1_RX_CONTROL_RXPBL_MASK (0x3f << EMAC_DMA_CH1_RX_CONTROL_RXPBL_SHIFT) #define EMAC_DMA_CH1_RX_CONTROL_RXPBL(n) (((n) << EMAC_DMA_CH1_RX_CONTROL_RXPBL_SHIFT) & EMAC_DMA_CH1_RX_CONTROL_RXPBL_MASK) #define EMAC_DMA_CH1_RX_CONTROL_ERIC (1 << 22) /* Bit 22: Early Receive Interrupt Control */ #define EMAC_DMA_CH1_RX_CONTROL_RPF (1 << 31) /* Bit 31: Rx Packet Flush */ /* DMA Channel 1 Tx Descriptor List Address (DMA_CH1_TXDESC_LIST_ADDRESS) */ #define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT (2) /* Bits 2-32: Start of Transmit List */ -#define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK (0x3FFFFFFF << EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) +#define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK (0x3fffffff << EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) #define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA(n) (((n) << EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) & EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK) /* DMA Channel 1 Rx Descriptor List Address (DMA_CH1_RXDESC_LIST_ADDRESS) */ #define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT (2) /* Bits 2-32: Start of Receive List */ -#define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK (0x3FFFFFFF << EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) +#define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK (0x3fffffff << EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) #define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA(n) (((n) << EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) & EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK) /* DMA Channel 1 Tx Descriptor Tail Pointer (DMA_CH1_TXDESC_TAIL_POINTER) */ #define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT (2) /* Bits 2-32: Transmit Descriptor Tail Pointer */ -#define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK (0x3FFFFFFF << EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT) +#define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK (0x3fffffff << EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT) #define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP(n) (((n) << EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT) & EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK) /* DMA Channel 1 Rx Descriptor Tail Pointer (DMA_CH1_RXDESC_TAIL_POINTER) */ #define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT (2) /* Bits 2-32: Receive Descriptor Tail Pointer */ -#define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK (0x3FFFFFFF << EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT) +#define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK (0x3fffffff << EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT) #define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP(n) (((n) << EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT) & EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK) /* DMA Channel 1 Tx Descriptor Ring Length (DMA_CH1_TXDESC_RING_LENGTH) */ #define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT (0) /* Bits 0-10: Transmit Descriptor Ring Length */ -#define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK (0x3FF << EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT) +#define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK (0x3ff << EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT) #define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL(n) (((n) << EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT) & EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK) /* DMA Channel 1 Rx Descriptor Ring Length (DMA_CH1_RXDESC_RING_LENGTH) */ #define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT (0) /* Bits 0-10: Receive Descriptor Ring Length */ -#define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK (0x3FF << EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT) +#define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK (0x3ff << EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT) #define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL(n) (((n) << EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT) & EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK) /* DMA Channel 1 Interrupt Enable (DMA_CH1_INTERRUPT_ENABLE) */ @@ -2944,7 +2944,7 @@ */ #define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT (0) /* Bits 0-8: Receive Interrupt Watchdog Timer Count */ -#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK (0xFF << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) +#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK (0xff << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) #define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT(n) (((n) << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) & EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK) #define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT (16) /* Bits 16-18: Receive Interrupt Watchdog Timer Count Units */ #define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK (0x3 << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT) @@ -2957,10 +2957,10 @@ #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC (1 << 0) /* Bit 0: Enable Slot Comparison */ #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC (1 << 1) /* Bit 1: Advance Slot Check */ #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT (4) /* Bits 4-16: Slot Interval Value */ -#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK (0xFFF << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT) +#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK (0xfff << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT) #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV(n) (((n) << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK) #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT (16) /* Bits 16-20: Reference Slot Number */ -#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK (0xF << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT) +#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK (0xf << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT) #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN(n) (((n) << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK) /* DMA Channel 1 Current Application Transmit Descriptor @@ -2968,7 +2968,7 @@ */ #define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT (0) /* Bits 0-32: Application Transmit Descriptor Address Pointer */ -#define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) +#define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK (0xffffffff << EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) #define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR(n) (((n) << EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK) /* DMA Channel 1 Current Application Receive Descriptor @@ -2976,7 +2976,7 @@ */ #define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT (0) /* Bits 0-32: Application Receive Descriptor Address Pointer */ -#define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) +#define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK (0xffffffff << EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) #define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR(n) (((n) << EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK) /* DMA Channel 1 Current Application Transmit Buffer @@ -2984,7 +2984,7 @@ */ #define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT (0) /* Bits 0-32: Application Transmit Buffer Address Pointer */ -#define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) +#define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK (0xffffffff << EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) #define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR(n) (((n) << EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK) /* DMA Channel 1 Current Application Receive Buffer @@ -2992,7 +2992,7 @@ */ #define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT (0) /* Bits 0-32: Application Receive Buffer Address Pointer */ -#define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) +#define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK (0xffffffff << EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) #define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR(n) (((n) << EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK) /* DMA Channel 1 Status (DMA_CH1_STATUS) */ @@ -3018,54 +3018,54 @@ /* DMA Channel 1 Miss Frame Counter (DMA_CH1_MISS_FRAME_CNT) */ #define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT (0) /* Bits 0-11: Dropped Packet Counters */ -#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK (0x7FF << EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT) +#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK (0x7ff << EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT) #define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC(n) (((n) << EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT) & EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK) #define EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO (1 << 15) /* Bit 15: Overflow status of the MFC Counter */ /* DMA Channel 1 Rx Parser Accept Count (DMA_CH1_RXP_ACCEPT_CNT) */ #define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT (0) /* Bits 0-31: Rx Parser Accept Counter */ -#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFF << EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT) +#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK (0x7fffffff << EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT) #define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC(n) (((n) << EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT) & EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK) #define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF (1 << 31) /* Bit 31: Rx Parser Accept Counter Overflow Bit */ /* DMA Channel 1 Rx ERI Count (DMA_CH1_RX_ERI_CNT) */ #define EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT (0) /* Bits 0-12: ERI Counter */ -#define EMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK (0xFFF << EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT) +#define EMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK (0xfff << EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT) #define EMAC_DMA_CH1_RX_ERI_CNT_ECNT(n) (((n) << EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT) & EMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK) #define EMAC_TDES3_CPC(x) (((uint32_t)(((uint32_t)(x)) << 26U)) & 0x0C000000U) #define EMAC_TDES3_CIC(x) (((uint32_t)(((uint32_t)(x)) << 16U)) & 0x00030000U) -#define EMAC_TDES3_OWN_MASK (0x80000000U) -#define EMAC_TDES3_FD_MASK (0x20000000U) -#define EMAC_TDES3_LD_MASK (0x10000000U) +#define EMAC_TDES3_OWN_MASK (0x80000000u) +#define EMAC_TDES3_FD_MASK (0x20000000u) +#define EMAC_TDES3_LD_MASK (0x10000000u) -#define EMAC_TDES2_IOC_MASK (0x80000000U) -#define EMAC_TDES2_TTSE_MASK (0x40000000U) -#define EMAC_TDES2_B1L_MASK (0x00003FFFU) +#define EMAC_TDES2_IOC_MASK (0x80000000u) +#define EMAC_TDES2_TTSE_MASK (0x40000000u) +#define EMAC_TDES2_B1L_MASK (0x00003fffu) -#define EMAC_RDES0_IVT_MASK (0xFFFF0000U) -#define EMAC_RDES0_IVT_SHIFT (16U) -#define EMAC_RDES0_OVT_MASK (0x0000FFFFU) +#define EMAC_RDES0_IVT_MASK (0xffff0000u) +#define EMAC_RDES0_IVT_SHIFT (16u) +#define EMAC_RDES0_OVT_MASK (0x0000ffffu) -#define EMAC_RDES1_TSA_MASK (0x00004000U) -#define EMAC_RDES1_IPCE_MASK (0x00000080U) -#define EMAC_RDES1_IPV6_MASK (0x00000020U) -#define EMAC_RDES1_IPV4_MASK (0x00000010U) -#define EMAC_RDES1_IPHE_MASK (0x00000008U) -#define EMAC_RDES1_PT_MASK (0x00000007U) +#define EMAC_RDES1_TSA_MASK (0x00004000u) +#define EMAC_RDES1_IPCE_MASK (0x00000080u) +#define EMAC_RDES1_IPV6_MASK (0x00000020u) +#define EMAC_RDES1_IPV4_MASK (0x00000010u) +#define EMAC_RDES1_IPHE_MASK (0x00000008u) +#define EMAC_RDES1_PT_MASK (0x00000007u) -#define EMAC_RDES3_PL_MASK (0x00007FFFU) -#define EMAC_RDES3_OWN_MASK (0x80000000U) -#define EMAC_RDES3_INTE_MASK (0x40000000U) -#define EMAC_RDES3_BUF1V_MASK (0x01000000U) -#define EMAC_RDES3_RS1V_MASK (0x04000000U) -#define EMAC_RDES3_RS0V_MASK (0x02000000U) +#define EMAC_RDES3_PL_MASK (0x00007fffu) +#define EMAC_RDES3_OWN_MASK (0x80000000u) +#define EMAC_RDES3_INTE_MASK (0x40000000u) +#define EMAC_RDES3_BUF1V_MASK (0x01000000u) +#define EMAC_RDES3_RS1V_MASK (0x04000000u) +#define EMAC_RDES3_RS0V_MASK (0x02000000u) -#define EMAC_RDES3_CTXT_MASK (0x40000000U) +#define EMAC_RDES3_CTXT_MASK (0x40000000u) -#define EMAC_INFO1_CONSUMED_MASK (0x00000001U) -#define EMAC_INFO1_LOCKED_MASK (0x10000000U) -#define EMAC_INFO1_LENGTH_MASK (0x00003FFFU) +#define EMAC_INFO1_CONSUMED_MASK (0x00000001u) +#define EMAC_INFO1_LOCKED_MASK (0x10000000u) +#define EMAC_INFO1_LENGTH_MASK (0x00003fffu) /**************************************************************************** * Public Types diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h index 715a4380ed8..4b6e8cd43ab 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h @@ -132,32 +132,32 @@ /* Output Update Disable Register (OUDIS) */ -#define EMIOS_OUDIS_OU0 (1 << 0) /* Bit 0: Channel 0 Output Update Disable (OU0) */ -#define EMIOS_OUDIS_OU1 (1 << 1) /* Bit 1: Channel 1 Output Update Disable (OU1) */ -#define EMIOS_OUDIS_OU2 (1 << 2) /* Bit 2: Channel 2 Output Update Disable (OU2) */ -#define EMIOS_OUDIS_OU3 (1 << 3) /* Bit 3: Channel 3 Output Update Disable (OU3) */ -#define EMIOS_OUDIS_OU4 (1 << 4) /* Bit 4: Channel 4 Output Update Disable (OU4) */ -#define EMIOS_OUDIS_OU5 (1 << 5) /* Bit 5: Channel 5 Output Update Disable (OU5) */ -#define EMIOS_OUDIS_OU6 (1 << 6) /* Bit 6: Channel 6 Output Update Disable (OU6) */ -#define EMIOS_OUDIS_OU7 (1 << 7) /* Bit 7: Channel 7 Output Update Disable (OU7) */ -#define EMIOS_OUDIS_OU8 (1 << 8) /* Bit 8: Channel 8 Output Update Disable (OU8) */ -#define EMIOS_OUDIS_OU9 (1 << 9) /* Bit 9: Channel 9 Output Update Disable (OU9) */ -#define EMIOS_OUDIS_OU10 (1 << 10) /* Bit 10: Channel 10 Output Update Disable (OU10) */ -#define EMIOS_OUDIS_OU11 (1 << 11) /* Bit 11: Channel 11 Output Update Disable (OU11) */ -#define EMIOS_OUDIS_OU12 (1 << 12) /* Bit 12: Channel 12 Output Update Disable (OU12) */ -#define EMIOS_OUDIS_OU13 (1 << 13) /* Bit 13: Channel 13 Output Update Disable (OU13) */ -#define EMIOS_OUDIS_OU14 (1 << 14) /* Bit 14: Channel 14 Output Update Disable (OU14) */ -#define EMIOS_OUDIS_OU15 (1 << 15) /* Bit 15: Channel 15 Output Update Disable (OU15) */ -#define EMIOS_OUDIS_OU16 (1 << 16) /* Bit 16: Channel 16 Output Update Disable (OU16) */ -#define EMIOS_OUDIS_OU17 (1 << 17) /* Bit 17: Channel 17 Output Update Disable (OU17) */ -#define EMIOS_OUDIS_OU18 (1 << 18) /* Bit 18: Channel 18 Output Update Disable (OU18) */ -#define EMIOS_OUDIS_OU19 (1 << 19) /* Bit 19: Channel 19 Output Update Disable (OU19) */ -#define EMIOS_OUDIS_OU20 (1 << 20) /* Bit 20: Channel 20 Output Update Disable (OU20) */ -#define EMIOS_OUDIS_OU21 (1 << 21) /* Bit 21: Channel 21 Output Update Disable (OU21) */ -#define EMIOS_OUDIS_OU22 (1 << 22) /* Bit 22: Channel 22 Output Update Disable (OU22) */ -#define EMIOS_OUDIS_OU23 (1 << 23) /* Bit 23: Channel 23 Output Update Disable (OU23) */ -#define EMIOS_OUDIS_OU(n) (1 << n) /* Bit n: Channel n Output Update Disable (OU23) */ - /* Bits 24-31: Reserved */ +#define EMIOS_OUDIS_OU0 (1 << 0) /* Bit 0: Channel 0 Output Update Disable (OU0) */ +#define EMIOS_OUDIS_OU1 (1 << 1) /* Bit 1: Channel 1 Output Update Disable (OU1) */ +#define EMIOS_OUDIS_OU2 (1 << 2) /* Bit 2: Channel 2 Output Update Disable (OU2) */ +#define EMIOS_OUDIS_OU3 (1 << 3) /* Bit 3: Channel 3 Output Update Disable (OU3) */ +#define EMIOS_OUDIS_OU4 (1 << 4) /* Bit 4: Channel 4 Output Update Disable (OU4) */ +#define EMIOS_OUDIS_OU5 (1 << 5) /* Bit 5: Channel 5 Output Update Disable (OU5) */ +#define EMIOS_OUDIS_OU6 (1 << 6) /* Bit 6: Channel 6 Output Update Disable (OU6) */ +#define EMIOS_OUDIS_OU7 (1 << 7) /* Bit 7: Channel 7 Output Update Disable (OU7) */ +#define EMIOS_OUDIS_OU8 (1 << 8) /* Bit 8: Channel 8 Output Update Disable (OU8) */ +#define EMIOS_OUDIS_OU9 (1 << 9) /* Bit 9: Channel 9 Output Update Disable (OU9) */ +#define EMIOS_OUDIS_OU10 (1 << 10) /* Bit 10: Channel 10 Output Update Disable (OU10) */ +#define EMIOS_OUDIS_OU11 (1 << 11) /* Bit 11: Channel 11 Output Update Disable (OU11) */ +#define EMIOS_OUDIS_OU12 (1 << 12) /* Bit 12: Channel 12 Output Update Disable (OU12) */ +#define EMIOS_OUDIS_OU13 (1 << 13) /* Bit 13: Channel 13 Output Update Disable (OU13) */ +#define EMIOS_OUDIS_OU14 (1 << 14) /* Bit 14: Channel 14 Output Update Disable (OU14) */ +#define EMIOS_OUDIS_OU15 (1 << 15) /* Bit 15: Channel 15 Output Update Disable (OU15) */ +#define EMIOS_OUDIS_OU16 (1 << 16) /* Bit 16: Channel 16 Output Update Disable (OU16) */ +#define EMIOS_OUDIS_OU17 (1 << 17) /* Bit 17: Channel 17 Output Update Disable (OU17) */ +#define EMIOS_OUDIS_OU18 (1 << 18) /* Bit 18: Channel 18 Output Update Disable (OU18) */ +#define EMIOS_OUDIS_OU19 (1 << 19) /* Bit 19: Channel 19 Output Update Disable (OU19) */ +#define EMIOS_OUDIS_OU20 (1 << 20) /* Bit 20: Channel 20 Output Update Disable (OU20) */ +#define EMIOS_OUDIS_OU21 (1 << 21) /* Bit 21: Channel 21 Output Update Disable (OU21) */ +#define EMIOS_OUDIS_OU22 (1 << 22) /* Bit 22: Channel 22 Output Update Disable (OU22) */ +#define EMIOS_OUDIS_OU23 (1 << 23) /* Bit 23: Channel 23 Output Update Disable (OU23) */ +#define EMIOS_OUDIS_OU(n) (1 << (n)) /* Bit n: Channel n Output Update Disable (OU23) */ + /* Bits 24-31: Reserved */ /* Disable Channel Register (UCDIS) */ @@ -191,14 +191,14 @@ #define EMIOS_A_SHIFT (0) /* Bits 0-15: A */ #define EMIOS_A_MASK (0xffff << EMIOS_A_SHIFT) -#define EMIOS_A(n) ((n << EMIOS_A_SHIFT) & EMIOS_A_MASK) +#define EMIOS_A(n) (((n) << EMIOS_A_SHIFT) & EMIOS_A_MASK) /* Bits 16-31: Reserved */ /* UC B n (Bn) */ #define EMIOS_B_SHIFT (0) /* Bits 0-15: B */ #define EMIOS_B_MASK (0xffff << EMIOS_B_SHIFT) -#define EMIOS_B(n) ((n << EMIOS_B_SHIFT) & EMIOS_B_MASK) +#define EMIOS_B(n) (((n) << EMIOS_B_SHIFT) & EMIOS_B_MASK) /* Bits 16-31: Reserved */ /* UC Counter n (CNTn) */ @@ -314,7 +314,7 @@ /* Bit 15: Reserved */ #define EMIOS_C2_UCEXTPRE_SHIFT (16) /* Bits 16-19: Extended Prescaler (UCEXTPRE) */ #define EMIOS_C2_UCEXTPRE_MASK (0x0f << EMIOS_C2_UCEXTPRE_SHIFT) -#define EMIOS_C2_UCEXTPRE(n) ((n << EMIOS_C2_UCEXTPRE_SHIFT) & EMIOS_C2_UCEXTPRE_MASK) +#define EMIOS_C2_UCEXTPRE(n) (((n) << EMIOS_C2_UCEXTPRE_SHIFT) & EMIOS_C2_UCEXTPRE_MASK) /* Bits 20-31: Reserved */ #endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EMIOS_H */ diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_flexcan.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_flexcan.h index 70cdb9c3ddc..5ef603e1333 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_flexcan.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_flexcan.h @@ -2669,7 +2669,7 @@ /* Bit 13: Reserved */ #define CAN_CTRL1_ERRMSK (1 << 14) /* Bit 14: Error Interrupt Mask (ERRMSK) */ #define CAN_CTRL1_BOFFMSK (1 << 15) /* Bit 15: Bus Off Interrupt Mask (BOFFMSK) */ -#define CAN_CTRL1_TIMINGMSK (0xFFFF << 16) +#define CAN_CTRL1_TIMINGMSK (0xffff << 16) #define CAN_CTRL1_PSEG2_SHIFT (16) /* Bits 16-18: Phase Segment 2 (PSEG2) */ #define CAN_CTRL1_PSEG2_MASK (0x07 << CAN_CTRL1_PSEG2_SHIFT) #define CAN_CTRL1_PSEG2(x) (((x) << CAN_CTRL1_PSEG2_SHIFT) & CAN_CTRL1_PSEG2_MASK) @@ -3121,10 +3121,10 @@ /* CAN MB TX codes */ #define CAN_TXMB_INACTIVE 0x8 /* MB is not active. */ #define CAN_TXMB_ABORT 0x9 /* MB is aborted. */ -#define CAN_TXMB_DATAORREMOTE 0xC /* MB is a TX Data Frame(when MB RTR = 0) or */ +#define CAN_TXMB_DATAORREMOTE 0xc /* MB is a TX Data Frame(when MB RTR = 0) or */ /* MB is a TX Remote Request Frame (when MB RTR = 1). */ -#define CAN_TXMB_TANSWER 0xE /* MB is a TX Response Request Frame from */ +#define CAN_TXMB_TANSWER 0xe /* MB is a TX Response Request Frame from */ /* an incoming Remote Request Frame. */ -#define CAN_TXMB_NOTUSED 0xF /* Not used.*/ +#define CAN_TXMB_NOTUSED 0xf /* Not used.*/ #endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_CAN_H */ diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h index 4e2abafda52..9c7e4a3a9c9 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h @@ -31,7 +31,7 @@ #define FS26_M_FS (1 << 31) /* Bit 31: Main or Fail-safe register selection (M/FS) */ #define FS26_REG_ADDR_SHIFT (25) /* Bits 25-31: Register Address + M/FS */ -#define FS26_REG_ADDR_MASK (0x7F << FS26_REG_ADDR_SHIFT) +#define FS26_REG_ADDR_MASK (0x7f << FS26_REG_ADDR_SHIFT) #define FS26_REG_ADDR(n) (((n) << FS26_REG_ADDR_SHIFT) & FS26_REG_ADDR_MASK) #define FS26_RW (1 << 24) /* Bit 24: Read/Write (reading Bit 24 = 0) */ @@ -49,17 +49,17 @@ /* FS26 Data encoding********************************************************/ #define FS26_DATA_LSB_SHIFT (8) /* Bits 8-15: DATA_LSB */ -#define FS26_DATA_LSB_MASK (0xFF << FS26_DATA_LSB_SHIFT) +#define FS26_DATA_LSB_MASK (0xff << FS26_DATA_LSB_SHIFT) #define FS26_DATA_LSB(n) (((n) << FS26_DATA_LSB_SHIFT) & FS26_DATA_LSB_MASK) #define FS26_DATA_MSB_SHIFT (16) /* Bits 16-23: DATA_MSB */ -#define FS26_DATA_MSB_MASK (0xFF << FS26_DATA_MSB_SHIFT) +#define FS26_DATA_MSB_MASK (0xff << FS26_DATA_MSB_SHIFT) #define FS26_DATA_MSB(n) (((n) << FS26_DATA_MSB_SHIFT) & FS26_DATA_MSB_MASK) #define FS26_DATA_SHIFT (8) /* Bits 8-23: DATA_MSB */ -#define FS26_DATA_MASK (0xFFFF << FS26_DATA_SHIFT) +#define FS26_DATA_MASK (0xffff << FS26_DATA_SHIFT) #define FS26_SET_DATA(n) (((n) << FS26_DATA_SHIFT) & FS26_DATA_MASK) #define FS26_GET_DATA(n) (((n) & FS26_DATA_MASK) >> FS26_DATA_SHIFT) #define FS26_CRC_SHIFT (0) /* Bits 0-7: CRC */ -#define FS26_CRC_MASK (0xFF << FS26_CRC_SHIFT) +#define FS26_CRC_MASK (0xff << FS26_CRC_SHIFT) #define FS26_CRC(n) (((n) << FS26_CRC_SHIFT) & FS26_CRC_MASK) /* FS26 SPI register map */ @@ -74,12 +74,12 @@ #define FS26_M_VSUP_FLG (0x7) /* */ #define FS26_M_VSUP_MSK (0x8) /* */ #define FS26_M_WIO_FLG (0x9) /* */ -#define FS26_M_WIO_MSK (0xA) /* */ -#define FS26_M_COM_FLG (0xB) /* */ -#define FS26_M_COM_MSK (0xC) /* */ -#define FS26_M_SYS_CFG (0xD) /* */ -#define FS26_M_TSD_CFG (0xE) /* */ -#define FS26_M_REG_CFG (0xF) /* */ +#define FS26_M_WIO_MSK (0xa) /* */ +#define FS26_M_COM_FLG (0xb) /* */ +#define FS26_M_COM_MSK (0xc) /* */ +#define FS26_M_SYS_CFG (0xd) /* */ +#define FS26_M_TSD_CFG (0xe) /* */ +#define FS26_M_REG_CFG (0xf) /* */ #define FS26_M_WIO_CFG (0x10) /* */ #define FS26_M_REG_CTRL1 (0x11) /* */ #define FS26_M_REG_CTRL2 (0x12) /* */ @@ -102,12 +102,12 @@ #define FS26_FS_I_SAFE_INPUTS (0x47) /* */ #define FS26_FS_I_NOT_SAFE_INPUTS (0x48) /* */ #define FS26_FS_I_FSSM (0x49) /* */ -#define FS26_FS_I_NOT_FSSM (0x4A) /* */ -#define FS26_FS_WDW_DURATION (0x4B) /* */ -#define FS26_FS_NOT_WDW_DURATION (0x4C) /* */ -#define FS26_FS_WD_ANSWER (0x4D) /* */ -#define FS26_FS_WD_TOKEN (0x4E) /* */ -#define FS26_FS_ABIST_ON_DEMAND (0x4F) /* */ +#define FS26_FS_I_NOT_FSSM (0x4a) /* */ +#define FS26_FS_WDW_DURATION (0x4b) /* */ +#define FS26_FS_NOT_WDW_DURATION (0x4c) /* */ +#define FS26_FS_WD_ANSWER (0x4d) /* */ +#define FS26_FS_WD_TOKEN (0x4e) /* */ +#define FS26_FS_ABIST_ON_DEMAND (0x4f) /* */ #define FS26_FS_OVUV_REG_STATUS (0x50) /* */ #define FS26_FS_RELEASE_FS0B_FS1B (0x51) /* */ #define FS26_FS_SAFE_IOS_1 (0x52) /* */ @@ -243,11 +243,11 @@ #define WD_RFR_CNT_SHIFT (8) /* Reflect the value of the Watchdog Refresh Counter */ #define WD_RFR_CNT_MASK (0x7 << WD_RFR_CNT_SHIFT) -#define WD_RFR_CNT(n) (n & (0x7 << WD_RFR_CNT_SHIFT)) +#define WD_RFR_CNT(n) ((n) & (0x7 << WD_RFR_CNT_SHIFT)) #define WD_ERR_CNT_SHIFT (0) /* Reflect the value of the Watchdog Error Counter */ -#define WD_ERR_CNT_MASK (0xF << WD_ERR_CNT_SHIFT) -#define WD_ERR_CNT(n) ((n & (0x7 << WD_RFR_CNT_SHIFT)) > 11) ? (11) : ((n & (0x7 << WD_RFR_CNT_SHIFT))) +#define WD_ERR_CNT_MASK (0xf << WD_ERR_CNT_SHIFT) +#define WD_ERR_CNT(n) (((n) & (0x7 << WD_RFR_CNT_SHIFT)) > 11) ? (11) : (((n) & (0x7 << WD_RFR_CNT_SHIFT))) /* FS26_FS_I_SAFE_INPUTS register */ @@ -349,13 +349,13 @@ #define DIS8S DIS8S_MASK #define FLT_ERR_CNT_SHIFT (0) /* Reflect the value of the Watchdog Error Counter */ -#define FLT_ERR_CNT_MASK (0xF << FLT_ERR_CNT_SHIFT) +#define FLT_ERR_CNT_MASK (0xf << FLT_ERR_CNT_SHIFT) #define FLT_ERR_CNT(n) ((n & (0x7 << FLT_ERR_CNT_SHIFT)) > 12) ? (12) : ((n & (0x7 << FLT_ERR_CNT_SHIFT))) /* FS26_FS_WDW_DURATION register */ #define WDW_PERIOD_SHIFT (12) /* Watchdog window period */ -#define WDW_PERIOD_MASK (0xF << WDW_PERIOD_SHIFT) +#define WDW_PERIOD_MASK (0xf << WDW_PERIOD_SHIFT) # define WDW_PERIOD_DISABLE (0x0 << WDW_PERIOD_SHIFT) # define WDW_PERIOD_1MS (0x1 << WDW_PERIOD_SHIFT) # define WDW_PERIOD_2MS (0x2 << WDW_PERIOD_SHIFT) @@ -366,12 +366,12 @@ # define WDW_PERIOD_12MS (0x7 << WDW_PERIOD_SHIFT) # define WDW_PERIOD_16MS (0x8 << WDW_PERIOD_SHIFT) # define WDW_PERIOD_24MS (0x9 << WDW_PERIOD_SHIFT) -# define WDW_PERIOD_32MS (0xA << WDW_PERIOD_SHIFT) -# define WDW_PERIOD_64MS (0xB << WDW_PERIOD_SHIFT) -# define WDW_PERIOD_128MS (0xC << WDW_PERIOD_SHIFT) -# define WDW_PERIOD_256MS (0xD << WDW_PERIOD_SHIFT) -# define WDW_PERIOD_512MS (0xE << WDW_PERIOD_SHIFT) -# define WDW_PERIOD_1024MS (0xF << WDW_PERIOD_SHIFT) +# define WDW_PERIOD_32MS (0xa << WDW_PERIOD_SHIFT) +# define WDW_PERIOD_64MS (0xb << WDW_PERIOD_SHIFT) +# define WDW_PERIOD_128MS (0xc << WDW_PERIOD_SHIFT) +# define WDW_PERIOD_256MS (0xd << WDW_PERIOD_SHIFT) +# define WDW_PERIOD_512MS (0xe << WDW_PERIOD_SHIFT) +# define WDW_PERIOD_1024MS (0xf << WDW_PERIOD_SHIFT) #define WDW_DC_SHIFT (6) /* Watchdog window duty cycle */ #define WDW_DC_MASK (0x7 << WDW_DC_SHIFT) @@ -382,7 +382,7 @@ # define WDW_DC_68_31 (0x4 << WDW_PERIOD_SHIFT) #define WDW_RECOVERY_SHIFT (0) /* Watchdog window period */ -#define WDW_RECOVERY_MASK (0xF << WDW_RECOVERY_SHIFT) +#define WDW_RECOVERY_MASK (0xf << WDW_RECOVERY_SHIFT) # define WDW_RECOVERY_DISABLE (0x0 << WDW_RECOVERY_SHIFT) # define WDW_RECOVERY_1MS (0x1 << WDW_RECOVERY_SHIFT) # define WDW_RECOVERY_2MS (0x2 << WDW_RECOVERY_SHIFT) @@ -393,12 +393,12 @@ # define WDW_RECOVERY_12MS (0x7 << WDW_RECOVERY_SHIFT) # define WDW_RECOVERY_16MS (0x8 << WDW_RECOVERY_SHIFT) # define WDW_RECOVERY_24MS (0x9 << WDW_RECOVERY_SHIFT) -# define WDW_RECOVERY_32MS (0xA << WDW_RECOVERY_SHIFT) -# define WDW_RECOVERY_64MS (0xB << WDW_RECOVERY_SHIFT) -# define WDW_RECOVERY_128MS (0xC << WDW_RECOVERY_SHIFT) -# define WDW_RECOVERY_256MS (0xD << WDW_RECOVERY_SHIFT) -# define WDW_RECOVERY_512MS (0xE << WDW_RECOVERY_SHIFT) -# define WDW_RECOVERY_1024MS (0xF << WDW_RECOVERY_SHIFT) +# define WDW_RECOVERY_32MS (0xa << WDW_RECOVERY_SHIFT) +# define WDW_RECOVERY_64MS (0xb << WDW_RECOVERY_SHIFT) +# define WDW_RECOVERY_128MS (0xc << WDW_RECOVERY_SHIFT) +# define WDW_RECOVERY_256MS (0xd << WDW_RECOVERY_SHIFT) +# define WDW_RECOVERY_512MS (0xe << WDW_RECOVERY_SHIFT) +# define WDW_RECOVERY_1024MS (0xf << WDW_RECOVERY_SHIFT) /* FS26_FS_DIAG_SAFETY1 register */ @@ -465,14 +465,14 @@ #define REG_CORRUPT REG_CORRUPT_MASK #define FS_STATES_SHIFT (0) /* LBIST STATUS */ -#define FS_STATES_MASK (0x1F << FS_STATES_SHIFT) +#define FS_STATES_MASK (0x1f << FS_STATES_SHIFT) #define FS_STATES FS_STATES_MASK # define FS_STATES_DEBUG_ENTRY (0x4 << FS_STATES_SHIFT) # define FS_STATES_ENABLE_MON (0x6 << FS_STATES_SHIFT) # define FS_STATES_RSTB_RELEASE (0x8 << FS_STATES_SHIFT) # define FS_STATES_INIT_FS (0x9 << FS_STATES_SHIFT) -# define FS_STATES_SAFETY_OUT_NOT (0xA << FS_STATES_SHIFT) -# define FS_STATES_NORMAL (0xB << FS_STATES_SHIFT) +# define FS_STATES_SAFETY_OUT_NOT (0xa << FS_STATES_SHIFT) +# define FS_STATES_NORMAL (0xb << FS_STATES_SHIFT) /* FS26_FS_GRL_FLAGS register */ diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h index 0eb9f99c3f6..ef189d60637 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h @@ -72,7 +72,7 @@ /* Bits 8-15: Reserved */ #define FXOSC_CTRL_EOCV_SHIFT (16) /* Bits 16-23: End of count value (EOCV) */ #define FXOSC_CTRL_EOCV_MASK (0xff << FXOSC_CTRL_EOCV_SHIFT) -#define FXOSC_CTRL_EOCV(n) ((n << FXOSC_CTRL_EOCV_SHIFT) & FXOSC_CTRL_EOCV_MASK) +#define FXOSC_CTRL_EOCV(n) (((n) << FXOSC_CTRL_EOCV_SHIFT) & FXOSC_CTRL_EOCV_MASK) #define FXOSC_CTRL_COMP_EN (1 << 24) /* Bit 24: Comparator enable (COMP_EN) */ # define FXOSC_CTRL_COMP_DIS (0 << 24) /* Comparator disable */ /* Bits 25-30: Reserved */ diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h index e8ac632f10f..fab62c1d9e2 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h @@ -403,7 +403,7 @@ #define QSPI_LUTKEY_KEY_SHIFT (0) /* Bits 0-31: Key to lock or unlock the LUT (KEY) */ #define QSPI_LUTKEY_KEY_MASK (0xffffffff << QSPI_LUTKEY_KEY_SHIFT) -#define QSPI_LUTKEY_KEY (0x5AF05AF0UL) +#define QSPI_LUTKEY_KEY (0x5AF05AF0ul) /* LUT Lock Configuration Register (LKCR) */ @@ -447,59 +447,58 @@ typedef enum { - QSPI_SIDE_A1 = 0x00u, /* Serial flash connected on side A1 */ - QSPI_SIDE_A2 = 0x01u, /* Serial flash connected on side A2 */ - QSPI_SIDE_B1 = 0x02u, /* Serial flash connected on side B1 */ - QSPI_SIDE_B2 = 0x03u, /* Serial flash connected on side B2 */ + QSPI_SIDE_A1 = 0x00u, /* Serial flash connected on side A1 */ + QSPI_SIDE_A2 = 0x01u, /* Serial flash connected on side A2 */ + QSPI_SIDE_B1 = 0x02u, /* Serial flash connected on side B1 */ + QSPI_SIDE_B2 = 0x03u, /* Serial flash connected on side B2 */ } s32k3xx_qspi_connectiontype; /* flash operation type */ typedef enum { - QSPI_OP_TYPE_CMD = 0x00u, /* Simple command */ - QSPI_OP_TYPE_WRITE_REG = 0x01u, /* Write value in external flash register */ - QSPI_OP_TYPE_RMW_REG = 0x02u, /* RMW command on external flash register */ - QSPI_OP_TYPE_READ_REG = 0x03u, /* Read external flash register until expected value is read */ - QSPI_OP_TYPE_QSPI_CFG = 0x04u, /* Re-configure QSPI controller */ + QSPI_OP_TYPE_CMD = 0x00u, /* Simple command */ + QSPI_OP_TYPE_WRITE_REG = 0x01u, /* Write value in external flash register */ + QSPI_OP_TYPE_RMW_REG = 0x02u, /* RMW command on external flash register */ + QSPI_OP_TYPE_READ_REG = 0x03u, /* Read external flash register until expected value is read */ + QSPI_OP_TYPE_QSPI_CFG = 0x04u, /* Re-configure QSPI controller */ } s32k3xx_qspi_optype; /* Lut commands */ typedef enum { - QSPI_LUT_INSTR_STOP = (0U << 10U), /* End of sequence */ - QSPI_LUT_INSTR_CMD = (1U << 10U), /* Command */ - QSPI_LUT_INSTR_ADDR = (2U << 10U), /* Address */ - QSPI_LUT_INSTR_DUMMY = (3U << 10U), /* Dummy cycles */ - QSPI_LUT_INSTR_MODE = (4U << 10U), /* 8-bit mode */ - QSPI_LUT_INSTR_MODE2 = (5U << 10U), /* 2-bit mode */ - QSPI_LUT_INSTR_MODE4 = (6U << 10U), /* 4-bit mode */ - QSPI_LUT_INSTR_READ = (7U << 10U), /* Read data */ - QSPI_LUT_INSTR_WRITE = (8U << 10U), /* Write data */ - QSPI_LUT_INSTR_JMP_ON_CS = (9U << 10U), /* Jump on chip select deassert and stop */ - QSPI_LUT_INSTR_ADDR_DDR = (10U << 10U), /* Address - DDR mode */ - QSPI_LUT_INSTR_MODE_DDR = (11U << 10U), /* 8-bit mode - DDR mode */ - QSPI_LUT_INSTR_MODE2_DDR = (12U << 10U), /* 2-bit mode - DDR mode */ - QSPI_LUT_INSTR_MODE4_DDR = (13U << 10U), /* 4-bit mode - DDR mode */ - QSPI_LUT_INSTR_READ_DDR = (14U << 10U), /* Read data - DDR mode */ - QSPI_LUT_INSTR_WRITE_DDR = (15U << 10U), /* Write data - DDR mode */ - QSPI_LUT_INSTR_DATA_LEARN = (16U << 10U), /* Data learning pattern */ - QSPI_LUT_INSTR_CMD_DDR = (17U << 10U), /* Command - DDR mode */ - QSPI_LUT_INSTR_CADDR = (18U << 10U), /* Column address */ - QSPI_LUT_INSTR_CADDR_DDR = (19U << 10U), /* Column address - DDR mode */ - QSPI_LUT_INSTR_JMP_TO_SEQ = (20U << 10U), /* Jump on chip select deassert and continue */ + QSPI_LUT_INSTR_STOP = (0u << 10u), /* End of sequence */ + QSPI_LUT_INSTR_CMD = (1u << 10u), /* Command */ + QSPI_LUT_INSTR_ADDR = (2u << 10u), /* Address */ + QSPI_LUT_INSTR_DUMMY = (3u << 10u), /* Dummy cycles */ + QSPI_LUT_INSTR_MODE = (4u << 10u), /* 8-bit mode */ + QSPI_LUT_INSTR_MODE2 = (5u << 10u), /* 2-bit mode */ + QSPI_LUT_INSTR_MODE4 = (6u << 10u), /* 4-bit mode */ + QSPI_LUT_INSTR_READ = (7u << 10u), /* Read data */ + QSPI_LUT_INSTR_WRITE = (8u << 10u), /* Write data */ + QSPI_LUT_INSTR_JMP_ON_CS = (9u << 10u), /* Jump on chip select deassert and stop */ + QSPI_LUT_INSTR_ADDR_DDR = (10u << 10u), /* Address - DDR mode */ + QSPI_LUT_INSTR_MODE_DDR = (11u << 10u), /* 8-bit mode - DDR mode */ + QSPI_LUT_INSTR_MODE2_DDR = (12u << 10u), /* 2-bit mode - DDR mode */ + QSPI_LUT_INSTR_MODE4_DDR = (13u << 10u), /* 4-bit mode - DDR mode */ + QSPI_LUT_INSTR_READ_DDR = (14u << 10u), /* Read data - DDR mode */ + QSPI_LUT_INSTR_WRITE_DDR = (15u << 10u), /* Write data - DDR mode */ + QSPI_LUT_INSTR_DATA_LEARN = (16u << 10u), /* Data learning pattern */ + QSPI_LUT_INSTR_CMD_DDR = (17u << 10u), /* Command - DDR mode */ + QSPI_LUT_INSTR_CADDR = (18u << 10u), /* Column address */ + QSPI_LUT_INSTR_CADDR_DDR = (19u << 10u), /* Column address - DDR mode */ + QSPI_LUT_INSTR_JMP_TO_SEQ = (20u << 10u), /* Jump on chip select deassert and continue */ } s32k3xx_qspi_lutcommandstype; /* Lut pad options */ typedef enum { - QSPI_LUT_PADS_1 = (0U << 8U), /* 1 Pad */ - QSPI_LUT_PADS_2 = (1U << 8U), /* 2 Pads */ - QSPI_LUT_PADS_4 = (2U << 8U), /* 4 Pads */ - QSPI_LUT_PADS_8 = (3U << 8U), /* 8 Pads */ + QSPI_LUT_PADS_1 = (0u << 8u), /* 1 Pad */ + QSPI_LUT_PADS_2 = (1u << 8u), /* 2 Pads */ + QSPI_LUT_PADS_4 = (2u << 8u), /* 4 Pads */ + QSPI_LUT_PADS_8 = (3u << 8u), /* 8 Pads */ } s32k3xx_qspi_lutpadstype; #endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H */ - diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_virtwrapper.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_virtwrapper.h index bb148f3e56f..53404433758 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_virtwrapper.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_virtwrapper.h @@ -198,7 +198,7 @@ /* Parameter_n Register (REG_D1055_1040) */ /* Bits 0-29: Reserved */ -#define VIRTWRAPPER_REG_D_REG_GCR_SHIFT (30) /* Bits 30-31: GCR REgister Of REG_PROT (REG_GCR) */ +#define VIRTWRAPPER_REG_D_REG_GCR_SHIFT (30) /* Bits 30-31: GCR Register Of REG_PROT (REG_GCR) */ #define VIRTWRAPPER_REG_D_REG_GCR_MASK (0x03 << VIRTWRAPPER_REG_D_REG_GCR_SHIFT) -#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_VIRTWRAPPER_H */ \ No newline at end of file +#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_VIRTWRAPPER_H */ diff --git a/arch/arm/src/s32k3xx/s32k3xx_edma.c b/arch/arm/src/s32k3xx/s32k3xx_edma.c index 1e1c210b208..49d4e4cc305 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_edma.c +++ b/arch/arm/src/s32k3xx/s32k3xx_edma.c @@ -94,7 +94,7 @@ /* Align to the cache line size which we assume is >= 8 */ # define EDMA_ALIGN ARMV7M_DCACHE_LINESIZE -# define EDMA_ALIGN_MASK (EDMA_ALIGN-1) +# define EDMA_ALIGN_MASK (EDMA_ALIGN - 1) # define EDMA_ALIGN_UP(n) (((n) + EDMA_ALIGN_MASK) & ~EDMA_ALIGN_MASK) #else @@ -164,6 +164,42 @@ struct s32k3xx_edma_s * Private Data ****************************************************************************/ +uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] = +{ + S32K3XX_EDMA_CH0_CSR, + S32K3XX_EDMA_CH1_CSR, + S32K3XX_EDMA_CH2_CSR, + S32K3XX_EDMA_CH3_CSR, + S32K3XX_EDMA_CH4_CSR, + S32K3XX_EDMA_CH5_CSR, + S32K3XX_EDMA_CH6_CSR, + S32K3XX_EDMA_CH7_CSR, + S32K3XX_EDMA_CH8_CSR, + S32K3XX_EDMA_CH9_CSR, + S32K3XX_EDMA_CH10_CSR, + S32K3XX_EDMA_CH11_CSR, + S32K3XX_EDMA_CH12_CSR, + S32K3XX_EDMA_CH13_CSR, + S32K3XX_EDMA_CH14_CSR, + S32K3XX_EDMA_CH15_CSR, + S32K3XX_EDMA_CH16_CSR, + S32K3XX_EDMA_CH17_CSR, + S32K3XX_EDMA_CH18_CSR, + S32K3XX_EDMA_CH19_CSR, + S32K3XX_EDMA_CH20_CSR, + S32K3XX_EDMA_CH21_CSR, + S32K3XX_EDMA_CH22_CSR, + S32K3XX_EDMA_CH23_CSR, + S32K3XX_EDMA_CH24_CSR, + S32K3XX_EDMA_CH25_CSR, + S32K3XX_EDMA_CH26_CSR, + S32K3XX_EDMA_CH27_CSR, + S32K3XX_EDMA_CH28_CSR, + S32K3XX_EDMA_CH29_CSR, + S32K3XX_EDMA_CH30_CSR, + S32K3XX_EDMA_CH31_CSR +}; + /* The state of the eDMA */ static struct s32k3xx_edma_s g_edma;