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More stm32f3discovery updates
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5624 42af7a65-404d-4744-a932-0658087f49c3
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@@ -120,9 +120,12 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
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/* The following requires exclusive access to the GPIO registers */
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flags = irqsave();
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#if defined(CONFIG_STM32_STM32F10XX)
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lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
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g_portchar[port], pinset, base, msg);
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if ((getreg32(STM32_RCC_APB2ENR) & RCC_APB2ENR_IOPEN(port)) != 0)
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{
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lldbg(" CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n",
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@@ -143,11 +146,38 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
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lldbg(" GPIO%c not enabled: APB2ENR: %08x\n",
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g_portchar[port], getreg32(STM32_RCC_APB2ENR));
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}
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#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
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#elif defined(CONFIG_STM32_STM32F30XX)
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DEBUGASSERT(port < STM32_NGPIO_PORTS);
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lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
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g_portchar[port], pinset, base, msg);
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/* GPIOs are always enabled */
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lldbg(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
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getreg32(base + STM32_GPIO_MODER_OFFSET),
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getreg32(base + STM32_GPIO_OTYPER_OFFSET),
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getreg32(base + STM32_GPIO_OSPEED_OFFSET),
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getreg32(base + STM32_GPIO_PUPDR_OFFSET));
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lldbg(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
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getreg32(base + STM32_GPIO_IDR_OFFSET),
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getreg32(base + STM32_GPIO_ODR_OFFSET),
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getreg32(base + STM32_GPIO_BSRR_OFFSET),
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getreg32(base + STM32_GPIO_LCKR_OFFSET));
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lldbg(" AFRH: %08x AFRL: %08x BRR: %04x\n",
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getreg32(base + STM32_GPIO_ARFH_OFFSET),
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getreg32(base + STM32_GPIO_AFRL_OFFSET),
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getreg32(base + STM32_GPIO_BRR_OFFSET));
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#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
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DEBUGASSERT(port < STM32_NGPIO_PORTS);
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lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
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g_portchar[port], pinset, base, msg);
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if ((getreg32(STM32_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0)
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{
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lldbg(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
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