From d5d770d0bcee1bf18ef4c5b5c7235e966776e1d1 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 8 Feb 2013 14:42:18 +0000 Subject: [PATCH] More stm32f3discovery updates git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5624 42af7a65-404d-4744-a932-0658087f49c3 --- arch/arm/src/stm32/stm32_dumpgpio.c | 32 ++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/stm32_dumpgpio.c b/arch/arm/src/stm32/stm32_dumpgpio.c index cd193383154..393467b19a6 100644 --- a/arch/arm/src/stm32/stm32_dumpgpio.c +++ b/arch/arm/src/stm32/stm32_dumpgpio.c @@ -120,9 +120,12 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) /* The following requires exclusive access to the GPIO registers */ flags = irqsave(); + #if defined(CONFIG_STM32_STM32F10XX) + lldbg("GPIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); + if ((getreg32(STM32_RCC_APB2ENR) & RCC_APB2ENR_IOPEN(port)) != 0) { lldbg(" CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n", @@ -143,11 +146,38 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) lldbg(" GPIO%c not enabled: APB2ENR: %08x\n", g_portchar[port], getreg32(STM32_RCC_APB2ENR)); } -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) + +#elif defined(CONFIG_STM32_STM32F30XX) + DEBUGASSERT(port < STM32_NGPIO_PORTS); lldbg("GPIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); + + /* GPIOs are always enabled */ + + lldbg(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); + lldbg(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); + lldbg(" AFRH: %08x AFRL: %08x BRR: %04x\n", + getreg32(base + STM32_GPIO_ARFH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET), + getreg32(base + STM32_GPIO_BRR_OFFSET)); + +#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) + + DEBUGASSERT(port < STM32_NGPIO_PORTS); + + lldbg("GPIO%c pinset: %08x base: %08x -- %s\n", + g_portchar[port], pinset, base, msg); + if ((getreg32(STM32_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0) { lldbg(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",