From cbf7401dfbd717bd8cc445462ad4567c1e636f28 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 6 Mar 2016 12:24:24 -0600 Subject: [PATCH] i.MX6 GPIO: Add IOMUXC logic to set pin as a GPIO --- arch/arm/src/imx6/chip/imx_gpio.h | 17 +- arch/arm/src/imx6/chip/imx_iomuxc.h | 660 +++++++++++++++++++--------- arch/arm/src/imx6/imx_gpio.c | 317 ++++++++++++- arch/arm/src/imx6/imx_iomuxc.h | 67 +++ 4 files changed, 854 insertions(+), 207 deletions(-) create mode 100644 arch/arm/src/imx6/imx_iomuxc.h diff --git a/arch/arm/src/imx6/chip/imx_gpio.h b/arch/arm/src/imx6/chip/imx_gpio.h index 6476c553bc5..b63cb1a963e 100644 --- a/arch/arm/src/imx6/chip/imx_gpio.h +++ b/arch/arm/src/imx6/chip/imx_gpio.h @@ -51,13 +51,16 @@ * Pre-processor Definitions ************************************************************************************/ -#define GPIO1 0 /* Port 1 index */ -#define GPIO2 1 /* Port 2 index */ -#define GPIO3 2 /* Port 3 index */ -#define GPIO4 3 /* Port 4 index */ -#define GPIO5 4 /* Port 5 index */ -#define GPIO6 5 /* Port 6 index */ -#define GPIO7 6 /* Port 7 index */ +#define GPIO1 0 /* Port 1 index */ +#define GPIO2 1 /* Port 2 index */ +#define GPIO3 2 /* Port 3 index */ +#define GPIO4 3 /* Port 4 index */ +#define GPIO5 4 /* Port 5 index */ +#define GPIO6 5 /* Port 6 index */ +#define GPIO7 6 /* Port 7 index */ + +#define IMX_GPIO_NPORTS 7 /* Seven total ports */ +#define IMX_GPIO_NPINS 32 /* Up to 32 pins per port */ /* GPIO Register Offsets ************************************************************/ diff --git a/arch/arm/src/imx6/chip/imx_iomuxc.h b/arch/arm/src/imx6/chip/imx_iomuxc.h index 97ca437c73d..17f392db9f9 100644 --- a/arch/arm/src/imx6/chip/imx_iomuxc.h +++ b/arch/arm/src/imx6/chip/imx_iomuxc.h @@ -78,207 +78,209 @@ /* Pad Mux Registers */ /* Pad Mux Register Indices (used by software for table lookups) */ -#define IMX_PAD_SD2_DATA1 0 -#define IMX_PAD_SD2_DATA2 1 -#define IMX_PAD_SD2_DATA0 2 -#define IMX_PAD_RGMII_TXC 3 -#define IMX_PAD_RGMII_TD0 4 -#define IMX_PAD_RGMII_TD1 5 -#define IMX_PAD_RGMII_TD2 6 -#define IMX_PAD_RGMII_TD3 7 -#define IMX_PAD_RGMII_RX_CTL 8 -#define IMX_PAD_RGMII_RD0 9 -#define IMX_PAD_RGMII_TX_CTL 10 -#define IMX_PAD_RGMII_RD1 11 -#define IMX_PAD_RGMII_RD2 12 -#define IMX_PAD_RGMII_RD3 13 -#define IMX_PAD_RGMII_RXC 14 -#define IMX_PAD_EIM_ADDR25 15 -#define IMX_PAD_EIM_EB2 16 -#define IMX_PAD_EIM_DATA16 17 -#define IMX_PAD_EIM_DATA17 18 -#define IMX_PAD_EIM_DATA18 19 -#define IMX_PAD_EIM_DATA19 20 -#define IMX_PAD_EIM_DATA20 21 -#define IMX_PAD_EIM_DATA21 22 -#define IMX_PAD_EIM_DATA22 23 -#define IMX_PAD_EIM_DATA23 24 -#define IMX_PAD_EIM_EB3 25 -#define IMX_PAD_EIM_DATA24 26 -#define IMX_PAD_EIM_DATA25 27 -#define IMX_PAD_EIM_DATA26 28 -#define IMX_PAD_EIM_DATA27 29 -#define IMX_PAD_EIM_DATA28 30 -#define IMX_PAD_EIM_DATA29 31 -#define IMX_PAD_EIM_DATA30 32 -#define IMX_PAD_EIM_DATA31 33 -#define IMX_PAD_EIM_ADDR24 34 -#define IMX_PAD_EIM_ADDR23 35 -#define IMX_PAD_EIM_ADDR22 36 -#define IMX_PAD_EIM_ADDR21 37 -#define IMX_PAD_EIM_ADDR20 38 -#define IMX_PAD_EIM_ADDR19 49 -#define IMX_PAD_EIM_ADDR18 40 -#define IMX_PAD_EIM_ADDR17 41 -#define IMX_PAD_EIM_ADDR16 42 -#define IMX_PAD_EIM_CS0 43 -#define IMX_PAD_EIM_CS1 44 -#define IMX_PAD_EIM_OE 45 -#define IMX_PAD_EIM_RW 46 -#define IMX_PAD_EIM_LBA 47 -#define IMX_PAD_EIM_EB0 58 -#define IMX_PAD_EIM_EB1 59 -#define IMX_PAD_EIM_AD00 50 -#define IMX_PAD_EIM_AD01 51 -#define IMX_PAD_EIM_AD02 52 -#define IMX_PAD_EIM_AD03 53 -#define IMX_PAD_EIM_AD04 54 -#define IMX_PAD_EIM_AD05 55 -#define IMX_PAD_EIM_AD06 56 -#define IMX_PAD_EIM_AD07 67 -#define IMX_PAD_EIM_AD08 68 -#define IMX_PAD_EIM_AD09 69 -#define IMX_PAD_EIM_AD10 60 -#define IMX_PAD_EIM_AD11 61 -#define IMX_PAD_EIM_AD12 62 -#define IMX_PAD_EIM_AD13 63 -#define IMX_PAD_EIM_AD14 64 -#define IMX_PAD_EIM_AD15 65 -#define IMX_PAD_EIM_WAIT 66 -#define IMX_PAD_EIM_BCLK 67 -#define IMX_PAD_DI0_DISP_CLK 68 -#define IMX_PAD_DI0_PIN15 69 -#define IMX_PAD_DI0_PIN02 70 -#define IMX_PAD_DI0_PIN03 71 -#define IMX_PAD_DI0_PIN04 72 -#define IMX_PAD_DISP0_DATA00 73 -#define IMX_PAD_DISP0_DATA01 74 -#define IMX_PAD_DISP0_DATA02 75 -#define IMX_PAD_DISP0_DATA03 76 -#define IMX_PAD_DISP0_DATA04 77 -#define IMX_PAD_DISP0_DATA05 78 -#define IMX_PAD_DISP0_DATA06 79 -#define IMX_PAD_DISP0_DATA07 80 -#define IMX_PAD_DISP0_DATA08 81 -#define IMX_PAD_DISP0_DATA09 82 -#define IMX_PAD_DISP0_DATA10 83 -#define IMX_PAD_DISP0_DATA11 84 -#define IMX_PAD_DISP0_DATA12 85 -#define IMX_PAD_DISP0_DATA13 86 -#define IMX_PAD_DISP0_DATA14 87 -#define IMX_PAD_DISP0_DATA15 88 -#define IMX_PAD_DISP0_DATA16 89 -#define IMX_PAD_DISP0_DATA17 90 -#define IMX_PAD_DISP0_DATA18 91 -#define IMX_PAD_DISP0_DATA19 92 -#define IMX_PAD_DISP0_DATA20 93 -#define IMX_PAD_DISP0_DATA21 94 -#define IMX_PAD_DISP0_DATA22 95 -#define IMX_PAD_DISP0_DATA23 96 -#define IMX_PAD_ENET_MDIO 97 -#define IMX_PAD_ENET_REF_CLK 98 -#define IMX_PAD_ENET_RX_ER 99 -#define IMX_PAD_ENET_CRS_DV 100 -#define IMX_PAD_ENET_RX_DATA1 101 -#define IMX_PAD_ENET_RX_DATA0 102 -#define IMX_PAD_ENET_TX_EN 103 -#define IMX_PAD_ENET_TX_DATA1 104 -#define IMX_PAD_ENET_TX_DATA0 105 -#define IMX_PAD_ENET_MDC 106 -#define IMX_PAD_KEY_COL0 107 -#define IMX_PAD_KEY_ROW0 108 -#define IMX_PAD_KEY_COL1 109 -#define IMX_PAD_KEY_ROW1 110 -#define IMX_PAD_KEY_COL2 111 -#define IMX_PAD_KEY_ROW2 112 -#define IMX_PAD_KEY_COL3 113 -#define IMX_PAD_KEY_ROW3 114 -#define IMX_PAD_KEY_COL4 115 -#define IMX_PAD_KEY_ROW4 116 -#define IMX_PAD_GPIO00 117 -#define IMX_PAD_GPIO01 118 -#define IMX_PAD_GPIO09 119 -#define IMX_PAD_GPIO03 120 -#define IMX_PAD_GPIO06 121 -#define IMX_PAD_GPIO02 122 -#define IMX_PAD_GPIO04 123 -#define IMX_PAD_GPIO05 124 -#define IMX_PAD_GPIO07 125 -#define IMX_PAD_GPIO08 126 -#define IMX_PAD_GPIO16 127 -#define IMX_PAD_GPIO17 128 -#define IMX_PAD_GPIO18 129 -#define IMX_PAD_GPIO19 130 -#define IMX_PAD_CSI0_PIXCLK 131 -#define IMX_PAD_CSI0_HSYNC 132 -#define IMX_PAD_CSI0_DATA_EN 133 -#define IMX_PAD_CSI0_VSYNC 134 -#define IMX_PAD_CSI0_DATA04 135 -#define IMX_PAD_CSI0_DATA05 136 -#define IMX_PAD_CSI0_DATA06 137 -#define IMX_PAD_CSI0_DATA07 138 -#define IMX_PAD_CSI0_DATA08 139 -#define IMX_PAD_CSI0_DATA09 140 -#define IMX_PAD_CSI0_DATA10 141 -#define IMX_PAD_CSI0_DATA11 142 -#define IMX_PAD_CSI0_DATA12 143 -#define IMX_PAD_CSI0_DATA13 144 -#define IMX_PAD_CSI0_DATA14 145 -#define IMX_PAD_CSI0_DATA15 146 -#define IMX_PAD_CSI0_DATA16 147 -#define IMX_PAD_CSI0_DATA17 148 -#define IMX_PAD_CSI0_DATA18 149 -#define IMX_PAD_CSI0_DATA19 150 -#define IMX_PAD_SD3_DATA7 151 -#define IMX_PAD_SD3_DATA6 152 -#define IMX_PAD_SD3_DATA5 153 -#define IMX_PAD_SD3_DATA4 154 -#define IMX_PAD_SD3_CMD 155 -#define IMX_PAD_SD3_CLK 156 -#define IMX_PAD_SD3_DATA0 157 -#define IMX_PAD_SD3_DATA1 158 -#define IMX_PAD_SD3_DATA2 159 -#define IMX_PAD_SD3_DATA3 160 -#define IMX_PAD_SD3_RESET 161 -#define IMX_PAD_NAND_CLE 162 -#define IMX_PAD_NAND_ALE 163 -#define IMX_PAD_NAND_WP 164 -#define IMX_PAD_NAND_READY 165 -#define IMX_PAD_NAND_CS0 166 -#define IMX_PAD_NAND_CS1 167 -#define IMX_PAD_NAND_CS2 168 -#define IMX_PAD_NAND_CS3 169 -#define IMX_PAD_SD4_CMD 170 -#define IMX_PAD_SD4_CLK 171 -#define IMX_PAD_NAND_DATA00 172 -#define IMX_PAD_NAND_DATA01 173 -#define IMX_PAD_NAND_DATA02 174 -#define IMX_PAD_NAND_DATA03 175 -#define IMX_PAD_NAND_DATA04 176 -#define IMX_PAD_NAND_DATA05 177 -#define IMX_PAD_NAND_DATA06 178 -#define IMX_PAD_NAND_DATA07 189 -#define IMX_PAD_SD4_DATA0 180 -#define IMX_PAD_SD4_DATA1 181 -#define IMX_PAD_SD4_DATA2 182 -#define IMX_PAD_SD4_DATA3 183 -#define IMX_PAD_SD4_DATA4 184 -#define IMX_PAD_SD4_DATA5 185 -#define IMX_PAD_SD4_DATA6 186 -#define IMX_PAD_SD4_DATA7 187 -#define IMX_PAD_SD1_DATA1 188 -#define IMX_PAD_SD1_DATA0 189 -#define IMX_PAD_SD1_DATA3 190 -#define IMX_PAD_SD1_CMD 191 -#define IMX_PAD_SD1_DATA2 192 -#define IMX_PAD_SD1_CLK 193 -#define IMX_PAD_SD2_CLK 194 -#define IMX_PAD_SD2_CMD 195 -#define IMX_PAD_SD2_DATA3 196 +#define IMX_PADMUX_SD2_DATA1_INDEX 0 +#define IMX_PADMUX_SD2_DATA2_INDEX 1 +#define IMX_PADMUX_SD2_DATA0_INDEX 2 +#define IMX_PADMUX_RGMII_TXC_INDEX 3 +#define IMX_PADMUX_RGMII_TD0_INDEX 4 +#define IMX_PADMUX_RGMII_TD1_INDEX 5 +#define IMX_PADMUX_RGMII_TD2_INDEX 6 +#define IMX_PADMUX_RGMII_TD3_INDEX 7 +#define IMX_PADMUX_RGMII_RX_CTL_INDEX 8 +#define IMX_PADMUX_RGMII_RD0_INDEX 9 +#define IMX_PADMUX_RGMII_TX_CTL_INDEX 10 +#define IMX_PADMUX_RGMII_RD1_INDEX 11 +#define IMX_PADMUX_RGMII_RD2_INDEX 12 +#define IMX_PADMUX_RGMII_RD3_INDEX 13 +#define IMX_PADMUX_RGMII_RXC_INDEX 14 +#define IMX_PADMUX_EIM_ADDR25_INDEX 15 +#define IMX_PADMUX_EIM_EB2_INDEX 16 +#define IMX_PADMUX_EIM_DATA16_INDEX 17 +#define IMX_PADMUX_EIM_DATA17_INDEX 18 +#define IMX_PADMUX_EIM_DATA18_INDEX 19 +#define IMX_PADMUX_EIM_DATA19_INDEX 20 +#define IMX_PADMUX_EIM_DATA20_INDEX 21 +#define IMX_PADMUX_EIM_DATA21_INDEX 22 +#define IMX_PADMUX_EIM_DATA22_INDEX 23 +#define IMX_PADMUX_EIM_DATA23_INDEX 24 +#define IMX_PADMUX_EIM_EB3_INDEX 25 +#define IMX_PADMUX_EIM_DATA24_INDEX 26 +#define IMX_PADMUX_EIM_DATA25_INDEX 27 +#define IMX_PADMUX_EIM_DATA26_INDEX 28 +#define IMX_PADMUX_EIM_DATA27_INDEX 29 +#define IMX_PADMUX_EIM_DATA28_INDEX 30 +#define IMX_PADMUX_EIM_DATA29_INDEX 31 +#define IMX_PADMUX_EIM_DATA30_INDEX 32 +#define IMX_PADMUX_EIM_DATA31_INDEX 33 +#define IMX_PADMUX_EIM_ADDR24_INDEX 34 +#define IMX_PADMUX_EIM_ADDR23_INDEX 35 +#define IMX_PADMUX_EIM_ADDR22_INDEX 36 +#define IMX_PADMUX_EIM_ADDR21_INDEX 37 +#define IMX_PADMUX_EIM_ADDR20_INDEX 38 +#define IMX_PADMUX_EIM_ADDR19_INDEX 49 +#define IMX_PADMUX_EIM_ADDR18_INDEX 40 +#define IMX_PADMUX_EIM_ADDR17_INDEX 41 +#define IMX_PADMUX_EIM_ADDR16_INDEX 42 +#define IMX_PADMUX_EIM_CS0_INDEX 43 +#define IMX_PADMUX_EIM_CS1_INDEX 44 +#define IMX_PADMUX_EIM_OE_INDEX 45 +#define IMX_PADMUX_EIM_RW_INDEX 46 +#define IMX_PADMUX_EIM_LBA_INDEX 47 +#define IMX_PADMUX_EIM_EB0_INDEX 58 +#define IMX_PADMUX_EIM_EB1_INDEX 59 +#define IMX_PADMUX_EIM_AD00_INDEX 50 +#define IMX_PADMUX_EIM_AD01_INDEX 51 +#define IMX_PADMUX_EIM_AD02_INDEX 52 +#define IMX_PADMUX_EIM_AD03_INDEX 53 +#define IMX_PADMUX_EIM_AD04_INDEX 54 +#define IMX_PADMUX_EIM_AD05_INDEX 55 +#define IMX_PADMUX_EIM_AD06_INDEX 56 +#define IMX_PADMUX_EIM_AD07_INDEX 67 +#define IMX_PADMUX_EIM_AD08_INDEX 68 +#define IMX_PADMUX_EIM_AD09_INDEX 69 +#define IMX_PADMUX_EIM_AD10_INDEX 60 +#define IMX_PADMUX_EIM_AD11_INDEX 61 +#define IMX_PADMUX_EIM_AD12_INDEX 62 +#define IMX_PADMUX_EIM_AD13_INDEX 63 +#define IMX_PADMUX_EIM_AD14_INDEX 64 +#define IMX_PADMUX_EIM_AD15_INDEX 65 +#define IMX_PADMUX_EIM_WAIT_INDEX 66 +#define IMX_PADMUX_EIM_BCLK_INDEX 67 +#define IMX_PADMUX_DI0_DISP_CLK_INDEX 68 +#define IMX_PADMUX_DI0_PIN15_INDEX 69 +#define IMX_PADMUX_DI0_PIN02_INDEX 70 +#define IMX_PADMUX_DI0_PIN03_INDEX 71 +#define IMX_PADMUX_DI0_PIN04_INDEX 72 +#define IMX_PADMUX_DISP0_DATA00_INDEX 73 +#define IMX_PADMUX_DISP0_DATA01_INDEX 74 +#define IMX_PADMUX_DISP0_DATA02_INDEX 75 +#define IMX_PADMUX_DISP0_DATA03_INDEX 76 +#define IMX_PADMUX_DISP0_DATA04_INDEX 77 +#define IMX_PADMUX_DISP0_DATA05_INDEX 78 +#define IMX_PADMUX_DISP0_DATA06_INDEX 79 +#define IMX_PADMUX_DISP0_DATA07_INDEX 80 +#define IMX_PADMUX_DISP0_DATA08_INDEX 81 +#define IMX_PADMUX_DISP0_DATA09_INDEX 82 +#define IMX_PADMUX_DISP0_DATA10_INDEX 83 +#define IMX_PADMUX_DISP0_DATA11_INDEX 84 +#define IMX_PADMUX_DISP0_DATA12_INDEX 85 +#define IMX_PADMUX_DISP0_DATA13_INDEX 86 +#define IMX_PADMUX_DISP0_DATA14_INDEX 87 +#define IMX_PADMUX_DISP0_DATA15_INDEX 88 +#define IMX_PADMUX_DISP0_DATA16_INDEX 89 +#define IMX_PADMUX_DISP0_DATA17_INDEX 90 +#define IMX_PADMUX_DISP0_DATA18_INDEX 91 +#define IMX_PADMUX_DISP0_DATA19_INDEX 92 +#define IMX_PADMUX_DISP0_DATA20_INDEX 93 +#define IMX_PADMUX_DISP0_DATA21_INDEX 94 +#define IMX_PADMUX_DISP0_DATA22_INDEX 95 +#define IMX_PADMUX_DISP0_DATA23_INDEX 96 +#define IMX_PADMUX_ENET_MDIO_INDEX 97 +#define IMX_PADMUX_ENET_REF_CLK_INDEX 98 +#define IMX_PADMUX_ENET_RX_ER_INDEX 99 +#define IMX_PADMUX_ENET_CRS_DV_INDEX 100 +#define IMX_PADMUX_ENET_RX_DATA1_INDEX 101 +#define IMX_PADMUX_ENET_RX_DATA0_INDEX 102 +#define IMX_PADMUX_ENET_TX_EN_INDEX 103 +#define IMX_PADMUX_ENET_TX_DATA1_INDEX 104 +#define IMX_PADMUX_ENET_TX_DATA0_INDEX 105 +#define IMX_PADMUX_ENET_MDC_INDEX 106 +#define IMX_PADMUX_KEY_COL0_INDEX 107 +#define IMX_PADMUX_KEY_ROW0_INDEX 108 +#define IMX_PADMUX_KEY_COL1_INDEX 109 +#define IMX_PADMUX_KEY_ROW1_INDEX 110 +#define IMX_PADMUX_KEY_COL2_INDEX 111 +#define IMX_PADMUX_KEY_ROW2_INDEX 112 +#define IMX_PADMUX_KEY_COL3_INDEX 113 +#define IMX_PADMUX_KEY_ROW3_INDEX 114 +#define IMX_PADMUX_KEY_COL4_INDEX 115 +#define IMX_PADMUX_KEY_ROW4_INDEX 116 +#define IMX_PADMUX_GPIO00_INDEX 117 +#define IMX_PADMUX_GPIO01_INDEX 118 +#define IMX_PADMUX_GPIO09_INDEX 119 +#define IMX_PADMUX_GPIO03_INDEX 120 +#define IMX_PADMUX_GPIO06_INDEX 121 +#define IMX_PADMUX_GPIO02_INDEX 122 +#define IMX_PADMUX_GPIO04_INDEX 123 +#define IMX_PADMUX_GPIO05_INDEX 124 +#define IMX_PADMUX_GPIO07_INDEX 125 +#define IMX_PADMUX_GPIO08_INDEX 126 +#define IMX_PADMUX_GPIO16_INDEX 127 +#define IMX_PADMUX_GPIO17_INDEX 128 +#define IMX_PADMUX_GPIO18_INDEX 129 +#define IMX_PADMUX_GPIO19_INDEX 130 +#define IMX_PADMUX_CSI0_PIXCLK_INDEX 131 +#define IMX_PADMUX_CSI0_HSYNC_INDEX 132 +#define IMX_PADMUX_CSI0_DATA_EN_INDEX 133 +#define IMX_PADMUX_CSI0_VSYNC_INDEX 134 +#define IMX_PADMUX_CSI0_DATA04_INDEX 135 +#define IMX_PADMUX_CSI0_DATA05_INDEX 136 +#define IMX_PADMUX_CSI0_DATA06_INDEX 137 +#define IMX_PADMUX_CSI0_DATA07_INDEX 138 +#define IMX_PADMUX_CSI0_DATA08_INDEX 139 +#define IMX_PADMUX_CSI0_DATA09_INDEX 140 +#define IMX_PADMUX_CSI0_DATA10_INDEX 141 +#define IMX_PADMUX_CSI0_DATA11_INDEX 142 +#define IMX_PADMUX_CSI0_DATA12_INDEX 143 +#define IMX_PADMUX_CSI0_DATA13_INDEX 144 +#define IMX_PADMUX_CSI0_DATA14_INDEX 145 +#define IMX_PADMUX_CSI0_DATA15_INDEX 146 +#define IMX_PADMUX_CSI0_DATA16_INDEX 147 +#define IMX_PADMUX_CSI0_DATA17_INDEX 148 +#define IMX_PADMUX_CSI0_DATA18_INDEX 149 +#define IMX_PADMUX_CSI0_DATA19_INDEX 150 +#define IMX_PADMUX_SD3_DATA7_INDEX 151 +#define IMX_PADMUX_SD3_DATA6_INDEX 152 +#define IMX_PADMUX_SD3_DATA5_INDEX 153 +#define IMX_PADMUX_SD3_DATA4_INDEX 154 +#define IMX_PADMUX_SD3_CMD_INDEX 155 +#define IMX_PADMUX_SD3_CLK_INDEX 156 +#define IMX_PADMUX_SD3_DATA0_INDEX 157 +#define IMX_PADMUX_SD3_DATA1_INDEX 158 +#define IMX_PADMUX_SD3_DATA2_INDEX 159 +#define IMX_PADMUX_SD3_DATA3_INDEX 160 +#define IMX_PADMUX_SD3_RESET_INDEX 161 +#define IMX_PADMUX_NAND_CLE_INDEX 162 +#define IMX_PADMUX_NAND_ALE_INDEX 163 +#define IMX_PADMUX_NAND_WP_INDEX 164 +#define IMX_PADMUX_NAND_READY_INDEX 165 +#define IMX_PADMUX_NAND_CS0_INDEX 166 +#define IMX_PADMUX_NAND_CS1_INDEX 167 +#define IMX_PADMUX_NAND_CS2_INDEX 168 +#define IMX_PADMUX_NAND_CS3_INDEX 169 +#define IMX_PADMUX_SD4_CMD_INDEX 170 +#define IMX_PADMUX_SD4_CLK_INDEX 171 +#define IMX_PADMUX_NAND_DATA00_INDEX 172 +#define IMX_PADMUX_NAND_DATA01_INDEX 173 +#define IMX_PADMUX_NAND_DATA02_INDEX 174 +#define IMX_PADMUX_NAND_DATA03_INDEX 175 +#define IMX_PADMUX_NAND_DATA04_INDEX 176 +#define IMX_PADMUX_NAND_DATA05_INDEX 177 +#define IMX_PADMUX_NAND_DATA06_INDEX 178 +#define IMX_PADMUX_NAND_DATA07_INDEX 189 +#define IMX_PADMUX_SD4_DATA0_INDEX 180 +#define IMX_PADMUX_SD4_DATA1_INDEX 181 +#define IMX_PADMUX_SD4_DATA2_INDEX 182 +#define IMX_PADMUX_SD4_DATA3_INDEX 183 +#define IMX_PADMUX_SD4_DATA4_INDEX 184 +#define IMX_PADMUX_SD4_DATA5_INDEX 185 +#define IMX_PADMUX_SD4_DATA6_INDEX 186 +#define IMX_PADMUX_SD4_DATA7_INDEX 187 +#define IMX_PADMUX_SD1_DATA1_INDEX 188 +#define IMX_PADMUX_SD1_DATA0_INDEX 189 +#define IMX_PADMUX_SD1_DATA3_INDEX 190 +#define IMX_PADMUX_SD1_CMD_INDEX 191 +#define IMX_PADMUX_SD1_DATA2_INDEX 192 +#define IMX_PADMUX_SD1_CLK_INDEX 193 +#define IMX_PADMUX_SD2_CLK_INDEX 194 +#define IMX_PADMUX_SD2_CMD_INDEX 195 +#define IMX_PADMUX_SD2_DATA3_INDEX 196 + +#define IMX_PADMUX_NREGISTERS 197 /* Pad Mux Register Offsets */ -#define IMX_PADMUX_OFFSET(n) (0x004c + ((n) << 2)) +#define IMX_PADMUX_OFFSET(n) (0x004c + ((unsigned int)(n) << 2)) #define IMX_PADMUX_SD2_DATA1_OFFSET 0x004c #define IMX_PADMUX_SD2_DATA2_OFFSET 0x0050 @@ -479,6 +481,264 @@ #define IMX_PADMUX_SD2_DATA3_OFFSET 0x035c /* Pad Control Registers */ +/* Pad Mux Register Indices (used by software for table lookups) */ + +#define IMX_PADCTL_SD2_DATA1_INDEX 0 +#define IMX_PADCTL_SD2_DATA2_INDEX 1 +#define IMX_PADCTL_SD2_DATA0_INDEX 2 +#define IMX_PADCTL_RGMII_TXC_INDEX 3 +#define IMX_PADCTL_RGMII_TD0_INDEX 4 +#define IMX_PADCTL_RGMII_TD1_INDEX 5 +#define IMX_PADCTL_RGMII_TD2_INDEX 6 +#define IMX_PADCTL_RGMII_TD3_INDEX 7 +#define IMX_PADCTL_RGMII_RX_CTL_INDEX 8 +#define IMX_PADCTL_RGMII_RD0_INDEX 9 +#define IMX_PADCTL_RGMII_TX_CTL_INDEX 10 +#define IMX_PADCTL_RGMII_RD1_INDEX 11 +#define IMX_PADCTL_RGMII_RD2_INDEX 12 +#define IMX_PADCTL_RGMII_RD3_INDEX 13 +#define IMX_PADCTL_RGMII_RXC_INDEX 14 +#define IMX_PADCTL_EIM_ADDR25_INDEX 15 +#define IMX_PADCTL_EIM_EB2_INDEX 16 +#define IMX_PADCTL_EIM_DATA16_INDEX 17 +#define IMX_PADCTL_EIM_DATA17_INDEX 18 +#define IMX_PADCTL_EIM_DATA18_INDEX 19 +#define IMX_PADCTL_EIM_DATA19_INDEX 20 +#define IMX_PADCTL_EIM_DATA20_INDEX 21 +#define IMX_PADCTL_EIM_DATA21_INDEX 22 +#define IMX_PADCTL_EIM_DATA22_INDEX 23 +#define IMX_PADCTL_EIM_DATA23_INDEX 24 +#define IMX_PADCTL_EIM_EB3_INDEX 25 +#define IMX_PADCTL_EIM_DATA24_INDEX 26 +#define IMX_PADCTL_EIM_DATA25_INDEX 27 +#define IMX_PADCTL_EIM_DATA26_INDEX 28 +#define IMX_PADCTL_EIM_DATA27_INDEX 29 +#define IMX_PADCTL_EIM_DATA28_INDEX 30 +#define IMX_PADCTL_EIM_DATA29_INDEX 31 +#define IMX_PADCTL_EIM_DATA30_INDEX 32 +#define IMX_PADCTL_EIM_DATA31_INDEX 33 +#define IMX_PADCTL_EIM_ADDR24_INDEX 34 +#define IMX_PADCTL_EIM_ADDR23_INDEX 35 +#define IMX_PADCTL_EIM_ADDR22_INDEX 36 +#define IMX_PADCTL_EIM_ADDR21_INDEX 37 +#define IMX_PADCTL_EIM_ADDR20_INDEX 38 +#define IMX_PADCTL_EIM_ADDR19_INDEX 39 +#define IMX_PADCTL_EIM_ADDR18_INDEX 40 +#define IMX_PADCTL_EIM_ADDR17_INDEX 41 +#define IMX_PADCTL_EIM_ADDR16_INDEX 42 +#define IMX_PADCTL_EIM_CS0_INDEX 43 +#define IMX_PADCTL_EIM_CS1_INDEX 44 +#define IMX_PADCTL_EIM_OE_INDEX 45 +#define IMX_PADCTL_EIM_RW_INDEX 46 +#define IMX_PADCTL_EIM_LBA_INDEX 47 +#define IMX_PADCTL_EIM_EB0_INDEX 48 +#define IMX_PADCTL_EIM_EB1_INDEX 49 +#define IMX_PADCTL_EIM_AD00_INDEX 50 +#define IMX_PADCTL_EIM_AD01_INDEX 51 +#define IMX_PADCTL_EIM_AD02_INDEX 52 +#define IMX_PADCTL_EIM_AD03_INDEX 53 +#define IMX_PADCTL_EIM_AD04_INDEX 54 +#define IMX_PADCTL_EIM_AD05_INDEX 55 +#define IMX_PADCTL_EIM_AD06_INDEX 56 +#define IMX_PADCTL_EIM_AD07_INDEX 57 +#define IMX_PADCTL_EIM_AD08_INDEX 58 +#define IMX_PADCTL_EIM_AD09_INDEX 59 +#define IMX_PADCTL_EIM_AD10_INDEX 60 +#define IMX_PADCTL_EIM_AD11_INDEX 61 +#define IMX_PADCTL_EIM_AD12_INDEX 62 +#define IMX_PADCTL_EIM_AD13_INDEX 63 +#define IMX_PADCTL_EIM_AD14_INDEX 64 +#define IMX_PADCTL_EIM_AD15_INDEX 65 +#define IMX_PADCTL_EIM_WAIT_INDEX 66 +#define IMX_PADCTL_EIM_BCLK_INDEX 67 +#define IMX_PADCTL_DI0_DISP_CLK_INDEX 68 +#define IMX_PADCTL_DI0_PIN15_INDEX 69 +#define IMX_PADCTL_DI0_PIN02_INDEX 70 +#define IMX_PADCTL_DI0_PIN03_INDEX 71 +#define IMX_PADCTL_DI0_PIN04_INDEX 72 +#define IMX_PADCTL_DISP0_DATA00_INDEX 73 +#define IMX_PADCTL_DISP0_DATA01_INDEX 74 +#define IMX_PADCTL_DISP0_DATA02_INDEX 75 +#define IMX_PADCTL_DISP0_DATA03_INDEX 76 +#define IMX_PADCTL_DISP0_DATA04_INDEX 77 +#define IMX_PADCTL_DISP0_DATA05_INDEX 78 +#define IMX_PADCTL_DISP0_DATA06_INDEX 79 +#define IMX_PADCTL_DISP0_DATA07_INDEX 80 +#define IMX_PADCTL_DISP0_DATA08_INDEX 81 +#define IMX_PADCTL_DISP0_DATA09_INDEX 82 +#define IMX_PADCTL_DISP0_DATA10_INDEX 83 +#define IMX_PADCTL_DISP0_DATA11_INDEX 84 +#define IMX_PADCTL_DISP0_DATA12_INDEX 85 +#define IMX_PADCTL_DISP0_DATA13_INDEX 86 +#define IMX_PADCTL_DISP0_DATA14_INDEX 87 +#define IMX_PADCTL_DISP0_DATA15_INDEX 88 +#define IMX_PADCTL_DISP0_DATA16_INDEX 89 +#define IMX_PADCTL_DISP0_DATA17_INDEX 90 +#define IMX_PADCTL_DISP0_DATA18_INDEX 91 +#define IMX_PADCTL_DISP0_DATA19_INDEX 92 +#define IMX_PADCTL_DISP0_DATA20_INDEX 93 +#define IMX_PADCTL_DISP0_DATA21_INDEX 94 +#define IMX_PADCTL_DISP0_DATA22_INDEX 95 +#define IMX_PADCTL_DISP0_DATA23_INDEX 96 +#define IMX_PADCTL_ENET_MDIO_INDEX 97 +#define IMX_PADCTL_ENET_REF_CLK_INDEX 98 +#define IMX_PADCTL_ENET_RX_ER_INDEX 99 +#define IMX_PADCTL_ENET_CRS_DV_INDEX 100 +#define IMX_PADCTL_ENET_RX_DATA1_INDEX 101 +#define IMX_PADCTL_ENET_RX_DATA0_INDEX 102 +#define IMX_PADCTL_ENET_TX_EN_INDEX 103 +#define IMX_PADCTL_ENET_TX_DATA1_INDEX 104 +#define IMX_PADCTL_ENET_TX_DATA0_INDEX 105 +#define IMX_PADCTL_ENET_MDC_INDEX 106 +#define IMX_PADCTL_DRAM_SDQS5_P_INDEX 107 +#define IMX_PADCTL_DRAM_DQM5_INDEX 108 +#define IMX_PADCTL_DRAM_DQM4_INDEX 109 +#define IMX_PADCTL_DRAM_SDQS4_P_INDEX 110 +#define IMX_PADCTL_DRAM_SDQS3_P_INDEX 111 +#define IMX_PADCTL_DRAM_DQM3_INDEX 112 +#define IMX_PADCTL_DRAM_SDQS2_P_INDEX 113 +#define IMX_PADCTL_DRAM_DQM2_INDEX 114 +#define IMX_PADCTL_DRAM_ADDR00_INDEX 115 +#define IMX_PADCTL_DRAM_ADDR01_INDEX 116 +#define IMX_PADCTL_DRAM_ADDR02_INDEX 117 +#define IMX_PADCTL_DRAM_ADDR03_INDEX 118 +#define IMX_PADCTL_DRAM_ADDR04_INDEX 119 +#define IMX_PADCTL_DRAM_ADDR05_INDEX 120 +#define IMX_PADCTL_DRAM_ADDR06_INDEX 121 +#define IMX_PADCTL_DRAM_ADDR07_INDEX 122 +#define IMX_PADCTL_DRAM_ADDR08_INDEX 123 +#define IMX_PADCTL_DRAM_ADDR09_INDEX 124 +#define IMX_PADCTL_DRAM_ADDR10_INDEX 125 +#define IMX_PADCTL_DRAM_ADDR11_INDEX 126 +#define IMX_PADCTL_DRAM_ADDR12_INDEX 127 +#define IMX_PADCTL_DRAM_ADDR13_INDEX 128 +#define IMX_PADCTL_DRAM_ADDR14_INDEX 129 +#define IMX_PADCTL_DRAM_ADDR15_INDEX 130 +#define IMX_PADCTL_DRAM_CAS_INDEX 131 +#define IMX_PADCTL_DRAM_CS0_INDEX 132 +#define IMX_PADCTL_DRAM_CS1_INDEX 133 +#define IMX_PADCTL_DRAM_RAS_INDEX 134 +#define IMX_PADCTL_DRAM_RESET_INDEX 135 +#define IMX_PADCTL_DRAM_SDBA0_INDEX 136 +#define IMX_PADCTL_DRAM_SDBA1_INDEX 137 +#define IMX_PADCTL_DRAM_SDCLK0_P_INDEX 138 +#define IMX_PADCTL_DRAM_SDBA2_INDEX 149 +#define IMX_PADCTL_DRAM_SDCKE0_INDEX 140 +#define IMX_PADCTL_DRAM_SDCLK1_P_INDEX 141 +#define IMX_PADCTL_DRAM_SDCKE1_INDEX 142 +#define IMX_PADCTL_DRAM_ODT0_INDEX 143 +#define IMX_PADCTL_DRAM_ODT1_INDEX 144 +#define IMX_PADCTL_DRAM_SDWE_B_INDEX 145 +#define IMX_PADCTL_DRAM_SDQS0_P_INDEX 146 +#define IMX_PADCTL_DRAM_DQM0_INDEX 147 +#define IMX_PADCTL_DRAM_SDQS1_P_INDEX 148 +#define IMX_PADCTL_DRAM_DQM1_INDEX 149 +#define IMX_PADCTL_DRAM_SDQS6_P_INDEX 150 +#define IMX_PADCTL_DRAM_DQM6_INDEX 151 +#define IMX_PADCTL_DRAM_SDQS7_P_INDEX 152 +#define IMX_PADCTL_DRAM_DQM7_INDEX 153 +#define IMX_PADCTL_KEY_COL0_INDEX 154 +#define IMX_PADCTL_KEY_ROW0_INDEX 155 +#define IMX_PADCTL_KEY_COL1_INDEX 156 +#define IMX_PADCTL_KEY_ROW1_INDEX 157 +#define IMX_PADCTL_KEY_COL2_INDEX 158 +#define IMX_PADCTL_KEY_ROW2_INDEX 159 +#define IMX_PADCTL_KEY_COL3_INDEX 160 +#define IMX_PADCTL_KEY_ROW3_INDEX 161 +#define IMX_PADCTL_KEY_COL4_INDEX 162 +#define IMX_PADCTL_KEY_ROW4_INDEX 163 +#define IMX_PADCTL_GPIO00_INDEX 164 +#define IMX_PADCTL_GPIO01_INDEX 165 +#define IMX_PADCTL_GPIO09_INDEX 166 +#define IMX_PADCTL_GPIO03_INDEX 167 +#define IMX_PADCTL_GPIO06_INDEX 168 +#define IMX_PADCTL_GPIO02_INDEX 169 +#define IMX_PADCTL_GPIO04_INDEX 170 +#define IMX_PADCTL_GPIO05_INDEX 171 +#define IMX_PADCTL_GPIO07_INDEX 172 +#define IMX_PADCTL_GPIO08_INDEX 173 +#define IMX_PADCTL_GPIO16_INDEX 174 +#define IMX_PADCTL_GPIO17_INDEX 175 +#define IMX_PADCTL_GPIO18_INDEX 176 +#define IMX_PADCTL_GPIO19_INDEX 177 +#define IMX_PADCTL_CSI0_PIXCLK_INDEX 178 +#define IMX_PADCTL_CSI0_HSYNC_INDEX 179 +#define IMX_PADCTL_CSI0_DATA_EN_INDEX 180 +#define IMX_PADCTL_CSI0_VSYNC_INDEX 181 +#define IMX_PADCTL_CSI0_DATA04_INDEX 182 +#define IMX_PADCTL_CSI0_DATA05_INDEX 183 +#define IMX_PADCTL_CSI0_DATA06_INDEX 184 +#define IMX_PADCTL_CSI0_DATA07_INDEX 185 +#define IMX_PADCTL_CSI0_DATA08_INDEX 186 +#define IMX_PADCTL_CSI0_DATA09_INDEX 187 +#define IMX_PADCTL_CSI0_DATA10_INDEX 188 +#define IMX_PADCTL_CSI0_DATA11_INDEX 189 +#define IMX_PADCTL_CSI0_DATA12_INDEX 190 +#define IMX_PADCTL_CSI0_DATA13_INDEX 191 +#define IMX_PADCTL_CSI0_DATA14_INDEX 192 +#define IMX_PADCTL_CSI0_DATA15_INDEX 193 +#define IMX_PADCTL_CSI0_DATA16_INDEX 194 +#define IMX_PADCTL_CSI0_DATA17_INDEX 195 +#define IMX_PADCTL_CSI0_DATA18_INDEX 196 +#define IMX_PADCTL_CSI0_DATA19_INDEX 197 +#define IMX_PADCTL_JTAG_TMS_INDEX 198 +#define IMX_PADCTL_JTAG_MOD_INDEX 199 +#define IMX_PADCTL_JTAG_TRSTB_INDEX 200 +#define IMX_PADCTL_JTAG_TDI_INDEX 201 +#define IMX_PADCTL_JTAG_TCK_INDEX 202 +#define IMX_PADCTL_JTAG_TDO_INDEX 203 +#define IMX_PADCTL_SD3_DATA7_INDEX 204 +#define IMX_PADCTL_SD3_DATA6_INDEX 205 +#define IMX_PADCTL_SD3_DATA5_INDEX 206 +#define IMX_PADCTL_SD3_DATA4_INDEX 207 +#define IMX_PADCTL_SD3_CMD_INDEX 208 +#define IMX_PADCTL_SD3_CLK_INDEX 209 +#define IMX_PADCTL_SD3_DATA0_INDEX 210 +#define IMX_PADCTL_SD3_DATA1_INDEX 211 +#define IMX_PADCTL_SD3_DATA2_INDEX 212 +#define IMX_PADCTL_SD3_DATA3_INDEX 213 +#define IMX_PADCTL_SD3_RESET_INDEX 214 +#define IMX_PADCTL_NAND_CLE_INDEX 215 +#define IMX_PADCTL_NAND_ALE_INDEX 216 +#define IMX_PADCTL_NAND_WP_INDEX 217 +#define IMX_PADCTL_NAND_READY_INDEX 218 +#define IMX_PADCTL_NAND_CS0_INDEX 219 +#define IMX_PADCTL_NAND_CS1_INDEX 220 +#define IMX_PADCTL_NAND_CS2_INDEX 221 +#define IMX_PADCTL_NAND_CS3_INDEX 222 +#define IMX_PADCTL_SD4_CMD_INDEX 223 +#define IMX_PADCTL_SD4_CLK_INDEX 224 +#define IMX_PADCTL_NAND_DATA00_INDEX 225 +#define IMX_PADCTL_NAND_DATA01_INDEX 226 +#define IMX_PADCTL_NAND_DATA02_INDEX 227 +#define IMX_PADCTL_NAND_DATA03_INDEX 228 +#define IMX_PADCTL_NAND_DATA04_INDEX 229 +#define IMX_PADCTL_NAND_DATA05_INDEX 230 +#define IMX_PADCTL_NAND_DATA06_INDEX 231 +#define IMX_PADCTL_NAND_DATA07_INDEX 232 +#define IMX_PADCTL_SD4_DATA0_INDEX 233 +#define IMX_PADCTL_SD4_DATA1_INDEX 234 +#define IMX_PADCTL_SD4_DATA2_INDEX 235 +#define IMX_PADCTL_SD4_DATA3_INDEX 236 +#define IMX_PADCTL_SD4_DATA4_INDEX 237 +#define IMX_PADCTL_SD4_DATA5_INDEX 238 +#define IMX_PADCTL_SD4_DATA6_INDEX 239 +#define IMX_PADCTL_SD4_DATA7_INDEX 240 +#define IMX_PADCTL_SD1_DATA1_INDEX 241 +#define IMX_PADCTL_SD1_DATA0_INDEX 242 +#define IMX_PADCTL_SD1_DATA3_INDEX 243 +#define IMX_PADCTL_SD1_CMD_INDEX 244 +#define IMX_PADCTL_SD1_DATA2_INDEX 245 +#define IMX_PADCTL_SD1_CLK_INDEX 246 +#define IMX_PADCTL_SD2_CLK_INDEX 247 +#define IMX_PADCTL_SD2_CMD_INDEX 248 +#define IMX_PADCTL_SD2_DATA3_INDEX 249 + +#define IMX_PADCTL_NREGISTERS 250 + +/* Pad Control Register Offsets */ + +#define IMX_PADCTL_OFFSET(n) (0x0360 + ((unsigned int)(n) << 2)) #define IMX_PADCTL_SD2_DATA1_OFFSET 0x0360 #define IMX_PADCTL_SD2_DATA2_OFFSET 0x0364 @@ -886,7 +1146,7 @@ /* Pad Mux Registers */ -#define IMX_PADMUX_ADDRESS(n) (IMX_IOMUXC_VBASE+IMX_PADCTL_OFFSET(n)) +#define IMX_PADMUX_ADDRESS(n) (IMX_IOMUXC_VBASE+IMX_PADMUX_OFFSET(n)) #define IMX_PADMUX_SD2_DATA1 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD2_DATA1_OFFSET) #define IMX_PADMUX_SD2_DATA2 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD2_DATA2_OFFSET) @@ -1088,6 +1348,8 @@ /* Pad Control Registers */ +#define IMX_PADCTL_ADDRESS(n) (IMX_IOMUXC_VBASE+IMX_PADCTL_OFFSET(n)) + #define IMX_PADCTL_SD2_DATA1 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD2_DATA1_OFFSET) #define IMX_PADCTL_SD2_DATA2 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD2_DATA2_OFFSET) #define IMX_PADCTL_SD2_DATA0 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD2_DATA0_OFFSET) diff --git a/arch/arm/src/imx6/imx_gpio.c b/arch/arm/src/imx6/imx_gpio.c index 1fe7a65ea79..c1d2175924f 100644 --- a/arch/arm/src/imx6/imx_gpio.c +++ b/arch/arm/src/imx6/imx_gpio.c @@ -41,13 +41,310 @@ #include #include +#include #include #include "chip.h" #include "up_arch.h" +#include "imx_iomuxc.h" #include "imx_gpio.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IMX_PADMUX_INVALID 255 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint8_t g_gpio1_padmux[IMX_GPIO_NPINS] = +{ + IMX_PADMUX_GPIO00_INDEX, /* GPIO1 Pin 0 */ + IMX_PADMUX_GPIO01_INDEX, /* GPIO1 Pin 1 */ + IMX_PADMUX_GPIO02_INDEX, /* GPIO1 Pin 2 */ + IMX_PADMUX_GPIO03_INDEX, /* GPIO1 Pin 3 */ + IMX_PADMUX_GPIO04_INDEX, /* GPIO1 Pin 4 */ + IMX_PADMUX_GPIO05_INDEX, /* GPIO1 Pin 5 */ + IMX_PADMUX_GPIO06_INDEX, /* GPIO1 Pin 6 */ + IMX_PADMUX_GPIO07_INDEX, /* GPIO1 Pin 7 */ + + IMX_PADMUX_GPIO08_INDEX, /* GPIO1 Pin 8 */ + IMX_PADMUX_GPIO09_INDEX, /* GPIO1 Pin 9 */ + IMX_PADMUX_SD2_CLK_INDEX, /* GPIO1 Pin 10 */ + IMX_PADMUX_SD2_CMD_INDEX, /* GPIO1 Pin 11 */ + IMX_PADMUX_SD2_DATA3_INDEX, /* GPIO1 Pin 12 */ + IMX_PADMUX_SD2_DATA2_INDEX, /* GPIO1 Pin 13 */ + IMX_PADMUX_SD2_DATA1_INDEX, /* GPIO1 Pin 14 */ + IMX_PADMUX_SD2_DATA0_INDEX, /* GPIO1 Pin 15 */ + + IMX_PADMUX_SD1_DATA0_INDEX, /* GPIO1 Pin 16 */ + IMX_PADMUX_SD1_DATA1_INDEX, /* GPIO1 Pin 17 */ + IMX_PADMUX_SD1_CMD_INDEX, /* GPIO1 Pin 18 */ + IMX_PADMUX_SD1_DATA2_INDEX, /* GPIO1 Pin 19 */ + IMX_PADMUX_SD1_CLK_INDEX, /* GPIO1 Pin 20 */ + IMX_PADMUX_SD1_DATA3_INDEX, /* GPIO1 Pin 21 */ + IMX_PADMUX_ENET_MDIO_INDEX, /* GPIO1 Pin 22 */ + IMX_PADMUX_ENET_REF_CLK_INDEX, /* GPIO1 Pin 23 */ + + IMX_PADMUX_ENET_RX_ER_INDEX, /* GPIO1 Pin 24 */ + IMX_PADMUX_ENET_CRS_DV_INDEX, /* GPIO1 Pin 25 */ + IMX_PADMUX_ENET_RX_DATA1_INDEX, /* GPIO1 Pin 26 */ + IMX_PADMUX_ENET_RX_DATA0_INDEX, /* GPIO1 Pin 27 */ + IMX_PADMUX_ENET_TX_EN_INDEX, /* GPIO1 Pin 28 */ + IMX_PADMUX_ENET_TX_DATA1_INDEX, /* GPIO1 Pin 29 */ + IMX_PADMUX_ENET_TX_DATA0_INDEX, /* GPIO1 Pin 30 */ + IMX_PADMUX_ENET_MDC_INDEX /* GPIO1 Pin 31 */ +}; + +static const uint8_t g_gpio2_padmux[IMX_GPIO_NPINS] = +{ + IMX_PADMUX_NAND_DATA00_INDEX, /* GPIO2 Pin 0 */ + IMX_PADMUX_NAND_DATA01_INDEX, /* GPIO2 Pin 1 */ + IMX_PADMUX_NAND_DATA02_INDEX, /* GPIO2 Pin 2 */ + IMX_PADMUX_NAND_DATA03_INDEX, /* GPIO2 Pin 3 */ + IMX_PADMUX_NAND_DATA04_INDEX, /* GPIO2 Pin 4 */ + IMX_PADMUX_NAND_DATA05_INDEX, /* GPIO2 Pin 5 */ + IMX_PADMUX_NAND_DATA06_INDEX, /* GPIO2 Pin 6 */ + IMX_PADMUX_NAND_DATA07_INDEX, /* GPIO2 Pin 7 */ + + IMX_PADMUX_SD4_DATA0_INDEX, /* GPIO2 Pin 8 */ + IMX_PADMUX_SD4_DATA1_INDEX, /* GPIO2 Pin 9 */ + IMX_PADMUX_SD4_DATA2_INDEX, /* GPIO2 Pin 10 */ + IMX_PADMUX_SD4_DATA3_INDEX, /* GPIO2 Pin 11 */ + IMX_PADMUX_SD4_DATA4_INDEX, /* GPIO2 Pin 12 */ + IMX_PADMUX_SD4_DATA5_INDEX, /* GPIO2 Pin 13 */ + IMX_PADMUX_SD4_DATA6_INDEX, /* GPIO2 Pin 14 */ + IMX_PADMUX_SD4_DATA7_INDEX, /* GPIO2 Pin 15 */ + + IMX_PADMUX_EIM_ADDR22_INDEX, /* GPIO2 Pin 16 */ + IMX_PADMUX_EIM_ADDR21_INDEX, /* GPIO2 Pin 17 */ + IMX_PADMUX_EIM_ADDR20_INDEX, /* GPIO2 Pin 18 */ + IMX_PADMUX_EIM_ADDR19_INDEX, /* GPIO2 Pin 19 */ + IMX_PADMUX_EIM_ADDR18_INDEX, /* GPIO2 Pin 20 */ + IMX_PADMUX_EIM_ADDR17_INDEX, /* GPIO2 Pin 21 */ + IMX_PADMUX_EIM_ADDR16_INDEX, /* GPIO2 Pin 22 */ + IMX_PADMUX_EIM_CS0_INDEX, /* GPIO2 Pin 23 */ + + IMX_PADMUX_EIM_CS1_INDEX, /* GPIO2 Pin 24 */ + IMX_PADMUX_EIM_OE_INDEX, /* GPIO2 Pin 25 */ + IMX_PADMUX_EIM_RW_INDEX, /* GPIO2 Pin 26 */ + IMX_PADMUX_EIM_LBA_INDEX, /* GPIO2 Pin 27 */ + IMX_PADMUX_EIM_EB0_INDEX, /* GPIO2 Pin 28 */ + IMX_PADMUX_EIM_EB1_INDEX, /* GPIO2 Pin 29 */ + IMX_PADMUX_EIM_EB2_INDEX, /* GPIO2 Pin 30 */ + IMX_PADMUX_EIM_EB3_INDEX, /* GPIO2 Pin 31 */ +}; + +static const uint8_t g_gpio3_padmux[IMX_GPIO_NPINS] = +{ + IMX_PADMUX_EIM_AD00_INDEX, /* GPIO3 Pin 0 */ + IMX_PADMUX_EIM_AD01_INDEX, /* GPIO3 Pin 1 */ + IMX_PADMUX_EIM_AD02_INDEX, /* GPIO3 Pin 2 */ + IMX_PADMUX_EIM_AD03_INDEX, /* GPIO3 Pin 3 */ + IMX_PADMUX_EIM_AD04_INDEX, /* GPIO3 Pin 4 */ + IMX_PADMUX_EIM_AD05_INDEX, /* GPIO3 Pin 5 */ + IMX_PADMUX_EIM_AD06_INDEX, /* GPIO3 Pin 6 */ + IMX_PADMUX_EIM_AD07_INDEX, /* GPIO3 Pin 7 */ + + IMX_PADMUX_EIM_AD08_INDEX, /* GPIO3 Pin 8 */ + IMX_PADMUX_EIM_AD09_INDEX, /* GPIO3 Pin 9 */ + IMX_PADMUX_EIM_AD10_INDEX, /* GPIO3 Pin 10 */ + IMX_PADMUX_EIM_AD11_INDEX, /* GPIO3 Pin 11 */ + IMX_PADMUX_EIM_AD12_INDEX, /* GPIO3 Pin 12 */ + IMX_PADMUX_EIM_AD13_INDEX, /* GPIO3 Pin 13 */ + IMX_PADMUX_EIM_AD14_INDEX, /* GPIO3 Pin 14 */ + IMX_PADMUX_EIM_AD15_INDEX, /* GPIO3 Pin 15 */ + + IMX_PADMUX_EIM_DATA16_INDEX, /* GPIO3 Pin 16 */ + IMX_PADMUX_EIM_DATA17_INDEX, /* GPIO3 Pin 17 */ + IMX_PADMUX_EIM_DATA18_INDEX, /* GPIO3 Pin 18 */ + IMX_PADMUX_EIM_DATA19_INDEX, /* GPIO3 Pin 19 */ + IMX_PADMUX_EIM_DATA20_INDEX, /* GPIO3 Pin 20 */ + IMX_PADMUX_EIM_DATA21_INDEX, /* GPIO3 Pin 21 */ + IMX_PADMUX_EIM_DATA22_INDEX, /* GPIO3 Pin 22 */ + IMX_PADMUX_EIM_DATA23_INDEX, /* GPIO3 Pin 23 */ + + IMX_PADMUX_EIM_DATA24_INDEX, /* GPIO3 Pin 24 */ + IMX_PADMUX_EIM_DATA25_INDEX, /* GPIO3 Pin 25 */ + IMX_PADMUX_EIM_DATA26_INDEX, /* GPIO3 Pin 26 */ + IMX_PADMUX_EIM_DATA27_INDEX, /* GPIO3 Pin 27 */ + IMX_PADMUX_EIM_DATA28_INDEX, /* GPIO3 Pin 28 */ + IMX_PADMUX_EIM_DATA29_INDEX, /* GPIO3 Pin 29 */ + IMX_PADMUX_EIM_DATA30_INDEX, /* GPIO3 Pin 30 */ + IMX_PADMUX_EIM_DATA31_INDEX, /* GPIO3 Pin 31 */ +}; + +static const uint8_t g_gpio4_padmux[IMX_GPIO_NPINS] = +{ + IMX_PADMUX_INVALID, /* GPIO4 Pin 0 */ + IMX_PADMUX_INVALID, /* GPIO4 Pin 1 */ + IMX_PADMUX_INVALID, /* GPIO4 Pin 2 */ + IMX_PADMUX_INVALID, /* GPIO4 Pin 3 */ + IMX_PADMUX_INVALID, /* GPIO4 Pin 4 */ + IMX_PADMUX_GPIO19_INDEX, /* GPIO4 Pin 5 */ + IMX_PADMUX_KEY_COL0_INDEX, /* GPIO4 Pin 6 */ + IMX_PADMUX_KEY_ROW0_INDEX, /* GPIO4 Pin 7 */ + + IMX_PADMUX_KEY_COL1_INDEX, /* GPIO4 Pin 8 */ + IMX_PADMUX_KEY_ROW1_INDEX, /* GPIO4 Pin 9 */ + IMX_PADMUX_KEY_COL2_INDEX, /* GPIO4 Pin 10 */ + IMX_PADMUX_KEY_ROW2_INDEX, /* GPIO4 Pin 11 */ + IMX_PADMUX_KEY_COL3_INDEX, /* GPIO4 Pin 12 */ + IMX_PADMUX_KEY_ROW3_INDEX, /* GPIO4 Pin 13 */ + IMX_PADMUX_KEY_COL4_INDEX, /* GPIO4 Pin 14 */ + IMX_PADMUX_KEY_ROW4_INDEX, /* GPIO4 Pin 15 */ + + IMX_PADMUX_DI0_DISP_CLK_INDEX, /* GPIO4 Pin 16 */ + IMX_PADMUX_DI0_PIN15_INDEX, /* GPIO4 Pin 17 */ + IMX_PADMUX_DI0_PIN02_INDEX, /* GPIO4 Pin 18 */ + IMX_PADMUX_DI0_PIN03_INDEX, /* GPIO4 Pin 19 */ + IMX_PADMUX_DI0_PIN04_INDEX, /* GPIO4 Pin 20 */ + IMX_PADMUX_DISP0_DATA00_INDEX, /* GPIO4 Pin 21 */ + IMX_PADMUX_DISP0_DATA01_INDEX, /* GPIO4 Pin 22 */ + IMX_PADMUX_DISP0_DATA02_INDEX, /* GPIO4 Pin 23 */ + + IMX_PADMUX_DISP0_DATA03_INDEX, /* GPIO4 Pin 24 */ + IMX_PADMUX_DISP0_DATA04_INDEX, /* GPIO4 Pin 25 */ + IMX_PADMUX_DISP0_DATA05_INDEX, /* GPIO4 Pin 26 */ + IMX_PADMUX_DISP0_DATA06_INDEX, /* GPIO4 Pin 27 */ + IMX_PADMUX_DISP0_DATA07_INDEX, /* GPIO4 Pin 28 */ + IMX_PADMUX_DISP0_DATA08_INDEX, /* GPIO4 Pin 29 */ + IMX_PADMUX_DISP0_DATA09_INDEX, /* GPIO4 Pin 30 */ + IMX_PADMUX_DISP0_DATA10_INDEX, /* GPIO4 Pin 31 */ +}; + +static const uint8_t g_gpio5_padmux[IMX_GPIO_NPINS] = +{ + IMX_PADMUX_EIM_WAIT_INDEX, /* GPIO5 Pin 0 */ + IMX_PADMUX_INVALID, /* GPIO5 Pin 1 */ + IMX_PADMUX_EIM_ADDR25_INDEX, /* GPIO5 Pin 2 */ + IMX_PADMUX_INVALID, /* GPIO5 Pin 3 */ + IMX_PADMUX_EIM_ADDR24_INDEX, /* GPIO5 Pin 4 */ + IMX_PADMUX_DISP0_DATA11_INDEX, /* GPIO5 Pin 5 */ + IMX_PADMUX_DISP0_DATA12_INDEX, /* GPIO5 Pin 6 */ + IMX_PADMUX_DISP0_DATA13_INDEX, /* GPIO5 Pin 7 */ + + IMX_PADMUX_DISP0_DATA14_INDEX, /* GPIO5 Pin 8 */ + IMX_PADMUX_DISP0_DATA15_INDEX, /* GPIO5 Pin 9 */ + IMX_PADMUX_DISP0_DATA16_INDEX, /* GPIO5 Pin 10 */ + IMX_PADMUX_DISP0_DATA17_INDEX, /* GPIO5 Pin 11 */ + IMX_PADMUX_DISP0_DATA18_INDEX, /* GPIO5 Pin 12 */ + IMX_PADMUX_DISP0_DATA19_INDEX, /* GPIO5 Pin 13 */ + IMX_PADMUX_DISP0_DATA20_INDEX, /* GPIO5 Pin 14 */ + IMX_PADMUX_DISP0_DATA21_INDEX, /* GPIO5 Pin 15 */ + + IMX_PADMUX_DISP0_DATA22_INDEX, /* GPIO5 Pin 16 */ + IMX_PADMUX_DISP0_DATA23_INDEX, /* GPIO5 Pin 17 */ + IMX_PADMUX_CSI0_PIXCLK_INDEX, /* GPIO5 Pin 18 */ + IMX_PADMUX_CSI0_HSYNC_INDEX, /* GPIO5 Pin 19 */ + IMX_PADMUX_CSI0_DATA_EN_INDEX, /* GPIO5 Pin 20 */ + IMX_PADMUX_CSI0_VSYNC_INDEX, /* GPIO5 Pin 21 */ + IMX_PADMUX_CSI0_DATA04_INDEX, /* GPIO5 Pin 22 */ + IMX_PADMUX_CSI0_DATA05_INDEX, /* GPIO5 Pin 23 */ + + IMX_PADMUX_CSI0_DATA06_INDEX, /* GPIO5 Pin 24 */ + IMX_PADMUX_CSI0_DATA07_INDEX, /* GPIO5 Pin 25 */ + IMX_PADMUX_CSI0_DATA08_INDEX, /* GPIO5 Pin 26 */ + IMX_PADMUX_CSI0_DATA09_INDEX, /* GPIO5 Pin 27 */ + IMX_PADMUX_CSI0_DATA10_INDEX, /* GPIO5 Pin 28 */ + IMX_PADMUX_CSI0_DATA11_INDEX, /* GPIO5 Pin 29 */ + IMX_PADMUX_CSI0_DATA12_INDEX, /* GPIO5 Pin 30 */ + IMX_PADMUX_CSI0_DATA13_INDEX, /* GPIO5 Pin 31 */ +}; + +static const uint8_t g_gpio6_padmux[IMX_GPIO_NPINS] = +{ + IMX_PADMUX_CSI0_DATA14_INDEX, /* GPIO6 Pin 0 */ + IMX_PADMUX_CSI0_DATA15_INDEX, /* GPIO6 Pin 1 */ + IMX_PADMUX_CSI0_DATA16_INDEX, /* GPIO6 Pin 2 */ + IMX_PADMUX_CSI0_DATA17_INDEX, /* GPIO6 Pin 3 */ + IMX_PADMUX_CSI0_DATA18_INDEX, /* GPIO6 Pin 4 */ + IMX_PADMUX_CSI0_DATA19_INDEX, /* GPIO6 Pin 5 */ + IMX_PADMUX_EIM_ADDR23_INDEX, /* GPIO6 Pin 6 */ + IMX_PADMUX_NAND_CLE_INDEX, /* GPIO6 Pin 7 */ + + IMX_PADMUX_NAND_ALE_INDEX, /* GPIO6 Pin 8 */ + IMX_PADMUX_NAND_WP_INDEX, /* GPIO6 Pin 9 */ + IMX_PADMUX_NAND_READY_INDEX, /* GPIO6 Pin 10 */ + IMX_PADMUX_NAND_CS0_INDEX, /* GPIO6 Pin 11 */ + IMX_PADMUX_INVALID, /* GPIO6 Pin 12 */ + IMX_PADMUX_INVALID, /* GPIO6 Pin 13 */ + IMX_PADMUX_NAND_CS1_INDEX, /* GPIO6 Pin 14 */ + IMX_PADMUX_NAND_CS2_INDEX, /* GPIO6 Pin 15 */ + + IMX_PADMUX_NAND_CS3_INDEX, /* GPIO6 Pin 16 */ + IMX_PADMUX_SD3_DATA7_INDEX, /* GPIO6 Pin 17 */ + IMX_PADMUX_SD3_DATA6_INDEX, /* GPIO6 Pin 18 */ + IMX_PADMUX_RGMII_TXC_INDEX, /* GPIO6 Pin 19 */ + IMX_PADMUX_RGMII_TD0_INDEX, /* GPIO6 Pin 20 */ + IMX_PADMUX_RGMII_TD1_INDEX, /* GPIO6 Pin 21 */ + IMX_PADMUX_RGMII_TD2_INDEX, /* GPIO6 Pin 22 */ + IMX_PADMUX_RGMII_TD3_INDEX, /* GPIO6 Pin 23 */ + + IMX_PADMUX_RGMII_RX_CTL_INDEX, /* GPIO6 Pin 24 */ + IMX_PADMUX_RGMII_RD0_INDEX, /* GPIO6 Pin 25 */ + IMX_PADMUX_RGMII_TX_CTL_INDEX, /* GPIO6 Pin 26 */ + IMX_PADMUX_RGMII_RD1_INDEX, /* GPIO6 Pin 27 */ + IMX_PADMUX_RGMII_RD2_INDEX, /* GPIO6 Pin 28 */ + IMX_PADMUX_RGMII_RD3_INDEX, /* GPIO6 Pin 29 */ + IMX_PADMUX_RGMII_RXC_INDEX, /* GPIO6 Pin 30 */ + IMX_PADMUX_EIM_BCLK_INDEX, /* GPIO6 Pin 31 */ +}; + +static const uint8_t g_gpio7_padmux[IMX_GPIO_NPINS] = +{ + IMX_PADMUX_SD3_DATA5_INDEX, /* GPIO7 Pin 0 */ + IMX_PADMUX_SD3_DATA4_INDEX, /* GPIO7 Pin 1 */ + IMX_PADMUX_SD3_CMD_INDEX, /* GPIO7 Pin 2 */ + IMX_PADMUX_SD3_CLK_INDEX, /* GPIO7 Pin 3 */ + IMX_PADMUX_SD3_DATA0_INDEX, /* GPIO7 Pin 4 */ + IMX_PADMUX_SD3_DATA1_INDEX, /* GPIO7 Pin 5 */ + IMX_PADMUX_SD3_DATA2_INDEX, /* GPIO7 Pin 6 */ + IMX_PADMUX_SD3_DATA3_INDEX, /* GPIO7 Pin 7 */ + + IMX_PADMUX_SD3_RESET_INDEX, /* GPIO7 Pin 8 */ + IMX_PADMUX_SD4_CMD_INDEX, /* GPIO7 Pin 9 */ + IMX_PADMUX_SD4_CLK_INDEX, /* GPIO7 Pin 10 */ + IMX_PADMUX_GPIO16_INDEX, /* GPIO7 Pin 11 */ + IMX_PADMUX_GPIO17_INDEX, /* GPIO7 Pin 12 */ + IMX_PADMUX_GPIO18_INDEX, /* GPIO7 Pin 13 */ + IMX_PADMUX_INVALID, /* GPIO7 Pin 14 */ + IMX_PADMUX_INVALID, /* GPIO7 Pin 15 */ + + IMX_PADMUX_INVALID, /* GPIO6 Pin 16 */ + IMX_PADMUX_INVALID, /* GPIO6 Pin 17 */ + IMX_PADMUX_INVALID, /* GPIO6 Pin 18 */ + IMX_PADMUX_INVALID, /* GPIO6 Pin 19 */ + IMX_PADMUX_INVALID, /* GPIO6 Pin 20 */ + IMX_PADMUX_INVALID, /* GPIO6 Pin 21 */ + IMX_PADMUX_INVALID, /* GPIO6 Pin 22 */ + IMX_PADMUX_INVALID, /* GPIO6 Pin 23 */ + + IMX_PADMUX_INVALID, /* GPIO6 Pin 24 */ + IMX_PADMUX_INVALID, /* GPIO6 Pin 25 */ + IMX_PADMUX_INVALID, /* GPIO6 Pin 26 */ + IMX_PADMUX_INVALID, /* GPIO6 Pin 27 */ + IMX_PADMUX_INVALID, /* GPIO6 Pin 28 */ + IMX_PADMUX_INVALID, /* GPIO6 Pin 29 */ + IMX_PADMUX_INVALID, /* GPIO6 Pin 30 */ + IMX_PADMUX_INVALID, /* GPIO6 Pin 31 */ +}; + +static FAR const uint8_t *g_gpio_padmux[IMX_GPIO_NPORTS+1] = +{ + g_gpio1_padmux, /* GPIO1 */ + g_gpio2_padmux, /* GPIO2 */ + g_gpio3_padmux, /* GPIO3 */ + g_gpio4_padmux, /* GPIO4 */ + g_gpio5_padmux, /* GPIO5 */ + g_gpio6_padmux, /* GPIO6 */ + g_gpio7_padmux, /* GPIO7 */ + NULL /* GPIO8 */ +}; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -115,12 +412,30 @@ static inline bool imx_gpio_getinput(int port, int pin) static inline int imx_gpio_configinput(gpio_pinset_t pinset, int port, int pin) { + FAR const uint8_t *table; + uintptr_t regaddr; + unsigned int index; + /* Configure pin as in input */ imx_gpio_dirin(port, pin); /* Configure pin as a GPIO */ -#warning Missing logic + + table = g_gpio_padmux[port]; + if (table == NULL) + { + return -EINVAL; + } + + index = table[pin]; + if (index >= IMX_PADMUX_NREGISTERS) + { + return -EINVAL; + } + + regaddr = IMX_PADMUX_ADDRESS(index); + putreg32(PADMUX_MUXMODE_ALT5, regaddr); /* Configure pin pad settings */ #warning Missing logic diff --git a/arch/arm/src/imx6/imx_iomuxc.h b/arch/arm/src/imx6/imx_iomuxc.h new file mode 100644 index 00000000000..402657c63d8 --- /dev/null +++ b/arch/arm/src/imx6/imx_iomuxc.h @@ -0,0 +1,67 @@ +/**************************************************************************** + * arch/arm/src/imx/imx_iomuxc.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX6_IMX_IOMUXC_H +#define __ARCH_ARM_SRC_IMX6_IMX_IOMUXC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip/imx_iomuxc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_IMX6_IMX_IOMUXC_H */