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risc-v/esp32c3: Fix regression on IRQ handling for ECALL instruction

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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
This commit is contained in:
Gustavo Henrique Nihei
2022-04-01 12:01:29 -03:00
committed by Alan Carvalho de Assis
parent 75ec6dffb6
commit c37474b5bd
1 changed files with 3 additions and 11 deletions
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arch/risc-v/src/esp32c3/esp32c3_irq.c
+3 -11
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@@ -359,25 +359,17 @@ IRAM_ATTR uintptr_t *esp32c3_dispatch_irq(uintptr_t mcause, uintptr_t *regs)
int irq;
uintptr_t *mepc = regs;
#ifdef CONFIG_ESP32C3_EXCEPTION_ENABLE_CACHE
if (((RISCV_IRQ_BIT & mcause) == 0) &&
(mcause != RISCV_IRQ_ECALLM))
{
#ifdef CONFIG_ESP32C3_EXCEPTION_ENABLE_CACHE
if (!spi_flash_cache_enabled())
{
spi_flash_enable_cache(0);
_err("ERROR: Cache was disabled and re-enabled\n");
}
}
#endif
}
else
{
/* Check "CURRENT_REGS" only in interrupt or ecall */
DEBUGASSERT(CURRENT_REGS == NULL);
}
CURRENT_REGS = regs;
irqinfo("INFO: mcause=%08" PRIXPTR "\n", mcause);
@@ -405,7 +397,7 @@ IRAM_ATTR uintptr_t *esp32c3_dispatch_irq(uintptr_t mcause, uintptr_t *regs)
if (mcause == RISCV_IRQ_ECALLM)
{
*mepc += 4;
irq_dispatch(ESP32C3_IRQ_ECALL_M, regs);
regs = riscv_doirq(ESP32C3_IRQ_ECALL_M, regs);
}
else
{