From c37474b5bd9b516a4c1c67af6db07235e128a293 Mon Sep 17 00:00:00 2001 From: Gustavo Henrique Nihei Date: Fri, 1 Apr 2022 12:01:29 -0300 Subject: [PATCH] risc-v/esp32c3: Fix regression on IRQ handling for ECALL instruction Signed-off-by: Gustavo Henrique Nihei --- arch/risc-v/src/esp32c3/esp32c3_irq.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/arch/risc-v/src/esp32c3/esp32c3_irq.c b/arch/risc-v/src/esp32c3/esp32c3_irq.c index e5e8d618121..c3f329d6c7c 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_irq.c +++ b/arch/risc-v/src/esp32c3/esp32c3_irq.c @@ -359,25 +359,17 @@ IRAM_ATTR uintptr_t *esp32c3_dispatch_irq(uintptr_t mcause, uintptr_t *regs) int irq; uintptr_t *mepc = regs; +#ifdef CONFIG_ESP32C3_EXCEPTION_ENABLE_CACHE if (((RISCV_IRQ_BIT & mcause) == 0) && (mcause != RISCV_IRQ_ECALLM)) { -#ifdef CONFIG_ESP32C3_EXCEPTION_ENABLE_CACHE if (!spi_flash_cache_enabled()) { spi_flash_enable_cache(0); _err("ERROR: Cache was disabled and re-enabled\n"); } + } #endif - } - else - { - /* Check "CURRENT_REGS" only in interrupt or ecall */ - - DEBUGASSERT(CURRENT_REGS == NULL); - } - - CURRENT_REGS = regs; irqinfo("INFO: mcause=%08" PRIXPTR "\n", mcause); @@ -405,7 +397,7 @@ IRAM_ATTR uintptr_t *esp32c3_dispatch_irq(uintptr_t mcause, uintptr_t *regs) if (mcause == RISCV_IRQ_ECALLM) { *mepc += 4; - irq_dispatch(ESP32C3_IRQ_ECALL_M, regs); + regs = riscv_doirq(ESP32C3_IRQ_ECALL_M, regs); } else {