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Merge remote-tracking branch 'mirtos/master' into dev

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Change-Id: I85394b24ce27d20ecbb130b85d844ab540507031
Signed-off-by: liuhaitao <liuhaitao@xiaomi.com>
This commit is contained in:
liuhaitao
2020-11-25 14:44:27 +08:00
parent 86dbc17a43 09778c38b1
commit c24f178af7
491 changed files with 13326 additions and 5249 deletions
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CONTRIBUTING.md
+6
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@@ -14,6 +14,12 @@ it is very important you follow these guidelines:
<first line (up to ~80 characters)>
<more paragraphs here>
* The first line should have a prefix to give context
(unless context is really clear), such as:
<keyword>: <message>
i.e sched: Fixed compiler warning
* Be sure to **fill in** the pull-request template with
meaningful content (be very descriptive, take your time).
Documentation/_static/custom.css
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@@ -78,3 +78,11 @@ kbd {
-webkit-border-radius: 3px;
text-shadow: 0 1px 0 #fff;
}
span.menuselection
{
margin: 0px 0.1em;
padding: 0.1em 0.1em;
border-radius: 3px;
border: 1px solid rgb(204, 204, 204);
}
Documentation/components/drivers/character/pwm.rst
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@@ -22,12 +22,12 @@ Files supporting PWM can be found in the following locations:
file includes both the application level interface to the PWM
driver as well as the interface between the "upper half" and
"lower half" drivers. The PWM module uses a standard character
driver framework. However, since the PWM driver is a devices
driver framework. However, since the PWM driver is a device
control interface and not a data transfer interface, the
majority of the functionality available to the application is
implemented in driver ioctl calls.
- **"Upper Half" Driver**. The generic, "upper half" PWM driver
resides at ``drivers/pwm.c``.
resides at ``drivers/timers/pwm.c``.
- **"Lower Half" Drivers**. Platform-specific PWM drivers reside
in ``arch/``\ *<architecture>*\ ``/src/``\ *<hardware>*
directory for the specific processor *<architecture>* and for
Documentation/components/drivers/character/watchdog.rst
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@@ -27,3 +27,130 @@ following locations:
``arch/``\ *<architecture>*\ ``/src/``\ *<hardware>* directory
for the specific processor *<architecture>* and for the
specific *<chip>* watchdog timer peripheral devices.
There are two ways to enable Watchdog Timer Support along with the Watchdog Example. The first is faster and simpler. Just run the following command to use a ready config file with watchdog timer support and example included. You need to check if there's a watchdog config file for your specific chip. You may check it at the specific board's path: ``/boards/<arch>/<chip>/<board>/config``.
.. code-block:: console
$ ./tools/configure.sh <board>:watchdog
And the second way is creating your own config file. To do so, follow the next instructions.
Enabling the Watchdog Support and Example in ``menuconfing``
------------------------------------------------------------
1. Select Watchdog Timer Instances
To select these wdts browse in the ``menuconfig`` using the following path:
Go into menu :menuselection:`System Type --> <Chip> Peripheral Selection` and press :kbd:`Enter`. Then select one or more watchdog timers according to availability of your chip.
2. Enable the Watchdog Timer Support
Go into menu :menuselection:`Device Drivers --> Timer Driver Support` and press :kbd:`Enter`. Then enable:
- [x] Watchdog Timer Support
3. Include the Watchdog Timer Example
Go into menu :menuselection:`Application Configuration --> Examples` and press :kbd:`Enter`. Then select the Watchdog Timer example.
- [x] Watchdog Timer example
Below the option, it is possible to manually configure some standard parameters that will be used by the example, but they also can be passed as command line arguments later.
The parameters are the following: the standard timer device path (which defines the WDT instance), the timeout period (which is the period on which the watchdog will expire),
the ping delay (which is the interval period between feeding the dog) and the ping time (which is the total interval that the example will feed the dog, after this interval,
the dog will starve and the chip will trigger an interrupt or reset.
4. Include the Debug Watchdog Feature
In order to get the watchdog timer status, you need to enable it. For production code and for your application you may disable it.
Go into menu :menuselection:`Build Setup --> Debug Options` and press :kbd:`Enter`. Then enable:
- [x] Enable Debug Features
- [x] Watchdog Timer Debug Features
Watchdog Timer Example
----------------------
The previously selected example will basically do the following:
* Open the watchdog device
* Set the watchdog timeout
* Start the watchdog timer
* Ping (feed the dog) during the ``pingtime`` with a delay of ``pingdelay`` and print out the wdt status in case debug was enabled.
* Enter into an endless loop without pinging. It will cause the watchdog timer to reset the chip on timeout, i.e., after timer expiration.
The `example code <https://github.com/apache/incubator-nuttx-apps/blob/master/examples/watchdog/watchdog_main.c>`_ may be explored, its path is at ``/examples/watchdog/watchdog_main.c`` in the apps' repository.
In NuttX, the watchdog timer driver is a character driver and when a chip supports multiple watchdog timers, each one is accessible through its respective special file in ``/dev`` directory. Each watchdog timer is registered using a unique numeric identifier (i.e. ``/dev/watchdog0``, ``/dev/watchdog1``, ...).
Use the following command to run the example:
.. code-block:: console
nsh> wdog
This command will use the watchdog timer 0. To use the others, specify it through a parameter (where x is the timer number):
.. code-block:: console
nsh> wdog -i /dev/watchdogx
Application Level Interface
----------------------------
The first necessary thing to be done in order to use the watchdog timer driver in an application is to include the header file for the NuttX Watchdog timer driver. It contains the Application Level Interface to the timer driver. To do so, include:
.. code-block:: c
#include <nuttx/timers/watchdog.h>
At an application level, the watchdog timer functionalities may be accessed through ``ioctl`` systems calls. These ``ioctl`` commands internally call lower-half layer operations and the parameters are forwarded to these operations through the ``ioctl`` system call. The example provides a great resource to demonstrate how to use those ``ioctl`` commands. The available ``ioctl`` commands are:
.. c:macro:: WDIOC_START
This command starts the watchdog timer.
.. c:macro:: WDIOC_STOP
This command stops the watchdog timer.
.. c:macro:: WDIOC_GETSTATUS
This command gets the status of the watchdog timer. It receives a writeable pointer to struct ``watchdog_status_s`` as parameter. The lower-half driver writes the current status in this struct.
.. c:struct:: watchdog_status_s
.. code-block:: c
struct watchdog_status_s
{
uint32_t flags; /* See WDFLAGS_* definitions above */
uint32_t timeout; /* The current timeout setting (in milliseconds) */
uint32_t timeleft; /* Time left until the watchdog expiration
* (in milliseconds) */
};
.. c:macro:: WDIOC_SETTIMEOUT
This command sets the timeout value, i.e., the value that will trigger the reset or interrupt. The argument is a ``uint32_t`` value in miliseconds.
.. c:macro:: WDIOC_CAPTURE
This command registers an user callback that will be triggered on timeout. It receives as argument a pointer to struct ``watchdog_capture_s``. If the user callback is NULL, then it configures only to reset. Not all chips support interrupt on timeout. This command is optional, i.e., if it's not used, the standard behaviour is to reset on timeout.
.. c:struct:: watchdog_capture_s
.. code-block:: c
struct watchdog_capture_s
{
CODE xcpt_t newhandler; /* The new watchdog capture handler */
CODE xcpt_t oldhandler; /* The previous watchdog capture handler (if any) */
};
.. c:macro:: WDIOC_KEEPALIVE
This command resets the watchdog timer ("ping", "pet the dog", "feed the dog").
Documentation/components/power.rst
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@@ -2,6 +2,10 @@
Power Management
================
.. todo::
This needs to be updated to account for the different governors
besides the activity-based one.
NuttX supports a simple power management (PM) sub-system which:
- Monitors activity from drivers (and from other parts of the
Documentation/index.rst
+2 -3
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@@ -20,15 +20,14 @@ Last Updated: |today|
:maxdepth: 2
Home <self>
introduction/index.rst
quickstart/index.rst
introduction/inviolables.rst
introduction/index.rst
boards/index.rst
components/index.rst
applications/index.rst
guides/index.rst
reference/index.rst
releases/index.rst
guides/index.rst
contributing/index.rst
glossary.rst
Documentation/introduction/about.rst
+3 -6
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@@ -1,9 +1,6 @@
===========
About NuttX
===========
Goals
=====
==================
About Apache NuttX
==================
NuttX is a real time embedded operating system (RTOS). Its goals are:
Documentation/introduction/trademarks.rst
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@@ -1,5 +1,3 @@
.. todo:: Revise status of NuttX trademark
==========
Trademarks
==========
Documentation/quickstart/build_and_make.rst
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@@ -1,59 +0,0 @@
.. include:: /substitutions.rst
.. _build_and_make:
Build and Make Details
======================
This is included for reference, and it's not necessary to know all these details.
As described in :ref:`compiling`, you use ``make`` at the root ``nuttx/`` directory to build NuttX. This is also
referenced as ``$(TOPDIR)`` in the ``Makefile``.
Root Directory
--------------
The ``$(TOPDIR)`` directory holds:
- The top level ```Makefile`` <#topmakefile>`__ that controls the
NuttX build.
That directory also holds:
- The makefile fragment :ref:`.config <nuttx_boards>`
that describes the current configuration, and
- The makefile fragment :ref:`Make.defs <nuttx_boards>`
that provides customized build targets.
Environment Variables
---------------------
The specific environmental definitions
are unique for each board but should include, as a minimum,
updates to the ``PATH`` variable to include the full path to the
architecture-specific toolchain identified in
:ref:`Make.defs <nuttx_boards>`.
First Time Make
---------------
Additional configuration actions will be taken the first time that system is built. These additional steps
include:
- Auto-generating the file ``include/nuttx/config.h`` using the
``$(TOPDIR)/.config`` file.
- Auto-generating the file ``$(TOPDIR)/.version`` with version
0.0 if one does not exist.
- Auto-generating the file ``include/nuttx/version.h`` using the
``$(TOPDIR)/.version`` file.
- Creating a link to
``$(TOPDIR)/arch/``\ *<arch-name>*\ ``/include`` at
``$(TOPDIR)/include/arch``.
- Creating a link to
``$(TOPDIR)/boards/``\ *<arch-name>*\ ``/``\ *<chip-name>*\ ``/``\ *<board-name>*\ ``/include``
at ``$(TOPDIR)/include/arch/board``.
- Creating a link to
``$(TOPDIR)/boards/``\ *<arch-name>*\ ``/``\ *<chip-name>*\ ``/``\ *<board-name>*\ ``/src``
at ``$(TOPDIR)/arch/``\ *<arch-name>*\ ``/src/board``
- Creating a link to ``${APPDIR}/include`` at
``$(TOPDIR)/include/apps``
- Creating make dependencies.
Documentation/quickstart/compiling.rst
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@@ -36,23 +36,15 @@ to ``configure.sh`` and indicate your host platform, such as:
The ``-l`` tells use that we're on Linux (macOS and Windows builds are
possible). Use the ``-h`` argument to see all available options.
Customize Your Configuration (Optional)
=======================================
This step is optional. Right now, this is mainly to get familiar with how it
works– you don't need to change any of the options now, but knowing how
to do this will come in handy later.
There are a lot of options. We'll cover a few of them here.
Don't worry about the complexity– you don't have to use most of the options.
You can then customize this configuration by using the menu based
configuration system with:
.. code-block:: console
$ cd nuttx/
$ make menuconfig
.. todo::
Explain some useful options.
Modifying the configuration is covered in :doc:`configuring`.
Build NuttX
===========
@@ -62,11 +54,11 @@ We can now build NuttX. To do so, you can simply run:
.. code-block:: console
$ cd nuttx/
$ make make
$ make
The build will complete by generating the binary outputs
inside `nuttx` directory. Typically this includes the `nuttx`
ELF file (suitable for debugging using `gdb`) and a `nuttx.bin`
inside ``nuttx`` directory. Typically this includes the ``nuttx``
ELF file (suitable for debugging using ``gdb``) and a ``nuttx.bin``
file that can be flashed to the board.
To clean the build, you can do:
@@ -75,11 +67,6 @@ To clean the build, you can do:
$ make clean
.. warning::
At the moment it is recommended that after modifying the
configuration you first clean before building again. This
is currently worked on.
----
Next up is :ref:`running`.
Documentation/quickstart/configuring.rst
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@@ -6,48 +6,31 @@ Configuring
Apache NuttX is a very configurable operating system. Nearly all features can be configured in or
out of the system. This makes it possible to compile a build tailored for your hardware and
application. It also makes configuring the system complex at times.
There is a configuration system that can be used on the commandline or in a GUI. I've found
the easiest way to configured Apache NuttX is to use the ``menuconfig`` system. This is used
via a terminal program and allows quick access to all of Apache NuttX's features via a system of
menus.
application.
The Apache NuttX configuration system uses Linux's
`kconfig system <https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt>`_ adapted for use with Apache
NuttX. Here's info on Linux's kconfig `menuconfig <https://en.wikipedia.org/wiki/Menuconfig>`_ system.
`kconfig system <https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt>`_ which
includes various frontends that allow you to modify configuration easily. Usually, the ``menuconfig``
frontend is used, which is a console based menu system (more info `here <https://en.wikipedia.org/wiki/Menuconfig>`_).
After you've configured your board (see :ref:`compiling`), you can use the menuconfig system
to change the configuration. Once you've configured, you can compile to make a build that
has your configuration options selected.
As previously explained in :doc:`compiling`, the first step is to load a premade configuration for
your board. Then, you can modify this configuration to your liking.
In this example, we will show how you modify the default configuration of the ``sim`` build.
#. Initialize Board Configuration
Here we'll use the simulator since that's the simplest to explain. You can do this with
any board and base configuration. Note here you should be supplying `configure.sh` the correct flag
for your build environment:
.. code-block:: bash
-l selects the Linux (l) host environment.
-m selects the macOS (m) host environment.
-c selects the Windows host and Cygwin (c) environment.
-g selects the Windows host and MinGW/MSYS environment.
-n selects the Windows host and Windows native (n) environment.
Select the simulator configuration for a Linux host:
.. code-block:: bash
.. code-block:: console
$ cd nuttx
$ make distclean # make a clean start, clearing out old configurations
$ ./tools/configure.sh -l sim:nsh
Copy files
Select CONFIG_HOST_LINUX=y
Refreshing...
#. Make
#. Build & run
.. code-block:: bash
.. code-block:: console
$ make clean; make
$ ./nuttx
@@ -55,15 +38,16 @@ has your configuration options selected.
From another terminal window, kill the simulator:
.. code-block:: bash
.. code-block:: console
$ pkill nuttx
#. Menu Configuration
#. Modify configuration
Showing that ``login:`` is annyoing. Let's use the ``menuconfig`` system to turn it off.
In this case we will remove the login feature (which will boot straight to the prompt). To
do so, we use the ``menuconfig`` frontend.
.. code-block:: bash
.. code-block:: console
$ make menuconfig
@@ -76,27 +60,24 @@ has your configuration options selected.
|br|
#. Application Configuration
The NSH Login setting is under :menuselection:`Application Configuration --> NSH Library`. You
can use :kbd:`🢁` and :kbd:`🢃` keys to navigate and :kbd:`↵` to enter a submenu.
To disable the corresponding setting go to :menuselection:`Console Login` and press :kbd:`spacebar` to
it (so that it has a blank space instead of a star in it).
The NSH Login setting is under ``Application Configuration > NSH Library``. Use
the up and down arrows to navigate to ``Application Configuration``; hit ``<return>`` to
select it. Now you're in the ``Application Configuration`` menu. Use the arrows to go
down to ``NSH Library`` and select that. Now navigate down to ``Console Login`` and use
the spacebar to uncheck that setting (so that it has a blank space instead of a star in it).
Now you need to exit ``menuconfig`` and save the modified configuration. Use the :kbd:`🡸` and
:kbd:`🡺` arrow keys to navigate the lower menu. If you select :menuselection:`Exit` you will be
prompted to save the config.
Now let's save. Use the right and left arrow keys to select the ``Exit`` menu item at the
bottom of the screen. Hit ``<return>`` to select it, hit ``<return>`` again, and again, finally
hitting ``<return>`` in the ``Save Configuration`` dialog box.
#. Build with the new Configuration
#. Make the New Configuration
.. code-block:: console
.. code-block:: bash
$ make clean; make
$ make
#. Run
.. code-block:: bash
.. code-block:: console
$ ./nuttx
NuttShell (NSH) NuttX-8.2
@@ -104,8 +85,42 @@ has your configuration options selected.
Success!
.. tip::
If you find that message of the day (MOTD) annoying and want to turn that off, it's
configured in ``Application Configuration > NSH Library >> Message of the Day (MOTD)``.
configured in :menuselection:`Application Configuration --> NSH Library --> Message of the Day (MOTD)`.
Fast configuration changes
--------------------------
If you know exactly which configuration symbol you want to change, you can use the ``kconfig-tweak`` tool (comes with the ``kconfig-frontends`` package) to quickly change a setting without going into the configuration frontend. This is useful to change settings such as debug options:
.. code-block:: console
$ kconfig-tweak --disable CONFIG_DEBUG_NET
$ make olddefconfig # needed to have the kconfig system check the config
$ kconfig-tweak --enable CONFIG_DEBUG_NET
$ make olddefconfig
This is also useful to script configuration changes that you perform often:
.. code-block:: console
#!/bin/bash
kconfig-tweak --disable CONFIG_DEBUG_ALERT
kconfig-tweak --disable CONFIG_DEBUG_FEATURES
kconfig-tweak --disable CONFIG_DEBUG_ERROR
kconfig-tweak --disable CONFIG_DEBUG_WARN
kconfig-tweak --disable CONFIG_DEBUG_INFO
kconfig-tweak --disable CONFIG_DEBUG_ASSERTIONS
kconfig-tweak --disable CONFIG_DEBUG_NET
kconfig-tweak --disable CONFIG_DEBUG_NET_ERROR
kconfig-tweak --disable CONFIG_DEBUG_NET_WARN
kconfig-tweak --disable CONFIG_DEBUG_NET_INFO
kconfig-tweak --disable CONFIG_DEBUG_SYMBOLS
kconfig-tweak --disable CONFIG_DEBUG_NOOPT
kconfig-tweak --disable CONFIG_SYSLOG_TIMESTAMP
make oldconfig
----
Documentation/quickstart/debugging.rst
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@@ -1,6 +1,7 @@
.. include:: /substitutions.rst
.. _debugging:
=========
Debugging
=========
@@ -9,27 +10,23 @@ to use debugging techniques to understand how the system works. Two tools that a
debugging using the GNU Debugger (gdb).
Debug Logging
-------------
=============
NuttX has a powerful system logging facility (syslog) with ``info``, ``warn``, and ``error`` levels. You can enable
debugging for your build for the subsystem or feature by using the ``menuconfig`` system.
.. code-block:: console
$ make menuconfig
The debug options are available under ``Build Setup`` > ``Debug Options``. You will most likely have to enable the
The debug options are available under :menuselection:`Build Setup --> Debug Options`. You will most likely have to enable the
following options:
* ``Enable Debug Features`` — selecting this will turn on subsystem-level debugging options, they will become visible
* :menuselection:`Enable Debug Features` — selecting this will turn on subsystem-level debugging options, they will become visible
on the page below. You can then select the ones you want.
* ``Enable Error Output`` — this will only log errors.
* ``Enable Warnings Output`` — this will log warnings and errors.
* ``Enable Informational Debug Output`` — this will produce informational output, warnings, and errors.
* :menuselection:`Enable Error Output` — this will only log errors.
* :menuselection:`Enable Warnings Output` — this will log warnings and errors.
* :menuselection:`Enable Informational Debug Output` — this will produce informational output, warnings, and errors.
You can then select from the subsystems that are available, Network, Scheduler, USB, etc. Note that you will need to
separately enable the subsystem elsewhere in the ``menuconfig`` system. To see the ``CONFIG`` define that is set,
use the arrow keys to highlight the subsystem (for instance, ``Network Debug Features``) and type '?'. This will show
use the arrow keys to highlight the subsystem (for instance, :menuselection:`Network Debug Features`) and type :kbd:`?`. This will show
you that the C macro that is set is called ``CONFIG_DEBUG_NET``. ``debug.h`` defines the ``netinfo()`` logging
function that will log output if this macro is set. You can search the source code for ``netinfo`` to see how it is
used.
@@ -44,82 +41,228 @@ the area you're interested in, and leave the rest disabled, save the config, and
list of debug feature logging functions in the file
`debug.h <https://github.com/apache/incubator-nuttx/blob/master/include/debug.h>`__.
Syslog timestamps can be enabled in the ``menuconfig`` system using ``Device Drivers`` > ``System Logging`` > ``Prepend
timestamp to syslog message`` (``CONFIG_SYSLOG_TIMESTAMP``).
Syslog timestamps can be enabled in the configuration in :menuselection:`Device Drivers --> System Logging --> Prepend
timestamp to syslog message` (``CONFIG_SYSLOG_TIMESTAMP``).
You may need to do a little bit of experimenting to find the combination of logging settings that work for the problem
you're trying to solve. See the file `debug.h <https://github.com/apache/incubator-nuttx/blob/master/include/debug.h>`_
for available debug settings that are available. This can also be configured via the ``menuconfig`` system.
for available debug settings that are available.
There are also subsystems that enable USB trace debugging, and you can log to memory too, if you need the logging to be
faster than what the console can output.
Changing Debug Settings Quickly
-------------------------------
Debugging with ``openocd`` and ``gdb``
======================================
You can use the ``kconfig-tweak`` script that comes with the ``kconfig-frontends`` tools to quickly change debug settings,
for instance turning them on or off before doing a build:
To debug our Nucleo board using its embedded SWD debug adapter,
start ``openocd`` with the following command:
.. code-block:: console
$ kconfig-tweak --disable CONFIG_DEBUG_NET
$ make olddefconfig # needed to have the kconfig system check the config
$ kconfig-tweak --enable CONFIG_DEBUG_NET
$ make olddefconfig
$ openocd -f interface/st-link-v2.cfg -f target/stm32f1x.cfg
You can put a bunch of these into a simple script to configure the logging the way you want:
This will start a ``gdb`` server. Then, start ``gdb`` with:
.. code-block:: console
#!/bin/bash
$ cd nuttx/
$ gdb-multiarch nuttx/nuttx
kconfig-tweak --disable CONFIG_DEBUG_ALERT
kconfig-tweak --disable CONFIG_DEBUG_FEATURES
kconfig-tweak --disable CONFIG_DEBUG_ERROR
kconfig-tweak --disable CONFIG_DEBUG_WARN
kconfig-tweak --disable CONFIG_DEBUG_INFO
kconfig-tweak --disable CONFIG_DEBUG_ASSERTIONS
kconfig-tweak --disable CONFIG_DEBUG_NET
kconfig-tweak --disable CONFIG_DEBUG_NET_ERROR
kconfig-tweak --disable CONFIG_DEBUG_NET_WARN
kconfig-tweak --disable CONFIG_DEBUG_NET_INFO
kconfig-tweak --disable CONFIG_DEBUG_SYMBOLS
kconfig-tweak --disable CONFIG_DEBUG_NOOPT
kconfig-tweak --disable CONFIG_SYSLOG_TIMESTAMP
make oldconfig
Inside ``gdb`` console, connect to the ``gdb`` server with:
.. code-block::
JTAG/SWD Debugging
------------------
(gdb) target extended-remote :3333
`JTAG <https://en.wikipedia.org/wiki/JTAG>`_ is a set of standards that specify a way to attach a hardware device to
your embedded board, and then remotely control the CPU. You can load code, start, stop, step through the program, and
examine variables and memory. `SWD <https://en.wikipedia.org/wiki/JTAG#Similar_interface_standards>`_ is an
Arm-specific interface with a reduced number of signals which can be used alternatively.
You can now use standard ``gdb`` commands. For example, to
reset the board:
The NuttX operating system uses `threads <https://en.wikipedia.org/wiki/Thread_(computing)>`_, so you need a
thread-aware debugger to do more than load code, start, and stop it. A thread-aware debugger will allow you to switch
threads to the one that is running the code you're interested in, for instance your application, or an operating system
network thread. So far, `OpenOCD <http://openocd.org/>`_ is the only supported NuttX thread-aware debugger.
.. code-block::
.. note::
OpenOCD hasn't announced a stable release for a few years but the development remains active. You'll need to use a
version of OpenOCD recent enough so that it includes NuttX support as `contributed by Sony upstream
<http://openocd.zylin.com/#/c/4103/>`_. The version included in official OS repositories will probably be too old.
You should build from source or use one of the unofficial, more recent builds. See `Getting OpenOCD
<http://openocd.org/getting-openocd/>`_ for more details.
(gdb) mon reset
You will need a board with a JTAG or SWD connector and an `OpenOCD-compatible hardware adapter
<http://openocd.org/supported-jtag-interfaces/>`_, ideally a fast one (USB 2.0 High Speed). For example an `Olimex
ARM USB TINY H <https://www.olimex.com/Products/ARM/JTAG/ARM-USB-TINY-H/>`_ or a `Segger J-Link
<https://www.segger.com/products/debug-probes/j-link/>`_. Many other adapters work too, follow the OpenOCD
instructions and the instructions that came with your adapter.
To halt the board:
See this article for more info:
`Debugging a Apache NuttX target with GDB and OpenOCD <https://micro-ros.github.io/docs/tutorials/advanced/nuttx/debugging/>`_.
.. code-block::
See the section :ref:`Running <running>` for a brief tutorial on how to use GDB.
(gdb) mon halt
To set a breakpoint:
----
.. code-block::
(gdb) breakpoint nsh_main
and to finally start nuttx:
.. code-block::
(gdb) continue
Continuing.
Breakpoint 1, nsh_main (argc=1, argv=0x200ddfac) at nsh_main.c:208
208 sched_getparam(0, &param);
(gdb) continue
Continuing.
.. tip::
You can abbreviate ``gdb`` commands: ``info b`` is a shortcut for
``information breakpoints``; ``c`` works the same as ``continue``, etc.
NuttX aware debugging
---------------------
Since NuttX is actually an RTOS, it is useful to have ``gdb`` be aware of the different
tasks/threads that are running. There are two ways to do this: via ``openocd``
itself or via ``gdb``. Note that in both cases, you need to enable debug symbols
(``CONFIG_DEBUG_SYMBOLS``).
With openocd
~~~~~~~~~~~~
``openocd`` supports various RTOS directly, including NuttX. It works by reading
into internal NuttX symbols which define the active tasks and their properties.
As a result, the ``gdb`` server will directly be aware of each task as a different
`thread`. The downside of this approach is that it depends on how you build NuttX
as there are some options hardcoded into
opencd. By default, it assumes:
* ``CONFIG_DISABLE_MQUEUE=y``
* ``CONFIG_PAGING=n``
If you need these options to be set differently, you will have to edit ``./src/rtos/nuttx_header.h`` from ``openocd``,
change the corresponding settings and then rebuild it.
Finally, to enable NuttX integration, you need to supply an additional ``openocd`` argument:
.. code-block:: console
$ openocd -f interface/st-link-v2.cfg -f target/stm32f1x.cfg -c '$_TARGETNAME configure -rtos nuttx'
Since ``openocd`` also needs to know the memory layout of certain datastructures, you need to have ``gdb``
run the following commands once the ``nuttx`` binary is loaded:
.. code-block::
eval "monitor nuttx.pid_offset %d", &((struct tcb_s *)(0))->pid
eval "monitor nuttx.xcpreg_offset %d", &((struct tcb_s *)(0))->xcp.regs
eval "monitor nuttx.state_offset %d", &((struct tcb_s *)(0))->task_state
eval "monitor nuttx.name_offset %d", &((struct tcb_s *)(0))->name
eval "monitor nuttx.name_size %d", sizeof(((struct tcb_s *)(0))->name)
One way to do this is to define a gdb `hook` function that will be called when running ``file`` command:
.. code-block::
define hookpost-file
eval "monitor nuttx.pid_offset %d", &((struct tcb_s *)(0))->pid
eval "monitor nuttx.xcpreg_offset %d", &((struct tcb_s *)(0))->xcp.regs
eval "monitor nuttx.state_offset %d", &((struct tcb_s *)(0))->task_state
eval "monitor nuttx.name_offset %d", &((struct tcb_s *)(0))->name
eval "monitor nuttx.name_size %d", sizeof(((struct tcb_s *)(0))->name)
end
You will see that ``openocd`` has received the memory offsets in its output:
.. code-block::
Open On-Chip Debugger 0.10.0+dev-01514-ga8edbd020-dirty (2020-11-20-14:23)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "swd". To override use 'transport select <transport>'.
Info : target type name = cortex_m
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
15:41:23: Debugging starts
Info : CMSIS-DAP: SWD Supported
Info : CMSIS-DAP: FW Version = 1.10
Info : CMSIS-DAP: Interface Initialised (SWD)
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 0 TDO = 0 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : clock speed 1000 kHz
Info : SWD DPIDR 0x2ba01477
Info : nrf52.cpu: hardware has 6 breakpoints, 4 watchpoints
Info : starting gdb server for nrf52.cpu on 3333
Info : Listening on port 3333 for gdb connections
Info : accepting 'gdb' connection on tcp/3333
Error: No symbols for NuttX
Info : nRF52832-QFAA(build code: B0) 512kB Flash, 64kB RAM
undefined debug reason 8 - target needs reset
Warn : Prefer GDB command "target extended-remote 3333" instead of "target remote 3333"
Info : pid_offset: 12
Info : xcpreg_offset: 132
Info : state_offset: 26
Info : name_offset: 208
Info : name_size: 32
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x000000dc msp: 0x20000cf0
target halted due to debug-request, current mode: Thread xPSR: 0x01000000 pc: 0x000000dc msp: 0x20000cf0
.. note:: You will probably see the ``Error: No symbols for NuttX`` error appear once at startup. This is OK
unless you see it every time you step the debugger. In this case, it would mean you did not enable debug symbols.
Now, You can now inspect threads:
.. code-block::
(gdb) info threads
Id Target Id Frame
* 1 Remote target nx_start_application () at init/nx_bringup.c:261
(gdb) info registers
r0 0x0 0
r1 0x2f 47
r2 0x0 0
r3 0x0 0
r4 0x0 0
r5 0x0 0
r6 0x0 0
r7 0x20000ca0 536874144
r8 0x0 0
r9 0x0 0
r10 0x0 0
r11 0x0 0
r12 0x9 9
sp 0x20000c98 0x20000c98
lr 0x19c5 6597
pc 0x1996 0x1996 <nx_start_application+10>
xPSR 0x41000000 1090519040
fpscr 0x0 0
msp 0x20000c98 0x20000c98
psp 0x0 0x0 <_vectors>
primask 0x0 0
basepri 0xe0 -32
faultmask 0x0 0
control 0x0 0
With gdb
~~~~~~~~
You can also do NuttX aware debugging using ``gdb`` scripting support.
The benefit is that it works also for the sim build where ``openocd`` is
not applicable. For this to work, you will need to enable PROC filesystem support
which will expose required task information (``CONFIG_FS_PROCFS=y``).
To use this approach, you can load the ``nuttx/tools/nuttx-gdbinit`` file. An
easy way to do this is to create a symbolic link:
.. code-block:: console
$ cd $HOME
$ ln -s nuttx/tools/nuttx-gdbinit .gdbinit
This way whenever gdb is started it will run the appropriate commands. To inspect
the threads you can now use the following ``gdb`` command:
.. code-block::
(gdb) info_nxthreads
target examined
_target_arch.name=armv7e-m
$_target_has_fpu : 0
$_target_has_smp : 0
saved current_tcb (pid=0)
* 0 Thread 0x20000308 (Name: Idle Task, State: Running, Priority: 0) 0xdc in __start()
1 Thread 0x20001480 (Name: init, State: Waiting,Semaphore, Priority: 100) 0x7e08 in arm_switchcontext()
Next up is :ref:`organization`.
Documentation/quickstart/index.rst
-1
View File
@@ -22,5 +22,4 @@ to build NuttX.
configuring.rst
debugging.rst
organization.rst
build_and_make.rst
Documentation/quickstart/organization.rst
+6 -6
View File
@@ -1,4 +1,9 @@
.. include:: /substitutions.rst
.. todo::
This is mostly untouched from the original documentation. It does
not really belong to "quickstart". Also, this needs cleanup.
.. _organization:
===================
@@ -506,10 +511,5 @@ support.
==================
The top-level ``Makefile`` in the ``$(TOPDIR)`` directory contains
all of the top-level control logic to build NuttX. Use of this
``Makefile`` to build NuttX is described
`below <#buildingnuttx>`__.
all of the top-level control logic to build NuttX.
----
Next up is :ref:`build_and_make`.
Documentation/quickstart/running.rst
+1 -117
View File
@@ -40,7 +40,7 @@ latest Git version. To install it you should:
$ git clone git://git.code.sf.net/p/openocd/code openocd
$ cd openocd
$ ./bootstrap
$ ./configure --prefix install/
$ ./configure --prefix=install/
$ make install
The resulting installation will be under ``openocd/install``. You can add
@@ -71,122 +71,6 @@ of your choice where you will see the ``nsh>`` prompt:
$ gtkterm -s 115200 -p /dev/ttyUSB0
Debugging
=========
Using ``openocd`` you can also debug NuttX. To do so, first run:
.. code-block:: console
$ openocd -f interface/st-link-v2.cfg -f target/stm32f1x.cfg
which will start a GDB server. Then, start ``gdb`` as:
.. code-block:: console
$ cd nuttx/
$ gdb-multiarch nuttx/nuttx
Inside ``gdb`` console, connect to the ``openocd`` server with:
.. code-block::
(gdb) target extended-remote :3333
You can debug using standard ``gdb`` commands.
Advanced Debugging with JTAG
----------------------------
If your board does not have an embedded programmer and uses
`JTAG <https://en.wikipedia.org/wiki/JTAG>`_ connector instead,
things are a bit different. This guide assumes you have a JTAG hardware debugger like a
`Segger J-Link <https://www.segger.com/products/debug-probes/j-link/>`_.
JTAG is a set of standards that let you
attach a hardware device to your embedded board, and then remotely control the CPU.
You can load code, start, stop, step through the program, and examine variables and memory.
#. Attach the Debugger Cables
#. Start the Debugger
Refer to your JTAG debugger's documentation for information on how to start a GDB Server process that gdb can
communicate with to load code and start, stop, and step the embedded board's CPU. Your command line may be
different from this one.
.. code-block:: console
$ JLinkGDBServer -device ATSAMA5D27 -if JTAG -speed 1000 -JTAGConf -1,-1
#. Launch the GNU Debugger
In another terminal window, launch the GDB. In the case of this guide, this came with the
ARM Embedded GNU Toolchain we downloaded in the Install step.
.. code-block:: console
$ cd nuttx/
$ gdb-multiarch nuttx/nuttx
#. Set gdb to talk with the J-Link
::
(gdb) target extended-remote :2331
#. Reset the board
::
(gdb) mon reset
#. You may need to switch to the serial console to hit a key to stop the board from booting from its boot monitor
(U-Boot, in the case of the SAMA5 boards from Microchip).
#. Halt the board
::
(gdb) mon halt
#. Load nuttx
::
(gdb) load nuttx
`/home/adamf/src/nuttx-sama5d36-xplained/nuttx/nuttx' has changed; re-reading symbols.
Loading section .text, size 0x9eae4 lma 0x20008000
Loading section .ARM.exidx, size 0x8 lma 0x200a6ae4
Loading section .data, size 0x125c lma 0x200a6aec
Start address 0x20008040, load size 654664
Transfer rate: 75 KB/sec, 15587 bytes/write.
(gdb)
#. Set a breakpoint
::
(gdb) breakpoint nsh_main
#. Start nuttx
::
(gdb) continue
Continuing.
Breakpoint 1, nsh_main (argc=1, argv=0x200ddfac) at nsh_main.c:208
208 sched_getparam(0, &param);
(gdb) continue
Continuing.
Debugging Shortcuts
-------------------
Note that you can abbreviate ``gdb`` commands, ``info b`` is a shortcut for
``information breakpoints``; ``c`` works the same as ``continue``, etc.
----
Next up is :ref:`configuring`.
Documentation/releases/index.rst
-6
View File
@@ -1,6 +0,0 @@
Releases
========
.. todo::
This should link (or include?) release notes. Maybe only show some recent ones and link
older ones
TODO
+2 -61
View File
@@ -1,4 +1,4 @@
NuttX TODO List (Last updated October 20, 2020)
NuttX TODO List (Last updated November 20, 2020)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -10,7 +10,7 @@ issues related to each board port.
nuttx/:
(16) Task/Scheduler (sched/)
(5) SMP
(3) SMP
(1) Memory Management (mm/)
(0) Power Management (drivers/pm)
(5) Signals (sched/signal, arch/)
@@ -448,34 +448,6 @@ o Task/Scheduler (sched/)
o SMP
^^^
Title: SMP AND DATA CACHES
Description: When spinlocks, semaphores, etc. are used in an SMP system with
a data cache, then there may be problems with cache coherency
in some CPU architectures: When one CPU modifies the shared
object, the changes may not be visible to another CPU if it
does not share the data cache. That would cause failure in
the IPC logic.
Flushing the D-cache on writes and invalidating before a read is
not really an option. That would essentially effect every memory
access and there may be side-effects due to cache line sizes
and alignment.
For the same reason a separate, non-cacheable memory region is
not an option. Essentially all data would have to go in the
non-cached region and you would have no benefit from the data
cache.
On ARM Cortex-A, each CPU has a separate data cache. However,
the MPCore's Snoop Controller Unit supports coherency among
the different caches. The SCU is enabled by the SCU control
register and each CPU participates in the SMP coherency by
setting the ACTLR_SMP bit in the auxiliary control register
(ACTLR).
Status: Closed
Priority: High on platforms that may have the issue.
Title: MISUSE OF sched_lock() IN SMP MODE
Description: The OS API sched_lock() disables pre-emption and locks a
task in place. In the single CPU case, it is also often
@@ -496,37 +468,6 @@ o SMP
Priority: Medium for SMP system. Not critical to single CPU systems.
NOTE: There are no known bugs from this potential problem.
Title: CORTEX-A GIC SGI INTERRUPT MASKING
Description: In the ARMv7-A GICv2 architecture, the inter-processor
interrupts (SGIs) are non maskable and will occur even if
interrupts are disabled. This adds a lot of complexity
to the ARMV7-A critical section design.
Masayuki Ishikawa has suggested the use of the GICv2 ICCMPR
register to control SGI interrupts. This register (much like
the ARMv7-M BASEPRI register) can be used to mask interrupts
by interrupt priority. Since SGIs may be assigned priorities
the ICCMPR should be able to block execution of SGIs as well.
Such an implementation would be very similar to the BASEPRI
(vs PRIMASK) implementation for the ARMv7-M: (1) The
up_irq_save() and up_irq_restore() registers would have to
set/restore the ICCMPR register, (2) register setup logic in
arch/arm/src/armv7-a for task start-up and signal dispatch
would have to set the ICCMPR correctly, and (3) the 'xcp'
structure would have to be extended to hold the ICCMPR
register; logic would have to added be save/restore the
ICCMPR register in the 'xcp' structure on each interrupt and
context switch.
This would also be an essential part of a high priority,
nested interrupt implementation (unrelated).
Status: Open
Priority: Low. There are no known issues with the current non-maskable
SGI implementation. This change would, however, lead to
simplification in the design and permit commonality with
other, non-GIC implementations.
Title: ISSUES WITH ACCESSING CPU INDEX
Description: The CPU number is accessed usually with the macro this_cpu().
The returned CPU number is then used for various things,
arch/arm/include/inttypes.h
+12 -12
View File
@@ -46,77 +46,77 @@
#define PRId8 "d"
#define PRId16 "d"
#define PRId32 "d"
#define PRId32 "ld"
#define PRId64 "lld"
#define PRIdPTR "d"
#define PRIi8 "i"
#define PRIi16 "i"
#define PRIi32 "i"
#define PRIi32 "li"
#define PRIi64 "lli"
#define PRIiPTR "i"
#define PRIo8 "o"
#define PRIo16 "o"
#define PRIo32 "o"
#define PRIo32 "lo"
#define PRIo64 "llo"
#define PRIoPTR "o"
#define PRIu8 "u"
#define PRIu16 "u"
#define PRIu32 "u"
#define PRIu32 "lu"
#define PRIu64 "llu"
#define PRIuPTR "u"
#define PRIx8 "x"
#define PRIx16 "x"
#define PRIx32 "x"
#define PRIx32 "lx"
#define PRIx64 "llx"
#define PRIxPTR "x"
#define PRIX8 "X"
#define PRIX16 "X"
#define PRIX32 "X"
#define PRIX32 "lX"
#define PRIX64 "llX"
#define PRIXPTR "X"
#define SCNd8 "hhd"
#define SCNd16 "hd"
#define SCNd32 "d"
#define SCNd32 "ld"
#define SCNd64 "lld"
#define SCNdPTR "d"
#define SCNi8 "hhi"
#define SCNi16 "hi"
#define SCNi32 "i"
#define SCNi32 "li"
#define SCNi64 "lli"
#define SCNiPTR "i"
#define SCNo8 "hho"
#define SCNo16 "ho"
#define SCNo32 "o"
#define SCNo32 "lo"
#define SCNo64 "llo"
#define SCNoPTR "o"
#define SCNu8 "hhu"
#define SCNu16 "hu"
#define SCNu32 "u"
#define SCNu32 "lu"
#define SCNu64 "llu"
#define SCNuPTR "u"
#define SCNx8 "hhx"
#define SCNx16 "hx"
#define SCNx32 "x"
#define SCNx32 "lx"
#define SCNx64 "llx"
#define SCNxPTR "x"
@@ -128,7 +128,7 @@
#define UINT8_C(x) x
#define UINT16_C(x) x
#define UINT32_C(x) x ## u
#define UINT32_C(x) x ## ul
#define UINT64_C(x) x ## ull
#endif /* __ARCH_ARM_INCLUDE_INTTYPES_H */
arch/arm/include/stm32/chip.h
+38
View File
@@ -2486,6 +2486,44 @@
# error "Unsupported STM32 chip"
#endif
/* Peripheral IP versions *************************************************************************/
/* Peripheral IP versions are invariant and should be decided here, not in
* Kconfig.
*
* REVISIT: Currently only SPI IP version is handled here, with others being
* handled in Kconfig. Those others need to be gradually refactored
* and resolved here.
*/
#if defined(CONFIG_STM32_STM32F10XX)
# define STM32_HAVE_IP_SPI_V1
#elif defined(CONFIG_STM32_STM32F20XX)
# define STM32_HAVE_IP_SPI_V2
#elif defined(CONFIG_STM32_STM32F30XX)
# define STM32_HAVE_IP_SPI_V3
#elif defined(CONFIG_STM32_STM32F33XX)
# define STM32_HAVE_IP_SPI_V1
#elif defined(CONFIG_STM32_STM32F37XX)
# define STM32_HAVE_IP_SPI_V3
#elif defined(CONFIG_STM32_STM32F4XXX)
# define STM32_HAVE_IP_SPI_V2
#elif defined(CONFIG_STM32_STM32G47XX)
# define STM32_HAVE_IP_SPI_V4
#elif defined(CONFIG_STM32_STM32L15XX)
# define STM32_HAVE_IP_SPI_V1
#else
# error "Did not resolve peripheral IP versions!"
#endif
/* NVIC priority levels ***************************************************************************/
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
arch/arm/include/types.h
+5 -2
View File
@@ -56,13 +56,16 @@ typedef unsigned char _uint8_t;
typedef signed short _int16_t;
typedef unsigned short _uint16_t;
typedef signed int _int32_t;
typedef unsigned int _uint32_t;
typedef signed long _int32_t;
typedef unsigned long _uint32_t;
typedef signed long long _int64_t;
typedef unsigned long long _uint64_t;
#define __INT64_DEFINED
typedef _int64_t _intmax_t;
typedef _uint64_t _uintmax_t;
/* A size is 4 bytes */
#if defined(__SIZE_TYPE__)
arch/arm/src/Makefile
+5 -2
View File
@@ -194,12 +194,15 @@ endif
# Dependencies
makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds)
$(call CATFILE, Make.dep, $^)
$(call DELFILE, $^)
.depend: Makefile chip$(DELIM)Make.defs $(SRCS) $(TOPDIR)$(DELIM).config
ifeq ($(BOARDMAKE),y)
$(Q) $(MAKE) -C board depend
endif
$(Q) $(MKDEP) $(patsubst %,--dep-path %,$(subst :, ,$(VPATH))) \
"$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep
$(Q) $(MAKE) makedepfile DEPPATH="$(patsubst %,--dep-path %,$(subst :, ,$(VPATH)))"
$(Q) touch $@
depend: .depend
arch/arm/src/a1x/a1x_serial.c
+2 -2
View File
@@ -108,7 +108,7 @@ static int up_attach(struct uart_dev_s *dev);
static void up_detach(struct uart_dev_s *dev);
static int uart_interrupt(int irq, void *context, void *arg);
static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
static int up_receive(struct uart_dev_s *dev, uint32_t *status);
static int up_receive(struct uart_dev_s *dev, unsigned int *status);
static void up_rxint(struct uart_dev_s *dev, bool enable);
static bool up_rxavailable(struct uart_dev_s *dev);
static void up_send(struct uart_dev_s *dev, int ch);
@@ -1316,7 +1316,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
*
****************************************************************************/
static int up_receive(struct uart_dev_s *dev, uint32_t *status)
static int up_receive(struct uart_dev_s *dev, unsigned int *status)
{
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
uint32_t rbr;
arch/arm/src/am335x/am335x_serial.c
+2 -2
View File
@@ -109,7 +109,7 @@ static int up_attach(struct uart_dev_s *dev);
static void up_detach(struct uart_dev_s *dev);
static int uart_interrupt(int irq, void *context, void *arg);
static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
static int up_receive(struct uart_dev_s *dev, uint32_t *status);
static int up_receive(struct uart_dev_s *dev, unsigned int *status);
static void up_rxint(struct uart_dev_s *dev, bool enable);
static bool up_rxavailable(struct uart_dev_s *dev);
static void up_send(struct uart_dev_s *dev, int ch);
@@ -1142,7 +1142,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
*
****************************************************************************/
static int up_receive(struct uart_dev_s *dev, uint32_t *status)
static int up_receive(struct uart_dev_s *dev, unsigned int *status)
{
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
uint32_t rbr;
arch/arm/src/armv6-m/arm_svcall.c
+2 -1
View File
@@ -24,6 +24,7 @@
#include <nuttx/config.h>
#include <inttypes.h>
#include <stdint.h>
#include <string.h>
#include <assert.h>
@@ -439,7 +440,7 @@ int arm_svcall(int irq, FAR void *context, FAR void *arg)
rtcb->flags |= TCB_FLAG_SYSCALL;
#else
svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
svcerr("ERROR: Bad SYS call: %" PRId32 "\n", regs[REG_R0]);
#endif
}
break;
arch/arm/src/armv7-a/arm_cpustart.c
-4
View File
@@ -171,10 +171,6 @@ int up_cpu_start(int cpu)
sched_note_cpu_start(this_task(), cpu);
#endif
/* Make the content of CPU0 L1 cache has been written to coherent L2 */
cp15_clean_dcache(CONFIG_RAM_START, CONFIG_RAM_END - 1);
/* Execute SGI1 */
return arm_cpu_sgi(GIC_IRQ_SGI1, (1 << cpu));
arch/arm/src/armv7-a/arm_l2cc_pl310.c
+25 -16
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/armv7-a/chip/arm-l2cc_pl310.c
*
* Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
@@ -36,7 +36,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/****************************************************************************
* Included Files
@@ -59,13 +59,15 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ***********************************************************/
/* Configuration ************************************************************/
/* Number of ways depends on ARM configuration */
#if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
# define PL310_NWAYS 8
# define PL310_WAY_MASK 0x000000ff
#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY)
# define PL310_NWAYS 16
# define PL310_WAY_MASK 0x0000ffff
#else
@@ -315,38 +317,45 @@ void arm_l2ccinitialize(void)
/* Make sure that this is a PL310 cache, version r3p2.
*
* REVISIT: The SAMA5D4 is supposed to report its ID as 0x410000C8 which is
* r3p2, but the chip that I have actually* reports 0x410000C9 which is some
* later revision.
* REVISIT: The SAMA5D4 is supposed to report its ID as 0x410000C8 which
* is r3p2, but the chip that I have actually* reports 0x410000C9 which
* is some later revision.
*/
//DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) == L2CC_IDR_REV_R3P2);
/* DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) ==
* L2CC_IDR_REV_R3P2);
*/
/* Make sure that actual cache configuration agrees with the configured
* cache configuration.
*/
#if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 0);
#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 1);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == L2CC_ACR_ASS);
#else
# error No associativity selected
#endif
#if defined(CONFIG_ARMV7A_WAYSIZE_16KB)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_16KB);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
L2CC_ACR_WAYSIZE_16KB);
#elif defined(CONFIG_ARMV7A_WAYSIZE_32KB)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_32KB);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
L2CC_ACR_WAYSIZE_32KB);
#elif defined(CONFIG_ARMV7A_WAYSIZE_64KB)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_64KB);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
L2CC_ACR_WAYSIZE_64KB);
#elif defined(CONFIG_ARMV7A_WAYSIZE_128KB)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_128KB);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
L2CC_ACR_WAYSIZE_128KB);
#elif defined(CONFIG_ARMV7A_WAYSIZE_256KB)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_256KB);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
L2CC_ACR_WAYSIZE_256KB);
#elif defined(CONFIG_ARMV7A_WAYSIZE_512KB)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_512KB);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
L2CC_ACR_WAYSIZE_512KB);
#else
# error No way size selected
#endif
arch/arm/src/armv7-a/l2cc_pl310.h
+130 -128
View File
@@ -52,11 +52,12 @@
* header file as L2CC_VBASE.
*/
#include "chip/chip.h"
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* General Definitions **************************************************************/
#define PL310_CACHE_LINE_SIZE 32
@@ -110,7 +111,7 @@
#define L2CC_DLKR_OFFSET(n) (0x0900 + ((n) << 3)) /* Data Lockdown Register */
#define L2CC_ILKR_OFFSET(n) (0x0904 + ((n) << 3)) /* Instruction Lockdown Register */
/* 0x0940-0x0f4c Reserved */
/* 0x0940-0x0f4c Reserved */
#ifdef CONFIG_PL310_LOCKDOWN_BY_LINE
# define L2CC_LKLN_OFFSET 0x0950 /* Lock Line Enable Register */
# define L2CC_UNLKW_OFFSET 0x0954 /* Unlock Way Register */
@@ -170,23 +171,23 @@
/* Cache ID Register (32-bit ID) */
#define L2CC_IDR_REV_MASK 0x0000003f
# define L2CC_IDR_REV_R0P0 0x00000000
# define L2CC_IDR_REV_R1P0 0x00000002
# define L2CC_IDR_REV_R2P0 0x00000004
# define L2CC_IDR_REV_R3P0 0x00000005
# define L2CC_IDR_REV_R3P1 0x00000006
# define L2CC_IDR_REV_R3P2 0x00000008
#define L2CC_IDR_REV_R0P0 0x00000000
#define L2CC_IDR_REV_R1P0 0x00000002
#define L2CC_IDR_REV_R2P0 0x00000004
#define L2CC_IDR_REV_R3P0 0x00000005
#define L2CC_IDR_REV_R3P1 0x00000006
#define L2CC_IDR_REV_R3P2 0x00000008
/* Cache Type Register */
#define L2CC_TYPR_IL2ASS (1 << 6) /* Bit 6: Instruction L2 Cache Associativity */
#define L2CC_TYPR_IL2WSIZE_SHIFT (8) /* Bits 8-10: Instruction L2 Cache Way Size */
#define L2CC_TYPR_IL2WSIZE_MASK (7 << L2CC_TYPR_IL2WSIZE_SHIFT)
# define L2CC_TYPR_IL2WSIZE(n) ((uint32_t)(n) << L2CC_TYPR_IL2WSIZE_SHIFT)
#define L2CC_TYPR_IL2WSIZE(n) ((uint32_t)(n) << L2CC_TYPR_IL2WSIZE_SHIFT)
#define L2CC_TYPR_DL2ASS (1 << 18) /* Bit 18: Data L2 Cache Associativity */
#define L2CC_TYPR_DL2WSIZE_SHIFT (20) /* Bits 20-22: Data L2 Cache Way Size */
#define L2CC_TYPR_DL2WSIZE_MASK (7 << L2CC_TYPR_DL2WSIZE_SHIFT)
# define L2CC_TYPR_DL2WSIZE(n) ((uint32_t)(n) << L2CC_TYPR_DL2WSIZE_SHIFT)
#define L2CC_TYPR_DL2WSIZE(n) ((uint32_t)(n) << L2CC_TYPR_DL2WSIZE_SHIFT)
/* Control Register */
@@ -202,21 +203,22 @@
#define L2CC_ACR_ASS (1 << 16) /* Bit 16: Associativity */
#define L2CC_ACR_WAYSIZE_SHIFT (17) /* Bits 17-19: Way Size */
#define L2CC_ACR_WAYSIZE_MASK (7 << L2CC_ACR_WAYSIZE_SHIFT)
# define L2CC_ACR_WAYSIZE_16KB (1 << L2CC_ACR_WAYSIZE_SHIFT)
# define L2CC_ACR_WAYSIZE_32KB (2 << L2CC_ACR_WAYSIZE_SHIFT)
# define L2CC_ACR_WAYSIZE_64KB (3 << L2CC_ACR_WAYSIZE_SHIFT)
# define L2CC_ACR_WAYSIZE_128KB (4 << L2CC_ACR_WAYSIZE_SHIFT)
# define L2CC_ACR_WAYSIZE_256KB (5 << L2CC_ACR_WAYSIZE_SHIFT)
# define L2CC_ACR_WAYSIZE_512KB (6 << L2CC_ACR_WAYSIZE_SHIFT)
#define L2CC_ACR_WAYSIZE_16KB (1 << L2CC_ACR_WAYSIZE_SHIFT)
#define L2CC_ACR_WAYSIZE_32KB (2 << L2CC_ACR_WAYSIZE_SHIFT)
#define L2CC_ACR_WAYSIZE_64KB (3 << L2CC_ACR_WAYSIZE_SHIFT)
#define L2CC_ACR_WAYSIZE_128KB (4 << L2CC_ACR_WAYSIZE_SHIFT)
#define L2CC_ACR_WAYSIZE_256KB (5 << L2CC_ACR_WAYSIZE_SHIFT)
#define L2CC_ACR_WAYSIZE_512KB (6 << L2CC_ACR_WAYSIZE_SHIFT)
#define L2CC_ACR_EMBEN (1 << 20) /* Bit 20: Event Monitor Bus Enable */
#define L2CC_ACR_PEN (1 << 21) /* Bit 21: Parity Enable */
#define L2CC_ACR_SAOEN (1 << 22) /* Bit 22: Shared Attribute Override Enable */
#define L2CC_ACR_FWA_SHIFT (23) /* Bits 23-24: Force Write Allocate */
#define L2CC_ACR_FWA_MASK (3 << L2CC_ACR_FWA_SHIFT)
# define L2CC_ACR_FWA_AWCACHE (0 << L2CC_ACR_FWA_SHIFT) /* Use AWCACHE attributes for WA */
# define L2CC_ACR_FWA_NOALLOC (1 << L2CC_ACR_FWA_SHIFT) /* No allocate */
# define L2CC_ACR_FWA_OVERRIDE (2 << L2CC_ACR_FWA_SHIFT) /* Override AWCACHE attributes */
# define L2CC_ACR_FWA_MAPPED (3 << L2CC_ACR_FWA_SHIFT) /* Internally mapped to 00 */
#define L2CC_ACR_FWA_AWCACHE (0 << L2CC_ACR_FWA_SHIFT) /* Use AWCACHE attributes for WA */
#define L2CC_ACR_FWA_NOALLOC (1 << L2CC_ACR_FWA_SHIFT) /* No allocate */
#define L2CC_ACR_FWA_OVERRIDE (2 << L2CC_ACR_FWA_SHIFT) /* Override AWCACHE attributes */
#define L2CC_ACR_FWA_MAPPED (3 << L2CC_ACR_FWA_SHIFT) /* Internally mapped to 00 */
#define L2CC_ACR_CRPOL (1 << 25) /* Bit 25: Cache Replacement Policy */
#define L2CC_ACR_NSLEN (1 << 26) /* Bit 26: Non-Secure Lockdown Enable */
#define L2CC_ACR_NSIAC (1 << 27) /* Bit 27: Non-Secure Interrupt Access Control */
@@ -230,25 +232,25 @@
#define L2CC_TRCR_TSETLAT_SHIFT (0) /* Bits 0-2: Setup Latency */
#define L2CC_TRCR_TSETLAT_MASK (7 << L2CC_TRCR_TSETLAT_SHIFT)
# define L2CC_TRCR_TSETLAT(n) ((uint32_t)(n) << L2CC_TRCR_TSETLAT_SHIFT)
#define L2CC_TRCR_TSETLAT(n) ((uint32_t)(n) << L2CC_TRCR_TSETLAT_SHIFT)
#define L2CC_TRCR_TRDLAT_SHIFT (4) /* Bits 4-6: Read Access Latency */
#define L2CC_TRCR_TRDLAT_MASK (7 << L2CC_TRCR_TRDLAT_SHIFT)
# define L2CC_TRCR_TRDLAT(n) ((uint32_t)(n) << L2CC_TRCR_TRDLAT_SHIFT)
#define L2CC_TRCR_TRDLAT(n) ((uint32_t)(n) << L2CC_TRCR_TRDLAT_SHIFT)
#define L2CC_TRCR_TWRLAT_SHIFT (8) /* Bits 8-10: Write Access Latency */
#define L2CC_TRCR_TWRLAT_MASK (7 << L2CC_TRCR_TWRLAT_SHIFT)
# define L2CC_TRCR_TWRLAT(n) ((uint32_t)(n) << L2CC_TRCR_TWRLAT_SHIFT)
#define L2CC_TRCR_TWRLAT(n) ((uint32_t)(n) << L2CC_TRCR_TWRLAT_SHIFT)
/* Data RAM Control Register */
#define L2CC_DRCR_DSETLAT_SHIFT (0) /* Bits 0-2: Setup Latency */
#define L2CC_DRCR_DSETLAT_MASK (7 << L2CC_DRCR_DSETLAT_SHIFT)
# define L2CC_DRCR_DSETLAT(n) ((uint32_t)(n) << L2CC_DRCR_DSETLAT_SHIFT)
#define L2CC_DRCR_DSETLAT(n) ((uint32_t)(n) << L2CC_DRCR_DSETLAT_SHIFT)
#define L2CC_DRCR_DRDLAT_SHIFT (4) /* Bits 4-6: Read Access Latency */
#define L2CC_DRCR_DRDLAT_MASK (7 << L2CC_DRCR_DRDLAT_SHIFT)
# define L2CC_DRCR_DRDLAT(n) ((uint32_t)(n) << L2CC_DRCR_DRDLAT_SHIFT)
#define L2CC_DRCR_DRDLAT(n) ((uint32_t)(n) << L2CC_DRCR_DRDLAT_SHIFT)
#define L2CC_DRCR_DWRLAT_SHIFT (8) /* Bits 8-10: Write Access Latency */
#define L2CC_DRCR_DWRLAT_MASK (7 << L2CC_DRCR_DWRLAT_SHIFT)
# define L2CC_DRCR_DWRLAT(n) ((uint32_t)(n) << L2CC_DRCR_DWRLAT_SHIFT)
#define L2CC_DRCR_DWRLAT(n) ((uint32_t)(n) << L2CC_DRCR_DWRLAT_SHIFT)
/* Event Counter Control Register */
@@ -258,60 +260,60 @@
/* Event Counter 1 Configuration Register */
#define L2CC_ECFGR1_EIGEN_SHIFT (0) /* Bits 0-1: Event Counter Interrupt Generation */
#define L2CC_ECFGR1_EIGEN_MASK (3 << L2CC_ECFGR1_EIGEN_SHIFT)
# define L2CC_ECFGR1_EIGEN_INTDIS (0 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables (default) */
# define L2CC_ECFGR1_EIGEN_INTENINCR (1 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Increment condition */
# define L2CC_ECFGR1_EIGEN_INTENOVER (2 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Overflow condition */
# define L2CC_ECFGR1_EIGEN_INTGENDIS (3 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables Interrupt generation */
#define L2CC_ECFGR1_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */
#define L2CC_ECFGR1_ESRC_MASK (15 << L2CC_ECFGR1_ESRC_SHIFT)
# define L2CC_ECFGR1_ESRC_CNTDIS (0 << L2CC_ECFGR1_ESRC_SHIFT) /* Counter Disabled */
# define L2CC_ECFGR1_ESRC_CO (1 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is CO */
# define L2CC_ECFGR1_ESRC_DRHIT (2 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DRHIT */
# define L2CC_ECFGR1_ESRC_DRREQ (3 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DRREQ */
# define L2CC_ECFGR1_ESRC_DWHIT (4 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWHIT */
# define L2CC_ECFGR1_ESRC_DWREQ (5 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWREQ */
# define L2CC_ECFGR1_ESRC_DWTREQ (6 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWTREQ */
# define L2CC_ECFGR1_ESRC_IRHIT (7 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IRHIT */
# define L2CC_ECFGR1_ESRC_IRREQ (8 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IRREQ */
# define L2CC_ECFGR1_ESRC_WA (9 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is WA */
# define L2CC_ECFGR1_ESRC_IPFALLOC (10 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IPFALLOC */
# define L2CC_ECFGR1_ESRC_EPFHIT (11 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFHIT */
# define L2CC_ECFGR1_ESRC_EPFALLOC (12 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFALLOC */
# define L2CC_ECFGR1_ESRC_SRRCVD (13 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRRCVD */
# define L2CC_ECFGR1_ESRC_SRCONF (14 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRCONF */
# define L2CC_ECFGR1_ESRC_EPFRCVD (15 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFRCVD */
#define L2CC_ECFGR1_EIGEN_SHIFT (0) /* Bits 0-1: Event Counter Interrupt Generation */
#define L2CC_ECFGR1_EIGEN_MASK (3 << L2CC_ECFGR1_EIGEN_SHIFT)
#define L2CC_ECFGR1_EIGEN_INTDIS (0 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables (default) */
#define L2CC_ECFGR1_EIGEN_INTENINCR (1 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Increment condition */
#define L2CC_ECFGR1_EIGEN_INTENOVER (2 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Overflow condition */
#define L2CC_ECFGR1_EIGEN_INTGENDIS (3 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables Interrupt generation */
#define L2CC_ECFGR1_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */
#define L2CC_ECFGR1_ESRC_MASK (15 << L2CC_ECFGR1_ESRC_SHIFT)
#define L2CC_ECFGR1_ESRC_CNTDIS (0 << L2CC_ECFGR1_ESRC_SHIFT) /* Counter Disabled */
#define L2CC_ECFGR1_ESRC_CO (1 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is CO */
#define L2CC_ECFGR1_ESRC_DRHIT (2 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DRHIT */
#define L2CC_ECFGR1_ESRC_DRREQ (3 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DRREQ */
#define L2CC_ECFGR1_ESRC_DWHIT (4 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWHIT */
#define L2CC_ECFGR1_ESRC_DWREQ (5 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWREQ */
#define L2CC_ECFGR1_ESRC_DWTREQ (6 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWTREQ */
#define L2CC_ECFGR1_ESRC_IRHIT (7 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IRHIT */
#define L2CC_ECFGR1_ESRC_IRREQ (8 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IRREQ */
#define L2CC_ECFGR1_ESRC_WA (9 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is WA */
#define L2CC_ECFGR1_ESRC_IPFALLOC (10 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IPFALLOC */
#define L2CC_ECFGR1_ESRC_EPFHIT (11 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFHIT */
#define L2CC_ECFGR1_ESRC_EPFALLOC (12 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFALLOC */
#define L2CC_ECFGR1_ESRC_SRRCVD (13 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRRCVD */
#define L2CC_ECFGR1_ESRC_SRCONF (14 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRCONF */
#define L2CC_ECFGR1_ESRC_EPFRCVD (15 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFRCVD */
/* Event Counter 0 Configuration Register */
#define L2CC_ECFGR0_EIGEN_SHIFT (0) /* Bits 0-1: Event Counter Interrupt Generation */
#define L2CC_ECFGR0_EIGEN_MASK (3 << L2CC_ECFGR0_EIGEN_SHIFT)
# define L2CC_ECFGR0_EIGEN_INTDIS (0 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables (default) */
# define L2CC_ECFGR0_EIGEN_INTENINCR (1 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Increment condition */
# define L2CC_ECFGR0_EIGEN_INTENOVER (2 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Overflow condition */
# define L2CC_ECFGR0_EIGEN_INTGENDIS (3 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables Interrupt generation */
#define L2CC_ECFGR0_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */
#define L2CC_ECFGR0_ESRC_MASK (15 << L2CC_ECFGR0_ESRC_SHIFT)
# define L2CC_ECFGR0_ESRC_CNTDIS (0 << L2CC_ECFGR0_ESRC_SHIFT) /* Counter Disabled */
# define L2CC_ECFGR0_ESRC_CO (1 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is CO */
# define L2CC_ECFGR0_ESRC_DRHIT (2 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DRHIT */
# define L2CC_ECFGR0_ESRC_DRREQ (3 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DRREQ */
# define L2CC_ECFGR0_ESRC_DWHIT (4 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWHIT */
# define L2CC_ECFGR0_ESRC_DWREQ (5 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWREQ */
# define L2CC_ECFGR0_ESRC_DWTREQ (6 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWTREQ */
# define L2CC_ECFGR0_ESRC_IRHIT (7 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IRHIT */
# define L2CC_ECFGR0_ESRC_IRREQ (8 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IRREQ */
# define L2CC_ECFGR0_ESRC_WA (9 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is WA */
# define L2CC_ECFGR0_ESRC_IPFALLOC (10 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IPFALLOC */
# define L2CC_ECFGR0_ESRC_EPFHIT (11 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFHIT */
# define L2CC_ECFGR0_ESRC_EPFALLOC (12 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFALLOC */
# define L2CC_ECFGR0_ESRC_SRRCVD (13 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRRCVD */
# define L2CC_ECFGR0_ESRC_SRCONF (14 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRCONF */
# define L2CC_ECFGR0_ESRC_EPFRCVD (15 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFRCVD */
#define L2CC_ECFGR0_EIGEN_SHIFT (0) /* Bits 0-1: Event Counter Interrupt Generation */
#define L2CC_ECFGR0_EIGEN_MASK (3 << L2CC_ECFGR0_EIGEN_SHIFT)
#define L2CC_ECFGR0_EIGEN_INTDIS (0 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables (default) */
#define L2CC_ECFGR0_EIGEN_INTENINCR (1 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Increment condition */
#define L2CC_ECFGR0_EIGEN_INTENOVER (2 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Overflow condition */
#define L2CC_ECFGR0_EIGEN_INTGENDIS (3 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables Interrupt generation */
#define L2CC_ECFGR0_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */
#define L2CC_ECFGR0_ESRC_MASK (15 << L2CC_ECFGR0_ESRC_SHIFT)
#define L2CC_ECFGR0_ESRC_CNTDIS (0 << L2CC_ECFGR0_ESRC_SHIFT) /* Counter Disabled */
#define L2CC_ECFGR0_ESRC_CO (1 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is CO */
#define L2CC_ECFGR0_ESRC_DRHIT (2 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DRHIT */
#define L2CC_ECFGR0_ESRC_DRREQ (3 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DRREQ */
#define L2CC_ECFGR0_ESRC_DWHIT (4 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWHIT */
#define L2CC_ECFGR0_ESRC_DWREQ (5 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWREQ */
#define L2CC_ECFGR0_ESRC_DWTREQ (6 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWTREQ */
#define L2CC_ECFGR0_ESRC_IRHIT (7 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IRHIT */
#define L2CC_ECFGR0_ESRC_IRREQ (8 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IRREQ */
#define L2CC_ECFGR0_ESRC_WA (9 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is WA */
#define L2CC_ECFGR0_ESRC_IPFALLOC (10 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IPFALLOC */
#define L2CC_ECFGR0_ESRC_EPFHIT (11 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFHIT */
#define L2CC_ECFGR0_ESRC_EPFALLOC (12 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFALLOC */
#define L2CC_ECFGR0_ESRC_SRRCVD (13 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRRCVD */
#define L2CC_ECFGR0_ESRC_SRCONF (14 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRCONF */
#define L2CC_ECFGR0_ESRC_EPFRCVD (15 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFRCVD */
/* Event Counter 1 Value Register (32-bit value) */
/* Event Counter 0 Value Register (32-bit value) */
/* Interrupt Mask Register, Masked Interrupt Status Register, Raw Interrupt Status
@@ -337,110 +339,110 @@
#define L2CC_IPALR_C (1 << 0) /* Bit 0: Cache Synchronization Status */
#define L2CC_IPALR_IDX_SHIFT (5) /* Bits 5-13: Index Number */
#define L2CC_IPALR_IDX_MASK (0x1ff << L2CC_IPALR_IDX_SHIFT)
# define L2CC_IPALR_IDX(n) ((uint32_t)(n) << L2CC_IPALR_IDX_SHIFT)
#define L2CC_IPALR_IDX(n) ((uint32_t)(n) << L2CC_IPALR_IDX_SHIFT)
#define L2CC_IPALR_TAG_SHIFT (14) /* Bits 14-31: Tag Number */
#define L2CC_IPALR_TAG_MASK (0x3ffff << L2CC_IPALR_TAG_SHIFT)
# define L2CC_IPALR_TAG(n) ((uint32_t)(n) << L2CC_IPALR_TAG_SHIFT)
#define L2CC_IPALR_TAG(n) ((uint32_t)(n) << L2CC_IPALR_TAG_SHIFT)
/* Invalidate Way Register */
#define L2CC_IWR_WAY(n) (1 << (n)) /* Bist 0-7: Invalidate Way Number n, n=0..7 */
# define L2CC_IWR_WAY0 (1 << 0) /* Bit 0: Invalidate Way Number 0 */
# define L2CC_IWR_WAY1 (1 << 1) /* Bit 1: Invalidate Way Number 1 */
# define L2CC_IWR_WAY2 (1 << 2) /* Bit 2: Invalidate Way Number 2 */
# define L2CC_IWR_WAY3 (1 << 3) /* Bit 3: Invalidate Way Number 3 */
# define L2CC_IWR_WAY4 (1 << 4) /* Bit 4: Invalidate Way Number 4 */
# define L2CC_IWR_WAY5 (1 << 5) /* Bit 5: Invalidate Way Number 5 */
# define L2CC_IWR_WAY6 (1 << 6) /* Bit 6: Invalidate Way Number 6 */
# define L2CC_IWR_WAY7 (1 << 7) /* Bit 7: Invalidate Way Number 7 */
#define L2CC_IWR_WAY0 (1 << 0) /* Bit 0: Invalidate Way Number 0 */
#define L2CC_IWR_WAY1 (1 << 1) /* Bit 1: Invalidate Way Number 1 */
#define L2CC_IWR_WAY2 (1 << 2) /* Bit 2: Invalidate Way Number 2 */
#define L2CC_IWR_WAY3 (1 << 3) /* Bit 3: Invalidate Way Number 3 */
#define L2CC_IWR_WAY4 (1 << 4) /* Bit 4: Invalidate Way Number 4 */
#define L2CC_IWR_WAY5 (1 << 5) /* Bit 5: Invalidate Way Number 5 */
#define L2CC_IWR_WAY6 (1 << 6) /* Bit 6: Invalidate Way Number 6 */
#define L2CC_IWR_WAY7 (1 << 7) /* Bit 7: Invalidate Way Number 7 */
/* Clean Physical Address Line Register */
#define L2CC_CPALR_C (1 << 0) /* Bit 0: Cache Synchronization Status */
#define L2CC_CPALR_IDX_SHIFT (5) /* Bits 5-13: Index number */
#define L2CC_CPALR_IDX_MASK (0x1ff << L2CC_CPALR_IDX_SHIFT)
# define L2CC_CPALR_IDX(n) ((uint32_t)(n) << L2CC_CPALR_IDX_SHIFT)
#define L2CC_CPALR_IDX(n) ((uint32_t)(n) << L2CC_CPALR_IDX_SHIFT)
#define L2CC_CPALR_TAG_SHIFT (14) /* Bits 14-31: Tag number */
#define L2CC_CPALR_TAG_MASK (0x3ffff << L2CC_CPALR_TAG_SHIFT)
# define L2CC_CPALR_TAG(n) ((uint32_t)(n) << L2CC_CPALR_TAG_SHIFT)
#define L2CC_CPALR_TAG(n) ((uint32_t)(n) << L2CC_CPALR_TAG_SHIFT)
/* Clean Index Register */
#define L2CC_CIR_C (1 << 0) /* Bit 0: Cache Synchronization Status */
#define L2CC_CIR_IDX_SHIFT (5) /* Bits 5-13: Index number */
#define L2CC_CIR_IDX_MASK (0x1ff << L2CC_CIR_IDX_SHIFT)
# define L2CC_CIR_IDX(n) ((uint32_t)(n) << L2CC_CIR_IDX_SHIFT)
#define L2CC_CIR_IDX(n) ((uint32_t)(n) << L2CC_CIR_IDX_SHIFT)
#define L2CC_CIR_WAY_SHIFT (28) /* Bits 28-30: Way number */
#define L2CC_CIR_WAY_MASK (7 << L2CC_CIR_WAY_SHIFT)
# define L2CC_CIR_WAY(n) ((uint32_t)(n) << L2CC_CIR_WAY_SHIFT)
#define L2CC_CIR_WAY(n) ((uint32_t)(n) << L2CC_CIR_WAY_SHIFT)
/* Clean Way Register */
#define L2CC_CWR_WAY(n) (1 << (n)) /* Bits 0-7: Clean Way Number n, n=0..7 */
# define L2CC_CWR_WAY0 (1 << 0) /* Bit 0: Clean Way Number 0 */
# define L2CC_CWR_WAY1 (1 << 1) /* Bit 1: Clean Way Number 1 */
# define L2CC_CWR_WAY2 (1 << 2) /* Bit 2: Clean Way Number 2 */
# define L2CC_CWR_WAY3 (1 << 3) /* Bit 3: Clean Way Number 3 */
# define L2CC_CWR_WAY4 (1 << 4) /* Bit 4: Clean Way Number 4 */
# define L2CC_CWR_WAY5 (1 << 5) /* Bit 5: Clean Way Number 5 */
# define L2CC_CWR_WAY6 (1 << 6) /* Bit 6: Clean Way Number 6 */
# define L2CC_CWR_WAY7 (1 << 7) /* Bit 7: Clean Way Number 7 */
#define L2CC_CWR_WAY0 (1 << 0) /* Bit 0: Clean Way Number 0 */
#define L2CC_CWR_WAY1 (1 << 1) /* Bit 1: Clean Way Number 1 */
#define L2CC_CWR_WAY2 (1 << 2) /* Bit 2: Clean Way Number 2 */
#define L2CC_CWR_WAY3 (1 << 3) /* Bit 3: Clean Way Number 3 */
#define L2CC_CWR_WAY4 (1 << 4) /* Bit 4: Clean Way Number 4 */
#define L2CC_CWR_WAY5 (1 << 5) /* Bit 5: Clean Way Number 5 */
#define L2CC_CWR_WAY6 (1 << 6) /* Bit 6: Clean Way Number 6 */
#define L2CC_CWR_WAY7 (1 << 7) /* Bit 7: Clean Way Number 7 */
/* Clean Invalidate Physical Address Line Register */
#define L2CC_CIPALR_C (1 << 0) /* Bit 0: Cache Synchronization Status */
#define L2CC_CIPALR_IDX_SHIFT (5) /* Bits 5-13: Index Number */
#define L2CC_CIPALR_IDX_MASK (0x1ff << L2CC_CIPALR_IDX_SHIFT)
# define L2CC_CIPALR_IDX(n) ((uint32_t)(n) << L2CC_CIPALR_IDX_SHIFT)
#define L2CC_CIPALR_IDX(n) ((uint32_t)(n) << L2CC_CIPALR_IDX_SHIFT)
#define L2CC_CIPALR_TAG_SHIFT (14) /* Bits 14-31: Tag Number */
#define L2CC_CIPALR_TAG_MASK (0x3ffff << L2CC_CIPALR_TAG_SHIFT)
# define L2CC_CIPALR_TAG(n) ((uint32_t)(n) << L2CC_CIPALR_TAG_SHIFT)
#define L2CC_CIPALR_TAG(n) ((uint32_t)(n) << L2CC_CIPALR_TAG_SHIFT)
/* Clean Invalidate Index Register */
#define L2CC_CIIR_C (1 << 0) /* Bit 0: Cache Synchronization Status */
#define L2CC_CIIR_IDX_SHIFT (5) /* Bits 5-13: Index Number */
#define L2CC_CIIR_IDX_MASK (0x1ff << L2CC_CIIR_IDX_SHIFT)
# define L2CC_CIIR_IDX(n) ((uint32_t)(n) << L2CC_CIIR_IDX_SHIFT)
#define L2CC_CIIR_IDX(n) ((uint32_t)(n) << L2CC_CIIR_IDX_SHIFT)
#define L2CC_CIIR_WAY_SHIFT (28) /* Bits 28-30: Way Number */
#define L2CC_CIIR_WAY_MASK (7 << L2CC_CIIR_WAY_SHIFT)
# define L2CC_CIIR_WAY(n) ((uint32_t)(n) << L2CC_CIIR_WAY_SHIFT)
#define L2CC_CIIR_WAY(n) ((uint32_t)(n) << L2CC_CIIR_WAY_SHIFT)
/* Clean Invalidate Way Register */
#define L2CC_CIWR_WAY(n) (1 << (n)) /* Bits 0-7: Clean Invalidate Way Number n, n=1..7 */
# define L2CC_CIWR_WAY0 (1 << 0) /* Bit 0: Clean Invalidate Way Number 0 */
# define L2CC_CIWR_WAY1 (1 << 1) /* Bit 1: Clean Invalidate Way Number 1 */
# define L2CC_CIWR_WAY2 (1 << 2) /* Bit 2: Clean Invalidate Way Number 2 */
# define L2CC_CIWR_WAY3 (1 << 3) /* Bit 3: Clean Invalidate Way Number 3 */
# define L2CC_CIWR_WAY4 (1 << 4) /* Bit 4: Clean Invalidate Way Number 4 */
# define L2CC_CIWR_WAY5 (1 << 5) /* Bit 5: Clean Invalidate Way Number 5 */
# define L2CC_CIWR_WAY6 (1 << 6) /* Bit 6: Clean Invalidate Way Number 6 */
# define L2CC_CIWR_WAY7 (1 << 7) /* Bit 7: Clean Invalidate Way Number 7 */
#define L2CC_CIWR_WAY0 (1 << 0) /* Bit 0: Clean Invalidate Way Number 0 */
#define L2CC_CIWR_WAY1 (1 << 1) /* Bit 1: Clean Invalidate Way Number 1 */
#define L2CC_CIWR_WAY2 (1 << 2) /* Bit 2: Clean Invalidate Way Number 2 */
#define L2CC_CIWR_WAY3 (1 << 3) /* Bit 3: Clean Invalidate Way Number 3 */
#define L2CC_CIWR_WAY4 (1 << 4) /* Bit 4: Clean Invalidate Way Number 4 */
#define L2CC_CIWR_WAY5 (1 << 5) /* Bit 5: Clean Invalidate Way Number 5 */
#define L2CC_CIWR_WAY6 (1 << 6) /* Bit 6: Clean Invalidate Way Number 6 */
#define L2CC_CIWR_WAY7 (1 << 7) /* Bit 7: Clean Invalidate Way Number 7 */
/* Data Lockdown Register */
#define L2CC_DLKR_DLK(n) (1 << (n)) /* Bits 0-7: Data Lockdown in Way Number n, n=0..7 */
# define L2CC_DLKR_DLK0 (1 << 0) /* Bit 0: Data Lockdown in Way Number 0 */
# define L2CC_DLKR_DLK1 (1 << 1) /* Bit 1: Data Lockdown in Way Number 1 */
# define L2CC_DLKR_DLK2 (1 << 2) /* Bit 2: Data Lockdown in Way Number 2 */
# define L2CC_DLKR_DLK3 (1 << 3) /* Bit 3: Data Lockdown in Way Number 3 */
# define L2CC_DLKR_DLK4 (1 << 4) /* Bit 4: Data Lockdown in Way Number 4 */
# define L2CC_DLKR_DLK5 (1 << 5) /* Bit 5: Data Lockdown in Way Number 5 */
# define L2CC_DLKR_DLK6 (1 << 6) /* Bit 6: Data Lockdown in Way Number 6 */
# define L2CC_DLKR_DLK7 (1 << 7) /* Bit 7: Data Lockdown in Way Number 7 */
#define L2CC_DLKR_DLK0 (1 << 0) /* Bit 0: Data Lockdown in Way Number 0 */
#define L2CC_DLKR_DLK1 (1 << 1) /* Bit 1: Data Lockdown in Way Number 1 */
#define L2CC_DLKR_DLK2 (1 << 2) /* Bit 2: Data Lockdown in Way Number 2 */
#define L2CC_DLKR_DLK3 (1 << 3) /* Bit 3: Data Lockdown in Way Number 3 */
#define L2CC_DLKR_DLK4 (1 << 4) /* Bit 4: Data Lockdown in Way Number 4 */
#define L2CC_DLKR_DLK5 (1 << 5) /* Bit 5: Data Lockdown in Way Number 5 */
#define L2CC_DLKR_DLK6 (1 << 6) /* Bit 6: Data Lockdown in Way Number 6 */
#define L2CC_DLKR_DLK7 (1 << 7) /* Bit 7: Data Lockdown in Way Number 7 */
/* Instruction Lockdown Register */
#define L2CC_ILKR_ILK(n) (1 << (n)) /* Bits 0-7: Instruction Lockdown in Way Number n, n=0..7 */
# define L2CC_ILKR_ILK0 (1 << 0) /* Bit 0: Instruction Lockdown in Way Number 0 */
# define L2CC_ILKR_ILK1 (1 << 1) /* Bit 1: Instruction Lockdown in Way Number 1 */
# define L2CC_ILKR_ILK2 (1 << 2) /* Bit 2: Instruction Lockdown in Way Number 2 */
# define L2CC_ILKR_ILK3 (1 << 3) /* Bit 3: Instruction Lockdown in Way Number 3 */
# define L2CC_ILKR_ILK4 (1 << 4) /* Bit 4: Instruction Lockdown in Way Number 4 */
# define L2CC_ILKR_ILK5 (1 << 5) /* Bit 5: Instruction Lockdown in Way Number 5 */
# define L2CC_ILKR_ILK6 (1 << 6) /* Bit 6: Instruction Lockdown in Way Number 6 */
# define L2CC_ILKR_ILK7 (1 << 7) /* Bit 7: Instruction Lockdown in Way Number 7 */
#define L2CC_ILKR_ILK0 (1 << 0) /* Bit 0: Instruction Lockdown in Way Number 0 */
#define L2CC_ILKR_ILK1 (1 << 1) /* Bit 1: Instruction Lockdown in Way Number 1 */
#define L2CC_ILKR_ILK2 (1 << 2) /* Bit 2: Instruction Lockdown in Way Number 2 */
#define L2CC_ILKR_ILK3 (1 << 3) /* Bit 3: Instruction Lockdown in Way Number 3 */
#define L2CC_ILKR_ILK4 (1 << 4) /* Bit 4: Instruction Lockdown in Way Number 4 */
#define L2CC_ILKR_ILK5 (1 << 5) /* Bit 5: Instruction Lockdown in Way Number 5 */
#define L2CC_ILKR_ILK6 (1 << 6) /* Bit 6: Instruction Lockdown in Way Number 6 */
#define L2CC_ILKR_ILK7 (1 << 7) /* Bit 7: Instruction Lockdown in Way Number 7 */
/* Lock Line Enable Register */
@@ -453,8 +455,8 @@
#ifdef CONFIG_PL310_LOCKDOWN_BY_LINE
# define L2CC_UNLKW_WAY_SHIFT (0) /* Bits 0-15: Unlock line for corresponding way */
# define L2CC_UNLKW_WAY_MASK (0xffff << L2CC_UNLKW_WAY_SHIFT)
# define L2CC_UNLKW_WAY_SET(n) ((uint32_t)(n) << L2CC_UNLKW_WAY_SHIFT)
# define L2CC_UNLKW_WAY_BIT(n) ((1 << (n)) << L2CC_UNLKW_WAY_SHIFT)
# define L2CC_UNLKW_WAY_SET(n) ((uint32_t)(n) << L2CC_UNLKW_WAY_SHIFT)
# define L2CC_UNLKW_WAY_BIT(n) ((1 << (n)) << L2CC_UNLKW_WAY_SHIFT)
#endif
/* Address filter start */
@@ -480,7 +482,7 @@
#define L2CC_PCR_SHIFT (0) /* Bits 0-4: Prefetch Offset */
#define L2CC_PCR_MASK (31 << L2CC_PCR_SHIFT)
# define L2CC_PCR_PREFETCH(n) ((uint32_t)(n) << L2CC_PCR_SHIFT)
#define L2CC_PCR_PREFETCH(n) ((uint32_t)(n) << L2CC_PCR_SHIFT)
#define L2CC_PCR_NSIDEN (1 << 21) /* Bit 21: Not Same ID on Exclusive Sequence Enable */
#define L2CC_PCR_IDLEN (1 << 23) /* Bit 23: INCR Double Linefill Enable */
#define L2CC_PCR_PDEN (1 << 24) /* Bit 24: Prefetch Drop Enable */
arch/arm/src/armv7-a/mmu.h
+247 -226
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/armv7-m/arm_svcall.c
+2 -1
View File
@@ -24,6 +24,7 @@
#include <nuttx/config.h>
#include <inttypes.h>
#include <stdint.h>
#include <string.h>
#include <assert.h>
@@ -453,7 +454,7 @@ int arm_svcall(int irq, FAR void *context, FAR void *arg)
rtcb->flags |= TCB_FLAG_SYSCALL;
#else
svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
svcerr("ERROR: Bad SYS call: %" PRId32 "\n", regs[REG_R0]);
#endif
}
break;
arch/arm/src/c5471/c5471_watchdog.c
+9 -5
View File
@@ -74,7 +74,7 @@
#define C5471_DISABLE_VALUE2 (0xa0 << 22)
#define CLOCK_KHZ 47500
#define CLOCK_MHZx2 95
#define CLOCK_MHZ_X2 95
/* Macros to manage access to the watchdog timer */
@@ -99,7 +99,8 @@ static int wdt_interrupt(int irq, void *context, FAR void *arg);
static int wdt_open(struct file *filep);
static int wdt_close(struct file *filep);
static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen);
static ssize_t wdt_write(struct file *filep, const char *buffer, size_t buflen);
static ssize_t wdt_write(struct file *filep, const char *buffer,
size_t buflen);
static int wdt_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
/****************************************************************************
@@ -184,7 +185,7 @@ static int wdt_setusec(uint32_t usec)
do
{
divisor = (CLOCK_MHZx2 * usec) / (prescaler * 2);
divisor = (CLOCK_MHZ_X2 * usec) / (prescaler * 2);
wdinfo("divisor=0x%x prescaler=0x%x\n", divisor, prescaler);
if (divisor >= 0x10000)
@@ -261,9 +262,11 @@ static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen)
wdinfo("buflen=%d\n", buflen);
if (buflen >= 18)
{
sprintf(buffer, "%08x %08x\n", c5471_wdt_cntl, c5471_wdt_count);
sprintf(buffer, "%08" PRIx32 " %08" PRIx32 "\n",
c5471_wdt_cntl, c5471_wdt_count);
return 18;
}
return 0;
}
@@ -271,7 +274,8 @@ static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen)
* Name: wdt_write
****************************************************************************/
static ssize_t wdt_write(struct file *filep, const char *buffer, size_t buflen)
static ssize_t wdt_write(struct file *filep, const char *buffer,
size_t buflen)
{
wdinfo("buflen=%d\n", buflen);
if (buflen)
arch/arm/src/common/arm_internal.h
+1 -1
View File
@@ -212,7 +212,7 @@ EXTERN volatile uint32_t *g_current_regs[1];
* CONFIG_RAM_END
*/
EXTERN const uint32_t g_idle_topstack;
EXTERN const uintptr_t g_idle_topstack;
/* Address of the saved user stack pointer */
arch/arm/src/common/arm_interruptcontext.c
-6
View File
@@ -60,12 +60,6 @@
bool up_interrupt_context(void)
{
#ifdef CONFIG_SMP
/* REVISIT: Currently up_irq_save() will not disable the Software
* Generated Interrupts (SGIs) for the case of ARMv7-A architecture using
* the GIC. So this will not be sufficient in that case, at least not
* until we add support for the ICCMPR.
*/
irqstate_t flags = up_irq_save();
#endif
arch/arm/src/common/arm_vfork.c
+9 -6
View File
@@ -24,6 +24,7 @@
#include <nuttx/config.h>
#include <inttypes.h>
#include <stdint.h>
#include <string.h>
#include <assert.h>
@@ -108,11 +109,12 @@ pid_t up_vfork(const struct vfork_s *context)
int ret;
sinfo("vfork context [%p]:\n", context);
sinfo(" r4:%08x r5:%08x r6:%08x r7:%08x\n",
sinfo(" r4:%08" PRIx32 " r5:%08" PRIx32
" r6:%08" PRIx32 " r7:%08" PRIx32 "\n",
context->r4, context->r5, context->r6, context->r7);
sinfo(" r8:%08x r9:%08x r10:%08x\n",
sinfo(" r8:%08" PRIx32 " r9:%08" PRIx32 " r10:%08" PRIx32 "\n",
context->r8, context->r9, context->r10);
sinfo(" fp:%08x sp:%08x lr:%08x\n",
sinfo(" fp:%08" PRIx32 " sp:%08" PRIx32 " lr:%08" PRIx32 "\n",
context->fp, context->sp, context->lr);
/* Allocate and initialize a TCB for the child task. */
@@ -155,7 +157,8 @@ pid_t up_vfork(const struct vfork_s *context)
DEBUGASSERT((uint32_t)parent->adj_stack_ptr > context->sp);
stackutil = (uint32_t)parent->adj_stack_ptr - context->sp;
sinfo("Parent: stacksize:%d stackutil:%d\n", stacksize, stackutil);
sinfo("Parent: stacksize:%zu stackutil:%" PRId32 "\n",
stacksize, stackutil);
/* Make some feeble effort to preserve the stack contents. This is
* feeble because the stack surely contains invalid pointers and other
@@ -180,9 +183,9 @@ pid_t up_vfork(const struct vfork_s *context)
newfp = context->fp;
}
sinfo("Parent: stack base:%08x SP:%08x FP:%08x\n",
sinfo("Parent: stack base:%p SP:%08" PRIx32 " FP:%08" PRIx32 "\n",
parent->adj_stack_ptr, context->sp, context->fp);
sinfo("Child: stack base:%08x SP:%08x FP:%08x\n",
sinfo("Child: stack base:%p SP:%08" PRIx32 " FP:%08" PRIx32 "\n",
child->cmn.adj_stack_ptr, newsp, newfp);
/* Update the stack pointer, frame pointer, and volatile registers. When
arch/arm/src/cxd56xx/cxd56_allocateheap.c
+1 -1
View File
@@ -69,7 +69,7 @@
* aligned).
*/
const uint32_t g_idle_topstack = (uint32_t)&_ebss +
const uintptr_t g_idle_topstack = (uintptr_t)&_ebss +
CONFIG_IDLETHREAD_STACKSIZE;
/****************************************************************************
arch/arm/src/cxd56xx/cxd56_irq.c
+1 -1
View File
@@ -277,7 +277,7 @@ static inline void cxd56_prioritize_syscall(int priority)
}
#endif
static int excinfo(int irq, uint32_t *regaddr, uint32_t *bit)
static int excinfo(int irq, uintptr_t *regaddr, uint32_t *bit)
{
*regaddr = NVIC_SYSHCON;
switch (irq)
arch/arm/src/cxd56xx/cxd56_serial.c
+2 -2
View File
@@ -121,7 +121,7 @@ static int up_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
static bool up_rxflowcontrol(FAR struct uart_dev_s *dev,
unsigned int nbuffered, bool upper);
#endif
static int up_receive(FAR struct uart_dev_s *dev, FAR uint32_t *status);
static int up_receive(FAR struct uart_dev_s *dev, FAR unsigned int *status);
static void up_rxint(FAR struct uart_dev_s *dev, bool enable);
static bool up_rxavailable(FAR struct uart_dev_s *dev);
static void up_send(FAR struct uart_dev_s *dev, int ch);
@@ -916,7 +916,7 @@ static int up_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
*
****************************************************************************/
static int up_receive(FAR struct uart_dev_s *dev, FAR uint32_t *status)
static int up_receive(FAR struct uart_dev_s *dev, FAR unsigned int *status)
{
FAR struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
uint32_t rbr;
arch/arm/src/dm320/dm320_serial.c
+18 -13
View File
@@ -1,7 +1,8 @@
/****************************************************************************
* arch/arm/src/dm320/dm320_serial.c
*
* Copyright (C) 2007-2009, 2012-2013, 2017 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2009, 2012-2013, 2017 Gregory Nutt.
* All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -89,7 +90,7 @@ static int up_attach(struct uart_dev_s *dev);
static void up_detach(struct uart_dev_s *dev);
static int up_interrupt(int irq, void *context, void *arg);
static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
static int up_receive(struct uart_dev_s *dev, uint32_t *status);
static int up_receive(struct uart_dev_s *dev, unsigned int *status);
static void up_rxint(struct uart_dev_s *dev, bool enable);
static bool up_rxavailable(struct uart_dev_s *dev);
static void up_send(struct uart_dev_s *dev, int ch);
@@ -178,7 +179,7 @@ static uart_dev_t g_uart1port =
{
.size = CONFIG_UART1_TXBUFSIZE,
.buffer = g_uart1txbuffer,
},
},
.ops = &g_uart_ops,
.priv = &g_uart1priv,
};
@@ -212,7 +213,8 @@ static inline uint16_t up_serialin(struct up_dev_s *priv, uint32_t offset)
* Name: up_serialout
****************************************************************************/
static inline void up_serialout(struct up_dev_s *priv, uint32_t offset, uint16_t value)
static inline void up_serialout(struct up_dev_s *priv, uint32_t offset,
uint16_t value)
{
putreg16(value, priv->uartbase + offset);
}
@@ -410,14 +412,15 @@ static void up_shutdown(struct uart_dev_s *dev)
* Name: up_attach
*
* Description:
* Configure the UART to operation in interrupt driven mode. This method is
* called when the serial port is opened. Normally, this is just after the
* Configure the UART to operation in interrupt driven mode. This method
* is called when the serial port is opened. Normally, this is just after
* the setup() method is called, however, the serial console may operate in
* a non-interrupt driven mode during the boot phase.
*
* RX and TX interrupts are not enabled when by the attach method (unless the
* hardware supports multiple levels of interrupt enabling). The RX and TX
* interrupts are not enabled until the txint() and rxint() methods are called.
* RX and TX interrupts are not enabled when by the attach method (unless
* the hardware supports multiple levels of interrupt enabling). The RX
* and TX interrupts are not enabled until the txint() and rxint() methods
* are called.
*
****************************************************************************/
@@ -437,6 +440,7 @@ static int up_attach(struct uart_dev_s *dev)
up_enable_irq(priv->irq);
}
return ret;
}
@@ -445,8 +449,8 @@ static int up_attach(struct uart_dev_s *dev)
*
* Description:
* Detach UART interrupts. This method is called when the serial port is
* closed normally just before the shutdown method is called. The exception is
* the serial console which is never shutdown.
* closed normally just before the shutdown method is called. The
* exception is the serial console which is never shutdown.
*
****************************************************************************/
@@ -588,7 +592,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
*
****************************************************************************/
static int up_receive(struct uart_dev_s *dev, uint32_t *status)
static int up_receive(struct uart_dev_s *dev, unsigned int *status)
{
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
uint16_t dtrr;
@@ -619,6 +623,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
{
priv->msr &= ~UART_MSR_RFTIE;
}
up_serialout(priv, UART_MSR, priv->msr);
}
@@ -671,6 +676,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
{
priv->msr &= ~UART_MSR_TFTIE;
}
up_serialout(priv, UART_MSR, priv->msr);
}
@@ -799,7 +805,6 @@ static inline void up_waittxready(void)
for (tmp = 1000 ; tmp > 0 ; tmp--)
{
if ((getreg16(DM320_REGISTER_BASE + UART_SR) & UART_SR_TFTI) != 0)
{
break;
arch/arm/src/efm32/efm32_leserial.c
+2 -2
View File
@@ -167,7 +167,7 @@ static int efm32_attach(struct uart_dev_s *dev);
static void efm32_detach(struct uart_dev_s *dev);
static int efm32_interrupt(int irq, void *context, FAR void *arg);
static int efm32_ioctl(struct file *filep, int cmd, unsigned long arg);
static int efm32_receive(struct uart_dev_s *dev, uint32_t *status);
static int efm32_receive(struct uart_dev_s *dev, unsigned int *status);
static void efm32_rxint(struct uart_dev_s *dev, bool enable);
static bool efm32_rxavailable(struct uart_dev_s *dev);
static void efm32_send(struct uart_dev_s *dev, int ch);
@@ -583,7 +583,7 @@ static int efm32_ioctl(struct file *filep, int cmd, unsigned long arg)
*
****************************************************************************/
static int efm32_receive(struct uart_dev_s *dev, uint32_t *status)
static int efm32_receive(struct uart_dev_s *dev, unsigned int *status)
{
struct efm32_leuart_s *priv = (struct efm32_leuart_s *)dev->priv;
uint32_t rxdatax;
arch/arm/src/eoss3/eoss3_serial.c
+3 -3
View File
@@ -80,7 +80,7 @@ static int eoss3_attach(struct uart_dev_s *dev);
static void eoss3_detach(struct uart_dev_s *dev);
static int eoss3_interrupt(int irq, void *context, FAR void *arg);
static int eoss3_ioctl(struct file *filep, int cmd, unsigned long arg);
static int eoss3_receive(struct uart_dev_s *dev, uint32_t *status);
static int eoss3_receive(struct uart_dev_s *dev, unsigned int *status);
static void eoss3_rxint(struct uart_dev_s *dev, bool enable);
static bool eoss3_rxavailable(struct uart_dev_s *dev);
static void eoss3_send(struct uart_dev_s *dev, int ch);
@@ -414,7 +414,7 @@ static int eoss3_ioctl(struct file *filep, int cmd, unsigned long arg)
*
****************************************************************************/
static int eoss3_receive(struct uart_dev_s *dev, uint32_t *status)
static int eoss3_receive(struct uart_dev_s *dev, unsigned int *status)
{
*status = getreg32(EOSS3_UART_RSR_ECR);
return (getreg32(EOSS3_UART_DR) & UART_DR_DATA_MASK);
@@ -633,4 +633,4 @@ int up_putc(int ch)
return ch;
}
#endif /* USE_SERIALDRIVER */
#endif /* USE_SERIALDRIVER */
arch/arm/src/imx1/imx_serial.c
+22 -14
View File
@@ -100,7 +100,8 @@ struct up_dev_s
****************************************************************************/
static inline uint32_t up_serialin(struct up_dev_s *priv, uint32_t offset);
static inline void up_serialout(struct up_dev_s *priv, uint32_t offset, uint32_t value);
static inline void up_serialout(struct up_dev_s *priv, uint32_t offset,
uint32_t value);
static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *ucr1);
static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t ucr1);
static inline void up_waittxready(struct up_dev_s *priv);
@@ -111,7 +112,7 @@ static int up_attach(struct uart_dev_s *dev);
static void up_detach(struct uart_dev_s *dev);
static int up_interrupt(int irq, void *context, FAR void *arg);
static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
static int up_receive(struct uart_dev_s *dev, uint32_t *status);
static int up_receive(struct uart_dev_s *dev, unsigned int *status);
static void up_rxint(struct uart_dev_s *dev, bool enable);
static bool up_rxavailable(struct uart_dev_s *dev);
static void up_send(struct uart_dev_s *dev, int ch);
@@ -223,7 +224,7 @@ static struct uart_dev_s g_uart2port =
{
.size = CONFIG_UART2_TXBUFSIZE,
.buffer = g_uart2txbuffer,
},
},
.ops = &g_uart_ops,
.priv = &g_uart2priv,
};
@@ -385,7 +386,8 @@ static inline uint32_t up_serialin(struct up_dev_s *priv, uint32_t offset)
* Name: up_serialout
****************************************************************************/
static inline void up_serialout(struct up_dev_s *priv, uint32_t offset, uint32_t value)
static inline void up_serialout(struct up_dev_s *priv, uint32_t offset,
uint32_t value)
{
putreg32(value, priv->uartbase + offset);
}
@@ -554,7 +556,7 @@ static int up_setup(struct uart_dev_s *dev)
*/
tmp = ((uint64_t)refclk << (16 - 4)) / config->baud;
DEBUGASSERT(tmp < 0x0000000100000000LL);
DEBUGASSERT(tmp < 0x0000000100000000ll);
ratio = (b16_t)tmp;
/* Pick a scale factor that gives us about 14 bits of accuracy.
@@ -679,9 +681,11 @@ static int up_setup(struct uart_dev_s *dev)
{
div = 6 - div;
}
regval = div << UART_UFCR_RFDIV_SHIFT;
/* Set the TX trigger level to interrupt when the TxFIFO has 2 or fewer characters.
/* Set the TX trigger level to interrupt when the TxFIFO has 2 or fewer
* characters.
* Set the RX trigger level to interrupt when the RxFIFO has 1 character.
*/
@@ -731,14 +735,15 @@ static void up_shutdown(struct uart_dev_s *dev)
* Name: up_attach
*
* Description:
* Configure the UART to operation in interrupt driven mode. This method is
* called when the serial port is opened. Normally, this is just after the
* Configure the UART to operation in interrupt driven mode. This method
* is called when the serial port is opened. Normally, this is just after
* the setup() method is called, however, the serial console may operate in
* a non-interrupt driven mode during the boot phase.
*
* RX and TX interrupts are not enabled when by the attach method (unless the
* hardware supports multiple levels of interrupt enabling). The RX and TX
* interrupts are not enabled until the txint() and rxint() methods are called.
* RX and TX interrupts are not enabled when by the attach method (unless
* the hardware supports multiple levels of interrupt enabling). The RX
* and TX interrupts are not enabled until the txint() and rxint() methods
* are called.
*
****************************************************************************/
@@ -779,6 +784,7 @@ static int up_attach(struct uart_dev_s *dev)
up_enable_irq(priv->irq);
}
#endif
return ret;
}
@@ -787,8 +793,8 @@ static int up_attach(struct uart_dev_s *dev)
*
* Description:
* Detach UART interrupts. This method is called when the serial port is
* closed normally just before the shutdown method is called. The exception is
* the serial console which is never shutdown.
* closed normally just before the shutdown method is called. The
* exception is the serial console which is never shutdown.
*
****************************************************************************/
@@ -925,7 +931,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
*
****************************************************************************/
static int up_receive(struct uart_dev_s *dev, uint32_t *status)
static int up_receive(struct uart_dev_s *dev, unsigned int *status)
{
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
uint32_t rxd0;
@@ -959,6 +965,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
{
priv->ucr1 &= ~UART_UCR1_RRDYEN;
}
up_serialout(priv, UART_UCR1, priv->ucr1);
}
@@ -1019,6 +1026,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
{
priv->ucr1 &= ~UART_UCR1_TXEMPTYEN;
}
up_serialout(priv, UART_UCR1, priv->ucr1);
}
arch/arm/src/imx6/Make.defs
+4
View File
@@ -117,6 +117,10 @@ endif
CMN_CSRCS += arm_cache.c
ifeq ($(CONFIG_ARCH_L2CACHE),y)
CMN_CSRCS += arm_l2cc_pl310.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_savefpu.S arm_restorefpu.S
CMN_CSRCS += arm_copyarmstate.c
arch/arm/src/imx6/chip.h
+6
View File
@@ -61,6 +61,12 @@
#define CHIP_MPCORE_VBASE IMX_ARMMP_VSECTION
/* arch/arm/src/armv7-a/l2cc_pl310.h includes this file and expects it
* to provide the address of the L2CC-PL310 implementation.
*/
#define L2CC_VBASE IMX_PL310_VBASE
/****************************************************************************
* Macro Definitions
****************************************************************************/
arch/arm/src/imx6/imx_serial.c
+9 -8
View File
@@ -231,7 +231,7 @@ static int imx_attach(struct uart_dev_s *dev);
static void imx_detach(struct uart_dev_s *dev);
static int imx_interrupt(int irq, void *context, FAR void *arg);
static int imx_ioctl(struct file *filep, int cmd, unsigned long arg);
static int imx_receive(struct uart_dev_s *dev, uint32_t *status);
static int imx_receive(struct uart_dev_s *dev, unsigned int *status);
static void imx_rxint(struct uart_dev_s *dev, bool enable);
static bool imx_rxavailable(struct uart_dev_s *dev);
static void imx_send(struct uart_dev_s *dev, int ch);
@@ -349,7 +349,7 @@ static struct uart_dev_s g_uart2port =
{
.size = CONFIG_UART2_TXBUFSIZE,
.buffer = g_uart2txbuffer,
},
},
.ops = &g_uart_ops,
.priv = &g_uart2priv,
};
@@ -578,14 +578,15 @@ static void imx_shutdown(struct uart_dev_s *dev)
* Name: imx_attach
*
* Description:
* Configure the UART to operation in interrupt driven mode. This method is
* called when the serial port is opened. Normally, this is just after the
* Configure the UART to operation in interrupt driven mode. This method
* is called when the serial port is opened. Normally, this is just after
* the setup() method is called, however, the serial console may operate in
* a non-interrupt driven mode during the boot phase.
*
* RX and TX interrupts are not enabled when by the attach method (unless the
* hardware supports multiple levels of interrupt enabling). The RX and TX
* interrupts are not enabled until the txint() and rxint() methods are called.
* RX and TX interrupts are not enabled when by the attach method (unless
* the hardware supports multiple levels of interrupt enabling). The RX
* and TX interrupts are not enabled until the txint() and rxint() methods
* are called.
*
****************************************************************************/
@@ -746,7 +747,7 @@ static int imx_ioctl(struct file *filep, int cmd, unsigned long arg)
*
****************************************************************************/
static int imx_receive(struct uart_dev_s *dev, uint32_t *status)
static int imx_receive(struct uart_dev_s *dev, unsigned int *status)
{
struct imx_uart_s *priv = (struct imx_uart_s *)dev->priv;
uint32_t rxd0;
arch/arm/src/imxrt/imxrt_enet.c
+29
View File
@@ -186,6 +186,7 @@
*
* The imxrt1050-evk board uses a KSZ8081 PHY
* The Versiboard2 uses a LAN8720 PHY
* The Teensy-4.1 board uses a DP83825I PHY
*
* ...and further PHY descriptions here.
*/
@@ -208,6 +209,15 @@
# define BOARD_PHY_10BASET(s) (((s)&MII_LAN8720_SPSCR_10MBPS) != 0)
# define BOARD_PHY_100BASET(s) (((s)&MII_LAN8720_SPSCR_100MBPS) != 0)
# define BOARD_PHY_ISDUPLEX(s) (((s)&MII_LAN8720_SPSCR_DUPLEX) != 0)
#elif defined(CONFIG_ETH0_PHY_DP83825I)
# define BOARD_PHY_NAME "DP83825I"
# define BOARD_PHYID1 MII_PHYID1_DP83825I
# define BOARD_PHYID2 MII_PHYID2_DP83825I
# define BOARD_PHY_STATUS MII_DP83825I_PHYSTS
# define BOARD_PHY_ADDR (0)
# define BOARD_PHY_10BASET(s) (((s) & MII_DP83825I_PHYSTS_SPEED) != 0)
# define BOARD_PHY_100BASET(s) (((s) & MII_DP83825I_PHYSTS_SPEED) == 0)
# define BOARD_PHY_ISDUPLEX(s) (((s) & MII_DP83825I_PHYSTS_DUPLEX) != 0)
#else
# error "Unrecognized or missing PHY selection"
#endif
@@ -2164,6 +2174,25 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy)
/* ...and reset PHY */
imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET);
#elif defined (CONFIG_ETH0_PHY_DP83825I)
/* Reset PHY */
imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET);
/* Set RMII mode and Indicate 50MHz clock */
imxrt_writemii(priv, phyaddr, MII_DP83825I_RCSR,
MII_DP83825I_RCSC_ELAST_2 | MII_DP83825I_RCSC_RMIICS);
imxrt_writemii(priv, phyaddr, MII_ADVERTISE,
MII_ADVERTISE_100BASETXFULL |
MII_ADVERTISE_100BASETXHALF |
MII_ADVERTISE_10BASETXFULL |
MII_ADVERTISE_10BASETXHALF |
MII_ADVERTISE_CSMA);
#endif
/* Start auto negotiation */
arch/arm/src/imxrt/imxrt_serial.c
+2 -2
View File
@@ -366,7 +366,7 @@ static int imxrt_attach(struct uart_dev_s *dev);
static void imxrt_detach(struct uart_dev_s *dev);
static int imxrt_interrupt(int irq, void *context, FAR void *arg);
static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg);
static int imxrt_receive(struct uart_dev_s *dev, uint32_t *status);
static int imxrt_receive(struct uart_dev_s *dev, unsigned int *status);
static void imxrt_rxint(struct uart_dev_s *dev, bool enable);
static bool imxrt_rxavailable(struct uart_dev_s *dev);
static void imxrt_send(struct uart_dev_s *dev, int ch);
@@ -1385,7 +1385,7 @@ static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg)
*
****************************************************************************/
static int imxrt_receive(struct uart_dev_s *dev, uint32_t *status)
static int imxrt_receive(struct uart_dev_s *dev, unsigned int *status)
{
struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv;
uint32_t rxd;
arch/arm/src/kinetis/kinetis_lpserial.c
+45 -29
View File
@@ -85,7 +85,8 @@
#if defined(HAVE_LPUART_DEVICE) && defined(USE_SERIALDRIVER)
/* Which LPUART with be tty0/console and which tty1? The console will always
* be ttyS0. If there is no console then will use the lowest numbered LPUART.
* be ttyS0. If there is no console then will use the lowest numbered
* LPUART.
*/
/* First pick the console and ttys0. This could be any of LPUART0-4 */
@@ -130,7 +131,9 @@
# endif
#endif
/* Pick ttys1. This could be any of LPUART0-4 excluding the console/ttyS0 LPUART. */
/* Pick ttys1. This could be any of LPUART0-4 excluding the console/ttyS0
* LPUART.
*/
#if defined(CONFIG_KINETIS_LPUART0) && !defined(LPUART0_ASSIGNED)
# define TTYS1_DEV g_lpuart0port /* LPUART0 is ttyS1 */
@@ -149,7 +152,9 @@
# define LPUART4_ASSIGNED 1
#endif
/* Pick ttys2. This could be any of LPUART1-4 excluding the console/ttyS0 LPUART. */
/* Pick ttys2. This could be any of LPUART1-4 excluding the console/ttyS0
* LPUART.
*/
#if defined(CONFIG_KINETIS_LPUART1) && !defined(LPUART1_ASSIGNED)
# define TTYS2_DEV g_lpuart1port /* LPUART1 is ttyS2 */
@@ -165,7 +170,9 @@
# define LPUART4_ASSIGNED 1
#endif
/* Pick ttys3. This could be any of LPUART2-4 excluding the console/ttyS0 LPUART. */
/* Pick ttys3. This could be any of LPUART2-4 excluding the console/ttyS0
* LPUART.
*/
#if defined(CONFIG_KINETIS_LPUART2) && !defined(LPUART2_ASSIGNED)
# define TTYS3_DEV g_lpuart2port /* LPUART2 is ttyS3 */
@@ -178,7 +185,9 @@
# define LPUART4_ASSIGNED 1
#endif
/* Pick ttys3. This could be any of LPUART3-4 excluding the console/ttyS0 LPUART. */
/* Pick ttys3. This could be any of LPUART3-4 excluding the console/ttyS0
* LPUART.
*/
#if defined(CONFIG_KINETIS_LPUART3) && !defined(LPUART3_ASSIGNED)
# define TTYS4_DEV g_lpuart3port /* LPUART3 is ttyS4 */
@@ -248,7 +257,7 @@ static int kinetis_attach(struct uart_dev_s *dev);
static void kinetis_detach(struct uart_dev_s *dev);
static int kinetis_interrupt(int irq, void *context, void *arg);
static int kinetis_ioctl(struct file *filep, int cmd, unsigned long arg);
static int kinetis_receive(struct uart_dev_s *dev, uint32_t *status);
static int kinetis_receive(struct uart_dev_s *dev, unsigned int *status);
static void kinetis_rxint(struct uart_dev_s *dev, bool enable);
static bool kinetis_rxavailable(struct uart_dev_s *dev);
#ifdef CONFIG_SERIAL_IFLOWCONTROL
@@ -338,7 +347,7 @@ static uart_dev_t g_lpuart0port =
{
.size = CONFIG_LPUART0_TXBUFSIZE,
.buffer = g_lpuart0txbuffer,
},
},
.ops = &g_lpuart_ops,
.priv = &g_lpuart0priv,
};
@@ -377,7 +386,7 @@ static uart_dev_t g_lpuart1port =
{
.size = CONFIG_LPUART1_TXBUFSIZE,
.buffer = g_lpuart1txbuffer,
},
},
.ops = &g_lpuart_ops,
.priv = &g_lpuart1priv,
};
@@ -416,7 +425,7 @@ static uart_dev_t g_lpuart2port =
{
.size = CONFIG_LPUART2_TXBUFSIZE,
.buffer = g_lpuart2txbuffer,
},
},
.ops = &g_lpuart_ops,
.priv = &g_lpuart2priv,
};
@@ -455,7 +464,7 @@ static uart_dev_t g_lpuart3port =
{
.size = CONFIG_LPUART3_TXBUFSIZE,
.buffer = g_lpuart3txbuffer,
},
},
.ops = &g_lpuart_ops,
.priv = &g_lpuart3priv,
};
@@ -494,7 +503,7 @@ static uart_dev_t g_lpuart4port =
{
.size = CONFIG_LPUART4_TXBUFSIZE,
.buffer = g_lpuart4txbuffer,
},
},
.ops = &g_lpuart_ops,
.priv = &g_lpuart4priv,
};
@@ -533,7 +542,9 @@ static void kinetis_setuartint(struct kinetis_dev_s *priv)
irqstate_t flags;
uint32_t regval;
/* Re-enable/re-disable interrupts corresponding to the state of bits in ie */
/* Re-enable/re-disable interrupts corresponding to the state of bits in
* ie
*/
flags = enter_critical_section();
regval = kinetis_serialin(priv, KINETIS_LPUART_CTRL_OFFSET);
@@ -551,7 +562,9 @@ static void kinetis_restoreuartint(struct kinetis_dev_s *priv, uint32_t ie)
{
irqstate_t flags;
/* Re-enable/re-disable interrupts corresponding to the state of bits in ie */
/* Re-enable/re-disable interrupts corresponding to the state of bits in
* ie
*/
flags = enter_critical_section();
priv->ie = ie & LPUART_CTRL_ALL_INTS;
@@ -645,7 +658,8 @@ static void kinetis_shutdown(struct uart_dev_s *dev)
* Configure the LPUART to operation in interrupt driven mode. This
* method is called when the serial port is opened. Normally, this is
* just after the setup() method is called, however, the serial
* console may operate in a non-interrupt driven mode during the boot phase.
* console may operate in a non-interrupt driven mode during the boot
* phase.
*
* RX and TX interrupts are not enabled when by the attach method (unless
* the hardware supports multiple levels of interrupt enabling). The RX
@@ -718,14 +732,15 @@ static int kinetis_interrupt(int irq, void *context, void *arg)
DEBUGASSERT(dev != NULL && dev->priv != NULL);
priv = (struct kinetis_dev_s *)dev->priv;
/* Read status register and qualify it with STAT bit corresponding CTRL IE bits */
/* Read status register and qualify it with STAT bit corresponding CTRL IE
* bits
*/
stat = kinetis_serialin(priv, KINETIS_LPUART_STAT_OFFSET);
ctrl = kinetis_serialin(priv, KINETIS_LPUART_CTRL_OFFSET);
stat &= LPUART_CTRL2STAT(ctrl);
do
{
/* Handle errors. This interrupt may be caused by:
*
* OR: Receiver Overrun Flag. To clear OR, when STAT read with OR set,
@@ -740,7 +755,6 @@ static int kinetis_interrupt(int irq, void *context, void *arg)
if (stat & LPUART_STAT_ERRORS)
{
/* Only Overrun error does not need a read operation */
if ((stat & LPUART_STAT_OR) != LPUART_STAT_OR)
@@ -781,7 +795,9 @@ static int kinetis_interrupt(int irq, void *context, void *arg)
uart_xmitchars(dev);
}
/* Read status register and requalify it with STAT bit corresponding CTRL IE bits */
/* Read status register and requalify it with STAT bit corresponding
* CTRL IE bits
*/
stat = kinetis_serialin(priv, KINETIS_LPUART_STAT_OFFSET);
ctrl = kinetis_serialin(priv, KINETIS_LPUART_CTRL_OFFSET);
@@ -850,7 +866,7 @@ static int kinetis_ioctl(struct file *filep, int cmd, unsigned long arg)
{
if ((arg & SER_SINGLEWIRE_PULLUP) != 0)
{
ret = -EINVAL; // Not supported
ret = -EINVAL; /* Not supported */
break;
}
@@ -888,9 +904,9 @@ static int kinetis_ioctl(struct file *filep, int cmd, unsigned long arg)
cfsetispeed(termiosp, priv->baud);
/* Note: CSIZE only supports 5-8 bits. The driver only support 8/9 bit
* modes and therefore is no way to report 9-bit mode, we always claim
* 8 bit mode.
/* Note: CSIZE only supports 5-8 bits. The driver only support 8/9
* bit modes and therefore is no way to report 9-bit mode, we always
* claim 8 bit mode.
*/
termiosp->c_cflag =
@@ -1060,7 +1076,7 @@ static int kinetis_ioctl(struct file *filep, int cmd, unsigned long arg)
*
****************************************************************************/
static int kinetis_receive(struct uart_dev_s *dev, uint32_t *status)
static int kinetis_receive(struct uart_dev_s *dev, unsigned int *status)
{
struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev->priv;
uint32_t regval;
@@ -1363,7 +1379,7 @@ unsigned int kinetis_lpuart_serialinit(unsigned int first)
char devname[] = "/dev/ttySx";
#endif
/* Register the console */
/* Register the console */
#ifdef HAVE_LPUART_CONSOLE
uart_register("/dev/console", &CONSOLE_DEV);
@@ -1387,22 +1403,22 @@ unsigned int kinetis_lpuart_serialinit(unsigned int first)
#else
devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
devname[(sizeof(devname) / sizeof(devname[0])) - 2] = '0' + first++;
uart_register(devname, &TTYS0_DEV);
#ifdef TTYS1_DEV
devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
devname[(sizeof(devname) / sizeof(devname[0])) - 2] = '0' + first++;
uart_register(devname, &TTYS1_DEV);
#endif
#ifdef TTYS2_DEV
devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
devname[(sizeof(devname) / sizeof(devname[0])) - 2] = '0' + first++;
uart_register(devname, &TTYS2_DEV);
#endif
#ifdef TTYS3_DEV
devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
devname[(sizeof(devname) / sizeof(devname[0])) - 2] = '0' + first++;
uart_register(devname, &TTYS3_DEV);
#endif
#ifdef TTYS4_DEV
devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
devname[(sizeof(devname) / sizeof(devname[0])) - 2] = '0' + first++;
uart_register(devname, &TTYS4_DEV);
#endif
#endif
arch/arm/src/kinetis/kinetis_sdhc.c
+1 -1
View File
@@ -310,7 +310,7 @@ static void kinetis_blocksetup(FAR struct sdio_dev_s *dev,
static int kinetis_recvsetup(FAR struct sdio_dev_s *dev,
FAR uint8_t *buffer, size_t nbytes);
static int kinetis_sendsetup(FAR struct sdio_dev_s *dev,
FAR const uint8_t *buffer, uint32_t nbytes);
FAR const uint8_t *buffer, size_t nbytes);
#endif
static int kinetis_cancel(FAR struct sdio_dev_s *dev);
arch/arm/src/kinetis/kinetis_serial.c
+2 -2
View File
@@ -343,7 +343,7 @@ static int up_interrupts(int irq, void *context, FAR void *arg);
static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
static void up_rxint(struct uart_dev_s *dev, bool enable);
#if !defined(SERIAL_HAVE_ALL_DMA)
static int up_receive(struct uart_dev_s *dev, uint32_t *status);
static int up_receive(struct uart_dev_s *dev, unsigned int *status);
static bool up_rxavailable(struct uart_dev_s *dev);
#endif
#ifdef CONFIG_SERIAL_IFLOWCONTROL
@@ -1567,7 +1567,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
****************************************************************************/
#if !defined(SERIAL_HAVE_ALL_DMA)
static int up_receive(struct uart_dev_s *dev, uint32_t *status)
static int up_receive(struct uart_dev_s *dev, unsigned int *status)
{
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
uint8_t s1;
arch/arm/src/kl/kl_serial.c
+2 -2
View File
@@ -173,7 +173,7 @@ static int up_attach(struct uart_dev_s *dev);
static void up_detach(struct uart_dev_s *dev);
static int up_interrupts(int irq, void *context, void *arg);
static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
static int up_receive(struct uart_dev_s *dev, uint32_t *status);
static int up_receive(struct uart_dev_s *dev, unsigned int *status);
static void up_rxint(struct uart_dev_s *dev, bool enable);
static bool up_rxavailable(struct uart_dev_s *dev);
static void up_send(struct uart_dev_s *dev, int ch);
@@ -635,7 +635,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
*
****************************************************************************/
static int up_receive(struct uart_dev_s *dev, uint32_t *status)
static int up_receive(struct uart_dev_s *dev, unsigned int *status)
{
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
uint8_t s1;
arch/arm/src/kl/kl_start.c
+3 -1
View File
@@ -80,7 +80,7 @@
* Public Data
****************************************************************************/
const uint32_t g_idle_topstack = IDLE_STACK;
const uintptr_t g_idle_topstack = IDLE_STACK;
/****************************************************************************
* Private Functions
@@ -135,6 +135,7 @@ void __start(void)
{
*dest++ = 0;
}
showprogress('B');
/* Move the initialized data section from his temporary holding spot in
@@ -147,6 +148,7 @@ void __start(void)
{
*dest++ = *src++;
}
showprogress('C');
/* Perform early serial initialization */

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