diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index f6649fd191f..3825b4f6757 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -14,6 +14,12 @@ it is very important you follow these guidelines: + + * The first line should have a prefix to give context + (unless context is really clear), such as: + + : + i.e sched: Fixed compiler warning * Be sure to **fill in** the pull-request template with meaningful content (be very descriptive, take your time). diff --git a/Documentation/_static/custom.css b/Documentation/_static/custom.css index a861bdb1140..521e0f7f7b4 100644 --- a/Documentation/_static/custom.css +++ b/Documentation/_static/custom.css @@ -78,3 +78,11 @@ kbd { -webkit-border-radius: 3px; text-shadow: 0 1px 0 #fff; } + +span.menuselection +{ + margin: 0px 0.1em; + padding: 0.1em 0.1em; + border-radius: 3px; + border: 1px solid rgb(204, 204, 204); +} diff --git a/Documentation/components/drivers/character/pwm.rst b/Documentation/components/drivers/character/pwm.rst index 918c0c107ae..62226378a31 100644 --- a/Documentation/components/drivers/character/pwm.rst +++ b/Documentation/components/drivers/character/pwm.rst @@ -22,12 +22,12 @@ Files supporting PWM can be found in the following locations: file includes both the application level interface to the PWM driver as well as the interface between the "upper half" and "lower half" drivers. The PWM module uses a standard character - driver framework. However, since the PWM driver is a devices + driver framework. However, since the PWM driver is a device control interface and not a data transfer interface, the majority of the functionality available to the application is implemented in driver ioctl calls. - **"Upper Half" Driver**. The generic, "upper half" PWM driver - resides at ``drivers/pwm.c``. + resides at ``drivers/timers/pwm.c``. - **"Lower Half" Drivers**. Platform-specific PWM drivers reside in ``arch/``\ **\ ``/src/``\ ** directory for the specific processor ** and for diff --git a/Documentation/components/drivers/character/watchdog.rst b/Documentation/components/drivers/character/watchdog.rst index 94a28c95b06..21092c57af3 100644 --- a/Documentation/components/drivers/character/watchdog.rst +++ b/Documentation/components/drivers/character/watchdog.rst @@ -27,3 +27,130 @@ following locations: ``arch/``\ **\ ``/src/``\ ** directory for the specific processor ** and for the specific ** watchdog timer peripheral devices. + +There are two ways to enable Watchdog Timer Support along with the Watchdog Example. The first is faster and simpler. Just run the following command to use a ready config file with watchdog timer support and example included. You need to check if there's a watchdog config file for your specific chip. You may check it at the specific board's path: ``/boards////config``. + +.. code-block:: console + + $ ./tools/configure.sh :watchdog + +And the second way is creating your own config file. To do so, follow the next instructions. + +Enabling the Watchdog Support and Example in ``menuconfing`` +------------------------------------------------------------ + +1. Select Watchdog Timer Instances + + To select these wdts browse in the ``menuconfig`` using the following path: + + Go into menu :menuselection:`System Type --> Peripheral Selection` and press :kbd:`Enter`. Then select one or more watchdog timers according to availability of your chip. + +2. Enable the Watchdog Timer Support + + Go into menu :menuselection:`Device Drivers --> Timer Driver Support` and press :kbd:`Enter`. Then enable: + + - [x] Watchdog Timer Support + +3. Include the Watchdog Timer Example + + Go into menu :menuselection:`Application Configuration --> Examples` and press :kbd:`Enter`. Then select the Watchdog Timer example. + + - [x] Watchdog Timer example + + Below the option, it is possible to manually configure some standard parameters that will be used by the example, but they also can be passed as command line arguments later. + The parameters are the following: the standard timer device path (which defines the WDT instance), the timeout period (which is the period on which the watchdog will expire), + the ping delay (which is the interval period between feeding the dog) and the ping time (which is the total interval that the example will feed the dog, after this interval, + the dog will starve and the chip will trigger an interrupt or reset. + +4. Include the Debug Watchdog Feature + + In order to get the watchdog timer status, you need to enable it. For production code and for your application you may disable it. + + Go into menu :menuselection:`Build Setup --> Debug Options` and press :kbd:`Enter`. Then enable: + + - [x] Enable Debug Features + - [x] Watchdog Timer Debug Features + +Watchdog Timer Example +---------------------- + +The previously selected example will basically do the following: + +* Open the watchdog device +* Set the watchdog timeout +* Start the watchdog timer +* Ping (feed the dog) during the ``pingtime`` with a delay of ``pingdelay`` and print out the wdt status in case debug was enabled. +* Enter into an endless loop without pinging. It will cause the watchdog timer to reset the chip on timeout, i.e., after timer expiration. + + +The `example code `_ may be explored, its path is at ``/examples/watchdog/watchdog_main.c`` in the apps' repository. + +In NuttX, the watchdog timer driver is a character driver and when a chip supports multiple watchdog timers, each one is accessible through its respective special file in ``/dev`` directory. Each watchdog timer is registered using a unique numeric identifier (i.e. ``/dev/watchdog0``, ``/dev/watchdog1``, ...). + +Use the following command to run the example: + +.. code-block:: console + + nsh> wdog + +This command will use the watchdog timer 0. To use the others, specify it through a parameter (where x is the timer number): + +.. code-block:: console + + nsh> wdog -i /dev/watchdogx + +Application Level Interface +---------------------------- + +The first necessary thing to be done in order to use the watchdog timer driver in an application is to include the header file for the NuttX Watchdog timer driver. It contains the Application Level Interface to the timer driver. To do so, include: + +.. code-block:: c + + #include + + +At an application level, the watchdog timer functionalities may be accessed through ``ioctl`` systems calls. These ``ioctl`` commands internally call lower-half layer operations and the parameters are forwarded to these operations through the ``ioctl`` system call. The example provides a great resource to demonstrate how to use those ``ioctl`` commands. The available ``ioctl`` commands are: + +.. c:macro:: WDIOC_START + +This command starts the watchdog timer. + +.. c:macro:: WDIOC_STOP + +This command stops the watchdog timer. + +.. c:macro:: WDIOC_GETSTATUS + +This command gets the status of the watchdog timer. It receives a writeable pointer to struct ``watchdog_status_s`` as parameter. The lower-half driver writes the current status in this struct. + +.. c:struct:: watchdog_status_s +.. code-block:: c + + struct watchdog_status_s + { + uint32_t flags; /* See WDFLAGS_* definitions above */ + uint32_t timeout; /* The current timeout setting (in milliseconds) */ + uint32_t timeleft; /* Time left until the watchdog expiration + * (in milliseconds) */ + }; + +.. c:macro:: WDIOC_SETTIMEOUT + +This command sets the timeout value, i.e., the value that will trigger the reset or interrupt. The argument is a ``uint32_t`` value in miliseconds. + +.. c:macro:: WDIOC_CAPTURE + +This command registers an user callback that will be triggered on timeout. It receives as argument a pointer to struct ``watchdog_capture_s``. If the user callback is NULL, then it configures only to reset. Not all chips support interrupt on timeout. This command is optional, i.e., if it's not used, the standard behaviour is to reset on timeout. + +.. c:struct:: watchdog_capture_s +.. code-block:: c + + struct watchdog_capture_s + { + CODE xcpt_t newhandler; /* The new watchdog capture handler */ + CODE xcpt_t oldhandler; /* The previous watchdog capture handler (if any) */ + }; + +.. c:macro:: WDIOC_KEEPALIVE + + This command resets the watchdog timer ("ping", "pet the dog", "feed the dog"). \ No newline at end of file diff --git a/Documentation/components/power.rst b/Documentation/components/power.rst index 7b9e35aa7db..7d967192aa2 100644 --- a/Documentation/components/power.rst +++ b/Documentation/components/power.rst @@ -2,6 +2,10 @@ Power Management ================ +.. todo:: + This needs to be updated to account for the different governors + besides the activity-based one. + NuttX supports a simple power management (PM) sub-system which: - Monitors activity from drivers (and from other parts of the diff --git a/Documentation/index.rst b/Documentation/index.rst index 26a1338ca33..832c250c892 100644 --- a/Documentation/index.rst +++ b/Documentation/index.rst @@ -20,15 +20,14 @@ Last Updated: |today| :maxdepth: 2 Home + introduction/index.rst quickstart/index.rst introduction/inviolables.rst - introduction/index.rst boards/index.rst components/index.rst applications/index.rst - guides/index.rst reference/index.rst - releases/index.rst + guides/index.rst contributing/index.rst glossary.rst diff --git a/Documentation/introduction/about.rst b/Documentation/introduction/about.rst index fdee8aa8ae0..7c76e86b84f 100644 --- a/Documentation/introduction/about.rst +++ b/Documentation/introduction/about.rst @@ -1,9 +1,6 @@ -=========== -About NuttX -=========== - -Goals -===== +================== +About Apache NuttX +================== NuttX is a real time embedded operating system (RTOS). Its goals are: diff --git a/Documentation/introduction/trademarks.rst b/Documentation/introduction/trademarks.rst index 025db4e8ce3..01f81b999b0 100644 --- a/Documentation/introduction/trademarks.rst +++ b/Documentation/introduction/trademarks.rst @@ -1,5 +1,3 @@ -.. todo:: Revise status of NuttX trademark - ========== Trademarks ========== diff --git a/Documentation/quickstart/build_and_make.rst b/Documentation/quickstart/build_and_make.rst deleted file mode 100644 index e69bd09e21c..00000000000 --- a/Documentation/quickstart/build_and_make.rst +++ /dev/null @@ -1,59 +0,0 @@ -.. include:: /substitutions.rst -.. _build_and_make: - -Build and Make Details -====================== - -This is included for reference, and it's not necessary to know all these details. - -As described in :ref:`compiling`, you use ``make`` at the root ``nuttx/`` directory to build NuttX. This is also -referenced as ``$(TOPDIR)`` in the ``Makefile``. - -Root Directory --------------- - -The ``$(TOPDIR)`` directory holds: - -- The top level ```Makefile`` <#topmakefile>`__ that controls the - NuttX build. - -That directory also holds: - -- The makefile fragment :ref:`.config ` - that describes the current configuration, and -- The makefile fragment :ref:`Make.defs ` - that provides customized build targets. - -Environment Variables ---------------------- - -The specific environmental definitions -are unique for each board but should include, as a minimum, -updates to the ``PATH`` variable to include the full path to the -architecture-specific toolchain identified in -:ref:`Make.defs `. - -First Time Make ---------------- - -Additional configuration actions will be taken the first time that system is built. These additional steps -include: - -- Auto-generating the file ``include/nuttx/config.h`` using the - ``$(TOPDIR)/.config`` file. -- Auto-generating the file ``$(TOPDIR)/.version`` with version - 0.0 if one does not exist. -- Auto-generating the file ``include/nuttx/version.h`` using the - ``$(TOPDIR)/.version`` file. -- Creating a link to - ``$(TOPDIR)/arch/``\ **\ ``/include`` at - ``$(TOPDIR)/include/arch``. -- Creating a link to - ``$(TOPDIR)/boards/``\ **\ ``/``\ **\ ``/``\ **\ ``/include`` - at ``$(TOPDIR)/include/arch/board``. -- Creating a link to - ``$(TOPDIR)/boards/``\ **\ ``/``\ **\ ``/``\ **\ ``/src`` - at ``$(TOPDIR)/arch/``\ **\ ``/src/board`` -- Creating a link to ``${APPDIR}/include`` at - ``$(TOPDIR)/include/apps`` -- Creating make dependencies. diff --git a/Documentation/quickstart/compiling.rst b/Documentation/quickstart/compiling.rst index 55f81d13507..b2c5fd632c5 100644 --- a/Documentation/quickstart/compiling.rst +++ b/Documentation/quickstart/compiling.rst @@ -36,23 +36,15 @@ to ``configure.sh`` and indicate your host platform, such as: The ``-l`` tells use that we're on Linux (macOS and Windows builds are possible). Use the ``-h`` argument to see all available options. -Customize Your Configuration (Optional) -======================================= - -This step is optional. Right now, this is mainly to get familiar with how it -works– you don't need to change any of the options now, but knowing how -to do this will come in handy later. - -There are a lot of options. We'll cover a few of them here. -Don't worry about the complexity– you don't have to use most of the options. +You can then customize this configuration by using the menu based +configuration system with: .. code-block:: console $ cd nuttx/ $ make menuconfig - -.. todo:: - Explain some useful options. + +Modifying the configuration is covered in :doc:`configuring`. Build NuttX =========== @@ -62,11 +54,11 @@ We can now build NuttX. To do so, you can simply run: .. code-block:: console $ cd nuttx/ - $ make make + $ make The build will complete by generating the binary outputs -inside `nuttx` directory. Typically this includes the `nuttx` -ELF file (suitable for debugging using `gdb`) and a `nuttx.bin` +inside ``nuttx`` directory. Typically this includes the ``nuttx`` +ELF file (suitable for debugging using ``gdb``) and a ``nuttx.bin`` file that can be flashed to the board. To clean the build, you can do: @@ -75,11 +67,6 @@ To clean the build, you can do: $ make clean -.. warning:: - At the moment it is recommended that after modifying the - configuration you first clean before building again. This - is currently worked on. - ---- Next up is :ref:`running`. diff --git a/Documentation/quickstart/configuring.rst b/Documentation/quickstart/configuring.rst index a289969d4db..0213d410a74 100644 --- a/Documentation/quickstart/configuring.rst +++ b/Documentation/quickstart/configuring.rst @@ -6,48 +6,31 @@ Configuring Apache NuttX is a very configurable operating system. Nearly all features can be configured in or out of the system. This makes it possible to compile a build tailored for your hardware and -application. It also makes configuring the system complex at times. - -There is a configuration system that can be used on the commandline or in a GUI. I've found -the easiest way to configured Apache NuttX is to use the ``menuconfig`` system. This is used -via a terminal program and allows quick access to all of Apache NuttX's features via a system of -menus. +application. The Apache NuttX configuration system uses Linux's -`kconfig system `_ adapted for use with Apache -NuttX. Here's info on Linux's kconfig `menuconfig `_ system. +`kconfig system `_ which +includes various frontends that allow you to modify configuration easily. Usually, the ``menuconfig`` +frontend is used, which is a console based menu system (more info `here `_). -After you've configured your board (see :ref:`compiling`), you can use the menuconfig system -to change the configuration. Once you've configured, you can compile to make a build that -has your configuration options selected. +As previously explained in :doc:`compiling`, the first step is to load a premade configuration for +your board. Then, you can modify this configuration to your liking. + +In this example, we will show how you modify the default configuration of the ``sim`` build. #. Initialize Board Configuration - Here we'll use the simulator since that's the simplest to explain. You can do this with - any board and base configuration. Note here you should be supplying `configure.sh` the correct flag - for your build environment: - - .. code-block:: bash - - -l selects the Linux (l) host environment. - -m selects the macOS (m) host environment. - -c selects the Windows host and Cygwin (c) environment. - -g selects the Windows host and MinGW/MSYS environment. - -n selects the Windows host and Windows native (n) environment. - - Select the simulator configuration for a Linux host: - - .. code-block:: bash + .. code-block:: console $ cd nuttx - $ make distclean # make a clean start, clearing out old configurations $ ./tools/configure.sh -l sim:nsh Copy files Select CONFIG_HOST_LINUX=y Refreshing... -#. Make + +#. Build & run - .. code-block:: bash + .. code-block:: console $ make clean; make $ ./nuttx @@ -55,15 +38,16 @@ has your configuration options selected. From another terminal window, kill the simulator: - .. code-block:: bash + .. code-block:: console $ pkill nuttx -#. Menu Configuration +#. Modify configuration - Showing that ``login:`` is annyoing. Let's use the ``menuconfig`` system to turn it off. + In this case we will remove the login feature (which will boot straight to the prompt). To + do so, we use the ``menuconfig`` frontend. - .. code-block:: bash + .. code-block:: console $ make menuconfig @@ -76,27 +60,24 @@ has your configuration options selected. |br| -#. Application Configuration + The NSH Login setting is under :menuselection:`Application Configuration --> NSH Library`. You + can use :kbd:`🢁` and :kbd:`🢃` keys to navigate and :kbd:`↵` to enter a submenu. + To disable the corresponding setting go to :menuselection:`Console Login` and press :kbd:`spacebar` to + it (so that it has a blank space instead of a star in it). - The NSH Login setting is under ``Application Configuration > NSH Library``. Use - the up and down arrows to navigate to ``Application Configuration``; hit ```` to - select it. Now you're in the ``Application Configuration`` menu. Use the arrows to go - down to ``NSH Library`` and select that. Now navigate down to ``Console Login`` and use - the spacebar to uncheck that setting (so that it has a blank space instead of a star in it). + Now you need to exit ``menuconfig`` and save the modified configuration. Use the :kbd:`🡸` and + :kbd:`🡺` arrow keys to navigate the lower menu. If you select :menuselection:`Exit` you will be + prompted to save the config. - Now let's save. Use the right and left arrow keys to select the ``Exit`` menu item at the - bottom of the screen. Hit ```` to select it, hit ```` again, and again, finally - hitting ```` in the ``Save Configuration`` dialog box. +#. Build with the new Configuration -#. Make the New Configuration + .. code-block:: console - .. code-block:: bash - - $ make clean; make + $ make #. Run - .. code-block:: bash + .. code-block:: console $ ./nuttx NuttShell (NSH) NuttX-8.2 @@ -104,8 +85,42 @@ has your configuration options selected. Success! +.. tip:: If you find that message of the day (MOTD) annoying and want to turn that off, it's - configured in ``Application Configuration > NSH Library >> Message of the Day (MOTD)``. + configured in :menuselection:`Application Configuration --> NSH Library --> Message of the Day (MOTD)`. + +Fast configuration changes +-------------------------- + +If you know exactly which configuration symbol you want to change, you can use the ``kconfig-tweak`` tool (comes with the ``kconfig-frontends`` package) to quickly change a setting without going into the configuration frontend. This is useful to change settings such as debug options: + +.. code-block:: console + + $ kconfig-tweak --disable CONFIG_DEBUG_NET + $ make olddefconfig # needed to have the kconfig system check the config + $ kconfig-tweak --enable CONFIG_DEBUG_NET + $ make olddefconfig + +This is also useful to script configuration changes that you perform often: + +.. code-block:: console + + #!/bin/bash + + kconfig-tweak --disable CONFIG_DEBUG_ALERT + kconfig-tweak --disable CONFIG_DEBUG_FEATURES + kconfig-tweak --disable CONFIG_DEBUG_ERROR + kconfig-tweak --disable CONFIG_DEBUG_WARN + kconfig-tweak --disable CONFIG_DEBUG_INFO + kconfig-tweak --disable CONFIG_DEBUG_ASSERTIONS + kconfig-tweak --disable CONFIG_DEBUG_NET + kconfig-tweak --disable CONFIG_DEBUG_NET_ERROR + kconfig-tweak --disable CONFIG_DEBUG_NET_WARN + kconfig-tweak --disable CONFIG_DEBUG_NET_INFO + kconfig-tweak --disable CONFIG_DEBUG_SYMBOLS + kconfig-tweak --disable CONFIG_DEBUG_NOOPT + kconfig-tweak --disable CONFIG_SYSLOG_TIMESTAMP + make oldconfig ---- diff --git a/Documentation/quickstart/debugging.rst b/Documentation/quickstart/debugging.rst index 379240d525f..cc3489eca88 100644 --- a/Documentation/quickstart/debugging.rst +++ b/Documentation/quickstart/debugging.rst @@ -1,6 +1,7 @@ .. include:: /substitutions.rst .. _debugging: +========= Debugging ========= @@ -9,27 +10,23 @@ to use debugging techniques to understand how the system works. Two tools that a debugging using the GNU Debugger (gdb). Debug Logging -------------- +============= NuttX has a powerful system logging facility (syslog) with ``info``, ``warn``, and ``error`` levels. You can enable debugging for your build for the subsystem or feature by using the ``menuconfig`` system. -.. code-block:: console - - $ make menuconfig - -The debug options are available under ``Build Setup`` > ``Debug Options``. You will most likely have to enable the +The debug options are available under :menuselection:`Build Setup --> Debug Options`. You will most likely have to enable the following options: -* ``Enable Debug Features`` — selecting this will turn on subsystem-level debugging options, they will become visible +* :menuselection:`Enable Debug Features` — selecting this will turn on subsystem-level debugging options, they will become visible on the page below. You can then select the ones you want. -* ``Enable Error Output`` — this will only log errors. -* ``Enable Warnings Output`` — this will log warnings and errors. -* ``Enable Informational Debug Output`` — this will produce informational output, warnings, and errors. +* :menuselection:`Enable Error Output` — this will only log errors. +* :menuselection:`Enable Warnings Output` — this will log warnings and errors. +* :menuselection:`Enable Informational Debug Output` — this will produce informational output, warnings, and errors. You can then select from the subsystems that are available, Network, Scheduler, USB, etc. Note that you will need to separately enable the subsystem elsewhere in the ``menuconfig`` system. To see the ``CONFIG`` define that is set, -use the arrow keys to highlight the subsystem (for instance, ``Network Debug Features``) and type '?'. This will show +use the arrow keys to highlight the subsystem (for instance, :menuselection:`Network Debug Features`) and type :kbd:`?`. This will show you that the C macro that is set is called ``CONFIG_DEBUG_NET``. ``debug.h`` defines the ``netinfo()`` logging function that will log output if this macro is set. You can search the source code for ``netinfo`` to see how it is used. @@ -44,82 +41,228 @@ the area you're interested in, and leave the rest disabled, save the config, and list of debug feature logging functions in the file `debug.h `__. -Syslog timestamps can be enabled in the ``menuconfig`` system using ``Device Drivers`` > ``System Logging`` > ``Prepend -timestamp to syslog message`` (``CONFIG_SYSLOG_TIMESTAMP``). +Syslog timestamps can be enabled in the configuration in :menuselection:`Device Drivers --> System Logging --> Prepend +timestamp to syslog message` (``CONFIG_SYSLOG_TIMESTAMP``). You may need to do a little bit of experimenting to find the combination of logging settings that work for the problem you're trying to solve. See the file `debug.h `_ -for available debug settings that are available. This can also be configured via the ``menuconfig`` system. +for available debug settings that are available. There are also subsystems that enable USB trace debugging, and you can log to memory too, if you need the logging to be faster than what the console can output. -Changing Debug Settings Quickly -------------------------------- +Debugging with ``openocd`` and ``gdb`` +====================================== -You can use the ``kconfig-tweak`` script that comes with the ``kconfig-frontends`` tools to quickly change debug settings, -for instance turning them on or off before doing a build: +To debug our Nucleo board using its embedded SWD debug adapter, +start ``openocd`` with the following command: .. code-block:: console - $ kconfig-tweak --disable CONFIG_DEBUG_NET - $ make olddefconfig # needed to have the kconfig system check the config - $ kconfig-tweak --enable CONFIG_DEBUG_NET - $ make olddefconfig + $ openocd -f interface/st-link-v2.cfg -f target/stm32f1x.cfg -You can put a bunch of these into a simple script to configure the logging the way you want: +This will start a ``gdb`` server. Then, start ``gdb`` with: .. code-block:: console - #!/bin/bash + $ cd nuttx/ + $ gdb-multiarch nuttx/nuttx - kconfig-tweak --disable CONFIG_DEBUG_ALERT - kconfig-tweak --disable CONFIG_DEBUG_FEATURES - kconfig-tweak --disable CONFIG_DEBUG_ERROR - kconfig-tweak --disable CONFIG_DEBUG_WARN - kconfig-tweak --disable CONFIG_DEBUG_INFO - kconfig-tweak --disable CONFIG_DEBUG_ASSERTIONS - kconfig-tweak --disable CONFIG_DEBUG_NET - kconfig-tweak --disable CONFIG_DEBUG_NET_ERROR - kconfig-tweak --disable CONFIG_DEBUG_NET_WARN - kconfig-tweak --disable CONFIG_DEBUG_NET_INFO - kconfig-tweak --disable CONFIG_DEBUG_SYMBOLS - kconfig-tweak --disable CONFIG_DEBUG_NOOPT - kconfig-tweak --disable CONFIG_SYSLOG_TIMESTAMP - make oldconfig +Inside ``gdb`` console, connect to the ``gdb`` server with: +.. code-block:: -JTAG/SWD Debugging ------------------- + (gdb) target extended-remote :3333 -`JTAG `_ is a set of standards that specify a way to attach a hardware device to -your embedded board, and then remotely control the CPU. You can load code, start, stop, step through the program, and -examine variables and memory. `SWD `_ is an -Arm-specific interface with a reduced number of signals which can be used alternatively. +You can now use standard ``gdb`` commands. For example, to +reset the board: -The NuttX operating system uses `threads `_, so you need a -thread-aware debugger to do more than load code, start, and stop it. A thread-aware debugger will allow you to switch -threads to the one that is running the code you're interested in, for instance your application, or an operating system -network thread. So far, `OpenOCD `_ is the only supported NuttX thread-aware debugger. +.. code-block:: -.. note:: - OpenOCD hasn't announced a stable release for a few years but the development remains active. You'll need to use a - version of OpenOCD recent enough so that it includes NuttX support as `contributed by Sony upstream - `_. The version included in official OS repositories will probably be too old. - You should build from source or use one of the unofficial, more recent builds. See `Getting OpenOCD - `_ for more details. + (gdb) mon reset -You will need a board with a JTAG or SWD connector and an `OpenOCD-compatible hardware adapter -`_, ideally a fast one (USB 2.0 High Speed). For example an `Olimex -ARM USB TINY H `_ or a `Segger J-Link -`_. Many other adapters work too, follow the OpenOCD -instructions and the instructions that came with your adapter. +To halt the board: -See this article for more info: -`Debugging a Apache NuttX target with GDB and OpenOCD `_. +.. code-block:: -See the section :ref:`Running ` for a brief tutorial on how to use GDB. + (gdb) mon halt + +To set a breakpoint: ----- +.. code-block:: + + (gdb) breakpoint nsh_main + +and to finally start nuttx: + +.. code-block:: + + (gdb) continue + Continuing. + + Breakpoint 1, nsh_main (argc=1, argv=0x200ddfac) at nsh_main.c:208 + 208 sched_getparam(0, ¶m); + (gdb) continue + Continuing. + +.. tip:: + + You can abbreviate ``gdb`` commands: ``info b`` is a shortcut for + ``information breakpoints``; ``c`` works the same as ``continue``, etc. + +NuttX aware debugging +--------------------- + +Since NuttX is actually an RTOS, it is useful to have ``gdb`` be aware of the different +tasks/threads that are running. There are two ways to do this: via ``openocd`` +itself or via ``gdb``. Note that in both cases, you need to enable debug symbols +(``CONFIG_DEBUG_SYMBOLS``). + +With openocd +~~~~~~~~~~~~ + +``openocd`` supports various RTOS directly, including NuttX. It works by reading +into internal NuttX symbols which define the active tasks and their properties. +As a result, the ``gdb`` server will directly be aware of each task as a different +`thread`. The downside of this approach is that it depends on how you build NuttX +as there are some options hardcoded into +opencd. By default, it assumes: + + * ``CONFIG_DISABLE_MQUEUE=y`` + * ``CONFIG_PAGING=n`` + +If you need these options to be set differently, you will have to edit ``./src/rtos/nuttx_header.h`` from ``openocd``, +change the corresponding settings and then rebuild it. + +Finally, to enable NuttX integration, you need to supply an additional ``openocd`` argument: + +.. code-block:: console + + $ openocd -f interface/st-link-v2.cfg -f target/stm32f1x.cfg -c '$_TARGETNAME configure -rtos nuttx' + +Since ``openocd`` also needs to know the memory layout of certain datastructures, you need to have ``gdb`` +run the following commands once the ``nuttx`` binary is loaded: + +.. code-block:: + + eval "monitor nuttx.pid_offset %d", &((struct tcb_s *)(0))->pid + eval "monitor nuttx.xcpreg_offset %d", &((struct tcb_s *)(0))->xcp.regs + eval "monitor nuttx.state_offset %d", &((struct tcb_s *)(0))->task_state + eval "monitor nuttx.name_offset %d", &((struct tcb_s *)(0))->name + eval "monitor nuttx.name_size %d", sizeof(((struct tcb_s *)(0))->name) + +One way to do this is to define a gdb `hook` function that will be called when running ``file`` command: + +.. code-block:: + + define hookpost-file + eval "monitor nuttx.pid_offset %d", &((struct tcb_s *)(0))->pid + eval "monitor nuttx.xcpreg_offset %d", &((struct tcb_s *)(0))->xcp.regs + eval "monitor nuttx.state_offset %d", &((struct tcb_s *)(0))->task_state + eval "monitor nuttx.name_offset %d", &((struct tcb_s *)(0))->name + eval "monitor nuttx.name_size %d", sizeof(((struct tcb_s *)(0))->name) + end + +You will see that ``openocd`` has received the memory offsets in its output: + +.. code-block:: + + Open On-Chip Debugger 0.10.0+dev-01514-ga8edbd020-dirty (2020-11-20-14:23) + Licensed under GNU GPL v2 + For bug reports, read + http://openocd.org/doc/doxygen/bugs.html + Info : auto-selecting first available session transport "swd". To override use 'transport select '. + Info : target type name = cortex_m + Info : Listening on port 6666 for tcl connections + Info : Listening on port 4444 for telnet connections + 15:41:23: Debugging starts + Info : CMSIS-DAP: SWD Supported + Info : CMSIS-DAP: FW Version = 1.10 + Info : CMSIS-DAP: Interface Initialised (SWD) + Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 0 TDO = 0 nTRST = 0 nRESET = 1 + Info : CMSIS-DAP: Interface ready + Info : clock speed 1000 kHz + Info : SWD DPIDR 0x2ba01477 + Info : nrf52.cpu: hardware has 6 breakpoints, 4 watchpoints + Info : starting gdb server for nrf52.cpu on 3333 + Info : Listening on port 3333 for gdb connections + Info : accepting 'gdb' connection on tcp/3333 + Error: No symbols for NuttX + Info : nRF52832-QFAA(build code: B0) 512kB Flash, 64kB RAM + undefined debug reason 8 - target needs reset + Warn : Prefer GDB command "target extended-remote 3333" instead of "target remote 3333" + Info : pid_offset: 12 + Info : xcpreg_offset: 132 + Info : state_offset: 26 + Info : name_offset: 208 + Info : name_size: 32 + target halted due to debug-request, current mode: Thread + xPSR: 0x01000000 pc: 0x000000dc msp: 0x20000cf0 + target halted due to debug-request, current mode: Thread xPSR: 0x01000000 pc: 0x000000dc msp: 0x20000cf0 + +.. note:: You will probably see the ``Error: No symbols for NuttX`` error appear once at startup. This is OK + unless you see it every time you step the debugger. In this case, it would mean you did not enable debug symbols. + +Now, You can now inspect threads: + +.. code-block:: + + (gdb) info threads + Id Target Id Frame + * 1 Remote target nx_start_application () at init/nx_bringup.c:261 + (gdb) info registers + r0 0x0 0 + r1 0x2f 47 + r2 0x0 0 + r3 0x0 0 + r4 0x0 0 + r5 0x0 0 + r6 0x0 0 + r7 0x20000ca0 536874144 + r8 0x0 0 + r9 0x0 0 + r10 0x0 0 + r11 0x0 0 + r12 0x9 9 + sp 0x20000c98 0x20000c98 + lr 0x19c5 6597 + pc 0x1996 0x1996 + xPSR 0x41000000 1090519040 + fpscr 0x0 0 + msp 0x20000c98 0x20000c98 + psp 0x0 0x0 <_vectors> + primask 0x0 0 + basepri 0xe0 -32 + faultmask 0x0 0 + control 0x0 0 + +With gdb +~~~~~~~~ + +You can also do NuttX aware debugging using ``gdb`` scripting support. +The benefit is that it works also for the sim build where ``openocd`` is +not applicable. For this to work, you will need to enable PROC filesystem support +which will expose required task information (``CONFIG_FS_PROCFS=y``). + +To use this approach, you can load the ``nuttx/tools/nuttx-gdbinit`` file. An +easy way to do this is to create a symbolic link: + +.. code-block:: console + + $ cd $HOME + $ ln -s nuttx/tools/nuttx-gdbinit .gdbinit + +This way whenever gdb is started it will run the appropriate commands. To inspect +the threads you can now use the following ``gdb`` command: + +.. code-block:: + + (gdb) info_nxthreads + target examined + _target_arch.name=armv7e-m + $_target_has_fpu : 0 + $_target_has_smp : 0 + saved current_tcb (pid=0) + * 0 Thread 0x20000308 (Name: Idle Task, State: Running, Priority: 0) 0xdc in __start() + 1 Thread 0x20001480 (Name: init, State: Waiting,Semaphore, Priority: 100) 0x7e08 in arm_switchcontext() -Next up is :ref:`organization`. diff --git a/Documentation/quickstart/index.rst b/Documentation/quickstart/index.rst index 0a029473033..e922ddcfd82 100644 --- a/Documentation/quickstart/index.rst +++ b/Documentation/quickstart/index.rst @@ -22,5 +22,4 @@ to build NuttX. configuring.rst debugging.rst organization.rst - build_and_make.rst diff --git a/Documentation/quickstart/organization.rst b/Documentation/quickstart/organization.rst index e2a1044ea2b..eecdc521155 100644 --- a/Documentation/quickstart/organization.rst +++ b/Documentation/quickstart/organization.rst @@ -1,4 +1,9 @@ .. include:: /substitutions.rst + +.. todo:: + This is mostly untouched from the original documentation. It does + not really belong to "quickstart". Also, this needs cleanup. + .. _organization: =================== @@ -506,10 +511,5 @@ support. ================== The top-level ``Makefile`` in the ``$(TOPDIR)`` directory contains -all of the top-level control logic to build NuttX. Use of this -``Makefile`` to build NuttX is described -`below <#buildingnuttx>`__. +all of the top-level control logic to build NuttX. ----- - -Next up is :ref:`build_and_make`. diff --git a/Documentation/quickstart/running.rst b/Documentation/quickstart/running.rst index 4bc59b225cc..6ad48e5e910 100644 --- a/Documentation/quickstart/running.rst +++ b/Documentation/quickstart/running.rst @@ -40,7 +40,7 @@ latest Git version. To install it you should: $ git clone git://git.code.sf.net/p/openocd/code openocd $ cd openocd $ ./bootstrap - $ ./configure --prefix install/ + $ ./configure --prefix=install/ $ make install The resulting installation will be under ``openocd/install``. You can add @@ -71,122 +71,6 @@ of your choice where you will see the ``nsh>`` prompt: $ gtkterm -s 115200 -p /dev/ttyUSB0 - -Debugging -========= - -Using ``openocd`` you can also debug NuttX. To do so, first run: - -.. code-block:: console - - $ openocd -f interface/st-link-v2.cfg -f target/stm32f1x.cfg - -which will start a GDB server. Then, start ``gdb`` as: - -.. code-block:: console - - $ cd nuttx/ - $ gdb-multiarch nuttx/nuttx - -Inside ``gdb`` console, connect to the ``openocd`` server with: - -.. code-block:: - - (gdb) target extended-remote :3333 - -You can debug using standard ``gdb`` commands. - -Advanced Debugging with JTAG ----------------------------- - -If your board does not have an embedded programmer and uses -`JTAG `_ connector instead, -things are a bit different. This guide assumes you have a JTAG hardware debugger like a -`Segger J-Link `_. -JTAG is a set of standards that let you -attach a hardware device to your embedded board, and then remotely control the CPU. -You can load code, start, stop, step through the program, and examine variables and memory. - -#. Attach the Debugger Cables - -#. Start the Debugger - - Refer to your JTAG debugger's documentation for information on how to start a GDB Server process that gdb can - communicate with to load code and start, stop, and step the embedded board's CPU. Your command line may be - different from this one. - - .. code-block:: console - - $ JLinkGDBServer -device ATSAMA5D27 -if JTAG -speed 1000 -JTAGConf -1,-1 - -#. Launch the GNU Debugger - - In another terminal window, launch the GDB. In the case of this guide, this came with the - ARM Embedded GNU Toolchain we downloaded in the Install step. - - .. code-block:: console - - $ cd nuttx/ - $ gdb-multiarch nuttx/nuttx - -#. Set gdb to talk with the J-Link - - :: - - (gdb) target extended-remote :2331 - -#. Reset the board - - :: - - (gdb) mon reset - -#. You may need to switch to the serial console to hit a key to stop the board from booting from its boot monitor - (U-Boot, in the case of the SAMA5 boards from Microchip). - -#. Halt the board - - :: - - (gdb) mon halt - -#. Load nuttx - - :: - - (gdb) load nuttx - `/home/adamf/src/nuttx-sama5d36-xplained/nuttx/nuttx' has changed; re-reading symbols. - Loading section .text, size 0x9eae4 lma 0x20008000 - Loading section .ARM.exidx, size 0x8 lma 0x200a6ae4 - Loading section .data, size 0x125c lma 0x200a6aec - Start address 0x20008040, load size 654664 - Transfer rate: 75 KB/sec, 15587 bytes/write. - (gdb) - -#. Set a breakpoint - - :: - - (gdb) breakpoint nsh_main - -#. Start nuttx - - :: - - (gdb) continue - Continuing. - - Breakpoint 1, nsh_main (argc=1, argv=0x200ddfac) at nsh_main.c:208 - 208 sched_getparam(0, ¶m); - (gdb) continue - Continuing. - -Debugging Shortcuts -------------------- - -Note that you can abbreviate ``gdb`` commands, ``info b`` is a shortcut for -``information breakpoints``; ``c`` works the same as ``continue``, etc. - ---- Next up is :ref:`configuring`. diff --git a/Documentation/releases/index.rst b/Documentation/releases/index.rst deleted file mode 100644 index 005b06f9d87..00000000000 --- a/Documentation/releases/index.rst +++ /dev/null @@ -1,6 +0,0 @@ -Releases -======== - -.. todo:: - This should link (or include?) release notes. Maybe only show some recent ones and link - older ones diff --git a/TODO b/TODO index 60c231ad8d5..acc6e5b201d 100644 --- a/TODO +++ b/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated October 20, 2020) +NuttX TODO List (Last updated November 20, 2020) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -10,7 +10,7 @@ issues related to each board port. nuttx/: (16) Task/Scheduler (sched/) - (5) SMP + (3) SMP (1) Memory Management (mm/) (0) Power Management (drivers/pm) (5) Signals (sched/signal, arch/) @@ -448,34 +448,6 @@ o Task/Scheduler (sched/) o SMP ^^^ - Title: SMP AND DATA CACHES - Description: When spinlocks, semaphores, etc. are used in an SMP system with - a data cache, then there may be problems with cache coherency - in some CPU architectures: When one CPU modifies the shared - object, the changes may not be visible to another CPU if it - does not share the data cache. That would cause failure in - the IPC logic. - - Flushing the D-cache on writes and invalidating before a read is - not really an option. That would essentially effect every memory - access and there may be side-effects due to cache line sizes - and alignment. - - For the same reason a separate, non-cacheable memory region is - not an option. Essentially all data would have to go in the - non-cached region and you would have no benefit from the data - cache. - - On ARM Cortex-A, each CPU has a separate data cache. However, - the MPCore's Snoop Controller Unit supports coherency among - the different caches. The SCU is enabled by the SCU control - register and each CPU participates in the SMP coherency by - setting the ACTLR_SMP bit in the auxiliary control register - (ACTLR). - - Status: Closed - Priority: High on platforms that may have the issue. - Title: MISUSE OF sched_lock() IN SMP MODE Description: The OS API sched_lock() disables pre-emption and locks a task in place. In the single CPU case, it is also often @@ -496,37 +468,6 @@ o SMP Priority: Medium for SMP system. Not critical to single CPU systems. NOTE: There are no known bugs from this potential problem. - Title: CORTEX-A GIC SGI INTERRUPT MASKING - Description: In the ARMv7-A GICv2 architecture, the inter-processor - interrupts (SGIs) are non maskable and will occur even if - interrupts are disabled. This adds a lot of complexity - to the ARMV7-A critical section design. - - Masayuki Ishikawa has suggested the use of the GICv2 ICCMPR - register to control SGI interrupts. This register (much like - the ARMv7-M BASEPRI register) can be used to mask interrupts - by interrupt priority. Since SGIs may be assigned priorities - the ICCMPR should be able to block execution of SGIs as well. - - Such an implementation would be very similar to the BASEPRI - (vs PRIMASK) implementation for the ARMv7-M: (1) The - up_irq_save() and up_irq_restore() registers would have to - set/restore the ICCMPR register, (2) register setup logic in - arch/arm/src/armv7-a for task start-up and signal dispatch - would have to set the ICCMPR correctly, and (3) the 'xcp' - structure would have to be extended to hold the ICCMPR - register; logic would have to added be save/restore the - ICCMPR register in the 'xcp' structure on each interrupt and - context switch. - - This would also be an essential part of a high priority, - nested interrupt implementation (unrelated). - Status: Open - Priority: Low. There are no known issues with the current non-maskable - SGI implementation. This change would, however, lead to - simplification in the design and permit commonality with - other, non-GIC implementations. - Title: ISSUES WITH ACCESSING CPU INDEX Description: The CPU number is accessed usually with the macro this_cpu(). The returned CPU number is then used for various things, diff --git a/arch/arm/include/inttypes.h b/arch/arm/include/inttypes.h index 509611e0b6e..f47ac324958 100644 --- a/arch/arm/include/inttypes.h +++ b/arch/arm/include/inttypes.h @@ -46,77 +46,77 @@ #define PRId8 "d" #define PRId16 "d" -#define PRId32 "d" +#define PRId32 "ld" #define PRId64 "lld" #define PRIdPTR "d" #define PRIi8 "i" #define PRIi16 "i" -#define PRIi32 "i" +#define PRIi32 "li" #define PRIi64 "lli" #define PRIiPTR "i" #define PRIo8 "o" #define PRIo16 "o" -#define PRIo32 "o" +#define PRIo32 "lo" #define PRIo64 "llo" #define PRIoPTR "o" #define PRIu8 "u" #define PRIu16 "u" -#define PRIu32 "u" +#define PRIu32 "lu" #define PRIu64 "llu" #define PRIuPTR "u" #define PRIx8 "x" #define PRIx16 "x" -#define PRIx32 "x" +#define PRIx32 "lx" #define PRIx64 "llx" #define PRIxPTR "x" #define PRIX8 "X" #define PRIX16 "X" -#define PRIX32 "X" +#define PRIX32 "lX" #define PRIX64 "llX" #define PRIXPTR "X" #define SCNd8 "hhd" #define SCNd16 "hd" -#define SCNd32 "d" +#define SCNd32 "ld" #define SCNd64 "lld" #define SCNdPTR "d" #define SCNi8 "hhi" #define SCNi16 "hi" -#define SCNi32 "i" +#define SCNi32 "li" #define SCNi64 "lli" #define SCNiPTR "i" #define SCNo8 "hho" #define SCNo16 "ho" -#define SCNo32 "o" +#define SCNo32 "lo" #define SCNo64 "llo" #define SCNoPTR "o" #define SCNu8 "hhu" #define SCNu16 "hu" -#define SCNu32 "u" +#define SCNu32 "lu" #define SCNu64 "llu" #define SCNuPTR "u" #define SCNx8 "hhx" #define SCNx16 "hx" -#define SCNx32 "x" +#define SCNx32 "lx" #define SCNx64 "llx" #define SCNxPTR "x" @@ -128,7 +128,7 @@ #define UINT8_C(x) x #define UINT16_C(x) x -#define UINT32_C(x) x ## u +#define UINT32_C(x) x ## ul #define UINT64_C(x) x ## ull #endif /* __ARCH_ARM_INCLUDE_INTTYPES_H */ diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h index ba6cdeb06a3..d7b08ec931e 100644 --- a/arch/arm/include/stm32/chip.h +++ b/arch/arm/include/stm32/chip.h @@ -2486,6 +2486,44 @@ # error "Unsupported STM32 chip" #endif +/* Peripheral IP versions *************************************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#if defined(CONFIG_STM32_STM32F10XX) +# define STM32_HAVE_IP_SPI_V1 + +#elif defined(CONFIG_STM32_STM32F20XX) +# define STM32_HAVE_IP_SPI_V2 + +#elif defined(CONFIG_STM32_STM32F30XX) +# define STM32_HAVE_IP_SPI_V3 + +#elif defined(CONFIG_STM32_STM32F33XX) +# define STM32_HAVE_IP_SPI_V1 + +#elif defined(CONFIG_STM32_STM32F37XX) +# define STM32_HAVE_IP_SPI_V3 + +#elif defined(CONFIG_STM32_STM32F4XXX) +# define STM32_HAVE_IP_SPI_V2 + +#elif defined(CONFIG_STM32_STM32G47XX) +# define STM32_HAVE_IP_SPI_V4 + +#elif defined(CONFIG_STM32_STM32L15XX) +# define STM32_HAVE_IP_SPI_V1 + +#else +# error "Did not resolve peripheral IP versions!" +#endif + /* NVIC priority levels ***************************************************************************/ #define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ diff --git a/arch/arm/include/types.h b/arch/arm/include/types.h index fd804a87cea..f651da4e7cc 100644 --- a/arch/arm/include/types.h +++ b/arch/arm/include/types.h @@ -56,13 +56,16 @@ typedef unsigned char _uint8_t; typedef signed short _int16_t; typedef unsigned short _uint16_t; -typedef signed int _int32_t; -typedef unsigned int _uint32_t; +typedef signed long _int32_t; +typedef unsigned long _uint32_t; typedef signed long long _int64_t; typedef unsigned long long _uint64_t; #define __INT64_DEFINED +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; + /* A size is 4 bytes */ #if defined(__SIZE_TYPE__) diff --git a/arch/arm/src/Makefile b/arch/arm/src/Makefile index 5224cacc98c..6477156c037 100644 --- a/arch/arm/src/Makefile +++ b/arch/arm/src/Makefile @@ -194,12 +194,15 @@ endif # Dependencies +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) + .depend: Makefile chip$(DELIM)Make.defs $(SRCS) $(TOPDIR)$(DELIM).config ifeq ($(BOARDMAKE),y) $(Q) $(MAKE) -C board depend endif - $(Q) $(MKDEP) $(patsubst %,--dep-path %,$(subst :, ,$(VPATH))) \ - "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile DEPPATH="$(patsubst %,--dep-path %,$(subst :, ,$(VPATH)))" $(Q) touch $@ depend: .depend diff --git a/arch/arm/src/a1x/a1x_serial.c b/arch/arm/src/a1x/a1x_serial.c index 10027ceeb7d..8865d792bf7 100644 --- a/arch/arm/src/a1x/a1x_serial.c +++ b/arch/arm/src/a1x/a1x_serial.c @@ -108,7 +108,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int uart_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -1316,7 +1316,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint32_t rbr; diff --git a/arch/arm/src/am335x/am335x_serial.c b/arch/arm/src/am335x/am335x_serial.c index 19bac0dccdc..574de3793c9 100644 --- a/arch/arm/src/am335x/am335x_serial.c +++ b/arch/arm/src/am335x/am335x_serial.c @@ -109,7 +109,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int uart_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -1142,7 +1142,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint32_t rbr; diff --git a/arch/arm/src/armv6-m/arm_svcall.c b/arch/arm/src/armv6-m/arm_svcall.c index 15c16f2d823..e61f83ab92d 100644 --- a/arch/arm/src/armv6-m/arm_svcall.c +++ b/arch/arm/src/armv6-m/arm_svcall.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -439,7 +440,7 @@ int arm_svcall(int irq, FAR void *context, FAR void *arg) rtcb->flags |= TCB_FLAG_SYSCALL; #else - svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]); + svcerr("ERROR: Bad SYS call: %" PRId32 "\n", regs[REG_R0]); #endif } break; diff --git a/arch/arm/src/armv7-a/arm_cpustart.c b/arch/arm/src/armv7-a/arm_cpustart.c index ca883d56de9..de6b037bf56 100644 --- a/arch/arm/src/armv7-a/arm_cpustart.c +++ b/arch/arm/src/armv7-a/arm_cpustart.c @@ -171,10 +171,6 @@ int up_cpu_start(int cpu) sched_note_cpu_start(this_task(), cpu); #endif - /* Make the content of CPU0 L1 cache has been written to coherent L2 */ - - cp15_clean_dcache(CONFIG_RAM_START, CONFIG_RAM_END - 1); - /* Execute SGI1 */ return arm_cpu_sgi(GIC_IRQ_SGI1, (1 << cpu)); diff --git a/arch/arm/src/armv7-a/arm_l2cc_pl310.c b/arch/arm/src/armv7-a/arm_l2cc_pl310.c index 3726cc881e2..d387bc8aa8e 100644 --- a/arch/arm/src/armv7-a/arm_l2cc_pl310.c +++ b/arch/arm/src/armv7-a/arm_l2cc_pl310.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/armv7-a/chip/arm-l2cc_pl310.c * * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. @@ -36,7 +36,7 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Included Files @@ -59,13 +59,15 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Configuration ***********************************************************/ + +/* Configuration ************************************************************/ + /* Number of ways depends on ARM configuration */ #if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY) # define PL310_NWAYS 8 # define PL310_WAY_MASK 0x000000ff -#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY) +#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY) # define PL310_NWAYS 16 # define PL310_WAY_MASK 0x0000ffff #else @@ -315,38 +317,45 @@ void arm_l2ccinitialize(void) /* Make sure that this is a PL310 cache, version r3p2. * - * REVISIT: The SAMA5D4 is supposed to report its ID as 0x410000C8 which is - * r3p2, but the chip that I have actually* reports 0x410000C9 which is some - * later revision. + * REVISIT: The SAMA5D4 is supposed to report its ID as 0x410000C8 which + * is r3p2, but the chip that I have actually* reports 0x410000C9 which + * is some later revision. */ - //DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) == L2CC_IDR_REV_R3P2); + /* DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) == + * L2CC_IDR_REV_R3P2); + */ /* Make sure that actual cache configuration agrees with the configured * cache configuration. */ - #if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY) DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 0); #elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 1); + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == L2CC_ACR_ASS); #else # error No associativity selected #endif #if defined(CONFIG_ARMV7A_WAYSIZE_16KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_16KB); + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_16KB); #elif defined(CONFIG_ARMV7A_WAYSIZE_32KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_32KB); + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_32KB); #elif defined(CONFIG_ARMV7A_WAYSIZE_64KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_64KB); + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_64KB); #elif defined(CONFIG_ARMV7A_WAYSIZE_128KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_128KB); + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_128KB); #elif defined(CONFIG_ARMV7A_WAYSIZE_256KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_256KB); + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_256KB); #elif defined(CONFIG_ARMV7A_WAYSIZE_512KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_512KB); + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_512KB); #else # error No way size selected #endif diff --git a/arch/arm/src/armv7-a/l2cc_pl310.h b/arch/arm/src/armv7-a/l2cc_pl310.h index 16d8f723cb4..1c283c93230 100644 --- a/arch/arm/src/armv7-a/l2cc_pl310.h +++ b/arch/arm/src/armv7-a/l2cc_pl310.h @@ -52,11 +52,12 @@ * header file as L2CC_VBASE. */ -#include "chip/chip.h" +#include "chip.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ + /* General Definitions **************************************************************/ #define PL310_CACHE_LINE_SIZE 32 @@ -110,7 +111,7 @@ #define L2CC_DLKR_OFFSET(n) (0x0900 + ((n) << 3)) /* Data Lockdown Register */ #define L2CC_ILKR_OFFSET(n) (0x0904 + ((n) << 3)) /* Instruction Lockdown Register */ - /* 0x0940-0x0f4c Reserved */ + /* 0x0940-0x0f4c Reserved */ #ifdef CONFIG_PL310_LOCKDOWN_BY_LINE # define L2CC_LKLN_OFFSET 0x0950 /* Lock Line Enable Register */ # define L2CC_UNLKW_OFFSET 0x0954 /* Unlock Way Register */ @@ -170,23 +171,23 @@ /* Cache ID Register (32-bit ID) */ #define L2CC_IDR_REV_MASK 0x0000003f -# define L2CC_IDR_REV_R0P0 0x00000000 -# define L2CC_IDR_REV_R1P0 0x00000002 -# define L2CC_IDR_REV_R2P0 0x00000004 -# define L2CC_IDR_REV_R3P0 0x00000005 -# define L2CC_IDR_REV_R3P1 0x00000006 -# define L2CC_IDR_REV_R3P2 0x00000008 +#define L2CC_IDR_REV_R0P0 0x00000000 +#define L2CC_IDR_REV_R1P0 0x00000002 +#define L2CC_IDR_REV_R2P0 0x00000004 +#define L2CC_IDR_REV_R3P0 0x00000005 +#define L2CC_IDR_REV_R3P1 0x00000006 +#define L2CC_IDR_REV_R3P2 0x00000008 /* Cache Type Register */ #define L2CC_TYPR_IL2ASS (1 << 6) /* Bit 6: Instruction L2 Cache Associativity */ #define L2CC_TYPR_IL2WSIZE_SHIFT (8) /* Bits 8-10: Instruction L2 Cache Way Size */ #define L2CC_TYPR_IL2WSIZE_MASK (7 << L2CC_TYPR_IL2WSIZE_SHIFT) -# define L2CC_TYPR_IL2WSIZE(n) ((uint32_t)(n) << L2CC_TYPR_IL2WSIZE_SHIFT) +#define L2CC_TYPR_IL2WSIZE(n) ((uint32_t)(n) << L2CC_TYPR_IL2WSIZE_SHIFT) #define L2CC_TYPR_DL2ASS (1 << 18) /* Bit 18: Data L2 Cache Associativity */ #define L2CC_TYPR_DL2WSIZE_SHIFT (20) /* Bits 20-22: Data L2 Cache Way Size */ #define L2CC_TYPR_DL2WSIZE_MASK (7 << L2CC_TYPR_DL2WSIZE_SHIFT) -# define L2CC_TYPR_DL2WSIZE(n) ((uint32_t)(n) << L2CC_TYPR_DL2WSIZE_SHIFT) +#define L2CC_TYPR_DL2WSIZE(n) ((uint32_t)(n) << L2CC_TYPR_DL2WSIZE_SHIFT) /* Control Register */ @@ -202,21 +203,22 @@ #define L2CC_ACR_ASS (1 << 16) /* Bit 16: Associativity */ #define L2CC_ACR_WAYSIZE_SHIFT (17) /* Bits 17-19: Way Size */ #define L2CC_ACR_WAYSIZE_MASK (7 << L2CC_ACR_WAYSIZE_SHIFT) -# define L2CC_ACR_WAYSIZE_16KB (1 << L2CC_ACR_WAYSIZE_SHIFT) -# define L2CC_ACR_WAYSIZE_32KB (2 << L2CC_ACR_WAYSIZE_SHIFT) -# define L2CC_ACR_WAYSIZE_64KB (3 << L2CC_ACR_WAYSIZE_SHIFT) -# define L2CC_ACR_WAYSIZE_128KB (4 << L2CC_ACR_WAYSIZE_SHIFT) -# define L2CC_ACR_WAYSIZE_256KB (5 << L2CC_ACR_WAYSIZE_SHIFT) -# define L2CC_ACR_WAYSIZE_512KB (6 << L2CC_ACR_WAYSIZE_SHIFT) +#define L2CC_ACR_WAYSIZE_16KB (1 << L2CC_ACR_WAYSIZE_SHIFT) +#define L2CC_ACR_WAYSIZE_32KB (2 << L2CC_ACR_WAYSIZE_SHIFT) +#define L2CC_ACR_WAYSIZE_64KB (3 << L2CC_ACR_WAYSIZE_SHIFT) +#define L2CC_ACR_WAYSIZE_128KB (4 << L2CC_ACR_WAYSIZE_SHIFT) +#define L2CC_ACR_WAYSIZE_256KB (5 << L2CC_ACR_WAYSIZE_SHIFT) +#define L2CC_ACR_WAYSIZE_512KB (6 << L2CC_ACR_WAYSIZE_SHIFT) #define L2CC_ACR_EMBEN (1 << 20) /* Bit 20: Event Monitor Bus Enable */ #define L2CC_ACR_PEN (1 << 21) /* Bit 21: Parity Enable */ #define L2CC_ACR_SAOEN (1 << 22) /* Bit 22: Shared Attribute Override Enable */ #define L2CC_ACR_FWA_SHIFT (23) /* Bits 23-24: Force Write Allocate */ #define L2CC_ACR_FWA_MASK (3 << L2CC_ACR_FWA_SHIFT) -# define L2CC_ACR_FWA_AWCACHE (0 << L2CC_ACR_FWA_SHIFT) /* Use AWCACHE attributes for WA */ -# define L2CC_ACR_FWA_NOALLOC (1 << L2CC_ACR_FWA_SHIFT) /* No allocate */ -# define L2CC_ACR_FWA_OVERRIDE (2 << L2CC_ACR_FWA_SHIFT) /* Override AWCACHE attributes */ -# define L2CC_ACR_FWA_MAPPED (3 << L2CC_ACR_FWA_SHIFT) /* Internally mapped to 00 */ +#define L2CC_ACR_FWA_AWCACHE (0 << L2CC_ACR_FWA_SHIFT) /* Use AWCACHE attributes for WA */ +#define L2CC_ACR_FWA_NOALLOC (1 << L2CC_ACR_FWA_SHIFT) /* No allocate */ +#define L2CC_ACR_FWA_OVERRIDE (2 << L2CC_ACR_FWA_SHIFT) /* Override AWCACHE attributes */ +#define L2CC_ACR_FWA_MAPPED (3 << L2CC_ACR_FWA_SHIFT) /* Internally mapped to 00 */ + #define L2CC_ACR_CRPOL (1 << 25) /* Bit 25: Cache Replacement Policy */ #define L2CC_ACR_NSLEN (1 << 26) /* Bit 26: Non-Secure Lockdown Enable */ #define L2CC_ACR_NSIAC (1 << 27) /* Bit 27: Non-Secure Interrupt Access Control */ @@ -230,25 +232,25 @@ #define L2CC_TRCR_TSETLAT_SHIFT (0) /* Bits 0-2: Setup Latency */ #define L2CC_TRCR_TSETLAT_MASK (7 << L2CC_TRCR_TSETLAT_SHIFT) -# define L2CC_TRCR_TSETLAT(n) ((uint32_t)(n) << L2CC_TRCR_TSETLAT_SHIFT) +#define L2CC_TRCR_TSETLAT(n) ((uint32_t)(n) << L2CC_TRCR_TSETLAT_SHIFT) #define L2CC_TRCR_TRDLAT_SHIFT (4) /* Bits 4-6: Read Access Latency */ #define L2CC_TRCR_TRDLAT_MASK (7 << L2CC_TRCR_TRDLAT_SHIFT) -# define L2CC_TRCR_TRDLAT(n) ((uint32_t)(n) << L2CC_TRCR_TRDLAT_SHIFT) +#define L2CC_TRCR_TRDLAT(n) ((uint32_t)(n) << L2CC_TRCR_TRDLAT_SHIFT) #define L2CC_TRCR_TWRLAT_SHIFT (8) /* Bits 8-10: Write Access Latency */ #define L2CC_TRCR_TWRLAT_MASK (7 << L2CC_TRCR_TWRLAT_SHIFT) -# define L2CC_TRCR_TWRLAT(n) ((uint32_t)(n) << L2CC_TRCR_TWRLAT_SHIFT) +#define L2CC_TRCR_TWRLAT(n) ((uint32_t)(n) << L2CC_TRCR_TWRLAT_SHIFT) /* Data RAM Control Register */ #define L2CC_DRCR_DSETLAT_SHIFT (0) /* Bits 0-2: Setup Latency */ #define L2CC_DRCR_DSETLAT_MASK (7 << L2CC_DRCR_DSETLAT_SHIFT) -# define L2CC_DRCR_DSETLAT(n) ((uint32_t)(n) << L2CC_DRCR_DSETLAT_SHIFT) +#define L2CC_DRCR_DSETLAT(n) ((uint32_t)(n) << L2CC_DRCR_DSETLAT_SHIFT) #define L2CC_DRCR_DRDLAT_SHIFT (4) /* Bits 4-6: Read Access Latency */ #define L2CC_DRCR_DRDLAT_MASK (7 << L2CC_DRCR_DRDLAT_SHIFT) -# define L2CC_DRCR_DRDLAT(n) ((uint32_t)(n) << L2CC_DRCR_DRDLAT_SHIFT) +#define L2CC_DRCR_DRDLAT(n) ((uint32_t)(n) << L2CC_DRCR_DRDLAT_SHIFT) #define L2CC_DRCR_DWRLAT_SHIFT (8) /* Bits 8-10: Write Access Latency */ #define L2CC_DRCR_DWRLAT_MASK (7 << L2CC_DRCR_DWRLAT_SHIFT) -# define L2CC_DRCR_DWRLAT(n) ((uint32_t)(n) << L2CC_DRCR_DWRLAT_SHIFT) +#define L2CC_DRCR_DWRLAT(n) ((uint32_t)(n) << L2CC_DRCR_DWRLAT_SHIFT) /* Event Counter Control Register */ @@ -258,60 +260,60 @@ /* Event Counter 1 Configuration Register */ - -#define L2CC_ECFGR1_EIGEN_SHIFT (0) /* Bits 0-1: Event Counter Interrupt Generation */ -#define L2CC_ECFGR1_EIGEN_MASK (3 << L2CC_ECFGR1_EIGEN_SHIFT) -# define L2CC_ECFGR1_EIGEN_INTDIS (0 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables (default) */ -# define L2CC_ECFGR1_EIGEN_INTENINCR (1 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Increment condition */ -# define L2CC_ECFGR1_EIGEN_INTENOVER (2 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Overflow condition */ -# define L2CC_ECFGR1_EIGEN_INTGENDIS (3 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables Interrupt generation */ -#define L2CC_ECFGR1_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */ -#define L2CC_ECFGR1_ESRC_MASK (15 << L2CC_ECFGR1_ESRC_SHIFT) -# define L2CC_ECFGR1_ESRC_CNTDIS (0 << L2CC_ECFGR1_ESRC_SHIFT) /* Counter Disabled */ -# define L2CC_ECFGR1_ESRC_CO (1 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is CO */ -# define L2CC_ECFGR1_ESRC_DRHIT (2 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DRHIT */ -# define L2CC_ECFGR1_ESRC_DRREQ (3 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DRREQ */ -# define L2CC_ECFGR1_ESRC_DWHIT (4 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWHIT */ -# define L2CC_ECFGR1_ESRC_DWREQ (5 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWREQ */ -# define L2CC_ECFGR1_ESRC_DWTREQ (6 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWTREQ */ -# define L2CC_ECFGR1_ESRC_IRHIT (7 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IRHIT */ -# define L2CC_ECFGR1_ESRC_IRREQ (8 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IRREQ */ -# define L2CC_ECFGR1_ESRC_WA (9 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is WA */ -# define L2CC_ECFGR1_ESRC_IPFALLOC (10 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IPFALLOC */ -# define L2CC_ECFGR1_ESRC_EPFHIT (11 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFHIT */ -# define L2CC_ECFGR1_ESRC_EPFALLOC (12 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFALLOC */ -# define L2CC_ECFGR1_ESRC_SRRCVD (13 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRRCVD */ -# define L2CC_ECFGR1_ESRC_SRCONF (14 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRCONF */ -# define L2CC_ECFGR1_ESRC_EPFRCVD (15 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFRCVD */ +#define L2CC_ECFGR1_EIGEN_SHIFT (0) /* Bits 0-1: Event Counter Interrupt Generation */ +#define L2CC_ECFGR1_EIGEN_MASK (3 << L2CC_ECFGR1_EIGEN_SHIFT) +#define L2CC_ECFGR1_EIGEN_INTDIS (0 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables (default) */ +#define L2CC_ECFGR1_EIGEN_INTENINCR (1 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Increment condition */ +#define L2CC_ECFGR1_EIGEN_INTENOVER (2 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Overflow condition */ +#define L2CC_ECFGR1_EIGEN_INTGENDIS (3 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables Interrupt generation */ +#define L2CC_ECFGR1_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */ +#define L2CC_ECFGR1_ESRC_MASK (15 << L2CC_ECFGR1_ESRC_SHIFT) +#define L2CC_ECFGR1_ESRC_CNTDIS (0 << L2CC_ECFGR1_ESRC_SHIFT) /* Counter Disabled */ +#define L2CC_ECFGR1_ESRC_CO (1 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is CO */ +#define L2CC_ECFGR1_ESRC_DRHIT (2 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DRHIT */ +#define L2CC_ECFGR1_ESRC_DRREQ (3 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DRREQ */ +#define L2CC_ECFGR1_ESRC_DWHIT (4 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWHIT */ +#define L2CC_ECFGR1_ESRC_DWREQ (5 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWREQ */ +#define L2CC_ECFGR1_ESRC_DWTREQ (6 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWTREQ */ +#define L2CC_ECFGR1_ESRC_IRHIT (7 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IRHIT */ +#define L2CC_ECFGR1_ESRC_IRREQ (8 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IRREQ */ +#define L2CC_ECFGR1_ESRC_WA (9 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is WA */ +#define L2CC_ECFGR1_ESRC_IPFALLOC (10 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IPFALLOC */ +#define L2CC_ECFGR1_ESRC_EPFHIT (11 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFHIT */ +#define L2CC_ECFGR1_ESRC_EPFALLOC (12 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFALLOC */ +#define L2CC_ECFGR1_ESRC_SRRCVD (13 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRRCVD */ +#define L2CC_ECFGR1_ESRC_SRCONF (14 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRCONF */ +#define L2CC_ECFGR1_ESRC_EPFRCVD (15 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFRCVD */ /* Event Counter 0 Configuration Register */ -#define L2CC_ECFGR0_EIGEN_SHIFT (0) /* Bits 0-1: Event Counter Interrupt Generation */ -#define L2CC_ECFGR0_EIGEN_MASK (3 << L2CC_ECFGR0_EIGEN_SHIFT) -# define L2CC_ECFGR0_EIGEN_INTDIS (0 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables (default) */ -# define L2CC_ECFGR0_EIGEN_INTENINCR (1 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Increment condition */ -# define L2CC_ECFGR0_EIGEN_INTENOVER (2 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Overflow condition */ -# define L2CC_ECFGR0_EIGEN_INTGENDIS (3 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables Interrupt generation */ -#define L2CC_ECFGR0_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */ -#define L2CC_ECFGR0_ESRC_MASK (15 << L2CC_ECFGR0_ESRC_SHIFT) -# define L2CC_ECFGR0_ESRC_CNTDIS (0 << L2CC_ECFGR0_ESRC_SHIFT) /* Counter Disabled */ -# define L2CC_ECFGR0_ESRC_CO (1 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is CO */ -# define L2CC_ECFGR0_ESRC_DRHIT (2 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DRHIT */ -# define L2CC_ECFGR0_ESRC_DRREQ (3 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DRREQ */ -# define L2CC_ECFGR0_ESRC_DWHIT (4 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWHIT */ -# define L2CC_ECFGR0_ESRC_DWREQ (5 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWREQ */ -# define L2CC_ECFGR0_ESRC_DWTREQ (6 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWTREQ */ -# define L2CC_ECFGR0_ESRC_IRHIT (7 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IRHIT */ -# define L2CC_ECFGR0_ESRC_IRREQ (8 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IRREQ */ -# define L2CC_ECFGR0_ESRC_WA (9 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is WA */ -# define L2CC_ECFGR0_ESRC_IPFALLOC (10 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IPFALLOC */ -# define L2CC_ECFGR0_ESRC_EPFHIT (11 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFHIT */ -# define L2CC_ECFGR0_ESRC_EPFALLOC (12 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFALLOC */ -# define L2CC_ECFGR0_ESRC_SRRCVD (13 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRRCVD */ -# define L2CC_ECFGR0_ESRC_SRCONF (14 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRCONF */ -# define L2CC_ECFGR0_ESRC_EPFRCVD (15 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFRCVD */ +#define L2CC_ECFGR0_EIGEN_SHIFT (0) /* Bits 0-1: Event Counter Interrupt Generation */ +#define L2CC_ECFGR0_EIGEN_MASK (3 << L2CC_ECFGR0_EIGEN_SHIFT) +#define L2CC_ECFGR0_EIGEN_INTDIS (0 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables (default) */ +#define L2CC_ECFGR0_EIGEN_INTENINCR (1 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Increment condition */ +#define L2CC_ECFGR0_EIGEN_INTENOVER (2 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Overflow condition */ +#define L2CC_ECFGR0_EIGEN_INTGENDIS (3 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables Interrupt generation */ +#define L2CC_ECFGR0_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */ +#define L2CC_ECFGR0_ESRC_MASK (15 << L2CC_ECFGR0_ESRC_SHIFT) +#define L2CC_ECFGR0_ESRC_CNTDIS (0 << L2CC_ECFGR0_ESRC_SHIFT) /* Counter Disabled */ +#define L2CC_ECFGR0_ESRC_CO (1 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is CO */ +#define L2CC_ECFGR0_ESRC_DRHIT (2 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DRHIT */ +#define L2CC_ECFGR0_ESRC_DRREQ (3 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DRREQ */ +#define L2CC_ECFGR0_ESRC_DWHIT (4 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWHIT */ +#define L2CC_ECFGR0_ESRC_DWREQ (5 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWREQ */ +#define L2CC_ECFGR0_ESRC_DWTREQ (6 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWTREQ */ +#define L2CC_ECFGR0_ESRC_IRHIT (7 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IRHIT */ +#define L2CC_ECFGR0_ESRC_IRREQ (8 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IRREQ */ +#define L2CC_ECFGR0_ESRC_WA (9 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is WA */ +#define L2CC_ECFGR0_ESRC_IPFALLOC (10 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IPFALLOC */ +#define L2CC_ECFGR0_ESRC_EPFHIT (11 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFHIT */ +#define L2CC_ECFGR0_ESRC_EPFALLOC (12 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFALLOC */ +#define L2CC_ECFGR0_ESRC_SRRCVD (13 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRRCVD */ +#define L2CC_ECFGR0_ESRC_SRCONF (14 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRCONF */ +#define L2CC_ECFGR0_ESRC_EPFRCVD (15 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFRCVD */ /* Event Counter 1 Value Register (32-bit value) */ + /* Event Counter 0 Value Register (32-bit value) */ /* Interrupt Mask Register, Masked Interrupt Status Register, Raw Interrupt Status @@ -337,110 +339,110 @@ #define L2CC_IPALR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ #define L2CC_IPALR_IDX_SHIFT (5) /* Bits 5-13: Index Number */ #define L2CC_IPALR_IDX_MASK (0x1ff << L2CC_IPALR_IDX_SHIFT) -# define L2CC_IPALR_IDX(n) ((uint32_t)(n) << L2CC_IPALR_IDX_SHIFT) +#define L2CC_IPALR_IDX(n) ((uint32_t)(n) << L2CC_IPALR_IDX_SHIFT) #define L2CC_IPALR_TAG_SHIFT (14) /* Bits 14-31: Tag Number */ #define L2CC_IPALR_TAG_MASK (0x3ffff << L2CC_IPALR_TAG_SHIFT) -# define L2CC_IPALR_TAG(n) ((uint32_t)(n) << L2CC_IPALR_TAG_SHIFT) +#define L2CC_IPALR_TAG(n) ((uint32_t)(n) << L2CC_IPALR_TAG_SHIFT) /* Invalidate Way Register */ #define L2CC_IWR_WAY(n) (1 << (n)) /* Bist 0-7: Invalidate Way Number n, n=0..7 */ -# define L2CC_IWR_WAY0 (1 << 0) /* Bit 0: Invalidate Way Number 0 */ -# define L2CC_IWR_WAY1 (1 << 1) /* Bit 1: Invalidate Way Number 1 */ -# define L2CC_IWR_WAY2 (1 << 2) /* Bit 2: Invalidate Way Number 2 */ -# define L2CC_IWR_WAY3 (1 << 3) /* Bit 3: Invalidate Way Number 3 */ -# define L2CC_IWR_WAY4 (1 << 4) /* Bit 4: Invalidate Way Number 4 */ -# define L2CC_IWR_WAY5 (1 << 5) /* Bit 5: Invalidate Way Number 5 */ -# define L2CC_IWR_WAY6 (1 << 6) /* Bit 6: Invalidate Way Number 6 */ -# define L2CC_IWR_WAY7 (1 << 7) /* Bit 7: Invalidate Way Number 7 */ +#define L2CC_IWR_WAY0 (1 << 0) /* Bit 0: Invalidate Way Number 0 */ +#define L2CC_IWR_WAY1 (1 << 1) /* Bit 1: Invalidate Way Number 1 */ +#define L2CC_IWR_WAY2 (1 << 2) /* Bit 2: Invalidate Way Number 2 */ +#define L2CC_IWR_WAY3 (1 << 3) /* Bit 3: Invalidate Way Number 3 */ +#define L2CC_IWR_WAY4 (1 << 4) /* Bit 4: Invalidate Way Number 4 */ +#define L2CC_IWR_WAY5 (1 << 5) /* Bit 5: Invalidate Way Number 5 */ +#define L2CC_IWR_WAY6 (1 << 6) /* Bit 6: Invalidate Way Number 6 */ +#define L2CC_IWR_WAY7 (1 << 7) /* Bit 7: Invalidate Way Number 7 */ /* Clean Physical Address Line Register */ #define L2CC_CPALR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ #define L2CC_CPALR_IDX_SHIFT (5) /* Bits 5-13: Index number */ #define L2CC_CPALR_IDX_MASK (0x1ff << L2CC_CPALR_IDX_SHIFT) -# define L2CC_CPALR_IDX(n) ((uint32_t)(n) << L2CC_CPALR_IDX_SHIFT) +#define L2CC_CPALR_IDX(n) ((uint32_t)(n) << L2CC_CPALR_IDX_SHIFT) #define L2CC_CPALR_TAG_SHIFT (14) /* Bits 14-31: Tag number */ #define L2CC_CPALR_TAG_MASK (0x3ffff << L2CC_CPALR_TAG_SHIFT) -# define L2CC_CPALR_TAG(n) ((uint32_t)(n) << L2CC_CPALR_TAG_SHIFT) +#define L2CC_CPALR_TAG(n) ((uint32_t)(n) << L2CC_CPALR_TAG_SHIFT) /* Clean Index Register */ #define L2CC_CIR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ #define L2CC_CIR_IDX_SHIFT (5) /* Bits 5-13: Index number */ #define L2CC_CIR_IDX_MASK (0x1ff << L2CC_CIR_IDX_SHIFT) -# define L2CC_CIR_IDX(n) ((uint32_t)(n) << L2CC_CIR_IDX_SHIFT) +#define L2CC_CIR_IDX(n) ((uint32_t)(n) << L2CC_CIR_IDX_SHIFT) #define L2CC_CIR_WAY_SHIFT (28) /* Bits 28-30: Way number */ #define L2CC_CIR_WAY_MASK (7 << L2CC_CIR_WAY_SHIFT) -# define L2CC_CIR_WAY(n) ((uint32_t)(n) << L2CC_CIR_WAY_SHIFT) +#define L2CC_CIR_WAY(n) ((uint32_t)(n) << L2CC_CIR_WAY_SHIFT) /* Clean Way Register */ #define L2CC_CWR_WAY(n) (1 << (n)) /* Bits 0-7: Clean Way Number n, n=0..7 */ -# define L2CC_CWR_WAY0 (1 << 0) /* Bit 0: Clean Way Number 0 */ -# define L2CC_CWR_WAY1 (1 << 1) /* Bit 1: Clean Way Number 1 */ -# define L2CC_CWR_WAY2 (1 << 2) /* Bit 2: Clean Way Number 2 */ -# define L2CC_CWR_WAY3 (1 << 3) /* Bit 3: Clean Way Number 3 */ -# define L2CC_CWR_WAY4 (1 << 4) /* Bit 4: Clean Way Number 4 */ -# define L2CC_CWR_WAY5 (1 << 5) /* Bit 5: Clean Way Number 5 */ -# define L2CC_CWR_WAY6 (1 << 6) /* Bit 6: Clean Way Number 6 */ -# define L2CC_CWR_WAY7 (1 << 7) /* Bit 7: Clean Way Number 7 */ +#define L2CC_CWR_WAY0 (1 << 0) /* Bit 0: Clean Way Number 0 */ +#define L2CC_CWR_WAY1 (1 << 1) /* Bit 1: Clean Way Number 1 */ +#define L2CC_CWR_WAY2 (1 << 2) /* Bit 2: Clean Way Number 2 */ +#define L2CC_CWR_WAY3 (1 << 3) /* Bit 3: Clean Way Number 3 */ +#define L2CC_CWR_WAY4 (1 << 4) /* Bit 4: Clean Way Number 4 */ +#define L2CC_CWR_WAY5 (1 << 5) /* Bit 5: Clean Way Number 5 */ +#define L2CC_CWR_WAY6 (1 << 6) /* Bit 6: Clean Way Number 6 */ +#define L2CC_CWR_WAY7 (1 << 7) /* Bit 7: Clean Way Number 7 */ /* Clean Invalidate Physical Address Line Register */ #define L2CC_CIPALR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ #define L2CC_CIPALR_IDX_SHIFT (5) /* Bits 5-13: Index Number */ #define L2CC_CIPALR_IDX_MASK (0x1ff << L2CC_CIPALR_IDX_SHIFT) -# define L2CC_CIPALR_IDX(n) ((uint32_t)(n) << L2CC_CIPALR_IDX_SHIFT) +#define L2CC_CIPALR_IDX(n) ((uint32_t)(n) << L2CC_CIPALR_IDX_SHIFT) #define L2CC_CIPALR_TAG_SHIFT (14) /* Bits 14-31: Tag Number */ #define L2CC_CIPALR_TAG_MASK (0x3ffff << L2CC_CIPALR_TAG_SHIFT) -# define L2CC_CIPALR_TAG(n) ((uint32_t)(n) << L2CC_CIPALR_TAG_SHIFT) +#define L2CC_CIPALR_TAG(n) ((uint32_t)(n) << L2CC_CIPALR_TAG_SHIFT) /* Clean Invalidate Index Register */ #define L2CC_CIIR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ #define L2CC_CIIR_IDX_SHIFT (5) /* Bits 5-13: Index Number */ #define L2CC_CIIR_IDX_MASK (0x1ff << L2CC_CIIR_IDX_SHIFT) -# define L2CC_CIIR_IDX(n) ((uint32_t)(n) << L2CC_CIIR_IDX_SHIFT) +#define L2CC_CIIR_IDX(n) ((uint32_t)(n) << L2CC_CIIR_IDX_SHIFT) #define L2CC_CIIR_WAY_SHIFT (28) /* Bits 28-30: Way Number */ #define L2CC_CIIR_WAY_MASK (7 << L2CC_CIIR_WAY_SHIFT) -# define L2CC_CIIR_WAY(n) ((uint32_t)(n) << L2CC_CIIR_WAY_SHIFT) +#define L2CC_CIIR_WAY(n) ((uint32_t)(n) << L2CC_CIIR_WAY_SHIFT) /* Clean Invalidate Way Register */ #define L2CC_CIWR_WAY(n) (1 << (n)) /* Bits 0-7: Clean Invalidate Way Number n, n=1..7 */ -# define L2CC_CIWR_WAY0 (1 << 0) /* Bit 0: Clean Invalidate Way Number 0 */ -# define L2CC_CIWR_WAY1 (1 << 1) /* Bit 1: Clean Invalidate Way Number 1 */ -# define L2CC_CIWR_WAY2 (1 << 2) /* Bit 2: Clean Invalidate Way Number 2 */ -# define L2CC_CIWR_WAY3 (1 << 3) /* Bit 3: Clean Invalidate Way Number 3 */ -# define L2CC_CIWR_WAY4 (1 << 4) /* Bit 4: Clean Invalidate Way Number 4 */ -# define L2CC_CIWR_WAY5 (1 << 5) /* Bit 5: Clean Invalidate Way Number 5 */ -# define L2CC_CIWR_WAY6 (1 << 6) /* Bit 6: Clean Invalidate Way Number 6 */ -# define L2CC_CIWR_WAY7 (1 << 7) /* Bit 7: Clean Invalidate Way Number 7 */ +#define L2CC_CIWR_WAY0 (1 << 0) /* Bit 0: Clean Invalidate Way Number 0 */ +#define L2CC_CIWR_WAY1 (1 << 1) /* Bit 1: Clean Invalidate Way Number 1 */ +#define L2CC_CIWR_WAY2 (1 << 2) /* Bit 2: Clean Invalidate Way Number 2 */ +#define L2CC_CIWR_WAY3 (1 << 3) /* Bit 3: Clean Invalidate Way Number 3 */ +#define L2CC_CIWR_WAY4 (1 << 4) /* Bit 4: Clean Invalidate Way Number 4 */ +#define L2CC_CIWR_WAY5 (1 << 5) /* Bit 5: Clean Invalidate Way Number 5 */ +#define L2CC_CIWR_WAY6 (1 << 6) /* Bit 6: Clean Invalidate Way Number 6 */ +#define L2CC_CIWR_WAY7 (1 << 7) /* Bit 7: Clean Invalidate Way Number 7 */ /* Data Lockdown Register */ #define L2CC_DLKR_DLK(n) (1 << (n)) /* Bits 0-7: Data Lockdown in Way Number n, n=0..7 */ -# define L2CC_DLKR_DLK0 (1 << 0) /* Bit 0: Data Lockdown in Way Number 0 */ -# define L2CC_DLKR_DLK1 (1 << 1) /* Bit 1: Data Lockdown in Way Number 1 */ -# define L2CC_DLKR_DLK2 (1 << 2) /* Bit 2: Data Lockdown in Way Number 2 */ -# define L2CC_DLKR_DLK3 (1 << 3) /* Bit 3: Data Lockdown in Way Number 3 */ -# define L2CC_DLKR_DLK4 (1 << 4) /* Bit 4: Data Lockdown in Way Number 4 */ -# define L2CC_DLKR_DLK5 (1 << 5) /* Bit 5: Data Lockdown in Way Number 5 */ -# define L2CC_DLKR_DLK6 (1 << 6) /* Bit 6: Data Lockdown in Way Number 6 */ -# define L2CC_DLKR_DLK7 (1 << 7) /* Bit 7: Data Lockdown in Way Number 7 */ +#define L2CC_DLKR_DLK0 (1 << 0) /* Bit 0: Data Lockdown in Way Number 0 */ +#define L2CC_DLKR_DLK1 (1 << 1) /* Bit 1: Data Lockdown in Way Number 1 */ +#define L2CC_DLKR_DLK2 (1 << 2) /* Bit 2: Data Lockdown in Way Number 2 */ +#define L2CC_DLKR_DLK3 (1 << 3) /* Bit 3: Data Lockdown in Way Number 3 */ +#define L2CC_DLKR_DLK4 (1 << 4) /* Bit 4: Data Lockdown in Way Number 4 */ +#define L2CC_DLKR_DLK5 (1 << 5) /* Bit 5: Data Lockdown in Way Number 5 */ +#define L2CC_DLKR_DLK6 (1 << 6) /* Bit 6: Data Lockdown in Way Number 6 */ +#define L2CC_DLKR_DLK7 (1 << 7) /* Bit 7: Data Lockdown in Way Number 7 */ /* Instruction Lockdown Register */ #define L2CC_ILKR_ILK(n) (1 << (n)) /* Bits 0-7: Instruction Lockdown in Way Number n, n=0..7 */ -# define L2CC_ILKR_ILK0 (1 << 0) /* Bit 0: Instruction Lockdown in Way Number 0 */ -# define L2CC_ILKR_ILK1 (1 << 1) /* Bit 1: Instruction Lockdown in Way Number 1 */ -# define L2CC_ILKR_ILK2 (1 << 2) /* Bit 2: Instruction Lockdown in Way Number 2 */ -# define L2CC_ILKR_ILK3 (1 << 3) /* Bit 3: Instruction Lockdown in Way Number 3 */ -# define L2CC_ILKR_ILK4 (1 << 4) /* Bit 4: Instruction Lockdown in Way Number 4 */ -# define L2CC_ILKR_ILK5 (1 << 5) /* Bit 5: Instruction Lockdown in Way Number 5 */ -# define L2CC_ILKR_ILK6 (1 << 6) /* Bit 6: Instruction Lockdown in Way Number 6 */ -# define L2CC_ILKR_ILK7 (1 << 7) /* Bit 7: Instruction Lockdown in Way Number 7 */ +#define L2CC_ILKR_ILK0 (1 << 0) /* Bit 0: Instruction Lockdown in Way Number 0 */ +#define L2CC_ILKR_ILK1 (1 << 1) /* Bit 1: Instruction Lockdown in Way Number 1 */ +#define L2CC_ILKR_ILK2 (1 << 2) /* Bit 2: Instruction Lockdown in Way Number 2 */ +#define L2CC_ILKR_ILK3 (1 << 3) /* Bit 3: Instruction Lockdown in Way Number 3 */ +#define L2CC_ILKR_ILK4 (1 << 4) /* Bit 4: Instruction Lockdown in Way Number 4 */ +#define L2CC_ILKR_ILK5 (1 << 5) /* Bit 5: Instruction Lockdown in Way Number 5 */ +#define L2CC_ILKR_ILK6 (1 << 6) /* Bit 6: Instruction Lockdown in Way Number 6 */ +#define L2CC_ILKR_ILK7 (1 << 7) /* Bit 7: Instruction Lockdown in Way Number 7 */ /* Lock Line Enable Register */ @@ -453,8 +455,8 @@ #ifdef CONFIG_PL310_LOCKDOWN_BY_LINE # define L2CC_UNLKW_WAY_SHIFT (0) /* Bits 0-15: Unlock line for corresponding way */ # define L2CC_UNLKW_WAY_MASK (0xffff << L2CC_UNLKW_WAY_SHIFT) -# define L2CC_UNLKW_WAY_SET(n) ((uint32_t)(n) << L2CC_UNLKW_WAY_SHIFT) -# define L2CC_UNLKW_WAY_BIT(n) ((1 << (n)) << L2CC_UNLKW_WAY_SHIFT) +# define L2CC_UNLKW_WAY_SET(n) ((uint32_t)(n) << L2CC_UNLKW_WAY_SHIFT) +# define L2CC_UNLKW_WAY_BIT(n) ((1 << (n)) << L2CC_UNLKW_WAY_SHIFT) #endif /* Address filter start */ @@ -480,7 +482,7 @@ #define L2CC_PCR_SHIFT (0) /* Bits 0-4: Prefetch Offset */ #define L2CC_PCR_MASK (31 << L2CC_PCR_SHIFT) -# define L2CC_PCR_PREFETCH(n) ((uint32_t)(n) << L2CC_PCR_SHIFT) +#define L2CC_PCR_PREFETCH(n) ((uint32_t)(n) << L2CC_PCR_SHIFT) #define L2CC_PCR_NSIDEN (1 << 21) /* Bit 21: Not Same ID on Exclusive Sequence Enable */ #define L2CC_PCR_IDLEN (1 << 23) /* Bit 23: INCR Double Linefill Enable */ #define L2CC_PCR_PDEN (1 << 24) /* Bit 24: Prefetch Drop Enable */ diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h index 332b50b5ed7..83eb36036a0 100644 --- a/arch/arm/src/armv7-a/mmu.h +++ b/arch/arm/src/armv7-a/mmu.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/************************************************************************************************************ * arch/arm/src/armv7-a/mmu.h * CP15 MMU register definitions * @@ -40,14 +40,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ************************************************************************************************************/ #ifndef __ARCH_ARM_SRC_ARMV7_A_MMU_H #define __ARCH_ARM_SRC_ARMV7_A_MMU_H -/************************************************************************************ +/************************************************************************************************************ * Included Files - ************************************************************************************/ + ************************************************************************************************************/ #include @@ -57,10 +57,11 @@ # include "chip.h" #endif /* __ASSEMBLY__ */ -/************************************************************************************ +/************************************************************************************************************ * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ************************************************************************************************************/ + +/* Configuration ********************************************************************************************/ #if defined(CONFIG_PAGING) || defined(CONFIG_ARCH_ADDRENV) @@ -73,7 +74,8 @@ #endif #endif /* CONFIG_PAGING */ -/* MMU CP15 Register Bit Definitions ************************************************/ +/* MMU CP15 Register Bit Definitions ************************************************************************/ + /* Reference: Cortex-A5 MPCore Paragraph 6.7, "MMU software accessible registers." */ /* TLB Type Register TLB Type Register @@ -84,9 +86,10 @@ */ /* System Control Register (SCTLR). see cstlr.h */ + /* Non-secure Access Control Register (NSACR). See cstlr.h */ -/* Translation Table Base Register 0 (TTBR0)*/ +/* Translation Table Base Register 0 (TTBR0) */ #define TTBR0_IRGN1 (1 << 0) /* Bit 0: Inner cacheability IRGN[1] (MP extensions) */ #define TTBR0_C (1 << 0) /* Bit 0: Inner cacheability for table walk */ @@ -94,15 +97,17 @@ /* Bit 2: Reserved */ #define TTBR0_RGN_SHIFT (3) /* Bits 3-4: Outer cacheable attributes for table walk */ #define TTBR0_RGN_MASK (3 << TTBR0_RGN_SHIFT) -# define TTBR0_RGN_NONE (0 << TTBR0_RGN_SHIFT) /* Non-cacheable */ -# define TTBR0_RGN_WBWA (1 << TTBR0_RGN_SHIFT) /* Write-Back cached + Write-Allocate */ -# define TTBR0_RGN_WT (2 << TTBR0_RGN_SHIFT) /* Write-Through */ -# define TTBR0_RGN_WB (3 << TTBR0_RGN_SHIFT) /* Write-Back */ -#define TTBR0_NOS (1 << 5) /* Bit 5: Not Outer Shareable bit */ -#define TTBR0_IRGN0 (1 << 6) /* Bit 6: Inner cacheability IRGN[0] (MP extensions) */ - /* Bits 7-n: Reserved, n=7-13 */ +#define TTBR0_RGN_NONE (0 << TTBR0_RGN_SHIFT) /* Non-cacheable */ +#define TTBR0_RGN_WBWA (1 << TTBR0_RGN_SHIFT) /* Write-Back cached + Write-Allocate */ +#define TTBR0_RGN_WT (2 << TTBR0_RGN_SHIFT) /* Write-Through */ +#define TTBR0_RGN_WB (3 << TTBR0_RGN_SHIFT) /* Write-Back */ +#define TTBR0_NOS (1 << 5) /* Bit 5: Not Outer Shareable bit */ +#define TTBR0_IRGN0 (1 << 6) /* Bit 6: Inner cacheability IRGN[0] (MP extensions) */ + /* Bits 7-n: Reserved, n=7-13 */ + #define _TTBR0_LOWER(n) (0xffffffff << (n)) - /* Bits (n+1)-31: Translation table base 0 */ + /* Bits (n+1)-31: Translation table base 0 */ + #define TTBR0_BASE_MASK(n) (~_TTBR0_LOWER(n)) /* Translation Table Base Register 1 (TTBR1) */ @@ -113,13 +118,14 @@ /* Bit 2: Reserved */ #define TTBR1_RGN_SHIFT (3) /* Bits 3-4: Outer cacheable attributes for table walk */ #define TTBR1_RGN_MASK (3 << TTBR1_RGN_SHIFT) -# define TTBR1_RGN_NONE (0 << TTBR1_RGN_SHIFT) /* Non-cacheable */ -# define TTBR1_RGN_WBWA (1 << TTBR1_RGN_SHIFT) /* Write-Back cached + Write-Allocate */ -# define TTBR1_RGN_WT (2 << TTBR1_RGN_SHIFT) /* Write-Through */ -# define TTBR1_RGN_WB (3 << TTBR1_RGN_SHIFT) /* Write-Back */ -#define TTBR1_NOS (1 << 5) /* Bit 5: Not Outer Shareable bit */ -#define TTBR1_IRGN0 (1 << 6) /* Bit 6: Inner cacheability IRGN[0] (MP extensions) */ - /* Bits 7-13: Reserved */ +#define TTBR1_RGN_NONE (0 << TTBR1_RGN_SHIFT) /* Non-cacheable */ +#define TTBR1_RGN_WBWA (1 << TTBR1_RGN_SHIFT) /* Write-Back cached + Write-Allocate */ +#define TTBR1_RGN_WT (2 << TTBR1_RGN_SHIFT) /* Write-Through */ +#define TTBR1_RGN_WB (3 << TTBR1_RGN_SHIFT) /* Write-Back */ +#define TTBR1_NOS (1 << 5) /* Bit 5: Not Outer Shareable bit */ +#define TTBR1_IRGN0 (1 << 6) /* Bit 6: Inner cacheability IRGN[0] (MP extensions) */ + /* Bits 7-13: Reserved */ + #define TTBR1_BASE_SHIFT (14) /* Bits 14-31: Translation table base 1 */ #define TTBR1_BASE_MASK (0xffffc000) @@ -127,14 +133,14 @@ #define TTBCR_N_SHIFT (0) /* Bits 0-2: Boundary size of TTBR0 */ #define TTBCR_N_MASK (7 << TTBCR_N_SHIFT) -# define TTBCR_N_16KB (0 << TTBCR_N_SHIFT) /* Reset value */ -# define TTBCR_N_8KB (1 << TTBCR_N_SHIFT) -# define TTBCR_N_4KB (2 << TTBCR_N_SHIFT) -# define TTBCR_N_2KB (3 << TTBCR_N_SHIFT) -# define TTBCR_N_1KB (4 << TTBCR_N_SHIFT) -# define TTBCR_N_512B (5 << TTBCR_N_SHIFT) -# define TTBCR_N_256B (6 << TTBCR_N_SHIFT) -# define TTBCR_N_128B (7 << TTBCR_N_SHIFT) +#define TTBCR_N_16KB (0 << TTBCR_N_SHIFT) /* Reset value */ +#define TTBCR_N_8KB (1 << TTBCR_N_SHIFT) +#define TTBCR_N_4KB (2 << TTBCR_N_SHIFT) +#define TTBCR_N_2KB (3 << TTBCR_N_SHIFT) +#define TTBCR_N_1KB (4 << TTBCR_N_SHIFT) +#define TTBCR_N_512B (5 << TTBCR_N_SHIFT) +#define TTBCR_N_256B (6 << TTBCR_N_SHIFT) +#define TTBCR_N_128B (7 << TTBCR_N_SHIFT) /* Bit 3: Reserved */ #define TTBCR_PD0 (1 << 4) /* Bit 4: Translation table walk on a TLB miss w/TTBR0 */ #define TTBCR_PD1 (1 << 5) /* Bit 5: Translation table walk on a TLB miss w/TTBR1 */ @@ -144,9 +150,9 @@ #define DACR_SHIFT(n) ((n) << 1) /* Domain n, n=0-15 */ #define DACR_MASK(n) (3 << DACR_SHIFT(n)) -# define DACR_NONE(n) (0 << DACR_SHIFT(n)) /* Any access generates a domain fault */ -# define DACR_CLIENT(n) (1 << DACR_SHIFT(n)) /* Accesses checked against permissions TLB */ -# define DACR_MANAGER(n) (3 << DACR_SHIFT(n)) /* Accesses are not checked */ +#define DACR_NONE(n) (0 << DACR_SHIFT(n)) /* Any access generates a domain fault */ +#define DACR_CLIENT(n) (1 << DACR_SHIFT(n)) /* Accesses checked against permissions TLB */ +#define DACR_MANAGER(n) (3 << DACR_SHIFT(n)) /* Accesses are not checked */ /* Data Fault Status Register (DFSR) */ @@ -222,6 +228,7 @@ #define TLB_VA_MASK (0xfffff000) /* Bits 12-31: Virtual address */ /* Primary Region Remap Register (PRRR) */ + /* Normal Memory Remap Register (NMRR) */ /* TLB Hitmap Register (TLBHR) */ @@ -234,7 +241,8 @@ /* Context ID Register (CONTEXTIDR). See cstlr.h */ -/* Translation Table Definitions ****************************************************/ +/* Translation Table Definitions ****************************************************************************/ + /* Hardware translation table definitions. Only the "short descriptor format" is * supported. * @@ -245,11 +253,11 @@ #define PMD_TYPE_SHIFT (0) /* Bits: 1:0: Type of mapping */ #define PMD_TYPE_MASK (3 << PMD_TYPE_SHIFT) -# define PMD_TYPE_FAULT (0 << PMD_TYPE_SHIFT) /* None */ -# define PMD_TYPE_PTE (1 << PMD_TYPE_SHIFT) /* Page table */ -# define PMD_TYPE_SECT (2 << PMD_TYPE_SHIFT) /* Section or supersection */ -# define PMD_TYPE_PXN (3 << PMD_TYPE_SHIFT) /* PXN Section or supersection */ - /* Bits 2-31: Depend on the mapping type */ +#define PMD_TYPE_FAULT (0 << PMD_TYPE_SHIFT) /* None */ +#define PMD_TYPE_PTE (1 << PMD_TYPE_SHIFT) /* Page table */ +#define PMD_TYPE_SECT (2 << PMD_TYPE_SHIFT) /* Section or supersection */ +#define PMD_TYPE_PXN (3 << PMD_TYPE_SHIFT) /* PXN Section or supersection */ + /* Bits 2-31: Depend on the mapping type */ /* Level 1 Fault Translation Table Format. * @@ -271,7 +279,7 @@ /* Bit 4: Should be zero (SBZ) */ #define PMD_PTE_DOM_SHIFT (5) /* Bits 5-8: Domain */ #define PMD_PTE_DOM_MASK (15 << PMD_PTE_DOM_SHIFT) -# define PMD_PTE_DOM(n) ((n) << PMD_PTE_DOM_SHIFT) +#define PMD_PTE_DOM(n) ((n) << PMD_PTE_DOM_SHIFT) /* Bit 9: Not implemented */ #define PMD_PTE_PADDR_MASK (0xfffffc00) /* Bits 10-31: Page table base address */ @@ -300,13 +308,13 @@ #define PMD_SECT_XN (1 << 4) /* Bit 4: Execute-never bit */ #define PMD_SECT_DOM_SHIFT (5) /* Bits 5-8: Domain */ #define PMD_SECT_DOM_MASK (15 << PMD_SECT_DOM_SHIFT) -# define PMD_SECT_DOM(n) ((n) << PMD_SECT_DOM_SHIFT) +#define PMD_SECT_DOM(n) ((n) << PMD_SECT_DOM_SHIFT) /* Bit 9: Implementation defined */ #define PMD_SECT_AP_SHIFT (10) /* Bits 10-11: Access Permissions bits AP[0:1] */ #define PMD_SECT_AP_MASK (3 << PMD_SECT_AP_SHIFT) -# define PMD_SECT_AP0 (1 << PMD_SECT_AP_SHIFT) /* AP[0]: Access permission bit 0 */ -# define PMD_SECT_AP1 (2 << PMD_SECT_AP_SHIFT) /* AP[1]: Access permission bit 1 */ -#define PMD_SECT_TEX_SHIFT (12) /* Bits 12-14: Memory region attribute bits */ +#define PMD_SECT_AP0 (1 << PMD_SECT_AP_SHIFT) /* AP[0]: Access permission bit 0 */ +#define PMD_SECT_AP1 (2 << PMD_SECT_AP_SHIFT) /* AP[1]: Access permission bit 1 */ +#define PMD_SECT_TEX_SHIFT (12) /* Bits 12-14: Memory region attribute bits */ #define PMD_SECT_TEX_MASK (7 << PMD_SECT_TEX_SHIFT) #define PMD_SECT_AP2 (1 << 15) /* Bit 15: AP[2]: Access permission bit 2 */ #define PMD_SECT_S (1 << 16) /* Bit 16: Shareable bit */ @@ -402,26 +410,29 @@ #define PTE_TYPE_SHIFT (0) /* Bits: 1:0: Type of mapping */ #define PTE_TYPE_MASK (3 << PTE_TYPE_SHIFT) -# define PTE_TYPE_FAULT (0 << PTE_TYPE_SHIFT) /* None */ -# define PTE_TYPE_LARGE (1 << PTE_TYPE_SHIFT) /* 64Kb of memory */ -# define PTE_TYPE_SMALL (2 << PTE_TYPE_SHIFT) /* 4Kb of memory */ -#define PTE_B (1 << 2) /* Bit 2: Bufferable bit */ -#define PTE_C (1 << 3) /* Bit 3: Cacheable bit */ -#define PTE_AP_SHIFT (4) /* Bits 4-5: Access Permissions bits AP[0:1] */ +#define PTE_TYPE_FAULT (0 << PTE_TYPE_SHIFT) /* None */ +#define PTE_TYPE_LARGE (1 << PTE_TYPE_SHIFT) /* 64Kb of memory */ +#define PTE_TYPE_SMALL (2 << PTE_TYPE_SHIFT) /* 4Kb of memory */ +#define PTE_B (1 << 2) /* Bit 2: Bufferable bit */ +#define PTE_C (1 << 3) /* Bit 3: Cacheable bit */ +#define PTE_AP_SHIFT (4) /* Bits 4-5: Access Permissions bits AP[0:1] */ #define PTE_AP_MASK (3 << PTE_AP_SHIFT) -# define PTE_AP0 (1 << PTE_AP_SHIFT) /* AP[0]: Access permission bit 0 */ -# define PTE_AP1 (2 << PTE_AP_SHIFT) /* AP[1]: Access permission bit 1 */ - /* Bits 6-8: Depend on entry type */ -#define PTE_AP2 (1 << 9) /* Bit 9: AP[2]: Access permission bit 2 */ -#define PTE_S (1 << 10) /* Bit 10: Shareable bit */ -#define PTE_NG (1 << 11) /* Bit 11: Not global bit. */ - /* Bits 12-31:Depend on entry type */ +#define PTE_AP0 (1 << PTE_AP_SHIFT) /* AP[0]: Access permission bit 0 */ +#define PTE_AP1 (2 << PTE_AP_SHIFT) /* AP[1]: Access permission bit 1 */ + /* Bits 6-8: Depend on entry type */ +#define PTE_AP2 (1 << 9) /* Bit 9: AP[2]: Access permission bit 2 */ +#define PTE_S (1 << 10) /* Bit 10: Shareable bit */ +#define PTE_NG (1 << 11) /* Bit 11: Not global bit. */ + /* Bits 12-31:Depend on entry type */ /* Large page -- 64Kb */ - /* Bits: 1:0: Type of mapping */ - /* Bit 2: Bufferable bit */ - /* Bit 3: Cacheable bit */ - /* Bits 4-5: Access Permissions bits AP[0:1] */ + +/* Bits: 1:0: Type of mapping + * Bit 2: Bufferable bit + * Bit 3: Cacheable bit + * Bits 4-5: Access Permissions bits AP[0:1] + */ + #define PTE_LARGE_TEX_SHIFT (12) /* Bits 12-14: Memory region attribute bits */ #define PTE_LARGE_TEX_MASK (7 << PTE_LARGE_TEX_SHIFT) #define PTE_LARGE_XN (1 << 15) /* Bit 15: Execute-never bit */ @@ -430,10 +441,12 @@ /* Small page -- 4Kb */ - /* Bits: 1:0: Type of mapping */ - /* Bit 2: Bufferable bit */ - /* Bit 3: Cacheable bit */ - /* Bits 4-5: Access Permissions bits AP[0:1] */ +/* Bits: 1:0: Type of mapping + * Bit 2: Bufferable bit + * Bit 3: Cacheable bit + * Bits 4-5: Access Permissions bits AP[0:1] + */ + #define PTE_SMALL_FLAG_MASK (0x0000003f) /* Bits 0-11: MMU flags (mostly) */ #define PTE_SMALL_PADDR_MASK (0xfffff000) /* Bits 12-31: Small page base address, PA[31:12] */ @@ -571,8 +584,15 @@ #define MMU_ROMFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_R1 | PMD_CACHEABLE | \ PMD_SECT_DOM(0)) + +#ifdef CONFIG_SMP +#define MMU_MEMFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | PMD_CACHEABLE | \ + PMD_SECT_S | PMD_SECT_DOM(0)) +#else #define MMU_MEMFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | PMD_CACHEABLE | \ PMD_SECT_DOM(0)) +#endif + #define MMU_IOFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | PMD_DEVICE | \ PMD_SECT_DOM(0) | PMD_SECT_XN) #define MMU_STRONGLY_ORDERED (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | \ @@ -626,7 +646,7 @@ #define PGTABLE_SIZE 0x00004000 -/* Virtual Page Table Location ******************************************************/ +/* Virtual Page Table Location ******************************************************************************/ #ifdef CONFIG_PAGING /* Check if the virtual address of the page table has been defined. It @@ -648,7 +668,7 @@ #endif /* PGTABLE_BASE_VADDR */ -/* MMU flags ************************************************************************/ +/* MMU flags ************************************************************************************************/ /* Create some friendly definitions to handle page table entries */ @@ -670,7 +690,7 @@ #define PG_L1_PADDRMASK PMD_SECT_PADDR_MASK -/* Addresses of Memory Regions ******************************************************/ +/* Addresses of Memory Regions ******************************************************************************/ /* We position the locked region PTEs at an offset into the first * L2 page table. The L1 entry points to an 1Mb aligned virtual @@ -720,7 +740,7 @@ #define PG_L2_DATA_VADDR (PG_L2_LOCKED_VADDR + PG_L2_TEXT_SIZE) #define PG_L2_DATA_SIZE (4*PG_DATA_NPAGES) -/* Page Table Info ******************************************************************/ +/* Page Table Info ******************************************************************************************/ /* The number of pages in the in the page table (PG_PGTABLE_NPAGES). We * position the page table PTEs just after the data section PTEs. @@ -734,7 +754,7 @@ #define PG_L2_PGTABLE_VADDR (PG_L2_DATA_VADDR + PG_L2_DATA_SIZE) #define PG_L2_PGTABLE_SIZE (4*PG_DATA_NPAGES) -/* Vector Mapping *******************************************************************/ +/* Vector Mapping *******************************************************************************************/ /* One page is required to map the vector table. The vector table could lie * at virtual address zero (or at the start of RAM which is aliased to address @@ -788,7 +808,7 @@ # error "Logic missing for high vectors in this case" #endif -/* Page Usage ***********************************************************************/ +/* Page Usage ***********************************************************************************************/ /* This is the total number of pages used in the text/data mapping: */ @@ -803,7 +823,7 @@ # error "Total pages required exceeds RAM size" #endif -/* Page Management ******************************************************************/ +/* Page Management ******************************************************************************************/ /* For page management purposes, the following summarize the "heap" of * free pages, operations on free pages and the L2 page table. @@ -868,9 +888,9 @@ #endif /* CONFIG_PAGING */ -/************************************************************************************ +/************************************************************************************************************ * Public Types - ************************************************************************************/ + ************************************************************************************************************/ #ifndef __ASSEMBLY__ /* struct section_mapping_s describes the L1 mapping of a large region of memory @@ -888,13 +908,13 @@ struct section_mapping_s }; #endif -/************************************************************************************ +/************************************************************************************************************ * Assembly Macros - ************************************************************************************/ + ************************************************************************************************************/ #ifdef __ASSEMBLY__ -/************************************************************************************ +/************************************************************************************************************ * Name: cp15_disable_mmu * * Description: @@ -903,15 +923,15 @@ struct section_mapping_s * Input Parameters: * None * - ************************************************************************************/ + ************************************************************************************************************/ - .macro cp15_disable_mmu, scratch - mrc p15, 0, \scratch, c1, c0, 0 - bic \scratch, \scratch, #1 - mcr p15, 0, \scratch, c1, c0, 0 - .endm + .macro cp15_disable_mmu, scratch + mrc p15, 0, \scratch, c1, c0, 0 + bic \scratch, \scratch, #1 + mcr p15, 0, \scratch, c1, c0, 0 + .endm -/************************************************************************************ +/************************************************************************************************************ * Name: cp15_invalidate_tlbs * * Description: @@ -925,13 +945,13 @@ struct section_mapping_s * Input Parameters: * None * - ************************************************************************************/ + ************************************************************************************************************/ - .macro cp15_invalidate_tlbs, scratch - mcr p15, 0, \scratch, c8, c7, 0 /* TLBIALL */ - .endm + .macro cp15_invalidate_tlbs, scratch + mcr p15, 0, \scratch, c8, c7, 0 /* TLBIALL */ + .endm -/************************************************************************************ +/************************************************************************************************************ * Name: cp15_invalidate_tlb_bymva * * Description: @@ -940,20 +960,20 @@ struct section_mapping_s * Input Parameters: * vaddr - The virtual address to be invalidated * - ************************************************************************************/ + ************************************************************************************************************/ - .macro cp15_invalidate_tlb_bymva, vaddr - dsb + .macro cp15_invalidate_tlb_bymva, vaddr + dsb #if defined(CONFIG_ARCH_CORTEXA8) - mcr p15, 0, \vaddr, c8, c7, 1 /* TLBIMVA */ + mcr p15, 0, \vaddr, c8, c7, 1 /* TLBIMVA */ #else - mcr p15, 0, \vaddr, c8, c3, 3 /* TLBIMVAAIS */ + mcr p15, 0, \vaddr, c8, c3, 3 /* TLBIMVAAIS */ #endif - dsb - isb - .endm + dsb + isb + .endm -/************************************************************************************ +/************************************************************************************************************ * Name: cp15_wrdacr * * Description: @@ -962,21 +982,21 @@ struct section_mapping_s * Input Parameters: * dacr - The new value of the DACR * - ************************************************************************************/ + ************************************************************************************************************/ - .macro cp15_wrdacr, dacr - mcr p15, 0, \dacr, c3, c0, 0 - nop - nop - nop - nop - nop - nop - nop - nop - .endm + .macro cp15_wrdacr, dacr + mcr p15, 0, \dacr, c3, c0, 0 + nop + nop + nop + nop + nop + nop + nop + nop + .endm -/************************************************************************************ +/************************************************************************************************************ * Name: cp15_wrttb * * Description: @@ -989,23 +1009,23 @@ struct section_mapping_s * Input Parameters: * ttb - The new value of the TTBR0 register * - ************************************************************************************/ + ************************************************************************************************************/ - .macro cp15_wrttb, ttb, scratch - mcr p15, 0, \ttb, c2, c0, 0 - nop - nop - nop - nop - nop - nop - nop - nop - mov \scratch, #0x0 - mcr p15, 0, \scratch, c2, c0, 2 - .endm + .macro cp15_wrttb, ttb, scratch + mcr p15, 0, \ttb, c2, c0, 0 + nop + nop + nop + nop + nop + nop + nop + nop + mov \scratch, #0x0 + mcr p15, 0, \scratch, c2, c0, 2 + .endm -/************************************************************************************ +/************************************************************************************************************ * Name: pg_l2map * * Description: @@ -1013,11 +1033,11 @@ struct section_mapping_s * written. This macro is used when CONFIG_PAGING is enable. This case, * it is used as follows: * - * ldr r0, =PGTABLE_L2_BASE_PADDR <-- Address in L2 table - * ldr r1, =PG_LOCKED_PBASE <-- Physical page memory address - * ldr r2, =CONFIG_PAGING_NLOCKED <-- number of pages - * ldr r3, =MMUFLAGS <-- L2 MMU flags - * pg_l2map r0, r1, r2, r3, r4 + * ldr r0, =PGTABLE_L2_BASE_PADDR <-- Address in L2 table + * ldr r1, =PG_LOCKED_PBASE <-- Physical page memory address + * ldr r2, =CONFIG_PAGING_NLOCKED <-- number of pages + * ldr r3, =MMUFLAGS <-- L2 MMU flags + * pg_l2map r0, r1, r2, r3, r4 * * Input Parameters: * l2 - Physical or virtual start address in the L2 page table, depending @@ -1038,44 +1058,44 @@ struct section_mapping_s * - The L2 page tables have been zeroed prior to calling this function * - pg_l1span has been called to initialize the L1 table. * - ************************************************************************************/ + ************************************************************************************************************/ #ifdef CONFIG_PAGING - .macro pg_l2map, l2, ppage, npages, mmuflags, tmp - b 2f + .macro pg_l2map, l2, ppage, npages, mmuflags, tmp + b 2f 1: - /* Write the one L2 entries. First, get tmp = (ppage | mmuflags), - * the value to write into the L2 PTE - */ + /* Write the one L2 entries. First, get tmp = (ppage | mmuflags), + * the value to write into the L2 PTE + */ - orr \tmp, \ppage, \mmuflags + orr \tmp, \ppage, \mmuflags - /* Write value into table at the current table address - * (and increment the L2 page table address by 4) - */ + /* Write value into table at the current table address + * (and increment the L2 page table address by 4) + */ - str \tmp, [\l2], #4 + str \tmp, [\l2], #4 - /* Update the physical address that will correspond to the next - * table entry. - */ + /* Update the physical address that will correspond to the next + * table entry. + */ - add \ppage, \ppage, #CONFIG_PAGING_PAGESIZE + add \ppage, \ppage, #CONFIG_PAGING_PAGESIZE - /* Decrement the number of pages written */ + /* Decrement the number of pages written */ - sub \npages, \npages, #1 + sub \npages, \npages, #1 2: - /* Check if all of the pages have been written. If not, then - * loop and write the next PTE. - */ + /* Check if all of the pages have been written. If not, then + * loop and write the next PTE. + */ - cmp \npages, #0 - bgt 1b - .endm + cmp \npages, #0 + bgt 1b + .endm #endif /* CONFIG_PAGING */ -/************************************************************************************ +/************************************************************************************************************ * Name: pg_l1span * * Description: @@ -1083,12 +1103,12 @@ struct section_mapping_s * entries will be written as many as needed to span npages. This macro is * used when CONFIG_PAGING is enable. In this case, it is used as follows: * - * ldr r0, =PG_L1_PGTABLE_PADDR <-- Address in the L1 table - * ldr r1, =PG_L2_PGTABLE_PADDR <-- Physical address of L2 page table - * ldr r2, =PG_PGTABLE_NPAGES <-- Total number of pages - * ldr r3, =PG_PGTABLE_NPAGE1 <-- Number of pages in the first PTE - * ldr r4, =MMU_L1_PGTABFLAGS <-- L1 MMU flags - * pg_l1span r0, r1, r2, r3, r4, r4 + * ldr r0, =PG_L1_PGTABLE_PADDR <-- Address in the L1 table + * ldr r1, =PG_L2_PGTABLE_PADDR <-- Physical address of L2 page table + * ldr r2, =PG_PGTABLE_NPAGES <-- Total number of pages + * ldr r3, =PG_PGTABLE_NPAGE1 <-- Number of pages in the first PTE + * ldr r4, =MMU_L1_PGTABFLAGS <-- L1 MMU flags + * pg_l1span r0, r1, r2, r3, r4, r4 * * Input Parameters (unmodified unless noted): * l1 - Physical or virtual address in the L1 table to begin writing (modified) @@ -1111,56 +1131,56 @@ struct section_mapping_s * - The MMU is not yet enabled * - The L2 page tables have been zeroed prior to calling this function * - ************************************************************************************/ + ************************************************************************************************************/ #ifdef CONFIG_PAGING - .macro pg_l1span, l1, l2, npages, ppage, mmuflags, tmp - b 2f + .macro pg_l1span, l1, l2, npages, ppage, mmuflags, tmp + b 2f 1: - /* Write the L1 table entry that refers to this (unmapped) small page - * table. - * - * tmp = (l2table | mmuflags), the value to write into the page table - */ + /* Write the L1 table entry that refers to this (unmapped) small page + * table. + * + * tmp = (l2table | mmuflags), the value to write into the page table + */ - orr \tmp, \l2, \mmuflags + orr \tmp, \l2, \mmuflags - /* Write the value into the L1 table at the correct offset. - * (and increment the L1 table address by 4) - */ + /* Write the value into the L1 table at the correct offset. + * (and increment the L1 table address by 4) + */ - str \tmp, [\l1], #4 + str \tmp, [\l1], #4 - /* Update the L2 page table address for the next L1 table entry. */ + /* Update the L2 page table address for the next L1 table entry. */ - add \l2, \l2, #PT_SIZE /* Next L2 page table start address */ + add \l2, \l2, #PT_SIZE /* Next L2 page table start address */ - /* Update the number of pages that we have account for (with - * non-mappings). NOTE that the first page may have fewer than - * the maximum entries per page table. - */ + /* Update the number of pages that we have account for (with + * non-mappings). NOTE that the first page may have fewer than + * the maximum entries per page table. + */ - sub \npages, \npages, \ppage - mov \ppage, #PTE_NPAGES + sub \npages, \npages, \ppage + mov \ppage, #PTE_NPAGES 2: - /* Check if all of the pages have been written. If not, then - * loop and write the next L1 entry. - */ + /* Check if all of the pages have been written. If not, then + * loop and write the next L1 entry. + */ - cmp \npages, #0 - bgt 1b - .endm + cmp \npages, #0 + bgt 1b + .endm #endif /* CONFIG_PAGING */ #endif /* __ASSEMBLY__ */ -/************************************************************************************ +/************************************************************************************************************ * Inline Functions - ************************************************************************************/ + ************************************************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/************************************************************************************************************ * Name: cp15_disable_mmu * * Description: @@ -1169,7 +1189,7 @@ struct section_mapping_s * Input Parameters: * None * - ************************************************************************************/ + ************************************************************************************************************/ static inline void cp15_disable_mmu(void) { @@ -1184,7 +1204,7 @@ static inline void cp15_disable_mmu(void) ); } -/************************************************************************************ +/************************************************************************************************************ * Name: cp15_invalidate_tlbs * * Description: @@ -1198,7 +1218,7 @@ static inline void cp15_disable_mmu(void) * Input Parameters: * None * - ************************************************************************************/ + ************************************************************************************************************/ static inline void cp15_invalidate_tlbs(void) { @@ -1211,7 +1231,7 @@ static inline void cp15_invalidate_tlbs(void) ); } -/************************************************************************************ +/************************************************************************************************************ * Name: cp15_invalidate_tlb_bymva * * Description: @@ -1220,7 +1240,7 @@ static inline void cp15_invalidate_tlbs(void) * Input Parameters: * vaddr - The virtual address to be invalidated * - ************************************************************************************/ + ************************************************************************************************************/ static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr) { @@ -1240,7 +1260,7 @@ static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr) ); } -/************************************************************************************ +/************************************************************************************************************ * Name: cp15_wrdacr * * Description: @@ -1249,7 +1269,7 @@ static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr) * Input Parameters: * dacr - The new value of the DACR * - ************************************************************************************/ + ************************************************************************************************************/ static inline void cp15_wrdacr(unsigned int dacr) { @@ -1270,7 +1290,7 @@ static inline void cp15_wrdacr(unsigned int dacr) ); } -/************************************************************************************ +/************************************************************************************************************ * Name: cp15_wrttb * * Description: @@ -1283,7 +1303,7 @@ static inline void cp15_wrdacr(unsigned int dacr) * Input Parameters: * ttb - The new value of the TTBR0 register * - ************************************************************************************/ + ************************************************************************************************************/ static inline void cp15_wrttb(unsigned int ttb) { @@ -1306,7 +1326,7 @@ static inline void cp15_wrttb(unsigned int ttb) ); } -/************************************************************************************* +/************************************************************************************************************ * Name: mmu_l1_getentry * * Description: @@ -1315,12 +1335,12 @@ static inline void cp15_wrttb(unsigned int ttb) * Input Parameters: * vaddr - The virtual address to be mapped. * - ************************************************************************************/ + ************************************************************************************************************/ #ifndef CONFIG_ARCH_ROMPGTABLE static inline uint32_t mmu_l1_getentry(uint32_t vaddr) { - uint32_t *l1table = (uint32_t*)PGTABLE_BASE_VADDR; + uint32_t *l1table = (uint32_t *)PGTABLE_BASE_VADDR; uint32_t index = vaddr >> 20; /* Return the address of the page table entry */ @@ -1329,7 +1349,7 @@ static inline uint32_t mmu_l1_getentry(uint32_t vaddr) } #endif -/************************************************************************************* +/************************************************************************************************************ * Name: mmu_l2_getentry * * Description: @@ -1340,12 +1360,12 @@ static inline uint32_t mmu_l1_getentry(uint32_t vaddr) * l2vaddr - The virtual address of the beginning of the L2 page table * vaddr - The virtual address to be mapped. * - ************************************************************************************/ + ************************************************************************************************************/ #ifndef CONFIG_ARCH_ROMPGTABLE static inline uint32_t mmu_l2_getentry(uint32_t l2vaddr, uint32_t vaddr) { - uint32_t *l2table = (uint32_t*)l2vaddr; + uint32_t *l2table = (uint32_t *)l2vaddr; uint32_t index; /* The table divides a 1Mb address space up into 256 entries, each @@ -1363,13 +1383,13 @@ static inline uint32_t mmu_l2_getentry(uint32_t l2vaddr, uint32_t vaddr) #endif /* __ASSEMBLY__ */ -/************************************************************************************ +/************************************************************************************************************ * Public Data - ************************************************************************************/ + ************************************************************************************************************/ -/************************************************************************************ +/************************************************************************************************************ * Public Function Prototypes - ************************************************************************************/ + ************************************************************************************************************/ #ifndef __ASSEMBLY__ #ifdef __cplusplus @@ -1380,7 +1400,7 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/************************************************************************************************************ * Name: mmu_l1_setentry * * Description: @@ -1394,13 +1414,13 @@ extern "C" * boundary * mmuflags - The MMU flags to use in the mapping. * - ************************************************************************************/ + ************************************************************************************************************/ #ifndef CONFIG_ARCH_ROMPGTABLE void mmu_l1_setentry(uint32_t paddr, uint32_t vaddr, uint32_t mmuflags); #endif -/**************************************************************************** +/************************************************************************************************************ * Name: mmu_l1_restore * * Description: @@ -1411,13 +1431,13 @@ void mmu_l1_setentry(uint32_t paddr, uint32_t vaddr, uint32_t mmuflags); * vaddr - A virtual address to be mapped * l1entry - The value to write into the page table entry * - ****************************************************************************/ + ************************************************************************************************************/ #if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_ADDRENV) void mmu_l1_restore(uintptr_t vaddr, uint32_t l1entry); #endif -/************************************************************************************ +/************************************************************************************************************ * Name: mmu_l1_clrentry * * Description: @@ -1427,13 +1447,13 @@ void mmu_l1_restore(uintptr_t vaddr, uint32_t l1entry); * Input Parameters: * vaddr - A virtual address within the L1 address region to be unmapped. * - ************************************************************************************/ + ************************************************************************************************************/ #if !defined (CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_ADDRENV) # define mmu_l1_clrentry(v) mmu_l1_restore(v,0) #endif -/**************************************************************************** +/************************************************************************************************************ * Name: mmu_l2_setentry * * Description: @@ -1448,14 +1468,14 @@ void mmu_l1_restore(uintptr_t vaddr, uint32_t l1entry); * address boundary * mmuflags - The MMU flags to use in the mapping. * - ****************************************************************************/ + ************************************************************************************************************/ #ifndef CONFIG_ARCH_ROMPGTABLE void mmu_l2_setentry(uint32_t l2vaddr, uint32_t paddr, uint32_t vaddr, uint32_t mmuflags); #endif -/**************************************************************************** +/************************************************************************************************************ * Name: mmu_l1_map_region * * Description: @@ -1465,13 +1485,13 @@ void mmu_l2_setentry(uint32_t l2vaddr, uint32_t paddr, uint32_t vaddr, * Input Parameters: * mapping - Describes the mapping to be performed. * - ****************************************************************************/ + ************************************************************************************************************/ #ifndef CONFIG_ARCH_ROMPGTABLE void mmu_l1_map_region(const struct section_mapping_s *mapping); #endif -/**************************************************************************** +/************************************************************************************************************ * Name: mmu_l1_map_regions * * Description: @@ -1482,13 +1502,14 @@ void mmu_l1_map_region(const struct section_mapping_s *mapping); * mappings - Describes the array of mappings to be performed. * count - The number of mappings to be performed. * - ****************************************************************************/ + ************************************************************************************************************/ + #ifndef CONFIG_ARCH_ROMPGTABLE void mmu_l1_map_regions(const struct section_mapping_s *mappings, size_t count); #endif -/**************************************************************************** +/************************************************************************************************************ * Name: mmu_invalidate_region * * Description: @@ -1498,7 +1519,7 @@ void mmu_l1_map_regions(const struct section_mapping_s *mappings, * vaddr - The beginning of the region to invalidate. * size - The size of the region in bytes to be invalidated. * - ****************************************************************************/ + ************************************************************************************************************/ #ifndef CONFIG_ARCH_ROMPGTABLE void mmu_invalidate_region(uint32_t vstart, size_t size); diff --git a/arch/arm/src/armv7-m/arm_svcall.c b/arch/arm/src/armv7-m/arm_svcall.c index 26108589a11..22fadb0a60d 100644 --- a/arch/arm/src/armv7-m/arm_svcall.c +++ b/arch/arm/src/armv7-m/arm_svcall.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -453,7 +454,7 @@ int arm_svcall(int irq, FAR void *context, FAR void *arg) rtcb->flags |= TCB_FLAG_SYSCALL; #else - svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]); + svcerr("ERROR: Bad SYS call: %" PRId32 "\n", regs[REG_R0]); #endif } break; diff --git a/arch/arm/src/c5471/c5471_watchdog.c b/arch/arm/src/c5471/c5471_watchdog.c index 32526fd9889..7db0144750d 100644 --- a/arch/arm/src/c5471/c5471_watchdog.c +++ b/arch/arm/src/c5471/c5471_watchdog.c @@ -74,7 +74,7 @@ #define C5471_DISABLE_VALUE2 (0xa0 << 22) #define CLOCK_KHZ 47500 -#define CLOCK_MHZx2 95 +#define CLOCK_MHZ_X2 95 /* Macros to manage access to the watchdog timer */ @@ -99,7 +99,8 @@ static int wdt_interrupt(int irq, void *context, FAR void *arg); static int wdt_open(struct file *filep); static int wdt_close(struct file *filep); static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen); -static ssize_t wdt_write(struct file *filep, const char *buffer, size_t buflen); +static ssize_t wdt_write(struct file *filep, const char *buffer, + size_t buflen); static int wdt_ioctl(FAR struct file *filep, int cmd, unsigned long arg); /**************************************************************************** @@ -184,7 +185,7 @@ static int wdt_setusec(uint32_t usec) do { - divisor = (CLOCK_MHZx2 * usec) / (prescaler * 2); + divisor = (CLOCK_MHZ_X2 * usec) / (prescaler * 2); wdinfo("divisor=0x%x prescaler=0x%x\n", divisor, prescaler); if (divisor >= 0x10000) @@ -261,9 +262,11 @@ static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen) wdinfo("buflen=%d\n", buflen); if (buflen >= 18) { - sprintf(buffer, "%08x %08x\n", c5471_wdt_cntl, c5471_wdt_count); + sprintf(buffer, "%08" PRIx32 " %08" PRIx32 "\n", + c5471_wdt_cntl, c5471_wdt_count); return 18; } + return 0; } @@ -271,7 +274,8 @@ static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen) * Name: wdt_write ****************************************************************************/ -static ssize_t wdt_write(struct file *filep, const char *buffer, size_t buflen) +static ssize_t wdt_write(struct file *filep, const char *buffer, + size_t buflen) { wdinfo("buflen=%d\n", buflen); if (buflen) diff --git a/arch/arm/src/common/arm_internal.h b/arch/arm/src/common/arm_internal.h index 396a4f368ec..d4f59f9db7a 100644 --- a/arch/arm/src/common/arm_internal.h +++ b/arch/arm/src/common/arm_internal.h @@ -212,7 +212,7 @@ EXTERN volatile uint32_t *g_current_regs[1]; * CONFIG_RAM_END */ -EXTERN const uint32_t g_idle_topstack; +EXTERN const uintptr_t g_idle_topstack; /* Address of the saved user stack pointer */ diff --git a/arch/arm/src/common/arm_interruptcontext.c b/arch/arm/src/common/arm_interruptcontext.c index 9c7f148d5bb..6ec9d122377 100644 --- a/arch/arm/src/common/arm_interruptcontext.c +++ b/arch/arm/src/common/arm_interruptcontext.c @@ -60,12 +60,6 @@ bool up_interrupt_context(void) { #ifdef CONFIG_SMP - /* REVISIT: Currently up_irq_save() will not disable the Software - * Generated Interrupts (SGIs) for the case of ARMv7-A architecture using - * the GIC. So this will not be sufficient in that case, at least not - * until we add support for the ICCMPR. - */ - irqstate_t flags = up_irq_save(); #endif diff --git a/arch/arm/src/common/arm_vfork.c b/arch/arm/src/common/arm_vfork.c index 78015695a73..35bd20ac980 100644 --- a/arch/arm/src/common/arm_vfork.c +++ b/arch/arm/src/common/arm_vfork.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -108,11 +109,12 @@ pid_t up_vfork(const struct vfork_s *context) int ret; sinfo("vfork context [%p]:\n", context); - sinfo(" r4:%08x r5:%08x r6:%08x r7:%08x\n", + sinfo(" r4:%08" PRIx32 " r5:%08" PRIx32 + " r6:%08" PRIx32 " r7:%08" PRIx32 "\n", context->r4, context->r5, context->r6, context->r7); - sinfo(" r8:%08x r9:%08x r10:%08x\n", + sinfo(" r8:%08" PRIx32 " r9:%08" PRIx32 " r10:%08" PRIx32 "\n", context->r8, context->r9, context->r10); - sinfo(" fp:%08x sp:%08x lr:%08x\n", + sinfo(" fp:%08" PRIx32 " sp:%08" PRIx32 " lr:%08" PRIx32 "\n", context->fp, context->sp, context->lr); /* Allocate and initialize a TCB for the child task. */ @@ -155,7 +157,8 @@ pid_t up_vfork(const struct vfork_s *context) DEBUGASSERT((uint32_t)parent->adj_stack_ptr > context->sp); stackutil = (uint32_t)parent->adj_stack_ptr - context->sp; - sinfo("Parent: stacksize:%d stackutil:%d\n", stacksize, stackutil); + sinfo("Parent: stacksize:%zu stackutil:%" PRId32 "\n", + stacksize, stackutil); /* Make some feeble effort to preserve the stack contents. This is * feeble because the stack surely contains invalid pointers and other @@ -180,9 +183,9 @@ pid_t up_vfork(const struct vfork_s *context) newfp = context->fp; } - sinfo("Parent: stack base:%08x SP:%08x FP:%08x\n", + sinfo("Parent: stack base:%p SP:%08" PRIx32 " FP:%08" PRIx32 "\n", parent->adj_stack_ptr, context->sp, context->fp); - sinfo("Child: stack base:%08x SP:%08x FP:%08x\n", + sinfo("Child: stack base:%p SP:%08" PRIx32 " FP:%08" PRIx32 "\n", child->cmn.adj_stack_ptr, newsp, newfp); /* Update the stack pointer, frame pointer, and volatile registers. When diff --git a/arch/arm/src/cxd56xx/cxd56_allocateheap.c b/arch/arm/src/cxd56xx/cxd56_allocateheap.c index fa24c29f21d..ae9279bac4f 100644 --- a/arch/arm/src/cxd56xx/cxd56_allocateheap.c +++ b/arch/arm/src/cxd56xx/cxd56_allocateheap.c @@ -69,7 +69,7 @@ * aligned). */ -const uint32_t g_idle_topstack = (uint32_t)&_ebss + +const uintptr_t g_idle_topstack = (uintptr_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE; /**************************************************************************** diff --git a/arch/arm/src/cxd56xx/cxd56_irq.c b/arch/arm/src/cxd56xx/cxd56_irq.c index d59872e6157..7dc9d339a3d 100644 --- a/arch/arm/src/cxd56xx/cxd56_irq.c +++ b/arch/arm/src/cxd56xx/cxd56_irq.c @@ -277,7 +277,7 @@ static inline void cxd56_prioritize_syscall(int priority) } #endif -static int excinfo(int irq, uint32_t *regaddr, uint32_t *bit) +static int excinfo(int irq, uintptr_t *regaddr, uint32_t *bit) { *regaddr = NVIC_SYSHCON; switch (irq) diff --git a/arch/arm/src/cxd56xx/cxd56_serial.c b/arch/arm/src/cxd56xx/cxd56_serial.c index c44be0070b9..c28a1c22da5 100644 --- a/arch/arm/src/cxd56xx/cxd56_serial.c +++ b/arch/arm/src/cxd56xx/cxd56_serial.c @@ -121,7 +121,7 @@ static int up_ioctl(FAR struct file *filep, int cmd, unsigned long arg); static bool up_rxflowcontrol(FAR struct uart_dev_s *dev, unsigned int nbuffered, bool upper); #endif -static int up_receive(FAR struct uart_dev_s *dev, FAR uint32_t *status); +static int up_receive(FAR struct uart_dev_s *dev, FAR unsigned int *status); static void up_rxint(FAR struct uart_dev_s *dev, bool enable); static bool up_rxavailable(FAR struct uart_dev_s *dev); static void up_send(FAR struct uart_dev_s *dev, int ch); @@ -916,7 +916,7 @@ static int up_ioctl(FAR struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(FAR struct uart_dev_s *dev, FAR uint32_t *status) +static int up_receive(FAR struct uart_dev_s *dev, FAR unsigned int *status) { FAR struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint32_t rbr; diff --git a/arch/arm/src/dm320/dm320_serial.c b/arch/arm/src/dm320/dm320_serial.c index 4cdcbc385ba..1e8de6b28bf 100644 --- a/arch/arm/src/dm320/dm320_serial.c +++ b/arch/arm/src/dm320/dm320_serial.c @@ -1,7 +1,8 @@ /**************************************************************************** * arch/arm/src/dm320/dm320_serial.c * - * Copyright (C) 2007-2009, 2012-2013, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2012-2013, 2017 Gregory Nutt. + * All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -89,7 +90,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -178,7 +179,7 @@ static uart_dev_t g_uart1port = { .size = CONFIG_UART1_TXBUFSIZE, .buffer = g_uart1txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_uart1priv, }; @@ -212,7 +213,8 @@ static inline uint16_t up_serialin(struct up_dev_s *priv, uint32_t offset) * Name: up_serialout ****************************************************************************/ -static inline void up_serialout(struct up_dev_s *priv, uint32_t offset, uint16_t value) +static inline void up_serialout(struct up_dev_s *priv, uint32_t offset, + uint16_t value) { putreg16(value, priv->uartbase + offset); } @@ -410,14 +412,15 @@ static void up_shutdown(struct uart_dev_s *dev) * Name: up_attach * * Description: - * Configure the UART to operation in interrupt driven mode. This method is - * called when the serial port is opened. Normally, this is just after the + * Configure the UART to operation in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after * the setup() method is called, however, the serial console may operate in * a non-interrupt driven mode during the boot phase. * - * RX and TX interrupts are not enabled when by the attach method (unless the - * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() methods are called. + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. * ****************************************************************************/ @@ -437,6 +440,7 @@ static int up_attach(struct uart_dev_s *dev) up_enable_irq(priv->irq); } + return ret; } @@ -445,8 +449,8 @@ static int up_attach(struct uart_dev_s *dev) * * Description: * Detach UART interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. The exception is - * the serial console which is never shutdown. + * closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. * ****************************************************************************/ @@ -588,7 +592,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint16_t dtrr; @@ -619,6 +623,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) { priv->msr &= ~UART_MSR_RFTIE; } + up_serialout(priv, UART_MSR, priv->msr); } @@ -671,6 +676,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) { priv->msr &= ~UART_MSR_TFTIE; } + up_serialout(priv, UART_MSR, priv->msr); } @@ -799,7 +805,6 @@ static inline void up_waittxready(void) for (tmp = 1000 ; tmp > 0 ; tmp--) { - if ((getreg16(DM320_REGISTER_BASE + UART_SR) & UART_SR_TFTI) != 0) { break; diff --git a/arch/arm/src/efm32/efm32_leserial.c b/arch/arm/src/efm32/efm32_leserial.c index 52be2151a1a..951dda623cf 100644 --- a/arch/arm/src/efm32/efm32_leserial.c +++ b/arch/arm/src/efm32/efm32_leserial.c @@ -167,7 +167,7 @@ static int efm32_attach(struct uart_dev_s *dev); static void efm32_detach(struct uart_dev_s *dev); static int efm32_interrupt(int irq, void *context, FAR void *arg); static int efm32_ioctl(struct file *filep, int cmd, unsigned long arg); -static int efm32_receive(struct uart_dev_s *dev, uint32_t *status); +static int efm32_receive(struct uart_dev_s *dev, unsigned int *status); static void efm32_rxint(struct uart_dev_s *dev, bool enable); static bool efm32_rxavailable(struct uart_dev_s *dev); static void efm32_send(struct uart_dev_s *dev, int ch); @@ -583,7 +583,7 @@ static int efm32_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int efm32_receive(struct uart_dev_s *dev, uint32_t *status) +static int efm32_receive(struct uart_dev_s *dev, unsigned int *status) { struct efm32_leuart_s *priv = (struct efm32_leuart_s *)dev->priv; uint32_t rxdatax; diff --git a/arch/arm/src/eoss3/eoss3_serial.c b/arch/arm/src/eoss3/eoss3_serial.c index b38bdcec1a7..ad14b0d8ac0 100644 --- a/arch/arm/src/eoss3/eoss3_serial.c +++ b/arch/arm/src/eoss3/eoss3_serial.c @@ -80,7 +80,7 @@ static int eoss3_attach(struct uart_dev_s *dev); static void eoss3_detach(struct uart_dev_s *dev); static int eoss3_interrupt(int irq, void *context, FAR void *arg); static int eoss3_ioctl(struct file *filep, int cmd, unsigned long arg); -static int eoss3_receive(struct uart_dev_s *dev, uint32_t *status); +static int eoss3_receive(struct uart_dev_s *dev, unsigned int *status); static void eoss3_rxint(struct uart_dev_s *dev, bool enable); static bool eoss3_rxavailable(struct uart_dev_s *dev); static void eoss3_send(struct uart_dev_s *dev, int ch); @@ -414,7 +414,7 @@ static int eoss3_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int eoss3_receive(struct uart_dev_s *dev, uint32_t *status) +static int eoss3_receive(struct uart_dev_s *dev, unsigned int *status) { *status = getreg32(EOSS3_UART_RSR_ECR); return (getreg32(EOSS3_UART_DR) & UART_DR_DATA_MASK); @@ -633,4 +633,4 @@ int up_putc(int ch) return ch; } -#endif /* USE_SERIALDRIVER */ \ No newline at end of file +#endif /* USE_SERIALDRIVER */ diff --git a/arch/arm/src/imx1/imx_serial.c b/arch/arm/src/imx1/imx_serial.c index 72b59c3f215..07ecbabf4c2 100644 --- a/arch/arm/src/imx1/imx_serial.c +++ b/arch/arm/src/imx1/imx_serial.c @@ -100,7 +100,8 @@ struct up_dev_s ****************************************************************************/ static inline uint32_t up_serialin(struct up_dev_s *priv, uint32_t offset); -static inline void up_serialout(struct up_dev_s *priv, uint32_t offset, uint32_t value); +static inline void up_serialout(struct up_dev_s *priv, uint32_t offset, + uint32_t value); static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *ucr1); static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t ucr1); static inline void up_waittxready(struct up_dev_s *priv); @@ -111,7 +112,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, FAR void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -223,7 +224,7 @@ static struct uart_dev_s g_uart2port = { .size = CONFIG_UART2_TXBUFSIZE, .buffer = g_uart2txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_uart2priv, }; @@ -385,7 +386,8 @@ static inline uint32_t up_serialin(struct up_dev_s *priv, uint32_t offset) * Name: up_serialout ****************************************************************************/ -static inline void up_serialout(struct up_dev_s *priv, uint32_t offset, uint32_t value) +static inline void up_serialout(struct up_dev_s *priv, uint32_t offset, + uint32_t value) { putreg32(value, priv->uartbase + offset); } @@ -554,7 +556,7 @@ static int up_setup(struct uart_dev_s *dev) */ tmp = ((uint64_t)refclk << (16 - 4)) / config->baud; - DEBUGASSERT(tmp < 0x0000000100000000LL); + DEBUGASSERT(tmp < 0x0000000100000000ll); ratio = (b16_t)tmp; /* Pick a scale factor that gives us about 14 bits of accuracy. @@ -679,9 +681,11 @@ static int up_setup(struct uart_dev_s *dev) { div = 6 - div; } + regval = div << UART_UFCR_RFDIV_SHIFT; - /* Set the TX trigger level to interrupt when the TxFIFO has 2 or fewer characters. + /* Set the TX trigger level to interrupt when the TxFIFO has 2 or fewer + * characters. * Set the RX trigger level to interrupt when the RxFIFO has 1 character. */ @@ -731,14 +735,15 @@ static void up_shutdown(struct uart_dev_s *dev) * Name: up_attach * * Description: - * Configure the UART to operation in interrupt driven mode. This method is - * called when the serial port is opened. Normally, this is just after the + * Configure the UART to operation in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after * the setup() method is called, however, the serial console may operate in * a non-interrupt driven mode during the boot phase. * - * RX and TX interrupts are not enabled when by the attach method (unless the - * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() methods are called. + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. * ****************************************************************************/ @@ -779,6 +784,7 @@ static int up_attach(struct uart_dev_s *dev) up_enable_irq(priv->irq); } #endif + return ret; } @@ -787,8 +793,8 @@ static int up_attach(struct uart_dev_s *dev) * * Description: * Detach UART interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. The exception is - * the serial console which is never shutdown. + * closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. * ****************************************************************************/ @@ -925,7 +931,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint32_t rxd0; @@ -959,6 +965,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) { priv->ucr1 &= ~UART_UCR1_RRDYEN; } + up_serialout(priv, UART_UCR1, priv->ucr1); } @@ -1019,6 +1026,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) { priv->ucr1 &= ~UART_UCR1_TXEMPTYEN; } + up_serialout(priv, UART_UCR1, priv->ucr1); } diff --git a/arch/arm/src/imx6/Make.defs b/arch/arm/src/imx6/Make.defs index e07033fcdfa..eb84c44ef17 100644 --- a/arch/arm/src/imx6/Make.defs +++ b/arch/arm/src/imx6/Make.defs @@ -117,6 +117,10 @@ endif CMN_CSRCS += arm_cache.c +ifeq ($(CONFIG_ARCH_L2CACHE),y) +CMN_CSRCS += arm_l2cc_pl310.c +endif + ifeq ($(CONFIG_ARCH_FPU),y) CMN_ASRCS += arm_savefpu.S arm_restorefpu.S CMN_CSRCS += arm_copyarmstate.c diff --git a/arch/arm/src/imx6/chip.h b/arch/arm/src/imx6/chip.h index c994f8c784b..705fbe6d5ef 100644 --- a/arch/arm/src/imx6/chip.h +++ b/arch/arm/src/imx6/chip.h @@ -61,6 +61,12 @@ #define CHIP_MPCORE_VBASE IMX_ARMMP_VSECTION +/* arch/arm/src/armv7-a/l2cc_pl310.h includes this file and expects it + * to provide the address of the L2CC-PL310 implementation. + */ + +#define L2CC_VBASE IMX_PL310_VBASE + /**************************************************************************** * Macro Definitions ****************************************************************************/ diff --git a/arch/arm/src/imx6/imx_serial.c b/arch/arm/src/imx6/imx_serial.c index 0fa910d60e0..a686b760d7c 100644 --- a/arch/arm/src/imx6/imx_serial.c +++ b/arch/arm/src/imx6/imx_serial.c @@ -231,7 +231,7 @@ static int imx_attach(struct uart_dev_s *dev); static void imx_detach(struct uart_dev_s *dev); static int imx_interrupt(int irq, void *context, FAR void *arg); static int imx_ioctl(struct file *filep, int cmd, unsigned long arg); -static int imx_receive(struct uart_dev_s *dev, uint32_t *status); +static int imx_receive(struct uart_dev_s *dev, unsigned int *status); static void imx_rxint(struct uart_dev_s *dev, bool enable); static bool imx_rxavailable(struct uart_dev_s *dev); static void imx_send(struct uart_dev_s *dev, int ch); @@ -349,7 +349,7 @@ static struct uart_dev_s g_uart2port = { .size = CONFIG_UART2_TXBUFSIZE, .buffer = g_uart2txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_uart2priv, }; @@ -578,14 +578,15 @@ static void imx_shutdown(struct uart_dev_s *dev) * Name: imx_attach * * Description: - * Configure the UART to operation in interrupt driven mode. This method is - * called when the serial port is opened. Normally, this is just after the + * Configure the UART to operation in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after * the setup() method is called, however, the serial console may operate in * a non-interrupt driven mode during the boot phase. * - * RX and TX interrupts are not enabled when by the attach method (unless the - * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() methods are called. + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. * ****************************************************************************/ @@ -746,7 +747,7 @@ static int imx_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int imx_receive(struct uart_dev_s *dev, uint32_t *status) +static int imx_receive(struct uart_dev_s *dev, unsigned int *status) { struct imx_uart_s *priv = (struct imx_uart_s *)dev->priv; uint32_t rxd0; diff --git a/arch/arm/src/imxrt/imxrt_enet.c b/arch/arm/src/imxrt/imxrt_enet.c index 900f3dabc17..278cd0ce7bd 100644 --- a/arch/arm/src/imxrt/imxrt_enet.c +++ b/arch/arm/src/imxrt/imxrt_enet.c @@ -186,6 +186,7 @@ * * The imxrt1050-evk board uses a KSZ8081 PHY * The Versiboard2 uses a LAN8720 PHY + * The Teensy-4.1 board uses a DP83825I PHY * * ...and further PHY descriptions here. */ @@ -208,6 +209,15 @@ # define BOARD_PHY_10BASET(s) (((s)&MII_LAN8720_SPSCR_10MBPS) != 0) # define BOARD_PHY_100BASET(s) (((s)&MII_LAN8720_SPSCR_100MBPS) != 0) # define BOARD_PHY_ISDUPLEX(s) (((s)&MII_LAN8720_SPSCR_DUPLEX) != 0) +#elif defined(CONFIG_ETH0_PHY_DP83825I) +# define BOARD_PHY_NAME "DP83825I" +# define BOARD_PHYID1 MII_PHYID1_DP83825I +# define BOARD_PHYID2 MII_PHYID2_DP83825I +# define BOARD_PHY_STATUS MII_DP83825I_PHYSTS +# define BOARD_PHY_ADDR (0) +# define BOARD_PHY_10BASET(s) (((s) & MII_DP83825I_PHYSTS_SPEED) != 0) +# define BOARD_PHY_100BASET(s) (((s) & MII_DP83825I_PHYSTS_SPEED) == 0) +# define BOARD_PHY_ISDUPLEX(s) (((s) & MII_DP83825I_PHYSTS_DUPLEX) != 0) #else # error "Unrecognized or missing PHY selection" #endif @@ -2164,6 +2174,25 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy) /* ...and reset PHY */ imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET); + +#elif defined (CONFIG_ETH0_PHY_DP83825I) + + /* Reset PHY */ + + imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET); + + /* Set RMII mode and Indicate 50MHz clock */ + + imxrt_writemii(priv, phyaddr, MII_DP83825I_RCSR, + MII_DP83825I_RCSC_ELAST_2 | MII_DP83825I_RCSC_RMIICS); + + imxrt_writemii(priv, phyaddr, MII_ADVERTISE, + MII_ADVERTISE_100BASETXFULL | + MII_ADVERTISE_100BASETXHALF | + MII_ADVERTISE_10BASETXFULL | + MII_ADVERTISE_10BASETXHALF | + MII_ADVERTISE_CSMA); + #endif /* Start auto negotiation */ diff --git a/arch/arm/src/imxrt/imxrt_serial.c b/arch/arm/src/imxrt/imxrt_serial.c index 0cd9e833abd..1d713abd2cd 100644 --- a/arch/arm/src/imxrt/imxrt_serial.c +++ b/arch/arm/src/imxrt/imxrt_serial.c @@ -366,7 +366,7 @@ static int imxrt_attach(struct uart_dev_s *dev); static void imxrt_detach(struct uart_dev_s *dev); static int imxrt_interrupt(int irq, void *context, FAR void *arg); static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg); -static int imxrt_receive(struct uart_dev_s *dev, uint32_t *status); +static int imxrt_receive(struct uart_dev_s *dev, unsigned int *status); static void imxrt_rxint(struct uart_dev_s *dev, bool enable); static bool imxrt_rxavailable(struct uart_dev_s *dev); static void imxrt_send(struct uart_dev_s *dev, int ch); @@ -1385,7 +1385,7 @@ static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int imxrt_receive(struct uart_dev_s *dev, uint32_t *status) +static int imxrt_receive(struct uart_dev_s *dev, unsigned int *status) { struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; uint32_t rxd; diff --git a/arch/arm/src/kinetis/kinetis_lpserial.c b/arch/arm/src/kinetis/kinetis_lpserial.c index 870d811abc8..6bf44b0189f 100644 --- a/arch/arm/src/kinetis/kinetis_lpserial.c +++ b/arch/arm/src/kinetis/kinetis_lpserial.c @@ -85,7 +85,8 @@ #if defined(HAVE_LPUART_DEVICE) && defined(USE_SERIALDRIVER) /* Which LPUART with be tty0/console and which tty1? The console will always - * be ttyS0. If there is no console then will use the lowest numbered LPUART. + * be ttyS0. If there is no console then will use the lowest numbered + * LPUART. */ /* First pick the console and ttys0. This could be any of LPUART0-4 */ @@ -130,7 +131,9 @@ # endif #endif -/* Pick ttys1. This could be any of LPUART0-4 excluding the console/ttyS0 LPUART. */ +/* Pick ttys1. This could be any of LPUART0-4 excluding the console/ttyS0 + * LPUART. + */ #if defined(CONFIG_KINETIS_LPUART0) && !defined(LPUART0_ASSIGNED) # define TTYS1_DEV g_lpuart0port /* LPUART0 is ttyS1 */ @@ -149,7 +152,9 @@ # define LPUART4_ASSIGNED 1 #endif -/* Pick ttys2. This could be any of LPUART1-4 excluding the console/ttyS0 LPUART. */ +/* Pick ttys2. This could be any of LPUART1-4 excluding the console/ttyS0 + * LPUART. + */ #if defined(CONFIG_KINETIS_LPUART1) && !defined(LPUART1_ASSIGNED) # define TTYS2_DEV g_lpuart1port /* LPUART1 is ttyS2 */ @@ -165,7 +170,9 @@ # define LPUART4_ASSIGNED 1 #endif -/* Pick ttys3. This could be any of LPUART2-4 excluding the console/ttyS0 LPUART. */ +/* Pick ttys3. This could be any of LPUART2-4 excluding the console/ttyS0 + * LPUART. + */ #if defined(CONFIG_KINETIS_LPUART2) && !defined(LPUART2_ASSIGNED) # define TTYS3_DEV g_lpuart2port /* LPUART2 is ttyS3 */ @@ -178,7 +185,9 @@ # define LPUART4_ASSIGNED 1 #endif -/* Pick ttys3. This could be any of LPUART3-4 excluding the console/ttyS0 LPUART. */ +/* Pick ttys3. This could be any of LPUART3-4 excluding the console/ttyS0 + * LPUART. + */ #if defined(CONFIG_KINETIS_LPUART3) && !defined(LPUART3_ASSIGNED) # define TTYS4_DEV g_lpuart3port /* LPUART3 is ttyS4 */ @@ -248,7 +257,7 @@ static int kinetis_attach(struct uart_dev_s *dev); static void kinetis_detach(struct uart_dev_s *dev); static int kinetis_interrupt(int irq, void *context, void *arg); static int kinetis_ioctl(struct file *filep, int cmd, unsigned long arg); -static int kinetis_receive(struct uart_dev_s *dev, uint32_t *status); +static int kinetis_receive(struct uart_dev_s *dev, unsigned int *status); static void kinetis_rxint(struct uart_dev_s *dev, bool enable); static bool kinetis_rxavailable(struct uart_dev_s *dev); #ifdef CONFIG_SERIAL_IFLOWCONTROL @@ -338,7 +347,7 @@ static uart_dev_t g_lpuart0port = { .size = CONFIG_LPUART0_TXBUFSIZE, .buffer = g_lpuart0txbuffer, - }, + }, .ops = &g_lpuart_ops, .priv = &g_lpuart0priv, }; @@ -377,7 +386,7 @@ static uart_dev_t g_lpuart1port = { .size = CONFIG_LPUART1_TXBUFSIZE, .buffer = g_lpuart1txbuffer, - }, + }, .ops = &g_lpuart_ops, .priv = &g_lpuart1priv, }; @@ -416,7 +425,7 @@ static uart_dev_t g_lpuart2port = { .size = CONFIG_LPUART2_TXBUFSIZE, .buffer = g_lpuart2txbuffer, - }, + }, .ops = &g_lpuart_ops, .priv = &g_lpuart2priv, }; @@ -455,7 +464,7 @@ static uart_dev_t g_lpuart3port = { .size = CONFIG_LPUART3_TXBUFSIZE, .buffer = g_lpuart3txbuffer, - }, + }, .ops = &g_lpuart_ops, .priv = &g_lpuart3priv, }; @@ -494,7 +503,7 @@ static uart_dev_t g_lpuart4port = { .size = CONFIG_LPUART4_TXBUFSIZE, .buffer = g_lpuart4txbuffer, - }, + }, .ops = &g_lpuart_ops, .priv = &g_lpuart4priv, }; @@ -533,7 +542,9 @@ static void kinetis_setuartint(struct kinetis_dev_s *priv) irqstate_t flags; uint32_t regval; - /* Re-enable/re-disable interrupts corresponding to the state of bits in ie */ + /* Re-enable/re-disable interrupts corresponding to the state of bits in + * ie + */ flags = enter_critical_section(); regval = kinetis_serialin(priv, KINETIS_LPUART_CTRL_OFFSET); @@ -551,7 +562,9 @@ static void kinetis_restoreuartint(struct kinetis_dev_s *priv, uint32_t ie) { irqstate_t flags; - /* Re-enable/re-disable interrupts corresponding to the state of bits in ie */ + /* Re-enable/re-disable interrupts corresponding to the state of bits in + * ie + */ flags = enter_critical_section(); priv->ie = ie & LPUART_CTRL_ALL_INTS; @@ -645,7 +658,8 @@ static void kinetis_shutdown(struct uart_dev_s *dev) * Configure the LPUART to operation in interrupt driven mode. This * method is called when the serial port is opened. Normally, this is * just after the setup() method is called, however, the serial - * console may operate in a non-interrupt driven mode during the boot phase. + * console may operate in a non-interrupt driven mode during the boot + * phase. * * RX and TX interrupts are not enabled when by the attach method (unless * the hardware supports multiple levels of interrupt enabling). The RX @@ -718,14 +732,15 @@ static int kinetis_interrupt(int irq, void *context, void *arg) DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct kinetis_dev_s *)dev->priv; - /* Read status register and qualify it with STAT bit corresponding CTRL IE bits */ + /* Read status register and qualify it with STAT bit corresponding CTRL IE + * bits + */ stat = kinetis_serialin(priv, KINETIS_LPUART_STAT_OFFSET); ctrl = kinetis_serialin(priv, KINETIS_LPUART_CTRL_OFFSET); stat &= LPUART_CTRL2STAT(ctrl); do { - /* Handle errors. This interrupt may be caused by: * * OR: Receiver Overrun Flag. To clear OR, when STAT read with OR set, @@ -740,7 +755,6 @@ static int kinetis_interrupt(int irq, void *context, void *arg) if (stat & LPUART_STAT_ERRORS) { - /* Only Overrun error does not need a read operation */ if ((stat & LPUART_STAT_OR) != LPUART_STAT_OR) @@ -781,7 +795,9 @@ static int kinetis_interrupt(int irq, void *context, void *arg) uart_xmitchars(dev); } - /* Read status register and requalify it with STAT bit corresponding CTRL IE bits */ + /* Read status register and requalify it with STAT bit corresponding + * CTRL IE bits + */ stat = kinetis_serialin(priv, KINETIS_LPUART_STAT_OFFSET); ctrl = kinetis_serialin(priv, KINETIS_LPUART_CTRL_OFFSET); @@ -850,7 +866,7 @@ static int kinetis_ioctl(struct file *filep, int cmd, unsigned long arg) { if ((arg & SER_SINGLEWIRE_PULLUP) != 0) { - ret = -EINVAL; // Not supported + ret = -EINVAL; /* Not supported */ break; } @@ -888,9 +904,9 @@ static int kinetis_ioctl(struct file *filep, int cmd, unsigned long arg) cfsetispeed(termiosp, priv->baud); - /* Note: CSIZE only supports 5-8 bits. The driver only support 8/9 bit - * modes and therefore is no way to report 9-bit mode, we always claim - * 8 bit mode. + /* Note: CSIZE only supports 5-8 bits. The driver only support 8/9 + * bit modes and therefore is no way to report 9-bit mode, we always + * claim 8 bit mode. */ termiosp->c_cflag = @@ -1060,7 +1076,7 @@ static int kinetis_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int kinetis_receive(struct uart_dev_s *dev, uint32_t *status) +static int kinetis_receive(struct uart_dev_s *dev, unsigned int *status) { struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev->priv; uint32_t regval; @@ -1363,7 +1379,7 @@ unsigned int kinetis_lpuart_serialinit(unsigned int first) char devname[] = "/dev/ttySx"; #endif -/* Register the console */ + /* Register the console */ #ifdef HAVE_LPUART_CONSOLE uart_register("/dev/console", &CONSOLE_DEV); @@ -1387,22 +1403,22 @@ unsigned int kinetis_lpuart_serialinit(unsigned int first) #else - devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + devname[(sizeof(devname) / sizeof(devname[0])) - 2] = '0' + first++; uart_register(devname, &TTYS0_DEV); #ifdef TTYS1_DEV - devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + devname[(sizeof(devname) / sizeof(devname[0])) - 2] = '0' + first++; uart_register(devname, &TTYS1_DEV); #endif #ifdef TTYS2_DEV - devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + devname[(sizeof(devname) / sizeof(devname[0])) - 2] = '0' + first++; uart_register(devname, &TTYS2_DEV); #endif #ifdef TTYS3_DEV - devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + devname[(sizeof(devname) / sizeof(devname[0])) - 2] = '0' + first++; uart_register(devname, &TTYS3_DEV); #endif #ifdef TTYS4_DEV - devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + devname[(sizeof(devname) / sizeof(devname[0])) - 2] = '0' + first++; uart_register(devname, &TTYS4_DEV); #endif #endif diff --git a/arch/arm/src/kinetis/kinetis_sdhc.c b/arch/arm/src/kinetis/kinetis_sdhc.c index 9fafc7b3b82..077c42676ed 100644 --- a/arch/arm/src/kinetis/kinetis_sdhc.c +++ b/arch/arm/src/kinetis/kinetis_sdhc.c @@ -310,7 +310,7 @@ static void kinetis_blocksetup(FAR struct sdio_dev_s *dev, static int kinetis_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, size_t nbytes); static int kinetis_sendsetup(FAR struct sdio_dev_s *dev, - FAR const uint8_t *buffer, uint32_t nbytes); + FAR const uint8_t *buffer, size_t nbytes); #endif static int kinetis_cancel(FAR struct sdio_dev_s *dev); diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c index 7ef82e78e47..d81b40e2a75 100644 --- a/arch/arm/src/kinetis/kinetis_serial.c +++ b/arch/arm/src/kinetis/kinetis_serial.c @@ -343,7 +343,7 @@ static int up_interrupts(int irq, void *context, FAR void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static void up_rxint(struct uart_dev_s *dev, bool enable); #if !defined(SERIAL_HAVE_ALL_DMA) -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static bool up_rxavailable(struct uart_dev_s *dev); #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL @@ -1567,7 +1567,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) ****************************************************************************/ #if !defined(SERIAL_HAVE_ALL_DMA) -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint8_t s1; diff --git a/arch/arm/src/kl/kl_serial.c b/arch/arm/src/kl/kl_serial.c index b0f01bb0cdd..a4b41a2ca92 100644 --- a/arch/arm/src/kl/kl_serial.c +++ b/arch/arm/src/kl/kl_serial.c @@ -173,7 +173,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupts(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -635,7 +635,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint8_t s1; diff --git a/arch/arm/src/kl/kl_start.c b/arch/arm/src/kl/kl_start.c index 01db1ad37e9..805a6770994 100644 --- a/arch/arm/src/kl/kl_start.c +++ b/arch/arm/src/kl/kl_start.c @@ -80,7 +80,7 @@ * Public Data ****************************************************************************/ -const uint32_t g_idle_topstack = IDLE_STACK; +const uintptr_t g_idle_topstack = IDLE_STACK; /**************************************************************************** * Private Functions @@ -135,6 +135,7 @@ void __start(void) { *dest++ = 0; } + showprogress('B'); /* Move the initialized data section from his temporary holding spot in @@ -147,6 +148,7 @@ void __start(void) { *dest++ = *src++; } + showprogress('C'); /* Perform early serial initialization */ diff --git a/arch/arm/src/lc823450/lc823450_mtd.c b/arch/arm/src/lc823450/lc823450_mtd.c index e78bbb2bfd4..7ef0d0e7156 100644 --- a/arch/arm/src/lc823450/lc823450_mtd.c +++ b/arch/arm/src/lc823450/lc823450_mtd.c @@ -26,6 +26,7 @@ #include +#include #include #include #include @@ -788,7 +789,7 @@ int lc823450_mtd_uninitialize(uint32_t devno) return -ENODEV; } - snprintf(devname, 16, "/dev/mtdblock%d", devno); + snprintf(devname, 16, "/dev/mtdblock%" PRId32, devno); #ifdef CONFIG_MTD_REGISTRATION mtd_unregister(g_mtdmaster[ch]); diff --git a/arch/arm/src/lc823450/lc823450_procfs_dvfs.c b/arch/arm/src/lc823450/lc823450_procfs_dvfs.c index b379b1bca68..bd3e5973c9b 100644 --- a/arch/arm/src/lc823450/lc823450_procfs_dvfs.c +++ b/arch/arm/src/lc823450/lc823450_procfs_dvfs.c @@ -27,6 +27,7 @@ #include #include +#include #include #include #include @@ -234,7 +235,7 @@ static ssize_t dvfs_read(FAR struct file *filep, FAR char *buffer, linesize = snprintf(priv->line, DVFS_LINELEN, - "fstat %d %d %d \n", + "fstat %" PRId32 " %" PRId32 " %" PRId32 " \n", g_dvfs_freq_stat[0], g_dvfs_freq_stat[1], g_dvfs_freq_stat[2]); diff --git a/arch/arm/src/lc823450/lc823450_serial.c b/arch/arm/src/lc823450/lc823450_serial.c index 7003f78f065..005d4c096e1 100644 --- a/arch/arm/src/lc823450/lc823450_serial.c +++ b/arch/arm/src/lc823450/lc823450_serial.c @@ -186,7 +186,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, FAR void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -845,7 +845,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint32_t rxd; diff --git a/arch/arm/src/lc823450/lc823450_usbdev.c b/arch/arm/src/lc823450/lc823450_usbdev.c index 7a98419025e..2401c6ba17f 100644 --- a/arch/arm/src/lc823450/lc823450_usbdev.c +++ b/arch/arm/src/lc823450/lc823450_usbdev.c @@ -618,7 +618,7 @@ static void *lc823450_epallocbuffer(struct usbdev_ep_s *ep, uint16_t bytes) # ifdef CONFIG_USBDEV_DMAMEMORY return usbdev_dma_alloc(bytes); # else - return kmm_alloc(bytes); + return kmm_malloc(bytes); # endif } #endif diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c index 0bf2840180e..a866663d101 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c @@ -382,7 +382,7 @@ static int lpc17_40_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, static int lpc17_40_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, size_t nbytes); static int lpc17_40_sendsetup(FAR struct sdio_dev_s *dev, - FAR const uint8_t *buffer, uint32_t nbytes); + FAR const uint8_t *buffer, size_t nbytes); static int lpc17_40_cancel(FAR struct sdio_dev_s *dev); static int lpc17_40_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd); diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c index 2047d216850..42fe0474e2f 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c @@ -105,7 +105,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -1459,7 +1459,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint32_t rbr; diff --git a/arch/arm/src/lpc214x/lpc214x_serial.c b/arch/arm/src/lpc214x/lpc214x_serial.c index 2384596d955..36ff7e5e85a 100644 --- a/arch/arm/src/lpc214x/lpc214x_serial.c +++ b/arch/arm/src/lpc214x/lpc214x_serial.c @@ -1,7 +1,8 @@ /**************************************************************************** * arch/arm/src/lpc214x/lpc214x_serial.c * - * Copyright (C) 2007-2009, 2012-2013, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2012-2013, 2017 Gregory Nutt. + * All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -89,7 +90,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -178,7 +179,7 @@ static uart_dev_t g_uart1port = { .size = CONFIG_UART1_TXBUFSIZE, .buffer = g_uart1txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_uart1priv, }; @@ -214,7 +215,8 @@ static inline uint8_t up_serialin(struct up_dev_s *priv, int offset) * Name: up_serialout ****************************************************************************/ -static inline void up_serialout(struct up_dev_s *priv, int offset, uint8_t value) +static inline void up_serialout(struct up_dev_s *priv, int offset, + uint8_t value) { putreg8(value, priv->uartbase + offset); } @@ -253,12 +255,16 @@ static inline void up_waittxready(struct up_dev_s *priv) int tmp; /* Limit how long we will wait for the TX available condition */ + for (tmp = 1000 ; tmp > 0 ; tmp--) { /* Check if the tranmitter holding register (THR) is empty */ - if ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & LPC214X_LSR_THRE) != 0) + + if ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & + LPC214X_LSR_THRE) != 0) { /* The THR is empty, return */ + break; } } @@ -394,14 +400,15 @@ static void up_shutdown(struct uart_dev_s *dev) * Name: up_attach * * Description: - * Configure the UART to operation in interrupt driven mode. This method is - * called when the serial port is opened. Normally, this is just after the + * Configure the UART to operation in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after * the setup() method is called, however, the serial console may operate in * a non-interrupt driven mode during the boot phase. * - * RX and TX interrupts are not enabled when by the attach method (unless the - * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() methods are called. + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. * ****************************************************************************/ @@ -430,8 +437,8 @@ static int up_attach(struct uart_dev_s *dev) * * Description: * Detach UART interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. The exception is - * the serial console which is never shutdown. + * closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. * ****************************************************************************/ @@ -542,6 +549,7 @@ static int up_interrupt(int irq, void *context, void *arg) } } } + return OK; } @@ -613,7 +621,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint8_t rbr; @@ -644,6 +652,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) { priv->ier &= ~LPC214X_IER_ERBFI; } + up_serialout(priv, LPC214X_UART_IER_OFFSET, priv->ier); } @@ -658,7 +667,8 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) static bool up_rxavailable(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - return ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & LPC214X_LSR_RDR) != 0); + return ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & + LPC214X_LSR_RDR) != 0); } /**************************************************************************** @@ -696,6 +706,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) { priv->ier &= ~LPC214X_IER_ETBEI; } + up_serialout(priv, LPC214X_UART_IER_OFFSET, priv->ier); } @@ -710,7 +721,8 @@ static void up_txint(struct uart_dev_s *dev, bool enable) static bool up_txready(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - return ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & LPC214X_LSR_THRE) != 0); + return ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & + LPC214X_LSR_THRE) != 0); } /**************************************************************************** @@ -724,7 +736,8 @@ static bool up_txready(struct uart_dev_s *dev) static bool up_txempty(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - return ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & LPC214X_LSR_THRE) != 0); + return ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & + LPC214X_LSR_THRE) != 0); } /**************************************************************************** diff --git a/arch/arm/src/lpc2378/lpc23xx_serial.c b/arch/arm/src/lpc2378/lpc23xx_serial.c index 49bbe49c169..89a9ce5ea6e 100644 --- a/arch/arm/src/lpc2378/lpc23xx_serial.c +++ b/arch/arm/src/lpc2378/lpc23xx_serial.c @@ -97,7 +97,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t * status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -177,7 +177,6 @@ static struct up_dev_s g_uart2priv = .parity = CONFIG_UART2_PARITY, .bits = CONFIG_UART2_BITS, .stopbits2 = CONFIG_UART2_2STOP, - }; static uart_dev_t g_uart2port = @@ -229,7 +228,8 @@ static inline uint8_t up_serialin(struct up_dev_s *priv, int offset) * Name: up_serialout ****************************************************************************/ -static inline void up_serialout(struct up_dev_s *priv, int offset, uint8_t value) +static inline void up_serialout(struct up_dev_s *priv, int offset, + uint8_t value) { putreg8(value, priv->uartbase + offset); } @@ -305,9 +305,9 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable) /**************************************************************************** * Name: up_configbaud ****************************************************************************/ + static inline void up_configbaud(struct up_dev_s *priv) { - /* In a buckled-up, embedded system, there is no reason to constantly * calculate the following. The calculation can be skipped if the MULVAL, * DIVADDVAL, and DIVISOR values are provided in the configuration file. @@ -347,12 +347,14 @@ static inline void up_configbaud(struct up_dev_s *priv) qtrclk = U0_PCLK >> 4; /* TODO: Different Uart port with different clocking */ - /* Try every valid multiplier, tmulval (or until a perfect match is found). */ + /* Try every valid multiplier, tmulval + * (or until a perfect match is found). + */ for (tmulval = 1; tmulval <= 15 && errval > 0; tmulval++) { - /* Try every valid pre-scale div, tdivaddval (or until a perfect match is - * found). + /* Try every valid pre-scale div, tdivaddval + * (or until a perfect match is found). */ for (tdivaddval = 0; tdivaddval <= 15 && errval > 0; tdivaddval++) @@ -408,6 +410,7 @@ static inline void up_configbaud(struct up_dev_s *priv) #else /* Configure the MS and LS DLAB registers */ + up_serialout(priv, UART_DLM_OFFSET, DLMVAL >> 8); up_serialout(priv, UART_DLL_OFFSET, DLLVAL & 0xff); @@ -436,7 +439,8 @@ static int up_setup(struct uart_dev_s *dev) /* Clear fifos */ - up_serialout(priv, UART_FCR_OFFSET, (FCR_RX_FIFO_RESET | FCR_TX_FIFO_RESET)); + up_serialout(priv, UART_FCR_OFFSET, + (FCR_RX_FIFO_RESET | FCR_TX_FIFO_RESET)); /* Set trigger */ @@ -484,10 +488,11 @@ static int up_setup(struct uart_dev_s *dev) (FCR_FIFO_TRIG8 | FCR_TX_FIFO_RESET | FCR_RX_FIFO_RESET | FCR_FIFO_ENABLE)); - /* The NuttX serial driver waits for the first THRE interrupt before sending - * serial data... However, it appears that the LPC2378 hardware too does not - * generate that interrupt until a transition from not-empty to empty. So, - * the current kludge here is to send one NULL at startup to kick things off. + /* The NuttX serial driver waits for the first THRE interrupt before + * sending serial data... However, it appears that the LPC2378 hardware + * too does not generate that interrupt until a transition from not-empty + * to empty. So, the current kludge here is to send one NULL at startup + * to kick things off. */ up_serialout(priv, UART_THR_OFFSET, '\0'); @@ -514,14 +519,15 @@ static void up_shutdown(struct uart_dev_s *dev) * Name: up_attach * * Description: - * Configure the UART to operation in interrupt driven mode. This method is - * called when the serial port is opened. Normally, this is just after the + * Configure the UART to operation in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after * the setup() method is called, however, the serial console may operate in * a non-interrupt driven mode during the boot phase. * - * RX and TX interrupts are not enabled when by the attach method (unless the - * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() methods are called. + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. * ****************************************************************************/ @@ -536,7 +542,8 @@ static int up_attach(struct uart_dev_s *dev) if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled in the - * UART */ + * UART + */ up_enable_irq(priv->irq); } @@ -549,8 +556,8 @@ static int up_attach(struct uart_dev_s *dev) * * Description: * Detach UART interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. The exception is - * the serial console which is never shutdown. + * closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. * ****************************************************************************/ @@ -585,11 +592,14 @@ static int up_interrupt(int irq, void *context, void *arg) priv = (struct up_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, until we have - * been looping for a long time. */ + * been looping for a long time. + */ for (passes = 0; passes < 256; passes++) { - /* Get the current UART status and check for loop termination conditions */ + /* Get the current UART status and check for loop termination + * conditions + */ status = up_serialin(priv, UART_IIR_OFFSET); @@ -597,7 +607,9 @@ static int up_interrupt(int irq, void *context, void *arg) if ((status & IIR_NO_INT) != 0) { - /* Break out of the loop when there is no longer a pending interrupt */ + /* Break out of the loop when there is no longer a pending + * interrupt + */ break; } @@ -654,6 +666,7 @@ static int up_interrupt(int irq, void *context, void *arg) } } } + return OK; } @@ -727,7 +740,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t * status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint8_t rbr; @@ -758,6 +771,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) { priv->ier &= ~IER_ERBFI; } + up_serialout(priv, UART_IER_OFFSET, priv->ier); } @@ -810,6 +824,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) { priv->ier &= ~IER_ETBEI; } + up_serialout(priv, UART_IER_OFFSET, priv->ier); } diff --git a/arch/arm/src/lpc31xx/lpc31_serial.c b/arch/arm/src/lpc31xx/lpc31_serial.c index fa5d1a8bfa4..099fd1dfde9 100644 --- a/arch/arm/src/lpc31xx/lpc31_serial.c +++ b/arch/arm/src/lpc31xx/lpc31_serial.c @@ -89,7 +89,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, FAR void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -280,7 +280,9 @@ static inline void up_configbaud(void) if (tmperr < errval) { - /* Yes, save these settings as the new, candidate optimal settings */ + /* Yes, save these settings as the new, candidate optimal + * settings + */ mulval = tmulval ; divaddval = tdivaddval; @@ -427,11 +429,11 @@ static void up_shutdown(struct uart_dev_s *dev) * Description: * Configure the UART to operation in interrupt driven mode. This method * is called when the serial port is opened. Normally, this is just after - * he the setup() method is called, however, the serial console may operate in + * he the setup() method is called, however, the serial console may operate * in a non-interrupt driven mode during the boot phase. * * RX and TX interrupts are not enabled when by the attach method (unless - * the hardware supports multiple levels of interrupt enabling). The RX and TX + * the hardware supports multiple levels of interrupt enabling). The RX * and TX interrupts are not enabled until the txint() and rxint() methods * are called. * @@ -519,8 +521,8 @@ static int up_interrupt(int irq, void *context, FAR void *arg) { /* Handle incoming, receive bytes (with or without timeout) */ - case UART_IIR_INTID_RDA: /* Received Data Available */ - case UART_IIR_INTID_TIMEOUT: /* Character time-out */ + case UART_IIR_INTID_RDA: /* Received Data Available */ + case UART_IIR_INTID_TIMEOUT: /* Character time-out */ { uart_recvchars(dev); break; @@ -565,6 +567,7 @@ static int up_interrupt(int irq, void *context, FAR void *arg) } } } + return OK; } @@ -637,7 +640,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { uint32_t rbr; @@ -667,6 +670,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) { priv->ier &= ~UART_IER_RDAINTEN; } + putreg32(priv->ier, LPC31_UART_IER); } @@ -717,6 +721,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) { priv->ier &= ~UART_IER_THREINTEN; } + putreg32(priv->ier, LPC31_UART_IER); } diff --git a/arch/arm/src/lpc43xx/lpc43_allocateheap.c b/arch/arm/src/lpc43xx/lpc43_allocateheap.c index b9d295c8f76..e828726058f 100644 --- a/arch/arm/src/lpc43xx/lpc43_allocateheap.c +++ b/arch/arm/src/lpc43xx/lpc43_allocateheap.c @@ -188,13 +188,16 @@ #ifndef CONFIG_LPC43_BOOT_SRAM /* Configuration A */ + /* CONFIG_RAM_START should be set to the base of local SRAM, Bank 0. */ # if CONFIG_RAM_START != LPC43_LOCSRAM_BANK0_BASE # error "CONFIG_RAM_START must be set to the base address of RAM bank 0" # endif -/* The configured RAM size should be equal to the size of local SRAM Bank 0. */ +/* The configured RAM size should be equal to the size of local SRAM Bank + * 0. + */ # if CONFIG_RAM_SIZE != LPC43_LOCSRAM_BANK0_SIZE # error "CONFIG_RAM_SIZE must be set to size of local SRAM Bank 0" @@ -213,13 +216,16 @@ #else /* CONFIG_LPC43_BOOT_SRAM */ /* Configuration B */ + /* CONFIG_RAM_START should be set to the base of local SRAM, Bank 1. */ # if CONFIG_RAM_START != LPC43_LOCSRAM_BANK1_BASE # error "CONFIG_RAM_START must be set to the base address of RAM bank 1" # endif -/* The configured RAM size should be equal to the size of local SRAM Bank 1. */ +/* The configured RAM size should be equal to the size of local SRAM Bank + * 1. + */ # if CONFIG_RAM_SIZE != LPC43_LOCSRAM_BANK1_SIZE # error "CONFIG_RAM_SIZE must be set to size of local SRAM Bank 1" @@ -334,7 +340,8 @@ * aligned). */ -const uint32_t g_idle_topstack = (uint32_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE; +const uintptr_t g_idle_topstack = (uintptr_t)&_ebss + + CONFIG_IDLETHREAD_STACKSIZE; #ifdef MM_HAVE_REGION static uint8_t g_mem_region_next = 0; @@ -408,7 +415,8 @@ static void mem_addregion(FAR void *region_start, size_t region_size) * * Kernel .data region. Size determined at link time. * Kernel .bss region Size determined at link time. - * Kernel IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Kernel IDLE thread stack. Size determined by + * CONFIG_IDLETHREAD_STACKSIZE. * Padding for alignment * User .data region. Size determined at link time. * User .bss region Size determined at link time. @@ -425,7 +433,8 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). */ - uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; size_t usize = CONFIG_RAM_END - ubase; int log2; @@ -492,7 +501,8 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). */ - uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; size_t usize = CONFIG_RAM_END - ubase; int log2; @@ -538,36 +548,42 @@ void arm_addregion(void) #ifdef MM_USE_LOCSRAM_BANK1 /* Add the SRAM to the user heap */ - mem_addregion((FAR void *)LPC43_LOCSRAM_BANK1_BASE, LPC43_LOCSRAM_BANK1_SIZE); + mem_addregion((FAR void *)LPC43_LOCSRAM_BANK1_BASE, + LPC43_LOCSRAM_BANK1_SIZE); #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Allow user-mode access to the SRAM heap */ - lpc43_mpu_uheap((uintptr_t)LPC43_LOCSRAM_BANK1_BASE, LPC43_LOCSRAM_BANK1_SIZE); + lpc43_mpu_uheap((uintptr_t)LPC43_LOCSRAM_BANK1_BASE, + LPC43_LOCSRAM_BANK1_SIZE); #endif #endif #ifdef MM_USE_AHBSRAM_BANK0 /* Add the SRAM to the user heap */ - mem_addregion((FAR void *)LPC43_AHBSRAM_BANK0_BASE, LPC43_AHBSRAM_BANK0_SIZE); + mem_addregion((FAR void *)LPC43_AHBSRAM_BANK0_BASE, + LPC43_AHBSRAM_BANK0_SIZE); #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Allow user-mode access to the SRAM heap */ - lpc43_mpu_uheap((uintptr_t)LPC43_AHBSRAM_BANK0_BASE, LPC43_AHBSRAM_BANK0_SIZE); + lpc43_mpu_uheap((uintptr_t)LPC43_AHBSRAM_BANK0_BASE, + LPC43_AHBSRAM_BANK0_SIZE); #endif #endif #ifdef MM_USE_AHBSRAM_BANK1 /* Add the SRAM to the user heap */ - mem_addregion((FAR void *)LPC43_AHBSRAM_BANK1_BASE, LPC43_AHBSRAM_BANK1_SIZE); + mem_addregion((FAR void *)LPC43_AHBSRAM_BANK1_BASE, + LPC43_AHBSRAM_BANK1_SIZE); #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Allow user-mode access to the SRAM heap */ - lpc43_mpu_uheap((uintptr_t)LPC43_AHBSRAM_BANK1_BASE, LPC43_AHBSRAM_BANK1_SIZE); + lpc43_mpu_uheap((uintptr_t)LPC43_AHBSRAM_BANK1_BASE, + LPC43_AHBSRAM_BANK1_SIZE); #endif #endif diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c index 419ec88cfdf..da1d4f2d0b3 100644 --- a/arch/arm/src/lpc43xx/lpc43_serial.c +++ b/arch/arm/src/lpc43xx/lpc43_serial.c @@ -114,7 +114,7 @@ static inline int up_set_rs485_mode(struct up_dev_s *priv, static inline int up_get_rs485_mode(struct up_dev_s *priv, struct serial_rs485 *mode); #endif -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -1139,7 +1139,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint32_t rbr; diff --git a/arch/arm/src/lpc54xx/lpc54_allocateheap.c b/arch/arm/src/lpc54xx/lpc54_allocateheap.c index 61700718365..90b25dd93e5 100644 --- a/arch/arm/src/lpc54xx/lpc54_allocateheap.c +++ b/arch/arm/src/lpc54xx/lpc54_allocateheap.c @@ -60,7 +60,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ + /* Terminology. In the flat build (CONFIG_BUILD_FLAT=y), there is only a * single heap access with the standard allocations (malloc/free). This * heap is referred to as the user heap. In the protected build @@ -141,7 +143,8 @@ * aligned). */ -const uint32_t g_idle_topstack = (uint32_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE; +const uintptr_t g_idle_topstack = (uintptr_t)&_ebss + + CONFIG_IDLETHREAD_STACKSIZE; /**************************************************************************** * Public Functions @@ -176,7 +179,8 @@ const uint32_t g_idle_topstack = (uint32_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE; * * Kernel .data region. Size determined at link time. * Kernel .bss region Size determined at link time. - * Kernel IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Kernel IDLE thread stack. Size determined by + * CONFIG_IDLETHREAD_STACKSIZE. * Padding for alignment * User .data region. Size determined at link time. * User .bss region Size determined at link time. @@ -197,7 +201,8 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). */ - uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; size_t usize = CONFIG_RAM_END - ubase; DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); @@ -236,7 +241,8 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). */ - uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); /* Return the kernel heap settings (i.e., the part of the heap region @@ -269,7 +275,8 @@ void arm_addregion(void) { /* Add the SRAM to the user heap */ - heapstart = (FAR void *)(LPC54_SRAMCS0_BASE + CONFIG_LPC54_EMC_STATIC_CS0_OFFSET); + heapstart = (FAR void *)(LPC54_SRAMCS0_BASE + + CONFIG_LPC54_EMC_STATIC_CS0_OFFSET); heapsize = CONFIG_LPC54_EMC_STATIC_CS0_SIZE; kumm_addregion(heapstart, heapsize); @@ -287,7 +294,8 @@ void arm_addregion(void) { /* Add the SRAM to the user heap */ - heapstart = (FAR void *)(LPC54_SRAMCS1_BASE + CONFIG_LPC54_EMC_STATIC_CS1_OFFSET); + heapstart = (FAR void *)(LPC54_SRAMCS1_BASE + + CONFIG_LPC54_EMC_STATIC_CS1_OFFSET); heapsize = CONFIG_LPC54_EMC_STATIC_CS1_SIZE; kumm_addregion(heapstart, heapsize); @@ -305,7 +313,8 @@ void arm_addregion(void) { /* Add the SRAM to the user heap */ - heapstart = (FAR void *)(LPC54_SRAMCS2_BASE + CONFIG_LPC54_EMC_STATIC_CS2_OFFSET); + heapstart = (FAR void *)(LPC54_SRAMCS2_BASE + + CONFIG_LPC54_EMC_STATIC_CS2_OFFSET); heapsize = CONFIG_LPC54_EMC_STATIC_CS2_SIZE; kumm_addregion(heapstart, heapsize); @@ -323,7 +332,8 @@ void arm_addregion(void) { /* Add the SRAM to the user heap */ - heapstart = (FAR void *)(LPC54_SRAMCS3_BASE + CONFIG_LPC54_EMC_STATIC_CS3_OFFSET); + heapstart = (FAR void *)(LPC54_SRAMCS3_BASE + + CONFIG_LPC54_EMC_STATIC_CS3_OFFSET); heapsize = CONFIG_LPC54_EMC_STATIC_CS3_SIZE; kumm_addregion(heapstart, heapsize); @@ -341,7 +351,8 @@ void arm_addregion(void) { /* Add the SDRAM to the user heap */ - heapstart = (FAR void *)(LPC54_DRAMCS0_BASE + CONFIG_LPC54_EMC_DYNAMIC_CS0_OFFSET); + heapstart = (FAR void *)(LPC54_DRAMCS0_BASE + + CONFIG_LPC54_EMC_DYNAMIC_CS0_OFFSET); heapsize = CONFIG_LPC54_EMC_DYNAMIC_CS0_SIZE; kumm_addregion(heapstart, heapsize); @@ -359,7 +370,8 @@ void arm_addregion(void) { /* Add the SDRAM to the user heap */ - heapstart = (FAR void *)(LPC54_DRAMCS1_BASE + CONFIG_LPC54_EMC_DYNAMIC_CS1_OFFSET); + heapstart = (FAR void *)(LPC54_DRAMCS1_BASE + + CONFIG_LPC54_EMC_DYNAMIC_CS1_OFFSET); heapsize = CONFIG_LPC54_EMC_DYNAMIC_CS1_SIZE; kumm_addregion(heapstart, heapsize); @@ -377,7 +389,8 @@ void arm_addregion(void) { /* Add the SDRAM to the user heap */ - heapstart = (FAR void *)(LPC54_DRAMCS2_BASE + CONFIG_LPC54_EMC_DYNAMIC_CS2_OFFSET); + heapstart = (FAR void *)(LPC54_DRAMCS2_BASE + + CONFIG_LPC54_EMC_DYNAMIC_CS2_OFFSET); heapsize = CONFIG_LPC54_EMC_DYNAMIC_CS2_SIZE; kumm_addregion(heapstart, heapsize); @@ -395,7 +408,8 @@ void arm_addregion(void) { /* Add the SDRAM to the user heap */ - heapstart = (FAR void *)(LPC54_DRAMCS3_BASE + CONFIG_LPC54_EMC_DYNAMIC_CS3_OFFSET); + heapstart = (FAR void *)(LPC54_DRAMCS3_BASE + + CONFIG_LPC54_EMC_DYNAMIC_CS3_OFFSET); heapsize = CONFIG_LPC54_EMC_DYNAMIC_CS3_SIZE; kumm_addregion(heapstart, heapsize); diff --git a/arch/arm/src/lpc54xx/lpc54_serial.c b/arch/arm/src/lpc54xx/lpc54_serial.c index 065138314e2..788b35b4f21 100644 --- a/arch/arm/src/lpc54xx/lpc54_serial.c +++ b/arch/arm/src/lpc54xx/lpc54_serial.c @@ -407,7 +407,7 @@ static int lpc54_attach(struct uart_dev_s *dev); static void lpc54_detach(struct uart_dev_s *dev); static int lpc54_interrupt(int irq, void *context, FAR void *arg); static int lpc54_ioctl(struct file *filep, int cmd, unsigned long arg); -static int lpc54_receive(struct uart_dev_s *dev, uint32_t *status); +static int lpc54_receive(struct uart_dev_s *dev, unsigned int *status); static void lpc54_rxint(struct uart_dev_s *dev, bool enable); static bool lpc54_rxavailable(struct uart_dev_s *dev); static void lpc54_send(struct uart_dev_s *dev, int ch); @@ -1199,7 +1199,7 @@ static int lpc54_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int lpc54_receive(struct uart_dev_s *dev, uint32_t *status) +static int lpc54_receive(struct uart_dev_s *dev, unsigned int *status) { struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev->priv; uint32_t fiford; diff --git a/arch/arm/src/max326xx/common/max326_start.c b/arch/arm/src/max326xx/common/max326_start.c index 1e6b683a60b..7136a9717dc 100644 --- a/arch/arm/src/max326xx/common/max326_start.c +++ b/arch/arm/src/max326xx/common/max326_start.c @@ -33,6 +33,10 @@ * ****************************************************************************/ +/**************************************************************************** + * Included Files + ****************************************************************************/ + #include #include @@ -91,7 +95,7 @@ * Public Data ****************************************************************************/ -const uint32_t g_idle_topstack = IDLE_STACK; +const uintptr_t g_idle_topstack = IDLE_STACK; /**************************************************************************** * Private Functions @@ -113,7 +117,8 @@ const uint32_t g_idle_topstack = IDLE_STACK; * done, the processor reserves space on the stack for the FP state, * but does not save that state information to the stack. * - * Software must not change the value of the ASPEN bit or LSPEN bit while either: + * Software must not change the value of the ASPEN bit or LSPEN bit while + * either: * - the CPACR permits access to CP10 and CP11, that give access to the FP * extension, or * - the CONTROL.FPCA bit is set to 1 diff --git a/arch/arm/src/max326xx/max32660/max32660_serial.c b/arch/arm/src/max326xx/max32660/max32660_serial.c index eb8a0278526..20cadea29e6 100644 --- a/arch/arm/src/max326xx/max32660/max32660_serial.c +++ b/arch/arm/src/max326xx/max32660/max32660_serial.c @@ -158,7 +158,7 @@ static int max326_attach(struct uart_dev_s *dev); static void max326_detach(struct uart_dev_s *dev); static int max326_interrupt(int irq, void *context, void *arg); static int max326_ioctl(struct file *filep, int cmd, unsigned long arg); -static int max326_receive(struct uart_dev_s *dev, uint32_t *status); +static int max326_receive(struct uart_dev_s *dev, unsigned int *status); static void max326_rxint(struct uart_dev_s *dev, bool enable); static bool max326_rxavailable(struct uart_dev_s *dev); static void max326_send(struct uart_dev_s *dev, int ch); @@ -631,7 +631,7 @@ static int max326_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int max326_receive(struct uart_dev_s *dev, uint32_t *status) +static int max326_receive(struct uart_dev_s *dev, unsigned int *status) { struct max326_dev_s *priv = (struct max326_dev_s *)dev->priv; diff --git a/arch/arm/src/nrf52/Kconfig b/arch/arm/src/nrf52/Kconfig index b104a5e0f77..3cdb76891b8 100644 --- a/arch/arm/src/nrf52/Kconfig +++ b/arch/arm/src/nrf52/Kconfig @@ -386,6 +386,24 @@ config NRF52_PROGMEM menu "GPIO Interrupt Configuration" +config NRF52_PER_PIN_INTERRUPTS + bool "Per-pin interrupt callbacks" + default n if DEFAULT_SMALL + default y if !DEFAULT_SMALL + depends on NRF52_GPIOTE + ---help--- + The GPIOTE peripheral supports a limited number of channels which can + be set to EVENT mode and thus generate interrupts on pin state changes. + Another mechanism offered by the GPIO/GPIOTE peripherals is the PORT + event. This event is generated from a signal shared by all pins in + the GPIO port. + + This option enables the ability to set per-pin callbacks that will + be invoked from the main GPIOTE ISR when a PORT event is generated. + As this involves extra storage to store each callback, this option can + be disabled to save space. In such case, it is possible to set a callback + for the whole PORT event directly. + endmenu # GPIO Interrupt Configuration menu "PWM configuration" diff --git a/arch/arm/src/nrf52/Make.defs b/arch/arm/src/nrf52/Make.defs index eeede65a0ba..51d08ea805f 100644 --- a/arch/arm/src/nrf52/Make.defs +++ b/arch/arm/src/nrf52/Make.defs @@ -159,3 +159,7 @@ endif ifeq ($(CONFIG_NRF52_SAADC),y) CHIP_CSRCS += nrf52_adc.c endif + +ifeq ($(CONFIG_PM),y) +CHIP_CSRCS += nrf52_pminitialize.c +endif diff --git a/arch/arm/src/nrf52/hardware/nrf52_gpio.h b/arch/arm/src/nrf52/hardware/nrf52_gpio.h index d14eaa408e3..57ab7717dde 100644 --- a/arch/arm/src/nrf52/hardware/nrf52_gpio.h +++ b/arch/arm/src/nrf52/hardware/nrf52_gpio.h @@ -57,6 +57,8 @@ # define NRF52_GPIO_NPORTS 1 #endif +#define NRF52_GPIO_NPINS 32 + /* Register offsets *****************************************************************/ #define NRF52_GPIO_OUT_OFFSET 0x0504 /* Write GPIO port */ @@ -95,6 +97,9 @@ /* Register bit definitions *********************************************************/ +#define GPIO_DETECTMODE_DEFAULT (0) +#define GPIO_DETECTMODE_LDETECT (1) + #define GPIO_CNF_DIR (1 << 0) /* Bit 0: Pin direction */ #define GPIO_CNF_INPUT (1 << 1) /* Bit 1: Input buffer disconnect */ #define GPIO_CNF_PULL_SHIFT (2) @@ -102,5 +107,20 @@ # define GPIO_CNF_PULL_DISABLED (0 << GPIO_CNF_PULL_SHIFT) # define GPIO_CNF_PULL_DOWN (1 << GPIO_CNF_PULL_SHIFT) # define GPIO_CNF_PULL_UP (3 << GPIO_CNF_PULL_SHIFT) +#define GPIO_CNF_DRIVE_SHIFT (8) +#define GPIO_CNF_DRIVE_MASK (0x7 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_S0S1 (0 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_H0S1 (1 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_S0H1 (2 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_H0H1 (3 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_D0S1 (4 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_D0H1 (5 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_S0D1 (6 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_H0D1 (7 << GPIO_CNF_DRIVE_SHIFT) +#define GPIO_CNF_SENSE_SHIFT (16) +#define GPIO_CNF_SENSE_MASK (0x3 << GPIO_CNF_SENSE_SHIFT) +# define GPIO_CNF_SENSE_DISABLED (0 << GPIO_CNF_SENSE_SHIFT) +# define GPIO_CNF_SENSE_HIGH (2 << GPIO_CNF_SENSE_SHIFT) +# define GPIO_CNF_SENSE_LOW (3 << GPIO_CNF_SENSE_SHIFT) #endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_GPIO_H */ diff --git a/arch/arm/src/nrf52/hardware/nrf52_gpiote.h b/arch/arm/src/nrf52/hardware/nrf52_gpiote.h index e4fb92bd48f..37a8d20d2b4 100644 --- a/arch/arm/src/nrf52/hardware/nrf52_gpiote.h +++ b/arch/arm/src/nrf52/hardware/nrf52_gpiote.h @@ -67,7 +67,8 @@ #define GPIOTE_INT_IN_MASK (0xff << GPIOTE_INT_IN_SHIFT) # define GPIOTE_INT_IN(i) ((1 << (i + GPIOTE_INT_IN_SHIFT)) & GPIOTE_INT_IN_MASK) -#define GPIOTE_INT_PORT 31 /* Bit 31: Enable interrupt for event PORT */ +#define GPIOTE_INT_PORT_SHIFT 31 /* Bit 31: Enable interrupt for event PORT */ +#define GPIOTE_INT_PORT (1 << GPIOTE_INT_PORT_SHIFT) /* CONFIG Register */ diff --git a/arch/arm/src/nrf52/hardware/nrf52_spi.h b/arch/arm/src/nrf52/hardware/nrf52_spi.h index 9a983612e7d..9498ab2bdc4 100644 --- a/arch/arm/src/nrf52/hardware/nrf52_spi.h +++ b/arch/arm/src/nrf52/hardware/nrf52_spi.h @@ -68,6 +68,7 @@ #define NRF52_SPIM_PSELDCX_OFFSET (0x056c) /* Pin select for DCX signal */ #define NRF52_SPIM_DCXCNT_OFFSET (0x0570) /* DCX configuration */ #define NRF52_SPIM_ORC_OFFSET (0x05c0) /* ORC */ +#define NRF52_SPIM_POWER_OFFSET (0x0ffc) /* Hidden POWER register, for applying errata workaround */ /* Register offsets for SPI slave (SPIS) ************************************/ @@ -153,12 +154,12 @@ #define SPIM_ENABLE_DIS (0) /* Disable SPIM */ #define SPIM_ENABLE_EN (0x7 << 0) /* Enable SPIM */ -/* PSEL(MOSI/MISO/SCK/CSN) Register */ +/* PSEL* Registers */ -#define SPIM_PSEL_PIN_SHIFT (0) /* Bits 0-4: pin number */ -#define SPIM_PSEL_PIN_MASK (0x1f << SPIM_PSEL_PIN_SHIFT) -#define SPIM_PSEL_PORT_SHIFT (5) /* Bit 5: port number */ -#define SPIM_PSEL_PORT_MASK (0x1 << SPIM_PSEL_PORT_SHIFT) +#define SPIM_PSEL_PIN_SHIFT (0) /* Bits 0-4: SCK pin number */ +#define SPIM_PSEL_PIN_MASK (0x1f << SPIM_PSELSCK_PIN_SHIFT) +#define SPIM_PSEL_PORT_SHIFT (5) /* Bit 5: SCK port number */ +#define SPIM_PSEL_PORT_MASK (0x1 << SPIM_PSELSCK_PORT_SHIFT) #define SPIM_PSEL_CONNECTED (1 << 31) /* Bit 31: Connection */ #define SPIM_PSEL_RESET (0xffffffff) diff --git a/arch/arm/src/nrf52/nrf52_allocateheap.c b/arch/arm/src/nrf52/nrf52_allocateheap.c index 313ab65699b..8f87b97b409 100644 --- a/arch/arm/src/nrf52/nrf52_allocateheap.c +++ b/arch/arm/src/nrf52/nrf52_allocateheap.c @@ -97,7 +97,8 @@ * aligned). */ -const uint32_t g_idle_topstack = (uint32_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE; +const uintptr_t g_idle_topstack = (uintptr_t)&_ebss + + CONFIG_IDLETHREAD_STACKSIZE; /**************************************************************************** * Public Functions @@ -132,7 +133,8 @@ const uint32_t g_idle_topstack = (uint32_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE; * * Kernel .data region. Size determined at link time. * Kernel .bss region Size determined at link time. - * Kernel IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Kernel IDLE thread stack. Size determined by + * CONFIG_IDLETHREAD_STACKSIZE. * Padding for alignment * User .data region. Size determined at link time. * User .bss region Size determined at link time. @@ -153,7 +155,8 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). */ - uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; size_t usize = CONFIG_RAM_END - ubase; DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); @@ -192,7 +195,8 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). */ - uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); /* Return the kernel heap settings (i.e., the part of the heap region diff --git a/arch/arm/src/nrf52/nrf52_gpio.c b/arch/arm/src/nrf52/nrf52_gpio.c index 3b6311361cb..6f5625c532f 100644 --- a/arch/arm/src/nrf52/nrf52_gpio.c +++ b/arch/arm/src/nrf52/nrf52_gpio.c @@ -144,22 +144,54 @@ static inline void nrf52_gpio_mode(nrf52_pinset_t cfgset, mode = cfgset & GPIO_MODE_MASK; regval = getreg32(offset); - regval &= GPIO_CNF_PULL_MASK; + regval &= ~GPIO_CNF_PULL_MASK; if (mode == GPIO_PULLUP) { - regval &= GPIO_CNF_PULL_MASK; regval |= GPIO_CNF_PULL_UP; } else if (mode == GPIO_PULLDOWN) { - regval &= GPIO_CNF_PULL_MASK; regval |= GPIO_CNF_PULL_DOWN; } putreg32(regval, offset); } +/**************************************************************************** + * Name: nrf52_gpio_sense + * + * Description: + * Set SENSE configuration for an input pin + * + ****************************************************************************/ + +static inline void nrf52_gpio_sense(nrf52_pinset_t cfgset, + unsigned int port, unsigned int pin) +{ + uint32_t mode; + uint32_t regval; + uint32_t offset; + + mode = cfgset & GPIO_SENSE_MASK; + + offset = nrf52_gpio_regget(port, NRF52_GPIO_PIN_CNF_OFFSET(pin)); + regval = getreg32(offset); + + regval &= ~GPIO_CNF_SENSE_MASK; + + if (mode == GPIO_SENSE_HIGH) + { + regval |= GPIO_CNF_SENSE_HIGH; + } + else if (mode == GPIO_SENSE_LOW) + { + regval |= GPIO_CNF_SENSE_LOW; + } + + putreg32(regval, offset); +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -204,7 +236,8 @@ int nrf52_gpio_config(nrf52_pinset_t cfgset) switch (cfgset & GPIO_FUNC_MASK) { case GPIO_INPUT: /* GPIO input pin */ - break; /* Already configured */ + nrf52_gpio_sense(cfgset, port, pin); + break; case GPIO_OUTPUT: /* GPIO outpout pin */ nrf52_gpio_output(cfgset, port, pin); @@ -313,3 +346,20 @@ bool nrf52_gpio_read(nrf52_pinset_t pinset) return (regval >> pin) & 1UL; } + +/**************************************************************************** + * Name: nrf52_gpio_detectmode + * + * Description: + * Set DETECTMODE to either default or latched + * + ****************************************************************************/ + +void nrf52_gpio_detectmode(int port, enum nrf52_gpio_detectmode_e mode) +{ + uint32_t offset = nrf52_gpio_regget(port, NRF52_GPIO_DETECTMODE_OFFSET); + + putreg32(mode == NRF52_GPIO_DETECTMODE_DETECT ? + GPIO_DETECTMODE_DEFAULT : + GPIO_DETECTMODE_LDETECT, offset); +} diff --git a/arch/arm/src/nrf52/nrf52_gpio.h b/arch/arm/src/nrf52/nrf52_gpio.h index 85fe0d01873..31bd8082103 100644 --- a/arch/arm/src/nrf52/nrf52_gpio.h +++ b/arch/arm/src/nrf52/nrf52_gpio.h @@ -187,6 +187,12 @@ typedef uint32_t nrf52_pinset_t; +enum nrf52_gpio_detectmode_e +{ + NRF52_GPIO_DETECTMODE_DETECT, + NRF52_GPIO_DETECTMODE_LDETECT, +}; + /************************************************************************************ * Public Data ************************************************************************************/ diff --git a/arch/arm/src/nrf52/nrf52_gpiote.c b/arch/arm/src/nrf52/nrf52_gpiote.c index 62cf57cfebd..09fb7435266 100644 --- a/arch/arm/src/nrf52/nrf52_gpiote.c +++ b/arch/arm/src/nrf52/nrf52_gpiote.c @@ -61,9 +61,21 @@ struct nrf52_gpiote_callback_s * Private Data ****************************************************************************/ -/* Interrupt handlers attached to each GPIOTE */ +/* Callbacks attached to each GPIOTE channel */ -static struct nrf52_gpiote_callback_s g_gpiote_callbacks[GPIOTE_CHANNELS]; +static struct nrf52_gpiote_callback_s g_gpiote_ch_callbacks[GPIOTE_CHANNELS]; + +#ifdef CONFIG_NRF52_PER_PIN_INTERRUPTS +/* Callbacks attached to each GPIO pin */ + +static struct nrf52_gpiote_callback_s + g_gpiote_pin_callbacks[NRF52_GPIO_NPORTS][NRF52_GPIO_NPINS]; +#else +/* Callback for the PORT event */ + +static struct nrf52_gpiote_callback_s + g_gpiote_port_callback[NRF52_GPIO_NPORTS]; +#endif /**************************************************************************** * Private Functions @@ -108,6 +120,9 @@ static int nrf52_gpiote_isr(int irq, FAR void *context, FAR void *arg) uint32_t regval = 0; int ret = OK; int i = 0; +#ifdef CONFIG_NRF52_PER_PIN_INTERRUPTS + int j = 0; +#endif /* Scan all GPIOTE channels */ @@ -115,7 +130,7 @@ static int nrf52_gpiote_isr(int irq, FAR void *context, FAR void *arg) { /* Only if callback is registered */ - if (g_gpiote_callbacks[i].callback != NULL) + if (g_gpiote_ch_callbacks[i].callback != NULL) { /* Get input event register */ @@ -124,8 +139,8 @@ static int nrf52_gpiote_isr(int irq, FAR void *context, FAR void *arg) { /* Execute callback */ - xcpt_t callback = g_gpiote_callbacks[i].callback; - FAR void *cbarg = g_gpiote_callbacks[i].arg; + xcpt_t callback = g_gpiote_ch_callbacks[i].callback; + FAR void *cbarg = g_gpiote_ch_callbacks[i].arg; ret = callback(irq, context, cbarg); /* Clear event */ @@ -135,6 +150,76 @@ static int nrf52_gpiote_isr(int irq, FAR void *context, FAR void *arg) } } + /* Check for PORT event */ + + regval = nrf52_gpiote_getreg(NRF52_GPIOTE_EVENTS_PORT_OFFSET); + if (regval) + { + uint32_t addr = 0; + + /* Ack PORT event */ + + nrf52_gpiote_putreg(NRF52_GPIOTE_EVENTS_PORT_OFFSET, 0); + + /* For each GPIO port, get LATCH register */ + + for (i = 0; i < NRF52_GPIO_NPORTS; i++) + { + switch (i) + { + case 0: + addr = NRF52_GPIO_P0_BASE + NRF52_GPIO_LATCH_OFFSET; + break; +#ifdef CONFIG_NRF52_HAVE_PORT1 + case 1: + addr = NRF52_GPIO_P1_BASE + NRF52_GPIO_LATCH_OFFSET; + break; +#endif + } + + /* Retrieve LATCH register */ + + regval = getreg32(addr); + + /* Clear LATCH register (this may set PORT again) */ + + putreg32(0xffffffff, addr); + +#ifdef CONFIG_NRF52_PER_PIN_INTERRUPTS + /* Check for pins with DETECT bit high in LATCH register + * and dispatch callback if set + */ + + for (j = 0; j < NRF52_GPIO_NPINS && regval; j++) + { + if (regval & (1 << j) && g_gpiote_pin_callbacks[i][j].callback) + { + /* Run callback */ + + xcpt_t callback = g_gpiote_pin_callbacks[i][j].callback; + FAR void *cbarg = g_gpiote_pin_callbacks[i][j].arg; + + ret = callback(irq, context, cbarg); + + /* Mark bit is as "visited", we can stop looping sooner + * this way + */ + + regval &= ~(1 << j); + } + } +#else + if (g_gpiote_port_callback[i].callback) + { + xcpt_t callback = g_gpiote_port_callback[i].callback; + FAR void *cbarg = g_gpiote_port_callback[i].arg; + + ret = callback(irq, context, cbarg); + } +#endif + } + } + return ret; } @@ -142,11 +227,126 @@ static int nrf52_gpiote_isr(int irq, FAR void *context, FAR void *arg) * Public Functions ****************************************************************************/ +#ifdef CONFIG_NRF52_PER_PIN_INTERRUPTS /**************************************************************************** - * Name: nrf52_gpiosetevent + * Name: nrf52_gpiote_set_pin_event * * Description: - * Sets/clears GPIO based event and interrupt triggers. + * Sets/clears a handler for a given pin for the GPIO PORT event. This + * will mean edge-sensitive or level-sensitive according to GPIO detect + * mode configuration for the port (see nrf52_gpio_detectmode()). Pin + * will be sensitive to high/low according to GPIO_SENSE_LOW/HIGH + * (set via nrf52_gpio_config()). + * + * The passed handler will be invoked from the main ISR for the PORT + * event and will take care of clearing the LATCH register. + * + * Input Parameters: + * - pinset: GPIO pin configuration + * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure indicating the + * nature of the failure. + * + ****************************************************************************/ + +void nrf52_gpiote_set_pin_event(uint32_t pinset, xcpt_t func, FAR void *arg) +{ + int pin = 0; + int port = 0; + irqstate_t flags; + + pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; +#ifdef CONFIG_NRF52_HAVE_PORT1 + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; +#endif + + flags = enter_critical_section(); + + g_gpiote_pin_callbacks[port][pin].callback = func; + g_gpiote_pin_callbacks[port][pin].arg = arg; + + leave_critical_section(flags); +} +#else +/**************************************************************************** + * Name: nrf52_gpiote_set_port_event + * + * Description: + * Sets/clears the handler for the GPIO PORT event. + * + * The passed handler will be invoked from the main ISR for the PORT + * event and will take care of clearing the LATCH register. + * + * Input Parameters: + * - pinset: GPIO port will be extracted from this parameter + * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure indicating the + * nature of the failure. + * + ****************************************************************************/ + +void nrf52_gpiote_set_port_event(uint32_t pinset, xcpt_t func, FAR void *arg) +{ + int port = 0; + irqstate_t flags; + +#ifdef CONFIG_NRF52_HAVE_PORT1 + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; +#endif + + flags = enter_critical_section(); + + g_gpiote_port_callback[port].callback = func; + g_gpiote_port_callback[port].arg = arg; + + if (func) + { + /* Enable the ISR */ + + nrf52_gpiote_putreg(NRF52_GPIOTE_INTENSET_OFFSET, GPIOTE_INT_PORT); + } + else + { +#if NRF52_GPIO_NPORTS > 1 + /* Check if we can disable the ISR */ + + int i; + + for (i = 0; i < NRF52_GPIO_NPORTS; i++) + { + if (g_gpiote_port_callback[port].callback) + { + break; + } + } + + if (i == NRF52_GPIO_NPORTS) + { + nrf52_gpiote_putreg(NRF52_GPIOTE_INTENCLR_OFFSET, GPIOTE_INT_PORT); + } +#else + /* Disable the ISR */ + + nrf52_gpiote_putreg(NRF52_GPIOTE_INTENCLR_OFFSET, GPIOTE_INT_PORT); +#endif + } + + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: nrf52_gpiote_set_ch_event + * + * Description: + * Configures a GPIOTE channel in EVENT mode, assigns it to a given pin + * and sets a handler for the corresponding channel events. * * Input Parameters: * - pinset: GPIO pin configuration @@ -162,122 +362,90 @@ static int nrf52_gpiote_isr(int irq, FAR void *context, FAR void *arg) * ****************************************************************************/ -int nrf52_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func, FAR void *arg) +void nrf52_gpiote_set_ch_event(uint32_t pinset, int channel, + bool risingedge, bool fallingedge, + xcpt_t func, FAR void *arg) { - int ret = OK; - int i = 0; int pin = 0; #ifdef CONFIG_NRF52_HAVE_PORT1 int port = 0; #endif uint32_t regval = 0; - bool found = false; irqstate_t flags; - /* Find available GPIOTE channel */ - - flags = enter_critical_section(); - - for (i = 0; i < GPIOTE_CHANNELS; i += 1) - { - if (g_gpiote_callbacks[i].callback == NULL) - { - found = true; - break; - } - } - - leave_critical_section(flags); - - /* Return error if there is no free channel */ - - if (found == false) - { - ret = -ENODEV; - goto errout; - } + DEBUGASSERT(channel < GPIOTE_CHANNELS); /* NOTE: GPIOTE module has priority over GPIO module * so GPIO configuration will be ignored */ - /* Select GPIOTE pin */ + flags = enter_critical_section(); - pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - regval = (pin << GPIOTE_CONFIG_PSEL_SHIFT); + if (func) + { + /* Select EVENT mode */ + + regval |= GPIOTE_CONFIG_MODE_EV; + + /* Select GPIOTE pin */ + + pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + regval |= (pin << GPIOTE_CONFIG_PSEL_SHIFT); #ifdef CONFIG_NRF52_HAVE_PORT1 - port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - regval |= (port << GPIOTE_CONFIG_PORT_SHIFT); + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + regval |= (port << GPIOTE_CONFIG_PORT_SHIFT); #endif - /* Select EVENT mode */ + /* Select polarity */ - if (event || func) - { - regval &= ~GPIOTE_CONFIG_MODE_MASK; - regval |= GPIOTE_CONFIG_MODE_EV; - } + if (risingedge == true && fallingedge == true) + { + regval |= GPIOTE_CONFIG_POL_TG; + } + else if (risingedge == true) + { + regval |= GPIOTE_CONFIG_POL_LTH; + } + else if (fallingedge == true) + { + regval |= GPIOTE_CONFIG_POL_HTL; + } - /* Select polarity */ + /* Enable callback for channel */ - if (risingedge == true && fallingedge == true) - { - regval |= GPIOTE_CONFIG_POL_TG; + g_gpiote_ch_callbacks[channel].callback = func; + g_gpiote_ch_callbacks[channel].arg = arg; + + /* Enable interrupt for given event */ + + nrf52_gpiote_putreg(NRF52_GPIOTE_INTENSET_OFFSET, + GPIOTE_INT_IN(channel)); } - else if (risingedge == true) + else { - regval |= GPIOTE_CONFIG_POL_LTH; - } - else if (fallingedge == true) - { - regval |= GPIOTE_CONFIG_POL_HTL; + /* Leave register as zero (disabled mode) */ + + /* Disable interrupt for given event */ + + nrf52_gpiote_putreg(NRF52_GPIOTE_INTENCLR_OFFSET, + GPIOTE_INT_IN(channel)); + + /* Remove callback configuration */ + + g_gpiote_ch_callbacks[channel].callback = NULL; + g_gpiote_ch_callbacks[channel].arg = NULL; } /* Write CONFIG register */ - nrf52_gpiote_putreg(NRF52_GPIOTE_CONFIG_OFFSET(i), regval); + nrf52_gpiote_putreg(NRF52_GPIOTE_CONFIG_OFFSET(channel), regval); - /* Enable interrupt for given event */ - - nrf52_gpiote_putreg(NRF52_GPIOTE_INTENSET_OFFSET, GPIOTE_INT_IN(i)); - - /* Connect callback */ - - g_gpiote_callbacks[i].callback = func; - g_gpiote_callbacks[i].arg = arg; - -errout: - return ret; + leave_critical_section(flags); } /**************************************************************************** - * Name: nrf52_gpiote_init - * - * Description: - * Initialize GPIOTE - * - ****************************************************************************/ - -int nrf52_gpiote_init(void) -{ - /* Reset GPIOTE data */ - - memset(&g_gpiote_callbacks, - 0, - sizeof(struct nrf52_gpiote_callback_s)*GPIOTE_CHANNELS); - - /* Attach GPIOTE interrupt handler */ - - irq_attach(NRF52_IRQ_GPIOTE, nrf52_gpiote_isr, NULL); - up_enable_irq(NRF52_IRQ_GPIOTE); - - return OK; -} - -/**************************************************************************** - * Name: nrf52_gpiotaskset + * Name: nrf52_gpio_set_task * * Description: * Configure GPIO in TASK mode (to be controlled via tasks). @@ -299,8 +467,9 @@ int nrf52_gpiote_init(void) * ****************************************************************************/ -int nrf52_gpiotaskset(uint32_t pinset, int channel, - bool output_high, enum nrf52_gpiote_outcfg_e outcfg) +void nrf52_gpiote_set_task(uint32_t pinset, int channel, + bool output_high, + enum nrf52_gpiote_outcfg_e outcfg) { uint32_t regval; int pin; @@ -351,6 +520,44 @@ int nrf52_gpiotaskset(uint32_t pinset, int channel, /* Write register */ nrf52_gpiote_putreg(NRF52_GPIOTE_CONFIG_OFFSET(channel), regval); +} + +/**************************************************************************** + * Name: nrf52_gpiote_init + * + * Description: + * Initialize GPIOTE + * + ****************************************************************************/ + +int nrf52_gpiote_init(void) +{ + /* Clear LATCH register(s) */ + + putreg32(0, NRF52_GPIO_P0_BASE + NRF52_GPIO_LATCH_OFFSET); + +#ifdef CONFIG_NRF52_HAVE_PORT1 + putreg32(0, NRF52_GPIO_P1_BASE + NRF52_GPIO_LATCH_OFFSET); +#endif + + /* Reset GPIOTE data */ + + memset(&g_gpiote_ch_callbacks, 0, sizeof(g_gpiote_ch_callbacks)); + +#ifdef CONFIG_NRF52_PER_PIN_INTERRUPTS + memset(&g_gpiote_pin_callbacks, 0, sizeof(g_gpiote_pin_callbacks)); + + /* Enable PORT event interrupt */ + + nrf52_gpiote_putreg(NRF52_GPIOTE_INTENSET_OFFSET, GPIOTE_INT_PORT); +#else + memset(&g_gpiote_port_callback, 0, sizeof(g_gpiote_port_callback)); +#endif + + /* Attach GPIOTE interrupt handler */ + + irq_attach(NRF52_IRQ_GPIOTE, nrf52_gpiote_isr, NULL); + up_enable_irq(NRF52_IRQ_GPIOTE); return OK; } diff --git a/arch/arm/src/nrf52/nrf52_gpiote.h b/arch/arm/src/nrf52/nrf52_gpiote.h index 108112145d3..75a7a8e0805 100644 --- a/arch/arm/src/nrf52/nrf52_gpiote.h +++ b/arch/arm/src/nrf52/nrf52_gpiote.h @@ -49,17 +49,19 @@ enum nrf52_gpiote_outcfg_e ****************************************************************************/ /**************************************************************************** - * Name: nrf52_gpiosetevent + * Name: nrf52_gpiote_set_ch_event * * Description: - * Sets/clears GPIO based event and interrupt triggers. + * Configures a GPIOTE channel in EVENT mode, assigns it to a given pin + * and sets a handler for the corresponding channel events. * * Input Parameters: - * - pinset: gpio pin configuration - * - rising/falling edge: enables - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback + * - pinset: GPIO pin configuration + * - risingedge: Enables interrupt on rising edges + * - fallingedge: Enables interrupt on falling edges + * - event: Generate event when set + * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback * * Returned Value: * Zero (OK) on success; a negated errno value on failure indicating the @@ -67,11 +69,65 @@ enum nrf52_gpiote_outcfg_e * ****************************************************************************/ -int nrf52_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func, FAR void *arg); +void nrf52_gpiote_set_ch_event(uint32_t pinset, int channel, + bool risingedge, bool fallingedge, + xcpt_t func, FAR void *arg); + +#ifdef CONFIG_NRF52_PER_PIN_INTERRUPTS +/**************************************************************************** + * Name: nrf52_gpiote_set_pin_event + * + * Description: + * Sets/clears a handler for a given pin for the GPIO PORT event. This + * will mean edge-sensitive or level-sensitive according to GPIO detect + * mode configuration for the port (see nrf52_gpio_detectmode()). Pin + * will be sensitive to high/low according to GPIO_SENSE_LOW/HIGH + * (set via nrf52_gpio_config()). + * + * The passed handler will be invoked from the main ISR for the PORT + * event and will take care of clearing the LATCH register. + * + * Input Parameters: + * - pinset: GPIO pin configuration + * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure indicating the + * nature of the failure. + * + ****************************************************************************/ + +void nrf52_gpiote_set_pin_event(uint32_t pinset, xcpt_t func, FAR void *arg); +#else /**************************************************************************** - * Name: nrf52_gpiotaskset + * Name: nrf52_gpiote_set_port_event + * + * Description: + * Sets/clears the handler for the GPIO PORT event. + * + * The passed handler will be invoked from the main ISR for the PORT + * event and will take care of clearing the LATCH register. + * + * Input Parameters: + * - pinset: GPIO port will be extracted from this parameter + * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure indicating the + * nature of the failure. + * + ****************************************************************************/ + +void nrf52_gpiote_set_port_event(uint32_t pinset, xcpt_t func, + FAR void *arg); + +#endif + +/**************************************************************************** + * Name: nrf52_gpio_set_task * * Description: * Configure GPIO in TASK mode (to be controlled via tasks). @@ -93,8 +149,8 @@ int nrf52_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, * ****************************************************************************/ -int nrf52_gpiotaskset(uint32_t pinset, int channel, bool output_high, - enum nrf52_gpiote_outcfg_e outcfg); +void nrf52_gpio_set_task(uint32_t pinset, int channel, + bool output_high, enum nrf52_gpiote_outcfg_e outcfg); /**************************************************************************** * Name: nrf52_gpiote_init diff --git a/arch/arm/src/nrf52/nrf52_pminitialize.c b/arch/arm/src/nrf52/nrf52_pminitialize.c new file mode 100644 index 00000000000..edd3c22ffcf --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_pminitialize.c @@ -0,0 +1,55 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_pminitialize.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_pminitialize + * + * Description: + * This function is called by MCU-specific logic at power-on reset in + * order to provide one-time initialization the power management subsystem. + * This function must be called *very* early in the initialization sequence + * *before* any other device drivers are initialized (since they may + * attempt to register with the power management subsystem). + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void arm_pminitialize(void) +{ + /* Then initialize the NuttX power management subsystem proper */ + + pm_initialize(); +} diff --git a/arch/arm/src/nrf52/nrf52_serial.c b/arch/arm/src/nrf52/nrf52_serial.c index c26234a000a..b1c17f25cbf 100644 --- a/arch/arm/src/nrf52/nrf52_serial.c +++ b/arch/arm/src/nrf52/nrf52_serial.c @@ -136,7 +136,7 @@ static int nrf52_attach(struct uart_dev_s *dev); static void nrf52_detach(struct uart_dev_s *dev); static int nrf52_interrupt(int irq, void *context, FAR void *arg); static int nrf52_ioctl(struct file *filep, int cmd, unsigned long arg); -static int nrf52_receive(struct uart_dev_s *dev, uint32_t *status); +static int nrf52_receive(struct uart_dev_s *dev, unsigned int *status); static void nrf52_rxint(struct uart_dev_s *dev, bool enable); static bool nrf52_rxavailable(struct uart_dev_s *dev); static void nrf52_send(struct uart_dev_s *dev, int ch); @@ -576,7 +576,7 @@ static int nrf52_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int nrf52_receive(struct uart_dev_s *dev, uint32_t *status) +static int nrf52_receive(struct uart_dev_s *dev, unsigned int *status) { struct nrf52_dev_s *priv = (struct nrf52_dev_s *)dev->priv; uint32_t data; diff --git a/arch/arm/src/nrf52/nrf52_spi.c b/arch/arm/src/nrf52/nrf52_spi.c index afc275c812f..57f836b93d2 100644 --- a/arch/arm/src/nrf52/nrf52_spi.c +++ b/arch/arm/src/nrf52/nrf52_spi.c @@ -31,8 +31,10 @@ #include #include #include +#include #include "arm_arch.h" +#include "barriers.h" #include "nrf52_gpio.h" #include "nrf52_spi.h" @@ -72,10 +74,10 @@ struct nrf52_spidev_s { struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t base; /* Base address of SPI register */ - nrf52_pinset_t sck_pin; /* Pin settings for SPI clock */ #ifdef CONFIG_NRF52_SPI_MASTER_INTERRUPTS uint32_t irq; /* SPI IRQ number */ #endif + nrf52_pinset_t sck_pin; /* SCK pin configuration */ uint32_t frequency; /* Requested clock frequency */ uint8_t mode; /* Mode 0,1,2,3 */ @@ -85,6 +87,7 @@ struct nrf52_spidev_s #ifdef CONFIG_NRF52_SPI_MASTER_INTERRUPTS sem_t sem_isr; /* Interrupt wait semaphore */ #endif + bool initialized; }; /**************************************************************************** @@ -97,8 +100,6 @@ static inline void nrf52_spi_putreg(FAR struct nrf52_spidev_s *priv, static inline uint32_t nrf52_spi_getreg(FAR struct nrf52_spidev_s *priv, uint32_t offset); -static void nrf52_spi_pselinit(uint32_t pselreg, nrf52_pinset_t pinset); - /* SPI methods */ static int nrf52_spi_lock(FAR struct spi_dev_s *dev, bool lock); @@ -131,12 +132,32 @@ static int nrf52_spi_isr(int irq, FAR void *context, FAR void *arg); /* Initialization */ static int nrf52_spi_init(FAR struct nrf52_spidev_s *priv); +static void nrf52_spi_pselinit(FAR struct nrf52_spidev_s *priv, + uint32_t offset, nrf52_pinset_t pinset); static void nrf52_spi_gpioinit(FAR struct nrf52_spidev_s *priv); +#ifdef CONFIG_PM +static int nrf52_spi_deinit(FAR struct nrf52_spidev_s *priv); +static void nrf52_spi_gpiodeinit(FAR struct nrf52_spidev_s *priv); + +static int nrf52_spi_pm_prepare(FAR struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static void nrf52_spi_pm_notify(FAR struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + /**************************************************************************** * Private Data ****************************************************************************/ +#ifdef CONFIG_PM +struct pm_callback_s g_pm_callbacks = +{ + .prepare = nrf52_spi_pm_prepare, + .notify = nrf52_spi_pm_notify +}; +#endif + /* SPI0 */ #ifdef CONFIG_NRF52_SPI0_MASTER @@ -179,10 +200,10 @@ static struct nrf52_spidev_s g_spi0dev = }, .base = NRF52_SPIM0_BASE, - .sck_pin = BOARD_SPI0_SCK_PIN, #ifdef CONFIG_NRF52_SPI_MASTER_INTERRUPTS .irq = NRF52_IRQ_SPI_TWI_0, #endif + .sck_pin = BOARD_SPI0_SCK_PIN, .frequency = 0, .mode = 0 }; @@ -230,10 +251,10 @@ static struct nrf52_spidev_s g_spi1dev = }, .base = NRF52_SPIM1_BASE, - .sck_pin = BOARD_SPI1_SCK_PIN, #ifdef CONFIG_NRF52_SPI_MASTER_INTERRUPTS .irq = NRF52_IRQ_SPI_TWI_1, #endif + .sck_pin = BOARD_SPI1_SCK_PIN, .frequency = 0, .mode = 0 }; @@ -281,10 +302,10 @@ static struct nrf52_spidev_s g_spi2dev = }, .base = NRF52_SPIM2_BASE, - .sck_pin = BOARD_SPI2_SCK_PIN, #ifdef CONFIG_NRF52_SPI_MASTER_INTERRUPTS .irq = NRF52_IRQ_SPI2, #endif + .sck_pin = BOARD_SPI2_SCK_PIN, .frequency = 0, .mode = 0 }; @@ -332,10 +353,10 @@ static struct nrf52_spidev_s g_spi3dev = }, .base = NRF52_SPIM3_BASE, - .sck_pin = BOARD_SPI3_SCK_PIN, #ifdef CONFIG_NRF52_SPI_MASTER_INTERRUPTS .irq = NRF52_IRQ_SPI3, #endif + .sck_pin = BOARD_SPI3_SCK_PIN, .frequency = 0, .mode = 0 }; @@ -404,107 +425,6 @@ static int nrf52_spi_isr(int irq, FAR void *context, FAR void *arg) } #endif -/**************************************************************************** - * Name: nrf52_spi_pselinit - * - * Description: - * Configure PSEL for SPI devices - * - ****************************************************************************/ - -static void nrf52_spi_pselinit(uint32_t pselreg, nrf52_pinset_t pinset) -{ - uint32_t regval; - int pin = GPIO_PIN_DECODE(pinset); - int port = GPIO_PORT_DECODE(pinset); - - regval = (pin << SPIM_PSEL_PIN_SHIFT); - regval |= (port << SPIM_PSEL_PORT_SHIFT); - putreg32(pselreg, regval); -} - -/**************************************************************************** - * Name: nrf52_spi_gpioinit - * - * Description: - * Configure GPIO for SPI pins - * - ****************************************************************************/ - -static void nrf52_spi_gpioinit(FAR struct nrf52_spidev_s *priv) -{ - nrf52_gpio_config(priv->sck_pin); - nrf52_spi_pselinit(priv->base + NRF52_SPIM_PSELSCK_OFFSET, - priv->sck_pin); -#ifdef CONFIG_NRF52_SPI0_MASTER - if (priv == &g_spi0dev) - { -#ifdef BOARD_SPI0_MISO_PIN - nrf52_gpio_config(BOARD_SPI0_MISO_PIN); - nrf52_spi_pselinit(priv->base + NRF52_SPIM_PSELMISO_OFFSET, - BOARD_SPI0_MISO_PIN); - nrf52_gpio_write(BOARD_SPI0_MISO_PIN, false); -#endif -#ifdef BOARD_SPI0_MOSI_PIN - nrf52_gpio_config(BOARD_SPI0_MOSI_PIN); - nrf52_spi_pselinit(priv->base + NRF52_SPIM_PSELMOSI_OFFSET, - BOARD_SPI0_MOSI_PIN); -#endif - } -#endif - -#ifdef CONFIG_NRF52_SPI1_MASTER - if (priv == &g_spi1dev) - { -#ifdef BOARD_SPI1_MISO_PIN - nrf52_gpio_config(BOARD_SPI1_MISO_PIN); - nrf52_spi_pselinit(priv->base + NRF52_SPIM_PSELMISO_OFFSET, - BOARD_SPI1_MISO_PIN); - nrf52_gpio_write(BOARD_SPI1_MISO_PIN, false); -#endif -#ifdef BOARD_SPI1_MOSI_PIN - nrf52_gpio_config(BOARD_SPI1_MOSI_PIN); - nrf52_spi_pselinit(priv->base + NRF52_SPIM_PSELMOSI_OFFSET, - BOARD_SPI1_MOSI_PIN); -#endif - } -#endif - -#ifdef CONFIG_NRF52_SPI2_MASTER - if (priv == &g_spi2dev) - { -#ifdef BOARD_SPI2_MISO_PIN - nrf52_gpio_config(BOARD_SPI2_MISO_PIN); - nrf52_spi_pselinit(priv->base + NRF52_SPIM_PSELMISO_OFFSET, - BOARD_SPI1_MISO_PIN); - nrf52_gpio_write(BOARD_SPI1_MISO_PIN, false); -#endif -#ifdef BOARD_SPI2_MOSI_PIN - nrf52_gpio_config(BOARD_SPI2_MOSI_PIN); - nrf52_spi_pselinit(priv->base + NRF52_SPIM_PSELMOSI_OFFSET, - BOARD_SPI2_MOSI_PIN); -#endif - } -#endif - -#ifdef CONFIG_NRF52_SPI3_MASTER - if (priv == &g_spi3dev) - { -#ifdef BOARD_SPI3_MISO_PIN - nrf52_gpio_config(BOARD_SPI3_MISO_PIN); - nrf52_spi_pselinit(priv->base + NRF52_SPIM_PSELMISO_OFFSET, - BOARD_SPI3_MISO_PIN); - nrf52_gpio_write(BOARD_SPI1_MISO_PIN, false); -#endif -#ifdef BOARD_SPI3_MOSI_PIN - nrf52_gpio_config(BOARD_SPI3_MOSI_PIN); - nrf52_spi_pselinit(priv->base + NRF52_SPIM_PSELMOSI_OFFSET, - BOARD_SPI3_MOSI_PIN); -#endif - } -#endif -} - /**************************************************************************** * Name: nrf52_spi_init * @@ -523,6 +443,8 @@ static int nrf52_spi_init(FAR struct nrf52_spidev_s *priv) nrf52_spi_gpioinit(priv); + /* NOTE: Chip select pin must be configured by board-specific logic */ + #ifdef CONFIG_NRF52_SPI_MASTER_INTERRUPTS /* Enable interrupts for RX and TX done */ @@ -536,6 +458,205 @@ static int nrf52_spi_init(FAR struct nrf52_spidev_s *priv) return OK; } +#ifdef CONFIG_PM +/**************************************************************************** + * Name: nrf52_spi_deinit + * + * Description: + * Configure SPI + * + ****************************************************************************/ + +static int nrf52_spi_deinit(FAR struct nrf52_spidev_s *priv) +{ + /* Disable SPI */ + + nrf52_spi_putreg(priv, NRF52_SPIM_ENABLE_OFFSET, SPIM_ENABLE_DIS); + +#ifdef CONFIG_ARCH_CHIP_NRF52832 + /* Apply workaround for errata 89 (replace dummy read by barrier to avoid + * compiler optimizing it away) + */ + + nrf52_spi_putreg(priv, NRF52_SPIM_POWER_OFFSET, 0); + ARM_DSB(); + ARM_ISB(); + nrf52_spi_putreg(priv, NRF52_SPIM_POWER_OFFSET, 1); +#endif + + /* Unconfigure SPI pins */ + + nrf52_spi_gpiodeinit(priv); + + return OK; +} +#endif + +/**************************************************************************** + * Name: nrf52_spi_pselinit + * + * Description: + * Configure PSEL for SPI devices + * + ****************************************************************************/ + +static void nrf52_spi_pselinit(FAR struct nrf52_spidev_s *priv, + uint32_t offset, nrf52_pinset_t pinset) +{ + uint32_t regval; + int pin = GPIO_PIN_DECODE(pinset); + int port = GPIO_PORT_DECODE(pinset); + + regval = (pin << SPIM_PSEL_PIN_SHIFT); + regval |= (port << SPIM_PSEL_PORT_SHIFT); + nrf52_spi_putreg(priv, offset, regval); +} + +/**************************************************************************** + * Name: nrf52_spi_gpioinit + * + * Description: + * Configure GPIO for SPI pins + * + ****************************************************************************/ + +static void nrf52_spi_gpioinit(FAR struct nrf52_spidev_s *priv) +{ + nrf52_gpio_config(priv->sck_pin); + nrf52_spi_pselinit(priv, NRF52_SPIM_PSELSCK_OFFSET, priv->sck_pin); + +#ifdef CONFIG_NRF52_SPI0_MASTER + if (priv == &g_spi0dev) + { +#ifdef BOARD_SPI0_MISO_PIN + nrf52_gpio_config(BOARD_SPI0_MISO_PIN); + nrf52_spi_pselinit(priv, NRF52_SPIM_PSELMISO_OFFSET, + BOARD_SPI0_MISO_PIN); +#endif +#ifdef BOARD_SPI0_MOSI_PIN + nrf52_gpio_config(BOARD_SPI0_MOSI_PIN); + nrf52_spi_pselinit(priv, NRF52_SPIM_PSELMOSI_OFFSET, + BOARD_SPI0_MOSI_PIN); + nrf52_gpio_write(BOARD_SPI0_MOSI_PIN, false); +#endif + } +#endif + +#ifdef CONFIG_NRF52_SPI1_MASTER + if (priv == &g_spi1dev) + { +#ifdef BOARD_SPI1_MISO_PIN + nrf52_gpio_config(BOARD_SPI1_MISO_PIN); + nrf52_spi_pselinit(priv, NRF52_SPIM_PSELMISO_OFFSET, + BOARD_SPI1_MISO_PIN); +#endif +#ifdef BOARD_SPI1_MOSI_PIN + nrf52_gpio_config(BOARD_SPI1_MOSI_PIN); + nrf52_spi_pselinit(priv, NRF52_SPIM_PSELMOSI_OFFSET, + BOARD_SPI1_MOSI_PIN); + nrf52_gpio_write(BOARD_SPI1_MOSI_PIN, false); +#endif + } +#endif + +#ifdef CONFIG_NRF52_SPI2_MASTER + if (priv == &g_spi2dev) + { +#ifdef BOARD_SPI2_MISO_PIN + nrf52_gpio_config(BOARD_SPI2_MISO_PIN); + nrf52_spi_pselinit(priv, NRF52_SPIM_PSELMISO_OFFSET, + BOARD_SPI2_MISO_PIN); +#endif +#ifdef BOARD_SPI2_MOSI_PIN + nrf52_gpio_config(BOARD_SPI2_MOSI_PIN); + nrf52_spi_pselinit(priv, NRF52_SPIM_PSELMOSI_OFFSET, + BOARD_SPI2_MOSI_PIN); + nrf52_gpio_write(BOARD_SPI2_MOSI_PIN, false); +#endif + } +#endif + +#ifdef CONFIG_NRF52_SPI3_MASTER + if (priv == &g_spi3dev) + { +#ifdef BOARD_SPI3_MISO_PIN + nrf52_gpio_config(BOARD_SPI3_MISO_PIN); + nrf52_spi_pselinit(priv, NRF52_SPIM_PSELMISO_OFFSET, + BOARD_SPI3_MISO_PIN); +#endif +#ifdef BOARD_SPI3_MOSI_PIN + nrf52_gpio_config(BOARD_SPI3_MOSI_PIN); + nrf52_spi_pselinit(priv, NRF52_SPIM_PSELMOSI_OFFSET, + BOARD_SPI3_MOSI_PIN); + nrf52_gpio_write(BOARD_SPI3_MOSI_PIN, false); +#endif + } +#endif +} + +#ifdef CONFIG_PM +/**************************************************************************** + * Name: nrf52_spi_gpioinit + * + * Description: + * Configure GPIO for SPI pins + * + ****************************************************************************/ + +static void nrf52_spi_gpiodeinit(FAR struct nrf52_spidev_s *priv) +{ + nrf52_gpio_unconfig(priv->sck_pin); + +#ifdef CONFIG_NRF52_SPI0_MASTER + if (priv == &g_spi0dev) + { +#ifdef BOARD_SPI0_MISO_PIN + nrf52_gpio_unconfig(BOARD_SPI0_MISO_PIN); +#endif +#ifdef BOARD_SPI0_MOSI_PIN + nrf52_gpio_unconfig(BOARD_SPI0_MOSI_PIN); +#endif + } +#endif + +#ifdef CONFIG_NRF52_SPI1_MASTER + if (priv == &g_spi1dev) + { +#ifdef BOARD_SPI1_MISO_PIN + nrf52_gpio_unconfig(BOARD_SPI1_MISO_PIN); +#endif +#ifdef BOARD_SPI1_MOSI_PIN + nrf52_gpio_unconfig(BOARD_SPI1_MOSI_PIN); +#endif + } +#endif + +#ifdef CONFIG_NRF52_SPI2_MASTER + if (priv == &g_spi2dev) + { +#ifdef BOARD_SPI2_MISO_PIN + nrf52_gpio_unconfig(BOARD_SPI2_MISO_PIN); +#endif +#ifdef BOARD_SPI2_MOSI_PIN + nrf52_gpio_unconfig(BOARD_SPI2_MOSI_PIN); +#endif + } +#endif + +#ifdef CONFIG_NRF52_SPI3_MASTER + if (priv == &g_spi3dev) + { +#ifdef BOARD_SPI3_MISO_PIN + nrf52_gpio_unconfig(BOARD_SPI3_MISO_PIN); +#endif +#ifdef BOARD_SPI3_MOSI_PIN + nrf52_gpio_unconfig(BOARD_SPI3_MOSI_PIN); +#endif + } +#endif +} +#endif + /**************************************************************************** * Name: nrf52_spi_lock * @@ -943,15 +1064,7 @@ static void nrf52_spi_exchange(FAR struct spi_dev_s *dev, { FAR struct nrf52_spidev_s *priv = (FAR struct nrf52_spidev_s *)dev; uint32_t regval = 0; - - if (nwords > 0xff) - { - /* MAXCNT register can only hold 8bits */ - - spierr("SPI transfer max of 255 bytes, %d requested\n") - DEBUGASSERT(false); - return; - } + size_t nwords_left = nwords; #ifdef CONFIG_NRF52_SPI_MASTER_WORKAROUND_1BYTE_TRANSFER if (nwords <= 1) @@ -966,11 +1079,6 @@ static void nrf52_spi_exchange(FAR struct spi_dev_s *dev, regval = (uint32_t)rxbuffer; nrf52_spi_putreg(priv, NRF52_SPIM_RXDPTR_OFFSET, regval); - - /* Write number of bytes in RXD buffer */ - - regval = nwords; - nrf52_spi_putreg(priv, NRF52_SPIM_RXDMAXCNT_OFFSET, regval); } else { @@ -983,51 +1091,86 @@ static void nrf52_spi_exchange(FAR struct spi_dev_s *dev, regval = (uint32_t)txbuffer; nrf52_spi_putreg(priv, NRF52_SPIM_TXDPTR_OFFSET, regval); - - /* Write number of bytes in TXD buffer */ - - regval = nwords; - nrf52_spi_putreg(priv, NRF52_SPIM_TXDMAXCNT_OFFSET, regval); } else { nrf52_spi_putreg(priv, NRF52_SPIM_TXDMAXCNT_OFFSET, 0); } - /* SPI start */ + /* If more than 255 bytes, enable list mode to send data + * in batches + */ - nrf52_spi_putreg(priv, NRF52_SPIM_TASK_START_OFFSET, SPIM_TASKS_START); - -#ifndef CONFIG_NRF52_SPI_MASTER_INTERRUPTS - /* Wait for RX done and TX done */ - - while (nrf52_spi_getreg(priv, NRF52_SPIM_EVENTS_END_OFFSET) != 1); - - /* Clear event */ - - nrf52_spi_putreg(priv, NRF52_SPIM_EVENTS_END_OFFSET, 0); -#else - /* Wait for transfer complete */ - - nxsem_wait(&priv->sem_isr); -#endif - - if (nrf52_spi_getreg(priv, NRF52_SPIM_TXDAMOUNT_OFFSET) != nwords) + if (nwords > 0xff) { - spierr("Incomplete transfer wrote %d expected %d\n", regval, nwords); + if (rxbuffer != NULL) + { + nrf52_spi_putreg(priv, NRF52_SPIM_RXDLIST_OFFSET, 1); + } + + if (txbuffer != NULL) + { + nrf52_spi_putreg(priv, NRF52_SPIM_TXDLIST_OFFSET, 1); + } } - /* SPI stop */ + while (nwords_left > 0) + { + size_t transfer_size = (nwords_left > 255 ? 255 : nwords_left); - nrf52_spi_putreg(priv, NRF52_SPIM_TASK_STOP_OFFSET, SPIM_TASKS_STOP); + if (rxbuffer != NULL) + { + /* Write number of bytes in RXD buffer */ - /* Wait for STOP event */ + nrf52_spi_putreg(priv, NRF52_SPIM_RXDMAXCNT_OFFSET, transfer_size); + } - while (nrf52_spi_getreg(priv, NRF52_SPIM_EVENTS_STOPPED_OFFSET) != 1); + if (txbuffer != NULL) + { + /* Write number of bytes in TXD buffer */ - /* Clear event */ + nrf52_spi_putreg(priv, NRF52_SPIM_TXDMAXCNT_OFFSET, transfer_size); + } - nrf52_spi_putreg(priv, NRF52_SPIM_EVENTS_STOPPED_OFFSET, 0); + /* SPI start */ + + nrf52_spi_putreg(priv, NRF52_SPIM_TASK_START_OFFSET, SPIM_TASKS_START); + +#ifndef CONFIG_NRF52_SPI_MASTER_INTERRUPTS + /* Wait for RX done and TX done */ + + while (nrf52_spi_getreg(priv, NRF52_SPIM_EVENTS_END_OFFSET) != 1); + + /* Clear event */ + + nrf52_spi_putreg(priv, NRF52_SPIM_EVENTS_END_OFFSET, 0); +#else + /* Wait for transfer complete */ + + nxsem_wait_uninterruptible(&priv->sem_isr); +#endif + + if (nrf52_spi_getreg(priv, NRF52_SPIM_TXDAMOUNT_OFFSET) != + transfer_size) + { + spierr("Incomplete transfer wrote %d expected %d\n", + regval, nwords); + } + + /* SPI stop */ + + nrf52_spi_putreg(priv, NRF52_SPIM_TASK_STOP_OFFSET, SPIM_TASKS_STOP); + + /* Wait for STOP event */ + + while (nrf52_spi_getreg(priv, NRF52_SPIM_EVENTS_STOPPED_OFFSET) != 1); + + /* Clear event */ + + nrf52_spi_putreg(priv, NRF52_SPIM_EVENTS_STOPPED_OFFSET, 0); + + nwords_left -= transfer_size; + } /* Clear RX/TX DMA after transfer */ @@ -1036,6 +1179,14 @@ static void nrf52_spi_exchange(FAR struct spi_dev_s *dev, nrf52_spi_putreg(priv, NRF52_SPIM_TXDPTR_OFFSET, 0); nrf52_spi_putreg(priv, NRF52_SPIM_TXDMAXCNT_OFFSET, 0); + /* Clear list mode */ + + if (nwords > 0xff) + { + nrf52_spi_putreg(priv, NRF52_SPIM_RXDLIST_OFFSET, 0); + nrf52_spi_putreg(priv, NRF52_SPIM_TXDLIST_OFFSET, 0); + } + #ifdef CONFIG_NRF52_SPI_MASTER_WORKAROUND_1BYTE_TRANSFER if (nwords <= 1) { @@ -1122,6 +1273,126 @@ static int nrf52_spi_trigger(FAR struct spi_dev_s *dev) } #endif +#ifdef CONFIG_PM +/**************************************************************************** + * Name: nrf52_spi_pm_prepare + ****************************************************************************/ + +static int nrf52_spi_pm_prepare(FAR struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + if (pmstate == PM_STANDBY || pmstate == PM_SLEEP) + { + bool active = false; + +#ifdef CONFIG_NRF52_SPI0_MASTER + active |= nrf52_spi_getreg(&g_spi0dev, SPIM_EVENTS_STARTED); +#endif +#ifdef CONFIG_NRF52_SPI1_MASTER + active |= nrf52_spi_getreg(&g_spi0dev, SPIM_EVENTS_STARTED); +#endif +#ifdef CONFIG_NRF52_SPI2_MASTER + active |= nrf52_spi_getreg(&g_spi0dev, SPIM_EVENTS_STARTED); +#endif +#ifdef CONFIG_NRF52_SPI3_MASTER + active |= nrf52_spi_getreg(&g_spi0dev, SPIM_EVENTS_STARTED); +#endif + + if (active) + { + /* SPI is being used, cannot disable */ + + return -1; + } + else + { + /* SPI is inactive, can go to sleep */ + + return 0; + } + } + else + { + /* We can always go to any other state */ + + return 0; + } +} + +/**************************************************************************** + * Name: nrf52_spi_pm_notify + ****************************************************************************/ + +static void nrf52_spi_pm_notify(FAR struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + if (pmstate == PM_SLEEP || pmstate == PM_STANDBY) + { + /* Deinit SPI peripheral on each initialized device */ + +#ifdef CONFIG_NRF52_SPI0_MASTER + if (g_spi0dev.initialized) + { + nrf52_spi_deinit(&g_spi0dev); + } +#endif + +#ifdef CONFIG_NRF52_SPI1_MASTER + if (g_spi1dev.initialized) + { + nrf52_spi_deinit(&g_spi1dev); + } +#endif + +#ifdef CONFIG_NRF52_SPI2_MASTER + if (g_spi2dev.initialized) + { + nrf52_spi_deinit(&g_spi2dev); + } +#endif + +#ifdef CONFIG_NRF52_SPI3_MASTER + if (g_spi3dev.initialized) + { + nrf52_spi_deinit(&g_spi3dev); + } +#endif + } + else + { + /* Reinit SPI peripheral on each initialized device */ + +#ifdef CONFIG_NRF52_SPI0_MASTER + if (g_spi0dev.initialized) + { + nrf52_spi_init(&g_spi0dev); + } +#endif + +#ifdef CONFIG_NRF52_SPI1_MASTER + if (g_spi1dev.initialized) + { + nrf52_spi_init(&g_spi1dev); + } +#endif + +#ifdef CONFIG_NRF52_SPI2_MASTER + if (g_spi2dev.initialized) + { + nrf52_spi_init(&g_spi2dev); + } +#endif + +#ifdef CONFIG_NRF52_SPI3_MASTER + if (g_spi3dev.initialized) + { + nrf52_spi_init(&g_spi3dev); + } +#endif + } +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -1190,6 +1461,10 @@ FAR struct spi_dev_s *nrf52_spibus_initialize(int port) nrf52_spi_init(priv); + /* Mark device as initialized */ + + priv->initialized = true; + /* Initialize the SPI semaphore */ nxsem_init(&priv->exclsem, 0, 1); diff --git a/arch/arm/src/nuc1xx/nuc_serial.c b/arch/arm/src/nuc1xx/nuc_serial.c index f1c8c06b09b..f59dc818761 100644 --- a/arch/arm/src/nuc1xx/nuc_serial.c +++ b/arch/arm/src/nuc1xx/nuc_serial.c @@ -102,7 +102,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -835,7 +835,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct nuc_dev_s *priv = (struct nuc_dev_s *)dev->priv; uint32_t rbr; diff --git a/arch/arm/src/nuc1xx/nuc_start.c b/arch/arm/src/nuc1xx/nuc_start.c index d4c5dfb9392..ffa9ac8ff97 100644 --- a/arch/arm/src/nuc1xx/nuc_start.c +++ b/arch/arm/src/nuc1xx/nuc_start.c @@ -77,7 +77,7 @@ * Public Data ****************************************************************************/ -const uint32_t g_idle_topstack = IDLE_STACK; +const uintptr_t g_idle_topstack = IDLE_STACK; /**************************************************************************** * Private Functions @@ -128,6 +128,7 @@ void __start(void) { *dest++ = 0; } + showprogress('B'); /* Move the initialized data section from his temporary holding spot in @@ -140,6 +141,7 @@ void __start(void) { *dest++ = *src++; } + showprogress('C'); /* Perform early serial initialization */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_serial.c b/arch/arm/src/s32k1xx/s32k1xx_serial.c index 3144d400849..8e6da23dbeb 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_serial.c +++ b/arch/arm/src/s32k1xx/s32k1xx_serial.c @@ -199,7 +199,7 @@ static int s32k1xx_attach(struct uart_dev_s *dev); static void s32k1xx_detach(struct uart_dev_s *dev); static int s32k1xx_interrupt(int irq, void *context, FAR void *arg); static int s32k1xx_ioctl(struct file *filep, int cmd, unsigned long arg); -static int s32k1xx_receive(struct uart_dev_s *dev, uint32_t *status); +static int s32k1xx_receive(struct uart_dev_s *dev, unsigned int *status); static void s32k1xx_rxint(struct uart_dev_s *dev, bool enable); static bool s32k1xx_rxavailable(struct uart_dev_s *dev); static void s32k1xx_send(struct uart_dev_s *dev, int ch); @@ -955,7 +955,7 @@ static int s32k1xx_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int s32k1xx_receive(struct uart_dev_s *dev, uint32_t *status) +static int s32k1xx_receive(struct uart_dev_s *dev, unsigned int *status) { struct s32k1xx_uart_s *priv = (struct s32k1xx_uart_s *)dev->priv; uint32_t rxd; diff --git a/arch/arm/src/sam34/sam_serial.c b/arch/arm/src/sam34/sam_serial.c index 7b60e496d50..9f26b20c532 100644 --- a/arch/arm/src/sam34/sam_serial.c +++ b/arch/arm/src/sam34/sam_serial.c @@ -379,7 +379,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -1192,7 +1192,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; diff --git a/arch/arm/src/sam34/sam_twi.c b/arch/arm/src/sam34/sam_twi.c index f54da620b4c..5c3bfe497fa 100644 --- a/arch/arm/src/sam34/sam_twi.c +++ b/arch/arm/src/sam34/sam_twi.c @@ -141,7 +141,7 @@ struct twi_dev_s /* Low-level helper functions */ -static void twi_takesem(sem_t *sem); +static int twi_takesem(sem_t *sem); #define twi_givesem(sem) (nxsem_post(sem)) #ifdef CONFIG_SAM34_TWI_REGDEBUG @@ -220,7 +220,8 @@ static const struct i2c_ops_s g_twiops = * dev - Instance of the SDIO device driver state structure. * * Returned Value: - * None + * EINVAL - Invalid attempt to get the semaphore + * EINTR - The wait was interrupted by the receipt of a signal. * ****************************************************************************/ diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c index 29dd837061c..fa1bd9e894c 100644 --- a/arch/arm/src/sam34/sam_udp.c +++ b/arch/arm/src/sam34/sam_udp.c @@ -96,6 +96,7 @@ #endif /* Driver Definitions *******************************************************/ + /* Initial interrupt mask: Reset + Suspend + Correct Transfer */ #define SAM_CNTR_SETUP (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM) @@ -133,6 +134,7 @@ #define sam_rqpeek(q) ((q)->head) /* USB trace ****************************************************************/ + /* Trace error codes */ #define SAM_TRACEERR_ALLOCFAIL 0x0001 @@ -223,17 +225,21 @@ /**************************************************************************** * Private Type Definitions ****************************************************************************/ + /* State of an endpoint */ enum sam_epstate_e { - /* --- All Endpoints --- */ + /* --- All Endpoints --- */ + UDP_EPSTATE_DISABLED = 0, /* Endpoint is disabled */ UDP_EPSTATE_STALLED, /* Endpoint is stalled */ UDP_EPSTATE_IDLE, /* Endpoint is idle (i.e. ready for transmission) */ UDP_EPSTATE_SENDING, /* Endpoint is sending data */ UDP_EPSTATE_RXSTOPPED, /* OUT endpoint is stopped waiting for a read request */ - /* --- Endpoint 0 Only --- */ + + /* --- Endpoint 0 Only --- */ + UDP_EPSTATE_EP0DATAOUT, /* Endpoint 0 is receiving SETUP OUT data */ UDP_EPSTATE_EP0STATUSIN, /* Endpoint 0 is sending SETUP status */ UDP_EPSTATE_EP0ADDRESS /* Address change is pending completion of status */ @@ -497,7 +503,8 @@ static const struct usb_epdesc_s g_ep0desc = .type = USB_DESC_TYPE_ENDPOINT, .addr = EP0, .attr = USB_EP_ATTR_XFER_CONTROL, - .mxpacketsize = {64, 0}, + .mxpacketsize = + {64, 0}, .interval = 0 }; @@ -595,6 +602,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = /**************************************************************************** * Register Operations ****************************************************************************/ + /**************************************************************************** * Name: sam_printreg * @@ -627,7 +635,8 @@ static void sam_checkreg(uintptr_t regaddr, uint32_t regval, bool iswrite) static uint32_t count = 0; static bool prevwrite = false; - /* Is this the same value that we read from/wrote to the same register last time? + /* Is this the same value that we read from/wrote to the same register + * last time? * Are we polling the register? If so, suppress the output. */ @@ -722,7 +731,7 @@ static void sam_putreg(uint32_t regval, uintptr_t regaddr) putreg32(regval, regaddr); } #else -static inline void sam_putreg(uint32_t regval, uint32_t regaddr) +static inline void sam_putreg(uint32_t regval, uintptr_t regaddr) { putreg32(regval, regaddr); } @@ -752,6 +761,7 @@ static void sam_dumpep(struct sam_usbdev_s *priv, uint8_t epno) /**************************************************************************** * Request Helpers ****************************************************************************/ + /**************************************************************************** * Name: sam_req_dequeue ****************************************************************************/ @@ -778,7 +788,8 @@ static struct sam_req_s *sam_req_dequeue(struct sam_rqhead_s *queue) * Name: sam_req_enqueue ****************************************************************************/ -static void sam_req_enqueue(struct sam_rqhead_s *queue, struct sam_req_s *req) +static void sam_req_enqueue(struct sam_rqhead_s *queue, + struct sam_req_s *req) { req->flink = NULL; if (!queue->head) @@ -907,10 +918,10 @@ static void sam_req_wrsetup(struct sam_usbdev_s *priv, * * Description: * Process the next queued write request. This function is called in one - * of three contexts: (1) When the endpoint is IDLE and a new write request - * is submitted (with interrupts disabled), (2) from TXCOMP interrupt - * handling when the current FIFO Tx transfer completes, or (3) when resuming - * a stalled IN or control endpoint. + * of three contexts: (1) When the endpoint is IDLE and a new write + * request is submitted (with interrupts disabled), (2) from TXCOMP + * interrupt handling when the current FIFO Tx transfer completes, or + * (3) when resuming a stalled IN or control endpoint. * * Calling rules: * @@ -1017,13 +1028,14 @@ static int sam_req_write(struct sam_usbdev_s *priv, struct sam_ep_s *privep) * this transfer. */ - else if ((privreq->req.len == 0 || privep->zlpneeded) && !privep->zlpsent) + else if ((privreq->req.len == 0 || privep->zlpneeded) && + !privep->zlpsent) { /* If we get here, then we sent the last of the data on the * previous pass and we need to send the zero length packet now. * - * A Zero Length Packet can be sent by setting just the TXPTKRDY flag - * in the UDP_EPTSETSTAx register + * A Zero Length Packet can be sent by setting just the TXPTKRDY + * flag in the UDP_EPTSETSTAx register */ privep->epstate = UDP_EPSTATE_SENDING; @@ -1032,9 +1044,9 @@ static int sam_req_write(struct sam_usbdev_s *priv, struct sam_ep_s *privep) privreq->inflight = 0; /* Set TXPKTRDY to notify the USB hardware that there is (null) - * TX packet available. We will be notified that the endpoints + * TX packet available. We will be notified that the endpoint's * FIFO has been released by the USB device when TXCOMP in the - * endpoints UDPEP_CSRx register has been set. + * endpoint's UDPEP_CSRx register has been set. */ usbtrace(TRACE_WRITE(epno), 0); @@ -1127,11 +1139,11 @@ static int sam_req_read(struct sam_usbdev_s *priv, struct sam_ep_s *privep, usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_EPOUTQEMPTY), epno); /* Disable further interrupts from this endpoint. The RXDATABK0/1 - * interrupt will pend until either another read request is received - * from the class driver or until the endpoint is reset because of - * no response. Set a flag so that we know that we are in this - * perverse state and can re-enable endpoint interrupts when the - * next read request is received. + * interrupt will pend until either another read request is + * received from the class driver or until the endpoint is reset + * because of no response. Set a flag so that we know that we are + * in this perverse state and can re-enable endpoint interrupts + * when the next read request is received. */ sam_putreg(UDP_INT_EP(epno), SAM_UDP_IDR); @@ -1190,8 +1202,8 @@ static int sam_req_read(struct sam_usbdev_s *priv, struct sam_ep_s *privep, * cannot be cleared until all of the data has been taken from the RX * FIFO. * - * Also, we need to remember which bank we read last so the interrupt handler - * can determine the correct bank read sequence for future reads. + * Also, we need to remember which bank we read last so the interrupt + * handler can determine the correct bank read sequence for future reads. */ privep->lastbank = bank; @@ -1227,6 +1239,7 @@ static void sam_req_cancel(struct sam_ep_s *privep, int16_t result) /**************************************************************************** * Interrupt Level Processing ****************************************************************************/ + /**************************************************************************** * Name: sam_ep0_read * @@ -1271,8 +1284,8 @@ static void sam_ep0_wrstatus(const uint8_t *buffer, size_t buflen) } /* Set TXPKTRDY to notify the USB hardware that there is TX data in the - * endpoint FIFO. We will be notified that the endpoints FIFO has been - * released by the USB device when TXCOMP in the endpoints UDPEP_CSRx + * endpoint FIFO. We will be notified that the endpoint's FIFO has been + * released by the USB device when TXCOMP in the endpoint's UDPEP_CSRx * register has been set. */ @@ -1456,10 +1469,12 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) case USB_REQ_RECIPIENT_ENDPOINT: { epno = USB_EPNO(index.b[LSB]); - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_EPGETSTATUS), epno); + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_EPGETSTATUS), + epno); if (epno >= SAM_UDP_NENDPOINTS) { - usbtrace(TRACE_DEVERROR(SAM_TRACEERR_BADEPGETSTATUS), epno); + usbtrace(TRACE_DEVERROR(SAM_TRACEERR_BADEPGETSTATUS), + epno); ep0result = UDP_EP0SETUP_STALL; } else @@ -1482,18 +1497,21 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) { if (index.w == 0) { - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_DEVGETSTATUS), 0); + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_DEVGETSTATUS), + 0); /* Features: Remote Wakeup=YES; selfpowered=? */ response.w = 0; - response.b[LSB] = (priv->selfpowered << USB_FEATURE_SELFPOWERED) | + response.b[LSB] = (priv->selfpowered << + USB_FEATURE_SELFPOWERED) | (1 << USB_FEATURE_REMOTEWAKEUP); nbytes = 2; /* Response size: 2 bytes */ } else { - usbtrace(TRACE_DEVERROR(SAM_TRACEERR_BADDEVGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(SAM_TRACEERR_BADDEVGETSTATUS), + 0); ep0result = UDP_EP0SETUP_STALL; } } @@ -1526,11 +1544,13 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) * len: zero, data = none */ - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_CLEARFEATURE), priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT) + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_CLEARFEATURE), + priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_ENDPOINT) { - /* Let the class implementation handle all recipients (except for the - * endpoint recipient) + /* Let the class implementation handle all recipients + * (except for the endpoint recipient) */ sam_ep0_dispatch(priv); @@ -1569,17 +1589,22 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_SETFEATURE), priv->ctrl.type); - if (((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) && + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_SETFEATURE), + priv->ctrl.type); + if (((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) && value.w == USB_FEATURE_TESTMODE) { /* Special case recipient=device test mode */ uinfo("test mode: %d\n", index.w); } - else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT) + else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_ENDPOINT) { - /* The class driver handles all recipients except recipient=endpoint */ + /* The class driver handles all recipients except + * recipient=endpoint + */ sam_ep0_dispatch(priv); ep0result = UDP_EP0SETUP_DISPATCHED; @@ -1617,7 +1642,8 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) * len: 0; data = none */ - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_DEVICE || + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_DEVICE || index.w != 0 || len.w != 0 || value.w > 127) { usbtrace(TRACE_DEVERROR(SAM_TRACEERR_BADSETADDRESS), 0); @@ -1630,7 +1656,8 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) * be set when the zero-length packet transfer completes. */ - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_EP0SETUPSETADDRESS), value.w); + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_EP0SETUPSETADDRESS), + value.w); priv->devaddr = value.w; ep0result = UDP_EP0SETUP_ADDRESS; } @@ -1643,6 +1670,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) * index: 0 or language ID; * len: descriptor len; data = descriptor */ + case USB_REQ_SETDESCRIPTOR: /* type: host-to-device; recipient = device * value: descriptor type and index @@ -1651,10 +1679,14 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_GETSETDESC), priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_GETSETDESC), + priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) { - /* The request seems valid... let the class implementation handle it */ + /* The request seems valid... let the class implementation handle + * it + */ sam_ep0_dispatch(priv); ep0result = UDP_EP0SETUP_DISPATCHED; @@ -1675,11 +1707,15 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_GETCONFIG), priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_GETCONFIG), + priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && value.w == 0 && index.w == 0 && len.w == 1) { - /* The request seems valid... let the class implementation handle it */ + /* The request seems valid... let the class implementation handle + * it + */ sam_ep0_dispatch(priv); ep0result = UDP_EP0SETUP_DISPATCHED; @@ -1701,12 +1737,14 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) { usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_SETCONFIG), priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && index.w == 0 && len.w == 0) { - /* The request seems valid... let the class implementation handle it. - * If the class implementation accepts it new configuration, it will - * call sam_ep_configure() to configure the endpoints. + /* The request seems valid... let the class implementation + * handle it. + * If the class implementation accepts it new configuration, it + * will call sam_ep_configure() to configure the endpoints. */ sam_ep0_dispatch(priv); @@ -1726,6 +1764,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) * index: interface; * len: 1; data = alt interface */ + case USB_REQ_SETINTERFACE: /* type: host-to-device; recipient = interface * value: alternate setting @@ -1756,7 +1795,8 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) default: { - usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDCTRLREQ), priv->ctrl.req); + usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDCTRLREQ), + priv->ctrl.req); ep0result = UDP_EP0SETUP_STALL; } break; @@ -1943,7 +1983,8 @@ static void sam_ep_bankinterrupt(struct sam_usbdev_s *priv, else { usbtrace(TRACE_DEVERROR(SAM_TRACEERR_RXDATABKERR), privep->epstate); - sam_csr_clrbits(epno, bank ? UDPEP_CSR_RXDATABK1 : UDPEP_CSR_RXDATABK0); + sam_csr_clrbits(epno, + bank ? UDPEP_CSR_RXDATABK1 : UDPEP_CSR_RXDATABK0); } } @@ -2023,7 +2064,6 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno) } } - /* OUT packet received. * * OUT packets are received in two banks. The hardware does not provide @@ -2061,7 +2101,7 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno) sam_ep_bankinterrupt(priv, privep, csr, 0); } - /* 3. and 7. - Only read bank 1*/ + /* 3. and 7. - Only read bank 1 */ else if (!bk0 && bk1) { @@ -2121,7 +2161,8 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno) /* ISO error */ - if (eptype == UDPEP_CSR_EPTYPE_ISOIN || eptype == UDPEP_CSR_EPTYPE_ISOOUT) + if (eptype == UDPEP_CSR_EPTYPE_ISOIN || + eptype == UDPEP_CSR_EPTYPE_ISOOUT) { privep->epstate = UDP_EPSTATE_IDLE; sam_req_complete(privep, -EIO); @@ -2165,23 +2206,24 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno) * before processing the SETUP command. */ - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_EP0SETUPOUT), priv->ctrl.req); + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_EP0SETUPOUT), + priv->ctrl.req); privep->epstate = UDP_EPSTATE_EP0DATAOUT; /* Clear the CSR:DIR bit to support the host-to-device data OUT * data transfer. This bit must be cleared before CSR:RXSETUP is * cleared at the end of the SETUP stage. * - * NOTE: Clearing this bit seems to be unnecessary. I think it must - * be cleared when RXSETUP is set. + * NOTE: Clearing this bit seems to be unnecessary. I think it + * must be cleared when RXSETUP is set. */ sam_csr_clrbits(epno, UDPEP_CSR_DIR); - /* Clear the RXSETUP indication. RXSETUP cannot be cleared before the - * SETUP packet has been read in from the FIFO. Otherwise, the USB - * device would accept the next Data OUT transfer and overwrite the - * SETUP packet in the FIFO. + /* Clear the RXSETUP indication. RXSETUP cannot be cleared before + * the SETUP packet has been read in from the FIFO. Otherwise, + * the USB device would accept the next Data OUT transfer and + * overwrite the SETUP packet in the FIFO. */ sam_csr_clrbits(epno, UDPEP_CSR_RXSETUP); @@ -2327,8 +2369,8 @@ static int sam_udp_interrupt(int irq, void *context, FAR void *arg) * * In this state UDPCK and MCK must be enabled. * - * Warning: Each time an ENDBUSRES interrupt is triggered, the Interrupt - * Mask Register and UDPEP_CSR registers have been reset. + * Warning: Each time an ENDBUSRES interrupt is triggered, the + * Interrupt Mask Register and UDPEP_CSR registers have been reset. */ if ((pending & UDP_ISR_ENDBUSRES) != 0) @@ -2447,6 +2489,7 @@ static void sam_csr_clrbits(uint8_t epno, uint32_t clrbits) /**************************************************************************** * Suspend/Resume Helpers ****************************************************************************/ + /**************************************************************************** * Name: sam_suspend ****************************************************************************/ @@ -2488,9 +2531,9 @@ static void sam_suspend(struct sam_usbdev_s *priv) static void sam_resume(struct sam_usbdev_s *priv) { - /* This function is called when either (1) a WKUP interrupt is received from - * the host PC, or (2) the class device implementation calls the wakeup() - * method. + /* This function is called when either (1) a WKUP interrupt is received + * from the host PC, or (2) the class device implementation calls the + * wakeup() method. */ /* Don't do anything if the device was not suspended */ @@ -2505,7 +2548,9 @@ static void sam_resume(struct sam_usbdev_s *priv) sam_enableclks(); - /* Restore full power -- whatever that means for this particular board */ + /* Restore full power -- whatever that means for this particular + * board + */ sam_udp_suspend((struct usbdev_s *)priv, true); @@ -2675,13 +2720,14 @@ static int sam_ep_resume(struct sam_ep_s *privep) sam_putreg(UDP_RSTEP(epno), SAM_UDP_RSTEP); - /* We need to add a delay between setting and clearing the endpoint reset - * bit in SAM_UDP_RSTEP. Without the delay the USB controller will (may?) - * not reset the endpoint. + /* We need to add a delay between setting and clearing the endpoint + * reset bit in SAM_UDP_RSTEP. Without the delay the USB controller + * will (may?) not reset the endpoint. * * If the endpoint is not being reset, the Data Toggle (DTGLE) bit will * not to be cleared which will cause the next transaction to fail if - * DTGLE is 1. If that happens the host will time-out and reset the bus. + * DTGLE is 1. If that happens the host will time-out and reset the + * bus. * * Adding this delay may also fix the USBMSC_STALL_RACEWAR in * usbmsc_scsi.c, however this has not been verified yet. @@ -2690,7 +2736,6 @@ static int sam_ep_resume(struct sam_ep_s *privep) up_udelay(10); sam_putreg(0, SAM_UDP_RSTEP); - /* Copy any requests in the pending request queue to the working * request queue. */ @@ -2834,6 +2879,7 @@ static int sam_ep_configure_internal(struct sam_ep_s *privep, privep->epstate = UDP_EPSTATE_IDLE; /* Initialize the endpoint hardware */ + /* Disable the endpoint */ csr = SAM_UDPEP_CSR(epno); @@ -2937,6 +2983,7 @@ static int sam_ep_configure_internal(struct sam_ep_s *privep, /**************************************************************************** * Endpoint operations ****************************************************************************/ + /**************************************************************************** * Name: sam_ep_configure * @@ -3154,7 +3201,8 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) #ifdef CONFIG_DEBUG_USB if (!priv->driver) { - usbtrace(TRACE_DEVERROR(SAM_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); + usbtrace(TRACE_DEVERROR(SAM_TRACEERR_NOTCONFIGURED), + priv->usbdev.speed); uerr("ERROR: driver=%p\n", priv->driver); return -ESHUTDOWN; } @@ -3333,6 +3381,7 @@ static int sam_ep_stallresume(struct usbdev_ep_s *ep, bool resume) /**************************************************************************** * Device Controller Operations ****************************************************************************/ + /**************************************************************************** * Name: sam_allocep * @@ -3366,8 +3415,9 @@ static struct usbdev_ep_s *sam_allocep(struct usbdev_s *dev, uint8_t epno, if (epno > 0) { - /* Otherwise, we will return the endpoint structure only for the requested - * 'logical' endpoint. All of the other checks will still be performed. + /* Otherwise, we will return the endpoint structure only for the + * requested 'logical' endpoint. All of the other checks will still + * be performed. * * First, verify that the logical endpoint is in the range supported by * by the hardware. @@ -3505,14 +3555,14 @@ static int sam_wakeup(struct usbdev_s *dev) * - "The device must force a K state from 1 to 15 ms to resume the host * * "Before sending a K state to the host, MCK, UDPCK and the transceiver - * must be enabled. Then to enable the remote wake-up feature, the RMWUPE bit - * in the UDP_GLB_STAT register must be enabled. To force the K state on the - * line, a transition of the ESR bit from 0 to 1 has to be done in the - * UDP_GLB_STAT register. This transition must be accomplished by first - * writing a 0 in the ESR bit and then writing a 1. + * must be enabled. Then to enable the remote wake-up feature, the RMWUPE + * bit in the UDP_GLB_STAT register must be enabled. To force the K state + * on the line, a transition of the ESR bit from 0 to 1 has to be done in + * the UDP_GLB_STAT register. This transition must be accomplished by + * first writing a 0 in the ESR bit and then writing a 1. * - * " The K state is automatically generated and released according to the USB - * 2.0 specification." + * " The K state is automatically generated and released according to the + * USB 2.0 specification." */ /* Make sure that the ESR bit is zero */ @@ -3524,7 +3574,7 @@ static int sam_wakeup(struct usbdev_s *dev) /* Wait 5msec in case we just entered the resume state */ - nxsig_usleep(5*1000); + nxsig_usleep(5 * 1000); /* Set the ESR bit to send the remote resume */ @@ -3790,8 +3840,8 @@ static void sam_hw_setup(struct sam_usbdev_s *priv) sam_putreg(UDP_INT_ALL, SAM_UDP_IDR); - /* Disable the 1.5 KOhm integrated pull-up on DDP and make sure that the UDP - * transceiver is not disabled + /* Disable the 1.5 KOhm integrated pull-up on DDP and make sure that the + * UDP transceiver is not disabled */ sam_putreg(0, SAM_UDP_TXVC); @@ -3876,6 +3926,7 @@ static void sam_sw_shutdown(struct sam_usbdev_s *priv) /**************************************************************************** * Public Functions ****************************************************************************/ + /**************************************************************************** * Name: arm_usbinitialize * Description: @@ -3976,8 +4027,8 @@ void arm_usbuninitialize(void) * Name: usbdev_register * * Description: - * Register a USB device class driver. The class driver's bind() method will be - * called to bind it to a USB device driver. + * Register a USB device class driver. The class driver's bind() method + * will be called to bind it to a USB device driver. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_dbgu.c b/arch/arm/src/sama5/sam_dbgu.c index 1116a43ef75..c6ee15cf34f 100644 --- a/arch/arm/src/sama5/sam_dbgu.c +++ b/arch/arm/src/sama5/sam_dbgu.c @@ -92,7 +92,7 @@ static int dbgu_attach(struct uart_dev_s *dev); static void dbgu_detach(struct uart_dev_s *dev); static int dbgu_interrupt(int irq, void *context, FAR void *arg); static int dbgu_ioctl(struct file *filep, int cmd, unsigned long arg); -static int dbgu_receive(struct uart_dev_s *dev, uint32_t *status); +static int dbgu_receive(struct uart_dev_s *dev, unsigned int *status); static void dbgu_rxint(struct uart_dev_s *dev, bool enable); static bool dbgu_rxavailable(struct uart_dev_s *dev); static void dbgu_send(struct uart_dev_s *dev, int ch); @@ -269,14 +269,15 @@ static void dbgu_shutdown(struct uart_dev_s *dev) * Name: dbgu_attach * * Description: - * Configure the DBGU to operation in interrupt driven mode. This method is - * called when the serial port is opened. Normally, this is just after the + * Configure the DBGU to operation in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after * the setup() method is called, however, the serial console may operate in * a non-interrupt driven mode during the boot phase. * - * RX and TX interrupts are not enabled when by the attach method (unless the - * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() methods are called. + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. * ****************************************************************************/ @@ -304,8 +305,8 @@ static int dbgu_attach(struct uart_dev_s *dev) * * Description: * Detach DBGU interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. The exception - * is the serial console which is never shutdown. + * closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. * ****************************************************************************/ @@ -348,14 +349,16 @@ static int dbgu_interrupt(int irq, void *context, FAR void *arg) { handled = false; - /* Get the DBGU/DBGU status (we are only interested in the unmasked interrupts). */ + /* Get the DBGU/DBGU status (we are only interested in the unmasked + * interrupts). + */ priv->sr = getreg32(SAM_DBGU_SR); /* Save for error reporting */ imr = getreg32(SAM_DBGU_IMR); /* Interrupt mask */ pending = priv->sr & imr; /* Mask out disabled interrupt sources */ - /* Handle an incoming, receive byte. RXRDY: At least one complete character - * has been received and US_RHR has not yet been read. + /* Handle an incoming, receive byte. RXRDY: At least one complete + * character has been received and US_RHR has not yet been read. */ if ((pending & DBGU_INT_RXRDY) != 0) @@ -434,7 +437,7 @@ static int dbgu_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int dbgu_receive(struct uart_dev_s *dev, uint32_t *status) +static int dbgu_receive(struct uart_dev_s *dev, unsigned int *status) { struct dbgu_dev_s *priv = (struct dbgu_dev_s *)dev->priv; @@ -460,8 +463,8 @@ static void dbgu_rxint(struct uart_dev_s *dev, bool enable) { if (enable) { - /* Receive an interrupt when their is anything in the Rx data register (or an Rx - * timeout occurs). + /* Receive an interrupt when their is anything in the Rx data register + * (or an Rx timeout occurs). */ #ifndef CONFIG_SUPPRESS_SERIAL_INTS diff --git a/arch/arm/src/sama5/sam_sdmmc.c b/arch/arm/src/sama5/sam_sdmmc.c index 842c1f70c1a..a0a8b86753f 100644 --- a/arch/arm/src/sama5/sam_sdmmc.c +++ b/arch/arm/src/sama5/sam_sdmmc.c @@ -328,7 +328,7 @@ static void sam_blocksetup(FAR struct sdio_dev_s *dev, static int sam_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, size_t nbytes); static int sam_sendsetup(FAR struct sdio_dev_s *dev, - FAR const uint8_t *buffer, uint32_t nbytes); + FAR const uint8_t *buffer, size_t nbytes); #endif static int sam_cancel(FAR struct sdio_dev_s *dev); diff --git a/arch/arm/src/sama5/sam_serial.c b/arch/arm/src/sama5/sam_serial.c index d553dd00fc7..4380b58ab6e 100644 --- a/arch/arm/src/sama5/sam_serial.c +++ b/arch/arm/src/sama5/sam_serial.c @@ -442,7 +442,7 @@ static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -1441,7 +1441,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; diff --git a/arch/arm/src/sama5/sam_udphs.c b/arch/arm/src/sama5/sam_udphs.c index f416030587a..fedcd0b6559 100644 --- a/arch/arm/src/sama5/sam_udphs.c +++ b/arch/arm/src/sama5/sam_udphs.c @@ -99,6 +99,7 @@ #undef CONFIG_SAMA5_UDPHS_SCATTERGATHER /* Driver Definitions *******************************************************/ + /* Initial interrupt mask: Reset + Suspend + Correct Transfer */ #define SAM_CNTR_SETUP (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM) @@ -134,6 +135,7 @@ #define sam_rqpeek(q) ((q)->head) /* USB trace ****************************************************************/ + /* Trace error codes */ #define SAM_TRACEERR_ALLOCFAIL 0x0001 @@ -227,17 +229,21 @@ /**************************************************************************** * Private Type Definitions ****************************************************************************/ + /* State of an endpoint */ enum sam_epstate_e { - /* --- All Endpoints --- */ + /* --- All Endpoints --- */ + UDPHS_EPSTATE_DISABLED = 0, /* Endpoint is disabled */ UDPHS_EPSTATE_STALLED, /* Endpoint is stalled */ UDPHS_EPSTATE_IDLE, /* Endpoint is idle (i.e. ready for transmission) */ UDPHS_EPSTATE_SENDING, /* Endpoint is sending data */ UDPHS_EPSTATE_RECEIVING, /* Endpoint is receiving data */ - /* --- Endpoint 0 Only --- */ + + /* --- Endpoint 0 Only --- */ + UDPHS_EPSTATE_EP0DATAOUT, /* Endpoint 0 is receiving SETUP OUT data */ UDPHS_EPSTATE_EP0STATUSIN, /* Endpoint 0 is sending SETUP status */ UDPHS_EPSTATE_EP0ADDRESS /* Address change is pending completion of status */ @@ -544,7 +550,8 @@ static const struct usb_epdesc_s g_ep0desc = .type = USB_DESC_TYPE_ENDPOINT, .addr = EP0, .attr = USB_EP_ATTR_XFER_CONTROL, - .mxpacketsize = {64, 0}, + .mxpacketsize = + {64, 0}, .interval = 0 }; @@ -557,7 +564,6 @@ static struct sam_dtd_s g_dtdpool[CONFIG_SAMA5_UDPHS_NDTDS] #endif #endif - /* Device error strings that may be enabled for more descriptive USB trace * output. */ @@ -655,6 +661,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = /**************************************************************************** * Register Operations ****************************************************************************/ + /**************************************************************************** * Name: sam_printreg * @@ -687,7 +694,8 @@ static void sam_checkreg(uintptr_t regaddr, uint32_t regval, bool iswrite) static uint32_t count = 0; static bool prevwrite = false; - /* Is this the same value that we read from/wrote to the same register last time? + /* Is this the same value that we read from/wrote to the same register + * last time? * Are we polling the register? If so, suppress the output. */ @@ -782,7 +790,7 @@ static void sam_putreg(uint32_t regval, uintptr_t regaddr) putreg32(regval, regaddr); } #else -static inline void sam_putreg(uint32_t regval, uint32_t regaddr) +static inline void sam_putreg(uint32_t regval, uintptr_t regaddr) { putreg32(regval, regaddr); } @@ -829,6 +837,7 @@ static void sam_dumpep(struct sam_usbdev_s *priv, int epno) /**************************************************************************** * DMA ****************************************************************************/ + /**************************************************************************** * Name: sam_dtd_alloc * @@ -933,8 +942,9 @@ static void sam_dma_single(uint8_t epno, struct sam_req_s *privreq, * ****************************************************************************/ -static void sam_dma_wrsetup(struct sam_usbdev_s *priv, struct sam_ep_s *privep, - struct sam_req_s *privreq) +static void sam_dma_wrsetup(struct sam_usbdev_s *priv, + struct sam_ep_s *privep, + struct sam_req_s *privreq) { uint32_t regval; int remaining; @@ -1068,6 +1078,7 @@ static void sam_dma_rdsetup(struct sam_usbdev_s *priv, /**************************************************************************** * Request Helpers ****************************************************************************/ + /**************************************************************************** * Name: sam_req_dequeue ****************************************************************************/ @@ -1094,7 +1105,8 @@ static struct sam_req_s *sam_req_dequeue(struct sam_rqhead_s *queue) * Name: sam_req_enqueue ****************************************************************************/ -static void sam_req_enqueue(struct sam_rqhead_s *queue, struct sam_req_s *req) +static void sam_req_enqueue(struct sam_rqhead_s *queue, + struct sam_req_s *req) { req->flink = NULL; if (!queue->head) @@ -1114,7 +1126,8 @@ static void sam_req_enqueue(struct sam_rqhead_s *queue, struct sam_req_s *req) ****************************************************************************/ static inline void -sam_req_abort(struct sam_ep_s *privep, struct sam_req_s *privreq, int16_t result) +sam_req_abort(struct sam_ep_s *privep, struct sam_req_s *privreq, + int16_t result) { usbtrace(TRACE_DEVERROR(SAM_TRACEERR_REQABORTED), (uint16_t)USB_EPNO(privep->ep.eplog)); @@ -1216,7 +1229,8 @@ static void sam_req_wrsetup(struct sam_usbdev_s *priv, /* Write access to the FIFO is not possible if TXDRY is set */ - DEBUGASSERT((sam_getreg(SAM_UDPHS_EPTSTA(epno)) & UDPHS_EPTSTA_TXRDY) == 0); + DEBUGASSERT((sam_getreg(SAM_UDPHS_EPTSTA(epno)) & UDPHS_EPTSTA_TXRDY) + == 0); /* Get the number of bytes remaining to be sent. */ @@ -1282,10 +1296,10 @@ static void sam_req_wrsetup(struct sam_usbdev_s *priv, * * Description: * Process the next queued write request. This function is called in one - * of three contexts: (1) When the endpoint is IDLE and a new write request - * is submitted (with interrupts disabled), (2) from interrupt handling - * when the current transfer completes (either DMA or FIFO), or (3) when - * resuming a stalled IN or control endpoint. + * of three contexts: (1) When the endpoint is IDLE and a new write + * request is submitted (with interrupts disabled), (2) from interrupt + * handling when the current transfer completes (either DMA or FIFO), + * or (3) when resuming a stalled IN or control endpoint. * * Calling rules: * @@ -1391,7 +1405,8 @@ static int sam_req_write(struct sam_usbdev_s *priv, struct sam_ep_s *privep) * this transfer. */ - else if ((privreq->req.len == 0 || privep->zlpneeded) && !privep->zlpsent) + else if ((privreq->req.len == 0 || privep->zlpneeded) && + !privep->zlpsent) { /* If we get here, then we sent the last of the data on the * previous pass and we need to send the zero length packet now. @@ -1615,7 +1630,9 @@ static int sam_req_read(struct sam_usbdev_s *priv, struct sam_ep_s *privep, privreq->req.xfrd += recvsize; privreq->inflight = 0; - /* If this was not a DMA transfer, read the incoming data from the FIFO */ + /* If this was not a DMA transfer, read the incoming data from the + * FIFO + */ if ((SAM_EPSET_DMA & SAM_EP_BIT(epno)) == 0) { @@ -1720,6 +1737,7 @@ static void sam_req_cancel(struct sam_ep_s *privep, int16_t result) /**************************************************************************** * Interrupt Level Processing ****************************************************************************/ + /**************************************************************************** * Name: sam_ep0_read * @@ -1924,10 +1942,12 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) case USB_REQ_RECIPIENT_ENDPOINT: { epno = USB_EPNO(index.b[LSB]); - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_EPGETSTATUS), epno); + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_EPGETSTATUS), + epno); if (epno >= SAM_UDPHS_NENDPOINTS) { - usbtrace(TRACE_DEVERROR(SAM_TRACEERR_BADEPGETSTATUS), epno); + usbtrace(TRACE_DEVERROR(SAM_TRACEERR_BADEPGETSTATUS), + epno); ep0result = UDPHS_EP0SETUP_STALL; } else @@ -1950,18 +1970,21 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) { if (index.w == 0) { - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_DEVGETSTATUS), 0); + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_DEVGETSTATUS), + 0); /* Features: Remote Wakeup=YES; selfpowered=? */ response.w = 0; - response.b[LSB] = (priv->selfpowered << USB_FEATURE_SELFPOWERED) | + response.b[LSB] = (priv->selfpowered << + USB_FEATURE_SELFPOWERED) | (1 << USB_FEATURE_REMOTEWAKEUP); nbytes = 2; /* Response size: 2 bytes */ } else { - usbtrace(TRACE_DEVERROR(SAM_TRACEERR_BADDEVGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(SAM_TRACEERR_BADDEVGETSTATUS), + 0); ep0result = UDPHS_EP0SETUP_STALL; } } @@ -1994,11 +2017,13 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) * len: zero, data = none */ - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_CLEARFEATURE), priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT) + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_CLEARFEATURE), + priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_ENDPOINT) { - /* Let the class implementation handle all recipients (except for the - * endpoint recipient) + /* Let the class implementation handle all recipients + * (except for the endpoint recipient) */ sam_ep0_dispatch(priv); @@ -2038,17 +2063,22 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_SETFEATURE), priv->ctrl.type); - if (((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) && + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_SETFEATURE), + priv->ctrl.type); + if (((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) && value.w == USB_FEATURE_TESTMODE) { /* Special case recipient=device test mode */ uinfo("test mode: %d\n", index.w); } - else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT) + else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_ENDPOINT) { - /* The class driver handles all recipients except recipient=endpoint */ + /* The class driver handles all recipients except + * recipient=endpoint + */ sam_ep0_dispatch(priv); ep0result = UDPHS_EP0SETUP_DISPATCHED; @@ -2087,7 +2117,8 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) * len: 0; data = none */ - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_DEVICE || + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_DEVICE || index.w != 0 || len.w != 0 || value.w > 127) { usbtrace(TRACE_DEVERROR(SAM_TRACEERR_BADSETADDRESS), 0); @@ -2100,7 +2131,8 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) * be set when the zero-length packet transfer completes. */ - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_EP0SETUPSETADDRESS), value.w); + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_EP0SETUPSETADDRESS), + value.w); priv->devaddr = value.w; ep0result = UDPHS_EP0SETUP_ADDRESS; } @@ -2113,6 +2145,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) * index: 0 or language ID; * len: descriptor len; data = descriptor */ + case USB_REQ_SETDESCRIPTOR: /* type: host-to-device; recipient = device * value: descriptor type and index @@ -2121,10 +2154,14 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_GETSETDESC), priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_GETSETDESC), + priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) { - /* The request seems valid... let the class implementation handle it */ + /* The request seems valid... let the class implementation + * handle it + */ sam_ep0_dispatch(priv); ep0result = UDPHS_EP0SETUP_DISPATCHED; @@ -2146,10 +2183,13 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) { usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_GETCONFIG), priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && value.w == 0 && index.w == 0 && len.w == 1) { - /* The request seems valid... let the class implementation handle it */ + /* The request seems valid... let the class implementation + * handle it + */ sam_ep0_dispatch(priv); ep0result = UDPHS_EP0SETUP_DISPATCHED; @@ -2171,12 +2211,14 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) { usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_SETCONFIG), priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && index.w == 0 && len.w == 0) { - /* The request seems valid... let the class implementation handle it. - * If the class implementation accespts it new configuration, it will - * call sam_ep_configure() to configure the endpoints. + /* The request seems valid... let the class implementation + * handle it. + * If the class implementation accespts it new configuration, + * it will call sam_ep_configure() to configure the endpoints. */ sam_ep0_dispatch(priv); @@ -2196,6 +2238,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) * index: interface; * len: 1; data = alt interface */ + case USB_REQ_SETINTERFACE: /* type: host-to-device; recipient = interface * value: alternate setting @@ -2226,7 +2269,8 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) default: { - usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDCTRLREQ), priv->ctrl.req); + usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDCTRLREQ), + priv->ctrl.req); ep0result = UDPHS_EP0SETUP_STALL; } break; @@ -2618,8 +2662,8 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno) len = GETUINT16(priv->ctrl.len); if (len == pktsize) { - /* Copy the OUT data from the EP0 FIFO into a special EP0 buffer - * and clear RXRDYTXKL in order to receive more data. + /* Copy the OUT data from the EP0 FIFO into a special EP0 + * buffer and clear RXRDYTXKL in order to receive more data. */ sam_ep0_read(priv->ep0out, len); @@ -2631,7 +2675,8 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno) } else { - usbtrace(TRACE_DEVERROR(SAM_TRACEERR_EP0SETUPOUTSIZE), pktsize); + usbtrace(TRACE_DEVERROR(SAM_TRACEERR_EP0SETUPOUTSIZE), + pktsize); /* STALL and discard received data. */ @@ -2663,8 +2708,8 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno) sam_putreg(regval, SAM_UDPHS_IEN); } - /* Discard any received data and clear UDPHS_EPTSTA_RXRDYTXKL so that we - * may receive more data. + /* Discard any received data and clear UDPHS_EPTSTA_RXRDYTXKL + * so that we may receive more data. */ sam_putreg(UDPHS_EPTSTA_RXRDYTXKL, SAM_UDPHS_EPTCLRSTA(epno)); @@ -2705,8 +2750,8 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno) /* If a request transfer was pending, complete it. Handle the case * where during the status phase of a control write transfer, the host - * receives the device ZLP and ack it, but the ack is not received by the - * device + * receives the device ZLP and ack it, but the ack is not received by + * the device */ if (privep->epstate == UDPHS_EPSTATE_RECEIVING || @@ -2744,7 +2789,8 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno) * complete before processing the SETUP command. */ - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_EP0SETUPOUT), priv->ctrl.req); + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_EP0SETUPOUT), + priv->ctrl.req); privep->epstate = UDPHS_EPSTATE_EP0DATAOUT; } else @@ -2772,8 +2818,8 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno) static int sam_udphs_interrupt(int irq, void *context, FAR void *arg) { /* For now there is only one USB controller, but we will always refer to - * it using a pointer to make any future ports to multiple UDPHS controllers - * easier. + * it using a pointer to make any future ports to multiple UDPHS + * controllers easier. */ struct sam_usbdev_s *priv = &g_udphs; @@ -2802,7 +2848,8 @@ static int sam_udphs_interrupt(int irq, void *context, FAR void *arg) if ((pending == UDPHS_INT_DETSUSPD) != 0) { - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_DETSUSPD), (uint16_t)pending); + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_DETSUSPD), + (uint16_t)pending); /* Enable wakeup interrupts */ @@ -2813,7 +2860,8 @@ static int sam_udphs_interrupt(int irq, void *context, FAR void *arg) /* Acknowledge interrupt */ - sam_putreg(UDPHS_INT_DETSUSPD | UDPHS_INT_WAKEUP, SAM_UDPHS_CLRINT); + sam_putreg(UDPHS_INT_DETSUSPD | UDPHS_INT_WAKEUP, + SAM_UDPHS_CLRINT); sam_suspend(priv); } @@ -2823,7 +2871,8 @@ static int sam_udphs_interrupt(int irq, void *context, FAR void *arg) { /* Acknowledge interrupt */ - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_INTSOF), (uint16_t)pending); + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_INTSOF), + (uint16_t)pending); sam_putreg(UDPHS_INT_INTSOF, SAM_UDPHS_CLRINT); } @@ -2832,12 +2881,14 @@ static int sam_udphs_interrupt(int irq, void *context, FAR void *arg) else if ((pending & UDPHS_INT_WAKEUP) != 0 || (pending & UDPHS_INT_ENDOFRSM) != 0) { - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_WAKEUP), (uint16_t)pending); + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_WAKEUP), + (uint16_t)pending); sam_resume(priv); /* Acknowledge interrupt */ - sam_putreg(UDPHS_INT_WAKEUP | UDPHS_INT_ENDOFRSM | UDPHS_INT_DETSUSPD, + sam_putreg(UDPHS_INT_WAKEUP | UDPHS_INT_ENDOFRSM | + UDPHS_INT_DETSUSPD, SAM_UDPHS_CLRINT); /* Enable suspend interrupts */ @@ -2888,7 +2939,8 @@ static int sam_udphs_interrupt(int irq, void *context, FAR void *arg) if ((pending & UDPHS_INT_ENDRESET) != 0) { - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_ENDRESET), (uint16_t)pending); + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_ENDRESET), + (uint16_t)pending); /* Handle the reset */ @@ -2912,7 +2964,8 @@ static int sam_udphs_interrupt(int irq, void *context, FAR void *arg) { /* Acknowledge interrupt */ - usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_UPSTRRES), (uint16_t)pending); + usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_UPSTRRES), + (uint16_t)pending); sam_putreg(UDPHS_INT_UPSTRRES, SAM_UDPHS_CLRINT); } @@ -2958,6 +3011,7 @@ static int sam_udphs_interrupt(int irq, void *context, FAR void *arg) /**************************************************************************** * Suspend/Resume Helpers ****************************************************************************/ + /**************************************************************************** * Name: sam_suspend ****************************************************************************/ @@ -3004,9 +3058,9 @@ static void sam_suspend(struct sam_usbdev_s *priv) static void sam_resume(struct sam_usbdev_s *priv) { - /* This function is called when either (1) a WKUP interrupt is received from - * the host PC, or (2) the class device implementation calls the wakeup() - * method. + /* This function is called when either (1) a WKUP interrupt is received + * from the host PC, or (2) the class device implementation calls the + * wakeup() method. */ /* Don't do anything if the device was not suspended */ @@ -3027,7 +3081,9 @@ static void sam_resume(struct sam_usbdev_s *priv) priv->devstate = priv->prevstate; - /* Restore full power -- whatever that means for this particular board */ + /* Restore full power -- whatever that means for this particular + * board + */ sam_usbsuspend((struct usbdev_s *)priv, true); @@ -3225,7 +3281,8 @@ static int sam_ep_configure_internal(struct sam_ep_s *privep, epno = USB_EPNO(desc->addr); dirin = (desc->addr & USB_DIR_MASK) == USB_REQ_DIR_IN; - eptype = (desc->attr & USB_EP_ATTR_XFERTYPE_MASK) >> USB_EP_ATTR_XFERTYPE_SHIFT; + eptype = (desc->attr & USB_EP_ATTR_XFERTYPE_MASK) >> + USB_EP_ATTR_XFERTYPE_SHIFT; maxpacket = GETUINT16(desc->mxpacketsize); nbtrans = 1; @@ -3235,6 +3292,7 @@ static int sam_ep_configure_internal(struct sam_ep_s *privep, if (priv->usbdev.speed == USB_SPEED_HIGH) { /* HS Interval, 125us */ + /* MPS: Bits 12:11 specify NB_TRANS, as USB 2.0 Spec. */ nbtrans = ((maxpacket >> 11) & 3); @@ -3252,14 +3310,15 @@ static int sam_ep_configure_internal(struct sam_ep_s *privep, maxpacket &= 0x7ff; } - /* Initialize the endpoint structure */ + /* Initialize the endpoint structure */ - privep->ep.eplog = desc->addr; /* Includes direction */ - privep->ep.maxpacket = maxpacket; - privep->epstate = UDPHS_EPSTATE_IDLE; - privep->bank = SAM_UDPHS_NBANKS(epno); + privep->ep.eplog = desc->addr; /* Includes direction */ + privep->ep.maxpacket = maxpacket; + privep->epstate = UDPHS_EPSTATE_IDLE; + privep->bank = SAM_UDPHS_NBANKS(epno); /* Initialize the endpoint hardware */ + /* Disable the endpoint */ sam_putreg(UDPHS_EPTCTL_SHRTPCKT | UDPHS_EPTCTL_BUSYBANK | @@ -3374,6 +3433,7 @@ static int sam_ep_configure_internal(struct sam_ep_s *privep, /**************************************************************************** * Endpoint operations ****************************************************************************/ + /**************************************************************************** * Name: sam_ep_configure * @@ -3579,7 +3639,8 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) #ifdef CONFIG_DEBUG_FEATURES if (!priv->driver) { - usbtrace(TRACE_DEVERROR(SAM_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); + usbtrace(TRACE_DEVERROR(SAM_TRACEERR_NOTCONFIGURED), + priv->usbdev.speed); uerr("ERROR: driver=%p\n", priv->driver); return -ESHUTDOWN; } @@ -3806,6 +3867,7 @@ static int sam_ep_stall(struct usbdev_ep_s *ep, bool resume) /**************************************************************************** * Device Controller Operations ****************************************************************************/ + /**************************************************************************** * Name: sam_allocep * @@ -3838,10 +3900,11 @@ static struct usbdev_ep_s *sam_allocep(struct usbdev_s *dev, uint8_t epno, if (epno > 0) { - /* Otherwise, we will return the endpoint structure only for the requested - * 'logical' endpoint. All of the other checks will still be performed. + /* Otherwise, we will return the endpoint structure only for the + * requested 'logical' endpoint. All of the other checks will still + * be performed. * - * First, verify that the logical endpoint is in the range supported by + * First, verify that the logical endpoint is in the range supported * by the hardware. */ @@ -3963,8 +4026,8 @@ static int sam_wakeup(struct usbdev_s *dev) /* Activate a remote wakeup. Setting this bit forces an external interrupt * on the UDPHS controller for Remote Wake UP purposes. An Upstream Resume - * is sent only after the UDPHS bus has been in SUSPEND state for at least 5 - * ms. + * is sent only after the UDPHS bus has been in SUSPEND state for at least + * 5 ms. */ regval = sam_getreg(SAM_UDPHS_CTRL); @@ -4192,8 +4255,8 @@ static void sam_hw_setup(struct sam_usbdev_s *priv) * * Paragraph 33.5.1. "One transceiver is shared with the USB High Speed * Device (port A). The selection between Host Port A and USB Device is - * controlled by the UDPHS enable bit (EN_UDPHS) located in the UDPHS_CTRL - * control register. + * controlled by the UDPHS enable bit (EN_UDPHS) located in the + * UDPHS_CTRL control register. * * "In the case the port A is driven by the USB High Speed Device, the ... * transceiver is automatically selected for Device operation once the @@ -4396,6 +4459,7 @@ static void sam_sw_shutdown(struct sam_usbdev_s *priv) /**************************************************************************** * Public Functions ****************************************************************************/ + /**************************************************************************** * Name: arm_usbinitialize * Description: @@ -4496,8 +4560,8 @@ void arm_usbuninitialize(void) * Name: usbdev_register * * Description: - * Register a USB device class driver. The class driver's bind() method will be - * called to bind it to a USB device driver. + * Register a USB device class driver. The class driver's bind() method + * will be called to bind it to a USB device driver. * ****************************************************************************/ diff --git a/arch/arm/src/samd2l2/sam_serial.c b/arch/arm/src/samd2l2/sam_serial.c index 25fb58fe304..040a84ad358 100644 --- a/arch/arm/src/samd2l2/sam_serial.c +++ b/arch/arm/src/samd2l2/sam_serial.c @@ -68,6 +68,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* If we are not using the serial driver for the console, then we still must * provide some minimal implementation of up_putc. */ @@ -261,7 +262,7 @@ static void sam_shutdown(struct uart_dev_s *dev); static int sam_attach(struct uart_dev_s *dev); static void sam_detach(struct uart_dev_s *dev); static int sam_ioctl(struct file *filep, int cmd, unsigned long arg); -static int sam_receive(struct uart_dev_s *dev, uint32_t *status); +static int sam_receive(struct uart_dev_s *dev, unsigned int *status); static void sam_rxint(struct uart_dev_s *dev, bool enable); static bool sam_rxavailable(struct uart_dev_s *dev); static void sam_send(struct uart_dev_s *dev, int ch); @@ -477,7 +478,7 @@ static uart_dev_t g_usart4port = { .size = CONFIG_USART4_TXBUFSIZE, .buffer = g_usart4txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_usart4priv, }; @@ -510,7 +511,7 @@ static uart_dev_t g_usart5port = { .size = CONFIG_USART5_TXBUFSIZE, .buffer = g_usart5txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_usart5priv, }; @@ -821,7 +822,7 @@ static int sam_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int sam_receive(struct uart_dev_s *dev, uint32_t *status) +static int sam_receive(struct uart_dev_s *dev, unsigned int *status) { struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; @@ -848,7 +849,9 @@ static void sam_rxint(struct uart_dev_s *dev, bool enable) if (enable) { - /* Receive an interrupt when their is anything in the Rx data register */ + /* Receive an interrupt when their is anything in the Rx data + * register + */ #ifndef CONFIG_SUPPRESS_SERIAL_INTS sam_serialout8(priv, SAM_USART_INTENSET_OFFSET, USART_INT_RXC); @@ -871,7 +874,8 @@ static void sam_rxint(struct uart_dev_s *dev, bool enable) static bool sam_rxavailable(struct uart_dev_s *dev) { struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; - return ((sam_serialin8(priv, SAM_USART_INTFLAG_OFFSET) & USART_INT_RXC) != 0); + return ((sam_serialin8(priv, SAM_USART_INTFLAG_OFFSET) & USART_INT_RXC) + != 0); } /**************************************************************************** @@ -929,7 +933,9 @@ static void sam_txint(struct uart_dev_s *dev, bool enable) } else { - /* Disable the TX interrupt. Only disable DRE, TXC will disable itself! */ + /* Disable the TX interrupt. Only disable DRE, TXC will disable + * itself! + */ sam_serialout8(priv, SAM_USART_INTENCLR_OFFSET, USART_INT_DRE); } @@ -948,7 +954,8 @@ static void sam_txint(struct uart_dev_s *dev, bool enable) static bool sam_txempty(struct uart_dev_s *dev) { struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; - return ((sam_serialin8(priv, SAM_USART_INTFLAG_OFFSET) & USART_INT_DRE) != 0); + return ((sam_serialin8(priv, SAM_USART_INTFLAG_OFFSET) & USART_INT_DRE) + != 0); } /**************************************************************************** diff --git a/arch/arm/src/samd2l2/sam_start.c b/arch/arm/src/samd2l2/sam_start.c index 408276c703e..27fee01c2d4 100644 --- a/arch/arm/src/samd2l2/sam_start.c +++ b/arch/arm/src/samd2l2/sam_start.c @@ -77,7 +77,7 @@ * Public Data ****************************************************************************/ -const uint32_t g_idle_topstack = IDLE_STACK; +const uintptr_t g_idle_topstack = IDLE_STACK; /**************************************************************************** * Private Functions @@ -138,7 +138,9 @@ void __start(void) sam_clockconfig(); - /* Configure the uart early so that we can get debug output as soon as possible */ + /* Configure the uart early so that we can get debug output as soon as + * possible + */ sam_lowsetup(); showprogress('A'); diff --git a/arch/arm/src/samd2l2/sam_usb.c b/arch/arm/src/samd2l2/sam_usb.c index ec3499bf3b4..ce709bf2c43 100644 --- a/arch/arm/src/samd2l2/sam_usb.c +++ b/arch/arm/src/samd2l2/sam_usb.c @@ -783,7 +783,7 @@ static void sam_putreg32(uint32_t regval, uintptr_t regaddr) putreg32(regval, regaddr); } #else -static inline void sam_putreg32(uint32_t regval, uint32_t regaddr) +static inline void sam_putreg32(uint32_t regval, uintptr_t regaddr) { putreg32(regval, regaddr); } @@ -836,7 +836,7 @@ static void sam_putreg16(uint16_t regval, uintptr_t regaddr) putreg16(regval, regaddr); } #else -static inline void sam_putreg16(uint16_t regval, uint32_t regaddr) +static inline void sam_putreg16(uint16_t regval, uintptr_t regaddr) { putreg16(regval, regaddr); } @@ -889,7 +889,7 @@ static void sam_putreg8(uint8_t regval, uintptr_t regaddr) putreg8(regval, regaddr); } #else -static inline void sam_putreg8(uint8_t regval, uint32_t regaddr) +static inline void sam_putreg8(uint8_t regval, uintptr_t regaddr) { putreg8(regval, regaddr); } @@ -2270,7 +2270,9 @@ static void sam_resume(struct sam_usbdev_s *priv) sam_enableclks(); - /* Restore full power -- whatever that means for this particular board */ + /* Restore full power -- whatever that means for this particular + * board + */ sam_usb_suspend((struct usbdev_s *)priv, true); diff --git a/arch/arm/src/samd5e5/sam_serial.c b/arch/arm/src/samd5e5/sam_serial.c index 8313c421b0c..24447b6e9c6 100644 --- a/arch/arm/src/samd5e5/sam_serial.c +++ b/arch/arm/src/samd5e5/sam_serial.c @@ -67,6 +67,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* If we are not using the serial driver for the console, then we still must * provide some minimal implementation of up_putc. */ @@ -328,7 +329,7 @@ static void sam_shutdown(struct uart_dev_s *dev); static int sam_attach(struct uart_dev_s *dev); static void sam_detach(struct uart_dev_s *dev); static int sam_ioctl(struct file *filep, int cmd, unsigned long arg); -static int sam_receive(struct uart_dev_s *dev, uint32_t *status); +static int sam_receive(struct uart_dev_s *dev, unsigned int *status); static void sam_rxint(struct uart_dev_s *dev, bool enable); static bool sam_rxavailable(struct uart_dev_s *dev); static void sam_send(struct uart_dev_s *dev, int ch); @@ -512,7 +513,7 @@ static uart_dev_t g_usart4port = { .size = CONFIG_USART4_TXBUFSIZE, .buffer = g_usart4txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_usart4priv, }; @@ -537,7 +538,7 @@ static uart_dev_t g_usart5port = { .size = CONFIG_USART5_TXBUFSIZE, .buffer = g_usart5txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_usart5priv, }; @@ -562,7 +563,7 @@ static uart_dev_t g_usart6port = { .size = CONFIG_USART6_TXBUFSIZE, .buffer = g_usart6txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_usart6priv, }; @@ -587,7 +588,7 @@ static uart_dev_t g_usart7port = { .size = CONFIG_USART7_TXBUFSIZE, .buffer = g_usart7txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_usart7priv, }; @@ -879,7 +880,7 @@ static int sam_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int sam_receive(struct uart_dev_s *dev, uint32_t *status) +static int sam_receive(struct uart_dev_s *dev, unsigned int *status) { struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; @@ -907,7 +908,9 @@ static void sam_rxint(struct uart_dev_s *dev, bool enable) if (enable) { #ifndef CONFIG_SUPPRESS_SERIAL_INTS - /* Receive an interrupt when their is anything in the Rx data register */ + /* Receive an interrupt when their is anything in the Rx data + * register + */ sam_serialout8(priv, SAM_USART_INTENSET_OFFSET, USART_INT_RXC); #endif @@ -929,7 +932,8 @@ static void sam_rxint(struct uart_dev_s *dev, bool enable) static bool sam_rxavailable(struct uart_dev_s *dev) { struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; - return ((sam_serialin8(priv, SAM_USART_INTFLAG_OFFSET) & USART_INT_RXC) != 0); + return ((sam_serialin8(priv, SAM_USART_INTFLAG_OFFSET) & USART_INT_RXC) + != 0); } /**************************************************************************** @@ -997,7 +1001,8 @@ static void sam_txint(struct uart_dev_s *dev, bool enable) static bool sam_txempty(struct uart_dev_s *dev) { struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; - return ((sam_serialin8(priv, SAM_USART_INTFLAG_OFFSET) & USART_INT_DRE) != 0); + return ((sam_serialin8(priv, SAM_USART_INTFLAG_OFFSET) & USART_INT_DRE) + != 0); } /**************************************************************************** diff --git a/arch/arm/src/samv7/sam_serial.c b/arch/arm/src/samv7/sam_serial.c index a9e3cf62d7d..f3a7b46904f 100644 --- a/arch/arm/src/samv7/sam_serial.c +++ b/arch/arm/src/samv7/sam_serial.c @@ -355,7 +355,7 @@ static int sam_attach(struct uart_dev_s *dev); static void sam_detach(struct uart_dev_s *dev); static int sam_interrupt(int irq, void *context, FAR void *arg); static int sam_ioctl(struct file *filep, int cmd, unsigned long arg); -static int sam_receive(struct uart_dev_s *dev, uint32_t *status); +static int sam_receive(struct uart_dev_s *dev, unsigned int *status); static void sam_rxint(struct uart_dev_s *dev, bool enable); static bool sam_rxavailable(struct uart_dev_s *dev); static void sam_send(struct uart_dev_s *dev, int ch); @@ -1255,7 +1255,7 @@ static int sam_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int sam_receive(struct uart_dev_s *dev, uint32_t *status) +static int sam_receive(struct uart_dev_s *dev, unsigned int *status) { struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; diff --git a/arch/arm/src/stm32/hardware/stm32_dmamux.h b/arch/arm/src/stm32/hardware/stm32_dmamux.h new file mode 100644 index 00000000000..9b0e9f15497 --- /dev/null +++ b/arch/arm/src/stm32/hardware/stm32_dmamux.h @@ -0,0 +1,177 @@ +/**************************************************************************** + * arch/arm/src/stm32/hardware/stm32_dmamux.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMAMUX_H +#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMAMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define DMAMUX1 0 + +/* Register Offsets *********************************************************/ + +#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000 + (0x0004 * (x))) /* DMAMUX1 request line multiplexer channel x configuration register */ +#define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0) /* 0x000 */ +#define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1) /* 0x004 */ +#define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2) /* 0x008 */ +#define STM32_DMAMUX_C3CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(3) /* 0x00c */ +#define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4) /* 0x010 */ +#define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5) /* 0x014 */ +#define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6) /* 0x018 */ +#define STM32_DMAMUX_C7CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(7) /* 0x01c */ +#define STM32_DMAMUX_C8CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(8) /* 0x020 */ +#define STM32_DMAMUX_C9CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(9) /* 0x024 */ +#define STM32_DMAMUX_C10CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(10) /* 0x028 */ +#define STM32_DMAMUX_C11CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(11) /* 0x02c */ +#define STM32_DMAMUX_C12CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(12) /* 0x030 */ +#define STM32_DMAMUX_C13CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(13) /* 0x034 */ +#define STM32_DMAMUX_C14CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(14) /* 0x038 */ +#define STM32_DMAMUX_C15CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(15) /* 0x03c */ + /* 0x040-0x07C: Reserved */ +#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ +#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ + /* 0x088-0x0FC: Reserved */ +#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100 + (0x004 * (x))) /* DMAMUX1 request generator channel x configuration register */ +#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0) +#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1) +#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2) +#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3) +#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ +#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ + /* 0x148-0x3FC: Reserved */ + +/* Register Addresses *******************************************************/ + +#define STM32_DMAMUX1_CXCR(x) (STM32_DMAMUX1_BASE + STM32_DMAMUX_CXCR_OFFSET(x)) +#define STM32_DMAMUX1_C0CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C0CR_OFFSET) +#define STM32_DMAMUX1_C1CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C1CR_OFFSET) +#define STM32_DMAMUX1_C2CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C2CR_OFFSET) +#define STM32_DMAMUX1_C3CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C3CR_OFFSET) +#define STM32_DMAMUX1_C4CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C4CR_OFFSET) +#define STM32_DMAMUX1_C5CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C5CR_OFFSET) +#define STM32_DMAMUX1_C6CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C6CR_OFFSET) +#define STM32_DMAMUX1_C7CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C7CR_OFFSET) +#define STM32_DMAMUX1_C8CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C8CR_OFFSET) +#define STM32_DMAMUX1_C9CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C9CR_OFFSET) +#define STM32_DMAMUX1_C10CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C10CR_OFFSET) +#define STM32_DMAMUX1_C11CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C11CR_OFFSET) +#define STM32_DMAMUX1_C12CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C12CR_OFFSET) +#define STM32_DMAMUX1_C13CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C13CR_OFFSET) +#define STM32_DMAMUX1_C14CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C14CR_OFFSET) +#define STM32_DMAMUX1_C15CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C15CR_OFFSET) + +#define STM32_DMAMUX1_CSR (STM32_DMAMUX1_BASE + STM32_DMAMUX_CSR_OFFSET) +#define STM32_DMAMUX1_CFR (STM32_DMAMUX1_BASE + STM32_DMAMUX_CFR_OFFSET) + +#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGXCR_OFFSET(x)) +#define STM32_DMAMUX1_RG0CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG0CR_OFFSET) +#define STM32_DMAMUX1_RG1CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG1CR_OFFSET) +#define STM32_DMAMUX1_RG2CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG2CR_OFFSET) +#define STM32_DMAMUX1_RG3CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG3CR_OFFSET) + +#define STM32_DMAMUX1_RGSR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGSR_OFFSET) +#define STM32_DMAMUX1_RGCFR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGCFR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* DMAMUX1 CxCR - request line multiplexer channel x configuration register */ + +#define DMAMUX_CCR_DMAREQID_SHIFT (0) /* Bits 0-6: DMA request identification */ +#define DMAMUX_CCR_DMAREQID_MASK (0x7f << DMAMUX_CCR_DMAREQID_SHIFT) +# define DMAMUX_CCR_DMAREQID(x) ((x) << DMAMUX_CCR_DMAREQID_SHIFT) +#define DMAMUX_CCR_SOIE (8) /* Bit 8: Synchronization overrun interrupt enable */ +#define DMAMUX_CCR_EGE (9) /* Bit 9: Event generation enable */ +#define DMAMUX_CCR_SE (16) /* Bit 16: Synchronization enable */ +#define DMAMUX_CCR_SPOL_SHIFT (17) /* Bits 17-18: Synchronization polarity */ +#define DMAMUX_CCR_SPOL_MASK (3 << DMAMUX_CCR_SPOL_SHIFT) +# define DMAMUX_CCR_SPOL_NONE (0x0 << DMAMUX_CCR_SPOL_SHIFT) /* No event: No trigger detection or generation */ +# define DMAMUX_CCR_SPOL_RISING (0x1 << DMAMUX_CCR_SPOL_SHIFT) /* Rising edge */ +# define DMAMUX_CCR_SPOL_FALLING (0x2 << DMAMUX_CCR_SPOL_SHIFT) /* Falling edge */ +# define DMAMUX_CCR_SPOL_BOTH (0x3 << DMAMUX_CCR_SPOL_SHIFT) /* Both rising and falling edges */ +#define DMAMUX_CCR_NBREQ_SHIFT (19) /* Bits 19-23: Number of DMA request - 1 to forward */ +#define DMAMUX_CCR_NBREQ_MASK (0x1f << DMAMUX_CCR_NBREQ_SHIFT) +#define DMAMUX_CCR_SYNCID_SHIFT (24) /* Bits 24-26: Synchronization identification */ +#define DMAMUX_CCR_SYNCID_MASK (7 << DMAMUX_CCR_SYNCID_SHIFT) + +/* DMAMUX1 CSR - request line multiplexer interrupt channel status register */ + +#define DMAMUX1_CSR_SOF(x) (1 << (x)) /* Synchronization overrun event flag */ + +/* DMAMUX1 CFR - request line multiplexer interrupt clear flag register */ + +#define DMAMUX1_CFR_SOF(x) (1 << (x)) /* Clear synchronization overrun event flag */ + +/* DMAMUX1 RGCR - request generator channel x configuration register */ + +#define DMAMUX_RGCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identification */ +#define DMAMUX_RGCR_SIGID_MASK (0x1f << DMAMUX_RGCR_SIGID_SHIFT) +#define DMAMUX_RGCR_OIE (8) /* Bit 8: Trigger overrun interrupt enable */ +#define DMAMUX_RGCR_GE (16) /* Bit 16: DMA request generator channel X enable*/ +#define DMAMUX_RGCR_GPOL_SHIFT (17) /* Bits 17-18: DMA request generator trigger polarity */ +#define DMAMUX_RGCR_GPOL_MASK (0x3 << DMAMUX_RGCR_GPOL_SHIFT) +# define DMAMUX_RGCR_GPOL_NONE (0x0 << DMAMUX_RGCR_GPOL_SHIFT) /* No event: No trigger detection or generation */ +# define DMAMUX_RGCR_GPOL_RISING (0x1 << DMAMUX_RGCR_GPOL_SHIFT) /* Rising edge */ +# define DMAMUX_RGCR_GPOL_FALLING (0x2 << DMAMUX_RGCR_GPOL_SHIFT) /* Falling edge */ +# define DMAMUX_RGCR_GPOL_BOTH (0x3 << DMAMUX_RGCR_GPOL_SHIFT) /* Both rising and falling edges */ +#define DMAMUX_RGCR_GNBREQ_SHIFT (19) /* Bits 19-23: Number of DMA requests to be generated -1 */ +#define DMAMUX_RGCR_GNBREQ_MASK (0x1f << DMAMUX_RGCR_GNBREQ_SHIFT) + +/* DMAMUX1 RGSR - request generator interrupt status register */ + +#define DMAMUX1_RGSR_OF(x) (1 << (x)) /* Trigger overrun event flag */ + +/* DMAMUX1 RGCFR - request generator interrupt clear flag register */ + +#define DMAMUX1_RGCFR_COF(x) (1 << (x)) /* Clear trigger overrun event flag */ + +/* DMA channel mapping + * + * XXXXX.DDD.CCCCCCCC + * C - DMAMUX request + * D - DMA controller + * X - free bits + */ + +#define DMAMAP_MAP(d,c) ((d) << 8 | (c)) +#define DMAMAP_CONTROLLER(m) ((m) >> 8 & 0x07) +#define DMAMAP_REQUEST(m) ((m) >> 0 & 0xff) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Import DMAMUX map */ + +#if defined(CONFIG_STM32_STM32G47XX) +# include "hardware/stm32g47xxx_dmamux.h" +#else +# error "Unsupported STM32 sub family" +#endif + +#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMAMUX_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_spi.h b/arch/arm/src/stm32/hardware/stm32_spi.h index c78700466fa..9d366171482 100644 --- a/arch/arm/src/stm32/hardware/stm32_spi.h +++ b/arch/arm/src/stm32/hardware/stm32_spi.h @@ -47,6 +47,44 @@ * Pre-processor Definitions ************************************************************************************/ +/* SPI version **********************************************************************/ + +/* SPI IP v1 is default unless v2 or greater is specified for this chip */ + +#undef HAVE_SPI_I2S /* No I2S mode in the SPI peripheral */ +#undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ +#undef HAVE_SPI_TI_MODE /* Motorola frame mode only; no TI mode */ +#undef HAVE_SPI_ARB_DATA_SIZE /* Data size 8 or 16 bit; not arbitrary 4-16 bit */ +#undef HAVE_SPI_FIFOS /* No Tx/Rx FIFOs */ +#undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ + +#if defined(STM32_HAVE_IP_SPI_V2) +# define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ +# undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ +# define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ +# undef HAVE_SPI_ARB_DATA_SIZE /* Data size 8 or 16 bit; not arbitrary 4-16 bit */ +# undef HAVE_SPI_FIFOS /* No Tx/Rx FIFOs */ +# undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ +#endif + +#if defined(STM32_HAVE_IP_SPI_V3) +# define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ +# undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ +# define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ +# define HAVE_SPI_ARB_DATA_SIZE /* Supports arbitrary data size from 4-16 bits */ +# define HAVE_SPI_FIFOS /* Have Tx/Rx FIFOs */ +# undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ +#endif + +#if defined(STM32_HAVE_IP_SPI_V4) +# define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ +# define HAVE_SPI_I2S_ASTRT /* Supports I2S asynchronous start capability */ +# define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ +# define HAVE_SPI_ARB_DATA_SIZE /* Supports arbitrary data size from 4-16 bits */ +# define HAVE_SPI_FIFOS /* Have Tx/Rx FIFOs */ +# define HAVE_SPI_NSSP /* Have NSS Pulse Management in master mode */ +#endif + /* Maximum allowed speed as per specifications for all SPIs */ #if defined(CONFIG_STM32_STM32F4XXX) @@ -65,8 +103,7 @@ #define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ #define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(HAVE_SPI_I2S) # define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ # define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ #endif @@ -74,42 +111,40 @@ /* Register Addresses ***************************************************************/ #if STM32_NSPI > 0 -# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) -# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) -# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) -# define STM32_SPI1_DR (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET) -# define STM32_SPI1_CRCPR (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET) -# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET) -# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET) +# define STM32_SPI1_CR1 (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI1_CR2 (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI1_SR (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI1_DR (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI1_CRCPR (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) #endif #if STM32_NSPI > 1 -# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) -# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) -# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) -# define STM32_SPI2_DR (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET) -# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET) -# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET) -# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET) -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) -# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET) -# define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET) +# define STM32_SPI2_CR1 (STM32_SPI2_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI2_DR (STM32_SPI2_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI2_CRCPR (STM32_SPI2_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE + STM32_SPI_TXCRCR_OFFSET) +# if defined(HAVE_SPI_I2S) +# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE + STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI2_I2SPR (STM32_SPI2_BASE + STM32_SPI_I2SPR_OFFSET) # endif #endif #if STM32_NSPI > 2 -# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) -# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) -# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET) -# define STM32_SPI3_DR (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET) -# define STM32_SPI3_CRCPR (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET) -# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET) -# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET) -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) -# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET) -# define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET) +# define STM32_SPI3_CR1 (STM32_SPI3_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI3_CR2 (STM32_SPI3_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI3_SR (STM32_SPI3_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI3_DR (STM32_SPI3_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI3_CRCPR (STM32_SPI3_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE + STM32_SPI_TXCRCR_OFFSET) +# if defined(HAVE_SPI_I2S) +# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE + STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI3_I2SPR (STM32_SPI3_BASE + STM32_SPI_I2SPR_OFFSET) # endif #endif @@ -117,10 +152,10 @@ /* SPI Control Register 1 */ -#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */ -#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */ -#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */ -#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */ +#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */ +#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */ +#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */ +#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */ #define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT) # define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */ # define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */ @@ -130,20 +165,20 @@ # define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */ # define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */ # define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */ -#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */ -#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */ -#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */ -#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */ -#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */ -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) -# define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */ +#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */ +#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */ +#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */ +#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */ +#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */ +#if defined(HAVE_SPI_ARB_DATA_SIZE) +# define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */ #else -# define SPI_CR1_DFF (1 << 11) /* Bit 11: Data Frame Format */ +# define SPI_CR1_DFF (1 << 11) /* Bit 11: Data Frame Format */ #endif -#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */ -#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */ +#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */ +#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */ /* SPI Control Register 2 */ @@ -151,35 +186,38 @@ #define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */ #define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) -# define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */ +#if defined(HAVE_SPI_NSSP) +# define SPI_CR2_NSSP (1 << 3) /* Bit 3: NSS Pulse Management (Master mode only) */ +#endif + +#if defined(HAVE_SPI_TI_MODE) +# define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format: 0=Motorola, 1=TI */ #endif #define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */ #define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */ #define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */ -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) -#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */ -#define SPI_CR2_DS_MASK (15 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS(n) ((uint32_t)((n) - 1) << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_4BIT (3 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_5BIT (4 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_6BIT (5 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_7BIT (6 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_8BIT (7 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_9BIT (8 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_10BIT (9 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_11BIT (10 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_12BIT (11 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_13BIT (12 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_14BIT (13 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_15BIT (14 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_16BIT (15 << SPI_CR2_DS_SHIFT) -#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */ -#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */ -#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */ +#if defined(HAVE_SPI_ARB_DATA_SIZE) +# define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */ +# define SPI_CR2_DS_MASK (15 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS(n) ((uint32_t)((n) - 1) << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_4BIT (3 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_5BIT (4 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_6BIT (5 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_7BIT (6 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_8BIT (7 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_9BIT (8 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_10BIT (9 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_11BIT (10 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_12BIT (11 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_13BIT (12 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_14BIT (13 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_15BIT (14 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_16BIT (15 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */ +# define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for reception */ +# define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */ #endif /* SPI status register */ @@ -187,8 +225,7 @@ #define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */ #define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(HAVE_SPI_I2S) # define SPI_SR_CHSIDE (1 << 2) /* Bit 2: Channel side */ # define SPI_SR_UDR (1 << 3) /* Bit 3: Underrun flag */ #endif @@ -198,62 +235,62 @@ #define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */ #define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(HAVE_SPI_I2S) || defined(HAVE_SPI_TI_MODE) # define SPI_SR_FRE (1 << 8) /* Bit 8: TI frame format error */ #endif -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) -#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */ -#define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT) -# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */ -# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */ -# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */ -# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */ -#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */ -#define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT) -# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */ -# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */ -# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ -# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ +#if defined(HAVE_SPI_FIFOS) +# define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */ +# define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT) +# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */ +# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */ +# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */ +# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */ +# define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */ +# define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT) +# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */ +# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */ +# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ +# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ #endif /* I2S configuration register */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) -# define SPI_I2SCFGR_CHLEN (1 << 0) /* Bit 0: Channel length (number of bits per audio channel) */ -# define SPI_I2SCFGR_DATLEN_SHIFT (1) /* Bit 1-2: Data length to be transferred */ +#if defined(HAVE_SPI_I2S) +# define SPI_I2SCFGR_CHLEN (1 << 0) /* Bit 0: Channel length (number of bits per audio channel) */ +# define SPI_I2SCFGR_DATLEN_SHIFT (1) /* Bit 1-2: Data length to be transferred */ # define SPI_I2SCFGR_DATLEN_MASK (3 << SPI_I2SCFGR_DATLEN_SHIFT) -# define SPI_I2SCFGR_DATLEN_16BIT (0 << SPI_I2SCFGR_DATLEN_SHIFT) /* 00: 16-bit data length */ -# define SPI_I2SCFGR_DATLEN_8BIT (1 << SPI_I2SCFGR_DATLEN_SHIFT) /* 01: 24-bit data length */ -# define SPI_I2SCFGR_DATLEN_32BIT (2 << SPI_I2SCFGR_DATLEN_SHIFT) /* 10: 32-bit data length */ -# define SPI_I2SCFGR_CKPOL (1 << 3) /* Bit 3: Steady state clock polarity */ -# define SPI_I2SCFGR_I2SSTD_SHIFT (4) /* Bit 4-5: I2S standard selection */ +# define SPI_I2SCFGR_DATLEN_16BIT (0 << SPI_I2SCFGR_DATLEN_SHIFT) /* 00: 16-bit data length */ +# define SPI_I2SCFGR_DATLEN_8BIT (1 << SPI_I2SCFGR_DATLEN_SHIFT) /* 01: 24-bit data length */ +# define SPI_I2SCFGR_DATLEN_32BIT (2 << SPI_I2SCFGR_DATLEN_SHIFT) /* 10: 32-bit data length */ +# define SPI_I2SCFGR_CKPOL (1 << 3) /* Bit 3: Steady state clock polarity */ +# define SPI_I2SCFGR_I2SSTD_SHIFT (4) /* Bit 4-5: I2S standard selection */ # define SPI_I2SCFGR_I2SSTD_MASK (3 << SPI_I2SCFGR_I2SSTD_SHIFT) -# define SPI_I2SCFGR_I2SSTD_PHILLIPS (xx << SPI_I2SCFGR_I2SSTD_SHIFT) /* 00: I2S Phillips standard. */ -# define SPI_I2SCFGR_I2SSTD_MSB (0 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */ -# define SPI_I2SCFGR_I2SSTD_LSB (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */ -# define SPI_I2SCFGR_I2SSTD_PCM (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */ -# define SPI_I2SCFGR_PCMSYNC (1 << 7) /* Bit 7: PCM frame synchronization */ -# define SPI_I2SCFGR_I2SCFG_SHIFT (8) /* Bit 8-9: I2S configuration mode */ +# define SPI_I2SCFGR_I2SSTD_PHILLIPS (0 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 00: I2S Phillips standard. */ +# define SPI_I2SCFGR_I2SSTD_MSB (1 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */ +# define SPI_I2SCFGR_I2SSTD_LSB (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */ +# define SPI_I2SCFGR_I2SSTD_PCM (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */ +# define SPI_I2SCFGR_PCMSYNC (1 << 7) /* Bit 7: PCM frame synchronization */ +# define SPI_I2SCFGR_I2SCFG_SHIFT (8) /* Bit 8-9: I2S configuration mode */ # define SPI_I2SCFGR_I2SCFG_MASK (3 << SPI_I2SCFGR_I2SCFG_SHIFT) -# define SPI_I2SCFGR_I2SCFG_STX (0 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 00: Slave - transmit */ -# define SPI_I2SCFGR_I2SCFG_SRX (1 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 01: Slave - receive */ -# define SPI_I2SCFGR_I2SCFG_MTX (2 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 10: Master - transmit */ -# define SPI_I2SCFGR_I2SCFG_MRX (3 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 11: Master - receive */ -# define SPI_I2SCFGR_I2SE (1 << 10) /* Bit 10: I2S Enable */ -# define SPI_I2SCFGR_I2SMOD (1 << 11) /* Bit 11: I2S mode selection */ +# define SPI_I2SCFGR_I2SCFG_STX (0 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 00: Slave - transmit */ +# define SPI_I2SCFGR_I2SCFG_SRX (1 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 01: Slave - receive */ +# define SPI_I2SCFGR_I2SCFG_MTX (2 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 10: Master - transmit */ +# define SPI_I2SCFGR_I2SCFG_MRX (3 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 11: Master - receive */ +# define SPI_I2SCFGR_I2SE (1 << 10) /* Bit 10: I2S Enable */ +# define SPI_I2SCFGR_I2SMOD (1 << 11) /* Bit 11: I2S mode selection */ +# if defined(HAVE_SPI_I2S_ASTRT) +# define SPI_I2SCFGR_ASTRTEN (1 << 12) /* Bit 12: Asynchronous start enable */ +# endif #endif /* I2S prescaler register */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) -# define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */ -# define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT) -# define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */ -# define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ +#if defined(HAVE_SPI_I2S) +# define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */ +# define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT) +# define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */ +# define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ #endif #endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SPI_H */ diff --git a/arch/arm/src/stm32/hardware/stm32g47xxx_dmamux.h b/arch/arm/src/stm32/hardware/stm32g47xxx_dmamux.h new file mode 100644 index 00000000000..c4287be3184 --- /dev/null +++ b/arch/arm/src/stm32/hardware/stm32g47xxx_dmamux.h @@ -0,0 +1,157 @@ +/************************************************************************************ + * arch/arm/src/stm32/hardware/stm32g47xxx_dmamux.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_DMAMUX_H +#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_DMAMUX_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* DMAMUX1 mapping ******************************************************************/ + +/* NOTE: DMAMUX1 channels 0 to 7 are connected to DMA1 channels 0 to 7. + * DMAMUX1 channels 8 to 15 are connected to DMA2 channels 0 to 7. + */ + +#define DMAMUX1_REQ_MEM2MEM (0) /* Memory to memory transfer */ +#define DMAMUX1_REQ_GEN0 (1) /* DMAMUX Request Generator 0 */ +#define DMAMUX1_REQ_GEN1 (2) /* DMAMUX Request Generator 1 */ +#define DMAMUX1_REQ_GEN2 (3) /* DMAMUX Request Generator 2 */ +#define DMAMUX1_REQ_GEN3 (4) /* DMAMUX Request Generator 3 */ +#define DMAMUX1_REQ_ADC1 (5) /* DMAMUX ADC1 request */ +#define DMAMUX1_REQ_DAC1_CH1 (6) /* DMAMUX DAC1 Channel 1 request */ +#define DMAMUX1_REQ_DAC1_CH2 (7) /* DMAMUX DAC1 Channel 2 request */ +#define DMAMUX1_REQ_TIM6_UP (8) /* DMAMUX TIM6 Update request */ +#define DMAMUX1_REQ_TIM7_UP (9) /* DMAMUX TIM7 Update request */ +#define DMAMUX1_REQ_SPI1_RX (10) /* DMAMUX SPI1 Rx request */ +#define DMAMUX1_REQ_SPI1_TX (11) /* DMAMUX SPI1 Tx request */ +#define DMAMUX1_REQ_SPI2_RX (12) /* DMAMUX SPI2 Rx request */ +#define DMAMUX1_REQ_SPI2_TX (13) /* DMAMUX SPI2 Tx request */ +#define DMAMUX1_REQ_SPI3_RX (14) /* DMAMUX SPI3 Rx request */ +#define DMAMUX1_REQ_SPI3_TX (15) /* DMAMUX SPI3 Tx request */ +#define DMAMUX1_REQ_I2C1_RX (16) /* DMAMUX I2C1 Rx request */ +#define DMAMUX1_REQ_I2C1_TX (17) /* DMAMUX I2C1 Tx request */ +#define DMAMUX1_REQ_I2C2_RX (18) /* DMAMUX I2C2 Rx request */ +#define DMAMUX1_REQ_I2C2_TX (19) /* DMAMUX I2C2 Tx request */ +#define DMAMUX1_REQ_I2C3_RX (20) /* DMAMUX I2C3 Rx request */ +#define DMAMUX1_REQ_I2C3_TX (21) /* DMAMUX I2C3 Tx request */ +#define DMAMUX1_REQ_I2C4_RX (22) /* DMAMUX I2C4 Rx request */ +#define DMAMUX1_REQ_I2C4_TX (23) /* DMAMUX I2C4 Tx request */ +#define DMAMUX1_REQ_USART1_RX (24) /* DMAMUX USART1 Rx request */ +#define DMAMUX1_REQ_USART1_TX (25) /* DMAMUX USART1 Tx request */ +#define DMAMUX1_REQ_USART2_RX (26) /* DMAMUX USART2 Rx request */ +#define DMAMUX1_REQ_USART2_TX (27) /* DMAMUX USART2 Tx request */ +#define DMAMUX1_REQ_USART3_RX (28) /* DMAMUX USART3 Rx request */ +#define DMAMUX1_REQ_USART3_TX (29) /* DMAMUX USART3 Tx request */ +#define DMAMUX1_REQ_UART4_RX (30) /* DMAMUX UART4 Rx request */ +#define DMAMUX1_REQ_UART4_TX (31) /* DMAMUX UART4 Tx request */ +#define DMAMUX1_REQ_UART5_RX (32) /* DMAMUX UART5 Rx request */ +#define DMAMUX1_REQ_UART5_TX (33) /* DMAMUX UART5 Tx request */ +#define DMAMUX1_REQ_LPUART1_RX (34) /* DMAMUX LPUART1 Rx request */ +#define DMAMUX1_REQ_LPUART1_TX (35) /* DMAMUX LPUART1 Tx request */ +#define DMAMUX1_REQ_ADC2 (36) /* DMAMUX ADC2 request */ +#define DMAMUX1_REQ_ADC3 (37) /* DMAMUX ADC3 request */ +#define DMAMUX1_REQ_ADC4 (38) /* DMAMUX ADC4 request */ +#define DMAMUX1_REQ_ADC5 (39) /* DMAMUX ADC5 request */ +#define DMAMUX1_REQ_QSPI (40) /* DMAMUX QSPI request */ +#define DMAMUX1_REQ_DAC2_CH1 (41) /* DMAMUX DAC2 Channel 1 request */ +#define DMAMUX1_REQ_TIM1_CH1 (42) /* DMAMUX TIM1 Channel 1 request */ +#define DMAMUX1_REQ_TIM1_CH2 (43) /* DMAMUX TIM1 Channel 2 request */ +#define DMAMUX1_REQ_TIM1_CH3 (44) /* DMAMUX TIM1 Channel 3 request */ +#define DMAMUX1_REQ_TIM1_CH4 (45) /* DMAMUX TIM1 Channel 4 request */ +#define DMAMUX1_REQ_TIM1_UP (46) /* DMAMUX TIM1 Update request */ +#define DMAMUX1_REQ_TIM1_TRIG (47) /* DMAMUX TIM1 Trigger request */ +#define DMAMUX1_REQ_TIM1_COM (48) /* DMAMUX TIM1 Commutation request */ +#define DMAMUX1_REQ_TIM8_CH1 (49) /* DMAMUX TIM8 Channel 1 request */ +#define DMAMUX1_REQ_TIM8_CH2 (50) /* DMAMUX TIM8 Channel 2 request */ +#define DMAMUX1_REQ_TIM8_CH3 (51) /* DMAMUX TIM8 Channel 3 request */ +#define DMAMUX1_REQ_TIM8_CH4 (52) /* DMAMUX TIM8 Channel 4 request */ +#define DMAMUX1_REQ_TIM8_UP (53) /* DMAMUX TIM8 Update request */ +#define DMAMUX1_REQ_TIM8_TRIG (54) /* DMAMUX TIM8 Trigger request */ +#define DMAMUX1_REQ_TIM8_COM (55) /* DMAMUX TIM8 Commutation request */ +#define DMAMUX1_REQ_TIM2_CH1 (56) /* DMAMUX TIM2 Channel 1 request */ +#define DMAMUX1_REQ_TIM2_CH2 (57) /* DMAMUX TIM2 Channel 2 request */ +#define DMAMUX1_REQ_TIM2_CH3 (58) /* DMAMUX TIM2 Channel 3 request */ +#define DMAMUX1_REQ_TIM2_CH4 (59) /* DMAMUX TIM2 Channel 4 request */ +#define DMAMUX1_REQ_TIM2_UP (60) /* DMAMUX TIM2 Update request */ +#define DMAMUX1_REQ_TIM3_CH1 (61) /* DMAMUX TIM3 Channel 1 request */ +#define DMAMUX1_REQ_TIM3_CH2 (62) /* DMAMUX TIM3 Channel 2 request */ +#define DMAMUX1_REQ_TIM3_CH3 (63) /* DMAMUX TIM3 Channel 3 request */ +#define DMAMUX1_REQ_TIM3_CH4 (64) /* DMAMUX TIM3 Channel 4 request */ +#define DMAMUX1_REQ_TIM3_UP (65) /* DMAMUX TIM3 Update request */ +#define DMAMUX1_REQ_TIM3_TRIG (66) /* DMAMUX TIM3 Trigger request */ +#define DMAMUX1_REQ_TIM4_CH1 (67) /* DMAMUX TIM4 Channel 1 request */ +#define DMAMUX1_REQ_TIM4_CH2 (68) /* DMAMUX TIM4 Channel 2 request */ +#define DMAMUX1_REQ_TIM4_CH3 (69) /* DMAMUX TIM4 Channel 3 request */ +#define DMAMUX1_REQ_TIM4_CH4 (70) /* DMAMUX TIM4 Channel 4 request */ +#define DMAMUX1_REQ_TIM4_UP (71) /* DMAMUX TIM4 Update request */ +#define DMAMUX1_REQ_TIM5_CH1 (72) /* DMAMUX TIM5 Channel 1 request */ +#define DMAMUX1_REQ_TIM5_CH2 (73) /* DMAMUX TIM5 Channel 2 request */ +#define DMAMUX1_REQ_TIM5_CH3 (74) /* DMAMUX TIM5 Channel 3 request */ +#define DMAMUX1_REQ_TIM5_CH4 (75) /* DMAMUX TIM5 Channel 4 request */ +#define DMAMUX1_REQ_TIM5_UP (76) /* DMAMUX TIM5 Update request */ +#define DMAMUX1_REQ_TIM5_TRIG (77) /* DMAMUX TIM5 Trigger request */ +#define DMAMUX1_REQ_TIM15_CH1 (78) /* DMAMUX TIM15 Channel 1 request */ +#define DMAMUX1_REQ_TIM15_UP (79) /* DMAMUX TIM15 Update request */ +#define DMAMUX1_REQ_TIM15_TRIG (80) /* DMAMUX TIM15 Trigger request */ +#define DMAMUX1_REQ_TIM15_COM (81) /* DMAMUX TIM15 Commutation request */ +#define DMAMUX1_REQ_TIM16_CH1 (82) /* DMAMUX TIM16 Channel 1 request */ +#define DMAMUX1_REQ_TIM16_UP (83) /* DMAMUX TIM16 Update request */ +#define DMAMUX1_REQ_TIM17_CH1 (84) /* DMAMUX TIM17 Channel 1 request */ +#define DMAMUX1_REQ_TIM17_UP (85) /* DMAMUX TIM17 Update request */ +#define DMAMUX1_REQ_TIM20_CH1 (86) /* DMAMUX TIM20 Channel 1 request */ +#define DMAMUX1_REQ_TIM20_CH2 (87) /* DMAMUX TIM20 Channel 2 request */ +#define DMAMUX1_REQ_TIM20_CH3 (88) /* DMAMUX TIM20 Channel 3 request */ +#define DMAMUX1_REQ_TIM20_CH4 (89) /* DMAMUX TIM20 Channel 4 request */ +#define DMAMUX1_REQ_TIM20_UP (90) /* DMAMUX TIM20 Update request */ +#define DMAMUX1_REQ_AES_IN (91) /* DMAMUX AES In request */ +#define DMAMUX1_REQ_AES_OUT (92) /* DMAMUX AES Out request */ +#define DMAMUX1_REQ_TIM20_TRIG (93) /* DMAMUX TIM20 Trigger request */ +#define DMAMUX1_REQ_TIM20_COM (94) /* DMAMUX TIM20 Commutation request */ +#define DMAMUX1_REQ_HRTIM1_M (95) /* DMAMUX HRTIM M request */ +#define DMAMUX1_REQ_HRTIM1_A (96) /* DMAMUX HRTIM A request */ +#define DMAMUX1_REQ_HRTIM1_B (97) /* DMAMUX HRTIM B request */ +#define DMAMUX1_REQ_HRTIM1_C (98) /* DMAMUX HRTIM C request */ +#define DMAMUX1_REQ_HRTIM1_D (99) /* DMAMUX HRTIM D request */ +#define DMAMUX1_REQ_HRTIM1_E (100) /* DMAMUX HRTIM E request */ +#define DMAMUX1_REQ_HRTIM1_F (101) /* DMAMUX HRTIM F request */ +#define DMAMUX1_REQ_DAC3_CH1 (102) /* DMAMUX DAC3 Channel 1 request */ +#define DMAMUX1_REQ_DAC3_CH2 (103) /* DMAMUX DAC3 Channel 2 request */ +#define DMAMUX1_REQ_DAC4_CH1 (104) /* DMAMUX DAC4 Channel 1 request */ +#define DMAMUX1_REQ_DAC4_CH2 (105) /* DMAMUX DAC4 Channel 2 request */ +#define DMAMUX1_REQ_SPI4_RX (106) /* DMAMUX SPI4 Rx request */ +#define DMAMUX1_REQ_SPI4_TX (107) /* DMAMUX SPI4 Tx request */ +#define DMAMUX1_REQ_SAI1_A (108) /* DMAMUX SAI1 A request */ +#define DMAMUX1_REQ_SAI1_B (109) /* DMAMUX SAI1 B request */ +#define DMAMUX1_REQ_FMAC_READ (110) /* DMAMUX FMAC Read request */ +#define DMAMUX1_REQ_FMAC_WRITE (111) /* DMAMUX FMAC Write request */ +#define DMAMUX1_REQ_CORDIC_READ (112) /* DMAMUX CORDIC Read request */ +#define DMAMUX1_REQ_CORDIC_WRITE (113) /* DMAMUX CORDIC Write request */ +#define DMAMUX1_REQ_UCPD1_RX (114) /* DMAMUX USBPD1 Rx request */ +#define DMAMUX1_REQ_UCPD1_TX (115) /* DMAMUX USBPD1 Tx request */ + +#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_DMAMUX_H */ diff --git a/arch/arm/src/stm32/stm32_1wire.h b/arch/arm/src/stm32/stm32_1wire.h index 3297c3cdcdf..f03b2a322d2 100644 --- a/arch/arm/src/stm32/stm32_1wire.h +++ b/arch/arm/src/stm32/stm32_1wire.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32/stm32_1wire.h * * Copyright (C) 2016 Aleksandr Vyhovanec. All rights reserved. @@ -31,30 +31,30 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32_STM32_1WIRE_H #define __ARCH_ARM_SRC_STM32_STM32_1WIRE_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "stm32_uart.h" -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: stm32_1wireinitialize * * Description: - * Initialize the selected 1-Wire port. And return a unique instance of struct - * struct onewire_dev_s. This function may be called to obtain multiple - * instances of the interface, each of which may be set up with a + * Initialize the selected 1-Wire port. And return a unique instance of + * struct struct onewire_dev_s. This function may be called to obtain + * multiple instances of the interface, each of which may be set up with a * different frequency and slave address. * * Input Parameters: diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c index 8fda778ea4a..9820f5305bd 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/stm32/stm32_adc.c @@ -45,6 +45,7 @@ #include #include +#include #include #include #include @@ -3134,7 +3135,7 @@ static void adc_ioc_enable_tvref_register(FAR struct adc_dev_s *dev, } } - ainfo("STM32_ADC_CR2 value: 0x%08x\n", + ainfo("STM32_ADC_CR2 value: 0x%08" PRIx32 "\n", adc_getreg(priv, STM32_ADC_CR2_OFFSET)); # endif /* CONFIG_STM32_ADC1 */ #else /* !HAVE_BASIC_ADC */ @@ -3147,7 +3148,7 @@ static void adc_ioc_enable_tvref_register(FAR struct adc_dev_s *dev, adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, ADC_CCR_TSVREFE, 0); } - ainfo("STM32_ADC_CCR value: 0x%08x\n", + ainfo("STM32_ADC_CCR value: 0x%08" PRIx32 "\n", adccmn_getreg(priv, STM32_ADC_CCR_OFFSET)); #endif } @@ -3277,24 +3278,27 @@ static void adc_dumpregs(FAR struct stm32_dev_s *priv) UNUSED(priv); #if defined(HAVE_IP_ADC_V2) - ainfo("ISR: 0x%08x IER: 0x%08x CR: 0x%08x CFGR1: 0x%08x\n", + ainfo("ISR: 0x%08" PRIx32 " IER: 0x%08" PRIx32 + " CR: 0x%08" PRIx32 " CFGR1: 0x%08" PRIx32 "\n", adc_getreg(priv, STM32_ADC_ISR_OFFSET), adc_getreg(priv, STM32_ADC_IER_OFFSET), adc_getreg(priv, STM32_ADC_CR_OFFSET), adc_getreg(priv, STM32_ADC_CFGR1_OFFSET)); #else - ainfo("SR: 0x%08x CR1: 0x%08x CR2: 0x%08x\n", + ainfo("SR: 0x%08" PRIx32 " CR1: 0x%08" PRIx32 + " CR2: 0x%08" PRIx32 "\n", adc_getreg(priv, STM32_ADC_SR_OFFSET), adc_getreg(priv, STM32_ADC_CR1_OFFSET), adc_getreg(priv, STM32_ADC_CR2_OFFSET)); #endif - ainfo("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n", + ainfo("SQR1: 0x%08" PRIx32 " SQR2: 0x%08" PRIx32 + " SQR3: 0x%08" PRIx32 "\n", adc_getreg(priv, STM32_ADC_SQR1_OFFSET), adc_getreg(priv, STM32_ADC_SQR2_OFFSET), adc_getreg(priv, STM32_ADC_SQR3_OFFSET)); - ainfo("SMPR1: 0x%08x SMPR2: 0x%08x\n", + ainfo("SMPR1: 0x%08" PRIx32 " SMPR2: 0x%08" PRIx32 "\n", adc_getreg(priv, STM32_ADC_SMPR1_OFFSET), adc_getreg(priv, STM32_ADC_SMPR2_OFFSET)); @@ -3304,16 +3308,17 @@ static void adc_dumpregs(FAR struct stm32_dev_s *priv) #endif #if defined(STM32_ADC_SQR5_OFFSET) - ainfo("SQR5: 0x%08x\n", + ainfo("SQR5: 0x%08" PRIx32 "\n", adc_getreg(priv, STM32_ADC_SQR5_OFFSET)); #endif #ifdef ADC_HAVE_INJECTED - ainfo("JSQR: 0x%08x\n", adc_getreg(priv, STM32_ADC_JSQR_OFFSET)); + ainfo("JSQR: 0x%08" PRIx32 "\n", adc_getreg(priv, STM32_ADC_JSQR_OFFSET)); #endif #if defined(HAVE_IP_ADC_V2) || (defined(HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC)) - ainfo("CCR: 0x%08x\n", adccmn_getreg(priv, STM32_ADC_CCR_OFFSET)); + ainfo("CCR: 0x%08" PRIx32 "\n", + adccmn_getreg(priv, STM32_ADC_CCR_OFFSET)); #endif } diff --git a/arch/arm/src/stm32/stm32_aes.c b/arch/arm/src/stm32/stm32_aes.c index 70a258afaf5..cd4377a7720 100644 --- a/arch/arm/src/stm32/stm32_aes.c +++ b/arch/arm/src/stm32/stm32_aes.c @@ -152,7 +152,8 @@ static void stm32aes_setiv(FAR const void *iv) putreg32(__builtin_bswap32(*in), STM32_AES_IVR0); } -static void stm32aes_encryptblock(FAR void *block_out, FAR const void *block_in) +static void stm32aes_encryptblock(FAR void *block_out, + FAR const void *block_in) { FAR uint32_t *in = (FAR uint32_t *)block_in; FAR uint32_t *out = (FAR uint32_t *)block_out; @@ -292,7 +293,7 @@ int aes_cypher(FAR void *out, FAR const void *in, uint32_t size, g_stm32aes_initdone = true; } - if ((size & (AES_BLOCK_SIZE-1)) != 0) + if ((size & (AES_BLOCK_SIZE - 1)) != 0) { return -EINVAL; } diff --git a/arch/arm/src/stm32/stm32_bbsram.h b/arch/arm/src/stm32/stm32_bbsram.h index 2e1b602c604..ba74579bf1c 100644 --- a/arch/arm/src/stm32/stm32_bbsram.h +++ b/arch/arm/src/stm32/stm32_bbsram.h @@ -91,7 +91,7 @@ struct bbsramd_s { uint8_t flags; /* The crc is valid and the file was closed */ uint8_t fileno; /* The minor number */ - uint16_t len; /* Total Bytes in this file*/ + uint16_t len; /* Total Bytes in this file */ struct timespec lastwrite; /* Last write time */ }; @@ -111,6 +111,7 @@ extern "C" /**************************************************************************** * Public Function Prototypes ****************************************************************************/ + /**************************************************************************** * Function: stm32_bbsraminitialize * @@ -151,7 +152,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * * Assumptions: * -****************************************************************************/ +*****************************************************************************/ #if defined(CONFIG_STM32_SAVE_CRASHDUMP) int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length); diff --git a/arch/arm/src/stm32/stm32_can.c b/arch/arm/src/stm32/stm32_can.c index 658147936eb..a443b1d1129 100644 --- a/arch/arm/src/stm32/stm32_can.c +++ b/arch/arm/src/stm32/stm32_can.c @@ -69,6 +69,7 @@ ****************************************************************************/ /* Delays *******************************************************************/ + /* Time out for INAK bit */ #define INAK_TIMEOUT 65535 @@ -294,7 +295,7 @@ static uint32_t stm32can_vgetreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - caninfo("[repeats %d more times]\n", count-3); + caninfo("[repeats %d more times]\n", count - 3); } /* Save the new address, value, and count */ @@ -844,11 +845,15 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, DEBUGASSERT(bt != NULL); regval = stm32can_getreg(priv, STM32_CAN_BTR_OFFSET); - bt->bt_sjw = ((regval & CAN_BTR_SJW_MASK) >> CAN_BTR_SJW_SHIFT) + 1; - bt->bt_tseg1 = ((regval & CAN_BTR_TS1_MASK) >> CAN_BTR_TS1_SHIFT) + 1; - bt->bt_tseg2 = ((regval & CAN_BTR_TS2_MASK) >> CAN_BTR_TS2_SHIFT) + 1; + bt->bt_sjw = ((regval & CAN_BTR_SJW_MASK) >> + CAN_BTR_SJW_SHIFT) + 1; + bt->bt_tseg1 = ((regval & CAN_BTR_TS1_MASK) >> + CAN_BTR_TS1_SHIFT) + 1; + bt->bt_tseg2 = ((regval & CAN_BTR_TS2_MASK) >> + CAN_BTR_TS2_SHIFT) + 1; - brp = ((regval & CAN_BTR_BRP_MASK) >> CAN_BTR_BRP_SHIFT) + 1; + brp = ((regval & CAN_BTR_BRP_MASK) >> + CAN_BTR_BRP_SHIFT) + 1; bt->bt_baud = STM32_PCLK1_FREQUENCY / (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); ret = OK; @@ -865,11 +870,11 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, * to indicate thenature of the error. * Dependencies: None * - * REVISIT: There is probably a limitation here: If there are multiple - * threads trying to send CAN packets, when one of these threads - * reconfigures the bitrate, the MCAN hardware will be reset and the - * context of operation will be lost. Hence, this IOCTL can only safely - * be executed in quiescent time periods. + * REVISIT: There is probably a limitation here: If there are + * multiple threads trying to send CAN packets, when one of these + * threads reconfigures the bitrate, the MCAN hardware will be reset + * and the context of operation will be lost. Hence, this IOCTL can + * only safely be executed in quiescent time periods. */ case CANIOC_SET_BITTIMING: @@ -889,8 +894,9 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, regval = stm32can_getreg(priv, STM32_CAN_BTR_OFFSET); - /* Extract bit timing data */ - /* tmp is in clocks per bit time */ + /* Extract bit timing data + * tmp is in clocks per bit time + */ tmp = STM32_PCLK1_FREQUENCY / bt->bt_baud; @@ -913,7 +919,7 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, else { - brp = (tmp + (can_bit_quanta/2)) / can_bit_quanta; + brp = (tmp + (can_bit_quanta / 2)) / can_bit_quanta; DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); } @@ -1105,11 +1111,13 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, case CANIOC_SET_NART: { uint32_t regval; + ret = stm32can_enterinitmode(priv); if (ret != 0) { return ret; } + regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); if (arg == 1) { @@ -1119,6 +1127,7 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, { regval &= ~CAN_MCR_NART; } + stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); return stm32can_exitinitmode(priv); } @@ -1127,11 +1136,13 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, case CANIOC_SET_ABOM: { uint32_t regval; + ret = stm32can_enterinitmode(priv); if (ret != 0) { return ret; } + regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); if (arg == 1) { @@ -1141,6 +1152,7 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, { regval &= ~CAN_MCR_ABOM; } + stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); return stm32can_exitinitmode(priv); } @@ -1255,7 +1267,8 @@ static int stm32can_send(FAR struct can_dev_s *dev, regval |= msg->cm_hdr.ch_id << CAN_TIR_STID_SHIFT; } #else - regval |= ( ( (uint32_t) msg->cm_hdr.ch_id << CAN_TIR_STID_SHIFT) & CAN_TIR_STID_MASK ); + regval |= (((uint32_t) msg->cm_hdr.ch_id << CAN_TIR_STID_SHIFT) & + CAN_TIR_STID_MASK); #ifdef CONFIG_CAN_USE_RTR regval |= (msg->cm_hdr.ch_rtr ? CAN_TIR_RTR : 0); @@ -1745,16 +1758,16 @@ static int stm32can_bittiming(FAR struct stm32_can_s *priv) } } - /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32_CAN_TSEG1, ts2 is - * CONFIG_STM32_CAN_TSEG2 and we calculate brp to achieve CAN_BIT_QUANTA quanta - * in the bit time + /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32_CAN_TSEG1, + * ts2 is CONFIG_STM32_CAN_TSEG2 and we calculate brp to achieve + * CAN_BIT_QUANTA quanta in the bit time */ else { ts1 = CONFIG_STM32_CAN_TSEG1; ts2 = CONFIG_STM32_CAN_TSEG2; - brp = (tmp + (CAN_BIT_QUANTA/2)) / CAN_BIT_QUANTA; + brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA; DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); } @@ -1773,7 +1786,8 @@ static int stm32can_bittiming(FAR struct stm32_can_s *priv) tmp = ((brp - 1) << CAN_BTR_BRP_SHIFT) | ((ts1 - 1) << CAN_BTR_TS1_SHIFT) | ((ts2 - 1) << CAN_BTR_TS2_SHIFT) | ((1 - 1) << CAN_BTR_SJW_SHIFT); #ifdef CONFIG_CAN_LOOPBACK -//tmp |= (CAN_BTR_LBKM | CAN_BTR_SILM); + /* tmp |= (CAN_BTR_LBKM | CAN_BTR_SILM); */ + tmp |= CAN_BTR_LBKM; #endif diff --git a/arch/arm/src/stm32/stm32_capture.c b/arch/arm/src/stm32/stm32_capture.c index d31a3554aa8..ffd314084ba 100644 --- a/arch/arm/src/stm32/stm32_capture.c +++ b/arch/arm/src/stm32/stm32_capture.c @@ -321,7 +321,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv, break; #endif -/* TIM6 and TIM7 cannot be used in capture */ + /* TIM6 and TIM7 cannot be used in capture */ #ifdef CONFIG_STM32_TIM8_CAP case STM32_TIM8_BASE: @@ -519,6 +519,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv, break; #endif } + return 0; } @@ -623,6 +624,7 @@ static inline int stm32_cap_set_rcc(FAR const struct stm32_cap_priv_s *priv, return OK; } + /************************************************************************************ * Basic Functions ************************************************************************************/ @@ -731,6 +733,7 @@ static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler, irq_detach(irq_of); } #endif + return OK; } @@ -902,7 +905,6 @@ static stm32_cap_flags_t stm32_cap_getflags(FAR struct stm32_cap_dev_s *dev) } return flags; - } /************************************************************************************ @@ -1015,7 +1017,8 @@ static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev, uint8_t channel return OK; } -static uint32_t stm32_cap_getcapture(FAR struct stm32_cap_dev_s *dev, uint8_t channel) +static uint32_t stm32_cap_getcapture(FAR struct stm32_cap_dev_s *dev, + uint8_t channel) { const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev; uint32_t offset; diff --git a/arch/arm/src/stm32/stm32_dbgmcu.h b/arch/arm/src/stm32/stm32_dbgmcu.h index d9e1886bb7d..1c6e7f7fd66 100644 --- a/arch/arm/src/stm32/stm32_dbgmcu.h +++ b/arch/arm/src/stm32/stm32_dbgmcu.h @@ -58,7 +58,7 @@ ************************************************************************************/ /************************************************************************************ - * Public Functions + * Public Function Prototypes ************************************************************************************/ #endif /* __ARCH_ARM_SRC_STM32_STM32_DBGMCU_H */ diff --git a/arch/arm/src/stm32/stm32_dma_v1.c b/arch/arm/src/stm32/stm32_dma_v1.c index d40ddca3445..d0e5582748c 100644 --- a/arch/arm/src/stm32/stm32_dma_v1.c +++ b/arch/arm/src/stm32/stm32_dma_v1.c @@ -743,7 +743,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) ****************************************************************************/ #ifdef CONFIG_STM32_DMACAPABLE -bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) +bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) { uint32_t transfer_size; uint32_t mend; diff --git a/arch/arm/src/stm32/stm32_dma_v2.c b/arch/arm/src/stm32/stm32_dma_v2.c index b02ec5aaf01..bd0dabbac7b 100644 --- a/arch/arm/src/stm32/stm32_dma_v2.c +++ b/arch/arm/src/stm32/stm32_dma_v2.c @@ -39,6 +39,7 @@ #include +#include #include #include #include @@ -597,7 +598,8 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, uint32_t regoffset; uint32_t regval; - dmainfo("paddr: %08x maddr: %08x ntransfers: %d scr: %08x\n", + dmainfo("paddr: %08" PRIx32 " maddr: %08" PRIx32 + " ntransfers: %zu scr: %08" PRIx32 "\n", paddr, maddr, ntransfers, scr); #ifdef CONFIG_STM32_DMACAPABLE @@ -864,7 +866,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) ****************************************************************************/ #ifdef CONFIG_STM32_DMACAPABLE -bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) +bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) { uint32_t transfer_size; uint32_t burst_length; diff --git a/arch/arm/src/stm32/stm32_i2c_alt.c b/arch/arm/src/stm32/stm32_i2c_alt.c index a64aa818098..3627833eae8 100644 --- a/arch/arm/src/stm32/stm32_i2c_alt.c +++ b/arch/arm/src/stm32/stm32_i2c_alt.c @@ -81,6 +81,7 @@ #include #include +#include #include #include #include @@ -673,7 +674,7 @@ static int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv) while (priv->intstate != INTSTATE_DONE && elapsed < timeout); - i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: %08x\n", + i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: %08" PRIx32 "\n", priv->intstate, (long)elapsed, (long)timeout, priv->status); /* Set the interrupt state back to IDLE */ @@ -746,7 +747,7 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv) * still pending. */ - i2cinfo("Timeout with CR1: %04x SR1: %04x\n", cr1, sr1); + i2cinfo("Timeout with CR1: %04" PRIx32 " SR1: %04" PRIx32 "\n", cr1, sr1); } /************************************************************************************ @@ -1295,7 +1296,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) { /* Start bit is set */ - i2cinfo("Entering address handling, status = %i\n", status); + i2cinfo("Entering address handling, status = %" PRIi32 "\n", status); /* Check for empty message (for robustness) */ @@ -1637,7 +1638,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) * (RXNE is set) then the driver can read from the data register. */ - i2cinfo("Entering read mode dcnt = %i msgc = %i, status %i\n", + i2cinfo("Entering read mode dcnt = %i msgc = %i, status %" PRIi32 "\n", priv->dcnt, priv->msgc, status); /* Implementation of method 2 for receiving data following @@ -1770,7 +1771,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) else { i2cerr("ERROR: I2C read mode no correct state detected\n"); - i2cerr(" state %i, dcnt=%i\n", status, priv->dcnt); + i2cerr(" state %" PRIi32 ", dcnt=%i\n", status, priv->dcnt); /* set condition to terminate ISR and wake waiting thread */ @@ -2096,7 +2097,7 @@ static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, status = stm32_i2c_getstatus(priv); ret = -ETIMEDOUT; - i2cerr("ERROR: Timed out: CR1: 0x%04x status: 0x%08x\n", + i2cerr("ERROR: Timed out: CR1: 0x%04x status: 0x%08" PRIx32 "\n", stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status); /* "Note: When the STOP, START or PEC bit is set, the software must diff --git a/arch/arm/src/stm32/stm32_lsi.c b/arch/arm/src/stm32/stm32_lsi.c index a6e7ddc3829..ba219762e89 100644 --- a/arch/arm/src/stm32/stm32_lsi.c +++ b/arch/arm/src/stm32/stm32_lsi.c @@ -69,8 +69,8 @@ void stm32_rcc_enablelsi(void) { - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION bit - * the RCC CSR register. + /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION + * bit in the RCC CSR register. */ modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); @@ -90,8 +90,8 @@ void stm32_rcc_enablelsi(void) void stm32_rcc_disablelsi(void) { - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION bit - * the RCC CSR register. + /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION + * bit in the RCC CSR register. */ modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); diff --git a/arch/arm/src/stm32/stm32_oneshot.c b/arch/arm/src/stm32/stm32_oneshot.c index 9e92e09d054..3ee6fe59ff0 100644 --- a/arch/arm/src/stm32/stm32_oneshot.c +++ b/arch/arm/src/stm32/stm32_oneshot.c @@ -275,7 +275,8 @@ int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, irqstate_t flags; tmrinfo("handler=%p arg=%p, ts=(%lu, %lu)\n", - handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + handler, arg, (unsigned long)ts->tv_sec, + (unsigned long)ts->tv_nsec); DEBUGASSERT(oneshot && handler && ts); DEBUGASSERT(oneshot->tch); diff --git a/arch/arm/src/stm32/stm32_oneshot.h b/arch/arm/src/stm32/stm32_oneshot.h index d32c924a79b..f0243c34f53 100644 --- a/arch/arm/src/stm32/stm32_oneshot.h +++ b/arch/arm/src/stm32/stm32_oneshot.h @@ -80,9 +80,9 @@ typedef void (*oneshot_handler_t)(void *arg); /* The oneshot client must allocate an instance of this structure and called - * stm32_oneshot_initialize() before using the oneshot facilities. The client - * should not access the contents of this structure directly since the - * contents are subject to change. + * stm32_oneshot_initialize() before using the oneshot facilities. The + * client should not access the contents of this structure directly since + * the contents are subject to change. */ struct stm32_oneshot_s diff --git a/arch/arm/src/stm32/stm32_oneshot_lowerhalf.c b/arch/arm/src/stm32/stm32_oneshot_lowerhalf.c index 4ea7b2bf857..39954f45a7b 100644 --- a/arch/arm/src/stm32/stm32_oneshot_lowerhalf.c +++ b/arch/arm/src/stm32/stm32_oneshot_lowerhalf.c @@ -54,7 +54,8 @@ * Private Types ****************************************************************************/ -/* This structure describes the state of the oneshot timer lower-half driver */ +/* This structure describes the state of the oneshot timer lower-half driver + */ struct stm32_oneshot_lowerhalf_s { diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/stm32/stm32_otgfsdev.c index 63fee03e5e2..13ef993f92a 100644 --- a/arch/arm/src/stm32/stm32_otgfsdev.c +++ b/arch/arm/src/stm32/stm32_otgfsdev.c @@ -41,6 +41,7 @@ #include #include +#include #include #include #include @@ -68,7 +69,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Configuration ***************************************************************/ +/* Configuration ************************************************************/ #ifndef CONFIG_USBDEV_EP0_MAXSIZE # define CONFIG_USBDEV_EP0_MAXSIZE 64 @@ -118,7 +119,8 @@ # error "FIFO allocations exceed FIFO memory size" #endif -/* The actual FIFO addresses that we use must be aligned to 4-byte boundaries; +/* The actual FIFO addresses that we use must be aligned to 4-byte + * boundaries; * FIFO sizes must be provided in units of 32-bit words. */ @@ -196,7 +198,7 @@ OTGFS_GINT_WKUP) #endif -/* Debug ***********************************************************************/ +/* Debug ********************************************************************/ /* Trace error codes */ @@ -283,7 +285,7 @@ #define STM32_TRACEINTID_SETUPDONE (90 + 3) #define STM32_TRACEINTID_SETUPRECVD (90 + 4) -/* Endpoints ******************************************************************/ +/* Endpoints ****************************************************************/ /* Number of endpoints */ @@ -306,17 +308,17 @@ #define STM32_MAXPACKET (64) /* Max packet size (1-64) */ -/* Delays **********************************************************************/ +/* Delays *******************************************************************/ #define STM32_READY_DELAY 200000 #define STM32_FLUSH_DELAY 200000 -/* Request queue operations ****************************************************/ +/* Request queue operations *************************************************/ #define stm32_rqempty(ep) ((ep)->head == NULL) #define stm32_rqpeek(ep) ((ep)->head) -/* Standard stuff **************************************************************/ +/* Standard stuff ***********************************************************/ #ifndef MIN # define MIN(a,b) ((a) < (b) ? (a) : (b)) @@ -520,7 +522,7 @@ struct stm32_usbdev_s * Private Function Prototypes ****************************************************************************/ -/* Register operations ********************************************************/ +/* Register operations ******************************************************/ #ifdef CONFIG_STM32_USBDEV_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); @@ -530,13 +532,14 @@ static void stm32_putreg(uint32_t val, uint32_t addr); # define stm32_putreg(val,addr) putreg32(val,addr) #endif -/* Request queue operations ****************************************************/ +/* Request queue operations *************************************************/ -static FAR struct stm32_req_s *stm32_req_remfirst(FAR struct stm32_ep_s *privep); +static FAR struct stm32_req_s *stm32_req_remfirst( + FAR struct stm32_ep_s *privep); static bool stm32_req_addlast(FAR struct stm32_ep_s *privep, FAR struct stm32_req_s *req); -/* Low level data transfers and request operations *****************************/ +/* Low level data transfers and request operations **************************/ /* Special endpoint 0 data transfer logic */ @@ -560,11 +563,14 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, static void stm32_rxfifo_read(FAR struct stm32_ep_s *privep, FAR uint8_t *dest, uint16_t len); -static void stm32_rxfifo_discard(FAR struct stm32_ep_s *privep, int len); +static void stm32_rxfifo_discard(FAR struct stm32_ep_s *privep, + int len); static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv, FAR struct stm32_ep_s *privep); -static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt); -static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt); +static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, + int bcnt); +static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, + int bcnt); static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, FAR struct stm32_ep_s *privep); @@ -576,10 +582,11 @@ static void stm32_req_complete(FAR struct stm32_ep_s *privep, static void stm32_req_cancel(FAR struct stm32_ep_s *privep, int16_t status); -/* Interrupt handling **********************************************************/ +/* Interrupt handling *******************************************************/ -static struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, - uint16_t eplog); +static struct stm32_ep_s *stm32_ep_findbyaddr( + struct stm32_usbdev_s *priv, + uint16_t eplog); static int stm32_req_dispatch(FAR struct stm32_usbdev_s *priv, FAR const struct usb_ctrlreq_s *ctrl); static void stm32_usbreset(FAR struct stm32_usbdev_s *priv); @@ -599,7 +606,8 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv); static inline void stm32_epin_runtestmode(FAR struct stm32_usbdev_s *priv); static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno); -static inline void stm32_epin_txfifoempty(FAR struct stm32_usbdev_s *priv, int epno); +static inline void stm32_epin_txfifoempty(FAR struct stm32_usbdev_s *priv, + int epno); static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv); /* Other second level interrupt processing */ @@ -619,9 +627,10 @@ static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv); /* First level interrupt processing */ -static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg); +static int stm32_usbinterrupt(int irq, FAR void *context, + FAR void *arg); -/* Endpoint operations *********************************************************/ +/* Endpoint operations ******************************************************/ /* Global OUT NAK controls */ @@ -646,15 +655,18 @@ static int stm32_ep_disable(FAR struct usbdev_ep_s *ep); /* Endpoint request management */ -static FAR struct usbdev_req_s *stm32_ep_allocreq(FAR struct usbdev_ep_s *ep); +static FAR struct usbdev_req_s *stm32_ep_allocreq( + FAR struct usbdev_ep_s *ep); static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *); /* Endpoint buffer management */ #ifdef CONFIG_USBDEV_DMA -static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, uint16_t bytes); -static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf); +static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, + uint16_t bytes); +static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, + FAR void *buf); #endif /* Endpoint request submission */ @@ -683,7 +695,7 @@ static FAR struct usbdev_ep_s *stm32_ep_alloc(FAR struct usbdev_s *dev, static void stm32_ep_free(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep); -/* USB device controller operations ********************************************/ +/* USB device controller operations *****************************************/ static int stm32_getframe(struct usbdev_s *dev); static int stm32_wakeup(struct usbdev_s *dev); @@ -694,7 +706,7 @@ static void stm32_setaddress(struct stm32_usbdev_s *priv, static int stm32_txfifo_flush(uint32_t txfnum); static int stm32_rxfifo_flush(void); -/* Initialization **************************************************************/ +/* Initialization ***********************************************************/ static void stm32_swinitialize(FAR struct stm32_usbdev_s *priv); static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv); @@ -741,37 +753,37 @@ static const struct usbdev_ops_s g_devops = #ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_deverror[] = { - TRACE_STR(STM32_TRACEERR_ALLOCFAIL ), - TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE ), - TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS ), - TRACE_STR(STM32_TRACEERR_BADEPNO ), - TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS ), - TRACE_STR(STM32_TRACEERR_BADGETCONFIG ), - TRACE_STR(STM32_TRACEERR_BADGETSETDESC ), - TRACE_STR(STM32_TRACEERR_BADGETSTATUS ), - TRACE_STR(STM32_TRACEERR_BADSETADDRESS ), - TRACE_STR(STM32_TRACEERR_BADSETCONFIG ), - TRACE_STR(STM32_TRACEERR_BADSETFEATURE ), - TRACE_STR(STM32_TRACEERR_BADTESTMODE ), - TRACE_STR(STM32_TRACEERR_BINDFAILED ), - TRACE_STR(STM32_TRACEERR_DISPATCHSTALL ), - TRACE_STR(STM32_TRACEERR_DRIVER ), + TRACE_STR(STM32_TRACEERR_ALLOCFAIL), + TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE), + TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADEPNO), + TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADGETCONFIG), + TRACE_STR(STM32_TRACEERR_BADGETSETDESC), + TRACE_STR(STM32_TRACEERR_BADGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADSETADDRESS), + TRACE_STR(STM32_TRACEERR_BADSETCONFIG), + TRACE_STR(STM32_TRACEERR_BADSETFEATURE), + TRACE_STR(STM32_TRACEERR_BADTESTMODE), + TRACE_STR(STM32_TRACEERR_BINDFAILED), + TRACE_STR(STM32_TRACEERR_DISPATCHSTALL), + TRACE_STR(STM32_TRACEERR_DRIVER), TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED), - TRACE_STR(STM32_TRACEERR_EP0NOSETUP ), - TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED ), - TRACE_STR(STM32_TRACEERR_EPINNULLPACKET ), - TRACE_STR(STM32_TRACEERR_EPINUNEXPECTED ), - TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET ), - TRACE_STR(STM32_TRACEERR_EPOUTUNEXPECTED ), - TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ ), - TRACE_STR(STM32_TRACEERR_INVALIDPARMS ), - TRACE_STR(STM32_TRACEERR_IRQREGISTRATION ), - TRACE_STR(STM32_TRACEERR_NOEP ), - TRACE_STR(STM32_TRACEERR_NOTCONFIGURED ), - TRACE_STR(STM32_TRACEERR_EPOUTQEMPTY ), - TRACE_STR(STM32_TRACEERR_EPINREQEMPTY ), - TRACE_STR(STM32_TRACEERR_NOOUTSETUP ), - TRACE_STR(STM32_TRACEERR_POLLTIMEOUT ), + TRACE_STR(STM32_TRACEERR_EP0NOSETUP), + TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED), + TRACE_STR(STM32_TRACEERR_EPINNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPINUNEXPECTED), + TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPOUTUNEXPECTED), + TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ), + TRACE_STR(STM32_TRACEERR_INVALIDPARMS), + TRACE_STR(STM32_TRACEERR_IRQREGISTRATION), + TRACE_STR(STM32_TRACEERR_NOEP), + TRACE_STR(STM32_TRACEERR_NOTCONFIGURED), + TRACE_STR(STM32_TRACEERR_EPOUTQEMPTY), + TRACE_STR(STM32_TRACEERR_EPINREQEMPTY), + TRACE_STR(STM32_TRACEERR_NOOUTSETUP), + TRACE_STR(STM32_TRACEERR_POLLTIMEOUT), TRACE_STR_END }; #endif @@ -783,48 +795,48 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = #ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_intdecode[] = { - TRACE_STR(STM32_TRACEINTID_USB ), - TRACE_STR(STM32_TRACEINTID_INTPENDING ), - TRACE_STR(STM32_TRACEINTID_EPOUT ), - TRACE_STR(STM32_TRACEINTID_EPIN ), - TRACE_STR(STM32_TRACEINTID_MISMATCH ), - TRACE_STR(STM32_TRACEINTID_WAKEUP ), - TRACE_STR(STM32_TRACEINTID_SUSPEND ), - TRACE_STR(STM32_TRACEINTID_SOF ), - TRACE_STR(STM32_TRACEINTID_RXFIFO ), - TRACE_STR(STM32_TRACEINTID_DEVRESET ), - TRACE_STR(STM32_TRACEINTID_ENUMDNE ), - TRACE_STR(STM32_TRACEINTID_IISOIXFR ), - TRACE_STR(STM32_TRACEINTID_IISOOXFR ), - TRACE_STR(STM32_TRACEINTID_SRQ ), - TRACE_STR(STM32_TRACEINTID_OTG ), - TRACE_STR(STM32_TRACEINTID_EPOUT_XFRC ), + TRACE_STR(STM32_TRACEINTID_USB), + TRACE_STR(STM32_TRACEINTID_INTPENDING), + TRACE_STR(STM32_TRACEINTID_EPOUT), + TRACE_STR(STM32_TRACEINTID_EPIN), + TRACE_STR(STM32_TRACEINTID_MISMATCH), + TRACE_STR(STM32_TRACEINTID_WAKEUP), + TRACE_STR(STM32_TRACEINTID_SUSPEND), + TRACE_STR(STM32_TRACEINTID_SOF), + TRACE_STR(STM32_TRACEINTID_RXFIFO), + TRACE_STR(STM32_TRACEINTID_DEVRESET), + TRACE_STR(STM32_TRACEINTID_ENUMDNE), + TRACE_STR(STM32_TRACEINTID_IISOIXFR), + TRACE_STR(STM32_TRACEINTID_IISOOXFR), + TRACE_STR(STM32_TRACEINTID_SRQ), + TRACE_STR(STM32_TRACEINTID_OTG), + TRACE_STR(STM32_TRACEINTID_EPOUT_XFRC), TRACE_STR(STM32_TRACEINTID_EPOUT_EPDISD), - TRACE_STR(STM32_TRACEINTID_EPOUT_SETUP ), - TRACE_STR(STM32_TRACEINTID_DISPATCH ), - TRACE_STR(STM32_TRACEINTID_GETSTATUS ), - TRACE_STR(STM32_TRACEINTID_EPGETSTATUS ), + TRACE_STR(STM32_TRACEINTID_EPOUT_SETUP), + TRACE_STR(STM32_TRACEINTID_DISPATCH), + TRACE_STR(STM32_TRACEINTID_GETSTATUS), + TRACE_STR(STM32_TRACEINTID_EPGETSTATUS), TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS), - TRACE_STR(STM32_TRACEINTID_IFGETSTATUS ), + TRACE_STR(STM32_TRACEINTID_IFGETSTATUS), TRACE_STR(STM32_TRACEINTID_CLEARFEATURE), - TRACE_STR(STM32_TRACEINTID_SETFEATURE ), - TRACE_STR(STM32_TRACEINTID_SETADDRESS ), - TRACE_STR(STM32_TRACEINTID_GETSETDESC ), - TRACE_STR(STM32_TRACEINTID_GETCONFIG ), - TRACE_STR(STM32_TRACEINTID_SETCONFIG ), - TRACE_STR(STM32_TRACEINTID_GETSETIF ), - TRACE_STR(STM32_TRACEINTID_SYNCHFRAME ), - TRACE_STR(STM32_TRACEINTID_EPIN_XFRC ), - TRACE_STR(STM32_TRACEINTID_EPIN_TOC ), - TRACE_STR(STM32_TRACEINTID_EPIN_ITTXFE ), - TRACE_STR(STM32_TRACEINTID_EPIN_EPDISD ), - TRACE_STR(STM32_TRACEINTID_EPIN_TXFE ), + TRACE_STR(STM32_TRACEINTID_SETFEATURE), + TRACE_STR(STM32_TRACEINTID_SETADDRESS), + TRACE_STR(STM32_TRACEINTID_GETSETDESC), + TRACE_STR(STM32_TRACEINTID_GETCONFIG), + TRACE_STR(STM32_TRACEINTID_SETCONFIG), + TRACE_STR(STM32_TRACEINTID_GETSETIF), + TRACE_STR(STM32_TRACEINTID_SYNCHFRAME), + TRACE_STR(STM32_TRACEINTID_EPIN_XFRC), + TRACE_STR(STM32_TRACEINTID_EPIN_TOC), + TRACE_STR(STM32_TRACEINTID_EPIN_ITTXFE), + TRACE_STR(STM32_TRACEINTID_EPIN_EPDISD), + TRACE_STR(STM32_TRACEINTID_EPIN_TXFE), TRACE_STR(STM32_TRACEINTID_EPIN_EMPWAIT), - TRACE_STR(STM32_TRACEINTID_OUTNAK ), - TRACE_STR(STM32_TRACEINTID_OUTRECVD ), - TRACE_STR(STM32_TRACEINTID_OUTDONE ), - TRACE_STR(STM32_TRACEINTID_SETUPDONE ), - TRACE_STR(STM32_TRACEINTID_SETUPRECVD ), + TRACE_STR(STM32_TRACEINTID_OUTNAK), + TRACE_STR(STM32_TRACEINTID_OUTRECVD), + TRACE_STR(STM32_TRACEINTID_OUTDONE), + TRACE_STR(STM32_TRACEINTID_SETUPDONE), + TRACE_STR(STM32_TRACEINTID_SETUPRECVD), TRACE_STR_END }; #endif @@ -856,8 +868,8 @@ static uint32_t stm32_getreg(uint32_t addr) uint32_t val = getreg32(addr); - /* Is this the same value that we read from the same register last time? Are - * we polling the register? If so, suppress some of the output. + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. */ if (addr == prevaddr && val == preval) @@ -883,7 +895,7 @@ static uint32_t stm32_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - uinfo("[repeats %d more times]\n", count-3); + uinfo("[repeats %d more times]\n", count - 3); } /* Save the new address, value, and count */ @@ -929,7 +941,8 @@ static void stm32_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -static FAR struct stm32_req_s *stm32_req_remfirst(FAR struct stm32_ep_s *privep) +static FAR struct stm32_req_s *stm32_req_remfirst( + FAR struct stm32_ep_s *privep) { FAR struct stm32_req_s *ret = privep->head; @@ -971,6 +984,7 @@ static bool stm32_req_addlast(FAR struct stm32_ep_s *privep, privep->tail->flink = req; privep->tail = req; } + return is_empty; } @@ -1137,7 +1151,9 @@ static void stm32_epin_transfer(FAR struct stm32_ep_s *privep, if (nbytes == 0) { - /* Yes.. leave the transfer size at zero and set the packet count to 1 */ + /* Yes.. leave the transfer size at zero and set the packet count to + * 1 + */ pktcnt = 1; } @@ -1150,7 +1166,8 @@ static void stm32_epin_transfer(FAR struct stm32_ep_s *privep, * perform the transfer. */ - pktcnt = ((uint32_t)nbytes + (privep->ep.maxpacket - 1)) / privep->ep.maxpacket; + pktcnt = ((uint32_t)nbytes + (privep->ep.maxpacket - 1)) / + privep->ep.maxpacket; } /* Set the XFRSIZ and PKTCNT */ @@ -1203,8 +1220,8 @@ static void stm32_epin_transfer(FAR struct stm32_ep_s *privep, stm32_putreg(regval, STM32_OTGFS_DIEPCTL(privep->epphy)); /* Transfer the data to the TxFIFO. At this point, the caller has already - * assured that there is sufficient space in the TxFIFO to hold the transfer - * we can just blindly continue. + * assured that there is sufficient space in the TxFIFO to hold the + * transfer we can just blindly continue. */ stm32_txfifo_write(privep, buf, nbytes); @@ -1275,9 +1292,9 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, privep->epphy, privreq, privreq->req.len, privreq->req.xfrd, privep->zlp); - /* Check for a special case: If we are just starting a request (xfrd==0) and - * the class driver is trying to send a zero-length packet (len==0). Then set - * the ZLP flag so that the packet will be sent. + /* Check for a special case: If we are just starting a request (xfrd==0) + * and the class driver is trying to send a zero-length packet (len==0). + * Then set the ZLP flag so that the packet will be sent. */ if (privreq->req.len == 0) @@ -1373,7 +1390,8 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, regval = stm32_getreg(regaddr); if ((int)(regval & OTGFS_DTXFSTS_MASK) < nwords) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EMPWAIT), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EMPWAIT), + (uint16_t)regval); /* There is insufficient space in the TxFIFO. Wait for a TxFIFO * empty interrupt and try again. @@ -1413,9 +1431,10 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, privreq->req.xfrd += nbytes; } - /* Note that the ZLP, if any, must be sent as a separate transfer. The need - * for a ZLP is indicated by privep->zlp. If all of the bytes were sent - * (including any final null packet) then we are finished with the transfer + /* Note that the ZLP, if any, must be sent as a separate transfer. The + * need for a ZLP is indicated by privep->zlp. If all of the bytes were + * sent (including any final null packet) then we are finished with the + * transfer */ if (privreq->req.xfrd >= privreq->req.len && !privep->zlp) @@ -1450,7 +1469,9 @@ static void stm32_rxfifo_read(FAR struct stm32_ep_s *privep, regaddr = STM32_OTGFS_DFIFO_DEP(EP0); - /* Read 32-bits and write 4 x 8-bits at time (to avoid unaligned accesses) */ + /* Read 32-bits and write 4 x 8-bits at time (to avoid unaligned + * accesses) + */ for (i = 0; i < len; i += 4) { @@ -1519,8 +1540,8 @@ static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv, { struct stm32_req_s *privreq; - /* Since a transfer just completed, there must be a read request at the head of - * the endpoint request queue. + /* Since a transfer just completed, there must be a read request at the + * head of the endpoint request queue. */ privreq = stm32_rqpeek(privep); @@ -1557,13 +1578,14 @@ static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv, * Name: stm32_ep0out_receive * * Description: - * This function is called from the RXFLVL interrupt handler when new incoming - * data is available in the endpoint's RxFIFO. This function will simply - * copy the incoming data into pending request's data buffer. + * This function is called from the RXFLVL interrupt handler when new + * incoming data is available in the endpoint's RxFIFO. This function + * will simply copy the incoming data into pending request's data buffer. * ****************************************************************************/ -static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt) +static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, + int bcnt) { FAR struct stm32_usbdev_s *priv; @@ -1615,13 +1637,14 @@ static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt) * Name: stm32_epout_receive * * Description: - * This function is called from the RXFLVL interrupt handler when new incoming - * data is available in the endpoint's RxFIFO. This function will simply - * copy the incoming data into pending request's data buffer. + * This function is called from the RXFLVL interrupt handler when new + * incoming data is available in the endpoint's RxFIFO. This function + * will simply copy the incoming data into pending request's data buffer. * ****************************************************************************/ -static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt) +static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, + int bcnt) { struct stm32_req_s *privreq; uint8_t *dest; @@ -1637,7 +1660,8 @@ static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt) { /* Incoming data is available in the RxFIFO, but there is no read setup * to receive the receive the data. This should not happen for data - * endpoints; those endpoints should have been NAKing any OUT data tokens. + * endpoints; those endpoints should have been NAKing any OUT data + * tokens. * * We should get here normally on OUT data phase following an OUT * SETUP command. EP0 data will still receive data in this case and it @@ -1654,7 +1678,8 @@ static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt) * NAKing is working as expected. */ - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), + privep->epphy); /* Discard the data in the RxFIFO */ @@ -1699,8 +1724,8 @@ static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt) * * Description: * This function is called when either (1) new read request is received, or - * (2) a pending receive request completes. If there is no read in pending, - * then this function will initiate the next OUT (read) operation. + * (2) a pending receive request completes. If there is no read in + * pending, then this function will initiate the next OUT (read) operation. * ****************************************************************************/ @@ -1713,30 +1738,34 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, uint32_t xfrsize; uint32_t pktcnt; - /* Make sure that there is not already a pending request request. If there is, - * just return, leaving the newly received request in the request queue. + /* Make sure that there is not already a pending request request. If + * there is, just return, leaving the newly received request in the + * request queue. */ if (!privep->active) { /* Loop until a valid request is found (or the request queue is empty). - * The loop is only need to look at the request queue again is an invalid - * read request is encountered. + * The loop is only need to look at the request queue again is an + * invalid read request is encountered. */ for (; ; ) { - /* Get a reference to the request at the head of the endpoint's request queue */ + /* Get a reference to the request at the head of the endpoint's + * request queue + */ privreq = stm32_rqpeek(privep); if (!privreq) { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), + privep->epphy); - /* There are no read requests to be setup. Configure the hardware to - * NAK any incoming packets. (This should already be the case. I - * think that the hardware will automatically NAK after a transfer is - * completed until SNAK is cleared). + /* There are no read requests to be setup. Configure the + * hardware to NAK any incoming packets. (This should already + * be the case. I think that the hardware will automatically + * NAK after a transfer is completed until SNAK is cleared). */ regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); @@ -1762,7 +1791,9 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, stm32_req_complete(privep, OK); } - /* Otherwise, we have a usable read request... break out of the loop */ + /* Otherwise, we have a usable read request... break out of the + * loop + */ else { @@ -1778,7 +1809,8 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, * maxpacket bytes). */ - pktcnt = (privreq->req.len + (privep->ep.maxpacket - 1)) / privep->ep.maxpacket; + pktcnt = (privreq->req.len + (privep->ep.maxpacket - 1)) / + privep->ep.maxpacket; xfrsize = pktcnt * privep->ep.maxpacket; /* Then setup the hardware to perform this transfer */ @@ -1857,7 +1889,8 @@ static void stm32_ep_flush(struct stm32_ep_s *privep) * Name: stm32_req_complete * * Description: - * Handle termination of the request at the head of the endpoint request queue. + * Handle termination of the request at the head of the endpoint request + * queue. * ****************************************************************************/ @@ -1957,8 +1990,8 @@ static struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, * Name: stm32_req_dispatch * * Description: - * Provide unhandled setup actions to the class driver. This is logically part - * of the USB interrupt handler. + * Provide unhandled setup actions to the class driver. This is logically + * part of the USB interrupt handler. * ****************************************************************************/ @@ -2142,7 +2175,8 @@ static inline void stm32_ep0out_testmode(FAR struct stm32_usbdev_s *priv, ****************************************************************************/ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, - FAR struct stm32_ctrlreq_s *ctrlreq) + FAR struct stm32_ctrlreq_s * + ctrlreq) { FAR struct stm32_ep_s *privep; @@ -2176,7 +2210,8 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, privep = stm32_ep_findbyaddr(priv, ctrlreq->index); if (!privep) { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), + 0); priv->stalled = true; } else @@ -2200,19 +2235,25 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, { if (ctrlreq->index == 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVGETSTATUS), 0); + usbtrace(TRACE_INTDECODE( + STM32_TRACEINTID_DEVGETSTATUS), + 0); /* Features: Remote Wakeup and self-powered */ - priv->ep0data[0] = (priv->selfpowered << USB_FEATURE_SELFPOWERED); - priv->ep0data[0] |= (priv->wakeup << USB_FEATURE_REMOTEWAKEUP); + priv->ep0data[0] = (priv->selfpowered << + USB_FEATURE_SELFPOWERED); + priv->ep0data[0] |= (priv->wakeup << + USB_FEATURE_REMOTEWAKEUP); priv->ep0data[1] = 0; stm32_ep0in_setupresponse(priv, priv->ep0data, 2); } else { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADDEVGETSTATUS), 0); + usbtrace(TRACE_DEVERROR( + STM32_TRACEERR_BADDEVGETSTATUS), + 0); priv->stalled = true; } } @@ -2338,15 +2379,17 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETADDRESS), ctrlreq->value); - if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETADDRESS), + ctrlreq->value); + if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && ctrlreq->index == 0 && ctrlreq->len == 0 && ctrlreq->value < 128 && priv->devstate != DEVSTATE_CONFIGURED) { - /* Save the address. We cannot actually change to the next address until - * the completion of the status phase. + /* Save the address. We cannot actually change to the next + * address until the completion of the status phase. */ stm32_setaddress(priv, (uint16_t)priv->ctrlreq.value[0]); @@ -2376,7 +2419,8 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), 0); - if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) + if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) { stm32_req_dispatch(priv, &priv->ctrlreq); } @@ -2398,7 +2442,8 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), 0); if (priv->addressed && - (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && + (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && ctrlreq->value == 0 && ctrlreq->index == 0 && ctrlreq->len == 1) @@ -2423,7 +2468,8 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), 0); if (priv->addressed && - (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && + (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && ctrlreq->index == 0 && ctrlreq->len == 0) { @@ -2545,7 +2591,8 @@ static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv) ctrlreq.len = GETUINT16(priv->ctrlreq.len); uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n", - ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len); + ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, + ctrlreq.len); /* Check for a standard request */ @@ -2566,13 +2613,14 @@ static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv) if (priv->stalled) { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), priv->ep0state); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), + priv->ep0state); stm32_ep0_stall(priv); } /* Reset state/data associated with the SETUP request */ - priv->ep0datlen = 0; + priv->ep0datlen = 0; } /**************************************************************************** @@ -2631,12 +2679,13 @@ static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, uint8_t epno) * Name: stm32_epout_interrupt * * Description: - * USB OUT endpoint interrupt handler. The core generates this interrupt when - * there is an interrupt is pending on one of the OUT endpoints of the core. - * The driver must read the OTGFS DAINT register to determine the exact number - * of the OUT endpoint on which the interrupt occurred, and then read the - * corresponding OTGFS DOEPINTx register to determine the exact cause of the - * interrupt. + * USB OUT endpoint interrupt handler. The core generates this interrupt + * when there is an interrupt is pending on one of the OUT endpoints of + * the core. + * The driver must read the OTGFS DAINT register to determine the exact + * number of the OUT endpoint on which the interrupt occurred, and then + * read the corresponding OTGFS DOEPINTx register to determine the exact + * cause of the interrupt. * ****************************************************************************/ @@ -2647,8 +2696,8 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) uint32_t doepint; int epno; - /* Get the pending, enabled interrupts for the OUT endpoint from the endpoint - * interrupt status register. + /* Get the pending, enabled interrupts for the OUT endpoint from the + * endpoint interrupt status register. */ regval = stm32_getreg(STM32_OTGFS_DAINT); @@ -2679,8 +2728,8 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) if ((daint & 1) != 0) { regval = stm32_getreg(STM32_OTGFS_DOEPINT(epno)); - uinfo("DOEPINT(%d) = %08x\n", epno, regval); - stm32_putreg(0xFF, STM32_OTGFS_DOEPINT(epno)); + uinfo("DOEPINT(%d) = %08" PRIx32 "\n", epno, regval); + stm32_putreg(0xff, STM32_OTGFS_DOEPINT(epno)); } epno++; @@ -2705,14 +2754,15 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) doepint &= stm32_getreg(STM32_OTGFS_DOEPMSK); /* Transfer completed interrupt. This interrupt is triggered when - * stm32_rxinterrupt() removes the last packet data from the RxFIFO. - * In this case, core internally sets the NAK bit for this endpoint to - * prevent it from receiving any more packets. + * stm32_rxinterrupt() removes the last packet data from the + * RxFIFO. In this case, core internally sets the NAK bit for this + * endpoint to prevent it from receiving any more packets. */ if ((doepint & OTGFS_DOEPINT_XFRC) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_XFRC), (uint16_t)doepint); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_XFRC), + (uint16_t)doepint); /* Clear the bit in DOEPINTn for this interrupt */ @@ -2731,18 +2781,21 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) if ((doepint & OTGFS_DOEPINT_EPDISD) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_EPDISD), (uint16_t)doepint); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_EPDISD), + (uint16_t)doepint); /* Clear the bit in DOEPINTn for this interrupt */ stm32_putreg(OTGFS_DOEPINT_EPDISD, STM32_OTGFS_DOEPINT(epno)); } #endif + /* Setup Phase Done (control EPs) */ if ((doepint & OTGFS_DOEPINT_SETUP) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_SETUP), priv->ep0state); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_SETUP), + priv->ep0state); /* Handle the receipt of the IN SETUP packets now (OUT setup * packet processing may be delayed until the accompanying @@ -2753,6 +2806,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) { stm32_ep0out_setup(priv); } + stm32_putreg(OTGFS_DOEPINT_SETUP, STM32_OTGFS_DOEPINT(epno)); } } @@ -2847,7 +2901,8 @@ static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno) * ****************************************************************************/ -static inline void stm32_epin_txfifoempty(FAR struct stm32_usbdev_s *priv, int epno) +static inline void stm32_epin_txfifoempty(FAR struct stm32_usbdev_s *priv, + int epno) { FAR struct stm32_ep_s *privep = &priv->epin[epno]; @@ -2863,11 +2918,12 @@ static inline void stm32_epin_txfifoempty(FAR struct stm32_usbdev_s *priv, int e * Name: stm32_epin_interrupt * * Description: - * USB IN endpoint interrupt handler. The core generates this interrupt when - * an interrupt is pending on one of the IN endpoints of the core. The driver - * must read the OTGFS DAINT register to determine the exact number of the IN - * endpoint on which the interrupt occurred, and then read the corresponding - * OTGFS DIEPINTx register to determine the exact cause of the interrupt. + * USB IN endpoint interrupt handler. The core generates this interrupt + * when an interrupt is pending on one of the IN endpoints of the core. + * The driver must read the OTGFS DAINT register to determine the exact + * number of the IN endpoint on which the interrupt occurred, and then + * read the corresponding OTGFS DIEPINTx register to determine the exact + * cause of the interrupt. * ****************************************************************************/ @@ -2879,8 +2935,8 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) uint32_t empty; int epno; - /* Get the pending, enabled interrupts for the IN endpoint from the endpoint - * interrupt status register. + /* Get the pending, enabled interrupts for the IN endpoint from the + * endpoint interrupt status register. */ daint = stm32_getreg(STM32_OTGFS_DAINT); @@ -2910,9 +2966,9 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) { if ((daint & 1) != 0) { - uinfo("DIEPINT(%d) = %08x\n", + uinfo("DIEPINT(%d) = %08" PRIx32 "\n", epno, stm32_getreg(STM32_OTGFS_DIEPINT(epno))); - stm32_putreg(0xFF, STM32_OTGFS_DIEPINT(epno)); + stm32_putreg(0xff, STM32_OTGFS_DIEPINT(epno)); } epno++; @@ -2958,6 +3014,7 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) diepint = stm32_getreg(STM32_OTGFS_DIEPINT(epno)) & mask; /* Decode and process the enabled, pending interrupts */ + /* Transfer completed interrupt */ if ((diepint & OTGFS_DIEPINT_XFRC) != 0) @@ -2984,20 +3041,22 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) if ((diepint & OTGFS_DIEPINT_TOC) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TOC), (uint16_t)diepint); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TOC), + (uint16_t)diepint); stm32_putreg(OTGFS_DIEPINT_TOC, STM32_OTGFS_DIEPINT(epno)); } - /* IN token received when TxFIFO is empty. Applies to non-periodic IN - * endpoints only. This interrupt indicates that an IN token was received - * when the associated TxFIFO (periodic/non-periodic) was empty. This - * interrupt is asserted on the endpoint for which the IN token was - * received. + /* IN token received when TxFIFO is empty. Applies to + * non-periodic IN endpoints only. This interrupt indicates + * that an IN token was received when the associated TxFIFO + * (periodic/non-periodic) was empty. This interrupt is asserted + * on the endpoint for which the IN token was received. */ if ((diepint & OTGFS_DIEPINT_ITTXFE) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_ITTXFE), (uint16_t)diepint); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_ITTXFE), + (uint16_t)diepint); stm32_epin_request(priv, &priv->epin[epno]); stm32_putreg(OTGFS_DIEPINT_ITTXFE, STM32_OTGFS_DIEPINT(epno)); } @@ -3008,35 +3067,41 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) #if 0 if ((diepint & OTGFS_DIEPINT_INEPNE) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_INEPNE), (uint16_t)diepint); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_INEPNE), + (uint16_t)diepint); stm32_putreg(OTGFS_DIEPINT_INEPNE, STM32_OTGFS_DIEPINT(epno)); } #endif + /* Endpoint disabled interrupt (ignored as this used only in polled * mode) */ #if 0 if ((diepint & OTGFS_DIEPINT_EPDISD) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EPDISD), (uint16_t)diepint); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EPDISD), + (uint16_t)diepint); stm32_putreg(OTGFS_DIEPINT_EPDISD, STM32_OTGFS_DIEPINT(epno)); } #endif + /* Transmit FIFO empty */ if ((diepint & OTGFS_DIEPINT_TXFE) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TXFE), (uint16_t)diepint); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TXFE), + (uint16_t)diepint); - /* If we were waiting for TxFIFO to become empty, the we might have both - * XFRC and TXFE interrupts pending. Since we do the same thing for both - * cases, ignore the TXFE if we have already processed the XFRC. + /* If we were waiting for TxFIFO to become empty, the we might + * have both XFRC and TXFE interrupts pending. Since we do + * the same thing for both cases, ignore the TXFE if we have + * already processed the XFRC. */ if ((diepint & OTGFS_DIEPINT_XFRC) == 0) { - /* Mask further FIFO empty interrupts. This will be re-enabled - * whenever we need to wait for a FIFO event. + /* Mask further FIFO empty interrupts. This will be + * re-enabled whenever we need to wait for a FIFO event. */ empty &= ~OTGFS_DIEPEMPMSK(epno); @@ -3177,7 +3242,8 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) /* Decode status fields */ - epphy = (regval & OTGFS_GRXSTSD_EPNUM_MASK) >> OTGFS_GRXSTSD_EPNUM_SHIFT; + epphy = (regval & OTGFS_GRXSTSD_EPNUM_MASK) >> + OTGFS_GRXSTSD_EPNUM_SHIFT; /* Workaround for bad values read from the STM32_OTGFS_GRXSTSP register * happens regval is 0xb4e48168 or 0xa80c9367 or 267E781c @@ -3192,11 +3258,11 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) switch (regval & OTGFS_GRXSTSD_PKTSTS_MASK) { - /* Global OUT NAK. This indicate that the global OUT NAK bit has taken - * effect. + /* Global OUT NAK. This indicate that the global OUT NAK bit + * has taken effect. * - * PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, DPID = Don't - * Care. + * PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, + * DPID = Don't Care. */ case OTGFS_GRXSTSD_PKTSTS_OUTNAK: @@ -3208,13 +3274,15 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) /* OUT data packet received. * * PKTSTS = DataOUT, BCNT = size of the received data OUT packet, - * EPNUM = EPNUM on which the packet was received, DPID = Actual Data PID. + * EPNUM = EPNUM on which the packet was received, DPID = Actual + * Data PID. */ case OTGFS_GRXSTSD_PKTSTS_OUTRECVD: { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy); - bcnt = (regval & OTGFS_GRXSTSD_BCNT_MASK) >> OTGFS_GRXSTSD_BCNT_SHIFT; + bcnt = (regval & OTGFS_GRXSTSD_BCNT_MASK) >> + OTGFS_GRXSTSD_BCNT_SHIFT; if (bcnt > 0) { stm32_epout_receive(privep, bcnt); @@ -3222,13 +3290,14 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) } break; - /* OUT transfer completed. This indicates that an OUT data transfer for - * the specified OUT endpoint has completed. After this entry is popped - * from the receive FIFO, the core asserts a Transfer Completed interrupt - * on the specified OUT endpoint. + /* OUT transfer completed. This indicates that an OUT data + * transfer for the specified OUT endpoint has completed. + * After this entry is popped from the receive FIFO, the core + * asserts a Transfer Completed interrupt on the specified OUT + * endpoint. * - * PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on - * which the data transfer is complete, DPID = Don't Care. + * PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP + * Num on which the data transfer is complete, DPID = Don't Care. */ case OTGFS_GRXSTSD_PKTSTS_OUTDONE: @@ -3237,11 +3306,12 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) } break; - /* SETUP transaction completed. This indicates that the Setup stage for - * the specified endpoint has completed and the Data stage has started. - * After this entry is popped from the receive FIFO, the core asserts a - * Setup interrupt on the specified control OUT endpoint (triggers an - * interrupt). + /* SETUP transaction completed. This indicates that the Setup + * stage for the specified endpoint has completed and the Data + * stage has started. + * After this entry is popped from the receive FIFO, the core + * asserts a Setup interrupt on the specified control OUT + * endpoint (triggers an interrupt). * * PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num, * DPID = Don't Care. @@ -3251,8 +3321,8 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy); - /* Now that the Setup Phase is complete if it was an OUT enable - * the endpoint + /* Now that the Setup Phase is complete if it was an OUT + * enable the endpoint * (Doing this here prevents the loss of the first FIFO word) */ @@ -3263,13 +3333,13 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTGFS_DOEPCTL0); regval |= OTGFS_DOEPCTL0_CNAK; stm32_putreg(regval, STM32_OTGFS_DOEPCTL0); - } } break; - /* SETUP data packet received. This indicates that a SETUP packet for the - * specified endpoint is now available for reading from the receive FIFO. + /* SETUP data packet received. This indicates that a SETUP + * packet for the specified endpoint is now available for + * reading from the receive FIFO. * * PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0. */ @@ -3278,23 +3348,26 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) { uint16_t datlen; - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), + epphy); - /* Read EP0 setup data. NOTE: If multiple SETUP packets are received, - * the last one overwrites the previous setup packets and only that - * last SETUP packet will be processed. + /* Read EP0 setup data. NOTE: If multiple SETUP packets are + * received, the last one overwrites the previous setup + * packets and only that last SETUP packet will be processed. */ - stm32_rxfifo_read(&priv->epout[EP0], (FAR uint8_t *)&priv->ctrlreq, - USB_SIZEOF_CTRLREQ); + stm32_rxfifo_read(&priv->epout[EP0], + (FAR uint8_t *)&priv->ctrlreq, + USB_SIZEOF_CTRLREQ); - /* Was this an IN or an OUT SETUP packet. If it is an OUT SETUP, - * then we need to wait for the completion of the data phase to - * process the setup command. If it is an IN SETUP packet, then - * we must processing the command BEFORE we enter the DATA phase. + /* Was this an IN or an OUT SETUP packet. If it is an OUT + * SETUP, then we need to wait for the completion of the + * data phase to process the setup command. If it is an + * IN SETUP packet, then we must processing the command + * BEFORE we enter the DATA phase. * - * If the data associated with the OUT SETUP packet is zero length, - * then, of course, we don't need to wait. + * If the data associated with the OUT SETUP packet is zero + * length, then, of course, we don't need to wait. */ datlen = GETUINT16(priv->ctrlreq.len); @@ -3306,8 +3379,8 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) } else { - /* We can process the setup data as soon as SETUP done word is - * popped of the RxFIFO. + /* We can process the setup data as soon as SETUP done + * word is popped of the RxFIFO. */ priv->ep0state = EP0STATE_SETUP_READY; @@ -3318,7 +3391,8 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) default: { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), - (regval & OTGFS_GRXSTSD_PKTSTS_MASK) >> OTGFS_GRXSTSD_PKTSTS_SHIFT); + (regval & OTGFS_GRXSTSD_PKTSTS_MASK) >> + OTGFS_GRXSTSD_PKTSTS_SHIFT); } break; } @@ -3342,7 +3416,9 @@ static inline void stm32_enuminterrupt(FAR struct stm32_usbdev_s *priv) stm32_ep0in_activate(); - /* Set USB turn-around time for the full speed device with internal PHY interface. */ + /* Set USB turn-around time for the full speed device with internal PHY + * interface. + */ regval = stm32_getreg(STM32_OTGFS_GUSBCFG); regval &= ~OTGFS_GUSBCFG_TRDT_MASK; @@ -3354,9 +3430,9 @@ static inline void stm32_enuminterrupt(FAR struct stm32_usbdev_s *priv) * Name: stm32_isocininterrupt * * Description: - * Incomplete isochronous IN transfer interrupt. Assertion of the incomplete - * isochronous IN transfer interrupt indicates an incomplete isochronous IN - * transfer on at least one of the isochronous IN endpoints. + * Incomplete isochronous IN transfer interrupt. Assertion of the + * incomplete isochronous IN transfer interrupt indicates an incomplete + * isochronous IN transfer on at least one of the isochronous IN endpoints. * ****************************************************************************/ @@ -3365,8 +3441,9 @@ static inline void stm32_isocininterrupt(FAR struct stm32_usbdev_s *priv) { int i; - /* The application must read the endpoint control register for all isochronous - * IN endpoints to detect endpoints with incomplete IN data transfers. + /* The application must read the endpoint control register for all + * isochronous IN endpoints to detect endpoints with incomplete IN data + * transfers. */ for (i = 0; i < STM32_NENDPOINTS; i++) @@ -3445,7 +3522,8 @@ static inline void stm32_isocoutinterrupt(FAR struct stm32_usbdev_s *priv) /* When it receives an IISOOXFR interrupt, the application must read the * control registers of all isochronous OUT endpoints to determine which * endpoints had an incomplete transfer in the current microframe. An - * endpoint transfer is incomplete if both the following conditions are true: + * endpoint transfer is incomplete if both the following conditions are + * true: * * DOEPCTLx:EONUM = DSTS:SOFFN[0], and * DOEPCTLx:EPENA = 1 @@ -3560,7 +3638,8 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) /* At present, there is only a single OTG FS device support. Hence it is * pre-allocated as g_otgfsdev. However, in most code, the private data * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple devices. + * global data) in order to simplify any future support for multiple + * devices. */ FAR struct stm32_usbdev_s *priv = &g_otgfsdev; @@ -3571,12 +3650,14 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) /* Assure that we are in device mode */ - DEBUGASSERT((stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) == OTGFS_GINTSTS_DEVMODE); + DEBUGASSERT((stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) == + OTGFS_GINTSTS_DEVMODE); /* Get the state of all enabled interrupts. We will do this repeatedly * some interrupts (like RXFLVL) will generate additional interrupting * events. */ + for (; ; ) { /* Get the set of pending, un-masked interrupts */ @@ -3589,7 +3670,8 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) * **Writable** pending irqs we will service below */ - stm32_putreg(((regval | reserved) & OTGFS_GINT_RC_W1), STM32_OTGFS_GINTSTS); + stm32_putreg(((regval | reserved) & OTGFS_GINT_RC_W1), + STM32_OTGFS_GINTSTS); /* Break out of the loop when there are no further pending (and * unmasked) interrupts to be processes. @@ -3599,7 +3681,9 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) { break; } - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_INTPENDING), (uint16_t)regval); + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_INTPENDING), + (uint16_t)regval); /* OUT endpoint interrupt. The core sets this bit to indicate that an * interrupt is pending on one of the OUT endpoints of the core. @@ -3607,7 +3691,8 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & OTGFS_GINT_OEP) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), + (uint16_t)regval); stm32_epout_interrupt(priv); } @@ -3626,7 +3711,8 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) #ifdef CONFIG_DEBUG_USB if ((regval & OTGFS_GINT_MMIS) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_MISMATCH), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_MISMATCH), + (uint16_t)regval); } #endif @@ -3634,7 +3720,8 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & OTGFS_GINT_WKUP) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), + (uint16_t)regval); stm32_resumeinterrupt(priv); } @@ -3642,7 +3729,8 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & OTGFS_GINT_USBSUSP) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND), + (uint16_t)regval); stm32_suspendinterrupt(priv); } @@ -3661,7 +3749,8 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & OTGFS_GINT_RXFLVL) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), + (uint16_t)regval); stm32_rxinterrupt(priv); } @@ -3669,7 +3758,8 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & OTGFS_GINT_RESETS) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVRESET), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVRESET), + (uint16_t)regval); /* Perform the device reset */ @@ -3682,7 +3772,8 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & OTGFS_GINT_ENUMDNE) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), + (uint16_t)regval); stm32_enuminterrupt(priv); } @@ -3695,7 +3786,8 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) #ifdef CONFIG_USBDEV_ISOCHRONOUS if ((regval & OTGFS_GINT_IISOIXFR) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), + (uint16_t)regval); stm32_isocininterrupt(priv); } @@ -3711,7 +3803,8 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & OTGFS_GINT_IISOOXFR) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR), + (uint16_t)regval); stm32_isocoutinterrupt(priv); } #endif @@ -3778,11 +3871,11 @@ static void stm32_enablegonak(FAR struct stm32_ep_s *privep) #else /* Since we are in the interrupt handler, we cannot wait inline for the - * GONAKEFF because it cannot occur until service the RXFLVL global interrupt - * and pop the OUTNAK word from the RxFIFO. + * GONAKEFF because it cannot occur until service the RXFLVL global + * interrupt and pop the OUTNAK word from the RxFIFO. * - * Perhaps it is sufficient to wait for Global OUT NAK status to be reported - * in OTGFS DCTL register? + * Perhaps it is sufficient to wait for Global OUT NAK status to be + * reported in OTGFS DCTL register? */ while ((stm32_getreg(STM32_OTGFS_DCTL) & OTGFS_DCTL_GONSTS) == 0); @@ -3821,7 +3914,8 @@ static void stm32_disablegonak(FAR struct stm32_ep_s *privep) * ****************************************************************************/ -static int stm32_epout_configure(FAR struct stm32_ep_s *privep, uint8_t eptype, +static int stm32_epout_configure(FAR struct stm32_ep_s *privep, + uint8_t eptype, uint16_t maxpacket) { uint32_t mpsiz; @@ -3916,7 +4010,8 @@ static int stm32_epout_configure(FAR struct stm32_ep_s *privep, uint8_t eptype, * ****************************************************************************/ -static int stm32_epin_configure(FAR struct stm32_ep_s *privep, uint8_t eptype, +static int stm32_epin_configure(FAR struct stm32_ep_s *privep, + uint8_t eptype, uint16_t maxpacket) { uint32_t mpsiz; @@ -3977,7 +4072,8 @@ static int stm32_epin_configure(FAR struct stm32_ep_s *privep, uint8_t eptype, regval |= OTGFS_DIEPCTL_CNAK; } - regval &= ~(OTGFS_DIEPCTL_MPSIZ_MASK | OTGFS_DIEPCTL_EPTYP_MASK | OTGFS_DIEPCTL_TXFNUM_MASK); + regval &= ~(OTGFS_DIEPCTL_MPSIZ_MASK | OTGFS_DIEPCTL_EPTYP_MASK | + OTGFS_DIEPCTL_TXFNUM_MASK); regval |= mpsiz; regval |= (eptype << OTGFS_DIEPCTL_EPTYP_SHIFT); regval |= (privep->epphy << OTGFS_DIEPCTL_TXFNUM_SHIFT); @@ -4181,7 +4277,9 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep) regval |= (OTGFS_DIEPCTL_EPDIS | OTGFS_DIEPCTL_SNAK); stm32_putreg(regval, regaddr); - /* Wait for the INEPNE interrupt that indicates that we are now in NAK mode */ + /* Wait for the INEPNE interrupt that indicates that we are now in NAK + * mode + */ regaddr = STM32_OTGFS_DIEPINT(privep->epphy); while ((stm32_getreg(regaddr) & OTGFS_DIEPINT_INEPNE) == 0); @@ -4310,7 +4408,8 @@ static FAR struct usbdev_req_s *stm32_ep_allocreq(FAR struct usbdev_ep_s *ep) * ****************************************************************************/ -static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) +static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, + FAR struct usbdev_req_s *req) { FAR struct stm32_req_s *privreq = (FAR struct stm32_req_s *)req; @@ -4376,7 +4475,8 @@ static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf) * ****************************************************************************/ -static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) +static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, + FAR struct usbdev_req_s *req) { FAR struct stm32_req_s *privreq = (FAR struct stm32_req_s *)req; FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; @@ -4390,7 +4490,8 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s * if (!req || !req->callback || !req->buf || !ep) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); + uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, + req->buf, ep); return -EINVAL; } #endif @@ -4401,7 +4502,8 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s * #ifdef CONFIG_DEBUG_FEATURES if (!priv->driver) { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), + priv->usbdev.speed); return -ESHUTDOWN; } #endif @@ -4470,7 +4572,8 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s * * ****************************************************************************/ -static int stm32_ep_cancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) +static int stm32_ep_cancel(FAR struct usbdev_ep_s *ep, + FAR struct usbdev_req_s *req) { FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; irqstate_t flags; @@ -4552,12 +4655,15 @@ static int stm32_epout_setstall(FAR struct stm32_ep_s *privep) return OK; #else /* This implementation follows the STMicro code example. */ + /* REVISIT: */ uint32_t regaddr; uint32_t regval; - /* Stall the OUT endpoint by setting the STALL bit in the DOECPTL register. */ + /* Stall the OUT endpoint by setting the STALL bit in the DOECPTL + * register. + */ regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); regval = stm32_getreg(regaddr); @@ -4708,6 +4814,7 @@ static int stm32_ep_stall(FAR struct usbdev_ep_s *ep, bool resume) { ret = stm32_ep_setstall(privep); } + leave_critical_section(flags); return ret; @@ -4740,12 +4847,13 @@ static void stm32_ep0_stall(FAR struct stm32_usbdev_s *priv) * Allocate an endpoint matching the parameters. * * Input Parameters: - * eplog - 7-bit logical endpoint number (direction bit ignored). Zero means - * that any endpoint matching the other requirements will suffice. The - * assigned endpoint can be found in the eplog field. + * eplog - 7-bit logical endpoint number (direction bit ignored). + * Zero means that any endpoint matching the other requirements + * will suffice. The assigned endpoint can be found in the eplog + * field. * in - true: IN (device-to-host) endpoint requested - * eptype - Endpoint type. One of {USB_EP_ATTR_XFER_ISOC, USB_EP_ATTR_XFER_BULK, - * USB_EP_ATTR_XFER_INT} + * eptype - Endpoint type. One of {USB_EP_ATTR_XFER_ISOC, + * USB_EP_ATTR_XFER_BULK, USB_EP_ATTR_XFER_INT} * ****************************************************************************/ @@ -4774,8 +4882,9 @@ static FAR struct usbdev_ep_s *stm32_ep_alloc(FAR struct usbdev_s *dev, if (epphy > 0) { - /* Otherwise, we will return the endpoint structure only for the requested - * 'logical' endpoint. All of the other checks will still be performed. + /* Otherwise, we will return the endpoint structure only for the + * requested 'logical' endpoint. All of the other checks will still + * be performed. * * First, verify that the logical endpoint is in the range supported by * by the hardware. @@ -4834,7 +4943,8 @@ static FAR struct usbdev_ep_s *stm32_ep_alloc(FAR struct usbdev_s *dev, * ****************************************************************************/ -static void stm32_ep_free(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep) +static void stm32_ep_free(FAR struct usbdev_s *dev, + FAR struct usbdev_ep_s *ep) { FAR struct stm32_usbdev_s *priv = (FAR struct stm32_usbdev_s *)dev; FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; @@ -5189,7 +5299,8 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) /* Disable global interrupts by clearing the GINTMASK bit in the GAHBCFG * register; Set the TXFELVL bit in the GAHBCFG register so that TxFIFO - * interrupts will occur when the TxFIFO is truly empty (not just half full). + * interrupts will occur when the TxFIFO is truly empty (not just half + * full). */ stm32_putreg(OTGFS_GAHBCFG_TXFELVL, STM32_OTGFS_GAHBCFG); @@ -5244,7 +5355,8 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) * Sense when Set */ - regval = (OTGFS_GCCFG_PWRDWN | OTGFS_GCCFG_VBUSASEN | OTGFS_GCCFG_VBUSBSEN); + regval = (OTGFS_GCCFG_PWRDWN | OTGFS_GCCFG_VBUSASEN | + OTGFS_GCCFG_VBUSBSEN); # ifndef CONFIG_USBDEV_VBUSSENSING regval |= OTGFS_GCCFG_NOVBUSSENS; # endif @@ -5255,8 +5367,8 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) stm32_putreg(regval, STM32_OTGFS_GCCFG); up_mdelay(20); - /* For the new OTG controller in the F446, F469 when VBUS sensing is not used we - * need to force the B session valid + /* For the new OTG controller in the F446, F469 when VBUS sensing is not + * used we need to force the B session valid */ #if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) @@ -5442,9 +5554,9 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) * Assumptions: * - This function is called very early in the initialization sequence * - PLL and GIO pin initialization is not performed here but should been in - * the low-level boot logic: PLL1 must be configured for operation at 48MHz - * and P0.23 and PO.31 in PINSEL1 must be configured for Vbus and USB connect - * LED. + * the low-level boot logic: PLL1 must be configured for operation at + * 48MHz and P0.23 and PO.31 in PINSEL1 must be configured for Vbus and + * USB connect LED. * ****************************************************************************/ @@ -5453,7 +5565,8 @@ void arm_usbinitialize(void) /* At present, there is only a single OTG FS device support. Hence it is * pre-allocated as g_otgfsdev. However, in most code, the private data * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple devices. + * global data) in order to simplify any future support for multiple + * devices. */ FAR struct stm32_usbdev_s *priv = &g_otgfsdev; @@ -5509,7 +5622,7 @@ void arm_usbinitialize(void) ret = irq_attach(STM32_IRQ_OTGFS, stm32_usbinterrupt, NULL); if (ret < 0) { - uerr("ERROR: irq_attach failed\n", ret); + uerr("ERROR: irq_attach failed: %d\n", ret); goto errout; } @@ -5543,7 +5656,8 @@ void arm_usbuninitialize(void) /* At present, there is only a single OTG FS device support. Hence it is * pre-allocated as g_otgfsdev. However, in most code, the private data * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple devices. + * global data) in order to simplify any future support for multiple + * devices. */ FAR struct stm32_usbdev_s *priv = &g_otgfsdev; @@ -5598,8 +5712,8 @@ void arm_usbuninitialize(void) * Name: usbdev_register * * Description: - * Register a USB device class driver. The class driver's bind() method will be - * called to bind it to a USB device driver. + * Register a USB device class driver. The class driver's bind() method + * will be called to bind it to a USB device driver. * ****************************************************************************/ @@ -5608,7 +5722,8 @@ int usbdev_register(struct usbdevclass_driver_s *driver) /* At present, there is only a single OTG FS device support. Hence it is * pre-allocated as g_otgfsdev. However, in most code, the private data * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple devices. + * global data) in order to simplify any future support for multiple + * devices. */ FAR struct stm32_usbdev_s *priv = &g_otgfsdev; @@ -5668,9 +5783,10 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * Name: usbdev_unregister * * Description: - * Un-register usbdev class driver.If the USB device is connected to a USB host, - * it will first disconnect(). The driver is also requested to unbind() and clean - * up any device state, before this procedure finally returns. + * Un-register usbdev class driver.If the USB device is connected to a USB + * host, it will first disconnect(). The driver is also requested to + * unbind() and clean up any device state, before this procedure finally + * returns. * ****************************************************************************/ @@ -5679,7 +5795,8 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) /* At present, there is only a single OTG FS device support. Hence it is * pre-allocated as g_otgfsdev. However, in most code, the private data * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple devices. + * global data) in order to simplify any future support for multiple + * devices. */ FAR struct stm32_usbdev_s *priv = &g_otgfsdev; diff --git a/arch/arm/src/stm32/stm32_otgfshost.c b/arch/arm/src/stm32/stm32_otgfshost.c index bdb66f53ad9..6587c867904 100644 --- a/arch/arm/src/stm32/stm32_otgfshost.c +++ b/arch/arm/src/stm32/stm32_otgfshost.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include @@ -2520,7 +2521,8 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv, /* AND the two to get the set of enabled, pending HC interrupts */ pending &= regval; - uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending); + uinfo("HCINTMSK%d: %08" PRIx32 " pending: %08" PRIx32 "\n", + chidx, regval, pending); /* Check for a pending ACK response received/transmitted interrupt */ @@ -2777,7 +2779,8 @@ static inline void stm32_gint_hcoutisr(FAR struct stm32_usbhost_s *priv, /* AND the two to get the set of enabled, pending HC interrupts */ pending &= regval; - uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending); + uinfo("HCINTMSK%d: %08" PRIx32 " pending: %08" PRIx32 "\n", + chidx, regval, pending); /* Check for a pending ACK response received/transmitted interrupt */ @@ -3099,7 +3102,7 @@ static inline void stm32_gint_rxflvlisr(FAR struct stm32_usbhost_s *priv) /* Read and pop the next status from the Rx FIFO */ grxsts = stm32_getreg(STM32_OTGFS_GRXSTSP); - uinfo("GRXSTS: %08x\n", grxsts); + uinfo("GRXSTS: %08" PRIx32 "\n", grxsts); /* Isolate the channel number/index in the status word */ @@ -3254,7 +3257,7 @@ static inline void stm32_gint_nptxfeisr(FAR struct stm32_usbhost_s *priv) /* Write the next group of packets into the Tx FIFO */ - uinfo("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d " + uinfo("HNPTXSTS: %08" PRIx32 " chidx: %d avail: %d buflen: %d xfrd: %d " "wrsize: %d\n", regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); @@ -3344,8 +3347,9 @@ static inline void stm32_gint_ptxfeisr(FAR struct stm32_usbhost_s *priv) /* Write the next group of packets into the Tx FIFO */ - uinfo("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n", - regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); + uinfo("HPTXSTS: %08" PRIx32 + " chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n", + regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); } @@ -4839,7 +4843,7 @@ static int stm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) unsigned int chidx = (unsigned int)ep; irqstate_t flags; - uinfo("chidx: %u: %d\n", chidx); + uinfo("chidx: %u\n", chidx); DEBUGASSERT(priv && chidx < STM32_MAX_TX_FIFOS); chan = &priv->chan[chidx]; diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/stm32/stm32_sdio.c index b1150b61a6e..9d52301f893 100644 --- a/arch/arm/src/stm32/stm32_sdio.c +++ b/arch/arm/src/stm32/stm32_sdio.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -458,7 +459,7 @@ static void stm32_blocksetup(FAR struct sdio_dev_s *dev, static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, size_t nbytes); static int stm32_sendsetup(FAR struct sdio_dev_s *dev, - FAR const uint8_t *buffer, uint32_t nbytes); + FAR const uint8_t *buffer, size_t nbytes); static int stm32_cancel(FAR struct sdio_dev_s *dev); static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd); @@ -622,8 +623,8 @@ static inline void stm32_setclkcr(uint32_t clkcr) regval |= clkcr; putreg32(regval, STM32_SDIO_CLKCR); - mcinfo("CLKCR: %08x PWR: %08x\n", - getreg32(STM32_SDIO_CLKCR), getreg32(STM32_SDIO_POWER)); + mcinfo("CLKCR: %08" PRIx32 " PWR: %08" PRIx32 "\n", + getreg32(STM32_SDIO_CLKCR), getreg32(STM32_SDIO_POWER)); } /**************************************************************************** @@ -1659,7 +1660,7 @@ static void stm32_reset(FAR struct sdio_dev_s *dev) stm32_setpwrctrl(SDIO_POWER_PWRCTRL_ON); leave_critical_section(flags); - mcinfo("CLCKR: %08x POWER: %08x\n", + mcinfo("CLCKR: %08" PRIx32 " POWER: %08" PRIx32 "\n", getreg32(STM32_SDIO_CLKCR), getreg32(STM32_SDIO_POWER)); } @@ -1894,7 +1895,8 @@ static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT; regval |= cmdidx | SDIO_CMD_CPSMEN; - mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval); + mcinfo("cmd: %08" PRIx32 " arg: %08" PRIx32 " regval: %08" PRIx32 "\n", + cmd, arg, regval); /* Write the SDIO CMD */ @@ -2174,8 +2176,9 @@ static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { if (--timeout <= 0) { - mcerr("ERROR: Timeout cmd: %08x events: %08x STA: %08x\n", - cmd, events, getreg32(STM32_SDIO_STA)); + mcerr("ERROR: Timeout cmd: %08" PRIx32 " events: %08" PRIx32 + " STA: %08" PRIx32 "\n", + cmd, events, getreg32(STM32_SDIO_STA)); return -ETIMEDOUT; } @@ -2263,12 +2266,12 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, regval = getreg32(STM32_SDIO_STA); if ((regval & SDIO_STA_CTIMEOUT) != 0) { - mcerr("ERROR: Command timeout: %08x\n", regval); + mcerr("ERROR: Command timeout: %08" PRIx32 "\n", regval); ret = -ETIMEDOUT; } else if ((regval & SDIO_STA_CCRCFAIL) != 0) { - mcerr("ERROR: CRC failure: %08x\n", regval); + mcerr("ERROR: CRC failure: %08" PRIx32 "\n", regval); ret = -EIO; } #ifdef CONFIG_DEBUG_MEMCARD_INFO @@ -2280,7 +2283,8 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, if ((uint8_t)(respcmd & SDIO_RESPCMD_MASK) != (cmd & MMCSD_CMDIDX_MASK)) { - mcerr("ERROR: RESCMD=%02x CMD=%08x\n", respcmd, cmd); + mcerr("ERROR: RESCMD=%02" PRIx32 " CMD=%08" PRIx32 "\n", + respcmd, cmd); ret = -EINVAL; } } @@ -2327,12 +2331,12 @@ static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, regval = getreg32(STM32_SDIO_STA); if (regval & SDIO_STA_CTIMEOUT) { - mcerr("ERROR: Timeout STA: %08x\n", regval); + mcerr("ERROR: Timeout STA: %08" PRIx32 "\n", regval); ret = -ETIMEDOUT; } else if (regval & SDIO_STA_CCRCFAIL) { - mcerr("ERROR: CRC fail STA: %08x\n", regval); + mcerr("ERROR: CRC fail STA: %08" PRIx32 "\n", regval); ret = -EIO; } } @@ -2386,7 +2390,7 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, regval = getreg32(STM32_SDIO_STA); if (regval & SDIO_STA_CTIMEOUT) { - mcerr("ERROR: Timeout STA: %08x\n", regval); + mcerr("ERROR: Timeout STA: %08" PRIx32 "\n", regval); ret = -ETIMEDOUT; } } diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c index e2f1670b40d..29b90ac488e 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/stm32/stm32_serial.c @@ -2315,11 +2315,9 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; -#if !(defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && defined(CONFIG_STM32_FLOWCONTROL_BROKEN)) - uint16_t ie; -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && defined(CONFIG_STM32_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -2363,9 +2361,7 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev, * enable Rx interrupts. */ - ie = priv->ie; - ie &= ~USART_CR1_RXNEIE; - up_restoreusartint(priv, ie); + uart_disablerxint(dev); return true; } @@ -2378,7 +2374,7 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev, * received. */ - up_rxint(dev, true); + uart_enablerxint(dev); } } #endif @@ -2477,8 +2473,11 @@ static void up_send(struct uart_dev_s *dev, int ch) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) - stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + { + stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + } #endif + up_serialout(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } diff --git a/arch/arm/src/stm32/stm32_spi.c b/arch/arm/src/stm32/stm32_spi.c index 5fb79c4f079..1ebcae17fa9 100644 --- a/arch/arm/src/stm32/stm32_spi.c +++ b/arch/arm/src/stm32/stm32_spi.c @@ -47,6 +47,7 @@ #include #include +#include #include #include #include @@ -1334,7 +1335,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) * faster. */ - spiinfo("Frequency %d->%d\n", frequency, actual); + spiinfo("Frequency %" PRIu32 "->%" PRIu32 "\n", frequency, actual); priv->frequency = frequency; priv->actual = actual; @@ -1623,7 +1624,8 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd) regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); - spiinfo("Sent: %04x Return: %04x Status: %02x\n", wd, ret, regval); + spiinfo("Sent: %04" PRIx32 " Return: %04" PRIx32 + " Status: %02" PRIx32 "\n", wd, ret, regval); UNUSED(regval); return ret; @@ -1797,9 +1799,9 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, #ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer && priv->txbuf == 0 && - !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || + !stm32_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) || (rxbuffer && priv->rxbuf == 0 && - !stm32_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) + !stm32_dmacapable((uintptr_t)rxbuffer, nwords, priv->rxccr))) { /* Unsupported memory region fall back to non-DMA method. */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h index 5add3acf5e6..2fe055cc6ce 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h @@ -36,7 +36,7 @@ /* Register Offsets *****************************************************************/ -#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX12 request line multiplexer channel x configuration register */ +#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX1 request line multiplexer channel x configuration register */ #define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0) #define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1) #define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2) @@ -45,16 +45,16 @@ #define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5) #define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6) /* 0x01C-0x07C: Reserved */ -#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX12 request line multiplexer interrupt channel status register */ -#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX12 request line multiplexer interrupt clear flag register */ +#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ +#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ /* 0x088-0x0FC: Reserved */ -#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX12 request generator channel x configuration register */ +#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX1 request generator channel x configuration register */ #define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0) #define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1) #define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2) #define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3) -#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX12 request generator interrupt status register */ -#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX12 request generator interrupt clear flag register */ +#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ +#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ /* 0x148-0x3FC: Reserved */ /* Register Addresses ***************************************************************/ @@ -82,48 +82,54 @@ /* Register Bitfield Definitions ****************************************************/ -/* DMAMUX12 request line multiplexer channel x configuration register */ +/* DMAMUX1 request line multiplexer channel x configuration register */ -#define DMAMUX_CCR_DMAREQID_SHIFT (0) /* Bits 0-6: DMA request identification */ +#define DMAMUX_CCR_DMAREQID_SHIFT (0) /* Bits 0-6: DMA request identification */ #define DMAMUX_CCR_DMAREQID_MASK (0x7f << DMAMUX_CCR_DMAREQID_SHIFT) -#define DMAMUX_CCR_SOIE (8) /* Bit 8: Synchronization overrun interrupt enable */ -#define DMAMUX_CCR_EGE (9) /* Bit 9: Event generation enable */ -#define DMAMUX_CCR_SE (16) /* Bit 16: Synchronization enable */ -#define DMAMUX_CCR_SPOL_SHIFT (17) /* Bits 17-18: Synchronization polarity */ -#define DMAMUX_CCR_SPOL_MASK (3 << DMAMUX_CCR_SPOL_SHIFT) -#define DMAMUX_CCR_NBREQ_SHIFT (19) /* Bits 19-23: Number of DMA request - 1 to forward */ +#define DMAMUX_CCR_SOIE (8) /* Bit 8: Synchronization overrun interrupt enable */ +#define DMAMUX_CCR_EGE (9) /* Bit 9: Event generation enable */ +#define DMAMUX_CCR_SE (16) /* Bit 16: Synchronization enable */ +#define DMAMUX_CCR_SPOL_SHIFT (17) /* Bits 17-18: Synchronization polarity */ +#define DMAMUX_CCR_SPOL_MASK (0x3 << DMAMUX_CCR_SPOL_SHIFT) +# define DMAMUX_CCR_SPOL_NONE (0x0 << DMAMUX_CCR_SPOL_SHIFT) /* No event: No trigger detection or generation */ +# define DMAMUX_CCR_SPOL_RISING (0x1 << DMAMUX_CCR_SPOL_SHIFT) /* Rising edge */ +# define DMAMUX_CCR_SPOL_FALLING (0x2 << DMAMUX_CCR_SPOL_SHIFT) /* Falling edge */ +# define DMAMUX_CCR_SPOL_BOTH (0x3 << DMAMUX_CCR_SPOL_SHIFT) /* Both rising and falling edges */ +#define DMAMUX_CCR_NBREQ_SHIFT (19) /* Bits 19-23: Number of DMA request - 1 to forward */ #define DMAMUX_CCR_NBREQ_MASK (0x1f << DMAMUX_CCR_NBREQ_SHIFT) -#define DMAMUX_CCR_SYNCID_SHIFT (24) /* Bits 24-26: Synchronization identification */ -#define DMAMUX_CCR_SYNCID_MASK (7 << DMAMUX_CCR_SYNCID_SHIFT) +#define DMAMUX_CCR_SYNCID_SHIFT (24) /* Bits 24-28: Synchronization identification */ +#define DMAMUX_CCR_SYNCID_MASK (0x1f << DMAMUX_CCR_SYNCID_SHIFT) -/* DMAMUX12 request line multiplexer interrupt channel status register */ +/* DMAMUX1 request line multiplexer interrupt channel status register */ -#define DMAMUX1_CSR_SOF(x) (1 << x) /* Synchronization overrun event flag */ +#define DMAMUX1_CSR_SOF(x) (1 << (x)) /* Synchronization overrun event flag */ -/* DMAMUX12 request line multiplexer interrupt clear flag register */ +/* DMAMUX1 request line multiplexer interrupt clear flag register */ -#define DMAMUX1_CFR_SOF(x) (1 << x) /* Clear synchronization overrun event flag */ +#define DMAMUX1_CFR_CSOF(x) (1 << (x)) /* Clear synchronization overrun event flag */ -/* DMAMUX12 request generator channel x configuration register */ +/* DMAMUX1 request generator channel x configuration register */ -#define DMAMUX_RGCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identifiaction - * WARNING: different length for DMAMUX1 and DMAMUX2 ! - */ +#define DMAMUX_RGCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identification */ #define DMAMUX_RGCR_SIGID_MASK (0x1f << DMAMUX_RGCR_SIGID_SHIFT) -#define DMAMUX_RGCR_OIE (8) /* Bit 8: Trigger overrun interrupt enable */ -#define DMAMUX_RGCR_GE (16) /* Bit 16: DMA request generator channel X enable*/ -#define DMAMUX_RGCR_GPOL_SHIFT (17) /* Bits 17-18: DMA request generator trigger polarity */ -#define DMAMUX_RGCR_GPOL_MASK (7 << DMAMUX_RGCR_GPOL_SHIFT) -#define DMAMUX_RGCR_GNBREQ_SHIFT (17) /* Bits 19-23: Number of DMA requests to be generated -1 */ -#define DMAMUX_RGCR_GNBREQL_MASK (7 << DMAMUX_RGCR_GNBREQ_SHIFT) +#define DMAMUX_RGCR_OIE (8) /* Bit 8: Trigger overrun interrupt enable */ +#define DMAMUX_RGCR_GE (16) /* Bit 16: DMA request generator channel X enable*/ +#define DMAMUX_RGCR_GPOL_SHIFT (17) /* Bits 17-18: DMA request generator trigger polarity */ +#define DMAMUX_RGCR_GPOL_MASK (0x3 << DMAMUX_RGCR_GPOL_SHIFT) +# define DMAMUX_RGCR_GPOL_NONE (0x0 << DMAMUX_RGCR_GPOL_SHIFT) /* No event: No trigger detection or generation */ +# define DMAMUX_RGCR_GPOL_RISING (0x1 << DMAMUX_RGCR_GPOL_SHIFT) /* Rising edge */ +# define DMAMUX_RGCR_GPOL_FALLING (0x2 << DMAMUX_RGCR_GPOL_SHIFT) /* Falling edge */ +# define DMAMUX_RGCR_GPOL_BOTH (0x3 << DMAMUX_RGCR_GPOL_SHIFT) /* Both rising and falling edges */ +#define DMAMUX_RGCR_GNBREQ_SHIFT (19) /* Bits 19-23: Number of DMA requests to be generated -1 */ +#define DMAMUX_RGCR_GNBREQL_MASK (0x1f << DMAMUX_RGCR_GNBREQ_SHIFT) -/* DMAMUX12 request generator interrupt status register */ +/* DMAMUX1 request generator interrupt status register */ -#define DMAMUX1_RGSR_SOF(x) (1 << x) /* Trigger overrun event flag */ +#define DMAMUX1_RGSR_OF(x) (1 << (x)) /* Trigger overrun event flag */ -/* DMAMUX12 request generator interrupt clear flag register */ +/* DMAMUX1 request generator interrupt clear flag register */ -#define DMAMUX1_RGCFR_SOF(x) (1 << x) /* Clear trigger overrun event flag */ +#define DMAMUX1_RGCFR_COF(x) (1 << (x)) /* Clear trigger overrun event flag */ /* DMA channel mapping * @@ -133,7 +139,7 @@ * X - free bits */ -#define DMAMAP_MAP(d,c) ((d) << 8 | c) +#define DMAMAP_MAP(d,c) ((d) << 8 | (c)) #define DMAMAP_CONTROLLER(m) ((m) >> 8 & 0x07) #define DMAMAP_REQUEST(m) ((m) >> 0 & 0xff) @@ -146,7 +152,7 @@ #if defined(CONFIG_STM32F0L0G0_STM32G0) # include "chip/stm32g0_dmamux.h" #else -# error "Unsupported STM32 M0 sub family" +# error "Unsupported STM32 F0/L0/G0 sub family" #endif #endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c b/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c index 157fe9cdeaa..7098a9ca8e4 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c +++ b/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c @@ -650,7 +650,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) ****************************************************************************/ #ifdef CONFIG_STM32F0L0G0_DMACAPABLE -bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) +bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) { uint32_t transfer_size; uint32_t mend; diff --git a/arch/arm/src/stm32f0l0g0/stm32_i2c.c b/arch/arm/src/stm32f0l0g0/stm32_i2c.c index ec2842ba311..a9e64fa207d 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_i2c.c +++ b/arch/arm/src/stm32f0l0g0/stm32_i2c.c @@ -219,6 +219,7 @@ #include #include +#include #include #include #include @@ -1044,7 +1045,7 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv) * still pending. */ - i2cinfo("Timeout with CR: %04x SR: %04x\n", cr, sr); + i2cinfo("Timeout with CR: %04" PRIx32 " SR: %04" PRIx32 "\n", cr, sr); } /************************************************************************************ @@ -1078,7 +1079,8 @@ static inline void stm32_i2c_sem_init(FAR struct i2c_master_s *dev) */ nxsem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, 0, 0); - nxsem_set_protocol(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, SEM_PRIO_NONE); + nxsem_set_protocol(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, + SEM_PRIO_NONE); #endif } @@ -1549,7 +1551,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); - i2cinfo("ENTER: status = 0x%08x\n", status); + i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); /* Update private version of the state assuming a good state */ @@ -1597,16 +1599,18 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) { /* NACK received on first (address) byte: address is invalid */ - i2cinfo("NACK: Address invalid: dcnt=%i msgc=%i status=0x%08x\n", - priv->dcnt, priv->msgc, status); + i2cinfo("NACK: Address invalid: dcnt=%i msgc=%i " + "status=0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } else { /* NACK received on regular byte */ - i2cinfo("NACK: NACK received: dcnt=%i msgc=%i status=0x%08x\n", - priv->dcnt, priv->msgc, status); + i2cinfo("NACK: NACK received: dcnt=%i msgc=%i " + "status=0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } @@ -1659,7 +1663,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) /* TXIS interrupt occurred, address valid, ready to transmit */ stm32_i2c_traceevent(priv, I2CEVENT_WRITE, 0); - i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08x\n", + i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); /* The first event after the address byte is sent will be either TXIS @@ -1716,8 +1720,9 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) { /* Unsupported state */ - i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, status 0x%08x\n", - priv->dcnt, status); + i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, " + "status 0x%08" PRIx32 "\n", + priv->dcnt, status); stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); /* Indicate the bad state, so that on termination HW will be reset */ @@ -1725,7 +1730,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) priv->status |= I2C_INT_BAD_STATE; } - i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08x\n", + i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); } @@ -1766,7 +1771,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) */ stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); - i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08x\n", + i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); /* If more bytes in the current message */ @@ -1806,7 +1811,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); - i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, status 0x%08x\n", + i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, " + "status 0x%08" PRIx32 "\n", priv->dcnt, status); /* Set signals that will terminate ISR and wake waiting thread */ @@ -1816,7 +1822,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) priv->msgc = 0; } - i2cinfo("RXNE: EXIT dcnt = %i msgc = %i status 0x%08x\n", + i2cinfo("RXNE: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); } @@ -1851,7 +1857,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) else if ((status & I2C_ISR_TC) != 0) { - i2cinfo("TC: ENTER dcnt = %i msgc = %i status 0x%08x\n", + i2cinfo("TC: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); /* Prior message has been sent successfully. Or there could have @@ -1908,8 +1914,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) priv->msgc = 0; } - i2cinfo("TC: EXIT dcnt = %i msgc = %i status 0x%08x\n", - priv->dcnt, priv->msgc, status); + i2cinfo("TC: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); } /* Transfer Complete (Reload) State Handler @@ -1949,7 +1955,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) else if ((status & I2C_ISR_TCR) != 0) { - i2cinfo("TCR: ENTER dcnt = %i msgc = %i status 0x%08x\n", + i2cinfo("TCR: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); /* If no more bytes in the current message to transfer */ @@ -2035,8 +2041,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } - i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08x\n", - priv->dcnt, priv->msgc, status); + i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); } } @@ -2049,7 +2055,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) else if (priv->dcnt == -1 && priv->msgc == 0) { status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); - i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08x\n", status); + i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", + status); stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); } @@ -2072,7 +2079,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); - i2cerr("ERROR: Invalid state detected, status 0x%08x\n", status); + i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", status); /* set condition to terminate ISR and wake waiting thread */ @@ -2146,7 +2153,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) } status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); - i2cinfo("EXIT: status = 0x%08x\n", status); + i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); return OK; } @@ -2357,19 +2364,21 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, /* Connection timed out */ errval = ETIMEDOUT; - i2cerr("ERROR: Waitdone timed out CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n", + i2cerr("ERROR: Waitdone timed out CR1: 0x%08" PRIx32 + " CR2: 0x%08" PRIx32 " status: 0x%08" PRIx32 "\n", cr1, cr2, status); } else { - i2cinfo("Waitdone success: CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n", - cr1, cr2, status); + i2cinfo("Waitdone success: CR1: 0x%08" PRIx32 + " CR2: 0x%08" PRIx32 " status: 0x%08" PRIx32 "\n", + cr1, cr2, status); } UNUSED(cr1); UNUSED(cr2); - i2cinfo("priv->status: 0x%08x\n", priv->status); + i2cinfo("priv->status: 0x%08" PRIx32 "\n", priv->status); /* Check for error status conditions */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwm.c b/arch/arm/src/stm32f0l0g0/stm32_pwm.c index 8b526cbe111..d76424d4a55 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwm.c +++ b/arch/arm/src/stm32f0l0g0/stm32_pwm.c @@ -45,6 +45,7 @@ #include +#include #include #include #include @@ -887,14 +888,15 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv, #endif #if defined(CONFIG_PWM_MULTICHAN) - pwminfo("TIM%u frequency: %u\n", + pwminfo("TIM%u frequency: %" PRIu32 "\n", priv->timid, info->frequency); #elif defined(CONFIG_PWM_PULSECOUNT) - pwminfo("TIM%u channel: %u frequency: %u duty: %08x count: %u\n", + pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 + " count: %u\n", priv->timid, priv->channels[0].channel, info->frequency, info->duty, info->count); #else - pwminfo("TIM%u channel: %u frequency: %u duty: %08x\n", + pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 "\n", priv->timid, priv->channels[0].channel, info->frequency, info->duty); #endif @@ -984,8 +986,9 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv, reload--; } - pwminfo("TIM%u PCLK: %u frequency: %u " - "TIMCLK: %u prescaler: %u reload: %u\n", + pwminfo("TIM%u PCLK: %" PRIu32 " frequency: %" PRIu32 " " + "TIMCLK: %" PRIu32 " prescaler: %" PRIu32 + " reload: %" PRIu32 "\n", priv->timid, priv->pclk, info->frequency, timclk, prescaler, reload); @@ -1191,7 +1194,7 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv, ccr = b16toi(duty * reload + b16HALF); - pwminfo("ccr: %u\n", ccr); + pwminfo("ccr: %" PRIu32 "\n", ccr); switch (mode) { @@ -1458,7 +1461,7 @@ static int stm32pwm_update_duty(FAR struct stm32_pwmtimer_s *priv, DEBUGASSERT(priv != NULL); - pwminfo("TIM%u channel: %u duty: %08x\n", + pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n", priv->timid, channel, duty); #ifndef CONFIG_PWM_MULTICHAN @@ -1477,7 +1480,7 @@ static int stm32pwm_update_duty(FAR struct stm32_pwmtimer_s *priv, ccr = b16toi(duty * reload + b16HALF); - pwminfo("ccr: %u\n", ccr); + pwminfo("ccr: %" PRIu32 "\n", ccr); switch (channel) { @@ -1799,7 +1802,7 @@ static int stm32pwm_setup(FAR struct pwm_lowerhalf_s *dev) pincfg = priv->channels[i].pincfg; if (pincfg != 0) { - pwminfo("pincfg: %08x\n", pincfg); + pwminfo("pincfg: %08" PRIx32 "\n", pincfg); stm32_configgpio(pincfg); } @@ -1809,7 +1812,7 @@ static int stm32pwm_setup(FAR struct pwm_lowerhalf_s *dev) pincfg = priv->channels[i].npincfg; if (pincfg != 0) { - pwminfo("npincfg: %08x\n", pincfg); + pwminfo("npincfg: %08" PRIx32 "\n", pincfg); stm32_configgpio(pincfg); } @@ -1859,7 +1862,7 @@ static int stm32pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) pincfg = priv->channels[i].pincfg; if (pincfg != 0) { - pwminfo("pincfg: %08x\n", pincfg); + pwminfo("pincfg: %08" PRIx32 "\n", pincfg); pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); pincfg |= GPIO_INPUT | GPIO_FLOAT; @@ -1870,7 +1873,7 @@ static int stm32pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) pincfg = priv->channels[i].npincfg; if (pincfg != 0) { - pwminfo("npincfg: %08x\n", pincfg); + pwminfo("npincfg: %08" PRIx32 "\n", pincfg); pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); pincfg |= GPIO_INPUT | GPIO_FLOAT; @@ -2109,7 +2112,8 @@ static int stm32pwm_stop(FAR struct pwm_lowerhalf_s *dev) putreg32(regval, regaddr); leave_critical_section(flags); - pwminfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit); + pwminfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", + regaddr, resetbit); stm32pwm_dumpregs(priv, "After stop"); return OK; } diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.c b/arch/arm/src/stm32f0l0g0/stm32_spi.c index d8427609617..7353d3693be 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_spi.c +++ b/arch/arm/src/stm32f0l0g0/stm32_spi.c @@ -1408,9 +1408,9 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, #ifdef CONFIG_STM32F0L0G0_DMACAPABLE if ((txbuffer && - !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || + !stm32_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) || (rxbuffer && - !stm32_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) + !stm32_dmacapable((uintptr_t)rxbuffer, nwords, priv->rxccr))) { /* Unsupported memory region, fall back to non-DMA method. */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_start.c b/arch/arm/src/stm32f0l0g0/stm32_start.c index 421b153094b..6b830d18f1b 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_start.c +++ b/arch/arm/src/stm32f0l0g0/stm32_start.c @@ -65,7 +65,7 @@ * Public Data ****************************************************************************/ -const uint32_t g_idle_topstack = IDLE_STACK; +const uintptr_t g_idle_topstack = IDLE_STACK; /**************************************************************************** * Private Functions diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim.c b/arch/arm/src/stm32f0l0g0/stm32_tim.c index e070eeeaf52..993a549830e 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_tim.c +++ b/arch/arm/src/stm32f0l0g0/stm32_tim.c @@ -1,4 +1,4 @@ -/*************************************************************************** +/**************************************************************************** * arch/arm/src/stm32f0l0g0/stm32_tim.c * * Copyright (C) 2019 Fundação CERTI. All rights reserved. @@ -42,6 +42,7 @@ #include #include +#include #include #include #include @@ -57,9 +58,9 @@ #include "stm32_gpio.h" #include "stm32_tim.h" -/*************************************************************************** +/**************************************************************************** * Private Types - ***************************************************************************/ + ****************************************************************************/ /* Configuration ************************************************************/ @@ -67,9 +68,9 @@ * include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32F0L0G0_TIMn is defined then the CONFIG_STM32F0L0G0_TIMn_PWM may - * also be defined to indicate that the timer is intended to be used for - * pulsed output modulation. + * CONFIG_STM32F0L0G0_TIMn is defined then the CONFIG_STM32F0L0G0_TIMn_PWM + * may also be defined to indicate that the timer is intended to be used + * for pulsed output modulation. * * - To control periodic ADC input sampling. If CONFIG_STM32F0L0G0_TIMn is * defined then CONFIG_STM32F0L0G0_TIMn_ADC may also be defined to indicate @@ -80,8 +81,8 @@ * timer "n" is intended to be used for that purpose. * * - To use a Quadrature Encoder. If CONFIG_STM32F0L0G0_TIMn is defined then - * CONFIG_STM32F0L0G0_TIMn_QE may also be defined to indicate that timer "n" - * is intended to be used for that purpose. + * CONFIG_STM32F0L0G0_TIMn_QE may also be defined to indicate that timer + * "n" is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. */ @@ -267,22 +268,28 @@ struct stm32_tim_priv_s /* Timer methods */ -static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); -static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq); +static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, + stm32_tim_mode_t mode); +static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, + uint32_t freq); static uint32_t stm32_tim_getclock(FAR struct stm32_tim_dev_s *dev); static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev, uint32_t period); static uint32_t stm32_tim_getperiod(FAR struct stm32_tim_dev_s *dev); static uint32_t stm32_tim_getcounter(FAR struct stm32_tim_dev_s *dev); -static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel, +static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, + uint8_t channel, stm32_tim_channel_t mode); -static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel, +static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, + uint8_t channel, uint32_t compare); -static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel); +static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, + uint8_t channel); static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source); -static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source); +static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, + int source); static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source); /**************************************************************************** @@ -503,7 +510,9 @@ static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev) stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val); } -/* Reset timer into system default state, but do not affect output/input pins */ +/* Reset timer into system default state, but do not affect output/input + * pins + */ static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev) { @@ -542,7 +551,7 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq) uint32_t freqin; int prescaler; - tmrinfo("Set clock=%d\n", freq); + tmrinfo("Set clock=%" PRId32 "\n", freq); DEBUGASSERT(dev != NULL); @@ -616,7 +625,7 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq) */ prescaler = freqin / freq; - tmrinfo(" timer freq=%d\n", freqin); + tmrinfo(" timer freq=%" PRId32 "\n", freqin); tmrinfo(" prescaler=%d\n", prescaler); /* We need to decrement value for '1', but only, if that will not to @@ -638,6 +647,7 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq) tmrinfo(" prescaler (adjusted)=%d\n", prescaler); /* PSC_OFFSET is the same for ATIM, BTIM or GTIM */ + stm32_putreg16(dev, STM32_BTIM_PSC_OFFSET, prescaler); stm32_tim_enable(dev); @@ -716,9 +726,11 @@ static uint32_t stm32_tim_getclock(FAR struct stm32_tim_dev_s *dev) static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev, uint32_t period) { - tmrinfo("Set period=%d\n", period); + tmrinfo("Set period=%" PRId32 "\n", period); DEBUGASSERT(dev != NULL); + /* ARR_OFFSET is the same for ATIM, BTIM or GTIM */ + stm32_putreg32(dev, STM32_BTIM_ARR_OFFSET, period); } @@ -734,11 +746,12 @@ static uint32_t stm32_tim_getcounter(FAR struct stm32_tim_dev_s *dev) /* According to STM32G0x0 datasheet, TIMx_CNT registers are 32-bits but * CNT field is 16-bits [15:0]. * TIM 1, 3, 6-7, 14-17 - * */ + /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. */ + uint32_t counter = stm32_getreg32(dev, STM32_BTIM_CNT_OFFSET); counter &= 0xffff; return counter; @@ -837,20 +850,25 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); + /* DIER_OFFSET is the same for ATIM, BTIM or GTIM */ + stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, 0, source); } static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); + /* DIER_OFFSET is the same for ATIM, BTIM or GTIM */ + stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, source, 0); } static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source) { /* SR_OFFSET is the same for ATIM, BTIM or GTIM */ + stm32_putreg16(dev, STM32_BTIM_SR_OFFSET, ~source); } @@ -908,14 +926,16 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, } stm32_tim_reload_counter(dev); + /* CR1_OFFSET is the same for ATIM, BTIM or GTIM */ + stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val); /* Advanced registers require Main Output Enable */ #if defined(CONFIG_STM32F0L0G0_TIM1) || defined(CONFIG_STM32F0L0G0_TIM8) if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE # if defined(CONFIG_STM32F0L0G0_TIM8) - ||((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE # endif ) { @@ -932,7 +952,9 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; + /* CCER_OFFSET and CCMR1_OFFSET are the same for ATIM and GTIM */ + uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; @@ -1180,6 +1202,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, break; #endif } + return OK; } diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c b/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c index f2b75582bdd..562373be5cd 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c @@ -47,6 +47,7 @@ #include +#include #include #include #include @@ -206,7 +207,6 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif - #ifdef CONFIG_STM32F0L0G0_TIM12 static struct stm32_lowerhalf_s g_tim12_lowerhalf = { @@ -300,8 +300,8 @@ static int stm32_timer_handler(int irq, void * context, void * arg) * Start the timer, resetting the time to the current timeout, * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * * Returned Value: * Zero on success; a negated errno value on failure. @@ -340,8 +340,8 @@ static int stm32_start(FAR struct timer_lowerhalf_s *lower) * Stop the timer * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * * Returned Value: * Zero on success; a negated errno value on failure. @@ -407,6 +407,7 @@ static int stm32_getstatus(FAR struct timer_lowerhalf_s *lower, } /* Get timeout */ + clock = STM32_TIM_GETCLOCK(priv->tim); period = STM32_TIM_GETPERIOD(priv->tim); @@ -422,10 +423,11 @@ static int stm32_getstatus(FAR struct timer_lowerhalf_s *lower, status->timeout = timeout; /* Get the time remaining until the timer expires (in microseconds) */ + counter = STM32_TIM_GETCOUNTER(priv->tim); status->timeleft = ((uint64_t) (timeout - counter) * clock) / 1000000; - tmrinfo("timeout=%u counter=%u\n", timeout, counter); - tmrinfo("timeleft=%u\n", status->timeleft); + tmrinfo("timeout=%" PRIu32 " counter=%" PRIu32 "\n", timeout, counter); + tmrinfo("timeleft=%" PRIu32 "\n", status->timeleft); return OK; } @@ -458,7 +460,7 @@ static int stm32_settimeout(FAR struct timer_lowerhalf_s *lower, return -EPERM; } - tmrinfo("Set timeout=%d\n", timeout); + tmrinfo("Set timeout=%" PRId32 "\n", timeout); maxtimeout = ((uint64_t)1 << priv->resolution) - 1; if (timeout > maxtimeout) @@ -473,7 +475,8 @@ static int stm32_settimeout(FAR struct timer_lowerhalf_s *lower, period = (uint32_t) timeout; } - tmrinfo(" clock=%lu period=%lu maxtimeout=%lu\n", clock, period, (uint32_t) maxtimeout); + tmrinfo(" clock=%lu period=%lu maxtimeout=%lu\n", clock, period, + (uint32_t)maxtimeout); STM32_TIM_SETCLOCK(priv->tim, clock); STM32_TIM_SETPERIOD(priv->tim, period); @@ -487,8 +490,8 @@ static int stm32_settimeout(FAR struct timer_lowerhalf_s *lower, * Call this user provided timeout callback. * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * callback - The new timer expiration function pointer. If this * function pointer is NULL, then the reset-on-expiration * behavior is restored, @@ -627,7 +630,7 @@ int stm32_timer_initialize(FAR const char *devpath, int timer) break; #endif default: - return -ENODEV;; + return -ENODEV; } /* Initialize the elements of lower half state structure */ diff --git a/arch/arm/src/stm32f7/stm32_adc.c b/arch/arm/src/stm32f7/stm32_adc.c index 2b5eb3c4ecc..0dde2113158 100644 --- a/arch/arm/src/stm32f7/stm32_adc.c +++ b/arch/arm/src/stm32f7/stm32_adc.c @@ -47,6 +47,7 @@ #include #include +#include #include #include #include @@ -92,6 +93,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* RCC reset ****************************************************************/ #define STM32_RCC_RSTR STM32_RCC_APB2RSTR @@ -124,7 +126,8 @@ #define ADC_IER_ALLINTS (ADC_IER_EOC | ADC_IER_AWD | ADC_IER_JEOC | \ ADC_IER_OVR) -/* ADC Channels/DMA ********************************************************/ +/* ADC Channels/DMA *********************************************************/ + /* The maximum number of channels that can be sampled. If DMA support is * not enabled, then only a single channel can be sampled. Otherwise, * data overruns would occur. @@ -174,7 +177,9 @@ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT)) -/* The last external channel on ADC 1 to enable Reading Vref or Vbat / Vsence */ +/* The last external channel on ADC 1 to enable Reading Vref or + * Vbat / Vsence + */ #define ADC_LAST_EXTERNAL_CHAN 15 @@ -284,7 +289,8 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable); static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg); static void adc_enable(FAR struct stm32_dev_s *priv, bool enable); -static uint32_t adc_sqrbits(FAR struct stm32_dev_s *priv, int first, int last, +static uint32_t adc_sqrbits(FAR struct stm32_dev_s *priv, int first, + int last, int offset); static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch); static bool adc_internal(FAR struct stm32_dev_s * priv); @@ -809,7 +815,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) /* Set the reload and prescaler values */ - tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler-1); + tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler - 1); tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); /* Clear the advanced timers repetition counter in TIM1 */ @@ -910,6 +916,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) case 4: /* TimerX TRGO event */ { /* TODO: TRGO support not yet implemented */ + /* Set the event TRGO */ ccenable = 0; @@ -1014,9 +1021,11 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) * * Description: * Called by power management framework when it wants to enter low power - * states. Check if ADC is in progress and if so prevent from entering STOP. + * states. Check if ADC is in progress and if so prevent from entering + * STOP. * ****************************************************************************/ + #ifdef CONFIG_PM static int adc_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e state) @@ -1151,7 +1160,6 @@ static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset) static void adc_enable(FAR struct stm32_dev_s *priv, bool enable) { - ainfo("enable: %d\n", enable ? 1 : 0); if (enable) @@ -1182,7 +1190,8 @@ static void adc_enable(FAR struct stm32_dev_s *priv, bool enable) ****************************************************************************/ #ifdef ADC_HAVE_DMA -static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg) +static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, + FAR void *arg) { FAR struct adc_dev_s *dev = (FAR struct adc_dev_s *)arg; FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; @@ -1199,7 +1208,8 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg) for (i = 0; i < priv->nchannels; i++) { - priv->cb->au_receive(dev, priv->chanlist[priv->current], priv->dmabuffer[priv->current]); + priv->cb->au_receive(dev, priv->chanlist[priv->current], + priv->dmabuffer[priv->current]); priv->current++; if (priv->current >= priv->nchannels) { @@ -1221,8 +1231,8 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg) * Name: adc_bind * * Description: - * Bind the upper-half driver callbacks to the lower-half implementation. This - * must be called early in order to receive ADC event notifications. + * Bind the upper-half driver callbacks to the lower-half implementation. + * This must be called early in order to receive ADC event notifications. * ****************************************************************************/ @@ -1404,18 +1414,19 @@ static void adc_reset(FAR struct adc_dev_s *dev) leave_critical_section(flags); - ainfo("SR: 0x%08x CR1: 0x%08x CR2: 0x%08x\n", + ainfo("SR: 0x%08" PRIx32 " CR1: 0x%08" PRIx32 + " CR2: 0x%08" PRIx32 "\n", adc_getreg(priv, STM32_ADC_SR_OFFSET), adc_getreg(priv, STM32_ADC_CR1_OFFSET), adc_getreg(priv, STM32_ADC_CR2_OFFSET)); - ainfo("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n", + ainfo("SQR1: 0x%08" PRIx32 " SQR2: 0x%08" PRIx32 + " SQR3: 0x%08" PRIx32 "\n", adc_getreg(priv, STM32_ADC_SQR1_OFFSET), adc_getreg(priv, STM32_ADC_SQR2_OFFSET), adc_getreg(priv, STM32_ADC_SQR3_OFFSET)); - ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC_CCR)); - + ainfo("CCR: 0x%08" PRIx32 "\n", getreg32(STM32_ADC_CCR)); } /**************************************************************************** @@ -1524,7 +1535,8 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) * Name: adc_sqrbits ****************************************************************************/ -static uint32_t adc_sqrbits(FAR struct stm32_dev_s *priv, int first, int last, +static uint32_t adc_sqrbits(FAR struct stm32_dev_s *priv, int first, + int last, int offset) { uint32_t bits = 0; @@ -1556,7 +1568,6 @@ static bool adc_internal(FAR struct stm32_dev_s * priv) { return true; } - } } @@ -1602,14 +1613,17 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch) priv->nchannels = 1; } - bits = adc_sqrbits(priv, ADC_SQR3_FIRST, ADC_SQR3_LAST, ADC_SQR3_SQ_OFFSET); + bits = adc_sqrbits(priv, ADC_SQR3_FIRST, ADC_SQR3_LAST, + ADC_SQR3_SQ_OFFSET); adc_modifyreg(priv, STM32_ADC_SQR3_OFFSET, ~ADC_SQR3_RESERVED, bits); - bits = adc_sqrbits(priv, ADC_SQR2_FIRST, ADC_SQR2_LAST, ADC_SQR2_SQ_OFFSET); + bits = adc_sqrbits(priv, ADC_SQR2_FIRST, ADC_SQR2_LAST, + ADC_SQR2_SQ_OFFSET); adc_modifyreg(priv, STM32_ADC_SQR2_OFFSET, ~ADC_SQR2_RESERVED, bits); bits = ((uint32_t)priv->nchannels - 1) << ADC_SQR1_L_SHIFT | - adc_sqrbits(priv, ADC_SQR1_FIRST, ADC_SQR1_LAST, ADC_SQR1_SQ_OFFSET); + adc_sqrbits(priv, ADC_SQR1_FIRST, ADC_SQR1_LAST, + ADC_SQR1_SQ_OFFSET); adc_modifyreg(priv, STM32_ADC_SQR1_OFFSET, ~ADC_SQR1_RESERVED, bits); return OK; diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index a1fbbcdd57b..5f4175179a3 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -40,6 +40,7 @@ #include +#include #include #include #include @@ -601,7 +602,8 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, uint32_t regoffset; uint32_t regval; - dmainfo("paddr: %08x maddr: %08x ntransfers: %d scr: %08x\n", + dmainfo("paddr: %08" PRIx32 " maddr: %08" PRIx32 + " ntransfers: %zu scr: %08" PRIx32 "\n", paddr, maddr, ntransfers, scr); #ifdef CONFIG_STM32F7_DMACAPABLE @@ -875,13 +877,14 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) ****************************************************************************/ #ifdef CONFIG_STM32F7_DMACAPABLE -bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) +bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) { uint32_t transfer_size; uint32_t burst_length; uint32_t mend; - dmainfo("stm32_dmacapable: 0x%08x/%u 0x%08x\n", maddr, count, ccr); + dmainfo("stm32_dmacapable: 0x%08" PRIxPTR + "/%" PRIu32 " 0x%08" PRIx32 "\n", maddr, count, ccr); /* Verify that the address conforms to the memory transfer size. * Transfers to/from memory performed by the DMA controller are diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index d6a29485b65..edaac429b05 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -230,6 +230,7 @@ #include #include +#include #include #include #include @@ -1068,7 +1069,7 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv) * still pending. */ - i2cinfo("Timeout with CR: %04x SR: %04x\n", cr, sr); + i2cinfo("Timeout with CR: %04" PRIx32 " SR: %04" PRIx32 "\n", cr, sr); } /************************************************************************************ @@ -1102,7 +1103,8 @@ static inline void stm32_i2c_sem_init(FAR struct i2c_master_s *dev) */ nxsem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, 0, 0); - nxsem_set_protocol(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, SEM_PRIO_NONE); + nxsem_set_protocol(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, + SEM_PRIO_NONE); #endif } @@ -1573,7 +1575,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); - i2cinfo("ENTER: status = 0x%08x\n", status); + i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); /* Update private version of the state assuming a good state */ @@ -1621,16 +1623,18 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) { /* NACK received on first (address) byte: address is invalid */ - i2cinfo("NACK: Address invalid: dcnt=%i msgc=%i status=0x%08x\n", - priv->dcnt, priv->msgc, status); + i2cinfo("NACK: Address invalid: " + "dcnt=%i msgc=%i status=0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } else { /* NACK received on regular byte */ - i2cinfo("NACK: NACK received: dcnt=%i msgc=%i status=0x%08x\n", - priv->dcnt, priv->msgc, status); + i2cinfo("NACK: NACK received: " + "dcnt=%i msgc=%i status=0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } @@ -1683,7 +1687,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) /* TXIS interrupt occurred, address valid, ready to transmit */ stm32_i2c_traceevent(priv, I2CEVENT_WRITE, 0); - i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08x\n", + i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); /* The first event after the address byte is sent will be either TXIS @@ -1740,8 +1744,9 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) { /* Unsupported state */ - i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, status 0x%08x\n", - priv->dcnt, status); + i2cerr("ERROR: TXIS Unsupported state detected, " + "dcnt=%i, status 0x%08" PRIx32 "\n", + priv->dcnt, status); stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); /* Indicate the bad state, so that on termination HW will be reset */ @@ -1749,7 +1754,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) priv->status |= I2C_INT_BAD_STATE; } - i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08x\n", + i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); } @@ -1790,7 +1795,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) */ stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); - i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08x\n", + i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); /* If more bytes in the current message */ @@ -1830,7 +1835,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); - i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, status 0x%08x\n", + i2cerr("ERROR: RXNE Unsupported state detected, " + "dcnt=%i, status 0x%08" PRIx32 "\n", priv->dcnt, status); /* Set signals that will terminate ISR and wake waiting thread */ @@ -1840,7 +1846,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) priv->msgc = 0; } - i2cinfo("RXNE: EXIT dcnt = %i msgc = %i status 0x%08x\n", + i2cinfo("RXNE: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); } @@ -1875,7 +1881,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) else if ((status & I2C_ISR_TC) != 0) { - i2cinfo("TC: ENTER dcnt = %i msgc = %i status 0x%08x\n", + i2cinfo("TC: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); /* Prior message has been sent successfully. Or there could have @@ -1932,8 +1938,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) priv->msgc = 0; } - i2cinfo("TC: EXIT dcnt = %i msgc = %i status 0x%08x\n", - priv->dcnt, priv->msgc, status); + i2cinfo("TC: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); } /* Transfer Complete (Reload) State Handler @@ -1973,8 +1979,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) else if ((status & I2C_ISR_TCR) != 0) { - i2cinfo("TCR: ENTER dcnt = %i msgc = %i status 0x%08x\n", - priv->dcnt, priv->msgc, status); + i2cinfo("TCR: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); /* If no more bytes in the current message to transfer */ @@ -2059,8 +2065,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } - i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08x\n", - priv->dcnt, priv->msgc, status); + i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); } } @@ -2073,7 +2079,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) else if (priv->dcnt == -1 && priv->msgc == 0) { status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); - i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08x\n", status); + i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", + status); stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); } @@ -2096,7 +2103,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); - i2cerr("ERROR: Invalid state detected, status 0x%08x\n", status); + i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", + status); /* set condition to terminate ISR and wake waiting thread */ @@ -2170,7 +2178,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) } status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); - i2cinfo("EXIT: status = 0x%08x\n", status); + i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); return OK; } @@ -2385,19 +2393,21 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, /* Connection timed out */ errval = ETIMEDOUT; - i2cerr("ERROR: Waitdone timed out CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n", + i2cerr("ERROR: Waitdone timed out CR1: 0x%08" PRIx32 + " CR2: 0x%08" PRIx32 " status: 0x%08" PRIx32 "\n", cr1, cr2, status); } else { - i2cinfo("Waitdone success: CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n", - cr1, cr2, status); + i2cinfo("Waitdone success: CR1: 0x%08" PRIx32 + " CR2: 0x%08" PRIx32 " status: 0x%08" PRIx32 "\n", + cr1, cr2, status); } UNUSED(cr1); UNUSED(cr2); - i2cinfo("priv->status: 0x%08x\n", priv->status); + i2cinfo("priv->status: 0x%08" PRIx32 "\n", priv->status); /* Check for error status conditions */ diff --git a/arch/arm/src/stm32f7/stm32_otg.h b/arch/arm/src/stm32f7/stm32_otg.h index 90672ae24a9..0ddd843ead8 100644 --- a/arch/arm/src/stm32f7/stm32_otg.h +++ b/arch/arm/src/stm32f7/stm32_otg.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32f7/stm32_otg.h * * Copyright (C) 2012-2013, 2016 Gregory Nutt. All rights reserved. @@ -31,14 +31,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F7_STM32_OTG_H #define __ARCH_ARM_SRC_STM32F7_STM32_OTG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -49,11 +49,11 @@ #if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGFSHS) -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Configuration ********************************************************************/ +/* Configuration ************************************************************/ #ifndef CONFIG_OTG_PRI # define CONFIG_OTG_PRI NVIC_SYSH_PRIORITY_DEFAULT @@ -83,9 +83,9 @@ # define STM32_OTG_FIFO_SIZE 4096 #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -105,9 +105,9 @@ extern "C" * Initialize USB host device controller hardware. * * Input Parameters: - * controller -- If the device supports more than USB host controller, then - * this identifies which controller is being initializeed. Normally, this - * is just zero. + * controller -- If the device supports more than USB host controller, + * then this identifies which controller is being initialized. + * Normally, this is just zero. * * Returned Value: * And instance of the USB host interface. The controlling task should @@ -128,17 +128,18 @@ struct usbhost_connection_s; FAR struct usbhost_connection_s *stm32_otghost_initialize(int controller); #endif -/************************************************************************************ +/**************************************************************************** * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32_usbsuspend logic if the OTG FS device driver - * is used. This function is called whenever the USB enters or leaves suspend - * mode. This is an opportunity for the board logic to shutdown clocks, power, - * etc. while the USB is suspended. + * Board logic must provide the stm32_usbsuspend logic if the OTG FS + * device driver is used. This function is called whenever the USB enters + * or leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. * - ************************************************************************************/ + ****************************************************************************/ +struct usbdev_s; void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume); #undef EXTERN diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c index e94f405e5aa..b92a37cbc0c 100644 --- a/arch/arm/src/stm32f7/stm32_otgdev.c +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -41,6 +41,7 @@ #include #include +#include #include #include #include @@ -177,7 +178,8 @@ # define CONFIG_USBDEV_EP8_TXFIFO_SIZE 0 # endif -/* The actual FIFO addresses that we use must be aligned to 4-byte boundaries; +/* The actual FIFO addresses that we use must be aligned to 4-byte + * boundaries; * FIFO sizes must be provided in units of 32-bit words. */ @@ -260,7 +262,9 @@ OTG_GINT_SRQ | \ OTG_GINT_WKUP) -/* Only stm32F723 has internal ULPI. We consider in HS only if a ULPI is present */ +/* Only stm32F723 has internal ULPI. We consider in HS only if a ULPI is + * present + */ # ifdef CONFIG_STM32F7_OTGFSHS # define OTG_GINT_RESERVED OTG_GINT_RESERVED_HS @@ -270,7 +274,7 @@ # define OTG_GINT_RC_W1 OTG_GINT_RC_W1_FS # endif -/* Debug ***********************************************************************/ +/* Debug ********************************************************************/ /* Trace error codes */ @@ -364,7 +368,7 @@ # define STM32_TRACEINTID_SETUPDONE (90 + 3) # define STM32_TRACEINTID_SETUPRECVD (90 + 4) -/* Endpoints ******************************************************************/ +/* Endpoints ****************************************************************/ /* Odd physical endpoint numbers are IN; even are OUT */ @@ -387,17 +391,17 @@ # define STM32_MAXPACKET (64) /* Max packet size (1-64) */ # endif -/* Delays **********************************************************************/ +/* Delays *******************************************************************/ # define STM32_READY_DELAY 200000 # define STM32_FLUSH_DELAY 200000 -/* Request queue operations ****************************************************/ +/* Request queue operations *************************************************/ # define stm32_rqempty(ep) ((ep)->head == NULL) # define stm32_rqpeek(ep) ((ep)->head) -/* Standard stuff **************************************************************/ +/* Standard stuff ***********************************************************/ # ifndef MIN # define MIN(a,b) ((a) < (b) ? (a) : (b)) @@ -599,14 +603,14 @@ static void stm32_putreg(uint32_t val, uint32_t addr); # define stm32_putreg(val,addr) putreg32(val,addr) # endif -/* Request queue operations **************************************************/ +/* Request queue operations *************************************************/ static FAR struct stm32_req_s *stm32_req_remfirst(FAR struct stm32_ep_s *privep); static bool stm32_req_addlast(FAR struct stm32_ep_s *privep, FAR struct stm32_req_s *req); -/* Low level data transfers and request operations ***************************/ +/* Low level data transfers and request operations **************************/ /* Special endpoint 0 data transfer logic */ @@ -635,17 +639,19 @@ static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv, FAR struct stm32_ep_s *privep); static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt); -static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt); +static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, + int bcnt); static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, FAR struct stm32_ep_s *privep); /* General request handling */ static void stm32_ep_flush(FAR struct stm32_ep_s *privep); -static void stm32_req_complete(FAR struct stm32_ep_s *privep, int16_t result); +static void stm32_req_complete(FAR struct stm32_ep_s *privep, + int16_t result); static void stm32_req_cancel(FAR struct stm32_ep_s *privep, int16_t status); -/* Interrupt handling ********************************************************/ +/* Interrupt handling *******************************************************/ static struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, uint16_t eplog); @@ -658,9 +664,10 @@ static void stm32_usbreset(FAR struct stm32_usbdev_s *priv); static inline void stm32_ep0out_testmode(FAR struct stm32_usbdev_s *priv, uint16_t index); static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, - FAR struct stm32_ctrlreq_s *ctrlreq); + FAR struct stm32_ctrlreq_s *ctrlreq); static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv); -static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, uint8_t epno); +static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, + uint8_t epno); static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv); /* Second level IN endpoint interrupt processing */ @@ -690,7 +697,7 @@ static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv); static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg); -/* Endpoint operations *********************************************************/ +/* Endpoint operations ******************************************************/ /* Global OUT NAK controls */ @@ -704,7 +711,8 @@ static int stm32_epout_configure(FAR struct stm32_ep_s *privep, static int stm32_epin_configure(FAR struct stm32_ep_s *privep, uint8_t eptype, uint16_t maxpacket); static int stm32_ep_configure(FAR struct usbdev_ep_s *ep, - FAR const struct usb_epdesc_s *desc, bool last); + FAR const struct usb_epdesc_s *desc, + bool last); static void stm32_ep0_configure(FAR struct stm32_usbdev_s *priv); /* Endpoint disable */ @@ -715,14 +723,16 @@ static int stm32_ep_disable(FAR struct usbdev_ep_s *ep); /* Endpoint request management */ -static FAR struct usbdev_req_s *stm32_ep_allocreq(FAR struct usbdev_ep_s *ep); +static FAR struct usbdev_req_s *stm32_ep_allocreq( + FAR struct usbdev_ep_s *ep); static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *); /* Endpoint buffer management */ # ifdef CONFIG_USBDEV_DMA -static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, uint16_t bytes); +static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, + uint16_t bytes); static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf); # endif @@ -750,9 +760,10 @@ static void stm32_ep0_stall(FAR struct stm32_usbdev_s *priv); static FAR struct usbdev_ep_s *stm32_ep_alloc(FAR struct usbdev_s *dev, uint8_t epno, bool in, uint8_t eptype); -static void stm32_ep_free(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep); +static void stm32_ep_free(FAR struct usbdev_s *dev, + FAR struct usbdev_ep_s *ep); -/* USB device controller operations ********************************************/ +/* USB device controller operations *****************************************/ static int stm32_getframe(struct usbdev_s *dev); static int stm32_wakeup(struct usbdev_s *dev); @@ -762,7 +773,7 @@ static void stm32_setaddress(struct stm32_usbdev_s *priv, uint16_t address); static int stm32_txfifo_flush(uint32_t txfnum); static int stm32_rxfifo_flush(void); -/* Initialization **************************************************************/ +/* Initialization ***********************************************************/ static void stm32_swinitialize(FAR struct stm32_usbdev_s *priv); static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv); @@ -920,8 +931,8 @@ static uint32_t stm32_getreg(uint32_t addr) uint32_t val = getreg32(addr); - /* Is this the same value that we read from the same register last time? Are - * we polling the register? If so, suppress some of the output. + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. */ if (addr == prevaddr && val == preval) @@ -993,7 +1004,8 @@ static void stm32_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -static FAR struct stm32_req_s *stm32_req_remfirst(FAR struct stm32_ep_s *privep) +static FAR struct stm32_req_s *stm32_req_remfirst( + FAR struct stm32_ep_s *privep) { FAR struct stm32_req_s *ret = privep->head; @@ -1201,19 +1213,21 @@ static void stm32_epin_transfer(FAR struct stm32_ep_s *privep, if (nbytes == 0) { - /* Yes.. leave the transfer size at zero and set the packet count to 1 */ + /* Yes.. leave the transfer size at zero and set the packet count to + * 1 + */ pktcnt = 1; } else { /* No.. Program the transfer size and packet count . First calculate: - * xfrsize = The total number of bytes to be sent. pktcnt = the number of - * packets (of maxpacket bytes) required to perform the transfer. + * xfrsize = The total number of bytes to be sent. pktcnt = the number + * of packets (of maxpacket bytes) required to perform the transfer. */ - pktcnt = - ((uint32_t) nbytes + (privep->ep.maxpacket - 1)) / privep->ep.maxpacket; + pktcnt = ((uint32_t) nbytes + (privep->ep.maxpacket - 1)) / + privep->ep.maxpacket; } /* Set the XFRSIZ and PKTCNT */ @@ -1221,8 +1235,8 @@ static void stm32_epin_transfer(FAR struct stm32_ep_s *privep, regval |= (pktcnt << OTG_DIEPTSIZ_PKTCNT_SHIFT); regval |= ((uint32_t) nbytes << OTG_DIEPTSIZ_XFRSIZ_SHIFT); - /* If this is an isochronous endpoint, then set the multi-count field to the - * PKTCNT as well. + /* If this is an isochronous endpoint, then set the multi-count field to + * the PKTCNT as well. */ if (privep->eptype == USB_EP_ATTR_XFER_ISOC) @@ -1266,8 +1280,8 @@ static void stm32_epin_transfer(FAR struct stm32_ep_s *privep, stm32_putreg(regval, STM32_OTG_DIEPCTL(privep->epphy)); /* Transfer the data to the TxFIFO. At this point, the caller has already - * assured that there is sufficient space in the TxFIFO to hold the transfer - * we can just blindly continue. + * assured that there is sufficient space in the TxFIFO to hold the + * transfer we can just blindly continue. */ stm32_txfifo_write(privep, buf, nbytes); @@ -1320,10 +1334,10 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINREQEMPTY), privep->epphy); - /* There is no TX transfer in progress and no new pending TX requests to - * send. To stop transmitting any data on a particular IN endpoint, the - * application must set the IN NAK bit. To set this bit, the following - * field must be programmed. + /* There is no TX transfer in progress and no new pending TX requests + * to send. To stop transmitting any data on a particular IN endpoint, + * the application must set the IN NAK bit. To set this bit, the + * following field must be programmed. */ regaddr = STM32_OTG_DIEPCTL(privep->epphy); @@ -1341,26 +1355,27 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, privep->epphy, privreq, privreq->req.len, privreq->req.xfrd, privep->zlp); - /* Check for a special case: If we are just starting a request (xfrd==0) and - * the class driver is trying to send a zero-length packet (len==0). Then - * set the ZLP flag so that the packet will be sent. + /* Check for a special case: If we are just starting a request (xfrd==0) + * and the class driver is trying to send a zero-length packet (len==0). + * Then set the ZLP flag so that the packet will be sent. */ if (privreq->req.len == 0) { - /* The ZLP flag is set TRUE whenever we want to force the driver to send - * a zero-length-packet on the next pass through the loop (below). The - * flag is cleared whenever a packet is sent in the loop below. + /* The ZLP flag is set TRUE whenever we want to force the driver to + * send a zero-length-packet on the next pass through the loop (below). + * The flag is cleared whenever a packet is sent in the loop below. */ privep->zlp = true; } - /* Add one more packet to the TxFIFO. We will wait for the transfer complete - * event before we add the next packet (or part of a packet to the TxFIFO). - * The documentation says that we can can multiple packets to the TxFIFO, but - * it seems that we need to get the transfer complete event before we can add - * the next (or maybe I have got something wrong?) + /* Add one more packet to the TxFIFO. We will wait for the transfer + * complete event before we add the next packet (or part of a packet to + * the TxFIFO). + * The documentation says that we can can multiple packets to the TxFIFO, + * but it seems that we need to get the transfer complete event before we + * can add the next (or maybe I have got something wrong?) */ # if 0 @@ -1384,8 +1399,8 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, if (nbytes > 0) { - /* Either send the maxpacketsize or all of the remaining data in the - * request. + /* Either send the maxpacketsize or all of the remaining data in + * the request. */ if (nbytes >= privep->ep.maxpacket) @@ -1402,9 +1417,9 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, { /* The ZLP flag is set TRUE whenever we want to force the * driver to send a zero-length-packet on the next pass - * through this loop. The flag is cleared (above) whenever we - * are committed to sending any packet and set here when we - * want to force one more pass through the loop. + * through this loop. The flag is cleared (above) whenever + * we are committed to sending any packet and set here when + * we want to force one more pass through the loop. */ privep->zlp = true; @@ -1477,9 +1492,10 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, privreq->req.xfrd += nbytes; } - /* Note that the ZLP, if any, must be sent as a separate transfer. The need - * for a ZLP is indicated by privep->zlp. If all of the bytes were sent - * (including any final null packet) then we are finished with the transfer + /* Note that the ZLP, if any, must be sent as a separate transfer. The + * need for a ZLP is indicated by privep->zlp. If all of the bytes were + * sent (including any final null packet) then we are finished with the + * transfer */ if (privreq->req.xfrd >= privreq->req.len && !privep->zlp) @@ -1508,13 +1524,15 @@ static void stm32_rxfifo_read(FAR struct stm32_ep_s *privep, uint32_t regaddr; int i; - /* Get the address of the RxFIFO. Note: there is only one RxFIFO so we might - * as well use the address associated with EP0. + /* Get the address of the RxFIFO. Note: there is only one RxFIFO so we + * might as well use the address associated with EP0. */ regaddr = STM32_OTG_DFIFO_DEP(EP0); - /* Read 32-bits and write 4 x 8-bits at time (to avoid unaligned accesses) */ + /* Read 32-bits and write 4 x 8-bits at time (to avoid unaligned + * accesses) + */ for (i = 0; i < len; i += 4) { @@ -1583,8 +1601,8 @@ static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv, { struct stm32_req_s *privreq; - /* Since a transfer just completed, there must be a read request at the head - * of the endpoint request queue. + /* Since a transfer just completed, there must be a read request at the + * head of the endpoint request queue. */ privreq = stm32_rqpeek(privep); @@ -1621,13 +1639,14 @@ static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv, * Name: stm32_ep0out_receive * * Description: - * This function is called from the RXFLVL interrupt handler when new incoming - * data is available in the endpoint's RxFIFO. This function will simply - * copy the incoming data into pending request's data buffer. + * This function is called from the RXFLVL interrupt handler when new + * incoming data is available in the endpoint's RxFIFO. This function + * will simply copy the incoming data into pending request's data buffer. * ****************************************************************************/ -static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt) +static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, + int bcnt) { FAR struct stm32_usbdev_s *priv; @@ -1639,8 +1658,8 @@ static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt) uinfo("EP0: bcnt=%d\n", bcnt); usbtrace(TRACE_READ(EP0), bcnt); - /* Verify that an OUT SETUP request as received before this data was received - * in the RxFIFO. + /* Verify that an OUT SETUP request as received before this data was + * received in the RxFIFO. */ if (priv->ep0state == EP0STATE_SETUP_OUT) @@ -1664,9 +1683,9 @@ static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt) } else { - /* This is an error. We don't have any idea what to do with the EP0 data - * in this case. Just read and discard it so that the RxFIFO does not - * become constipated. + /* This is an error. We don't have any idea what to do with the EP0 + * data in this case. Just read and discard it so that the RxFIFO + * does not become constipated. */ usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOOUTSETUP), priv->ep0state); @@ -1679,13 +1698,14 @@ static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt) * Name: stm32_epout_receive * * Description: - * This function is called from the RXFLVL interrupt handler when new incoming - * data is available in the endpoint's RxFIFO. This function will simply - * copy the incoming data into pending request's data buffer. + * This function is called from the RXFLVL interrupt handler when new + * incoming data is available in the endpoint's RxFIFO. This function + * will simply copy the incoming data into pending request's data buffer. * ****************************************************************************/ -static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt) +static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, + int bcnt) { struct stm32_req_s *privreq; uint8_t *dest; @@ -1719,7 +1739,8 @@ static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt) * NAKing is working as expected. */ - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), + privep->epphy); /* Discard the data in the RxFIFO */ @@ -1764,8 +1785,8 @@ static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt) * * Description: * This function is called when either (1) new read request is received, or - * (2) a pending receive request completes. If there is no read in pending, - * then this function will initiate the next OUT (read) operation. + * (2) a pending receive request completes. If there is no read in + * pending, then this function will initiate the next OUT (read) operation. * ****************************************************************************/ @@ -1779,14 +1800,15 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, uint32_t pktcnt; /* Make sure that there is not already a pending request request. If there - * is, just return, leaving the newly received request in the request queue. + * is, just return, leaving the newly received request in the request + * queue. */ if (!privep->active) { /* Loop until a valid request is found (or the request queue is empty). - * The loop is only need to look at the request queue again is an invalid - * read request is encountered. + * The loop is only need to look at the request queue again is an + * invalid read request is encountered. */ for (; ; ) @@ -1802,9 +1824,9 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, privep->epphy); /* There are no read requests to be setup. Configure the - * hardware to NAK any incoming packets. (This should already be - * the case. I think that the hardware will automatically NAK - * after a transfer is completed until SNAK is cleared). + * hardware to NAK any incoming packets. (This should already + * be the case. I think that the hardware will automatically + * NAK after a transfer is completed until SNAK is cleared). */ regaddr = STM32_OTG_DOEPCTL(privep->epphy); @@ -1830,7 +1852,9 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, stm32_req_complete(privep, OK); } - /* Otherwise, we have a usable read request... break out of the loop */ + /* Otherwise, we have a usable read request... break out of the + * loop + */ else { @@ -1839,15 +1863,15 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, } /* Setup the pending read into the request buffer. First calculate: - * + * * pktcnt = the number of packets (of maxpacket bytes) required to * perform the transfer. * xfrsize = The total number of bytes required (in units of maxpacket * bytes). */ - pktcnt = - (privreq->req.len + (privep->ep.maxpacket - 1)) / privep->ep.maxpacket; + pktcnt = (privreq->req.len + (privep->ep.maxpacket - 1)) / + privep->ep.maxpacket; xfrsize = pktcnt * privep->ep.maxpacket; /* Then setup the hardware to perform this transfer */ @@ -1891,8 +1915,8 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, privep->active = true; - /* EP0 is a special case. We need to know when to switch back to normal - * SETUP processing. + /* EP0 is a special case. We need to know when to switch back to + * normal SETUP processing. */ if (privep->epphy == EP0) @@ -1926,7 +1950,8 @@ static void stm32_ep_flush(struct stm32_ep_s *privep) * Name: stm32_req_complete * * Description: - * Handle termination of the request at the head of the endpoint request queue. + * Handle termination of the request at the head of the endpoint request + * queue. * ****************************************************************************/ @@ -1979,7 +2004,8 @@ static void stm32_req_cancel(struct stm32_ep_s *privep, int16_t status) while (!stm32_rqempty(privep)) { - usbtrace(TRACE_COMPLETE(privep->epphy), (stm32_rqpeek(privep))->req.xfrd); + usbtrace(TRACE_COMPLETE(privep->epphy), + (stm32_rqpeek(privep))->req.xfrd); stm32_req_complete(privep, status); } } @@ -2025,8 +2051,8 @@ static struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, * Name: stm32_req_dispatch * * Description: - * Provide unhandled setup actions to the class driver. This is logically part - * of the USB interrupt handler. + * Provide unhandled setup actions to the class driver. This is logically + * part of the USB interrupt handler. * ****************************************************************************/ @@ -2214,7 +2240,7 @@ static inline void stm32_ep0out_testmode(FAR struct stm32_usbdev_s *priv, ****************************************************************************/ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, - FAR struct stm32_ctrlreq_s *ctrlreq) + FAR struct stm32_ctrlreq_s *ctrlreq) { FAR struct stm32_ep_s *privep; @@ -2272,8 +2298,9 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, { if (ctrlreq->index == 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVGETSTATUS), - 0); + usbtrace( + TRACE_INTDECODE(STM32_TRACEINTID_DEVGETSTATUS), + 0); /* Features: Remote Wakeup and self-powered */ @@ -2287,8 +2314,9 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADDEVGETSTATUS), - 0); + usbtrace( + TRACE_DEVERROR(STM32_TRACEERR_BADDEVGETSTATUS), + 0); priv->stalled = true; } } @@ -2414,13 +2442,16 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETADDRESS), ctrlreq->value); - if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE - && ctrlreq->index == 0 && ctrlreq->len == 0 && ctrlreq->value < 128 + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETADDRESS), + ctrlreq->value); + if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE + && ctrlreq->index == 0 && ctrlreq->len == 0 + && ctrlreq->value < 128 && priv->devstate != DEVSTATE_CONFIGURED) { - /* Save the address. We cannot actually change to the next address - * until the completion of the status phase. + /* Save the address. We cannot actually change to the next + * address until the completion of the status phase. */ stm32_setaddress(priv, (uint16_t) priv->ctrlreq.value[0]); @@ -2475,8 +2506,10 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), 0); if (priv->addressed && - (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE - && ctrlreq->value == 0 && ctrlreq->index == 0 && ctrlreq->len == 1) + (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE + && ctrlreq->value == 0 && ctrlreq->index == 0 + && ctrlreq->len == 1) { stm32_req_dispatch(priv, &priv->ctrlreq); } @@ -2498,7 +2531,8 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), 0); if (priv->addressed && - (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE + (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && ctrlreq->index == 0 && ctrlreq->len == 0) { /* Give the configuration to the class driver */ @@ -2619,7 +2653,8 @@ static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv) ctrlreq.len = GETUINT16(priv->ctrlreq.len); uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n", - ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len); + ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, + ctrlreq.len); /* Check for a standard request */ @@ -2640,7 +2675,8 @@ static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv) if (priv->stalled) { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), priv->ep0state); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), + priv->ep0state); stm32_ep0_stall(priv); } @@ -2668,8 +2704,9 @@ static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, uint8_t epno) { privep = &priv->epout[EP0]; - /* In the EP0STATE_DATA_OUT state, we are receiving data into the request - * buffer. In that case, we must continue the request processing. + /* In the EP0STATE_DATA_OUT state, we are receiving data into the + * request buffer. In that case, we must continue the request + * processing. */ if (priv->ep0state == EP0STATE_DATA_OUT) @@ -2678,8 +2715,8 @@ static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, uint8_t epno) stm32_epout_complete(priv, privep); - /* If we are not actively processing an OUT request, then we need to - * setup to receive the next control request. + /* If we are not actively processing an OUT request, then we need + * to setup to receive the next control request. */ if (!privep->active) @@ -2704,12 +2741,13 @@ static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, uint8_t epno) * Name: stm32_epout_interrupt * * Description: - * USB OUT endpoint interrupt handler. The core generates this interrupt when - * there is an interrupt is pending on one of the OUT endpoints of the core. - * The driver must read the OTG DAINT register to determine the exact number - * of the OUT endpoint on which the interrupt occurred, and then read the - * corresponding OTG DOEPINTx register to determine the exact cause of the - * interrupt. + * USB OUT endpoint interrupt handler. The core generates this interrupt + * when there is an interrupt is pending on one of the OUT endpoints of the + * core. + * The driver must read the OTG DAINT register to determine the exact + * number of the OUT endpoint on which the interrupt occurred, and then + * read the corresponding OTG DOEPINTx register to determine the exact + * cause of the interrupt. * ****************************************************************************/ @@ -2720,8 +2758,8 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) uint32_t doepint; int epno; - /* Get the pending, enabled interrupts for the OUT endpoint from the endpoint - * interrupt status register. + /* Get the pending, enabled interrupts for the OUT endpoint from the + * endpoint interrupt status register. */ regval = stm32_getreg(STM32_OTG_DAINT); @@ -2752,7 +2790,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) if ((daint & 1) != 0) { regval = stm32_getreg(STM32_OTG_DOEPINT(epno)); - uerr("DOEPINT(%d) = %08x\n", epno, regval); + uerr("DOEPINT(%d) = %08" PRIx32 "\n", epno, regval); stm32_putreg(0xff, STM32_OTG_DOEPINT(epno)); } @@ -2778,7 +2816,8 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) doepint &= stm32_getreg(STM32_OTG_DOEPMSK); /* Transfer completed interrupt. This interrupt is triggered when - * stm32_rxinterrupt() removes the last packet data from the RxFIFO. + * stm32_rxinterrupt() removes the last packet data from the + * RxFIFO. * In this case, core internally sets the NAK bit for this endpoint * to prevent it from receiving any more packets. */ @@ -2813,6 +2852,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) stm32_putreg(OTG_DOEPINT_EPDISD, STM32_OTG_DOEPINT(epno)); } # endif + /* Setup Phase Done (control EPs) */ if ((doepint & OTG_DOEPINT_SETUP) != 0) @@ -2829,6 +2869,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) { stm32_ep0out_setup(priv); } + stm32_putreg(OTG_DOEPINT_SETUP, STM32_OTG_DOEPINT(epno)); } } @@ -2884,8 +2925,8 @@ static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno) stm32_epin_request(priv, privep); - /* If we are not actively processing an OUT request, then we need to - * setup to receive the next control request. + /* If we are not actively processing an OUT request, then we need + * to setup to receive the next control request. */ if (!privep->active) @@ -2940,11 +2981,12 @@ static inline void stm32_epin_txfifoempty(FAR struct stm32_usbdev_s *priv, * Name: stm32_epin_interrupt * * Description: - * USB IN endpoint interrupt handler. The core generates this interrupt when - * an interrupt is pending on one of the IN endpoints of the core. The driver - * must read the OTG DAINT register to determine the exact number of the IN - * endpoint on which the interrupt occurred, and then read the corresponding - * OTG DIEPINTx register to determine the exact cause of the interrupt. + * USB IN endpoint interrupt handler. The core generates this interrupt + * when an interrupt is pending on one of the IN endpoints of the core. + * The driver must read the OTG DAINT register to determine the exact + * number of the IN endpoint on which the interrupt occurred, and then + * read the corresponding OTG DIEPINTx register to determine the exact + * cause of the interrupt. * ****************************************************************************/ @@ -2956,8 +2998,8 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) uint32_t empty; int epno; - /* Get the pending, enabled interrupts for the IN endpoint from the endpoint - * interrupt status register. + /* Get the pending, enabled interrupts for the IN endpoint from the + * endpoint interrupt status register. */ daint = stm32_getreg(STM32_OTG_DAINT); @@ -2977,7 +3019,8 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) */ daint = stm32_getreg(STM32_OTG_DAINT); - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINUNEXPECTED), (uint16_t) daint); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINUNEXPECTED), + (uint16_t)daint); daint &= OTG_DAINT_IEP_MASK; epno = 0; @@ -2986,7 +3029,7 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) { if ((daint & 1) != 0) { - uerr("DIEPINT(%d) = %08x\n", + uerr("DIEPINT(%d) = %08" PRIx32 "\n", epno, stm32_getreg(STM32_OTG_DIEPINT(epno))); stm32_putreg(0xff, STM32_OTG_DIEPINT(epno)); } @@ -3015,10 +3058,10 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) mask = stm32_getreg(STM32_OTG_DIEPMSK); /* Check if the TxFIFO not empty interrupt is enabled for this - * endpoint in the DIEPMSK register. Bits n corresponds to endpoint - * n in the register. That condition corresponds to bit 7 of the - * DIEPINT interrupt status register. There is no TXFE bit in the - * mask register, so we fake one here. + * endpoint in the DIEPMSK register. Bits n corresponds to + * endpoint n in the register. That condition corresponds to bit 7 + * of the DIEPINT interrupt status register. There is no TXFE bit + * in the mask register, so we fake one here. */ empty = stm32_getreg(STM32_OTG_DIEPEMPMSK); @@ -3034,6 +3077,7 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) diepint = stm32_getreg(STM32_OTG_DIEPINT(epno)) & mask; /* Decode and process the enabled, pending interrupts */ + /* Transfer completed interrupt */ if ((diepint & OTG_DIEPINT_XFRC) != 0) @@ -3042,9 +3086,9 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) (uint16_t) diepint); /* It is possible that logic may be waiting for a the TxFIFO to - * become empty. We disable the TxFIFO empty interrupt here; it - * will be re-enabled if there is still insufficient space in the - * TxFIFO. + * become empty. We disable the TxFIFO empty interrupt here; + * it will be re-enabled if there is still insufficient space + * in the TxFIFO. */ empty &= ~OTG_DIEPEMPMSK(epno); @@ -3066,10 +3110,10 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) } /* IN token received when TxFIFO is empty. Applies to non-periodic - * IN endpoints only. This interrupt indicates that an IN token was - * received when the associated TxFIFO (periodic/non-periodic) was - * empty. This interrupt is asserted on the endpoint for which the IN - * token was received. + * IN endpoints only. This interrupt indicates that an IN token + * was received when the associated TxFIFO (periodic/non-periodic) + * was empty. This interrupt is asserted on the endpoint for which + * the IN token was received. */ if ((diepint & OTG_DIEPINT_ITTXFE) != 0) @@ -3091,6 +3135,7 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) stm32_putreg(OTG_DIEPINT_INEPNE, STM32_OTG_DIEPINT(epno)); } # endif + /* Endpoint disabled interrupt (ignored as this used only in polled * mode) */ @@ -3102,6 +3147,7 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) stm32_putreg(OTG_DIEPINT_EPDISD, STM32_OTG_DIEPINT(epno)); } # endif + /* Transmit FIFO empty */ if ((diepint & OTG_DIEPINT_TXFE) != 0) @@ -3111,8 +3157,8 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) /* If we were waiting for TxFIFO to become empty, the we might * have both XFRC and TXFE interrupts pending. Since we do the - * same thing for both cases, ignore the TXFE if we have already - * processed the XFRC. + * same thing for both cases, ignore the TXFE if we have + * already processed the XFRC. */ if ((diepint & OTG_DIEPINT_XFRC) == 0) @@ -3226,7 +3272,9 @@ static inline void stm32_suspendinterrupt(FAR struct stm32_usbdev_s *priv) } # endif - /* Let the board-specific logic know that we have entered the suspend state */ + /* Let the board-specific logic know that we have entered the suspend + * state + */ stm32_usbsuspend((FAR struct usbdev_s *)priv, false); } @@ -3284,7 +3332,8 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) case OTG_GRXSTSD_PKTSTS_OUTRECVD: { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy); - bcnt = (regval & OTG_GRXSTSD_BCNT_MASK) >> OTG_GRXSTSD_BCNT_SHIFT; + bcnt = (regval & OTG_GRXSTSD_BCNT_MASK) >> + OTG_GRXSTSD_BCNT_SHIFT; if (bcnt > 0) { stm32_epout_receive(privep, bcnt); @@ -3292,10 +3341,10 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) } break; - /* OUT transfer completed. This indicates that an OUT data transfer - * for the specified OUT endpoint has completed. After this entry is - * popped from the receive FIFO, the core asserts a Transfer - * Completed interrupt on the specified OUT endpoint. + /* OUT transfer completed. This indicates that an OUT data + * transfer for the specified OUT endpoint has completed. After + * this entry is popped from the receive FIFO, the core asserts + * a Transfer Completed interrupt on the specified OUT endpoint. * * PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on * which the data transfer is complete, DPID = Don't Care. @@ -3321,9 +3370,9 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy); - /* Now that the Setup Phase is complete if it was an OUT enable the - * endpoint (Doing this here prevents the loss of the first FIFO - * word) + /* Now that the Setup Phase is complete if it was an OUT enable + * the endpoint (Doing this here prevents the loss of the first + * FIFO word) */ if (priv->ep0state == EP0STATE_SETUP_OUT) @@ -3351,8 +3400,8 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy); /* Read EP0 setup data. NOTE: If multiple SETUP packets are - * received, the last one overwrites the previous setup packets and - * only that last SETUP packet will be processed. + * received, the last one overwrites the previous setup packets + * and only that last SETUP packet will be processed. */ stm32_rxfifo_read(&priv->epout[EP0], @@ -3361,11 +3410,11 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) /* Was this an IN or an OUT SETUP packet. If it is an OUT SETUP, * then we need to wait for the completion of the data phase to - * process the setup command. If it is an IN SETUP packet, then we - * must processing the command BEFORE we enter the DATA phase. + * process the setup command. If it is an IN SETUP packet, then + * we must processing the command BEFORE we enter the DATA phase. * - * If the data associated with the OUT SETUP packet is zero length, - * then, of course, we don't need to wait. + * If the data associated with the OUT SETUP packet is zero + * length, then, of course, we don't need to wait. */ datlen = GETUINT16(priv->ctrlreq.len); @@ -3375,8 +3424,8 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) } else { - /* We can process the setup data as soon as SETUP done word is - * popped of the RxFIFO. + /* We can process the setup data as soon as SETUP done word + * is popped of the RxFIFO. */ priv->ep0state = EP0STATE_SETUP_READY; @@ -3429,9 +3478,9 @@ static inline void stm32_enuminterrupt(FAR struct stm32_usbdev_s *priv) * Name: stm32_isocininterrupt * * Description: - * Incomplete isochronous IN transfer interrupt. Assertion of the incomplete - * isochronous IN transfer interrupt indicates an incomplete isochronous IN - * transfer on at least one of the isochronous IN endpoints. + * Incomplete isochronous IN transfer interrupt. Assertion of the + * incomplete isochronous IN transfer interrupt indicates an incomplete + * isochronous IN transfer on at least one of the isochronous IN endpoints. * ****************************************************************************/ @@ -3472,8 +3521,8 @@ static inline void stm32_isocininterrupt(FAR struct stm32_usbdev_s *priv) doepctl = stm32_getreg(regaddr); dsts = stm32_getreg(STM32_OTG_DSTS); - /* EONUM = 0:even frame, 1:odd frame SOFFN = Frame number of the received - * SOF + /* EONUM = 0:even frame, 1:odd frame SOFFN = Frame number of the + * received SOF */ eonum = ((doepctl & OTG_DIEPCTL_EONUM) != 0); @@ -3637,7 +3686,8 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) /* At present, there is only a single OTG device support. Hence it is * pre-allocated as g_otghsdev. However, in most code, the private data * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple devices. + * global data) in order to simplify any future support for multiple + * devices. */ FAR struct stm32_usbdev_s *priv = &g_otghsdev; @@ -3651,8 +3701,9 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) DEBUGASSERT((stm32_getreg(STM32_OTG_GINTSTS) & OTG_GINTSTS_CMOD) == OTG_GINTSTS_DEVMODE); - /* Get the state of all enabled interrupts. We will do this repeatedly some - * interrupts (like RXFLVL) will generate additional interrupting events. + /* Get the state of all enabled interrupts. We will do this repeatedly + * some interrupts (like RXFLVL) will generate additional interrupting + * events. */ for (; ; ) @@ -3667,17 +3718,20 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) * pending irqs we will service below. */ - stm32_putreg(((regval | reserved) & OTG_GINT_RC_W1), STM32_OTG_GINTSTS); + stm32_putreg(((regval | reserved) & OTG_GINT_RC_W1), + STM32_OTG_GINTSTS); - /* Break out of the loop when there are no further pending (and unmasked) - * interrupts to be processes. + /* Break out of the loop when there are no further pending + * (and unmasked) interrupts to be processes. */ if (regval == 0) { break; } - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_INTPENDING), (uint16_t) regval); + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_INTPENDING), + (uint16_t)regval); /* OUT endpoint interrupt. The core sets this bit to indicate that an * interrupt is pending on one of the OUT endpoints of the core. @@ -3685,7 +3739,8 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & OTG_GINT_OEP) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), (uint16_t) regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), + (uint16_t)regval); stm32_epout_interrupt(priv); } @@ -3695,7 +3750,8 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & OTG_GINT_IEP) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), (uint16_t) regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), + (uint16_t)regval); stm32_epin_interrupt(priv); } @@ -3713,7 +3769,8 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & OTG_GINT_WKUP) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), (uint16_t) regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), + (uint16_t)regval); stm32_resumeinterrupt(priv); } @@ -3741,7 +3798,8 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & OTG_GINT_RXFLVL) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), (uint16_t) regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), + (uint16_t)regval); stm32_rxinterrupt(priv); } @@ -3783,12 +3841,12 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) /* Incomplete isochronous OUT transfer. For isochronous OUT endpoints, * the XFRC interrupt may not always be asserted. If the core drops - * isochronous OUT data packets, the application could fail to detect the - * XFRC interrupt. The incomplete Isochronous OUT data interrupt + * isochronous OUT data packets, the application could fail to detect + * the XFRC interrupt. The incomplete Isochronous OUT data interrupt * indicates that an XFRC interrupt was not asserted on at least one of * the isochronous OUT endpoints. At this point, the endpoint with the - * incomplete transfer remains enabled, but no active transfers remain in - * progress on this endpoint on the USB. + * incomplete transfer remains enabled, but no active transfers remain + * in progress on this endpoint on the USB. */ if ((regval & OTG_GINT_IISOOXFR) != 0) @@ -3851,9 +3909,9 @@ static void stm32_enablegonak(FAR struct stm32_ep_s *privep) stm32_putreg(regval, STM32_OTG_DCTL); # if 0 - /* Wait for the GONAKEFF interrupt that indicates that the OUT NAK mode is in - * effect. When the interrupt handler pops the OUTNAK word from the RxFIFO, - * the core sets the GONAKEFF interrupt. + /* Wait for the GONAKEFF interrupt that indicates that the OUT NAK mode is + * in effect. When the interrupt handler pops the OUTNAK word from the + * RxFIFO, the core sets the GONAKEFF interrupt. */ while ((stm32_getreg(STM32_OTG_GINTSTS) & OTG_GINT_GONAKEFF) == 0); @@ -3861,11 +3919,11 @@ static void stm32_enablegonak(FAR struct stm32_ep_s *privep) # else /* Since we are in the interrupt handler, we cannot wait inline for the - * GONAKEFF because it cannot occur until service the RXFLVL global interrupt - * and pop the OUTNAK word from the RxFIFO. + * GONAKEFF because it cannot occur until service the RXFLVL global + * interrupt and pop the OUTNAK word from the RxFIFO. * - * Perhaps it is sufficient to wait for Global OUT NAK status to be reported - * in OTG DCTL register? + * Perhaps it is sufficient to wait for Global OUT NAK status to be + * reported in OTG DCTL register? */ while ((stm32_getreg(STM32_OTG_DCTL) & OTG_DCTL_GONSTS) == 0); @@ -4165,8 +4223,8 @@ static void stm32_epout_disable(FAR struct stm32_ep_s *privep) /* Is this an IN or an OUT endpoint */ - /* Before disabling any OUT endpoint, the application must enable Global OUT - * NAK mode in the core. + /* Before disabling any OUT endpoint, the application must enable Global + * OUT NAK mode in the core. */ flags = enter_critical_section(); @@ -4199,8 +4257,8 @@ static void stm32_epout_disable(FAR struct stm32_ep_s *privep) stm32_putreg(OTG_DOEPINT_EPDISD, STM32_OTG_DOEPINT(privep->epphy)); - /* Then disable the Global OUT NAK mode to continue receiving data from other - * non-disabled OUT endpoints. + /* Then disable the Global OUT NAK mode to continue receiving data from + * other non-disabled OUT endpoints. */ stm32_disablegonak(privep); @@ -4234,7 +4292,8 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep) usbtrace(TRACE_EPDISABLE, privep->epphy); - /* After USB reset, the endpoint will already be deactivated by the hardware. + /* After USB reset, the endpoint will already be deactivated by the + * hardware. * Trying to disable again will just hang in the wait. */ @@ -4245,8 +4304,8 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep) return; } - /* This INEPNE wait logic is suggested by reference manual, but seems to get - * stuck to infinite loop. + /* This INEPNE wait logic is suggested by reference manual, but seems to + * get stuck to infinite loop. */ # if 0 @@ -4264,7 +4323,9 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep) regval |= (OTG_DIEPCTL_EPDIS | OTG_DIEPCTL_SNAK); stm32_putreg(regval, regaddr); - /* Wait for the INEPNE interrupt that indicates that we are now in NAK mode */ + /* Wait for the INEPNE interrupt that indicates that we are now in NAK + * mode + */ regaddr = STM32_OTG_DIEPINT(privep->epphy); while ((stm32_getreg(regaddr) & OTG_DIEPINT_INEPNE) == 0); @@ -4274,8 +4335,8 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep) stm32_putreg(OTG_DIEPINT_INEPNE, regaddr); # endif - /* Deactivate and disable the endpoint by setting the EPDIS and SNAK bits the - * DIEPCTLx register. + /* Deactivate and disable the endpoint by setting the EPDIS and SNAK bits + * the DIEPCTLx register. */ flags = enter_critical_section(); @@ -4477,8 +4538,8 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, if (!req || !req->callback || !req->buf || !ep) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, - ep); + uinfo("req=%p callback=%p buf=%p ep=%p\n", + req, req->callback, req->buf, ep); return -EINVAL; } # endif @@ -4516,8 +4577,8 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, if (stm32_req_addlast(privep, privreq) && !privep->active) { - /* If a request was added to an IN endpoint, then attempt to send the - * request data buffer now. + /* If a request was added to an IN endpoint, then attempt to send + * the request data buffer now. */ if (privep->isin) @@ -4534,9 +4595,9 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, } } - /* If the request was added to an OUT endpoint, then attempt to setup - * a read into the request data buffer now (this will, of course, - * fail if there is already a read in place). + /* If the request was added to an OUT endpoint, then attempt to + * setup a read into the request data buffer now (this will, + * of course, fail if there is already a read in place). */ else @@ -4577,9 +4638,9 @@ static int stm32_ep_cancel(FAR struct usbdev_ep_s *ep, flags = enter_critical_section(); - /* FIXME: if the request is the first, then we need to flush the EP otherwise - * just remove it from the list but ... all other implementations cancel all - * requests ... + /* FIXME: if the request is the first, then we need to flush the EP + * otherwise just remove it from the list but ... all other + * implementations cancel all requests ... */ stm32_req_cancel(privep, -ESHUTDOWN); @@ -4609,8 +4670,8 @@ static int stm32_epout_setstall(FAR struct stm32_ep_s *privep) stm32_enablegonak(privep); - /* Disable and STALL the OUT endpoint by setting the EPDIS and STALL bits in - * the DOECPTL register. + /* Disable and STALL the OUT endpoint by setting the EPDIS and STALL bits + * in the DOECPTL register. */ regaddr = STM32_OTG_DOEPCTL(privep->epphy); @@ -4641,12 +4702,15 @@ static int stm32_epout_setstall(FAR struct stm32_ep_s *privep) return OK; # else /* This implementation follows the STMicro code example. */ + /* REVISIT: */ uint32_t regaddr; uint32_t regval; - /* Stall the OUT endpoint by setting the STALL bit in the DOECPTL register. */ + /* Stall the OUT endpoint by setting the STALL bit in the DOECPTL + * register. + */ regaddr = STM32_OTG_DOEPCTL(privep->epphy); regval = stm32_getreg(regaddr); @@ -4797,6 +4861,7 @@ static int stm32_ep_stall(FAR struct usbdev_ep_s *ep, bool resume) { ret = stm32_ep_setstall(privep); } + leave_critical_section(flags); return ret; @@ -4829,12 +4894,13 @@ static void stm32_ep0_stall(FAR struct stm32_usbdev_s *priv) * Allocate an endpoint matching the parameters. * * Input Parameters: - * eplog - 7-bit logical endpoint number (direction bit ignored). Zero means - * that any endpoint matching the other requirements will suffice. The - * assigned endpoint can be found in the eplog field. + * eplog - 7-bit logical endpoint number (direction bit ignored). Zero + * means that any endpoint matching the other requirements will + * suffice. The assigned endpoint can be found in the eplog + * field. * in - true: IN (device-to-host) endpoint requested - * eptype - Endpoint type. One of {USB_EP_ATTR_XFER_ISOC, USB_EP_ATTR_XFER_BULK, - * USB_EP_ATTR_XFER_INT} + * eptype - Endpoint type. One of {USB_EP_ATTR_XFER_ISOC, + * USB_EP_ATTR_XFER_BULK, USB_EP_ATTR_XFER_INT} * ****************************************************************************/ @@ -4924,7 +4990,8 @@ static FAR struct usbdev_ep_s *stm32_ep_alloc(FAR struct usbdev_s *dev, * ****************************************************************************/ -static void stm32_ep_free(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep) +static void stm32_ep_free(FAR struct usbdev_s *dev, + FAR struct usbdev_ep_s *ep) { FAR struct stm32_usbdev_s *priv = (FAR struct stm32_usbdev_s *)dev; FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; @@ -5216,8 +5283,8 @@ static void stm32_swinitialize(FAR struct stm32_usbdev_s *priv) privep->dev = priv; privep->isin = 1; - /* The index, i, is the physical endpoint address; Map this to a logical - * endpoint address usable by the class driver. + /* The index, i, is the physical endpoint address; Map this to a + * logical endpoint address usable by the class driver. */ privep->epphy = i; @@ -5242,8 +5309,8 @@ static void stm32_swinitialize(FAR struct stm32_usbdev_s *priv) privep->ep.ops = &g_epops; privep->dev = priv; - /* The index, i, is the physical endpoint address; Map this to a logical - * endpoint address usable by the class driver. + /* The index, i, is the physical endpoint address; Map this to a + * logical endpoint address usable by the class driver. */ privep->epphy = i; @@ -5275,7 +5342,8 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) /* Disable global interrupts by clearing the GINTMASK bit in the GAHBCFG * register; Set the TXFELVL bit in the GAHBCFG register so that TxFIFO - * interrupts will occur when the TxFIFO is truly empty (not just half full). + * interrupts will occur when the TxFIFO is truly empty (not just half + * full). */ stm32_putreg(OTG_GAHBCFG_TXFELVL, STM32_OTG_GAHBCFG); @@ -5361,6 +5429,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) # endif /* CONFIG_STM32F7_OTGFSHS */ /* Common USB OTG core initialization */ + /* Reset after a PHY select and set Host mode. First, wait for AHB master * IDLE state. */ @@ -5427,6 +5496,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) up_mdelay(50); /* Initialize device mode */ + /* Restart the PHY Clock */ stm32_putreg(0, STM32_OTG_PCGCCTL); @@ -5588,8 +5658,8 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) # if defined(CONFIG_STM32F7_OTGFSHS) && defined(CONFIG_STM32F7_NO_ULPI) /* Disable the ULPI Clock enable in RCC AHB1 Register. This must be done * because if both the ULPI and the FS PHY clock enable bits are set at the - * same time, the ARM never awakens from WFI due to some bug / errata in the - * chip. + * same time, the ARM never awakens from WFI due to some bug / errata in + * the chip. */ regval = stm32_getreg(STM32_RCC_AHB1LPENR); @@ -5622,8 +5692,8 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) /* Enable the USB global interrupt by setting GINTMSK in the global OTG AHB * configuration register; Set the TXFELVL bit in the GAHBCFG register so - * that TxFIFO interrupts will occur when the TxFIFO is truly empty (not just - * half full). + * that TxFIFO interrupts will occur when the TxFIFO is truly empty (not + * just half full). */ stm32_putreg(OTG_GAHBCFG_GINTMSK | OTG_GAHBCFG_TXFELVL, STM32_OTG_GAHBCFG); @@ -5642,9 +5712,9 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) * Assumptions: * - This function is called very early in the initialization sequence * - PLL and GIO pin initialization is not performed here but should been in - * the low-level boot logic: PLL1 must be configured for operation at 48MHz - * and P0.23 and PO.31 in PINSEL1 must be configured for Vbus and USB connect - * LED. + * the low-level boot logic: PLL1 must be configured for operation at + * 48MHz and P0.23 and PO.31 in PINSEL1 must be configured for Vbus and + * USB connect LED. * ****************************************************************************/ @@ -5653,7 +5723,8 @@ void arm_usbinitialize(void) /* At present, there is only a single OTG device support. Hence it is * pre-allocated as g_otghsdev. However, in most code, the private data * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple devices. + * global data) in order to simplify any future support for multiple + * devices. */ FAR struct stm32_usbdev_s *priv = &g_otghsdev; @@ -5694,7 +5765,7 @@ void arm_usbinitialize(void) ret = irq_attach(STM32_IRQ_OTG, stm32_usbinterrupt, NULL); if (ret < 0) { - uerr("irq_attach failed\n", ret); + uerr("irq_attach failed: %d\n", ret); goto errout; } @@ -5729,7 +5800,8 @@ void arm_usbuninitialize(void) /* At present, there is only a single OTG device support. Hence it is * pre-allocated as g_otghsdev. However, in most code, the private data * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple devices. + * global data) in order to simplify any future support for multiple + * devices. */ FAR struct stm32_usbdev_s *priv = &g_otghsdev; @@ -5784,8 +5856,8 @@ void arm_usbuninitialize(void) * Name: usbdev_register * * Description: - * Register a USB device class driver. The class driver's bind() method will be - * called to bind it to a USB device driver. + * Register a USB device class driver. The class driver's bind() method + * will be called to bind it to a USB device driver. * ****************************************************************************/ @@ -5794,7 +5866,8 @@ int usbdev_register(struct usbdevclass_driver_s *driver) /* At present, there is only a single OTG device support. Hence it is * pre-allocated as g_otghsdev. However, in most code, the private data * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple devices. + * global data) in order to simplify any future support for multiple + * devices. */ FAR struct stm32_usbdev_s *priv = &g_otghsdev; @@ -5859,9 +5932,10 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * Name: usbdev_unregister * * Description: - * Un-register usbdev class driver.If the USB device is connected to a USB host, - * it will first disconnect(). The driver is also requested to unbind() and clean - * up any device state, before this procedure finally returns. + * Un-register usbdev class driver.If the USB device is connected to a + * USB host, it will first disconnect(). The driver is also requested to + * unbind() and clean up any device state, before this procedure finally + * returns. * ****************************************************************************/ @@ -5870,7 +5944,8 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) /* At present, there is only a single OTG device support. Hence it is * pre-allocated as g_otghsdev. However, in most code, the private data * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple devices. + * global data) in order to simplify any future support for multiple + * devices. */ FAR struct stm32_usbdev_s *priv = &g_otghsdev; @@ -5886,8 +5961,8 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) } # endif - /* Reset the hardware and cancel all requests. All requests must be canceled - * while the class driver is still bound. + /* Reset the hardware and cancel all requests. All requests must be + * canceled while the class driver is still bound. */ flags = enter_critical_section(); diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index c3c1cd5e8b5..3cd947b848e 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -41,6 +41,7 @@ #include +#include #include #include #include @@ -549,7 +550,7 @@ static void stm32_blocksetup(FAR struct sdio_dev_s *dev, static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, size_t nbytes); static int stm32_sendsetup(FAR struct sdio_dev_s *dev, - FAR const uint8_t *buffer, uint32_t nbytes); + FAR const uint8_t *buffer, size_t nbytes); static int stm32_cancel(FAR struct sdio_dev_s *dev); static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd); @@ -836,7 +837,7 @@ static inline void stm32_setclkcr(struct stm32_dev_s *priv, uint32_t clkcr) regval |= clkcr; sdmmc_putreg32(priv, regval, STM32_SDMMC_CLKCR_OFFSET); - mcinfo("CLKCR: %08x PWR: %08x\n", + mcinfo("CLKCR: %08" PRIx32 "PWR: %08" PRIx32 "\n", sdmmc_getreg32(priv, STM32_SDMMC_CLKCR_OFFSET), sdmmc_getreg32(priv, STM32_SDMMC_POWER_OFFSET)); } @@ -1940,7 +1941,7 @@ static void stm32_reset(FAR struct sdio_dev_s *dev) stm32_setpwrctrl(priv, STM32_SDMMC_POWER_PWRCTRL_ON); leave_critical_section(flags); - mcinfo("CLCKR: %08x POWER: %08x\n", + mcinfo("CLCKR: %08" PRIx32 " POWER: %08" PRIx32 "\n", sdmmc_getreg32(priv, STM32_SDMMC_CLKCR_OFFSET), sdmmc_getreg32(priv, STM32_SDMMC_POWER_OFFSET)); } @@ -2188,7 +2189,8 @@ static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT; regval |= cmdidx | STM32_SDMMC_CMD_CPSMEN; - mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval); + mcinfo("cmd: %08" PRIx32 " arg: %08" PRIx32 + " regval: %08" PRIx32 "\n", cmd, arg, regval); /* Write the SDIO CMD */ @@ -2449,8 +2451,9 @@ static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { if (--timeout <= 0) { - mcerr("ERROR: Timeout cmd: %08x events: %08x STA: %08x\n", - cmd, events, sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET)); + mcerr("ERROR: Timeout cmd: %08" PRIx32 + " events: %08" PRIx32 " STA: %08" PRIx32 "\n", + cmd, events, sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET)); return -ETIMEDOUT; } @@ -2539,12 +2542,12 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, regval = sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET); if ((regval & STM32_SDMMC_STA_CTIMEOUT) != 0) { - mcerr("ERROR: Command timeout: %08x\n", regval); + mcerr("ERROR: Command timeout: %08" PRIx32 "\n", regval); ret = -ETIMEDOUT; } else if ((regval & STM32_SDMMC_STA_CCRCFAIL) != 0) { - mcerr("ERROR: CRC failure: %08x\n", regval); + mcerr("ERROR: CRC failure: %08" PRIx32 "\n", regval); ret = -EIO; } #ifdef CONFIG_DEBUG_FEATURES @@ -2605,12 +2608,12 @@ static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, regval = sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET); if (regval & STM32_SDMMC_STA_CTIMEOUT) { - mcerr("ERROR: Timeout STA: %08x\n", regval); + mcerr("ERROR: Timeout STA: %08" PRIx32 "\n", regval); ret = -ETIMEDOUT; } else if (regval & STM32_SDMMC_STA_CCRCFAIL) { - mcerr("ERROR: CRC fail STA: %08x\n", regval); + mcerr("ERROR: CRC fail STA: %08" PRIx32 "\n", regval); ret = -EIO; } } @@ -2653,7 +2656,7 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R4_RESPONSE && (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE) { - mcerr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd); ret = -EINVAL; } else @@ -2666,7 +2669,7 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, regval = sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET); if (regval & STM32_SDMMC_STA_CTIMEOUT) { - mcerr("ERROR: Timeout STA: %08x\n", regval); + mcerr("ERROR: Timeout STA: %08" PRIx32 "\n", regval); ret = -ETIMEDOUT; } } diff --git a/arch/arm/src/stm32f7/stm32_spi.c b/arch/arm/src/stm32f7/stm32_spi.c index e394a44d090..f5433199c0e 100644 --- a/arch/arm/src/stm32f7/stm32_spi.c +++ b/arch/arm/src/stm32f7/stm32_spi.c @@ -48,6 +48,7 @@ #include #include +#include #include #include #include @@ -1348,7 +1349,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, * will be faster. */ - spiinfo("Frequency %d->%d\n", frequency, actual); + spiinfo("Frequency %" PRId32 "->%" PRId32 "\n", frequency, actual); priv->frequency = frequency; priv->actual = actual; @@ -1635,11 +1636,15 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd) if (priv->nbits > 8) { - spiinfo("Sent: %04x Return: %04x Status: %02x\n", wd, ret, regval); + spiinfo("Sent: %04" PRIx32 " Return: %04" PRIx32 + " Status: %02" PRIx32 "\n", + wd, ret, regval); } else { - spiinfo("Sent: %02x Return: %02x Status: %02x\n", wd, ret, regval); + spiinfo("Sent: %02" PRIx32 " Return: %02" PRIx32 + " Status: %02" PRIx32 "\n", + wd, ret, regval); } UNUSED(regval); @@ -1820,9 +1825,9 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, /* If this bus uses a in driver DMA aligned buffers we can skip the test */ if ((txbuffer && priv->txbuf == 0 && - !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || + !stm32_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) || (rxbuffer && priv->rxbuf == 0 && - !stm32_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) + !stm32_dmacapable((uintptr_t)rxbuffer, nwords, priv->rxccr))) { /* Unsupported memory region or not in driver buffers * fall back to non-DMA method. diff --git a/arch/arm/src/stm32h7/hardware/stm32_dmamux.h b/arch/arm/src/stm32h7/hardware/stm32_dmamux.h index 4cf6349cf61..2c12df36861 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_dmamux.h +++ b/arch/arm/src/stm32h7/hardware/stm32_dmamux.h @@ -133,46 +133,55 @@ /* DMAMUX12 request line multiplexer channel x configuration register */ -#define DMAMUX_CCR_DMAREQID_SHIFT (0) /* Bits 0-6: DMA request identification */ +#define DMAMUX_CCR_DMAREQID_SHIFT (0) /* Bits 0-6: DMA request identification */ #define DMAMUX_CCR_DMAREQID_MASK (0x7f << DMAMUX_CCR_DMAREQID_SHIFT) -#define DMAMUX_CCR_SOIE (8) /* Bit 8: Synchronization overrun interrupt enable */ -#define DMAMUX_CCR_EGE (9) /* Bit 9: Event generation enable */ -#define DMAMUX_CCR_SE (16) /* Bit 16: Synchronization enable */ -#define DMAMUX_CCR_SPOL_SHIFT (17) /* Bits 17-18: Synchronization polarity */ -#define DMAMUX_CCR_SPOL_MASK (3 << DMAMUX_CCR_SPOL_SHIFT) -#define DMAMUX_CCR_NBREQ_SHIFT (19) /* Bits 19-23: Number of DMA request - 1 to forward */ +#define DMAMUX_CCR_SOIE (8) /* Bit 8: Synchronization overrun interrupt enable */ +#define DMAMUX_CCR_EGE (9) /* Bit 9: Event generation enable */ +#define DMAMUX_CCR_SE (16) /* Bit 16: Synchronization enable */ +#define DMAMUX_CCR_SPOL_SHIFT (17) /* Bits 17-18: Synchronization polarity */ +#define DMAMUX_CCR_SPOL_MASK (0x3 << DMAMUX_CCR_SPOL_SHIFT) +# define DMAMUX_CCR_SPOL_NONE (0x0 << DMAMUX_CCR_SPOL_SHIFT) /* No event: No trigger detection or generation */ +# define DMAMUX_CCR_SPOL_RISING (0x1 << DMAMUX_CCR_SPOL_SHIFT) /* Rising edge */ +# define DMAMUX_CCR_SPOL_FALLING (0x2 << DMAMUX_CCR_SPOL_SHIFT) /* Falling edge */ +# define DMAMUX_CCR_SPOL_BOTH (0x3 << DMAMUX_CCR_SPOL_SHIFT) /* Both rising and falling edges */ +#define DMAMUX_CCR_NBREQ_SHIFT (19) /* Bits 19-23: Number of DMA request - 1 to forward */ #define DMAMUX_CCR_NBREQ_MASK (0x1f << DMAMUX_CCR_NBREQ_SHIFT) -#define DMAMUX_CCR_SYNCID_SHIFT (24) /* Bits 24-26: Synchronization identification */ +#define DMAMUX_CCR_SYNCID_SHIFT (24) /* Bits 24-26: Synchronization identification */ #define DMAMUX_CCR_SYNCID_MASK (7 << DMAMUX_CCR_SYNCID_SHIFT) /* DMAMUX12 request line multiplexer interrupt channel status register */ -#define DMAMUX1_CSR_SOF(x) (1 << x) /* Synchronization overrun event flag */ +#define DMAMUX1_CSR_SOF(x) (1 << (x)) /* Synchronization overrun event flag */ /* DMAMUX12 request line multiplexer interrupt clear flag register */ -#define DMAMUX1_CFR_SOF(x) (1 << x) /* Clear synchronization overrun event flag */ +#define DMAMUX1_CFR_CSOF(x) (1 << (x)) /* Clear synchronization overrun event flag */ /* DMAMUX12 request generator channel x configuration register */ -#define DMAMUX_RGCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identifiaction - * WARNING: different length for DMAMUX1 and DMAMUX2 ! - */ +#define DMAMUX_RGCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identification + * WARNING: different length for DMAMUX1 and DMAMUX2! + * DMAMUX1: 3 bits; DMAMUX2: 5 bits + */ #define DMAMUX_RGCR_SIGID_MASK (0x1f << DMAMUX_RGCR_SIGID_SHIFT) -#define DMAMUX_RGCR_OIE (8) /* Bit 8: Trigger overrun interrupt enable */ -#define DMAMUX_RGCR_GE (16) /* Bit 16: DMA request generator channel X enable*/ -#define DMAMUX_RGCR_GPOL_SHIFT (17) /* Bits 17-18: DMA request generator trigger polarity */ -#define DMAMUX_RGCR_GPOL_MASK (7 << DMAMUX_RGCR_GPOL_SHIFT) -#define DMAMUX_RGCR_GNBREQ_SHIFT (17) /* Bits 19-23: Number of DMA requests to be generated -1 */ -#define DMAMUX_RGCR_GNBREQL_MASK (7 << DMAMUX_RGCR_GNBREQ_SHIFT) +#define DMAMUX_RGCR_OIE (8) /* Bit 8: Trigger overrun interrupt enable */ +#define DMAMUX_RGCR_GE (16) /* Bit 16: DMA request generator channel X enable*/ +#define DMAMUX_RGCR_GPOL_SHIFT (17) /* Bits 17-18: DMA request generator trigger polarity */ +#define DMAMUX_RGCR_GPOL_MASK (0x3 << DMAMUX_RGCR_GPOL_SHIFT) +# define DMAMUX_RGCR_GPOL_NONE (0x0 << DMAMUX_RGCR_GPOL_SHIFT) /* No event: No trigger detection or generation */ +# define DMAMUX_RGCR_GPOL_RISING (0x1 << DMAMUX_RGCR_GPOL_SHIFT) /* Rising edge */ +# define DMAMUX_RGCR_GPOL_FALLING (0x2 << DMAMUX_RGCR_GPOL_SHIFT) /* Falling edge */ +# define DMAMUX_RGCR_GPOL_BOTH (0x3 << DMAMUX_RGCR_GPOL_SHIFT) /* Both rising and falling edges */ +#define DMAMUX_RGCR_GNBREQ_SHIFT (19) /* Bits 19-23: Number of DMA requests to be generated -1 */ +#define DMAMUX_RGCR_GNBREQL_MASK (0x1f << DMAMUX_RGCR_GNBREQ_SHIFT) /* DMAMUX12 request generator interrupt status register */ -#define DMAMUX1_RGSR_SOF(x) (1 << x) /* Trigger overrun event flag */ +#define DMAMUX1_RGSR_OF(x) (1 << (x)) /* Trigger overrun event flag */ /* DMAMUX12 request generator interrupt clear flag register */ -#define DMAMUX1_RGCFR_SOF(x) (1 << x) /* Clear trigger overrun event flag */ +#define DMAMUX1_RGCFR_COF(x) (1 << (x)) /* Clear trigger overrun event flag */ /* DMA channel mapping * @@ -182,7 +191,7 @@ * X - free bits */ -#define DMAMAP_MAP(d,c) ((d) << 8 | c) +#define DMAMAP_MAP(d,c) ((d) << 8 | (c)) #define DMAMAP_CONTROLLER(m) ((m) >> 8 & 0x07) #define DMAMAP_REQUEST(m) ((m) >> 0 & 0xff) diff --git a/arch/arm/src/stm32h7/stm32_allocateheap.c b/arch/arm/src/stm32h7/stm32_allocateheap.c index 376738bd05a..36c7d9efc76 100644 --- a/arch/arm/src/stm32h7/stm32_allocateheap.c +++ b/arch/arm/src/stm32h7/stm32_allocateheap.c @@ -40,6 +40,7 @@ #include #include +#include #include #include #include @@ -314,7 +315,7 @@ static void addregion (uintptr_t start, uint32_t size, const char *desc) { /* Display memory ranges to help debugging */ - minfo("%uKb of %s at %p\n", size / 1024, desc, (FAR void *)start); + minfo("%" PRIu32 "Kb of %s at %p\n", size / 1024, desc, (FAR void *)start); #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -344,10 +345,16 @@ static void addregion (uintptr_t start, uint32_t size, const char *desc) void arm_addregion(void) { - addregion (SRAM123_START, SRAM123_END - SRAM123_START, "SRAM1,2,3"); + /* At this point there is already one region allocated for "kernel" heap */ unsigned mm_regions = 1; + if (mm_regions < CONFIG_MM_REGIONS) + { + addregion (SRAM123_START, SRAM123_END - SRAM123_START, "SRAM1,2,3"); + mm_regions++; + } + if (mm_regions < CONFIG_MM_REGIONS) { addregion (SRAM4_START, SRAM4_END - SRAM4_START, "SRAM4"); diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c b/arch/arm/src/stm32h7/stm32_ethernet.c index 6a231b5cf97..a829fdc3288 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.c +++ b/arch/arm/src/stm32h7/stm32_ethernet.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -41,6 +42,7 @@ #include #include #include +#include #if defined(CONFIG_NET_PKT) # include @@ -1102,7 +1104,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) txdesc = priv->txhead; txfirst = txdesc; - ninfo("d_len: %d d_buf: %p txhead: %p tdes3: %08x\n", + ninfo("d_len: %d d_buf: %p txhead: %p tdes3: %08" PRIx32 "\n", priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->des3); DEBUGASSERT(txdesc); @@ -1823,7 +1825,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) * next frame. */ - nwarn("WARNING: DROPPED RX descriptor errors: %08x\n", + nwarn("WARNING: DROPPED RX descriptor errors: " + "%08" PRIx32 "\n", rxdesc->des3); stm32_freesegment(priv, rxcurr, priv->segments); } @@ -2082,7 +2085,8 @@ static void stm32_freeframe(struct stm32_ethmac_s *priv) * TX descriptors. */ - ninfo("txtail: %p des0: %08x des2: %08x des3: %08x\n", + ninfo("txtail: %p des0: %08" PRIx32 + " des2: %08" PRIx32 " des3: %08" PRIx32 "\n", txdesc, txdesc->des0, txdesc->des2, txdesc->des3); DEBUGASSERT(txdesc->des0 != 0); @@ -2564,8 +2568,8 @@ static int stm32_ifup(struct net_driver_s *dev) #ifdef CONFIG_NET_IPv4 ninfo("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + (int)(dev->d_ipaddr & 0xff), (int)((dev->d_ipaddr >> 8) & 0xff), + (int)((dev->d_ipaddr >> 16) & 0xff), (int)(dev->d_ipaddr >> 24)); #endif #ifdef CONFIG_NET_IPv6 ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", diff --git a/arch/arm/src/stm32h7/stm32_i2c.c b/arch/arm/src/stm32h7/stm32_i2c.c index 67b3613ddf6..0ca9cbe1f72 100644 --- a/arch/arm/src/stm32h7/stm32_i2c.c +++ b/arch/arm/src/stm32h7/stm32_i2c.c @@ -199,6 +199,7 @@ #include #include +#include #include #include #include @@ -1026,7 +1027,7 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv) * still pending. */ - i2cinfo("Timeout with CR: %04x SR: %04x\n", cr, sr); + i2cinfo("Timeout with CR: %04" PRIx32 " SR: %04" PRIx32 "\n", cr, sr); } /************************************************************************************ @@ -1532,7 +1533,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); - i2cinfo("ENTER: status = 0x%08x\n", status); + i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); /* Update private version of the state assuming a good state */ @@ -1580,15 +1581,17 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) { /* NACK received on first (address) byte: address is invalid */ - i2cinfo("NACK: Address invalid: dcnt=%i msgc=%i status=0x%08x\n", - priv->dcnt, priv->msgc, status); + i2cinfo("NACK: Address invalid: dcnt=%i msgc=%i " + "status=0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } else { /* NACK received on regular byte */ - i2cinfo("NACK: NACK received: dcnt=%i msgc=%i status=0x%08x\n", + i2cinfo("NACK: NACK received: dcnt=%i msgc=%i " + "status=0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } @@ -1642,7 +1645,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) /* TXIS interrupt occurred, address valid, ready to transmit */ stm32_i2c_traceevent(priv, I2CEVENT_WRITE, 0); - i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08x\n", + i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); /* The first event after the address byte is sent will be either TXIS @@ -1699,8 +1702,9 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) { /* Unsupported state */ - i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, status 0x%08x\n", - priv->dcnt, status); + i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, " + "status 0x%08" PRIx32 "\n", + priv->dcnt, status); stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); /* Indicate the bad state, so that on termination HW will be reset */ @@ -1708,7 +1712,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) priv->status |= I2C_INT_BAD_STATE; } - i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08x\n", + i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); } @@ -1749,7 +1753,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) */ stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); - i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08x\n", + i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); /* If more bytes in the current message */ @@ -1789,7 +1793,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); - i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, status 0x%08x\n", + i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, " + "status 0x%08" PRIx32 "\n", priv->dcnt, status); /* Set signals that will terminate ISR and wake waiting thread */ @@ -1799,7 +1804,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) priv->msgc = 0; } - i2cinfo("RXNE: EXIT dcnt = %i msgc = %i status 0x%08x\n", + i2cinfo("RXNE: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); } @@ -1834,7 +1839,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) else if ((status & I2C_ISR_TC) != 0) { - i2cinfo("TC: ENTER dcnt = %i msgc = %i status 0x%08x\n", + i2cinfo("TC: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); /* Prior message has been sent successfully. Or there could have @@ -1891,7 +1896,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) priv->msgc = 0; } - i2cinfo("TC: EXIT dcnt = %i msgc = %i status 0x%08x\n", + i2cinfo("TC: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); } @@ -1932,8 +1937,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) else if ((status & I2C_ISR_TCR) != 0) { - i2cinfo("TCR: ENTER dcnt = %i msgc = %i status 0x%08x\n", - priv->dcnt, priv->msgc, status); + i2cinfo("TCR: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); /* If no more bytes in the current message to transfer */ @@ -2018,8 +2023,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } - i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08x\n", - priv->dcnt, priv->msgc, status); + i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); } } @@ -2032,7 +2037,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) else if (priv->dcnt == -1 && priv->msgc == 0) { status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); - i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08x\n", status); + i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", + status); stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); } @@ -2055,7 +2061,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); - i2cerr("ERROR: Invalid state detected, status 0x%08x\n", status); + i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", + status); /* set condition to terminate ISR and wake waiting thread */ @@ -2129,7 +2136,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) } status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); - i2cinfo("EXIT: status = 0x%08x\n", status); + i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); return OK; } @@ -2344,19 +2351,23 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, /* Connection timed out */ errval = ETIMEDOUT; - i2cerr("ERROR: Waitdone timed out CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n", + i2cerr("ERROR: Waitdone timed out CR1: 0x%08" PRIx32 + " CR2: 0x%08" PRIx32 + " status: 0x%08" PRIx32 "\n", cr1, cr2, status); } else { - i2cinfo("Waitdone success: CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n", - cr1, cr2, status); + i2cinfo("Waitdone success: CR1: 0x%08" PRIx32 + " CR2: 0x%08" PRIx32 + " status: 0x%08" PRIx32 "\n", + cr1, cr2, status); } UNUSED(cr1); UNUSED(cr2); - i2cinfo("priv->status: 0x%08x\n", priv->status); + i2cinfo("priv->status: 0x%08" PRIx32 "\n", priv->status); /* Check for error status conditions */ diff --git a/arch/arm/src/stm32h7/stm32_otg.h b/arch/arm/src/stm32h7/stm32_otg.h index 28312364542..d76553924e5 100644 --- a/arch/arm/src/stm32h7/stm32_otg.h +++ b/arch/arm/src/stm32h7/stm32_otg.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32h7/stm32_otg.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. @@ -31,14 +31,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32H7_STM32_OTG_H #define __ARCH_ARM_SRC_STM32H7_STM32_OTG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -49,15 +49,16 @@ #if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_OTGHS) -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ #if defined(CONFIG_STM32H7_OTGFS) # define STM32_IRQ_OTG STM32_IRQ_OTGFS # define STM32_OTG_BASE STM32_OTGFS_BASE /* OTG FS */ -# define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */ +# define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */ # define GPIO_OTG_DM GPIO_OTGFS_DM # define GPIO_OTG_DP GPIO_OTGFS_DP # define GPIO_OTG_ID GPIO_OTGFS_ID @@ -68,7 +69,7 @@ #if defined(CONFIG_STM32H7_OTGHS) # define STM32_IRQ_OTG STM32_IRQ_OTGHS # define STM32_OTG_BASE STM32_OTGHS_BASE /* OTG HS/FS */ -# define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */ +# define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */ # define GPIO_OTG_DM GPIO_OTGHS_DM # define GPIO_OTG_DP GPIO_OTGHS_DP # define GPIO_OTG_ID GPIO_OTGHS_ID @@ -76,9 +77,9 @@ # define STM32_OTG_FIFO_SIZE 4096 #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -99,8 +100,8 @@ extern "C" * * Input Parameters: * controller -- If the device supports more than USB host controller, then - * this identifies which controller is being initializeed. Normally, this - * is just zero. + * this identifies which controller is being initialized. Normally, + * this is just zero. * * Returned Value: * And instance of the USB host interface. The controlling task should @@ -121,17 +122,18 @@ struct usbhost_connection_s; FAR struct usbhost_connection_s *stm32_otgfshost_initialize(int controller); #endif -/************************************************************************************ +/**************************************************************************** * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32_usbsuspend logic if the OTG FS device driver - * is used. This function is called whenever the USB enters or leaves suspend - * mode. This is an opportunity for the board logic to shutdown clocks, power, - * etc. while the USB is suspended. + * Board logic must provide the stm32_usbsuspend logic if the OTG FS + * device driver is used. This function is called whenever the USB enters + * or leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. * - ************************************************************************************/ + ****************************************************************************/ +struct usbdev_s; void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume); #undef EXTERN diff --git a/arch/arm/src/stm32h7/stm32_otghost.c b/arch/arm/src/stm32h7/stm32_otghost.c index e34132010ae..d00db4f710d 100644 --- a/arch/arm/src/stm32h7/stm32_otghost.c +++ b/arch/arm/src/stm32h7/stm32_otghost.c @@ -42,6 +42,7 @@ #include #include +#include #include #include #include @@ -73,9 +74,7 @@ #include "stm32_otg.h" #include "stm32_usbhost.h" -#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_EXPERIMENTAL) - -#warning OTG host not tested for STM32H7! +#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32H7_OTGFS) /**************************************************************************** * Pre-processor Definitions @@ -1231,7 +1230,7 @@ static void stm32_chan_wakeup(FAR struct stm32_usbhost_s *priv, ****************************************************************************/ static int stm32_ctrlchan_alloc(FAR struct stm32_usbhost_s *priv, - uint8_t epno, uint8_t funcaddr + uint8_t epno, uint8_t funcaddr, uint8_t speed, FAR struct stm32_ctrlinfo_s *ctrlep) { @@ -2527,7 +2526,8 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv, /* AND the two to get the set of enabled, pending HC interrupts */ pending &= regval; - uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending); + uinfo("HCINTMSK%d: %08" PRIx32 " pending: %08" PRIx32 "\n", + chidx, regval, pending); /* Check for a pending ACK response received/transmitted interrupt */ @@ -2780,7 +2780,8 @@ static inline void stm32_gint_hcoutisr(FAR struct stm32_usbhost_s *priv, /* AND the two to get the set of enabled, pending HC interrupts */ pending &= regval; - uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending); + uinfo("HCINTMSK%d: %08" PRIx32 " pending: %08" PRIx32 "\n", + chidx, regval, pending); /* Check for a pending ACK response received/transmitted interrupt */ @@ -3100,7 +3101,7 @@ static inline void stm32_gint_rxflvlisr(FAR struct stm32_usbhost_s *priv) /* Read and pop the next status from the Rx FIFO */ grxsts = stm32_getreg(STM32_OTG_GRXSTSP); - uinfo("GRXSTS: %08x\n", grxsts); + uinfo("GRXSTS: %08" PRIx32 "\n", grxsts); /* Isolate the channel number/index in the status word */ @@ -3254,7 +3255,7 @@ static inline void stm32_gint_nptxfeisr(FAR struct stm32_usbhost_s *priv) /* Write the next group of packets into the Tx FIFO */ - uinfo("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d " + uinfo("HNPTXSTS: %08" PRIx32 " chidx: %d avail: %d buflen: %d xfrd: %d " "wrsize: %d\n", regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); @@ -3344,8 +3345,9 @@ static inline void stm32_gint_ptxfeisr(FAR struct stm32_usbhost_s *priv) /* Write the next group of packets into the Tx FIFO */ - uinfo("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n", - regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); + uinfo("HPTXSTS: %08" PRIx32 + " chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n", + regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); } @@ -4237,6 +4239,7 @@ static int stm32_epalloc(FAR struct usbhost_driver_s *drvr, static int stm32_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) { FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr; + int ret; DEBUGASSERT(priv); @@ -4835,7 +4838,7 @@ static int stm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) unsigned int chidx = (unsigned int)ep; irqstate_t flags; - uinfo("chidx: %u: %d\n", chidx); + uinfo("chidx: %u\n", chidx); DEBUGASSERT(priv && chidx < STM32_MAX_TX_FIFOS); chan = &priv->chan[chidx]; @@ -5481,7 +5484,7 @@ FAR struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) /* Enable VDD33USB supply level detector */ regval |= STM32_PWR_CR3_USB33DEN; - stm32_putreg(regval, STM32_PWR_CR3); + stm32_putreg(STM32_PWR_CR3, regval); while ((stm32_getreg(STM32_PWR_CR3) & STM32_PWR_CR3_USB33RDY) == 0) { diff --git a/arch/arm/src/stm32h7/stm32_pwm.c b/arch/arm/src/stm32h7/stm32_pwm.c index 63f31fe9797..6a2b9322b47 100644 --- a/arch/arm/src/stm32h7/stm32_pwm.c +++ b/arch/arm/src/stm32h7/stm32_pwm.c @@ -42,6 +42,7 @@ #include +#include #include #include #include @@ -2009,7 +2010,7 @@ static int pwm_duty_update(FAR struct pwm_lowerhalf_s *dev, uint8_t channel, DEBUGASSERT(priv != NULL); - pwminfo("TIM%u channel: %u duty: %08x\n", + pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n", priv->timid, channel, duty); #ifndef CONFIG_PWM_MULTICHAN @@ -2028,7 +2029,7 @@ static int pwm_duty_update(FAR struct pwm_lowerhalf_s *dev, uint8_t channel, ccr = b16toi(duty * reload + b16HALF); - pwminfo("ccr: %u\n", ccr); + pwminfo("ccr: %" PRIu32 "\n", ccr); /* Write corresponding CCR register */ @@ -2136,8 +2137,9 @@ static int pwm_frequency_update(FAR struct pwm_lowerhalf_s *dev, reload--; } - pwminfo("TIM%u PCLK: %u frequency: %u TIMCLK: %u " - "prescaler: %u reload: %u\n", + pwminfo("TIM%u PCLK: %" PRIu32 " frequency: %" PRIu32 + " TIMCLK: %" PRIu32 + " prescaler: %" PRIu32 " reload: %" PRIu32 "\n", priv->timid, priv->pclk, frequency, timclk, prescaler, reload); /* Set the reload and prescaler values */ @@ -3388,10 +3390,10 @@ static int pwm_timer(FAR struct pwm_lowerhalf_s *dev, DEBUGASSERT(priv != NULL && info != NULL); #if defined(CONFIG_PWM_MULTICHAN) - pwminfo("TIM%u frequency: %u\n", + pwminfo("TIM%u frequency: %" PRIu32 "\n", priv->timid, info->frequency); #else - pwminfo("TIM%u channel: %u frequency: %u duty: %08x\n", + pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 "\n", priv->timid, priv->channels[0].channel, info->frequency, info->duty); #endif @@ -3771,7 +3773,8 @@ static int pwm_set_apb_clock(FAR struct stm32_pwmtimer_s *priv, bool on) /* Enable/disable APB 1/2 clock for timer */ - pwminfo("RCC_APBxENR base: %08x bits: %04x\n", regaddr, en_bit); + pwminfo("RCC_APBxENR base: %08" PRIx32 " bits: %04" PRIx32 "\n", + regaddr, en_bit); if (on) { @@ -3839,7 +3842,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) pincfg = priv->channels[i].out1.pincfg; if (pincfg != 0) { - pwminfo("pincfg: %08x\n", pincfg); + pwminfo("pincfg: %08" PRIx32 "\n", pincfg); stm32_configgpio(pincfg); pwm_dumpgpio(pincfg, "PWM setup"); @@ -3858,7 +3861,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) if (pincfg != 0) { - pwminfo("pincfg: %08x\n", pincfg); + pwminfo("pincfg: %08" PRIx32 "\n", pincfg); stm32_configgpio(pincfg); pwm_dumpgpio(pincfg, "PWM setup"); @@ -3933,7 +3936,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) pincfg = priv->channels[i].out1.pincfg; if (pincfg != 0) { - pwminfo("pincfg: %08x\n", pincfg); + pwminfo("pincfg: %08" PRIx32 "\n", pincfg); pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); pincfg |= PINCFG_DEFAULT; @@ -3945,7 +3948,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) pincfg = priv->channels[i].out2.pincfg; if (pincfg != 0) { - pwminfo("pincfg: %08x\n", pincfg); + pwminfo("pincfg: %08" PRIx32 "\n", pincfg); pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); pincfg |= PINCFG_DEFAULT; @@ -4227,7 +4230,8 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) putreg32(regval, regaddr); leave_critical_section(flags); - pwminfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit); + pwminfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", + regaddr, resetbit); pwm_dumpregs(dev, "After stop"); errout: diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.c b/arch/arm/src/stm32h7/stm32_sdmmc.c index 9b7462791c8..f60a5d79121 100644 --- a/arch/arm/src/stm32h7/stm32_sdmmc.c +++ b/arch/arm/src/stm32h7/stm32_sdmmc.c @@ -493,7 +493,7 @@ static void stm32_blocksetup(FAR struct sdio_dev_s *dev, static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, size_t nbytes); static int stm32_sendsetup(FAR struct sdio_dev_s *dev, - FAR const uint8_t *buffer, uint32_t nbytes); + FAR const uint8_t *buffer, size_t nbytes); #endif static int stm32_cancel(FAR struct sdio_dev_s *dev); diff --git a/arch/arm/src/stm32l4/stm32l4_can.c b/arch/arm/src/stm32l4/stm32l4_can.c index e56b4997f5c..5d1890b4d7b 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.c +++ b/arch/arm/src/stm32l4/stm32l4_can.c @@ -1092,7 +1092,7 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd, return ret; } - regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); if (arg == 1) { regval |= CAN_MCR_NART; @@ -1102,7 +1102,7 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd, regval &= ~CAN_MCR_NART; } - stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); return stm32l4can_exitinitmode(priv); } break; @@ -1116,7 +1116,7 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd, return ret; } - regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); if (arg == 1) { regval |= CAN_MCR_ABOM; @@ -1126,7 +1126,7 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd, regval &= ~CAN_MCR_ABOM; } - stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); return stm32l4can_exitinitmode(priv); } break; diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.c b/arch/arm/src/stm32l4/stm32l4_sdmmc.c index f65d9da7ece..0b2a4586106 100644 --- a/arch/arm/src/stm32l4/stm32l4_sdmmc.c +++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.c @@ -484,7 +484,7 @@ static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, size_t nbytes); static int stm32_sendsetup(FAR struct sdio_dev_s *dev, - FAR const uint8_t *buffer, uint32_t nbytes); + FAR const uint8_t *buffer, size_t nbytes); static int stm32_cancel(FAR struct sdio_dev_s *dev); static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd); diff --git a/arch/arm/src/str71x/str71x_serial.c b/arch/arm/src/str71x/str71x_serial.c index fa6c1a19aff..2639471e2b2 100644 --- a/arch/arm/src/str71x/str71x_serial.c +++ b/arch/arm/src/str71x/str71x_serial.c @@ -1,7 +1,8 @@ /**************************************************************************** * arch/arm/src/str71x/str71x_serial.c * - * Copyright (C) 2008-2009, 2012-2013, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2008-2009, 2012-2013, 2017 Gregory Nutt. + * All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -202,9 +203,9 @@ # define RXENABLE_BITS STR71X_UARTIER_RNE #endif -/* Which ever model is used, there seems to be some timing disconnects between - * Rx FIFO not full and Rx FIFO half full indications. Best bet is to use - * both. +/* Which ever model is used, there seems to be some timing disconnects + * between Rx FIFO not full and Rx FIFO half full indications. Best bet + * is to use both. */ #define RXAVAILABLE_BITS (STR71X_UARTSR_RNE|STR71X_UARTSR_RHF) @@ -232,7 +233,8 @@ struct up_dev_s /* Internal Helpers */ static inline uint16_t up_serialin(struct up_dev_s *priv, int offset); -static inline void up_serialout(struct up_dev_s *priv, int offset, uint16_t value); +static inline void up_serialout(struct up_dev_s *priv, int offset, + uint16_t value); static inline void up_disableuartint(struct up_dev_s *priv, uint16_t *ier); static inline void up_restoreuartint(struct up_dev_s *priv, uint16_t ier); #ifdef HAVE_CONSOLE @@ -247,7 +249,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -351,7 +353,7 @@ static uart_dev_t g_uart1port = { .size = CONFIG_UART1_TXBUFSIZE, .buffer = g_uart1txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_uart1priv, }; @@ -434,7 +436,8 @@ static inline uint16_t up_serialin(struct up_dev_s *priv, int offset) * Name: up_serialout ****************************************************************************/ -static inline void up_serialout(struct up_dev_s *priv, int offset, uint16_t value) +static inline void up_serialout(struct up_dev_s *priv, int offset, + uint16_t value) { putreg16(value, priv->uartbase + offset); } @@ -482,6 +485,7 @@ static inline void up_waittxnotfull(struct up_dev_s *priv) if ((up_serialin(priv, STR71X_UART_SR_OFFSET) & STR71X_UARTSR_TF) == 0) { /* The TX FIFO is not full... return */ + break; } } @@ -509,7 +513,7 @@ static int up_setup(struct uart_dev_s *dev) /* Set the BAUD rate */ divisor = 16 * priv->baud; - baud = (STR71X_PCLK1 + divisor/2) / divisor; + baud = (STR71X_PCLK1 + divisor / 2) / divisor; up_serialout(priv, STR71X_UART_BR_OFFSET, baud); /* Get mode setting */ @@ -591,14 +595,15 @@ static void up_shutdown(struct uart_dev_s *dev) * Name: up_attach * * Description: - * Configure the UART to operation in interrupt driven mode. This method is - * called when the serial port is opened. Normally, this is just after the + * Configure the UART to operation in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after * the setup() method is called, however, the serial console may operate in * a non-interrupt driven mode during the boot phase. * - * RX and TX interrupts are not enabled when by the attach method (unless the - * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() methods are called. + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. * ****************************************************************************/ @@ -627,8 +632,8 @@ static int up_attach(struct uart_dev_s *dev) * * Description: * Detach UART interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. The exception is - * the serial console which is never shutdown. + * closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. * ****************************************************************************/ @@ -753,7 +758,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint16_t rxbufr; @@ -788,6 +793,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) { priv->ier &= ~RXENABLE_BITS; } + up_serialout(priv, STR71X_UART_IER_OFFSET, priv->ier); } @@ -802,7 +808,8 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) static bool up_rxavailable(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - return ((up_serialin(priv, STR71X_UART_SR_OFFSET) & RXAVAILABLE_BITS) != 0); + return ((up_serialin(priv, STR71X_UART_SR_OFFSET) & + RXAVAILABLE_BITS) != 0); } /**************************************************************************** @@ -844,6 +851,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) priv->ier &= ~STR71X_UARTSR_THE; } + up_serialout(priv, STR71X_UART_IER_OFFSET, priv->ier); } @@ -858,7 +866,8 @@ static void up_txint(struct uart_dev_s *dev, bool enable) static bool up_txready(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - return ((up_serialin(priv, STR71X_UART_SR_OFFSET) & STR71X_UARTSR_TF) == 0); + return ((up_serialin(priv, STR71X_UART_SR_OFFSET) & + STR71X_UARTSR_TF) == 0); } /**************************************************************************** @@ -872,7 +881,8 @@ static bool up_txready(struct uart_dev_s *dev) static bool up_txempty(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - return ((up_serialin(priv, STR71X_UART_SR_OFFSET) & STR71X_UARTSR_TE) != 0); + return ((up_serialin(priv, STR71X_UART_SR_OFFSET) & + STR71X_UARTSR_TE) != 0); } /**************************************************************************** diff --git a/arch/arm/src/tiva/common/tiva_serial.c b/arch/arm/src/tiva/common/tiva_serial.c index a6566611a19..77ce40f5c92 100644 --- a/arch/arm/src/tiva/common/tiva_serial.c +++ b/arch/arm/src/tiva/common/tiva_serial.c @@ -324,7 +324,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -1168,7 +1168,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint32_t rxd; diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c index 85d59ce369a..7aa3b4cd93f 100644 --- a/arch/arm/src/xmc4/xmc4_serial.c +++ b/arch/arm/src/xmc4/xmc4_serial.c @@ -263,7 +263,7 @@ static int xmc4_attach(struct uart_dev_s *dev); static void xmc4_detach(struct uart_dev_s *dev); static int xmc4_interrupt(int irq, void *context, FAR void *arg); static int xmc4_ioctl(struct file *filep, int cmd, unsigned long arg); -static int xmc4_receive(struct uart_dev_s *dev, uint32_t *status); +static int xmc4_receive(struct uart_dev_s *dev, unsigned int *status); static void xmc4_rxint(struct uart_dev_s *dev, bool enable); static bool xmc4_rxavailable(struct uart_dev_s *dev); static void xmc4_send(struct uart_dev_s *dev, int ch); @@ -851,7 +851,7 @@ static int xmc4_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int xmc4_receive(struct uart_dev_s *dev, uint32_t *status) +static int xmc4_receive(struct uart_dev_s *dev, unsigned int *status) { struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; uint32_t outr; diff --git a/arch/avr/include/avr/types.h b/arch/avr/include/avr/types.h index ef11383a5de..788f9c4371c 100644 --- a/arch/avr/include/avr/types.h +++ b/arch/avr/include/avr/types.h @@ -79,6 +79,9 @@ typedef double double_t; #define __INT64_DEFINED +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; + /* A (near) size is 2 bytes */ #if defined(__SIZE_TYPE__) diff --git a/arch/avr/include/avr32/types.h b/arch/avr/include/avr32/types.h index 81a6a669144..2412d58c189 100644 --- a/arch/avr/include/avr32/types.h +++ b/arch/avr/include/avr32/types.h @@ -76,6 +76,9 @@ typedef signed long long _int64_t; typedef unsigned long long _uint64_t; #define __INT64_DEFINED +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; + /* A size is 4 bytes */ #if defined(__SIZE_TYPE__) diff --git a/arch/avr/src/Makefile b/arch/avr/src/Makefile index 29bbd9fa660..e91f0da2ce9 100644 --- a/arch/avr/src/Makefile +++ b/arch/avr/src/Makefile @@ -140,12 +140,15 @@ export_startup: board/libboard$(LIBEXT) $(STARTUP_OBJS) # Dependencies +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) + .depend: Makefile chip/Make.defs $(SRCS) $(TOPDIR)$(DELIM).config ifeq ($(BOARDMAKE),y) $(Q) $(MAKE) -C board depend endif - $(Q) $(MKDEP) --dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR) \ - "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile DEPPATH="--dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR)" $(Q) touch $@ depend: .depend diff --git a/arch/avr/src/at32uc3/at32uc3_serial.c b/arch/avr/src/at32uc3/at32uc3_serial.c index dd3917318bd..91249b84e43 100644 --- a/arch/avr/src/at32uc3/at32uc3_serial.c +++ b/arch/avr/src/at32uc3/at32uc3_serial.c @@ -161,7 +161,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -539,7 +539,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint32_t rhr; diff --git a/arch/hc/include/hc12/types.h b/arch/hc/include/hc12/types.h index 19804853bfb..df179a84117 100644 --- a/arch/hc/include/hc12/types.h +++ b/arch/hc/include/hc12/types.h @@ -85,6 +85,9 @@ typedef signed long long _int64_t; typedef unsigned long long _uint64_t; #define __INT64_DEFINED +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; + /* A size is two bytes */ #if defined(__SIZE_TYPE__) @@ -102,7 +105,7 @@ typedef signed short _ssize_t; typedef unsigned short _size_t; #endif -/* This is the size of the interrupt state save returned by up_irq_save()*/ +/* This is the size of the interrupt state save returned by up_irq_save() */ typedef unsigned int irqstate_t; diff --git a/arch/hc/include/hcs12/types.h b/arch/hc/include/hcs12/types.h index 1f21c2b82de..5521b6f5ff9 100644 --- a/arch/hc/include/hcs12/types.h +++ b/arch/hc/include/hcs12/types.h @@ -86,6 +86,9 @@ typedef signed long long _int64_t; typedef unsigned long long _uint64_t; #define __INT64_DEFINED +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; + /* A size is two bytes */ #if defined(__SIZE_TYPE__) @@ -103,7 +106,7 @@ typedef signed short _ssize_t; typedef unsigned short _size_t; #endif -/* This is the size of the interrupt state save returned by up_irq_save()*/ +/* This is the size of the interrupt state save returned by up_irq_save() */ typedef unsigned char irqstate_t; diff --git a/arch/hc/src/Makefile b/arch/hc/src/Makefile index b521aa57667..e0d5331c9d9 100644 --- a/arch/hc/src/Makefile +++ b/arch/hc/src/Makefile @@ -155,12 +155,15 @@ export_startup: board/libboard$(LIBEXT) $(STARTUP_OBJS) # Dependencies +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) + .depend: Makefile chip/Make.defs $(SRCS) $(TOPDIR)$(DELIM).config ifeq ($(BOARDMAKE),y) $(Q) $(MAKE) -C board depend endif - $(Q) $(MKDEP) --dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR) \ - "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile DEPPATH="--dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR)" $(Q) touch $@ depend: .depend diff --git a/arch/hc/src/m9s12/m9s12_serial.c b/arch/hc/src/m9s12/m9s12_serial.c index 4f7bcad5f4a..374f2e0f0a3 100644 --- a/arch/hc/src/m9s12/m9s12_serial.c +++ b/arch/hc/src/m9s12/m9s12_serial.c @@ -1,7 +1,8 @@ /**************************************************************************** * arch/hc/src/m9s12/m9s12_serial.c * - * Copyright (C) 2009, 2011-2012, 2016-2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2011-2012, 2016-2017 Gregory Nutt. + * All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -125,7 +126,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -242,7 +243,8 @@ static inline uint8_t up_serialin(struct up_dev_s *priv, int offset) * Name: up_serialout ****************************************************************************/ -static inline void up_serialout(struct up_dev_s *priv, int offset, uint8_t value) +static inline void up_serialout(struct up_dev_s *priv, int offset, + uint8_t value) { putreg8(value, priv->uartbase + offset); } @@ -332,7 +334,7 @@ static inline void up_waittxnotfull(struct up_dev_s *priv) static int up_setup(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #ifndef CONFIG_SUPPRESS_SCI_CONFIG uint8_t cr1; #endif @@ -367,7 +369,7 @@ static int up_setup(struct uart_dev_s *dev) default: break; case 1: - cr1 |= SCI_CR1_PE|SCI_CR1_PT; + cr1 |= SCI_CR1_PE | SCI_CR1_PT; break; case 2: cr1 |= SCI_CR1_PE; @@ -382,7 +384,7 @@ static int up_setup(struct uart_dev_s *dev) */ priv->im = 0; - up_serialout(priv, HCS12_SCI_CR2_OFFSET, (SCI_CR2_TE|SCI_CR2_RE)); + up_serialout(priv, HCS12_SCI_CR2_OFFSET, (SCI_CR2_TE | SCI_CR2_RE)); return OK; } @@ -396,7 +398,7 @@ static int up_setup(struct uart_dev_s *dev) static void up_shutdown(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; up_disablesciint(priv, NULL); } @@ -409,15 +411,16 @@ static void up_shutdown(struct uart_dev_s *dev) * the setup() method is called, however, the serial console may operate in * a non-interrupt driven mode during the boot phase. * - * RX and TX interrupts are not enabled when by the attach method (unless the - * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() methods are called. + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. * ****************************************************************************/ static int up_attach(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -425,13 +428,14 @@ static int up_attach(struct uart_dev_s *dev) ret = irq_attach(priv->irq, up_interrupt, dev); if (ret == OK) { - /* Enable the Rx interrupt (the TX interrupt is still disabled - * until we have something to send). - */ + /* Enable the Rx interrupt (the TX interrupt is still disabled + * until we have something to send). + */ - priv->im = SCI_CR2_RIE; - up_setsciint(priv); + priv->im = SCI_CR2_RIE; + up_setsciint(priv); } + return ret; } @@ -447,7 +451,7 @@ static int up_attach(struct uart_dev_s *dev) static void up_detach(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; up_disablesciint(priv, NULL); irq_detach(priv->irq); } @@ -473,7 +477,7 @@ static int up_interrupt(int irq, void *context, void *arg) bool handled; DEBUGASSERT(dev != NULL && dev->priv != NULL); - priv = (struct up_dev_s*)dev->priv; + priv = (struct up_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, * until we have been looping for a long time. @@ -492,23 +496,24 @@ static int up_interrupt(int irq, void *context, void *arg) if ((mis & SCI_SR1_RDRF) != 0) { - /* Rx buffer not empty ... process incoming bytes */ + /* Rx buffer not empty ... process incoming bytes */ - uart_recvchars(dev); - handled = true; + uart_recvchars(dev); + handled = true; } /* Handle outgoing, transmit bytes */ if ((mis & SCI_SR1_TDRE) != 0) { - /* Tx FIFO not full ... process outgoing bytes */ + /* Tx FIFO not full ... process outgoing bytes */ - uart_xmitchars(dev); - handled = true; + uart_xmitchars(dev); + handled = true; } } - return OK; + + return OK; } /**************************************************************************** @@ -547,9 +552,9 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; int rxd; /* Return the error indications */ @@ -580,7 +585,7 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status) static void up_rxint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; if (enable) { @@ -610,7 +615,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) static bool up_rxavailable(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return ((up_serialin(priv, HCS12_SCI_SR1_OFFSET) & SCI_SR1_RDRF) != 0); } @@ -624,7 +629,7 @@ static bool up_rxavailable(struct uart_dev_s *dev) static void up_send(struct uart_dev_s *dev, int ch) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint8_t regval; if (priv->bits == 9) @@ -638,6 +643,7 @@ static void up_send(struct uart_dev_s *dev, int ch) { regval |= SCI_DRH_T8; } + up_serialout(priv, HCS12_SCI_DRH_OFFSET, regval); } @@ -654,7 +660,7 @@ static void up_send(struct uart_dev_s *dev, int ch) static void up_txint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; flags = enter_critical_section(); @@ -692,7 +698,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) static bool up_txready(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return ((up_serialin(priv, HCS12_SCI_SR1_OFFSET) & SCI_SR1_TDRE) != 0); } @@ -706,7 +712,7 @@ static bool up_txready(struct uart_dev_s *dev) static bool up_txempty(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return ((up_serialin(priv, HCS12_SCI_SR1_OFFSET) & SCI_SR1_TC) != 0); } @@ -779,7 +785,7 @@ void up_serialinit(void) int up_putc(int ch) { #ifdef HAVE_CONSOLE - struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv; + struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv; uint32_t im; up_disablesciint(priv, &im); diff --git a/arch/mips/include/inttypes.h b/arch/mips/include/inttypes.h index d7bacdbed59..97f3075da72 100644 --- a/arch/mips/include/inttypes.h +++ b/arch/mips/include/inttypes.h @@ -46,89 +46,89 @@ #define PRId8 "d" #define PRId16 "d" -#define PRId32 "d" +#define PRId32 "ld" #define PRId64 "lld" #define PRIdPTR "d" #define PRIi8 "i" #define PRIi16 "i" -#define PRIi32 "i" +#define PRIi32 "li" #define PRIi64 "lli" #define PRIiPTR "i" #define PRIo8 "o" #define PRIo16 "o" -#define PRIo32 "o" +#define PRIo32 "lo" #define PRIo64 "llo" #define PRIoPTR "o" #define PRIu8 "u" #define PRIu16 "u" -#define PRIu32 "u" +#define PRIu32 "lu" #define PRIu64 "llu" #define PRIuPTR "u" #define PRIx8 "x" #define PRIx16 "x" -#define PRIx32 "x" +#define PRIx32 "lx" #define PRIx64 "llx" #define PRIxPTR "x" #define PRIX8 "X" #define PRIX16 "X" -#define PRIX32 "X" +#define PRIX32 "lX" #define PRIX64 "llX" #define PRIXPTR "X" #define SCNd8 "hhd" #define SCNd16 "hd" -#define SCNd32 "d" +#define SCNd32 "ld" #define SCNd64 "lld" #define SCNdPTR "d" #define SCNi8 "hhi" #define SCNi16 "hi" -#define SCNi32 "i" +#define SCNi32 "li" #define SCNi64 "lli" #define SCNiPTR "i" #define SCNo8 "hho" #define SCNo16 "ho" -#define SCNo32 "o" +#define SCNo32 "lo" #define SCNo64 "llo" #define SCNoPTR "o" #define SCNu8 "hhu" #define SCNu16 "hu" -#define SCNu32 "u" +#define SCNu32 "lu" #define SCNu64 "llu" #define SCNuPTR "u" #define SCNx8 "hhx" #define SCNx16 "hx" -#define SCNx32 "x" +#define SCNx32 "lx" #define SCNx64 "llx" #define SCNxPTR "x" #define INT8_C(x) x #define INT16_C(x) x -#define INT32_C(x) x +#define INT32_C(x) x ## l #define INT64_C(x) x ## ll #define UINT8_C(x) x #define UINT16_C(x) x -#define UINT32_C(x) x ## u +#define UINT32_C(x) x ## ul #define UINT64_C(x) x ## ull #endif /* __ARCH_MIPS_INCLUDE_INTTYPES_H */ diff --git a/arch/mips/include/types.h b/arch/mips/include/types.h index f135a517d7a..935c66dae83 100644 --- a/arch/mips/include/types.h +++ b/arch/mips/include/types.h @@ -69,13 +69,16 @@ typedef unsigned char _uint8_t; typedef signed short _int16_t; typedef unsigned short _uint16_t; -typedef signed int _int32_t; -typedef unsigned int _uint32_t; +typedef signed long _int32_t; +typedef unsigned long _uint32_t; typedef signed long long _int64_t; typedef unsigned long long _uint64_t; #define __INT64_DEFINED +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; + /* A size is 4 bytes */ #if defined(__SIZE_TYPE__) diff --git a/arch/mips/src/Makefile b/arch/mips/src/Makefile index bc2c19db8c0..cdbd2a8fb6f 100644 --- a/arch/mips/src/Makefile +++ b/arch/mips/src/Makefile @@ -138,12 +138,15 @@ export_startup: board/libboard$(LIBEXT) $(STARTUP_OBJS) # Dependencies +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) + .depend: Makefile chip/Make.defs $(SRCS) $(TOPDIR)$(DELIM).config ifeq ($(BOARDMAKE),y) $(Q) $(MAKE) -C board depend endif - $(Q) $(MKDEP) --dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR) \ - "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile DEPPATH="--dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR)" $(Q) touch $@ depend: .depend diff --git a/arch/mips/src/pic32mx/pic32mx_serial.c b/arch/mips/src/pic32mx/pic32mx_serial.c index 6f753aca5bf..727cd77578f 100644 --- a/arch/mips/src/pic32mx/pic32mx_serial.c +++ b/arch/mips/src/pic32mx/pic32mx_serial.c @@ -176,7 +176,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -653,7 +653,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; diff --git a/arch/mips/src/pic32mz/pic32mz_serial.c b/arch/mips/src/pic32mz/pic32mz_serial.c index 6c0c1b9772a..bcbf1c3db76 100644 --- a/arch/mips/src/pic32mz/pic32mz_serial.c +++ b/arch/mips/src/pic32mz/pic32mz_serial.c @@ -278,7 +278,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, FAR void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -904,7 +904,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; diff --git a/arch/misoc/include/types.h b/arch/misoc/include/types.h index e448a8cd3cd..c04aec07791 100644 --- a/arch/misoc/include/types.h +++ b/arch/misoc/include/types.h @@ -76,6 +76,9 @@ typedef signed long long _int64_t; typedef unsigned long long _uint64_t; #define __INT64_DEFINED +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; + /* A size is 4 bytes */ #if defined(__SIZE_TYPE__) diff --git a/arch/misoc/src/Makefile b/arch/misoc/src/Makefile index 2fd406e8f55..d6e2eb5d763 100644 --- a/arch/misoc/src/Makefile +++ b/arch/misoc/src/Makefile @@ -141,12 +141,15 @@ export_startup: board/libboard$(LIBEXT) $(STARTUP_OBJS) # Dependencies +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) + .depend: Makefile chip/Make.defs $(SRCS) $(TOPDIR)$(DELIM).config ifeq ($(BOARDMAKE),y) $(Q) $(MAKE) -C board depend endif - $(Q) $(MKDEP) --dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR) \ - "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile DEPPATH="--dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR)" $(Q) touch $@ depend: .depend diff --git a/arch/or1k/include/types.h b/arch/or1k/include/types.h index 43de7d4400e..0e7c4a35c94 100644 --- a/arch/or1k/include/types.h +++ b/arch/or1k/include/types.h @@ -79,6 +79,9 @@ typedef unsigned long long _uint64_t; #define __INT64_DEFINED 1 +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; + /* A size is 4 bytes */ #if defined(__SIZE_TYPE__) diff --git a/arch/or1k/src/Makefile b/arch/or1k/src/Makefile index 7b1a552e9c1..93b6f2ee59e 100644 --- a/arch/or1k/src/Makefile +++ b/arch/or1k/src/Makefile @@ -181,12 +181,15 @@ endif # Dependencies +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) + .depend: Makefile chip$(DELIM)Make.defs $(SRCS) $(TOPDIR)$(DELIM).config ifeq ($(BOARDMAKE),y) $(Q) $(MAKE) -C board depend endif - $(Q) $(MKDEP) $(patsubst %,--dep-path %,$(subst :, ,$(VPATH))) \ - "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile DEPPATH="$(patsubst %,--dep-path %,$(subst :, ,$(VPATH)))" $(Q) touch $@ depend: .depend diff --git a/arch/renesas/include/m16c/types.h b/arch/renesas/include/m16c/types.h index 6842101aa87..5f61d27e5f4 100644 --- a/arch/renesas/include/m16c/types.h +++ b/arch/renesas/include/m16c/types.h @@ -78,6 +78,9 @@ typedef signed long long _int64_t; typedef unsigned long long _uint64_t; #define __INT64_DEFINED +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; + /* A size is 2 bytes */ #if defined(__SIZE_TYPE__) diff --git a/arch/renesas/include/rx65n/inttypes.h b/arch/renesas/include/rx65n/inttypes.h index 2c9e0d0303a..0dc7bba2f2f 100644 --- a/arch/renesas/include/rx65n/inttypes.h +++ b/arch/renesas/include/rx65n/inttypes.h @@ -41,89 +41,89 @@ #define PRId8 "d" #define PRId16 "d" -#define PRId32 "d" +#define PRId32 "ld" #define PRId64 "lld" #define PRIdPTR "d" #define PRIi8 "i" #define PRIi16 "i" -#define PRIi32 "i" +#define PRIi32 "li" #define PRIi64 "lli" #define PRIiPTR "i" #define PRIo8 "o" #define PRIo16 "o" -#define PRIo32 "o" +#define PRIo32 "lo" #define PRIo64 "llo" #define PRIoPTR "o" #define PRIu8 "u" #define PRIu16 "u" -#define PRIu32 "u" +#define PRIu32 "lu" #define PRIu64 "llu" #define PRIuPTR "u" #define PRIx8 "x" #define PRIx16 "x" -#define PRIx32 "x" +#define PRIx32 "lx" #define PRIx64 "llx" #define PRIxPTR "x" #define PRIX8 "X" #define PRIX16 "X" -#define PRIX32 "X" +#define PRIX32 "lX" #define PRIX64 "llX" #define PRIXPTR "X" #define SCNd8 "hhd" #define SCNd16 "hd" -#define SCNd32 "d" +#define SCNd32 "ld" #define SCNd64 "lld" #define SCNdPTR "d" #define SCNi8 "hhi" #define SCNi16 "hi" -#define SCNi32 "i" +#define SCNi32 "li" #define SCNi64 "lli" #define SCNiPTR "i" #define SCNo8 "hho" #define SCNo16 "ho" -#define SCNo32 "o" +#define SCNo32 "lo" #define SCNo64 "llo" #define SCNoPTR "o" #define SCNu8 "hhu" #define SCNu16 "hu" -#define SCNu32 "u" +#define SCNu32 "lu" #define SCNu64 "llu" #define SCNuPTR "u" #define SCNx8 "hhx" #define SCNx16 "hx" -#define SCNx32 "x" +#define SCNx32 "lx" #define SCNx64 "llx" #define SCNxPTR "x" #define INT8_C(x) x #define INT16_C(x) x -#define INT32_C(x) x +#define INT32_C(x) x ## l #define INT64_C(x) x ## ll #define UINT8_C(x) x #define UINT16_C(x) x -#define UINT32_C(x) x ## u +#define UINT32_C(x) x ## ul #define UINT64_C(x) x ## ull #endif /* __ARCH_RENESAS_INCLUDE_RX65N_INTTYPES_H */ diff --git a/arch/renesas/include/rx65n/types.h b/arch/renesas/include/rx65n/types.h index c300b540f0c..f01ba758718 100644 --- a/arch/renesas/include/rx65n/types.h +++ b/arch/renesas/include/rx65n/types.h @@ -54,13 +54,16 @@ typedef unsigned char _uint8_t; typedef signed short _int16_t; typedef unsigned short _uint16_t; -typedef signed int _int32_t; -typedef unsigned int _uint32_t; +typedef signed long _int32_t; +typedef unsigned long _uint32_t; typedef signed long long _int64_t; typedef unsigned long long _uint64_t; #define __INT64_DEFINED +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; + /* A size is 4 bytes */ #if defined(__SIZE_TYPE__) diff --git a/arch/renesas/include/sh1/types.h b/arch/renesas/include/sh1/types.h index 1851ead8f1e..fdf849528e7 100644 --- a/arch/renesas/include/sh1/types.h +++ b/arch/renesas/include/sh1/types.h @@ -76,6 +76,9 @@ typedef signed long long _int64_t; typedef unsigned long long _uint64_t; #define __INT64_DEFINED +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; + /* A size is 4 bytes */ #if defined(__SIZE_TYPE__) diff --git a/arch/renesas/include/sh1Ptypes.h b/arch/renesas/include/sh1Ptypes.h index aeb288a7484..9b130d1f21a 100644 --- a/arch/renesas/include/sh1Ptypes.h +++ b/arch/renesas/include/sh1Ptypes.h @@ -76,11 +76,6 @@ typedef signed long long _int64_t; typedef unsigned long long _uint64_t; #define __INT64_DEFINED -/* A pointer is 4 bytes */ - -typedef signed int _intptr_t; -typedef unsigned int _uintptr_t; - /* This is the size of the interrupt state save returned by * up_irq_save() */ diff --git a/arch/renesas/src/Makefile b/arch/renesas/src/Makefile index c5566a5efce..8c62b8de7d2 100644 --- a/arch/renesas/src/Makefile +++ b/arch/renesas/src/Makefile @@ -149,11 +149,15 @@ export_startup: board/libboard$(LIBEXT) $(STARTUP_OBJS) # Dependencies +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) + .depend: Makefile chip/Make.defs $(SRCS) $(TOPDIR)$(DELIM).config ifeq ($(BOARDMAKE),y) $(Q) $(MAKE) -C board depend endif - $(Q) $(MKDEP) --dep-path chip --dep-path common "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile DEPPATH="--dep-path chip --dep-path common" $(Q) touch $@ depend: .depend diff --git a/arch/renesas/src/rx65n/rx65n_serial.c b/arch/renesas/src/rx65n/rx65n_serial.c index 57d6b951ca5..82f10881d1f 100644 --- a/arch/renesas/src/rx65n/rx65n_serial.c +++ b/arch/renesas/src/rx65n/rx65n_serial.c @@ -284,7 +284,7 @@ static int up_xmtinterrupt(int irq, void *context, FAR void *arg); static int up_rcvinterrupt(int irq, void *context, FAR void *arg); static int up_eriinterrupt(int irq, void *context, FAR void *arg); static int up_teiinterrupt(int irq, void *context, FAR void *arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); diff --git a/arch/renesas/src/sh1/sh1_serial.c b/arch/renesas/src/sh1/sh1_serial.c index 4c38ab4b5c2..0a075400d1c 100644 --- a/arch/renesas/src/sh1/sh1_serial.c +++ b/arch/renesas/src/sh1/sh1_serial.c @@ -138,14 +138,14 @@ struct up_dev_s { - uint32_t scibase; /* Base address of SCI registers */ - uint32_t baud; /* Configured baud */ - volatile uint8_t scr; /* Saved SCR value */ - volatile uint8_t ssr; /* Saved SR value (only used during interrupt processing) */ - uint8_t irq; /* Base IRQ associated with this SCI */ - uint8_t parity; /* 0=none, 1=odd, 2=even */ - uint8_t bits; /* Number of bits (7 or 8) */ - bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ + uint32_t scibase; /* Base address of SCI registers */ + uint32_t baud; /* Configured baud */ + volatile uint8_t scr; /* Saved SCR value */ + volatile uint8_t ssr; /* Saved SR value (only used during interrupt processing) */ + uint8_t irq; /* Base IRQ associated with this SCI */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ }; /**************************************************************************** @@ -157,7 +157,7 @@ static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, FAR void *arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -251,7 +251,7 @@ static uart_dev_t g_sci1port = { .size = CONFIG_SCI1_TXBUFSIZE, .buffer = g_sci1txbuffer, - }, + }, .ops = &g_sci_ops, .priv = &g_sci1priv, }; @@ -274,7 +274,8 @@ static inline uint8_t up_serialin(struct up_dev_s *priv, int offset) * Name: up_serialout ****************************************************************************/ -static inline void up_serialout(struct up_dev_s *priv, int offset, uint8_t value) +static inline void up_serialout(struct up_dev_s *priv, int offset, + uint8_t value) { putreg8(value, priv->scibase + offset); } @@ -333,6 +334,7 @@ static inline void up_waittxready(struct up_dev_s *priv) if ((up_serialin(priv, SH1_SCI_SSR_OFFSET) & SH1_SCISSR_TDRE) != 0) { /* The TDR is empty... return */ + break; } } @@ -389,7 +391,7 @@ static inline void up_setbrr(struct up_dev_s *priv, unsigned int baud) static int up_setup(struct uart_dev_s *dev) { #ifndef CONFIG_SUPPRESS_SCI_CONFIG - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint8_t smr; /* Disable the transmitter and receiver */ @@ -410,7 +412,7 @@ static int up_setup(struct uart_dev_s *dev) if (priv->parity == 1) { - smr |= (SH1_SCISMR_PE|SH1_SCISMR_OE); + smr |= (SH1_SCISMR_PE | SH1_SCISMR_OE); } else if (priv->parity == 2) { @@ -457,7 +459,7 @@ static int up_setup(struct uart_dev_s *dev) static void up_shutdown(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; up_disablesciint(priv, NULL); } @@ -470,15 +472,16 @@ static void up_shutdown(struct uart_dev_s *dev) * the setup() method is called, however, the serial console may operate in * a non-interrupt driven mode during the boot phase. * - * RX and TX interrupts are not enabled when by the attach method (unless the - * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() methods are called. + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. * ****************************************************************************/ static int up_attach(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; int ret; /* Attach the RDR full IRQ (RXI) that is enabled by the RIE SCR bit */ @@ -486,14 +489,17 @@ static int up_attach(struct uart_dev_s *dev) ret = irq_attach(priv->irq + SH1_RXI_IRQ_OFFSET, up_interrupt, dev); if (ret == OK) { - /* The RIE interrupt enable also enables the receive error interrupt (ERI) */ + /* The RIE interrupt enable also enables the receive error interrupt + * (ERI) + */ ret = irq_attach(priv->irq + SH1_ERI_IRQ_OFFSET, up_interrupt, dev); if (ret == OK) { /* Attach the TDR empty IRQ (TXI) enabled by the TIE SCR bit */ - ret = irq_attach(priv->irq + SH1_TXI_IRQ_OFFSET, up_interrupt, dev); + ret = irq_attach(priv->irq + SH1_TXI_IRQ_OFFSET, up_interrupt, + dev); if (ret == OK) { #ifdef CONFIG_ARCH_IRQPRIO @@ -524,14 +530,14 @@ static int up_attach(struct uart_dev_s *dev) * * Description: * Detach SCI interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. The exception is - * the serial console which is never shutdown. + * closed normally just before the shutdown method is called. + * The exception is the serial console which is never shutdown. * ****************************************************************************/ static void up_detach(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Disable all SCI interrupts */ @@ -571,7 +577,7 @@ static int up_interrupt(int irq, void *context, FAR void *arg) struct up_dev_s *priv; DEBUGASSERT(dev != NULL && dev->priv != NULL); - priv = (struct up_dev_s*)dev->priv; + priv = (struct up_dev_s *)dev->priv; /* Get the current SCI status */ @@ -589,30 +595,34 @@ static int up_interrupt(int irq, void *context, FAR void *arg) if ((priv->ssr & SH1_SCISSR_RDRF) != 0) { - /* Rx data register not empty ... process incoming bytes */ + /* Rx data register not empty ... process incoming bytes */ - uart_recvchars(dev); + uart_recvchars(dev); } - /* Clear all read related events (probably already done in up_receive)) */ + /* Clear all read related events (probably already done in + * up_receive)) + */ - priv->ssr &= ~(SH1_SCISSR_RDRF|SH1_SCISSR_ORER|SH1_SCISSR_FER|SH1_SCISSR_PER); + priv->ssr &= ~(SH1_SCISSR_RDRF | SH1_SCISSR_ORER | SH1_SCISSR_FER | + SH1_SCISSR_PER); } /* Handle outgoing, transmit bytes (TDRE: Transmit Data Register Empty) - * when TIE is enabled. TIE is only enabled when the driver is waiting with - * buffered data. Since TDRE is usually true, + * when TIE is enabled. TIE is only enabled when the driver is waiting + * with buffered data. Since TDRE is usually true, */ - if ((priv->ssr & SH1_SCISSR_TDRE) != 0 && (priv->scr & SH1_SCISCR_TIE) != 0) + if ((priv->ssr & SH1_SCISSR_TDRE) != 0 && + (priv->scr & SH1_SCISCR_TIE) != 0) { - /* Tx data register empty ... process outgoing bytes */ + /* Tx data register empty ... process outgoing bytes */ - uart_xmitchars(dev); + uart_xmitchars(dev); - /* Clear the TDR empty flag (Possibly done in up_send, will have not - * effect if the TDR is still empty) - */ + /* Clear the TDR empty flag (Possibly done in up_send, will have not + * effect if the TDR is still empty) + */ priv->ssr &= ~SH1_SCISSR_TDRE; } @@ -639,7 +649,7 @@ static int up_interrupt(int irq, void *context, FAR void *arg) static int up_receive(struct uart_dev_s *dev, unsigned int *status) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint8_t rdr; uint8_t ssr; @@ -647,12 +657,13 @@ static int up_receive(struct uart_dev_s *dev, unsigned int *status) rdr = up_serialin(priv, SH1_SCI_RDR_OFFSET); - /* Clear all read related status in real ssr (so that when when rxavailable - * is called again, it will return false. + /* Clear all read related status in real ssr (so that when when + * rxavailable is called again, it will return false. */ ssr = up_serialin(priv, SH1_SCI_SSR_OFFSET); - ssr &= ~(SH1_SCISSR_RDRF|SH1_SCISSR_ORER|SH1_SCISSR_FER|SH1_SCISSR_PER); + ssr &= ~(SH1_SCISSR_RDRF | SH1_SCISSR_ORER | SH1_SCISSR_FER | + SH1_SCISSR_PER); up_serialout(priv, SH1_SCI_SSR_OFFSET, ssr); /* For status, return the SSR at the time that the interrupt was received */ @@ -674,7 +685,7 @@ static int up_receive(struct uart_dev_s *dev, unsigned int *status) static void up_rxint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; /* Disable interrupts to prevent asynchronous accesses */ @@ -716,7 +727,7 @@ static bool up_rxavailable(struct uart_dev_s *dev) { /* Return true if the RDR full bit is set in the SSR */ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return ((up_serialin(priv, SH1_SCI_SSR_OFFSET) & SH1_SCISSR_RDRF) != 0); } @@ -730,7 +741,7 @@ static bool up_rxavailable(struct uart_dev_s *dev) static void up_send(struct uart_dev_s *dev, int ch) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint8_t ssr; /* Write the data to the TDR */ @@ -754,7 +765,7 @@ static void up_send(struct uart_dev_s *dev, int ch) static void up_txint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; /* Disable interrupts to prevent asynchronous accesses */ @@ -809,7 +820,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) static bool up_txready(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return (up_serialin(priv, SH1_SCI_SSR_OFFSET) & SH1_SCISSR_TDRE) != 0; } @@ -888,7 +899,7 @@ void up_consoleinit(void) int up_putc(int ch) { #ifdef HAVE_CONSOLE - struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv; + struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv; uint8_t scr; up_disablesciint(priv, &scr); diff --git a/arch/risc-v/include/inttypes.h b/arch/risc-v/include/inttypes.h index d0940d1337d..61ae0baf41f 100644 --- a/arch/risc-v/include/inttypes.h +++ b/arch/risc-v/include/inttypes.h @@ -44,91 +44,111 @@ * Pre-processor Definitions ****************************************************************************/ +#if defined(__LP64__) +#define _PRI32PREFIX +#define _PRI64PREFIX "l" +#define _PRIPTRPREFIX "l" +#define _SCN32PREFIX +#define _SCN64PREFIX "l" +#define _SCNPTRPREFIX "l" +#define INT32_C(x) x +#define INT64_C(x) x ## l +#define UINT32_C(x) x ## u +#define UINT64_C(x) x ## ul +#else /* defined(__LP64__) */ +#define _PRI32PREFIX "l" +#define _PRI64PREFIX "ll" +#define _PRIPTRPREFIX +#define _SCN32PREFIX "l" +#define _SCN64PREFIX "ll" +#define _SCNPTRPREFIX +#define INT32_C(x) x ## l +#define INT64_C(x) x ## ll +#define UINT32_C(x) x ## ul +#define UINT64_C(x) x ## ull +#endif /* defined(__LP64__) */ + #define PRId8 "d" #define PRId16 "d" -#define PRId32 "d" -#define PRId64 "lld" +#define PRId32 _PRI32PREFIX "d" +#define PRId64 _PRI64PREFIX "d" -#define PRIdPTR "d" +#define PRIdPTR _PRIPTRPREFIX "d" #define PRIi8 "i" #define PRIi16 "i" -#define PRIi32 "i" -#define PRIi64 "lli" +#define PRIi32 _PRI32PREFIX "i" +#define PRIi64 _PRI64PREFIX "i" -#define PRIiPTR "i" +#define PRIiPTR _PRIPTRPREFIX "i" #define PRIo8 "o" #define PRIo16 "o" -#define PRIo32 "o" -#define PRIo64 "llo" +#define PRIo32 _PRI32PREFIX "o" +#define PRIo64 _PRI64PREFIX "o" -#define PRIoPTR "o" +#define PRIoPTR _PRIPTRPREFIX "o" #define PRIu8 "u" #define PRIu16 "u" -#define PRIu32 "u" -#define PRIu64 "llu" +#define PRIu32 _PRI32PREFIX "u" +#define PRIu64 _PRI64PREFIX "u" -#define PRIuPTR "u" +#define PRIuPTR _PRIPTRPREFIX "u" #define PRIx8 "x" #define PRIx16 "x" -#define PRIx32 "x" -#define PRIx64 "llx" +#define PRIx32 _PRI32PREFIX "x" +#define PRIx64 _PRI64PREFIX "x" -#define PRIxPTR "x" +#define PRIxPTR _PRIPTRPREFIX "x" #define PRIX8 "X" #define PRIX16 "X" -#define PRIX32 "X" -#define PRIX64 "llX" +#define PRIX32 _PRI32PREFIX "X" +#define PRIX64 _PRI64PREFIX "X" -#define PRIXPTR "X" +#define PRIXPTR _PRIPTRPREFIX "X" #define SCNd8 "hhd" #define SCNd16 "hd" -#define SCNd32 "d" -#define SCNd64 "lld" +#define SCNd32 _SCN32PREFIX "d" +#define SCNd64 _SCN64PREFIX "d" -#define SCNdPTR "d" +#define SCNdPTR _SCNPTRPREFIX "d" #define SCNi8 "hhi" #define SCNi16 "hi" -#define SCNi32 "i" -#define SCNi64 "lli" +#define SCNi32 _SCN32PREFIX "i" +#define SCNi64 _SCN64PREFIX "i" -#define SCNiPTR "i" +#define SCNiPTR _SCNPTRPREFIX "i" #define SCNo8 "hho" #define SCNo16 "ho" -#define SCNo32 "o" -#define SCNo64 "llo" +#define SCNo32 _SCN32PREFIX "o" +#define SCNo64 _SCN64PREFIX "o" -#define SCNoPTR "o" +#define SCNoPTR _SCNPTRPREFIX "o" #define SCNu8 "hhu" #define SCNu16 "hu" -#define SCNu32 "u" -#define SCNu64 "llu" +#define SCNu32 _SCN32PREFIX "u" +#define SCNu64 _SCN64PREFIX "u" -#define SCNuPTR "u" +#define SCNuPTR _SCNPTRPREFIX "u" #define SCNx8 "hhx" #define SCNx16 "hx" -#define SCNx32 "x" -#define SCNx64 "llx" +#define SCNx32 _SCN32PREFIX "x" +#define SCNx64 _SCN64PREFIX "x" -#define SCNxPTR "x" +#define SCNxPTR _SCNPTRPREFIX "x" #define INT8_C(x) x #define INT16_C(x) x -#define INT32_C(x) x -#define INT64_C(x) x ## ll #define UINT8_C(x) x #define UINT16_C(x) x -#define UINT32_C(x) x ## u -#define UINT64_C(x) x ## ull #endif /* __ARCH_RISCV_INCLUDE_INTTYPES_H */ diff --git a/arch/risc-v/include/types.h b/arch/risc-v/include/types.h index f4b4e55d451..c9d2060294f 100644 --- a/arch/risc-v/include/types.h +++ b/arch/risc-v/include/types.h @@ -69,13 +69,24 @@ typedef unsigned char _uint8_t; typedef signed short _int16_t; typedef unsigned short _uint16_t; +#ifdef __LP64__ typedef signed int _int32_t; typedef unsigned int _uint32_t; +typedef signed long _int64_t; +typedef unsigned long _uint64_t; +#else /* __LP64__ */ +typedef signed long _int32_t; +typedef unsigned long _uint32_t; + typedef signed long long _int64_t; typedef unsigned long long _uint64_t; +#endif /* __LP64__ */ #define __INT64_DEFINED +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; + #ifdef __LP64__ /* A size is 8 bytes */ diff --git a/arch/risc-v/src/Makefile b/arch/risc-v/src/Makefile index 5eb527ed0d7..caa9147bdaf 100644 --- a/arch/risc-v/src/Makefile +++ b/arch/risc-v/src/Makefile @@ -184,12 +184,15 @@ endif # Dependencies +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) + .depend: Makefile $(SRCS) $(TOPDIR)$(DELIM).config ifeq ($(BOARDMAKE),y) $(Q) $(MAKE) -C board depend endif - $(Q) $(MKDEP) $(patsubst %,--dep-path %,$(subst :, ,$(VPATH))) \ - "$(CC)" -- $(CFLAGS) -- $(SRCS) > Make.dep + $(Q) $(MAKE) makedepfile DEPPATH="$(patsubst %,--dep-path %,$(subst :, ,$(VPATH)))" $(Q) touch $@ depend: .depend diff --git a/arch/risc-v/src/fe310/fe310_schedulesigaction.c b/arch/risc-v/src/fe310/fe310_schedulesigaction.c index c2a69365466..33b5b46b2bc 100644 --- a/arch/risc-v/src/fe310/fe310_schedulesigaction.c +++ b/arch/risc-v/src/fe310/fe310_schedulesigaction.c @@ -41,6 +41,7 @@ #include +#include #include #include #include @@ -165,8 +166,9 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) up_savestate(tcb->xcp.regs); - sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n", - tcb->xcp.saved_epc, tcb->xcp.saved_status, + sinfo("PC/STATUS Saved: %08" PRIx32 "/%08" PRIx32 + " New: %08" PRIx32 "/%08" PRIx32 "\n", + tcb->xcp.saved_epc, tcb->xcp.saved_int_ctx, g_current_regs[REG_EPC], g_current_regs[REG_INT_CTX]); } } @@ -199,8 +201,9 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) tcb->xcp.regs[REG_INT_CTX] = int_ctx; - sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n", - tcb->xcp.saved_epc, tcb->xcp.saved_status, + sinfo("PC/STATUS Saved: %08" PRIx32 "/%08" PRIx32 + " New: %08" PRIx32 "/%08" PRIx32 "\n", + tcb->xcp.saved_epc, tcb->xcp.saved_int_ctx, tcb->xcp.regs[REG_EPC], tcb->xcp.regs[REG_INT_CTX]); } } diff --git a/arch/risc-v/src/fe310/fe310_serial.c b/arch/risc-v/src/fe310/fe310_serial.c index 82bad7ea160..fa8a69fb082 100644 --- a/arch/risc-v/src/fe310/fe310_serial.c +++ b/arch/risc-v/src/fe310/fe310_serial.c @@ -135,7 +135,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, FAR void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -444,7 +444,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { /* Return status information */ diff --git a/arch/risc-v/src/gap8/gap8_schedulesigaction.c b/arch/risc-v/src/gap8/gap8_schedulesigaction.c index 4c2a7fb9e2b..00b0601d42a 100644 --- a/arch/risc-v/src/gap8/gap8_schedulesigaction.c +++ b/arch/risc-v/src/gap8/gap8_schedulesigaction.c @@ -162,7 +162,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) up_savestate(tcb->xcp.regs); sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n", - tcb->xcp.saved_epc, tcb->xcp.saved_status, + tcb->xcp.saved_epc, tcb->xcp.saved_int_ctx, g_current_regs[REG_EPC], g_current_regs[REG_STATUS]); } } @@ -190,7 +190,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) tcb->xcp.regs[REG_EPC] = (uint32_t)up_sigdeliver; sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n", - tcb->xcp.saved_epc, tcb->xcp.saved_status, + tcb->xcp.saved_epc, tcb->xcp.saved_int_ctx, tcb->xcp.regs[REG_EPC], tcb->xcp.regs[REG_STATUS]); } } diff --git a/arch/risc-v/src/gap8/gap8_uart.c b/arch/risc-v/src/gap8/gap8_uart.c index 26c6bc3b7cf..99aaa84f507 100644 --- a/arch/risc-v/src/gap8/gap8_uart.c +++ b/arch/risc-v/src/gap8/gap8_uart.c @@ -115,7 +115,7 @@ static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -434,7 +434,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct gap8_uart_t *the_uart = (struct gap8_uart_t *)dev->priv; uint8_t ch = the_uart->rx_buf[0]; diff --git a/arch/risc-v/src/k210/k210_schedulesigaction.c b/arch/risc-v/src/k210/k210_schedulesigaction.c index da8711223a9..26a6c7771df 100644 --- a/arch/risc-v/src/k210/k210_schedulesigaction.c +++ b/arch/risc-v/src/k210/k210_schedulesigaction.c @@ -41,6 +41,7 @@ #include +#include #include #include #include @@ -172,8 +173,9 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) up_savestate(tcb->xcp.regs); - sinfo("PC/STATUS Saved: %016x/%016x New: %016x/%016x\n", - tcb->xcp.saved_epc, tcb->xcp.saved_status, + sinfo("PC/STATUS Saved: %016" PRIx64 "/%016" PRIx64 + " New: %016" PRIx64 "/%016" PRIx64 "\n", + tcb->xcp.saved_epc, tcb->xcp.saved_int_ctx, CURRENT_REGS[REG_EPC], CURRENT_REGS[REG_INT_CTX]); } } @@ -207,8 +209,9 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) tcb->xcp.regs[REG_INT_CTX] = int_ctx; - sinfo("PC/STATUS Saved: %016x/%016x New: %016x/%016x\n", - tcb->xcp.saved_epc, tcb->xcp.saved_status, + sinfo("PC/STATUS Saved: %016" PRIx64 "/%016" PRIx64 + " New: %016" PRIx64 "/%016" PRIx64 "\n", + tcb->xcp.saved_epc, tcb->xcp.saved_int_ctx, tcb->xcp.regs[REG_EPC], tcb->xcp.regs[REG_INT_CTX]); } } diff --git a/arch/risc-v/src/k210/k210_serial.c b/arch/risc-v/src/k210/k210_serial.c index 572dd938dd5..e12fd89bf00 100644 --- a/arch/risc-v/src/k210/k210_serial.c +++ b/arch/risc-v/src/k210/k210_serial.c @@ -135,7 +135,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, FAR void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -444,7 +444,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { /* Return status information */ diff --git a/arch/risc-v/src/litex/litex_serial.c b/arch/risc-v/src/litex/litex_serial.c index 161843fb391..9647d26f539 100644 --- a/arch/risc-v/src/litex/litex_serial.c +++ b/arch/risc-v/src/litex/litex_serial.c @@ -144,7 +144,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, FAR void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -452,7 +452,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; int rxdata; diff --git a/arch/risc-v/src/nr5m100/nr5_schedulesigaction.c b/arch/risc-v/src/nr5m100/nr5_schedulesigaction.c index 8c1af39b6f7..0614f72a29a 100644 --- a/arch/risc-v/src/nr5m100/nr5_schedulesigaction.c +++ b/arch/risc-v/src/nr5m100/nr5_schedulesigaction.c @@ -167,7 +167,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) up_savestate(tcb->xcp.regs); sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n", - tcb->xcp.saved_epc, tcb->xcp.saved_status, + tcb->xcp.saved_epc, tcb->xcp.saved_int_ctx, g_current_regs[REG_EPC], g_current_regs[REG_STATUS]); } } @@ -200,7 +200,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) tcb->xcp.regs[REG_INT_CTX] = int_ctx; sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n", - tcb->xcp.saved_epc, tcb->xcp.saved_status, + tcb->xcp.saved_epc, tcb->xcp.saved_int_ctx, tcb->xcp.regs[REG_EPC], tcb->xcp.regs[REG_STATUS]); } } diff --git a/arch/risc-v/src/nr5m100/nr5_serial.c b/arch/risc-v/src/nr5m100/nr5_serial.c index 7765a1ac71b..bc5c225f03e 100644 --- a/arch/risc-v/src/nr5m100/nr5_serial.c +++ b/arch/risc-v/src/nr5m100/nr5_serial.c @@ -161,7 +161,7 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, FAR void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); static void up_send(struct uart_dev_s *dev, int ch); @@ -570,7 +570,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int up_receive(struct uart_dev_s *dev, uint32_t *status) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; diff --git a/arch/risc-v/src/rv32im/riscv_sigdeliver.c b/arch/risc-v/src/rv32im/riscv_sigdeliver.c index c1b7ece650c..cdb2741e02a 100644 --- a/arch/risc-v/src/rv32im/riscv_sigdeliver.c +++ b/arch/risc-v/src/rv32im/riscv_sigdeliver.c @@ -44,6 +44,7 @@ #include +#include #include #include #include @@ -111,7 +112,7 @@ void up_sigdeliver(void) * errno that is needed by the user logic (it is probably EINTR). */ - sinfo("Resuming EPC: %08x INT_CTX: %08x\n", + sinfo("Resuming EPC: %08" PRIx32 " INT_CTX: %08" PRIx32 "\n", regs[REG_EPC], regs[REG_INT_CTX]); up_irq_save(); diff --git a/arch/risc-v/src/rv32im/riscv_swint.c b/arch/risc-v/src/rv32im/riscv_swint.c index 51204cd0cde..de3ecb3eb3e 100644 --- a/arch/risc-v/src/rv32im/riscv_swint.c +++ b/arch/risc-v/src/rv32im/riscv_swint.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -294,7 +295,7 @@ int up_swint(int irq, FAR void *context, FAR void *arg) rtcb->flags |= TCB_FLAG_SYSCALL; #else - svcerr("ERROR: Bad SYS call: %d\n", regs[REG_A0]); + svcerr("ERROR: Bad SYS call: %" PRId32 "\n", regs[REG_A0]); #endif } break; diff --git a/arch/risc-v/src/rv64gc/riscv_sigdeliver.c b/arch/risc-v/src/rv64gc/riscv_sigdeliver.c index 9f21dcc9aae..b08dff18efe 100644 --- a/arch/risc-v/src/rv64gc/riscv_sigdeliver.c +++ b/arch/risc-v/src/rv64gc/riscv_sigdeliver.c @@ -44,6 +44,7 @@ #include +#include #include #include #include @@ -140,7 +141,7 @@ void up_sigdeliver(void) * errno that is needed by the user logic (it is probably EINTR). */ - sinfo("Resuming EPC: %016x INT_CTX: %016x\n", + sinfo("Resuming EPC: %016" PRIx64 " INT_CTX: %016" PRIx64 "\n", regs[REG_EPC], regs[REG_INT_CTX]); /* Call enter_critical_section() to disable local interrupts before diff --git a/arch/risc-v/src/rv64gc/riscv_swint.c b/arch/risc-v/src/rv64gc/riscv_swint.c index 8061102f28a..8fe94359e55 100644 --- a/arch/risc-v/src/rv64gc/riscv_swint.c +++ b/arch/risc-v/src/rv64gc/riscv_swint.c @@ -39,6 +39,7 @@ #include +#include #include #include #include @@ -439,7 +440,7 @@ int up_swint(int irq, FAR void *context, FAR void *arg) rtcb->flags |= TCB_FLAG_SYSCALL; #else - svcerr("ERROR: Bad SYS call: %d\n", regs[REG_A0]); + svcerr("ERROR: Bad SYS call: %" PRId64 "\n", regs[REG_A0]); #endif } break; diff --git a/arch/sim/include/inttypes.h b/arch/sim/include/inttypes.h index 4404aae83e3..31942efac23 100644 --- a/arch/sim/include/inttypes.h +++ b/arch/sim/include/inttypes.h @@ -44,131 +44,93 @@ * Pre-processor Definitions ****************************************************************************/ +#if defined(__APPLE_CC__) || !defined(_LP64) +# define _PRI64PREFIX "ll" +# define _SCN64PREFIX "ll" +# define INT64_C(x) x ## ll +# define UINT64_C(x) x ## ull +#else +# define _PRI64PREFIX "l" +# define _SCN64PREFIX "l" +# define INT64_C(x) x ## l +# define UINT64_C(x) x ## ul +#endif + # define PRId8 "d" # define PRId16 "d" # define PRId32 "d" -# define PRId64 "lld" +# define PRId64 _PRI64PREFIX "d" # define PRIi8 "i" # define PRIi16 "i" # define PRIi32 "i" -# define PRIi64 "lli" +# define PRIi64 _PRI64PREFIX "i" # define PRIo8 "o" # define PRIo16 "o" # define PRIo32 "o" -# define PRIo64 "llo" +# define PRIo64 _PRI64PREFIX "o" # define PRIu8 "u" # define PRIu16 "u" # define PRIu32 "u" -# define PRIu64 "llu" - -# define PRIuMAX "llu" +# define PRIu64 _PRI64PREFIX "u" # define PRIx8 "x" # define PRIx16 "x" # define PRIx32 "x" -# define PRIx64 "llx" +# define PRIx64 _PRI64PREFIX "x" # define PRIX8 "X" # define PRIX16 "X" # define PRIX32 "X" -# define PRIX64 "llX" +# define PRIX64 _PRI64PREFIX "X" # define SCNd8 "hhd" # define SCNd16 "hd" # define SCNd32 "d" -# define SCNd64 "lld" - -# define SCNdMAX "lld" +# define SCNd64 _SCN64PREFIX "d" # define SCNi8 "hhi" # define SCNi16 "hi" # define SCNi32 "i" -# define SCNi64 "lli" - -# define SCNiLEAST8 "hhi" -# define SCNiLEAST16 "hi" -# define SCNiLEAST32 "i" -# define SCNiLEAST64 "lli" - -# define SCNiFAST8 "hhi" -# define SCNiFAST16 "hi" -# define SCNiFAST32 "i" -# define SCNiFAST64 "lli" - -# define SCNiMAX "lli" +# define SCNi64 _SCN64PREFIX "i" # define SCNo8 "hho" # define SCNo16 "ho" # define SCNo32 "o" -# define SCNo64 "llo" - -# define SCNoLEAST8 "hho" -# define SCNoLEAST16 "ho" -# define SCNoLEAST32 "o" -# define SCNoLEAST64 "llo" - -# define SCNoFAST8 "hho" -# define SCNoFAST16 "ho" -# define SCNoFAST32 "o" -# define SCNoFAST64 "llo" - -# define SCNoMAX "llo" +# define SCNo64 _SCN64PREFIX "o" # define SCNu8 "hhu" # define SCNu16 "hu" # define SCNu32 "u" -# define SCNu64 "llu" - -# define SCNuLEAST8 "hhu" -# define SCNuLEAST16 "hu" -# define SCNuLEAST32 "u" -# define SCNuLEAST64 "llu" - -# define SCNuFAST8 "hhu" -# define SCNuFAST16 "hu" -# define SCNuFAST32 "u" -# define SCNuFAST64 "llu" +# define SCNu64 _SCN64PREFIX "u" # define SCNx8 "hhx" # define SCNx16 "hx" # define SCNx32 "x" -# define SCNx64 "llx" - -# define SCNxLEAST8 "hhx" -# define SCNxLEAST16 "hx" -# define SCNxLEAST32 "x" -# define SCNxLEAST64 "llx" - -# define SCNxFAST8 "hhx" -# define SCNxFAST16 "hx" -# define SCNxFAST32 "x" -# define SCNxFAST64 "llx" +# define SCNx64 _SCN64PREFIX "x" # define INT8_C(x) x # define INT16_C(x) x # define INT32_C(x) x -# define INT64_C(x) x ## ll # define UINT8_C(x) x # define UINT16_C(x) x # define UINT32_C(x) x ## u -# define UINT64_C(x) x ## ull #if defined(CONFIG_HOST_X86_64) && !defined(CONFIG_SIM_M32) -# define PRIdPTR "lld" -# define PRIiPTR "lli" -# define PRIoPTR "llo" -# define PRIuPTR "llu" -# define PRIxPTR "llx" -# define PRIXPTR "llX" -# define SCNdPTR "lld" -# define SCNiPTR "lli" -# define SCNoPTR "llo" -# define SCNuPTR "llu" -# define SCNxPTR "llx" +# define PRIdPTR "ld" +# define PRIiPTR "li" +# define PRIoPTR "lo" +# define PRIuPTR "lu" +# define PRIxPTR "lx" +# define PRIXPTR "lX" +# define SCNdPTR "ld" +# define SCNiPTR "li" +# define SCNoPTR "lo" +# define SCNuPTR "lu" +# define SCNxPTR "lx" #else # define PRIdPTR "d" # define PRIiPTR "i" diff --git a/arch/sim/include/types.h b/arch/sim/include/types.h index d9d4fd3aee7..5d0958e7a76 100644 --- a/arch/sim/include/types.h +++ b/arch/sim/include/types.h @@ -72,10 +72,35 @@ typedef unsigned short _uint16_t; typedef signed int _int32_t; typedef unsigned int _uint32_t; +/* Note about host OS types: + * - int64_t is long long for 64-bit macOS + * - int64_t is long for Ubuntu x86-64 + * + * Note for sim/macOS modules: + * For sim/macOS, usually x86_64-elf-gcc from homebrew is used + * as MODULECC. It seems to be configured as __INT64_TYPE__ == long int. + * The __APPLE_CC__ check below is to workaround it. + * (The host cc defines __APPLE_CC__, while x86_64-elf-gcc doesn't.) + * XXX It is a problem if you need C++ symbols in symtabs for modules. + */ + +#if defined(__APPLE_CC__) || !defined(_LP64) typedef signed long long _int64_t; typedef unsigned long long _uint64_t; +#else +typedef signed long _int64_t; +typedef unsigned long _uint64_t; +#endif #define __INT64_DEFINED +#if defined(__APPLE_CC__) +typedef signed long _intmax_t; +typedef unsigned long _uintmax_t; +#else +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; +#endif + #if defined(CONFIG_HOST_X86_64) && !defined(CONFIG_SIM_M32) /* 64-bit build on 64-bit machine: A size is 8 bytes */ diff --git a/arch/sim/src/Makefile b/arch/sim/src/Makefile index af0f2289821..611f09a2b2e 100644 --- a/arch/sim/src/Makefile +++ b/arch/sim/src/Makefile @@ -330,12 +330,15 @@ export_startup: board/libboard$(LIBEXT) up_head.o $(HOSTOBJS) nuttx-names.dat # Dependencies +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) $(HOSTSRCS:.c=.ddh) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) + .depend: Makefile $(SRCS) $(TOPDIR)$(DELIM).config $(Q) if [ -e board/Makefile ]; then \ $(MAKE) -C board depend ; \ fi - $(Q) $(MKDEP) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(ASRCS) $(CSRCS) >Make.dep - $(Q) $(MKDEP) $(DEPPATH) "$(CC)" -- $(HOSTCFLAGS) -- $(HOSTSRCS) >>Make.dep + $(Q) $(MAKE) makedepfile $(Q) touch $@ depend: .depend diff --git a/arch/x86/include/i486/types.h b/arch/x86/include/i486/types.h index c5e665213fa..378ae339d3f 100644 --- a/arch/x86/include/i486/types.h +++ b/arch/x86/include/i486/types.h @@ -77,6 +77,9 @@ typedef signed long long _int64_t; typedef unsigned long long _uint64_t; #define __INT64_DEFINED +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; + /* A size is 4 bytes */ #if defined(__SIZE_TYPE__) diff --git a/arch/x86/src/Makefile b/arch/x86/src/Makefile index 3dc110fa165..fa2cfd39984 100644 --- a/arch/x86/src/Makefile +++ b/arch/x86/src/Makefile @@ -153,12 +153,15 @@ export_startup: board/libboard$(LIBEXT) $(STARTUP_OBJS) # Dependencies +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) + .depend: Makefile chip/Make.defs $(SRCS) $(TOPDIR)$(DELIM).config ifeq ($(BOARDMAKE),y) $(Q) $(MAKE) -C board depend endif - $(Q) $(MKDEP) --dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR) \ - "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile DEPPATH="--dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR)" $(Q) touch $@ depend: .depend diff --git a/arch/x86_64/include/intel64/inttypes.h b/arch/x86_64/include/intel64/inttypes.h index 19a8d39041e..7ad148a3691 100644 --- a/arch/x86_64/include/intel64/inttypes.h +++ b/arch/x86_64/include/intel64/inttypes.h @@ -32,88 +32,88 @@ #define PRId8 "d" #define PRId16 "d" #define PRId32 "d" -#define PRId64 "lld" +#define PRId64 "ld" -#define PRIdPTR "lld" +#define PRIdPTR "ld" #define PRIi8 "i" #define PRIi16 "i" #define PRIi32 "i" -#define PRIi64 "lli" +#define PRIi64 "li" -#define PRIiPTR "lli" +#define PRIiPTR "li" #define PRIo8 "o" #define PRIo16 "o" #define PRIo32 "o" -#define PRIo64 "llo" +#define PRIo64 "lo" -#define PRIoPTR "llo" +#define PRIoPTR "lo" #define PRIu8 "u" #define PRIu16 "u" #define PRIu32 "u" -#define PRIu64 "llu" +#define PRIu64 "lu" -#define PRIuPTR "llu" +#define PRIuPTR "lu" #define PRIx8 "x" #define PRIx16 "x" #define PRIx32 "x" -#define PRIx64 "llx" +#define PRIx64 "lx" -#define PRIxPTR "llx" +#define PRIxPTR "lx" #define PRIX8 "X" #define PRIX16 "X" #define PRIX32 "X" -#define PRIX64 "llX" +#define PRIX64 "lX" -#define PRIXPTR "llX" +#define PRIXPTR "lX" #define SCNd8 "hhd" #define SCNd16 "hd" #define SCNd32 "d" -#define SCNd64 "lld" +#define SCNd64 "ld" -#define SCNdPTR "lld" +#define SCNdPTR "ld" #define SCNi8 "hhi" #define SCNi16 "hi" #define SCNi32 "i" -#define SCNi64 "lli" +#define SCNi64 "li" -#define SCNiPTR "lli" +#define SCNiPTR "li" #define SCNo8 "hho" #define SCNo16 "ho" #define SCNo32 "o" -#define SCNo64 "llo" +#define SCNo64 "lo" -#define SCNoPTR "llo" +#define SCNoPTR "lo" #define SCNu8 "hhu" #define SCNu16 "hu" #define SCNu32 "u" -#define SCNu64 "llu" +#define SCNu64 "lu" #define SCNuPTR "u" #define SCNx8 "hhx" #define SCNx16 "hx" #define SCNx32 "x" -#define SCNx64 "llx" +#define SCNx64 "lx" -#define SCNxPTR "x" +#define SCNxPTR "lx" #define INT8_C(x) x #define INT16_C(x) x #define INT32_C(x) x -#define INT64_C(x) x ## ll +#define INT64_C(x) x ## l #define UINT8_C(x) x #define UINT16_C(x) x #define UINT32_C(x) x ## u -#define UINT64_C(x) x ## ull +#define UINT64_C(x) x ## ul #endif /* __ARCH_X86_64_INCLUDE_INTEL64_INTTYPES_H */ diff --git a/arch/x86_64/include/intel64/types.h b/arch/x86_64/include/intel64/types.h index bb99f255e7a..6a52fe0da93 100644 --- a/arch/x86_64/include/intel64/types.h +++ b/arch/x86_64/include/intel64/types.h @@ -58,14 +58,12 @@ typedef unsigned short _uint16_t; typedef signed int _int32_t; typedef unsigned int _uint32_t; -typedef signed long long _int64_t; -typedef unsigned long long _uint64_t; +typedef signed long _int64_t; +typedef unsigned long _uint64_t; #define __INT64_DEFINED -/* A pointer is 8 bytes */ - -typedef signed long long _intptr_t; -typedef unsigned long long _uintptr_t; +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; #if defined(__SIZE_TYPE__) /* If __SIZE_TYPE__ is defined we define ssize_t based on size_t. diff --git a/arch/x86_64/src/Makefile b/arch/x86_64/src/Makefile index f4aab34aa81..dac97433221 100644 --- a/arch/x86_64/src/Makefile +++ b/arch/x86_64/src/Makefile @@ -148,12 +148,15 @@ export_startup: board/libboard$(LIBEXT) $(STARTUP_OBJS) # Dependencies +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) + .depend: Makefile chip/Make.defs $(SRCS) $(TOPDIR)$(DELIM).config ifeq ($(BOARDMAKE),y) $(Q) $(MAKE) -C board depend endif - $(Q) $(MKDEP) --dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR) \ - "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile DEPPATH="--dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR)" $(Q) touch $@ depend: .depend diff --git a/arch/x86_64/src/intel64/intel64_handlers.c b/arch/x86_64/src/intel64/intel64_handlers.c index c6963e9fa78..7e569a0c441 100644 --- a/arch/x86_64/src/intel64/intel64_handlers.c +++ b/arch/x86_64/src/intel64/intel64_handlers.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -163,7 +164,8 @@ uint64_t *isr_handler(uint64_t *regs, uint64_t irq) */ _alert("PANIC:\n"); - _alert("Exception %lld occurred with error code %lld:\n", + _alert("Exception %" PRId64 " occurred " + "with error code %" PRId64 ":\n", irq, regs[REG_ERRCODE]); up_registerdump(regs); diff --git a/arch/x86_64/src/intel64/intel64_tickless.c b/arch/x86_64/src/intel64/intel64_tickless.c index 84d59f2cdc7..11097edda93 100644 --- a/arch/x86_64/src/intel64/intel64_tickless.c +++ b/arch/x86_64/src/intel64/intel64_tickless.c @@ -436,7 +436,7 @@ int up_alarm_start(FAR const struct timespec *ts) up_tmr_sync_down(); - tmrinfo("%d.%09d\n", ts->tv_sec, ts->tv_nsec); + tmrinfo("%d.%09ld\n", ts->tv_sec, ts->tv_nsec); tmrinfo("start\n"); return OK; diff --git a/arch/x86_64/src/intel64/up_regdump.c b/arch/x86_64/src/intel64/up_regdump.c index 70e8daf1be8..bcc1f32feec 100644 --- a/arch/x86_64/src/intel64/up_regdump.c +++ b/arch/x86_64/src/intel64/up_regdump.c @@ -24,6 +24,7 @@ #include +#include #include #include @@ -43,7 +44,7 @@ void print_mem(void *sp, size_t size) int i; int j; - _alert("Memory Dump (%d bytes):\n", size); + _alert("Memory Dump (%zu bytes):\n", size); for (i = 0; i < size / 8; i++) { @@ -57,8 +58,8 @@ void print_mem(void *sp, size_t size) } buf[8] = '\0'; - _alert(" %016llx\t%02x %02x %02x %02x %02x %02x %02x %02x\t%s\n", - (sp + i * 8), + _alert(" %016" PRIxPTR "\t%02x %02x %02x %02x %02x %02x %02x %02x\t%s\n", + (uintptr_t)(sp + i * 8), *((uint8_t *)(sp + i * 8 + 0)), *((uint8_t *)(sp + i * 8 + 1)), *((uint8_t *)(sp + i * 8 + 2)), @@ -84,7 +85,7 @@ void backtrace(uint64_t rbp) break; } - _alert(" %016llx\t%016llx\n", + _alert(" %016" PRIx64 "\t%016" PRIx64 "\n", *((uint64_t *)(rbp)), *((uint64_t *)(rbp + 1 * 8))); if ((rbp) && *((uint64_t *)(rbp + 1 * 8))) @@ -107,28 +108,37 @@ void up_registerdump(uint64_t *regs) asm volatile ("mov %%cr2, %%rax; mov %%rax, %0"::"m"(cr2):"memory", "rax"); _alert("----------------CUT HERE-----------------\n"); _alert("Gerneral Informations:\n"); - _alert("CPL: %d, RPL: %d\n", regs[REG_CS] & 0x3, regs[REG_DS] & 0x3); - _alert("RIP: %016llx, RSP: %016llx\n", regs[REG_RIP], regs[REG_RSP]); - _alert("RBP: %016llx, RFLAGS: %016llx\n", + _alert("CPL: %" PRId64 ", RPL: %" PRId64 "\n", + regs[REG_CS] & 0x3, regs[REG_DS] & 0x3); + _alert("RIP: %016" PRIx64 ", RSP: %016" PRIx64 "\n", + regs[REG_RIP], regs[REG_RSP]); + _alert("RBP: %016" PRIx64 ", RFLAGS: %016" PRIx64 "\n", regs[REG_RBP], regs[REG_RFLAGS]); - _alert("MSR_STAR: %016llx, MSR_LSTAR: %016llx\n", + _alert("MSR_STAR: %016" PRIx64 ", MSR_LSTAR: %016" PRIx64 "\n", read_msr(0xc0000081), read_msr(0xc0000082)); - _alert("MXCSR: %016llx, MSR_FS_BASE: %016llx\n", + _alert("MXCSR: %016" PRIx64 ", MSR_FS_BASE: %016" PRIx64 "\n", mxcsr, read_msr(MSR_FS_BASE)); - _alert("CR2: %016llx\n", cr2); + _alert("CR2: %016" PRIx64 "\n", cr2); _alert("Selector Dump:\n"); - _alert("CS: %016llx, DS: %016llx, SS: %016llx\n", + _alert("CS: %016" PRIx64 ", DS: %016" PRIx64 ", SS: %016" PRIx64 "\n", regs[REG_CS], regs[REG_DS], regs[REG_SS]); - _alert("ES: %016llx, FS: %016llx, GS: %016llx\n", + _alert("ES: %016" PRIx64 ", FS: %016" PRIx64 ", GS: %016" PRIx64 "\n", regs[REG_ES], regs[REG_FS], regs[REG_GS]); _alert("Register Dump:\n"); - _alert("RAX: %016llx, RBX: %016llx\n", regs[REG_RAX], regs[REG_RBX]); - _alert("RCX: %016llx, RDX: %016llx\n", regs[REG_RCX], regs[REG_RDX]); - _alert("RDI: %016llx, RSI: %016llx\n", regs[REG_RDI], regs[REG_RSI]); - _alert(" R8: %016llx, R9: %016llx\n", regs[REG_R8] , regs[REG_R9]); - _alert("R10: %016llx, R11: %016llx\n", regs[REG_R10], regs[REG_R11]); - _alert("R12: %016llx, R13: %016llx\n", regs[REG_R12], regs[REG_R13]); - _alert("R14: %016llx, R15: %016llx\n", regs[REG_R14], regs[REG_R15]); + _alert("RAX: %016" PRIx64 ", RBX: %016" PRIx64 "\n", + regs[REG_RAX], regs[REG_RBX]); + _alert("RCX: %016" PRIx64 ", RDX: %016" PRIx64 "\n", + regs[REG_RCX], regs[REG_RDX]); + _alert("RDI: %016" PRIx64 ", RSI: %016" PRIx64 "\n", + regs[REG_RDI], regs[REG_RSI]); + _alert(" R8: %016" PRIx64 ", R9: %016" PRIx64 "\n", + regs[REG_R8] , regs[REG_R9]); + _alert("R10: %016" PRIx64 ", R11: %016" PRIx64 "\n", + regs[REG_R10], regs[REG_R11]); + _alert("R12: %016" PRIx64 ", R13: %016" PRIx64 "\n", + regs[REG_R12], regs[REG_R13]); + _alert("R14: %016" PRIx64 ", R15: %016" PRIx64 "\n", + regs[REG_R14], regs[REG_R15]); _alert("Dumping Stack (+-64 bytes):\n"); if (regs[REG_RSP] > 0 && regs[REG_RSP] < 0x1000000) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 250384c020c..5ef6d021e20 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -94,6 +94,20 @@ config XTENSA_CP_INITSET is provided by CONFIG_XTENSA_CP_INITSET. Each bit corresponds to one coprocessor with the same bit layout as for the CPENABLE register. +config XTENSA_DUMPBT_ON_ASSERT + bool "Dump backtrace on assertions" + default y + depends on DEBUG_ALERT + ---help--- + Enable a backtrace dump on assertions. + +config XTENSA_BTDEPTH + int "Backtrace depth" + default 50 + depends on XTENSA_DUMPBT_ON_ASSERT + ---help--- + This is the depth of the backtrace. + config XTENSA_USE_SEPARATE_IMEM bool "Use a separate heap for internal memory" default n diff --git a/arch/xtensa/include/types.h b/arch/xtensa/include/types.h index bb13a1b3e65..496fd6288f6 100644 --- a/arch/xtensa/include/types.h +++ b/arch/xtensa/include/types.h @@ -69,13 +69,16 @@ typedef unsigned char _uint8_t; typedef signed short _int16_t; typedef unsigned short _uint16_t; -typedef signed long _int32_t; -typedef unsigned long _uint32_t; +typedef signed int _int32_t; +typedef unsigned int _uint32_t; typedef signed long long _int64_t; typedef unsigned long long _uint64_t; #define __INT64_DEFINED +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; + /* A size is 4 bytes */ #if defined(__SIZE_TYPE__) diff --git a/arch/xtensa/src/Makefile b/arch/xtensa/src/Makefile index ad0e4faaadd..31a454457b5 100644 --- a/arch/xtensa/src/Makefile +++ b/arch/xtensa/src/Makefile @@ -139,12 +139,15 @@ export_startup: board/libboard$(LIBEXT) $(STARTUP_OBJS) # Dependencies +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) + .depend: Makefile chip/Make.defs $(SRCS) $(TOPDIR)$(DELIM).config ifeq ($(BOARDMAKE),y) $(Q) $(MAKE) -C board depend endif - $(Q) $(MKDEP) --dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR) \ - "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile DEPPATH="--dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR)" $(Q) touch $@ depend: .depend diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 27f2de96f31..5b770a4880a 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -361,5 +361,9 @@ void xtensa_pminitialize(void); void up_stack_color(FAR void *stackbase, size_t nbytes); #endif +#ifdef CONFIG_XTENSA_DUMPBT_ON_ASSERT +void xtensa_backtrace_start(uint32_t *pc, uint32_t *sp, uint32_t *next_pc); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_H */ diff --git a/arch/xtensa/src/common/xtensa_backtrace.S b/arch/xtensa/src/common/xtensa_backtrace.S new file mode 100644 index 00000000000..f4360466046 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_backtrace.S @@ -0,0 +1,103 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_dumpstate.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "xtensa_abi.h" + +/* + * This is how the stack looks like when calling the function below: + * + * High Addr + * .................. + * | i-3 BSA | + * | i-1 locals | Function B + * .................. i-1 SP + * | i-2 BSA | + * | i locals | Function A (Start of backtrace) + * ------------------ i SP + * | i-1 BSA | + * | i+1 locals | Backtracing function (e.g. xtensa_btdump()) + * ------------------ i+1 SP + * | i BSA | + * | i+2 locals | xtensa_backtrace_start() + * ------------------ i+2 SP + * | i+1 BSA | + * | i+3 locals | xtensa_window_spill() + * ------------------ i+3 SP + * .................. Low Addr + */ + +/**************************************************************************** + * Name: xtensa_backtrace_start + * + * Description: + * Get the first frame of the current stack's backtrace + * + * Given the following function call flow (B -> A -> X -> xtensa_backtrace_start), + * this function will do the following: + * - Flush CPU registers and window frames onto the current stack + * - Return PC and SP of function A (i.e. start of the stack's backtrace) + * - Return PC of function B (i.e. next_pc) + * + * Input Parameters: + * pc - PC of the first frame in the backtrace + * sp - SP of the first frame in the backtrace + * next_pc - PC of the first frame's caller + * + * C callable as: + * void xtensa_backtrace_start(uint32_t *pc, uint32_t *sp, uint32_t *next_pc) + * + ****************************************************************************/ + + .section .iram1, "ax" + .global xtensa_backtrace_start + .type xtensa_backtrace_start, @function + .align 4 + +xtensa_backtrace_start: + + ENTRY(32) + + call8 xtensa_window_spill /* Spill registers onto stack (excluding this + * function) */ + + /* a2, a3, a4 should be out arguments for i SP, i PC, i-1 PC respectively. + * Use a5 and a6 as scratch. + */ + + l32e a5, sp, -16 /* Get i PC, which is ret addres of i+1 */ + s32i a5, a2, 0 /* Store i PC to arg *pc */ + l32e a6, sp, -12 /* Get i+1 SP. Used to access i BS */ + l32e a5, a6, -12 /* Get i SP */ + s32i a5, a3, 0 /* Store i SP to arg *sp */ + l32e a5, a6, -16 /* Get i-1 PC, which is ret address of i */ + s32i a5, a4, 0 /* Store i-1 PC to arg *next_pc */ + RET0 + + .size xtensa_backtrace_start, . - xtensa_backtrace_start + diff --git a/arch/xtensa/src/common/xtensa_createstack.c b/arch/xtensa/src/common/xtensa_createstack.c index d91f0ade934..2dce2dceea7 100644 --- a/arch/xtensa/src/common/xtensa_createstack.c +++ b/arch/xtensa/src/common/xtensa_createstack.c @@ -60,9 +60,9 @@ * Pre-processor Macros ****************************************************************************/ -/* XTENSA requires at least a 4-byte stack alignment. */ +/* XTENSA requires at least a 16-byte stack alignment. */ -#define STACK_ALIGNMENT 4 +#define STACK_ALIGNMENT 16 /* Stack alignment macros */ diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c index 85461760a62..7b31d325e39 100644 --- a/arch/xtensa/src/common/xtensa_dumpstate.c +++ b/arch/xtensa/src/common/xtensa_dumpstate.c @@ -32,12 +32,12 @@ #include #include +#include #include #include - #include "sched/sched.h" #include "xtensa.h" -#include "chip_macros.h" +#include "chip_memory.h" #ifdef CONFIG_DEBUG_ALERT @@ -150,6 +150,109 @@ static inline void xtensa_registerdump(void) #endif } +#ifdef CONFIG_XTENSA_DUMPBT_ON_ASSERT + +/**************************************************************************** + * Name: xtensa_getcause + ****************************************************************************/ + +static inline uint32_t xtensa_getcause(void) +{ + uint32_t cause; + + __asm__ __volatile__ + ( + "rsr %0, EXCCAUSE" : "=r"(cause) + ); + + return cause; +} + +/**************************************************************************** + * Name: stackpc + ****************************************************************************/ + +static inline uint32_t stackpc(uint32_t pc) +{ + if (pc & 0x80000000) + { + /* Top two bits of a0 (return address) specify window increment. + * Overwrite to map to address space. + */ + + pc = (pc & 0x3fffffff) | 0x40000000; + } + + /* Minus 3 to get PC of previous instruction (i.e. instruction executed + * before return address). + */ + + return pc - 3; +} + +/**************************************************************************** + * Name: corruptedframe + ****************************************************************************/ + +static inline bool corruptedframe(uint32_t pc, uint32_t sp) +{ + return !(xtensa_ptr_exec((void *)stackpc(pc)) || xtensa_sp_sane(sp)); +} + +/**************************************************************************** + * Name: nextframe + ****************************************************************************/ + +static bool nextframe(uint32_t *pc, uint32_t *sp, uint32_t *npc) +{ + /* Use frame(i - 1)'s base save area located below frame(i)'s sp to get + * frame(i - 1)'s sp and frame(i - 2)'s pc. Base save area consists of + * 4 words under SP. + */ + + void *bsa = (void *)*sp; + + *pc = *npc; + *npc = *((uint32_t *)(bsa - 16)); + *sp = *((uint32_t *)(bsa - 12)); + + return !corruptedframe(*pc, *sp); +} + +/**************************************************************************** + * Name: xtensa_btdump + ****************************************************************************/ + +static inline void xtensa_btdump(void) +{ + uint32_t pc; + uint32_t sp; + uint32_t npc; + int i; + bool corrupted = false; + + xtensa_backtrace_start(&pc, &sp, &npc); + + _alert("Backtrace0: %x:%x\n", stackpc(pc), sp); + + corrupted = corruptedframe(pc, sp) && + !(xtensa_getcause() == EXCCAUSE_INSTR_PROHIBITED); + + for (i = 1; i <= CONFIG_XTENSA_BTDEPTH && npc != 0 && !corrupted; i++) + { + if (!nextframe(&pc, &sp, &npc)) + { + corrupted = true; + } + + _alert("Backtrace%d: %x:%x\n", i, stackpc(pc), sp); + } + + _alert("BACKTRACE %s\n", + (corrupted ? "CORRUPTED!" : (npc == 0 ? "Done":"CONTINUES..."))); +} +#endif /* CONFIG_XTENSA_DUMPBT_ON_ASSERT */ + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -179,6 +282,12 @@ void xtensa_dumpstate(void) xtensa_registerdump(); + /* Dump the backtrace */ + +#ifdef CONFIG_XTENSA_DUMPBT_ON_ASSERT + xtensa_btdump(); +#endif + /* Get the limits on the user stack memory */ ustackbase = (uint32_t)rtcb->adj_stack_ptr; @@ -267,4 +376,4 @@ void xtensa_dumpstate(void) up_showtasks(); } -#endif /* CONFIG_ARCH_STACKDUMP */ +#endif /* CONFIG_DEBUG_ALERT */ diff --git a/arch/xtensa/src/common/xtensa_windowspill.S b/arch/xtensa/src/common/xtensa_windowspill.S index c69cf3a8c6a..eed7c3b5520 100644 --- a/arch/xtensa/src/common/xtensa_windowspill.S +++ b/arch/xtensa/src/common/xtensa_windowspill.S @@ -41,6 +41,8 @@ #include #include +#include + #include "xtensa_abi.h" /**************************************************************************** @@ -144,13 +146,13 @@ _xtensa_window_spill: rsr a2, WINDOWBASE addi a2, a2, 1 - ssr a2 /* sar = WINDOWBASE + 1 */ + ssr a2 /* sar = WINDOWBASE + 1 */ rsr a3, WINDOWSTART - srl a2, a3 /* a2 is 0... | 000000xxxxxxxxxx = WINDOWSTART >> sar */ - sll a3, a3 /* a3 is 1yyyyy0000000000 | 0... = WINDOWSTART << (32 - sar) */ - bgez a3, .Linvalid_ws /* verify that msbit is indeed set */ + srl a2, a3 /* a2 is 0... | 000000xxxxxxxxxx = WINDOWSTART >> sar */ + sll a3, a3 /* a3 is 1yyyyy0000000000 | 0... = WINDOWSTART << (32 - sar) */ + bgez a3, .Linvalid_ws /* verify that msbit is indeed set */ - srli a3, a3, 32-WSBITS /* a3 is 0... | 1yyyyy0000000000 = a3 >> (32-NAREG/4) */ + srli a3, a3, 32-WSBITS /* a3 is 0... | 1yyyyy0000000000 = a3 >> (32-NAREG/4) */ or a2, a2, a3 /* a2 is 0... | 1yyyyyxxxxxxxxxx */ /* FIND THE FIRST ONE @@ -165,28 +167,28 @@ _xtensa_window_spill: */ #if XCHAL_HAVE_NSA - neg a3, a2 /* Keep only the least-significant bit set of a2 ... */ - and a3, a3, a2 /* ... in a3 */ - nsau a3, a3 /* Get index of that bit, numbered from msbit (32 if absent) */ + neg a3, a2 /* Keep only the least-significant bit set of a2 ... */ + and a3, a3, a2 /* ... in a3 */ + nsau a3, a3 /* Get index of that bit, numbered from msbit (32 if absent) */ ssl a3 /* Set sar = 32 - a3 = bit index numbered from lsbit + 1 */ #else /* XCHAL_HAVE_NSA */ wsr a2, WINDOWSTART /* temporarily save rotated start bits - * (we can use WINDOWSTART because WOE=0) */ + * (we can use WINDOWSTART because WOE=0) */ /* NOTE: this could be optimized a bit, by explicit coding rather than the macro. */ - find_ls_one a3, a2 /* Set a3 to index of lsmost bit set in a2 (a2 clobbered) */ + find_ls_one a3, a2 /* Set a3 to index of lsmost bit set in a2 (a2 clobbered) */ - addi a2, a3, 1 /* Index+1 */ - ssr a2 /* Set sar = index + 1 */ - rsr a2, WINDOWSTART /* Restore a2 (rotated start bits) */ + addi a2, a3, 1 /* Index+1 */ + ssr a2 /* Set sar = index + 1 */ + rsr a2, WINDOWSTART /* Restore a2 (rotated start bits) */ #endif /* XCHAL_HAVE_NSA */ - srl a2, a2 /* Right-justify the rotated start bits (dropping lsbit set) */ - wsr a2, WINDOWSTART /* Save rotated + justified window start bits, - * because a2 will disappear when modifying WINDOWBASE - * again, we can use WINDOWSTART because WOE=0 */ + srl a2, a2 /* Right-justify the rotated start bits (dropping lsbit set) */ + wsr a2, WINDOWSTART /* Save rotated + justified window start bits, + * because a2 will disappear when modifying WINDOWBASE + * again, we can use WINDOWSTART because WOE=0 */ /* Rotate WindowBase so that a0 of the next window to spill is in a4 * (ie. leaving us with a2 and a3 to play with, because a0 and a1 @@ -202,12 +204,12 @@ _xtensa_window_spill: add a3, a2, a3 /* a3 = WINDOWBASE + index */ #endif /* XCHAL_HAVE_NSA */ - wsr a3, WINDOWBASE /* Effectively do: rotw index */ - rsync /* Wait for write to WINDOWBASE to complete */ + wsr a3, WINDOWBASE /* Effectively do: rotw index */ + rsync /* Wait for write to WINDOWBASE to complete */ /* Now our registers have changed! */ - rsr a2, WINDOWSTART /* Restore a2 (rotated + justified window start bits) */ + rsr a2, WINDOWSTART /* Restore a2 (rotated + justified window start bits) */ /* We are now ready to start the window spill loop. * Relative to the above, a2 and WINDOWBASE are now as follows: @@ -230,54 +232,53 @@ _xtensa_window_spill: /* Top of save loop. */ /* Find the size of this call and branch to the appropriate save routine. */ - beqz a2, .Ldone /* If no start bit remaining, we're done */ - bbsi.l a2, 0, .Lspill4 /* If next start bit is set, it's a call4 */ - bbsi.l a2, 1, .Lspill8 /* If 2nd next bit set, it's a call8 */ - bbsi.l a2, 2, .Lspill12 /* If 3rd next bit set, it's a call12 */ - j .Linvalid_window /* Else it's an invalid window! */ + beqz a2, .Ldone /* If no start bit remaining, we're done */ + bbsi.l a2, 0, .Lspill4 /* If next start bit is set, it's a call4 */ + bbsi.l a2, 1, .Lspill8 /* If 2nd next bit set, it's a call8 */ + bbsi.l a2, 2, .Lspill12 /* If 3rd next bit set, it's a call12 */ + j .Linvalid_window /* Else it's an invalid window! */ /* SAVE A CALL4 */ .Lspill4: - addi a3, a9, -16 /* a3 gets call[i+1]'s sp - 16 */ - s32i a4, a3, 0 /* Store call[i]'s a0 */ - s32i a5, a3, 4 /* Store call[i]'s a1 */ - s32i a6, a3, 8 /* Store call[i]'s a2 */ - s32i a7, a3, 12 /* Store call[i]'s a3 */ + addi a3, a9, -16 /* a3 gets call[i+1]'s sp - 16 */ + s32i a4, a3, 0 /* Store call[i]'s a0 */ + s32i a5, a3, 4 /* Store call[i]'s a1 */ + s32i a6, a3, 8 /* Store call[i]'s a2 */ + s32i a7, a3, 12 /* Store call[i]'s a3 */ - srli a6, a2, 1 /* Move and shift the start bits */ - rotw 1 /* Rotate the window */ + srli a6, a2, 1 /* Move and shift the start bits */ + rotw 1 /* Rotate the window */ j .Lspill_loop /* SAVE A CALL8 */ .Lspill8: - addi a3, a13, -16 /* a0 gets call[i+1]'s sp - 16 */ - s32i a4, a3, 0 /* Store call[i]'s a0 */ - s32i a5, a3, 4 /* Store call[i]'s a1 */ - s32i a6, a3, 8 /* Store call[i]'s a2 */ - s32i a7, a3, 12 /* Store call[i]'s a3 */ + addi a3, a13, -16 /* a0 gets call[i+1]'s sp - 16 */ + s32i a4, a3, 0 /* Store call[i]'s a0 */ + s32i a5, a3, 4 /* Store call[i]'s a1 */ + s32i a6, a3, 8 /* Store call[i]'s a2 */ + s32i a7, a3, 12 /* Store call[i]'s a3 */ - addi a3, a5, -12 /* Call[i-1]'s sp address */ - l32i a3, a3, 0 /* a3 is call[i-1]'s sp - * (load slot) */ - addi a3, a3, -32 /* a3 points to our spill area */ + addi a3, a5, -12 /* Call[i-1]'s sp address */ + l32i a3, a3, 0 /* a3 is call[i-1]'s sp (load slot) */ + addi a3, a3, -32 /* a3 points to our spill area */ - s32i a8, a3, 0 /* Store call[i]'s a4 */ - s32i a9, a3, 4 /* Store call[i]'s a5 */ - s32i a10, a3, 8 /* Store call[i]'s a6 */ - s32i a11, a3, 12 /* Store call[i]'s a7 */ + s32i a8, a3, 0 /* Store call[i]'s a4 */ + s32i a9, a3, 4 /* Store call[i]'s a5 */ + s32i a10, a3, 8 /* Store call[i]'s a6 */ + s32i a11, a3, 12 /* Store call[i]'s a7 */ - srli a10, a2, 2 /* Move and shift the start bits */ - rotw 2 /* Rotate the window */ + srli a10, a2, 2 /* Move and shift the start bits */ + rotw 2 /* Rotate the window */ j .Lspill_loop /* SAVE A CALL12 */ .Lspill12: - rotw 1 /* Rotate to see call[i+1]'s sp */ + rotw 1 /* Rotate to see call[i+1]'s sp */ addi a13, a13, -16 /* Set to the reg save area */ s32i a0, a13, 0 /* Store call[i]'s a0 */ @@ -286,41 +287,41 @@ _xtensa_window_spill: s32i a3, a13, 12 /* Store call[i]'s a3 */ addi a3, a1, -12 /* Call[i-1]'s sp address */ - l32i a3, a3, 0 /* a3 has call[i-1]'s sp */ + l32i a3, a3, 0 /* a3 has call[i-1]'s sp */ addi a13, a13, 16 /* Restore call[i+1]'s sp (here to fill load slot) */ addi a3, a3, -48 /* a3 points to our save area */ - s32i a4, a3, 0 /* Store call[i]'s a4 */ - s32i a5, a3, 4 /* Store call[i]'s a5 */ - s32i a6, a3, 8 /* Store call[i]'s a6 */ + s32i a4, a3, 0 /* Store call[i]'s a4 */ + s32i a5, a3, 4 /* Store call[i]'s a5 */ + s32i a6, a3, 8 /* Store call[i]'s a6 */ s32i a7, a3, 12 /* Store call[i]'s a7 */ s32i a8, a3, 16 /* Store call[i]'s a4 */ s32i a9, a3, 20 /* Store call[i]'s a5 */ s32i a10, a3, 24 /* Store call[i]'s a6 */ s32i a11, a3, 28 /* Store call[i]'s a7 */ - rotw -1 /* Rotate to see start bits (a2) */ + rotw -1 /* Rotate to see start bits (a2) */ srli a14, a2, 3 /* Move and shift the start bits */ - rotw 3 /* Rotate to next window */ + rotw 3 /* Rotate to next window */ j .Lspill_loop .Ldone: - rotw 1 /* Back to the original window */ - rsr a2, WINDOWBASE /* Get (original) window base */ - ssl a2 /* Setup for shift left by WINDOWBASE */ + rotw 1 /* Back to the original window */ + rsr a2, WINDOWBASE /* Get (original) window base */ + ssl a2 /* Setup for shift left by WINDOWBASE */ movi a2, 1 - sll a2, a2 /* Compute new WINDOWSTART = 1<4MiB external RAM" + default y + help + The ESP32 only supports 4MiB of external RAM in its address + space. The hardware does support larger memories, but these + have to be bank-switched in and out of this address space. + Enabling this allows you to reserve some MMU pages for this, + which allows the use of the esp_himem api to manage these + banks. + #Note that this is limited to 62 banks, as + #esp_spiram_writeback_cache needs some kind of mapping of + #some banks below that mark to work. We cannot at this + #moment guarantee this to exist when himem is enabled. + If spiram 2T mode is enabled, the size of 64Mbit psram will + be changed as 32Mbit, so himem will be unusable. + +config SPIRAM_BANKSWITCH_RESERVE + int "Amount of 32K pages to reserve for bank switching" + depends on ESP32_SPIRAM_BANKSWITCH_ENABLE + default 8 + range 1 62 + help + Select the amount of banks reserved for bank switching. Note + that the amount of RAM allocatable with malloc will decrease + by 32K for each page reserved here. + Note that this reservation is only actually done if your + program actually uses the himem API. Without any himem + calls, the reservation is not done and the original amount + of memory will be available. + endmenu #SPI RAM Config menu "Ethernet configuration" diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 5373f732d1f..c53ce20fee5 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -65,6 +65,10 @@ ifeq ($(CONFIG_DEBUG_ALERT),y) CMN_CSRCS += xtensa_dumpstate.c endif +ifeq ($(CONFIG_XTENSA_DUMPBT_ON_ASSERT),y) + CMN_ASRCS += xtensa_backtrace.S +endif + ifeq ($(CONFIG_SPINLOCK),y) CMN_CSRCS += xtensa_testset.c endif @@ -121,6 +125,7 @@ endif ifeq ($(CONFIG_ESP32_SPIRAM),y) CHIP_CSRCS += esp32_spiram.c CHIP_CSRCS += esp32_psram.c +CHIP_CSRCS += esp32_himem.c endif ifeq ($(CONFIG_ESP32_EMAC),y) @@ -164,7 +169,6 @@ CHIP_CSRCS += esp32_wtd.c endif endif - ifeq ($(CONFIG_ARCH_USE_MODULE_TEXT),y) CHIP_CSRCS += esp32_modtext.c CMN_ASRCS += xtensa_loadstore.S diff --git a/arch/xtensa/src/esp32/chip_memory.h b/arch/xtensa/src/esp32/chip_memory.h new file mode 100644 index 00000000000..6038a11356d --- /dev/null +++ b/arch/xtensa/src/esp32/chip_memory.h @@ -0,0 +1,68 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/chip_memory.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_MEMORY_H +#define __ARCH_XTENSA_SRC_ESP32_CHIP_MEMORY_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/esp32_soc.h" + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: xtensa_sp_sane + ****************************************************************************/ + +static inline bool xtensa_sp_sane(uint32_t sp) +{ + return (esp32_sp_dram(sp) && ((sp & 0x0f) == 0)); +} + +/**************************************************************************** + * Name: xtensa_ptr_extram + ****************************************************************************/ + +static inline bool xtensa_ptr_exec(const void *p) +{ + return esp32_ptr_exec(p); +} + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_SRC_ESP32_CHIP_MEMORY_H */ + diff --git a/arch/xtensa/src/esp32/esp32_gpio.c b/arch/xtensa/src/esp32/esp32_gpio.c index 09737c7f62a..cd1276bd216 100644 --- a/arch/xtensa/src/esp32/esp32_gpio.c +++ b/arch/xtensa/src/esp32/esp32_gpio.c @@ -357,7 +357,7 @@ void esp32_gpioirqenable(int irq, gpio_intrtype_t intrtype) #endif int pin; - DEBUGASSERT(irq <= ESP32_FIRST_GPIOIRQ && irq <= ESP32_LAST_GPIOIRQ); + DEBUGASSERT(irq >= ESP32_FIRST_GPIOIRQ && irq <= ESP32_LAST_GPIOIRQ); /* Convert the IRQ number to a pin number */ @@ -418,7 +418,7 @@ void esp32_gpioirqdisable(int irq) uint32_t regval; int pin; - DEBUGASSERT(irq <= ESP32_FIRST_GPIOIRQ && irq <= ESP32_LAST_GPIOIRQ); + DEBUGASSERT(irq >= ESP32_FIRST_GPIOIRQ && irq <= ESP32_LAST_GPIOIRQ); /* Convert the IRQ number to a pin number */ diff --git a/arch/xtensa/src/esp32/esp32_himem.c b/arch/xtensa/src/esp32/esp32_himem.c new file mode 100644 index 00000000000..c8c398a048a --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_himem.c @@ -0,0 +1,856 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_himem.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "esp32_spiram.h" +#include "esp32_himem.h" +#include "hardware/esp32_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* So, why does the API look this way and is so inflexible to not allow any + * maps beyond the full 32K chunks? Most of it has to do with the fact that + * the cache works on the *virtual* addresses What this comes down to is that + * while it's allowed to map a range of physical memory into the address + * space two times, there's no cache consistency between the two regions. + * + * This means that a write to region A may or may not show up, perhaps + * delayed, in region B, as it depends on the time that the writeback to SPI + * RAM is done on A and the time before the corresponding cache line is + * invalidated on B. Note that this goes for every 32-byte cache line: this + * implies that if a program writes to address X and Y within A, the write to + * Y may show up before the write to X does. + * + * It gets even worse when both A and B are written: theoretically, a write + * to a 32-byte cache line in A can be entirely undone because of a write to + * a different addres in B that happens to be in the same 32-byte cache line. + * + * Because of these reasons, we do not allow double mappings at all. This, + * however, has other implications that make supporting ranges not really + * useful. Because the lack of double mappings, applications will need to do + * their own management of mapped regions, meaning they will normally map in + * and out blocks at a time anyway, as mapping more fluent regions would + * result in the chance of accidentally mapping two overlapping regions. As + * this is the case, to keep the code simple, at the moment we just force + * these blocks to be equal to the 32K MMU page size. The API itself does + * allow for more granular allocations, so if there's a pressing need for a + * more complex solution in the future, we can do this. + * + * Note: In the future, we can expand on this api to do a memcpy() between + * SPI RAM and (internal) memory using the SPI1 peripheral. This needs + * support for SPI1 to be in the SPI driver, however. + */ + +/* How many 32KB pages will be reserved for bank switch */ + +#if CONFIG_ESP32_SPIRAM_BANKSWITCH_ENABLE +# define SPIRAM_BANKSWITCH_RESERVE CONFIG_SPIRAM_BANKSWITCH_RESERVE +#else +# define SPIRAM_BANKSWITCH_RESERVE 0 +#endif + +#define CACHE_BLOCKSIZE (32*1024) + +/* Start of the virtual address range reserved for himem use */ + +#define VIRT_HIMEM_RANGE_START (SOC_EXTRAM_DATA_LOW + \ + (128 - SPIRAM_BANKSWITCH_RESERVE) * \ + CACHE_BLOCKSIZE) + +/* Start MMU block reserved for himem use */ + +#define VIRT_HIMEM_RANGE_BLOCKSTART (128-SPIRAM_BANKSWITCH_RESERVE) + +/* Start physical block */ + +#define PHYS_HIMEM_BLOCKSTART (128 - SPIRAM_BANKSWITCH_RESERVE) + +#define HIMEM_CHECK(cond, str, err) if (cond) \ + do \ + { merr("%s: %s", __FUNCTION__, str); \ + return err; \ + } while(0) + +/* Character driver methods */ + +static int himem_open(FAR struct file *filep); +static int himem_close(FAR struct file *filep); +static ssize_t himem_read(FAR struct file *filep, FAR char *buffer, + size_t buflen); +static ssize_t himem_write(FAR struct file *filep, FAR const char *buffer, + size_t buflen); +static int himem_ioctl(FAR struct file *filep, int cmd, + unsigned long arg); + +/* This structure is used only for access control */ + +struct himem_access_s +{ + sem_t exclsem; /* Supports mutual exclusion */ +}; + +/* Metadata for a block of physical RAM */ + +typedef struct +{ + unsigned int is_alloced: 1; + unsigned int is_mapped: 1; +} ramblock_t; + +/* Metadata for a 32-K memory address range */ + +typedef struct +{ + unsigned int is_alloced: 1; + unsigned int is_mapped: 1; + unsigned int ram_block: 16; +} rangeblock_t; + +static ramblock_t *g_ram_descriptor = NULL; +static rangeblock_t *g_range_descriptor = NULL; +static int g_ramblockcnt = 0; +static const int g_rangeblockcnt = SPIRAM_BANKSWITCH_RESERVE; + +/* Used by the spinlock */ + +irqstate_t spinlock_flags; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct file_operations g_himemfops = +{ + himem_open, + himem_close, + himem_read, + himem_write, + NULL, + himem_ioctl, + NULL +}; + +/**************************************************************************** + * Private functions + ****************************************************************************/ + +static inline int ramblock_idx_valid(int ramblock_idx) +{ + return (ramblock_idx >= 0 && ramblock_idx < g_ramblockcnt); +} + +static inline int rangeblock_idx_valid(int rangeblock_idx) +{ + return (rangeblock_idx >= 0 && rangeblock_idx < g_rangeblockcnt); +} + +static void set_bank(int virt_bank, int phys_bank, int ct) +{ + int r; + + r = cache_sram_mmu_set(0, 0, SOC_EXTRAM_DATA_LOW + CACHE_BLOCKSIZE * + virt_bank, phys_bank * CACHE_BLOCKSIZE, 32, ct); + DEBUGASSERT(r == 0); + r = cache_sram_mmu_set(1, 0, SOC_EXTRAM_DATA_LOW + CACHE_BLOCKSIZE * + virt_bank, phys_bank * CACHE_BLOCKSIZE, 32, ct); + DEBUGASSERT(r == 0); + + UNUSED(r); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +size_t esp_himem_get_phys_size(void) +{ + int paddr_start = (4096 * 1024) - (CACHE_BLOCKSIZE * + SPIRAM_BANKSWITCH_RESERVE); + return esp_spiram_get_size() - paddr_start; +} + +size_t esp_himem_get_free_size(void) +{ + size_t ret = 0; + int i; + + for (i = 0; i < g_ramblockcnt; i++) + { + if (!g_ram_descriptor[i].is_alloced) + { + ret += CACHE_BLOCKSIZE; + } + } + + return ret; +} + +size_t esp_himem_reserved_area_size(void) +{ + return CACHE_BLOCKSIZE * SPIRAM_BANKSWITCH_RESERVE; +} + +int esp_himem_init(void) +{ + FAR struct himem_access_s *priv; + int paddr_start = (4096 * 1024) - (CACHE_BLOCKSIZE * + SPIRAM_BANKSWITCH_RESERVE); + int paddr_end; + int maxram; + int ret; + + if (SPIRAM_BANKSWITCH_RESERVE == 0) + { + return -ENODEV; + } + + /* Allocate a new himem access instance */ + + priv = (FAR struct himem_access_s *) + kmm_zalloc(sizeof(struct himem_access_s)); + + if (!priv) + { + merr("ERROR: Failed to allocate device structure\n"); + return -ENOMEM; + } + + maxram = esp_spiram_get_size(); + + /* Catch double init */ + + /* Looks weird; last arg is empty so it expands to 'return ;' */ + + HIMEM_CHECK(g_ram_descriptor != NULL, "already initialized", (int) NULL); + + HIMEM_CHECK(g_range_descriptor != NULL, "already initialized", (int) NULL); + + /* need to have some reserved banks */ + + HIMEM_CHECK(SPIRAM_BANKSWITCH_RESERVE == 0, "No banks reserved for \ + himem", (int) NULL); + + /* Start and end of physical reserved memory. Note it starts slightly under + * the 4MiB mark as the reserved banks can't have an unity mapping to be + * used by malloc anymore; we treat them as himem instead. + */ + + paddr_end = maxram; + g_ramblockcnt = ((paddr_end - paddr_start) / CACHE_BLOCKSIZE); + + /* Allocate data structures */ + + g_ram_descriptor = kmm_zalloc(sizeof(ramblock_t) * g_ramblockcnt); + g_range_descriptor = kmm_zalloc(sizeof(rangeblock_t) * \ + SPIRAM_BANKSWITCH_RESERVE); + + if (g_ram_descriptor == NULL || g_range_descriptor == NULL) + { + merr("Cannot allocate memory for meta info. Not initializing!"); + free(g_ram_descriptor); + free(g_range_descriptor); + return -ENOMEM; + } + + /* Register the character driver */ + + ret = register_driver("/dev/himem", &g_himemfops, 0666, priv); + if (ret < 0) + { + merr("ERROR: Failed to register driver: %d\n", ret); + kmm_free(priv); + } + + minfo("Initialized. Using last %d 32KB address blocks for bank \ + switching on %d KB of physical memory.\n", + SPIRAM_BANKSWITCH_RESERVE, (paddr_end - paddr_start) / 1024); + + return OK; +} + +/* Allocate count not-necessarily consecutive physical RAM blocks, return + * numbers in blocks[]. Return true if blocks can be allocated, false if not. + */ + +static bool allocate_blocks(int count, uint16_t *blocks_out) +{ + int n = 0; + int i; + + for (i = 0; i < g_ramblockcnt && n != count; i++) + { + if (!g_ram_descriptor[i].is_alloced) + { + blocks_out[n] = i; + n++; + } + } + + if (n == count) + { + /* All blocks could be allocated. Mark as in use. */ + + for (i = 0; i < count; i++) + { + g_ram_descriptor[blocks_out[i]].is_alloced = true; + DEBUGASSERT(g_ram_descriptor[blocks_out[i]].is_mapped == false); + } + + return true; + } + else + { + /* Error allocating blocks */ + + return false; + } +} + +int esp_himem_alloc(size_t size, esp_himem_handle_t *handle_out) +{ + esp_himem_ramdata_t *r; + int blocks; + int ok; + + /* If the size is not multiple of BLOCKSIZE, there is an issue */ + + if (size % CACHE_BLOCKSIZE != 0) + { + return -EINVAL; + } + + blocks = size / CACHE_BLOCKSIZE; + + r = kmm_malloc(sizeof(esp_himem_ramdata_t)); + if (!r) + { + goto nomem; + } + + r->block = kmm_malloc(sizeof(uint16_t) * blocks); + if (!r->block) + { + goto nomem; + } + + spinlock_flags = spin_lock_irqsave(); + + ok = allocate_blocks(blocks, r->block); + + spin_unlock_irqrestore(spinlock_flags); + if (!ok) + { + goto nomem; + } + + r->block_ct = blocks; + *handle_out = r; + + return OK; + +nomem: + if (r) + { + free(r->block); + free(r); + } + + return -ENOMEM; +} + +int esp_himem_free(esp_himem_handle_t handle) +{ + int i; + + /* Check if any of the blocks is still mapped; fail if this is the case. */ + + for (i = 0; i < handle->block_ct; i++) + { + DEBUGASSERT(ramblock_idx_valid(handle->block[i])); + HIMEM_CHECK(g_ram_descriptor[handle->block[i]].is_mapped, + "block in range still mapped", -EINVAL); + } + + /* Mark blocks as free */ + + spinlock_flags = spin_lock_irqsave(); + for (i = 0; i < handle->block_ct; i++) + { + g_ram_descriptor[handle->block[i]].is_alloced = false; + } + + spin_unlock_irqrestore(spinlock_flags); + + /* Free handle */ + + free(handle->block); + free(handle); + return OK; +} + +int esp_himem_alloc_map_range(size_t size, + esp_himem_rangehandle_t *handle_out) +{ + esp_himem_rangedata_t *r; + int i; + int blocks; + int start_free; + + HIMEM_CHECK(g_ram_descriptor == NULL, "Himem not available!", + -EINVAL); + + HIMEM_CHECK(size % CACHE_BLOCKSIZE != 0, + "requested size not aligned to blocksize", + -EINVAL); + + blocks = size / CACHE_BLOCKSIZE; + + r = kmm_malloc(sizeof(esp_himem_rangedata_t) * 1); + if (!r) + { + return -ENOMEM; + } + + r->block_ct = blocks; + r->block_start = -1; + + start_free = 0; + spinlock_flags = spin_lock_irqsave(); + + for (i = 0; i < g_rangeblockcnt; i++) + { + if (g_range_descriptor[i].is_alloced) + { + start_free = i + 1; /* optimistically assume next block is free... */ + } + else + { + if (i - start_free == blocks - 1) + { + /* We found a span of blocks that's big enough to allocate + * the requested range in. + */ + + r->block_start = start_free; + break; + } + } + } + + if (r->block_start == -1) + { + /* Couldn't find enough free blocks */ + + free(r); + spin_unlock_irqrestore(spinlock_flags); + return -ENOMEM; + } + + /* Range is found. Mark the blocks as in use. */ + + for (i = 0; i < blocks; i++) + { + g_range_descriptor[r->block_start + i].is_alloced = 1; + } + + spin_unlock_irqrestore(spinlock_flags); + + /* All done. */ + + *handle_out = r; + return OK; +} + +int esp_himem_free_map_range(esp_himem_rangehandle_t handle) +{ + int i; + + /* Check if any of the blocks in the range have a mapping */ + + for (i = 0; i < handle->block_ct; i++) + { + DEBUGASSERT(rangeblock_idx_valid(handle->block_start + i)); + + /* should be allocated, if handle is valid */ + + DEBUGASSERT(g_range_descriptor[i + \ + handle->block_start].is_alloced == 1); + + HIMEM_CHECK(g_range_descriptor[i + handle->block_start].is_mapped, + "memory still mapped to range", -EINVAL); + } + + /* We should be good to free this. Mark blocks as free. */ + + spinlock_flags = spin_lock_irqsave(); + + for (i = 0; i < handle->block_ct; i++) + { + g_range_descriptor[i + handle->block_start].is_alloced = 0; + } + + spin_unlock_irqrestore(spinlock_flags); + free(handle); + return OK; +} + +int esp_himem_map(esp_himem_handle_t handle, + esp_himem_rangehandle_t range, + size_t ram_offset, + size_t range_offset, + size_t len, + int flags, + void **out_ptr) +{ + int i; + int ram_block = ram_offset / CACHE_BLOCKSIZE; + int range_block = range_offset / CACHE_BLOCKSIZE; + int blockcount = len / CACHE_BLOCKSIZE; + + HIMEM_CHECK(g_ram_descriptor == NULL, "Himem not available!", + -EINVAL); + + /* Offsets and length must be block-aligned */ + + HIMEM_CHECK(ram_offset % CACHE_BLOCKSIZE != 0, + "ram offset not aligned to blocksize", -EINVAL); + + HIMEM_CHECK(range_offset % CACHE_BLOCKSIZE != 0, + "range not aligned to blocksize", -EINVAL); + + HIMEM_CHECK(len % CACHE_BLOCKSIZE != 0, + "length not aligned to blocksize", -EINVAL); + + /* ram and range should be within allocated range */ + + HIMEM_CHECK(ram_block + blockcount > handle->block_ct, + "args not in range of phys ram handle", -EINVAL); + + HIMEM_CHECK(range_block + blockcount > range->block_ct, + "args not in range of range handle", -EINVAL); + + /* Check if ram blocks aren't already mapped, and if memory range is + * unmapped. + */ + + for (i = 0; i < blockcount; i++) + { + HIMEM_CHECK(g_ram_descriptor[handle->block[i + ram_block]].is_mapped, + "ram already mapped", -EINVAL); + + HIMEM_CHECK(g_range_descriptor[range->block_start + i + + range_block].is_mapped, "range already mapped", + -EINVAL); + } + + /* Map and mark as mapped */ + + spinlock_flags = spin_lock_irqsave(); + + for (i = 0; i < blockcount; i++) + { + DEBUGASSERT(ramblock_idx_valid(handle->block[i + ram_block])); + g_ram_descriptor[handle->block[i + ram_block]].is_mapped = 1; + g_range_descriptor[range->block_start + i + range_block].is_mapped = 1; + g_range_descriptor[range->block_start + i + range_block].ram_block = + handle->block[i + ram_block]; + } + + spin_unlock_irqrestore(spinlock_flags); + + for (i = 0; i < blockcount; i++) + { + set_bank(VIRT_HIMEM_RANGE_BLOCKSTART + range->block_start + i + + range_block, handle->block[i + ram_block] + + PHYS_HIMEM_BLOCKSTART, 1); + } + + /* Set out pointer */ + + *out_ptr = (void *)(VIRT_HIMEM_RANGE_START + + (range->block_start + range_offset) * CACHE_BLOCKSIZE); + + return OK; +} + +int esp_himem_unmap(esp_himem_rangehandle_t range, void *ptr, + size_t len) +{ + /* Note: doesn't actually unmap, just clears cache and marks blocks as + * unmapped. + * Future optimization: could actually lazy-unmap here: essentially, do + * nothing and only clear the cache when we re-use the block for a + * different physical address. + */ + + int range_offset = (uint32_t)ptr - VIRT_HIMEM_RANGE_START; + int range_block = (range_offset / CACHE_BLOCKSIZE) - range->block_start; + int blockcount = len / CACHE_BLOCKSIZE; + int i; + + HIMEM_CHECK(range_offset % CACHE_BLOCKSIZE != 0, + "range offset not block-aligned", -EINVAL); + + HIMEM_CHECK(len % CACHE_BLOCKSIZE != 0, + "map length not block-aligned", -EINVAL); + + HIMEM_CHECK(range_block + blockcount > range->block_ct, + "range out of bounds for handle", -EINVAL); + + spinlock_flags = spin_lock_irqsave(); + + for (i = 0; i < blockcount; i++) + { + int ramblock = g_range_descriptor[range->block_start + i + + range_block].ram_block; + + DEBUGASSERT(ramblock_idx_valid(ramblock)); + g_ram_descriptor[ramblock].is_mapped = 0; + g_range_descriptor[range->block_start + i + range_block].is_mapped = 0; + } + + esp_spiram_writeback_cache(); + spin_unlock_irqrestore(spinlock_flags); + return OK; +} + +/**************************************************************************** + * Name: himem_open + * + * Description: + * This function is called whenever the LM-75 device is opened. + * + ****************************************************************************/ + +static int himem_open(FAR struct file *filep) +{ + return OK; +} + +/**************************************************************************** + * Name: himem_close + * + * Description: + * This routine is called when the LM-75 device is closed. + * + ****************************************************************************/ + +static int himem_close(FAR struct file *filep) +{ + return OK; +} + +/**************************************************************************** + * Name: himem_read + ****************************************************************************/ + +static ssize_t himem_read(FAR struct file *filep, FAR char *buffer, + size_t buflen) +{ + return -ENOSYS; +} + +/**************************************************************************** + * Name: himem_write + ****************************************************************************/ + +static ssize_t himem_write(FAR struct file *filep, FAR const char *buffer, + size_t buflen) +{ + return -ENOSYS; +} + +/**************************************************************************** + * Name: himem_ioctl + ****************************************************************************/ + +static int himem_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +{ + int ret = OK; + + switch (cmd) + { + /* Allocate the physical RAM blocks */ + + case HIMEMIOC_ALLOC_BLOCKS: + { + FAR struct esp_himem_par *param = + (FAR struct esp_himem_par *)((uintptr_t)arg); + + DEBUGASSERT(param != NULL); + + /* Allocate the memory we're going to check. */ + + ret = esp_himem_alloc(param->memfree, &(param->handle)); + if (ret < 0) + { + minfo("Error: esp_himem_alloc() failed!\n"); + return ret; + } + } + break; + + /* Free the physical RAM blocks */ + + case HIMEMIOC_FREE_BLOCKS: + { + FAR struct esp_himem_par *param = + (FAR struct esp_himem_par *)((uintptr_t)arg); + + DEBUGASSERT(param != NULL); + + ret = esp_himem_free(param->handle); + if (ret < 0) + { + minfo("Error: esp_himem_free() failed!\n"); + return ret; + } + } + break; + + /* Allocate the maping range */ + + case HIMEMIOC_ALLOC_MAP_RANGE: + { + FAR struct esp_himem_par *param = + (FAR struct esp_himem_par *)((uintptr_t)arg); + + DEBUGASSERT(param != NULL); + + /* Allocate a block of address range */ + + ret = esp_himem_alloc_map_range(ESP_HIMEM_BLKSZ, &(param->range)); + if (ret < 0) + { + minfo("Error: esp_himem_alloc_map_range() failed!\n"); + return ret; + } + } + break; + + /* Free the maping range */ + + case HIMEMIOC_FREE_MAP_RANGE: + { + FAR struct esp_himem_par *param = + (FAR struct esp_himem_par *)((uintptr_t)arg); + + DEBUGASSERT(param != NULL); + + ret = esp_himem_free_map_range(param->range); + if (ret < 0) + { + minfo("Error: esp_himem_free_map_range() failed!\n"); + return ret; + } + } + break; + + /* Map the himem blocks */ + + case HIMEMIOC_MAP: + { + FAR struct esp_himem_par *param = + (FAR struct esp_himem_par *)((uintptr_t)arg); + + DEBUGASSERT(param != NULL); + + ret = esp_himem_map(param->handle, + param->range, + param->ram_offset, + param->range_offset, + param->len, + param->flags, + (void **) &(param->ptr)); + if (ret < 0) + { + minfo("error: esp_himem_map() failed!\n"); + return ret; + } + } + break; + + /* Unmap the himem blocks */ + + case HIMEMIOC_UNMAP: + { + FAR struct esp_himem_par *param = + (FAR struct esp_himem_par *)((uintptr_t)arg); + + DEBUGASSERT(param != NULL); + + ret = esp_himem_unmap(param->range, + (void *) param->ptr, + param->len); + if (ret < 0) + { + minfo("error: esp_himem_unmap() failed!\n"); + return ret; + } + } + break; + + /* Get the physical external memory size */ + + case HIMEMIOC_GET_PHYS_SIZE: + { + FAR struct esp_himem_par *param = + (FAR struct esp_himem_par *)((uintptr_t)arg); + + DEBUGASSERT(param != NULL); + + param->memcnt = esp_himem_get_phys_size(); + } + break; + + /* Get the free memory size */ + + case HIMEMIOC_GET_FREE_SIZE: + { + FAR struct esp_himem_par *param = + (FAR struct esp_himem_par *)((uintptr_t)arg); + + DEBUGASSERT(param != NULL); + + param->memfree = esp_himem_get_free_size(); + } + break; + + default: + { + sninfo("Unrecognized cmd: %d\n", cmd); + ret = -ENOTTY; + } + break; + } + + return ret; +} + diff --git a/arch/xtensa/src/esp32/esp32_himem.h b/arch/xtensa/src/esp32/esp32_himem.h new file mode 100644 index 00000000000..99526a8c12e --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_himem.h @@ -0,0 +1,193 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_himem.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_HIMEM_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_HIMEM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Indicates that a mapping will only be read from. Note that this is unused + * for now. + */ + +#define ESP_HIMEM_MAPFLAG_RO 1 + +/* Allocate a block in high memory + * + * params: + * size Size of the to-be-allocated block, in bytes. Note that this + * needs to be a multiple of the external RAM mmu block size + * (32K). + * [out] handle_out Handle to be returned + * + * returns: + * - ESP_OK if succesful + * - ESP_ERR_NO_MEM if out of memory + * - ESP_ERR_INVALID_SIZE if size is not a multiple of 32K + */ + +int esp_himem_alloc(size_t size, esp_himem_handle_t *handle_out); + +/* Description: Allocate a memory region to map blocks into + * + * This allocates a contiguous CPU memory region that can be used to map + * blocks of physical memory into. + * + * params: + * size Size of the range to be allocated. Note this needs to be a multiple + * of the external RAM mmu block size (32K). + * [out] handle_out Handle to be returned + * + * returns: + * - ESP_OK if succesful + * - ESP_ERR_NO_MEM if out of memory or address space + * - ESP_ERR_INVALID_SIZE if size is not a multiple of 32K + */ + +int esp_himem_alloc_map_range(size_t size, esp_himem_rangehandle_t + *handle_out); + +/* Description: Map a block of high memory into the CPUs address space + * + * This effectively makes the block available for read/write operations. + * + * Note: The region to be mapped needs to have offsets and sizes that are + * aligned to the SPI RAM MMU block size (32K) + * + * params: + * handle Handle to the block of memory, as given by esp_himem_alloc + * range Range handle to map the memory in + * ram_offset Offset into the block of physical memory of the block to + * map + * range_offset Offset into the address range where the block will be + * mapped, + * len Length of region to map + * flags One of ESP_HIMEM_MAPFLAG_* + * [out] out_ptr Pointer to variable to store resulting memory pointer in + * + * returns: + * - ESP_OK if the memory could be mapped + * - ESP_ERR_INVALID_ARG if offset, range or len aren't MMU-block-aligned + * (32K) + * - ESP_ERR_INVALID_SIZE if the offsets/lengths don't fit in the allocated + * memory or range + * - ESP_ERR_INVALID_STATE if a block in the selected ram offset/length is + * already mapped, or if a block in the selected range offset/length + * already has a mapping. + */ + +int esp_himem_map(esp_himem_handle_t handle, + esp_himem_rangehandle_t range, + size_t ram_offset, + size_t range_offset, + size_t len, + int flags, + void **out_ptr); + +/* Description: Free a block of physical memory + * + * This clears out the associated handle making the memory available for + * re-allocation again. + * This will only succeed if none of the memory blocks currently have a + * mapping. + * + * params: + * handle Handle to the block of memory, as given by esp_himem_alloc + * + * returns: + * - ESP_OK if the memory is succesfully freed + * - ESP_ERR_INVALID_ARG if the handle still is (partially) mapped + */ + +int esp_himem_free(esp_himem_handle_t handle); + +/* Description: Free a mapping range + * + * This clears out the associated handle making the range available for + * re-allocation again. + * This will only succeed if none of the range blocks currently are used for + * a mapping. + * + * params: + * handle Handle to the range block, as given by esp_himem_alloc_map_range + * + * returns: + * - ESP_OK if the memory is succesfully freed + * - ESP_ERR_INVALID_ARG if the handle still is (partially) mapped to + */ + +int esp_himem_free_map_range(esp_himem_rangehandle_t handle); + +/* Description: Unmap a region + * + * params: + * range Range handle + * ptr Pointer returned by esp_himem_map + * len Length of the block to be unmapped. Must be aligned to the SPI RAM + * MMU blocksize (32K) + * returns: + * - ESP_OK if the memory is succesfully unmapped, + * - ESP_ERR_INVALID_ARG if ptr or len are invalid. + */ + +int esp_himem_unmap(esp_himem_rangehandle_t range, void *ptr, + size_t len); + +/* Description: Get total amount of memory under control of himem API + * + * returns: + * Amount of memory, in bytes + */ + +size_t esp_himem_get_phys_size(void); + +/* Description: Get free amount of memory under control of himem API + * + * returns: + * Amount of free memory, in bytes + */ + +size_t esp_himem_get_free_size(void); + +/* Description: Get amount of SPI memory address space needed for + * bankswitching + * + * Note: This is also weakly defined in esp32/spiram.c and returns 0 there, + * so if no other function in this file is used, no memory is reserved. + * + * return: + * Amount of reserved area, in bytes + */ + +size_t esp_himem_reserved_area_size(void); + +#ifdef __cplusplus +} +#endif +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_HIMEM_H */ diff --git a/arch/xtensa/src/esp32/esp32_spi.c b/arch/xtensa/src/esp32/esp32_spi.c index 494f1d11868..1f67784ae0a 100644 --- a/arch/xtensa/src/esp32/esp32_spi.c +++ b/arch/xtensa/src/esp32/esp32_spi.c @@ -27,6 +27,7 @@ #ifdef CONFIG_ESP32_SPI #include +#include #include #include #include @@ -586,7 +587,8 @@ static void esp32_spi_select(FAR struct spi_dev_s *dev, esp32_gpiowrite(priv->config->cs_pin, value); #endif - spiinfo("devid: %08lx CS: %s\n", devid, selected ? "select" : "free"); + spiinfo("devid: %08" PRIx32 " CS: %s\n", + devid, selected ? "select" : "free"); } #endif diff --git a/arch/xtensa/src/esp32/esp32_spiflash.c b/arch/xtensa/src/esp32/esp32_spiflash.c index eb077c75791..95611b569f5 100644 --- a/arch/xtensa/src/esp32/esp32_spiflash.c +++ b/arch/xtensa/src/esp32/esp32_spiflash.c @@ -53,6 +53,14 @@ #define SPI_FLASH_WRITE_BUF_SIZE (32) #define SPI_FLASH_READ_BUF_SIZE (64) +#define SPI_FLASH_WRITE_WORDS (SPI_FLASH_WRITE_BUF_SIZE / 4) +#define SPI_FLASH_READ_WORDS (SPI_FLASH_READ_BUF_SIZE / 4) + +#define SPI_FLASH_MAP_PAGE_SIZE (0x10000) + +#define SPI_FLASH_ENCRYPT_UNIT_SIZE (32) +#define SPI_FLASH_ENCRYPT_WORDS (32 / 4) + #define ESP32_MTD_OFFSET CONFIG_ESP32_MTD_OFFSET #define ESP32_MTD_SIZE CONFIG_ESP32_MTD_SIZE @@ -63,10 +71,26 @@ #define MTD_BLK2SIZE(_priv, _b) (MTD_BLKSIZE(_priv) * (_b)) #define MTD_SIZE2BLK(_priv, _s) ((_s) / MTD_BLKSIZE(_priv)) +#define MMU_ADDR2PAGE(_addr) ((_addr) / SPI_FLASH_MAP_PAGE_SIZE) +#define MMU_ADDR2OFF(_addr) ((_addr) % SPI_FLASH_MAP_PAGE_SIZE) +#define MMU_BYTES2PAGES(_n) (((_n) + SPI_FLASH_MAP_PAGE_SIZE - 1) \ + / SPI_FLASH_MAP_PAGE_SIZE) + #ifndef MIN # define MIN(a, b) (((a) < (b)) ? (a) : (b)) #endif +#define DPORT_INTERRUPT_DISABLE() +#define DPORT_INTERRUPT_RESTORE() + +/* Flash MMU table for PRO CPU */ + +#define PRO_MMU_TABLE ((volatile uint32_t *)DPORT_PRO_FLASH_MMU_TABLE_REG) + +/* Flash MMU table for APP CPU */ + +#define APP_MMU_TABLE ((volatile uint32_t *)DPORT_APP_FLASH_MMU_TABLE_REG) + /**************************************************************************** * Private Types ****************************************************************************/ @@ -99,6 +123,31 @@ struct esp32_spiflash_s uint8_t *dummies; }; +/* SPI Flash map request data */ + +struct spiflash_map_req +{ + /* Request mapping SPI Flash base address */ + + uint32_t src_addr; + + /* Request mapping SPI Flash size */ + + uint32_t size; + + /* Mapped memory pointer */ + + void *ptr; + + /* Mapped started MMU page index */ + + uint32_t start_page; + + /* Mapped MMU page count */ + + uint32_t page_cnt; +}; + /**************************************************************************** * ROM function prototypes ****************************************************************************/ @@ -121,7 +170,6 @@ static inline void spi_set_regbits(struct esp32_spiflash_s *priv, int offset, uint32_t bits); static inline void spi_reset_regbits(struct esp32_spiflash_s *priv, int offset, uint32_t bits); -static inline void IRAM_ATTR spi_memcpy(void *d, const void *s, uint32_t n); /* Misc. helpers */ @@ -161,12 +209,24 @@ static int esp32_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks); static ssize_t esp32_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, FAR uint8_t *buffer); +static ssize_t esp32_read_decrypt(FAR struct mtd_dev_s *dev, + off_t offset, + size_t nbytes, + FAR uint8_t *buffer); static ssize_t esp32_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks, FAR uint8_t *buffer); +static ssize_t esp32_bread_decrypt(FAR struct mtd_dev_s *dev, + off_t startblock, + size_t nblocks, + FAR uint8_t *buffer); static ssize_t esp32_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, FAR const uint8_t *buffer); static ssize_t esp32_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks, FAR const uint8_t *buffer); +static ssize_t esp32_bwrite_encrypt(FAR struct mtd_dev_s *dev, + off_t startblock, + size_t nblocks, + FAR const uint8_t *buffer); static int esp32_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg); @@ -198,7 +258,26 @@ static struct esp32_spiflash_s g_esp32_spiflash1 = .dummies = g_rom_spiflash_dummy_len_plus }; -/* Ensure exclusive access to the driver */ +static struct esp32_spiflash_s g_esp32_spiflash1_encrypt = +{ + .mtd = + { + .erase = esp32_erase, + .bread = esp32_bread_decrypt, + .bwrite = esp32_bwrite_encrypt, + .read = esp32_read_decrypt, + .ioctl = esp32_ioctl, +#ifdef CONFIG_MTD_BYTE_WRITE + .write = NULL, +#endif + .name = "esp32_mainflash_encrypt" + }, + .config = &g_esp32_spiflash1_config, + .chip = &g_rom_flashchip, + .dummies = g_rom_spiflash_dummy_len_plus +}; + +/* Enxusre exculisve access to the driver */ static sem_t g_exclsem = SEM_INITIALIZER(1); @@ -297,35 +376,6 @@ static inline void spi_reset_regbits(struct esp32_spiflash_s *priv, putreg32(tmp & (~bits), priv->config->reg_base + offset); } -/**************************************************************************** - * Name: spi_memcpy - * - * Description: - * Copy data from one block of memory to another block of memory. - * The function must be linked in IRAM not in flash, so add this function - * instead of libc memcpy. - * - * Input Parameters: - * d - destination address - * s - source address - * n - data bytes - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void IRAM_ATTR spi_memcpy(void *d, const void *s, uint32_t n) -{ - uint8_t *dest = (uint8_t *)d; - const uint8_t *src = (const uint8_t *)s; - - while (n--) - { - *dest++ = *src++; - } -} - /**************************************************************************** * Name: esp32_spiflash_opstart * @@ -719,7 +769,7 @@ static int esp32_write_status(FAR struct esp32_spiflash_s *priv, * ****************************************************************************/ -static int esp32_enable_write(FAR struct esp32_spiflash_s *priv) +static int IRAM_ATTR esp32_enable_write(FAR struct esp32_spiflash_s *priv) { uint32_t flags; uint32_t regval; @@ -772,6 +822,8 @@ static int IRAM_ATTR esp32_erasesector(FAR struct esp32_spiflash_s *priv, int me; uint32_t flags; + esp32_set_write_opt(priv); + if (esp32_wait_idle(priv) != OK) { return -EIO; @@ -806,6 +858,78 @@ static int IRAM_ATTR esp32_erasesector(FAR struct esp32_spiflash_s *priv, return 0; } +/**************************************************************************** + * Name: esp32_writeonce + * + * Description: + * Write max 32 byte data to SPI Flash at designated address. + * + * ESP32 can write max 32 byte once transmission by hardware. + * + * Input Parameters: + * spi - ESP32 SPI Flash chip data + * addr - target address + * buffer - data buffer pointer + * size - data number by bytes + * + * Returned Value: + * 0 if success or a negative value if fail. + * + ****************************************************************************/ + +static int IRAM_ATTR esp32_writeonce(FAR struct esp32_spiflash_s *priv, + uint32_t addr, + const uint32_t *buffer, + uint32_t size) +{ + uint32_t regval; + uint32_t i; + + if (size > SPI_FLASH_WRITE_BUF_SIZE) + { + return -EINVAL; + } + + if (esp32_wait_idle(priv) != OK) + { + return -EIO; + } + + if (esp32_enable_write(priv) != OK) + { + return -EIO; + } + + regval = addr & 0xffffff; + regval |= size << ESP_ROM_SPIFLASH_BYTES_LEN; + spi_set_reg(priv, SPI_ADDR_OFFSET, regval); + + for (i = 0; i < (size / 4); i++) + { + spi_set_reg(priv, SPI_W0_OFFSET + i * 4, buffer[i]); + } + + if (size & 0x3) + { + memcpy(®val, &buffer[i], size & 0x3); + spi_set_reg(priv, SPI_W0_OFFSET + i * 4, regval); + } + + spi_set_reg(priv, SPI_RD_STATUS_OFFSET, 0); + spi_set_reg(priv, SPI_CMD_OFFSET, SPI_FLASH_PP); + while (spi_get_reg(priv, SPI_CMD_OFFSET) != 0) + { + ; + } + + if (esp32_wait_idle(priv) != OK) + { + return -EIO; + } + + return OK; +} + /**************************************************************************** * Name: esp32_writedata * @@ -823,34 +947,22 @@ static int IRAM_ATTR esp32_erasesector(FAR struct esp32_spiflash_s *priv, * ****************************************************************************/ -static int esp32_writedata(FAR struct esp32_spiflash_s *priv, uint32_t addr, - const uint8_t *buffer, uint32_t size) +static int IRAM_ATTR esp32_writedata(FAR struct esp32_spiflash_s *priv, + uint32_t addr, + const uint8_t *buffer, + uint32_t size) { - uint32_t regval; - uint32_t i; - uint32_t bytes; - uint32_t tmp; - uint32_t res; - const uint8_t *tmpbuff = buffer; - int ret = OK; + int ret; int me; uint32_t flags; + uint32_t off = 0; + uint32_t bytes; + uint32_t tmp_buf[SPI_FLASH_WRITE_WORDS]; - if (esp32_wait_idle(priv) != OK) - { - return -EIO; - } + esp32_set_write_opt(priv); while (size > 0) { - flags = esp32_spiflash_opstart(priv, &me); - - if (esp32_enable_write(priv) != OK) - { - esp32_spiflash_opdone(priv, flags, me); - return -EIO; - } - bytes = MTD_BLKSIZE(priv) - addr % MTD_BLKSIZE(priv) ; if (!bytes) { @@ -862,41 +974,175 @@ static int esp32_writedata(FAR struct esp32_spiflash_s *priv, uint32_t addr, bytes = MIN(bytes, SPI_FLASH_WRITE_BUF_SIZE); } - regval = addr & 0xffffff; - regval |= bytes << ESP_ROM_SPIFLASH_BYTES_LEN; - spi_set_reg(priv, SPI_ADDR_OFFSET, regval); + memcpy(tmp_buf, &buffer[off], bytes); - for (i = 0; i < bytes; i += 4) + flags = esp32_spiflash_opstart(priv, &me); + ret = esp32_writeonce(priv, addr, tmp_buf, bytes); + esp32_spiflash_opdone(priv, flags, me); + + if (ret) { - res = MIN(4, bytes - i); - - spi_memcpy(&tmp, tmpbuff, res); - spi_set_reg(priv, SPI_W0_OFFSET + i, tmp); - tmpbuff += res; - } - - spi_set_reg(priv, SPI_RD_STATUS_OFFSET, 0); - spi_set_reg(priv, SPI_CMD_OFFSET, SPI_FLASH_PP); - while (spi_get_reg(priv, SPI_CMD_OFFSET) != 0) - { - ; - } - - if (esp32_wait_idle(priv) != OK) - { - esp32_spiflash_opdone(priv, flags, me); - return -EIO; + return ret; } addr += bytes; size -= bytes; - - esp32_spiflash_opdone(priv, flags, me); + off += bytes; } + return OK; +} + +/**************************************************************************** + * Name: esp32_writedata + * + * Description: + * Write plaintext data to SPI Flash at designated address by SPI Flash + * hardware encryption, and written data in SPI Flash is ciphertext. + * + * Input Parameters: + * spi - ESP32 SPI Flash chip data + * addr - target address + * buffer - data buffer pointer + * size - data number + * + * Returned Value: + * 0 if success or a negative value if fail. + * + ****************************************************************************/ + +static int IRAM_ATTR esp32_writedata_encrypted( + FAR struct esp32_spiflash_s *priv, + uint32_t addr, + const uint8_t *buffer, + uint32_t size) +{ + int i; + int blocks; + int ret = OK; + int me; + uint32_t flags; + uint32_t tmp_buf[SPI_FLASH_ENCRYPT_WORDS]; + + if (addr % SPI_FLASH_ENCRYPT_UNIT_SIZE) + { + ferr("ERROR: address=0x%x is not %d-byte align\n", + addr, SPI_FLASH_ENCRYPT_UNIT_SIZE); + return -EINVAL; + } + + if (size % SPI_FLASH_ENCRYPT_UNIT_SIZE) + { + ferr("ERROR: size=%u is not %d-byte align\n", + size, SPI_FLASH_ENCRYPT_UNIT_SIZE); + return -EINVAL; + } + + blocks = size / SPI_FLASH_ENCRYPT_UNIT_SIZE; + + for (i = 0; i < blocks; i++) + { + memcpy(tmp_buf, buffer, SPI_FLASH_ENCRYPT_UNIT_SIZE); + + flags = esp32_spiflash_opstart(priv, &me); + esp_rom_spiflash_write_encrypted_enable(); + + ret = esp_rom_spiflash_prepare_encrypted_data(addr, tmp_buf); + if (ret) + { + ferr("ERROR: Failed to prepare encrypted data\n"); + goto exit; + } + + ret = esp32_writeonce(priv, addr, tmp_buf, + SPI_FLASH_ENCRYPT_UNIT_SIZE); + if (ret) + { + ferr("ERROR: Failed to write encrypted data @ 0x%x\n", addr); + goto exit; + } + + esp_rom_spiflash_write_encrypted_disable(); + esp32_spiflash_opdone(priv, flags, me); + + addr += SPI_FLASH_ENCRYPT_UNIT_SIZE; + buffer += SPI_FLASH_ENCRYPT_UNIT_SIZE; + size -= SPI_FLASH_ENCRYPT_UNIT_SIZE; + } + + return 0; + +exit: + esp_rom_spiflash_write_encrypted_disable(); + esp32_spiflash_opdone(priv, flags, me); + return ret; } +/**************************************************************************** + * Name: esp32_readdata + * + * Description: + * Read max 64 byte data data from SPI Flash at designated address. + * + * ESP32 can read max 64 byte once transmission by hardware. + * + * Input Parameters: + * spi - ESP32 SPI Flash chip data + * addr - target address + * buffer - data buffer pointer + * size - data number by bytes + * + * Returned Value: + * OK if success or a negative value if fail. + * + ****************************************************************************/ + +static int IRAM_ATTR esp32_readonce(FAR struct esp32_spiflash_s *priv, + uint32_t addr, + uint32_t *buffer, + uint32_t size) +{ + uint32_t regval; + uint32_t i; + + if (size > SPI_FLASH_READ_BUF_SIZE) + { + return -EINVAL; + } + + if (esp32_wait_idle(priv) != OK) + { + return -EIO; + } + + regval = ((size << 3) - 1) << SPI_USR_MISO_DBITLEN_S; + spi_set_reg(priv, SPI_MISO_DLEN_OFFSET, regval); + + regval = addr << 8; + spi_set_reg(priv, SPI_ADDR_OFFSET, regval); + + spi_set_reg(priv, SPI_RD_STATUS_OFFSET, 0); + spi_set_reg(priv, SPI_CMD_OFFSET, SPI_USR); + while (spi_get_reg(priv, SPI_CMD_OFFSET) != 0) + { + ; + } + + for (i = 0; i < (size / 4); i++) + { + buffer[i] = spi_get_reg(priv, SPI_W0_OFFSET + i * 4); + } + + if (size & 0x3) + { + regval = spi_get_reg(priv, SPI_W0_OFFSET + i * 4); + memcpy(&buffer[i], ®val, size & 0x3); + } + + return OK; +} + /**************************************************************************** * Name: esp32_readdata * @@ -914,59 +1160,197 @@ static int esp32_writedata(FAR struct esp32_spiflash_s *priv, uint32_t addr, * ****************************************************************************/ -static int esp32_readdata(FAR struct esp32_spiflash_s *priv, uint32_t addr, - uint8_t *buffer, uint32_t size) +static int IRAM_ATTR esp32_readdata(FAR struct esp32_spiflash_s *priv, + uint32_t addr, + uint8_t *buffer, + uint32_t size) { - uint32_t regval; - uint32_t i; - uint32_t bytes; - uint32_t tmp; - uint32_t res; - uint8_t *tmpbuff = buffer; + int ret; int me; uint32_t flags; - - if (esp32_wait_idle(priv) != OK) - { - return -EIO; - } + uint32_t off = 0; + uint32_t bytes; + uint32_t tmp_buf[SPI_FLASH_READ_WORDS]; while (size > 0) { - flags = esp32_spiflash_opstart(priv, &me); - bytes = MIN(size, SPI_FLASH_READ_BUF_SIZE); - regval = ((bytes << 3) - 1) << SPI_USR_MISO_DBITLEN_S; - spi_set_reg(priv, SPI_MISO_DLEN_OFFSET, regval); - regval = addr << 8; - spi_set_reg(priv, SPI_ADDR_OFFSET, regval); + flags = esp32_spiflash_opstart(priv, &me); + ret = esp32_readonce(priv, addr, tmp_buf, bytes); + esp32_spiflash_opdone(priv, flags, me); - spi_set_reg(priv, SPI_RD_STATUS_OFFSET, 0); - spi_set_reg(priv, SPI_CMD_OFFSET, SPI_USR); - while (spi_get_reg(priv, SPI_CMD_OFFSET) != 0) + if (ret) { - ; + return ret; } - for (i = 0; i < bytes; i += 4) - { - res = MIN(4, bytes - i); - - tmp = spi_get_reg(priv, SPI_W0_OFFSET + i); - spi_memcpy(tmpbuff, &tmp, res); - tmpbuff += res; - } + memcpy(&buffer[off], tmp_buf, bytes); addr += bytes; size -= bytes; - - esp32_spiflash_opdone(priv, flags, me); + off += bytes; } return OK; } +/**************************************************************************** + * Name: esp32_mmap + * + * Description: + * Mapped SPI Flash address to ESP32's address bus, so that software + * can read SPI Flash data by reading data from memory access. + * + * If SPI Flash hardware encryption is enable, the read from mapped + * address is decrypted. + * + * Input Parameters: + * spi - ESP32 SPI Flash chip data + * req - SPI Flash mapping requesting parameters + * + * Returned Value: + * 0 if success or a negative value if fail. + * + ****************************************************************************/ + +static int IRAM_ATTR esp32_mmap(FAR struct esp32_spiflash_s *priv, + struct spiflash_map_req *req) +{ + int ret; + int i; + int me; + int start_page; + int flash_page; + int page_cnt; + uint32_t flags; + + flags = esp32_spiflash_opstart(priv, &me); + + for (start_page = DROM0_PAGES_START; + start_page < DROM0_PAGES_END; + ++start_page) + { + if (PRO_MMU_TABLE[start_page] == INVALID_MMU_VAL +#ifdef CONFIG_SMP + && APP_MMU_TABLE[start_page] == INVALID_MMU_VAL +#endif + ) + { + break; + } + } + + flash_page = MMU_ADDR2PAGE(req->src_addr); + page_cnt = MMU_BYTES2PAGES(req->size); + + if (start_page + page_cnt < DROM0_PAGES_END) + { + for (i = 0; i < page_cnt; i++) + { + PRO_MMU_TABLE[start_page + i] = flash_page + i; +#ifdef CONFIG_SMP + APP_MMU_TABLE[start_page + i] = flash_page + i; +#endif + } + + req->start_page = start_page; + req->page_cnt = page_cnt; + req->ptr = (void *)(VADDR0_START_ADDR + + start_page * SPI_FLASH_MAP_PAGE_SIZE + + MMU_ADDR2OFF(req->src_addr)); + + ret = 0; + } + else + { + ret = -ENOBUFS; + } + + esp32_spiflash_opdone(priv, flags, me); + + return ret; +} + +/**************************************************************************** + * Name: esp32_ummap + * + * Description: + * Unmap SPI Flash address in ESP32's address bus, and free resource. + * + * Input Parameters: + * spi - ESP32 SPI Flash chip data + * req - SPI Flash mapping requesting paramters + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void IRAM_ATTR esp32_ummap(FAR struct esp32_spiflash_s *priv, + const struct spiflash_map_req *req) +{ + uint32_t flags; + int me; + int i; + + flags = esp32_spiflash_opstart(priv, &me); + + for (i = req->start_page; i < req->start_page + req->page_cnt; ++i) + { + PRO_MMU_TABLE[i] = INVALID_MMU_VAL; +#ifdef CONFIG_SMP + APP_MMU_TABLE[i] = INVALID_MMU_VAL; +#endif + } + + esp32_spiflash_opdone(priv, flags, me); +} + +/**************************************************************************** + * Name: esp32_readdata_encrypted + * + * Description: + * Read decrypted data from SPI Flash at designated address when + * enable SPI Flash hardware encryption. + * + * Input Parameters: + * spi - ESP32 SPI Flash chip data + * addr - target address + * buffer - data buffer pointer + * size - data number + * + * Returned Value: + * OK if success or a negative value if fail. + * + ****************************************************************************/ + +static int IRAM_ATTR esp32_readdata_encrypted( + FAR struct esp32_spiflash_s *priv, + uint32_t addr, + uint8_t *buffer, + uint32_t size) +{ + int ret; + struct spiflash_map_req req = + { + .src_addr = addr, + .size = size + }; + + ret = esp32_mmap(priv, &req); + if (ret) + { + return ret; + } + + memcpy(buffer, req.ptr, size); + + esp32_ummap(priv, &req); + + return OK; +} + /**************************************************************************** * Name: esp32_erase * @@ -1006,7 +1390,6 @@ static int esp32_erase(FAR struct mtd_dev_s *dev, off_t startblock, return ret; } - esp32_set_write_opt(priv); ret = esp32_erasesector(priv, addr, size); nxsem_post(&g_exclsem); @@ -1044,24 +1427,12 @@ static ssize_t esp32_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, FAR uint8_t *buffer) { int ret; - uint8_t *tmpbuff = buffer; FAR struct esp32_spiflash_s *priv = MTD2PRIV(dev); #ifdef CONFIG_ESP32_SPIFLASH_DEBUG finfo("esp32_read(%p, 0x%x, %d, %p)\n", dev, offset, nbytes, buffer); #endif -#ifdef CONFIG_XTENSA_USE_SEPARATE_IMEM - if (esp32_ptr_extram(buffer)) - { - tmpbuff = xtensa_imm_malloc(nbytes); - if (tmpbuff == NULL) - { - return (ssize_t)-ENOMEM; - } - } -#endif - /* Acquire the semaphore. */ ret = nxsem_wait(&g_exclsem); @@ -1071,7 +1442,7 @@ static ssize_t esp32_read(FAR struct mtd_dev_s *dev, off_t offset, } esp32_set_read_opt(priv); - ret = esp32_readdata(priv, offset, tmpbuff, nbytes); + ret = esp32_readdata(priv, offset, buffer, nbytes); nxsem_post(&g_exclsem); @@ -1085,13 +1456,6 @@ static ssize_t esp32_read(FAR struct mtd_dev_s *dev, off_t offset, #endif error_with_buffer: -#ifdef CONFIG_XTENSA_USE_SEPARATE_IMEM - if (esp32_ptr_extram(buffer)) - { - memcpy(buffer, tmpbuff, (ret == OK) ? nbytes : 0); - xtensa_imm_free(tmpbuff); - } -#endif return (ssize_t)ret; } @@ -1139,6 +1503,109 @@ static ssize_t esp32_bread(FAR struct mtd_dev_s *dev, off_t startblock, return ret; } +/**************************************************************************** + * Name: esp32_read_decrypt + * + * Description: + * Read encrypted data and decrypt automatically from SPI Flash + * at designated address. + * + * Input Parameters: + * dev - ESP32 MTD device data + * offset - target address offset + * nbytes - data number + * buffer - data buffer pointer + * + * Returned Value: + * Read data bytes if success or a negative value if fail. + * + ****************************************************************************/ + +static ssize_t esp32_read_decrypt(FAR struct mtd_dev_s *dev, + off_t offset, + size_t nbytes, + FAR uint8_t *buffer) +{ + int ret; + uint8_t *tmpbuff = buffer; + FAR struct esp32_spiflash_s *priv = MTD2PRIV(dev); + +#ifdef CONFIG_ESP32_SPIFLASH_DEBUG + finfo("esp32_read_decrypt(%p, 0x%x, %d, %p)\n", + dev, offset, nbytes, buffer); +#endif + + /* Acquire the semaphore. */ + + ret = nxsem_wait(&g_exclsem); + if (ret < 0) + { + goto error_with_buffer; + } + + ret = esp32_readdata_encrypted(priv, offset, tmpbuff, nbytes); + + nxsem_post(&g_exclsem); + + if (ret == OK) + { + ret = nbytes; + } + +#ifdef CONFIG_ESP32_SPIFLASH_DEBUG + finfo("esp32_read_decrypt()=%d\n", ret); +#endif + +error_with_buffer: + + return (ssize_t)ret; +} + +/**************************************************************************** + * Name: esp32_bread_decrypt + * + * Description: + * Read encrypted data and decrypt automatically from designated blocks. + * + * Input Parameters: + * dev - ESP32 MTD device data + * startblock - start block number, it is not equal to SPI Flash's block + * nblocks - blocks number + * buffer - data buffer pointer + * + * Returned Value: + * Read block number if success or a negative value if fail. + * + ****************************************************************************/ + +static ssize_t esp32_bread_decrypt(FAR struct mtd_dev_s *dev, + off_t startblock, + size_t nblocks, + FAR uint8_t *buffer) +{ + int ret; + FAR struct esp32_spiflash_s *priv = MTD2PRIV(dev); + uint32_t addr = MTD_BLK2SIZE(priv, startblock); + uint32_t size = MTD_BLK2SIZE(priv, nblocks); + +#ifdef CONFIG_ESP32_SPIFLASH_DEBUG + finfo("esp32_bread_decrypt(%p, 0x%x, %d, %p)\n", + dev, startblock, nblocks, buffer); +#endif + + ret = esp32_read_decrypt(dev, addr, size, buffer); + if (ret == size) + { + ret = nblocks; + } + +#ifdef CONFIG_ESP32_SPIFLASH_DEBUG + finfo("esp32_bread_decrypt()=%d\n", ret); +#endif + + return ret; +} + /**************************************************************************** * Name: esp32_write * @@ -1160,7 +1627,6 @@ static ssize_t esp32_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, FAR const uint8_t *buffer) { int ret; - uint8_t *tmpbuff = (uint8_t *)buffer; FAR struct esp32_spiflash_s *priv = MTD2PRIV(dev); ASSERT(buffer); @@ -1170,19 +1636,6 @@ static ssize_t esp32_write(FAR struct mtd_dev_s *dev, off_t offset, return -EINVAL; } -#ifdef CONFIG_XTENSA_USE_SEPARATE_IMEM - if (esp32_ptr_extram(buffer)) - { - tmpbuff = xtensa_imm_malloc(nbytes); - if (tmpbuff == NULL) - { - return (ssize_t)-ENOMEM; - } - - memcpy(tmpbuff, buffer, nbytes); - } -#endif - #ifdef CONFIG_ESP32_SPIFLASH_DEBUG finfo("esp32_write(%p, 0x%x, %d, %p)\n", dev, offset, nbytes, buffer); #endif @@ -1195,8 +1648,7 @@ static ssize_t esp32_write(FAR struct mtd_dev_s *dev, off_t offset, goto error_with_buffer; } - esp32_set_write_opt(priv); - ret = esp32_writedata(priv, offset, tmpbuff, nbytes); + ret = esp32_writedata(priv, offset, buffer, nbytes); nxsem_post(&g_exclsem); @@ -1210,12 +1662,6 @@ static ssize_t esp32_write(FAR struct mtd_dev_s *dev, off_t offset, #endif error_with_buffer: -#ifdef CONFIG_XTENSA_USE_SEPARATE_IMEM - if (esp32_ptr_extram(buffer)) - { - xtensa_imm_free(tmpbuff); - } -#endif return (ssize_t)ret; } @@ -1264,6 +1710,63 @@ static ssize_t esp32_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, return ret; } +/**************************************************************************** + * Name: esp32_bwrite_encrypt + * + * Description: + * Write data to designated blocks by SPI Flash hardware encryption. + * + * Input Parameters: + * dev - ESP32 MTD device data + * startblock - start MTD block number, + * it is not equal to SPI Flash's block + * nblocks - blocks number + * buffer - data buffer pointer + * + * Returned Value: + * Writen block number if success or a negative value if fail. + * + ****************************************************************************/ + +static ssize_t esp32_bwrite_encrypt(FAR struct mtd_dev_s *dev, + off_t startblock, + size_t nblocks, + FAR const uint8_t *buffer) +{ + ssize_t ret; + FAR struct esp32_spiflash_s *priv = MTD2PRIV(dev); + uint32_t addr = MTD_BLK2SIZE(priv, startblock); + uint32_t size = MTD_BLK2SIZE(priv, nblocks); + +#ifdef CONFIG_ESP32_SPIFLASH_DEBUG + finfo("esp32_bwrite_encrypt(%p, 0x%x, %d, %p)\n", + dev, startblock, nblocks, buffer); +#endif + + ret = nxsem_wait(&g_exclsem); + if (ret < 0) + { + goto error_with_buffer; + } + + ret = esp32_writedata_encrypted(priv, addr, buffer, size); + + nxsem_post(&g_exclsem); + + if (ret == OK) + { + ret = nblocks; + } + +#ifdef CONFIG_ESP32_SPIFLASH_DEBUG + finfo("esp32_bwrite_encrypt()=%d\n", ret); +#endif + +error_with_buffer: + + return ret; +} + /**************************************************************************** * Name: esp32_ioctl * @@ -1398,4 +1901,25 @@ FAR struct mtd_dev_s *esp32_spiflash_get_mtd(void) return &priv->mtd; } +/**************************************************************************** + * Name: esp32_spiflash_get_mtd + * + * Description: + * Get ESP32 SPI Flash encryption raw MTD. + * + * Input Parameters: + * None + * + * Returned Value: + * ESP32 SPI Flash encryption raw MTD data pointer. + * + ****************************************************************************/ + +FAR struct mtd_dev_s *esp32_spiflash_encrypt_get_mtd(void) +{ + struct esp32_spiflash_s *priv = &g_esp32_spiflash1_encrypt; + + return &priv->mtd; +} + #endif /* CONFIG_ESP32_SPIFLASH */ diff --git a/arch/xtensa/src/esp32/esp32_spiflash.h b/arch/xtensa/src/esp32/esp32_spiflash.h index 1b3702d02c2..3c9099aa1a7 100644 --- a/arch/xtensa/src/esp32/esp32_spiflash.h +++ b/arch/xtensa/src/esp32/esp32_spiflash.h @@ -78,6 +78,22 @@ FAR struct mtd_dev_s *esp32_spiflash_alloc_mtdpart(void); FAR struct mtd_dev_s *esp32_spiflash_get_mtd(void); +/**************************************************************************** + * Name: esp32_spiflash_get_mtd + * + * Description: + * Get ESP32 SPI Flash encryption raw MTD. + * + * Input Parameters: + * None + * + * Returned Value: + * ESP32 SPI Flash encryption raw MTD data pointer. + * + ****************************************************************************/ + +FAR struct mtd_dev_s *esp32_spiflash_encrypt_get_mtd(void); + #ifdef __cplusplus } #endif diff --git a/arch/xtensa/src/esp32/esp32_tim.c b/arch/xtensa/src/esp32/esp32_tim.c index b0f21bad122..0b6f53fc8db 100644 --- a/arch/xtensa/src/esp32/esp32_tim.c +++ b/arch/xtensa/src/esp32/esp32_tim.c @@ -935,7 +935,7 @@ FAR struct esp32_tim_dev_s *esp32_tim0_init(void) if (tim->inuse == true) { - tmrerr("ERROR: TIMER %d is already in use\n", timer); + tmrerr("ERROR: Timer0 is already in use\n"); tim = NULL; } diff --git a/arch/xtensa/src/esp32/esp32_wifi_adapter.c b/arch/xtensa/src/esp32/esp32_wifi_adapter.c index 859eda40b2d..a0e7bfd625b 100644 --- a/arch/xtensa/src/esp32/esp32_wifi_adapter.c +++ b/arch/xtensa/src/esp32/esp32_wifi_adapter.c @@ -259,6 +259,7 @@ static void esp_coex_condition_set(uint32_t type, bool dissatisfy); static int32_t esp_coex_wifi_request(uint32_t event, uint32_t latency, uint32_t duration); static int32_t esp_coex_wifi_release(uint32_t event); +static unsigned long esp_random_ulong(void); /**************************************************************************** * Public Functions declaration @@ -389,7 +390,7 @@ wifi_osi_funcs_t g_wifi_osi_funcs = ._nvs_erase_key = esp_nvs_erase_key, ._get_random = esp_get_random, ._get_time = esp_get_time, - ._random = esp_random, + ._random = esp_random_ulong, ._log_write = esp_log_write, ._log_writev = esp_log_writev, ._log_timestamp = esp_log_timestamp, @@ -1154,7 +1155,7 @@ static void *esp_queue_create(uint32_t queue_len, uint32_t item_size) } snprintf(mq_adpt->name, sizeof(mq_adpt->name), - "/tmp/%X", mq_adpt); + "/tmp/%p", mq_adpt); attr.mq_maxmsg = queue_len; attr.mq_msgsize = item_size; @@ -3672,6 +3673,20 @@ static int32_t esp_coex_wifi_release(uint32_t event) return 0; } +/**************************************************************************** + * Name: esp_random_ulong + * + * Description: + * A simpler wrapper of esp_random. + * Just convert the return value from uint32_t to unsigned long. + * + ****************************************************************************/ + +static unsigned long esp_random_ulong(void) +{ + return esp_random(); +} + /**************************************************************************** * Functions needed by libphy.a ****************************************************************************/ diff --git a/arch/xtensa/src/esp32/esp32_wtd_lowerhalf.c b/arch/xtensa/src/esp32/esp32_wtd_lowerhalf.c index 8e2a9f62bb4..ca05afa9070 100644 --- a/arch/xtensa/src/esp32/esp32_wtd_lowerhalf.c +++ b/arch/xtensa/src/esp32/esp32_wtd_lowerhalf.c @@ -78,6 +78,7 @@ struct esp32_wtd_lowerhalf_s uint32_t lastreset; /* The last reset time */ bool started; /* True: Timer has been started */ xcpt_t handler; /* User Handler */ + void *upper; /* Pointer to watchdog_upperhalf_s */ }; /**************************************************************************** @@ -168,7 +169,7 @@ static int esp32_wtd_start(FAR struct watchdog_lowerhalf_s *lower) int ret = OK; irqstate_t flags; - wdinfo("Entry: started=%d\n"); + wdinfo("Entry: started\n"); DEBUGASSERT(priv); if (priv->started == true) @@ -559,7 +560,7 @@ static xcpt_t esp32_wtd_capture(FAR struct watchdog_lowerhalf_s *lower, if (priv->peripheral == TIMER) { - ESP32_WTD_STG_CONF(priv->wtd, STAGE_0, RESET_SYSTEM_TIMER); + ESP32_WTD_STG_CONF(priv->wtd, STAGE_0, RESET_SYSTEM_TIMER); } else { @@ -590,7 +591,7 @@ static int esp32_wdt_handler(int irq, FAR void *context, FAR void *arg) /* Run the user callback */ - priv->handler(irq, context, NULL); + priv->handler(irq, context, priv->upper); ESP32_WTD_ACKINT(priv->wtd); /* Clear the Interrupt */ ESP32_WTD_LOCK(priv->wtd); @@ -623,7 +624,6 @@ static int esp32_wdt_handler(int irq, FAR void *context, FAR void *arg) int esp32_wtd_initialize(FAR const char *devpath, uint8_t wdt) { struct esp32_wtd_lowerhalf_s *lower = NULL; - FAR void *handle = NULL; int ret = OK; DEBUGASSERT(devpath); @@ -694,14 +694,15 @@ int esp32_wtd_initialize(FAR const char *devpath, uint8_t wdt) ESP32_WTD_LOCK(lower->wtd); - /* Register the watchdog driver as /dev/watchdogX. The returned value from - * watchdog_register is a handle that could be used with - * watchdog_unregister(). REVISIT: The returned handle is discarded here. + /* Register the watchdog driver as /dev/watchdogX. If the registration goes + * right the returned value from watchdog_register is a pointer to + * watchdog_upperhalf_s that can be either used with watchdog_unregister() + * or with the handler's arg. */ - handle = watchdog_register(devpath, + lower->upper = watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)lower); - if (handle == NULL) + if (lower->upper == NULL) { /* The actual cause of the failure may have been a failure to allocate * perhaps a failure to register the watchdog driver (such as if the diff --git a/arch/xtensa/src/esp32/hardware/esp32_dport.h b/arch/xtensa/src/esp32/hardware/esp32_dport.h index f81b6dea815..d5a74becb13 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_dport.h +++ b/arch/xtensa/src/esp32/hardware/esp32_dport.h @@ -4387,4 +4387,12 @@ #define DPORT_DATE_S 0 #define DPORT_DPORT_DATE_VERSION 0x1605190 +/* SPI Flash MMU table regitser base address for PRO CPU */ + +#define DPORT_PRO_FLASH_MMU_TABLE_REG (DR_REG_DPORT_BASE + 0x10000) + +/* SPI Flash MMU table regitser base address for APP CPU */ + +#define DPORT_APP_FLASH_MMU_TABLE_REG (DR_REG_DPORT_BASE + 0x12000) + #endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_DPORT_H */ diff --git a/arch/xtensa/src/esp32/hardware/esp32_soc.h b/arch/xtensa/src/esp32/hardware/esp32_soc.h index 2109315fad1..12baf3e7f01 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_soc.h +++ b/arch/xtensa/src/esp32/hardware/esp32_soc.h @@ -275,6 +275,11 @@ #define SOC_EXTRAM_DATA_LOW 0x3f800000 #define SOC_EXTRAM_DATA_HIGH 0x3fc00000 +/* Virtual address 0 */ + +#define VADDR0_START_ADDR SOC_DROM_LOW +#define VADDR0_END_ADDR (SOC_DROM_HIGH - 1) + /* Interrupt hardware source table * This table is decided by hardware, don't touch this. */ @@ -776,10 +781,32 @@ extern int rom_i2c_writeReg(int block, int block_id, int reg_add, #define FE2_TX_INF_FORCE_PD_V 1 #define FE2_TX_INF_FORCE_PD_S 9 +/* RO data page in MMU index */ + +#define DROM0_PAGES_START 0 +#define DROM0_PAGES_END 64 + +/* MMU invaild value */ + +#define INVALID_MMU_VAL 0x100 + /**************************************************************************** * Inline Functions ****************************************************************************/ +/**************************************************************************** + * Name: esp32_sp_dram + * + * Description: + * Check if the stack pointer is in DRAM. + * + ****************************************************************************/ + +static inline bool IRAM_ATTR esp32_sp_dram(uint32_t sp) +{ + return (sp >= SOC_DRAM_LOW + 0x10 && sp < SOC_DRAM_HIGH - 0x10); +} + /**************************************************************************** * Name: esp32_ptr_extram * @@ -794,4 +821,24 @@ static inline bool IRAM_ATTR esp32_ptr_extram(const void *p) (intptr_t)p < SOC_EXTRAM_DATA_HIGH); } +/**************************************************************************** + * Name: esp32_ptr_exec + * + * Description: + * Check if the pointer is within an executable range. + * + ****************************************************************************/ + +static inline bool IRAM_ATTR esp32_ptr_exec(const void *p) +{ + intptr_t ip = (intptr_t)p; + return (ip >= SOC_IROM_LOW && ip < SOC_IROM_HIGH) + || (ip >= SOC_IRAM_LOW && ip < SOC_IRAM_HIGH) + || (ip >= SOC_IROM_MASK_LOW && ip < SOC_IROM_MASK_HIGH) +#if defined(SOC_CACHE_APP_LOW) && !defined(CONFIG_SMP) + || (ip >= SOC_CACHE_APP_LOW && ip < SOC_CACHE_APP_HIGH) +#endif + || (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH); +} + #endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SOC_H */ diff --git a/arch/z16/include/types.h b/arch/z16/include/types.h index e1e7f3ab9c3..e9a6eaa4a04 100644 --- a/arch/z16/include/types.h +++ b/arch/z16/include/types.h @@ -72,6 +72,9 @@ typedef unsigned short _uint16_t; typedef signed int _int32_t; typedef unsigned int _uint32_t; +typedef _int32_t _intmax_t; +typedef _uint32_t _uintmax_t; + /* A size is 4 bytes */ #if defined(__SIZE_TYPE__) diff --git a/arch/z80/include/ez80/types.h b/arch/z80/include/ez80/types.h index edfd6f12979..6db23df3eb3 100644 --- a/arch/z80/include/ez80/types.h +++ b/arch/z80/include/ez80/types.h @@ -84,6 +84,9 @@ typedef unsigned int _uint24_t; typedef signed long _int32_t; typedef unsigned long _uint32_t; +typedef _int32_t _intmax_t; +typedef _uint32_t _uintmax_t; + /* A pointer is 2 or 3 bytes, depending upon if the ez80 is in z80 * compatibility mode or not * diff --git a/arch/z80/include/z180/types.h b/arch/z80/include/z180/types.h index cbdd94318d6..c18f072ee19 100644 --- a/arch/z80/include/z180/types.h +++ b/arch/z80/include/z180/types.h @@ -84,6 +84,9 @@ typedef signed long long _int64_t; typedef unsigned long long _uint64_t; #define __INT64_DEFINED +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; + /* A size is 2 bytes */ #if defined(__SIZE_TYPE__) diff --git a/arch/z80/include/z8/types.h b/arch/z80/include/z8/types.h index eae4e9f49b3..d620f5fc67f 100644 --- a/arch/z80/include/z8/types.h +++ b/arch/z80/include/z8/types.h @@ -62,7 +62,8 @@ * the user prefers to use the definitions provided by their toolchain header * files * - * These are the sizes of the types supported by the ZiLOG Z8Encore! compiler: + * These are the sizes of the types supported by the ZiLOG Z8Encore! + * compiler: * * int - 16-bits * short - 16-bits @@ -87,6 +88,9 @@ typedef unsigned int _uint16_t; typedef signed long _int32_t; typedef unsigned long _uint32_t; +typedef _int32_t _intmax_t; +typedef _uint32_t _uintmax_t; + /* A size is 2 bytes */ #if defined(__SIZE_TYPE__) diff --git a/arch/z80/include/z80/types.h b/arch/z80/include/z80/types.h index fb774dd75e3..021152b3595 100644 --- a/arch/z80/include/z80/types.h +++ b/arch/z80/include/z80/types.h @@ -84,6 +84,9 @@ typedef signed long long _int64_t; typedef unsigned long long _uint64_t; #define __INT64_DEFINED +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; + /* A size is 2 bytes */ #if defined(__SIZE_TYPE__) diff --git a/audio/Makefile b/audio/Makefile index 9fcabcdc47c..a8c782938e6 100644 --- a/audio/Makefile +++ b/audio/Makefile @@ -68,9 +68,13 @@ $(COBJS): %$(OBJEXT): %.c $(BIN): $(OBJS) $(call ARCHIVE, $@, $(OBJS)) + +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) .depend: Makefile $(SRCS) $(TOPDIR)$(DELIM).config - $(Q) $(MKDEP) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile $(Q) touch $@ depend: .depend diff --git a/binfmt/Makefile b/binfmt/Makefile index 23dcdab4f4a..fd5299536bd 100644 --- a/binfmt/Makefile +++ b/binfmt/Makefile @@ -80,9 +80,13 @@ $(BINFMT_COBJS): %$(OBJEXT): %.c $(BIN): $(BINFMT_OBJS) $(call ARCHIVE, $@, $(BINFMT_OBJS)) + +makedepfile: $(BINFMT_CSRCS:.c=.ddc) $(BINFMT_ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) .depend: Makefile $(BINFMT_SRCS) $(TOPDIR)$(DELIM).config - $(Q) $(MKDEP) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(BINFMT_SRCS) >Make.dep + $(Q) $(MAKE) makedepfile $(Q) touch $@ depend: .depend diff --git a/binfmt/binfmt_dumpmodule.c b/binfmt/binfmt_dumpmodule.c index c10621bddb9..9928c8aad51 100644 --- a/binfmt/binfmt_dumpmodule.c +++ b/binfmt/binfmt_dumpmodule.c @@ -74,7 +74,7 @@ int dump_module(FAR const struct binary_s *bin) binfo(" filename: %s\n", bin->filename); binfo(" argv: %p\n", bin->argv); binfo(" entrypt: %p\n", bin->entrypt); - binfo(" mapped: %p size=%d\n", bin->mapped, bin->mapsize); + binfo(" mapped: %p size=%zd\n", bin->mapped, bin->mapsize); binfo(" alloc: %p %p %p\n", bin->alloc[0], bin->alloc[1], bin->alloc[2]); @@ -85,7 +85,7 @@ int dump_module(FAR const struct binary_s *bin) #ifdef CONFIG_ARCH_ADDRENV binfo(" addrenv: %p\n", bin->addrenv); #endif - binfo(" stacksize: %d\n", bin->stacksize); + binfo(" stacksize: %zd\n", bin->stacksize); binfo(" unload: %p\n", bin->unload); } diff --git a/binfmt/libelf/libelf_bind.c b/binfmt/libelf/libelf_bind.c index 4daac9a906b..ef42a4f7eed 100644 --- a/binfmt/libelf/libelf_bind.c +++ b/binfmt/libelf/libelf_bind.c @@ -39,6 +39,7 @@ #include +#include #include #include #include @@ -338,8 +339,9 @@ static int elf_relocate(FAR struct elf_loadinfo_s *loadinfo, int relidx, rel->r_offset > dstsec->sh_size - sizeof(uint32_t)) { berr("Section %d reloc %d: Relocation address out of range, " - "offset %d size %d\n", - relidx, i, rel->r_offset, dstsec->sh_size); + "offset %" PRIdPTR " size %jd\n", + relidx, i, (uintptr_t)rel->r_offset, + (uintmax_t)dstsec->sh_size); ret = -EINVAL; break; } @@ -522,8 +524,9 @@ static int elf_relocateadd(FAR struct elf_loadinfo_s *loadinfo, int relidx, rela->r_offset > dstsec->sh_size) { berr("Section %d reloc %d: Relocation address out of range, " - "offset %d size %d\n", - relidx, i, rela->r_offset, dstsec->sh_size); + "offset %" PRIdPTR " size %jd\n", + relidx, i, (uintptr_t)rela->r_offset, + (uintmax_t)dstsec->sh_size); ret = -EINVAL; break; } diff --git a/binfmt/libelf/libelf_symbols.c b/binfmt/libelf/libelf_symbols.c index 34a3c0c7f17..bacab25a224 100644 --- a/binfmt/libelf/libelf_symbols.c +++ b/binfmt/libelf/libelf_symbols.c @@ -39,6 +39,7 @@ #include +#include #include #include #include @@ -323,9 +324,11 @@ int elf_symvalue(FAR struct elf_loadinfo_s *loadinfo, FAR Elf_Sym *sym, * entry */ - binfo("SHN_UNDEF: name=%s %08x+%08x=%08x\n", - loadinfo->iobuffer, sym->st_value, symbol->sym_value, - sym->st_value + symbol->sym_value); + binfo("SHN_UNDEF: name=%s " + "%08" PRIxPTR "+%08" PRIxPTR "=%08" PRIxPTR "\n", + loadinfo->iobuffer, (uintptr_t)sym->st_value, + (uintptr_t)symbol->sym_value, + (uintptr_t)(sym->st_value + symbol->sym_value)); sym->st_value += ((uintptr_t)symbol->sym_value); } @@ -335,8 +338,9 @@ int elf_symvalue(FAR struct elf_loadinfo_s *loadinfo, FAR Elf_Sym *sym, { secbase = loadinfo->shdr[sym->st_shndx].sh_addr; - binfo("Other: %08x+%08x=%08x\n", - sym->st_value, secbase, sym->st_value + secbase); + binfo("Other: %08" PRIxPTR "+%08" PRIxPTR "=%08" PRIxPTR "\n", + (uintptr_t)sym->st_value, secbase, + (uintptr_t)(sym->st_value + secbase)); sym->st_value += secbase; } diff --git a/boards/Makefile b/boards/Makefile index c6a7c9228a4..8169ebdbcd1 100644 --- a/boards/Makefile +++ b/boards/Makefile @@ -98,14 +98,13 @@ $(CXXOBJS): %$(OBJEXT): %.cxx $(BIN): $(OBJS) $(call ARCHIVE, $@, $(OBJS)) + +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) $(CXXSRCS:.cxx=.ddx) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) .depend: Makefile $(SRCS) $(TOPDIR)$(DELIM).config -ifneq ($(SRCS),) - $(Q) $(MKDEP) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep -endif -ifneq ($(CXXSRCS),) - $(Q) $(MKDEP) "$(CXX)" -- $(CXXFLAGS) -- $(CXXSRCS) >>Make.dep -endif + $(Q) $(MAKE) makedepfile $(Q) touch $@ depend: .depend diff --git a/boards/arm/imx6/sabre-6quad/README.txt b/boards/arm/imx6/sabre-6quad/README.txt index cc80d3bcf5a..f9a06ea478f 100644 --- a/boards/arm/imx6/sabre-6quad/README.txt +++ b/boards/arm/imx6/sabre-6quad/README.txt @@ -592,24 +592,7 @@ Debugging with QEMU The nuttx ELF image can be debugged with QEMU. -1. Before debugging, following change (enabling wfi instruction in up_idle) - is recommended to reduce CPU usage on host PC. - -diff --git a/arch/arm/src/common/up_idle.c b/arch/arm/src/common/up_idle.c -index 45fab0b7c6..c54c1178a1 100644 ---- a/arch/arm/src/common/up_idle.c -+++ b/arch/arm/src/common/up_idle.c -@@ -71,7 +71,7 @@ void up_idle(void) - - /* Sleep until an interrupt occurs to save power */ - --#if 0 -+#if 1 - asm("WFI"); /* For example */ - #endif - #endif - -2. Also, to debug the nuttx (ELF) with symbols, following change must +1. To debug the nuttx (ELF) with symbols, following change must be applied to defconfig. diff --git a/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig b/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig @@ -624,6 +607,33 @@ index b15becbb51..3ad4d13ad7 100644 +CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_ZERO=y +2. Please note that QEMU does not report PL310 (L2CC) related + registers correctly, so if you enable CONFIG_DEBUG_ASSERTION + the nuttx will stop with DEBUGASSERT(). To avoid this, + comment out the following lines. + +--- a/arch/arm/src/armv7-a/arm_l2cc_pl310.c ++++ b/arch/arm/src/armv7-a/arm_l2cc_pl310.c +@@ -333,7 +333,7 @@ void arm_l2ccinitialize(void) + #if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY) + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 0); + #elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY) +- DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == L2CC_ACR_ASS); ++ //DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == L2CC_ACR_ASS); + #else + # error No associativity selected + #endif +@@ -345,8 +345,8 @@ void arm_l2ccinitialize(void) + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_32KB); + #elif defined(CONFIG_ARMV7A_WAYSIZE_64KB) +- DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == +- L2CC_ACR_WAYSIZE_64KB); ++ // DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == ++ // L2CC_ACR_WAYSIZE_64KB); + #elif defined(CONFIG_ARMV7A_WAYSIZE_128KB) + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_128KB); 3. Run QEMU @@ -691,58 +701,7 @@ Open Issues: This will cause the interrupt handlers on other CPUs to spin until leave_critical_section() is called. More verification is needed. -2. Cache Concurrency. Cache coherency in SMP configurations is managed by the - MPCore snoop control unit (SCU). But I don't think I have the set up - correctly yet. - - Currently cache inconsistencies appear to be the root cause of all current SMP - issues. SMP works as expected if the caches are disabled, but otherwise there - are problems (usually hangs): - - This will disable the caches: - -diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S -index 27c2a5b..2a6274c 100644 ---- a/arch/arm/src/armv7-a/arm_head.S -+++ b/arch/arm/src/armv7-a/arm_head.S -@@ -454,6 +454,7 @@ __start: - * after SMP cache coherency has been setup. - */ - -+#if 0 // REMOVE ME - #if !defined(CPU_DCACHE_DISABLE) && !defined(CONFIG_SMP) - /* Dcache enable - * -@@ -471,6 +472,7 @@ __start: - - orr r0, r0, #(SCTLR_I) - #endif -+#endif // REMOVE ME - - #ifdef CPU_ALIGNMENT_TRAP - /* Alignment abort enable -diff --git a/arch/arm/src/armv7-a/arm_scu.c b/arch/arm/src/armv7-a/arm_scu.c -index eedf179..1db2092 100644 ---- a/arch/arm/src/armv7-a/arm_scu.c -+++ b/arch/arm/src/armv7-a/arm_scu.c -@@ -156,6 +156,7 @@ static inline void arm_set_actlr(uint32_t actlr) - - void arm_enable_smp(int cpu) - { -+#if 0 // REMOVE ME - uint32_t regval; - - /* Handle actions unique to CPU0 which comes up first */ -@@ -222,6 +223,7 @@ void arm_enable_smp(int cpu) - regval = arm_get_sctlr(); - regval |= SCTLR_C; - arm_set_sctlr(regval); -+#endif // REMOVE ME - } - - #endif - -3. Recent redesigns to SMP of another ARMv7-M platform have made changes to the OS +2. Recent redesigns to SMP of another ARMv7-M platform have made changes to the OS SMP support. There are no known problem but the changes have not been verified fully (see STATUS above for 2019-02-06). diff --git a/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig b/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig index 30aa9a25a8b..b804cde2f7a 100644 --- a/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig +++ b/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig @@ -17,12 +17,18 @@ CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_LOWVECTORS=y CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7A_ASSOCIATIVITY_16WAY=y +CONFIG_ARMV7A_L2CC_PL310=y +CONFIG_ARMV7A_WAYSIZE_64KB=y CONFIG_BOARD_LOOPSPERMSEC=99369 CONFIG_BOOT_RUNFROMSDRAM=y CONFIG_BUILTIN=y +CONFIG_CLOCK_MONOTONIC=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_ZERO=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXPERIMENTAL=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y @@ -35,6 +41,8 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y +CONFIG_PL310_LOCKDOWN_BY_LINE=y +CONFIG_PL310_LOCKDOWN_BY_MASTER=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAMLOG=y CONFIG_RAMLOG_BUFSIZE=16384 @@ -53,5 +61,7 @@ CONFIG_START_MONTH=3 CONFIG_START_YEAR=2016 CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y CONFIG_UART1_SERIAL_CONSOLE=y CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/imx6/sabre-6quad/configs/smp/defconfig b/boards/arm/imx6/sabre-6quad/configs/smp/defconfig index 110b33b9d12..5f2ee1a10de 100644 --- a/boards/arm/imx6/sabre-6quad/configs/smp/defconfig +++ b/boards/arm/imx6/sabre-6quad/configs/smp/defconfig @@ -17,14 +17,19 @@ CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_LOWVECTORS=y CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7A_ASSOCIATIVITY_16WAY=y +CONFIG_ARMV7A_L2CC_PL310=y +CONFIG_ARMV7A_WAYSIZE_64KB=y CONFIG_BOARD_LOOPSPERMSEC=99369 CONFIG_BOOT_RUNFROMSDRAM=y CONFIG_BUILTIN=y +CONFIG_CLOCK_MONOTONIC=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_ZERO=y CONFIG_DRIVER_NOTE=y CONFIG_EXAMPLES_HELLO=y +CONFIG_EXPERIMENTAL=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y @@ -36,6 +41,8 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y +CONFIG_PL310_LOCKDOWN_BY_LINE=y +CONFIG_PL310_LOCKDOWN_BY_MASTER=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAMLOG=y CONFIG_RAMLOG_BUFSIZE=16384 @@ -58,6 +65,7 @@ CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_SYSTEM=y CONFIG_SYSTEM_TASKSET=y +CONFIG_TESTING_GETPRIME=y CONFIG_TESTING_OSTEST=y CONFIG_TESTING_OSTEST_FPUTESTDISABLE=y CONFIG_TESTING_SMP=y diff --git a/boards/arm/kinetis/freedom-k64f/configs/demo/defconfig b/boards/arm/kinetis/freedom-k64f/configs/demo/defconfig index e8ae493ced0..6e595a9a1a2 100644 --- a/boards/arm/kinetis/freedom-k64f/configs/demo/defconfig +++ b/boards/arm/kinetis/freedom-k64f/configs/demo/defconfig @@ -46,8 +46,10 @@ CONFIG_MMCSD_MULTIBLOCK_DISABLE=y CONFIG_MMCSD_SDIO=y CONFIG_MOTOROLA_SREC=y CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETUTILS_NETCAT=y CONFIG_NET_BROADCAST=y CONFIG_NET_SOCKOPTS=y +CONFIG_NET_TCP=y CONFIG_NET_UDP=y CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/lc823450/lc823450-xgevk/configs/rndis/defconfig b/boards/arm/lc823450/lc823450-xgevk/configs/rndis/defconfig index f7695b3072e..fbd46d77f8e 100644 --- a/boards/arm/lc823450/lc823450-xgevk/configs/rndis/defconfig +++ b/boards/arm/lc823450/lc823450-xgevk/configs/rndis/defconfig @@ -190,6 +190,7 @@ CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_UART0_TXBUFSIZE=2048 CONFIG_USBDEV=y CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USBDEV_DMA=y CONFIG_USBDEV_DUALSPEED=y CONFIG_USBDEV_MAXPOWER=500 CONFIG_USERMAIN_STACKSIZE=3072 diff --git a/boards/arm/lpc31xx/ea3131/configs/pgnsh/defconfig b/boards/arm/lpc31xx/ea3131/configs/pgnsh/defconfig index 8131be5b4ed..4fc372956f4 100644 --- a/boards/arm/lpc31xx/ea3131/configs/pgnsh/defconfig +++ b/boards/arm/lpc31xx/ea3131/configs/pgnsh/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16945 CONFIG_BOOT_RUNFROMISRAM=y CONFIG_BUILD_2PASS=y +CONFIG_DISABLE_ENVIRON=y CONFIG_FS_FAT=y CONFIG_HOST_WINDOWS=y CONFIG_LPC31_SPI=y diff --git a/boards/arm/nrf52/nrf52832-mdk/scripts/Make.defs b/boards/arm/nrf52/nrf52832-mdk/scripts/Make.defs index 7766ad20441..1db56274715 100644 --- a/boards/arm/nrf52/nrf52832-mdk/scripts/Make.defs +++ b/boards/arm/nrf52/nrf52832-mdk/scripts/Make.defs @@ -35,8 +35,8 @@ CXX = $(CROSSDEV)g++ CPP = $(CROSSDEV)gcc -E LD = $(CROSSDEV)ld STRIP = $(CROSSDEV)strip --strip-unneeded -AR = $(ARCROSSDEV)ar rcs -NM = $(ARCROSSDEV)nm +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm OBJCOPY = $(CROSSDEV)objcopy OBJDUMP = $(CROSSDEV)objdump diff --git a/boards/arm/nrf52/nrf52832-sparkfun/scripts/Make.defs b/boards/arm/nrf52/nrf52832-sparkfun/scripts/Make.defs index 58df2d5821c..99af1b4da3b 100644 --- a/boards/arm/nrf52/nrf52832-sparkfun/scripts/Make.defs +++ b/boards/arm/nrf52/nrf52832-sparkfun/scripts/Make.defs @@ -35,8 +35,8 @@ CXX = $(CROSSDEV)g++ CPP = $(CROSSDEV)gcc -E LD = $(CROSSDEV)ld STRIP = $(CROSSDEV)strip --strip-unneeded -AR = $(ARCROSSDEV)ar rcs -NM = $(ARCROSSDEV)nm +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm OBJCOPY = $(CROSSDEV)objcopy OBJDUMP = $(CROSSDEV)objdump diff --git a/boards/arm/nrf52/nrf52840-dk/configs/sx127x/defconfig b/boards/arm/nrf52/nrf52840-dk/configs/sx127x/defconfig new file mode 100644 index 00000000000..9a723fe42f0 --- /dev/null +++ b/boards/arm/nrf52/nrf52840-dk/configs/sx127x/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nrf52840-dk" +CONFIG_ARCH_BOARD_NRF52840_DK=y +CONFIG_ARCH_CHIP="nrf52" +CONFIG_ARCH_CHIP_NRF52840=y +CONFIG_ARCH_CHIP_NRF52=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_STDARG_H=y +CONFIG_BOARD_LOOPSPERMSEC=5500 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_LPWAN=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXAMPLES_SX127X=y +CONFIG_EXAMPLES_SX127X_RFFREQ=433000000 +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_LPWAN_SX127X=y +CONFIG_LPWAN_SX127X_RXSUPPORT=y +CONFIG_LPWAN_SX127X_TXSUPPORT=y +CONFIG_MAX_TASKS=16 +CONFIG_MM_REGIONS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NRF52_GPIOTE=y +CONFIG_NRF52_SPI0_MASTER=y +CONFIG_NRF52_UART0=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65535 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=26 +CONFIG_START_MONTH=3 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/nrf52/nrf52840-dk/src/nrf52_highpri.c b/boards/arm/nrf52/nrf52840-dk/src/nrf52_highpri.c index 5420939498e..391e8769dd6 100644 --- a/boards/arm/nrf52/nrf52840-dk/src/nrf52_highpri.c +++ b/boards/arm/nrf52/nrf52840-dk/src/nrf52_highpri.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -265,7 +266,7 @@ int highpri_main(int argc, char *argv[]) /* Then print out what is happening */ - printf("Elapsed time: %d seconds\n\n", seconds); + printf("Elapsed time: %" PRId32 " seconds\n\n", seconds); for (i = 0, total = 0; i < 16; i++) { total += basepri[i]; diff --git a/boards/arm/nrf52/nrf52840-dk/src/nrf52_sx127x.c b/boards/arm/nrf52/nrf52840-dk/src/nrf52_sx127x.c index 61a640e5957..0625a8b0535 100644 --- a/boards/arm/nrf52/nrf52840-dk/src/nrf52_sx127x.c +++ b/boards/arm/nrf52/nrf52840-dk/src/nrf52_sx127x.c @@ -88,7 +88,7 @@ static int sx127x_irq0_attach(xcpt_t isr, FAR void *arg) /* IRQ on rising edge */ - nrf52_gpiosetevent(GPIO_SX127X_DIO0, true, false, false, isr, arg); + nrf52_gpiote_set_ch_event(GPIO_SX127X_DIO0, 0, true, false, isr, arg); return OK; } diff --git a/boards/arm/samd2l2/arduino-m0/src/sam_usb.c b/boards/arm/samd2l2/arduino-m0/src/sam_usb.c index d00431b06ad..f7810bb8721 100644 --- a/boards/arm/samd2l2/arduino-m0/src/sam_usb.c +++ b/boards/arm/samd2l2/arduino-m0/src/sam_usb.c @@ -111,11 +111,11 @@ void weak_function sam_usbinitialize(void) * Name: sam_usbsuspend * * Description: - * Board logic must provide the sam_usbsuspend logic if the USBDEV driver is - * used. + * Board logic must provide the sam_usbsuspend logic if the USBDEV driver + * is used. * This function is called whenever the USB enters or leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, etc. - * while the USB is suspended. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. * ****************************************************************************/ diff --git a/boards/arm/stm32/common/include/stm32_l3gd20.h b/boards/arm/stm32/common/include/stm32_l3gd20.h index 230f106fdff..8b38ebd9b60 100644 --- a/boards/arm/stm32/common/include/stm32_l3gd20.h +++ b/boards/arm/stm32/common/include/stm32_l3gd20.h @@ -62,7 +62,8 @@ extern "C" * Initialize and register the L3GD20 3 axis gyroscope sensor driver. * * Input Parameters: - * devno - The device number, used to build the device path as /dev/sensor/gyro_uncalN + * devno - The device number, used to build the device path as + * /dev/sensor/gyro_uncalN * busno - The SPI bus number * * Returned Value: diff --git a/boards/arm/stm32/common/src/stm32_l3gd20.c b/boards/arm/stm32/common/src/stm32_l3gd20.c index efa04944b6b..e32cfb12c5b 100644 --- a/boards/arm/stm32/common/src/stm32_l3gd20.c +++ b/boards/arm/stm32/common/src/stm32_l3gd20.c @@ -86,7 +86,8 @@ static int l3gd20_attach(FAR struct l3gd20_config_s *cfg, xcpt_t irq) * Initialize and register the L3GD20 3 axis gyroscope sensor driver. * * Input Parameters: - * devno - The device number, used to build the device path as /dev/sensor/gyro_uncalN + * devno - The device number, used to build the device path as + * /dev/sensor/gyro_uncalN * busno - The SPI bus number * * Returned Value: diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c index a1deac11e12..f5d79d6db6c 100644 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c +++ b/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -501,10 +502,10 @@ int highpri_main(int argc, char *argv[]) g_highpri.lock = true; #ifndef CONFIG_STM32_ADC1_DMA - printf("%d [%d] %0.3fV\n", g_highpri.cntr1, g_highpri.current, + printf("%" PRId32 " [%d] %0.3fV\n", g_highpri.cntr1, g_highpri.current, g_highpri.r_volt[g_highpri.current]); #else - printf("%d ", g_highpri.cntr1); + printf("%" PRId32 " ", g_highpri.cntr1); for (i = 0; i < REG_NCHANNELS; i += 1) { @@ -517,7 +518,7 @@ int highpri_main(int argc, char *argv[]) #ifdef HIGHPRI_HAVE_INJECTED /* Print data from injected channels */ - printf("%d ", g_highpri.cntr2); + printf("%" PRId32 " ", g_highpri.cntr2); for (i = 0; i < INJ_NCHANNELS; i += 1) { diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c index 32acb0ac4ee..161b5c0ea0d 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c +++ b/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -543,10 +544,10 @@ int highpri_main(int argc, char *argv[]) g_highpri.lock = true; #ifndef CONFIG_STM32_ADC1_DMA - printf("%d [%d] %0.3fV\n", g_highpri.cntr1, g_highpri.current, + printf("%" PRId32 " [%d] %0.3fV\n", g_highpri.cntr1, g_highpri.current, g_highpri.r_volt[g_highpri.current]); #else - printf("%d ", g_highpri.cntr1); + printf("%" PRId32 " ", g_highpri.cntr1); for (i = 0; i < REG_NCHANNELS; i += 1) { @@ -559,7 +560,7 @@ int highpri_main(int argc, char *argv[]) #ifdef HIGHPRI_HAVE_INJECTED /* Print data from injected channels */ - printf("%d ", g_highpri.cntr2); + printf("%" PRId32 " ", g_highpri.cntr2); for (i = 0; i < INJ_NCHANNELS; i += 1) { diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c index a5d0662deeb..b3af2a5a11d 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c +++ b/boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -453,8 +454,8 @@ static int slaves_configure(FAR struct spwm_s *spwm) per = fclk / CONFIG_NUCLEOF334R8_SPWM_PWM_FREQ; if (per > HRTIM_PER_MAX) { - printf("ERROR: can not achieve pwm freq=%llu if fclk=%llu\n", - CONFIG_NUCLEOF334R8_SPWM_PWM_FREQ, fclk); + printf("ERROR: can not achieve pwm freq=%ju if fclk=%llu\n", + (uintmax_t)CONFIG_NUCLEOF334R8_SPWM_PWM_FREQ, fclk); ret = -EINVAL; goto errout; } diff --git a/boards/arm/stm32/photon/configs/adb/defconfig b/boards/arm/stm32/photon/configs/adb/defconfig new file mode 100644 index 00000000000..86527bc06da --- /dev/null +++ b/boards/arm/stm32/photon/configs/adb/defconfig @@ -0,0 +1,80 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ADBD_AUTHENTICATION=y +CONFIG_ADBD_AUTH_PUBKEY=y +CONFIG_ADBD_BOARD_INIT=y +CONFIG_ADBD_DEVICE_ID="serialno" +CONFIG_ADBD_FILE_SERVICE=y +CONFIG_ADBD_LOGCAT_SERVICE=y +CONFIG_ADBD_SHELL_SERVICE=y +CONFIG_ADBD_USB_SERVER=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="photon" +CONFIG_ARCH_BOARD_PHOTON=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CLOCK_MONOTONIC=y +CONFIG_DEBUG_ERROR=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_WARN=y +CONFIG_DEV_FIFO_SIZE=128 +CONFIG_DEV_PIPE_MAXSIZE=128 +CONFIG_DEV_PIPE_SIZE=128 +CONFIG_DEV_URANDOM=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBUV=y +CONFIG_LIBUV_PIPE=y +CONFIG_LIBUV_STREAM=y +CONFIG_MAX_TASKS=16 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PHOTON_DFU_BOOTLOADER=y +CONFIG_PHOTON_IWDG=y +CONFIG_PHOTON_WDG_THREAD=y +CONFIG_PIPES=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAMLOG_BUFSIZE=2048 +CONFIG_RAMLOG_OVERWRITE=y +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_IWDG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGHS=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_ADBD=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBADB=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USERMAIN_STACKSIZE=3072 +CONFIG_USER_ENTRYPOINT="adbd_main" diff --git a/boards/arm/stm32/photon/src/Make.defs b/boards/arm/stm32/photon/src/Make.defs index 7d9fe34102a..c8f79bdcdd0 100644 --- a/boards/arm/stm32/photon/src/Make.defs +++ b/boards/arm/stm32/photon/src/Make.defs @@ -77,6 +77,10 @@ ifneq ($(CONFIG_NSH_CUSTOMROMFS),y) endif endif +ifeq ($(CONFIG_USBDEV_COMPOSITE),y) +CSRCS += stm32_composite.c +endif + DEPPATH += --dep-path board VPATH += :board CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board) diff --git a/boards/arm/stm32/photon/src/stm32_bringup.c b/boards/arm/stm32/photon/src/stm32_bringup.c index 0335974c723..5ac7f9081b0 100644 --- a/boards/arm/stm32/photon/src/stm32_bringup.c +++ b/boards/arm/stm32/photon/src/stm32_bringup.c @@ -52,6 +52,10 @@ #include "photon.h" #include "stm32_wdg.h" +#ifdef CONFIG_USBADB +# include +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -60,10 +64,10 @@ * Name: stm32_bringup * * Description: - * Called either by board_initialize() if CONFIG_BOARD_LATE_INITIALIZE or by - * board_app_initialize if CONFIG_LIB_BOARDCTL is selected. This function - * initializes and configures all on-board features appropriate for the - * selected configuration. + * Called either by board_initialize() if CONFIG_BOARD_LATE_INITIALIZE or + * by board_app_initialize if CONFIG_LIB_BOARDCTL is selected. + * This function initializes and configures all on-board features + * appropriate for the selected configuration. * ****************************************************************************/ @@ -153,5 +157,26 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_USBDEV_COMPOSITE + +#ifndef CONFIG_BOARDCTL_USBDEVCTRL + ret = board_composite_initialize(0); + if (ret != OK) + { + syslog(LOG_ERR, "Failed to initialize composite: %d\n", ret); + return ret; + } + + if (board_composite_connect(0, 0) == NULL) + { + syslog(LOG_ERR, "Failed to connect composite: %d\n", ret); + return ret; + } +#endif /* !CONFIG_BOARDCTL_USBDEVCTRL */ +#else +#ifdef CONFIG_USBADB + usbdev_adb_initialize(); +#endif +#endif /* CONFIG_USBDEV_COMPOSITE */ return ret; } diff --git a/boards/arm/stm32/photon/src/stm32_composite.c b/boards/arm/stm32/photon/src/stm32_composite.c new file mode 100644 index 00000000000..7594a39aadb --- /dev/null +++ b/boards/arm/stm32/photon/src/stm32_composite.c @@ -0,0 +1,164 @@ +/**************************************************************************** + * boards/arm/stm32/photon/src/stm32_composite.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_composite0_connect + * + * Description: + * Connect the USB composite device on the specified USB device port for + * configuration 0. + * + * Input Parameters: + * port - The USB device port. + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +static FAR void *board_composite0_connect(int port) +{ + /* Here we are composing the configuration of the usb composite device. + * + * The standard is to use one CDC/ACM and one USB mass storage device. + */ + + /* Change "dev" array size to add more composite devs */ + + struct composite_devdesc_s dev[1]; + int ifnobase = 0; + int strbase = (COMPOSITE_NSTRIDS) - 1; + + int dev_idx = 0; + +#ifdef CONFIG_USBADB + /* Configure the ADB USB device */ + + /* Ask the adb driver to fill in the constants we didn't + * know here. + */ + + usbdev_adb_get_composite_devdesc(&dev[dev_idx]); + + /* Interfaces */ + + dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[dev_idx].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[dev_idx].devinfo.epno[USBADB_EP_BULKIN_IDX] = 1; + dev[dev_idx].devinfo.epno[USBADB_EP_BULKOUT_IDX] = 2; + + /* Count up the base numbers */ + + ifnobase += dev[dev_idx].devinfo.ninterfaces; + strbase += dev[dev_idx].devinfo.nstrings; + + dev_idx += 1; +#endif + + /* Add other composite devices here */ + + return composite_initialize(dev_idx, dev); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_composite_initialize + * + * Description: + * Perform architecture specific initialization of a composite USB device. + * + ****************************************************************************/ + +int board_composite_initialize(int port) +{ + return OK; +} + +/**************************************************************************** + * Name: board_composite_connect + * + * Description: + * Connect the USB composite device on the specified USB device port using + * the specified configuration. The interpretation of the configid is + * board specific. + * + * Input Parameters: + * port - The USB device port. + * configid - The USB composite configuration + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +FAR void *board_composite_connect(int port, int configid) +{ + if (configid == 0) + { + return board_composite0_connect(port); + } + + return NULL; +} + +#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_boot.c b/boards/arm/stm32/stm32butterfly2/src/stm32_boot.c index a7d90d43ec6..eeeac7f90cb 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_boot.c +++ b/boards/arm/stm32/stm32butterfly2/src/stm32_boot.c @@ -1,4 +1,4 @@ -/***************************************************************************** +/**************************************************************************** * boards/arm/stm32/stm32butterfly2/src/boot.c * * Copyright (C) 2016 Michał Łyszczek. All rights reserved. @@ -32,7 +32,7 @@ * POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Included Files ****************************************************************************/ @@ -42,11 +42,11 @@ #include "stm32_butterfly2.h" -/***************************************************************************** +/**************************************************************************** * Public Functions ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Name: stm32_boardinitialize * * Description: @@ -60,7 +60,7 @@ void stm32_boardinitialize(void) stm32_usb_initialize(); } -/***************************************************************************** +/**************************************************************************** * Name: board_app_initialize * * Description: @@ -78,7 +78,7 @@ int board_app_initialize(uintptr_t arg) ret = stm32_mmcsd_initialize(CONFIG_NSH_MMCSDMINOR); if (ret < 0) { - syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", ret); + syslog(LOG_ERR, "Failed to initialize SD slot: %d\n", ret); return ret; } #endif diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_spi.c b/boards/arm/stm32/stm32butterfly2/src/stm32_spi.c index 5eb35e729f5..2386fd4cc40 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_spi.c +++ b/boards/arm/stm32/stm32butterfly2/src/stm32_spi.c @@ -1,4 +1,4 @@ -/***************************************************************************** +/**************************************************************************** * boards/arm/stm32/stm32butterfly2/src/stm32_spi.c * * Copyright (C) 2016 Michał Łyszczek. All rights reserved. @@ -32,10 +32,11 @@ * POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Included Files ****************************************************************************/ +#include #include #include @@ -43,11 +44,11 @@ #include "stm32_gpio.h" #include "stm32_spi.h" -/***************************************************************************** +/**************************************************************************** * Public Functions ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Name: stm32_spidev_initialize * * Description: @@ -66,7 +67,7 @@ void stm32_spidev_initialize(void) stm32_configgpio(GPIO_SD_CD); } -/***************************************************************************** +/**************************************************************************** * Name: stm32_spi1select * * Description: @@ -76,7 +77,8 @@ void stm32_spidev_initialize(void) void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool select) { - spiinfo("INFO: Selecting spi dev: %d, state: %d\n", devid, select); + spiinfo("INFO: Selecting spi dev: %" PRId32 ", state: %d\n", + devid, select); if (devid == SPIDEV_MMCSD(0)) { @@ -84,7 +86,7 @@ void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, } } -/***************************************************************************** +/**************************************************************************** * Name: stm32_spi1status * * Description: @@ -93,7 +95,7 @@ void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) { - spiinfo("INFO: Requesting info from spi dev: %d\n", devid); + spiinfo("INFO: Requesting info from spi dev: %" PRId32 "\n", devid); if (devid == SPIDEV_MMCSD(0)) { diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c index e965a440d44..67a8f288f74 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c +++ b/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -492,10 +493,10 @@ int highpri_main(int argc, char *argv[]) g_highpri.lock = true; #ifndef CONFIG_STM32_ADC1_DMA - printf("%d [%d] %0.3fV\n", g_highpri.cntr1, g_highpri.current, + printf("%" PRId32 " [%d] %0.3fV\n", g_highpri.cntr1, g_highpri.current, g_highpri.r_volt[g_highpri.current]); #else - printf("%d ", g_highpri.cntr1); + printf("%" PRId32 " ", g_highpri.cntr1); for (i = 0; i < REG_NCHANNELS; i += 1) { @@ -508,7 +509,7 @@ int highpri_main(int argc, char *argv[]) #ifdef HIGHPRI_HAVE_INJECTED /* Print data from injected channels */ - printf("%d ", g_highpri.cntr2); + printf("%" PRId32 " ", g_highpri.cntr2); for (i = 0; i < INJ_NCHANNELS; i += 1) { diff --git a/boards/arm/stm32/stm32ldiscovery/Kconfig b/boards/arm/stm32/stm32ldiscovery/Kconfig index ea61f463bfd..a78d6e1be52 100644 --- a/boards/arm/stm32/stm32ldiscovery/Kconfig +++ b/boards/arm/stm32/stm32ldiscovery/Kconfig @@ -3,7 +3,7 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -if ARCH_BOARD_STM32FL_DISCOVERY +if ARCH_BOARD_STM32L_DISCOVERY config STM32LDISCO_QETIMER int "Timer to use with QE encoder" diff --git a/boards/arm/stm32/stm32ldiscovery/README.txt b/boards/arm/stm32/stm32ldiscovery/README.txt index 0dd15ee5fd6..7fdfdae3199 100644 --- a/boards/arm/stm32/stm32ldiscovery/README.txt +++ b/boards/arm/stm32/stm32ldiscovery/README.txt @@ -199,8 +199,8 @@ LEDs These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is defined. In that case, the usage by the board port is defined in - include/board.h and src/up_leds.c. The LEDs are used to encode OS-related - events as follows: + include/board.h and src/stm32_autoleds.c. The LEDs are used to encode + OS-related events as follows: SYMBOL Meaning LED state LED3 LED4 diff --git a/boards/arm/stm32/stm32ldiscovery/include/board.h b/boards/arm/stm32/stm32ldiscovery/include/board.h index 5f459e6f6ee..46f3b70d92a 100644 --- a/boards/arm/stm32/stm32ldiscovery/include/board.h +++ b/boards/arm/stm32/stm32ldiscovery/include/board.h @@ -52,19 +52,22 @@ * Pre-processor Definitions ****************************************************************************/ -/* Clocking *************************************************************************/ -/* Four different clock sources can be used to drive the system clock (SYSCLK): +/* Clocking *****************************************************************/ + +/* Four different clock sources can be used to drive the system clock + * (SYSCLK): * * - HSI high-speed internal oscillator clock * Generated from an internal 16 MHz RC oscillator * - HSE high-speed external oscillator clock - * Normally driven by an external crystal (X3). However, this crystal is not fitted - * on the STM32L-Discovery board. + * Normally driven by an external crystal (X3). However, this crystal is + * not fitted on the STM32L-Discovery board. * - PLL clock * - MSI multispeed internal oscillator clock - * The MSI clock signal is generated from an internal RC oscillator. Seven frequency - * ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz, - * 2.097 MHz (default value) and 4.194 MHz. + * The MSI clock signal is generated from an internal RC oscillator. + * Seven frequency ranges are available: 65.536 kHz, 131.072 kHz, + * 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and + * 4.194 MHz. * * The devices have the following two secondary clock sources * - LSI low-speed internal RC clock @@ -95,13 +98,15 @@ * MHz frequency. This is required to provide a 48 MHz clock to the USB or * SDIO (SDIOCLK or USBCLK = PLLVCO/2). * SYSCLK - * The system clock is derived from the PLL VCO divided by the output division factor. + * The system clock is derived from the PLL VCO divided by the output + * division factor. * Limitations: * 96 MHz as PLLVCO when the product is in range 1 (1.8V), * 48 MHz as PLLVCO when the product is in range 2 (1.5V), * 24 MHz when the product is in range 3 (1.2V). * Output division to avoid exceeding 32 MHz as SYSCLK. - * The minimum input clock frequency for PLL is 2 MHz (when using HSE as PLL source). + * The minimum input clock frequency for PLL is 2 MHz (when using HSE as + * PLL source). */ #define STM32_CFGR_PLLSRC 0 /* Source is 16MHz HSI */ @@ -115,8 +120,8 @@ # define STM32_PLL_FREQUENCY (4*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 64MHz */ #endif -/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output - * frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). +/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO + * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). */ #define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ @@ -159,23 +164,25 @@ #define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) -/* LED definitions ******************************************************************/ +/* LED definitions **********************************************************/ + /* The STM32L-Discovery board has four LEDs. Two of these are controlled by * logic on the board and are not available for software control: * - * LD1 COM: LD2 default status is red. LD2 turns to green to indicate that - * communications are in progress between the PC and the ST-LINK/V2. + * LD1 COM: LD2 default status is red. LD2 turns to green to indicate + * that communications are in progress between the PC and the + * ST-LINK/V2. * LD2 PWR: Red LED indicates that the board is powered. * * And two LEDs can be controlled by software: * - * User LD3: Green LED is a user LED connected to the I/O PB7 of the STM32L152 - * MCU. - * User LD4: Blue LED is a user LED connected to the I/O PB6 of the STM32L152 - * MCU. + * User LD3: Green LED is a user LED connected to the I/O PB7 of the + * STM32L152 MCU. + * User LD4: Blue LED is a user LED connected to the I/O PB6 of the + * STM32L152 MCU. * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any - * way. The following definitions are used to access individual LEDs. + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. */ /* LED index values for use with board_userled() */ @@ -189,8 +196,9 @@ #define BOARD_LED1_BIT (1 << BOARD_LED1) #define BOARD_LED2_BIT (1 << BOARD_LED2) -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on board the - * STM32L-Discovery. The following definitions describe how NuttX controls the LEDs: +/* If CONFIG_ARCH_LEDS is defined, then NuttX will control the 2 LEDs on + * board the STM32L-Discovery. The following definitions describe how NuttX + * controls the LEDs: * * SYMBOL Meaning LED state * LED1 LED2 @@ -215,12 +223,14 @@ #define LED_ASSERTION 2 #define LED_PANIC 3 -/* Button definitions ***************************************************************/ -/* The STM32L-Discovery supports two buttons; only one button is controllable by - * software: +/* Button definitions *******************************************************/ + +/* The STM32L-Discovery supports two buttons; only one button is controllable + * by software: * - * B1 USER: user and wake-up button connected to the I/O PA0 of the STM32L152RBT6. - * B2 RESET: pushbutton connected to NRST is used to RESET the STM32L152RBT6. + * B1 USER: user and wake-up button connected to the I/O PA0 of the + * STM32L152. + * B2 RESET: pushbutton connected to NRST is used to RESET the STM32L152. */ #define BUTTON_USER 0 @@ -228,11 +238,12 @@ #define BUTTON_USER_BIT (1 << BUTTON_USER) -/* Alternate Pin Functions **********************************************************/ -/* The STM32L-Discovery has no on-board RS-232 driver. Further, there are no USART - * pins that do not conflict with the on board resources, in particular, the LCD: - * Most USART pins are available if the LCD is enabled; USART2 may be used if either - * the LCD or the on-board LEDs are disabled. +/* Alternate Pin Functions **************************************************/ + +/* The STM32L-Discovery has no on-board RS-232 driver. Further, there + * are no USART pins that do not conflict with the on board resources, in + * particular, the LCD. Most USART pins are available if the LCD is enabled; + * USART2 may be used if either the LCD or the on-board LEDs are disabled. * * PA9 USART1_TX LCD glass COM1 P2, pin 22 * PA10 USART1_RX LCD glass COM2 P2, pin 21 diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_appinit.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_appinit.c index a20a0c4c5a0..0bd7f814b3d 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_appinit.c +++ b/boards/arm/stm32/stm32ldiscovery/src/stm32_appinit.c @@ -39,8 +39,6 @@ #include -#include - #include #include @@ -77,7 +75,11 @@ int board_app_initialize(uintptr_t arg) { +#ifndef CONFIG_BOARD_LATE_INITIALIZE /* Perform board initialization here */ return stm32_bringup(); +#else + return OK; +#endif } diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c index db59e10e5c0..2c6157c1ab2 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c +++ b/boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c @@ -55,7 +55,8 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on + +/* If CONFIG_ARCH_LEDS is defined, then NuttX will control the 2 LEDs on * board the STM32L-Discovery. The following definitions describe how NuttX * controls the LEDs: * diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c index 1158c0bf986..8aa7f0edc91 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c +++ b/boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c @@ -47,14 +47,6 @@ #include "arm_arch.h" #include "stm32ldiscovery.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -63,16 +55,17 @@ * Name: stm32_boardinitialize * * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. * ****************************************************************************/ void stm32_boardinitialize(void) { - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function - * stm32_spidev_initialize() has been brought into the link. + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. */ #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) @@ -93,22 +86,23 @@ void stm32_boardinitialize(void) * Name: board_late_initialize * * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional initialization call - * will be performed in the boot-up sequence to a function called - * board_late_initialize(). board_late_initialize() will be called immediately after - * up_initialize() is called and just before the initial application is started. - * This additional initialization phase may be used, for example, to initialize - * board-specific device drivers. + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. * ****************************************************************************/ #ifdef CONFIG_BOARD_LATE_INITIALIZE void board_late_initialize(void) { -#ifndef CONFIG_LIB_BOARDCTL - /* Perform board initialization here instead of from the board_app_initialize(). */ + /* Perform board initialization here instead of from the + * board_app_initialize(). + */ stm32_bringup(); -#endif } #endif diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c index ad6d370a764..13ce8c9309d 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c +++ b/boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c @@ -39,17 +39,20 @@ #include +#include +#include #include -#include #include +#include +#include #include #include "stm32ldiscovery.h" #ifdef CONFIG_SENSORS_QENCODER -#include "board_qencoder.h" +# include "board_qencoder.h" #endif /**************************************************************************** @@ -74,7 +77,34 @@ int stm32_bringup(void) { int ret = OK; +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#if defined(CONFIG_USERLED) && !defined(CONFIG_ARCH_LEDS) +#ifdef CONFIG_USERLED_LOWER + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#else + /* Enable USER LED support for some other purpose */ + + board_userled_initialize(); +#endif /* CONFIG_USERLED_LOWER */ +#endif /* CONFIG_USERLED && !CONFIG_ARCH_LEDS */ + #ifdef CONFIG_BUTTONS +#ifdef CONFIG_BUTTONS_LOWER /* Register the BUTTON driver */ ret = btn_lower_initialize("/dev/buttons"); @@ -82,7 +112,12 @@ int stm32_bringup(void) { syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); } -#endif +#else + /* Enable BUTTON support for some other purpose */ + + board_button_initialize(); +#endif /* CONFIG_BUTTONS_LOWER */ +#endif /* CONFIG_BUTTONS */ #ifdef CONFIG_STM32_LCD /* Initialize the SLCD and register the SLCD device as /dev/slcd0 */ diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h b/boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h index 8e98af08d00..fbc68e26ecd 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h +++ b/boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h @@ -34,8 +34,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_STM32F3DISCOVERY_SRC_STM32F3DISCOVERY_H -#define __BOARDS_ARM_STM32_STM32F3DISCOVERY_SRC_STM32F3DISCOVERY_H +#ifndef __BOARDS_ARM_STM32_STM32LDISCOVERY_SRC_STM32LDISCOVERY_H +#define __BOARDS_ARM_STM32_STM32LDISCOVERY_SRC_STM32LDISCOVERY_H /**************************************************************************** * Included Files @@ -289,4 +289,4 @@ int stm32_pwm_setup(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32_STM32F3DISCOVERY_SRC_STM32F3DISCOVERY_H */ +#endif /* __BOARDS_ARM_STM32_STM32LDISCOVERY_SRC_STM32LDISCOVERY_H */ diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c index 06b0083f785..3eed410dc00 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c +++ b/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -175,8 +176,9 @@ int highpri_main(int argc, char *argv[]) g_highpri.dev = dev; prescaler = STM32_TIM_SETCLOCK(dev, CONFIG_VIEWTOOL_TIM6_FREQUENCY); - printf("TIM6 CLKIN=%d Hz, Frequency=%d Hz, prescaler=%d\n", - STM32_APB1_TIM6_CLKIN, CONFIG_VIEWTOOL_TIM6_FREQUENCY, prescaler); + printf("TIM6 CLKIN=%jd Hz, Frequency=%d Hz, prescaler=%d\n", + (uintmax_t)STM32_APB1_TIM6_CLKIN, CONFIG_VIEWTOOL_TIM6_FREQUENCY, + prescaler); STM32_TIM_SETPERIOD(dev, CONFIG_VIEWTOOL_TIM6_PERIOD); printf("TIM6 period=%d cyles; interrupt rate=%d Hz\n", @@ -233,7 +235,7 @@ int highpri_main(int argc, char *argv[]) /* Then print out what is happening */ - printf("Elapsed time: %d seconds\n\n", seconds); + printf("Elapsed time: %" PRId32 " seconds\n\n", seconds); for (i = 0, total = 0; i < 16; i++) { total += basepri[i]; diff --git a/boards/arm/stm32h7/nucleo-h743zi/Kconfig b/boards/arm/stm32h7/nucleo-h743zi/Kconfig index 58dcb157885..c648632e492 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/Kconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/Kconfig @@ -5,4 +5,42 @@ if ARCH_BOARD_NUCLEO_H743ZI +choice + prompt "STM Nucleo-144 Board Variant" + default STM_NUCLEO144_MB1364 + +config STM_NUCLEO144_MB1364 + bool "Nucleo-H743ZI2 (MB1364)" + ---help--- + This is the current version of the Nucelo-144 for the H743ZI + +config STM_NUCLEO144_MB1137 + bool "Nucleo-H743ZI (MB1137)" + ---help--- + This is the origional version of the Nucelo-144 for the H743ZI + +endchoice + +config STM32_ROMFS + bool "Automount baked-in ROMFS image" + default n + depends on FS_ROMFS + ---help--- + Select STM32_ROMFS_IMAGEFILE, STM32_ROMFS_DEV_MINOR, STM32_ROMFS_MOUNTPOINT + +config STM32_ROMFS_DEV_MINOR + int "Minor for the block device backing the data" + depends on STM32_ROMFS + default 64 + +config STM32_ROMFS_MOUNTPOINT + string "Mountpoint of the custom romfs image" + depends on STM32_ROMFS + default "/rom" + +config STM32_ROMFS_IMAGEFILE + string "ROMFS image file to include into build" + depends on STM32_ROMFS + default "../../../rom.img" + endif # ARCH_BOARD_NUCLEO_H743ZI diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig new file mode 100644 index 00000000000..f6f8068aee1 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_DTCMEXCLUDE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-h743zi" +CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H743ZI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARDCTL_APP_SYMTAB=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ELF=y +CONFIG_EXAMPLES_ELF=y +CONFIG_EXECFUNCS_HAVE_SYMTAB=y +CONFIG_EXECFUNCS_SYSTEM_SYMTAB=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INTELHEX_BINARY=y +CONFIG_MAX_TASKS=16 +CONFIG_MM_REGIONS=4 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PIPES=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_USART3=y +CONFIG_STM32_ROMFS=y +CONFIG_STM32_ROMFS_IMAGEFILE="../../apps/examples/elf/tests/romfs.img" +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig new file mode 100644 index 00000000000..a1107cf433a --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig @@ -0,0 +1,90 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-h743zi" +CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H743ZI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETH0_PHY_LAN8742A=y +CONFIG_FAT_LCNAMES=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MAX_TASKS=16 +CONFIG_MM_REGIONS=4 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETUTILS_DISCOVER=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_ARP_SEND=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1500 +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_IGMP=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_ROUTE=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_ETHMAC=y +CONFIG_STM32H7_OTGFS=y +CONFIG_STM32H7_PHYSR=31 +CONFIG_STM32H7_PHYSR_100FD=0x0018 +CONFIG_STM32H7_PHYSR_100HD=0x0008 +CONFIG_STM32H7_PHYSR_10FD=0x0014 +CONFIG_STM32H7_PHYSR_10HD=0x0004 +CONFIG_STM32H7_PHYSR_ALTCONFIG=y +CONFIG_STM32H7_PHYSR_ALTMODE=0x001c +CONFIG_STM32H7_USART3=y +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBHOST=y +CONFIG_USBHOST_MSC=y +CONFIG_USBHOST_MSC_NOTIFIER=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig index 17d3987fe33..d0f88553a0e 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig @@ -27,7 +27,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y CONFIG_MAX_TASKS=16 -CONFIG_MM_REGIONS=3 +CONFIG_MM_REGIONS=4 CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig index 20bdd7a4285..8c38126d9c1 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig @@ -39,7 +39,7 @@ CONFIG_LCD_MAXCONTRAST=255 CONFIG_LCD_SH1106_OLED_132=y CONFIG_LCD_SSD1306_I2C=y CONFIG_MAX_TASKS=16 -CONFIG_MM_REGIONS=3 +CONFIG_MM_REGIONS=4 CONFIG_MQ_MAXMSGSIZE=128 CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig new file mode 100644 index 00000000000..5ff752662b5 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-h743zi" +CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H743ZI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FAT_LCNAMES=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MAX_TASKS=16 +CONFIG_MM_REGIONS=4 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_OTGFS=y +CONFIG_STM32H7_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBHOST=y +CONFIG_USBHOST_INT_DISABLE=y +CONFIG_USBHOST_MSC=y +CONFIG_USBHOST_MSC_NOTIFIER=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig index 726f6ec49f9..8a2b5a7d11e 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig @@ -27,7 +27,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y CONFIG_MAX_TASKS=16 -CONFIG_MM_REGIONS=3 +CONFIG_MM_REGIONS=4 CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/scripts/Make.defs b/boards/arm/stm32h7/nucleo-h743zi/scripts/Make.defs index fc4620c8000..7383b443617 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/scripts/Make.defs +++ b/boards/arm/stm32h7/nucleo-h743zi/scripts/Make.defs @@ -70,6 +70,18 @@ NXFLATLDFLAGS1 = -r -d -warn-common NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections LDNXFLATFLAGS = -e main -s 2048 +# ELF module definitions + +CELFFLAGS = $(CFLAGS) -mlong-calls # --target1-abs +CXXELFFLAGS = $(CXXFLAGS) -mlong-calls # --target1-abs + +LDELFFLAGS = -r -e main +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + LDELFFLAGS += -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld}" +else + LDELFFLAGS += -T $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld +endif + ifneq ($(CROSSDEV),arm-nuttx-elf-) LDFLAGS += -nostartfiles -nodefaultlibs endif diff --git a/boards/arm/stm32h7/nucleo-h743zi/scripts/gnu-elf.ld b/boards/arm/stm32h7/nucleo-h743zi/scripts/gnu-elf.ld new file mode 100644 index 00000000000..6175e44d400 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h743zi/scripts/gnu-elf.ld @@ -0,0 +1,126 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h743zi/scripts/gnu-elf.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +SECTIONS +{ + .text 0x00000000 : + { + _stext = . ; + *(.text) + *(.text.*) + *(.gnu.warning) + *(.stub) + *(.glue_7) + *(.glue_7t) + *(.jcr) + + /* C++ support: The .init and .fini sections contain specific logic + * to manage static constructors and destructors. + */ + + *(.gnu.linkonce.t.*) + *(.init) /* Old ABI */ + *(.fini) /* Old ABI */ + _etext = . ; + } + + .ARM.extab : + { + *(.ARM.extab*) + } + + .ARM.exidx : + { + *(.ARM.exidx*) + } + + .rodata : + { + _srodata = . ; + *(.rodata) + *(.rodata1) + *(.rodata.*) + *(.gnu.linkonce.r*) + _erodata = . ; + } + + .data : + { + _sdata = . ; + *(.data) + *(.data1) + *(.data.*) + *(.gnu.linkonce.d*) + . = ALIGN(4); + _edata = . ; + } + + /* C++ support. For each global and static local C++ object, + * GCC creates a small subroutine to construct the object. Pointers + * to these routines (not the routines themselves) are stored as + * simple, linear arrays in the .ctors section of the object file. + * Similarly, pointers to global/static destructor routines are + * stored in .dtors. + */ + + .ctors : + { + _sctors = . ; + *(.ctors) /* Old ABI: Unallocated */ + *(.init_array) /* New ABI: Allocated */ + _edtors = . ; + } + + .dtors : + { + _sdtors = . ; + *(.dtors) /* Old ABI: Unallocated */ + *(.fini_array) /* New ABI: Allocated */ + _edtors = . ; + } + + .bss : + { + _sbss = . ; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.b*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + } + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/Makefile b/boards/arm/stm32h7/nucleo-h743zi/src/Makefile index aaf5f497d58..fddb0919f20 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h743zi/src/Makefile @@ -51,6 +51,10 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif +ifeq ($(CONFIG_STM32_ROMFS),y) +CSRCS += stm32_romfs_initialize.c +endif + ifeq ($(CONFIG_STM32H7_SPI),y) CSRCS += stm32_spi.c endif diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h b/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h index 19720229ada..fd84a4ac3e6 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h +++ b/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h @@ -52,6 +52,38 @@ /* Configuration ************************************************************/ +#define HAVE_PROC 1 +#define HAVE_USBDEV 1 +#define HAVE_USBHOST 1 +#define HAVE_USBMONITOR 1 + +/* Can't support USB host or device features if USB OTG FS is not enabled */ + +#ifndef CONFIG_STM32H7_OTGFS +# undef HAVE_USBDEV +# undef HAVE_USBHOST +# undef HAVE_USBMONITOR +#endif + +/* Can't support USB device monitor if USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +# undef HAVE_USBMONITOR +#endif + +/* Can't support USB host is USB host is not enabled */ + +#ifndef CONFIG_USBHOST +# undef HAVE_USBHOST +#endif + +/* Check if we should enable the USB monitor before starting NSH */ + +#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_USBMONITOR) +# undef HAVE_USBMONITOR +#endif + /* procfs File System */ #ifdef CONFIG_FS_PROCFS @@ -112,8 +144,13 @@ #define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \ GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9) -#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \ +#if defined(CONFIG_STM_NUCLEO144_MB1137) +# define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \ GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN6) +#elif defined(CONFIG_STM_NUCLEO144_MB1364) +# define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \ + GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN10) +#endif #ifdef CONFIG_USBHOST # define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_EXTI|GPIO_FLOAT| \ @@ -234,12 +271,26 @@ int stm32_gpio_initialize(void); * * Description: * Called from stm32_usbinitialize very early in inialization to setup - * USB-related GPIO pins for the nucleo-144 board. + * USB-related GPIO pins for the NUCLEO-H743ZI board. * ****************************************************************************/ #ifdef CONFIG_STM32H7_OTGFS -void stm32_usbinitialize(void); +void weak_function stm32_usbinitialize(void); +#endif + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. This function will start a thread that will monitor for + * device connection/disconnection events. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +int stm32_usbhost_initialize(void); #endif /**************************************************************************** diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c index 331ea00fd44..f49d3d00154 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c @@ -44,6 +44,14 @@ #include #include +#ifdef CONFIG_USBMONITOR +#include +#endif + +#ifdef CONFIG_STM32H7_OTGFS +#include "stm32_usbhost.h" +#endif + #include "nucleo-h743zi.h" #ifdef CONFIG_BUTTONS @@ -55,6 +63,10 @@ # include "stm32_rtc.h" #endif +#ifdef CONFIG_STM32_ROMFS +# include "stm32_romfs.h" +#endif + #include "stm32_gpio.h" /**************************************************************************** @@ -132,7 +144,8 @@ static void stm32_i2ctool(void) * CONFIG_BOARD_LATE_INITIALIZE=y : * Called from board_late_initialize(). * - * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y && CONFIG_NSH_ARCHINIT: + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y && + * CONFIG_NSH_ARCHINIT: * Called from the NSH library * ****************************************************************************/ @@ -170,6 +183,17 @@ int stm32_bringup(void) } #endif /* CONFIG_FS_PROCFS */ +#ifdef CONFIG_STM32_ROMFS + /* Mount the romfs partition */ + + ret = stm32_romfs_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); + } +#endif + #ifdef HAVE_RTC_DRIVER /* Instantiate the STM32 lower-half RTC driver */ @@ -206,6 +230,33 @@ int stm32_bringup(void) } #endif /* CONFIG_BUTTONS */ +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() + * starts a thread will monitor for USB connection and + * disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize USB host: %d\n", + ret); + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to start USB monitor: %d\n", + ret); + } +#endif + #ifdef CONFIG_ADC /* Initialize ADC and register the ADC driver. */ @@ -231,7 +282,8 @@ int stm32_bringup(void) ret = stm32_lsm6dsl_initialize("/dev/lsm6dsl0"); if (ret < 0) { - syslog(LOG_ERR, "ERROR: Failed to initialize LSM6DSL driver: %d\n", ret); + syslog(LOG_ERR, "ERROR: Failed to initialize LSM6DSL driver: %d\n", + ret); } #endif /* CONFIG_SENSORS_LSM6DSL */ @@ -239,7 +291,8 @@ int stm32_bringup(void) ret = stm32_lsm9ds1_initialize(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: Failed to initialize LSM9DS1 driver: %d\n", ret); + syslog(LOG_ERR, "ERROR: Failed to initialize LSM9DS1 driver: %d\n", + ret); } #endif /* CONFIG_SENSORS_LSM6DSL */ @@ -247,7 +300,8 @@ int stm32_bringup(void) ret = stm32_lsm303agr_initialize("/dev/lsm303mag0"); if (ret < 0) { - syslog(LOG_ERR, "ERROR: Failed to initialize LSM303AGR driver: %d\n", ret); + syslog(LOG_ERR, "ERROR: Failed to initialize LSM303AGR driver: %d\n", + ret); } #endif /* CONFIG_SENSORS_LSM303AGR */ @@ -265,7 +319,8 @@ int stm32_bringup(void) ret = stm32_wlinitialize(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", ret); + syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", + ret); } #endif /* CONFIG_WL_NRF24L01 */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs.h b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs.h new file mode 100644 index 00000000000..7ad7c718100 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs.h @@ -0,0 +1,61 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32H7_NUCLEOH743ZI_SRC_STM32_ROMFS_H +#define __BOARDS_ARM_STM32H7_NUCLEOH743ZI_SRC_STM32_ROMFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_STM32_ROMFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ROMFS_SECTOR_SIZE 64 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_romfs_initialize + * + * Description: + * Registers built-in ROMFS image as block device and mounts it. + * + * Returned Value: + * Zero (OK) on success, a negated errno value on error. + * + * Assumptions/Limitations: + * Memory addresses [&romfs_data_begin .. &romfs_data_begin) should contain + * ROMFS volume data, as included in the assembly snippet above (l. 84). + * + ****************************************************************************/ + +int stm32_romfs_initialize(void); + +#endif /* CONFIG_STM32_ROMFS */ + +#endif /* __BOARDS_ARM_STM32H7_NUCLEOH743ZI_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs_initialize.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs_initialize.c new file mode 100644 index 00000000000..661937758e1 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs_initialize.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs_initialize.c + * This file provides contents of an optional ROMFS volume, mounted at boot. + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include "stm32_romfs.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_ROMFS +# error "CONFIG_STM32_ROMFS must be defined" +#else + +#ifndef CONFIG_STM32_ROMFS_IMAGEFILE +# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" +#endif + +#ifndef CONFIG_STM32_ROMFS_DEV_MINOR +# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" +#endif + +#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT +# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" +#endif + +#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) + +#define STR2(m) #m +#define STR(m) STR2(m) + +#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) +#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +__asm__ ( + " .section .rodata \n" + " .balign 16 \n" + " .globl romfs_data_begin \n" + "romfs_data_begin: \n" + " .incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE)"\n" + " .balign " STR(ROMFS_SECTOR_SIZE) "\n" + " .globl romfs_data_end \n" + "romfs_data_end: \n" + " .globl romfs_data_size \n" + "romfs_data_size: \n" + " .word romfs_data_end - romfs_data_begin \n" + ); + +extern const char romfs_data_begin; +extern const char romfs_data_end; +extern const int romfs_data_size; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_romfs_initialize + * + * Description: + * Registers the aboveincluded binary file as block device. + * Then mounts the block device as ROMFS filesystems. + * + * Returned Value: + * Zero (OK) on success, a negated errno value on error. + * + * Assumptions/Limitations: + * Memory addresses [&romfs_data_begin .. &romfs_data_begin) should contain + * ROMFS volume data, as included in the assembly snippet above (l. 84). + * + ****************************************************************************/ + +int stm32_romfs_initialize(void) +{ + uintptr_t romfs_data_len; + int ret; + + /* Create a ROM disk for the /etc filesystem */ + + romfs_data_len = (uintptr_t)&romfs_data_end - (uintptr_t)&romfs_data_begin; + + ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, &romfs_data_begin, + NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); + if (ret < 0) + { + ferr("ERROR: romdisk_register failed: %d\n", -ret); + return ret; + } + + /* Mount the file system */ + + finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", + CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); + + ret = mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, + "romfs", MS_RDONLY, NULL); + if (ret < 0) + { + ferr("ERROR: mount(%s,%s,romfs) failed: %d\n", + MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, errno); + return ret; + } + + return OK; +} + +#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_ssd1306.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_ssd1306.c index 372a3240802..e5c0b9e1229 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_ssd1306.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_ssd1306.c @@ -84,7 +84,7 @@ FAR struct lcd_dev_s *board_lcd_getdev(int devno) g_lcddev = ssd1306_initialize(g_i2c, NULL, devno); if (!g_lcddev) { - lcderr("ERROR: Failed to bind I2C port 1 to OLED %d: %d\n", devno); + lcderr("ERROR: Failed to bind I2C port 1 to OLED %d\n", devno); } else { diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c index ba4bb9dd447..c7ce67cf41c 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c @@ -273,9 +273,15 @@ void stm32_usbhost_vbusdrive(int iface, bool enable) { DEBUGASSERT(iface == 0); - /* Set the Power Switch by driving the active low enable pin */ + /* Set the Power Switch by driving the active high enable pin */ +#if defined(CONFIG_STM_NUCLEO144_MB1137) + stm32_gpiowrite(GPIO_OTGFS_PWRON, enable); +#elif defined(CONFIG_STM_NUCLEO144_MB1364) stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable); +#else +# error "Non-supported board" +#endif } #endif diff --git a/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig b/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig index 3263732e6e9..cdc9a428743 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig @@ -27,7 +27,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INTELHEX_BINARY=y CONFIG_MAX_TASKS=16 -CONFIG_MM_REGIONS=3 +CONFIG_MM_REGIONS=4 CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/sim/sim/sim/configs/bluetooth/defconfig b/boards/sim/sim/sim/configs/bluetooth/defconfig index 60c9f302592..dfd3dbc3bef 100644 --- a/boards/sim/sim/sim/configs/bluetooth/defconfig +++ b/boards/sim/sim/sim/configs/bluetooth/defconfig @@ -16,7 +16,6 @@ CONFIG_ARCH_SIM=y CONFIG_BLUETOOTH_MAX_CONN=2 CONFIG_BLUETOOTH_MAX_PAIRED=2 CONFIG_BLUETOOTH_NULL=y -CONFIG_BLUETOOTH_SMP_SELFTEST=y CONFIG_BOARDCTL_POWEROFF=y CONFIG_BOARD_LOOPSPERMSEC=0 CONFIG_BOOT_RUNFROMEXTSRAM=y diff --git a/boards/sim/sim/sim/configs/cxxtest/Make.defs b/boards/sim/sim/sim/configs/cxxtest/Make.defs deleted file mode 100644 index 7959db2203c..00000000000 --- a/boards/sim/sim/sim/configs/cxxtest/Make.defs +++ /dev/null @@ -1,144 +0,0 @@ -############################################################################ -# boards/sim/sim/sim/configs/cxxtest/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk - -HOSTOS = ${shell uname -o 2>/dev/null || uname -s 2>/dev/null || echo "Other"} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -g -endif - -ifneq ($(CONFIG_DEBUG_NOOPT),y) - ARCHOPTIMIZATION += -O2 -fno-strict-aliasing -endif - -ARCHCPUFLAGS = -fno-builtin -ifeq ($(CONFIG_CXX_EXCEPTION),y) - ARCHCPUFLAGSXX = -fno-builtin -else - ARCHCPUFLAGSXX = -fno-builtin -fno-exceptions -fcheck-new -endif -ARCHPICFLAGS = -fpic -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHWARNINGSXX = -Wall -Wshadow -Wundef - -# Add -fno-common because macOS "ld -r" doesn't seem to pick objects -# for common symbols. -ARCHCPUFLAGS += -fno-common -ARCHCPUFLAGSXX += -fno-common - -ifeq ($(CONFIG_SIM_M32),y) - ARCHCPUFLAGS += -m32 - ARCHCPUFLAGSXX += -m32 -endif - -CC = $(CROSSDEV)cc -CXX = $(CROSSDEV)c++ -CPP = $(CROSSDEV)cc -E -LD = $(CROSSDEV)ld -ifeq ($(CONFIG_HOST_MACOS),y) -STRIP = $(CROSSDEV)strip -AR = $(TOPDIR)/tools/macar-rcs.sh -else -STRIP = $(CROSSDEV)strip --strip-unneeded -AR = $(CROSSDEV)ar rcs -endif -NM = $(CROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -CFLAGS := $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -CXXFLAGS := $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGSXX) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -# Loadable module definitions - -CMODULEFLAGS = $(CFLAGS) -# -fno-pic to avoid GOT relocations -CMODULEFLAGS += -fno-pic -ifeq ($(CONFIG_LIBC_ARCH_ELF_64BIT),y) - # For amd64: - # It seems macOS/x86_64 loads the program text around 00000001_xxxxxxxx. - # The gcc default (-mcmodel=small) would produce out-of-range 32-bit - # relocations. - # Even on Linux, NuttX modules are loaded into the NuttX heap, which - # can be out of range with -mcmodel=small. - CMODULEFLAGS += -mcmodel=large -endif -# On Linux, we (ab)use the host compiler to compile binaries for NuttX. -# Explicitly disable features which might be default on the host while -# not available on NuttX. -CMODULEFLAGS += -fno-stack-protector - -LDMODULEFLAGS = -r -e module_initialize -ifeq ($(CONFIG_CYGWIN_WINTOOL),y) - LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}" -else - LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld -endif - -# NuttX modules are ELF binaries. -# Non-ELF platforms like macOS need to use a separate ELF toolchain. -ifeq ($(CONFIG_HOST_MACOS),y) - # eg. brew install x86_64-elf-gcc - MODULECC = x86_64-elf-gcc - MODULELD = x86_64-elf-ld - MODULESTRIP = x86_64-elf-strip --strip-unneeded -endif - -# ELF module definitions - -CELFFLAGS = $(CFLAGS) -CXXELFFLAGS = $(CXXFLAGS) -# -fno-pic to avoid GOT relocations -CELFFLAGS += -fno-pic -CXXELFFLAGS += -fno-pic - -LDELFFLAGS = -r -e main -ifeq ($(CONFIG_CYGWIN_WINTOOL),y) - LDELFFLAGS += -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld}" -else - LDELFFLAGS += -T $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld -endif - -LDLINKFLAGS = $(ARCHSCRIPT) # Link flags used with $(LD) -CCLINKFLAGS = $(ARCHSCRIPT) # Link flags used with $(CC) -LDFLAGS = $(ARCHSCRIPT) # For backward compatibility, same as CCLINKFLAGS - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - CCLINKFLAGS += -g -endif - -ifeq ($(CONFIG_SIM_M32),y) - LDLINKFLAGS += -melf_i386 - CCLINKFLAGS += -m32 - LDFLAGS += -m32 - LDMODULEFLAGS += -melf_i386 - LDELFFLAGS += -melf_i386 - HOSTLDFLAGS += -m32 -endif - -HOSTCFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGS) $(HOSTINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe diff --git a/boards/sim/sim/sim/configs/libcxxtest/defconfig b/boards/sim/sim/sim/configs/libcxxtest/defconfig new file mode 100644 index 00000000000..19d6155d388 --- /dev/null +++ b/boards/sim/sim/sim/configs/libcxxtest/defconfig @@ -0,0 +1,106 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_CXX_EXCEPTION is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="sim" +CONFIG_ARCH_BOARD="sim" +CONFIG_ARCH_BOARD_SIM=y +CONFIG_ARCH_CHIP="sim" +CONFIG_ARCH_SIM=y +CONFIG_BOARDCTL_APP_SYMTAB=y +CONFIG_BOARDCTL_POWEROFF=y +CONFIG_BOARD_LOOPSPERMSEC=0 +CONFIG_BOOT_RUNFROMEXTSRAM=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_BINFMT=y +CONFIG_DEBUG_BINFMT_ERROR=y +CONFIG_DEBUG_BINFMT_INFO=y +CONFIG_DEBUG_BINFMT_WARN=y +CONFIG_DEBUG_ERROR=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEBUG_WARN=y +CONFIG_DEV_LOOP=y +CONFIG_DEV_ZERO=y +CONFIG_DHCPC_RENEW_STACKSIZE=4096 +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_EXAMPLES_NETTEST=y +CONFIG_FSUTILS_PASSWD=y +CONFIG_FSUTILS_PASSWD_READONLY=y +CONFIG_FS_BINFS=y +CONFIG_FS_HOSTFS=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HOST_MACOS=y +CONFIG_IDLETHREAD_STACKSIZE=4096 +CONFIG_IOB_NOTIFIER=y +CONFIG_LIBCXX=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIB_ENVPATH=y +CONFIG_MAX_TASKS=64 +CONFIG_MM_FILL_ALLOCATIONS=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_IFINDEX=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDOWN_NOTIFIER=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NET_ARP_SEND=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_ICMPv6=y +CONFIG_NET_ICMPv6_AUTOCONF=y +CONFIG_NET_ICMPv6_NEIGHBOR=y +CONFIG_NET_ICMPv6_ROUTER=y +CONFIG_NET_ICMPv6_SOCKET=y +CONFIG_NET_IPv6=y +CONFIG_NET_LOCAL=y +CONFIG_NET_PROMISCUOUS=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_NOTIFIER=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_NOTIFIER=y +CONFIG_NFILE_DESCRIPTORS=32 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_ARCHROMFS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_NSH_ROMFSDEVNO=1 +CONFIG_NSH_ROMFSETC=y +CONFIG_PATH_INITIAL="/bin" +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=2048 +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RTC=y +CONFIG_RTC_ARCH=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_LPWORKSTACKSIZE=4096 +CONFIG_SCHED_ONEXIT=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_MONTH=6 +CONFIG_START_YEAR=2008 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_SYSLOG_CONSOLE=y +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_STACKSIZE=4096 +CONFIG_SYSTEM_PING=y +CONFIG_SYSTEM_PING_STACKSIZE=4096 +CONFIG_TESTING_CXXTEST=y +CONFIG_USERMAIN_STACKSIZE=4096 +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/sim/sim/sim/scripts/Make.defs b/boards/sim/sim/sim/scripts/Make.defs index 00d73caa442..ab2be781822 100644 --- a/boards/sim/sim/sim/scripts/Make.defs +++ b/boards/sim/sim/sim/scripts/Make.defs @@ -23,6 +23,24 @@ include $(TOPDIR)/tools/Config.mk HOSTOS = ${shell uname -o 2>/dev/null || uname -s 2>/dev/null || echo "Other"} +# NuttX is sometimes built as a native target. +# In that case, the __NuttX__ macro is predefined by the compiler. +# https://github.com/NuttX/buildroot +# +# In other cases, __NuttX__ is an ordinary user-definded macro. +# It's especially the case for NuttX sim, which is a target to run +# the entire NuttX as a program on the host OS, which can be Linux, +# macOS, Windows, etc. +# https://cwiki.apache.org/confluence/display/NUTTX/NuttX+Simulation +# In that case, the host OS compiler is used to build NuttX. +# Thus, eg. NuttX sim on macOS is built with __APPLE__. +# We #undef predefined macros for those possible host OSes here +# because the OS APIs this library should use are of NuttX, +# not the host OS. + +ARCHDEFINES += -U_AIX -U_WIN32 -U__APPLE__ -U__FreeBSD__ +ARCHDEFINES += -U__NetBSD__ -U__linux__ -U__sun__ -U__unix__ + ifeq ($(CONFIG_DEBUG_SYMBOLS),y) ARCHOPTIMIZATION = -g endif @@ -41,8 +59,8 @@ ifeq ($(CONFIG_CXX_EXCEPTION),) ARCHCPUFLAGSXX += -fno-exceptions endif ARCHPICFLAGS = -fpic -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHWARNINGS = -Wstrict-prototypes -Wundef +ARCHWARNINGSXX = -Wundef # Add -fvisibility=hidden # Because we don't want export nuttx's symbols to share libraries @@ -146,7 +164,7 @@ ifeq ($(CONFIG_SIM_M32),y) endif HOSTCFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGS) $(HOSTINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe + $(ARCHCPUFLAGS) $(HOSTINCLUDES) $(EXTRAFLAGS) -pipe ifeq ($(CONFIG_BT_LIBUSB),y) STDLIBS += -lusb-1.0 diff --git a/boards/xtensa/esp32/esp32-core/Kconfig b/boards/xtensa/esp32/esp32-core/Kconfig index e6a5e293ccf..9a42a5d3cca 100644 --- a/boards/xtensa/esp32/esp32-core/Kconfig +++ b/boards/xtensa/esp32/esp32-core/Kconfig @@ -63,6 +63,22 @@ choice depends on FS_LITTLEFS endchoice +config ESP32_SPIFLASH_ENCRYPTION_TEST + bool "SPI Flash encryption test" + default n + depends on ESP32_SPIFLASH + select DEBUG_ASSERTIONS + help + Enable SPI Flash encryption test. This option will also select + DEBUG_ASSERTIONS to enable kernel assert macro. + +config ESP32_SPIFLASH_TEST_ADDRESS + hex "SPI Flash test address" + default 0x180000 + depends on ESP32_SPIFLASH_ENCRYPTION_TEST + help + SPI Flash encryption test read/write address. + if PM config PM_ALARM_SEC diff --git a/boards/xtensa/esp32/esp32-core/README.txt b/boards/xtensa/esp32/esp32-core/README.txt index c8d68bae0ca..31b487dc1fe 100644 --- a/boards/xtensa/esp32/esp32-core/README.txt +++ b/boards/xtensa/esp32/esp32-core/README.txt @@ -22,6 +22,8 @@ Contents o Serial Console o Buttons and LEDs o Ethernet + o 64-bit Timers + o Watchdog Timers o SMP o OpenOCD for the ESP32 o Executing and Debugging from FLASH and IRAM @@ -31,7 +33,8 @@ Contents STATUS ====== - Currently we have support to UART, SPI, I2C, Ethernet, etc. + Currently we have support to UART, SPI, I2C, Ethernet, Timers, + Watchdog Timers, etc. Espressif is working to include support to WiFi and Bluetooth, but it will depends on their external libraries to get it up and running. @@ -204,8 +207,8 @@ Ethernet ======== ESP32 has a 802.11 hardware MAC, so just connects to external PHY chip. - Due to ESP32's GPIOs are not enough, so recommanded users to use RMII - to connect ESP32 to PHY chip, current driver also only supports RMII option. + Due to the limited number of GPIOs in ESP32, it's recommended to use RMII to + connect to an external PHY chip. Current driver also only supports RMII option. The RMII GPIO pins are fixed, but the SMI and functional GPIO pins are optional. @@ -240,6 +243,25 @@ board + LAN8720 module. If users have some issue about using this driver, please refer the upper official document, specially the issue that GPIO0 causes failing to bring the ESP32 chip up. +64-bit Timers +============= + + ESP32 has 4 generic timers of 64 bits (2 from Group 0 and 2 from Group 1). They're + acessible as character drivers, the configuration along with a guidance on how + to run the example and the description of the application level interface can be found here: + + https://nuttx.apache.org/docs/latest/components/drivers/character/timer.html + +Watchdog Timers +=============== + + ESP32 has 3 WDTs. 2 MWDTS from the Timers Module and 1 RWDT from the RTC Module + (Currently not supported yet). They're acessible as character drivers, + The configuration along with a guidance on how to run the example and the description + of the application level interface can be found here: + + https://nuttx.apache.org/docs/latest/components/drivers/character/watchdog.html + SMP === @@ -809,6 +831,30 @@ NOTES: RAMTest: Pattern test: 3f800000 65536 33333333 cccccccc RAMTest: Address-in-address test: 3f800000 65536 + timer: + + This config test the general use purpose timers. It includes the 4 timers, + adds driver support, registers the timers as devices and includes the timer + example. + + To test it, just run the following: + + `nsh> timer -d /dev/timerx` + + Where x in the timer instance. + + watchdog: + + This config test the watchdog timers. It includes the 2 MWDTS, + adds driver support, registers the WDTs as devices and includes the watchdog + example. + + To test it, just run the following: + + `nsh> wdog -d /dev/watchdogx` + + Where x in the watchdog instance. + Things to Do ============ diff --git a/boards/xtensa/esp32/esp32-core/scripts/esp32_rom.ld b/boards/xtensa/esp32/esp32-core/scripts/esp32_rom.ld index 870c405e1e3..306f4ef6a04 100644 --- a/boards/xtensa/esp32/esp32-core/scripts/esp32_rom.ld +++ b/boards/xtensa/esp32/esp32-core/scripts/esp32_rom.ld @@ -1851,6 +1851,7 @@ PROVIDE ( g_rom_flashchip = 0x3ffae270 ); PROVIDE ( g_rom_spiflash_dummy_len_plus = 0x3ffae290 ); PROVIDE ( esp_rom_spiflash_read_user_cmd = 0x400621b0 ); PROVIDE ( esp_rom_spiflash_write_encrypted_enable = 0x40062df4 ); +PROVIDE ( esp_rom_spiflash_write_encrypted_disable = 0x40062e60 ); PROVIDE ( esp_rom_spiflash_prepare_encrypted_data = 0x40062e1c ); PROVIDE ( esp_rom_printf = ets_printf ); diff --git a/boards/xtensa/esp32/esp32-core/src/esp32-core.h b/boards/xtensa/esp32/esp32-core/src/esp32-core.h index 0bce83f0f34..3627b2348ff 100644 --- a/boards/xtensa/esp32/esp32-core/src/esp32-core.h +++ b/boards/xtensa/esp32/esp32-core/src/esp32-core.h @@ -118,5 +118,25 @@ int esp32_timer_driver_init(void); int esp32_wtd_driver_init(void); #endif +/**************************************************************************** + * Name: esp32_spiflash_encrypt_test + * + * Description: + * Test ESP32 SPI Flash driver read/write with encryption. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_SPIFLASH_ENCRYPTION_TEST + +void esp32_spiflash_encrypt_test(void); + +#endif + #endif /* __ASSEMBLY__ */ #endif /* __BOARDS_XTENSA_ESP32_ESP32_CORE_SRC_ESP32_CORE_H */ diff --git a/boards/xtensa/esp32/esp32-core/src/esp32_bringup.c b/boards/xtensa/esp32/esp32-core/src/esp32_bringup.c index c337c062de2..5ba1c714d56 100644 --- a/boards/xtensa/esp32/esp32-core/src/esp32_bringup.c +++ b/boards/xtensa/esp32/esp32-core/src/esp32_bringup.c @@ -61,6 +61,7 @@ #include #include +#include #include "esp32_procfs_imm.h" #include "esp32-core.h" @@ -142,6 +143,15 @@ int esp32_bringup(void) #endif +#if defined(CONFIG_ESP32_SPIRAM) && \ + defined(CONFIG_ESP32_SPIRAM_BANKSWITCH_ENABLE) + ret = esp_himem_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to init HIMEM: %d\n", ret); + } +#endif + #ifdef CONFIG_FS_PROCFS /* Mount the procfs file system */ @@ -156,12 +166,17 @@ int esp32_bringup(void) ret = esp32_mmcsd_initialize(0); if (ret < 0) { - syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", ret); + syslog(LOG_ERR, "Failed to initialize SD slot: %d\n", ret); return ret; } #endif #ifdef CONFIG_ESP32_SPIFLASH + +#ifdef CONFIG_ESP32_SPIFLASH_ENCRYPTION_TEST + esp32_spiflash_encrypt_test(); +#endif + ret = esp32_spiflash_init(); if (ret) { diff --git a/boards/xtensa/esp32/esp32-core/src/esp32_spiflash.c b/boards/xtensa/esp32/esp32-core/src/esp32_spiflash.c index 3ac6ca674d6..7407117c4c9 100644 --- a/boards/xtensa/esp32/esp32-core/src/esp32_spiflash.c +++ b/boards/xtensa/esp32/esp32-core/src/esp32_spiflash.c @@ -99,3 +99,164 @@ int esp32_spiflash_init(void) return ret; } +/**************************************************************************** + * Name: esp32_spiflash_encrypt_test + * + * Description: + * Test ESP32 SPI Flash driver read/write with encryption. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_SPIFLASH_ENCRYPTION_TEST + +void esp32_spiflash_encrypt_test(void) +{ + int i; + int ret; + uint8_t *wbuf; + uint8_t *rbuf; + struct mtd_geometry_s geo; + uint32_t erase_block; + uint32_t erase_nblocks; + uint32_t rw_block; + uint32_t rw_nblocks; + struct mtd_dev_s *mtd = esp32_spiflash_get_mtd(); + struct mtd_dev_s *enc_mtd = esp32_spiflash_encrypt_get_mtd(); + const uint32_t address = CONFIG_ESP32_SPIFLASH_TEST_ADDRESS; + const uint32_t size = 4096; + + ret = MTD_IOCTL(enc_mtd, MTDIOC_GEOMETRY, + (unsigned long)(uintptr_t)&geo); + if (ret < 0) + { + ferr("ERROR: Failed to get GEO errno =%d\n", ret); + DEBUGASSERT(0); + } + + wbuf = kmm_malloc(size); + if (!wbuf) + { + ferr("ERROR: Failed to alloc %d heap\n", size); + DEBUGASSERT(0); + } + + rbuf = kmm_malloc(size); + if (!rbuf) + { + ferr("ERROR: Failed to alloc %d heap\n", size); + DEBUGASSERT(0); + } + + for (i = 0; i < size; i++) + { + wbuf[i] = (uint8_t)random(); + } + + erase_block = address / geo.erasesize; + erase_nblocks = size / geo.erasesize; + + rw_block = address / geo.blocksize; + rw_nblocks = size / geo.blocksize; + + ret = MTD_ERASE(enc_mtd, erase_block, erase_nblocks); + if (ret != erase_nblocks) + { + ferr("ERROR: Failed to erase block errno=%d\n", ret); + DEBUGASSERT(0); + } + + ret = MTD_BWRITE(enc_mtd, rw_block, rw_nblocks, wbuf); + if (ret != rw_nblocks) + { + ferr("ERROR: Failed to encrypt write errno=%d\n", ret); + DEBUGASSERT(0); + } + + memset(rbuf, 0, size); + ret = MTD_BREAD(enc_mtd, rw_block, rw_nblocks, rbuf); + if (ret != rw_nblocks) + { + ferr("ERROR: Failed to decrypt read errno=%d\n", ret); + DEBUGASSERT(0); + } + + if (memcmp(wbuf, rbuf, size)) + { + ferr("ASSERT: Encrypted and decrypted data is not same\n"); + DEBUGASSERT(0); + } + + memset(rbuf, 0, size); + ret = MTD_BREAD(mtd, rw_block, rw_nblocks, rbuf); + if (ret != rw_nblocks) + { + ferr("ERROR: Failed to read errno=%d\n", ret); + DEBUGASSERT(0); + } + + if (!memcmp(wbuf, rbuf, size)) + { + ferr("ASSERT: Encrypted and normal data is same\n"); + DEBUGASSERT(0); + } + + for (i = 0; i < size; i++) + { + wbuf[i] = (uint8_t)random(); + } + + ret = MTD_ERASE(enc_mtd, erase_block, erase_nblocks); + if (ret != erase_nblocks) + { + ferr("ERROR: Failed to erase errno=%d\n", ret); + DEBUGASSERT(0); + } + + ret = MTD_BWRITE(mtd, rw_block, rw_nblocks, wbuf); + if (ret != rw_nblocks) + { + ferr("ERROR: Failed to write errno=%d\n", ret); + DEBUGASSERT(0); + } + + memset(rbuf, 0, size); + ret = MTD_BREAD(enc_mtd, rw_block, rw_nblocks, rbuf); + if (ret != rw_nblocks) + { + ferr("ERROR: Failed to decrypt read errno=%d\n", ret); + DEBUGASSERT(0); + } + + if (!memcmp(wbuf, rbuf, size)) + { + ferr("ASSERT: Normal and decrypted data is same\n"); + DEBUGASSERT(0); + } + + memset(rbuf, 0, size); + ret = MTD_BREAD(mtd, rw_block, rw_nblocks, rbuf); + if (ret != rw_nblocks) + { + ferr("ERROR: Failed to read errno=%d\n", ret); + DEBUGASSERT(0); + } + + if (memcmp(wbuf, rbuf, size)) + { + ferr("ASSERT: Normal and normal data is not same\n"); + DEBUGASSERT(0); + } + + kmm_free(wbuf); + kmm_free(rbuf); + + finfo("INFO: ESP32 SPI Flash encryption test successfully\n"); +} + +#endif /* CONFIG_ESP32_SPIFLASH_ENCRYPTION_TEST */ diff --git a/crypto/Makefile b/crypto/Makefile index fd663fe816a..68eb31a3843 100644 --- a/crypto/Makefile +++ b/crypto/Makefile @@ -89,10 +89,14 @@ $(COBJS): %$(OBJEXT): %.c $(BIN): $(OBJS) $(call ARCHIVE, $@, $(OBJS)) + +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) .depend: Makefile $(SRCS) $(TOPDIR)$(DELIM).config ifeq ($(CONFIG_CRYPTO),y) - $(Q) $(MKDEP) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile endif $(Q) touch $@ diff --git a/drivers/Makefile b/drivers/Makefile index d8d1a76cda7..1c1139d8adc 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -119,9 +119,13 @@ $(COBJS): %$(OBJEXT): %.c $(BIN): $(OBJS) $(call ARCHIVE, $@, $(OBJS)) + +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) .depend: Makefile $(SRCS) $(TOPDIR)$(DELIM).config - $(Q) $(MKDEP) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile $(Q) touch $@ depend: .depend diff --git a/drivers/analog/Kconfig b/drivers/analog/Kconfig index 8fe91d718bc..c33dd53736a 100644 --- a/drivers/analog/Kconfig +++ b/drivers/analog/Kconfig @@ -157,6 +157,37 @@ config ADS7828_FREQUENCY endif # ADC_ADS7828 +config ADC_MAX1161X + bool "Maxim MAX11612-11617 support" + default n + select I2C + ---help--- + Enable driver support for the MAX1161X 12-Bit I2C powered ADC Family. + + This driver supports reading single or multiple ADC conversion result + as well as onfiguring the ADC, via ioctl calls. + +if ADC_MAX1161X + +config MAX1161X_FREQUENCY + int "Maxim MAX1161X I2C frequency" + default 100000 + ---help--- + MAX1161X supports standard, fast, and high-speed I2C modes. + +choice + prompt "Maxim MAX1161X Chip Type" + + config MAX1161X_4CHAN + bool "MAX11612/MAX11613 4 Channels" + config MAX1161X_8CHAN + bool "MAX11614/MAX11615 8 Channels" + config MAX1161X_12CHAN + bool "MAX11616/MAX11617 12 Channels" +endchoice + +endif # ADC_MAX1161X + endif # ADC config COMP diff --git a/drivers/analog/Make.defs b/drivers/analog/Make.defs index a47f1c46ae0..c5f4fab12e6 100644 --- a/drivers/analog/Make.defs +++ b/drivers/analog/Make.defs @@ -107,6 +107,10 @@ ifeq ($(CONFIG_ADC_ADS7828),y) CSRCS += ads7828.c endif +ifeq ($(CONFIG_ADC_MAX1161X),y) + CSRCS += max1161x.c +endif + ifeq ($(CONFIG_ADC_LTC1867L),y) CSRCS += ltc1867l.c endif diff --git a/drivers/analog/max1161x.c b/drivers/analog/max1161x.c new file mode 100644 index 00000000000..1b96c8742ea --- /dev/null +++ b/drivers/analog/max1161x.c @@ -0,0 +1,596 @@ +/**************************************************************************** + * drivers/analog/max1161x.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * This driver is for a whole family of I2C ADC chips: + * +--------------+-----+----+--------+---------+ + * | Type | VCC | In | Pkg | I2C Addr| + * +--------------+-----+----+--------+---------+ + * | MAX11612EUA+ | 5V0 | 4 | 8μMAX | 0110100 | + * | MAX11613EUA+ | 3V3 | 4 | 8μMAX | 0110100 | + * | MAX11613EWC+ | 3V3 | 4 | 12WLP | 0110100 | + * | MAX11614EEE+ | 5V0 | 8 | 16QSOP | 0110011 | + * | MAX11615EEE+ | 3V3 | 8 | 16QSOP | 0110011 | + * | MAX11615EWE+ | 3V3 | 8 | 16WLP | 0110011 | + * | MAX11616EEE+ | 5V0 | 12 | 16QSOP | 0110101 | + * | MAX11617EEE+ | 3V3 | 12 | 16QSOP | 0110101 | + * | MAX11617EWE+ | 3V3 | 12 | 16WLP | 0110101 | + * +--------------+-----+----+--------+---------+ + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_ADC_MAX1161X) + +#if defined(CONFIG_MAX1161X_4CHAN) +#define MAX1161X_NUM_CHANNELS 4 +#define MAX1161X_CHANNELSTROBED 0x000f +#define MAX1161X_I2C_ADDR 0x34u +#elif defined(CONFIG_MAX1161X_8CHAN) +#define MAX1161X_NUM_CHANNELS 8 +#define MAX1161X_CHANNELSTROBED 0x00ff +#define MAX1161X_I2C_ADDR 0x33u +#elif defined(CONFIG_MAX1161X_12CHAN) +#define MAX1161X_NUM_CHANNELS 12 +#define MAX1161X_CHANNELSTROBED 0x0fff +#define MAX1161X_I2C_ADDR 0x35u +#else +#error "MAX1161X Chip Type not defined" +#endif + +#define MAX1161X_SETUP_MARKER (1 << 7) +#define MAX1161X_SETUP_REF_SHIFT 4 +#define MAX1161X_SETUP_REF_MASK (7 << MAX1161X_SETUP_REF_SHIFT) +#define MAX1161X_SETUP_CLK (1 << 3) +#define MAX1161X_SETUP_UNIBIP (1 << 2) +#define MAX1161X_SETUP_RESET (1 << 1) + +#define MAX1161X_CMD_MARKER (0 << 7) +#define MAX1161X_CMD_SCAN_SHIFT 5 +#define MAX1161X_CMD_SCAN_MASK (3 << MAX1161X_CMD_SCAN_SHIFT) +#define MAX1161X_CMD_CHANNEL_SHIFT 1 +#define MAX1161X_CMD_CHANNEL_MASK (15 << MAX1161X_CMD_CHANNEL_SHIFT) +#define MAX1161X_CMD_SNGDIF (1 << 0) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct max1161x_dev_s +{ + FAR struct i2c_master_s *i2c; + FAR const struct adc_callback_s *cb; + uint8_t addr; + + /* List of channels to read on every convert trigger. + * Bit position corresponds to channel. i.e. bit0 = 1 to read channel 0. + */ + + uint16_t chanstrobed; + + /* Current configuration of the ADC. There are two bytes holding + * the complete configuration - the Setup Byte has Bit 7 always set, + * while the command byte has bit 7 alway reset + */ + + uint8_t setupbyte; + uint8_t cmdbyte; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* max1161x helpers */ + +static int max1161x_readchannel(FAR struct max1161x_dev_s *priv, + FAR struct adc_msg_s *msg); + +/* ADC methods */ + +static int max1161x_bind(FAR struct adc_dev_s *dev, + FAR const struct adc_callback_s *callback); +static void max1161x_reset(FAR struct adc_dev_s *dev); +static int max1161x_setup(FAR struct adc_dev_s *dev); +static void max1161x_shutdown(FAR struct adc_dev_s *dev); +static void max1161x_rxint(FAR struct adc_dev_s *dev, bool enable); +static int max1161x_ioctl(FAR struct adc_dev_s *dev, int cmd, + unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct adc_ops_s g_adcops = +{ + .ao_bind = max1161x_bind, /* ao_bind */ + .ao_reset = max1161x_reset, /* ao_reset */ + .ao_setup = max1161x_setup, /* ao_setup */ + .ao_shutdown = max1161x_shutdown, /* ao_shutdown */ + .ao_rxint = max1161x_rxint, /* ao_rxint */ + .ao_ioctl = max1161x_ioctl /* ao_read */ +}; + +static struct max1161x_dev_s g_adcpriv; + +static struct adc_dev_s g_adcdev = +{ + .ad_ops = &g_adcops, + .ad_priv = &g_adcpriv, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: max1161x_manage_strobe + * + * Description: + * Controls which channels are read on ANIOC_TRIGGER. By default all + * channels are read. + * + * Returned Value: + * 0 on success. Negated errno on failure. + * + ****************************************************************************/ + +static int max1161x_manage_strobe(FAR struct max1161x_dev_s *priv, + uint8_t channel, bool add_nremove) +{ + int ret = OK; + + if (priv == NULL || channel >= MAX1161X_NUM_CHANNELS) + { + ret = -EINVAL; + } + else + { + uint16_t flag = 1U << channel; + + if (add_nremove) + { + priv->chanstrobed |= flag; + } + else + { + priv->chanstrobed &= ~flag; + } + } + + return ret; +} + +/**************************************************************************** + * Name: max1161x_readchannel + * + * Description: + * Reads a conversion from the ADC. + * + * Input Parameters: + * msg - msg->am_channel should be set to the channel to be read. + * msg->am_data will store the result of the read. + * + * Returned Value: + * 0 on success. Negated errno on failure. + * + * Assumptions/Limitations: + * NOTE: When used in single-ended mode, msg->am_channel will be converted + * to the corresponding channel selection bits in the command byte. + * In differential mode, msg->am_channel is used as the channel + * selection bits. The corresponding "channels" are as follows: + * + * msg->am_channel Analog Source + * 0 +CH0, -CH1 + * 1 +CH1, -CH0 + * 2 +CH2, -CH3 + * 3 +CH3, -CH2 + * 4 +CH4, -CH5 + * 5 +CH5, -CH4 + * 6 +CH6, -CH7 + * 7 +CH7, -CH6 + * + ****************************************************************************/ + +static int max1161x_readchannel(FAR struct max1161x_dev_s *priv, + FAR struct adc_msg_s *msg) +{ + int ret = OK; + if (priv == NULL || msg == NULL) + { + ret = -EINVAL; + } + else + { + struct i2c_msg_s i2cmsg[3]; + uint8_t channel = msg->am_channel & ~(MAX1161X_CMD_CHANNEL_MASK); + + uint8_t setupbyte = priv->setupbyte; + uint8_t cmdbyte = priv->cmdbyte & ~(MAX1161X_CMD_CHANNEL_MASK); + cmdbyte |= channel << MAX1161X_CMD_CHANNEL_SHIFT; + + i2cmsg[0].frequency = CONFIG_MAX1161X_FREQUENCY; + i2cmsg[0].addr = priv->addr; + i2cmsg[0].flags = I2C_M_NOSTOP; + i2cmsg[0].buffer = &setupbyte; + i2cmsg[0].length = sizeof(setupbyte); + + i2cmsg[1].frequency = CONFIG_MAX1161X_FREQUENCY; + i2cmsg[1].addr = priv->addr; + i2cmsg[1].flags = I2C_M_NOSTOP; + i2cmsg[1].buffer = &cmdbyte; + i2cmsg[1].length = sizeof(cmdbyte); + + i2cmsg[2].frequency = CONFIG_MAX1161X_FREQUENCY; + i2cmsg[2].addr = priv->addr; + i2cmsg[2].flags = I2C_M_READ; + + uint16_t buf; + i2cmsg[2].buffer = (uint8_t *)(&buf); + i2cmsg[2].length = sizeof(buf); + ret = I2C_TRANSFER(priv->i2c, i2cmsg, 3); + if (ret < 0) + { + aerr("MAX1161X I2C transfer failed: %d", ret); + } + + msg->am_data = be16toh(buf) & 0x0fffu; + } + + return ret; +} + +/**************************************************************************** + * Name: max1161x_bind + * + * Description: + * Bind the upper-half driver callbacks to the lower-half implementation. + * This must be called early in order to receive ADC event notifications. + * + ****************************************************************************/ + +static int max1161x_bind(FAR struct adc_dev_s *dev, + FAR const struct adc_callback_s *callback) +{ + FAR struct max1161x_dev_s *priv = + (FAR struct max1161x_dev_s *)dev->ad_priv; + + DEBUGASSERT(priv != NULL); + priv->cb = callback; + return OK; +} + +/**************************************************************************** + * Name: max1161x_reset + * + * Description: + * Reset the ADC device. Called early to initialize the hardware. This + * is called, before ao_setup() and on error conditions. + * + ****************************************************************************/ + +static void max1161x_reset(FAR struct adc_dev_s *dev) +{ + FAR struct max1161x_dev_s *priv = + (FAR struct max1161x_dev_s *)dev->ad_priv; + + priv->setupbyte = MAX1161X_SETUP_MARKER; + priv->cmdbyte = MAX1161X_CMD_MARKER; + priv->chanstrobed = MAX1161X_CHANNELSTROBED; + +#ifndef MAX1161X_ENABLE_SCAN + priv->cmdbyte &= ~(MAX1161X_CMD_SCAN_MASK); + priv->cmdbyte |= (MAX1161X_SCAN_NONE << MAX1161X_CMD_SCAN_SHIFT); +#endif +} + +/**************************************************************************** + * Name: max1161x_setup + * + * Description: + * Configure the ADC. This method is called the first time that the ADC + * device is opened. The MAX1161X is quite simple and nothing special is + * needed to be done. + * + ****************************************************************************/ + +static int max1161x_setup(FAR struct adc_dev_s *dev) +{ + return OK; +} + +/**************************************************************************** + * Name: max1161x_shutdown + * + * Description: + * Disable the ADC. This method is called when the ADC device is closed. + * This method should reverse the operation of the setup method, but as + * the MAX1161X is quite simple does not need to do anything. + * + ****************************************************************************/ + +static void max1161x_shutdown(FAR struct adc_dev_s *dev) +{ +} + +/**************************************************************************** + * Name: max1161x_rxint + * + * Description: + * Needed for ADC upper-half compatibility but conversion interrupts + * are not supported by the MAX1161X. + * + ****************************************************************************/ + +static void max1161x_rxint(FAR struct adc_dev_s *dev, bool enable) +{ +} + +/**************************************************************************** + * Name: max1161x_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int max1161x_ioctl(FAR struct adc_dev_s *dev, int cmd, + unsigned long arg) +{ + FAR struct max1161x_dev_s *priv = + (FAR struct max1161x_dev_s *)dev->ad_priv; + int ret = OK; + + switch (cmd) + { + case ANIOC_TRIGGER: + { + struct adc_msg_s msg; + int i; + + for (i = 0; (i < MAX1161X_NUM_CHANNELS) && (ret == OK); i++) + { + if ((priv->chanstrobed >> i) & 1u) + { + msg.am_channel = i; + ret = max1161x_readchannel(priv, &msg); + if (ret == OK) + { + priv->cb->au_receive(&g_adcdev, i, msg.am_data); + } + } + } + } + break; + + /* Add a channel to list of channels read on ANIOC_TRIGGER */ + + case ANIOC_MAX1161X_ADD_CHAN: + { + ret = max1161x_manage_strobe(priv, (uint8_t)arg, true); + } + break; + + /* Remove a channel from list of channels read on ANIOC_TRIGGER */ + + case ANIOC_MAX1161X_REMOVE_CHAN: + { + ret = max1161x_manage_strobe(priv, (uint8_t)arg, false); + } + break; + + /* Read a single channel from the ADC */ + + case ANIOC_MAX1161X_READ_CHANNEL: + { + FAR struct adc_msg_s *msg = (FAR struct adc_msg_s *)arg; + ret = max1161x_readchannel(priv, msg); + } + break; + + /* Set the ADC reference source and pin function */ + + case ANIOC_MAX1161X_SET_REF: + { + switch (arg) + { + case MAX1161X_REF_VDD_AIN_NC_OFF: + case MAX1161X_REF_EXT_RIN_IN_OFF: + case MAX1161X_REF_INT_AIN_NC_OFF: + case MAX1161X_REF_INT_AIN_NC_ON: + case MAX1161X_REF_INT_ROUT_OUT_OFF: + case MAX1161X_REF_INT_ROUT_OUT_ON: + { + priv->setupbyte &= ~(MAX1161X_SETUP_REF_MASK); + priv->setupbyte |= (arg << MAX1161X_SETUP_REF_SHIFT); + } + break; + + default: + { + ret = -EINVAL; + } + break; + } + } + break; + + /* Set clock source */ + + case ANIOC_MAX1161X_SET_CLOCK: + { + if (arg == MAX1161X_CLOCK_EXT) + { + priv->setupbyte |= MAX1161X_SETUP_CLK; + } + else if (arg == MAX1161X_CLOCK_INT) + { + priv->setupbyte &= ~MAX1161X_SETUP_CLK; + } + else + { + ret = -EINVAL; + } + } + break; + + /* Set the ADC Unipolar/Bipolar Mode */ + + case ANIOC_MAX1161X_SET_UNIBIP: + { + if (arg == MAX1161X_BIPOLAR) + { + priv->setupbyte |= MAX1161X_SETUP_UNIBIP; + } + else if (arg == MAX1161X_UNIPOLAR) + { + priv->setupbyte &= ~MAX1161X_SETUP_UNIBIP; + } + else + { + ret = -EINVAL; + } + } + break; + + /* Set the ADC Scan Mode */ + + case ANIOC_MAX1161X_SET_SCAN: + { +#ifdef MAX1161X_ENABLE_SCAN + switch (arg) + { + case MAX1161X_SCAN_FROM_ZERO : + case MAX1161X_SCAN_EIGHT_TIMES: + case MAX1161X_SCAN_UPPER: + case MAX1161X_SCAN_NONE: + { + priv->cmdbyte &= ~(MAX1161X_CMD_SCAN_MASK); + priv->cmdbyte |= (arg << MAX1161X_CMD_SCAN_SHIFT); + } + break; + + default: + { + ret = -EINVAL; + } + break; + } +#endif + } + break; + + /* Set the ADC Single Ended/Differential Mode */ + + case ANIOC_MAX1161X_SET_SNGDIF: + { + if (arg == MAX1161X_SINGLE_ENDED) + { + priv->cmdbyte |= MAX1161X_CMD_SNGDIF; + } + else if (arg == MAX1161X_DIFFERENTIAL) + { + priv->cmdbyte &= ~MAX1161X_CMD_SNGDIF; + } + else + { + ret = -EINVAL; + } + } + break; + + /* Command was not recognized */ + + default: + ret = -ENOTTY; + aerr("MAX1161X ERROR: Unrecognized cmd: %d\n", cmd); + break; + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: max1161x_initialize + * + * Description: + * Initialize the selected adc + * + * Input Parameters: + * i2c - Pointer to a I2C master struct for the bus the ADC resides on. + * + * Returned Value: + * Valid ADC device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +FAR struct adc_dev_s *max1161x_initialize(FAR struct i2c_master_s *i2c) +{ + DEBUGASSERT(i2c != NULL); + + /* Driver state data */ + + FAR struct max1161x_dev_s *priv; + priv = (FAR struct max1161x_dev_s *)g_adcdev.ad_priv; + + priv->cb = NULL; + priv->i2c = i2c; + priv->addr = MAX1161X_I2C_ADDR; + priv->setupbyte = MAX1161X_SETUP_MARKER; + priv->cmdbyte = MAX1161X_CMD_MARKER; + priv->chanstrobed = MAX1161X_CHANNELSTROBED; + +#ifndef MAX1161X_ENABLE_SCAN + priv->cmdbyte &= ~(MAX1161X_CMD_SCAN_MASK); + priv->cmdbyte |= (MAX1161X_SCAN_NONE << MAX1161X_CMD_SCAN_SHIFT); +#endif + + return &g_adcdev; +} + +#endif diff --git a/drivers/audio/Kconfig b/drivers/audio/Kconfig index 610109c96e7..a5182fa6bec 100644 --- a/drivers/audio/Kconfig +++ b/drivers/audio/Kconfig @@ -40,6 +40,14 @@ if AUDIO_CXD56 if AUDIO_DRIVER_SPECIFIC_BUFFERS +config AUDIO_CXD56_SRC + bool "CXD56 audio sample rate convertor" + select AUDIO_SRC + default n + ---help--- + Enable support for audio playback using the CXD5247 chip on the + CXD56 Spresense board with sample rate convertor. + config CXD56_AUDIO_NUM_BUFFERS int "Number of audio buffers to use" default 4 diff --git a/drivers/audio/Make.defs b/drivers/audio/Make.defs index b0c0535635e..cb8bb6e7dad 100644 --- a/drivers/audio/Make.defs +++ b/drivers/audio/Make.defs @@ -41,6 +41,9 @@ ifeq ($(CONFIG_DRIVERS_AUDIO),y) ifeq ($(CONFIG_AUDIO_CXD56),y) CSRCS += cxd56.c +ifeq ($(CONFIG_AUDIO_CXD56_SRC),y) +CSRCS += cxd56_src.c +endif endif ifeq ($(CONFIG_AUDIO_VS1053),y) diff --git a/drivers/audio/audio_null.c b/drivers/audio/audio_null.c index c966e73f893..0b7b709465e 100644 --- a/drivers/audio/audio_null.c +++ b/drivers/audio/audio_null.c @@ -46,6 +46,7 @@ #include #include +#include #include #include #include @@ -528,7 +529,8 @@ static int null_start(FAR struct audio_lowerhalf_s *dev) /* Create a message queue for the worker thread */ - snprintf(priv->mqname, sizeof(priv->mqname), "/tmp/%X", priv); + snprintf(priv->mqname, sizeof(priv->mqname), "/tmp/%" PRIXPTR, + (uintptr_t)priv); attr.mq_maxmsg = 16; attr.mq_msgsize = sizeof(struct audio_msg_s); diff --git a/drivers/audio/cs4344.c b/drivers/audio/cs4344.c index 907ef4c7c18..928a573bb3b 100644 --- a/drivers/audio/cs4344.c +++ b/drivers/audio/cs4344.c @@ -27,6 +27,7 @@ #include #include +#include #include #include #include @@ -777,7 +778,8 @@ static int cs4344_start(FAR struct audio_lowerhalf_s *dev) /* Create a message queue for the worker thread */ - snprintf(priv->mqname, sizeof(priv->mqname), "/tmp/%X", priv); + snprintf(priv->mqname, sizeof(priv->mqname), "/tmp/%" PRIXPTR, + (uintptr_t)priv); attr.mq_maxmsg = 16; attr.mq_msgsize = sizeof(struct audio_msg_s); diff --git a/drivers/audio/cs43l22.c b/drivers/audio/cs43l22.c index dac7854320f..24e37a04765 100644 --- a/drivers/audio/cs43l22.c +++ b/drivers/audio/cs43l22.c @@ -44,6 +44,7 @@ #include #include +#include #include #include #include @@ -1214,7 +1215,8 @@ static int cs43l22_start(FAR struct audio_lowerhalf_s *dev) /* Create a message queue for the worker thread */ - snprintf(priv->mqname, sizeof(priv->mqname), "/tmp/%X", priv); + snprintf(priv->mqname, sizeof(priv->mqname), "/tmp/%" PRIXPTR, + (uintptr_t)priv); attr.mq_maxmsg = 16; attr.mq_msgsize = sizeof(struct audio_msg_s); diff --git a/drivers/audio/cxd56.c b/drivers/audio/cxd56.c index 259e7aee39a..935303f26a7 100644 --- a/drivers/audio/cxd56.c +++ b/drivers/audio/cxd56.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include @@ -54,6 +55,10 @@ #include "cxd56.h" +#ifdef CONFIG_AUDIO_CXD56_SRC +#include "cxd56_src.h" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -1271,6 +1276,157 @@ static void cxd56_reset_channel_sel(cxd56_dmahandle_t handle) } } +#ifdef CONFIG_CXD56_AUCIO_SRC +static void _process_audio_with_src(cxd56_dmahandle_t hdl, uint16_t err_code) +{ + struct audio_msg_s msg; + struct cxd56_dev_s *dev; + irqstate_t flags; + bool request_buffer = true; + int ret; + + dev = g_dev[hdl]; + + /* Trigger new DMA job */ + + flags = spin_lock_irqsave(); + + if (err_code == CXD56_AUDIO_ECODE_DMA_TRANS) + { + /* Notify end of data */ + + if (dev->state != CXD56_DEV_STATE_PAUSED + && dq_count(&dev->down_pendq) == 0) + { + msg.msg_id = AUDIO_MSG_STOP; + msg.u.data = 0; + spin_unlock_irqrestore(flags); + ret = nxmq_send(dev->mq, (FAR const char *)&msg, + sizeof(msg), CONFIG_CXD56_MSG_PRIO); + flags = spin_lock_irqsave(); + if (ret != OK) + { + auderr("ERROR: nxmq_send to stop failed (%d)\n", ret); + } + } + } + + if (dq_count(&dev->down_runq) > 0) + { + FAR struct ap_buffer_s *src_apb; + + src_apb = (struct ap_buffer_s *) dq_get(&dev->down_runq); + src_apb->nbytes = 0; + dq_put(&dev->down_doneq, &src_apb->dq_entry); + + if (src_apb->flags & AUDIO_APB_SRC_FINAL) + { + struct ap_buffer_s *apb; + + apb = dq_get(&dev->up_runq); + spin_unlock_irqrestore(flags); + dev->dev.upper(dev->dev.priv, AUDIO_CALLBACK_DEQUEUE, apb, OK); + flags = spin_lock_irqsave(); + + /* End of data? */ + + if ((apb->flags & AUDIO_APB_FINAL) != 0) + { + msg.msg_id = AUDIO_MSG_STOP; + msg.u.data = 0; + spin_unlock_irqrestore(flags); + ret = nxmq_send(dev->mq, (FAR const char *)&msg, + sizeof(msg), CONFIG_CXD56_MSG_PRIO); + flags = spin_lock_irqsave(); + if (ret != OK) + { + auderr("ERROR: nxmq_send to stop failed (%d)\n", ret); + } + + request_buffer = false; + } + } + } + + if (request_buffer && dev->mq != NULL) + { + /* Request more data */ + + msg.msg_id = AUDIO_MSG_DATA_REQUEST; + msg.u.data = 0; + spin_unlock_irqrestore(flags); + ret = nxmq_send(dev->mq, (FAR const char *) &msg, + sizeof(msg), CONFIG_CXD56_MSG_PRIO); + flags = spin_lock_irqsave(); + if (ret != OK) + { + auderr("ERROR: nxmq_send to request failed (%d)\n", ret); + } + } + + spin_unlock_irqrestore(flags); +} + +#else +static void _process_audio(cxd56_dmahandle_t hdl, uint16_t err_code) +{ + struct audio_msg_s msg; + struct cxd56_dev_s *dev; + irqstate_t flags; + int ret; + + dev = g_dev[hdl]; + + /* Trigger new DMA job */ + + flags = spin_lock_irqsave(); + + if (dq_count(&dev->up_runq) > 0) + { + FAR struct ap_buffer_s *apb; + + apb = (struct ap_buffer_s *) dq_get(&dev->up_runq); + spin_unlock_irqrestore(flags); + dev->dev.upper(dev->dev.priv, AUDIO_CALLBACK_DEQUEUE, apb, OK); + flags = spin_lock_irqsave(); + } + + spin_unlock_irqrestore(flags); + + if (err_code == CXD56_AUDIO_ECODE_DMA_TRANS) + { + /* Notify end of data */ + + if (dev->state != CXD56_DEV_STATE_PAUSED) + { + audinfo("DMA_TRANS up_pendq=%d \n", + dq_count(&dev->up_pendq)); + msg.msg_id = AUDIO_MSG_STOP; + msg.u.data = 0; + ret = nxmq_send(dev->mq, (FAR const char *)&msg, + sizeof(msg), CONFIG_CXD56_MSG_PRIO); + if (ret != OK) + { + auderr("ERROR: nxmq_send to stop failed (%d)\n", ret); + } + } + } + else if (dev->mq != NULL) + { + /* Request more data */ + + msg.msg_id = AUDIO_MSG_DATA_REQUEST; + msg.u.data = 0; + ret = nxmq_send(dev->mq, (FAR const char *) &msg, + sizeof(msg), CONFIG_CXD56_MSG_PRIO); + if (ret != OK) + { + auderr("ERROR: nxmq_send to request failed (%d)\n", ret); + } + } +} +#endif + static void cxd56_dma_int_handler(void) { uint16_t err_code; @@ -1359,60 +1515,11 @@ static void cxd56_dma_int_handler(void) if (err_code != CXD56_AUDIO_ECODE_DMA_HANDLE_INV) { - struct audio_msg_s msg; - struct cxd56_dev_s *dev; - irqstate_t flags; - int ret; - - dev = g_dev[hdl]; - - /* Trigger new DMA job */ - - flags = spin_lock_irqsave(); - - if (dq_count(&dev->up_runq) > 0) - { - FAR struct ap_buffer_s *apb; - - apb = (struct ap_buffer_s *) dq_get(&dev->up_runq); - spin_unlock_irqrestore(flags); - dev->dev.upper(dev->dev.priv, AUDIO_CALLBACK_DEQUEUE, apb, OK); - flags = spin_lock_irqsave(); - } - - spin_unlock_irqrestore(flags); - - if (err_code == CXD56_AUDIO_ECODE_DMA_TRANS) - { - /* Notify end of data */ - - if (dev->state != CXD56_DEV_STATE_PAUSED) - { - audinfo("DMA_TRANS up_pendq=%d \n", - dq_count(&dev->up_pendq)); - msg.msg_id = AUDIO_MSG_STOP; - msg.u.data = 0; - ret = nxmq_send(dev->mq, (FAR const char *)&msg, - sizeof(msg), CONFIG_CXD56_MSG_PRIO); - if (ret != OK) - { - auderr("ERROR: nxmq_send to stop failed (%d)\n", ret); - } - } - } - else if (dev->mq != NULL) - { - /* Request more data */ - - msg.msg_id = AUDIO_MSG_DATA_REQUEST; - msg.u.data = 0; - ret = nxmq_send(dev->mq, (FAR const char *) &msg, - sizeof(msg), CONFIG_CXD56_MSG_PRIO); - if (ret != OK) - { - auderr("ERROR: nxmq_send to request failed (%d)\n", ret); - } - } +#ifdef CONFIG_CXD56_AUCIO_SRC + _process_audio_with_src(hdl, err_code); +#else + _process_audio(hdl, err_code); +#endif } } @@ -1626,6 +1733,11 @@ static void cxd56_init_dma(FAR struct cxd56_dev_s *dev) dq_clear(&dev->up_pendq); dq_clear(&dev->up_runq); +#ifdef CONFIG_AUDIO_CXD56_SRC + dq_clear(&dev->down_pendq); + dq_clear(&dev->down_runq); + dq_clear(&dev->down_doneq); +#endif ints = CXD56_DMA_INT_DONE | CXD56_DMA_INT_ERR | CXD56_DMA_INT_CMB; @@ -2692,6 +2804,15 @@ static int cxd56_configure(FAR struct audio_lowerhalf_s *lower, priv->channels = caps->ac_channels; priv->bitwidth = caps->ac_controls.b[2]; +#ifdef CONFIG_AUDIO_CXD56_SRC + ret = cxd56_src_init(priv, &priv->down_doneq, &priv->down_pendq); + if (ret != OK) + { + auderr("ERROR: Could not initialize SRC (%d)\n", ret); + return -ENOMEM; + } + +#endif g_dev[priv->dma_handle] = priv; poweron = 1; @@ -3067,7 +3188,13 @@ static int cxd56_start_dma(FAR struct cxd56_dev_s *dev) int ret = OK; flags = spin_lock_irqsave(); +#ifdef CONFIG_AUDIO_CXD56_SRC + FAR struct ap_buffer_s *src_apb; + + if (dq_count(&dev->down_pendq) == 0) +#else if (dq_count(&dev->up_pendq) == 0) +#endif { /* Underrun occurred, stop DMA and change state for buffering */ @@ -3089,7 +3216,11 @@ static int cxd56_start_dma(FAR struct cxd56_dev_s *dev) { /* Fill up with as many DMA requests as we can */ +#ifdef CONFIG_AUDIO_CXD56_SRC + while (dq_count(&dev->down_pendq) > 0) +#else while (dq_count(&dev->up_pendq) > 0) +#endif { if (cxd56_dma_is_busy(dev->dma_handle)) { @@ -3099,9 +3230,15 @@ static int cxd56_start_dma(FAR struct cxd56_dev_s *dev) goto exit; } +#ifdef CONFIG_AUDIO_CXD56_SRC + src_apb = (struct ap_buffer_s *) dq_peek(&dev->down_pendq); + addr = ((uint32_t)src_apb->samp) & CXD56_DMA_START_ADDR_MASK; + size = (src_apb->nbytes / (dev->bitwidth / 8) / dev->channels) - 1; +#else apb = (struct ap_buffer_s *) dq_peek(&dev->up_pendq); addr = ((uint32_t)apb->samp) & CXD56_DMA_START_ADDR_MASK; size = (apb->nbytes / (dev->bitwidth / 8) / dev->channels) - 1; +#endif if (dev->dma_handle == CXD56_AUDIO_DMA_MIC) { @@ -3113,7 +3250,13 @@ static int cxd56_start_dma(FAR struct cxd56_dev_s *dev) if (dev->bitwidth == 16 && CXD56_DMA_FORMAT == CXD56_DMA_FORMAT_RL) { - cxd56_swap_buffer_rl((uint32_t)apb->samp, apb->nbytes); +#ifdef CONFIG_AUDIO_CXD56_SRC + cxd56_swap_buffer_rl((uint32_t)src_apb->samp, + src_apb->nbytes); +#else + cxd56_swap_buffer_rl((uint32_t)apb->samp, + apb->nbytes); +#endif } write_reg(REG_I2S1_OUT_START_ADR, addr); @@ -3222,10 +3365,19 @@ static int cxd56_start_dma(FAR struct cxd56_dev_s *dev) cxd56_set_dma_running(dev->dma_handle, true); } +#ifdef CONFIG_AUDIO_CXD56_SRC + dq_get(&dev->down_pendq); + dq_put(&dev->down_runq, &src_apb->dq_entry); + + apb = (struct ap_buffer_s *) dq_get(&dev->up_pendq); +#else dq_get(&dev->up_pendq); +#endif dq_put(&dev->up_runq, &apb->dq_entry); + dev->state = CXD56_DEV_STATE_STARTED; +#ifndef CONFIG_AUDIO_CXD56_SRC if ((apb->flags & AUDIO_APB_FINAL) != 0) { /* If the apb is final, send stop message */ @@ -3246,6 +3398,7 @@ static int cxd56_start_dma(FAR struct cxd56_dev_s *dev) goto exit; } } +#endif } } @@ -3268,29 +3421,40 @@ static int cxd56_enqueuebuffer(FAR struct audio_lowerhalf_s *lower, FAR struct cxd56_dev_s *priv = (FAR struct cxd56_dev_s *)lower; struct audio_msg_s msg; irqstate_t flags; + int ret; - flags = spin_lock_irqsave(); - - apb->dq_entry.flink = NULL; - dq_put(&priv->up_pendq, &apb->dq_entry); - - spin_unlock_irqrestore(flags); - - if (priv->mq != NULL) +#ifdef CONFIG_AUDIO_CXD56_SRC + ret = cxd56_src_enqueue(apb); + if (ret != OK) { - int ret; - - msg.msg_id = AUDIO_MSG_ENQUEUE; - msg.u.data = 0; - - ret = nxmq_send(priv->mq, (FAR const char *) &msg, - sizeof(msg), CONFIG_CXD56_MSG_PRIO); - if (ret != OK) - { - auderr("ERROR: nxmq_send to enqueue failed (%d)\n", ret); - return ret; - } + auderr("ERROR: SRC processing failed (%d)\n", ret); } + else + { +#endif + flags = spin_lock_irqsave(); + + apb->dq_entry.flink = NULL; + dq_put(&priv->up_pendq, &apb->dq_entry); + + spin_unlock_irqrestore(flags); + + if (priv->mq != NULL) + { + msg.msg_id = AUDIO_MSG_ENQUEUE; + msg.u.data = 0; + + ret = nxmq_send(priv->mq, (FAR const char *) &msg, + sizeof(msg), CONFIG_CXD56_MSG_PRIO); + if (ret != OK) + { + auderr("ERROR: nxmq_send to enqueue failed (%d)\n", ret); + return ret; + } + } +#ifdef CONFIG_AUDIO_CXD56_SRC + } +#endif return OK; } @@ -3408,6 +3572,20 @@ static void *cxd56_workerthread(pthread_addr_t pvarg) priv->running = false; } +#ifdef CONFIG_AUDIO_CXD56_SRC + ret = cxd56_src_stop(); + if (ret != OK) + { + auderr("ERROR: Could not stop SRC (%d)\n", ret); + } + + ret = cxd56_src_deinit(); + if (ret != OK) + { + auderr("ERROR: Could not deinit SRC (%d)\n", ret); + } + +#endif priv->state = CXD56_DEV_STATE_STOPPED; priv->running = false; audinfo("Workerthread stopped.\n"); @@ -3475,7 +3653,8 @@ static int cxd56_init_worker(FAR struct audio_lowerhalf_s *dev) void *value; int ret; - snprintf(priv->mqname, sizeof(priv->mqname), "/tmp/%X", priv); + snprintf(priv->mqname, sizeof(priv->mqname), "/tmp/%" PRIXPTR, + (uintptr_t)priv); m_attr.mq_maxmsg = 16; m_attr.mq_msgsize = sizeof(struct audio_msg_s); @@ -3545,6 +3724,11 @@ struct audio_lowerhalf_s *cxd56_initialize( nxsem_init(&priv->pendsem, 0, 1); dq_init(&priv->up_pendq); dq_init(&priv->up_runq); +#ifdef CONFIG_AUDIO_CXD56_SRC + dq_init(&priv->down_pendq); + dq_init(&priv->down_runq); + dq_init(&priv->down_doneq); +#endif } return &priv->dev; diff --git a/drivers/audio/cxd56.h b/drivers/audio/cxd56.h index 65a385786ce..efff9d383a7 100644 --- a/drivers/audio/cxd56.h +++ b/drivers/audio/cxd56.h @@ -287,6 +287,12 @@ struct cxd56_dev_s struct dq_queue_s up_pendq; /* Pending buffers from app to process */ struct dq_queue_s up_runq; /* Buffers from app being played */ +#ifdef CONFIG_AUDIO_CXD56_SRC + struct dq_queue_s down_pendq; /* Pending SRC buffers to be DMA'd */ + struct dq_queue_s down_runq; /* SRC buffers being processed */ + struct dq_queue_s down_doneq; /* Done SRC buffers to be re-used */ +#endif + uint16_t samplerate; /* Sample rate */ #ifndef CONFIG_AUDIO_EXCLUDE_VOLUME int16_t volume; /* Output volume {0..63} */ diff --git a/drivers/audio/cxd56_src.c b/drivers/audio/cxd56_src.c new file mode 100644 index 00000000000..70ec5994d7a --- /dev/null +++ b/drivers/audio/cxd56_src.c @@ -0,0 +1,603 @@ +/**************************************************************************** + * drivers/audio/cxd56_src.c + * + * Copyright 2020 Sony Semiconductor Solutions Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "cxd56.h" +#include "cxd56_src.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* For debugging: dump pre/post SRC data to sdcard */ + +/* #define DUMP_DATA */ + +/* Note: 24 bit samples not currently supported by SRC */ + +#define BUFFER_SAMPLES (CONFIG_CXD56_AUDIO_BUFFER_SIZE / 2) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +enum cxd56_srcstate_e +{ + CXD56_SRC_OFF, + CXD56_SRC_RUNNING, + CXD56_SRC_STOPPING, + CXD56_SRC_STOPPED +}; + +struct cxd56_srcdata_s +{ + enum cxd56_srcstate_e state; + + float float_in[BUFFER_SAMPLES]; + float float_out[BUFFER_SAMPLES]; + int float_in_offset; + + SRC_DATA src_data; + SRC_STATE *src_state; + + struct dq_queue_s *inq; + struct dq_queue_s *outq; + + char mqname[32]; + mqd_t mq; + sem_t pendsem; + pthread_t threadid; + + uint8_t bytewidth; + uint8_t channels; + + float buf_count; + float buf_increment; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct cxd56_srcdata_s g_src; + +#ifdef DUMP_DATA +static char *dump_name_pre = "/mnt/sd0/dump/nx_player_dump_pre.pcm"; +static char *dump_name_post = "/mnt/sd0/dump/nx_player_dump_post.pcm"; +int dump_file_pre = -1; +int dump_file_post = -1; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +extern void src_short_to_float_array (const short *in, float *out, int len); +extern void src_float_to_short_array (const float *in, short *out, int len); +extern void src_int_to_float_array (const int *in, float *out, int len); +extern void src_float_to_int_array (const float *in, int *out, int len); + +static struct ap_buffer_s *cxd56_src_get_apb() +{ + struct ap_buffer_s *src_apb; + irqstate_t flags; + + flags = spin_lock_irqsave(); + + if (dq_count(g_src.inq) == 0) + { + size_t bufsize = sizeof(struct ap_buffer_s) + + CONFIG_CXD56_AUDIO_BUFFER_SIZE; + + spin_unlock_irqrestore(flags); + + src_apb = kmm_zalloc(bufsize); + + flags = spin_lock_irqsave(); + + if (!src_apb) + { + auderr("ERROR: Couldn't allocate SRC APB (size %d)\n", bufsize); + + goto errorout_with_lock; + } + + src_apb->nmaxbytes = CONFIG_CXD56_AUDIO_BUFFER_SIZE; + src_apb->nbytes = 0; + src_apb->samp = (FAR uint8_t *)(&src_apb->samp + 1); + } + else + { + src_apb = (struct ap_buffer_s *) dq_get(g_src.inq); + } + + src_apb->flags = 0; + +errorout_with_lock: + + spin_unlock_irqrestore(flags); + + return src_apb; +} + +/* Apply SRC on incoming APB and add one or more APBs to the + * out queue accordingly. + */ + +static int cxd56_src_process(FAR struct ap_buffer_s *apb) +{ + int ret = OK; + irqstate_t flags; + struct ap_buffer_s *src_apb; + + /* audinfo("SRC: Process (size = %d)\n", apb->nbytes); */ + +#ifdef DUMP_DATA + write(dump_file_pre, + (char *) (apb->samp + apb->curbyte), + apb->nbytes - apb->curbyte); +#endif + + /* Special case of one-to-one ratio */ + + if (g_src.src_data.src_ratio == 1.0f) + { + src_apb = cxd56_src_get_apb(); + if (!src_apb) + { + ret = -ENOMEM; + goto exit; + } + + memcpy(src_apb->samp, apb->samp, apb->nbytes); + src_apb->nbytes = apb->nbytes; + src_apb->flags |= AUDIO_APB_SRC_FINAL; + + flags = spin_lock_irqsave(); + dq_put(g_src.outq, &src_apb->dq_entry); + spin_unlock_irqrestore(flags); + + goto exit; + } + + /* Perform SRC on new buffer and left overs from previous ones */ + + while (apb->curbyte < apb->nbytes) + { + int float_in_left; + int frames_in; + + short *apb_addr = (const short *)(apb->samp + apb->curbyte); + + /* Fill up incoming float buffer */ + + float_in_left = BUFFER_SAMPLES - g_src.float_in_offset; + + src_short_to_float_array(apb_addr, + (g_src.float_in + g_src.float_in_offset), + float_in_left); + g_src.src_data.output_frames = BUFFER_SAMPLES / g_src.channels; + g_src.src_data.input_frames = BUFFER_SAMPLES / g_src.channels; + + /* Incoming data larger than ingoing float buffer? */ + + frames_in = (apb->nbytes - apb->curbyte) / g_src.bytewidth; + + if (frames_in >= float_in_left || g_src.state == CXD56_SRC_STOPPING) + { + int apb_nframes; + int apb_nmaxframes; + int src_nframes; + int src_copyframes; + + float *float_out_src; + short *src_apb_dest; + + /* Run SRC */ + + g_src.src_data.data_out = g_src.float_out; + g_src.src_data.data_in = g_src.float_in; + + ret = src_process(g_src.src_state, &g_src.src_data); + if (ret != 0) + { + auderr("ERROR: SRC failed (\"%s\")\n", src_strerror(ret)); + } + + /* Move unused data to start of float_in for next round */ + + g_src.float_in_offset = + g_src.src_data.input_frames_used * g_src.channels; + memcpy((void *)g_src.float_in, + (void *)(g_src.float_in + g_src.float_in_offset), + (BUFFER_SAMPLES - g_src.float_in_offset) * sizeof(float)); + + g_src.float_in_offset = BUFFER_SAMPLES - g_src.float_in_offset; + + /* Prepare apb to dma */ + + src_apb = cxd56_src_get_apb(); + if (!src_apb) + { + ret = -ENOMEM; + goto exit; + } + + apb_nframes = + src_apb->nbytes / g_src.bytewidth / g_src.channels; + apb_nmaxframes = + src_apb->nmaxbytes / g_src.bytewidth / g_src.channels; + + src_nframes = g_src.src_data.output_frames_gen; + src_copyframes = apb_nmaxframes - apb_nframes; + + /* Generated frames will exceed apb size left */ + + if (apb_nframes + src_nframes >= apb_nmaxframes + || g_src.state == CXD56_SRC_STOPPING) + { + /* Convert SRC float data into APB to be sent */ + + float_out_src = g_src.float_out; + src_apb_dest = (short *)(src_apb->samp + src_apb->nbytes); + + src_float_to_short_array(float_out_src, src_apb_dest, + src_copyframes * g_src.channels); + src_nframes -= src_copyframes; + src_apb->nbytes = src_apb->nmaxbytes; + + /* Increase SRC buffer processing counter */ + + g_src.buf_count += g_src.buf_increment; + if (g_src.buf_count > 1.0f) + { + src_apb->flags |= AUDIO_APB_SRC_FINAL; + g_src.buf_count -= 1.0f; + } + + /* Put in out queue to be DMA'd */ + + flags = spin_lock_irqsave(); + dq_put(g_src.outq, &src_apb->dq_entry); + spin_unlock_irqrestore(flags); + +#ifdef DUMP_DATA + write(dump_file_post, src_apb->samp, src_apb->nbytes); +#endif + + /* Fetch the next APB to fill up */ + + src_apb = cxd56_src_get_apb(); + if (!src_apb) + { + ret = -ENOMEM; + goto exit; + } + + apb_nframes = + src_apb->nbytes / g_src.bytewidth / g_src.channels; + } + + /* Convert remaining SRC float data into next APB */ + + float_out_src = g_src.float_out + src_copyframes * g_src.channels; + src_apb_dest = (short *)(src_apb->samp + src_apb->nbytes); + + src_float_to_short_array(float_out_src, src_apb_dest, + src_nframes * g_src.channels); + + src_apb->nbytes += g_src.bytewidth * src_nframes * g_src.channels; + + flags = spin_lock_irqsave(); + dq_put_back(g_src.inq, &src_apb->dq_entry); + spin_unlock_irqrestore(flags); + + apb->curbyte += (float_in_left * g_src.bytewidth); + } + else + { + g_src.float_in_offset += frames_in; + apb->curbyte = apb->nbytes - 1; + + break; + } + } + +exit: + return ret; +} + +/* SRC control and processing thread */ + +static void *cxd56_src_thread(pthread_addr_t pvarg) +{ + struct audio_msg_s msg; + unsigned int prio; + int ret; + int size; + + audinfo("SRC: Thread started\n"); + + g_src.state = CXD56_SRC_RUNNING; + + while (g_src.state == CXD56_SRC_RUNNING) + { + size = nxmq_receive(g_src.mq, (FAR char *)&msg, sizeof(msg), &prio); + + /* Handle the case when we return with no message */ + + if (size == 0) + { + audinfo("SRC: Zero message, stop\n"); + g_src.state = CXD56_SRC_STOPPED; + break; + } + + /* Process the message */ + + switch (msg.msg_id) + { + case AUDIO_MSG_START: + break; + case AUDIO_MSG_STOP: + g_src.state = CXD56_SRC_STOPPED; + break; + case AUDIO_MSG_ENQUEUE: + ret = cxd56_src_process(msg.u.ptr); + if (ret != OK) + { + auderr("ERROR: SRC processing failed (%d)\n", ret); + g_src.state = CXD56_SRC_STOPPED; + } + break; + } + } + + return NULL; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: cxd56_src_init + * + * Description: Initializes the SRC using audio settings set in the given + * audio device. When SRC is running the resulting buffers will + * be put into the queue "outq" for playback, and after it has + * been played it is expected to be put in the "inq" queue to be + * filled up with new data. + * + ****************************************************************************/ + +int cxd56_src_init(FAR struct cxd56_dev_s *dev, + FAR struct dq_queue_s *inq, + FAR struct dq_queue_s *outq) +{ + struct sched_param sparam; + struct mq_attr m_attr; + pthread_attr_t t_attr; + void *value; + int error; + int ret = OK; + + g_src.buf_count = 0.0f; + if (dev->samplerate < 48000) + { + g_src.buf_increment = dev->samplerate / 48000.0f; + } + + g_src.inq = inq; + g_src.outq = outq; + g_src.bytewidth = dev->bitwidth / 8; + g_src.channels = dev->channels; + g_src.float_in_offset = 0; + snprintf(g_src.mqname, sizeof(g_src.mqname), "/tmp/%X", &g_src); + + audinfo("SRC: Init (rate = %d, channels = %d, width = %d)\n", + dev->samplerate, g_src.channels, g_src.bytewidth); + + m_attr.mq_maxmsg = 16; + m_attr.mq_msgsize = sizeof(struct audio_msg_s); + m_attr.mq_curmsgs = 0; + m_attr.mq_flags = 0; + + g_src.mq = mq_open(g_src.mqname, O_RDWR | O_CREAT, 0644, &m_attr); + if (g_src.mq == NULL) + { + auderr("ERROR: Could not allocate SRC message queue.\n"); + return -ENOMEM; + } + +#ifdef DUMP_DATA + unlink(dump_name_pre); + unlink(dump_name_post); + dump_file_pre = open(dump_name_pre, O_WRONLY | O_CREAT | O_APPEND); + dump_file_post = open(dump_name_post, O_WRONLY | O_CREAT | O_APPEND); +#endif + + /* Join any old worker threads to prevent memory leaks */ + + if (g_src.threadid != 0) + { + pthread_join(g_src.threadid, &value); + } + + pthread_attr_init(&t_attr); + sparam.sched_priority = sched_get_priority_max(SCHED_FIFO) - 3; + (void)pthread_attr_setschedparam(&t_attr, &sparam); + (void)pthread_attr_setstacksize(&t_attr, + CONFIG_CXD56_AUDIO_SRC_STACKSIZE); + + ret = pthread_create(&g_src.threadid, &t_attr, cxd56_src_thread, + (pthread_addr_t)&g_src); + if (ret != OK) + { + auderr("ERROR: SRC pthread_create failed (%d)\n", ret); + return ret; + } + + pthread_setname_np(g_src.threadid, "cxd56_src"); + + /* Initialize sample rate converter */ + + g_src.src_data.src_ratio = (double) (48000.0f / dev->samplerate); + if (g_src.src_data.src_ratio == 1.0f) + { + audinfo("SRC in and out rate is the same, will copy only.\n"); + } + + g_src.src_state = src_new(SRC_LINEAR, g_src.channels, &error); + if (g_src.src_state == NULL) + { + auderr("ERROR: Could not initialize SRC (%d)\n", src_strerror(error)); + ret = error; + } + + return ret; +} + +/**************************************************************************** + * Name: cxd56_src_deinit + * + * Description: Releases the SRC instance and related resources. + * + ****************************************************************************/ + +int cxd56_src_deinit(void) +{ + struct ap_buffer_s *src_apb; + + audinfo("SRC: Deinit\n"); + + /* Free SRC buffers */ + + while (dq_count(g_src.inq)) + { + src_apb = (struct ap_buffer_s *) dq_get(g_src.inq); + kmm_free(src_apb); + } + + while (dq_count(g_src.outq)) + { + src_apb = (struct ap_buffer_s *) dq_get(g_src.outq); + kmm_free(src_apb); + } + + src_delete(g_src.src_state); + +#ifdef DUMP_DATA + if (dump_file_pre) + close(dump_file_pre); + + if (dump_file_post) + close(dump_file_post); +#endif + + return OK; +} + +/**************************************************************************** + * Name: cxd56_src_enqueue + * + * Description: Enqueues a audio buffer for SRC processing. The result will + * be put in the outgoing queue given during initialization. + * + ****************************************************************************/ + +int cxd56_src_enqueue(FAR struct ap_buffer_s *apb) +{ + int ret; + struct audio_msg_s msg; + + audinfo("SRC: Enqueue %x\n", apb); + + msg.msg_id = AUDIO_MSG_ENQUEUE; + msg.u.ptr = apb; + ret = nxmq_send(g_src.mq, (FAR const char *)&msg, + sizeof(msg), CONFIG_CXD56_MSG_PRIO); + if (ret != OK) + { + auderr("ERROR: SRC APB enqueue failed (%d)\n", ret); + } + + return ret; +} + +/**************************************************************************** + * Name: cxd56_src_stop + * + * Description: Stops the SRC processing thread. + * + ****************************************************************************/ + +int cxd56_src_stop(void) +{ + int ret; + void *value; + struct audio_msg_s msg; + + audinfo("SRC: Stop\n"); + + msg.msg_id = AUDIO_MSG_STOP; + msg.u.data = 0; + ret = nxmq_send(g_src.mq, (FAR const char *)&msg, + sizeof(msg), CONFIG_CXD56_MSG_PRIO); + if (ret != OK) + { + auderr("ERROR: SRC stop failed (%d)\n", ret); + } + + pthread_join(g_src.threadid, &value); + g_src.threadid = 0; + + return ret; +} diff --git a/drivers/audio/cxd56_src.h b/drivers/audio/cxd56_src.h new file mode 100644 index 00000000000..e05a190caf2 --- /dev/null +++ b/drivers/audio/cxd56_src.h @@ -0,0 +1,120 @@ +/**************************************************************************** + * drivers/audio/cxd56_src.h + * + * Copyright 2020 Sony Semiconductor Solutions Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __DRIVERS_AUDIO_CXD56_SRC_H +#define __DRIVERS_AUDIO_CXD56_SRC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#ifdef CONFIG_AUDIO + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_CXD56_AUDIO_SRC_STACKSIZE +# define CONFIG_CXD56_AUDIO_SRC_STACKSIZE 768 +#endif + +#ifndef CONFIG_CXD56_SRC_MSG_PRIO +# define CONFIG_CXD56_SRC_MSG_PRIO 1 +#endif + +#ifndef SRC_SINC_BEST_QUALITY +# define SRC_SINC_BEST_QUALITY 0 +#endif + +#ifndef SRC_SINC_MEDIUM_QUALITY +# define SRC_SINC_MEDIUM_QUALITY 1 +#endif + +#ifndef SRC_SINC_FASTEST +# define SRC_SINC_FASTEST 2 +#endif + +#ifndef SRC_ZERO_ORDER_HOLD +# define SRC_ZERO_ORDER_HOLD 3 +#endif + +#ifndef SRC_LINEAR +# define SRC_LINEAR 4 +#endif + +#define AUDIO_APB_SRC_FINAL (1 << 4) /* Last buffer in SRC processing */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef struct SRC_STATE_TAG SRC_STATE; + +typedef struct +{ + const float *data_in; + float *data_out; + long input_frames; + long output_frames; + long input_frames_used; + long output_frames_gen; + int end_of_input; + double src_ratio; +} SRC_DATA; + +SRC_STATE *src_new (int converter_type, int channels, int *error); + +SRC_STATE *src_delete (SRC_STATE *state); + +int src_process (SRC_STATE *state, SRC_DATA *data); + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +int cxd56_src_init(FAR struct cxd56_dev_s *dev, FAR struct dq_queue_s *inq, + FAR struct dq_queue_s *outq); +int cxd56_src_deinit(void); +int cxd56_src_enqueue(FAR struct ap_buffer_s *apb); +int cxd56_src_stop(void); + +#endif /* CONFIG_AUDIO */ + +#endif /* __DRIVERS_AUDIO_CXD56_SRC_H */ diff --git a/drivers/audio/vs1053.c b/drivers/audio/vs1053.c index 296c26211cf..5dcf1c3e5e9 100644 --- a/drivers/audio/vs1053.c +++ b/drivers/audio/vs1053.c @@ -45,6 +45,7 @@ #include #include +#include #include #include #include @@ -1486,7 +1487,8 @@ static int vs1053_start(FAR struct audio_lowerhalf_s *lower) /* Create a message queue for the worker thread */ - snprintf(dev->mqname, sizeof(dev->mqname), "/tmp/%X", dev); + snprintf(dev->mqname, sizeof(dev->mqname), "/tmp/%" PRIXPTR, + (uintptr_t)dev); attr.mq_maxmsg = 16; attr.mq_msgsize = sizeof(struct audio_msg_s); attr.mq_curmsgs = 0; diff --git a/drivers/audio/wm8776.c b/drivers/audio/wm8776.c index dc35179f42a..8794965710c 100644 --- a/drivers/audio/wm8776.c +++ b/drivers/audio/wm8776.c @@ -27,6 +27,7 @@ #include #include +#include #include #include #include @@ -747,7 +748,8 @@ static int wm8776_start(FAR struct audio_lowerhalf_s *dev) /* Create a message queue for the worker thread */ - snprintf(priv->mqname, sizeof(priv->mqname), "/tmp/%X", priv); + snprintf(priv->mqname, sizeof(priv->mqname), "/tmp/%" PRIXPTR, + (uintptr_t)priv); attr.mq_maxmsg = 16; attr.mq_msgsize = sizeof(struct audio_msg_s); diff --git a/drivers/audio/wm8904.c b/drivers/audio/wm8904.c index cb10c23d87c..1ddb4e15684 100644 --- a/drivers/audio/wm8904.c +++ b/drivers/audio/wm8904.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include #include @@ -1603,7 +1604,8 @@ static int wm8904_start(FAR struct audio_lowerhalf_s *dev) /* Create a message queue for the worker thread */ - snprintf(priv->mqname, sizeof(priv->mqname), "/tmp/%X", priv); + snprintf(priv->mqname, sizeof(priv->mqname), "/tmp/%" PRIXPTR, + (uintptr_t)priv); attr.mq_maxmsg = 16; attr.mq_msgsize = sizeof(struct audio_msg_s); diff --git a/drivers/bch/bchlib_cache.c b/drivers/bch/bchlib_cache.c index 02d39ed2e59..dc39d821a19 100644 --- a/drivers/bch/bchlib_cache.c +++ b/drivers/bch/bchlib_cache.c @@ -142,7 +142,7 @@ int bchlib_flushsector(FAR struct bchlib_s *bch) ret = inode->u.i_bops->write(inode, bch->buffer, bch->sector, 1); if (ret < 0) { - ferr("Write failed: %d\n"); + ferr("Write failed: %zd\n", ret); } #if defined(CONFIG_BCH_ENCRYPTION) @@ -187,7 +187,7 @@ int bchlib_readsector(FAR struct bchlib_s *bch, size_t sector) ret = inode->u.i_bops->read(inode, bch->buffer, sector, 1); if (ret < 0) { - ferr("Read failed: %d\n"); + ferr("Read failed: %zd\n", ret); } bch->sector = sector; diff --git a/drivers/bch/bchlib_read.c b/drivers/bch/bchlib_read.c index 1a28995a1f7..770dded807f 100644 --- a/drivers/bch/bchlib_read.c +++ b/drivers/bch/bchlib_read.c @@ -159,7 +159,7 @@ ssize_t bchlib_read(FAR void *handle, FAR char *buffer, size_t offset, sector, nsectors); if (ret < 0) { - ferr("ERROR: Read failed: %d\n"); + ferr("ERROR: Read failed: %d\n", ret); return ret; } diff --git a/drivers/i2c/i2c_driver.c b/drivers/i2c/i2c_driver.c index f326469635f..6dded767ba7 100644 --- a/drivers/i2c/i2c_driver.c +++ b/drivers/i2c/i2c_driver.c @@ -239,7 +239,7 @@ static int i2cdrvr_ioctl(FAR struct file *filep, int cmd, unsigned long arg) FAR struct i2c_transfer_s *transfer; int ret; - i2cinfo("cmd=%x arg=%08x\n", cmd, arg); + i2cinfo("cmd=%x arg=%08lx\n", cmd, arg); /* Get our private data structure */ diff --git a/drivers/input/button_lower.c b/drivers/input/button_lower.c index 06aaff3e424..e045af7d9c5 100644 --- a/drivers/input/button_lower.c +++ b/drivers/input/button_lower.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include @@ -98,7 +99,7 @@ static FAR void *g_btnarg; static btn_buttonset_t btn_supported(FAR const struct btn_lowerhalf_s *lower) { - iinfo("NUM_BUTTONS: %02x\n", g_btnnum); + iinfo("NUM_BUTTONS: %02" PRIx32 "\n", g_btnnum); return (btn_buttonset_t)((1 << g_btnnum) - 1); } @@ -138,7 +139,7 @@ static void btn_enable(FAR const struct btn_lowerhalf_s *lower, flags = enter_critical_section(); btn_disable(); - iinfo("press: %02x release: %02x handler: %p arg: %p\n", + iinfo("press: %02" PRIx32 " release: %02" PRIx32 " handler: %p arg: %p\n", press, release, handler, arg); /* If no events are indicated or if no handler is provided, then this diff --git a/drivers/input/button_upper.c b/drivers/input/button_upper.c index 8f4020db208..8f281c89fdf 100644 --- a/drivers/input/button_upper.c +++ b/drivers/input/button_upper.c @@ -575,7 +575,8 @@ static int btn_ioctl(FAR struct file *filep, int cmd, unsigned long arg) switch (cmd) { /* Command: BTNIOC_SUPPORTED - * Description: Report the set of button events supported by the hardware; + * Description: Report the set of button events supported by the + * hardware; * Argument: A pointer to writeable integer value in which to return * the set of supported buttons. * Return: Zero (OK) on success. Minus one will be returned on @@ -662,7 +663,7 @@ static int btn_ioctl(FAR struct file *filep, int cmd, unsigned long arg) break; default: - ierr("ERROR: Unrecognized command: %ld\n", cmd); + ierr("ERROR: Unrecognized command: %d\n", cmd); ret = -ENOTTY; break; } @@ -782,7 +783,6 @@ errout_with_dusem: int btn_register(FAR const char *devname, FAR const struct btn_lowerhalf_s *lower) - { FAR struct btn_upperhalf_s *priv; int ret; diff --git a/drivers/leds/apa102.c b/drivers/leds/apa102.c index a2a41512a5f..6b40f4f8a44 100644 --- a/drivers/leds/apa102.c +++ b/drivers/leds/apa102.c @@ -139,6 +139,7 @@ static inline void apa102_write32(FAR struct apa102_dev_s *priv, apa102_configspi(priv->spi); /* Note: APA102 doesn't use chip select */ + /* Send 32 bits (4 bytes) */ SPI_SEND(priv->spi, (value & 0xff)); @@ -168,7 +169,7 @@ static int apa102_open(FAR struct file *filep) * Name: apa102_close * * Description: - * This routine is called when the LM-75 device is closed. + * This routine is called when the APA102 device is closed. * ****************************************************************************/ @@ -181,7 +182,8 @@ static int apa102_close(FAR struct file *filep) * Name: apa102_read ****************************************************************************/ -static ssize_t apa102_read(FAR struct file *filep, FAR char *buffer, size_t buflen) +static ssize_t apa102_read(FAR struct file *filep, FAR char *buffer, + size_t buflen) { return -ENOSYS; } @@ -217,7 +219,8 @@ static ssize_t apa102_write(FAR struct file *filep, FAR const char *buffer, if ((buflen % 4) != 0) { - snerr("ERROR: Each LED uses 4 bytes, so (buflen % 4) needs to be 0!\n"); + snerr("ERROR: Each LED uses 4 bytes, so (buflen % 4)" + " needs to be 0!\n"); return -1; } @@ -240,7 +243,7 @@ static ssize_t apa102_write(FAR struct file *filep, FAR const char *buffer, apa102_write32(priv, APA102_END_FRAME); - for (i = 0; i < (1 + nleds/32); i++) + for (i = 0; i < (1 + nleds / 32); i++) { apa102_write32(priv, 0); } @@ -262,11 +265,8 @@ static ssize_t apa102_write(FAR struct file *filep, FAR const char *buffer, * * Input Parameters: * devpath - The full path to the driver to register. E.g., "/dev/temp0" - * i2c - An instance of the I2C interface to use to communicate with + * spi - An instance of the SPI interface to use to communicate with * APA102 - * addr - The I2C address of the LM-75. The base I2C address of the - * APA102 is 0x48. Bits 0-3 can be controlled to get 8 unique - * addresses from 0x48 through 0x4f. * * Returned Value: * Zero (OK) on success; a negated errno value on failure. diff --git a/drivers/leds/userled_lower.c b/drivers/leds/userled_lower.c index 70e8b12d7ce..90bd9526020 100644 --- a/drivers/leds/userled_lower.c +++ b/drivers/leds/userled_lower.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include @@ -89,7 +90,7 @@ static const struct userled_lowerhalf_s g_userled_lower = static userled_set_t userled_supported(FAR const struct userled_lowerhalf_s *lower) { - ledinfo("BOARD_NLEDS: %02x\n", g_lednum); + ledinfo("BOARD_NLEDS: %02" PRIx32 "\n", g_lednum); return (userled_set_t)((1 << g_lednum) - 1); } diff --git a/drivers/leds/userled_upper.c b/drivers/leds/userled_upper.c index bd69bf118f3..562faba5268 100644 --- a/drivers/leds/userled_upper.c +++ b/drivers/leds/userled_upper.c @@ -169,7 +169,8 @@ static int userled_open(FAR struct file *filep) /* Allocate a new open structure */ - opriv = (FAR struct userled_open_s *)kmm_zalloc(sizeof(struct userled_open_s)); + opriv = (FAR struct userled_open_s *) + kmm_zalloc(sizeof(struct userled_open_s)); if (!opriv) { lederr("ERROR: Failed to allocate open structure\n"); @@ -347,7 +348,8 @@ static int userled_ioctl(FAR struct file *filep, int cmd, unsigned long arg) FAR const struct userled_lowerhalf_s *lower; int ret; - DEBUGASSERT(filep != NULL && filep->f_priv != NULL && filep->f_inode != NULL); + DEBUGASSERT(filep != NULL && filep->f_priv != NULL && + filep->f_inode != NULL); inode = filep->f_inode; DEBUGASSERT(inode->i_private); priv = (FAR struct userled_upperhalf_s *)inode->i_private; @@ -370,8 +372,8 @@ static int userled_ioctl(FAR struct file *filep, int cmd, unsigned long arg) * Description: Report the set of LEDs supported by the hardware; * Argument: A pointer to writeable userled_set_t value in which to * return the set of supported LEDs. - * Return: Zero (OK) on success. Minus one will be returned on failure - * with the errno value set appropriately. + * Return: Zero (OK) on success. Minus one will be returned on + * failure with the errno value set appropriately. */ case ULEDIOC_SUPPORTED: @@ -391,13 +393,14 @@ static int userled_ioctl(FAR struct file *filep, int cmd, unsigned long arg) /* Command: ULEDIOC_SETLED * Description: Set the state of one LED. * Argument: A read-only pointer to an instance of struct userled_s - * Return: Zero (OK) on success. Minus one will be returned on failure - * with the errno value set appropriately. + * Return: Zero (OK) on success. Minus one will be returned on + * failure with the errno value set appropriately. */ case ULEDIOC_SETLED: { - FAR struct userled_s *userled = (FAR struct userled_s *)((uintptr_t)arg); + FAR struct userled_s *userled = (FAR struct userled_s *) + ((uintptr_t)arg); int led; bool ledon; @@ -438,8 +441,8 @@ static int userled_ioctl(FAR struct file *filep, int cmd, unsigned long arg) /* Command: ULEDIOC_SETALL * Description: Set the state of all LEDs. * Argument: A value of type userled_set_t cast to unsigned long - * Return: Zero (OK) on success. Minus one will be returned on failure - * with the errno value set appropriately. + * Return: Zero (OK) on success. Minus one will be returned on + * failure with the errno value set appropriately. */ case ULEDIOC_SETALL: @@ -466,10 +469,10 @@ static int userled_ioctl(FAR struct file *filep, int cmd, unsigned long arg) /* Command: ULEDIOC_GETALL * Description: Get the state of one LED. - * Argument: A write-able pointer to a userled_set_t memory location in - * which to return the LED state. - * Return: Zero (OK) on success. Minus one will be returned on failure - * with the errno value set appropriately. + * Argument: A write-able pointer to a userled_set_t memory location + * in which to return the LED state. + * Return: Zero (OK) on success. Minus one will be returned on + * failure with the errno value set appropriately. */ case ULEDIOC_GETALL: @@ -487,7 +490,7 @@ static int userled_ioctl(FAR struct file *filep, int cmd, unsigned long arg) break; default: - lederr("ERROR: Unrecognized command: %ld\n", cmd); + lederr("ERROR: Unrecognized command: %d\n", cmd); ret = -ENOTTY; break; } diff --git a/drivers/loop/losetup.c b/drivers/loop/losetup.c index df2f8e77d93..427467cef9d 100644 --- a/drivers/loop/losetup.c +++ b/drivers/loop/losetup.c @@ -228,7 +228,7 @@ static ssize_t loop_read(FAR struct inode *inode, FAR unsigned char *buffer, nsectors * dev->sectsize); if (nbytesread < 0 && nbytesread != -EINTR) { - ferr("ERROR: Read failed: %d\n", nbytesread); + ferr("ERROR: Read failed: %zd\n", nbytesread); return (int)nbytesread; } } @@ -275,7 +275,7 @@ static ssize_t loop_write(FAR struct inode *inode, nsectors * dev->sectsize); if (nbyteswritten < 0 && nbyteswritten != -EINTR) { - ferr("ERROR: nx_write failed: %d\n", nbyteswritten); + ferr("ERROR: nx_write failed: %zd\n", nbyteswritten); return nbyteswritten; } } diff --git a/drivers/mmcsd/mmcsd_sdio.c b/drivers/mmcsd/mmcsd_sdio.c index 11cfffb0e33..1d16a8a4825 100644 --- a/drivers/mmcsd/mmcsd_sdio.c +++ b/drivers/mmcsd/mmcsd_sdio.c @@ -31,6 +31,7 @@ #include #include +#include #include #include #include @@ -321,7 +322,8 @@ static int mmcsd_sendcmdpoll(FAR struct mmcsd_state_s *priv, uint32_t cmd, ret = SDIO_WAITRESPONSE(priv->dev, cmd); if (ret != OK) { - ferr("ERROR: Wait for response to cmd: %08x failed: %d\n", + ferr("ERROR: Wait for response to cmd: %08" PRIx32 + " failed: %d\n", cmd, ret); } } @@ -395,7 +397,7 @@ static int mmsd_recv_r1(FAR struct mmcsd_state_s *priv, uint32_t cmd) * indication for later use. */ - ferr("ERROR: R1=%08x\n", r1); + ferr("ERROR: R1=%08" PRIx32 "\n", r1); priv->locked = ((r1 & MMCSD_R1_CARDISLOCKED) != 0); ret = -EIO; } @@ -449,7 +451,7 @@ static int mmsd_recv_r6(FAR struct mmcsd_state_s *priv, uint32_t cmd) ret = -EIO; } - ferr("ERROR: Failed to get RCA. R6=%08x: %d\n", r6, ret); + ferr("ERROR: Failed to get RCA. R6=%08" PRIx32 ": %d\n", r6, ret); return ret; } @@ -1066,7 +1068,7 @@ static int mmcsd_get_r1(FAR struct mmcsd_state_s *priv, FAR uint32_t *r1) /* We must tell someone which error bits were set. */ - fwarn("WARNING: mmcsd_get_r1 returned errors: R1=%08x\n", + fwarn("WARNING: mmcsd_get_r1 returned errors: R1=%08" PRIx32 "\n", local_r1); ret = -EIO; } @@ -1271,7 +1273,7 @@ static int mmcsd_transferready(FAR struct mmcsd_state_s *priv) * if this error occurs. */ - ferr("ERROR: Unexpected R1 state: %08x\n", r1); + ferr("ERROR: Unexpected R1 state: %08" PRIx32 "\n", r1); ret = -EINVAL; goto errorout; } @@ -1368,7 +1370,7 @@ static ssize_t mmcsd_readsingle(FAR struct mmcsd_state_s *priv, off_t offset; int ret; - finfo("startblock=%d\n", startblock); + finfo("startblock=%jd\n", (intmax_t)startblock); DEBUGASSERT(priv != NULL && buffer != NULL); /* Check if the card is locked */ @@ -1422,7 +1424,7 @@ static ssize_t mmcsd_readsingle(FAR struct mmcsd_state_s *priv, offset = startblock << priv->blockshift; } - finfo("offset=%d\n", offset); + finfo("offset=%jd\n", (intmax_t)offset); /* Select the block size for the card */ @@ -1505,7 +1507,7 @@ static ssize_t mmcsd_readmultiple(FAR struct mmcsd_state_s *priv, off_t offset; int ret; - finfo("startblock=%d nblocks=%d\n", startblock, nblocks); + finfo("startblock=%jd nblocks=%zu\n", (intmax_t)startblock, nblocks); DEBUGASSERT(priv != NULL && buffer != NULL && nblocks > 1); /* Check if the card is locked */ @@ -1561,7 +1563,7 @@ static ssize_t mmcsd_readmultiple(FAR struct mmcsd_state_s *priv, offset = startblock << priv->blockshift; } - finfo("nbytes=%d byte offset=%d\n", nbytes, offset); + finfo("nbytes=%zu byte offset=%jd\n", nbytes, (intmax_t)offset); /* Select the block size for the card */ @@ -1713,7 +1715,7 @@ static ssize_t mmcsd_writesingle(FAR struct mmcsd_state_s *priv, off_t offset; int ret; - finfo("startblock=%d\n", startblock); + finfo("startblock=%jd\n", (intmax_t)startblock); DEBUGASSERT(priv != NULL && buffer != NULL); /* Check if the card is locked or write protected (either via software or @@ -1769,7 +1771,7 @@ static ssize_t mmcsd_writesingle(FAR struct mmcsd_state_s *priv, offset = startblock << priv->blockshift; } - finfo("offset=%d\n", offset); + finfo("offset=%jd\n", (intmax_t)offset); /* Select the block size for the card */ @@ -1883,7 +1885,7 @@ static ssize_t mmcsd_writemultiple(FAR struct mmcsd_state_s *priv, int ret; int evret = OK; - finfo("startblock=%d nblocks=%d\n", startblock, nblocks); + finfo("startblock=%jd nblocks=%zu\n", (intmax_t)startblock, nblocks); DEBUGASSERT(priv != NULL && buffer != NULL && nblocks > 1); /* Check if the card is locked or write protected (either via software or @@ -1941,7 +1943,7 @@ static ssize_t mmcsd_writemultiple(FAR struct mmcsd_state_s *priv, offset = startblock << priv->blockshift; } - finfo("nbytes=%d byte offset=%d\n", nbytes, offset); + finfo("nbytes=%zu byte offset=%jd\n", nbytes, (intmax_t)offset); /* Select the block size for the card */ @@ -3196,7 +3198,7 @@ static int mmcsd_cardidentify(FAR struct mmcsd_state_s *priv) } else { - ferr("ERROR: R7: %08x\n", response); + ferr("ERROR: R7: %08" PRIx32 "\n", response); return -EIO; } } @@ -3259,7 +3261,7 @@ static int mmcsd_cardidentify(FAR struct mmcsd_state_s *priv) * must be SD V1.x */ - finfo("R3: %08x\n", response); + finfo("R3: %08" PRIx32 "\n", response); if (priv->type == MMCSD_CARDTYPE_UNKNOWN) { finfo("SD V1.x card\n"); diff --git a/drivers/mmcsd/mmcsd_spi.c b/drivers/mmcsd/mmcsd_spi.c index 0bdb467a2dd..812faff2c19 100644 --- a/drivers/mmcsd/mmcsd_spi.c +++ b/drivers/mmcsd/mmcsd_spi.c @@ -28,6 +28,7 @@ #include +#include #include #include #include @@ -563,11 +564,11 @@ static uint32_t mmcsd_sendcmd(FAR struct mmcsd_slot_s *slot, if (busy != 0xff) { - ferr("ERROR: Failed: card still busy (%02x)\n", busy); + ferr("ERROR: Failed: card still busy (%02" PRIx32 ")\n", busy); return (uint32_t)-1; } - finfo("CMD%d[%08x] R1B=%02x\n", + finfo("CMD%d[%08" PRIx32 "] R1B=%02" PRIx8 "\n", cmd->cmd & 0x3f, arg, response); } break; @@ -576,7 +577,7 @@ static uint32_t mmcsd_sendcmd(FAR struct mmcsd_slot_s *slot, case MMCSD_CMDRESP_R1: { - finfo("CMD%d[%08x] R1=%02x\n", + finfo("CMD%d[%08" PRIx32 "] R1=%02" PRIx8 "\n", cmd->cmd & 0x3f, arg, response); } break; @@ -588,7 +589,7 @@ static uint32_t mmcsd_sendcmd(FAR struct mmcsd_slot_s *slot, result = ((uint32_t)(response & 0xff) << 8); result |= SPI_SEND(spi, 0xff) & 0xff; - finfo("CMD%d[%08x] R2=%04x\n", + finfo("CMD%d[%08" PRIx32 "] R2=%04" PRIx32 "\n", cmd->cmd & 0x3f, arg, result); } break; @@ -602,7 +603,7 @@ static uint32_t mmcsd_sendcmd(FAR struct mmcsd_slot_s *slot, slot->ocr |= ((uint32_t)(SPI_SEND(spi, 0xff) & 0xff) << 8); slot->ocr |= SPI_SEND(spi, 0xff) & 0xff; - finfo("CMD%d[%08x] R1=%02x OCR=%08x\n", + finfo("CMD%d[%08" PRIx32 "] R1=%02" PRIx8 " OCR=%08" PRIx32 "\n", cmd->cmd & 0x3f, arg, response, slot->ocr); } break; @@ -617,7 +618,7 @@ static uint32_t mmcsd_sendcmd(FAR struct mmcsd_slot_s *slot, slot->r7 |= ((uint32_t)(SPI_SEND(spi, 0xff) & 0xff) << 8); slot->r7 |= SPI_SEND(spi, 0xff) & 0xff; - finfo("CMD%d[%08x] R1=%02x R7=%08x\n", + finfo("CMD%d[%08" PRIx32 "] R1=%02" PRIx8 " R7=%08" PRIx32 "\n", cmd->cmd & 0x3f, arg, response, slot->r7); } break; @@ -641,11 +642,11 @@ static void mmcsd_setblklen(FAR struct mmcsd_slot_s *slot, uint32_t length) { uint32_t response; - finfo("Set block length to %d\n", length); + finfo("Set block length to %" PRId32 "\n", length); response = mmcsd_sendcmd(slot, &g_cmd16, length); if (response != MMCSD_SPIR1_OK) { - ferr("ERROR: Failed to set block length: %02x\n", response); + ferr("ERROR: Failed to set block length: %02" PRIx32 "\n", response); } } @@ -792,10 +793,10 @@ static void mmcsd_decodecsd(FAR struct mmcsd_slot_s *slot, uint8_t *csd) } finfo("SPI Frequency\n"); - finfo(" Maximum: %d Hz\n", maxfrequency); - finfo(" Actual: %d Hz\n", frequency); - finfo("Read access time: %d ticks\n", slot->taccess); - finfo("Write access time: %d ticks\n", slot->twrite); + finfo(" Maximum: %" PRId32 " Hz\n", maxfrequency); + finfo(" Actual: %" PRId32 " Hz\n", frequency); + finfo("Read access time: %" PRId32 " ticks\n", slot->taccess); + finfo("Write access time: %" PRId32 " ticks\n", slot->twrite); /* Get the physical geometry of the card: sector size and number of * sectors. The card's total capacity is computed from @@ -866,7 +867,7 @@ static void mmcsd_decodecsd(FAR struct mmcsd_slot_s *slot, uint8_t *csd) #endif slot->nsectors = csize << csizemult; finfo("Sector size: %d\n", SECTORSIZE(slot)); - finfo("Number of sectors: %d\n", slot->nsectors); + finfo("Number of sectors: %" PRId32 "\n", slot->nsectors); } /**************************************************************************** @@ -923,7 +924,7 @@ static int mmcsd_getcardinfo(FAR struct mmcsd_slot_s *slot, uint8_t *buffer, result = mmcsd_sendcmd(slot, cmd, 0); if (result != MMCSD_SPIR1_OK) { - ferr("ERROR: CMD9/10 failed: R1=%02x\n", result); + ferr("ERROR: CMD9/10 failed: R1=%02" PRIx32 "\n", result); return -EIO; } @@ -959,7 +960,7 @@ static int mmcsd_getcardinfo(FAR struct mmcsd_slot_s *slot, uint8_t *buffer, } } - ferr("ERROR: %d. Did not find start of block\n"); + ferr("ERROR: Did not find start of block\n"); return -EIO; } @@ -1217,12 +1218,12 @@ static ssize_t mmcsd_read(FAR struct inode *inode, unsigned char *buffer, if (IS_BLOCK(slot->type)) { offset = start_sector; - finfo("nbytes=%d sector offset=%d\n", nbytes, offset); + finfo("nbytes=%zu sector offset=%jd\n", nbytes, (intmax_t)offset); } else { offset = start_sector * SECTORSIZE(slot); - finfo("nbytes=%d byte offset=%d\n", nbytes, offset); + finfo("nbytes=%zu byte offset=%jd\n", nbytes, (intmax_t)offset); } /* Select the slave */ @@ -1386,12 +1387,12 @@ static ssize_t mmcsd_write(FAR struct inode *inode, if (IS_BLOCK(slot->type)) { offset = start_sector; - finfo("nbytes=%d sector offset=%d\n", nbytes, offset); + finfo("nbytes=%zu sector offset=%jd\n", nbytes, (intmax_t)offset); } else { offset = start_sector * SECTORSIZE(slot); - finfo("nbytes=%d byte offset=%d\n", nbytes, offset); + finfo("nbytes=%zu byte offset=%jd\n", nbytes, (intmax_t)offset); } mmcsd_dumpbuffer("Write buffer", buffer, nbytes); @@ -1687,7 +1688,7 @@ static int mmcsd_mediainitialize(FAR struct mmcsd_slot_s *slot) if (result != MMCSD_SPIR1_IDLESTATE) { - ferr("ERROR: Send CMD0 failed: R1=%02x\n", result); + ferr("ERROR: Send CMD0 failed: R1=%02" PRIx32 "\n", result); SPI_SELECT(spi, SPIDEV_MMCSD(0), false); mmcsd_semgive(slot); return -EIO; @@ -1717,7 +1718,7 @@ static int mmcsd_mediainitialize(FAR struct mmcsd_slot_s *slot) elapsed = 0; do { - finfo("%d. Send CMD55/ACMD41\n", elapsed); + finfo("%ju. Send CMD55/ACMD41\n", (uintmax_t)elapsed); result = mmcsd_sendcmd(slot, &g_cmd55, 0); if (result == MMCSD_SPIR1_IDLESTATE || result == MMCSD_SPIR1_OK) @@ -1743,7 +1744,7 @@ static int mmcsd_mediainitialize(FAR struct mmcsd_slot_s *slot) result = mmcsd_sendcmd(slot, &g_cmd58, 0); if (result == MMCSD_SPIR1_OK) { - finfo("OCR: %08x\n", slot->ocr); + finfo("OCR: %08" PRIx32 "\n", slot->ocr); if ((slot->ocr & MMCSD_OCR_CCS) != 0) { finfo("Identified SD ver2 card/with block access\n"); @@ -1788,7 +1789,7 @@ static int mmcsd_mediainitialize(FAR struct mmcsd_slot_s *slot) { if (IS_SD(slot->type)) { - finfo("%d. Send CMD55/ACMD41\n", elapsed); + finfo("%ju. Send CMD55/ACMD41\n", (uintmax_t)elapsed); result = mmcsd_sendcmd(slot, &g_cmd55, 0); if (result == MMCSD_SPIR1_IDLESTATE || result == MMCSD_SPIR1_OK) @@ -1839,7 +1840,7 @@ static int mmcsd_mediainitialize(FAR struct mmcsd_slot_s *slot) result = mmcsd_getcsd(slot, csd); if (result != OK) { - ferr("ERROR: mmcsd_getcsd(CMD9) failed: %d\n", result); + ferr("ERROR: mmcsd_getcsd(CMD9) failed: %" PRId32 "\n", result); SPI_SELECT(spi, SPIDEV_MMCSD(0), false); mmcsd_semgive(slot); return -EIO; diff --git a/drivers/modem/altair/altmdm_spi.c b/drivers/modem/altair/altmdm_spi.c index 10738c38755..d2bccd6bad9 100644 --- a/drivers/modem/altair/altmdm_spi.c +++ b/drivers/modem/altair/altmdm_spi.c @@ -719,8 +719,8 @@ static void show_txheader(FAR struct altmdm_dev_s *priv) ****************************************************************************/ static void parse_rxheader(FAR struct altmdm_dev_s *priv, - FAR int *total_size, FAR int *actual_size, - FAR int *is_reset, FAR int *is_bufful) + FAR int32_t *total_size, FAR int32_t *actual_size, + FAR int *is_reset, FAR int32_t *is_bufful) { FAR struct altmdm_spi_xferhdr_s *rx_header = &priv->spidev.rx_param.header; @@ -1286,9 +1286,9 @@ static int do_xfersleep(FAR struct altmdm_dev_s *priv, uint32_t is_rcvrready) int ret; int resp = 0; int is_reset = 0; - int total_size; - int actual_size; - int is_bufful; + int32_t total_size; + int32_t actual_size; + int32_t is_bufful; /* Transfer header for sleep request */ diff --git a/drivers/mtd/ftl.c b/drivers/mtd/ftl.c index 7d20667fd53..2019e026e2f 100644 --- a/drivers/mtd/ftl.c +++ b/drivers/mtd/ftl.c @@ -26,6 +26,7 @@ #include #include +#include #include #include #include @@ -188,8 +189,8 @@ static ssize_t ftl_reload(FAR void *priv, FAR uint8_t *buffer, nread = MTD_BREAD(dev->mtd, startblock, nblocks, buffer); if (nread != nblocks) { - ferr("ERROR: Read %d blocks starting at block %d failed: %d\n", - nblocks, startblock, nread); + ferr("ERROR: Read %zu blocks starting at block %jd failed: %zd\n", + nblocks, (intmax_t)startblock, nread); } return nread; @@ -207,7 +208,7 @@ static ssize_t ftl_read(FAR struct inode *inode, unsigned char *buffer, { FAR struct ftl_struct_s *dev; - finfo("sector: %d nsectors: %d\n", start_sector, nsectors); + finfo("sector: %zu nsectors: %d\n", start_sector, nsectors); DEBUGASSERT(inode && inode->i_private); @@ -282,7 +283,8 @@ static ssize_t ftl_flush(FAR void *priv, FAR const uint8_t *buffer, nxfrd = MTD_BREAD(dev->mtd, rwblock, dev->blkper, dev->eblock); if (nxfrd != dev->blkper) { - ferr("ERROR: Read erase block %d failed: %d\n", rwblock, nxfrd); + ferr("ERROR: Read erase block %jd failed: %zd\n", + (intmax_t)rwblock, nxfrd); return -EIO; } @@ -292,7 +294,8 @@ static ssize_t ftl_flush(FAR void *priv, FAR const uint8_t *buffer, ret = MTD_ERASE(dev->mtd, eraseblock, 1); if (ret < 0) { - ferr("ERROR: Erase block=%d failed: %d\n", eraseblock, ret); + ferr("ERROR: Erase block=%jd failed: %d\n", + (intmax_t)eraseblock, ret); return ret; } @@ -309,8 +312,8 @@ static ssize_t ftl_flush(FAR void *priv, FAR const uint8_t *buffer, nbytes = dev->geo.erasesize - offset; } - finfo("Copy %d bytes into erase block=%d at offset=%d\n", - nbytes, eraseblock, offset); + finfo("Copy %d bytes into erase block=%jd at offset=%jd\n", + nbytes, (intmax_t)eraseblock, (intmax_t)offset); memcpy(dev->eblock + offset, buffer, nbytes); @@ -319,7 +322,8 @@ static ssize_t ftl_flush(FAR void *priv, FAR const uint8_t *buffer, nxfrd = MTD_BWRITE(dev->mtd, rwblock, dev->blkper, dev->eblock); if (nxfrd != dev->blkper) { - ferr("ERROR: Write erase block %d failed: %d\n", rwblock, nxfrd); + ferr("ERROR: Write erase block %jd failed: %zu\n", + (intmax_t)rwblock, nxfrd); return -EIO; } @@ -347,20 +351,21 @@ static ssize_t ftl_flush(FAR void *priv, FAR const uint8_t *buffer, ret = MTD_ERASE(dev->mtd, eraseblock, 1); if (ret < 0) { - ferr("ERROR: Erase block=%d failed: %d\n", eraseblock, ret); + ferr("ERROR: Erase block=%jd failed: %d\n", + (intmax_t)eraseblock, ret); return ret; } /* Write a full erase back to flash */ - finfo("Write %d bytes into erase block=%d at offset=0\n", - dev->geo.erasesize, alignedblock); + finfo("Write %" PRId32 " bytes into erase block=%jd at offset=0\n", + dev->geo.erasesize, (intmax_t)alignedblock); nxfrd = MTD_BWRITE(dev->mtd, alignedblock, dev->blkper, buffer); if (nxfrd != dev->blkper) { - ferr("ERROR: Write erase block %d failed: %d\n", - alignedblock, nxfrd); + ferr("ERROR: Write erase block %jd failed: %zu\n", + (intmax_t)alignedblock, nxfrd); return -EIO; } @@ -387,8 +392,8 @@ static ssize_t ftl_flush(FAR void *priv, FAR const uint8_t *buffer, nxfrd = MTD_BREAD(dev->mtd, alignedblock, dev->blkper, dev->eblock); if (nxfrd != dev->blkper) { - ferr("ERROR: Read erase block %d failed: %d\n", - alignedblock, nxfrd); + ferr("ERROR: Read erase block %jd failed: %zu\n", + (intmax_t)alignedblock, nxfrd); return -EIO; } @@ -398,15 +403,16 @@ static ssize_t ftl_flush(FAR void *priv, FAR const uint8_t *buffer, ret = MTD_ERASE(dev->mtd, eraseblock, 1); if (ret < 0) { - ferr("ERROR: Erase block=%d failed: %d\n", eraseblock, ret); + ferr("ERROR: Erase block=%jd failed: %d\n", + (intmax_t)eraseblock, ret); return ret; } /* Copy the user data at the beginning the buffered erase block */ nbytes = remaining * dev->geo.blocksize; - finfo("Copy %d bytes into erase block=%d at offset=0\n", - nbytes, alignedblock); + finfo("Copy %d bytes into erase block=%jd at offset=0\n", + nbytes, (intmax_t)alignedblock); memcpy(dev->eblock, buffer, nbytes); /* And write the erase back to flash */ @@ -414,8 +420,8 @@ static ssize_t ftl_flush(FAR void *priv, FAR const uint8_t *buffer, nxfrd = MTD_BWRITE(dev->mtd, alignedblock, dev->blkper, dev->eblock); if (nxfrd != dev->blkper) { - ferr("ERROR: Write erase block %d failed: %d\n", - alignedblock, nxfrd); + ferr("ERROR: Write erase block %jd failed: %zu\n", + (intmax_t)alignedblock, nxfrd); return -EIO; } } @@ -436,7 +442,7 @@ static ssize_t ftl_write(FAR struct inode *inode, { struct ftl_struct_s *dev; - finfo("sector: %d nsectors: %d\n", start_sector, nsectors); + finfo("sector: %zu nsectors: %d\n", start_sector, nsectors); DEBUGASSERT(inode && inode->i_private); dev = (struct ftl_struct_s *)inode->i_private; @@ -473,7 +479,7 @@ static int ftl_geometry(FAR struct inode *inode, finfo("available: true mediachanged: false writeenabled: %s\n", geometry->geo_writeenabled ? "true" : "false"); - finfo("nsectors: %d sectorsize: %d\n", + finfo("nsectors: %zu sectorsize: %zu\n", geometry->geo_nsectors, geometry->geo_sectorsize); return OK; diff --git a/drivers/mtd/mtd_partition.c b/drivers/mtd/mtd_partition.c index 359de88a063..32d59cfe2c5 100644 --- a/drivers/mtd/mtd_partition.c +++ b/drivers/mtd/mtd_partition.c @@ -80,6 +80,7 @@ struct mtd_partition_s struct mtd_dev_s child; /* The "child" MTD vtable that manages the * sub-region */ + /* Other implementation specific data may follow here */ FAR struct mtd_dev_s *parent; /* The "parent" MTD driver that manages the @@ -323,8 +324,8 @@ static ssize_t part_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, * ****************************************************************************/ -static ssize_t part_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, - FAR uint8_t *buffer) +static ssize_t part_read(FAR struct mtd_dev_s *dev, off_t offset, + size_t nbytes, FAR uint8_t *buffer) { FAR struct mtd_partition_s *priv = (FAR struct mtd_partition_s *)dev; off_t newoffset; @@ -361,8 +362,8 @@ static ssize_t part_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, ****************************************************************************/ #ifdef CONFIG_MTD_BYTE_WRITE -static ssize_t part_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, - FAR const uint8_t *buffer) +static ssize_t part_write(FAR struct mtd_dev_s *dev, off_t offset, + size_t nbytes, FAR const uint8_t *buffer) { FAR struct mtd_partition_s *priv = (FAR struct mtd_partition_s *)dev; off_t newoffset; @@ -373,7 +374,9 @@ static ssize_t part_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes if (priv->parent->write) { - /* Make sure that write would not extend past the end of the partition */ + /* Make sure that write would not extend past the end of the + * partition + */ if (!part_bytecheck(priv, offset + nbytes - 1)) { @@ -413,8 +416,8 @@ static int part_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg) FAR struct mtd_geometry_s *geo = (FAR struct mtd_geometry_s *)arg; if (geo) { - /* Populate the geometry structure with information needed to know - * the capacity and how to access the device. + /* Populate the geometry structure with information needed to + * know the capacity and how to access the device. */ geo->blocksize = priv->blocksize; @@ -442,7 +445,8 @@ static int part_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg) * return the sum to the caller. */ - *ppv = (FAR void *)(base + priv->firstblock * priv->blocksize); + *ppv = (FAR void *)(base + + priv->firstblock * priv->blocksize); } } } @@ -497,7 +501,8 @@ static int part_procfs_open(FAR struct file *filep, FAR const char *relpath, /* Allocate a container to hold the task and attribute selection */ - attr = (FAR struct part_procfs_file_s *)kmm_zalloc(sizeof(struct part_procfs_file_s)); + attr = (FAR struct part_procfs_file_s *) + kmm_zalloc(sizeof(struct part_procfs_file_s)); if (!attr) { ferr("ERROR: Failed to allocate file attributes\n"); @@ -571,7 +576,8 @@ static ssize_t part_procfs_read(FAR struct file *filep, FAR char *buffer, if (attr->nextpart == g_pfirstpartition) { #ifdef CONFIG_MTD_PARTITION_NAMES - total = snprintf(buffer, buflen, "%-*s Start Size MTD\n", PART_NAME_MAX, "Name"); + total = snprintf(buffer, buflen, "%-*s Start Size MTD\n", + PART_NAME_MAX, "Name"); #else total = snprintf(buffer, buflen, " Start Size MTD\n"); #endif @@ -591,8 +597,8 @@ static ssize_t part_procfs_read(FAR struct file *filep, FAR char *buffer, return 0; } - /* Get the number of blocks per erase. There must be an even number - * of blocks in one erase blocks. + /* Get the number of blocks per erase. There must be an even + * number of blocks in one erase blocks. */ blkpererase = geo.erasesize / geo.blocksize; @@ -623,13 +629,16 @@ static ssize_t part_procfs_read(FAR struct file *filep, FAR char *buffer, /* Terminate the partition name and add to output buffer */ - ret = snprintf(&buffer[total], buflen - total, "%s%7d %7d %s\n", - partname, attr->nextpart->firstblock / blkpererase, - attr->nextpart->neraseblocks, attr->nextpart->parent->name); + ret = snprintf(&buffer[total], buflen - total, "%s%7ju %ju %s\n", + partname, + (uintmax_t)attr->nextpart->firstblock / blkpererase, + (uintmax_t)attr->nextpart->neraseblocks, + attr->nextpart->parent->name); #else - ret = snprintf(&buffer[total], buflen - total, "%7d %7d %s\n", - attr->nextpart->firstblock / blkpererase, - attr->nextpart->neraseblocks, attr->nextpart->parent->name); + ret = snprintf(&buffer[total], buflen - total, "%7ju %7ju %s\n", + (uintmax_t)attr->nextpart->firstblock / blkpererase, + (uintmax_t)attr->nextpart->neraseblocks, + attr->nextpart->parent->name); #endif if (ret + total < buflen) @@ -672,7 +681,8 @@ static ssize_t part_procfs_read(FAR struct file *filep, FAR char *buffer, * ****************************************************************************/ -static int part_procfs_dup(FAR const struct file *oldp, FAR struct file *newp) +static int part_procfs_dup(FAR const struct file *oldp, + FAR struct file *newp) { FAR struct part_procfs_file_s *oldattr; FAR struct part_procfs_file_s *newattr; @@ -686,7 +696,8 @@ static int part_procfs_dup(FAR const struct file *oldp, FAR struct file *newp) /* Allocate a new container to hold the task and attribute selection */ - newattr = (FAR struct part_procfs_file_s *)kmm_zalloc(sizeof(struct part_procfs_file_s)); + newattr = (FAR struct part_procfs_file_s *) + kmm_zalloc(sizeof(struct part_procfs_file_s)); if (!newattr) { ferr("ERROR: Failed to allocate file attributes\n"); @@ -753,7 +764,8 @@ static int part_procfs_stat(const char *relpath, struct stat *buf) * ****************************************************************************/ -FAR struct mtd_dev_s *mtd_partition(FAR struct mtd_dev_s *mtd, off_t firstblock, +FAR struct mtd_dev_s *mtd_partition(FAR struct mtd_dev_s *mtd, + off_t firstblock, off_t nblocks) { FAR struct mtd_partition_s *part; @@ -808,7 +820,8 @@ FAR struct mtd_dev_s *mtd_partition(FAR struct mtd_dev_s *mtd, off_t firstblock, /* Allocate a partition device structure */ - part = (FAR struct mtd_partition_s *)kmm_zalloc(sizeof(struct mtd_partition_s)); + part = (FAR struct mtd_partition_s *) + kmm_zalloc(sizeof(struct mtd_partition_s)); if (!part) { ferr("ERROR: Failed to allocate memory for the partition device\n"); @@ -851,12 +864,14 @@ FAR struct mtd_dev_s *mtd_partition(FAR struct mtd_dev_s *mtd, off_t firstblock, struct mtd_partition_s *plast; /* Add the partition to the end of the list */ + part->pnext = NULL; plast = g_pfirstpartition; while (plast->pnext != NULL) { /* Get pointer to next partition */ + plast = plast->pnext; } diff --git a/drivers/mtd/mtd_progmem.c b/drivers/mtd/mtd_progmem.c index a35f7fbbbac..8308a7fe0f4 100644 --- a/drivers/mtd/mtd_progmem.c +++ b/drivers/mtd/mtd_progmem.c @@ -131,7 +131,7 @@ static struct progmem_dev_s g_progmem = * ****************************************************************************/ -static int32_t progmem_log2(uint32_t blocksize) +static int32_t progmem_log2(size_t blocksize) { uint32_t log2 = 0; @@ -280,8 +280,9 @@ static ssize_t progmem_write(FAR struct mtd_dev_s *dev, off_t offset, off_t startblock; ssize_t result; - /* Write the specified blocks from the provided user buffer and return status - * (The positive, number of blocks actually written or a negated errno) + /* Write the specified blocks from the provided user buffer and return + * status (The positive number of blocks actually written or a negated + * errno). */ startblock = offset >> priv->blkshift; @@ -295,7 +296,8 @@ static ssize_t progmem_write(FAR struct mtd_dev_s *dev, off_t offset, * Name: progmem_ioctl ****************************************************************************/ -static int progmem_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg) +static int progmem_ioctl(FAR struct mtd_dev_s *dev, int cmd, + unsigned long arg) { FAR struct progmem_dev_s *priv = (FAR struct progmem_dev_s *)dev; int ret = -EINVAL; /* Assume good command with bad parameters */ @@ -307,13 +309,13 @@ static int progmem_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg) FAR struct mtd_geometry_s *geo = (FAR struct mtd_geometry_s *)arg; if (geo) { - /* Populate the geometry structure with information needed to know - * the capacity and how to access the device. + /* Populate the geometry structure with information needed to + * know the capacity and how to access the device. * - * NOTE: that the device is treated as though it where just an array - * of fixed size blocks. That is most likely not true, but the client - * will expect the device logic to do whatever is necessary to make it - * appear so. + * NOTE: that the device is treated as though it where just an + * array of fixed size blocks. That is most likely not true, + * but the client will expect the device logic to do whatever + * is necessary to make it appear so. */ geo->blocksize = (1 << priv->blkshift); /* Size of one read/write block */ diff --git a/drivers/mtd/mtd_rwbuffer.c b/drivers/mtd/mtd_rwbuffer.c index 14971313007..4c4169751df 100644 --- a/drivers/mtd/mtd_rwbuffer.c +++ b/drivers/mtd/mtd_rwbuffer.c @@ -43,6 +43,7 @@ #include +#include #include #include #include @@ -174,8 +175,8 @@ static int mtd_erase(FAR struct mtd_dev_s *dev, off_t block, size_t nblocks) size_t nsectors; int ret; - finfo("block: %08lx nsectors: %lu\n", - (unsigned long)block, (unsigned int)nsectors); + finfo("block: %08zx nsectors: %zu\n", + (intmax_t)block, nsectors); /* Convert to logical sectors and sector numbers */ @@ -259,7 +260,8 @@ static int mtd_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg) { case MTDIOC_GEOMETRY: { - FAR struct mtd_geometry_s *geo = (FAR struct mtd_geometry_s *)((uintptr_t)arg); + FAR struct mtd_geometry_s *geo = (FAR struct mtd_geometry_s *) + ((uintptr_t)arg); if (geo) { /* Populate the geometry structure with information need to know @@ -384,6 +386,7 @@ FAR struct mtd_dev_s *mtd_rwb_initialize(FAR struct mtd_dev_s *mtd) DEBUGASSERT((size_t)priv->spb * geo.blocksize == geo.erasesize); /* Values must be provided to rwb_initialize() */ + /* Supported geometry */ priv->rwb.blocksize = geo.blocksize; diff --git a/drivers/mtd/smart.c b/drivers/mtd/smart.c index bc2d8632e57..bd1ebaccfa9 100644 --- a/drivers/mtd/smart.c +++ b/drivers/mtd/smart.c @@ -45,6 +45,7 @@ #include #include #include +#include #include #include #include @@ -875,8 +876,8 @@ static ssize_t smart_reload(struct smart_struct_s *dev, FAR uint8_t *buffer, nread = MTD_BREAD(dev->mtd, mtdstartblock, mtdblocks, buffer); if (nread != mtdblocks) { - ferr("ERROR: Read %d blocks starting at block %d failed: %d\n", - nblocks, startblock, nread); + ferr("ERROR: Read %zd blocks starting at block %jd failed: %zd\n", + nblocks, (intmax_t)startblock, nread); } return nread; @@ -955,7 +956,8 @@ static ssize_t smart_write(FAR struct inode *inode, mtdblockcount = nsectors * dev->mtdblkspersector; mtdblkspererase = dev->mtdblkspersector * dev->sectorsperblk; - finfo("mtdsector: %d mtdnsectors: %d\n", mtdstartblock, mtdblockcount); + finfo("mtdsector: %jd mtdnsectors: %jd\n", + (intmax_t)mtdstartblock, (intmax_t)mtdblockcount); /* Start at first block to be written */ @@ -977,7 +979,8 @@ static ssize_t smart_write(FAR struct inode *inode, ret = MTD_ERASE(dev->mtd, eraseblock, 1); if (ret < 0) { - ferr("ERROR: Erase block=%d failed: %d\n", eraseblock, ret); + ferr("ERROR: Erase block=%jd failed: %d\n", + (intmax_t)eraseblock, ret); /* Unlock the mutex if we add one */ @@ -1000,13 +1003,15 @@ static ssize_t smart_write(FAR struct inode *inode, /* Try to write to the sector. */ - finfo("Write MTD block %d from offset %d\n", nextblock, offset); + finfo("Write MTD block %jd from offset %jd\n", + (intmax_t)nextblock, (intmax_t)offset); nxfrd = MTD_BWRITE(dev->mtd, nextblock, blkstowrite, &buffer[offset]); if (nxfrd != blkstowrite) { /* The block is not empty!! What to do? */ - ferr("ERROR: Write block %d failed: %d.\n", nextblock, nxfrd); + ferr("ERROR: Write block %jd failed: %zd.\n", + (intmax_t)nextblock, nxfrd); /* Unlock the mutex if we add one */ @@ -1114,7 +1119,9 @@ static int smart_setsectorsize(FAR struct smart_struct_s *dev, uint16_t size) } else { - /* Set the sectors per erase block and available sectors per erase block */ + /* Set the sectors per erase block and available sectors per erase + * block + */ dev->sectorsperblk = erasesize / dev->sectorsize; if (dev->sectorsperblk == 256) @@ -1181,7 +1188,7 @@ static int smart_setsectorsize(FAR struct smart_struct_s *dev, uint16_t size) if (totalsectors > 65536) { - ferr("ERROR: Invalid SMART sector count %ld\n", totalsectors); + ferr("ERROR: Invalid SMART sector count %" PRIu32 "\n", totalsectors); return -EINVAL; } else if (totalsectors == 65536) @@ -1473,7 +1480,9 @@ static int smart_add_sector_to_cache(FAR struct smart_struct_s *dev, } else { - /* Cache is full. We must find the least accessed entry and replace it */ + /* Cache is full. We must find the least accessed entry and replace + * it + */ oldest = 0xffff; for (x = 0; x < CONFIG_MTD_SMART_SECTOR_CACHE_SIZE; x++) @@ -1642,7 +1651,9 @@ static uint16_t smart_cache_lookup(FAR struct smart_struct_s *dev, if (logicalsector == logical) { - /* This is the sector we are looking for! Add it to the cache */ + /* This is the sector we are looking for! Add it to the + * cache + */ physical = block * dev->sectorsperblk + sector; smart_add_sector_to_cache(dev, logical, physical, @@ -2318,7 +2329,9 @@ static int smart_scan(FAR struct smart_struct_s *dev) continue; } - /* Now compare if this logical sector matches the current sector */ + /* Now compare if this logical sector matches the current + * sector + */ if (duplogsector == logicalsector) { @@ -2948,7 +2961,9 @@ static int smart_relocate_static_data(FAR struct smart_struct_s *dev, continue; } - /* Find a new sector where it can live, NOT in this erase block */ + /* Find a new sector where it can live, NOT in this erase + * block + */ newsector = nextsector++; @@ -3117,11 +3132,11 @@ static inline int smart_llformat(FAR struct smart_struct_s *dev, ferr("ERROR: Invalid geometery ... " "Sectors per erase block must be 1-256\n"); - ferr(" Erase block size = %d\n", + ferr(" Erase block size = %" PRId32 "\n", dev->erasesize); ferr(" Sector size = %d\n", dev->sectorsize); - ferr(" Sectors/erase block = %d\n", + ferr(" Sectors/erase block = %" PRId32 "\n", dev->erasesize / dev->sectorsize); return -EINVAL; @@ -5286,7 +5301,9 @@ static inline int smart_allocsector(FAR struct smart_struct_s *dev, #else /* CONFIG_MTD_SMART_ENABLE_CRC */ - /* Write the logical sector to the flash. We will fill it in with data later. */ + /* Write the logical sector to the flash. We will fill it in with data + * later. + */ ret = smart_write_alloc_sector(dev, logsector, physicalsector); if (ret != 1) @@ -5351,7 +5368,7 @@ static inline int smart_freesector(FAR struct smart_struct_s *dev, (1 << (logicalsector & 0x07)))) #endif { - ferr("ERROR: Invalid release - sector %d not allocated\n", + ferr("ERROR: Invalid release - sector %ld not allocated\n", logicalsector); ret = -EINVAL; goto errout; @@ -5381,7 +5398,7 @@ static inline int smart_freesector(FAR struct smart_struct_s *dev, * code? */ - ferr("ERROR: Sector %d logical sector in header doesn't match\n", + ferr("ERROR: Sector %ld logical sector in header doesn't match\n", logicalsector); ret = -EINVAL; goto errout; @@ -5478,7 +5495,9 @@ static int smart_ioctl(FAR struct inode *inode, int cmd, unsigned long arg) } #endif - /* Just change the BIOC_XIPBASE command to the MTDIOC_XIPBASE command. */ + /* Just change the BIOC_XIPBASE command to the MTDIOC_XIPBASE + * command. + */ cmd = MTDIOC_XIPBASE; break; diff --git a/drivers/mtd/sst25xx.c b/drivers/mtd/sst25xx.c index 68cd6ed0fb6..95ee4c70e72 100644 --- a/drivers/mtd/sst25xx.c +++ b/drivers/mtd/sst25xx.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * drivers/mtd/sst25xx.c * Driver for SPI-based SST25VF parts 64MBit and larger. * @@ -39,15 +39,16 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include +#include #include #include #include @@ -61,14 +62,16 @@ #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ -/* Per the data sheet, SST25 parts can be driven with either SPI mode 0 (CPOL=0 and - * CPHA=0) or mode 3 (CPOL=1 and CPHA=1). So you may need to specify - * CONFIG_SST25XX_SPIMODE to select the best mode for your device. If - * CONFIG_SST25XX_SPIMODE is not defined, mode 0 will be used. + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Per the data sheet, SST25 parts can be driven with either SPI mode 0 + * (CPOL=0 and CPHA=0) or mode 3 (CPOL=1 and CPHA=1). So you may need to + * specify CONFIG_SST25XX_SPIMODE to select the best mode for your device. + * If CONFIG_SST25XX_SPIMODE is not defined, mode 0 will be used. */ #ifndef CONFIG_SST25XX_SPIMODE @@ -81,8 +84,8 @@ # define CONFIG_SST25XX_SPIFREQUENCY 20000000 #endif -/* Various manufacturers may have produced the parts. 0xBF is the manufacturer ID - * for the SST serial FLASH. +/* Various manufacturers may have produced the parts. 0xBF is the + * manufacturer ID for the SST serial FLASH. */ #ifndef CONFIG_SST25XX_MANUFACTURER @@ -93,7 +96,8 @@ # define CONFIG_SST25XX_MEMORY_TYPE 0x25 #endif -/* SST25 Registers *******************************************************************/ +/* SST25 Registers **********************************************************/ + /* Identification register values */ #define SST25_MANUFACTURER CONFIG_SST25XX_MANUFACTURER @@ -112,7 +116,10 @@ #define SST25_SST25064_NPAGES 32768 /* Instructions */ -/* Command Value N Description Addr Dummy Data */ + +/* Command Value N Description Addr Dummy Data + */ + #define SST25_WREN 0x06 /* 1 Write Enable 0 0 0 */ #define SST25_WRDI 0x04 /* 1 Write Disable 0 0 0 */ #define SST25_RDID 0x9f /* 1 Read Identification 0 0 1-3 */ @@ -149,14 +156,14 @@ # define SST25_SR_BP_UPPERQTR (6 << SST25_SR_BP_SHIFT) /* Upper quarter */ # define SST25_SR_BP_UPPERHALF (7 << SST25_SR_BP_SHIFT) /* Upper half */ # define SST25_SR_BP_ALL (8 << SST25_SR_BP_SHIFT) /* All sectors */ -#define SST_SR_SEC (1 << 6) /* Security ID status */ -#define SST25_SR_SRWD (1 << 7) /* Bit 7: Status register write protect */ +#define SST_SR_SEC (1 << 6) /* Security ID status */ +#define SST25_SR_SRWD (1 << 7) /* Bit 7: Status register write protect */ #define SST25_DUMMY 0xa5 -/************************************************************************************ +/**************************************************************************** * Private Types - ************************************************************************************/ + ****************************************************************************/ /* This type represents the state of the MTD device. The struct mtd_dev_s * must appear at the beginning of the definition so that you can freely @@ -174,9 +181,9 @@ struct sst25xx_dev_s uint8_t lastwaswrite; /* Indicates if last operation was write */ }; -/************************************************************************************ +/**************************************************************************** * Private Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /* Helpers */ @@ -185,37 +192,43 @@ static inline void sst25xx_unlock(FAR struct spi_dev_s *dev); static inline int sst25xx_readid(struct sst25xx_dev_s *priv); static void sst25xx_waitwritecomplete(struct sst25xx_dev_s *priv); static void sst25xx_writeenable(struct sst25xx_dev_s *priv); -static inline void sst25xx_sectorerase(struct sst25xx_dev_s *priv, off_t offset, uint8_t type); +static inline void sst25xx_sectorerase(struct sst25xx_dev_s *priv, + off_t offset, uint8_t type); static inline int sst25xx_bulkerase(struct sst25xx_dev_s *priv); -static inline void sst25xx_pagewrite(struct sst25xx_dev_s *priv, FAR const uint8_t *buffer, - off_t offset); +static inline void sst25xx_pagewrite(struct sst25xx_dev_s *priv, + FAR const uint8_t *buffer, + off_t offset); /* MTD driver methods */ -static int sst25xx_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks); +static int sst25xx_erase(FAR struct mtd_dev_s *dev, off_t startblock, + size_t nblocks); static ssize_t sst25xx_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks, FAR uint8_t *buf); static ssize_t sst25xx_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks, FAR const uint8_t *buf); -static ssize_t sst25xx_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, - FAR uint8_t *buffer); +static ssize_t sst25xx_read(FAR struct mtd_dev_s *dev, off_t offset, + size_t nbytes, + FAR uint8_t *buffer); #ifdef CONFIG_MTD_BYTE_WRITE -static ssize_t sst25xx_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, - FAR const uint8_t *buffer); +static ssize_t sst25xx_write(FAR struct mtd_dev_s *dev, off_t offset, + size_t nbytes, + FAR const uint8_t *buffer); #endif -static int sst25xx_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg); +static int sst25xx_ioctl(FAR struct mtd_dev_s *dev, int cmd, + unsigned long arg); -/************************************************************************************ +/**************************************************************************** * Private Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sst25xx_lock - ************************************************************************************/ + ****************************************************************************/ static void sst25xx_lock(FAR struct spi_dev_s *dev) { @@ -223,16 +236,18 @@ static void sst25xx_lock(FAR struct spi_dev_s *dev) * lock SPI to have exclusive access to the buses for a sequence of * transfers. The bus should be locked before the chip is selected. * - * This is a blocking call and will not return until we have exclusive access to - * the SPI bus. We will retain that exclusive access until the bus is unlocked. + * This is a blocking call and will not return until we have exclusive + * access to the SPI bus. We will retain that exclusive access until + * the bus is unlocked. */ SPI_LOCK(dev, true); - /* After locking the SPI bus, the we also need call the setfrequency, setbits, and - * setmode methods to make sure that the SPI is properly configured for the device. - * If the SPI bus is being shared, then it may have been left in an incompatible - * state. + /* After locking the SPI bus, the we also need call the setfrequency, + * setbits, and setmode methods to make sure that the SPI is properly + * configured for the device. + * If the SPI bus is being shared, then it may have been left in an + * incompatible state. */ SPI_SETMODE(dev, CONFIG_SST25XX_SPIMODE); @@ -241,18 +256,18 @@ static void sst25xx_lock(FAR struct spi_dev_s *dev) SPI_SETFREQUENCY(dev, CONFIG_SST25XX_SPIFREQUENCY); } -/************************************************************************************ +/**************************************************************************** * Name: sst25xx_unlock - ************************************************************************************/ + ****************************************************************************/ static inline void sst25xx_unlock(FAR struct spi_dev_s *dev) { SPI_LOCK(dev, false); } -/************************************************************************************ +/**************************************************************************** * Name: sst25xx_readid - ************************************************************************************/ + ****************************************************************************/ static inline int sst25xx_readid(struct sst25xx_dev_s *priv) { @@ -291,22 +306,22 @@ static inline int sst25xx_readid(struct sst25xx_dev_s *priv) if (capacity == SST25_SST25064_CAPACITY) { - /* Save the FLASH geometry */ + /* Save the FLASH geometry */ - priv->sectorshift = SST25_SST25064_SECTOR_SHIFT; - priv->nsectors = SST25_SST25064_NSECTORS; - priv->pageshift = SST25_SST25064_PAGE_SHIFT; - priv->npages = SST25_SST25064_NPAGES; - return OK; + priv->sectorshift = SST25_SST25064_SECTOR_SHIFT; + priv->nsectors = SST25_SST25064_NSECTORS; + priv->pageshift = SST25_SST25064_PAGE_SHIFT; + priv->npages = SST25_SST25064_NPAGES; + return OK; } } return -ENODEV; } -/************************************************************************************ +/**************************************************************************** * Name: sst25xx_waitwritecomplete - ************************************************************************************/ + ****************************************************************************/ static void sst25xx_waitwritecomplete(struct sst25xx_dev_s *priv) { @@ -333,7 +348,9 @@ static void sst25xx_waitwritecomplete(struct sst25xx_dev_s *priv) SPI_SEND(priv->dev, SST25_RDSR); - /* Send a dummy byte to generate the clock needed to shift out the status */ + /* Send a dummy byte to generate the clock needed to shift out the + * status + */ status = SPI_SEND(priv->dev, SST25_DUMMY); @@ -341,9 +358,9 @@ static void sst25xx_waitwritecomplete(struct sst25xx_dev_s *priv) SPI_SELECT(priv->dev, SPIDEV_FLASH(0), false); - /* Given that writing could take up to few tens of milliseconds, and erasing - * could take more. The following short delay in the "busy" case will allow - * other peripherals to access the SPI bus. + /* Given that writing could take up to few tens of milliseconds, and + * erasing could take more. The following short delay in the "busy" + * case will allow other peripherals to access the SPI bus. */ if ((status & SST25_SR_WIP) != 0) @@ -360,9 +377,9 @@ static void sst25xx_waitwritecomplete(struct sst25xx_dev_s *priv) finfo("Complete\n"); } -/************************************************************************************ +/**************************************************************************** * Name: sst25xx_writeenable - ************************************************************************************/ + ****************************************************************************/ static void sst25xx_writeenable(struct sst25xx_dev_s *priv) { @@ -380,9 +397,9 @@ static void sst25xx_writeenable(struct sst25xx_dev_s *priv) finfo("Enabled\n"); } -/************************************************************************************ +/**************************************************************************** * Name: sst25xx_unprotect - ************************************************************************************/ + ****************************************************************************/ static void sst25xx_unprotect(struct sst25xx_dev_s *priv) { @@ -407,11 +424,12 @@ static void sst25xx_unprotect(struct sst25xx_dev_s *priv) SPI_SELECT(priv->dev, SPIDEV_FLASH(0), false); } -/************************************************************************************ +/**************************************************************************** * Name: sst25xx_sectorerase - ************************************************************************************/ + ****************************************************************************/ -static void sst25xx_sectorerase(struct sst25xx_dev_s *priv, off_t sector, uint8_t type) +static void sst25xx_sectorerase(struct sst25xx_dev_s *priv, off_t sector, + uint8_t type) { off_t offset; @@ -457,9 +475,9 @@ static void sst25xx_sectorerase(struct sst25xx_dev_s *priv, off_t sector, uint8_ finfo("Erased\n"); } -/************************************************************************************ +/**************************************************************************** * Name: sst25xx_bulkerase - ************************************************************************************/ + ****************************************************************************/ static inline int sst25xx_bulkerase(struct sst25xx_dev_s *priv) { @@ -494,12 +512,13 @@ static inline int sst25xx_bulkerase(struct sst25xx_dev_s *priv) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: sst25xx_pagewrite - ************************************************************************************/ + ****************************************************************************/ -static inline void sst25xx_pagewrite(struct sst25xx_dev_s *priv, FAR const uint8_t *buffer, - off_t page) +static inline void sst25xx_pagewrite(struct sst25xx_dev_s *priv, + FAR const uint8_t *buffer, + off_t page) { off_t offset = page << priv->pageshift; @@ -542,9 +561,9 @@ static inline void sst25xx_pagewrite(struct sst25xx_dev_s *priv, FAR const uint8 finfo("Written\n"); } -/************************************************************************************ +/**************************************************************************** * Name: sst25xx_bytewrite - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_MTD_BYTE_WRITE static inline void sst25xx_bytewrite(struct sst25xx_dev_s *priv, @@ -591,11 +610,12 @@ static inline void sst25xx_bytewrite(struct sst25xx_dev_s *priv, } #endif -/************************************************************************************ +/**************************************************************************** * Name: sst25xx_erase - ************************************************************************************/ + ****************************************************************************/ -static int sst25xx_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks) +static int sst25xx_erase(FAR struct mtd_dev_s *dev, off_t startblock, + size_t nblocks) { FAR struct sst25xx_dev_s *priv = (FAR struct sst25xx_dev_s *)dev; size_t blocksleft = nblocks; @@ -667,11 +687,12 @@ static int sst25xx_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nbl return (int)nblocks; } -/************************************************************************************ +/**************************************************************************** * Name: sst25xx_bread - ************************************************************************************/ + ****************************************************************************/ -static ssize_t sst25xx_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks, +static ssize_t sst25xx_bread(FAR struct mtd_dev_s *dev, off_t startblock, + size_t nblocks, FAR uint8_t *buffer) { FAR struct sst25xx_dev_s *priv = (FAR struct sst25xx_dev_s *)dev; @@ -679,23 +700,26 @@ static ssize_t sst25xx_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks); - /* On this device, we can handle the block read just like the byte-oriented read */ + /* On this device, we can handle the block read just like the + * byte-oriented read + */ nbytes = sst25xx_read(dev, startblock << priv->pageshift, nblocks << priv->pageshift, buffer); if (nbytes > 0) { - return nbytes >> priv->pageshift; + return nbytes >> priv->pageshift; } return (int)nbytes; } -/************************************************************************************ +/**************************************************************************** * Name: sst25xx_bwrite - ************************************************************************************/ + ****************************************************************************/ -static ssize_t sst25xx_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks, +static ssize_t sst25xx_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, + size_t nblocks, FAR const uint8_t *buffer) { FAR struct sst25xx_dev_s *priv = (FAR struct sst25xx_dev_s *)dev; @@ -712,17 +736,18 @@ static ssize_t sst25xx_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_ sst25xx_pagewrite(priv, buffer, startblock); buffer += pagesize; startblock++; - } + } sst25xx_unlock(priv->dev); return nblocks; } -/************************************************************************************ +/**************************************************************************** * Name: sst25xx_read - ************************************************************************************/ + ****************************************************************************/ -static ssize_t sst25xx_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, +static ssize_t sst25xx_read(FAR struct mtd_dev_s *dev, off_t offset, + size_t nbytes, FAR uint8_t *buffer) { FAR struct sst25xx_dev_s *priv = (FAR struct sst25xx_dev_s *)dev; @@ -772,13 +797,14 @@ static ssize_t sst25xx_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbyt return nbytes; } -/************************************************************************************ +/**************************************************************************** * Name: sst25xx_write - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_MTD_BYTE_WRITE -static ssize_t sst25xx_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, - FAR const uint8_t *buffer) +static ssize_t sst25xx_write(FAR struct mtd_dev_s *dev, off_t offset, + size_t nbytes, + FAR const uint8_t *buffer) { FAR struct sst25xx_dev_s *priv = (FAR struct sst25xx_dev_s *)dev; int startpage; @@ -811,7 +837,7 @@ static ssize_t sst25xx_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nby count = nbytes; pagesize = (1 << priv->pageshift); - bytestowrite = pagesize - (offset & (pagesize-1)); + bytestowrite = pagesize - (offset & (pagesize - 1)); sst25xx_bytewrite(priv, buffer, offset, bytestowrite); /* Update offset and count */ @@ -848,11 +874,12 @@ static ssize_t sst25xx_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nby } #endif /* CONFIG_MTD_BYTE_WRITE */ -/************************************************************************************ +/**************************************************************************** * Name: sst25xx_ioctl - ************************************************************************************/ + ****************************************************************************/ -static int sst25xx_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg) +static int sst25xx_ioctl(FAR struct mtd_dev_s *dev, int cmd, + unsigned long arg) { FAR struct sst25xx_dev_s *priv = (FAR struct sst25xx_dev_s *)dev; int ret = -EINVAL; /* Assume good command with bad parameters */ @@ -863,16 +890,17 @@ static int sst25xx_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg) { case MTDIOC_GEOMETRY: { - FAR struct mtd_geometry_s *geo = (FAR struct mtd_geometry_s *)((uintptr_t)arg); + FAR struct mtd_geometry_s *geo = (FAR struct mtd_geometry_s *) + ((uintptr_t)arg); if (geo) { - /* Populate the geometry structure with information need to know - * the capacity and how to access the device. + /* Populate the geometry structure with information need to + * know the capacity and how to access the device. * - * NOTE: that the device is treated as though it where just an array - * of fixed size blocks. That is most likely not true, but the client - * will expect the device logic to do whatever is necessary to make it - * appear so. + * NOTE: that the device is treated as though it where just + * an array of fixed size blocks. That is most likely not + * true, but the client will expect the device logic to do + * whatever is necessary to make it appear so. */ geo->blocksize = (1 << priv->pageshift); @@ -881,7 +909,8 @@ static int sst25xx_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg) ret = OK; - finfo("blocksize: %d erasesize: %d neraseblocks: %d\n", + finfo("blocksize: %" PRId32 " erasesize: %" PRId32 + " neraseblocks: %" PRId32 "\n", geo->blocksize, geo->erasesize, geo->neraseblocks); } } @@ -907,19 +936,20 @@ static int sst25xx_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg) return ret; } -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sst25xx_initialize * * Description: - * Create an initialize MTD device instance. MTD devices are not registered - * in the file system, but are created as instances that can be bound to - * other functions (such as a block or character driver front end). + * Create an initialize MTD device instance. MTD devices are not + * registered in the file system, but are created as instances that can + * be bound to other functions (such as a block or character driver front + * end). * - ************************************************************************************/ + ****************************************************************************/ FAR struct mtd_dev_s *sst25xx_initialize(FAR struct spi_dev_s *dev) { @@ -931,11 +961,12 @@ FAR struct mtd_dev_s *sst25xx_initialize(FAR struct spi_dev_s *dev) /* Allocate a state structure (we allocate the structure instead of using * a fixed, static allocation so that we can handle multiple FLASH devices. * The current implementation would handle only one FLASH part per SPI - * device (only because of the SPIDEV_FLASH(0) definition) and so would have - * to be extended to handle multiple FLASH parts on the same SPI bus. + * device (only because of the SPIDEV_FLASH(0) definition) and so would + * have to be extended to handle multiple FLASH parts on the same SPI bus. */ - priv = (FAR struct sst25xx_dev_s *)kmm_zalloc(sizeof(struct sst25xx_dev_s)); + priv = (FAR struct sst25xx_dev_s *) + kmm_zalloc(sizeof(struct sst25xx_dev_s)); if (priv) { /* Initialize the allocated structure. (unsupported methods were @@ -963,7 +994,9 @@ FAR struct mtd_dev_s *sst25xx_initialize(FAR struct spi_dev_s *dev) ret = sst25xx_readid(priv); if (ret != OK) { - /* Unrecognized! Discard all of that work we just did and return NULL */ + /* Unrecognized! Discard all of that work we just did and return + * NULL + */ ferr("ERROR: Unrecognized\n"); kmm_free(priv); @@ -971,7 +1004,9 @@ FAR struct mtd_dev_s *sst25xx_initialize(FAR struct spi_dev_s *dev) } else { - /* Make sure that the FLASH is unprotected so that we can write into it */ + /* Make sure that the FLASH is unprotected so that we can write + * into it + */ sst25xx_unprotect(priv); } diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 49c73b7b603..cbc809ba768 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -389,6 +389,9 @@ config ETH0_PHY_KSZ90x1 config ETH0_PHY_DP83848C bool "National Semiconductor DP83848C PHY" +config ETH0_PHY_DP83825I + bool "Texas Instruments DP83825I PHY" + config ETH0_PHY_TJA1100 bool "NXP TJA1100 PHY" select ARCH_PHY_100BASE_T1 @@ -445,6 +448,9 @@ config ETH1_PHY_KSZ90x1 config ETH1_PHY_DP83848C bool "National Semiconductor DP83848C PHY" +config ETH1_PHY_DP83825I + bool "Texas Instruments DP83825I PHY" + config ETH1_PHY_TJA1100 bool "NXP TJA1100 PHY" select ARCH_PHY_100BASE_T1 diff --git a/drivers/net/loopback.c b/drivers/net/loopback.c index f7e4b55d2d5..569e9d6637f 100644 --- a/drivers/net/loopback.c +++ b/drivers/net/loopback.c @@ -304,8 +304,8 @@ static int lo_ifup(FAR struct net_driver_s *dev) #ifdef CONFIG_NET_IPv4 ninfo("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + (int)(dev->d_ipaddr & 0xff), (int)((dev->d_ipaddr >> 8) & 0xff), + (int)((dev->d_ipaddr >> 16) & 0xff), (int)(dev->d_ipaddr >> 24)); #endif #ifdef CONFIG_NET_IPv6 ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", diff --git a/drivers/net/telnet.c b/drivers/net/telnet.c index fb7cea5b57a..241ef778f6d 100644 --- a/drivers/net/telnet.c +++ b/drivers/net/telnet.c @@ -359,7 +359,7 @@ static ssize_t telnet_receive(FAR struct telnet_dev_s *priv, int nread; uint8_t ch; - ninfo("srclen: %d destlen: %d\n", srclen, destlen); + ninfo("srclen: %zd destlen: %zd\n", srclen, destlen); for (nread = 0; srclen > 0 && nread < destlen; srclen--) { @@ -809,7 +809,7 @@ static ssize_t telnet_read(FAR struct file *filep, FAR char *buffer, ssize_t nread = 0; int ret; - ninfo("len: %d\n", len); + ninfo("len: %zd\n", len); /* First, handle the case where there are still valid bytes left in the * I/O buffer from the last time that read was called. NOTE: Much of @@ -892,7 +892,7 @@ static ssize_t telnet_write(FAR struct file *filep, FAR const char *buffer, char ch; bool eol; - ninfo("len: %d\n", len); + ninfo("len: %zd\n", len); /* Process each character from the user buffer */ @@ -917,7 +917,7 @@ static ssize_t telnet_write(FAR struct file *filep, FAR const char *buffer, ret = psock_send(&priv->td_psock, priv->td_txbuffer, ncopied, 0); if (ret < 0) { - nerr("ERROR: psock_send failed '%s': %d\n", + nerr("ERROR: psock_send failed '%s': %zd\n", priv->td_txbuffer, ret); return ret; } @@ -935,7 +935,7 @@ static ssize_t telnet_write(FAR struct file *filep, FAR const char *buffer, ret = psock_send(&priv->td_psock, priv->td_txbuffer, ncopied, 0); if (ret < 0) { - nerr("ERROR: psock_send failed '%s': %d\n", + nerr("ERROR: psock_send failed '%s': %zd\n", priv->td_txbuffer, ret); return ret; } diff --git a/drivers/ramdisk.c b/drivers/ramdisk.c index 4ca5ad620ea..5dccdbe1121 100644 --- a/drivers/ramdisk.c +++ b/drivers/ramdisk.c @@ -26,6 +26,7 @@ #include #include +#include #include #include #include @@ -231,7 +232,7 @@ static ssize_t rd_read(FAR struct inode *inode, unsigned char *buffer, DEBUGASSERT(inode && inode->i_private); dev = (FAR struct rd_struct_s *)inode->i_private; - finfo("sector: %d nsectors: %d sectorsize: %d\n", + finfo("sector: %zd nsectors: %d sectorsize: %d\n", start_sector, dev->rd_sectsize, nsectors); if (start_sector < dev->rd_nsectors && @@ -265,7 +266,7 @@ static ssize_t rd_write(FAR struct inode *inode, const unsigned char *buffer, DEBUGASSERT(inode && inode->i_private); dev = (struct rd_struct_s *)inode->i_private; - finfo("sector: %d nsectors: %d sectorsize: %d\n", + finfo("sector: %zd nsectors: %d sectorsize: %d\n", start_sector, dev->rd_sectsize, nsectors); if (!RDFLAG_IS_WRENABLED(dev->rd_flags)) @@ -313,7 +314,7 @@ static int rd_geometry(FAR struct inode *inode, struct geometry *geometry) finfo("available: true mediachanged: false writeenabled: %s\n", geometry->geo_writeenabled ? "true" : "false"); - finfo("nsectors: %d sectorsize: %d\n", + finfo("nsectors: %zd sectorsize: %zd\n", geometry->geo_nsectors, geometry->geo_sectorsize); return OK; @@ -414,7 +415,7 @@ int ramdisk_register(int minor, FAR uint8_t *buffer, uint32_t nsectors, char devname[16]; int ret = -ENOMEM; - finfo("buffer: %p nsectors: %d sectsize: %d\n", + finfo("buffer: %p nsectors: %" PRIu32 " sectsize: %" PRIu16 "\n", buffer, nsectors, sectsize); /* Sanity check */ diff --git a/drivers/rc/dummy.c b/drivers/rc/dummy.c index 074deba3533..48ad445574c 100644 --- a/drivers/rc/dummy.c +++ b/drivers/rc/dummy.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -184,7 +185,8 @@ static int dummy_tx_ir(FAR struct lirc_lowerhalf_s *lower, static int dummy_tx_scancode(FAR struct lirc_lowerhalf_s *lower, FAR struct lirc_scancode *txbuf) { - rcinfo("Dummy RC send scancode data:%u to device\n", txbuf->scancode); + rcinfo("Dummy RC send scancode data:%" PRIu64 " to device\n", + txbuf->scancode); return 0; } diff --git a/drivers/rwbuffer.c b/drivers/rwbuffer.c index 106592ab9b4..3fa71d54b7f 100644 --- a/drivers/rwbuffer.c +++ b/drivers/rwbuffer.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include @@ -535,7 +536,8 @@ int rwb_invalidate_writebuffer(FAR struct rwbuffer_s *rwb, off_t wrbend; off_t invend; - finfo("startblock=%d blockcount=%p\n", startblock, blockcount); + finfo("startblock=%jd blockcount=%zu\n", + (intmax_t)startblock, blockcount); ret = rwb_semtake(&rwb->wrsem); if (ret < 0) @@ -676,7 +678,8 @@ int rwb_invalidate_readahead(FAR struct rwbuffer_s *rwb, off_t rhbend; off_t invend; - finfo("startblock=%d blockcount=%p\n", startblock, blockcount); + finfo("startblock=%jd blockcount=%zu\n", + (intmax_t)startblock, blockcount); ret = rwb_semtake(&rwb->rhsem); if (ret < 0) diff --git a/drivers/sensors/sensor.c b/drivers/sensors/sensor.c index b12d7674780..8145b31041a 100644 --- a/drivers/sensors/sensor.c +++ b/drivers/sensors/sensor.c @@ -99,7 +99,7 @@ static int sensor_poll(FAR struct file *filep, FAR struct pollfd *fds, static const struct sensor_info g_sensor_info[] = { - {1, "custom"}, + {0, NULL}, {sizeof(struct sensor_event_accel), "accel"}, {sizeof(struct sensor_event_mag), "mag"}, {sizeof(struct sensor_event_gyro), "gyro"}, diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 61b0bd20df8..91787ef2473 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -924,6 +924,20 @@ static ssize_t uart_read(FAR struct file *filep, FAR char *buffer, size_t buflen /* Re-enable UART Rx interrupts */ uart_enablerxint(dev); + + /* Check again if the RX buffer is empty. The UART driver + * might have buffered data received between disabling the + * RX interrupt and entering the critical section. Some + * drivers (looking at you, cdcacm...) will push the buffer + * to the receive queue during uart_enablerxint(). + * Just continue processing the RX queue if this happens. + */ + + if (rxbuf->head != rxbuf->tail) + { + leave_critical_section(flags); + continue; + } #endif #ifdef CONFIG_SERIAL_REMOVABLE diff --git a/drivers/syslog/vsyslog.c b/drivers/syslog/vsyslog.c index 3421f514dc2..e6cf91716c5 100644 --- a/drivers/syslog/vsyslog.c +++ b/drivers/syslog/vsyslog.c @@ -132,8 +132,8 @@ int nx_vsyslog(int priority, FAR const IPTR char *fmt, FAR va_list *ap) #if defined(CONFIG_SYSLOG_TIMESTAMP) /* Pre-pend the message with the current time, if available */ - ret = lib_sprintf(&stream.public, "[%5d.%06d] ", - ts.tv_sec, ts.tv_nsec / 1000); + ret = lib_sprintf(&stream.public, "[%5jd.%06ld] ", + (uintmax_t)ts.tv_sec, ts.tv_nsec / 1000); #else ret = 0; #endif diff --git a/drivers/timers/pwm.c b/drivers/timers/pwm.c index 238640de8c1..d35c5c7276c 100644 --- a/drivers/timers/pwm.c +++ b/drivers/timers/pwm.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include @@ -117,12 +118,12 @@ static void pwm_dump(FAR const char *msg, FAR const struct pwm_info_s *info, int i; #endif - pwminfo("%s: frequency: %d\n", msg, info->frequency); + pwminfo("%s: frequency: %" PRId32 "\n", msg, info->frequency); #ifdef CONFIG_PWM_MULTICHAN for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) { - pwminfo(" channel: %d duty: %08x\n", + pwminfo(" channel: %d duty: %08" PRIx32 "\n", info->channels[i].channel, info->channels[i].duty); } #else @@ -248,7 +249,7 @@ static int pwm_close(FAR struct file *filep) /* Disable the PWM device */ DEBUGASSERT(lower->ops->shutdown != NULL); - pwminfo("calling shutdown: %d\n"); + pwminfo("calling shutdown\n"); lower->ops->shutdown(lower); } diff --git a/drivers/usbdev/adb.c b/drivers/usbdev/adb.c index 28423f9cfcd..d9ceb3c2bdc 100644 --- a/drivers/usbdev/adb.c +++ b/drivers/usbdev/adb.c @@ -1157,6 +1157,7 @@ static int usbclass_setup(FAR struct usbdevclass_driver_s *driver, { #ifndef CONFIG_USBADB_COMPOSITE case USB_REQ_GETDESCRIPTOR: + { /* The value field specifies the descriptor type in the * MS byte and the descriptor index in the LS byte * (order is little endian) @@ -1216,6 +1217,8 @@ static int usbclass_setup(FAR struct usbdevclass_driver_s *driver, } break; } + } + break; /* If the serial device is used in as part of a composite device, * then the overall composite class configuration is managed by @@ -1267,13 +1270,6 @@ static int usbclass_setup(FAR struct usbdevclass_driver_s *driver, } #ifndef CONFIG_USBADB_COMPOSITE - - /* Composite should send only one resquest for USB_REQ_SETCONFIGURATION. - * Hence ADB driver cannot submit to ep0; composite has to handle it. - */ - - #warning composite_ep0submit() seems broken so skip it in case of composite - /* Respond to the setup command if data was returned. On an error return * value (ret < 0), the USB driver will stall. */ @@ -1297,6 +1293,12 @@ static int usbclass_setup(FAR struct usbdevclass_driver_s *driver, usbclass_ep0incomplete(dev->ep0, ctrlreq); } } +#else + /* Composite should send only one resquest for USB_REQ_SETCONFIGURATION. + * Hence ADB driver cannot submit to ep0; composite has to handle it. + */ + + #warning composite_ep0submit() seems broken so skip it in case of composite #endif /* !CONFIG_USBADB_COMPOSITE */ /* Returning a negative value will cause a STALL */ diff --git a/drivers/usbhost/usbhost_enumerate.c b/drivers/usbhost/usbhost_enumerate.c index 3bf93ad4faf..e693443405a 100644 --- a/drivers/usbhost/usbhost_enumerate.c +++ b/drivers/usbhost/usbhost_enumerate.c @@ -178,7 +178,8 @@ static inline int usbhost_configdesc(const uint8_t *configdesc, int cfglen, ifdesc = (struct usb_ifdesc_s *)configdesc; if (ifdesc->type == USB_DESC_TYPE_INTERFACE) { - /* Yes, extract the class information from the interface descriptor. + /* Yes, extract the class information from the interface + * descriptor. * Typically these values are zero meaning that the "real" ID * information resides in the device descriptor. */ @@ -192,7 +193,7 @@ static inline int usbhost_configdesc(const uint8_t *configdesc, int cfglen, return OK; } - /* Increment the address of the next descriptor */ + /* Increment the address of the next descriptor */ configdesc += ifdesc->len; remaining -= ifdesc->len; @@ -281,8 +282,8 @@ static inline int usbhost_classbind(FAR struct usbhost_hubport_s *hport, * into this caller-provided memory location. * * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value is - * returned indicating the nature of the failure + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure * * Assumptions: * - Only a single class bound to a single device is supported. @@ -430,11 +431,11 @@ int usbhost_enumerate(FAR struct usbhost_hubport_s *hport, ret = DRVR_CTRLOUT(hport->drvr, hport->ep0, ctrlreq, NULL); if (ret < 0) { - uerr("ERROR: Failed to set address: %d\n"); + uerr("ERROR: Failed to set address: %d\n", ret); goto errout; } - nxsig_usleep(2*1000); + nxsig_usleep(2 * 1000); /* Assign the function address to the port */ @@ -459,7 +460,7 @@ int usbhost_enumerate(FAR struct usbhost_hubport_s *hport, ret = DRVR_CTRLIN(hport->drvr, hport->ep0, ctrlreq, buffer); if (ret < 0) - { + { uerr("ERROR: Failed to get configuration descriptor, length=%d: %d\n", USB_SIZEOF_CFGDESC, ret); goto errout; @@ -467,12 +468,14 @@ int usbhost_enumerate(FAR struct usbhost_hubport_s *hport, /* Extract the full size of the configuration data */ - cfglen = (unsigned int)usbhost_getle16(((struct usb_cfgdesc_s *)buffer)->totallen); + cfglen = (unsigned int) + usbhost_getle16(((struct usb_cfgdesc_s *)buffer)->totallen); uinfo("sizeof config data: %d\n", cfglen); if (cfglen > maxlen) { - uerr("ERROR: Configuration doesn't fit in buffer, length=%d, maxlen=%d\n", + uerr("ERROR: Configuration doesn't fit in buffer, " + "length=%d, maxlen=%d\n", cfglen, maxlen); ret = -E2BIG; goto errout; @@ -532,7 +535,7 @@ int usbhost_enumerate(FAR struct usbhost_hubport_s *hport, /* Some devices may require some delay before initialization */ - nxsig_usleep(100*1000); + nxsig_usleep(100 * 1000); #ifdef CONFIG_USBHOST_COMPOSITE /* Check if the device attached to the downstream port if a USB composite diff --git a/drivers/usbhost/usbhost_storage.c b/drivers/usbhost/usbhost_storage.c index 0fe12198b4d..967daeff38b 100644 --- a/drivers/usbhost/usbhost_storage.c +++ b/drivers/usbhost/usbhost_storage.c @@ -2144,7 +2144,7 @@ static ssize_t usbhost_write(FAR struct inode *inode, ssize_t nbytes; int ret; - uinfo("sector: %d nsectors: %d sectorsize: %d\n"); + uinfo("sector: %zu nsectors: %u\n", startsector, nsectors); DEBUGASSERT(inode && inode->i_private); priv = (FAR struct usbhost_state_s *)inode->i_private; diff --git a/drivers/usbhost/usbhost_trace.c b/drivers/usbhost/usbhost_trace.c index bc9963893c7..e6c16944bad 100644 --- a/drivers/usbhost/usbhost_trace.c +++ b/drivers/usbhost/usbhost_trace.c @@ -170,6 +170,7 @@ void usbhost_trace_common(uint32_t event) } } } + leave_critical_section(flags); } #endif /* CONFIG_USBHOST_TRACE */ @@ -202,7 +203,10 @@ void usbhost_trace1(uint16_t id, uint32_t u23) /* Get the format associated with the trace */ fmt = usbhost_trformat1(id); - DEBUGASSERT(fmt); + if (fmt == NULL) + { + return; + } /* Just print the data using syslog() */ @@ -220,7 +224,10 @@ void usbhost_trace2(uint16_t id, uint8_t u7, uint16_t u16) /* Get the format associated with the trace */ fmt = usbhost_trformat2(id); - DEBUGASSERT(fmt); + if (fmt == NULL) + { + return; + } /* Just print the data using syslog() */ diff --git a/drivers/wireless/gs2200m.c b/drivers/wireless/gs2200m.c index b1cba2c514a..6bcce63997a 100644 --- a/drivers/wireless/gs2200m.c +++ b/drivers/wireless/gs2200m.c @@ -1629,8 +1629,9 @@ static enum pkt_type_e gs2200m_get_mac(FAR struct gs2200m_dev_s *dev) goto errout; } - n = sscanf(pkt_dat.msg[0], "%2x:%2x:%2x:%2x:%2x:%2x", - &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); + n = sscanf(pkt_dat.msg[0], "%2" PRIx32 ":%2" PRIx32 ":%2" PRIx32 + ":%2" PRIx32 ":%2" PRIx32 ":%2" PRIx32, + &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); DEBUGASSERT(n == 6); for (n = 0; n < 6; n++) @@ -2766,7 +2767,7 @@ static int gs2200m_ioctl_iwreq(FAR struct gs2200m_dev_s *dev, goto errout; } - n = sscanf(pkt_dat.msg[2], "BSSID=%x:%x:%x:%x:%x:%x %s", + n = sscanf(pkt_dat.msg[2], "BSSID=%c:%c:%c:%c:%c:%c %s", &res->u.ap_addr.sa_data[0], &res->u.ap_addr.sa_data[1], &res->u.ap_addr.sa_data[2], &res->u.ap_addr.sa_data[3], &res->u.ap_addr.sa_data[4], &res->u.ap_addr.sa_data[5], @@ -2785,7 +2786,7 @@ static int gs2200m_ioctl_iwreq(FAR struct gs2200m_dev_s *dev, goto errout; } - n = sscanf(pkt_dat.msg[2], "%s CHANNEL=%d %s", + n = sscanf(pkt_dat.msg[2], "%s CHANNEL=%" SCNd32 " %s", cmd, &res->u.freq.m, cmd2); ASSERT(3 == n); wlinfo("CHANNEL:%d\n", res->u.freq.m); @@ -2798,7 +2799,7 @@ static int gs2200m_ioctl_iwreq(FAR struct gs2200m_dev_s *dev, goto errout; } - n = sscanf(pkt_dat.msg[3], "RSSI=%d", &res->u.qual.level); + n = sscanf(pkt_dat.msg[3], "RSSI=%" SCNd8, &res->u.qual.level); ASSERT(1 == n); wlinfo("RSSI:%d\n", res->u.qual.level); } diff --git a/drivers/wireless/ieee802154/mrf24j40/mrf24j40_regops.c b/drivers/wireless/ieee802154/mrf24j40/mrf24j40_regops.c index b6d6cc32be2..7cae957de12 100644 --- a/drivers/wireless/ieee802154/mrf24j40/mrf24j40_regops.c +++ b/drivers/wireless/ieee802154/mrf24j40/mrf24j40_regops.c @@ -43,6 +43,7 @@ #include #include +#include #include #include "mrf24j40.h" @@ -158,7 +159,7 @@ int mrf24j40_regdump(FAR struct mrf24j40_radio_s *dev) { if ((i & 15) == 0) { - len = sprintf(buf, "%02x: ", i & 0xff); + len = sprintf(buf, "%02" PRIx32 ": ", i & 0xff); } len += sprintf(buf + len, "%02x ", mrf24j40_getreg(dev->spi, i)); @@ -175,7 +176,7 @@ int mrf24j40_regdump(FAR struct mrf24j40_radio_s *dev) { if ((i & 15) == 0) { - len = sprintf(buf, "%02x: ", i & 0xff); + len = sprintf(buf, "%02" PRIx32 ": ", i & 0xff); } len += sprintf(buf + len, "%02x ", mrf24j40_getreg(dev->spi, i)); diff --git a/fs/Makefile b/fs/Makefile index 786c94967f6..6d7717ada53 100644 --- a/fs/Makefile +++ b/fs/Makefile @@ -97,9 +97,13 @@ $(BIN): $(OBJS) $(call ARCHIVE, $@, $(OBJS)) context:: + +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) .depend: Makefile $(SRCS) $(TOPDIR)$(DELIM).config - $(Q) $(MKDEP) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile $(Q) touch $@ depend: .depend diff --git a/fs/binfs/fs_binfs.c b/fs/binfs/fs_binfs.c index 81b960f5a0e..f59e4518335 100644 --- a/fs/binfs/fs_binfs.c +++ b/fs/binfs/fs_binfs.c @@ -193,7 +193,7 @@ static ssize_t binfs_read(FAR struct file *filep, { /* Reading is not supported. Just return end-of-file */ - finfo("Read %d bytes from offset %d\n", buflen, filep->f_pos); + finfo("Read %zu bytes from offset %d\n", buflen, filep->f_pos); return 0; } diff --git a/fs/fat/fs_fat32util.c b/fs/fat/fs_fat32util.c index e58ab62d159..c69cc9d3775 100644 --- a/fs/fat/fs_fat32util.c +++ b/fs/fat/fs_fat32util.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include @@ -106,10 +107,11 @@ static int fat_checkbootrecord(struct fat_mountpt_s *fs) if (FBR_GETSIGNATURE(fs->fs_buffer) != BOOT_SIGNATURE16 || FBR_GETBYTESPERSEC(fs->fs_buffer) != fs->fs_hwsectorsize) { - fwarn("WARNING: Signature: %04x FS sectorsize: %d HW sectorsize: %d\n", + fwarn("WARNING: Signature: %04x FS sectorsize: %d " + "HW sectorsize: %jd\n", FBR_GETSIGNATURE(fs->fs_buffer), FBR_GETBYTESPERSEC(fs->fs_buffer), - fs->fs_hwsectorsize); + (intmax_t)fs->fs_hwsectorsize); return -EINVAL; } @@ -146,7 +148,7 @@ static int fat_checkbootrecord(struct fat_mountpt_s *fs) if (!fs->fs_nfatsects || fs->fs_nfatsects >= fs->fs_hwnsectors) { - fwarn("WARNING: fs_nfatsects %d fs_hwnsectors: %d\n", + fwarn("WARNING: fs_nfatsects %" PRId32 " fs_hwnsectors: %" PRId32 "\n", fs->fs_nfatsects, fs->fs_hwnsectors); return -EINVAL; @@ -166,8 +168,8 @@ static int fat_checkbootrecord(struct fat_mountpt_s *fs) if (!fs->fs_fattotsec || fs->fs_fattotsec > fs->fs_hwnsectors) { - fwarn("WARNING: fs_fattotsec %d fs_hwnsectors: %d\n", - fs->fs_fattotsec, fs->fs_hwnsectors); + fwarn("WARNING: fs_fattotsec %" PRId32 " fs_hwnsectors: %jd\n", + fs->fs_fattotsec, (intmax_t)fs->fs_hwnsectors); return -EINVAL; } @@ -177,8 +179,8 @@ static int fat_checkbootrecord(struct fat_mountpt_s *fs) fs->fs_fatresvdseccount = FBR_GETRESVDSECCOUNT(fs->fs_buffer); if (fs->fs_fatresvdseccount > fs->fs_hwnsectors) { - fwarn("WARNING: fs_fatresvdseccount %d fs_hwnsectors: %d\n", - fs->fs_fatresvdseccount, fs->fs_hwnsectors); + fwarn("WARNING: fs_fatresvdseccount %d fs_hwnsectors: %jd\n", + fs->fs_fatresvdseccount, (intmax_t)fs->fs_hwnsectors); return -EINVAL; } @@ -196,8 +198,8 @@ static int fat_checkbootrecord(struct fat_mountpt_s *fs) ntotalfatsects - rootdirsectors; if (ndatasectors > fs->fs_hwnsectors) { - fwarn("WARNING: ndatasectors %d fs_hwnsectors: %d\n", - ndatasectors, fs->fs_hwnsectors); + fwarn("WARNING: ndatasectors %" PRId32 " fs_hwnsectors: %jd\n", + ndatasectors, (intmax_t)fs->fs_hwnsectors); return -EINVAL; } @@ -229,7 +231,7 @@ static int fat_checkbootrecord(struct fat_mountpt_s *fs) } else { - fwarn("WARNING: notfat32: %d fs_nclusters: %d\n", + fwarn("WARNING: notfat32: %d fs_nclusters: %" PRId32 "\n", notfat32, fs->fs_nclusters); return -EINVAL; @@ -634,21 +636,21 @@ int fat_mount(struct fat_mountpt_s *fs, bool writeable) /* We did it! */ finfo("FAT%d:\n", fs->fs_type == 0 ? 12 : fs->fs_type == 1 ? 16 : 32); - finfo("\tHW sector size: %d\n", fs->fs_hwsectorsize); - finfo("\t sectors: %d\n", fs->fs_hwnsectors); + finfo("\tHW sector size: %jd\n", (intmax_t)fs->fs_hwsectorsize); + finfo("\t sectors: %jd\n", (intmax_t)fs->fs_hwnsectors); finfo("\tFAT reserved: %d\n", fs->fs_fatresvdseccount); - finfo("\t sectors: %d\n", fs->fs_fattotsec); - finfo("\t start sector: %d\n", fs->fs_fatbase); - finfo("\t root sector: %d\n", fs->fs_rootbase); + finfo("\t sectors: %" PRId32 "\n", fs->fs_fattotsec); + finfo("\t start sector: %jd\n", (intmax_t)fs->fs_fatbase); + finfo("\t root sector: %jd\n", (intmax_t)fs->fs_rootbase); finfo("\t root entries: %d\n", fs->fs_rootentcnt); - finfo("\t data sector: %d\n", fs->fs_database); - finfo("\t FSINFO sector: %d\n", fs->fs_fsinfo); + finfo("\t data sector: %jd\n", (intmax_t)fs->fs_database); + finfo("\t FSINFO sector: %jd\n", (intmax_t)fs->fs_fsinfo); finfo("\t Num FATs: %d\n", fs->fs_fatnumfats); - finfo("\t FAT sectors: %d\n", fs->fs_nfatsects); + finfo("\t FAT sectors: %" PRId32 "\n", fs->fs_nfatsects); finfo("\t sectors/cluster: %d\n", fs->fs_fatsecperclus); - finfo("\t max clusters: %d\n", fs->fs_nclusters); - finfo("\tFSI free count %d\n", fs->fs_fsifreecount); - finfo("\t next free %d\n", fs->fs_fsinextfree); + finfo("\t max clusters: %" PRId32 "\n", fs->fs_nclusters); + finfo("\tFSI free count %" PRId32 "\n", fs->fs_fsifreecount); + finfo("\t next free %" PRId32 "\n", fs->fs_fsinextfree); return OK; @@ -2160,8 +2162,9 @@ int fat_currentsector(struct fat_mountpt_s *fs, struct fat_file_s *ff, ff->ff_sectorsincluster = fs->fs_fatsecperclus - sectoroffset; - finfo("position=%d currentsector=%d sectorsincluster=%d\n", - position, ff->ff_currentsector, ff->ff_sectorsincluster); + finfo("position=%jd currentsector=%jd sectorsincluster=%d\n", + (intmax_t)position, (intmax_t)ff->ff_currentsector, + ff->ff_sectorsincluster); return OK; } diff --git a/fs/inode/fs_files.c b/fs/inode/fs_files.c index 7c527f7c071..af466e8f998 100644 --- a/fs/inode/fs_files.c +++ b/fs/inode/fs_files.c @@ -150,9 +150,9 @@ void files_releaselist(FAR struct filelist *list) * because there should not be any references in this context. */ - for (i = 0; i < CONFIG_NFILE_DESCRIPTORS; i++) + for (i = CONFIG_NFILE_DESCRIPTORS; i > 0; i--) { - _files_close(&list->fl_files[i]); + _files_close(&list->fl_files[i - 1]); } /* Destroy the semaphore */ diff --git a/fs/mmap/fs_mmap.c b/fs/mmap/fs_mmap.c index a7ff023b6e9..cc90282741a 100644 --- a/fs/mmap/fs_mmap.c +++ b/fs/mmap/fs_mmap.c @@ -152,7 +152,7 @@ FAR void *mmap(FAR void *start, size_t length, int prot, int flags, if (length == 0) { - ferr("ERROR: Invalid length, length=%d\n", length); + ferr("ERROR: Invalid length, length=%zu\n", length); errcode = EINVAL; goto errout; } diff --git a/fs/nxffs/nxffs_cache.c b/fs/nxffs/nxffs_cache.c index 63bf071e1c0..9581d66d811 100644 --- a/fs/nxffs/nxffs_cache.c +++ b/fs/nxffs/nxffs_cache.c @@ -44,6 +44,8 @@ #include #include #include +#include +#include #include @@ -82,7 +84,8 @@ int nxffs_rdcache(FAR struct nxffs_volume_s *volume, off_t block) nxfrd = MTD_BREAD(volume->mtd, block, 1, volume->cache); if (nxfrd != 1) { - ferr("ERROR: Read block %d failed: %d\n", block, nxfrd); + ferr("ERROR: Read block %jd failed: %zu\n", + (intmax_t)block, nxfrd); return -EIO; } @@ -117,7 +120,8 @@ int nxffs_wrcache(FAR struct nxffs_volume_s *volume) nxfrd = MTD_BWRITE(volume->mtd, volume->cblock, 1, volume->cache); if (nxfrd != 1) { - ferr("ERROR: Write block %d failed: %d\n", volume->cblock, nxfrd); + ferr("ERROR: Write block %jd failed: %zu\n", + (intmax_t)volume->cblock, nxfrd); return -EIO; } @@ -179,8 +183,9 @@ off_t nxffs_iotell(FAR struct nxffs_volume_s *volume) * over bad blocks and block headers as necessary. * * Input Parameters: - * volume - Describes the NXFFS volume. The parameters ioblock and iooffset - * in the volume structure determine the behavior of nxffs_getc(). + * volume - Describes the NXFFS volume. The parameters ioblock and + * iooffset in the volume structure determine the behavior of + * nxffs_getc(). * reserve - If less than this much space is available at the end of the * block, then skip to the next block. * @@ -200,7 +205,9 @@ int nxffs_getc(FAR struct nxffs_volume_s *volume, uint16_t reserve) do { - /* Check if we have the reserve amount at the end of the current block */ + /* Check if we have the reserve amount at the end of the current + * block + */ if (volume->iooffset + reserve > volume->geo.blocksize) { diff --git a/fs/nxffs/nxffs_initialize.c b/fs/nxffs/nxffs_initialize.c index 8491d6c85b0..5695a72769f 100644 --- a/fs/nxffs/nxffs_initialize.c +++ b/fs/nxffs/nxffs_initialize.c @@ -495,11 +495,7 @@ int nxffs_limits(FAR struct nxffs_volume_s *volume) } else { - volume->ioblock += 1; - volume->iooffset = SIZEOF_NXFFS_BLOCK_HDR; - - offset = volume->ioblock * volume->geo.blocksize + - volume->iooffset; + offset += nerased + 1; nerased = 0; } } diff --git a/fs/nxffs/nxffs_open.c b/fs/nxffs/nxffs_open.c index c08a0548626..b060ebc9bc1 100644 --- a/fs/nxffs/nxffs_open.c +++ b/fs/nxffs/nxffs_open.c @@ -99,7 +99,8 @@ static struct nxffs_wrfile_s g_wrfile; * * On successful return the following are also valid: * - * wrfile->ofile.entry.hoffset - FLASH offset to candidate header position + * wrfile->ofile.entry.hoffset - FLASH offset to candidate header + * position * volume->ioblock - Read/write block number of the block containing the * header position * volume->iooffset - The offset in the block to the candidate header @@ -217,7 +218,8 @@ static inline int nxffs_nampos(FAR struct nxffs_volume_s *volume, * * On successful return the following are also valid: * - * wrfile->ofile.entry.hoffset - FLASH offset to candidate header position + * wrfile->ofile.entry.hoffset - FLASH offset to candidate header + * position * volume->ioblock - Read/write block number of the block containing the * header position * volume->iooffset - The offset in the block to the candidate header @@ -451,9 +453,10 @@ static inline int nxffs_wropen(FAR struct nxffs_volume_s *volume, else if ((oflags & (O_CREAT | O_TRUNC)) == (O_CREAT | O_TRUNC)) { - /* Just schedule the removal the file and fall through to re-create it. - * Note that the old file of the same name will not actually be removed - * until the new file is successfully written. + /* Just schedule the removal the file and fall through to re-create + * it. + * Note that the old file of the same name will not actually be + * removed until the new file is successfully written. */ truncate = true; @@ -465,7 +468,8 @@ static inline int nxffs_wropen(FAR struct nxffs_volume_s *volume, else { - ferr("ERROR: File %s exists and we were not asked to truncate it\n"); + ferr("ERROR: File %s exists and we were not asked to " + "truncate it\n", name); ret = -ENOSYS; goto errout_with_exclsem; } @@ -501,7 +505,8 @@ static inline int nxffs_wropen(FAR struct nxffs_volume_s *volume, wrfile = &g_wrfile; memset(wrfile, 0, sizeof(struct nxffs_wrfile_s)); #else - wrfile = (FAR struct nxffs_wrfile_s *)kmm_zalloc(sizeof(struct nxffs_wrfile_s)); + wrfile = (FAR struct nxffs_wrfile_s *) + kmm_zalloc(sizeof(struct nxffs_wrfile_s)); if (!wrfile) { ret = -ENOMEM; @@ -736,7 +741,8 @@ static inline int nxffs_rdopen(FAR struct nxffs_volume_s *volume, { /* Not already open.. create a new open structure */ - ofile = (FAR struct nxffs_ofile_s *)kmm_zalloc(sizeof(struct nxffs_ofile_s)); + ofile = (FAR struct nxffs_ofile_s *) + kmm_zalloc(sizeof(struct nxffs_ofile_s)); if (!ofile) { ferr("ERROR: ofile allocation failed\n"); @@ -876,7 +882,8 @@ static inline int nxffs_wrclose(FAR struct nxffs_volume_s *volume, ret = nxffs_wrblkhdr(volume, wrfile); if (ret < 0) { - ferr("ERROR: Failed to write the final block of the file: %d\n", -ret); + ferr("ERROR: Failed to write the final block of the file: %d\n", + -ret); goto errout; } } @@ -970,7 +977,8 @@ FAR struct nxffs_ofile_s *nxffs_findofile(FAR struct nxffs_volume_s *volume, * ****************************************************************************/ -FAR struct nxffs_wrfile_s *nxffs_findwriter(FAR struct nxffs_volume_s *volume) +FAR struct nxffs_wrfile_s *nxffs_findwriter( + FAR struct nxffs_volume_s *volume) { /* We can tell if the write is in-use because it will have an allocated * name attached. @@ -1205,8 +1213,8 @@ errout: * entry - Describes the inode header to write * * Returned Value: - * Zero is returned on success; Otherwise, a negated errno value is returned - * indicating the nature of the failure. + * Zero is returned on success; Otherwise, a negated errno value is + * returned indicating the nature of the failure. * ****************************************************************************/ @@ -1288,8 +1296,8 @@ errout: * entry - Describes the new inode entry * * Returned Value: - * Zero is returned on success; Otherwise, a negated errno value is returned - * indicating the nature of the failure. + * Zero is returned on success; Otherwise, a negated errno value is + * returned indicating the nature of the failure. * ****************************************************************************/ diff --git a/fs/nxffs/nxffs_pack.c b/fs/nxffs/nxffs_pack.c index a87a88f13d1..aefff8778b3 100644 --- a/fs/nxffs/nxffs_pack.c +++ b/fs/nxffs/nxffs_pack.c @@ -337,7 +337,8 @@ static inline int nxffs_startpos(FAR struct nxffs_volume_s *volume, */ nbytes += blkentry.datlen; - offset = blkentry.hoffset + SIZEOF_NXFFS_DATA_HDR + blkentry.datlen; + offset = blkentry.hoffset + SIZEOF_NXFFS_DATA_HDR + + blkentry.datlen; } /* Make sure there is space at this location for an inode header */ @@ -454,10 +455,10 @@ static int nxffs_destsetup(FAR struct nxffs_volume_s *volume, /* The destination can be in one of three of states: * * State 1: The inode position was not yet been found. This condition can - * only occur on initial entry into nxffs_packblock() when there we no space - * for the inode header at the end of the previous block. We must now be - * at the beginning of a shiny new I/O block, so we should always have - * space for a new inode header right here. + * only occur on initial entry into nxffs_packblock() when there we no + * space for the inode header at the end of the previous block. We must + * now be at the beginning of a shiny new I/O block, so we should always + * have space for a new inode header right here. */ if (pack->dest.entry.hoffset == 0) @@ -528,8 +529,8 @@ static int nxffs_destsetup(FAR struct nxffs_volume_s *volume, pack->iooffset += namlen; } - /* State 3: Inode header not-written, inode name written. Still need the position - * of the first data block. + /* State 3: Inode header not-written, inode name written. Still need the + * position of the first data block. * * Deal with the special case where the source inode is a zero length file * with no data blocks to be transferred. @@ -539,16 +540,16 @@ static int nxffs_destsetup(FAR struct nxffs_volume_s *volume, { if (pack->dest.entry.doffset == 0) { - /* Will the data block header plus a minimal amount of data fit in this - * block? (or the whole file if the file is very small). + /* Will the data block header plus a minimal amount of data fit in + * this block? (or the whole file if the file is very small). */ mindata = MIN(NXFFS_MINDATA, pack->dest.entry.datlen); if (pack->iooffset + SIZEOF_NXFFS_DATA_HDR + mindata > volume->geo.blocksize) { - /* No.. return an indication that we are at the end of the block - * and try again later. + /* No.. return an indication that we are at the end of the + * block and try again later. */ ret = -ENOSPC; @@ -560,29 +561,31 @@ static int nxffs_destsetup(FAR struct nxffs_volume_s *volume, pack->dest.entry.doffset = nxffs_packtell(volume, pack); pack->iooffset += SIZEOF_NXFFS_DATA_HDR; - /* Initialize the output data stream to start with the first data block */ + /* Initialize the output data stream to start with the first data + * block + */ pack->dest.blkoffset = pack->dest.entry.doffset; pack->dest.blklen = 0; pack->dest.blkpos = 0; } - /* State 4: Starting a new block. Verify that there is space in the current - * block for another (minimal sized) block + /* State 4: Starting a new block. Verify that there is space in the + * current block for another (minimal sized) block */ if (pack->dest.blkoffset == 0) { - /* Will the data block header plus a minimal amount of data fit in this - * block? (or the whole file if the file is very small). + /* Will the data block header plus a minimal amount of data fit in + * this block? (or the whole file if the file is very small). */ mindata = MIN(NXFFS_MINDATA, pack->dest.entry.datlen); if (pack->iooffset + SIZEOF_NXFFS_DATA_HDR + mindata > volume->geo.blocksize) { - /* No.. return an indication that we are at the end of the block - * and try again later. + /* No.. return an indication that we are at the end of the + * block and try again later. */ ret = -ENOSPC; @@ -691,7 +694,8 @@ static int nxffs_wrinodehdr(FAR struct nxffs_volume_s *volume, /* Calculate the CRC */ crc = crc32((FAR const uint8_t *)inode, SIZEOF_NXFFS_INODE_HDR); - crc = crc32part((FAR const uint8_t *)pack->dest.entry.name, namlen, crc); + crc = crc32part((FAR const uint8_t *)pack->dest.entry.name, namlen, + crc); /* Finish the inode header */ @@ -705,7 +709,7 @@ static int nxffs_wrinodehdr(FAR struct nxffs_volume_s *volume, ret = nxffs_updateinode(volume, &pack->dest.entry); if (ret < 0) { - ferr("ERROR: Failed to update inode info: %s\n", -ret); + ferr("ERROR: Failed to update inode info: %d\n", -ret); } } @@ -742,9 +746,9 @@ static void nxffs_wrdathdr(FAR struct nxffs_volume_s *volume, if (pack->dest.blklen > 0) { - /* Get the offset in the block corresponding to the location of the data - * block header. NOTE: This must lie in the same block as we currently have - * buffered. + /* Get the offset in the block corresponding to the location of the + * data block header. NOTE: This must lie in the same block as we + * currently have buffered. */ ioblock = nxffs_getblock(volume, pack->dest.blkoffset); @@ -928,8 +932,8 @@ static inline int nxffs_packblock(FAR struct nxffs_volume_s *volume, } /* Loop, transferring data from the source block to the destination pack - * buffer until either (1) the source stream is exhausted, (2) the destination - * block is full, or (3) an error occurs. + * buffer until either (1) the source stream is exhausted, (2) the + * destination block is full, or (3) an error occurs. */ for (; ; ) @@ -962,8 +966,8 @@ static inline int nxffs_packblock(FAR struct nxffs_volume_s *volume, ret = nxffs_nextentry(volume, offset, &pack->src.entry); if (ret < 0) { - /* No more valid inode entries. Just return an end-of-flash error - * indication. + /* No more valid inode entries. Just return an end-of-flash + * error indication. */ return -ENOSPC; @@ -989,10 +993,11 @@ static inline int nxffs_packblock(FAR struct nxffs_volume_s *volume, * the inode header? */ - if (pack->iooffset + SIZEOF_NXFFS_INODE_HDR > volume->geo.blocksize) + if (pack->iooffset + SIZEOF_NXFFS_INODE_HDR > + volume->geo.blocksize) { - /* No, just return success... we will handle this condition when - * this function is called on the next I/O block. + /* No, just return success... we will handle this condition + * when this function is called on the next I/O block. */ return OK; @@ -1003,9 +1008,9 @@ static inline int nxffs_packblock(FAR struct nxffs_volume_s *volume, ret = nxffs_destsetup(volume, pack); if (ret < 0) { - /* -ENOSPC is a special return value which simply means that all of the - * has been used up to the end. We need to return OK in this case and - * resume at the next block. + /* -ENOSPC is a special return value which simply means that + * all of the has been used up to the end. We need to return + * OK in this case and resume at the next block. */ if (ret == -ENOSPC) @@ -1014,7 +1019,8 @@ static inline int nxffs_packblock(FAR struct nxffs_volume_s *volume, } else { - ferr("ERROR: Failed to configure the dest stream: %d\n", -ret); + ferr("ERROR: Failed to configure the dest stream: %d\n", + -ret); return ret; } } @@ -1037,7 +1043,9 @@ static inline int nxffs_packblock(FAR struct nxffs_volume_s *volume, if (pack->iooffset >= volume->geo.blocksize) { - /* Yes.. Write the destination data block header and return success */ + /* Yes.. Write the destination data block header and return + * success + */ nxffs_wrdathdr(volume, pack); return OK; @@ -1081,10 +1089,10 @@ nxffs_setupwriter(FAR struct nxffs_volume_s *volume, * this packing activity. The writer may have failed in one of several * different stages: * - * hoffset == 0: The write failed early before even FLASH for the inode - * header was set aside. - * noffset == 0: The write failed after the inode header was set aside, - * but before the inode name was written. + * hoffset == 0: The write failed early before even FLASH for the + * inode header was set aside. + * noffset == 0: The write failed after the inode header was set + * aside, but before the inode name was written. * doffset == 0: The write failed after writing the inode name, bue * before any data blocks were written to FLASH. * @@ -1182,8 +1190,8 @@ static inline int nxffs_packwriter(FAR struct nxffs_volume_s *volume, } /* Loop, transferring data from the source block to the destination pack - * buffer until either (1) the source stream is exhausted, (2) the destination - * block is full, or (3) an error occurs. + * buffer until either (1) the source stream is exhausted, (2) the + * destination block is full, or (3) an error occurs. */ for (; ; ) @@ -1237,7 +1245,9 @@ static inline int nxffs_packwriter(FAR struct nxffs_volume_s *volume, if (pack->iooffset >= volume->geo.blocksize) { - /* Yes.. Write the destination data block header and return success */ + /* Yes.. Write the destination data block header and return + * success + */ nxffs_wrdathdr(volume, pack); return OK; @@ -1287,10 +1297,10 @@ int nxffs_pack(FAR struct nxffs_volume_s *volume) if (iooffset == 0) { /* Offset zero is only returned if no valid blocks were found on the - * FLASH media or if there are no valid inode entries on the FLASH after - * the first valid block. There are two possibilities: (1) there - * really is nothing on the FLASH, or (2) there is a file being written - * to the FLASH now. + * FLASH media or if there are no valid inode entries on the FLASH + * after the first valid block. There are two possibilities: (1) + * there* really is nothing on the FLASH, or (2) there is a file being + * written to the FLASH now. */ /* Is there a writer? */ @@ -1350,11 +1360,12 @@ int nxffs_pack(FAR struct nxffs_volume_s *volume) if (ret == -ENOSPC) { /* In the case where the volume is full, nxffs_startpos() will - * recalculate the free FLASH offset and store it in iooffset. There - * may be deleted files at the end of FLASH. In this case, we don't - * have to pack any files, we simply have to erase FLASH at the end. - * But don't do this unless there is some particularly big FLASH - * savings (otherwise, we risk wearing out these final blocks). + * recalculate the free FLASH offset and store it in iooffset. + * There may be deleted files at the end of FLASH. In this case, + * we don't have to pack any files, we simply have to erase FLASH + * at the end. But don't do this unless there is some particularly + * big FLASH savings (otherwise, we risk wearing out these final + * blocks). */ if (iooffset + CONFIG_NXFFS_TAILTHRESHOLD < volume->froffset) @@ -1419,7 +1430,8 @@ start_pack: * previously marked bad blocks. */ - ret = MTD_BREAD(volume->mtd, pack.block0, volume->blkper, volume->pack); + ret = MTD_BREAD(volume->mtd, pack.block0, volume->blkper, + volume->pack); if (ret < 0) { ferr("ERROR: Failed to read erase block %d: %d\n", eblock, -ret); @@ -1498,7 +1510,8 @@ start_pack: if (ret < 0) { /* The error -ENOSPC is a special value that simply - * means that there is nothing further to be packed. + * means that there is nothing further to be + * packed. */ if (ret == -ENOSPC) @@ -1506,10 +1519,11 @@ start_pack: packed = true; /* Writing is performed at the end of the free - * FLASH region and this implementation is restricted - * to a single writer. The new inode is not - * written to FLASH until the writer is closed - * and so will not be found by nxffs_packblock(). + * FLASH region and this implementation is + * restricted to a single writer. The new + * inode is not written to FLASH until the + * writer is closed and so will not be found + * by nxffs_packblock(). */ wrfile = nxffs_setupwriter(volume, &pack); @@ -1518,15 +1532,17 @@ start_pack: { /* Otherwise, something really bad happened */ - ferr("ERROR: Failed to pack into block %d: %d\n", + ferr("ERROR: Failed to pack into block %d: " + "%d\n", block, ret); goto errout_with_pack; } } } - /* If all of the "normal" inodes have been packed, then check if - * we need to pack the current, in-progress write operation. + /* If all of the "normal" inodes have been packed, then + * check if we need to pack the current, in-progress write + * operation. */ if (wrfile) @@ -1539,7 +1555,8 @@ start_pack: if (ret < 0) { /* The error -ENOSPC is a special value that simply - * means that there is nothing further to be packed. + * means that there is nothing further to be + * packed. */ if (ret == -ENOSPC) @@ -1550,7 +1567,8 @@ start_pack: { /* Otherwise, something really bad happened */ - ferr("ERROR: Failed to pack into block %d: %d\n", + ferr("ERROR: Failed to pack into block %d: " + "%d\n", block, ret); goto errout_with_pack; } @@ -1591,7 +1609,8 @@ start_pack: /* Write the packed I/O block to FLASH */ - ret = MTD_BWRITE(volume->mtd, pack.block0, volume->blkper, volume->pack); + ret = MTD_BWRITE(volume->mtd, pack.block0, volume->blkper, + volume->pack); if (ret < 0) { ferr("ERROR: Failed to write erase block %d [%d]: %d\n", diff --git a/fs/nxffs/nxffs_read.c b/fs/nxffs/nxffs_read.c index f7333c2c005..94bcc9c2e4a 100644 --- a/fs/nxffs/nxffs_read.c +++ b/fs/nxffs/nxffs_read.c @@ -41,6 +41,7 @@ #include +#include #include #include #include @@ -101,7 +102,9 @@ static ssize_t nxffs_rdseek(FAR struct nxffs_volume_s *volume, datend = 0; do { - /* Check if the next data block contains the sought after file position */ + /* Check if the next data block contains the sought after file + * position + */ ret = nxffs_nextblock(volume, offset, blkentry); if (ret < 0) @@ -124,7 +127,8 @@ static ssize_t nxffs_rdseek(FAR struct nxffs_volume_s *volume, /* Return the offset to the data within the current data block */ blkentry->foffset = fpos - datstart; - nxffs_ioseek(volume, blkentry->hoffset + SIZEOF_NXFFS_DATA_HDR + blkentry->foffset); + nxffs_ioseek(volume, blkentry->hoffset + SIZEOF_NXFFS_DATA_HDR + + blkentry->foffset); return OK; } @@ -151,7 +155,7 @@ ssize_t nxffs_read(FAR struct file *filep, FAR char *buffer, size_t buflen) size_t readsize; int ret; - finfo("Read %d bytes from offset %d\n", buflen, filep->f_pos); + finfo("Read %zu bytes from offset %jd\n", buflen, (intmax_t)filep->f_pos); /* Sanity checks */ @@ -322,7 +326,8 @@ int nxffs_nextblock(FAR struct nxffs_volume_s *volume, off_t offset, if (ch != g_datamagic[nmagic]) { /* Ooops... this is the not the right character for the magic - * Sequence. Check if we need to restart or to cancel the sequence: + * Sequence. Check if we need to restart or to cancel the + * sequence: */ if (ch == g_datamagic[0]) @@ -355,7 +360,8 @@ int nxffs_nextblock(FAR struct nxffs_volume_s *volume, off_t offset, /* Read the block header and verify the block at that address */ - ret = nxffs_rdblkhdr(volume, blkentry->hoffset, &blkentry->datlen); + ret = nxffs_rdblkhdr(volume, blkentry->hoffset, + &blkentry->datlen); if (ret == OK) { finfo("Found a valid data block, offset: %d datlen: %d\n", @@ -386,8 +392,8 @@ int nxffs_nextblock(FAR struct nxffs_volume_s *volume, off_t offset, * * Input Parameters: * volume - Describes the current volume. - * offset - The byte offset from the beginning of FLASH where the data block - * header is expected. + * offset - The byte offset from the beginning of FLASH where the data + * block header is expected. * datlen - A memory location to return the data block length. * * Returned Value: @@ -406,7 +412,9 @@ int nxffs_rdblkhdr(FAR struct nxffs_volume_s *volume, off_t offset, uint16_t dlen; int ret; - /* Make sure that the block containing the data block header is in the cache */ + /* Make sure that the block containing the data block header is in the + * cache + */ nxffs_ioseek(volume, offset); ret = nxffs_rdcache(volume, volume->ioblock); @@ -433,7 +441,8 @@ int nxffs_rdblkhdr(FAR struct nxffs_volume_s *volume, off_t offset, if ((uint32_t)doffset + (uint32_t)dlen > (uint32_t)volume->geo.blocksize) { - ferr("ERROR: Data length=%d is unreasonable at offset=%d\n", dlen, doffset); + ferr("ERROR: Data length=%d is unreasonable at offset=%d\n", dlen, + doffset); return -EIO; } diff --git a/fs/nxffs/nxffs_reformat.c b/fs/nxffs/nxffs_reformat.c index 338efa93d7f..7b77cd7c209 100644 --- a/fs/nxffs/nxffs_reformat.c +++ b/fs/nxffs/nxffs_reformat.c @@ -41,6 +41,7 @@ #include +#include #include #include #include @@ -106,7 +107,8 @@ static int nxffs_format(FAR struct nxffs_volume_s *volume) nxfrd = MTD_BWRITE(volume->mtd, lblock, volume->blkper, volume->pack); if (nxfrd != volume->blkper) { - ferr("ERROR: Write erase block %d failed: %d\n", lblock, nxfrd); + ferr("ERROR: Write erase block %jd failed: %zd\n", + (intmax_t)lblock, nxfrd); return -EIO; } } @@ -157,7 +159,8 @@ static int nxffs_badblocks(FAR struct nxffs_volume_s *volume) nxfrd = MTD_BREAD(volume->mtd, lblock, volume->blkper, volume->pack); if (nxfrd != volume->blkper) { - ferr("ERROR: Read erase block %d failed: %d\n", lblock, nxfrd); + ferr("ERROR: Read erase block %jd failed: %zd\n", + (intmax_t)lblock, nxfrd); return -EIO; } #endif @@ -178,7 +181,8 @@ static int nxffs_badblocks(FAR struct nxffs_volume_s *volume) i++, block++, blkptr += volume->geo.blocksize) #endif { - FAR struct nxffs_block_s *blkhdr = (FAR struct nxffs_block_s *)blkptr; + FAR struct nxffs_block_s *blkhdr = + (FAR struct nxffs_block_s *)blkptr; /* Assume that this is a good block until we learn otherwise */ @@ -207,8 +211,8 @@ static int nxffs_badblocks(FAR struct nxffs_volume_s *volume) if (memcmp(blkhdr->magic, g_blockmagic, NXFFS_MAGICSIZE) != 0 || blkhdr->state != BLOCK_STATE_GOOD) { - /* The block is not formatted with the NXFFS magic bytes or else - * the block is specifically marked bad. + /* The block is not formatted with the NXFFS magic bytes or + * else the block is specifically marked bad. */ good = false; @@ -220,9 +224,11 @@ static int nxffs_badblocks(FAR struct nxffs_volume_s *volume) else { - size_t blocksize = volume->geo.blocksize - SIZEOF_NXFFS_BLOCK_HDR; - size_t erasesize = nxffs_erased(&blkptr[SIZEOF_NXFFS_BLOCK_HDR], - blocksize); + size_t blocksize = volume->geo.blocksize - + SIZEOF_NXFFS_BLOCK_HDR; + size_t erasesize = nxffs_erased( + &blkptr[SIZEOF_NXFFS_BLOCK_HDR], + blocksize); good = (blocksize == erasesize); } @@ -246,8 +252,8 @@ static int nxffs_badblocks(FAR struct nxffs_volume_s *volume) volume->pack); if (nxfrd != volume->blkper) { - ferr("ERROR: Write erase block %d failed: %d\n", - lblock, nxfrd); + ferr("ERROR: Write erase block %jd failed: %zd\n", + (intmax_t)lblock, nxfrd); return -EIO; } } diff --git a/fs/nxffs/nxffs_stat.c b/fs/nxffs/nxffs_stat.c index 9ac3bea1319..96c9fd78641 100644 --- a/fs/nxffs/nxffs_stat.c +++ b/fs/nxffs/nxffs_stat.c @@ -148,7 +148,7 @@ int nxffs_stat(FAR struct inode *mountpt, FAR const char *relpath, ret = nxffs_findinode(volume, relpath, &entry); if (ret < 0) { - ferr("ERROR: Inode '%s' not found: %d\n", -ret); + ferr("ERROR: Inode '%s' not found: %d\n", relpath, -ret); goto errout_with_semaphore; } @@ -198,7 +198,7 @@ int nxffs_fstat(FAR const struct file *filep, FAR struct stat *buf) FAR struct nxffs_ofile_s *ofile; int ret; - finfo("Buf %s\n", buf); + finfo("Buf %p\n", buf); DEBUGASSERT(filep != NULL && buf != NULL); /* Recover the open file state from the struct file instance */ diff --git a/fs/nxffs/nxffs_write.c b/fs/nxffs/nxffs_write.c index 31b72f1b121..d59e787ba92 100644 --- a/fs/nxffs/nxffs_write.c +++ b/fs/nxffs/nxffs_write.c @@ -41,6 +41,7 @@ #include +#include #include #include #include @@ -531,7 +532,7 @@ ssize_t nxffs_write(FAR struct file *filep, FAR const char *buffer, ssize_t total; int ret; - finfo("Write %d bytes to offset %d\n", buflen, filep->f_pos); + finfo("Write %zd bytes to offset %jd\n", buflen, (intmax_t)filep->f_pos); /* Sanity checks */ diff --git a/fs/procfs/fs_procfscpuload.c b/fs/procfs/fs_procfscpuload.c index da13d72e6f1..ee6970441ec 100644 --- a/fs/procfs/fs_procfscpuload.c +++ b/fs/procfs/fs_procfscpuload.c @@ -46,6 +46,7 @@ #include #include #include +#include #include #include #include @@ -252,7 +253,8 @@ static ssize_t cpuload_read(FAR struct file *filep, FAR char *buffer, fracpart = 0; } - linesize = snprintf(attr->line, CPULOAD_LINELEN, "%3d.%01d%%\n", + linesize = snprintf(attr->line, CPULOAD_LINELEN, + "%3" PRId32 ".%01" PRId32 "%%\n", intpart, fracpart); /* Save the linesize in case we are re-entered with f_pos > 0 */ diff --git a/fs/procfs/fs_procfsiobinfo.c b/fs/procfs/fs_procfsiobinfo.c index 44e7486a080..dad8fdc4a4d 100644 --- a/fs/procfs/fs_procfsiobinfo.c +++ b/fs/procfs/fs_procfsiobinfo.c @@ -168,6 +168,9 @@ static FAR const char *g_iob_user_names[] = #endif #ifdef CONFIG_WIRELESS_BLUETOOTH "bluetooth", +#endif +#ifdef CONFIG_NET_CAN + "can", #endif "global", }; @@ -294,7 +297,7 @@ static ssize_t iobinfo_read(FAR struct file *filep, FAR char *buffer, /* The first line is the headers */ linesize = snprintf(iobfile->line, IOBINFO_LINELEN, - " TOTAL TOTAL\n"); + " TOTAL TOTAL\n"); copysize = procfs_memcpy(iobfile->line, linesize, buffer, buflen, &offset); @@ -306,7 +309,8 @@ static ssize_t iobinfo_read(FAR struct file *filep, FAR char *buffer, buflen -= copysize; linesize = snprintf(iobfile->line, IOBINFO_LINELEN, - " USER CONSUMED PRODUCED\n"); + " USER CONSUMED " + "PRODUCED\n"); copysize = procfs_memcpy(iobfile->line, linesize, buffer, buflen, &offset); diff --git a/fs/procfs/fs_procfsproc.c b/fs/procfs/fs_procfsproc.c index 0584a9eaa88..3cbf4587a97 100644 --- a/fs/procfs/fs_procfsproc.c +++ b/fs/procfs/fs_procfsproc.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include @@ -630,9 +631,9 @@ static ssize_t proc_status(FAR struct proc_file_s *procfile, return totalsize; } - /* Show the signal mask */ + /* Show the signal mask. Note: sigset_t is uint32_t on NuttX. */ - linesize = snprintf(procfile->line, STATUS_LINELEN, "%-12s%08x\n", + linesize = snprintf(procfile->line, STATUS_LINELEN, "%-12s%08" PRIx32 "\n", "SigMask:", tcb->sigprocmask); copysize = procfs_memcpy(procfile->line, linesize, buffer, remaining, &offset); @@ -769,7 +770,8 @@ static ssize_t proc_loadavg(FAR struct proc_file_s *procfile, fracpart = 0; } - linesize = snprintf(procfile->line, STATUS_LINELEN, "%3d.%01d%%", + linesize = snprintf(procfile->line, STATUS_LINELEN, + "%3" PRId32 ".%01" PRId32 "%%", intpart, fracpart); copysize = procfs_memcpy(procfile->line, linesize, buffer, buflen, &offset); diff --git a/fs/procfs/fs_procfsuptime.c b/fs/procfs/fs_procfsuptime.c index fd92869bd17..12dd895b7e9 100644 --- a/fs/procfs/fs_procfsuptime.c +++ b/fs/procfs/fs_procfsuptime.c @@ -268,7 +268,7 @@ static ssize_t uptime_read(FAR struct file *filep, FAR char *buffer, /* Convert the seconds + hundredths of seconds to a string */ #ifdef CONFIG_SYSTEM_TIME64 - linesize = snprintf(attr->line, UPTIME_LINELEN, "%7llu.%02u\n", + linesize = snprintf(attr->line, UPTIME_LINELEN, "%7" PRIu64 ".%02u\n", sec, csec); #else linesize = snprintf(attr->line, UPTIME_LINELEN, "%7lu.%02u\n", diff --git a/fs/romfs/fs_romfs.c b/fs/romfs/fs_romfs.c index 1676aa3c553..675d075ffc2 100644 --- a/fs/romfs/fs_romfs.c +++ b/fs/romfs/fs_romfs.c @@ -254,7 +254,7 @@ static int romfs_open(FAR struct file *filep, FAR const char *relpath, rf = (FAR struct romfs_file_s *)kmm_zalloc(sizeof(struct romfs_file_s)); if (!rf) { - ferr("ERROR: Failed to allocate private data\n", ret); + ferr("ERROR: Failed to allocate private data\n"); ret = -ENOMEM; goto errout_with_semaphore; } @@ -375,7 +375,7 @@ static ssize_t romfs_read(FAR struct file *filep, FAR char *buffer, int sectorndx; int ret; - finfo("Read %d bytes from offset %d\n", buflen, filep->f_pos); + finfo("Read %zu bytes from offset %jd\n", buflen, (intmax_t)filep->f_pos); /* Sanity checks */ @@ -443,7 +443,8 @@ static ssize_t romfs_read(FAR struct file *filep, FAR char *buffer, /* Read all of the sectors directly into user memory */ - finfo("Read %d sectors starting with %d\n", nsectors, sector); + finfo("Read %d sectors starting with %jd\n", nsectors, + (intmax_t)sector); ret = romfs_hwread(rm, userbuffer, sector, nsectors); if (ret < 0) { @@ -460,7 +461,7 @@ static ssize_t romfs_read(FAR struct file *filep, FAR char *buffer, * it is already there then all is well. */ - finfo("Read sector %d\n", sector); + finfo("Read sector %jd\n", (intmax_t)sector); ret = romfs_filecacheread(rm, rf, sector); if (ret < 0) { @@ -510,7 +511,7 @@ static off_t romfs_seek(FAR struct file *filep, off_t offset, int whence) off_t position; int ret; - finfo("Seek to offset: %d whence: %d\n", offset, whence); + finfo("Seek to offset: %jd whence: %d\n", (intmax_t)offset, whence); /* Sanity checks */ @@ -575,7 +576,7 @@ static off_t romfs_seek(FAR struct file *filep, off_t offset, int whence) /* Set file position and return success */ filep->f_pos = position; - finfo("New file position: %d\n", filep->f_pos); + finfo("New file position: %jd\n", (intmax_t)filep->f_pos); romfs_semgive(rm); return OK; @@ -676,7 +677,7 @@ static int romfs_dup(FAR const struct file *oldp, FAR struct file *newp) newrf = (FAR struct romfs_file_s *)kmm_malloc(sizeof(struct romfs_file_s)); if (!newrf) { - ferr("ERROR: Failed to allocate private data\n", ret); + ferr("ERROR: Failed to allocate private data\n"); ret = -ENOMEM; goto errout_with_semaphore; } @@ -824,7 +825,7 @@ static int romfs_opendir(FAR struct inode *mountpt, FAR const char *relpath, { /* The entry is not a directory */ - ferr("ERROR: '%s' is not a directory: %d\n", relpath); + ferr("ERROR: '%s' is not a directory\n", relpath); ret = -ENOTDIR; goto errout_with_semaphore; } diff --git a/fs/romfs/fs_romfsutil.c b/fs/romfs/fs_romfsutil.c index 608b41717b3..dc15cc5f232 100644 --- a/fs/romfs/fs_romfsutil.c +++ b/fs/romfs/fs_romfsutil.c @@ -27,6 +27,7 @@ #include #include +#include #include #include #include @@ -416,7 +417,8 @@ int romfs_filecacheread(struct romfs_mountpt_s *rm, struct romfs_file_s *rf, { int ret; - finfo("sector: %d cached: %d sectorsize: %d XIP base: %p buffer: %p\n", + finfo("sector: %" PRId32 " cached: %" PRId32 + " sectorsize: %d XIP base: %p buffer: %p\n", sector, rf->rf_cachesector, rm->rm_hwsectorsize, rm->rm_xipbase, rf->rf_buffer); diff --git a/fs/smartfs/smartfs_procfs.c b/fs/smartfs/smartfs_procfs.c index c302d302c28..1d6db338aae 100644 --- a/fs/smartfs/smartfs_procfs.c +++ b/fs/smartfs/smartfs_procfs.c @@ -847,10 +847,11 @@ static size_t smartfs_status_read(FAR struct file *filep, FAR char *buffer, "Total Sectors: %d\nSector Size: %d\n" "Format Sector: %d\nDir Sector: %d\n" "Free Sectors: %d\nReleased Sectors: %d\n" - "Unused Sectors: %d\nBlock Erases: %d\n" + "Unused Sectors: %" PRIu32 "\n" + "Block Erases: %" PRIu32 "\n" "Sectors Per Block: %d\nSector Utilization:%d%%\n" #ifdef CONFIG_MTD_SMART_WEAR_LEVEL - "Uneven Wear Count: %d\n" + "Uneven Wear Count: %" PRIu32 "\n" #endif , procfs_data.formatversion, procfs_data.namelen, diff --git a/fs/spiffs/src/spiffs_core.c b/fs/spiffs/src/spiffs_core.c index 8354fd01c9c..725424f5ade 100644 --- a/fs/spiffs/src/spiffs_core.c +++ b/fs/spiffs/src/spiffs_core.c @@ -45,6 +45,7 @@ #include +#include #include #include @@ -241,7 +242,8 @@ static int spiffs_objlu_scan_callback(FAR struct spiffs_s *fs, int16_t objid, ****************************************************************************/ static int spiffs_objlu_find_id_and_span_callback(FAR struct spiffs_s *fs, - int16_t objid, int16_t blkndx, + int16_t objid, + int16_t blkndx, int entry, FAR const void *user_const, FAR void *user_var) @@ -283,7 +285,8 @@ static int spiffs_objlu_find_id_and_span_callback(FAR struct spiffs_s *fs, * ****************************************************************************/ -static int spiffs_find_objhdr_pgndx_callback(FAR struct spiffs_s *fs, int16_t objid, +static int spiffs_find_objhdr_pgndx_callback(FAR struct spiffs_s *fs, + int16_t objid, int16_t blkndx, int entry, FAR const void *user_const, FAR void *user_var) @@ -352,7 +355,8 @@ static int if (conflicting_name != NULL && (objid & SPIFFS_OBJID_NDXFLAG) != 0) { struct spiffs_pgobj_ndxheader_s objhdr; - int16_t pgndx = SPIFFS_OBJ_LOOKUP_ENTRY_TO_PGNDX(fs, blkndx, entry); + int16_t pgndx = SPIFFS_OBJ_LOOKUP_ENTRY_TO_PGNDX(fs, blkndx, + entry); int ret; ret = spiffs_cache_read(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, @@ -415,7 +419,8 @@ spiffs_objlu_find_free_objid_compact_callback(FAR struct spiffs_s *fs, int ret; ret = spiffs_cache_read(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, - SPIFFS_OBJ_LOOKUP_ENTRY_TO_PADDR(fs, blkndx, entry), + SPIFFS_OBJ_LOOKUP_ENTRY_TO_PADDR(fs, blkndx, + entry), sizeof(struct spiffs_pgobj_ndxheader_s), (FAR uint8_t *)&objhdr); if (ret >= 0 && objhdr.phdr.spndx == 0 && @@ -582,7 +587,8 @@ int spiffs_foreach_objlu(FAR struct spiffs_s *fs, int16_t starting_block, int entries_per_page; int ret; - entry_count = SPIFFS_GEO_BLOCK_COUNT(fs) * SPIFFS_OBJ_LOOKUP_MAX_ENTRIES(fs); + entry_count = SPIFFS_GEO_BLOCK_COUNT(fs) * + SPIFFS_OBJ_LOOKUP_MAX_ENTRIES(fs); cur_block = starting_block; cur_block_addr = starting_block * SPIFFS_GEO_BLOCK_SIZE(fs); objlu_buf = (FAR int16_t *)fs->lu_work; @@ -668,17 +674,18 @@ int spiffs_foreach_objlu(FAR struct spiffs_s *fs, int16_t starting_block, if (ret == SPIFFS_VIS_COUNTINUE_RELOAD) { physoff = cur_block_addr + - SPIFFS_PAGE_TO_PADDR(fs, obj_lookup_page); + SPIFFS_PAGE_TO_PADDR(fs, obj_lookup_page); ret = spiffs_cache_read(fs, - SPIFFS_OP_T_OBJ_LU | - SPIFFS_OP_C_READ, 0, - physoff, - SPIFFS_GEO_PAGE_SIZE(fs), - fs->lu_work); + SPIFFS_OP_T_OBJ_LU | + SPIFFS_OP_C_READ, 0, + physoff, + SPIFFS_GEO_PAGE_SIZE(fs), + fs->lu_work); if (ret < 0) { - ferr("ERROR: spiffs_cache_read() failed: %d\n", + ferr("ERROR: spiffs_cache_read() failed: " + "%d\n", ret); return ret; } @@ -1089,9 +1096,9 @@ int spiffs_page_allocate_data(FAR struct spiffs_s *fs, int16_t objid, ph->flags &= ~SPIFFS_PH_FLAG_USED; ret = spiffs_cache_write(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, 0, - SPIFFS_OBJ_LOOKUP_ENTRY_TO_PADDR(fs, blkndx, entry), - sizeof(struct spiffs_page_header_s), - (FAR uint8_t *)ph); + SPIFFS_OBJ_LOOKUP_ENTRY_TO_PADDR(fs, blkndx, entry), + sizeof(struct spiffs_page_header_s), + (FAR uint8_t *)ph); if (ret < 0) { ferr("ERROR: spiffs_cache_write() failed: %d\n", ret); @@ -1103,9 +1110,9 @@ int spiffs_page_allocate_data(FAR struct spiffs_s *fs, int16_t objid, if (data) { ret = spiffs_cache_write(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, 0, - SPIFFS_OBJ_LOOKUP_ENTRY_TO_PADDR(fs, blkndx, entry) + - sizeof(struct spiffs_page_header_s) + page_offs, - len, data); + SPIFFS_OBJ_LOOKUP_ENTRY_TO_PADDR(fs, blkndx, entry) + + sizeof(struct spiffs_page_header_s) + page_offs, + len, data); if (ret < 0) { ferr("ERROR: spiffs_cache_write() failed: %d\n", ret); @@ -1119,9 +1126,9 @@ int spiffs_page_allocate_data(FAR struct spiffs_s *fs, int16_t objid, { ph->flags &= ~SPIFFS_PH_FLAG_FINAL; ret = spiffs_cache_write(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, 0, - SPIFFS_OBJ_LOOKUP_ENTRY_TO_PADDR(fs, blkndx, entry) + - offsetof(struct spiffs_page_header_s, flags), - sizeof(uint8_t), (FAR uint8_t *)&ph->flags); + SPIFFS_OBJ_LOOKUP_ENTRY_TO_PADDR(fs, blkndx, entry) + + offsetof(struct spiffs_page_header_s, flags), + sizeof(uint8_t), (FAR uint8_t *)&ph->flags); if (ret < 0) { ferr("ERROR: spiffs_cache_write() failed: %d\n", ret); @@ -1216,10 +1223,10 @@ int spiffs_page_move(FAR struct spiffs_s *fs, /* Mark entry in destination object lookup */ ret = spiffs_cache_write(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_UPDT, 0, - SPIFFS_BLOCK_TO_PADDR(fs, SPIFFS_BLOCK_FOR_PAGE(fs, free_pgndx)) + - SPIFFS_OBJ_LOOKUP_ENTRY_FOR_PAGE(fs, free_pgndx) * - sizeof(int16_t), sizeof(int16_t), - (FAR uint8_t *)&ndx); + SPIFFS_BLOCK_TO_PADDR(fs, SPIFFS_BLOCK_FOR_PAGE(fs, free_pgndx)) + + SPIFFS_OBJ_LOOKUP_ENTRY_FOR_PAGE(fs, free_pgndx) * + sizeof(int16_t), sizeof(int16_t), + (FAR uint8_t *)&ndx); if (ret < 0) { ferr("ERROR: spiffs_cache_write() failed: %d\n", ret); @@ -1233,7 +1240,8 @@ int spiffs_page_move(FAR struct spiffs_s *fs, /* Mark finalized in destination page */ phdr->flags &= ~(SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_USED); - ret = spiffs_cache_write(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, objid, + ret = spiffs_cache_write(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, + objid, SPIFFS_PAGE_TO_PADDR(fs, free_pgndx) + offsetof(struct spiffs_page_header_s, flags), sizeof(uint8_t), (FAR uint8_t *)&phdr->flags); @@ -1267,10 +1275,10 @@ int spiffs_page_delete(FAR struct spiffs_s *fs, int16_t pgndx) int16_t d_objid = SPIFFS_OBJID_DELETED; ret = spiffs_cache_write(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_DELE, 0, - SPIFFS_BLOCK_TO_PADDR(fs, SPIFFS_BLOCK_FOR_PAGE(fs, pgndx)) + - SPIFFS_OBJ_LOOKUP_ENTRY_FOR_PAGE(fs, pgndx) * - sizeof(int16_t), sizeof(int16_t), - (FAR uint8_t *)&d_objid); + SPIFFS_BLOCK_TO_PADDR(fs, SPIFFS_BLOCK_FOR_PAGE(fs, pgndx)) + + SPIFFS_OBJ_LOOKUP_ENTRY_FOR_PAGE(fs, pgndx) * + sizeof(int16_t), sizeof(int16_t), + (FAR uint8_t *)&d_objid); if (ret < 0) { ferr("ERROR: spiffs_cache_write() failed: %d\n", ret); @@ -1371,16 +1379,19 @@ int spiffs_fobj_create(FAR struct spiffs_s *fs, objndx_hdr.phdr.objid = objid; objndx_hdr.phdr.spndx = 0; objndx_hdr.phdr.flags = - 0xff & ~(SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_INDEX | SPIFFS_PH_FLAG_USED); + 0xff & ~(SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_INDEX | + SPIFFS_PH_FLAG_USED); objndx_hdr.type = type; objndx_hdr.size = SPIFFS_UNDEFINED_LEN; - strncpy((char *)objndx_hdr.name, (const char *)name, CONFIG_SPIFFS_NAME_MAX); + strncpy((char *)objndx_hdr.name, (const char *)name, + CONFIG_SPIFFS_NAME_MAX); /* Update page */ ret = spiffs_cache_write(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, 0, - SPIFFS_OBJ_LOOKUP_ENTRY_TO_PADDR(fs, blkndx, entry), + SPIFFS_OBJ_LOOKUP_ENTRY_TO_PADDR(fs, blkndx, + entry), sizeof(struct spiffs_pgobj_ndxheader_s), (FAR uint8_t *)&objndx_hdr); @@ -1532,7 +1543,9 @@ void spiffs_fobj_event(FAR struct spiffs_s *fs, fobj != NULL; fobj = next) { - /* Set up for the next time through the loop (in case fobj is deleted) */ + /* Set up for the next time through the loop (in case fobj is + * deleted) + */ next = (FAR struct spiffs_file_s *)dq_next((FAR dq_entry_t *)fobj); @@ -1549,7 +1562,8 @@ void spiffs_fobj_event(FAR struct spiffs_s *fs, if (ev != SPIFFS_EV_NDXDEL) { - finfo("Setting objid=%d (offset=%d) objhdr_pgndx to %04x size=%d\n", + finfo("Setting objid=%d (offset=%d) objhdr_pgndx " + "to %04x size=%d\n", fobj->objid, fobj->offset, new_pgndx, new_size); fobj->objhdr_pgndx = new_pgndx; @@ -1581,7 +1595,8 @@ void spiffs_fobj_event(FAR struct spiffs_s *fs, if (fobj->cache_page && fobj->cache_page->offset > act_new_size + 1) { - spiffs_cacheinfo("File truncated, dropping cache page=%d, " + spiffs_cacheinfo("File truncated, " + "dropping cache page=%d, " "no writeback\n", fobj->cache_page->cpndx); @@ -1662,7 +1677,8 @@ int spiffs_fobj_open_bypage(FAR struct spiffs_s *fs, int16_t pgndx, physoff = SPIFFS_BLOCK_TO_PADDR(fs, blkndx) + entry * sizeof(int16_t); ret = spiffs_cache_read(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_READ, 0, - physoff, sizeof(int16_t), (FAR uint8_t *)&objid); + physoff, sizeof(int16_t), + (FAR uint8_t *)&objid); /* Fill in the parts of the open file structure known only to the core * logic. @@ -1775,21 +1791,23 @@ ssize_t spiffs_fobj_append(FAR struct spiffs_s *fs, * 0xffffffff) */ - ret = spiffs_page_index_check(fs, fobj, cur_objndx_pgndx, 0); + ret = spiffs_page_index_check(fs, fobj, + cur_objndx_pgndx, 0); if (ret < 0) { - ferr("ERROR: spiffs_page_index_check() failed: %d\n", - ret); + ferr("ERROR: spiffs_page_index_check() failed: " + "%d\n", + ret); return ret; } ret = spiffs_cache_write(fs, - SPIFFS_OP_T_OBJNDX | SPIFFS_OP_C_UPDT, - fobj->objid, - SPIFFS_PAGE_TO_PADDR(fs, cur_objndx_pgndx), - SPIFFS_GEO_PAGE_SIZE(fs), - fs->work); + SPIFFS_OP_T_OBJNDX | SPIFFS_OP_C_UPDT, + fobj->objid, + SPIFFS_PAGE_TO_PADDR(fs, cur_objndx_pgndx), + SPIFFS_GEO_PAGE_SIZE(fs), + fs->work); if (ret < 0) { ferr("ERROR: spiffs_cache_write() failed: %d\n", @@ -1808,12 +1826,14 @@ ssize_t spiffs_fobj_append(FAR struct spiffs_s *fs, &new_objhdr_page); if (ret < 0) { - ferr("ERROR: spiffs_fobj_update_ndxhdr() failed: %d\n", + ferr("ERROR: spiffs_fobj_update_ndxhdr() failed: " + "%d\n", ret); return ret; } - finfo("objid=%04x store new objhdr, %04x:%04x, nwritten=%d\n", + finfo("objid=%04x store new objhdr, " + "%04x:%04x, nwritten=%d\n", fobj->objid, new_objhdr_page, 0, nwritten); } } @@ -1825,23 +1845,26 @@ ssize_t spiffs_fobj_append(FAR struct spiffs_s *fs, prev_objndx_spndx); if (ret < 0) { - ferr("ERROR: spiffs_page_index_check() failed: %d\n", ret); + ferr("ERROR: spiffs_page_index_check() failed: " + "%d\n", ret); return ret; } ret = spiffs_cache_write(fs, - SPIFFS_OP_T_OBJNDX | SPIFFS_OP_C_UPDT, - fobj->objid, - SPIFFS_PAGE_TO_PADDR(fs, cur_objndx_pgndx), - SPIFFS_GEO_PAGE_SIZE(fs), - fs->work); + SPIFFS_OP_T_OBJNDX | SPIFFS_OP_C_UPDT, + fobj->objid, + SPIFFS_PAGE_TO_PADDR(fs, cur_objndx_pgndx), + SPIFFS_GEO_PAGE_SIZE(fs), + fs->work); if (ret < 0) { ferr("ERROR: spiffs_cache_write() failed: %d\n", ret); return ret; } - spiffs_fobj_event(fs, (FAR struct spiffs_page_objndx_s *)fs->work, + spiffs_fobj_event(fs, + (FAR struct spiffs_page_objndx_s *) + fs->work, SPIFFS_EV_NDXUPD, fobj->objid, objndx->phdr.spndx, cur_objndx_pgndx, 0); @@ -1881,7 +1904,8 @@ ssize_t spiffs_fobj_append(FAR struct spiffs_s *fs, ret = spiffs_cache_read(fs, SPIFFS_OP_T_OBJNDX | SPIFFS_OP_C_READ, fobj->objid, - SPIFFS_PAGE_TO_PADDR(fs, cur_objndx_pgndx), + SPIFFS_PAGE_TO_PADDR(fs, + cur_objndx_pgndx), SPIFFS_GEO_PAGE_SIZE(fs), fs->work); if (ret < 0) { @@ -1915,7 +1939,8 @@ ssize_t spiffs_fobj_append(FAR struct spiffs_s *fs, 0xff & ~(SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_INDEX); ret = spiffs_page_allocate_data(fs, - fobj->objid | SPIFFS_OBJID_NDXFLAG, + fobj->objid | + SPIFFS_OBJID_NDXFLAG, &phdr, 0, 0, 0, 1, &cur_objndx_pgndx); if (ret < 0) @@ -1928,14 +1953,17 @@ ssize_t spiffs_fobj_append(FAR struct spiffs_s *fs, /* Quick "load" of new object index page */ memset(fs->work, 0xff, SPIFFS_GEO_PAGE_SIZE(fs)); - memcpy(fs->work, &phdr, sizeof(struct spiffs_page_header_s)); + memcpy(fs->work, &phdr, + sizeof(struct spiffs_page_header_s)); spiffs_fobj_event(fs, - (FAR struct spiffs_page_objndx_s *)fs->work, + (FAR struct spiffs_page_objndx_s *) + fs->work, SPIFFS_EV_NDXNEW, fobj->objid, cur_objndx_spndx, cur_objndx_pgndx, 0); - finfo("objid=%04x create objndx page, %04x:%04x, nwritten=%d\n", + finfo("objid=%04x create objndx page, " + "%04x:%04x, nwritten=%d\n", fobj->objid, cur_objndx_pgndx, cur_objndx_spndx, nwritten); } @@ -1956,22 +1984,26 @@ ssize_t spiffs_fobj_append(FAR struct spiffs_s *fs, { ret = spiffs_objlu_find_id_and_span(fs, - fobj->objid | SPIFFS_OBJID_NDXFLAG, + fobj->objid | + SPIFFS_OBJID_NDXFLAG, cur_objndx_spndx, 0, &pgndx); if (ret < 0) { - ferr("ERROR: spiffs_objlu_find_id_and_span() failed: %d\n", + ferr("ERROR: spiffs_objlu_find_id_and_span() " + "failed: %d\n", ret); return ret; } } - finfo("objid=%04x found object index at page=%04x [fobj size=%d]\n", + finfo("objid=%04x found object index at " + "page=%04x [fobj size=%d]\n", fobj->objid, pgndx, fobj->size); ret = spiffs_cache_read(fs, - SPIFFS_OP_T_OBJNDX | SPIFFS_OP_C_READ, + SPIFFS_OP_T_OBJNDX | + SPIFFS_OP_C_READ, fobj->objid, SPIFFS_PAGE_TO_PADDR(fs, pgndx), SPIFFS_GEO_PAGE_SIZE(fs), @@ -2016,7 +2048,8 @@ ssize_t spiffs_fobj_append(FAR struct spiffs_s *fs, phdr.flags = 0xff & ~(SPIFFS_PH_FLAG_FINAL); /* Finalize immediately */ ret = spiffs_page_allocate_data(fs, - fobj->objid & ~SPIFFS_OBJID_NDXFLAG, + fobj->objid & + ~SPIFFS_OBJID_NDXFLAG, &phdr, &data[nwritten], to_write, page_offs, 1, &data_page); @@ -2057,10 +2090,12 @@ ssize_t spiffs_fobj_append(FAR struct spiffs_s *fs, ret = spiffs_cache_write(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, fobj->objid, SPIFFS_PAGE_TO_PADDR(fs, data_page) + - sizeof(struct spiffs_page_header_s) + page_offs, + sizeof(struct spiffs_page_header_s) + + page_offs, to_write, &data[nwritten]); - finfo("objid=%04x store to existing data page, %04x:%04x offset=%d, " + finfo("objid=%04x store to existing data page, " + "%04x:%04x offset=%d, " "len=%d, nwritten=%d\n", fobj->objid, data_page, data_spndx, page_offs, to_write, nwritten); @@ -2071,14 +2106,17 @@ ssize_t spiffs_fobj_append(FAR struct spiffs_s *fs, break; } - /* Update memory representation of object index page with new data page */ + /* Update memory representation of object index page with new data + * page + */ if (cur_objndx_spndx == 0) { /* Update object index header page */ ((FAR int16_t *)((FAR uint8_t *) objhdr + - sizeof(struct spiffs_pgobj_ndxheader_s)))[data_spndx] = data_page; + sizeof(struct spiffs_pgobj_ndxheader_s)))[data_spndx] = + data_page; finfo("objid=%04x wrote page %04x to objhdr entry=%04x in mem\n", fobj->objid, data_page, data_spndx); @@ -2170,11 +2208,14 @@ ssize_t spiffs_fobj_append(FAR struct spiffs_s *fs, if (offset == 0) { - /* Wrote to empty object - simply update size and write whole page */ + /* Wrote to empty object - simply update size and write whole + * page + */ objhdr->size = offset + nwritten; - finfo("objid=%04x store fresh objhdr page, %04x:%04x, nwritten=%d\n", + finfo("objid=%04x store fresh objhdr page, " + "%04x:%04x, nwritten=%d\n", fobj->objid, cur_objndx_pgndx, cur_objndx_spndx, nwritten); ret2 = spiffs_page_index_check(fs, fobj, cur_objndx_pgndx, @@ -2188,7 +2229,8 @@ ssize_t spiffs_fobj_append(FAR struct spiffs_s *fs, ret2 = spiffs_cache_write(fs, SPIFFS_OP_T_OBJNDX | SPIFFS_OP_C_UPDT, fobj->objid, - SPIFFS_PAGE_TO_PADDR(fs, cur_objndx_pgndx), + SPIFFS_PAGE_TO_PADDR(fs, + cur_objndx_pgndx), SPIFFS_GEO_PAGE_SIZE(fs), fs->work); if (ret2 < 0) { @@ -2307,7 +2349,8 @@ ssize_t spiffs_fobj_modify(FAR struct spiffs_s *fs, fs->work, 0, 0, &new_objhdr_pgndx); - finfo("Store modified objhdr page, %04x:%04x, nwritten=%d\n", + finfo("Store modified objhdr page, " + "%04x:%04x, nwritten=%d\n", new_objhdr_pgndx, 0, nwritten); if (ret < 0) @@ -2327,11 +2370,13 @@ ssize_t spiffs_fobj_modify(FAR struct spiffs_s *fs, prev_objndx_spndx); if (ret < 0) { - ferr("ERROR: spiffs_page_index_check() failed: %d\n", ret); + ferr("ERROR: spiffs_page_index_check() failed: %d\n", + ret); return ret; } - ret = spiffs_page_move(fs, fobj->objid, (FAR uint8_t *)objndx, + ret = spiffs_page_move(fs, fobj->objid, + (FAR uint8_t *)objndx, fobj->objid, 0, cur_objndx_pgndx, &new_objndx_pgndx); @@ -2346,10 +2391,11 @@ ssize_t spiffs_fobj_modify(FAR struct spiffs_s *fs, } spiffs_fobj_event(fs, - (FAR struct spiffs_page_objndx_s *)objndx, - SPIFFS_EV_NDXUPD, fobj->objid, - objndx->phdr.spndx, new_objndx_pgndx, - 0); + (FAR struct spiffs_page_objndx_s *) + objndx, + SPIFFS_EV_NDXUPD, fobj->objid, + objndx->phdr.spndx, new_objndx_pgndx, + 0); } } @@ -2365,7 +2411,8 @@ ssize_t spiffs_fobj_modify(FAR struct spiffs_s *fs, ret = spiffs_cache_read(fs, SPIFFS_OP_T_OBJNDX | SPIFFS_OP_C_READ, fobj->objid, - SPIFFS_PAGE_TO_PADDR(fs, cur_objndx_pgndx), + SPIFFS_PAGE_TO_PADDR(fs, + cur_objndx_pgndx), SPIFFS_GEO_PAGE_SIZE(fs), fs->work); if (ret < 0) { @@ -2397,12 +2444,14 @@ ssize_t spiffs_fobj_modify(FAR struct spiffs_s *fs, { ret = spiffs_objlu_find_id_and_span(fs, - fobj->objid | SPIFFS_OBJID_NDXFLAG, + fobj->objid | + SPIFFS_OBJID_NDXFLAG, cur_objndx_spndx, 0, &pgndx); if (ret < 0) { - ferr("ERROR: spiffs_objlu_find_id_and_span() failed: %d\n", + ferr("ERROR: spiffs_objlu_find_id_and_span() failed: " + "%d\n", ret); return ret; } @@ -2469,17 +2518,20 @@ ssize_t spiffs_fobj_modify(FAR struct spiffs_s *fs, /* A full page, allocate and write a new page of data */ ret = spiffs_page_allocate_data(fs, - fobj->objid & ~SPIFFS_OBJID_NDXFLAG, + fobj->objid & + ~SPIFFS_OBJID_NDXFLAG, &phdr, &data[nwritten], to_write, page_offs, 1, &data_pgndx); - finfo("Store new data page, %04x:%04x offset=%d, len=%d, nwritten=%d\n", + finfo("Store new data page, %04x:%04x offset=%d, " + "len=%d, nwritten=%d\n", data_pgndx, data_spndx, page_offs, to_write, nwritten); } else { /* Write to existing page, allocate new and copy unmodified data */ - ret = spiffs_page_data_check(fs, fobj, orig_data_pgndx, data_spndx); + ret = spiffs_page_data_check(fs, fobj, orig_data_pgndx, + data_spndx); if (ret < 0) { ferr("ERROR: spiffs_page_data_check() failed: %d\n", ret); @@ -2487,7 +2539,8 @@ ssize_t spiffs_fobj_modify(FAR struct spiffs_s *fs, } ret = spiffs_page_allocate_data(fs, - fobj->objid & ~SPIFFS_OBJID_NDXFLAG, + fobj->objid & + ~SPIFFS_OBJID_NDXFLAG, &phdr, 0, 0, 0, 0, &data_pgndx); if (ret < 0) { @@ -2504,8 +2557,10 @@ ssize_t spiffs_fobj_modify(FAR struct spiffs_s *fs, ret = spiffs_phys_cpy(fs, fobj->objid, SPIFFS_PAGE_TO_PADDR(fs, data_pgndx) + sizeof(struct spiffs_page_header_s), - SPIFFS_PAGE_TO_PADDR(fs, orig_data_pgndx) + - sizeof(struct spiffs_page_header_s), page_offs); + SPIFFS_PAGE_TO_PADDR(fs, + orig_data_pgndx) + + sizeof(struct spiffs_page_header_s), + page_offs); if (ret < 0) { ferr("ERROR: spiffs_phys_cpy() failed: %d\n", ret); @@ -2520,10 +2575,12 @@ ssize_t spiffs_fobj_modify(FAR struct spiffs_s *fs, ret = spiffs_phys_cpy(fs, fobj->objid, SPIFFS_PAGE_TO_PADDR(fs, data_pgndx) + - sizeof(struct spiffs_page_header_s) + page_offs + + sizeof(struct spiffs_page_header_s) + + page_offs + to_write, SPIFFS_PAGE_TO_PADDR(fs, orig_data_pgndx) - + sizeof(struct spiffs_page_header_s) + page_offs + + + sizeof(struct spiffs_page_header_s) + + page_offs + to_write, SPIFFS_DATA_PAGE_SIZE(fs) - (page_offs + to_write)); @@ -2535,8 +2592,10 @@ ssize_t spiffs_fobj_modify(FAR struct spiffs_s *fs, } ret = spiffs_cache_write(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, - fobj->objid, SPIFFS_PAGE_TO_PADDR(fs, data_pgndx) + - sizeof(struct spiffs_page_header_s) + page_offs, + fobj->objid, + SPIFFS_PAGE_TO_PADDR(fs, data_pgndx) + + sizeof(struct spiffs_page_header_s) + + page_offs, to_write, &data[nwritten]); if (ret < 0) { @@ -2548,8 +2607,10 @@ ssize_t spiffs_fobj_modify(FAR struct spiffs_s *fs, ret = spiffs_cache_write(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, fobj->objid, SPIFFS_PAGE_TO_PADDR(fs, data_pgndx) + - offsetof(struct spiffs_page_header_s, flags), - sizeof(uint8_t), (FAR uint8_t *)&phdr.flags); + offsetof(struct spiffs_page_header_s, + flags), + sizeof(uint8_t), + (FAR uint8_t *)&phdr.flags); if (ret < 0) { ferr("ERROR: spiffs_cache_write() failed: %d\n", ret); @@ -2571,14 +2632,17 @@ ssize_t spiffs_fobj_modify(FAR struct spiffs_s *fs, break; } - /* Update memory representation of object index page with new data page */ + /* Update memory representation of object index page with new data + * page + */ if (cur_objndx_spndx == 0) { /* Update object index header page */ ((FAR int16_t *)((FAR uint8_t *)objhdr + - sizeof(struct spiffs_pgobj_ndxheader_s)))[data_spndx] = data_pgndx; + sizeof(struct spiffs_pgobj_ndxheader_s)))[data_spndx] = + data_pgndx; finfo("Wrote page %04x to objhdr entry=%04x in mem\n", data_pgndx, data_spndx); @@ -2588,8 +2652,8 @@ ssize_t spiffs_fobj_modify(FAR struct spiffs_s *fs, /* Update object index page */ ((FAR int16_t *)((FAR uint8_t *)objndx + - sizeof(struct spiffs_page_objndx_s)))[SPIFFS_OBJNDX_ENTRY(fs, data_spndx)] = - data_pgndx; + sizeof(struct spiffs_page_objndx_s))) + [SPIFFS_OBJNDX_ENTRY(fs, data_spndx)] = data_pgndx; finfo("Wrote page %04x to objndx entry %04x in mem\n", data_pgndx, (int16_t)SPIFFS_OBJNDX_ENTRY(fs, data_spndx)); @@ -2736,7 +2800,8 @@ int spiffs_fobj_truncate(FAR struct spiffs_s *fs, * remove the file, then there is nothing to do. */ - if ((fobj->size == SPIFFS_UNDEFINED_LEN || fobj->size == 0) && !remove_full) + if ((fobj->size == SPIFFS_UNDEFINED_LEN || fobj->size == 0) && + !remove_full) { /* Do nothing */ @@ -2775,7 +2840,9 @@ int spiffs_fobj_truncate(FAR struct spiffs_s *fs, cur_size = fobj->size; } - /* Before truncating, check if object is to be fully removed and mark this */ + /* Before truncating, check if object is to be fully removed and mark + * this + */ if (remove_full && new_size == 0) { @@ -2856,7 +2923,8 @@ int spiffs_fobj_truncate(FAR struct spiffs_s *fs, &new_objhdr_pgndx); if (ret < 0) { - ferr("ERROR: spiffs_fobj_update_ndxhdr() failed: %d\n", + ferr("ERROR: spiffs_fobj_update_ndxhdr() failed: " + "%d\n", ret); return ret; } @@ -2875,7 +2943,8 @@ int spiffs_fobj_truncate(FAR struct spiffs_s *fs, else { ret = spiffs_objlu_find_id_and_span(fs, - fobj->objid | SPIFFS_OBJID_NDXFLAG, + fobj->objid | + SPIFFS_OBJID_NDXFLAG, cur_objndx_spndx, 0, &objndx_pgndx); if (ret < 0) @@ -2995,8 +3064,8 @@ int spiffs_fobj_truncate(FAR struct spiffs_s *fs, /* Delete last page, partially */ - bytes_to_remove = - SPIFFS_DATA_PAGE_SIZE(fs) - (new_size % SPIFFS_DATA_PAGE_SIZE(fs)); + bytes_to_remove = SPIFFS_DATA_PAGE_SIZE(fs) - + (new_size % SPIFFS_DATA_PAGE_SIZE(fs)); finfo("Delete %d bytes from data page=%04x for data spndx=%04x, " "cur_size=%d\n", @@ -3016,7 +3085,8 @@ int spiffs_fobj_truncate(FAR struct spiffs_s *fs, /* Allocate new page and copy unmodified data */ ret = spiffs_page_allocate_data(fs, - fobj->objid & ~SPIFFS_OBJID_NDXFLAG, + fobj->objid & + ~SPIFFS_OBJID_NDXFLAG, &phdr, 0, 0, 0, 0, &new_data_pgndx); if (ret < 0) @@ -3050,8 +3120,10 @@ int spiffs_fobj_truncate(FAR struct spiffs_s *fs, ret = spiffs_cache_write(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, fobj->objid, SPIFFS_PAGE_TO_PADDR(fs, new_data_pgndx) + - offsetof(struct spiffs_page_header_s, flags), - sizeof(uint8_t), (FAR uint8_t *)&phdr.flags); + offsetof(struct spiffs_page_header_s, + flags), + sizeof(uint8_t), + (FAR uint8_t *)&phdr.flags); if (ret < 0) { ferr("ERROR: spiffs_cache_write() failed: %d\n", ret); @@ -3274,12 +3346,14 @@ ssize_t spiffs_object_read(FAR struct spiffs_s *fs, { ret = spiffs_objlu_find_id_and_span(fs, - fobj->objid | SPIFFS_OBJID_NDXFLAG, + fobj->objid | + SPIFFS_OBJID_NDXFLAG, cur_objndx_spndx, 0, &objndx_pgndx); if (ret < 0) { - ferr("ERROR: spiffs_objlu_find_id_and_span() failed: %d\n", + ferr("ERROR: spiffs_objlu_find_id_and_span() failed: " + "%d\n", ret); return ret; } @@ -3345,7 +3419,8 @@ ssize_t spiffs_object_read(FAR struct spiffs_s *fs, len_to_read = MIN(len_to_read, fobj->size); - finfo("Read offset=%d rd=%d data spndx=%d is data_pgndx=%d addr=%p\n", + finfo("Read offset=%d rd=%d data spndx=%d is " + "data_pgndx=%d addr=%" PRIu32 "\n", cur_offset, len_to_read, data_spndx, data_pgndx, (SPIFFS_PAGE_TO_PADDR(fs, data_pgndx) + sizeof(struct spiffs_page_header_s) + @@ -3405,7 +3480,8 @@ int spiffs_objlu_find_free_objid(FAR struct spiffs_s *fs, int16_t *objid, int16_t free_objid; int ret = OK; - max_objects = (SPIFFS_GEO_BLOCK_COUNT(fs) * SPIFFS_OBJ_LOOKUP_MAX_ENTRIES(fs)) / 2; + max_objects = (SPIFFS_GEO_BLOCK_COUNT(fs) * + SPIFFS_OBJ_LOOKUP_MAX_ENTRIES(fs)) / 2; free_objid = SPIFFS_OBJID_FREE; state.min_objid = 1; @@ -3434,9 +3510,9 @@ int spiffs_objlu_find_free_objid(FAR struct spiffs_s *fs, int16_t *objid, memset(fs->work, 0, SPIFFS_GEO_PAGE_SIZE(fs)); ret = spiffs_foreach_objlu(fs, 0, 0, 0, 0, - spiffs_objlu_find_free_objid_bitmap_callback, - conflicting_name, &state.min_objid, - 0, 0); + spiffs_objlu_find_free_objid_bitmap_callback, + conflicting_name, &state.min_objid, + 0, 0); if (ret == SPIFFS_VIS_END) { ret = OK; @@ -3521,7 +3597,9 @@ int spiffs_objlu_find_free_objid(FAR struct spiffs_s *fs, int16_t *objid, if (min_count == 0) { - /* No objid in this range, skip compacting and use directly */ + /* No objid in this range, skip compacting and use + * directly + */ *objid = min_i * state.compaction + state.min_objid; return OK; @@ -3555,17 +3633,16 @@ int spiffs_objlu_find_free_objid(FAR struct spiffs_s *fs, int16_t *objid, * byte */ - state.compaction = - (state.max_objid - - state.min_objid) / ((SPIFFS_GEO_PAGE_SIZE(fs) / sizeof(uint8_t))); + state.compaction = (state.max_objid - state.min_objid) / + ((SPIFFS_GEO_PAGE_SIZE(fs) / sizeof(uint8_t))); finfo("COMP min=%04x max=%04x compact=%d\n", state.min_objid, state.max_objid, state.compaction); memset(fs->work, 0, SPIFFS_GEO_PAGE_SIZE(fs)); ret = spiffs_foreach_objlu(fs, 0, 0, 0, 0, - spiffs_objlu_find_free_objid_compact_callback, - &state, 0, 0, 0); + spiffs_objlu_find_free_objid_compact_callback, + &state, 0, 0, 0); if (ret == SPIFFS_VIS_END) { ret = OK; diff --git a/fs/spiffs/src/spiffs_mtd.c b/fs/spiffs/src/spiffs_mtd.c index 1a3feb74bc6..ac2846ea726 100644 --- a/fs/spiffs/src/spiffs_mtd.c +++ b/fs/spiffs/src/spiffs_mtd.c @@ -471,7 +471,7 @@ ssize_t spiffs_mtd_erase(FAR struct spiffs_s *fs, off_t offset, size_t len) nerased = MTD_ERASE(fs->mtd, eblkstart, eblkend - eblkstart); if (nerased < 0) { - ferr("ERROR: MTD_ERASE() failed: %d\n"); + ferr("ERROR: MTD_ERASE() failed: %zd\n", nerased); return nerased; } diff --git a/fs/spiffs/src/spiffs_vfs.c b/fs/spiffs/src/spiffs_vfs.c index 9e262ac2d12..475c9c9c127 100644 --- a/fs/spiffs/src/spiffs_vfs.c +++ b/fs/spiffs/src/spiffs_vfs.c @@ -1838,7 +1838,7 @@ static int spiffs_rename(FAR struct inode *mountpt, &oldpgndx); if (ret < 0) { - fwarn("WARNING: spiffs_find_objhdr_pgndx failed: %d\n"); + fwarn("WARNING: spiffs_find_objhdr_pgndx failed: %d\n", ret); goto errout_with_lock; } diff --git a/fs/vfs/fs_epoll.c b/fs/vfs/fs_epoll.c index 4babda57c79..ef1b1fd9965 100644 --- a/fs/vfs/fs_epoll.c +++ b/fs/vfs/fs_epoll.c @@ -41,6 +41,7 @@ #include +#include #include #include #include @@ -165,7 +166,7 @@ int epoll_ctl(int epfd, int op, int fd, struct epoll_event *ev) switch (op) { case EPOLL_CTL_ADD: - finfo("%08x CTL ADD(%d): fd=%d ev=%08x\n", + finfo("%08x CTL ADD(%d): fd=%d ev=%08" PRIx32 "\n", epfd, eph->occupied, fd, ev->events); eph->data[eph->occupied] = ev->data; @@ -202,7 +203,7 @@ int epoll_ctl(int epfd, int op, int fd, struct epoll_event *ev) { int i; - finfo("%08x CTL MOD(%d): fd=%d ev=%08x\n", + finfo("%08x CTL MOD(%d): fd=%d ev=%08" PRIx32 "\n", epfd, eph->occupied, fd, ev->events); for (i = 0; i < eph->occupied; i++) diff --git a/fs/vfs/fs_fdopen.c b/fs/vfs/fs_fdopen.c index 295a3d59022..cace0ca49de 100644 --- a/fs/vfs/fs_fdopen.c +++ b/fs/vfs/fs_fdopen.c @@ -178,36 +178,61 @@ int fs_fdopen(int fd, int oflags, FAR struct tcb_s *tcb, goto errout; } + /* Get the stream list from the TCB */ + +#ifdef CONFIG_MM_KERNEL_HEAP + slist = tcb->group->tg_streamlist; +#else + slist = &tcb->group->tg_streamlist; +#endif + /* Allocate FILE structure */ -#ifdef CONFIG_STDIO_DISABLE_BUFFERING - stream = group_zalloc(tcb->group, sizeof(FILE)); - if (stream == NULL) + if (fd >= 3) { - ret = -ENOMEM; - goto errout; + stream = group_zalloc(tcb->group, sizeof(FILE)); + if (stream == NULL) + { + ret = -ENOMEM; + goto errout; + } + + /* Add FILE structure to the stream list */ + + ret = nxsem_wait(&slist->sl_sem); + if (ret < 0) + { + group_free(tcb->group, stream); + goto errout; + } + + if (slist->sl_tail) + { + slist->sl_tail->fs_next = stream; + slist->sl_tail = stream; + } + else + { + slist->sl_head = stream; + slist->sl_tail = stream; + } + + nxsem_post(&slist->sl_sem); + + /* Initialize the semaphore the manages access to the buffer */ + + lib_sem_initialize(stream); } -#else - stream = group_malloc(tcb->group, sizeof(FILE) + - CONFIG_STDIO_BUFFER_SIZE); - if (stream == NULL) + else { - ret = -ENOMEM; - goto errout; + stream = &slist->sl_std[fd]; } - /* Zero the structure */ - - memset(stream, 0, sizeof(FILE)); - - /* Initialize the semaphore the manages access to the buffer */ - - lib_sem_initialize(stream); - +#ifndef CONFIG_STDIO_DISABLE_BUFFERING #if CONFIG_STDIO_BUFFER_SIZE > 0 /* Set up pointers */ - stream->fs_bufstart = (FAR unsigned char *)(stream + 1); + stream->fs_bufstart = stream->fs_buffer; stream->fs_bufend = &stream->fs_bufstart[CONFIG_STDIO_BUFFER_SIZE]; stream->fs_bufpos = stream->fs_bufstart; stream->fs_bufread = stream->fs_bufstart; @@ -229,34 +254,6 @@ int fs_fdopen(int fd, int oflags, FAR struct tcb_s *tcb, stream->fs_fd = fd; stream->fs_oflags = oflags; - /* Get the stream list from the TCB */ - -#ifdef CONFIG_MM_KERNEL_HEAP - slist = tcb->group->tg_streamlist; -#else - slist = &tcb->group->tg_streamlist; -#endif - - /* Add FILE structure to the stream list */ - - ret = nxsem_wait(&slist->sl_sem); - if (ret < 0) - { - goto errout_with_mem; - } - - if (slist->sl_tail) - { - slist->sl_tail->fs_next = stream; - slist->sl_tail = stream; - } - else - { - slist->sl_head = stream; - slist->sl_tail = stream; - } - - nxsem_post(&slist->sl_sem); if (filep != NULL) { *filep = stream; @@ -264,9 +261,6 @@ int fs_fdopen(int fd, int oflags, FAR struct tcb_s *tcb, return OK; -errout_with_mem: - group_free(tcb->group, stream); - errout: if (filep != NULL) { diff --git a/graphics/Makefile b/graphics/Makefile index 9a733beb618..5eda6b40774 100644 --- a/graphics/Makefile +++ b/graphics/Makefile @@ -124,8 +124,12 @@ $(BIN): $(OBJS) mklibgraphics: $(BIN) +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) + .depend: gensources Makefile $(SRCS) $(TOPDIR)$(DELIM).config - $(Q) $(MKDEP) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile $(Q) touch $@ depend: .depend diff --git a/graphics/nxmu/nxmu_server.c b/graphics/nxmu/nxmu_server.c index 40c9f06cfef..fab4fde8f14 100644 --- a/graphics/nxmu/nxmu_server.c +++ b/graphics/nxmu/nxmu_server.c @@ -39,6 +39,7 @@ #include +#include #include #include #include @@ -70,7 +71,8 @@ static inline void nxmu_disconnect(FAR struct nxmu_conn_s *conn) outmsg.msgid = NX_CLIMSG_DISCONNECTED; - ret = nxmu_sendclient(conn, &outmsg, sizeof(struct nxclimsg_disconnected_s)); + ret = nxmu_sendclient(conn, &outmsg, + sizeof(struct nxclimsg_disconnected_s)); if (ret < 0) { gerr("ERROR: nxmu_sendclient failed: %d\n", ret); @@ -95,7 +97,9 @@ static inline void nxmu_connect(FAR struct nxmu_conn_s *conn) sprintf(mqname, NX_CLIENT_MQNAMEFMT, conn->cid); - /* Open the client MQ -- this should have already been created by the client */ + /* Open the client MQ -- this should have already been created by the + * client + */ conn->swrmq = mq_open(mqname, O_WRONLY); if (conn->swrmq == (mqd_t)-1) @@ -308,275 +312,307 @@ int nx_runinstance(FAR const char *mqname, FAR NX_DRIVERTYPE *dev) for (; ; ) { - /* Receive the next server message */ + /* Receive the next server message */ - nbytes = nxmq_receive(nxmu.conn.crdmq, buffer, NX_MXSVRMSGLEN, 0); - if (nbytes < 0) - { - if (nbytes != -EINTR) - { - gerr("ERROR: nxmq_receive() failed: %d\n", nbytes); - ret = nbytes; - goto errout; - } + nbytes = nxmq_receive(nxmu.conn.crdmq, buffer, NX_MXSVRMSGLEN, 0); + if (nbytes < 0) + { + if (nbytes != -EINTR) + { + gerr("ERROR: nxmq_receive() failed: %d\n", nbytes); + ret = nbytes; + goto errout; + } - continue; - } + continue; + } - /* Dispatch the message appropriately */ + /* Dispatch the message appropriately */ - DEBUGASSERT(nbytes >= sizeof(struct nxsvrmsg_releasebkgd_s)); - msg = (FAR struct nxsvrmsg_s *)buffer; + DEBUGASSERT(nbytes >= sizeof(struct nxsvrmsg_releasebkgd_s)); + msg = (FAR struct nxsvrmsg_s *)buffer; - ginfo("Received opcode=%d nbytes=%d\n", msg->msgid, nbytes); - switch (msg->msgid) - { - /* Messages sent from clients to the NX server *********************/ + ginfo("Received opcode=%" PRId32 " nbytes=%d\n", msg->msgid, nbytes); + switch (msg->msgid) + { + /* Messages sent from clients to the NX server ********************/ - case NX_SVRMSG_CONNECT: /* Establish connection with new NX server client */ - { - FAR struct nxsvrmsg_s *connmsg = (FAR struct nxsvrmsg_s *)buffer; - nxmu_connect(connmsg->conn); - } - break; + case NX_SVRMSG_CONNECT: /* Establish connection with new NX server client */ + { + FAR struct nxsvrmsg_s *connmsg = + (FAR struct nxsvrmsg_s *)buffer; + nxmu_connect(connmsg->conn); + } + break; - case NX_SVRMSG_DISCONNECT: /* Tear down connection with terminating client */ - { - FAR struct nxsvrmsg_s *disconnmsg = (FAR struct nxsvrmsg_s *)buffer; - nxmu_disconnect(disconnmsg->conn); - } - break; + case NX_SVRMSG_DISCONNECT: /* Tear down connection with terminating client */ + { + FAR struct nxsvrmsg_s *disconnmsg = + (FAR struct nxsvrmsg_s *)buffer; + nxmu_disconnect(disconnmsg->conn); + } + break; - case NX_SVRMSG_OPENWINDOW: /* Create a new window */ - { - FAR struct nxsvrmsg_openwindow_s *openmsg = (FAR struct nxsvrmsg_openwindow_s *)buffer; - nxmu_openwindow(&nxmu.be, openmsg->wnd); - } - break; + case NX_SVRMSG_OPENWINDOW: /* Create a new window */ + { + FAR struct nxsvrmsg_openwindow_s *openmsg = + (FAR struct nxsvrmsg_openwindow_s *)buffer; + nxmu_openwindow(&nxmu.be, openmsg->wnd); + } + break; - case NX_SVRMSG_CLOSEWINDOW: /* Close an existing window */ - { - FAR struct nxsvrmsg_closewindow_s *closemsg = (FAR struct nxsvrmsg_closewindow_s *)buffer; - nxbe_closewindow(closemsg->wnd); - } - break; + case NX_SVRMSG_CLOSEWINDOW: /* Close an existing window */ + { + FAR struct nxsvrmsg_closewindow_s *closemsg = + (FAR struct nxsvrmsg_closewindow_s *)buffer; + nxbe_closewindow(closemsg->wnd); + } + break; - case NX_SVRMSG_BLOCKED: /* Block messages to a window */ - { - FAR struct nxsvrmsg_blocked_s *blocked = (FAR struct nxsvrmsg_blocked_s *)buffer; - nxmu_event(blocked->wnd, NXEVENT_BLOCKED, blocked->arg); - } - break; + case NX_SVRMSG_BLOCKED: /* Block messages to a window */ + { + FAR struct nxsvrmsg_blocked_s *blocked = + (FAR struct nxsvrmsg_blocked_s *)buffer; + nxmu_event(blocked->wnd, NXEVENT_BLOCKED, blocked->arg); + } + break; - case NX_SVRMSG_SYNCH: /* Synchronization request */ - { - FAR struct nxsvrmsg_synch_s *synch = (FAR struct nxsvrmsg_synch_s *)buffer; - nxmu_event(synch->wnd, NXEVENT_SYNCHED, synch->arg); - } - break; + case NX_SVRMSG_SYNCH: /* Synchronization request */ + { + FAR struct nxsvrmsg_synch_s *synch = + (FAR struct nxsvrmsg_synch_s *)buffer; + nxmu_event(synch->wnd, NXEVENT_SYNCHED, synch->arg); + } + break; #if defined(CONFIG_NX_SWCURSOR) || defined(CONFIG_NX_HWCURSOR) - case NX_SVRMSG_CURSOR_ENABLE: /* Enable/disable cursor */ - { - FAR struct nxsvrmsg_curenable_s *enabmsg = (FAR struct nxsvrmsg_curenable_s *)buffer; - nxbe_cursor_enable(&nxmu.be, enabmsg->enable); - } - break; + case NX_SVRMSG_CURSOR_ENABLE: /* Enable/disable cursor */ + { + FAR struct nxsvrmsg_curenable_s *enabmsg = + (FAR struct nxsvrmsg_curenable_s *)buffer; + nxbe_cursor_enable(&nxmu.be, enabmsg->enable); + } + break; #if defined(CONFIG_NX_HWCURSORIMAGE) || defined(CONFIG_NX_SWCURSOR) - case NX_SVRMSG_CURSOR_IMAGE: /* Set cursor image */ - { - FAR struct nxsvrmsg_curimage_s *imgmsg = (FAR struct nxsvrmsg_curimage_s *)buffer; - nxbe_cursor_setimage(&nxmu.be, &imgmsg->image); - } - break; + case NX_SVRMSG_CURSOR_IMAGE: /* Set cursor image */ + { + FAR struct nxsvrmsg_curimage_s *imgmsg = + (FAR struct nxsvrmsg_curimage_s *)buffer; + nxbe_cursor_setimage(&nxmu.be, &imgmsg->image); + } + break; #endif - case NX_SVRMSG_CURSOR_SETPOS: /* Set cursor position */ - { - FAR struct nxsvrmsg_curpos_s *posmsg = (FAR struct nxsvrmsg_curpos_s *)buffer; - nxbe_cursor_setposition(&nxmu.be, &posmsg->pos); - } - break; + case NX_SVRMSG_CURSOR_SETPOS: /* Set cursor position */ + { + FAR struct nxsvrmsg_curpos_s *posmsg = + (FAR struct nxsvrmsg_curpos_s *)buffer; + nxbe_cursor_setposition(&nxmu.be, &posmsg->pos); + } + break; #endif - case NX_SVRMSG_REQUESTBKGD: /* Give access to the background window */ - { - FAR struct nxsvrmsg_requestbkgd_s *rqbgmsg = (FAR struct nxsvrmsg_requestbkgd_s *)buffer; - nxmu_requestbkgd(rqbgmsg->conn, &nxmu.be, rqbgmsg->cb, rqbgmsg->arg); - } - break; + case NX_SVRMSG_REQUESTBKGD: /* Give access to the background window */ + { + FAR struct nxsvrmsg_requestbkgd_s *rqbgmsg = + (FAR struct nxsvrmsg_requestbkgd_s *)buffer; + nxmu_requestbkgd(rqbgmsg->conn, &nxmu.be, rqbgmsg->cb, + rqbgmsg->arg); + } + break; - case NX_SVRMSG_RELEASEBKGD: /* End access to the background window */ - { - nxmu_releasebkgd(&nxmu); - } - break; + case NX_SVRMSG_RELEASEBKGD: /* End access to the background window */ + { + nxmu_releasebkgd(&nxmu); + } + break; - case NX_SVRMSG_SETPOSITION: /* Change window position */ - { - FAR struct nxsvrmsg_setposition_s *setposmsg = (FAR struct nxsvrmsg_setposition_s *)buffer; - nxbe_setposition(setposmsg->wnd, &setposmsg->pos); - } - break; + case NX_SVRMSG_SETPOSITION: /* Change window position */ + { + FAR struct nxsvrmsg_setposition_s *setposmsg = + (FAR struct nxsvrmsg_setposition_s *)buffer; + nxbe_setposition(setposmsg->wnd, &setposmsg->pos); + } + break; - case NX_SVRMSG_SETSIZE: /* Change window size */ - { - FAR struct nxsvrmsg_setsize_s *setsizemsg = (FAR struct nxsvrmsg_setsize_s *)buffer; - nxbe_setsize(setsizemsg->wnd, &setsizemsg->size); - } - break; + case NX_SVRMSG_SETSIZE: /* Change window size */ + { + FAR struct nxsvrmsg_setsize_s *setsizemsg = + (FAR struct nxsvrmsg_setsize_s *)buffer; + nxbe_setsize(setsizemsg->wnd, &setsizemsg->size); + } + break; - case NX_SVRMSG_GETPOSITION: /* Get the window size/position */ - { - FAR struct nxsvrmsg_getposition_s *getposmsg = (FAR struct nxsvrmsg_getposition_s *)buffer; - nxmu_reportposition(getposmsg->wnd); - } - break; + case NX_SVRMSG_GETPOSITION: /* Get the window size/position */ + { + FAR struct nxsvrmsg_getposition_s *getposmsg = + (FAR struct nxsvrmsg_getposition_s *)buffer; + nxmu_reportposition(getposmsg->wnd); + } + break; - case NX_SVRMSG_RAISE: /* Move the window to the top of the display */ - { - FAR struct nxsvrmsg_raise_s *raisemsg = (FAR struct nxsvrmsg_raise_s *)buffer; - nxbe_raise(raisemsg->wnd); - } - break; + case NX_SVRMSG_RAISE: /* Move the window to the top of the display */ + { + FAR struct nxsvrmsg_raise_s *raisemsg = + (FAR struct nxsvrmsg_raise_s *)buffer; + nxbe_raise(raisemsg->wnd); + } + break; - case NX_SVRMSG_LOWER: /* Lower the window to the bottom of the display */ - { - FAR struct nxsvrmsg_lower_s *lowermsg = (FAR struct nxsvrmsg_lower_s *)buffer; - nxbe_lower(lowermsg->wnd); - } - break; + case NX_SVRMSG_LOWER: /* Lower the window to the bottom of the display */ + { + FAR struct nxsvrmsg_lower_s *lowermsg = + (FAR struct nxsvrmsg_lower_s *)buffer; + nxbe_lower(lowermsg->wnd); + } + break; - case NX_SVRMSG_MODAL: /* Select/De-select window modal state */ - { - FAR struct nxsvrmsg_modal_s *modalmsg = (FAR struct nxsvrmsg_modal_s *)buffer; - nxbe_modal(modalmsg->wnd, modalmsg->modal); - } - break; + case NX_SVRMSG_MODAL: /* Select/De-select window modal state */ + { + FAR struct nxsvrmsg_modal_s *modalmsg = + (FAR struct nxsvrmsg_modal_s *)buffer; + nxbe_modal(modalmsg->wnd, modalmsg->modal); + } + break; - case NX_SVRMSG_SETVISIBILITY: /* Show or hide a window */ - { - FAR struct nxsvrmsg_setvisibility_s *vismsg = + case NX_SVRMSG_SETVISIBILITY: /* Show or hide a window */ + { + FAR struct nxsvrmsg_setvisibility_s *vismsg = (FAR struct nxsvrmsg_setvisibility_s *)buffer; - nxbe_setvisibility(vismsg->wnd, vismsg->hide); - } - break; + nxbe_setvisibility(vismsg->wnd, vismsg->hide); + } + break; - case NX_SVRMSG_SETPIXEL: /* Set a single pixel in the window with a color */ - { - FAR struct nxsvrmsg_setpixel_s *setmsg = (FAR struct nxsvrmsg_setpixel_s *)buffer; - nxbe_setpixel(setmsg->wnd, &setmsg->pos, setmsg->color); - } - break; + case NX_SVRMSG_SETPIXEL: /* Set a single pixel in the window with a color */ + { + FAR struct nxsvrmsg_setpixel_s *setmsg = + (FAR struct nxsvrmsg_setpixel_s *)buffer; + nxbe_setpixel(setmsg->wnd, &setmsg->pos, setmsg->color); + } + break; - case NX_SVRMSG_FILL: /* Fill a rectangular region in the window with a color */ - { - FAR struct nxsvrmsg_fill_s *fillmsg = (FAR struct nxsvrmsg_fill_s *)buffer; - nxbe_fill(fillmsg->wnd, &fillmsg->rect, fillmsg->color); - } - break; + case NX_SVRMSG_FILL: /* Fill a rectangular region in the window with a color */ + { + FAR struct nxsvrmsg_fill_s *fillmsg = + (FAR struct nxsvrmsg_fill_s *)buffer; + nxbe_fill(fillmsg->wnd, &fillmsg->rect, fillmsg->color); + } + break; - case NX_SVRMSG_GETRECTANGLE: /* Get a rectangular region from the window */ - { - FAR struct nxsvrmsg_getrectangle_s *getmsg = (FAR struct nxsvrmsg_getrectangle_s *)buffer; - nxbe_getrectangle(getmsg->wnd, &getmsg->rect, getmsg->plane, getmsg->dest, getmsg->deststride); + case NX_SVRMSG_GETRECTANGLE: /* Get a rectangular region from the window */ + { + FAR struct nxsvrmsg_getrectangle_s *getmsg = + (FAR struct nxsvrmsg_getrectangle_s *)buffer; + nxbe_getrectangle(getmsg->wnd, &getmsg->rect, getmsg->plane, + getmsg->dest, getmsg->deststride); - if (getmsg->sem_done) - { - nxsem_post(getmsg->sem_done); - } - } - break; + if (getmsg->sem_done) + { + nxsem_post(getmsg->sem_done); + } + } + break; - case NX_SVRMSG_FILLTRAP: /* Fill a trapezoidal region in the window with a color */ - { - FAR struct nxsvrmsg_filltrapezoid_s *trapmsg = (FAR struct nxsvrmsg_filltrapezoid_s *)buffer; - nxbe_filltrapezoid(trapmsg->wnd, &trapmsg->clip, &trapmsg->trap, trapmsg->color); - } - break; - case NX_SVRMSG_MOVE: /* Move a rectangular region within the window */ - { - FAR struct nxsvrmsg_move_s *movemsg = (FAR struct nxsvrmsg_move_s *)buffer; - nxbe_move(movemsg->wnd, &movemsg->rect, &movemsg->offset); - } - break; + case NX_SVRMSG_FILLTRAP: /* Fill a trapezoidal region in the window with a color */ + { + FAR struct nxsvrmsg_filltrapezoid_s *trapmsg = + (FAR struct nxsvrmsg_filltrapezoid_s *)buffer; + nxbe_filltrapezoid(trapmsg->wnd, &trapmsg->clip, + &trapmsg->trap, trapmsg->color); + } + break; - case NX_SVRMSG_BITMAP: /* Copy a rectangular bitmap into the window */ - { - FAR struct nxsvrmsg_bitmap_s *bmpmsg = (FAR struct nxsvrmsg_bitmap_s *)buffer; - nxbe_bitmap(bmpmsg->wnd, &bmpmsg->dest, bmpmsg->src, &bmpmsg->origin, bmpmsg->stride); + case NX_SVRMSG_MOVE: /* Move a rectangular region within the window */ + { + FAR struct nxsvrmsg_move_s *movemsg = + (FAR struct nxsvrmsg_move_s *)buffer; + nxbe_move(movemsg->wnd, &movemsg->rect, &movemsg->offset); + } + break; - if (bmpmsg->sem_done) - { - nxsem_post(bmpmsg->sem_done); - } - } - break; + case NX_SVRMSG_BITMAP: /* Copy a rectangular bitmap into the window */ + { + FAR struct nxsvrmsg_bitmap_s *bmpmsg = + (FAR struct nxsvrmsg_bitmap_s *)buffer; + nxbe_bitmap(bmpmsg->wnd, &bmpmsg->dest, bmpmsg->src, + &bmpmsg->origin, bmpmsg->stride); - case NX_SVRMSG_SETBGCOLOR: /* Set the color of the background */ - { - FAR struct nxsvrmsg_setbgcolor_s *bgcolormsg = - (FAR struct nxsvrmsg_setbgcolor_s *)buffer; + if (bmpmsg->sem_done) + { + nxsem_post(bmpmsg->sem_done); + } + } + break; - /* Has the background color changed? */ + case NX_SVRMSG_SETBGCOLOR: /* Set the color of the background */ + { + FAR struct nxsvrmsg_setbgcolor_s *bgcolormsg = + (FAR struct nxsvrmsg_setbgcolor_s *)buffer; - if (!nxgl_colorcmp(nxmu.be.bgcolor, bgcolormsg->color)) - { - /* Yes.. fill the background */ + /* Has the background color changed? */ - nxgl_colorcopy(nxmu.be.bgcolor, bgcolormsg->color); - nxbe_fill(&nxmu.be.bkgd, &nxmu.be.bkgd.bounds, bgcolormsg->color); - } - } - break; + if (!nxgl_colorcmp(nxmu.be.bgcolor, bgcolormsg->color)) + { + /* Yes.. fill the background */ + + nxgl_colorcopy(nxmu.be.bgcolor, bgcolormsg->color); + nxbe_fill(&nxmu.be.bkgd, &nxmu.be.bkgd.bounds, + bgcolormsg->color); + } + } + break; #ifdef CONFIG_NX_XYINPUT - case NX_SVRMSG_MOUSEIN: /* New mouse report from mouse client */ - { - FAR struct nxsvrmsg_mousein_s *mousemsg = (FAR struct nxsvrmsg_mousein_s *)buffer; - nxmu_mousein(&nxmu, &mousemsg->pt, mousemsg->buttons); - } - break; + case NX_SVRMSG_MOUSEIN: /* New mouse report from mouse client */ + { + FAR struct nxsvrmsg_mousein_s *mousemsg = + (FAR struct nxsvrmsg_mousein_s *)buffer; + nxmu_mousein(&nxmu, &mousemsg->pt, mousemsg->buttons); + } + break; #endif #ifdef CONFIG_NX_KBD - case NX_SVRMSG_KBDIN: /* New keyboard report from keyboard client */ - { - FAR struct nxsvrmsg_kbdin_s *kbdmsg = (FAR struct nxsvrmsg_kbdin_s *)buffer; - nxmu_kbdin(&nxmu, kbdmsg->nch, kbdmsg->ch); - } - break; + case NX_SVRMSG_KBDIN: /* New keyboard report from keyboard client */ + { + FAR struct nxsvrmsg_kbdin_s *kbdmsg = + (FAR struct nxsvrmsg_kbdin_s *)buffer; + nxmu_kbdin(&nxmu, kbdmsg->nch, kbdmsg->ch); + } + break; #endif - case NX_SVRMSG_REDRAWREQ: /* Request re-drawing of rectangular region */ - { - FAR struct nxsvrmsg_redrawreq_s *redrawmsg = (FAR struct nxsvrmsg_redrawreq_s *)buffer; - nxmu_redraw(redrawmsg->wnd, &redrawmsg->rect); - } - break; - - /* Messages sent to the background window **************************/ - - case NX_CLIMSG_REDRAW: /* Re-draw the background window */ + case NX_SVRMSG_REDRAWREQ: /* Request re-drawing of rectangular region */ { - FAR struct nxclimsg_redraw_s *redraw = (FAR struct nxclimsg_redraw_s *)buffer; + FAR struct nxsvrmsg_redrawreq_s *redrawmsg = + (FAR struct nxsvrmsg_redrawreq_s *)buffer; + nxmu_redraw(redrawmsg->wnd, &redrawmsg->rect); + } + break; + + /* Messages sent to the background window *************************/ + + case NX_CLIMSG_REDRAW: /* Re-draw the background window */ + { + FAR struct nxclimsg_redraw_s *redraw = + (FAR struct nxclimsg_redraw_s *)buffer; DEBUGASSERT(redraw->wnd == &nxmu.be.bkgd); ginfo("Re-draw background rect={(%d,%d),(%d,%d)}\n", redraw->rect.pt1.x, redraw->rect.pt1.y, redraw->rect.pt2.x, redraw->rect.pt2.y); nxbe_fill(&nxmu.be.bkgd, &redraw->rect, nxmu.be.bgcolor); } - break; + break; - case NX_CLIMSG_MOUSEIN: /* Ignored */ - case NX_CLIMSG_KBDIN: - break; + case NX_CLIMSG_MOUSEIN: /* Ignored */ + case NX_CLIMSG_KBDIN: + break; - case NX_CLIMSG_CONNECTED: /* Shouldn't happen */ - case NX_CLIMSG_DISCONNECTED: - default: - gerr("ERROR: Unrecognized command: %d\n", msg->msgid); - break; - } + case NX_CLIMSG_CONNECTED: /* Shouldn't happen */ + case NX_CLIMSG_DISCONNECTED: + default: + gerr("ERROR: Unrecognized command: %" PRId32 "\n", msg->msgid); + break; + } } nxmu_shutdown(&nxmu); diff --git a/include/inttypes.h b/include/inttypes.h index a404bbe142e..8a3cb4307fe 100644 --- a/include/inttypes.h +++ b/include/inttypes.h @@ -306,6 +306,21 @@ #define SCNxFAST64 SCNx64 #endif +/* intmax_t/uintmax_t */ + +#define PRIdMAX "jd" +#define PRIiMAX "ji" +#define PRIoMAX "jo" +#define PRIuMAX "ju" +#define PRIxMAX "jx" +#define PRIXMAX "jX" + +#define SCNdMAX "jd" +#define SCNiMAX "ji" +#define SCNoMAX "jo" +#define SCNuMAX "ju" +#define SCNxMAX "jx" + /**************************************************************************** * Type Definitions ****************************************************************************/ diff --git a/include/nuttx/analog/adc.h b/include/nuttx/analog/adc.h index 3e3323a3cc5..0fb99c199b0 100644 --- a/include/nuttx/analog/adc.h +++ b/include/nuttx/analog/adc.h @@ -298,6 +298,22 @@ FAR struct adc_dev_s *lmp92001_adc_initialize(FAR struct i2c_master_s *i2c, FAR struct adc_dev_s *ads7828_initialize(FAR struct i2c_master_s *i2c, uint8_t addr); +/**************************************************************************** + * Name: max1161x_initialize + * + * Description: + * Initialize ADC + * + * Input Parameters: + * i2c - Pointer to a valid I2C master struct. + * + * Returned Value: + * Valid MX1161X device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +FAR struct adc_dev_s *max1161x_initialize(FAR struct i2c_master_s *i2c); + #if defined(__cplusplus) } #endif diff --git a/include/nuttx/analog/ioctl.h b/include/nuttx/analog/ioctl.h index 25279839a8a..f9d6653b909 100644 --- a/include/nuttx/analog/ioctl.h +++ b/include/nuttx/analog/ioctl.h @@ -82,13 +82,12 @@ /* See include/nuttx/analog/lm92001.h */ -#define AN_LMP92001_FIRST (AN_FIRST + AN_NCMDS + AN_ADS2142_NCMDS) +#define AN_LMP92001_FIRST (AN_ADS2142_FIRST + AN_ADS2142_NCMDS) #define AN_LMP92001_NCMDS 7 /* See include/nuttx/analog/ads7828.h */ -#define AN_ADS7828_FIRST (AN_FIRST + AN_NCMDS + AN_ADS2142_NCMDS + \ - AN_LMP92001_NCMDS) +#define AN_ADS7828_FIRST (AN_LMP92001_FIRST + AN_LMP92001_NCMDS) #define AN_ADS7828_NCMDS 6 /* See arch/arm/src/stm32l4/stm32l4_adc.h */ @@ -96,6 +95,11 @@ #define AN_STM32L4_FIRST (AN_ADS7828_FIRST + AN_ADS7828_NCMDS) #define AN_STM32L4_NCMDS 2 +/* See include/nuttx/analog/max1161x.h */ + +#define AN_MAX1161X_FIRST (AN_STM32L4_FIRST + AN_STM32L4_NCMDS) +#define AN_MAX1161X_NCMDS 8 + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ diff --git a/include/nuttx/analog/max1161x.h b/include/nuttx/analog/max1161x.h new file mode 100644 index 00000000000..64859f4eff8 --- /dev/null +++ b/include/nuttx/analog/max1161x.h @@ -0,0 +1,122 @@ +/**************************************************************************** + * include/nuttx/analog/max1161x.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_ANALOG_MAX1161X_H +#define __INCLUDE_NUTTX_ANALOG_MAX1161X_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IOCTL Commands + * Cmd: ANIOC_MAX1161X_SET_REF Arg: enum max1161x_ref_e + * Cmd: ANIOC_MAX1161X_SET_CLOCK Arg: enum max1161x_clock_e + * Cmd: ANIOC_MAX1161X_SET_UNIBIP Arg: enum max1161x_unibip_e + * Cmd: ANIOC_MAX1161X_SET_SCAN Arg: enum max1161x_scan_e + * Cmd: ANIOC_MAX1161X_ADD_CHAN Arg: uint8_t value + * Cmd: ANIOC_MAX1161X_REMOVE_CHAN Arg: uint8_t value + * Cmd: ANIOC_MAX1161X_SET_SNGDIF Arg: enum max1161x_sngdif_e + * Cmd: ANIOC_MAX1161X_READ_CHANNEL Arg: struct adc_msg_s *channel + */ + +#define ANIOC_MAX1161X_SET_REF _ANIOC(AN_MAX1161X_FIRST + 0) +#define ANIOC_MAX1161X_SET_CLOCK _ANIOC(AN_MAX1161X_FIRST + 1) +#define ANIOC_MAX1161X_SET_UNIBIP _ANIOC(AN_MAX1161X_FIRST + 2) +#define ANIOC_MAX1161X_SET_SCAN _ANIOC(AN_MAX1161X_FIRST + 3) +#define ANIOC_MAX1161X_ADD_CHAN _ANIOC(AN_MAX1161X_FIRST + 4) +#define ANIOC_MAX1161X_REMOVE_CHAN _ANIOC(AN_MAX1161X_FIRST + 5) +#define ANIOC_MAX1161X_SET_SNGDIF _ANIOC(AN_MAX1161X_FIRST + 6) +#define ANIOC_MAX1161X_READ_CHANNEL _ANIOC(AN_MAX1161X_FIRST + 7) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Setup Byte */ + +/**************************************************************************** + * +----+----+----+------+---------+---------+---------------+ + * |SEL2|SEL1|SEL0| VREF | Ref Pin | Ref Dir | Int Ref State | + * +----+----+----+------+---------+---------+---------------+ + * | 0 | 0 | x | VDD | AIN | NC | off | + * | 0 | 1 | x | EXT | RIN | IN | off | + * | 1 | 0 | 0 | INT | AIN | NC | off | + * | 1 | 0 | 1 | INT | AIN | NC | on | + * | 1 | 1 | 0 | INT | ROUT | OUT | off | + * | 1 | 1 | 1 | INT | ROUT | OUT | on | + * +----+----+----+------+---------+---------+---------------+ + ****************************************************************************/ + +enum max1161x_ref_e +{ + MAX1161X_REF_VDD_AIN_NC_OFF = 0u, + MAX1161X_REF_EXT_RIN_IN_OFF = 2u, + MAX1161X_REF_INT_AIN_NC_OFF = 4u, + MAX1161X_REF_INT_AIN_NC_ON = 5u, + MAX1161X_REF_INT_ROUT_OUT_OFF = 6u, + MAX1161X_REF_INT_ROUT_OUT_ON = 7u, +}; + +enum max1161x_clock_e +{ + MAX1161X_CLOCK_INT = 0u, + MAX1161X_CLOCK_EXT +}; + +enum max1161x_unibip_e +{ + MAX1161X_UNIPOLAR = 0u, + MAX1161X_BIPOLAR +}; + +enum max1161x_reset_e +{ + MAX1161X_NO_RESET = 0u, + MAX1161X_RESET +}; + +/* Configuration Byte */ + +enum max1161x_scan_e +{ + MAX1161X_SCAN_FROM_ZERO = 0u, + MAX1161X_SCAN_EIGHT_TIMES, + MAX1161X_SCAN_UPPER, + MAX1161X_SCAN_NONE +}; + +enum max1161x_sngdif_e +{ + MAX1161X_DIFFERENTIAL = 0u, + MAX1161X_SINGLE_ENDED +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __INCLUDE_NUTTX_ANALOG_MAX1161X_H */ diff --git a/include/nuttx/clock.h b/include/nuttx/clock.h index ab6f55b557e..b11b1cfc693 100644 --- a/include/nuttx/clock.h +++ b/include/nuttx/clock.h @@ -124,7 +124,7 @@ * the system timer is given by USEC_PER_TICK. This is the expected number * of microseconds between calls from the processor-specific logic to * nxsched_process_timer(). The default value of USEC_PER_TICK is 10000 - * microseconds (100KHz). However, this default setting can be overridden + * microseconds (100 Hz). However, this default setting can be overridden * by defining the interval in microseconds as CONFIG_USEC_PER_TICK in the * NuttX configuration file. * diff --git a/include/nuttx/compiler.h b/include/nuttx/compiler.h index 6bb2e6c9907..2ee6bcf5799 100644 --- a/include/nuttx/compiler.h +++ b/include/nuttx/compiler.h @@ -143,6 +143,9 @@ # define inline_function __attribute__ ((always_inline,no_instrument_function)) # define noinline_function __attribute__ ((noinline)) +# define printflike(a, b) __attribute__((__format__ (__printf__, a, b))) +# define scanflike(a, b) __attribute__((__format__ (__scanf__, a, b))) + /* GCC does not use storage classes to qualify addressing */ # define FAR @@ -358,6 +361,9 @@ # define inline_function # define noinline_function +# define printflike(a, b) +# define scanflike(a, b) + /* The reentrant attribute informs SDCC that the function * must be reentrant. In this case, SDCC will store input * arguments on the stack to support reentrancy. @@ -484,6 +490,8 @@ # define naked_function # define inline_function # define noinline_function +# define printflike(a, b) +# define scanflike(a, b) /* REVISIT: */ @@ -584,6 +592,8 @@ # define naked_function # define inline_function # define noinline_function +# define printflike(a, b) +# define scanflike(a, b) # define FAR # define NEAR @@ -639,6 +649,8 @@ # define naked_function # define inline_function # define noinline_function +# define printflike(a, b) +# define scanflike(a, b) # define FAR # define NEAR diff --git a/include/nuttx/fs/fs.h b/include/nuttx/fs/fs.h index 975838db76c..e8ad6c4e760 100644 --- a/include/nuttx/fs/fs.h +++ b/include/nuttx/fs/fs.h @@ -469,6 +469,9 @@ struct file_struct FAR unsigned char *fs_bufend; /* Pointer to 1 past end of buffer */ FAR unsigned char *fs_bufpos; /* Current position in buffer */ FAR unsigned char *fs_bufread; /* Pointer to 1 past last buffered read char. */ +# if CONFIG_STDIO_BUFFER_SIZE > 0 + unsigned char fs_buffer[CONFIG_STDIO_BUFFER_SIZE]; +# endif #endif uint16_t fs_oflags; /* Open mode flags */ uint8_t fs_flags; /* Stream flags */ @@ -481,6 +484,7 @@ struct file_struct struct streamlist { sem_t sl_sem; /* For thread safety */ + struct file_struct sl_std[3]; FAR struct file_struct *sl_head; FAR struct file_struct *sl_tail; }; diff --git a/include/nuttx/fs/ioctl.h b/include/nuttx/fs/ioctl.h index 8526c9117be..07481a57e9d 100644 --- a/include/nuttx/fs/ioctl.h +++ b/include/nuttx/fs/ioctl.h @@ -100,6 +100,7 @@ #define _NOTECTLBASE (0x2c00) /* Note filter control ioctl commands*/ #define _NOTERAMBASE (0x2d00) /* Noteram device ioctl commands*/ #define _RCIOCBASE (0x2e00) /* Remote Control device ioctl commands */ +#define _HIMEMBASE (0x2f00) /* Himem device ioctl commands*/ #define _WLIOCBASE (0x8b00) /* Wireless modules ioctl network commands */ /* boardctl() commands share the same number space */ @@ -545,6 +546,11 @@ #define _RCIOCVALID(c) (_IOC_TYPE(c)==_RCIOCBASE) #define _RCIOC(nr) _IOC(_RCIOCBASE,nr) +/* Hime drivers *************************************************************/ + +#define _HIMEMIOCVALID(c) (_IOC_TYPE(c) == _HIMEMBASE) +#define _HIMEMIOC(nr) _IOC(_HIMEMBASE, nr) + /* Wireless driver network ioctl definitions ********************************/ /* (see nuttx/include/wireless/wireless.h */ diff --git a/include/nuttx/himem/himem.h b/include/nuttx/himem/himem.h new file mode 100644 index 00000000000..96e65691711 --- /dev/null +++ b/include/nuttx/himem/himem.h @@ -0,0 +1,173 @@ +/**************************************************************************** + * include/nuttx/himem/himem.h + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_HIMEM_HIMEM_H +#define __INCLUDE_NUTTX_HIMEM_HIMEM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#ifdef CONFIG_ESP32_SPIRAM + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* ESP32 MMU block size */ + +#define ESP_HIMEM_BLKSZ (0x8000) + +/* Command: HIMEMIOC_ALLOC_BLOCKS + * Description: Allocate a certain number of physical RAM blocks. + * Arguments: A structure containing the size of physical block to allocate + * and its esp_himem_handle_t. + * Return: Zero (OK) on success. Minus one will be returned on failure + * with the errno value set appropriately. + */ + +#define HIMEMIOC_ALLOC_BLOCKS _HIMEMIOC(0x0001) + +/* Command: HIMEMIOC_FREE_BLOCKS + * Description: Free a certain number of physical RAM blocks. + * Arguments: A structure containing the size of physical block to allocate + * and its esp_himem_handle_t. + * Return: Zero (OK) on success. Minus one will be returned on failure + * with the errno value set appropriately. + */ + +#define HIMEMIOC_FREE_BLOCKS _HIMEMIOC(0x0002) + +/* Command: HIMEMIOC_ALLOC_MAP_RANGE + * Description: Free the physical RAM blocks + * Arguments: A structure containing the block size and its + * esp_himem_rangehandle_t. + * Return: Zero (OK) on success. Minus one will be returned on failure + * with the errno value set appropriately. + */ + +#define HIMEMIOC_ALLOC_MAP_RANGE _HIMEMIOC(0x0003) + +/* Command: HIMEMIOC_FREE_MAP_RANGE + * Description: Maps the memory addresses to the physical psram range. + * Arguments: A structure containing the esp_himem_handle_t handle, the + * esp_himem_rangehandle_t, the ram offset, the range offset, + * the length, the memory flags and the output pointer. + * Return: Zero (OK) on success. Minus one will be returned on failure + * with the errno value set appropriately. + */ + +#define HIMEMIOC_FREE_MAP_RANGE _HIMEMIOC(0x0004) + +/* Command: HIMEMIOC_MAP + * Description: Maps the memory addresses to the physical psram range. + * Arguments: A structure containing the esp_himem_handle_t handle, the + * esp_himem_rangehandle_t, the ram offset, the range offset, + * the length, the memory flags and the output pointer. + * Return: Zero (OK) on success. Minus one will be returned on failure + * with the errno value set appropriately. + */ + +#define HIMEMIOC_MAP _HIMEMIOC(0x0005) + +/* Command: HIMEMIOC_UNMAP + * Description: Unmaps the memory addresses to the physical psram range. + * Arguments: A structure containing the esp_himem_rangehandle_t, the + * memory pointer and the memory length. + * the length, the memory flags and the output pointer. + * Return: Zero (OK) on success. Minus one will be returned on failure + * with the errno value set appropriately. + */ + +#define HIMEMIOC_UNMAP _HIMEMIOC(0x0006) + +/* Command: HIMEMIOC_GET_PHYS_SIZE + * Description: Get the size of physical external memory + * Arguments: None + * Return: Zero (OK) on success. Minus one will be returned on failure + * with the errno value set appropriately. + */ + +#define HIMEMIOC_GET_PHYS_SIZE _HIMEMIOC(0x0007) + +/* Command: HIMEMIOC_GET_FREE_SIZE + * Description: Get the amount of free memory + * Arguments: None + * Return: Zero (OK) on success. Minus one will be returned on failure + * with the errno value set appropriately. + */ + +#define HIMEMIOC_GET_FREE_SIZE _HIMEMIOC(0x0008) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Handle for a window of address space */ + +typedef struct esp_himem_rangedata_t +{ + int block_ct; + int block_start; +} esp_himem_rangedata_t; + +/* Handle for a range of physical memory */ + +typedef struct esp_himem_ramdata_t +{ + int block_ct; + uint16_t *block; +} esp_himem_ramdata_t; + +/* Opaque pointers as handles for ram/range data */ + +typedef struct esp_himem_ramdata_t *esp_himem_handle_t; +typedef struct esp_himem_rangedata_t *esp_himem_rangehandle_t; + +/* Structs with the parameters passed to the IOCTLs */ + +struct esp_himem_par +{ + esp_himem_handle_t handle; + esp_himem_rangehandle_t range; + size_t ram_offset; + size_t range_offset; + size_t memfree; + size_t memcnt; + size_t len; + int flags; + uint32_t *ptr; +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +int esp_himem_init(void); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_ESP32_SPIRAM */ +#endif /* __INCLUDE_NUTTX_HIMEM_HIMEM_H */ diff --git a/include/nuttx/net/mii.h b/include/nuttx/net/mii.h index 819fb647ac9..e692fa56ea7 100644 --- a/include/nuttx/net/mii.h +++ b/include/nuttx/net/mii.h @@ -71,9 +71,13 @@ #define MII_MMDCONTROL 0x0d /* MMD access control register */ #define MII_ESTATUS 0x0f /* Extended status register */ -/* Extended Registers: Registers 16-31 may be used for vendor specific abilities */ +/* Extended Registers: Registers 16-31 may be used for vendor specific + * abilities + */ -/* National Semiconductor DP83840: 0x07-0x11, 0x14, 0x1a, 0x1d-0x1f reserved */ +/* National Semiconductor DP83840: 0x07-0x11, 0x14, 0x1a, 0x1d-0x1f + * reserved + */ #define MII_DP83840_COUNTER 0x12 /* Disconnect counter */ #define MII_DP83840_FCSCOUNTER 0x13 /* False carrier sense counter */ @@ -143,7 +147,9 @@ #define MII_KSZ8081_PHYCTRL1 0x1e /* PHY Control 1 */ #define MII_KSZ8081_PHYCTRL2 0x1f /* PHY Control 2 */ -/* National Semiconductor DP83848C PHY Extended Registers. 0x8-0x15, 0x13, 0x1c reserved */ +/* National Semiconductor DP83848C PHY Extended Registers. + * 0x8-0x15, 0x13, 0x1c reserved + */ #define MII_DP83848C_STS 0x10 /* RO PHY Status Register */ #define MII_DP83848C_MICR 0x11 /* RW MII Interrupt Control Register */ @@ -158,6 +164,24 @@ #define MII_DP83848C_CDCTRL1 0x1b /* RW CD Test Control Register and BIST Extensions Register */ #define MII_DP83848C_EDCR 0x1e /* RW Energy Detect Control Register */ +/* Texas Instruments DP83825I PHY Extended Registers. */ + +#define MII_DP83825I_PHYSTS 0x10 /* RO PHY Status Register */ +#define MII_DP83825I_PHYSCR 0x11 /* RW PHY Specific Control Register */ +#define MII_DP83825I_MISR1 0x12 /* RO MII Interrupt Status Register 1 */ +#define MII_DP83825I_MISR2 0x13 /* RO MII Interrupt Status Register 2 */ +#define MII_DP83825I_FCSCR 0x14 /* RO False Carrier Sense Counter Register */ +#define MII_DP83825I_RECR 0x15 /* RO Receive Error Counter Register */ +#define MII_DP83825I_BICSR 0x16 /* RW BIST Control Register */ +#define MII_DP83825I_RCSR 0x17 /* RW RMII and Control and Status Register */ +#define MII_DP83825I_LEDCR 0x18 /* RW LED Direct Control Register */ +#define MII_DP83825I_PHYCR 0x19 /* RW PHY Control Register */ +#define MII_DP83825I_10BTSCR 0x1a /* RW 10Base-T Status/Control Register */ +#define MII_DP83825I_BICSR1 0x1b /* RW BIST Control Register 1 */ +#define MII_DP83825I_BICSR2 0x1c /* RW BIST Control Register 2 */ +#define MII_DP83825I_LEDCR 0x1e /* RW Energy Detect Control Register */ +#define MII_DP83825I_PHYRCR 0x1f /* RW PHY Reset Control Register */ + /* SMSC LAN8720 PHY Extended Registers */ #define MII_LAN8720_REV 0x10 /* Silicon Revision Register */ @@ -219,7 +243,9 @@ #define MII_MSR_100BASETXFULL (1 << 14) /* Bit 14: 100BASE-TX full duplex able */ #define MII_MSR_100BASET4 (1 << 15) /* Bit 15: 100BASE-T4 able */ -/* MII ID1 register bits: Bits 3-18 of the Organizationally Unique identifier (OUI) */ +/* MII ID1 register bits: Bits 3-18 of the Organizationally Unique + * identifier (OUI) + */ /* MII ID2 register bits */ @@ -318,6 +344,7 @@ # define MII_MMDCONTROL_FUNC_WINCR (3 << MII_MMDCONTROL_FUNC_SHIFT) /* Data, post incr on writes */ /* Extended status register */ + /* Bits 0-11: Reserved */ #define MII_ESTATUS_1000BASETHALF (1 << 12) /* Bit 12: 1000BASE-T Half Duplex able */ #define MII_ESTATUS_1000BASETFULL (1 << 13) /* Bit 13: 1000BASE-T Full Duplex able */ @@ -348,6 +375,30 @@ #define MII_RBR_RMIIREV10 (1 << 4) /* Bit 4: 0=RMIIv1.2 1-RMIIv1.0 */ #define MII_RBR_RMIIMODE (1 << 5) /* Bit 5: 0=MII mode 1=RMII mode */ +/* Texas Instruments DP83825I ***********************************************/ + +/* DP838825I MII ID1/2 register bits */ + +#define MII_PHYID1_DP83825I 0x2000 /* ID1 value for DP838825 */ +#define MII_PHYID2_DP83825I 0xa140 /* ID2 value for DP838825 */ + +/* PHYSTS Register (0x10) */ + +#define MII_DP83825I_PHYSTS_SPEED (1 << 1) /* Bit 2: Speed Status Register */ +#define MII_DP83825I_PHYSTS_DUPLEX (1 << 2) /* Bit 3: Duplex Status Register */ + +/* RCSC Register (0x17) */ + +#define MII_DP83825I_RCSC_ELAST_MASK 0x0003 /* Bits 0-1: Receive elasticity buffer */ +# define MII_DP83825I_RCSC_ELAST_14 0x0000 /* 14 bit tolerance */ +# define MII_DP83825I_RCSC_ELAST_2 0x0001 /* 2 bit tolerance */ +# define MII_DP83825I_RCSC_ELAST_6 0x0002 /* 6 bit tolerance */ +# define MII_DP83825I_RCSC_ELAST_10 0x0003 /* 10 bit tolerance */ +#define MII_DP83825I_RCSC_RXUNFSTS (1 << 2) /* Bit 2: RX FIFO underflow */ +#define MII_DP83825I_RCSC_RXOVFSTS (1 << 3) /* Bit 3: RX FIFO overflow */ +#define MII_DP83825I_RCSC_RMIIREV10 (1 << 4) /* Bit 4: 0=RMIIv1.2 1-RMIIv1.0 */ +#define MII_DP83825I_RCSC_RMIICS (1 << 7) /* Bit 7: 0=25MHz 1=50MHz */ + /* SMSC LAN8720 *************************************************************/ /* SMSC LAN8720 MII ID1/2 register bits */ @@ -480,7 +531,7 @@ #define LM_LEDCONFIG_LED0_10BASET (6 << LM_LEDCONFIG_LED0_SHIFT) /* 10BASE-T mode */ #define LM_LEDCONFIG_LED0_FDUPLEX (7 << LM_LEDCONFIG_LED0_SHIFT) /* Full duplex */ #define LM_LEDCONFIG_LED0_OKRXTX (8 << LM_LEDCONFIG_LED0_SHIFT) /* Full duplex */ -#define LM_LEDCONFIG_LED1_SHIFT (4) /* Bits 7-4: LED1 Source */ +#define LM_LEDCONFIG_LED1_SHIFT (4) /* Bits 7-4: LED1 Source */ #define LM_LEDCONFIG_LED1_MASK (0x0f << LM_LEDCONFIG_LED1_SHIFT) #define LM_LEDCONFIG_LED1_LINKOK (0 << LM_LEDCONFIG_LED1_SHIFT) /* Link OK */ #define LM_LEDCONFIG_LED1_RXTX (1 << LM_LEDCONFIG_LED1_SHIFT) /* RX or TX activity */ @@ -543,6 +594,7 @@ # define KS8721_10BTCR_MODE_10BTFD (5 << KS8721_10BTCR_MODE_SHIFT) /* 10BASE-T full duplex */ # define KS8721_10BTCR_MODE_100BTFD (6 << KS8721_10BTCR_MODE_SHIFT) /* 100BASE-T full duplex */ # define KS8721_10BTCR_MODE_ISOLATE (7 << KS8721_10BTCR_MODE_SHIFT) /* PHY/MII isolate */ + #define KS8721_10BTCR_ISOLATE (1 << 5) /* Bit 5: PHY isolate */ #define KS8721_10BTCR_PAUSE (1 << 6) /* Bit 6: Enable pause */ #define KS8721_10BTCR_ANEGCOMP (1 << 7) /* Bit 7: Auto-negotiation complete */ @@ -567,9 +619,11 @@ #define MII_PHYID2_KSZ8081 0x1560 /* ID2 value for Micrel KSZ8081 */ /* KSZ8081 Digital Reserve Control */ + /* Bits 5-15: Reserved */ #define KSZ8081_DRCTRL_PLLOFF (1 << 4) /* Bit 4: Turn PLL off in EDPD mode */ /* Bits 0-3: Reserved */ + /* KSZ8041/51/81 Register 0x1b: Interrupt control/status */ #define MII_KSZ80X1_INT_JEN (1 << 15) /* Jabber interrupt enable */ @@ -613,10 +667,12 @@ # define MII_PHYCTRL2_MODE_DUPLEX (4 << MII_PHYCTRL2_MODE_SHIFT) /* Full duplex */ # define MII_PHYCTRL2_MODE_10FDX (5 << MII_PHYCTRL2_MODE_SHIFT) /* 10Base-T full-duplex */ # define MII_PHYCTRL2_MODE_100FDX (6 << MII_PHYCTRL2_MODE_SHIFT) /* 100Base-T full-duplex */ + #define MII_PHYCTRL2_SEQTEST (1 << 1) /* Bit 1: Enable SQE test */ #define MII_PHYCTRL2_DISDS (1 << 0) /* Bit 1: Disable data scrambling */ /* KSZ8051/81 Register 0x1e: PHY Control 1 */ + /* Bits 10-15: Reserved */ #define MII_PHYCTRL1_ENPAUSE (1 << 9) /* Bit 9: Enable pause */ #define MII_PHYCTRL1_LINKSTATUS (1 << 8) /* Bit 8: Link status */ @@ -721,6 +777,7 @@ # define MII_CONFIG2_SNR_AV64 (1 << MII_CONFIG2_SNR_SHIFT) /* signal to noise ratio averaging over 64 symbols */ # define MII_CONFIG2_SNR_AV128 (2 << MII_CONFIG2_SNR_SHIFT) /* signal to noise ratio averaging over 128 symbols */ # define MII_CONFIG2_SNR_AV256 (3 << MII_CONFIG2_SNR_SHIFT) /* signal to noise ratio averaging over 256 symbols */ + #define MII_CONFIG2_WLIM_SHIFT (6) /* SQI warning limit */ #define MII_CONFIG2_WLIM_MASK (7 << MII_CONFIG2_WLIM_SHIFT) # define MII_CONFIG2_WLIM_NO (0 << MII_CONFIG2_WLIM_SHIFT) /* no warning */ @@ -731,6 +788,7 @@ # define MII_CONFIG2_WLIM_E (5 << MII_CONFIG2_WLIM_SHIFT) /* Class E SNR warning limit */ # define MII_CONFIG2_WLIM_F (6 << MII_CONFIG2_WLIM_SHIFT) /* Class F SNR warning limit */ # define MII_CONFIG2_WLIM_G (7 << MII_CONFIG2_WLIM_SHIFT) /* Class G SNR warning limit */ + #define MII_CONFIG2_SNR_F_SHIFT (3) /* signal to noise ratio fail limit */ #define MII_CONFIG2_SNR_F_MASK (7 << MII_CONFIG2_SNR_F_SHIFT) # define MII_CONFIG2_SNR_F_NL (0 << MII_CONFIG2_SNR_F_SHIFT) /* no limit */ @@ -741,8 +799,9 @@ # define MII_CONFIG2_SNR_F_CLE (5 << MII_CONFIG2_SNR_F_SHIFT) /* Class E */ # define MII_CONFIG2_SNR_F_CLF (6 << MII_CONFIG2_SNR_F_SHIFT) /* Class F */ # define MII_CONFIG2_SNR_F_CLG (7 << MII_CONFIG2_SNR_F_SHIFT) /* Class G */ + #define MII_CONFIG2_JUMBO_EN (1 << 2) /* enable packets up to 16 kB instead of 4 kB */ -#define MII_CONFIG2_SLP_T_SHIFT (0) /* sleep request timeout */ +#define MII_CONFIG2_SLP_T_SHIFT (0) /* sleep request timeout */ #define MII_CONFIG2_SLP_T_MASK (3 << MII_CONFIG2_SLP_T_SHIFT) # define MII_CONFIG2_SLP_T_04 (0 << MII_CONFIG2_SLP_T_SHIFT) /* sleep request timeout 0.4 ms */ # define MII_CONFIG2_SLP_T_1 (1 << MII_CONFIG2_SLP_T_SHIFT) /* sleep request timeout 1 ms */ diff --git a/include/nuttx/power/pm.h b/include/nuttx/power/pm.h index 21cfd6156f1..c2262468ce5 100644 --- a/include/nuttx/power/pm.h +++ b/include/nuttx/power/pm.h @@ -1,37 +1,20 @@ /**************************************************************************** - * include/nuttx/power/pm.h - * NuttX Power Management Interfaces + * arch/arm/src/nrf52/nrf52_pminitialize.c * - * Copyright (C) 2011-2012, 2015-2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Author: Matias Nitsche + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -227,12 +210,12 @@ struct pm_governor_s * * Description: * Invoked by the PM system during initialization, to allow the governor - * to initialize its internal data. This can be left to NULL if not needed - * by the governor. + * to initialize its internal data. This can be left to NULL if not + * needed by the governor. * * NOTE: since this will be called from pm_initialize(), the system * is in very early boot state when this callback is invoked. Thus, - * only ver basic initialization should be performed (e.g. no memory + * only very basic initialization should be performed (e.g. no memory * should be allocated). * **************************************************************************/ @@ -379,8 +362,9 @@ int pm_unregister(FAR struct pm_callback_s *callbacks); * higher priorities. Higher priority activity can prevent the system * from entering reduced power states for a longer period of time. * - * As an example, a button press might be higher priority activity because - * it means that the user is actively interacting with the device. + * As an example, a button press might be higher priority activity + * because it means that the user is actively interacting with the + * device. * * Returned Value: * None. @@ -405,7 +389,8 @@ void pm_activity(int domain, int priority); * domain - The domain of the PM activity * state - The state want to stay. * - * As an example, media player might stay in normal state during playback. + * As an example, media player might stay in normal state during + * playback. * * Returned Value: * None. @@ -465,15 +450,15 @@ uint32_t pm_staycount(int domain, enum pm_state_e state); * * Description: * This function is called from the MCU-specific IDLE loop to monitor the - * the power management conditions. This function returns the "recommended" - * power management state based on the PM configuration and activity - * reported in the last sampling periods. The power management state is - * not automatically changed, however. The IDLE loop must call + * the power management conditions. This function returns the + * "recommended" power management state based on the PM configuration and + * activity reported in the last sampling periods. The power management + * state is not automatically changed, however. The IDLE loop must call * pm_changestate() in order to make the state change. * - * These two steps are separated because the platform-specific IDLE loop may - * have additional situational information that is not available to the - * the PM sub-system. For example, the IDLE loop may know that the + * These two steps are separated because the platform-specific IDLE loop + * may have additional situational information that is not available to + * the the PM sub-system. For example, the IDLE loop may know that the * battery charge level is very low and may force lower power states * even if there is activity. * diff --git a/include/nuttx/sensors/ioctl.h b/include/nuttx/sensors/ioctl.h index b724267a158..776a1fad9e6 100644 --- a/include/nuttx/sensors/ioctl.h +++ b/include/nuttx/sensors/ioctl.h @@ -262,11 +262,11 @@ /* Command: SNIOC_GET_NEVENTBUF * Description: the number of sensor events that sensor buffer of upper half holds. * Argument: This is the number of events pointer, is output parameter. - * Note: We need to tell the application layer number of sensor events in - * sensor buffer. This buffer is used to solve the problem that the - * application layer can't read the sensor event in time. We recommend - * the number of sensor events in application layer's buffer is same as - * result by call this function. + * Note: Tell the application layer number of sensor events in sensor buffer. + * This buffer is used to solve the problem that the application layer + * can't read the sensor event in time. Recommend the number of sensor + * events in application layer's buffer is same as result by call this + * function. * This is number of sensor events rather than the length of buffer. * See sensor.h(struct sensor_lower_half_s buffer_bytes). */ @@ -274,11 +274,11 @@ #define SNIOC_GET_NEVENTBUF _SNIOC(0x0070) /* Command: SNIOC_SET_BUFFER_SIZE - * Description: Use to set size of intermediate circual buffer in upper half driver. + * Description: Set size of intermediate circualr buffer in upper half driver. * Argument: This is the size of buffer pointer. - * Note: The application layer can set size of intermediate circual buffer - * by this ioctl cmd. The size is in bytes, it should be a multiple of - * an event. + * Note: The application layer can set size of intermediate circualr buffer + * by this ioctl command. The size is in bytes, it should be a multiple + * of an event. */ #define SNIOC_SET_BUFFER_SIZE _SNIOC(0x0071) diff --git a/include/nuttx/sensors/sensor.h b/include/nuttx/sensors/sensor.h index 802e62f5b5d..23d155b0a58 100644 --- a/include/nuttx/sensors/sensor.h +++ b/include/nuttx/sensors/sensor.h @@ -446,7 +446,7 @@ struct sensor_ops_s * If *period_us > max_delay it will be truncated to max_dealy and if * *period_us < min_delay it will be replaced by min_delay. * - * Before changing the interval, You need to push the prepared data to + * Before changing the interval, you need to push the prepared data to * ensure that they are not lost. * * Input Parameters: @@ -471,7 +471,7 @@ struct sensor_ops_s * This function can be called while the sensor is activated, * in which case it must not cause any sensor measurements to be lost. * So, it is necessary to flush fifo or read ready data from data - * register to prevent data lost before You using batch mode. + * register to prevent data lost before you using batch mode. * * This sensor default mode isn't batch mode, so you need call this * function and *latency_us != 0. @@ -509,15 +509,16 @@ struct sensor_ops_s /************************************************************************** * Name: fetch * - * We can fetch sensor register data by this function. It will use buffer - * of sensor_read provided and disables intermediate buffer of upper half. - * We recommend lowerhalf driver writer to use this function for slower - * ODR(output data rate) of sensor because this way saves space and simple. + * Fetch sensor register data by this function. It will use buffer of + * userspace provided and disables intermediate buffer of upper half. It's + * recommend that the lowerhalf driver writer to use this function for + * slower sensor ODR (output data rate) of sensor because this way saves + * space and it's simple. * - * If fectch isn't NULL, upper half driver will disable intermediate + * If fetch isn't NULL, upper half driver will disable intermediate * buffer and userspace can't set buffer size by ioctl. * - * You can call this function to read sensor register data by i2c/spi bus + * You can call this function to read sensor register data by I2C/SPI bus * when open mode is non-block, and poll are always successful. * When you call this function and open mode is block, you will wait * until sensor data ready, then read sensor data. @@ -540,7 +541,7 @@ struct sensor_ops_s /************************************************************************** * Name: control * - * In this method, user can set some special config for the sensor, + * With this method, the user can set some special config for the sensor, * such as changing the custom mode, setting the custom resolution, reset, * etc, which are all parsed and implemented by lower half driver. * @@ -656,14 +657,14 @@ extern "C" * "upper half" Sensor device and registers that device so that can be used * by application code. * - * You can register the chararter device by node name format based on the + * You can register the character device by node name format based on the * type of sensor. Multiple types of the same type are distinguished by * numbers. eg: accel0, accel1. This type of sensor must be less than * SENSOR_TYPE_COUNT. This API corresponds to the sensor_unregister. * * Input Parameters: * dev - A pointer to an instance of lower half sensor driver. This - * instance is bound to the sensor driver and must persists as long + * instance is bound to the sensor driver and must persist as long * as the driver persists. * devno - The user specifies which device of this type, from 0. If the * devno alerady exists, -EEXIST will be returned. @@ -689,7 +690,7 @@ int sensor_register(FAR struct sensor_lowerhalf_s *dev, int devno); * * Input Parameters: * dev - A pointer to an instance of lower half sensor driver. This - * instance is bound to the sensor driver and must persists as long + * instance is bound to the sensor driver and must persist as long * as the driver persists. * path - The user specifies path of device. ex: /dev/sensor/xxx. * esize - The element size of intermediate circular buffer. @@ -707,7 +708,7 @@ int sensor_custom_register(FAR struct sensor_lowerhalf_s *dev, * Name: sensor_unregister * * Description: - * This function unregister character node and release all resource about + * This function unregisters character node and releases all resource from * upper half driver. This API corresponds to the sensor_register. * * Input Parameters: @@ -723,7 +724,7 @@ void sensor_unregister(FAR struct sensor_lowerhalf_s *dev, int devno); * Name: sensor_custom_unregister * * Description: - * This function unregister character node and release all resource about + * This function unregisters character node and releases all resource from * upper half driver. This API corresponds to the sensor_custom_register. * * Input Parameters: diff --git a/include/nuttx/signal.h b/include/nuttx/signal.h index bc57ab6b69f..f8f80d305d6 100644 --- a/include/nuttx/signal.h +++ b/include/nuttx/signal.h @@ -366,7 +366,7 @@ int nxsig_kill(pid_t pid, int signo); * is forever. * * If the info argument is non-NULL, the selected signal number is stored - * in the si_signo member and the cause of the signal is store din the + * in the si_signo member and the cause of the signal is stored in the * si_code member. The content of si_value is only meaningful if the * signal was generated by sigqueue(). * diff --git a/include/nuttx/spi/spi.h b/include/nuttx/spi/spi.h index 8df48a55aea..6f7f889f136 100644 --- a/include/nuttx/spi/spi.h +++ b/include/nuttx/spi/spi.h @@ -57,7 +57,7 @@ /* These SPI configuration options affect the form of the SPI interface: * * CONFIG_SPI_EXCHANGE - Driver supports a single exchange method - * (vs a recvblock() and sndblock ()methods). + * (vs a recvblock() and sndblock() methods). * CONFIG_SPI_CMDDATA - Devices on the SPI bus require out-of-band support * to distinguish command transfers from data transfers. Such devices * will often support either 9-bit SPI (yech) or 8-bit SPI and a GPIO @@ -95,7 +95,7 @@ * Name: SPI_SELECT * * Description: - * Enable/disable the SPI chip select. The implementation of this method + * Enable/disable the SPI chip select. The implementation of this method * must include handshaking: If a device is selected, it must hold off * all other attempts to select the device until the device is deselected. * Required. @@ -173,7 +173,7 @@ * Name: SPI_SETBITS * * Description: - * Set the number if bits per word. + * Set the number of bits per word. * * Input Parameters: * dev - Device-specific state data @@ -290,7 +290,7 @@ * Name: SPI_CMDDATA * * Description: - * Some devices require and additional out-of-band bit to specify if the + * Some devices require an additional out-of-band bit to specify if the * next word sent to the device is a command or data. This is typical, for * example, in "9-bit" displays where the 9th bit is the CMD/DATA bit. * This function provides selection of command or data. @@ -322,7 +322,7 @@ * * Input Parameters: * dev - Device-specific state data - * wd - The word to send. the size of the data is determined by the + * wd - The word to send. The size of the data is determined by the * number of bits selected for the SPI interface. * * Returned Value: @@ -341,7 +341,7 @@ * Input Parameters: * dev - Device-specific state data * buffer - A pointer to the buffer of data to be sent - * nwords - the length of data to send from the buffer in number of words. + * nwords - The length of data to send from the buffer in number of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is * packed into uint8_t's; if nbits >8, the data is packed into @@ -367,10 +367,10 @@ * Input Parameters: * dev - Device-specific state data * buffer - A pointer to the buffer in which to receive data - * nwords - the length of data that can be received in the buffer in number + * nwords - The length of data that can be received in the buffer in number * of words. The wordsize is determined by the number of bits- * per-word selected for the SPI interface. If nbits <= 8, the - * data is packed into uint8_t's; if nbits >8, the data is packed + * data is packed into uint8_t's; if nbits > 8, the data is packed * into uint16_t's * * Returned Value: @@ -394,8 +394,8 @@ * dev - Device-specific state data * txbuffer - A pointer to the buffer of data to be sent * rxbuffer - A pointer to the buffer in which to receive data - * nwords - the length of data that to be exchanged in units of words. - * The wordsize is determined by the number of bits-per-word + * nwords - The length of data to be exchanged in units of words. The + * wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is * packed into uint8_t's; if nbits >8, the data is packed into * uint16_t's @@ -413,8 +413,8 @@ * Name: SPI_REGISTERCALLBACK * * Description: - * Register a callback that that will be invoked on any media status - * change (i.e, anything that would be reported differently by SPI_STATUS). + * Register a callback that will be invoked on any media status change + * (i.e, anything that would be reported differently by SPI_STATUS). * Optional * * Input Parameters: diff --git a/include/nuttx/streams.h b/include/nuttx/streams.h index 73714df87d8..63fb83f2c30 100644 --- a/include/nuttx/streams.h +++ b/include/nuttx/streams.h @@ -310,7 +310,8 @@ void lib_rawsostream(FAR struct lib_rawsostream_s *outstream, int fd); * Name: lib_lowoutstream * * Description: - * Initializes a stream for use with low-level, architecture-specific output. + * Initializes a stream for use with low-level, architecture-specific + * output. * Defined in ib/stdio/lib_lowoutstream.c * * Input Parameters: @@ -451,7 +452,7 @@ int lib_snoflush(FAR struct lib_sostream_s *this); ****************************************************************************/ int lib_sprintf(FAR struct lib_outstream_s *obj, - FAR const IPTR char *fmt, ...); + FAR const IPTR char *fmt, ...) printflike(2, 3); /**************************************************************************** * Name: lib_vsprintf @@ -463,7 +464,7 @@ int lib_sprintf(FAR struct lib_outstream_s *obj, ****************************************************************************/ int lib_vsprintf(FAR struct lib_outstream_s *obj, - FAR const IPTR char *src, va_list ap); + FAR const IPTR char *src, va_list ap) printflike(2, 0); /**************************************************************************** * Name: lib_vscanf @@ -475,7 +476,7 @@ int lib_vsprintf(FAR struct lib_outstream_s *obj, ****************************************************************************/ int lib_vscanf(FAR struct lib_instream_s *obj, FAR int *lastc, - FAR const IPTR char *src, va_list ap); + FAR const IPTR char *src, va_list ap) scanflike(3, 0); #undef EXTERN #if defined(__cplusplus) diff --git a/include/stdint.h b/include/stdint.h index 69c54be9d43..469e3a23723 100644 --- a/include/stdint.h +++ b/include/stdint.h @@ -147,19 +147,6 @@ # define UINTMAX_MIN UINT64_MIN # define UINTMAX_MAX UINT64_MAX -# define PRIdMAX PRId64 -# define PRIiMAX PRIi64 -# define PRIoMAX PRIo64 -# define PRIuMAX PRIu64 -# define PRIxMAX PRIx64 -# define PRIXMAX PRIX64 - -# define SCNdMAX SCNd64 -# define SCNiMAX SCNi64 -# define SCNoMAX SCNo64 -# define SCNuMAX SCNu64 -# define SCNxMAX SCNx64 - # define INTMAX_C(x) INT64_C(x) # define UINTMAX_C(x) UINT64_C(x) #else @@ -169,19 +156,6 @@ # define UINTMAX_MIN UINT32_MIN # define UINTMAX_MAX UINT32_MAX -# define PRIdMAX PRId32 -# define PRIiMAX PRIi32 -# define PRIoMAX PRIo32 -# define PRIuMAX PRIu32 -# define PRIxMAX PRIx32 -# define PRIXMAX PRIX32 - -# define SCNdMAX SCNd32 -# define SCNiMAX SCNi32 -# define SCNoMAX SCNo32 -# define SCNuMAX SCNu32 -# define SCNxMAX SCNx32 - # define INTMAX_C(x) INT32_C(x) # define UINTMAX_C(x) UINT32_C(x) #endif @@ -300,13 +274,8 @@ typedef _uint_farptr_t uint_farptr_t; /* Greatest-width integer types */ -#ifdef __INT64_DEFINED -typedef _int64_t intmax_t; -typedef _uint64_t uintmax_t; -#else -typedef _int32_t intmax_t; -typedef _uint32_t uintmax_t; -#endif +typedef _intmax_t intmax_t; +typedef _uintmax_t uintmax_t; #endif /* CONFIG_ARCH_STDINT_H */ #endif /* __INCLUDE_STDINT_H */ diff --git a/include/stdio.h b/include/stdio.h index 49f46d20fa4..a79a0071eba 100644 --- a/include/stdio.h +++ b/include/stdio.h @@ -78,9 +78,9 @@ /* The first three _iob entries are reserved for standard I/O */ -#define stdin (nxsched_get_streams()->sl_head) -#define stdout (nxsched_get_streams()->sl_head->fs_next) -#define stderr (nxsched_get_streams()->sl_head->fs_next->fs_next) +#define stdin (&nxsched_get_streams()->sl_std[0]) +#define stdout (&nxsched_get_streams()->sl_std[1]) +#define stderr (&nxsched_get_streams()->sl_std[2]) /* Path to the directory where temporary files can be created */ @@ -141,13 +141,15 @@ int fgetc(FAR FILE *stream); int fgetpos(FAR FILE *stream, FAR fpos_t *pos); FAR char *fgets(FAR char *s, int n, FAR FILE *stream); FAR FILE *fopen(FAR const char *path, FAR const char *type); -int fprintf(FAR FILE *stream, FAR const IPTR char *format, ...); +int fprintf(FAR FILE *stream, FAR const IPTR char *format, ...) + printflike(2, 3); int fputc(int c, FAR FILE *stream); int fputs(FAR const IPTR char *s, FAR FILE *stream); size_t fread(FAR void *ptr, size_t size, size_t n_items, FAR FILE *stream); FAR FILE *freopen(FAR const char *path, FAR const char *mode, FAR FILE *stream); -int fscanf(FAR FILE *stream, FAR const IPTR char *fmt, ...); +int fscanf(FAR FILE *stream, FAR const IPTR char *fmt, ...) + scanflike(2, 3); int fseek(FAR FILE *stream, long int offset, int whence); int fseeko(FAR FILE *stream, off_t offset, int whence); int fsetpos(FAR FILE *stream, FAR fpos_t *pos); @@ -174,28 +176,35 @@ int ungetc(int c, FAR FILE *stream); */ void perror(FAR const char *s); -int printf(FAR const IPTR char *fmt, ...); +int printf(FAR const IPTR char *fmt, ...) printflike(1, 2); int putc(int c, FAR FILE *stream); int putchar(int c); int puts(FAR const IPTR char *s); int rename(FAR const char *oldpath, FAR const char *newpath); -int sprintf(FAR char *buf, FAR const IPTR char *fmt, ...); -int asprintf(FAR char **ptr, FAR const IPTR char *fmt, ...); +int sprintf(FAR char *buf, FAR const IPTR char *fmt, ...) + printflike(2, 3); +int asprintf(FAR char **ptr, FAR const IPTR char *fmt, ...) + printflike(2, 3); int snprintf(FAR char *buf, size_t size, - FAR const IPTR char *fmt, ...); -int sscanf(FAR const char *buf, FAR const IPTR char *fmt, ...); + FAR const IPTR char *fmt, ...) printflike(3, 4); +int sscanf(FAR const char *buf, FAR const IPTR char *fmt, ...) + scanflike(2, 3); -int scanf(FAR const IPTR char *fmt, ...); -int vasprintf(FAR char **ptr, FAR const IPTR char *fmt, va_list ap); +int scanf(FAR const IPTR char *fmt, ...) scanflike(1, 2); +int vasprintf(FAR char **ptr, FAR const IPTR char *fmt, va_list ap) + printflike(2, 0); int vfprintf(FAR FILE *stream, FAR const IPTR char *fmt, - va_list ap); -int vfscanf(FAR FILE *stream, FAR const IPTR char *fmt, va_list ap); -int vprintf(FAR const IPTR char *fmt, va_list ap); -int vscanf(FAR const IPTR char *fmt, va_list ap); + va_list ap) printflike(2, 0); +int vfscanf(FAR FILE *stream, FAR const IPTR char *fmt, va_list ap) + scanflike(2, 0); +int vprintf(FAR const IPTR char *fmt, va_list ap) printflike(1, 0); +int vscanf(FAR const IPTR char *fmt, va_list ap) scanflike(1, 0); int vsnprintf(FAR char *buf, size_t size, FAR const IPTR char *fmt, - va_list ap); -int vsprintf(FAR char *buf, FAR const IPTR char *fmt, va_list ap); -int vsscanf(FAR const char *buf, FAR const IPTR char *fmt, va_list ap); + va_list ap) printflike(3, 0); +int vsprintf(FAR char *buf, FAR const IPTR char *fmt, va_list ap) + printflike(2, 0); +int vsscanf(FAR const char *buf, FAR const IPTR char *fmt, va_list ap) + scanflike(2, 0); /* Operations on file descriptors including: * @@ -205,8 +214,9 @@ int vsscanf(FAR const char *buf, FAR const IPTR char *fmt, va_list ap); */ FAR FILE *fdopen(int fd, FAR const char *type); -int dprintf(int fd, FAR const IPTR char *fmt, ...); -int vdprintf(int fd, FAR const IPTR char *fmt, va_list ap); +int dprintf(int fd, FAR const IPTR char *fmt, ...) printflike(2, 3); +int vdprintf(int fd, FAR const IPTR char *fmt, va_list ap) + printflike(2, 0); /* Operations on paths */ diff --git a/include/sys/epoll.h b/include/sys/epoll.h index 60e1a3f404b..35685044779 100644 --- a/include/sys/epoll.h +++ b/include/sys/epoll.h @@ -74,6 +74,10 @@ enum EPOLL_EVENTS #define EPOLLERR EPOLLERR EPOLLHUP = POLLHUP, #define EPOLLHUP EPOLLHUP + EPOLLRDHUP = 0x2000, +#define EPOLLRDHUP EPOLLRDHUP + EPOLLWAKEUP = 1u << 29, +#define EPOLLWAKEUP EPOLLWAKEUP EPOLLONESHOT = 1u << 30, #define EPOLLONESHOT EPOLLONESHOT }; diff --git a/libs/libc/Kconfig b/libs/libc/Kconfig index 3c271532962..0496f030df2 100644 --- a/libs/libc/Kconfig +++ b/libs/libc/Kconfig @@ -6,6 +6,7 @@ comment "Standard C Library Options" source libs/libc/stdio/Kconfig +source libs/libc/audio/Kconfig source libs/libc/math/Kconfig source libs/libc/machine/Kconfig source libs/libc/stdlib/Kconfig diff --git a/libs/libc/Makefile b/libs/libc/Makefile index ca0d4122bc1..8371b115200 100644 --- a/libs/libc/Makefile +++ b/libs/libc/Makefile @@ -149,28 +149,36 @@ endif # Context -context: +context:: ifeq ($(CONFIG_LIB_ZONEINFO_ROMFS),y) $(Q) $(MAKE) -C zoneinfo context BIN=$(BIN) endif # Dependencies +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, bin/Make.dep, $^) + $(call DELFILE, $^) + +makekdepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, kbin/Make.dep, $^) + $(call DELFILE, $^) + .depend: Makefile $(SRCS) $(TOPDIR)$(DELIM).config - $(Q) $(MKDEP) --obj-path bin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >bin/Make.dep + $(Q) $(MAKE) makedepfile ifneq ($(CONFIG_BUILD_FLAT),y) - $(Q) $(MKDEP) --obj-path kbin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) $(KDEFINE) -- $(SRCS) >kbin/Make.dep + $(Q) $(MAKE) makekdepfile CFLAGS="$(CFLAGS) $(KDEFINE)" endif ifeq ($(CONFIG_LIB_ZONEINFO_ROMFS),y) $(Q) $(MAKE) -C zoneinfo depend BIN=$(BIN) endif $(Q) touch $@ -depend: .depend +depend:: .depend # Clean most derived files, retaining the configuration -clean: +clean:: $(Q) $(MAKE) -C bin clean $(Q) $(MAKE) -C kbin clean $(Q) $(MAKE) -C zoneinfo clean BIN=$(BIN) @@ -180,7 +188,7 @@ clean: # Deep clean -- removes all traces of the configuration -distclean: clean +distclean:: clean $(Q) $(MAKE) -C bin distclean $(Q) $(MAKE) -C kbin distclean $(Q) $(MAKE) -C zoneinfo distclean BIN=$(BIN) diff --git a/libs/libc/audio/Kconfig b/libs/libc/audio/Kconfig new file mode 100644 index 00000000000..df8024422e0 --- /dev/null +++ b/libs/libc/audio/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + + +source libs/libc/audio/libsrc/Kconfig diff --git a/libs/libc/audio/Make.defs b/libs/libc/audio/Make.defs index 33ea6e97406..ae41ee2b77c 100644 --- a/libs/libc/audio/Make.defs +++ b/libs/libc/audio/Make.defs @@ -36,6 +36,8 @@ ifeq ($(CONFIG_AUDIO),y) CSRCS += lib_buffer.c +include audio/libsrc/Make.defs + # Add the audio/ directory to the build DEPPATH += --dep-path audio diff --git a/libs/libc/audio/libsrc/Kconfig b/libs/libc/audio/libsrc/Kconfig new file mode 100644 index 00000000000..09f4ab4bbe2 --- /dev/null +++ b/libs/libc/audio/libsrc/Kconfig @@ -0,0 +1,43 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +config AUDIO_SRC + bool "Audio Samplerate Convertor Library" + default n + ---help--- + Enable build for various SRC functions + +if AUDIO_SRC + +choice + prompt "Audio Conversion Quality" + default SINC_FAST_CONVERTER + ---help--- + Audio Conversion Quality options: + Slowest conversion speed with best quality. + Medium conversion speed with medium qulity + Fastest conversion with lowest quality + +config SINC_FAST_CONVERTER + bool "Fastest conversion with lowest quality" + ---help--- + Fastest conversion with lowest quality. + Suitable for most boards due to resource constrains. + +config SINC_MEDIUM_CONVERTER + bool "Medium conversion speed with medium qulity" + ---help--- + Medium conversion speed with medium qulity. + Not suitable for most boards due to resource constrains. + +config SINC_BEST_CONVERTER + bool "Slowest conversion speed with best quality" + ---help--- + Slowest conversion speed with best quality. + Not suitable for most boards due to resource constrains. + +endchoice + +endif # LIBSRC diff --git a/libs/libc/audio/libsrc/Make.defs b/libs/libc/audio/libsrc/Make.defs new file mode 100644 index 00000000000..a2d2756d538 --- /dev/null +++ b/libs/libc/audio/libsrc/Make.defs @@ -0,0 +1,62 @@ +############################################################################ +# audio/libsrc/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +ifeq ($(CONFIG_AUDIO_SRC),y) + +PACKAGE=libsamplerate +VERSION=0.1.9 + +libsamplerate: + $(Q) wget https://codeload.github.com/libsndfile/libsamplerate/zip/master -O libsamplerate.zip + $(Q) unzip -o libsamplerate.zip + $(Q) mv libsamplerate-master libsamplerate + $(Q) cp -rf libsamplerate/src/samplerate.h $(TOPDIR)$(DELIM)include$(DELIM)nuttx$(DELIM)audio$(DELIM) + +context:: libsamplerate + +CSRCS += samplerate.c +CSRCS += src_sinc.c +CSRCS += src_linear.c +CSRCS += src_zoh.c + +CFLAGS += -DPACKAGE=\"$(PACKAGE)\" -DVERSION=\"$(VERSION)\" + +ifeq ($(CONFIG_SINC_FAST_CONVERTER),y) +CFLAGS += -DENABLE_SINC_FAST_CONVERTER +endif + +ifeq ($(CONFIG_SINC_MEDIUM_CONVERTER),y) +CFLAGS += -DENABLE_SINC_MEDIUM_CONVERTER +endif + +ifeq ($(CONFIG_SINC_BEST_CONVERTER),y) +CFLAGS += -DENABLE_SINC_BEST_CONVERTER +endif + +VPATH += libsamplerate/src +SUBDIRS += libsamplerate/src +DEPPATH += --dep-path libsamplerate/src + +distclean:: + $(call DELDIR, $(TOPDIR)$(DELIM)include$(DELIM)nuttx$(DELIM)audio$(DELIM)samplerate.h) + $(call DELDIR, libsamplerate) + $(call DELFILE, libsamplerate.zip) + +endif diff --git a/libs/libc/bin/Makefile b/libs/libc/bin/Makefile index ffccef3b484..dedc963fb00 100644 --- a/libs/libc/bin/Makefile +++ b/libs/libc/bin/Makefile @@ -37,7 +37,7 @@ include $(TOPDIR)/Make.defs all: .PHONY: clean distclean - + # Clean Targets: clean: diff --git a/libs/libc/libc.csv b/libs/libc/libc.csv index de0d74860a3..a5395ed6fa3 100644 --- a/libs/libc/libc.csv +++ b/libs/libc/libc.csv @@ -55,6 +55,7 @@ "gethostname","unistd.h","","int","FAR char *","size_t" "getopt","unistd.h","","int","int","FAR char * const []|FAR char * const *","FAR const char *" "getoptargp","unistd.h","","FAR char **" +"getopterrp","unistd.h","","FAR int *" "getoptindp","unistd.h","","FAR int *" "getoptoptp","unistd.h","","FAR int *" "gets","stdio.h","defined(CONFIG_FILE_STREAM)","FAR char *","FAR char *" diff --git a/libs/libc/machine/arm/armv7-m/arch_elf.c b/libs/libc/machine/arm/armv7-m/arch_elf.c index 67153942073..e96af64d069 100644 --- a/libs/libc/machine/arm/armv7-m/arch_elf.c +++ b/libs/libc/machine/arm/armv7-m/arch_elf.c @@ -39,6 +39,7 @@ #include +#include #include #include #include @@ -80,7 +81,8 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if (ehdr->e_ident[EI_CLASS] != ELFCLASS32) { - berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]); + berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", + ehdr->e_ident[EI_CLASS]); return false; } @@ -92,11 +94,13 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB) #endif { - berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]); + berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n", + ehdr->e_ident[EI_DATA]); return false; } /* TODO: Check ABI here. */ + return true; } @@ -154,8 +158,10 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, case R_ARM_CALL: case R_ARM_JUMP24: { - binfo("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%p' st_value=%08lx\n", - ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr), + binfo("Performing PC24 [%" PRId32 "] link at " + "addr %08lx [%08lx] to sym '%p' st_value=%08lx\n", + ELF32_R_TYPE(rel->r_info), (long)addr, + (long)(*(uint32_t *)addr), sym, (long)sym->st_value); offset = (*(uint32_t *)addr & 0x00ffffff) << 2; @@ -165,9 +171,11 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, } offset += sym->st_value - addr; - if (offset & 3 || offset < (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000) + if (offset & 3 || offset < (int32_t) 0xfe000000 || + offset >= (int32_t) 0x02000000) { - berr("ERROR: ERROR: PC24 [%d] relocation out of range, offset=%08lx\n", + berr("ERROR: ERROR: PC24 [%" PRId32 "] " + "relocation out of range, offset=%08lx\n", ELF32_R_TYPE(rel->r_info), offset); return -EINVAL; @@ -183,8 +191,10 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, case R_ARM_ABS32: case R_ARM_TARGET1: /* New ABI: TARGET1 always treated as ABS32 */ { - binfo("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n", - (long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value); + binfo("Performing ABS32 link " + "at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n", + (long)addr, (long)(*(uint32_t *)addr), + sym, (long)sym->st_value); *(uint32_t *)addr += sym->st_value; } @@ -194,8 +204,10 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, case R_ARM_TARGET2: /* TARGET2 is a platform-specific relocation: gcc-arm-none-eabi * performs a self relocation */ { - binfo("Performing TARGET2 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n", - (long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value); + binfo("Performing TARGET2 link " + "at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n", + (long)addr, (long)(*(uint32_t *)addr), + sym, (long)sym->st_value); *(uint32_t *)addr += sym->st_value - addr; } @@ -243,8 +255,10 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, upper_insn = (uint32_t)(*(uint16_t *)addr); lower_insn = (uint32_t)(*(uint16_t *)(addr + 2)); - binfo("Performing THM_JUMP24 [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n", - ELF32_R_TYPE(rel->r_info), (long)addr, (int)upper_insn, (int)lower_insn, + binfo("Performing THM_JUMP24 [%" PRId32 "] link " + "at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n", + ELF32_R_TYPE(rel->r_info), (long)addr, + (int)upper_insn, (int)lower_insn, sym, (long)sym->st_value); /* Extract the 25-bit offset from the 32-bit instruction: @@ -277,8 +291,9 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, /* And perform the relocation */ - binfo(" S=%d J1=%d J2=%d offset=%08lx branch target=%08lx\n", - S, J1, J2, (long)offset, offset + sym->st_value - addr); + binfo(" S=%" PRId32 " J1=%" PRId32 " J2=%" PRId32 + " offset=%08" PRIx32 " branch target=%08lx\n", + S, J1, J2, offset, offset + sym->st_value - addr); offset += sym->st_value - addr; @@ -288,7 +303,8 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, if (ELF32_ST_TYPE(sym->st_info) == STT_FUNC && (offset & 1) == 0) { - berr("ERROR: ERROR: JUMP24 [%d] requires odd offset, offset=%08lx\n", + berr("ERROR: ERROR: JUMP24 [%" PRId32 "] " + "requires odd offset, offset=%08lx\n", ELF32_R_TYPE(rel->r_info), offset); return -EINVAL; @@ -298,7 +314,8 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, if (offset < (int32_t)0xff000000 || offset >= (int32_t)0x01000000) { - berr("ERROR: ERROR: JUMP24 [%d] relocation out of range, branch target=%08lx\n", + berr("ERROR: ERROR: JUMP24 [%" PRId32 "] " + "relocation out of range, branch target=%08lx\n", ELF32_R_TYPE(rel->r_info), offset); return -EINVAL; @@ -312,14 +329,17 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, J1 = S ^ (~(offset >> 23) & 1); J2 = S ^ (~(offset >> 22) & 1); - upper_insn = ((upper_insn & 0xf800) | (S << 10) | ((offset >> 12) & 0x03ff)); + upper_insn = ((upper_insn & 0xf800) | (S << 10) | + ((offset >> 12) & 0x03ff)); *(uint16_t *)addr = (uint16_t)upper_insn; - lower_insn = ((lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | ((offset >> 1) & 0x07ff)); + lower_insn = ((lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | + ((offset >> 1) & 0x07ff)); *(uint16_t *)(addr + 2) = (uint16_t)lower_insn; - binfo(" S=%d J1=%d J2=%d insn [%04x %04x]\n", - S, J1, J2, (int)upper_insn, (int)lower_insn); + binfo(" S=%" PRId32 " J1=%" PRId32 " J2=%" PRId32 + " insn [%04" PRIx32 " %04" PRIx32 "]\n", + S, J1, J2, upper_insn, lower_insn); } break; @@ -340,8 +360,10 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, case R_ARM_PREL31: { - binfo("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n", - (long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value); + binfo("Performing PREL31 link " + "at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n", + (long)addr, (long)(*(uint32_t *)addr), + sym, (long)sym->st_value); offset = *(uint32_t *)addr + sym->st_value - addr; *(uint32_t *)addr = offset & 0x7fffffff; @@ -351,8 +373,10 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, case R_ARM_MOVW_ABS_NC: case R_ARM_MOVT_ABS: { - binfo("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n", - ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr), + binfo("Performing MOVx_ABS [%" PRId32 "] link " + "at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n", + ELF32_R_TYPE(rel->r_info), (long)addr, + (long)(*(uint32_t *)addr), sym, (long)sym->st_value); offset = *(uint32_t *)addr; @@ -405,8 +429,10 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, upper_insn = (uint32_t)(*(uint16_t *)addr); lower_insn = (uint32_t)(*(uint16_t *)(addr + 2)); - binfo("Performing THM_MOVx [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n", - ELF32_R_TYPE(rel->r_info), (long)addr, (int)upper_insn, (int)lower_insn, + binfo("Performing THM_MOVx [%" PRId32 "] link " + "at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n", + ELF32_R_TYPE(rel->r_info), (long)addr, + (int)upper_insn, (int)lower_insn, sym, (long)sym->st_value); /* Extract the 16-bit offset from the 32-bit instruction */ @@ -423,8 +449,9 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, offset += sym->st_value; - /* Update the immediate value in the instruction. For MOVW we want the bottom - * 16-bits; for MOVT we want the top 16-bits. + /* Update the immediate value in the instruction. + * For MOVW we want the bottom 16-bits; for MOVT we want + * the top 16-bits. */ if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS) @@ -457,7 +484,8 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, if (ELF32_ST_TYPE(sym->st_info) == STT_FUNC && (offset & 1) == 0) { - berr("ERROR: JUMP11 [%d] requires odd offset, offset=%08lx\n", + berr("ERROR: JUMP11 [%" PRId32 "] " + "requires odd offset, offset=%08lx\n", ELF32_R_TYPE(rel->r_info), offset); return -EINVAL; @@ -467,7 +495,8 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, if (offset < (int32_t)0xfffff800 || offset >= (int32_t)0x0800) { - berr("ERROR: JUMP11 [%d] relocation out of range, branch taget=%08lx\n", + berr("ERROR: JUMP11 [%" PRId32 "] " + "relocation out of range, branch taget=%08lx\n", ELF32_R_TYPE(rel->r_info), offset); return -EINVAL; @@ -481,7 +510,8 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, break; default: - berr("ERROR: Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info)); + berr("ERROR: Unsupported relocation: %" PRId32 "\n", + ELF32_R_TYPE(rel->r_info)); return -EINVAL; } diff --git a/libs/libc/machine/risc-v/rv64/arch_elf.c b/libs/libc/machine/risc-v/rv64/arch_elf.c index d27ac924392..acc02435d28 100644 --- a/libs/libc/machine/risc-v/rv64/arch_elf.c +++ b/libs/libc/machine/risc-v/rv64/arch_elf.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -222,7 +223,7 @@ bool up_checkarch(FAR const Elf64_Ehdr *ehdr) if ((ehdr->e_entry & 1) != 0) { - berr("ERROR: Entry point is not properly aligned: %08x\n", + berr("ERROR: Entry point is not properly aligned: %08" PRIx64 "\n", ehdr->e_entry); } @@ -274,9 +275,9 @@ int up_relocateadd(FAR const Elf64_Rela *rel, FAR const Elf64_Sym *sym, { /* NOTE: RELAX has no symbol, so just return */ - binfo("%s at %08lx [%08x] \n", + binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] \n", _get_rname(relotype), - (long)addr, _get_val((uint16_t *)addr)); + addr, _get_val((uint16_t *)addr)); return OK; } @@ -292,10 +293,11 @@ int up_relocateadd(FAR const Elf64_Rela *rel, FAR const Elf64_Sym *sym, { case R_RISCV_64: { - binfo("%s at %08lx [%08x] to sym=%p st_value=%08lx\n", + binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] " + "to sym=%p st_value=%08" PRIx64 "\n", _get_rname(relotype), - (long)addr, _get_val((uint16_t *)addr), - sym, (long)sym->st_value); + addr, _get_val((uint16_t *)addr), + sym, sym->st_value); _set_val((uint16_t *)addr, (uint32_t)(sym->st_value + rel->r_addend)); @@ -305,10 +307,11 @@ int up_relocateadd(FAR const Elf64_Rela *rel, FAR const Elf64_Sym *sym, case R_RISCV_PCREL_LO12_I: case R_RISCV_PCREL_LO12_S: { - binfo("%s at %08lx [%08x] to sym=%p st_value=%08lx\n", + binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] " + "to sym=%p st_value=%08" PRIx64 "\n", _get_rname(relotype), - (long)addr, _get_val((uint16_t *)addr), - sym, (long)sym->st_value); + addr, _get_val((uint16_t *)addr), + sym, sym->st_value); /* NOTE: imm value for mv has been adjusted in previous HI20 */ } @@ -317,10 +320,11 @@ int up_relocateadd(FAR const Elf64_Rela *rel, FAR const Elf64_Sym *sym, case R_RISCV_PCREL_HI20: case R_RISCV_CALL: { - binfo("%s at %08lx [%08x] to sym=%p st_value=%08lx\n", + binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] " + "to sym=%p st_value=%08" PRIx64 "\n", _get_rname(relotype), - (long)addr, _get_val((uint16_t *)addr), - sym, (long)sym->st_value); + addr, _get_val((uint16_t *)addr), + sym, sym->st_value); offset = (long)sym->st_value - (long)addr; @@ -341,7 +345,7 @@ int up_relocateadd(FAR const Elf64_Rela *rel, FAR const Elf64_Sym *sym, (((int32_t)imm_lo >> 5) << 25) + (((int32_t)imm_lo & 0x1f) << 7); - binfo("imm_lo=%d (%x), val=%x \n", imm_lo, imm_lo, val); + binfo("imm_lo=%ld (%lx), val=%x \n", imm_lo, imm_lo, val); _add_val((uint16_t *)(addr + 4), val); } @@ -370,7 +374,7 @@ int up_relocateadd(FAR const Elf64_Rela *rel, FAR const Elf64_Sym *sym, ASSERT(offset && val); - binfo("offset for Bx=%ld (0x%x) (val=0x%08x) already set! \n", + binfo("offset for Bx=%ld (0x%lx) (val=0x%08x) already set! \n", offset, offset, val); } break; @@ -393,7 +397,7 @@ int up_relocateadd(FAR const Elf64_Rela *rel, FAR const Elf64_Sym *sym, ASSERT(offset && val); - binfo("offset for C.J=%ld (0x%x) (val=0x%04x) already set! \n", + binfo("offset for C.J=%ld (0x%lx) (val=0x%04x) already set! \n", offset, offset, val); } break; @@ -416,13 +420,13 @@ int up_relocateadd(FAR const Elf64_Rela *rel, FAR const Elf64_Sym *sym, ASSERT(offset && val); - binfo("offset for C.Bx=%ld (0x%x) (val=0x%04x) already set!\n", + binfo("offset for C.Bx=%ld (0x%lx) (val=0x%04x) already set!\n", offset, offset, val); } break; default: - berr("ERROR: Unsupported relocation: %d\n", + berr("ERROR: Unsupported relocation: %" PRId64 "\n", ELF64_R_TYPE(rel->r_info)); ASSERT(false); return -EINVAL; diff --git a/libs/libc/misc/lib_stream.c b/libs/libc/misc/lib_stream.c index 9a222cab536..cd07f5e4819 100644 --- a/libs/libc/misc/lib_stream.c +++ b/libs/libc/misc/lib_stream.c @@ -85,6 +85,15 @@ void lib_stream_initialize(FAR struct task_group_s *group) _SEM_INIT(&list->sl_sem, 0, 1); list->sl_head = NULL; list->sl_tail = NULL; + + /* Initialize stdin, stdout and stderr stream */ + + list->sl_std[0].fs_fd = -1; + lib_sem_initialize(&list->sl_std[0]); + list->sl_std[1].fs_fd = -1; + lib_sem_initialize(&list->sl_std[1]); + list->sl_std[2].fs_fd = -1; + lib_sem_initialize(&list->sl_std[2]); } #endif /* CONFIG_FILE_STREAM */ @@ -147,6 +156,14 @@ void lib_stream_release(FAR struct task_group_s *group) group_free(group, stream); } } + + /* Destroy stdin, stdout and stderr stream */ + +#ifndef CONFIG_STDIO_DISABLE_BUFFERING + _SEM_DESTROY(&list->sl_std[0].fs_sem); + _SEM_DESTROY(&list->sl_std[1].fs_sem); + _SEM_DESTROY(&list->sl_std[2].fs_sem); +#endif } #endif /* CONFIG_FILE_STREAM */ diff --git a/libs/libc/modlib/modlib_bind.c b/libs/libc/modlib/modlib_bind.c index 4c1b9e0f4c1..b9de73acf89 100644 --- a/libs/libc/modlib/modlib_bind.c +++ b/libs/libc/modlib/modlib_bind.c @@ -301,8 +301,10 @@ static int modlib_relocate(FAR struct module_s *modp, rel->r_offset > dstsec->sh_size - sizeof(uint32_t)) { berr("ERROR: Section %d reloc %d: " - "Relocation address out of range, offset %d size %d\n", - relidx, i, rel->r_offset, dstsec->sh_size); + "Relocation address out of range, " + "offset %" PRIuPTR " size %ju\n", + relidx, i, (uintptr_t)rel->r_offset, + (uintmax_t)dstsec->sh_size); ret = -EINVAL; break; } @@ -487,8 +489,10 @@ static int modlib_relocateadd(FAR struct module_s *modp, rela->r_offset > dstsec->sh_size - sizeof(uint32_t)) { berr("ERROR: Section %d reloc %d: " - "Relocation address out of range, offset %d size %d\n", - relidx, i, rela->r_offset, dstsec->sh_size); + "Relocation address out of range, " + "offset %" PRIuPTR " size %ju\n", + relidx, i, (uintptr_t)rela->r_offset, + (uintmax_t)dstsec->sh_size); ret = -EINVAL; break; } diff --git a/libs/libc/modlib/modlib_symbols.c b/libs/libc/modlib/modlib_symbols.c index 3082db2291b..3d3fd437e6d 100644 --- a/libs/libc/modlib/modlib_symbols.c +++ b/libs/libc/modlib/modlib_symbols.c @@ -24,6 +24,8 @@ #include +#include +#include #include #include #include @@ -366,7 +368,7 @@ int modlib_symvalue(FAR struct module_s *modp, (FAR void *)&exportinfo); if (ret < 0) { - berr("ERROR: modlib_symcallback failed: \n", ret); + berr("ERROR: modlib_symcallback failed: %d\n", ret); return ret; } @@ -401,9 +403,11 @@ int modlib_symvalue(FAR struct module_s *modp, * entry */ - binfo("SHN_UNDEF: name=%s %08x+%08x=%08x\n", - loadinfo->iobuffer, sym->st_value, symbol->sym_value, - sym->st_value + symbol->sym_value); + binfo("SHN_UNDEF: name=%s " + "%08" PRIxPTR "+%08" PRIxPTR "=%08" PRIxPTR "\n", + loadinfo->iobuffer, + (uintptr_t)sym->st_value, (uintptr_t)symbol->sym_value, + (uintptr_t)(sym->st_value + symbol->sym_value)); sym->st_value += ((uintptr_t)symbol->sym_value); } @@ -413,8 +417,9 @@ int modlib_symvalue(FAR struct module_s *modp, { secbase = loadinfo->shdr[sym->st_shndx].sh_addr; - binfo("Other: %08x+%08x=%08x\n", - sym->st_value, secbase, sym->st_value + secbase); + binfo("Other: %08" PRIxPTR "+%08" PRIxPTR "=%08" PRIxPTR "\n", + (uintptr_t)sym->st_value, secbase, + (uintptr_t)(sym->st_value + secbase)); sym->st_value += secbase; } diff --git a/libs/libc/netdb/lib_dnsquery.c b/libs/libc/netdb/lib_dnsquery.c index dd07768d60a..bcf777dbecd 100644 --- a/libs/libc/netdb/lib_dnsquery.c +++ b/libs/libc/netdb/lib_dnsquery.c @@ -487,10 +487,10 @@ static int dns_recv_response(int sd, FAR union dns_addr_u *addr, int naddr, nameptr += 10 + 4; ninfo("IPv4 address: %d.%d.%d.%d\n", - (ans->u.ipv4.s_addr) & 0xff, - (ans->u.ipv4.s_addr >> 8) & 0xff, - (ans->u.ipv4.s_addr >> 16) & 0xff, - (ans->u.ipv4.s_addr >> 24) & 0xff); + (int)((ans->u.ipv4.s_addr) & 0xff), + (int)((ans->u.ipv4.s_addr >> 8) & 0xff), + (int)((ans->u.ipv4.s_addr >> 16) & 0xff), + (int)((ans->u.ipv4.s_addr >> 24) & 0xff)); inaddr = &addr[naddr_read].ipv4; inaddr->sin_family = AF_INET; diff --git a/libs/libc/pthread/pthread_attr_setstacksize.c b/libs/libc/pthread/pthread_attr_setstacksize.c index 6e7a55f0fe4..b820bdb0739 100644 --- a/libs/libc/pthread/pthread_attr_setstacksize.c +++ b/libs/libc/pthread/pthread_attr_setstacksize.c @@ -68,7 +68,7 @@ int pthread_attr_setstacksize(FAR pthread_attr_t *attr, size_t stacksize) { int ret; - linfo("attr=0x%p stacksize=%ld\n", attr, stacksize); + linfo("attr=0x%p stacksize=%zu\n", attr, stacksize); if (!attr || stacksize < PTHREAD_STACK_MIN) { diff --git a/libs/libc/stdio/lib_libvsprintf.c b/libs/libc/stdio/lib_libvsprintf.c index 6f38a0dbc68..7f147cf7923 100644 --- a/libs/libc/stdio/lib_libvsprintf.c +++ b/libs/libc/stdio/lib_libvsprintf.c @@ -375,7 +375,9 @@ static int vsprintf_internal(FAR struct lib_outstream_s *stream, } } - if (c == 'z') + /* Note: On Nuttx, ptrdiff_t == intptr_t == ssize_t. */ + + if (c == 'z' || c == 't') { switch (sizeof(size_t)) { diff --git a/libs/libc/stdlib/lib_strtoull.c b/libs/libc/stdlib/lib_strtoull.c index 5f8265026a9..735e90c60d1 100644 --- a/libs/libc/stdlib/lib_strtoull.c +++ b/libs/libc/stdlib/lib_strtoull.c @@ -68,7 +68,8 @@ * ****************************************************************************/ -unsigned long long strtoull(FAR const char *nptr, FAR char **endptr, int base) +unsigned long long strtoull(FAR const char *nptr, + FAR char **endptr, int base) { unsigned long long accum = 0; unsigned long long limit; diff --git a/libs/libc/time/lib_strftime.c b/libs/libc/time/lib_strftime.c index 46165a57c1b..c68d72fbc9a 100644 --- a/libs/libc/time/lib_strftime.c +++ b/libs/libc/time/lib_strftime.c @@ -77,7 +77,8 @@ static const char * const g_abbrev_wdayname[7] = static const char * const g_wdayname[7] = { - "Sunday", "Monday", "Tuesday", "Wednesday", "Thursday", "Friday", "Saturday" + "Sunday", "Monday", "Tuesday", "Wednesday", "Thursday", "Friday", + "Saturday" }; static const char * const g_abbrev_monthname[12] = @@ -120,8 +121,10 @@ static const char * const g_monthname[12] = * %e Like %d, the day of the month as a decimal number, but a leading * zero is replaced by a space. * %h Equivalent to %b. (SU) - * %H The hour as a decimal number using a 24-hour clock (range 00 to 23). - * %I The hour as a decimal number using a 12-hour clock (range 01 to 12). + * %H The hour as a decimal number using a 24-hour clock + * (range 00 to 23). + * %I The hour as a decimal number using a 12-hour clock + * (range 01 to 12). * %j The day of the year as a decimal number (range 001 to 366). * %k The hour (24-hour clock) as a decimal number (range 0 to 23); * single digits are preceded by a blank. (See also %H.) (TZ) @@ -207,7 +210,9 @@ size_t strftime(FAR char *s, size_t max, FAR const char *format, case 'h': - /* %b: The abbreviated month name according to the current locale. */ + /* %b: The abbreviated month name according to the current + * locale. + */ case 'b': { @@ -231,7 +236,9 @@ size_t strftime(FAR char *s, size_t max, FAR const char *format, } break; - /* %y: The year as a decimal number without a century (range 00 to 99). */ + /* %y: The year as a decimal number without a century + * (range 00 to 99). + */ case 'y': { @@ -247,7 +254,9 @@ size_t strftime(FAR char *s, size_t max, FAR const char *format, } break; - /* %d: The day of the month as a decimal number (range 01 to 31). */ + /* %d: The day of the month as a decimal number + * (range 01 to 31). + */ case 'd': { @@ -255,8 +264,8 @@ size_t strftime(FAR char *s, size_t max, FAR const char *format, } break; - /* %e: Like %d, the day of the month as a decimal number, but a leading - * zero is replaced by a space. + /* %e: Like %d, the day of the month as a decimal number, but + * a leading zero is replaced by a space. */ case 'e': @@ -265,7 +274,9 @@ size_t strftime(FAR char *s, size_t max, FAR const char *format, } break; - /* %H: The hour as a decimal number using a 24-hour clock (range 00 to 23). */ + /* %H: The hour as a decimal number using a 24-hour clock + * (range 00 to 23). + */ case 'H': { @@ -273,7 +284,9 @@ size_t strftime(FAR char *s, size_t max, FAR const char *format, } break; - /* %I: The hour as a decimal number using a 12-hour clock (range 01 to 12). */ + /* %I: The hour as a decimal number using a 12-hour clock + * (range 01 to 12). + */ case 'I': { @@ -281,21 +294,23 @@ size_t strftime(FAR char *s, size_t max, FAR const char *format, } break; - /* %j: The day of the year as a decimal number (range 001 to 366). */ + /* %j: The day of the year as a decimal number + * (range 001 to 366). + */ case 'j': { if (tm->tm_mon < 12) { value = clock_daysbeforemonth(tm->tm_mon, - clock_isleapyear(tm->tm_year)) + - tm->tm_mday; + clock_isleapyear(tm->tm_year)) + tm->tm_mday; len = snprintf(dest, chleft, "%03d", value); } } break; - /* %k: The hour (24-hour clock) as a decimal number (range 0 to 23); + /* %k: The hour (24-hour clock) as a decimal number + * (range 0 to 23); * single digits are preceded by a blank. */ @@ -305,7 +320,8 @@ size_t strftime(FAR char *s, size_t max, FAR const char *format, } break; - /* %l: The hour (12-hour clock) as a decimal number (range 1 to 12); + /* %l: The hour (12-hour clock) as a decimal number + * (range 1 to 12); * single digits are preceded by a blank. */ @@ -374,18 +390,20 @@ size_t strftime(FAR char *s, size_t max, FAR const char *format, } break; - /* %s: The number of seconds since the Epoch, that is, since 1970-01-01 - * 00:00:00 UTC. Hmmm... mktime argume is not 'const'. + /* %s: The number of seconds since the Epoch, that is, + * since 1970-01-01 00:00:00 UTC. + * Hmmm... mktime argume is not 'const'. */ case 's': { - len = snprintf(dest, chleft, "%d", mktime((FAR struct tm *)tm)); + len = snprintf(dest, chleft, "%ju", + (uintmax_t)mktime((FAR struct tm *)tm)); } break; - /* %S: The second as a decimal number (range 00 to 60). (The range is - * up to 60 to allow for occasional leap seconds.) + /* %S: The second as a decimal number (range 00 to 60). + * (The range is up to 60 to allow for occasional leap seconds.) */ case 'S': diff --git a/libs/libc/unistd/Make.defs b/libs/libc/unistd/Make.defs index 40410dbd810..3955fe87e5f 100644 --- a/libs/libc/unistd/Make.defs +++ b/libs/libc/unistd/Make.defs @@ -36,9 +36,9 @@ # Add the unistd C files to the build CSRCS += lib_access.c lib_daemon.c lib_swab.c lib_pathconf.c lib_sysconf.c -CSRCS += lib_getopt.c lib_getoptargp.c lib_getoptindp.c lib_getoptoptp.c -CSRCS += lib_alarm.c lib_fstatvfs.c lib_statvfs.c lib_sleep.c lib_usleep.c -CSRCS += lib_seteuid.c lib_setegid.c lib_geteuid.c lib_getegid.c +CSRCS += lib_getopt.c lib_getoptargp.c lib_getopterrp.c lib_getoptindp.c +CSRCS += lib_getoptoptp.c lib_alarm.c lib_fstatvfs.c lib_statvfs.c lib_sleep.c +CSRCS += lib_usleep.c lib_seteuid.c lib_setegid.c lib_geteuid.c lib_getegid.c CSRCS += lib_setreuid.c lib_setregid.c CSRCS += lib_getrusage.c lib_utimes.c CSRCS += lib_setrlimit.c lib_getrlimit.c diff --git a/libs/libc/unistd/lib_getopterrp.c b/libs/libc/unistd/lib_getopterrp.c new file mode 100644 index 00000000000..333e82b131e --- /dev/null +++ b/libs/libc/unistd/lib_getopterrp.c @@ -0,0 +1,45 @@ +/**************************************************************************** + * libs/libc/unistd/lib_getopterrp.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: getopterrp + * + * Description: + * Returns a pointer to opterr. This function is only used for external + * modules that need to access the base, global variable, opterr. + * + ****************************************************************************/ + +FAR int *getopterrp(void) +{ + return &opterr; +} diff --git a/libs/libc/uuid/lib_uuid_from_string.c b/libs/libc/uuid/lib_uuid_from_string.c index 4b6e962a2ac..6dd4329f988 100644 --- a/libs/libc/uuid/lib_uuid_from_string.c +++ b/libs/libc/uuid/lib_uuid_from_string.c @@ -22,6 +22,7 @@ * Included Files ****************************************************************************/ +#include #include #include #include @@ -79,7 +80,10 @@ void uuid_from_string(const char *s, uuid_t *u, uint32_t *status) } n = sscanf(s, - "%8x-%4hx-%4hx-%2hhx%2hhx-%2hhx%2hhx%2hhx%2hhx%2hhx%2hhx", + "%08" SCNx32 "-%04" SCNx16 "-%04" SCNx16 + "-%02" SCNx8 "%02" SCNx8 + "-%02" SCNx8 "%02" SCNx8 "%02" SCNx8 + "%02" SCNx8 "%02" SCNx8 "%02" SCNx8, &u->time_low, &u->time_mid, &u->time_hi_and_version, &u->clock_seq_hi_and_reserved, &u->clock_seq_low, &u->node[0], &u->node[1], &u->node[2], &u->node[3], &u->node[4], &u->node[5]); diff --git a/libs/libc/uuid/lib_uuid_to_string.c b/libs/libc/uuid/lib_uuid_to_string.c index dc8c5613480..e6eb1c77101 100644 --- a/libs/libc/uuid/lib_uuid_to_string.c +++ b/libs/libc/uuid/lib_uuid_to_string.c @@ -64,7 +64,10 @@ void uuid_to_string(const uuid_t *u, char **s, uint32_t *status) } c = asprintf(s, - "%08x-%04x-%04x-%02x%02x-%02x%02x%02x%02x%02x%02x", + "%08" PRIx32 "-%04" PRIx16 "-%04" PRIx16 + "-%02" PRIx8 "%02" PRIx8 + "-%02" PRIx8 "%02" PRIx8 "%02" PRIx8 + "%02" PRIx8 "%02" PRIx8 "%02" PRIx8, u->time_low, u->time_mid, u->time_hi_and_version, u->clock_seq_hi_and_reserved, u->clock_seq_low, u->node[0], u->node[1], u->node[2], u->node[3], u->node[4], u->node[5]); diff --git a/libs/libc/zoneinfo/Makefile b/libs/libc/zoneinfo/Makefile index d6e66361c37..44e3df0c740 100644 --- a/libs/libc/zoneinfo/Makefile +++ b/libs/libc/zoneinfo/Makefile @@ -118,8 +118,12 @@ context: .tzbuilt romfs # Create dependencies +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) + .depend: Makefile $(SRCS) $(TOPDIR)$(DELIM).config - $(Q) $(MKDEP) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile $(Q) touch $@ depend: .depend diff --git a/libs/libdsp/Makefile b/libs/libdsp/Makefile index bc3be54cb75..6d1ed1a88a1 100644 --- a/libs/libdsp/Makefile +++ b/libs/libdsp/Makefile @@ -49,9 +49,13 @@ $(COBJS): %$(OBJEXT): %.c $(BIN): $(OBJS) $(call ARCHIVE, $@, $(OBJS)) + +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) .depend: Makefile $(SRCS) $(TOPDIR)$(DELIM).config - $(Q) $(MKDEP) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile $(Q) touch $@ depend: .depend diff --git a/libs/libnx/Makefile b/libs/libnx/Makefile index 86ef567b331..2408eee6abc 100644 --- a/libs/libnx/Makefile +++ b/libs/libnx/Makefile @@ -235,10 +235,18 @@ endif # Dependencies +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, bin/Make.dep, $^) + $(call DELFILE, $^) + +makekdepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, kbin/Make.dep, $^) + $(call DELFILE, $^) + .depend: Makefile gensources $(SRCS) $(TOPDIR)$(DELIM).config - $(Q) $(MKDEP) --obj-path bin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >bin/Make.dep + $(Q) $(MAKE) makedepfile ifneq ($(CONFIG_BUILD_FLAT),y) - $(Q) $(MKDEP) --obj-path kbin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) $(KDEFINE) -- $(SRCS) >kbin/Make.dep + $(Q) $(MAKE) makekdepfile CFLAGS="$(CFLAGS) $(KDEFINE)" endif $(Q) touch $@ diff --git a/libs/libnx/kbin/Makefile b/libs/libnx/kbin/Makefile index e3475231f9c..dd4e30e3c50 100644 --- a/libs/libnx/kbin/Makefile +++ b/libs/libnx/kbin/Makefile @@ -37,7 +37,7 @@ include $(TOPDIR)/Make.defs all: .PHONY: clean distclean - + # Clean Targets: clean: diff --git a/libs/libnx/nxfonts/nxfonts_cache.c b/libs/libnx/nxfonts/nxfonts_cache.c index 316a7e0c06b..0acedc66619 100644 --- a/libs/libnx/nxfonts/nxfonts_cache.c +++ b/libs/libnx/nxfonts/nxfonts_cache.c @@ -587,7 +587,7 @@ static FAR struct nxfonts_fcache_s * { FAR struct nxfonts_fcache_s *fcache; - ginfo("fontid=%p fgcolor=%u bgcolor=%u bpp=%d\n", + ginfo("fontid=%d fgcolor=%u bgcolor=%u bpp=%d\n", fontid, fgcolor, bgcolor, bpp); /* Search for a cache for this font characteristics */ @@ -646,7 +646,7 @@ FCACHE nxf_cache_connect(enum nx_fontid_e fontid, FAR struct nxfonts_fcache_s *priv; int errcode; - ginfo("fontid=%p fgcolor=%u bgcolor=%u bpp=%d maxglyphs=%d\n", + ginfo("fontid=%d fgcolor=%u bgcolor=%u bpp=%d maxglyphs=%d\n", fontid, fgcolor, bgcolor, bpp, maxglyphs); /* Get exclusive access to the font cache list */ diff --git a/libs/libnx/nxglib/nxglib_splitline.c b/libs/libnx/nxglib/nxglib_splitline.c index c73e450c70e..7f5a1f586b9 100644 --- a/libs/libnx/nxglib/nxglib_splitline.c +++ b/libs/libnx/nxglib/nxglib_splitline.c @@ -41,6 +41,7 @@ #include #include +#include #include #include @@ -128,7 +129,8 @@ int nxgl_splitline(FAR struct nxgl_vector_s *vector, b16_t b16y; ginfo("vector: (%d,%d)->(%d,%d) linewidth: %d\n", - vector->pt1.x, vector->pt1.y, vector->pt2.x, vector->pt2.y, linewidth); + vector->pt1.x, vector->pt1.y, vector->pt2.x, vector->pt2.y, + linewidth); /* First, check the linewidth */ @@ -219,7 +221,8 @@ int nxgl_splitline(FAR struct nxgl_vector_s *vector, traps[1].bot.x2 = traps[1].bot.x1; traps[1].bot.y = line.pt2.y; - ginfo("Vertical traps[1]: (%08x,%08x,%d),(%08x,%08x, %d)\n", + ginfo("Vertical traps[1]: (%08" PRIx32 ",%08" PRIx32 ",%d)," + "(%08" PRIx32 ",%08" PRIx32 ", %d)\n", traps[1].top.x1, traps[1].top.x2, traps[1].top.y, traps[1].bot.x1, traps[1].bot.x2, traps[1].bot.y); @@ -255,7 +258,8 @@ int nxgl_splitline(FAR struct nxgl_vector_s *vector, traps[1].bot.x1 = tmp; } - ginfo("Horizontal traps[1]: (%08x,%08x,%d),(%08x,%08x, %d)\n", + ginfo("Horizontal traps[1]: (%08" PRIx32 ",%08" PRIx32 ",%d)," + "(%08" PRIx32 ",%08" PRIx32 ", %d)\n", traps[1].top.x1, traps[1].top.x2, traps[1].top.y, traps[1].bot.x1, traps[1].bot.x2, traps[1].bot.y); @@ -279,29 +283,32 @@ int nxgl_splitline(FAR struct nxgl_vector_s *vector, } /* Applying the line width to the line results in a rotated, rectangle. - * Get the Y offset from an end of the original thin line to a corner of the fat line. + * Get the Y offset from an end of the original thin line to a corner of + * the fat line. * * Angle of line: angle = atan2(iheight, iwidth) * Y offset from line: b16yoffset = linewidth * cos(angle) * - * For near verical lines, b16yoffset is be nearly zero. For near horizontal - * lines, b16yOffset is be about the same as linewidth. + * For near verical lines, b16yoffset is be nearly zero. For near + * horizontal lines, b16yOffset is be about the same as linewidth. */ angle = b16atan2(itob16(iheight), itob16(iwidth)); cosangle = b16cos(angle); b16yoffset = (linewidth * cosangle + 1) >> 1; - /* Get the X offset from an end of the original thin line to a corner of the fat line. + /* Get the X offset from an end of the original thin line to a corner of + * the fat line. * - * For near vertical lines, b16xoffset is about the same as linewidth. For near - * horizontal lines, b16xoffset is nearly zero. + * For near vertical lines, b16xoffset is about the same as linewidth. + * For near horizontal lines, b16xoffset is nearly zero. */ sinangle = b16sin(angle); b16xoffset = (linewidth * sinangle + 1) >> 1; - ginfo("height: %d width: %d angle: %08x b16yoffset: %08x b16xoffset: %08x\n", + ginfo("height: %d width: %d angle: %08" PRIx32 " " + "b16yoffset: %08" PRIx32 " b16xoffset: %08" PRIx32 "\n", iheight, iwidth, angle, b16yoffset, b16xoffset); /* Now we know all four points of the rotated rectangle */ @@ -331,7 +338,10 @@ int nxgl_splitline(FAR struct nxgl_vector_s *vector, quad[2].x = b16x + b16xoffset; quad[3].x = b16x - b16xoffset; - ginfo("Southeast: quad (%08x,%08x),(%08x,%08x),(%08x,%08x),(%08x,%08x)\n", + ginfo("Southeast: quad (%08" PRIx32 ",%08" PRIx32 ")," + "(%08" PRIx32 ",%08" PRIx32 ")," + "(%08" PRIx32 ",%08" PRIx32 ")," + "(%08" PRIx32 ",%08" PRIx32 ")\n", quad[0].x, quad[0].y, quad[1].x, quad[1].y, quad[2].x, quad[2].y, quad[3].x, quad[3].y); @@ -352,29 +362,35 @@ int nxgl_splitline(FAR struct nxgl_vector_s *vector, /* quad[1] is at the bottom left of the triangle. Interpolate * to get the corresponding point on the right side. * - * Interpolation is from quad[0] along the line quad[0]->quad[2] - * which as the same slope as the line (positive) + * Interpolation is from quad[0] along the line + * quad[0]->quad[2] which as the same slope as the line + * (positive) */ b16dxdy = itob16(iwidth) / iheight; traps[0].bot.x1 = quad[1].x; - traps[0].bot.x2 = nxgl_interpolate(quad[0].x, quad[1].y - quad[0].y, b16dxdy); + traps[0].bot.x2 = nxgl_interpolate(quad[0].x, + quad[1].y - quad[0].y, + b16dxdy); traps[0].bot.y = b16toi(quad[1].y + b16HALF); - /* quad[1] is at the top left of the second trapezoid. quad[2} is - * at the bottom right of the second trapezoid. Interpolate to get - * corresponding point on the left side. + /* quad[1] is at the top left of the second trapezoid. + * quad[2} is at the bottom right of the second trapezoid. + * Interpolate to get corresponding point on the left side. * - * Interpolation is from quad[1] along the line quad[1]->quad[3] - * which as the same slope as the line (positive) + * Interpolation is from quad[1] along the line + * quad[1]->quad[3] which as the same slope as the line + * (positive) */ traps[1].top.x1 = traps[0].bot.x1; traps[1].top.x2 = traps[0].bot.x2; traps[1].top.y = traps[0].bot.y; - traps[1].bot.x1 = nxgl_interpolate(traps[1].top.x1, quad[2].y - quad[1].y, b16dxdy); + traps[1].bot.x1 = nxgl_interpolate(traps[1].top.x1, + quad[2].y - quad[1].y, + b16dxdy); traps[1].bot.x2 = quad[2].x; traps[1].bot.y = b16toi(quad[2].y + b16HALF); } @@ -383,22 +399,26 @@ int nxgl_splitline(FAR struct nxgl_vector_s *vector, /* quad[2] is at the bottom right of the triangle. Interpolate * to get the corresponding point on the left side. * - * Interpolation is from quad[0] along the line quad[0]->quad[1] - * which orthogonal to the slope of the line (and negative) + * Interpolation is from quad[0] along the line + * quad[0]->quad[1] which orthogonal to the slope of the line + * (and negative) */ b16dxdy = -itob16(iheight) / iwidth; - traps[0].bot.x1 = nxgl_interpolate(quad[0].x, quad[2].y - quad[0].y, b16dxdy); + traps[0].bot.x1 = nxgl_interpolate(quad[0].x, + quad[2].y - quad[0].y, + b16dxdy); traps[0].bot.x2 = quad[2].x; traps[0].bot.y = b16toi(quad[2].y + b16HALF); - /* quad[2] is at the top right of the second trapezoid. quad[1} is - * at the bottom left of the second trapezoid. Interpolate to get - * corresponding point on the right side. + /* quad[2] is at the top right of the second trapezoid. + * quad[1} is at the bottom left of the second trapezoid. + * Interpolate to get corresponding point on the right side. * - * Interpolation is from quad[2] along the line quad[2]->quad[3] - * which as the same slope as the previous interpolation. + * Interpolation is from quad[2] along the line + * quad[2]->quad[3] which as the same slope as the previous + * interpolation. */ traps[1].top.x1 = traps[0].bot.x1; @@ -406,11 +426,15 @@ int nxgl_splitline(FAR struct nxgl_vector_s *vector, traps[1].top.y = traps[0].bot.y; traps[1].bot.x1 = quad[1].x; - traps[1].bot.x2 = nxgl_interpolate(traps[1].top.x2, quad[1].y - quad[2].y, b16dxdy); + traps[1].bot.x2 = nxgl_interpolate(traps[1].top.x2, + quad[1].y - quad[2].y, + b16dxdy); traps[1].bot.y = b16toi(quad[1].y + b16HALF); } - /* The final trapezond (triangle) at the bottom is new well defined */ + /* The final trapezond (triangle) at the bottom is new well + * defined + */ traps[2].top.x1 = traps[1].bot.x1; traps[2].top.x2 = traps[1].bot.x2; @@ -432,7 +456,10 @@ int nxgl_splitline(FAR struct nxgl_vector_s *vector, quad[2].x = b16x - b16xoffset; quad[3].x = b16x + b16xoffset; - ginfo("Southwest: quad (%08x,%08x),(%08x,%08x),(%08x,%08x),(%08x,%08x)\n", + ginfo("Southwest: quad (%08" PRIx32 ",%08" PRIx32 ")," + "(%08" PRIx32 ",%08" PRIx32 ")," + "(%08" PRIx32 ",%08" PRIx32 ")," + "(%08" PRIx32 ",%08" PRIx32 ")\n", quad[0].x, quad[0].y, quad[1].x, quad[1].y, quad[2].x, quad[2].y, quad[3].x, quad[3].y); @@ -453,22 +480,26 @@ int nxgl_splitline(FAR struct nxgl_vector_s *vector, /* quad[1] is at the bottom right of the triangle. Interpolate * to get the corresponding point on the left side. * - * Interpolation is from quad[0] along the line quad[0]->quad[2] - * which as the same slope as the line (negative) + * Interpolation is from quad[0] along the line + * quad[0]->quad[2] which as the same slope as the line + * (negative) */ b16dxdy = -itob16(iwidth) / iheight; - traps[0].bot.x1 = nxgl_interpolate(traps[0].top.x1, quad[1].y - quad[0].y, b16dxdy); + traps[0].bot.x1 = nxgl_interpolate(traps[0].top.x1, + quad[1].y - quad[0].y, + b16dxdy); traps[0].bot.x2 = quad[1].x; traps[0].bot.y = b16toi(quad[1].y + b16HALF); - /* quad[1] is at the top right of the second trapezoid. quad[2} is - * at the bottom left of the second trapezoid. Interpolate to get - * corresponding point on the right side. + /* quad[1] is at the top right of the second trapezoid. + * quad[2} is at the bottom left of the second trapezoid. + * Interpolate to get corresponding point on the right side. * - * Interpolation is from quad[1] along the line quad[1]->quad[3] - * which as the same slope as the line (negative) + * Interpolation is from quad[1] along the line + * quad[1]->quad[3] which as the same slope as the line + * (negative) */ traps[1].top.x1 = traps[0].bot.x1; @@ -476,7 +507,9 @@ int nxgl_splitline(FAR struct nxgl_vector_s *vector, traps[1].top.y = traps[0].bot.y; traps[1].bot.x1 = quad[2].x; - traps[1].bot.x2 = nxgl_interpolate(traps[1].top.x2, quad[2].y - quad[1].y, b16dxdy); + traps[1].bot.x2 = nxgl_interpolate(traps[1].top.x2, + quad[2].y - quad[1].y, + b16dxdy); traps[1].bot.y = b16toi(quad[2].y + b16HALF); } else @@ -484,34 +517,42 @@ int nxgl_splitline(FAR struct nxgl_vector_s *vector, /* quad[2] is at the bottom left of the triangle. Interpolate * to get the corresponding point on the right side. * - * Interpolation is from quad[0] along the line quad[0]->quad[1] - * which orthogonal to the slope of the line (and positive) + * Interpolation is from quad[0] along the line + * quad[0]->quad[1] which orthogonal to the slope of the line + * (and positive) */ b16dxdy = itob16(iheight) / iwidth; traps[0].bot.x1 = quad[2].x; - traps[0].bot.x2 = nxgl_interpolate(traps[0].top.x2, quad[2].y - quad[0].y, b16dxdy); + traps[0].bot.x2 = nxgl_interpolate(traps[0].top.x2, + quad[2].y - quad[0].y, + b16dxdy); traps[0].bot.y = b16toi(quad[2].y + b16HALF); - /* quad[2] is at the top left of the second trapezoid. quad[1} is - * at the bottom right of the second trapezoid. Interpolate to get - * corresponding point on the left side. + /* quad[2] is at the top left of the second trapezoid. + * quad[1} is at the bottom right of the second trapezoid. + * Interpolate to get corresponding point on the left side. * - * Interpolation is from quad[2] along the line quad[2]->quad[3] - * which as the same slope as the previous interpolation. + * Interpolation is from quad[2] along the line + * quad[2]->quad[3] which as the same slope as the previous + * interpolation. */ traps[1].top.x1 = traps[0].bot.x1; traps[1].top.x2 = traps[0].bot.x2; traps[1].top.y = traps[0].bot.y; - traps[1].bot.x1 = nxgl_interpolate(traps[1].top.x1, quad[1].y - quad[2].y, b16dxdy); + traps[1].bot.x1 = nxgl_interpolate(traps[1].top.x1, + quad[1].y - quad[2].y, + b16dxdy); traps[1].bot.x2 = quad[1].x; traps[1].bot.y = b16toi(quad[1].y + b16HALF); } - /* The final trapezond (triangle) at the bottom is new well defined */ + /* The final trapezond (triangle) at the bottom is new well + * defined + */ traps[2].top.x1 = traps[1].bot.x1; traps[2].top.x2 = traps[1].bot.x2; @@ -522,13 +563,16 @@ int nxgl_splitline(FAR struct nxgl_vector_s *vector, traps[2].bot.y = b16toi(quad[3].y + b16HALF); } - ginfo("traps[0]: (%08x,%08x,%d),(%08x,%08x,%d)\n", + ginfo("traps[0]: (%08" PRIx32 ",%08" PRIx32 ",%d)," + "(%08" PRIx32 ",%08" PRIx32 ",%d)\n", traps[0].top.x1, traps[0].top.x2, traps[0].top.y, traps[0].bot.x1, traps[0].bot.x2, traps[0].bot.y); - ginfo("traps[1]: (%08x,%08x,%d),(%08x,%08x,%d)\n", + ginfo("traps[1]: (%08" PRIx32 ",%08" PRIx32 ",%d)," + "(%08" PRIx32 ",%08" PRIx32 ",%d)\n", traps[1].top.x1, traps[1].top.x2, traps[1].top.y, traps[1].bot.x1, traps[1].bot.x2, traps[1].bot.y); - ginfo("traps[2]: (%08x,%08x,%d),(%08x,%08x,%d)\n", + ginfo("traps[2]: (%08" PRIx32 ",%08" PRIx32 ",%d)," + "(%08" PRIx32 ",%08" PRIx32 ",%d)\n", traps[2].top.x1, traps[2].top.x2, traps[2].top.y, traps[2].bot.x1, traps[2].bot.x2, traps[2].bot.y); @@ -547,7 +591,8 @@ int nxgl_splitline(FAR struct nxgl_vector_s *vector, traps[1].bot.x2 = traps[1].bot.x1 + itob16(linewidth - 1); traps[1].bot.y = line.pt2.y; - ginfo("Horizontal traps[1]: (%08x,%08x,%d),(%08x,%08x, %d)\n", + ginfo("Horizontal traps[1]: (%08" PRIx32 ",%08" PRIx32 ",%d)," + "(%08" PRIx32 ",%08" PRIx32 ", %d)\n", traps[1].top.x1, traps[1].top.x2, traps[1].top.y, traps[1].bot.x1, traps[1].bot.x2, traps[1].bot.y); diff --git a/libs/libnx/nxmu/nx_eventhandler.c b/libs/libnx/nxmu/nx_eventhandler.c index d5c3a219c95..38ddc4706e6 100644 --- a/libs/libnx/nxmu/nx_eventhandler.c +++ b/libs/libnx/nxmu/nx_eventhandler.c @@ -144,8 +144,9 @@ int nx_eventhandler(NXHANDLE handle) { if (errcode == EAGAIN) { - /* EAGAIN is not an error. It occurs because the MQ is opened with - * O_NONBLOCK and there is no message available now. + /* EAGAIN is not an error. It occurs because the MQ is + * opened with O_NONBLOCK and there is no message + * available now. */ return OK; @@ -166,7 +167,7 @@ int nx_eventhandler(NXHANDLE handle) /* Dispatch the message appropriately */ msg = (struct nxsvrmsg_s *)buffer; - ginfo("Received msgid=%d\n", msg->msgid); + ginfo("Received msgid=%" PRId32 "\n", msg->msgid); switch (msg->msgid) { case NX_CLIMSG_CONNECTED: @@ -180,24 +181,28 @@ int nx_eventhandler(NXHANDLE handle) case NX_CLIMSG_REDRAW: { - FAR struct nxclimsg_redraw_s *redraw = (FAR struct nxclimsg_redraw_s *)buffer; + FAR struct nxclimsg_redraw_s *redraw = + (FAR struct nxclimsg_redraw_s *)buffer; wnd = redraw->wnd; DEBUGASSERT(wnd); if (wnd->cb->redraw) { - wnd->cb->redraw((NXWINDOW)wnd, &redraw->rect, redraw->more, wnd->arg); + wnd->cb->redraw((NXWINDOW)wnd, &redraw->rect, redraw->more, + wnd->arg); } } break; case NX_CLIMSG_NEWPOSITION: { - FAR struct nxclimsg_newposition_s *postn = (FAR struct nxclimsg_newposition_s *)buffer; + FAR struct nxclimsg_newposition_s *postn = + (FAR struct nxclimsg_newposition_s *)buffer; wnd = postn->wnd; DEBUGASSERT(wnd); if (wnd->cb->position) { - wnd->cb->position((NXWINDOW)wnd, &postn->size, &postn->pos, &postn->bounds, wnd->arg); + wnd->cb->position((NXWINDOW)wnd, &postn->size, &postn->pos, + &postn->bounds, wnd->arg); } } break; @@ -205,12 +210,14 @@ int nx_eventhandler(NXHANDLE handle) #ifdef CONFIG_NX_XYINPUT case NX_CLIMSG_MOUSEIN: { - FAR struct nxclimsg_mousein_s *mouse = (FAR struct nxclimsg_mousein_s *)buffer; + FAR struct nxclimsg_mousein_s *mouse = + (FAR struct nxclimsg_mousein_s *)buffer; wnd = mouse->wnd; DEBUGASSERT(wnd); if (wnd->cb->mousein) { - wnd->cb->mousein((NXWINDOW)wnd, &mouse->pos, mouse->buttons, wnd->arg); + wnd->cb->mousein((NXWINDOW)wnd, &mouse->pos, mouse->buttons, + wnd->arg); } } break; @@ -219,7 +226,8 @@ int nx_eventhandler(NXHANDLE handle) #ifdef CONFIG_NX_KBD case NX_CLIMSG_KBDIN: { - FAR struct nxclimsg_kbdin_s *kbd = (FAR struct nxclimsg_kbdin_s *)buffer; + FAR struct nxclimsg_kbdin_s *kbd = + (FAR struct nxclimsg_kbdin_s *)buffer; wnd = kbd->wnd; DEBUGASSERT(wnd); if (wnd->cb->kbdin) @@ -232,18 +240,20 @@ int nx_eventhandler(NXHANDLE handle) case NX_CLIMSG_EVENT: { - FAR struct nxclimsg_event_s *event = (FAR struct nxclimsg_event_s *)buffer; + FAR struct nxclimsg_event_s *event = + (FAR struct nxclimsg_event_s *)buffer; wnd = event->wnd; DEBUGASSERT(wnd); if (wnd->cb->event) { - wnd->cb->event((NXWINDOW)wnd, event->event, wnd->arg, event->arg); + wnd->cb->event((NXWINDOW)wnd, event->event, wnd->arg, + event->arg); } } break; default: - gerr("ERROR: Unrecognized message opcode: %d\n", + gerr("ERROR: Unrecognized message opcode: %" PRId32 "\n", ((FAR struct nxsvrmsg_s *)buffer)->msgid); break; } diff --git a/libs/libxx/0001-libc-Fix-a-few-warnings.patch b/libs/libxx/0001-libc-Fix-a-few-warnings.patch new file mode 100644 index 00000000000..b7bb109a015 --- /dev/null +++ b/libs/libxx/0001-libc-Fix-a-few-warnings.patch @@ -0,0 +1,43 @@ +From acd7be74ca12f8f08e52d6d80850a9b230109134 Mon Sep 17 00:00:00 2001 +From: YAMAMOTO Takashi +Date: Wed, 28 Oct 2020 15:40:16 -0400 +Subject: [PATCH] [libc++] Fix a few warnings + +Found during a NuttX porting effort. +But these changes are not directly relevant to NuttX. + +Differential Revision: https://reviews.llvm.org/D90139 +--- + src/filesystem/operations.cpp | 2 +- + src/locale.cpp | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/filesystem/operations.cpp libcxx/src/filesystem/operations.cpp +index 95d7d0d9642..788e31b673a 100644 +--- a/src/filesystem/operations.cpp ++++ libcxx/src/filesystem/operations.cpp +@@ -534,7 +534,7 @@ path __canonical(path const& orig_p, error_code* ec) { + ErrorHandler err("canonical", ec, &orig_p, &cwd); + + path p = __do_absolute(orig_p, &cwd, ec); +-#if _POSIX_VERSION >= 200112 ++#if defined(_POSIX_VERSION) && _POSIX_VERSION >= 200112 + std::unique_ptr + hold(::realpath(p.c_str(), nullptr), &::free); + if (hold.get() == nullptr) +diff --git a/src/locale.cpp libcxx/src/locale.cpp +index b9180880e49..02dbb334ff8 100644 +--- a/src/locale.cpp ++++ libcxx/src/locale.cpp +@@ -1149,7 +1149,7 @@ ctype::__classic_upper_table() _NOEXCEPT + { + return _LIBCPP_GET_C_LOCALE->__ctype_toupper; + } +-#elif __NetBSD__ ++#elif defined(__NetBSD__) + const short* + ctype::__classic_lower_table() _NOEXCEPT + { +-- +2.17.1 + diff --git a/libs/libxx/0001-libc-Fix-tests-failing-with-Clang-after-removing-GCC.patch b/libs/libxx/0001-libc-Fix-tests-failing-with-Clang-after-removing-GCC.patch new file mode 100644 index 00000000000..5e288388118 --- /dev/null +++ b/libs/libxx/0001-libc-Fix-tests-failing-with-Clang-after-removing-GCC.patch @@ -0,0 +1,26 @@ +From 81b6aa0e27abc3037c84d1ff2065bf60207f9b8b Mon Sep 17 00:00:00 2001 +From: Louis Dionne +Date: Fri, 30 Oct 2020 14:55:37 -0400 +Subject: [PATCH] [libc++] Fix tests failing with Clang after removing GCC + warnings + +--- + src/filesystem/filesystem_common.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/filesystem/filesystem_common.h libcxx/src/filesystem/filesystem_common.h +index a7828ef3863..dc55f93da70 100644 +--- a/src/filesystem/filesystem_common.h ++++ libcxx/src/filesystem/filesystem_common.h +@@ -198,7 +198,7 @@ private: + using chrono::duration; + using chrono::duration_cast; + +-using TimeSpec = std::timespec; ++using TimeSpec = timespec; + using StatT = struct stat; + + template +Date: Fri, 30 Oct 2020 11:19:07 -0400 +Subject: [PATCH] [libc++] NFC: Fix several GCC warnings in the test suite + +- Several -Wshadow warnings +- Several places where we did not initialize our base class explicitly +- Unused variable warnings +- Some tautological comparisons +- Some places where we'd pass null arguments to functions expecting + non-null (in unevaluated contexts) +- Add a few pragmas to turn off spurious warnings +- Fix warnings about declarations that don't declare anything +- Properly disable deprecation warnings in ext/ tests (the pragmas we + were using didn't work on GCC) +- Disable include_as_c.sh.cpp because GCC complains about C++ flags + when compiling as C. I couldn't find a way to fix this one properly, + so I'm disabling the test. This isn't great, but at least we'll be + able to enable warnings in the whole test suite with GCC. +--- + src/filesystem/filesystem_common.h | 55 ++++++++++++----------- + 1 file changed, 28 insertions(+), 27 deletions(-) + +diff --git a/src/filesystem/filesystem_common.h libcxx/src/filesystem/filesystem_common.h +index fe5c42f5e6d..a7828ef3863 100644 +--- a/src/filesystem/filesystem_common.h ++++ libcxx/src/filesystem/filesystem_common.h +@@ -13,8 +13,9 @@ + #include "filesystem" + #include "array" + #include "chrono" +-#include "cstdlib" + #include "climits" ++#include "cstdlib" ++#include "ctime" + + #include + #include +@@ -47,7 +48,7 @@ static string format_string_imp(const char* msg, ...) { + struct GuardVAList { + va_list& target; + bool active = true; +- GuardVAList(va_list& target) : target(target), active(true) {} ++ GuardVAList(va_list& tgt) : target(tgt), active(true) {} + void clear() { + if (active) + va_end(target); +@@ -134,50 +135,50 @@ path error_value() { + + template + struct ErrorHandler { +- const char* func_name; +- error_code* ec = nullptr; +- const path* p1 = nullptr; +- const path* p2 = nullptr; ++ const char* func_name_; ++ error_code* ec_ = nullptr; ++ const path* p1_ = nullptr; ++ const path* p2_ = nullptr; + + ErrorHandler(const char* fname, error_code* ec, const path* p1 = nullptr, + const path* p2 = nullptr) +- : func_name(fname), ec(ec), p1(p1), p2(p2) { +- if (ec) +- ec->clear(); ++ : func_name_(fname), ec_(ec), p1_(p1), p2_(p2) { ++ if (ec_) ++ ec_->clear(); + } + +- T report(const error_code& m_ec) const { +- if (ec) { +- *ec = m_ec; ++ T report(const error_code& ec) const { ++ if (ec_) { ++ *ec_ = ec; + return error_value(); + } +- string what = string("in ") + func_name; +- switch (bool(p1) + bool(p2)) { ++ string what = string("in ") + func_name_; ++ switch (bool(p1_) + bool(p2_)) { + case 0: +- __throw_filesystem_error(what, m_ec); ++ __throw_filesystem_error(what, ec); + case 1: +- __throw_filesystem_error(what, *p1, m_ec); ++ __throw_filesystem_error(what, *p1_, ec); + case 2: +- __throw_filesystem_error(what, *p1, *p2, m_ec); ++ __throw_filesystem_error(what, *p1_, *p2_, ec); + } + _LIBCPP_UNREACHABLE(); + } + + template +- T report(const error_code& m_ec, const char* msg, Args const&... args) const { +- if (ec) { +- *ec = m_ec; ++ T report(const error_code& ec, const char* msg, Args const&... args) const { ++ if (ec_) { ++ *ec_ = ec; + return error_value(); + } + string what = +- string("in ") + func_name + ": " + format_string(msg, args...); +- switch (bool(p1) + bool(p2)) { ++ string("in ") + func_name_ + ": " + format_string(msg, args...); ++ switch (bool(p1_) + bool(p2_)) { + case 0: +- __throw_filesystem_error(what, m_ec); ++ __throw_filesystem_error(what, ec); + case 1: +- __throw_filesystem_error(what, *p1, m_ec); ++ __throw_filesystem_error(what, *p1_, ec); + case 2: +- __throw_filesystem_error(what, *p1, *p2, m_ec); ++ __throw_filesystem_error(what, *p1_, *p2_, ec); + } + _LIBCPP_UNREACHABLE(); + } +@@ -197,8 +198,8 @@ private: + using chrono::duration; + using chrono::duration_cast; + +-using TimeSpec = struct ::timespec; +-using StatT = struct ::stat; ++using TimeSpec = std::timespec; ++using StatT = struct stat; + + template ::value> +-- +2.17.1 + diff --git a/libs/libxx/0001-libcxx-Check-_LIBCPP_PROVIDES_DEFAULT_RUNE_TABLE-fir.patch b/libs/libxx/0001-libcxx-Check-_LIBCPP_PROVIDES_DEFAULT_RUNE_TABLE-fir.patch new file mode 100644 index 00000000000..87572590281 --- /dev/null +++ b/libs/libxx/0001-libcxx-Check-_LIBCPP_PROVIDES_DEFAULT_RUNE_TABLE-fir.patch @@ -0,0 +1,78 @@ +From 3e8b517a509ae043571d8d0b00625d8a03eb5d05 Mon Sep 17 00:00:00 2001 +From: Xiang Xiao +Date: Mon, 9 Nov 2020 21:45:57 +0800 +Subject: [PATCH] [libcxx] Check _LIBCPP_PROVIDES_DEFAULT_RUNE_TABLE first in + __locale + +just like what's done in __locale.cpp + +Co-authored-by: Chao An + +Signed-off-by: Xiang Xiao + +Differential Revision: https://reviews.llvm.org/D91074 +--- + include/__locale | 40 +++++++++++++++++++++------------------- + 1 file changed, 21 insertions(+), 19 deletions(-) + +diff --git a/include/__locale libcxx/include/__locale +index 125adcf68c8..e973ce52646 100644 +--- a/include/__locale ++++ libcxx/include/__locale +@@ -397,7 +397,26 @@ locale::operator()(const basic_string<_CharT, _Traits, _Allocator>& __x, + class _LIBCPP_TYPE_VIS ctype_base + { + public: +-#if defined(__GLIBC__) ++#if defined(_LIBCPP_PROVIDES_DEFAULT_RUNE_TABLE) ++ typedef unsigned long mask; ++ static const mask space = 1<<0; ++ static const mask print = 1<<1; ++ static const mask cntrl = 1<<2; ++ static const mask upper = 1<<3; ++ static const mask lower = 1<<4; ++ static const mask alpha = 1<<5; ++ static const mask digit = 1<<6; ++ static const mask punct = 1<<7; ++ static const mask xdigit = 1<<8; ++ static const mask blank = 1<<9; ++#if defined(__BIONIC__) ++ // Historically this was a part of regex_traits rather than ctype_base. The ++ // historical value of the constant is preserved for ABI compatibility. ++ static const mask __regex_word = 0x8000; ++#else ++ static const mask __regex_word = 1<<10; ++#endif // defined(__BIONIC__) ++#elif defined(__GLIBC__) + typedef unsigned short mask; + static const mask space = _ISspace; + static const mask print = _ISprint; +@@ -486,24 +505,7 @@ public: + # define _LIBCPP_CTYPE_MASK_IS_COMPOSITE_ALPHA + # define _LIBCPP_CTYPE_MASK_IS_COMPOSITE_XDIGIT + #else +- typedef unsigned long mask; +- static const mask space = 1<<0; +- static const mask print = 1<<1; +- static const mask cntrl = 1<<2; +- static const mask upper = 1<<3; +- static const mask lower = 1<<4; +- static const mask alpha = 1<<5; +- static const mask digit = 1<<6; +- static const mask punct = 1<<7; +- static const mask xdigit = 1<<8; +- static const mask blank = 1<<9; +-#if defined(__BIONIC__) +- // Historically this was a part of regex_traits rather than ctype_base. The +- // historical value of the constant is preserved for ABI compatibility. +- static const mask __regex_word = 0x8000; +-#else +- static const mask __regex_word = 1<<10; +-#endif // defined(__BIONIC__) ++#error unkown classic_table, try _LIBCPP_PROVIDES_DEFAULT_RUNE_TABLE + #endif + static const mask alnum = alpha | digit; + static const mask graph = alnum | punct; +-- +2.17.1 + diff --git a/libs/libxx/0001-libcxx-Port-to-NuttX-https-nuttx.apache.org-RTOS.patch b/libs/libxx/0001-libcxx-Port-to-NuttX-https-nuttx.apache.org-RTOS.patch index 964ce7c5438..b8f0efd7b56 100644 --- a/libs/libxx/0001-libcxx-Port-to-NuttX-https-nuttx.apache.org-RTOS.patch +++ b/libs/libxx/0001-libcxx-Port-to-NuttX-https-nuttx.apache.org-RTOS.patch @@ -1,4 +1,4 @@ -From 10891b1c9eda0c87e33b0c0ba87f17a83930093c Mon Sep 17 00:00:00 2001 +From 6b12d8b5c30a84aa5767b1b18ecf5ba5e99a1654 Mon Sep 17 00:00:00 2001 From: Xiang Xiao Date: Fri, 2 Oct 2020 13:25:43 +0800 Subject: [PATCH] [libcxx] Port to NuttX(https://nuttx.apache.org/) RTOS @@ -9,54 +9,19 @@ Co-authored-by: YAMAMOTO Takashi Differential Revision: https://reviews.llvm.org/D88718 --- - include/__config | 31 +++++++++++++++++++++++++- + include/__config | 3 ++- include/__locale | 2 ++ - include/support/nuttx/xlocale.h | 18 +++++++++++++++ + include/support/nuttx/xlocale.h | 18 ++++++++++++++++++ src/include/config_elast.h | 4 ++++ src/locale.cpp | 2 +- - 5 files changed, 55 insertions(+), 2 deletions(-) + 5 files changed, 27 insertions(+), 2 deletions(-) create mode 100644 include/support/nuttx/xlocale.h diff --git a/include/__config libcxx/include/__config -index 575147cead4..32036094017 100644 +index eeef9c53a9f..9ace3b46028 100644 --- a/include/__config +++ libcxx/include/__config -@@ -10,6 +10,34 @@ - #ifndef _LIBCPP_CONFIG - #define _LIBCPP_CONFIG - -+// NuttX is sometimes built as a native target. -+// In that case, the __NuttX__ macro is predefined by the compiler. -+// https://github.com/NuttX/buildroot -+// -+// In other cases, __NuttX__ is an ordinary user-definded macro. -+// It's especially the case for NuttX sim, which is a target to run -+// the entire NuttX as a program on the host OS, which can be Linux, -+// macOS, Windows, etc. -+// https://cwiki.apache.org/confluence/display/NUTTX/NuttX+Simulation -+// In that case, the host OS compiler is used to build NuttX. -+// Thus, eg. NuttX sim on macOS is built with __APPLE__. -+// We #undef predefined macros for those possible host OSes here -+// because the OS APIs this library should use are of NuttX, -+// not the host OS. -+#if defined(__NuttX__) -+#undef __linux__ -+#undef __APPLE__ -+#undef __FreeBSD__ -+#undef __NetBSD__ -+#undef _WIN32 -+#undef __sun__ -+#undef _AIX -+// For the current use of the __unix__ macro in this library, -+// NuttX is not __unix__. -+// This might need to be revisited in future. -+#undef __unix__ -+#endif -+ - #if defined(_MSC_VER) && !defined(__clang__) - # if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) - # define _LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER -@@ -1125,6 +1153,7 @@ _LIBCPP_FUNC_VIS extern "C" void __sanitizer_annotate_contiguous_container( +@@ -1117,6 +1117,7 @@ _LIBCPP_FUNC_VIS extern "C" void __sanitizer_annotate_contiguous_container( # if defined(__FreeBSD__) || \ defined(__wasi__) || \ defined(__NetBSD__) || \ @@ -64,7 +29,7 @@ index 575147cead4..32036094017 100644 defined(__linux__) || \ defined(__GNU__) || \ defined(__APPLE__) || \ -@@ -1227,7 +1256,7 @@ _LIBCPP_FUNC_VIS extern "C" void __sanitizer_annotate_contiguous_container( +@@ -1219,7 +1220,7 @@ _LIBCPP_FUNC_VIS extern "C" void __sanitizer_annotate_contiguous_container( # endif #endif @@ -74,10 +39,10 @@ index 575147cead4..32036094017 100644 #define _LIBCPP_PROVIDES_DEFAULT_RUNE_TABLE #endif diff --git a/include/__locale libcxx/include/__locale -index 6d10fa4d3d6..fb391861f23 100644 +index 125adcf68c8..ebededf066b 100644 --- a/include/__locale +++ libcxx/include/__locale -@@ -21,6 +21,8 @@ +@@ -22,6 +22,8 @@ #if defined(_LIBCPP_MSVCRT_LIKE) # include # include @@ -130,7 +95,7 @@ index 501cbc4ffeb..3113f9fb5cd 100644 // No _LIBCPP_ELAST needed on Fuchsia #elif defined(__wasi__) diff --git a/src/locale.cpp libcxx/src/locale.cpp -index b9180880e49..25699f29ec9 100644 +index 5fdc14992f8..ed93727b544 100644 --- a/src/locale.cpp +++ libcxx/src/locale.cpp @@ -30,7 +30,7 @@ diff --git a/libs/libxx/Makefile b/libs/libxx/Makefile index 87cf1960566..6c787fe2a10 100644 --- a/libs/libxx/Makefile +++ b/libs/libxx/Makefile @@ -91,8 +91,12 @@ $(BIN): $(OBJS) dirlinks:: +makedepfile: $(CXXSRCS:.cxx=.ddx) $(CPPSRCS:.cpp=.ddp) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) + .depend: Makefile $(SRCS) $(TOPDIR)$(DELIM).config - $(Q) $(MKDEP) $(DEPPATH) "$(CXX)" -- $(CXXFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile $(Q) touch $@ depend: .depend diff --git a/libs/libxx/libcxx.defs b/libs/libxx/libcxx.defs index 434780d466f..8b0dfcdee14 100644 --- a/libs/libxx/libcxx.defs +++ b/libs/libxx/libcxx.defs @@ -25,6 +25,10 @@ $(TOPDIR)/include/libcxx: # $(Q) tar -xf libcxx-$(VERSION).src.tar.xz # $(Q) $(DELFILE) libcxx-$(VERSION).src.tar.xz # $(Q) mv libcxx-$(VERSION).src libcxx +# $(Q) patch -p0 < 0001-libc-Fix-a-few-warnings.patch +# $(Q) patch -p0 < 0001-libc-NFC-Fix-several-GCC-warnings-in-the-test-suite.patch +# $(Q) patch -p0 < 0001-libc-Fix-tests-failing-with-Clang-after-removing-GCC.patch +# $(Q) patch -p0 < 0001-libcxx-Check-_LIBCPP_PROVIDES_DEFAULT_RUNE_TABLE-fir.patch # $(Q) patch -p0 < 0001-libcxx-Port-to-NuttX-https-nuttx.apache.org-RTOS.patch $(Q) $(DIRLINK) $(CURDIR)/libcxx/include $(TOPDIR)/include/libcxx diff --git a/mm/Makefile b/mm/Makefile index ae04d1980af..a2b6cb57afa 100644 --- a/mm/Makefile +++ b/mm/Makefile @@ -82,10 +82,18 @@ endif # Dependencies +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, bin/Make.dep, $^) + $(call DELFILE, $^) + +makekdepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, kbin/Make.dep, $^) + $(call DELFILE, $^) + .depend: Makefile $(SRCS) $(TOPDIR)$(DELIM).config - $(Q) $(MKDEP) --obj-path bin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >bin/Make.dep + $(Q) $(MAKE) makedepfile ifneq ($(CONFIG_BUILD_FLAT),y) - $(Q) $(MKDEP) --obj-path kbin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) $(KDEFINE) -- $(SRCS) >kbin/Make.dep + $(Q) $(MAKE) makekdepfile CFLAGS="$(CFLAGS) $(KDEFINE)" endif $(Q) touch $@ diff --git a/mm/mm_heap/mm_initialize.c b/mm/mm_heap/mm_initialize.c index e49e249ffad..b30b5016335 100644 --- a/mm/mm_heap/mm_initialize.c +++ b/mm/mm_heap/mm_initialize.c @@ -92,7 +92,7 @@ void mm_addregion(FAR struct mm_heap_s *heap, FAR void *heapstart, heapend = MM_ALIGN_DOWN((uintptr_t)heapstart + (uintptr_t)heapsize); heapsize = heapend - heapbase; - minfo("Region %d: base=%p size=%u\n", IDX + 1, heapstart, heapsize); + minfo("Region %d: base=%p size=%zu\n", IDX + 1, heapstart, heapsize); /* Add the size of this region to the total size of the heap */ @@ -157,7 +157,7 @@ void mm_initialize(FAR struct mm_heap_s *heap, FAR void *heapstart, { int i; - minfo("Heap: start=%p size=%u\n", heapstart, heapsize); + minfo("Heap: start=%p size=%zu\n", heapstart, heapsize); /* The following two lines have cause problems for some older ZiLog * compilers in the past (but not the more recent). Life is easier if we diff --git a/mm/mm_heap/mm_malloc.c b/mm/mm_heap/mm_malloc.c index 71a5c5af819..1c45aacc535 100644 --- a/mm/mm_heap/mm_malloc.c +++ b/mm/mm_heap/mm_malloc.c @@ -250,11 +250,11 @@ FAR void *mm_malloc(FAR struct mm_heap_s *heap, size_t size) #ifdef CONFIG_DEBUG_MM if (!ret) { - mwarn("WARNING: Allocation failed, size %d\n", alignsize); + mwarn("WARNING: Allocation failed, size %zu\n", alignsize); } else { - minfo("Allocated %p, size %d\n", ret, alignsize); + minfo("Allocated %p, size %zu\n", ret, alignsize); } #endif diff --git a/net/Makefile b/net/Makefile index db40ad6398d..7cf01a1ad9d 100644 --- a/net/Makefile +++ b/net/Makefile @@ -91,10 +91,14 @@ $(COBJS): %$(OBJEXT): %.c $(BIN): $(OBJS) $(call ARCHIVE, $@, $(OBJS)) + +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) .depend: Makefile $(SRCS) $(TOPDIR)$(DELIM).config ifeq ($(CONFIG_NET),y) - $(Q) $(MKDEP) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile endif $(Q) touch $@ diff --git a/net/bluetooth/bluetooth_sendto.c b/net/bluetooth/bluetooth_sendto.c index 7223078cf44..b4a930d9c4a 100644 --- a/net/bluetooth/bluetooth_sendto.c +++ b/net/bluetooth/bluetooth_sendto.c @@ -93,7 +93,7 @@ static uint16_t bluetooth_sendto_eventhandler(FAR struct net_driver_s *dev, int hdrlen; int ret; - DEBUGASSERT(pvpriv != NULL && dev != NULL && pvconn != NULL); + DEBUGASSERT(pvpriv != NULL && dev != NULL); /* Ignore polls from non Bluetooth network drivers */ @@ -109,7 +109,7 @@ static uint16_t bluetooth_sendto_eventhandler(FAR struct net_driver_s *dev, pstate = (FAR struct bluetooth_sendto_s *)pvpriv; radio = (FAR struct radio_driver_s *)dev; - ninfo("flags: %04x sent: %d\n", flags, pstate->is_sent); + ninfo("flags: %04x sent: %zd\n", flags, pstate->is_sent); if (pstate != NULL && (flags & BLUETOOTH_POLL) != 0) { diff --git a/net/bluetooth/bluetooth_sockif.c b/net/bluetooth/bluetooth_sockif.c index f1829e7ebe4..434cbf4295a 100644 --- a/net/bluetooth/bluetooth_sockif.c +++ b/net/bluetooth/bluetooth_sockif.c @@ -401,8 +401,8 @@ static int bluetooth_bind(FAR struct socket *psock, FAR const struct sockaddr_l2 *iaddr; if (addrlen < sizeof(struct sockaddr_l2)) { - nerr("ERROR: Invalid address length: %d < %d\n", - addrlen, sizeof(struct sockaddr_l2)); + nerr("ERROR: Invalid address length: %zu < %zu\n", + (size_t)addrlen, sizeof(struct sockaddr_l2)); return -EBADF; } @@ -415,8 +415,8 @@ static int bluetooth_bind(FAR struct socket *psock, FAR const struct sockaddr_hci *hciaddr; if (addrlen < sizeof(struct sockaddr_hci)) { - nerr("ERROR: Invalid address length: %d < %d\n", - addrlen, sizeof(struct sockaddr_hci)); + nerr("ERROR: Invalid address length: %zu < %zu\n", + (size_t)addrlen, sizeof(struct sockaddr_hci)); return -EBADF; } diff --git a/net/can/can_getsockopt.c b/net/can/can_getsockopt.c index af46244f896..319b5b3667e 100644 --- a/net/can/can_getsockopt.c +++ b/net/can/can_getsockopt.c @@ -139,10 +139,10 @@ int can_getsockopt(FAR struct socket *psock, int option, } else { - FAR int *loopback = (FAR int32_t *)value; - *loopback = conn->loopback; - *value_len = sizeof(conn->loopback); - ret = OK; + FAR int32_t *loopback = (FAR int32_t *)value; + *loopback = conn->loopback; + *value_len = sizeof(conn->loopback); + ret = OK; } break; @@ -158,10 +158,10 @@ int can_getsockopt(FAR struct socket *psock, int option, } else { - FAR int *recv_own_msgs = (FAR int32_t *)value; - *recv_own_msgs = conn->recv_own_msgs; - *value_len = sizeof(conn->recv_own_msgs); - ret = OK; + FAR int32_t *recv_own_msgs = (FAR int32_t *)value; + *recv_own_msgs = conn->recv_own_msgs; + *value_len = sizeof(conn->recv_own_msgs); + ret = OK; } break; @@ -178,10 +178,10 @@ int can_getsockopt(FAR struct socket *psock, int option, } else { - FAR int *fd_frames = (FAR int32_t *)value; - *fd_frames = conn->fd_frames; - *value_len = sizeof(conn->fd_frames); - ret = OK; + FAR int32_t *fd_frames = (FAR int32_t *)value; + *fd_frames = conn->fd_frames; + *value_len = sizeof(conn->fd_frames); + ret = OK; } break; #endif @@ -202,10 +202,10 @@ int can_getsockopt(FAR struct socket *psock, int option, } else { - FAR int *tx_deadline = (FAR int32_t *)value; - *tx_deadline = conn->tx_deadline; - *value_len = sizeof(conn->tx_deadline); - ret = OK; + FAR int32_t *tx_deadline = (FAR int32_t *)value; + *tx_deadline = conn->tx_deadline; + *value_len = sizeof(conn->tx_deadline); + ret = OK; } break; #endif diff --git a/net/ieee802154/ieee802154_sendto.c b/net/ieee802154/ieee802154_sendto.c index 05dae325c29..391e4c63d72 100644 --- a/net/ieee802154/ieee802154_sendto.c +++ b/net/ieee802154/ieee802154_sendto.c @@ -282,7 +282,7 @@ static uint16_t ieee802154_sendto_eventhandler(FAR struct net_driver_s *dev, int hdrlen; int ret; - DEBUGASSERT(pvpriv != NULL && dev != NULL && pvconn != NULL); + DEBUGASSERT(pvpriv != NULL && dev != NULL); /* Ignore polls from non IEEE 802.15.4 network drivers */ diff --git a/net/igmp/igmp_group.c b/net/igmp/igmp_group.c index 1adf873d071..31ca186a096 100644 --- a/net/igmp/igmp_group.c +++ b/net/igmp/igmp_group.c @@ -46,6 +46,8 @@ #include #include +#include +#include #include #include #include @@ -106,7 +108,7 @@ FAR struct igmp_group_s *igmp_grpalloc(FAR struct net_driver_s *dev, { FAR struct igmp_group_s *group; - ninfo("addr: %08x dev: %p\n", *addr, dev); + ninfo("addr: %08" PRIx32 " dev: %p\n", (uint32_t)*addr, dev); group = (FAR struct igmp_group_s *)kmm_zalloc(sizeof(struct igmp_group_s)); grpinfo("group: %p\n", group); @@ -160,7 +162,8 @@ FAR struct igmp_group_s *igmp_grpfind(FAR struct net_driver_s *dev, group; group = group->next) { - grpinfo("Compare: %08x vs. %08x\n", group->grpaddr, *addr); + grpinfo("Compare: %08" PRIx32 " vs. %08" PRIx32 "\n", + (uint32_t)group->grpaddr, (uint32_t)*addr); if (net_ipv4addr_cmp(group->grpaddr, *addr)) { grpinfo("Match!\n"); diff --git a/net/igmp/igmp_input.c b/net/igmp/igmp_input.c index 668538f88c4..f963c337df6 100644 --- a/net/igmp/igmp_input.c +++ b/net/igmp/igmp_input.c @@ -45,6 +45,8 @@ #include #include +#include +#include #include #include @@ -157,7 +159,8 @@ void igmp_input(struct net_driver_s *dev) group = igmp_grpallocfind(dev, &destipaddr); if (group == NULL) { - nerr("ERROR: Failed to find/allocate group: %08x\n", destipaddr); + nerr("ERROR: Failed to find/allocate group: %08" PRIx32 "\n", + (uint32_t)destipaddr); return; } diff --git a/net/igmp/igmp_join.c b/net/igmp/igmp_join.c index ca145b02b5d..c87f231fb8b 100644 --- a/net/igmp/igmp_join.c +++ b/net/igmp/igmp_join.c @@ -45,6 +45,8 @@ #include #include +#include +#include #include @@ -116,7 +118,8 @@ * ****************************************************************************/ -int igmp_joingroup(struct net_driver_s *dev, FAR const struct in_addr *grpaddr) +int igmp_joingroup(struct net_driver_s *dev, + FAR const struct in_addr *grpaddr) { struct igmp_group_s *group; int ret; @@ -130,7 +133,7 @@ int igmp_joingroup(struct net_driver_s *dev, FAR const struct in_addr *grpaddr) { /* No... allocate a new entry */ - ninfo("Join to new group: %08x\n", grpaddr->s_addr); + ninfo("Join to new group: %08" PRIx32 "\n", (uint32_t)grpaddr->s_addr); group = igmp_grpalloc(dev, &grpaddr->s_addr); IGMP_STATINCR(g_netstats.igmp.joins); diff --git a/net/igmp/igmp_mcastmac.c b/net/igmp/igmp_mcastmac.c index 88c12a8cb7d..f5ad89b07c0 100644 --- a/net/igmp/igmp_mcastmac.c +++ b/net/igmp/igmp_mcastmac.c @@ -45,6 +45,8 @@ #include #include +#include +#include #include #include @@ -79,8 +81,8 @@ static void igmp_mcastmac(in_addr_t *ip, FAR uint8_t *mac) mac[4] = ip4_addr3(*ip); mac[5] = ip4_addr4(*ip); - ninfo("IP: %08x -> MAC: %02x%02x%02x%02x%02x%02x\n", - *ip, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + ninfo("IP: %08" PRIx32 " -> MAC: %02x%02x%02x%02x%02x%02x\n", + (uint32_t)*ip, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); } /**************************************************************************** @@ -99,7 +101,7 @@ void igmp_addmcastmac(FAR struct net_driver_s *dev, FAR in_addr_t *ip) { uint8_t mcastmac[6]; - ninfo("Adding: IP %08x\n", *ip); + ninfo("Adding: IP %08" PRIx32 "\n", (uint32_t)*ip); if (dev->d_addmac) { igmp_mcastmac(ip, mcastmac); @@ -119,7 +121,7 @@ void igmp_removemcastmac(FAR struct net_driver_s *dev, FAR in_addr_t *ip) { uint8_t mcastmac[6]; - ninfo("Removing: IP %08x\n", *ip); + ninfo("Removing: IP %08" PRIx32 "\n", (uint32_t)*ip); if (dev->d_rmmac) { igmp_mcastmac(ip, mcastmac); diff --git a/net/igmp/igmp_poll.c b/net/igmp/igmp_poll.c index ae6b3830d61..a8b008bcc1b 100644 --- a/net/igmp/igmp_poll.c +++ b/net/igmp/igmp_poll.c @@ -45,6 +45,8 @@ #include #include +#include +#include #include #include @@ -99,16 +101,16 @@ static inline void igmp_sched_send(FAR struct net_driver_s *dev, if (group->msgid == IGMPv2_MEMBERSHIP_REPORT) { dest = &group->grpaddr; - ninfo("Send IGMPv2_MEMBERSHIP_REPORT, dest=%08x flags=%02x\n", - *dest, group->flags); + ninfo("Send IGMPv2_MEMBERSHIP_REPORT, dest=%08" PRIx32 " flags=%02x\n", + (uint32_t)*dest, group->flags); SET_LASTREPORT(group->flags); /* Remember we were the last to report */ } else { DEBUGASSERT(group->msgid == IGMP_LEAVE_GROUP); dest = &g_ipv4_allrouters; - ninfo("Send IGMP_LEAVE_GROUP, dest=%08x flags=%02x\n", - *dest, group->flags); + ninfo("Send IGMP_LEAVE_GROUP, dest=%08" PRIx32 " flags=%02x\n", + (uint32_t)*dest, group->flags); } /* Send the message */ diff --git a/net/local/local_fifo.c b/net/local/local_fifo.c index da8b1b6a7d3..2b4f9b741c7 100644 --- a/net/local/local_fifo.c +++ b/net/local/local_fifo.c @@ -43,6 +43,7 @@ #include #include +#include #include #include #include @@ -87,7 +88,7 @@ static inline void local_cs_name(FAR struct local_conn_s *conn, } else { - snprintf(path, LOCAL_FULLPATH_LEN - 1, "%s" LOCAL_CS_SUFFIX "%x", + snprintf(path, LOCAL_FULLPATH_LEN - 1, "%s" LOCAL_CS_SUFFIX "%" PRIx32, conn->lc_path, conn->lc_instance_id); } @@ -114,7 +115,7 @@ static inline void local_sc_name(FAR struct local_conn_s *conn, } else { - snprintf(path, LOCAL_FULLPATH_LEN - 1, "%s" LOCAL_SC_SUFFIX "%x", + snprintf(path, LOCAL_FULLPATH_LEN - 1, "%s" LOCAL_SC_SUFFIX "%" PRIx32, conn->lc_path, conn->lc_instance_id); } @@ -379,7 +380,8 @@ int local_create_fifos(FAR struct local_conn_s *conn) ****************************************************************************/ #ifdef CONFIG_NET_LOCAL_DGRAM -int local_create_halfduplex(FAR struct local_conn_s *conn, FAR const char *path) +int local_create_halfduplex(FAR struct local_conn_s *conn, + FAR const char *path) { char fullpath[LOCAL_FULLPATH_LEN]; diff --git a/net/local/local_recvfrom.c b/net/local/local_recvfrom.c index 12eaca42d77..8440b2e385d 100644 --- a/net/local/local_recvfrom.c +++ b/net/local/local_recvfrom.c @@ -42,6 +42,7 @@ #include #include +#include #include #include #include @@ -339,7 +340,9 @@ psock_dgram_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, goto errout_with_infd; } - /* Adjust the number of bytes remaining to be read from the packet */ + /* Adjust the number of bytes remaining to be read from the + * packet + */ DEBUGASSERT(tmplen <= remaining); remaining -= tmplen; @@ -443,7 +446,7 @@ ssize_t local_recvfrom(FAR struct socket *psock, FAR void *buf, #endif { DEBUGPANIC(); - nerr("ERROR: Unrecognized socket type: %s\n", psock->s_type); + nerr("ERROR: Unrecognized socket type: %" PRIu8 "\n", psock->s_type); return -EINVAL; } } diff --git a/net/local/local_sendpacket.c b/net/local/local_sendpacket.c index 644dd310f39..39f78b9fc62 100644 --- a/net/local/local_sendpacket.c +++ b/net/local/local_sendpacket.c @@ -102,7 +102,7 @@ static int local_fifo_write(FAR struct file *filep, FAR const uint8_t *buf, { if (nwritten != -EINTR) { - nerr("ERROR: nx_write failed: %d\n", nwritten); + nerr("ERROR: nx_write failed: %zd\n", nwritten); return (int)nwritten; } diff --git a/net/local/local_sockif.c b/net/local/local_sockif.c index 6e9c7facd7d..577eb4191af 100644 --- a/net/local/local_sockif.c +++ b/net/local/local_sockif.c @@ -292,7 +292,7 @@ static int local_bind(FAR struct socket *psock, if (addr->sa_family != AF_LOCAL || addrlen < sizeof(sa_family_t)) { - nerr("ERROR: Invalid address length: %d < %d\n", + nerr("ERROR: Invalid address length: %d < %zu\n", addrlen, sizeof(sa_family_t)); return -EBADF; } diff --git a/net/procfs/netdev_statistics.c b/net/procfs/netdev_statistics.c index f71fcf0dcd3..95b18ac7e41 100644 --- a/net/procfs/netdev_statistics.c +++ b/net/procfs/netdev_statistics.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include @@ -72,11 +73,13 @@ static int netprocfs_inet6draddress(FAR struct netprocfs_file_s *netfile); static int netprocfs_blank_line(FAR struct netprocfs_file_s *netfile); #endif #ifdef CONFIG_NETDEV_STATISTICS -static int netprocfs_rxstatistics_header(FAR struct netprocfs_file_s *netfile); +static int netprocfs_rxstatistics_header( + FAR struct netprocfs_file_s *netfile); static int netprocfs_rxstatistics(FAR struct netprocfs_file_s *netfile); static int netprocfs_rxpackets_header(FAR struct netprocfs_file_s *netfile); static int netprocfs_rxpackets(FAR struct netprocfs_file_s *netfile); -static int netprocfs_txstatistics_header(FAR struct netprocfs_file_s *netfile); +static int netprocfs_txstatistics_header( + FAR struct netprocfs_file_s *netfile); static int netprocfs_txstatistics(FAR struct netprocfs_file_s *netfile); static int netprocfs_errors(FAR struct netprocfs_file_s *netfile); #endif /* CONFIG_NETDEV_STATISTICS */ @@ -380,7 +383,8 @@ static int netprocfs_blank_line(FAR struct netprocfs_file_s *netfile) ****************************************************************************/ #ifdef CONFIG_NETDEV_STATISTICS -static int netprocfs_rxstatistics_header(FAR struct netprocfs_file_s *netfile) +static int netprocfs_rxstatistics_header( + FAR struct netprocfs_file_s *netfile) { DEBUGASSERT(netfile != NULL); return snprintf(netfile->line, NET_LINELEN , "\tRX: %-8s %-8s %-8s\n", @@ -492,7 +496,8 @@ static int netprocfs_rxpackets(FAR struct netprocfs_file_s *netfile) ****************************************************************************/ #ifdef CONFIG_NETDEV_STATISTICS -static int netprocfs_txstatistics_header(FAR struct netprocfs_file_s *netfile) +static int netprocfs_txstatistics_header( + FAR struct netprocfs_file_s *netfile) { DEBUGASSERT(netfile != NULL); @@ -515,7 +520,8 @@ static int netprocfs_txstatistics(FAR struct netprocfs_file_s *netfile) dev = netfile->dev; stats = &dev->d_statistics; - return snprintf(netfile->line, NET_LINELEN, "\t %08lx %08lx %08lx %08lx\n", + return snprintf(netfile->line, NET_LINELEN, + "\t %08lx %08lx %08lx %08lx\n", (unsigned long)stats->tx_packets, (unsigned long)stats->tx_done, (unsigned long)stats->tx_errors, @@ -537,7 +543,8 @@ static int netprocfs_errors(FAR struct netprocfs_file_s *netfile) dev = netfile->dev; stats = &dev->d_statistics; - return snprintf(netfile->line, NET_LINELEN , "\tTotal Errors: %08x\n\n", + return snprintf(netfile->line, NET_LINELEN, + "\tTotal Errors: %08" PRIx32 "\n\n", stats->errors); } #endif /* CONFIG_NETDEV_STATISTICS */ diff --git a/net/sixlowpan/sixlowpan_framelist.c b/net/sixlowpan/sixlowpan_framelist.c index 28669a56fcf..60783ccf4e1 100644 --- a/net/sixlowpan/sixlowpan_framelist.c +++ b/net/sixlowpan/sixlowpan_framelist.c @@ -207,8 +207,8 @@ static uint16_t sixlowpan_protosize(FAR const struct ipv6_hdr_s *ipv6hdr, #ifdef CONFIG_WIRELESS_IEEE802154 static int sixlowpan_ieee802154_metadata(FAR struct radio_driver_s *radio, - FAR const struct netdev_varaddr_s *destmac, - FAR union sixlowpan_metadata_u *meta) + FAR const struct netdev_varaddr_s *destmac, + FAR union sixlowpan_metadata_u *meta) { struct ieee802_txmetadata_s pktmeta; int ret; @@ -306,8 +306,8 @@ static int sixlowpan_ieee802154_metadata(FAR struct radio_driver_s *radio, #ifdef CONFIG_WIRELESS_PKTRADIO static int sixlowpan_pktradio_metadata(FAR struct radio_driver_s *radio, - FAR const struct netdev_varaddr_s *destmac, - FAR union sixlowpan_metadata_u *meta) + FAR const struct netdev_varaddr_s *destmac, + FAR union sixlowpan_metadata_u *meta) { FAR struct pktradio_metadata_s *pktmeta = &meta->pktradio; @@ -421,7 +421,7 @@ int sixlowpan_queue_frames(FAR struct radio_driver_s *radio, iob->io_pktlen = 0; fptr = iob->io_data; - ninfo("Sending packet length %d\n", buflen); + ninfo("Sending packet length %zd\n", buflen); /* Get the metadata that describes the MAC header on the packet */ @@ -548,7 +548,7 @@ int sixlowpan_queue_frames(FAR struct radio_driver_s *radio, * The following fragments contain only the fragn dispatch. */ - ninfo("Sending fragmented packet length %d\n", buflen); + ninfo("Sending fragmented packet length %zd\n", buflen); /* Create 1st Fragment */ @@ -568,8 +568,8 @@ int sixlowpan_queue_frames(FAR struct radio_driver_s *radio, * 1. Datagram size describes the total (un-fragmented) payload. * 2. Datagram tag identifies the set of fragments and is used to * match fragments of the same payload. - * 3. Datagram offset identifies the fragment’s offset within the un- - * fragmented payload. + * 3. Datagram offset identifies the fragment’s offset within the + * unfragmented payload. * * The fragment header length is 4 bytes for the first header and 5 * bytes for all subsequent headers. diff --git a/net/sixlowpan/sixlowpan_input.c b/net/sixlowpan/sixlowpan_input.c index 585b8b7d4bc..012fd87a7b2 100644 --- a/net/sixlowpan/sixlowpan_input.c +++ b/net/sixlowpan/sixlowpan_input.c @@ -412,7 +412,7 @@ static int sixlowpan_frame_process(FAR struct radio_driver_s *radio, { /* The packet is a fragment but its size does not match. */ - nwarn("WARNING: Dropping 6LoWPAN packet. Bad fragsize: %u vs &u\n", + nwarn("WARNING: Dropping 6LoWPAN packet. Bad fragsize: %u vs %u\n", fragsize, reass->rb_pktlen); ret = -EPERM; goto errout_with_reass; @@ -855,7 +855,7 @@ int sixlowpan_input(FAR struct radio_driver_s *radio, if (hdrlen > radio->r_dev.d_len) { - nwarn("WARNING: Packet too small: Have %u need >%u\n", + nwarn("WARNING: Packet too small: Have %u need >%zu\n", radio->r_dev.d_len, hdrlen); goto drop; } diff --git a/net/sixlowpan/sixlowpan_send.c b/net/sixlowpan/sixlowpan_send.c index cc68ce66727..b2c6456021e 100644 --- a/net/sixlowpan/sixlowpan_send.c +++ b/net/sixlowpan/sixlowpan_send.c @@ -103,7 +103,7 @@ static uint16_t send_eventhandler(FAR struct net_driver_s *dev, { FAR struct sixlowpan_send_s *sinfo = (FAR struct sixlowpan_send_s *)pvpriv; - ninfo("flags: %04x: %d\n", flags); + ninfo("flags: %04x\n", flags); /* Verify that this is a compatible network driver. */ diff --git a/net/sixlowpan/sixlowpan_tcpsend.c b/net/sixlowpan/sixlowpan_tcpsend.c index 28d20f9fd5b..81ba7b5cfea 100644 --- a/net/sixlowpan/sixlowpan_tcpsend.c +++ b/net/sixlowpan/sixlowpan_tcpsend.c @@ -312,6 +312,15 @@ static uint16_t tcp_send_eventhandler(FAR struct net_driver_s *dev, return flags; } + /* Check if the IEEE802.15.4 network driver went down */ + + if ((flags & NETDEV_DOWN) != 0) + { + nwarn("WARNING: Device is down\n"); + sinfo->s_result = -ENOTCONN; + goto end_wait; + } + /* The TCP socket is connected and, hence, should be bound to a device. * Make sure that the polling device is the one that we are bound to. */ @@ -323,16 +332,7 @@ static uint16_t tcp_send_eventhandler(FAR struct net_driver_s *dev, return flags; } - /* Check if the IEEE802.15.4 network driver went down */ - - if ((flags & NETDEV_DOWN) != 0) - { - nwarn("WARNING: Device is down\n"); - sinfo->s_result = -ENOTCONN; - goto end_wait; - } - - ninfo("flags: %04x acked: %u sent: %u\n", + ninfo("flags: %04x acked: %u sent: %zu\n", flags, sinfo->s_acked, sinfo->s_sent); /* If this packet contains an acknowledgement, then update the count of @@ -350,7 +350,7 @@ static uint16_t tcp_send_eventhandler(FAR struct net_driver_s *dev, */ sinfo->s_acked = tcp_getsequence(tcp->ackno) - sinfo->s_isn; - ninfo("ACK: acked=%d sent=%d buflen=%d\n", + ninfo("ACK: acked=%d sent=%zd buflen=%zd\n", sinfo->s_acked, sinfo->s_sent, sinfo->s_buflen); /* Have all of the bytes in the buffer been sent and acknowledged? */ @@ -451,7 +451,7 @@ static uint16_t tcp_send_eventhandler(FAR struct net_driver_s *dev, sndlen = winleft; } - ninfo("s_buflen=%u s_sent=%u mss=%u winsize=%u sndlen=%d\n", + ninfo("s_buflen=%zu s_sent=%zu mss=%u winsize=%u sndlen=%d\n", sinfo->s_buflen, sinfo->s_sent, conn->mss, conn->winsize, sndlen); @@ -518,7 +518,7 @@ static uint16_t tcp_send_eventhandler(FAR struct net_driver_s *dev, g_netstats.tcp.sent++; #endif - ninfo("Sent: acked=%d sent=%d buflen=%d tx_unacked=%d\n", + ninfo("Sent: acked=%d sent=%zd buflen=%zd tx_unacked=%d\n", sinfo->s_acked, sinfo->s_sent, sinfo->s_buflen, conn->tx_unacked); } @@ -868,7 +868,7 @@ void sixlowpan_tcp_send(FAR struct net_driver_s *dev, if (ipv6hdr->ipv6.proto != IP_PROTO_TCP) { - nwarn("WARNING: Expected TCP prototype: %u vs %s\n", + nwarn("WARNING: Expected TCP prototype: %u vs %u\n", ipv6hdr->ipv6.proto, IP_PROTO_TCP); } else diff --git a/net/socket/send.c b/net/socket/send.c index 66d1e3af31e..92b152c7757 100644 --- a/net/socket/send.c +++ b/net/socket/send.c @@ -110,7 +110,7 @@ ssize_t psock_send(FAR struct socket *psock, FAR const void *buf, size_t len, ret = psock->s_sockif->si_send(psock, buf, len, flags); if (ret < 0) { - nerr("ERROR: socket si_send() (or usrsock_sendto()) failed: %d\n", + nerr("ERROR: socket si_send() (or usrsock_sendto()) failed: %zd\n", ret); } diff --git a/net/tcp/tcp_close.c b/net/tcp/tcp_close.c index 2d57588fb35..15927a60f21 100644 --- a/net/tcp/tcp_close.c +++ b/net/tcp/tcp_close.c @@ -81,9 +81,9 @@ static uint16_t tcp_close_eventhandler(FAR struct net_driver_s *dev, FAR struct tcp_close_s *pstate = (FAR struct tcp_close_s *)pvpriv; FAR struct tcp_conn_s *conn = (FAR struct tcp_conn_s *)pvconn; - DEBUGASSERT(pstate != NULL && conn != NULL); + DEBUGASSERT(pstate != NULL); - ninfo("conn: %p flags: %04x\n", conn, flags); + ninfo("flags: %04x\n", flags); /* TCP_DISCONN_EVENTS: * TCP_CLOSE: The remote host has closed the connection diff --git a/net/tcp/tcp_input.c b/net/tcp/tcp_input.c index 09fee452fe1..0ae1388aeaf 100644 --- a/net/tcp/tcp_input.c +++ b/net/tcp/tcp_input.c @@ -47,6 +47,7 @@ #if defined(CONFIG_NET) && defined(CONFIG_NET_TCP) +#include #include #include #include @@ -508,7 +509,8 @@ found: if ((conn->tcpstateflags & TCP_STATE_MASK) == TCP_ESTABLISHED) { nwarn("WARNING: ackseq > unackseq\n"); - nwarn("sndseq=%u tx_unacked=%u unackseq=%u ackseq=%u\n", + nwarn("sndseq=%" PRIu32 " tx_unacked=%u " + "unackseq=%" PRIu32 " ackseq=%" PRIu32 "\n", tcp_getsequence(conn->sndseq), conn->tx_unacked, unackseq, ackseq); @@ -521,8 +523,10 @@ found: * be beyond ackseq. */ - ninfo("sndseq: %08x->%08x unackseq: %08x new tx_unacked: %d\n", - tcp_getsequence(conn->sndseq), ackseq, unackseq, conn->tx_unacked); + ninfo("sndseq: %08" PRIx32 "->%08" PRIx32 + " unackseq: %08" PRIx32 " new tx_unacked: %d\n", + tcp_getsequence(conn->sndseq), ackseq, unackseq, + conn->tx_unacked); tcp_setsequence(conn->sndseq, ackseq); /* Do RTT estimation, unless we have done retransmissions. */ diff --git a/net/tcp/tcp_send.c b/net/tcp/tcp_send.c index 8adf61d9884..882764ce368 100644 --- a/net/tcp/tcp_send.c +++ b/net/tcp/tcp_send.c @@ -311,19 +311,6 @@ static void tcp_sendcommon(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn, FAR struct tcp_hdr_s *tcp) { - /* If keepalive is outstanding, cancel it */ - -#ifdef CONFIG_NET_TCP_KEEPALIVE - if (conn->keepretries > 0) - { - uint32_t saveseq = tcp_getsequence(conn->sndseq); - saveseq += conn->tx_unacked; - tcp_setsequence(conn->sndseq, saveseq); - conn->tx_unacked--; - conn->keepretries = 0; - } -#endif /* CONFIG_NET_TCP_KEEPALIVE */ - /* Copy the IP address into the IPv6 header */ #ifdef CONFIG_NET_IPv6 diff --git a/net/tcp/tcp_send_buffered.c b/net/tcp/tcp_send_buffered.c index 598392eca8d..040ad561831 100644 --- a/net/tcp/tcp_send_buffered.c +++ b/net/tcp/tcp_send_buffered.c @@ -327,6 +327,30 @@ static uint16_t psock_send_eventhandler(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn = (FAR struct tcp_conn_s *)pvconn; FAR struct socket *psock = (FAR struct socket *)pvpriv; + /* Check for a loss of connection */ + + if ((flags & TCP_DISCONN_EVENTS) != 0) + { + ninfo("Lost connection: %04x\n", flags); + + /* We could get here recursively through the callback actions of + * tcp_lost_connection(). So don't repeat that action if we have + * already been disconnected. + */ + + if (psock->s_conn != NULL && _SS_ISCONNECTED(psock->s_flags)) + { + /* Report not connected */ + + tcp_lost_connection(psock, psock->s_sndcb, flags); + } + + /* Free write buffers and terminate polling */ + + psock_lost_connection(psock, psock->s_conn, !!(flags & NETDEV_DOWN)); + return flags; + } + /* The TCP socket is connected and, hence, should be bound to a device. * Make sure that the polling device is the one that we are bound to. */ @@ -494,30 +518,6 @@ static uint16_t psock_send_eventhandler(FAR struct net_driver_s *dev, } } - /* Check for a loss of connection */ - - else if ((flags & TCP_DISCONN_EVENTS) != 0) - { - ninfo("Lost connection: %04x\n", flags); - - /* We could get here recursively through the callback actions of - * tcp_lost_connection(). So don't repeat that action if we have - * already been disconnected. - */ - - if (psock->s_conn != NULL && _SS_ISCONNECTED(psock->s_flags)) - { - /* Report not connected */ - - tcp_lost_connection(psock, psock->s_sndcb, flags); - } - - /* Free write buffers and terminate polling */ - - psock_lost_connection(psock, conn, !!(flags & NETDEV_DOWN)); - return flags; - } - /* Check if we are being asked to retransmit data */ else if ((flags & TCP_REXMIT) != 0) @@ -734,7 +734,7 @@ static uint16_t psock_send_eventhandler(FAR struct net_driver_s *dev, sndlen = conn->winsize; } - ninfo("SEND: wrb=%p pktlen=%u sent=%u sndlen=%u mss=%u " + ninfo("SEND: wrb=%p pktlen=%u sent=%u sndlen=%zu mss=%u " "winsize=%u\n", wrb, TCP_WBPKTLEN(wrb), TCP_WBSENT(wrb), sndlen, conn->mss, conn->winsize); diff --git a/net/tcp/tcp_send_unbuffered.c b/net/tcp/tcp_send_unbuffered.c index a17a6571c16..abdd11decb6 100644 --- a/net/tcp/tcp_send_unbuffered.c +++ b/net/tcp/tcp_send_unbuffered.c @@ -45,6 +45,7 @@ #include #include +#include #include #include #include @@ -196,7 +197,7 @@ static uint16_t tcpsend_eventhandler(FAR struct net_driver_s *dev, return flags; } - ninfo("flags: %04x acked: %d sent: %d\n", + ninfo("flags: %04x acked: %" PRId32 " sent: %zd\n", flags, pstate->snd_acked, pstate->snd_sent); /* If this packet contains an acknowledgement, then update the count of @@ -236,7 +237,7 @@ static uint16_t tcpsend_eventhandler(FAR struct net_driver_s *dev, */ pstate->snd_acked = tcp_getsequence(tcp->ackno) - pstate->snd_isn; - ninfo("ACK: acked=%d sent=%d buflen=%d\n", + ninfo("ACK: acked=%" PRId32 " sent=%zd buflen=%zd\n", pstate->snd_acked, pstate->snd_sent, pstate->snd_buflen); /* Have all of the bytes in the buffer been sent and acknowledged? */ @@ -427,7 +428,8 @@ static uint16_t tcpsend_eventhandler(FAR struct net_driver_s *dev, */ seqno = pstate->snd_sent + pstate->snd_isn; - ninfo("SEND: sndseq %08x->%08x\n", conn->sndseq, seqno); + ninfo("SEND: sndseq %08" PRIx32 "->%08" PRIx32 "\n", + tcp_getsequence(conn->sndseq), seqno); tcp_setsequence(conn->sndseq, seqno); #ifdef NEED_IPDOMAIN_SUPPORT @@ -448,7 +450,7 @@ static uint16_t tcpsend_eventhandler(FAR struct net_driver_s *dev, /* Update the amount of data sent (but not necessarily ACKed) */ pstate->snd_sent += sndlen; - ninfo("SEND: acked=%d sent=%d buflen=%d\n", + ninfo("SEND: acked=%" PRId32 " sent=%zd buflen=%zd\n", pstate->snd_acked, pstate->snd_sent, pstate->snd_buflen); } } diff --git a/net/tcp/tcp_sendfile.c b/net/tcp/tcp_sendfile.c index d9c4640e670..a1676caa4b3 100644 --- a/net/tcp/tcp_sendfile.c +++ b/net/tcp/tcp_sendfile.c @@ -236,19 +236,6 @@ static uint16_t sendfile_eventhandler(FAR struct net_driver_s *dev, FAR struct sendfile_s *pstate = (FAR struct sendfile_s *)pvpriv; int ret; - /* The TCP socket is connected and, hence, should be bound to a device. - * Make sure that the polling device is the own that we are bound to. - */ - - DEBUGASSERT(conn->dev != NULL); - if (dev != conn->dev) - { - return flags; - } - - ninfo("flags: %04x acked: %d sent: %d\n", - flags, pstate->snd_acked, pstate->snd_sent); - /* Check for a loss of connection */ if ((flags & TCP_DISCONN_EVENTS) != 0) @@ -276,6 +263,20 @@ static uint16_t sendfile_eventhandler(FAR struct net_driver_s *dev, goto end_wait; } + /* The TCP socket is connected and, hence, should be bound to a device. + * Make sure that the polling device is the own that we are bound to. + */ + + DEBUGASSERT(conn); + DEBUGASSERT(conn->dev != NULL); + if (dev != conn->dev) + { + return flags; + } + + ninfo("flags: %04x acked: %d sent: %d\n", + flags, pstate->snd_acked, pstate->snd_sent); + /* We get here if (1) not all of the data has been ACKed, (2) we have been * asked to retransmit data, (3) the connection is still healthy, and (4) * the outgoing packet is available for our use. In this case, we are diff --git a/net/tcp/tcp_timer.c b/net/tcp/tcp_timer.c index d42914e8baa..e769c7abaf1 100644 --- a/net/tcp/tcp_timer.c +++ b/net/tcp/tcp_timer.c @@ -341,36 +341,13 @@ void tcp_timer(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn, case TCP_ESTABLISHED: - /* In the ESTABLISHED state, we have to differentiate - * between a keepalive and actual transmitted data. + /* In the ESTABLISHED state, we call upon the application + * to do the actual retransmit after which we jump into + * the code for sending out the packet. */ -#ifdef CONFIG_NET_TCP_KEEPALIVE - if (conn->keepretries > 0) - { - /* In case of a keepalive timeout (based on RTT) the - * state has to be set back into idle so that a new - * keepalive can be fired. - */ - - uint32_t saveseq = tcp_getsequence(conn->sndseq); - saveseq += conn->tx_unacked; - tcp_setsequence(conn->sndseq, saveseq); - conn->tx_unacked--; - } - else -#endif - { - /* If there is a timeout on outstanding data we call - * upon the application to do the actual retransmit - * after which we jump into the code for sending out - * the packet. - */ - - result = tcp_callback(dev, conn, TCP_REXMIT); - tcp_rexmit(dev, conn, result); - } - + result = tcp_callback(dev, conn, TCP_REXMIT); + tcp_rexmit(dev, conn, result); goto done; case TCP_FIN_WAIT_1: @@ -466,14 +443,13 @@ void tcp_timer(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn, } #endif - /* And send the probe (along with a garbage byte). - * The packet we sned must have these properties: + /* And send the probe. + * The packet we send must have these properties: * * - TCP_ACK flag (only) is set. * - Sequence number is the sequence number of * previously ACKed data, i.e., the expected * sequence number minus one. - * - The data payload is one or two bytes. * * tcp_send() will send the TCP sequence number as * conn->sndseq. Rather than creating a new @@ -483,13 +459,9 @@ void tcp_timer(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn, saveseq = tcp_getsequence(conn->sndseq); tcp_setsequence(conn->sndseq, saveseq - 1); - tcp_send(dev, conn, TCP_ACK, tcpiplen + 1); + tcp_send(dev, conn, TCP_ACK, tcpiplen); - /* Increment the number of un-ACKed bytes due to - * the dummy byte that we just sent. - */ - - conn->tx_unacked++; + tcp_setsequence(conn->sndseq, saveseq); #ifdef CONFIG_NET_TCP_WRITE_BUFFERS /* Increment the un-ACKed sequence number */ diff --git a/net/tcp/tcp_wrbuffer_dump.c b/net/tcp/tcp_wrbuffer_dump.c index 1af76573952..53dd37ffedc 100644 --- a/net/tcp/tcp_wrbuffer_dump.c +++ b/net/tcp/tcp_wrbuffer_dump.c @@ -39,6 +39,7 @@ #include +#include #include #include @@ -63,7 +64,7 @@ void tcp_wrbuffer_dump(FAR const char *msg, FAR struct tcp_wrbuffer_s *wrb, unsigned int len, unsigned int offset) { - syslog(LOG_DEBUG, "%s: wrb=%p segno=%d sent=%d nrtx=%d\n", + syslog(LOG_DEBUG, "%s: wrb=%p segno=%" PRIu32 " sent=%d nrtx=%d\n", msg, wrb, TCP_WBSEQNO(wrb), TCP_WBSENT(wrb), TCP_WBNRTX(wrb)); iob_dump("I/O Buffer Chain", TCP_WBIOB(wrb), len, offset); } diff --git a/net/udp/udp_sendto_buffered.c b/net/udp/udp_sendto_buffered.c index aee41e4d18c..a2511924f14 100644 --- a/net/udp/udp_sendto_buffered.c +++ b/net/udp/udp_sendto_buffered.c @@ -369,23 +369,7 @@ static uint16_t sendto_eventhandler(FAR struct net_driver_s *dev, FAR struct udp_conn_s *conn = (FAR struct udp_conn_s *)pvconn; FAR struct socket *psock = (FAR struct socket *)pvpriv; - DEBUGASSERT(dev != NULL && conn != NULL && psock != NULL); - - /* The UDP socket should be bound to a device. Make sure that the polling - * device is the one that we are bound to. - * - * REVISIT: There is a logical error here for the case where there are - * multiple network devices. In that case, the packets may need to be sent - * in a different order than they were queued. The packet we may need to - * send on this device may not be at the head of the list. Forcing FIFO - * packet transmission could degrade performance! - */ - - DEBUGASSERT(conn->dev != NULL); - if (dev != conn->dev) - { - return flags; - } + DEBUGASSERT(dev != NULL && psock != NULL); ninfo("flags: %04x\n", flags); @@ -399,7 +383,24 @@ static uint16_t sendto_eventhandler(FAR struct net_driver_s *dev, * the next transfer. */ - sendto_writebuffer_release(psock, conn); + sendto_writebuffer_release(psock, psock->s_conn); + return flags; + } + + /* The UDP socket should be bound to a device. Make sure that the polling + * device is the one that we are bound to. + * + * REVISIT: There is a logical error here for the case where there are + * multiple network devices. In that case, the packets may need to be sent + * in a different order than they were queued. The packet we may need to + * send on this device may not be at the head of the list. Forcing FIFO + * packet transmission could degrade performance! + */ + + DEBUGASSERT(conn != NULL); + DEBUGASSERT(conn->dev != NULL); + if (dev != conn->dev) + { return flags; } @@ -499,8 +500,8 @@ static uint16_t sendto_eventhandler(FAR struct net_driver_s *dev, ****************************************************************************/ ssize_t psock_udp_sendto(FAR struct socket *psock, FAR const void *buf, - size_t len, int flags, FAR const struct sockaddr *to, - socklen_t tolen) + size_t len, int flags, + FAR const struct sockaddr *to, socklen_t tolen) { FAR struct udp_conn_s *conn; FAR struct udp_wrbuffer_s *wrb; @@ -695,7 +696,8 @@ ssize_t psock_udp_sendto(FAR struct socket *psock, FAR const void *buf, addr6->sin6_family = AF_INET6; addr6->sin6_port = conn->rport; - net_ipv6addr_copy(addr6->sin6_addr.s6_addr, conn->u.ipv6.raddr); + net_ipv6addr_copy(addr6->sin6_addr.s6_addr, + conn->u.ipv6.raddr); } #endif /* CONFIG_NET_IPv6 */ } diff --git a/openamp/Makefile b/openamp/Makefile index d9e9eb3d4c3..100baadbfb1 100644 --- a/openamp/Makefile +++ b/openamp/Makefile @@ -47,8 +47,12 @@ $(BIN): $(OBJS) dirlinks:: +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) + .depend: Makefile $(SRCS) $(TOPDIR)$(DELIM).config - $(Q) $(MKDEP) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile $(Q) touch $@ depend: .depend diff --git a/pass1/Makefile b/pass1/Makefile index 27704f6f2f9..d9a90294316 100644 --- a/pass1/Makefile +++ b/pass1/Makefile @@ -57,9 +57,13 @@ $(COBJS): %$(OBJEXT): %.c $(BIN): $(OBJS) $(call ARCHIVE, $@, $(OBJS)) + +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) .depend: Makefile $(SRCS) $(TOPDIR)$(DELIM).config - $(Q) $(MKDEP) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile $(Q) touch $@ depend: .depend diff --git a/sched/Makefile b/sched/Makefile index 2ac07430563..fb3bd8deb50 100644 --- a/sched/Makefile +++ b/sched/Makefile @@ -58,9 +58,13 @@ $(COBJS): %$(OBJEXT): %.c $(BIN): $(OBJS) $(call ARCHIVE, $@, $(OBJS)) + +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) .depend: Makefile $(SRCS) $(TOPDIR)$(DELIM).config - $(Q) $(MKDEP) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile $(Q) touch $@ depend: .depend diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 9eeb4b4c4aa..c26e6d6dc3f 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -353,10 +353,6 @@ try_again_in_irq: * and try again. Briefly re-enabling interrupts should * be sufficient to permit processing the pending pause * request. - * - * NOTE: This should never happen on architectures like - * the Cortex-A; the inter-CPU interrupt (SGI) is not - * maskable. */ up_irq_restore(ret); diff --git a/sched/module/mod_modhandle.c b/sched/module/mod_modhandle.c index a612d380ec7..81a83f35ffa 100644 --- a/sched/module/mod_modhandle.c +++ b/sched/module/mod_modhandle.c @@ -85,7 +85,7 @@ FAR void *modhandle(FAR const char *name) modp = modlib_registry_find(name); if (modp == NULL) { - berr("ERROR: Failed to find module %s: %d\n", name, modp); + berr("ERROR: Failed to find module %s\n", name); set_errno(ENOENT); } diff --git a/sched/pthread/pthread_getaffinity.c b/sched/pthread/pthread_getaffinity.c index 31ebd983eb9..2375e092bd3 100644 --- a/sched/pthread/pthread_getaffinity.c +++ b/sched/pthread/pthread_getaffinity.c @@ -40,6 +40,7 @@ #include #include +#include #include #include #include @@ -82,12 +83,12 @@ int pthread_getaffinity_np(pthread_t thread, size_t cpusetsize, { int ret; - sinfo("thread ID=%d cpusetsize=%d cpuset=%p\n", - (int)thread, (int)cpusetsize, cpusetsize); - DEBUGASSERT(thread > 0 && cpusetsize == sizeof(cpu_set_t) && cpuset != NULL); + sinfo("thread ID=%d cpusetsize=%zu cpuset=%ju\n", + (int)thread, cpusetsize, (uintmax_t)*cpuset); + /* Let nxsched_get_affinity do all of the work */ ret = nxsched_get_affinity((pid_t)thread, cpusetsize, cpuset); diff --git a/sched/pthread/pthread_join.c b/sched/pthread/pthread_join.c index 994bc7d5a15..328708bc31e 100644 --- a/sched/pthread/pthread_join.c +++ b/sched/pthread/pthread_join.c @@ -137,6 +137,15 @@ int pthread_join(pthread_t thread, FAR pthread_addr_t *pexit_value) } else { + /* NOTE: sched_lock() is not enough for SMP + * because another CPU would continue the pthread and exit + * sequences so need to protect it with a critical section + */ + +#ifdef CONFIG_SMP + irqstate_t flags = enter_critical_section(); +#endif + /* We found the join info structure. Increment for the reference * to the join structure that we have. This will keep things * stable for we have to do @@ -211,6 +220,10 @@ int pthread_join(pthread_t thread, FAR pthread_addr_t *pexit_value) sched_unlock(); +#ifdef CONFIG_SMP + leave_critical_section(flags); +#endif + /* Release our reference to the join structure and, if the reference * count decrements to zero, deallocate the join structure. */ diff --git a/sched/pthread/pthread_setaffinity.c b/sched/pthread/pthread_setaffinity.c index 8c6d4fd4abf..3b8d1c51a2c 100644 --- a/sched/pthread/pthread_setaffinity.c +++ b/sched/pthread/pthread_setaffinity.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include @@ -69,12 +70,12 @@ int pthread_setaffinity_np(pthread_t thread, size_t cpusetsize, { int ret; - sinfo("thread ID=%d cpusetsize=%d cpuset=%p\n", - (int)thread, (int)cpusetsize, cpusetsize); - DEBUGASSERT(thread > 0 && cpusetsize == sizeof(cpu_set_t) && cpuset != NULL); + sinfo("thread ID=%d cpusetsize=%zu cpuset=%ju\n", + (int)thread, cpusetsize, (uintmax_t)*cpuset); + /* Let nxsched_set_affinity do all of the work, adjusting the return * value. */ diff --git a/sched/sched/Make.defs b/sched/sched/Make.defs index 21dd5cc06ee..f46c39db7ae 100644 --- a/sched/sched/Make.defs +++ b/sched/sched/Make.defs @@ -85,7 +85,6 @@ CSRCS += sched_processtimer.c endif ifeq ($(CONFIG_SMP),y) -CSRCS += sched_tasklistlock.c CSRCS += sched_thistask.c endif diff --git a/sched/sched/sched.h b/sched/sched/sched.h index 084ba3c8ee2..71d4f460312 100644 --- a/sched/sched/sched.h +++ b/sched/sched/sched.h @@ -417,9 +417,6 @@ FAR struct tcb_s *this_task(void); int nxsched_select_cpu(cpu_set_t affinity); int nxsched_pause_cpu(FAR struct tcb_s *tcb); -irqstate_t nxsched_lock_tasklist(void); -void nxsched_unlock_tasklist(irqstate_t lock); - # define nxsched_islocked_global() spin_islocked(&g_cpu_schedlock) # define nxsched_islocked_tcb(tcb) nxsched_islocked_global() diff --git a/sched/sched/sched_addblocked.c b/sched/sched/sched_addblocked.c index 6b6d8559c7c..3965f61193c 100644 --- a/sched/sched/sched_addblocked.c +++ b/sched/sched/sched_addblocked.c @@ -77,12 +77,6 @@ void nxsched_add_blocked(FAR struct tcb_s *btcb, tstate_t task_state) DEBUGASSERT(task_state >= FIRST_BLOCKED_STATE && task_state <= LAST_BLOCKED_STATE); -#ifdef CONFIG_SMP - /* Lock the tasklists before accessing */ - - irqstate_t lock = nxsched_lock_tasklist(); -#endif - /* Add the TCB to the blocked task list associated with this state. */ tasklist = TLIST_BLOCKED(task_state); @@ -102,12 +96,6 @@ void nxsched_add_blocked(FAR struct tcb_s *btcb, tstate_t task_state) dq_addlast((FAR dq_entry_t *)btcb, tasklist); } -#ifdef CONFIG_SMP - /* Unlock the tasklists */ - - nxsched_unlock_tasklist(lock); -#endif - /* Make sure the TCB's state corresponds to the list */ btcb->task_state = task_state; diff --git a/sched/sched/sched_addreadytorun.c b/sched/sched/sched_addreadytorun.c index acb5ecac08f..0d610b53157 100644 --- a/sched/sched/sched_addreadytorun.c +++ b/sched/sched/sched_addreadytorun.c @@ -174,10 +174,6 @@ bool nxsched_add_readytorun(FAR struct tcb_s *btcb) int cpu; int me; - /* Lock the tasklists before accessing */ - - irqstate_t lock = nxsched_lock_tasklist(); - /* Check if the blocked TCB is locked to this CPU */ if ((btcb->flags & TCB_FLAG_CPU_LOCKED) != 0) @@ -276,9 +272,7 @@ bool nxsched_add_readytorun(FAR struct tcb_s *btcb) if (cpu != me) { - nxsched_unlock_tasklist(lock); DEBUGVERIFY(up_cpu_pause(cpu)); - lock = nxsched_lock_tasklist(); } /* Add the task to the list corresponding to the selected state @@ -433,9 +427,6 @@ bool nxsched_add_readytorun(FAR struct tcb_s *btcb) } } - /* Unlock the tasklists */ - - nxsched_unlock_tasklist(lock); return doswitch; } diff --git a/sched/sched/sched_mergepending.c b/sched/sched/sched_mergepending.c index 3aba52e39a9..05eaa660b1a 100644 --- a/sched/sched/sched_mergepending.c +++ b/sched/sched/sched_mergepending.c @@ -184,10 +184,6 @@ bool nxsched_merge_pending(void) int cpu; int me; - /* Lock the tasklist before accessing */ - - irqstate_t lock = nxsched_lock_tasklist(); - /* Remove and process every TCB in the g_pendingtasks list. * * Do nothing if (1) pre-emption is still disabled (by any CPU), or (2) if @@ -204,7 +200,7 @@ bool nxsched_merge_pending(void) { /* The pending task list is empty */ - goto errout_with_lock; + goto errout; } cpu = nxsched_select_cpu(ALL_CPUS); /* REVISIT: Maybe ptcb->affinity */ @@ -228,9 +224,7 @@ bool nxsched_merge_pending(void) /* Add the pending task to the correct ready-to-run list. */ - nxsched_unlock_tasklist(lock); ret |= nxsched_add_readytorun(tcb); - lock = nxsched_lock_tasklist(); /* This operation could cause the scheduler to become locked. * Check if that happened. @@ -251,7 +245,7 @@ bool nxsched_merge_pending(void) * pending task list. */ - goto errout_with_lock; + goto errout; } /* Set up for the next time through the loop */ @@ -262,7 +256,7 @@ bool nxsched_merge_pending(void) { /* The pending task list is empty */ - goto errout_with_lock; + goto errout; } cpu = nxsched_select_cpu(ALL_CPUS); /* REVISIT: Maybe ptcb->affinity */ @@ -278,11 +272,8 @@ bool nxsched_merge_pending(void) TSTATE_TASK_READYTORUN); } -errout_with_lock: +errout: - /* Unlock the tasklist */ - - nxsched_unlock_tasklist(lock); return ret; } #endif /* CONFIG_SMP */ diff --git a/sched/sched/sched_mergeprioritized.c b/sched/sched/sched_mergeprioritized.c index 9ad49337eca..3afb2b2cdd3 100644 --- a/sched/sched/sched_mergeprioritized.c +++ b/sched/sched/sched_mergeprioritized.c @@ -68,12 +68,6 @@ void nxsched_merge_prioritized(FAR dq_queue_t *list1, FAR dq_queue_t *list2, FAR struct tcb_s *tcb2; FAR struct tcb_s *tmp; -#ifdef CONFIG_SMP - /* Lock the tasklists before accessing */ - - irqstate_t lock = nxsched_lock_tasklist(); -#endif - DEBUGASSERT(list1 != NULL && list2 != NULL); /* Get a private copy of list1, clearing list1. We do this early so that @@ -90,7 +84,7 @@ void nxsched_merge_prioritized(FAR dq_queue_t *list1, FAR dq_queue_t *list2, { /* Special case.. list1 is empty. There is nothing to be done. */ - goto ret_with_lock; + goto out; } /* Now the TCBs are no longer accessible and we can change the state on @@ -113,7 +107,7 @@ void nxsched_merge_prioritized(FAR dq_queue_t *list1, FAR dq_queue_t *list2, /* Special case.. list2 is empty. Move list1 to list2. */ dq_move(&clone, list2); - goto ret_with_lock; + goto out; } /* Now loop until all entries from list1 have been merged into list2. tcb1 @@ -163,12 +157,7 @@ void nxsched_merge_prioritized(FAR dq_queue_t *list1, FAR dq_queue_t *list2, } while (tcb1 != NULL); -ret_with_lock: +out: -#ifdef CONFIG_SMP - /* Unlock the tasklists */ - - nxsched_unlock_tasklist(lock); -#endif return; } diff --git a/sched/sched/sched_removereadytorun.c b/sched/sched/sched_removereadytorun.c index 094ffa2ca7a..963a259b68f 100644 --- a/sched/sched/sched_removereadytorun.c +++ b/sched/sched/sched_removereadytorun.c @@ -140,10 +140,6 @@ bool nxsched_remove_readytorun(FAR struct tcb_s *rtcb) bool doswitch = false; int cpu; - /* Lock the tasklists before accessing */ - - irqstate_t lock = nxsched_lock_tasklist(); - /* Which CPU (if any) is the task running on? Which task list holds the * TCB? */ @@ -188,9 +184,7 @@ bool nxsched_remove_readytorun(FAR struct tcb_s *rtcb) me = this_cpu(); if (cpu != me) { - nxsched_unlock_tasklist(lock); DEBUGVERIFY(up_cpu_pause(cpu)); - lock = nxsched_lock_tasklist(); } /* The task is running but the CPU that it was running on has been @@ -336,9 +330,6 @@ bool nxsched_remove_readytorun(FAR struct tcb_s *rtcb) rtcb->task_state = TSTATE_TASK_INVALID; - /* Unlock the tasklists */ - - nxsched_unlock_tasklist(lock); return doswitch; } #endif /* CONFIG_SMP */ diff --git a/sched/sched/sched_tasklistlock.c b/sched/sched/sched_tasklistlock.c deleted file mode 100644 index 64aa808adbb..00000000000 --- a/sched/sched/sched_tasklistlock.c +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * sched/sched/sched_tasklistlock.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include - -#include "sched/sched.h" - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Splinlock to protect the tasklists */ - -static volatile spinlock_t g_tasklist_lock SP_SECTION = SP_UNLOCKED; - -/* Handles nested calls */ - -static volatile uint8_t g_tasklist_lock_count[CONFIG_SMP_NCPUS]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: nxsched_lock_tasklist() - * - * Description: - * Disable local interrupts and take the global spinlock (g_tasklist_lock) - * if the call counter (g_tasklist_lock_count[cpu]) equals to 0. Then the - * counter on the CPU is incremented to allow nested call. - * - * NOTE: This API is used to protect tasklists in the scheduler. So do not - * use this API for other purposes. - * - * Returned Value: - * An opaque, architecture-specific value that represents the state of - * the interrupts prior to the call to nxsched_lock_tasklist(); - ****************************************************************************/ - -irqstate_t nxsched_lock_tasklist(void) -{ - int me; - irqstate_t ret; - - ret = up_irq_save(); - me = this_cpu(); - - if (0 == g_tasklist_lock_count[me]) - { - spin_lock(&g_tasklist_lock); - } - - g_tasklist_lock_count[me]++; - DEBUGASSERT(0 != g_tasklist_lock_count[me]); - return ret; -} - -/**************************************************************************** - * Name: nxsched_unlock_tasklist() - * - * Description: - * Decrement the call counter (g_tasklist_lock_count[cpu]) and if it - * decrements to zero then release the spinlock (g_tasklist_lock) and - * restore the interrupt state as it was prior to the previous call to - * nxsched_lock_tasklist(). - * - * NOTE: This API is used to protect tasklists in the scheduler. So do not - * use this API for other purposes. - * - * Input Parameters: - * lock - The architecture-specific value that represents the state of - * the interrupts prior to the call to nxsched_lock_tasklist(). - * - * Returned Value: - * None - ****************************************************************************/ - -void nxsched_unlock_tasklist(irqstate_t lock) -{ - int me; - - me = this_cpu(); - - DEBUGASSERT(0 < g_tasklist_lock_count[me]); - g_tasklist_lock_count[me]--; - - if (0 == g_tasklist_lock_count[me]) - { - spin_unlock(&g_tasklist_lock); - } - - up_irq_restore(lock); -} diff --git a/sched/sched/sched_timerexpiration.c b/sched/sched/sched_timerexpiration.c index 8677271d6e3..409a9a566af 100644 --- a/sched/sched/sched_timerexpiration.c +++ b/sched/sched/sched_timerexpiration.c @@ -439,7 +439,7 @@ static void nxsched_timer_start(unsigned int ticks) if (ret < 0) { - serr("ERROR: up_timer_start/up_alarm_start failed: %d\n"); + serr("ERROR: up_timer_start/up_alarm_start failed: %d\n", ret); UNUSED(ret); } } diff --git a/sched/sched/sched_waitid.c b/sched/sched/sched_waitid.c index b8fb630b9c3..20019342af1 100644 --- a/sched/sched/sched_waitid.c +++ b/sched/sched/sched_waitid.c @@ -143,6 +143,14 @@ int nx_waitid(int idtype, id_t id, FAR siginfo_t *info, int options) sigemptyset(&set); nxsig_addset(&set, SIGCHLD); + /* NOTE: sched_lock() is not enough for SMP + * because the child task is running on another CPU + */ + +#ifdef CONFIG_SMP + irqstate_t flags = enter_critical_section(); +#endif + /* Disable pre-emption so that nothing changes while the loop executes */ sched_lock(); @@ -379,6 +387,11 @@ int nx_waitid(int idtype, id_t id, FAR siginfo_t *info, int options) errout: sched_unlock(); + +#ifdef CONFIG_SMP + leave_critical_section(flags); +#endif + return ret; } diff --git a/sched/sched/sched_waitpid.c b/sched/sched/sched_waitpid.c index b23a68ecd95..0dd7de6ca51 100644 --- a/sched/sched/sched_waitpid.c +++ b/sched/sched/sched_waitpid.c @@ -72,6 +72,14 @@ pid_t nx_waitpid(pid_t pid, int *stat_loc, int options) DEBUGASSERT(stat_loc); + /* NOTE: sched_lock() is not enough for SMP + * because the child task is running on another CPU + */ + +#ifdef CONFIG_SMP + irqstate_t flags = enter_critical_section(); +#endif + /* Disable pre-emption so that nothing changes in the following tests */ sched_lock(); @@ -158,11 +166,15 @@ pid_t nx_waitpid(pid_t pid, int *stat_loc, int options) /* On success, return the PID */ - sched_unlock(); - return pid; + ret = pid; errout: sched_unlock(); + +#ifdef CONFIG_SMP + leave_critical_section(flags); +#endif + return ret; } @@ -199,6 +211,14 @@ pid_t nx_waitpid(pid_t pid, int *stat_loc, int options) sigemptyset(&set); nxsig_addset(&set, SIGCHLD); + /* NOTE: sched_lock() is not enough for SMP + * because the child task is running on another CPU + */ + +#ifdef CONFIG_SMP + irqstate_t flags = enter_critical_section(); +#endif + /* Disable pre-emption so that nothing changes while the loop executes */ sched_lock(); @@ -438,11 +458,17 @@ pid_t nx_waitpid(pid_t pid, int *stat_loc, int options) } } - sched_unlock(); - return pid; + /* On success, return the PID */ + + ret = pid; errout: sched_unlock(); + +#ifdef CONFIG_SMP + leave_critical_section(flags); +#endif + return ret; } #endif /* CONFIG_SCHED_HAVE_PARENT */ diff --git a/sched/semaphore/sem_holder.c b/sched/semaphore/sem_holder.c index b3da8f38800..e98f08dd516 100644 --- a/sched/semaphore/sem_holder.c +++ b/sched/semaphore/sem_holder.c @@ -328,7 +328,7 @@ static int nxsem_boostholderprio(FAR struct semholder_s *pholder, if (!nxsched_verify_tcb(htcb)) { - swarn("WARNING: TCB 0x%08x is a stale handle, counts lost\n", htcb); + swarn("WARNING: TCB %p is a stale handle, counts lost\n", htcb); nxsem_freeholder(sem, pholder); } @@ -492,7 +492,7 @@ static int nxsem_restoreholderprio(FAR struct tcb_s *htcb, if (!nxsched_verify_tcb(htcb)) { - swarn("WARNING: TCB 0x%08x is a stale handle, counts lost\n", htcb); + swarn("WARNING: TCB %p is a stale handle, counts lost\n", htcb); pholder = nxsem_findholder(sem, htcb); if (pholder != NULL) diff --git a/sched/signal/sig_dispatch.c b/sched/signal/sig_dispatch.c index e57bbefdd1b..7f4ac043cb1 100644 --- a/sched/signal/sig_dispatch.c +++ b/sched/signal/sig_dispatch.c @@ -40,6 +40,7 @@ #include +#include #include #include #include @@ -305,7 +306,7 @@ int nxsig_tcbdispatch(FAR struct tcb_s *stcb, siginfo_t *info) int masked; int ret = OK; - sinfo("TCB=0x%08x signo=%d code=%d value=%d mask=%08x\n", + sinfo("TCB=%p signo=%d code=%d value=%d mask=%08" PRIx32 "\n", stcb, info->si_signo, info->si_code, info->si_value.sival_int, stcb->sigprocmask); diff --git a/sched/signal/sig_notification.c b/sched/signal/sig_notification.c index dae99a56164..2c0cf3c984a 100644 --- a/sched/signal/sig_notification.c +++ b/sched/signal/sig_notification.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -101,7 +102,7 @@ static void nxsig_notification_worker(FAR void *arg) int nxsig_notification(pid_t pid, FAR struct sigevent *event, int code, FAR struct sigwork_s *work) { - sinfo("pid=%p signo=%d code=%d sival_ptr=%p\n", + sinfo("pid=%" PRIu16 " signo=%d code=%d sival_ptr=%p\n", pid, event->sigev_signo, code, event->sigev_value.sival_ptr); /* Notify client via a signal? */ diff --git a/sched/signal/sig_timedwait.c b/sched/signal/sig_timedwait.c index 01c093ae2a4..b8797a515fd 100644 --- a/sched/signal/sig_timedwait.c +++ b/sched/signal/sig_timedwait.c @@ -195,7 +195,7 @@ void nxsig_wait_irq(FAR struct tcb_s *wtcb, int errcode) * is forever. * * If the info argument is non-NULL, the selected signal number is stored - * in the si_signo member and the cause of the signal is store din the + * in the si_signo member and the cause of the signal is stored in the * si_code member. The content of si_value is only meaningful if the * signal was generated by sigqueue() (or nxsig_queue). * diff --git a/sched/task/task_exithook.c b/sched/task/task_exithook.c index 8b9ff31d8dd..9b9477c0f32 100644 --- a/sched/task/task_exithook.c +++ b/sched/task/task_exithook.c @@ -634,6 +634,12 @@ void nxtask_exithook(FAR struct tcb_s *tcb, int status, bool nonblocking) nxtask_recover(tcb); + /* NOTE: signal handling needs to be done in a criticl section */ + +#ifdef CONFIG_SMP + irqstate_t flags = enter_critical_section(); +#endif + /* Send the SIGCHLD signal to the parent task group */ nxtask_signalparent(tcb, status); @@ -668,6 +674,10 @@ void nxtask_exithook(FAR struct tcb_s *tcb, int status, bool nonblocking) nxsig_cleanup(tcb); /* Deallocate Signal lists */ +#ifdef CONFIG_SMP + leave_critical_section(flags); +#endif + /* This function can be re-entered in certain cases. Set a flag * bit in the TCB to not that we have already completed this exit * processing. diff --git a/sched/timer/timer.h b/sched/timer/timer.h index 70c18e10610..5cdc4060cb4 100644 --- a/sched/timer/timer.h +++ b/sched/timer/timer.h @@ -50,6 +50,7 @@ struct posix_timer_s { FAR struct posix_timer_s *flink; + clockid_t pt_clock; /* Specifies the clock to use as the timing base. */ uint8_t pt_flags; /* See PT_FLAGS_* definitions */ uint8_t pt_crefs; /* Reference count */ pid_t pt_owner; /* Creator of timer */ diff --git a/sched/timer/timer_create.c b/sched/timer/timer_create.c index 43703883d37..9e4762294c8 100644 --- a/sched/timer/timer_create.c +++ b/sched/timer/timer_create.c @@ -124,8 +124,7 @@ static FAR struct posix_timer_s *timer_allocate(void) * value of the timer ID. * * Each implementation defines a set of clocks that can be used as timing - * bases for per-thread timers. All implementations shall support a - * clock_id of CLOCK_REALTIME. + * bases for per-thread timers. * * Input Parameters: * clockid - Specifies the clock to use as the timing base. @@ -157,9 +156,13 @@ int timer_create(clockid_t clockid, FAR struct sigevent *evp, { FAR struct posix_timer_s *ret; - /* Sanity checks. Also, we support only CLOCK_REALTIME */ + /* Sanity checks. */ - if (timerid == NULL || clockid != CLOCK_REALTIME) + if (timerid == NULL || (clockid != CLOCK_REALTIME +#ifdef CONFIG_CLOCK_MONOTONIC + && clockid != CLOCK_MONOTONIC +#endif /* CONFIG_CLOCK_MONOTONIC */ + )) { set_errno(EINVAL); return ERROR; @@ -176,6 +179,7 @@ int timer_create(clockid_t clockid, FAR struct sigevent *evp, /* Initialize the timer instance */ + ret->pt_clock = clockid; ret->pt_crefs = 1; ret->pt_owner = getpid(); ret->pt_delay = 0; diff --git a/sched/timer/timer_settime.c b/sched/timer/timer_settime.c index 26b7e41a2fe..660a04a8fd1 100644 --- a/sched/timer/timer_settime.c +++ b/sched/timer/timer_settime.c @@ -285,12 +285,9 @@ int timer_settime(timer_t timerid, int flags, if ((flags & TIMER_ABSTIME) != 0) { - /* Calculate a delay corresponding to the absolute time in 'value'. - * NOTE: We have internal knowledge the clock_abstime2ticks only - * returns an error if clockid != CLOCK_REALTIME. - */ + /* Calculate a delay corresponding to the absolute time in 'value' */ - clock_abstime2ticks(CLOCK_REALTIME, &value->it_value, &delay); + clock_abstime2ticks(timer->pt_clock, &value->it_value, &delay); } else { diff --git a/syscall/Makefile b/syscall/Makefile index 9ad30b62c49..3d94e7c05af 100644 --- a/syscall/Makefile +++ b/syscall/Makefile @@ -93,9 +93,12 @@ $(BIN3): $(WRAP_OBJS) $(SYSCALLWRAPS): .context +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) + .depend: Makefile $(SRCS) $(TOPDIR)$(DELIM).config - $(Q) $(MKDEP) $(PROXYDEPPATH) $(STUBDEPPATH) $(WRAPDEPPATH) \ - "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile DEPPATH="$(PROXYDEPPATH) $(STUBDEPPATH) $(WRAPDEPPATH)" $(Q) touch $@ depend: .depend diff --git a/tools/Config.mk b/tools/Config.mk index b3626b57c74..0e2aac9cab3 100644 --- a/tools/Config.mk +++ b/tools/Config.mk @@ -200,6 +200,23 @@ else MKDEP ?= $(TOPDIR)$(DELIM)tools$(DELIM)mkdeps$(HOSTEXEEXT) endif +# Per-file dependency generation rules + +%.dds: %.S + $(Q) $(MKDEP) --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $< > $@ + +%.ddc: %.c + $(Q) $(MKDEP) --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $< > $@ + +%.ddp: %.cpp + $(Q) $(MKDEP) --obj-suffix $(OBJEXT) $(DEPPATH) "$(CXX)" -- $(CXXFLAGS) -- $< > $@ + +%.ddx: %.cxx + $(Q) $(MKDEP) --obj-suffix $(OBJEXT) $(DEPPATH) "$(CXX)" -- $(CXXFLAGS) -- $< > $@ + +%.ddh: %.c + $(Q) $(MKDEP) --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(HOSTCFLAGS) -- $< > $@ + # INCDIR - Convert a list of directory paths to a list of compiler include # directories # Example: CFFLAGS += ${shell $(INCDIR) [options] "compiler" "dir1" "dir2" "dir2" ...} diff --git a/tools/Directories.mk b/tools/Directories.mk index 07989a41e62..e1d961dd3ea 100644 --- a/tools/Directories.mk +++ b/tools/Directories.mk @@ -112,9 +112,7 @@ CLEANDIRS += syscall endif endif -ifeq ($(CONFIG_LIB_ZONEINFO_ROMFS),y) CONTEXTDIRS += libs$(DELIM)libc -endif ifeq ($(CONFIG_NX),y) KERNDEPDIRS += graphics diff --git a/tools/README.txt b/tools/README.txt index 329de097036..92fb20e7023 100644 --- a/tools/README.txt +++ b/tools/README.txt @@ -1002,6 +1002,7 @@ testbuild.sh Default $WD/../nuttx, where $WD is the parent directory of the directory where this script is. -p only print the list of configs without running any builds + -C Skip tree cleanness check. -G Use "git clean -xfdq" instead of "make distclean" to clean the tree. This option may speed up the builds. However, note that: * This assumes that your trees are git based. diff --git a/tools/nuttx-gdbinit b/tools/nuttx-gdbinit index 2266bf4e5fb..89c95bf9c14 100644 --- a/tools/nuttx-gdbinit +++ b/tools/nuttx-gdbinit @@ -48,9 +48,15 @@ define _examine_target if ($_target_examined == 0x0) _examine_arch - python gdb.execute("set $_target_has_fpu = 0") - python if (type(gdb.lookup_global_symbol("fpuconfig")) is gdb.Symbol) : \ - gdb.execute("set $_target_has_fpu = 1") + set $_tcb0 = g_pidhash[0].tcb + set $_xcp_nregs = sizeof($_tcb0->xcp.regs) / sizeof($_tcb0->xcp.regs[0]) + set $_target_has_fpu = 0 + + if ($_streq($_target_arch, "armv7e-m") == 1) + if ($_xcp_nregs != 19) + set $_target_has_fpu = 1 + end + end python gdb.execute("set $_target_has_smp = 0") python if (type(gdb.lookup_global_symbol("g_assignedtasks")) is gdb.Symbol) : \ diff --git a/tools/testbuild.sh b/tools/testbuild.sh index 6c3d8d8c5c4..4260bd9b47f 100755 --- a/tools/testbuild.sh +++ b/tools/testbuild.sh @@ -50,6 +50,7 @@ unset JOPTION PRINTLISTONLY=0 GITCLEAN=0 SAVEARTIFACTS=0 +CHECKCLEAN=1 case $(uname -s) in Darwin*) @@ -84,6 +85,7 @@ function showusage { echo " -t provides the absolute path to top nuttx/ directory. Default ../nuttx" echo " -p only print the list of configs without running any builds" echo " -A store the build executable artifact in ARTIFACTDIR (defaults to ../buildartifacts" + echo " -C Skip tree cleanness check." echo " -G Use \"git clean -xfdq\" instead of \"make distclean\" to clean the tree." echo " This option may speed up the builds. However, note that:" echo " * This assumes that your trees are git based." @@ -138,6 +140,9 @@ while [ ! -z "$1" ]; do -A ) SAVEARTIFACTS=1 ;; + -C ) + CHECKCLEAN=0 + ;; -h ) showusage ;; @@ -208,14 +213,16 @@ function distclean { # Ensure nuttx and apps directory in clean state even with --ignored - if [ -d $nuttx/.git ] || [ -d $APPSDIR/.git ]; then - if [[ -n $(git -C $nuttx status --ignored -s) ]]; then - git -C $nuttx status --ignored - fail=1 - fi - if [[ -n $(git -C $APPSDIR status --ignored -s) ]]; then - git -C $APPSDIR status --ignored - fail=1 + if [ ${CHECKCLEAN} -ne 0 ]; then + if [ -d $nuttx/.git ] || [ -d $APPSDIR/.git ]; then + if [[ -n $(git -C $nuttx status --ignored -s) ]]; then + git -C $nuttx status --ignored + fail=1 + fi + if [[ -n $(git -C $APPSDIR status --ignored -s) ]]; then + git -C $APPSDIR status --ignored + fail=1 + fi fi fi fi @@ -269,14 +276,16 @@ function build { # Ensure nuttx and apps directory in clean state - if [ -d $nuttx/.git ] || [ -d $APPSDIR/.git ]; then - if [[ -n $(git -C $nuttx status -s) ]]; then - git -C $nuttx status - fail=1 - fi - if [[ -n $(git -C $APPSDIR status -s) ]]; then - git -C $APPSDIR status - fail=1 + if [ ${CHECKCLEAN} -ne 0 ]; then + if [ -d $nuttx/.git ] || [ -d $APPSDIR/.git ]; then + if [[ -n $(git -C $nuttx status -s) ]]; then + git -C $nuttx status + fail=1 + fi + if [[ -n $(git -C $APPSDIR status -s) ]]; then + git -C $APPSDIR status + fail=1 + fi fi fi diff --git a/video/Makefile b/video/Makefile index 92492d37530..87752291db9 100644 --- a/video/Makefile +++ b/video/Makefile @@ -55,9 +55,13 @@ $(COBJS): %$(OBJEXT): %.c $(BIN): $(OBJS) $(call ARCHIVE, $@, $(OBJS)) + +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) .depend: Makefile $(SRCS) $(TOPDIR)$(DELIM).config - $(Q) $(MKDEP) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile $(Q) touch $@ depend: .depend diff --git a/wireless/Makefile b/wireless/Makefile index edd90823289..b2c46fa6353 100644 --- a/wireless/Makefile +++ b/wireless/Makefile @@ -60,9 +60,13 @@ $(COBJS): %$(OBJEXT): %.c $(BIN): $(OBJS) $(call ARCHIVE, $@, $(OBJS)) + +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) .depend: Makefile $(SRCS) $(TOPDIR)$(DELIM).config - $(Q) $(MKDEP) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MAKE) makedepfile $(Q) touch $@ depend: .depend diff --git a/wireless/bluetooth/bt_att.c b/wireless/bluetooth/bt_att.c index dfcb5ed900e..9119338edd1 100644 --- a/wireless/bluetooth/bt_att.c +++ b/wireless/bluetooth/bt_att.c @@ -1865,7 +1865,7 @@ FAR struct bt_buf_s *bt_att_create_pdu(FAR struct bt_conn_s *conn, if (len + sizeof(op) > att->mtu) { - wlwarn("ATT MTU exceeded, max %u, wanted %u\n", att->mtu, len); + wlwarn("ATT MTU exceeded, max %u, wanted %zu\n", att->mtu, len); return NULL; } diff --git a/wireless/bluetooth/bt_buf.c b/wireless/bluetooth/bt_buf.c index e4d760efde8..cb4a9d55622 100644 --- a/wireless/bluetooth/bt_buf.c +++ b/wireless/bluetooth/bt_buf.c @@ -365,7 +365,7 @@ FAR struct bt_buf_s *bt_buf_alloc(enum bt_buf_type_e type, buf->data = buf->frame->io_data + reserve_head; } - wlinfo("buf %p type %d reserve %u\n", buf, buf->type, reserve_head); + wlinfo("buf %p type %d reserve %zu\n", buf, buf->type, reserve_head); return buf; } @@ -531,7 +531,7 @@ FAR void *bt_buf_extend(FAR struct bt_buf_s *buf, size_t len) { FAR uint8_t *tail = bt_buf_tail(buf); - wlinfo("buf %p len %u\n", buf, len); + wlinfo("buf %p len %zu\n", buf, len); DEBUGASSERT(bt_buf_tailroom(buf) >= len); @@ -582,7 +582,7 @@ void bt_buf_put_le16(FAR struct bt_buf_s *buf, uint16_t value) FAR void *bt_buf_provide(FAR struct bt_buf_s *buf, size_t len) { - wlinfo("buf %p len %u\n", buf, len); + wlinfo("buf %p len %zu\n", buf, len); DEBUGASSERT(buf != NULL && buf->frame != NULL && bt_buf_headroom(buf) >= len); @@ -609,7 +609,7 @@ FAR void *bt_buf_provide(FAR struct bt_buf_s *buf, size_t len) FAR void *bt_buf_consume(FAR struct bt_buf_s *buf, size_t len) { - wlinfo("buf %p len %u\n", buf, len); + wlinfo("buf %p len %zu\n", buf, len); DEBUGASSERT(buf->len >= len); diff --git a/wireless/bluetooth/bt_ioctl.c b/wireless/bluetooth/bt_ioctl.c index ff59932e806..486ce83b3b8 100644 --- a/wireless/bluetooth/bt_ioctl.c +++ b/wireless/bluetooth/bt_ioctl.c @@ -477,7 +477,7 @@ int btnet_ioctl(FAR struct net_driver_s *netdev, int cmd, unsigned long arg) FAR struct btreq_s *btreq = (FAR struct btreq_s *)((uintptr_t)arg); int ret; - wlinfo("cmd=%04x arg=%ul\n", cmd, arg); + wlinfo("cmd=%04x arg=%lu\n", cmd, arg); DEBUGASSERT(netdev != NULL && netdev->d_private != NULL); if (btreq == NULL)