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Alan Carvalho
2017-05-23 14:21:56 -03:00
parent c2e8d2e51b 0c9abbfe67
commit bb0685c0db
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Documentation/NuttxPortingGuide.html
+431 -1
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@@ -12,7 +12,7 @@
<h1><big><font color="#3c34ec">
<i>NuttX RTOS Porting Guide</i>
</font></big></h1>
<p>Last Updated: February 7, 2017</p>
<p>Last Updated: May 20, 2017</p>
</td>
</tr>
</table>
@@ -178,6 +178,13 @@
<a href="#leddefinitions">4.11.2 LED Definitions</a><br>
<a href="#ledapis">4.11.3 Common LED interfaces</a>
</ul>
<a href="#iobs">4.12 I/O Buffer Management</a>
<ul>
<a href="#iobconfig">4.12.1 Configuration Options</a><br>
<a href="#iobthrottle">4.12.2 Throttling</a><br>
<a href="#iobtypes">4.12.3 Public Types</a><br>
<a href="#iobprotos">4.12.4 Public Function Prototypes</a>
</ul>
</ul>
<a href="#NxFileSystem">5.0 NuttX File System</a><br>
<a href="#DeviceDrivers">6.0 NuttX Device Drivers</a>
@@ -4172,6 +4179,429 @@ void board_autoled_off(int led);
</li>
</ul>
<h2><a name="iobs">4.12 I/O Buffer Management</a></h2>
NuttX supports generic I/O buffer management (IOB) logic.
This logic was originally added to support network I/O buffering, but has been generalized to meet buffering requirements by all device drivers.
At the time of this writing, IOBs are currently used not only be networking but also by logic in <code>drivers/syslog</code> and <code>drivers/wireless</code>.
NOTE that some of the wording in this section still reflects those legacy roots as a part of the networking subsystem.
This objectives of this feature are:
<ol>
<li>
Provide common I/O buffer management logic for all drivers,
</li>
<li>
Support I/O buffer allocation from both the tasking and interrupt level contexts.
</li>
<li>
Use a fixed amount of pre-allocated memory.
</li>
<li>
No costly, non-deterministic dynamic memory allocation.
</li>
<li>
When the fixed number of pre-allocated I/O buffers is exhausted, further attempts to allocate memory from tasking logic will cause the task to block and wait until a an I/O buffer to be freed.
</li>
<li>
Each I/O buffer should be small, but can be chained together to support buffering of larger thinks such as full size network packets.
</li>
<li>
Support <i>throttling</i> logic to prevent lower priority tasks from hogging all available I/O buffering.
</li>
</ol>
<h3><a name="iobconfig">4.12.1 Configuration Options</a></h3>
<dl>
<dt><code>CONFIG_MM_IOB</code>
<dd>Enables generic I/O buffer support. This setting will build the common I/O buffer (IOB) support library.
<dt><code>CONFIG_IOB_NBUFFERS</code>
<dd>Number of pre-allocated I/O buffers. Each packet is represented by a series of small I/O buffers in a chain. This setting determines the number of preallocated I/O buffers available for packet data.
The default value is setup for network support. The default is 8 buffers if neither TCP read-ahead or TCP write buffering is enabled (neither <code>CONFIG_NET_TCP_WRITE_BUFFERS</code> nor <code>CONFIG_NET_TCP_READAHEAD</code>), 24 if only write buffering is enabled, and 36 if both read-ahead and write buffering are enabled.
<dt><code>CONFIG_IOB_BUFSIZE</code>
<dd>Payload size of one I/O buffer. Each packet is represented by a series of small I/O buffers in a chain. This setting determines the data payload each preallocated I/O buffer. The default value is 196 bytes.
<dt><code>CONFIG_IOB_NCHAINS</code>
<dd>Number of pre-allocated I/O buffer chain heads. These tiny nodes are used as <i>containers</i> to support queueing of I/O buffer chains. This will limit the number of I/O transactions that can be <i>in-flight</i> at any give time. The default value of zero disables this features.
<dd>These generic I/O buffer chain containers are not currently used by any logic in NuttX. That is because their other other specialized I/O buffer chain containers that also carry a payload of usage specific information.
The default value is zero if nether TCP nor UDP read-ahead buffering is enabled (i.e., neither <code>CONFIG_NET_TCP_READAHEAD</code> && !<code>CONFIG_NET_UDP_READAHEAD</code> or eight if either is enabled.
<dt><code>CONFIG_IOB_THROTTLE</code>
<dd>I/O buffer throttle value. TCP write buffering and read-ahead buffer use the same pool of free I/O buffers. In order to prevent uncontrolled incoming TCP packets from hogging all of the available, pre-allocated I/O buffers, a throttling value is required. This throttle value assures that I/O buffers will be denied to the read-ahead logic before TCP writes are halted.
The default 0 if neither TCP write buffering nor TCP reada-ahead buffering is enabled. Otherwise, the default is 8.
<dt><code>CONFIG_IOB_DEBUG</code>
<dd>Force I/O buffer debug. This option will force debug output from I/O buffer logic. This is not normally something that would want to do but is convenient if you are debugging the I/O buffer logic and do not want to get overloaded with other un-related debug output.
NOTE that this selection is not avaiable if DEBUG features are not enabled (<code>CONFIG_DEBUG_FEATURES</code>) with IOBs are being used to syslog buffering logic (<code>CONFIG_SYSLOG_BUFFER</code>).
</dl>
<h3><a name="iobthrottle">4.12.2 Throttling</a></h3>
<b></b>
An allocation throttle was added. I/O buffer allocation logic supports a throttle value originally for read-ahead buffering to prevent the read-ahead logic from consuming all available I/O buffers and blocking the write buffering logic. This throttle logic is only needed for networking only if both write buffering and read-ahead buffering are used. Of use of I/O buffering might have other motivations for throttling.
<h3><a name="iobtypes">4.12.3 Public Types</a></h3>
<p>
This structure epresents one I/O buffer. A packet is contained by one or more I/O buffers in a chain. The <code>io_pktlen</code> is only valid for the I/O buffer at the head of the chain.
</p>
<pre>
struct iob_s
{
/* Singly-link list support */
FAR struct iob_s *io_flink;
/* Payload */
#if CONFIG_IOB_BUFSIZE < 256
uint8_t io_len; /* Length of the data in the entry */
uint8_t io_offset; /* Data begins at this offset */
#else
uint16_t io_len; /* Length of the data in the entry */
uint16_t io_offset; /* Data begins at this offset */
#endif
uint16_t io_pktlen; /* Total length of the packet */
uint8_t io_data[CONFIG_IOB_BUFSIZE];
};
</pre>
<p>
This container structure supports queuing of I/O buffer chains. This structure is intended only for internal use by the IOB module.
</p>
<pre>
#if CONFIG_IOB_NCHAINS > 0
struct iob_qentry_s
{
/* Singly-link list support */
FAR struct iob_qentry_s *qe_flink;
/* Payload -- Head of the I/O buffer chain */
FAR struct iob_s *qe_head;
};
#endif /* CONFIG_IOB_NCHAINS > 0 */
</pre>
<p>
The I/O buffer queue head structure.
</p>
<pre>
#if CONFIG_IOB_NCHAINS > 0
struct iob_queue_s
{
/* Head of the I/O buffer chain list */
FAR struct iob_qentry_s *qh_head;
FAR struct iob_qentry_s *qh_tail;
};
#endif /* CONFIG_IOB_NCHAINS > 0 */
</pre>
<h3><a name="iobprotos">4.12.4 Public Function Prototypes</a></h3>
<ul>
<li><a href="#iob_initialize">4.12.4.1 <code>iob_initialize()</code></a></li>
<li><a href="#iob_alloc">4.12.4.2 <code>iob_alloc()</code></a></li>
<li><a href="#iob_tryalloc">4.12.4.3 <code>iob_tryalloc()</code></a></li>
<li><a href="#iob_free">4.12.4.4 <code>iob_free()</code></a></li>
<li><a href="#iob_free_chain">4.12.4.5 <code>iob_free_chain()</code></a></li>
<li><a href="#iob_add_queue">4.12.4.6 <code>iob_add_queue()</code></a></li>
<li><a href="#iob_tryadd_queue">4.12.4.7 <code>iob_tryadd_queue()</code></a></li>
<li><a href="#iob_remove_queue">4.12.4.8 <code>iob_remove_queue()</code></a></li>
<li><a href="#iob_peek_queue">4.12.4.9 <code>iob_peek_queue()</code></a></li>
<li><a href="#iob_free_queue">4.12.4.10 <code>iob_free_queue()</code></a></li>
<li><a href="#iob_copyin">4.12.4.11 <code>iob_copyin()</code></a></li>
<li><a href="#iob_trycopyin">4.12.4.12 <code>iob_trycopyin()</code></a></li>
<li><a href="#iob_copyout">4.12.4.13 <code>iob_copyout()</code></a></li>
<li><a href="#iob_clone">4.12.4.14 <code>iob_clone()</code></a></li>
<li><a href="#iob_concat">4.12.4.15 <code>iob_concat()</code></a></li>
<li><a href="#iob_trimhead">4.12.4.16 <code>iob_trimhead()</code></a></li>
<li><a href="#iob_trimhead_queue">4.12.4.17 <code>iob_trimhead_queue()</code></a></li>
<li><a href="#iob_trimtail">4.12.4.18 <code>iob_trimtail()</code></a></li>
<li><a href="#iob_pack">4.12.4.19 <code>iob_pack()</code></a></li>
<li><a href="#iob_contig">4.12.4.20 <code>iob_contig()</code></a></li>
<li><a href="#iob_dump">4.12.4.21 <code>iob_dump()</code></a></li>
</ul>
<h4><a name="iob_initialize">4.12.4.1 <code>iob_initialize()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
void iob_initialize(void);
</pre>
<p><b>Description</b>.
Set up the I/O buffers for normal operations.
</p>
<h4><a name="iob_alloc">4.12.4.2 <code>iob_alloc()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
FAR struct iob_s *iob_alloc(bool throttled);
</pre>
<p><b>Description</b>.
Allocate an I/O buffer by taking the buffer at the head of the free list.
</p>
<h4><a name="iob_tryalloc">4.12.4.3 <code>iob_tryalloc()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
FAR struct iob_s *iob_tryalloc(bool throttled);
</pre>
<p><b>Description</b>.
Try to allocate an I/O buffer by taking the buffer at the head of the free list without waiting for a buffer to become free.
</p>
<h4><a name="iob_free">4.12.4.4 <code>iob_free()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
FAR struct iob_s *iob_free(FAR struct iob_s *iob);
</pre>
<p><b>Description</b>.
Free the I/O buffer at the head of a buffer chain returning it to the free list. The link to the next I/O buffer in the chain is return.
</p>
<h4><a name="iob_free_chain">4.12.4.5 <code>iob_free_chain()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
void iob_free_chain(FAR struct iob_s *iob);
</pre>
<p><b>Description</b>.
Free an entire buffer chain, starting at the beginning of the I/O buffer chain
</p>
<h4><a name="iob_add_queue">4.12.4.6 <code>iob_add_queue()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
#if CONFIG_IOB_NCHAINS > 0
int iob_add_queue(FAR struct iob_s *iob, FAR struct iob_queue_s *iobq);
#endif /* CONFIG_IOB_NCHAINS > 0 */
</pre>
<p><b>Description</b>.
Add one I/O buffer chain to the end of a queue. May fail due to lack of resources.
</p>
<h4><a name="iob_tryadd_queue">4.12.4.7 <code>iob_tryadd_queue()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
#if CONFIG_IOB_NCHAINS > 0
int iob_tryadd_queue(FAR struct iob_s *iob, FAR struct iob_queue_s *iobq);
#endif /* CONFIG_IOB_NCHAINS > 0 */
</pre>
<p><b>Description</b>.
Add one I/O buffer chain to the end of a queue without waiting for resources to become free.
</p>
<h4><a name="iob_remove_queue">4.12.4.8 <code>iob_remove_queue()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
#if CONFIG_IOB_NCHAINS > 0
FAR struct iob_s *iob_remove_queue(FAR struct iob_queue_s *iobq);
#endif /* CONFIG_IOB_NCHAINS > 0 */
</pre>
<p><b>Description</b>.
Remove and return one I/O buffer chain from the head of a queue.
</p>
<p><b>Returned Value</b>.
Returns a reference to the I/O buffer chain at the head of the queue.
</p>
<h4><a name="iob_peek_queue">4.12.4.9 <code>iob_peek_queue()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
#if CONFIG_IOB_NCHAINS > 0
FAR struct iob_s *iob_peek_queue(FAR struct iob_queue_s *iobq);
#endif
</pre>
<p><b>Description</b>.
Return a reference to the I/O buffer chain at the head of a queue. This is similar to iob_remove_queue except that the I/O buffer chain is in place at the head of the queue. The I/O buffer chain may safely be modified by the caller but must be removed from the queue before it can be freed.
</p>
<p><b>Returned Value</b>.
Returns a reference to the I/O buffer chain at the head of the queue.
</p>
<h4><a name="iob_free_queue">4.12.4.10 <code>iob_free_queue()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
#if CONFIG_IOB_NCHAINS > 0
void iob_free_queue(FAR struct iob_queue_s *qhead);
#endif /* CONFIG_IOB_NCHAINS > 0 */
</pre>
<p><b>Description</b>.
Free an entire queue of I/O buffer chains.
</p>
<h4><a name="iob_copyin">4.12.4.11 <code>iob_copyin()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
int iob_copyin(FAR struct iob_s *iob, FAR const uint8_t *src,
unsigned int len, unsigned int offset, bool throttled);
</pre>
<p><b>Description</b>.
Copy data <code>len</code> bytes from a user buffer into the I/O buffer chain, starting at <code>offset</code>, extending the chain as necessary.
</p>
<h4><a name="iob_trycopyin">4.12.4.12 <code>iob_trycopyin()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
int iob_trycopyin(FAR struct iob_s *iob, FAR const uint8_t *src,
unsigned int len, unsigned int offset, bool throttled);
</pre>
<p><b>Description</b>.
Copy data <code>len</code> bytes from a user buffer into the I/O buffer chain, starting at <code>offset</code>, extending the chain as necessary BUT without waiting if buffers are not available.
</p>
<h4><a name="iob_copyout">4.12.4.13 <code>iob_copyout()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
int iob_copyout(FAR uint8_t *dest, FAR const struct iob_s *iob,
unsigned int len, unsigned int offset);
</pre>
<p><b>Description</b>.
Copy data <code>len</code> bytes of data into the user buffer starting at <code>offset</code> in the I/O buffer, returning that actual number of bytes copied out.
</p>
<h4><a name="iob_clone">4.12.4.14 <code>iob_clone()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
int iob_clone(FAR struct iob_s *iob1, FAR struct iob_s *iob2, bool throttled);
</pre>
<p><b>Description</b>.
Duplicate (and pack) the data in <code>iob1</code> in <code>iob2</code>. <code>iob2</code> must be empty.
</p>
<h4><a name="iob_concat">4.12.4.15 <code>iob_concat()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
void iob_concat(FAR struct iob_s *iob1, FAR struct iob_s *iob2);
</pre>
<p><b>Description</b>.
Concatenate iob_s chain iob2 to iob1.
</p>
<h4><a name="iob_trimhead">4.12.4.16 <code>iob_trimhead()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
FAR struct iob_s *iob_trimhead(FAR struct iob_s *iob, unsigned int trimlen);
</pre>
<p><b>Description</b>.
Remove bytes from the beginning of an I/O chain. Emptied I/O buffers are freed and, hence, the beginning of the chain may change.
</p>
<h4><a name="iob_trimhead_queue">4.12.4.17 <code>iob_trimhead_queue()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
#if CONFIG_IOB_NCHAINS > 0
FAR struct iob_s *iob_trimhead_queue(FAR struct iob_queue_s *qhead,
unsigned int trimlen);
#endif
</pre>
<p><b>Description</b>.
Remove bytes from the beginning of an I/O chain at the head of the queue. Emptied I/O buffers are freed and, hence, the head of the queue may change.
</p>
<p>
This function is just a wrapper around iob_trimhead() that assures that the iob at the head of queue is modified with the trimming operations.
</p>
<p><b>Returned Value</b>.
The new iob at the head of the queue is returned.
</p>
<h4><a name="iob_trimtail">4.12.4.18 <code>iob_trimtail()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
FAR struct iob_s *iob_trimtail(FAR struct iob_s *iob, unsigned int trimlen);
</pre>
<p><b>Description</b>.
Remove bytes from the end of an I/O chain. Emptied I/O buffers are freed NULL will be returned in the special case where the entry I/O buffer chain is freed.
</p>
<h4><a name="iob_pack">4.12.4.19 <code>iob_pack()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
FAR struct iob_s *iob_pack(FAR struct iob_s *iob);
</pre>
<p><b>Description</b>.
Pack all data in the I/O buffer chain so that the data offset is zero and all but the final buffer in the chain are filled. Any emptied buffers at the end of the chain are freed.
</p>
<h4><a name="iob_contig">4.12.4.20 <code>iob_contig()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
int iob_contig(FAR struct iob_s *iob, unsigned int len);
</pre>
<p><b>Description</b>.
Ensure that there is <code>len</code> bytes of contiguous space at the beginning of the I/O buffer chain starting at <code>iob</code>.
</p>
<h4><a name="iob_dump">4.12.4.21 <code>iob_dump()</code></a></h4>
<p><b>Function Prototype</b>:
<pre>
#include &lt;nuttx/mm/iob.h&gt;
#ifdef CONFIG_DEBUG_FEATURES
void iob_dump(FAR const char *msg, FAR struct iob_s *iob, unsigned int len,
unsigned int offset);
#endif
</pre>
<p><b>Description</b>.
Dump the contents of a I/O buffer chain
</p>
<table width ="100%">
<tr bgcolor="#e4e4e4">
<td>
TODO
+39 -2
View File
@@ -1,4 +1,4 @@
NuttX TODO List (Last updated April 15, 2017)
NuttX TODO List (Last updated May 18, 2017)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -25,7 +25,7 @@ nuttx/:
(12) Libraries (libc/, libm/)
(10) File system/Generic drivers (fs/, drivers/)
(9) Graphics Subsystem (graphics/)
(2) Build system / Toolchains
(3) Build system / Toolchains
(3) Linux/Cywgin simulation (arch/sim)
(4) ARM (arch/arm/)
@@ -1825,6 +1825,43 @@ o Build system
Priority: Low, since I am not aware of anyone using the Windows Native build.
But, of course, very high if you want to use it.
Title: CONTROL-C CAN BREAK DEPENDENCIES
Description: If you control C out of a make, then there are things that can go
wrong. For one, you can break the dependencies in this scenario:
- The build in a given directory begins with all of the compilations.
On terminal, this the long phase with CC: on each line. As each
.o file is created, it is timestamped with the current time.
- The dependencies on each .o are such that the C file will be re-
compile if the .o file is OLDER that the corresponding .a archive
file.
- The compilation phase is followed by a single, relatively short
AR: phase that adds each of the file to the .a archive file. As
each file is added to archive, the timestamp of the of archive is
updated to the current time. After the first .o file has been
added, then archive file will have a newly timestamp than any of
the newly compiled .o file.
- If the user aborts with control-C during this AR: phase, then we
are left with: (1) not all of the files have bee added to the
archive, and (2) the archive file has a newer timestamp than any
of the .o file.
So when the make is restarted after a control, the dependencies will
see that the .a archive file has the newer time stamp and those .o
file will never be added to the archive until the directory is cleaned
or some other dependency changes.
Status Open
Priority: Medium-High. It is a rare event that control-C happens at just the
point in time. However, when it does occur the resulting code may
have binary incompatiblies in the code taken from the out-of-sync
archives and cost a lot of debug time before you realize the issue.
A work-around is to do 'make clean' if you ever decide to control-C
out of a make.
o Other drivers (drivers/)
^^^^^^^^^^^^^^^^^^^^^^^^
arch/Kconfig
+4
View File
@@ -124,6 +124,10 @@ source arch/xtensa/Kconfig
source arch/z16/Kconfig
source arch/z80/Kconfig
config ARCH_TOOLCHAIN_IAR
bool
default n
config ARCH_TOOLCHAIN_GNU
bool
default n
arch/arm/Kconfig
-9
View File
@@ -456,15 +456,6 @@ config ARCH_CHIP
default "tms570" if ARCH_CHIP_TMS570
default "xmc4" if ARCH_CHIP_XMC4
config ARM_TOOLCHAIN_IAR
bool
default n
config ARM_TOOLCHAIN_GNU
bool
default n
select ARCH_TOOLCHAIN_GNU
config ARMV7M_USEBASEPRI
bool "Use BASEPRI Register"
default n
arch/arm/src/Makefile
+2 -2
View File
@@ -172,10 +172,10 @@ VPATH += chip
VPATH += common
VPATH += $(ARCH_SUBDIR)
ifeq ($(CONFIG_ARM_TOOLCHAIN_IAR),y)
ifeq ($(CONFIG_ARCH_TOOLCHAIN_IAR),y)
VPATH += chip$(DELIM)iar
VPATH += $(ARCH_SUBDIR)$(DELIM)iar
else # ifeq ($(CONFIG_ARM_TOOLCHAIN_GNU),y)
else # ifeq ($(CONFIG_ARCH_TOOLCHAIN_GNU),y)
VPATH += chip$(DELIM)gnu
VPATH += $(ARCH_SUBDIR)$(DELIM)gnu
endif
arch/arm/src/armv6-m/Kconfig
+9 -9
View File
@@ -13,41 +13,41 @@ choice
config ARMV6M_TOOLCHAIN_ATOLLIC
bool "Atollic Lite/Pro for Windows"
depends on TOOLCHAIN_WINDOWS
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
config ARMV6M_TOOLCHAIN_BUILDROOT
bool "Buildroot (Cygwin or Linux)"
depends on !WINDOWS_NATIVE
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
config ARMV6M_TOOLCHAIN_CODEREDL
bool "CodeRed for Linux"
depends on HOST_LINUX
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
config ARMV6M_TOOLCHAIN_CODEREDW
bool "CodeRed for Windows"
depends on TOOLCHAIN_WINDOWS
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
config ARMV6M_TOOLCHAIN_CODESOURCERYL
bool "CodeSourcery GNU toolchain under Linux"
depends on HOST_LINUX
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
config ARMV6M_TOOLCHAIN_CODESOURCERYW
bool "CodeSourcery GNU toolchain under Windows"
depends on TOOLCHAIN_WINDOWS
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
config ARMV6M_TOOLCHAIN_DEVKITARM
bool "devkitARM GNU toolchain"
depends on TOOLCHAIN_WINDOWS
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
config ARMV6M_TOOLCHAIN_GNU_EABIL
bool "Generic GNU EABI toolchain under Linux (or other POSIX environment)"
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
configured for arm-none-eabi.
@@ -55,7 +55,7 @@ config ARMV6M_TOOLCHAIN_GNU_EABIL
config ARMV6M_TOOLCHAIN_GNU_EABIW
bool "Generic GNU EABI toolchain under Windows"
depends on TOOLCHAIN_WINDOWS
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
configured for arm-none-eabi.
arch/arm/src/armv7-a/Kconfig
+7 -7
View File
@@ -133,12 +133,12 @@ choice
config ARMV7A_TOOLCHAIN_BUILDROOT
bool "Buildroot (Cygwin or Linux)"
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
depends on !WINDOWS_NATIVE
config ARMV7A_TOOLCHAIN_CODESOURCERYL
bool "CodeSourcery GNU toolchain under Linux"
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
depends on HOST_LINUX
---help---
For use with the GNU toolchain built with the NuttX buildroot package.
@@ -147,24 +147,24 @@ config ARMV7A_TOOLCHAIN_CODESOURCERYL
config ARMV7A_TOOLCHAIN_CODESOURCERYW
bool "CodeSourcery GNU toolchain under Windows"
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
depends on TOOLCHAIN_WINDOWS
config ARMV7A_TOOLCHAIN_DEVKITARM
bool "devkitARM GNU toolchain"
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
depends on TOOLCHAIN_WINDOWS
config ARMV7A_TOOLCHAIN_GNU_EABIL
bool "Generic GNU EABI toolchain under Linux (or other POSIX environment)"
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
configured for arm-none-eabi-.
config ARMV7A_TOOLCHAIN_GNU_EABIW
bool "Generic GNU EABI toolchain under Windows"
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
depends on TOOLCHAIN_WINDOWS
---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
@@ -172,7 +172,7 @@ config ARMV7A_TOOLCHAIN_GNU_EABIW
config ARMV7A_TOOLCHAIN_GNU_OABI
bool "Generic GNU OABI toolchain"
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
---help---
This option should work for any GNU toolchain configured for arm-elf-.
arch/arm/src/armv7-m/Kconfig
+12 -12
View File
@@ -54,52 +54,52 @@ choice
config ARMV7M_TOOLCHAIN_IARW
bool "IAR for Windows"
depends on TOOLCHAIN_WINDOWS
select ARM_TOOLCHAIN_IAR
select ARCH_TOOLCHAIN_IAR
config ARMV7M_TOOLCHAIN_IARL
bool "IAR for Linux"
depends on HOST_LINUX
select ARM_TOOLCHAIN_IAR
select ARCH_TOOLCHAIN_IAR
config ARMV7M_TOOLCHAIN_ATOLLIC
bool "Atollic Lite/Pro for Windows"
depends on TOOLCHAIN_WINDOWS
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
config ARMV7M_TOOLCHAIN_BUILDROOT
bool "Buildroot (Cygwin or Linux)"
depends on !WINDOWS_NATIVE
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
config ARMV7M_TOOLCHAIN_CODEREDL
bool "CodeRed for Linux"
depends on HOST_LINUX
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
config ARMV7M_TOOLCHAIN_CODEREDW
bool "CodeRed for Windows"
depends on TOOLCHAIN_WINDOWS
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
config ARMV7M_TOOLCHAIN_CODESOURCERYL
bool "CodeSourcery GNU toolchain under Linux"
depends on HOST_LINUX
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
config ARMV7M_TOOLCHAIN_CODESOURCERYW
bool "CodeSourcery GNU toolchain under Windows"
depends on TOOLCHAIN_WINDOWS
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
config ARMV7M_TOOLCHAIN_DEVKITARM
bool "devkitARM GNU toolchain"
depends on TOOLCHAIN_WINDOWS
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
config ARMV7M_TOOLCHAIN_GNU_EABIL
bool "Generic GNU EABI toolchain under Linux (or other POSIX environment)"
depends on !WINDOWS_NATIVE
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
configured for arm-none-eabi.
@@ -107,7 +107,7 @@ config ARMV7M_TOOLCHAIN_GNU_EABIL
config ARMV7M_TOOLCHAIN_GNU_EABIW
bool "Generic GNU EABI toolchain under Windows"
depends on TOOLCHAIN_WINDOWS
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
configured for arm-none-eabi.
@@ -115,7 +115,7 @@ config ARMV7M_TOOLCHAIN_GNU_EABIW
config ARMV7M_TOOLCHAIN_RAISONANCE
bool "STMicro Raisonance for Windows"
depends on TOOLCHAIN_WINDOWS
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
endchoice
arch/arm/src/armv7-r/Kconfig
+7 -7
View File
@@ -149,12 +149,12 @@ choice
config ARMV7R_TOOLCHAIN_BUILDROOT
bool "Buildroot (Cygwin or Linux)"
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
depends on !WINDOWS_NATIVE
config ARMV7R_TOOLCHAIN_CODESOURCERYL
bool "CodeSourcery GNU toolchain under Linux"
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
depends on HOST_LINUX
---help---
For use with the GNU toolchain built with the NuttX buildroot package.
@@ -163,24 +163,24 @@ config ARMV7R_TOOLCHAIN_CODESOURCERYL
config ARMV7R_TOOLCHAIN_CODESOURCERYW
bool "CodeSourcery GNU toolchain under Windows"
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
depends on TOOLCHAIN_WINDOWS
config ARMV7R_TOOLCHAIN_DEVKITARM
bool "devkitARM GNU toolchain"
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
depends on TOOLCHAIN_WINDOWS
config ARMV7R_TOOLCHAIN_GNU_EABIL
bool "Generic GNU EABI toolchain under Linux (or other POSIX environment)"
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
configured for arm-none-eabi-.
config ARMV7R_TOOLCHAIN_GNU_EABIW
bool "Generic GNU EABI toolchain under Windows"
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
depends on TOOLCHAIN_WINDOWS
---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
@@ -188,7 +188,7 @@ config ARMV7R_TOOLCHAIN_GNU_EABIW
config ARMV7R_TOOLCHAIN_GNU_OABI
bool "Generic GNU OABI toolchain"
select ARM_TOOLCHAIN_GNU
select ARCH_TOOLCHAIN_GNU
---help---
This option should work for any GNU toolchain configured for arm-elf-.
arch/arm/src/stm32/Kconfig
+89
View File
@@ -1530,6 +1530,7 @@ config STM32_STM32F40XX
select STM32_HAVE_TIM4
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
select STM32_HAVE_I2S3
select STM32_HAVE_I2C2
select STM32_HAVE_I2C3
@@ -1542,6 +1543,9 @@ config STM32_STM32F401
select STM32_HAVE_TIM9
select STM32_HAVE_TIM10
select STM32_HAVE_TIM11
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
select STM32_HAVE_I2S3
config STM32_STM32F410
bool
@@ -1563,6 +1567,9 @@ config STM32_STM32F411
select STM32_HAVE_TIM9
select STM32_HAVE_TIM10
select STM32_HAVE_TIM11
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
select STM32_HAVE_I2S3
select STM32_HAVE_SPI4
select STM32_HAVE_SPI5
@@ -1655,6 +1662,9 @@ config STM32_STM32F427
select STM32_HAVE_DAC2
select STM32_HAVE_RNG
select STM32_HAVE_ETHMAC
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
select STM32_HAVE_I2S3
select STM32_HAVE_SPI4
select STM32_HAVE_SPI5
select STM32_HAVE_SPI6
@@ -1691,6 +1701,9 @@ config STM32_STM32F429
select STM32_HAVE_DAC2
select STM32_HAVE_RNG
select STM32_HAVE_ETHMAC
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
select STM32_HAVE_I2S3
select STM32_HAVE_SPI4
select STM32_HAVE_SPI5
select STM32_HAVE_SPI6
@@ -2016,6 +2029,10 @@ config STM32_HAVE_SPI3
bool
default n
config STM32_HAVE_I2S3
bool
default n
config STM32_HAVE_SPI4
bool
default n
@@ -2353,6 +2370,13 @@ config STM32_SPI3
select SPI
select STM32_SPI
config STM32_I2S3
bool "I2S3"
default n
depends on STM32_HAVE_I2S3
select I2S
select STM32_I2S
config STM32_SPI4
bool "SPI4"
default n
@@ -2610,6 +2634,11 @@ config STM32_SPI3_REMAP
default n
depends on STM32_STM32F10XX && STM32_SPI3 && !STM32_VALUELINE
config STM32_I2S3_REMAP
bool "I2S3 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_I2S3 && !STM32_VALUELINE
choice
prompt "TIM1 Alternate Pin Mappings"
depends on STM32_STM32F10XX && STM32_TIM1
@@ -6270,6 +6299,66 @@ config STM32_SPI_DMA
endmenu
menu "I2S Configuration"
depends on STM32_I2S3
config STM32_I2S_MCK
bool "I2S_MCK"
default n
---help---
TBD.
config STM32_I2S_MAXINFLIGHT
int "I2S queue size"
default 16
---help---
This is the total number of transfers, both RX and TX, that can be
enqueue before the caller is required to wait. This setting
determines the number certain queue data structures that will be
pre-allocated.
comment "I2S3 Configuration"
config STM32_I2S3_DATALEN
int "Data width (bits)"
default 16
---help---
Data width in bits. This is a default value and may be change
via the I2S interface
#if STM32_I2S
config STM32_I2S3_RX
bool "Enable I2C receiver"
default n
---help---
Enable I2S receipt logic
config STM32_I2S3_TX
bool "Enable I2C transmitter"
default n
---help---
Enable I2S transmission logic
config STM32_I2S_DMADEBUG
bool "I2S DMA transfer debug"
depends on DEBUG_DMA
default n
---help---
Enable special debug instrumentation analyze I2S DMA data transfers.
This logic is as non-invasive as possible: It samples DMA
registers at key points in the data transfer and then dumps all of
the registers at the end of the transfer.
config STM32_I2S_REGDEBUG
bool "SSC Register level debug"
depends on DEBUG
default n
---help---
Output detailed register-level SSC device debug information.
Very invasive! Requires also DEBUG.
endmenu # I2S Configuration
menu "I2C Configuration"
depends on STM32_I2C
arch/arm/src/stm32/Make.defs
+1 -1
View File
@@ -101,7 +101,7 @@ CHIP_ASRCS =
CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c
CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c
CHIP_CSRCS += stm32_irq.c stm32_dma.c stm32_lowputc.c
CHIP_CSRCS += stm32_serial.c stm32_spi.c stm32_sdio.c stm32_tim.c
CHIP_CSRCS += stm32_serial.c stm32_spi.c stm32_i2s.c stm32_sdio.c stm32_tim.c
CHIP_CSRCS += stm32_waste.c stm32_ccm.c stm32_uid.c stm32_capture.c
ifeq ($(CONFIG_TIMER),y)
arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
+1 -1
View File
@@ -615,7 +615,7 @@
#endif
#define GPIO_SPI3_MISO_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4)
#define GPIO_SPI3_MISO_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN11)
#define GPIO_SPI3_MISO_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN7)
#define GPIO_SPI3_MOSI_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5)
#define GPIO_SPI3_MOSI_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN12)
#define GPIO_SPI3_NSS_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
arch/arm/src/stm32/stm32_can.c
+71 -31
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_can.c
*
* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
@@ -74,10 +74,6 @@
#define INAK_TIMEOUT 65535
/* Mailboxes ****************************************************************/
#define CAN_ALL_MAILBOXES (CAN_TSR_TME0 | CAN_TSR_TME1 | CAN_TSR_TME2)
/* Bit timing ***************************************************************/
#define CAN_BIT_QUANTA (CONFIG_CAN_TSEG1 + CONFIG_CAN_TSEG2 + 1)
@@ -172,6 +168,12 @@ static int stm32can_bittiming(FAR struct stm32_can_s *priv);
static int stm32can_cellinit(FAR struct stm32_can_s *priv);
static int stm32can_filterinit(FAR struct stm32_can_s *priv);
/* TX mailbox status */
static bool stm32can_txmb0empty(uint32_t tsr_regval);
static bool stm32can_txmb1empty(uint32_t tsr_regval);
static bool stm32can_txmb2empty(uint32_t tsr_regval);
/****************************************************************************
* Private Data
****************************************************************************/
@@ -1170,15 +1172,15 @@ static int stm32can_send(FAR struct can_dev_s *dev,
/* Select one empty transmit mailbox */
regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET);
if ((regval & CAN_TSR_TME0) != 0 && (regval & CAN_TSR_RQCP0) == 0)
if (stm32can_txmb0empty(regval))
{
txmb = 0;
}
else if ((regval & CAN_TSR_TME1) != 0 && (regval & CAN_TSR_RQCP1) == 0)
else if (stm32can_txmb1empty(regval))
{
txmb = 1;
}
else if ((regval & CAN_TSR_TME2) != 0 && (regval & CAN_TSR_RQCP2) == 0)
else if (stm32can_txmb2empty(regval))
{
txmb = 2;
}
@@ -1321,7 +1323,8 @@ static bool stm32can_txready(FAR struct can_dev_s *dev)
regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET);
caninfo("CAN%d TSR: %08x\n", priv->port, regval);
return (regval & CAN_ALL_MAILBOXES) != 0;
return stm32can_txmb0empty(regval) || stm32can_txmb1empty(regval) ||
stm32can_txmb2empty(regval);
}
/****************************************************************************
@@ -1352,7 +1355,8 @@ static bool stm32can_txempty(FAR struct can_dev_s *dev)
regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET);
caninfo("CAN%d TSR: %08x\n", priv->port, regval);
return (regval & CAN_ALL_MAILBOXES) == CAN_ALL_MAILBOXES;
return stm32can_txmb0empty(regval) && stm32can_txmb1empty(regval) &&
stm32can_txmb2empty(regval);
}
/****************************************************************************
@@ -1553,14 +1557,9 @@ static int stm32can_txinterrupt(int irq, FAR void *context, FAR void *arg)
stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP0);
/* Check for errors */
/* Tell the upper half that the transfer is finished. */
if ((regval & CAN_TSR_TXOK0) != 0)
{
/* Tell the upper half that the tansfer is finished. */
(void)can_txdone(dev);
}
(void)can_txdone(dev);
}
/* Check for RQCP1: Request completed mailbox 1 */
@@ -1573,14 +1572,9 @@ static int stm32can_txinterrupt(int irq, FAR void *context, FAR void *arg)
stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP1);
/* Check for errors */
/* Tell the upper half that the transfer is finished. */
if ((regval & CAN_TSR_TXOK1) != 0)
{
/* Tell the upper half that the tansfer is finished. */
(void)can_txdone(dev);
}
(void)can_txdone(dev);
}
/* Check for RQCP2: Request completed mailbox 2 */
@@ -1593,14 +1587,9 @@ static int stm32can_txinterrupt(int irq, FAR void *context, FAR void *arg)
stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP2);
/* Check for errors */
/* Tell the upper half that the transfer is finished. */
if ((regval & CAN_TSR_TXOK2) != 0)
{
/* Tell the upper half that the tansfer is finished. */
(void)can_txdone(dev);
}
(void)can_txdone(dev);
}
return OK;
@@ -2111,6 +2100,57 @@ static int stm32can_delstdfilter(FAR struct stm32_can_s *priv, int arg)
return -ENOTTY;
}
/****************************************************************************
* Name: stm32can_txmb0empty
*
* Input Parameter:
* tsr_regval - value of CAN transmit status register
*
* Returned Value:
* Returns true if mailbox 0 is empty and can be used for sending.
*
****************************************************************************/
static bool stm32can_txmb0empty(uint32_t tsr_regval)
{
return (tsr_regval & CAN_TSR_TME0) != 0 &&
(tsr_regval & CAN_TSR_RQCP0) == 0;
}
/****************************************************************************
* Name: stm32can_txmb1empty
*
* Input Parameter:
* tsr_regval - value of CAN transmit status register
*
* Returned Value:
* Returns true if mailbox 1 is empty and can be used for sending.
*
****************************************************************************/
static bool stm32can_txmb1empty(uint32_t tsr_regval)
{
return (tsr_regval & CAN_TSR_TME1) != 0 &&
(tsr_regval & CAN_TSR_RQCP1) == 0;
}
/****************************************************************************
* Name: stm32can_txmb2empty
*
* Input Parameter:
* tsr_regval - value of CAN transmit status register
*
* Returned Value:
* Returns true if mailbox 2 is empty and can be used for sending.
*
****************************************************************************/
static bool stm32can_txmb2empty(uint32_t tsr_regval)
{
return (tsr_regval & CAN_TSR_TME2) != 0 &&
(tsr_regval & CAN_TSR_RQCP2) == 0;
}
/****************************************************************************
* Public Functions
****************************************************************************/
arch/arm/src/stm32/stm32_eth.c
+50 -2
View File
@@ -54,6 +54,7 @@
#include <nuttx/irq.h>
#include <nuttx/wdog.h>
#include <nuttx/wqueue.h>
#include <nuttx/net/phy.h>
#include <nuttx/net/mii.h>
#include <nuttx/net/arp.h>
#include <nuttx/net/netdev.h>
@@ -189,6 +190,42 @@
# endif
#endif
/* These definitions are used to enable the PHY interrupts */
#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
# if defined( CONFIG_ETH0_PHY_AM79C874)
# error missing logic
# elif defined( CONFIG_ETH0_PHY_KS8721)
# error missing logic
# elif defined( CONFIG_ETH0_PHY_KSZ8041)
# error missing logic
# elif defined( CONFIG_ETH0_PHY_KSZ8051)
# error missing logic
# elif defined( CONFIG_ETH0_PHY_KSZ8061)
# error missing logic
# elif defined( CONFIG_ETH0_PHY_KSZ8081)
# define MII_INT_REG MII_KSZ8081_INT
# define MII_INT_SETEN MII_KSZ80x1_INT_LDEN | MII_KSZ80x1_INT_LUEN
# define MII_INT_CLREN 0
# elif defined( CONFIG_ETH0_PHY_KSZ90x1)
# error missing logic
# elif defined( CONFIG_ETH0_PHY_DP83848C)
# error missing logic
# elif defined( CONFIG_ETH0_PHY_LAN8720)
# error missing logic
# elif defined( CONFIG_ETH0_PHY_LAN8740)
# error missing logic
# elif defined( CONFIG_ETH0_PHY_LAN8740A)
# error missing logic
# elif defined( CONFIG_ETH0_PHY_LAN8742A)
# error missing logic
# elif defined( CONFIG_ETH0_PHY_DM9161)
# error missing logic
# else
# error unknown PHY
# endif
#endif
#ifdef CONFIG_STM32_ETH_PTP
# warning "CONFIG_STM32_ETH_PTP is not yet supported"
#endif
@@ -2889,8 +2926,19 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
static int stm32_phyintenable(struct stm32_ethmac_s *priv)
{
#warning Missing logic
return -ENOSYS;
uint16_t phyval;
int ret;
ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_INT_REG, &phyval);
if (ret == OK)
{
/* Enable link up/down interrupts */
ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_INT_REG,
(phyval & ~MII_INT_CLREN) | MII_INT_SETEN);
}
return ret;
}
#endif
arch/arm/src/stm32/stm32_i2s.c
+2658
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/stm32/stm32_i2s.h
+90
View File
@@ -0,0 +1,90 @@
/************************************************************************************
* arch/arm/src/stm32/stm32_i2s.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_I2S_H
#define __ARCH_ARM_SRC_STM32_I2S_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/audio/i2s.h>
#include "chip.h"
#include "chip/stm32_i2s.h"
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Data
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
* Name: stm32_i2sdev_initialize
*
* Description:
* Initialize the selected I2S port
*
* Input Parameter:
* Port number (for hardware that has mutiple I2S interfaces)
*
* Returned Value:
* Valid I2S device structure reference on succcess; a NULL on failure
*
************************************************************************************/
FAR struct i2s_dev_s *stm32_i2sdev_initialize(int port);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32_I2S_H */
arch/arm/src/stm32/stm32_iwdg.c
-4
View File
@@ -271,10 +271,6 @@ static void stm32_putreg(uint16_t val, uint32_t addr)
* Input Parameters:
* priv - A pointer the internal representation of the "lower-half"
* driver state structure.
* timeout - The new timeout value in milliseconds.
*
* Returned Values:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
arch/arm/src/stm32/stm32_otgfshost.c
+16 -5
View File
@@ -1952,14 +1952,25 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
delay = 1000;
}
/* Wait for the next polling interval.
/* Wait for the next polling interval. For interrupt and
* isochronous endpoints, this is necessaryto assure the
* polling interval. It is used in other cases only to
* prevent the polling from consuming too much CPU bandwith.
*
* REVISIT: This delay could require more resolution than
* is provided by the system timer. In that case, the
* delay could be significantly longer than required.
* Small delays could require more resolution than is provided
* by the system timer. For example, if the system timer
* resolution is 10MS, then usleep(1000) will actually request
* a delay 20MS (due to both quantization and rounding).
*
* REVISIT: So which is better? To ignore tiny delays and
* hog the system bandwidth? Or to wait for an excessive
* amount and destroy system throughput?
*/
usleep(delay);
if (delay > CONFIG_USEC_PER_TICK)
{
usleep(delay - CONFIG_USEC_PER_TICK);
}
}
}
else
arch/arm/src/stm32/stm32_otghshost.c
+16 -5
View File
@@ -1957,14 +1957,25 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
delay = 1000;
}
/* Wait for the next polling interval.
/* Wait for the next polling interval. For interrupt and
* isochronous endpoints, this is necessaryto assure the
* polling interval. It is used in other cases only to
* prevent the polling from consuming too much CPU bandwith.
*
* REVISIT: This delay could require more resolution than
* is provided by the system timer. In that case, the
* delay could be significantly longer than required.
* Small delays could require more resolution than is provided
* by the system timer. For example, if the system timer
* resolution is 10MS, then usleep(1000) will actually request
* a delay 20MS (due to both quantization and rounding).
*
* REVISIT: So which is better? To ignore tiny delays and
* hog the system bandwidth? Or to wait for an excessive
* amount and destroy system throughput?
*/
usleep(delay);
if (delay > CONFIG_USEC_PER_TICK)
{
usleep(delay - CONFIG_USEC_PER_TICK);
}
}
}
else
arch/arm/src/stm32/stm32_serial.c
+25 -4
View File
@@ -1050,10 +1050,10 @@ static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t valu
}
/****************************************************************************
* Name: up_restoreusartint
* Name: up_setusartint
****************************************************************************/
static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie)
static inline void up_setusartint(struct up_dev_s *priv, uint16_t ie)
{
uint32_t cr;
@@ -1074,12 +1074,31 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie)
up_serialout(priv, STM32_USART_CR3_OFFSET, cr);
}
/****************************************************************************
* Name: up_restoreusartint
****************************************************************************/
static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie)
{
irqstate_t flags;
flags = enter_critical_section();
up_setusartint(priv, ie);
leave_critical_section(flags);
}
/****************************************************************************
* Name: up_disableusartint
****************************************************************************/
static inline void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
{
irqstate_t flags;
flags = enter_critical_section();
if (ie)
{
uint32_t cr1;
@@ -1116,7 +1135,9 @@ static inline void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
/* Disable all interrupts */
up_restoreusartint(priv, 0);
up_setusartint(priv, 0);
leave_critical_section(flags);
}
/****************************************************************************
arch/arm/src/stm32/stm32f30xxx_i2c.c
+4 -4
View File
@@ -318,7 +318,7 @@ static int stm32_i2c_reset(FAR struct i2c_master_s *dev);
/* Device Structures, Instantiation */
const struct i2c_ops_s stm32_i2c_ops =
static const struct i2c_ops_s stm32_i2c_ops =
{
.transfer = stm32_i2c_transfer
#ifdef CONFIG_I2C_RESET
@@ -340,7 +340,7 @@ static const struct stm32_i2c_config_s stm32_i2c1_config =
#endif
};
struct stm32_i2c_priv_s stm32_i2c1_priv =
static struct stm32_i2c_priv_s stm32_i2c1_priv =
{
.ops = &stm32_i2c_ops,
.config = &stm32_i2c1_config,
@@ -369,7 +369,7 @@ static const struct stm32_i2c_config_s stm32_i2c2_config =
#endif
};
struct stm32_i2c_priv_s stm32_i2c2_priv =
static struct stm32_i2c_priv_s stm32_i2c2_priv =
{
.ops = &stm32_i2c_ops,
.config = &stm32_i2c2_config,
@@ -398,7 +398,7 @@ static const struct stm32_i2c_config_s stm32_i2c3_config =
#endif
};
struct stm32_i2c_priv_s stm32_i2c3_priv =
static struct stm32_i2c_priv_s stm32_i2c3_priv =
{
.ops = &stm32_i2c_ops,
.config = &stm32_i2c3_config,
arch/arm/src/stm32f0/stm32f0_i2c.c
+4 -4
View File
@@ -307,7 +307,7 @@ static int stm32f0_i2c_reset(FAR struct i2c_master_s *dev);
/* Device Structures, Instantiation */
const struct i2c_ops_s stm32f0_i2c_ops =
static const struct i2c_ops_s stm32f0_i2c_ops =
{
.transfer = stm32f0_i2c_transfer
#ifdef CONFIG_I2C_RESET
@@ -328,7 +328,7 @@ static const struct stm32f0_i2c_config_s stm32f0_i2c1_config =
#endif
};
struct stm32f0_i2c_priv_s stm32f0_i2c1_priv =
static struct stm32f0_i2c_priv_s stm32f0_i2c1_priv =
{
.ops = &stm32f0_i2c_ops,
.config = &stm32f0_i2c1_config,
@@ -356,7 +356,7 @@ static const struct stm32f0_i2c_config_s stm32f0_i2c2_config =
#endif
};
struct stm32f0_i2c_priv_s stm32f0_i2c2_priv =
static struct stm32f0_i2c_priv_s stm32f0_i2c2_priv =
{
.ops = &stm32f0_i2c_ops,
.config = &stm32f0_i2c2_config,
@@ -384,7 +384,7 @@ static const struct stm32f0_i2c_config_s stm32f0_i2c3_config =
#endif
};
struct stm32f0_i2c_priv_s stm32f0_i2c3_priv =
static struct stm32f0_i2c_priv_s stm32f0_i2c3_priv =
{
.ops = &stm32f0_i2c_ops,
.config = &stm32f0_i2c3_config,
arch/arm/src/stm32f0/stm32f0_serial.c
+27 -5
View File
@@ -769,10 +769,10 @@ static inline void stm32f0serial_putreg(FAR struct stm32f0_serial_s *priv,
}
/****************************************************************************
* Name: stm32f0serial_restoreusartint
* Name: stm32f0serial_setusartint
****************************************************************************/
static void stm32f0serial_restoreusartint(FAR struct stm32f0_serial_s *priv,
static void stm32f0serial_setusartint(FAR struct stm32f0_serial_s *priv,
uint16_t ie)
{
uint32_t cr;
@@ -794,13 +794,33 @@ static void stm32f0serial_restoreusartint(FAR struct stm32f0_serial_s *priv,
stm32f0serial_putreg(priv, STM32F0_USART_CR3_OFFSET, cr);
}
/****************************************************************************
* Name: stm32f0serial_restoreusartint
****************************************************************************/
static void stm32f0serial_restoreusartint(FAR struct stm32f0_serial_s *priv,
uint16_t ie)
{
irqstate_t flags;
flags = enter_critical_section();
stm32f0serial_setusartint(priv, ie);
leave_critical_section(flags);
}
/****************************************************************************
* Name: stm32f0serial_disableusartint
****************************************************************************/
static inline void stm32f0serial_disableusartint(FAR struct stm32f0_serial_s *priv,
FAR uint16_t *ie)
static void stm32f0serial_disableusartint(FAR struct stm32f0_serial_s *priv,
FAR uint16_t *ie)
{
irqstate_t flags;
flags = enter_critical_section();
if (ie)
{
uint32_t cr1;
@@ -837,7 +857,9 @@ static inline void stm32f0serial_disableusartint(FAR struct stm32f0_serial_s *pr
/* Disable all interrupts */
stm32f0serial_restoreusartint(priv, 0);
stm32f0serial_setusartint(priv, 0);
leave_critical_section(flags);
}
/****************************************************************************
arch/arm/src/stm32f7/stm32_i2c.c
+126 -126
View File
@@ -290,7 +290,7 @@
#if !defined(CONFIG_STM32F7_I2CTIMEOSEC) && !defined(CONFIG_STM32F7_I2CTIMEOMS)
# define CONFIG_STM32F7_I2CTIMEOSEC 0
# define CONFIG_STM32F7_I2CTIMEOMS 500 /* Default is 500 milliseconds */
# warning "Using Defualt 500 Ms Timeout"
# warning "Using Default 500 Ms Timeout"
#elif !defined(CONFIG_STM32F7_I2CTIMEOSEC)
# define CONFIG_STM32F7_I2CTIMEOSEC 0 /* User provided milliseconds */
#elif !defined(CONFIG_STM32F7_I2CTIMEOMS)
@@ -445,7 +445,7 @@ struct stm32_i2c_priv_s
struct stm32_i2c_inst_s
{
struct i2c_ops_s *ops; /* Standard I2C operations */
const struct i2c_ops_s *ops; /* Standard I2C operations */
struct stm32_i2c_priv_s *priv; /* Common driver private data structure */
};
@@ -495,7 +495,7 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
int count);
#ifdef CONFIG_I2C_RESET
int stm32_i2c_reset(FAR struct i2c_master_s * dev);
static int stm32_i2c_reset(FAR struct i2c_master_s * dev);
#endif
/************************************************************************************
@@ -516,7 +516,7 @@ static const struct stm32_i2c_config_s stm32_i2c1_config =
#endif
};
struct stm32_i2c_priv_s stm32_i2c1_priv =
static struct stm32_i2c_priv_s stm32_i2c1_priv =
{
.config = &stm32_i2c1_config,
.refs = 0,
@@ -545,7 +545,7 @@ static const struct stm32_i2c_config_s stm32_i2c2_config =
#endif
};
struct stm32_i2c_priv_s stm32_i2c2_priv =
static struct stm32_i2c_priv_s stm32_i2c2_priv =
{
.config = &stm32_i2c2_config,
.refs = 0,
@@ -574,7 +574,7 @@ static const struct stm32_i2c_config_s stm32_i2c3_config =
#endif
};
struct stm32_i2c_priv_s stm32_i2c3_priv =
static struct stm32_i2c_priv_s stm32_i2c3_priv =
{
.config = &stm32_i2c3_config,
.refs = 0,
@@ -603,7 +603,7 @@ static const struct stm32_i2c_config_s stm32_i2c4_config =
#endif
};
struct stm32_i2c_priv_s stm32_i2c4_priv =
static struct stm32_i2c_priv_s stm32_i2c4_priv =
{
.config = &stm32_i2c4_config,
.refs = 0,
@@ -620,7 +620,7 @@ struct stm32_i2c_priv_s stm32_i2c4_priv =
/* Device Structures, Instantiation */
struct i2c_ops_s stm32_i2c_ops =
static const struct i2c_ops_s stm32_i2c_ops =
{
.transfer = stm32_i2c_transfer
#ifdef CONFIG_I2C_RESET
@@ -2485,6 +2485,124 @@ static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
return stm32_i2c_process(dev, msgs, count);
}
/************************************************************************************
* Name: stm32_i2c_reset
*
* Description:
* Reset an I2C bus
*
************************************************************************************/
#ifdef CONFIG_I2C_RESET
static int stm32_i2c_reset(FAR struct i2c_master_s * dev)
{
struct stm32_i2c_priv_s * priv;
unsigned int clock_count;
unsigned int stretch_count;
uint32_t scl_gpio;
uint32_t sda_gpio;
int ret = ERROR;
ASSERT(dev);
/* Get I2C private structure */
priv = ((struct stm32_i2c_inst_s *)dev)->priv;
/* Our caller must own a ref */
ASSERT(priv->refs > 0);
/* Lock out other clients */
stm32_i2c_sem_wait(dev);
/* De-init the port */
stm32_i2c_deinit(priv);
/* Use GPIO configuration to un-wedge the bus */
scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin);
sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin);
/* Let SDA go high */
stm32_gpiowrite(sda_gpio, 1);
/* Clock the bus until any slaves currently driving it let it go. */
clock_count = 0;
while (!stm32_gpioread(sda_gpio))
{
/* Give up if we have tried too hard */
if (clock_count++ > 10)
{
goto out;
}
/* Sniff to make sure that clock stretching has finished.
*
* If the bus never relaxes, the reset has failed.
*/
stretch_count = 0;
while (!stm32_gpioread(scl_gpio))
{
/* Give up if we have tried too hard */
if (stretch_count++ > 10)
{
goto out;
}
up_udelay(10);
}
/* Drive SCL low */
stm32_gpiowrite(scl_gpio, 0);
up_udelay(10);
/* Drive SCL high again */
stm32_gpiowrite(scl_gpio, 1);
up_udelay(10);
}
/* Generate a start followed by a stop to reset slave
* state machines.
*/
stm32_gpiowrite(sda_gpio, 0);
up_udelay(10);
stm32_gpiowrite(scl_gpio, 0);
up_udelay(10);
stm32_gpiowrite(scl_gpio, 1);
up_udelay(10);
stm32_gpiowrite(sda_gpio, 1);
up_udelay(10);
/* Revert the GPIO configuration. */
stm32_unconfiggpio(sda_gpio);
stm32_unconfiggpio(scl_gpio);
/* Re-init the port */
stm32_i2c_init(priv);
ret = OK;
out:
/* Release the port for re-use by other clients */
stm32_i2c_sem_post(dev);
return ret;
}
#endif /* CONFIG_I2C_RESET */
/************************************************************************************
* Public Functions
************************************************************************************/
@@ -2608,122 +2726,4 @@ int stm32_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
return OK;
}
/************************************************************************************
* Name: stm32_i2c_reset
*
* Description:
* Reset an I2C bus
*
************************************************************************************/
#ifdef CONFIG_I2C_RESET
int stm32_i2c_reset(FAR struct i2c_master_s * dev)
{
struct stm32_i2c_priv_s * priv;
unsigned int clock_count;
unsigned int stretch_count;
uint32_t scl_gpio;
uint32_t sda_gpio;
int ret = ERROR;
ASSERT(dev);
/* Get I2C private structure */
priv = ((struct stm32_i2c_inst_s *)dev)->priv;
/* Our caller must own a ref */
ASSERT(priv->refs > 0);
/* Lock out other clients */
stm32_i2c_sem_wait(dev);
/* De-init the port */
stm32_i2c_deinit(priv);
/* Use GPIO configuration to un-wedge the bus */
scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin);
sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin);
/* Let SDA go high */
stm32_gpiowrite(sda_gpio, 1);
/* Clock the bus until any slaves currently driving it let it go. */
clock_count = 0;
while (!stm32_gpioread(sda_gpio))
{
/* Give up if we have tried too hard */
if (clock_count++ > 10)
{
goto out;
}
/* Sniff to make sure that clock stretching has finished.
*
* If the bus never relaxes, the reset has failed.
*/
stretch_count = 0;
while (!stm32_gpioread(scl_gpio))
{
/* Give up if we have tried too hard */
if (stretch_count++ > 10)
{
goto out;
}
up_udelay(10);
}
/* Drive SCL low */
stm32_gpiowrite(scl_gpio, 0);
up_udelay(10);
/* Drive SCL high again */
stm32_gpiowrite(scl_gpio, 1);
up_udelay(10);
}
/* Generate a start followed by a stop to reset slave
* state machines.
*/
stm32_gpiowrite(sda_gpio, 0);
up_udelay(10);
stm32_gpiowrite(scl_gpio, 0);
up_udelay(10);
stm32_gpiowrite(scl_gpio, 1);
up_udelay(10);
stm32_gpiowrite(sda_gpio, 1);
up_udelay(10);
/* Revert the GPIO configuration. */
stm32_unconfiggpio(sda_gpio);
stm32_unconfiggpio(scl_gpio);
/* Re-init the port */
stm32_i2c_init(priv);
ret = OK;
out:
/* Release the port for re-use by other clients */
stm32_i2c_sem_post(dev);
return ret;
}
#endif /* CONFIG_I2C_RESET */
#endif /* CONFIG_STM32F7_I2C1 || CONFIG_STM32F7_I2C2 || CONFIG_STM32F7_I2C3 */
arch/arm/src/stm32f7/stm32_otghost.c
+16 -5
View File
@@ -1951,14 +1951,25 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
delay = 1000;
}
/* Wait for the next polling interval.
/* Wait for the next polling interval. For interrupt and
* isochronous endpoints, this is necessaryto assure the
* polling interval. It is used in other cases only to
* prevent the polling from consuming too much CPU bandwith.
*
* REVISIT: This delay could require more resolution than
* is provided by the system timer. In that case, the
* delay could be significantly longer than required.
* Small delays could require more resolution than is provided
* by the system timer. For example, if the system timer
* resolution is 10MS, then usleep(1000) will actually request
* a delay 20MS (due to both quantization and rounding).
*
* REVISIT: So which is better? To ignore tiny delays and
* hog the system bandwidth? Or to wait for an excessive
* amount and destroy system throughput?
*/
usleep(delay);
if (delay > CONFIG_USEC_PER_TICK)
{
usleep(delay - CONFIG_USEC_PER_TICK);
}
}
}
else
arch/arm/src/stm32f7/stm32_serial.c
+26 -4
View File
@@ -1096,10 +1096,10 @@ static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t valu
}
/****************************************************************************
* Name: up_restoreusartint
* Name: up_setusartint
****************************************************************************/
static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie)
static inline void up_setusartint(struct up_dev_s *priv, uint16_t ie)
{
uint32_t cr;
@@ -1120,12 +1120,31 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie)
up_serialout(priv, STM32_USART_CR3_OFFSET, cr);
}
/****************************************************************************
* Name: up_restoreusartint
****************************************************************************/
static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie)
{
irqstate_t flags;
flags = enter_critical_section();
up_setusartint(priv, ie);
leave_critical_section(flags);
}
/****************************************************************************
* Name: up_disableusartint
****************************************************************************/
static inline void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
{
irqstate_t flags;
flags = enter_critical_section();
if (ie)
{
uint32_t cr1;
@@ -1162,7 +1181,9 @@ static inline void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
/* Disable all interrupts */
up_restoreusartint(priv, 0);
up_setusartint(priv, 0);
leave_critical_section(flags);
}
/****************************************************************************
@@ -2868,6 +2889,7 @@ int up_putc(int ch)
up_lowputc(ch);
up_restoreusartint(priv, ie);
#endif
return ch;
}
arch/arm/src/stm32l4/Kconfig
+2 -12
View File
@@ -1008,14 +1008,6 @@ config STM32L4_SPI3
select SPI
select STM32L4_SPI
config STM32L4_USART1
bool "USART1"
default n
depends on STM32L4_HAVE_USART1
select ARCH_HAVE_SERIAL_TERMIOS
select USART1_SERIALDRIVER
select STM32L4_USART
config STM32L4_USART2
bool "USART2"
default n
@@ -1155,8 +1147,9 @@ config STM32L4_TIM8
config STM32L4_USART1
bool "USART1"
default n
select USART1_SERIALDRIVER
depends on STM32L4_HAVE_USART1
select ARCH_HAVE_SERIAL_TERMIOS
select USART1_SERIALDRIVER
select STM32L4_USART
config STM32L4_TIM15
@@ -1306,9 +1299,6 @@ config STM32L4_SAI2PLL
Set this true and provide configuration parameters in
board.h to use this PLL.
config STM32L4_USART
bool
menu "Timer Configuration"
if SCHED_TICKLESS
arch/arm/src/stm32l4/Make.defs
+5 -2
View File
@@ -102,8 +102,8 @@ CHIP_ASRCS =
CHIP_CSRCS = stm32l4_allocateheap.c stm32l4_exti_gpio.c stm32l4_gpio.c
CHIP_CSRCS += stm32l4_idle.c stm32l4_irq.c stm32l4_lowputc.c stm32l4_rcc.c
CHIP_CSRCS += stm32l4_serial.c stm32l4_start.c stm32l4_waste.c stm32l4_uid.c
CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c stm32l4_pwr.c
CHIP_CSRCS += stm32l4_tim.c stm32l4_flash.c
CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c stm32l4_lsi.c
CHIP_CSRCS += stm32l4_pwr.c stm32l4_tim.c stm32l4_flash.c
ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += stm32l4_tim_lowerhalf.c
@@ -216,3 +216,6 @@ ifeq ($(CONFIG_STM32L4_FIREWALL),y)
CHIP_CSRCS += stm32l4_firewall.c
endif
ifeq ($(CONFIG_STM32L4_IWDG),y)
CHIP_CSRCS += stm32l4_iwdg.c
endif
arch/arm/src/stm32l4/README.txt
+4 -4
View File
@@ -8,7 +8,7 @@ Most code is copied and adapted from the STM32 Port.
TODO list
---------
Peripherals with equivalent implementation in STM32 port
Peripherals with implementation in STM32 port:
IRQs : OK
GPIO : OK
@@ -42,10 +42,11 @@ AES : TODO
RNG : works
CRC : TODO (configurable polynomial)
WWDG : TODO
IWDG : TODO
IWDG : works
MMCSD : TODO
ADC : TODO
DAC : TODO
DMA2D : TODO (Chrom-Art Accelerator for image manipulation)
New peripherals with implementation to be written from scratch
These are Low Priority TODO items, unless someone requests or contributes
@@ -61,7 +62,6 @@ COMP : There is some code (Analog comparators)
DFSDM : TODO (Digital Filter and Sigma-Delta Modulator)
LCD : TODO (Segment LCD controller)
SAIPLL : works (PLL For Digital Audio interfaces, and other things)
SAI : TODO (Digital Audio interfaces, I2S, SPDIF, etc)
SAI : There is some code (Digital Audio interfaces, I2S, SPDIF, etc)
HASH : TODO (SHA-1, SHA-224, SHA-256, HMAC)
DCMI : TODO (Digital Camera interfaces)
DMA2D : TODO (Chrom-Art Accelerator for image manipulation)
arch/arm/src/stm32l4/chip/stm32l4_wdg.h
+154
View File
@@ -0,0 +1,154 @@
/************************************************************************************
* arch/arm/src/stm32l4/chip/stm32l4_wdg.h
*
* Copyright (C) 2009, 2011-2013, 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* Juha Niskanen <juha.niskanen@haltian.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_WDG_H
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_WDG_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32L4_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */
#define STM32L4_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */
#define STM32L4_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */
#define STM32L4_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */
#define STM32L4_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */
#define STM32L4_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */
#define STM32L4_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */
#define STM32L4_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */
/* Register Addresses ***************************************************************/
#define STM32L4_IWDG_KR (STM32L4_IWDG_BASE+STM32L4_IWDG_KR_OFFSET)
#define STM32L4_IWDG_PR (STM32L4_IWDG_BASE+STM32L4_IWDG_PR_OFFSET)
#define STM32L4_IWDG_RLR (STM32L4_IWDG_BASE+STM32L4_IWDG_RLR_OFFSET)
#define STM32L4_IWDG_SR (STM32L4_IWDG_BASE+STM32L4_IWDG_SR_OFFSET)
#define STM32L4_IWDG_WINR (STM32L4_IWDG_BASE+STM32L4_IWDG_WINR_OFFSET)
#define STM32L4_WWDG_CR (STM32L4_WWDG_BASE+STM32L4_WWDG_CR_OFFSET)
#define STM32L4_WWDG_CFR (STM32L4_WWDG_BASE+STM32L4_WWDG_CFR_OFFSET)
#define STM32L4_WWDG_SR (STM32L4_WWDG_BASE+STM32L4_WWDG_SR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* Key register (32-bit) */
#define IWDG_KR_KEY_SHIFT (0) /* Bits 15:0: Key value (write only, read 0000h) */
#define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT)
#define IWDG_KR_KEY_ENABLE (0x5555) /* Enable register access */
#define IWDG_KR_KEY_DISABLE (0x0000) /* Disable register access */
#define IWDG_KR_KEY_RELOAD (0xaaaa) /* Reload the counter */
#define IWDG_KR_KEY_START (0xcccc) /* Start the watchdog */
/* Prescaler register (32-bit) */
#define IWDG_PR_SHIFT (0) /* Bits 2:0: Prescaler divider */
#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT)
# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */
# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */
# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */
# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */
# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */
# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */
# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */
/* Reload register (32-bit) */
#define IWDG_RLR_RL_SHIFT (0) /* Bits 11:0 RL[11:0]: Watchdog counter reload value */
#define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT)
#define IWDG_RLR_MAX (0xfff)
/* Status register (32-bit) */
#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */
#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */
#define IWDG_SR_WVU (1 << 2) /* Bit 2: Watchdog counter window value update */
/* Window register (32-bit) */
#define IWDG_WINR_SHIFT (0) /* Bits 11:0 WIN[11:0]: Watchdog counter window value */
#define IWDG_WINR_MASK (0x0fff << IWDG_WINR_SHIFT)
/* Control Register (32-bit) */
#define WWDG_CR_T_SHIFT (0) /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */
#define WWDG_CR_T_MASK (0x7f << WWDG_CR_T_SHIFT)
# define WWDG_CR_T_MAX (0x3f << WWDG_CR_T_SHIFT)
# define WWDG_CR_T_RESET (0x40 << WWDG_CR_T_SHIFT)
#define WWDG_CR_WDGA (1 << 7) /* Bit 7: Activation bit */
/* Configuration register (32-bit) */
#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */
#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT)
#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */
#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT)
# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */
# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */
# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */
# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */
#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */
/* Status register (32-bit) */
#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_WDG_H */
arch/arm/src/stm32l4/stm32l4_i2c.c
+6 -6
View File
@@ -307,7 +307,7 @@ static int stm32l4_i2c_reset(FAR struct i2c_master_s *dev);
/* Device Structures, Instantiation */
const struct i2c_ops_s stm32l4_i2c_ops =
static const struct i2c_ops_s stm32l4_i2c_ops =
{
.transfer = stm32l4_i2c_transfer
#ifdef CONFIG_I2C_RESET
@@ -329,7 +329,7 @@ static const struct stm32l4_i2c_config_s stm32l4_i2c1_config =
#endif
};
struct stm32l4_i2c_priv_s stm32l4_i2c1_priv =
static struct stm32l4_i2c_priv_s stm32l4_i2c1_priv =
{
.ops = &stm32l4_i2c_ops,
.config = &stm32l4_i2c1_config,
@@ -358,7 +358,7 @@ static const struct stm32l4_i2c_config_s stm32l4_i2c2_config =
#endif
};
struct stm32l4_i2c_priv_s stm32l4_i2c2_priv =
static struct stm32l4_i2c_priv_s stm32l4_i2c2_priv =
{
.ops = &stm32l4_i2c_ops,
.config = &stm32l4_i2c2_config,
@@ -387,7 +387,7 @@ static const struct stm32l4_i2c_config_s stm32l4_i2c3_config =
#endif
};
struct stm32l4_i2c_priv_s stm32l4_i2c3_priv =
static struct stm32l4_i2c_priv_s stm32l4_i2c3_priv =
{
.ops = &stm32l4_i2c_ops,
.config = &stm32l4_i2c3_config,
@@ -416,7 +416,7 @@ static const struct stm32l4_i2c_config_s stm32l4_i2c4_config =
#endif
};
struct stm32l4_i2c_priv_s stm32l4_i2c4_priv =
static struct stm32l4_i2c_priv_s stm32l4_i2c4_priv =
{
.ops = &stm32l4_i2c_ops,
.config = &stm32l4_i2c4_config,
@@ -1831,7 +1831,7 @@ static int stm32l4_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg
* dev - Device-specific state data
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
* Zero (OK) on success; negative value on failure.
*
************************************************************************************/
arch/arm/src/stm32l4/stm32l4_iwdg.c
+658
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/stm32l4/stm32l4_lsi.c
+87
View File
@@ -0,0 +1,87 @@
/****************************************************************************
* arch/arm/src/stm32l4/stm32l4_lsi.c
*
* Copyright (C) 2012, 2015-2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* Juha Niskanen <juha.niskanen@haltian.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "up_arch.h"
#include "stm32l4_rcc.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32l4_rcc_enablelsi
*
* Description:
* Enable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void stm32l4_rcc_enablelsi(void)
{
/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
* bit the RCC CSR register.
*/
modifyreg32(STM32L4_RCC_CSR, 0, RCC_CSR_LSION);
/* Wait for the internal LSI oscillator to be stable. */
while ((getreg32(STM32L4_RCC_CSR) & RCC_CSR_LSIRDY) == 0);
}
/****************************************************************************
* Name: stm32l4_rcc_disablelsi
*
* Description:
* Disable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void stm32l4_rcc_disablelsi(void)
{
/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
* bit the RCC CSR register.
*/
modifyreg32(STM32L4_RCC_CSR, RCC_CSR_LSION, 0);
/* LSIRDY should go low after 3 LSI clock cycles */
}
arch/arm/src/stm32l4/stm32l4_otgfshost.c
+16 -5
View File
@@ -1956,14 +1956,25 @@ static ssize_t stm32l4_in_transfer(FAR struct stm32l4_usbhost_s *priv,
delay = 1000;
}
/* Wait for the next polling interval.
/* Wait for the next polling interval. For interrupt and
* isochronous endpoints, this is necessaryto assure the
* polling interval. It is used in other cases only to
* prevent the polling from consuming too much CPU bandwith.
*
* REVISIT: This delay could require more resolution than
* is provided by the system timer. In that case, the
* delay could be significantly longer than required.
* Small delays could require more resolution than is provided
* by the system timer. For example, if the system timer
* resolution is 10MS, then usleep(1000) will actually request
* a delay 20MS (due to both quantization and rounding).
*
* REVISIT: So which is better? To ignore tiny delays and
* hog the system bandwidth? Or to wait for an excessive
* amount and destroy system throughput?
*/
usleep(delay);
if (delay > CONFIG_USEC_PER_TICK)
{
usleep(delay - CONFIG_USEC_PER_TICK);
}
}
}
else
arch/arm/src/stm32l4/stm32l4_serial.c
+28 -6
View File
@@ -765,11 +765,11 @@ static inline void stm32l4serial_putreg(FAR struct stm32l4_serial_s *priv,
}
/****************************************************************************
* Name: stm32l4serial_restoreusartint
* Name: stm32l4serial_setusartint
****************************************************************************/
static void stm32l4serial_restoreusartint(FAR struct stm32l4_serial_s *priv,
uint16_t ie)
static inline void stm32l4serial_setusartint(FAR struct stm32l4_serial_s *priv,
uint16_t ie)
{
uint32_t cr;
@@ -790,13 +790,33 @@ static void stm32l4serial_restoreusartint(FAR struct stm32l4_serial_s *priv,
stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, cr);
}
/****************************************************************************
* Name: up_restoreusartint
****************************************************************************/
static void stm32l4serial_restoreusartint(FAR struct stm32l4_serial_s *priv,
uint16_t ie)
{
irqstate_t flags;
flags = enter_critical_section();
stm32l4serial_setusartint(priv, ie);
leave_critical_section(flags);
}
/****************************************************************************
* Name: stm32l4serial_disableusartint
****************************************************************************/
static inline void stm32l4serial_disableusartint(FAR struct stm32l4_serial_s *priv,
FAR uint16_t *ie)
static void stm32l4serial_disableusartint(FAR struct stm32l4_serial_s *priv,
FAR uint16_t *ie)
{
irqstate_t flags;
flags = enter_critical_section();
if (ie)
{
uint32_t cr1;
@@ -833,7 +853,9 @@ static inline void stm32l4serial_disableusartint(FAR struct stm32l4_serial_s *pr
/* Disable all interrupts */
stm32l4serial_restoreusartint(priv, 0);
stm32l4serial_setusartint(priv, 0);
leave_critical_section(flags);
}
/****************************************************************************
arch/arm/src/stm32l4/stm32l4_wdg.h
+119
View File
@@ -0,0 +1,119 @@
/****************************************************************************
* arch/arm/src/stm32l4/stm32l4_wdg.h
*
* Copyright (C) 2012, 2015, 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_WDG_H
#define __ARCH_ARM_SRC_STM32L4_STM32L4_WDG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/stm32l4_wdg.h"
#ifdef CONFIG_WATCHDOG
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32l4_iwdginitialize
*
* Description:
* Initialize the IWDG watchdog time. The watchdog timer is initialized
* and registers as 'devpath. The initial state of the watchdog time is
* disabled.
*
* Input Parameters:
* devpath - The full path to the watchdog. This should be of the form
* /dev/watchdog0
* lsifreq - The calibrated LSI clock frequency
*
* Returned Values:
* None
*
****************************************************************************/
#ifdef CONFIG_STM32L4_IWDG
void stm32l4_iwdginitialize(FAR const char *devpath, uint32_t lsifreq);
#endif
/****************************************************************************
* Name: stm32l4_wwdginitialize
*
* Description:
* Initialize the WWDG watchdog time. The watchdog timer is initialized and
* registers as 'devpath. The initial state of the watchdog time is
* disabled.
*
* Input Parameters:
* devpath - The full path to the watchdog. This should be of the form
* /dev/watchdog0
*
* Returned Values:
* None
*
****************************************************************************/
#ifdef CONFIG_STM32L4_WWDG
void stm32l4_wwdginitialize(FAR const char *devpath);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_WATCHDOG */
#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_WDG_H */
arch/arm/src/tiva/tiva_i2c.c
+2 -2
View File
@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/tiva/tiva_i2c.c
*
* Copyright (C) 2014-2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2014-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* The basic structure of this driver derives in spirit (if nothing more) from the
@@ -1378,7 +1378,7 @@ static int tiva_i2c_process(struct tiva_i2c_priv_s *priv, uint32_t status)
*
************************************************************************************/
#if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C0)
#ifndef CONFIG_I2C_POLLED
static int tiva_i2c_interrupt(int irq, void *context, void *arg)
{
struct tiva_i2c_priv_s *priv = (struct tiva_i2c_priv_s *)arg;
binfmt/libelf/libelf_dtors.c
+3 -3
View File
@@ -163,14 +163,14 @@ int elf_loaddtors(FAR struct elf_loadinfo_s *loadinfo)
{
/* Allocate memory to hold a copy of the .dtor section */
loadinfo->ctoralloc = (binfmt_dtor_t *)kumm_malloc(dtorsize);
if (!loadinfo->ctoralloc)
loadinfo->dtoralloc = (binfmt_dtor_t *)kumm_malloc(dtorsize);
if (!loadinfo->dtoralloc)
{
berr("Failed to allocate memory for .dtors\n");
return -ENOMEM;
}
loadinfo->dtors = (binfmt_dtor_t *)loadinfo->ctoralloc;
loadinfo->dtors = (binfmt_dtor_t *)loadinfo->dtoralloc;
/* Read the section header table into memory */
configs/arduino-due/nsh/defconfig
+1 -2
View File
@@ -124,8 +124,7 @@ CONFIG_ARCH_CORTEXM3=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARCH_CHIP="sam34"
# CONFIG_ARM_TOOLCHAIN_IAR is not set
CONFIG_ARM_TOOLCHAIN_GNU=y
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
# CONFIG_ARMV7M_USEBASEPRI is not set
CONFIG_ARCH_HAVE_CMNVECTOR=y
# CONFIG_ARMV7M_CMNVECTOR is not set
configs/bambino-200e/netnsh/defconfig
+2 -2
View File
@@ -123,8 +123,8 @@ CONFIG_ARCH_CORTEXM4=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARCH_CHIP="lpc43xx"
# CONFIG_ARM_TOOLCHAIN_IAR is not set
CONFIG_ARM_TOOLCHAIN_GNU=y
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
CONFIG_ARCH_TOOLCHAIN_GNU=y
# CONFIG_ARMV7M_USEBASEPRI is not set
CONFIG_ARCH_HAVE_CMNVECTOR=y
CONFIG_ARMV7M_CMNVECTOR=y
configs/bambino-200e/nsh/defconfig
+2 -2
View File
@@ -121,8 +121,8 @@ CONFIG_ARCH_CORTEXM4=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARCH_CHIP="lpc43xx"
# CONFIG_ARM_TOOLCHAIN_IAR is not set
CONFIG_ARM_TOOLCHAIN_GNU=y
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
CONFIG_ARCH_TOOLCHAIN_GNU=y
# CONFIG_ARMV7M_USEBASEPRI is not set
CONFIG_ARCH_HAVE_CMNVECTOR=y
CONFIG_ARMV7M_CMNVECTOR=y
configs/bambino-200e/usbnsh/defconfig
+2 -2
View File
@@ -121,8 +121,8 @@ CONFIG_ARCH_CORTEXM4=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARCH_CHIP="lpc43xx"
# CONFIG_ARM_TOOLCHAIN_IAR is not set
CONFIG_ARM_TOOLCHAIN_GNU=y
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
CONFIG_ARCH_TOOLCHAIN_GNU=y
# CONFIG_ARMV7M_USEBASEPRI is not set
CONFIG_ARCH_HAVE_CMNVECTOR=y
CONFIG_ARMV7M_CMNVECTOR=y
configs/c5471evm/httpd/defconfig
+1 -2
View File
@@ -123,8 +123,7 @@ CONFIG_ARCH_ARM7TDMI=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="arm"
CONFIG_ARCH_CHIP="c5471"
# CONFIG_ARM_TOOLCHAIN_IAR is not set
# CONFIG_ARM_TOOLCHAIN_GNU is not set
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
# CONFIG_ARCH_HAVE_FPU is not set
# CONFIG_ARCH_HAVE_DPFPU is not set
# CONFIG_ARCH_HAVE_TRUSTZONE is not set
configs/c5471evm/nettest/defconfig
+1 -2
View File
@@ -123,8 +123,7 @@ CONFIG_ARCH_ARM7TDMI=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="arm"
CONFIG_ARCH_CHIP="c5471"
# CONFIG_ARM_TOOLCHAIN_IAR is not set
# CONFIG_ARM_TOOLCHAIN_GNU is not set
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
# CONFIG_ARCH_HAVE_FPU is not set
# CONFIG_ARCH_HAVE_DPFPU is not set
# CONFIG_ARCH_HAVE_TRUSTZONE is not set
configs/c5471evm/nsh/defconfig
+1 -2
View File
@@ -123,8 +123,7 @@ CONFIG_ARCH_ARM7TDMI=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="arm"
CONFIG_ARCH_CHIP="c5471"
# CONFIG_ARM_TOOLCHAIN_IAR is not set
# CONFIG_ARM_TOOLCHAIN_GNU is not set
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
# CONFIG_ARCH_HAVE_FPU is not set
# CONFIG_ARCH_HAVE_DPFPU is not set
# CONFIG_ARCH_HAVE_TRUSTZONE is not set
configs/cc3200-launchpad/nsh/defconfig
+2 -2
View File
@@ -121,8 +121,8 @@ CONFIG_ARCH_CORTEXM4=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARCH_CHIP="tiva"
# CONFIG_ARM_TOOLCHAIN_IAR is not set
CONFIG_ARM_TOOLCHAIN_GNU=y
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
CONFIG_ARCH_TOOLCHAIN_GNU=y
CONFIG_ARMV7M_USEBASEPRI=y
CONFIG_ARCH_HAVE_CMNVECTOR=y
# CONFIG_ARMV7M_CMNVECTOR is not set
configs/clicker2-stm32/knsh/defconfig
+1 -2
View File
@@ -130,8 +130,7 @@ CONFIG_ARCH_CORTEXM4=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARCH_CHIP="stm32"
# CONFIG_ARM_TOOLCHAIN_IAR is not set
CONFIG_ARM_TOOLCHAIN_GNU=y
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
# CONFIG_ARMV7M_USEBASEPRI is not set
CONFIG_ARCH_HAVE_CMNVECTOR=y
# CONFIG_ARMV7M_CMNVECTOR is not set
configs/clicker2-stm32/mrf24j40-radio/defconfig
+5 -7
View File
@@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y
#
# Build Configuration
#
# CONFIG_APPS_DIR="../apps"
CONFIG_APPS_DIR="../apps"
CONFIG_BUILD_FLAT=y
# CONFIG_BUILD_2PASS is not set
@@ -125,8 +125,7 @@ CONFIG_ARCH_CORTEXM4=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARCH_CHIP="stm32"
# CONFIG_ARM_TOOLCHAIN_IAR is not set
CONFIG_ARM_TOOLCHAIN_GNU=y
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
# CONFIG_ARMV7M_USEBASEPRI is not set
CONFIG_ARCH_HAVE_CMNVECTOR=y
# CONFIG_ARMV7M_CMNVECTOR is not set
@@ -980,8 +979,7 @@ CONFIG_IOB_NCHAINS=0
#
CONFIG_WIRELESS=y
CONFIG_WIRELESS_IEEE802154=y
CONFIG_IEEE802154_MAC=y
# CONFIG_IEEE802154_MAC_DEV is not set
CONFIG_IEEE802154_MAC_DEV=y
CONFIG_MAC802154_HPWORK=y
CONFIG_IEEE802154_NTXDESC=3
CONFIG_IEEE802154_IND_PREALLOC=20
@@ -1164,10 +1162,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
# CONFIG_EXAMPLES_NXFFS is not set
# CONFIG_EXAMPLES_NXHELLO is not set
# CONFIG_EXAMPLES_NXIMAGE is not set
# CONFIG_EXAMPLES_NX is not set
# CONFIG_EXAMPLES_NXLINES is not set
# CONFIG_EXAMPLES_NXTERM is not set
# CONFIG_EXAMPLES_NXTEXT is not set
@@ -1372,7 +1370,7 @@ CONFIG_READLINE_ECHO=y
#
# IEEE 802.15.4 applications
#
# CONFIG_IEEE802154_LIBMAC is not set
CONFIG_IEEE802154_LIBMAC=y
CONFIG_IEEE802154_LIBUTILS=y
CONFIG_IEEE802154_I8SAK=y
CONFIG_IEEE802154_I8SAK_PRIORITY=100
configs/clicker2-stm32/nsh/defconfig
+1 -2
View File
@@ -125,8 +125,7 @@ CONFIG_ARCH_CORTEXM4=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARCH_CHIP="stm32"
# CONFIG_ARM_TOOLCHAIN_IAR is not set
CONFIG_ARM_TOOLCHAIN_GNU=y
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
# CONFIG_ARMV7M_USEBASEPRI is not set
CONFIG_ARCH_HAVE_CMNVECTOR=y
# CONFIG_ARMV7M_CMNVECTOR is not set
configs/clicker2-stm32/src/stm32_mrf24j40.c
+1 -6
View File
@@ -1,5 +1,5 @@
/****************************************************************************
* configs/freedom-kl25z/src/stm32_mrf24j40.c
* configs/clicker2-stm32/src/stm32_mrf24j40.c
*
* Copyright (C) 2017 Gregory Nutt, All rights reserver
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -220,9 +220,7 @@ static void stm32_enable_irq(FAR const struct mrf24j40_lower_s *lower,
static int stm32_mrf24j40_devsetup(FAR struct stm32_priv_s *priv)
{
FAR struct ieee802154_radio_s *radio;
#ifdef CONFIG_IEEE802154_MAC
MACHANDLE mac;
#endif
FAR struct spi_dev_s *spi;
int ret;
@@ -248,7 +246,6 @@ static int stm32_mrf24j40_devsetup(FAR struct stm32_priv_s *priv)
return -ENODEV;
}
#if defined(CONFIG_IEEE802154_MAC)
/* Create a 802.15.4 MAC device from a 802.15.4 compatible radio device. */
mac = mac802154_create(radio);
@@ -285,8 +282,6 @@ static int stm32_mrf24j40_devsetup(FAR struct stm32_priv_s *priv)
}
#endif
#endif /* CONFIG_IEEE802154_MAC */
return OK;
}

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