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STM32L4: Add IWDG peripheral. This is the same as for STM32 except that prescale and reload can be
changed after watchdog has been started, as this seems to work on L4.
This commit is contained in:
Juha Niskanen
committed by
Gregory Nutt
Gregory Nutt
parent
4d5c1c7dba
commit
0c9abbfe67
@@ -271,10 +271,6 @@ static void stm32_putreg(uint16_t val, uint32_t addr)
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* Input Parameters:
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* priv - A pointer the internal representation of the "lower-half"
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* driver state structure.
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* timeout - The new timeout value in milliseconds.
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*
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* Returned Values:
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* Zero on success; a negated errno value on failure.
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*
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****************************************************************************/
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@@ -102,8 +102,8 @@ CHIP_ASRCS =
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CHIP_CSRCS = stm32l4_allocateheap.c stm32l4_exti_gpio.c stm32l4_gpio.c
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CHIP_CSRCS += stm32l4_idle.c stm32l4_irq.c stm32l4_lowputc.c stm32l4_rcc.c
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CHIP_CSRCS += stm32l4_serial.c stm32l4_start.c stm32l4_waste.c stm32l4_uid.c
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CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c stm32l4_pwr.c
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CHIP_CSRCS += stm32l4_tim.c stm32l4_flash.c
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CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c stm32l4_lsi.c
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CHIP_CSRCS += stm32l4_pwr.c stm32l4_tim.c stm32l4_flash.c
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ifeq ($(CONFIG_TIMER),y)
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CHIP_CSRCS += stm32l4_tim_lowerhalf.c
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@@ -216,3 +216,6 @@ ifeq ($(CONFIG_STM32L4_FIREWALL),y)
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CHIP_CSRCS += stm32l4_firewall.c
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endif
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ifeq ($(CONFIG_STM32L4_IWDG),y)
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CHIP_CSRCS += stm32l4_iwdg.c
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endif
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@@ -8,7 +8,7 @@ Most code is copied and adapted from the STM32 Port.
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TODO list
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---------
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Peripherals with equivalent implementation in STM32 port
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Peripherals with implementation in STM32 port:
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IRQs : OK
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GPIO : OK
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@@ -42,10 +42,11 @@ AES : TODO
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RNG : works
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CRC : TODO (configurable polynomial)
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WWDG : TODO
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IWDG : TODO
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IWDG : works
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MMCSD : TODO
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ADC : TODO
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DAC : TODO
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DMA2D : TODO (Chrom-Art Accelerator for image manipulation)
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New peripherals with implementation to be written from scratch
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These are Low Priority TODO items, unless someone requests or contributes
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@@ -61,7 +62,6 @@ COMP : There is some code (Analog comparators)
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DFSDM : TODO (Digital Filter and Sigma-Delta Modulator)
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LCD : TODO (Segment LCD controller)
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SAIPLL : works (PLL For Digital Audio interfaces, and other things)
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SAI : TODO (Digital Audio interfaces, I2S, SPDIF, etc)
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SAI : There is some code (Digital Audio interfaces, I2S, SPDIF, etc)
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HASH : TODO (SHA-1, SHA-224, SHA-256, HMAC)
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DCMI : TODO (Digital Camera interfaces)
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DMA2D : TODO (Chrom-Art Accelerator for image manipulation)
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@@ -0,0 +1,154 @@
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/************************************************************************************
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* arch/arm/src/stm32l4/chip/stm32l4_wdg.h
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*
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* Copyright (C) 2009, 2011-2013, 2017 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* Juha Niskanen <juha.niskanen@haltian.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_WDG_H
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#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_WDG_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32L4_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */
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#define STM32L4_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */
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#define STM32L4_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */
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#define STM32L4_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */
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#define STM32L4_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */
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#define STM32L4_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */
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#define STM32L4_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */
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#define STM32L4_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */
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/* Register Addresses ***************************************************************/
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#define STM32L4_IWDG_KR (STM32L4_IWDG_BASE+STM32L4_IWDG_KR_OFFSET)
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#define STM32L4_IWDG_PR (STM32L4_IWDG_BASE+STM32L4_IWDG_PR_OFFSET)
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#define STM32L4_IWDG_RLR (STM32L4_IWDG_BASE+STM32L4_IWDG_RLR_OFFSET)
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#define STM32L4_IWDG_SR (STM32L4_IWDG_BASE+STM32L4_IWDG_SR_OFFSET)
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#define STM32L4_IWDG_WINR (STM32L4_IWDG_BASE+STM32L4_IWDG_WINR_OFFSET)
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#define STM32L4_WWDG_CR (STM32L4_WWDG_BASE+STM32L4_WWDG_CR_OFFSET)
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#define STM32L4_WWDG_CFR (STM32L4_WWDG_BASE+STM32L4_WWDG_CFR_OFFSET)
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#define STM32L4_WWDG_SR (STM32L4_WWDG_BASE+STM32L4_WWDG_SR_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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/* Key register (32-bit) */
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#define IWDG_KR_KEY_SHIFT (0) /* Bits 15:0: Key value (write only, read 0000h) */
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#define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT)
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#define IWDG_KR_KEY_ENABLE (0x5555) /* Enable register access */
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#define IWDG_KR_KEY_DISABLE (0x0000) /* Disable register access */
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#define IWDG_KR_KEY_RELOAD (0xaaaa) /* Reload the counter */
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#define IWDG_KR_KEY_START (0xcccc) /* Start the watchdog */
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/* Prescaler register (32-bit) */
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#define IWDG_PR_SHIFT (0) /* Bits 2:0: Prescaler divider */
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#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT)
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# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */
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# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */
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# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */
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# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */
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# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */
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# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */
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# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */
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/* Reload register (32-bit) */
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#define IWDG_RLR_RL_SHIFT (0) /* Bits 11:0 RL[11:0]: Watchdog counter reload value */
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#define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT)
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#define IWDG_RLR_MAX (0xfff)
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/* Status register (32-bit) */
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#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */
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#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */
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#define IWDG_SR_WVU (1 << 2) /* Bit 2: Watchdog counter window value update */
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/* Window register (32-bit) */
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#define IWDG_WINR_SHIFT (0) /* Bits 11:0 WIN[11:0]: Watchdog counter window value */
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#define IWDG_WINR_MASK (0x0fff << IWDG_WINR_SHIFT)
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/* Control Register (32-bit) */
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#define WWDG_CR_T_SHIFT (0) /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */
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#define WWDG_CR_T_MASK (0x7f << WWDG_CR_T_SHIFT)
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# define WWDG_CR_T_MAX (0x3f << WWDG_CR_T_SHIFT)
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# define WWDG_CR_T_RESET (0x40 << WWDG_CR_T_SHIFT)
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#define WWDG_CR_WDGA (1 << 7) /* Bit 7: Activation bit */
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/* Configuration register (32-bit) */
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#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */
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#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT)
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#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */
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#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT)
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# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */
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# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */
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# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */
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# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */
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#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */
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/* Status register (32-bit) */
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#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_WDG_H */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,87 @@
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/****************************************************************************
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* arch/arm/src/stm32l4/stm32l4_lsi.c
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*
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* Copyright (C) 2012, 2015-2017 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* Juha Niskanen <juha.niskanen@haltian.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
|
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*
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
|
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
|
||||
*
|
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "up_arch.h"
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#include "stm32l4_rcc.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32l4_rcc_enablelsi
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*
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* Description:
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* Enable the Internal Low-Speed (LSI) RC Oscillator.
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*
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****************************************************************************/
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void stm32l4_rcc_enablelsi(void)
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{
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/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
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* bit the RCC CSR register.
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*/
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modifyreg32(STM32L4_RCC_CSR, 0, RCC_CSR_LSION);
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/* Wait for the internal LSI oscillator to be stable. */
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while ((getreg32(STM32L4_RCC_CSR) & RCC_CSR_LSIRDY) == 0);
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}
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/****************************************************************************
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* Name: stm32l4_rcc_disablelsi
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*
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* Description:
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* Disable the Internal Low-Speed (LSI) RC Oscillator.
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*
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****************************************************************************/
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void stm32l4_rcc_disablelsi(void)
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{
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/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
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* bit the RCC CSR register.
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*/
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modifyreg32(STM32L4_RCC_CSR, RCC_CSR_LSION, 0);
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/* LSIRDY should go low after 3 LSI clock cycles */
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}
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@@ -0,0 +1,119 @@
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/****************************************************************************
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* arch/arm/src/stm32l4/stm32l4_wdg.h
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*
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* Copyright (C) 2012, 2015, 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_WDG_H
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#define __ARCH_ARM_SRC_STM32L4_STM32L4_WDG_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/stm32l4_wdg.h"
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#ifdef CONFIG_WATCHDOG
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32l4_iwdginitialize
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*
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* Description:
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* Initialize the IWDG watchdog time. The watchdog timer is initialized
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* and registers as 'devpath. The initial state of the watchdog time is
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* disabled.
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*
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* Input Parameters:
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* devpath - The full path to the watchdog. This should be of the form
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* /dev/watchdog0
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* lsifreq - The calibrated LSI clock frequency
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*
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* Returned Values:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_STM32L4_IWDG
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void stm32l4_iwdginitialize(FAR const char *devpath, uint32_t lsifreq);
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#endif
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/****************************************************************************
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* Name: stm32l4_wwdginitialize
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*
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* Description:
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* Initialize the WWDG watchdog time. The watchdog timer is initialized and
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* registers as 'devpath. The initial state of the watchdog time is
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* disabled.
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*
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* Input Parameters:
|
||||
* devpath - The full path to the watchdog. This should be of the form
|
||||
* /dev/watchdog0
|
||||
*
|
||||
* Returned Values:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32L4_WWDG
|
||||
void stm32l4_wwdginitialize(FAR const char *devpath);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_WATCHDOG */
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_WDG_H */
|
||||
|
||||
Reference in New Issue
Block a user