mirror of
https://github.com/apache/nuttx.git
synced 2026-06-06 08:36:24 +08:00
Merge branch 'master' of bitbucket.org:nuttx/nuttx
This commit is contained in:
Gregory Nutt
@@ -3130,7 +3130,7 @@
|
||||
point numbers.
|
||||
* lib/stdio/lib_libdtoa.c and lib_libvsprintf.c: Correct some floating
|
||||
point options.
|
||||
* arch/arm/lpc43xx/lpc32_usb0dev.c: Add framework for development of
|
||||
* arch/arm/lpc43xx/lpc43_usb0dev.c: Add framework for development of
|
||||
an USB0, device-side driver for the LPC43XX. The initial check-in,
|
||||
however, is simply for the LPC31xx driver with name changes. The
|
||||
LPC31xx has the same USB IP, but will require some additional initialization
|
||||
@@ -4440,7 +4440,7 @@
|
||||
* binfmt/binfmt_execmodule.c: Here is a place where I forget
|
||||
to update the call to sched_releasetcb() to pass the thread
|
||||
type as the second parameter (2013-03-23).
|
||||
* arch/arm/src/lm, kinetis, lpc32, and nuc1xx: Add kernel build
|
||||
* arch/arm/src/lm, kinetis, lpc43, and nuc1xx: Add kernel build
|
||||
support to all ARMv7-M and ARMv6-M chips. There are no
|
||||
configurations in place to to verify these additions!
|
||||
(2013-03-24).
|
||||
@@ -10964,7 +10964,7 @@
|
||||
(2015-09-09).
|
||||
* configs/nucleo-f303re: Support for the STMicro Nucleo F303RE board
|
||||
from Paul Alexander Patience (2015-09-10).
|
||||
* arch/arm/src/lpc43xx/lpc32_ehci.c and .h: LPC43xx EHCI driver from
|
||||
* arch/arm/src/lpc43xx/lpc43_ehci.c and .h: LPC43xx EHCI driver from
|
||||
Ilya Averyanov (2015-09-10).
|
||||
* ARMv7-M, all "lazy" interrupt stack logic. Assembly instruction
|
||||
that fetches the saved value is incorrect; replace with more
|
||||
@@ -12348,7 +12348,7 @@
|
||||
adds DEBUGASSERT for invalid geometry and additional memory debug
|
||||
logic. Also fixes the dangling pointer on error bug. From Ken
|
||||
Pettit (2016-07-14).
|
||||
* arch/arm/src/lpc32xx: Extend LPC43xx EMC code to support SDRAM on a
|
||||
* arch/arm/src/lpc43xx: Extend LPC43xx EMC code to support SDRAM on a
|
||||
dynamic memory interface. From Vytautas Lukenskas (2016-07-19).
|
||||
* arch/sim/src: Add the simulated QSPI (N25Q) flash to the simulation
|
||||
and modify sim up_spiflash.c to enable it to run with different MTD
|
||||
@@ -12772,6 +12772,9 @@
|
||||
* STM32 DMA2D: fix an error in up_dma2dcreatelayer where an invalid
|
||||
pointer was returned when a certain underlying function failed. From
|
||||
Jens Gräf (2016-10-07).
|
||||
|
||||
7.19 2016-12-26 Gregory Nutt <gnutt@nuttx.org>
|
||||
|
||||
* include/nuttx/fs/nxffs.h: Needs forward reference to struct mtd_dev_s
|
||||
and needs to include stdbool.h (2016-10-09).
|
||||
* STM32F103 Minimum: Note in Kconfig that the board supports buttons.
|
||||
@@ -12844,16 +12847,16 @@
|
||||
(2016-10-19).
|
||||
* libc/locale: Allows c++ code to compile with or without
|
||||
CONFIG_LIBC_LOCALE and will generate a link error if CONFIG_LIBC_LOCALE
|
||||
is not defined and setlocale is referneced. With CONFIG_LIBC_LOCALE
|
||||
is not defined and setlocale is referenced. With CONFIG_LIBC_LOCALE
|
||||
defined setlocale will act as if MB string is not supported and return
|
||||
"C" for POSIX. C and "". From David Sidrane (2016-10-19).
|
||||
* Add vectors for interrupt levels 2-6 (2016-10-20).
|
||||
* strtof: Add strtof() as simply a copy of strtod with types and
|
||||
* Xtensa ESP32: Add vectors for interrupt levels 2-6 (2016-10-20).
|
||||
* strtof(): Add strtof() as simply a copy of strtod with types and
|
||||
limits changed (2016-10-20).
|
||||
* arch/arm/src/stm32v7: Register the watchdog device at the configured
|
||||
device path CONFIG_WATCHDOG_DEVPATH vs. hard-coded /dev/wdt. From Frank
|
||||
Benkert (2016-10-21).
|
||||
* configs/*/defdonf The buttons example was changed to archbuttons. As
|
||||
* configs/*/defconfig: The buttons example was changed to archbuttons. As
|
||||
a result all of the button configurations are broken and need some
|
||||
renaming in the defconfig files. Noted by Frank Berkert (2016-10-21).
|
||||
* configs/stm32f103-minimum: Add support to PWM on STM32F103-Minimum
|
||||
@@ -12909,7 +12912,7 @@
|
||||
found in the F4. From David Sidrane (2016-10-26).
|
||||
* arch/arm/src/stm32f7: stm32f76xx77xx_pinmap.h Missed one. From
|
||||
David Sidrane (2016-10-26).
|
||||
* LPC32xx serial: Fix a typo in ioctl TIOCSRS485 ioctl. From Vytautas
|
||||
* LPC43xx serial: Fix a typo in ioctl TIOCSRS485 ioctl. From Vytautas
|
||||
Lukenskas (2016-10-27).
|
||||
* sched/clock: Correct clock initialization. The correct range for
|
||||
the month is 0-11 but is entered as 1-12 in the .config file
|
||||
@@ -12919,7 +12922,7 @@
|
||||
* sched/Kconfig: Add ranges to START_YEAR, MONTH, and DAY (2016-10-28).
|
||||
* configs/nucleo-f303re: Add STM32 F303RE hello configuration; remove
|
||||
duplicate setting from board.h. From Marc Rechté (2016-10-18).
|
||||
* arch/arm/src/lpc32xx: Restore RS485 mode on serial port open (if
|
||||
* arch/arm/src/lpc43xx: Restore RS485 mode on serial port open (if
|
||||
RS485 is enabled via menuconfig). From Vytautas Lukenskas (2016-10-28).
|
||||
* arch/arm/src/stm32f7: otgdev fixed typo. From David Sidrane
|
||||
(2016-10-28).
|
||||
@@ -12949,14 +12952,12 @@
|
||||
From Paul A. Patience (2016-11-02).
|
||||
* drivers/ and drivers/spi: Fix Kconfig warning. This commit moves the
|
||||
ARCH_HAVE_SPI options outside the check for SPI. Those options don't
|
||||
depend on SPI, and Kconfig files in arch/ enable them even if SPI isn't
|
||||
enabled.
|
||||
|
||||
Sourcing the driver's Kconfig in drivers/Kconfig only if support for
|
||||
the driver is enabled prevents us from defining these ARCH_HAVE options
|
||||
in the driver's Kconfig. We should probably remove the other checks in
|
||||
drivers/Kconfig and check if the drivers are enabled only in their
|
||||
Kconfig. From Paul A. Patience (2016-11-02).
|
||||
depend on SPI, and Kconfig files in arch/ enable them even if SPI
|
||||
isn't enabled. Source the driver's Kconfig in drivers/Kconfig only
|
||||
if support for the driver is enabled prevents us from defining these
|
||||
ARCH_HAVE options in the driver's Kconfig. We should probably remove
|
||||
the other checks in drivers/Kconfig and check if the drivers are
|
||||
enabled only in their Kconfig. From Paul A. Patience (2016-11-02).
|
||||
* Move protoypes for the non-standard include/semaphore.h file to the
|
||||
non-standard include/nuttx/semaphore.h with the other non-standard
|
||||
semaphore interfaces (2016-11-02).
|
||||
@@ -13100,7 +13101,7 @@
|
||||
argument so that there can be additional usage. From Sebastien Lorquet
|
||||
(2016-11-17).
|
||||
* All timer lower half drivers. Port Sebastien's changes to all all
|
||||
other implementations of the timer lower half. Very many just and
|
||||
other implementations of the timer lower half. Many changes and
|
||||
untested. Expect some problems. (2016-11-17).
|
||||
* sched/irq: irq_csection() has a bad assumption in the SMP case. It
|
||||
assumed that the state of certain variables. That was true on entry
|
||||
@@ -13236,7 +13237,7 @@
|
||||
and execute "make" it will not detect that Pin.cxx was modified. I
|
||||
think there is some other place I should modify, but I didn't find
|
||||
it. From Alan Carvalho de Assis (2016-11-27).
|
||||
* ARMv7-A/i.MX6 SMP: Move SMP coherernt cache setup to earlier in
|
||||
* ARMv7-A/i.MX6 SMP: Move SMP coherent cache setup to earlier in
|
||||
initialization of CPUn, n>0 (2016-11-27).
|
||||
* ARMv7 GIC: SGIs are non-maskable but go through the same path as other,
|
||||
maskable interrupts. Added logic to serialize SGI processing when
|
||||
@@ -13356,5 +13357,122 @@
|
||||
* Add task_setcancelstate(), task_setcanceltype(), and task_testcancel().
|
||||
These are non-standard interfaces analogous to the correponding pthread_
|
||||
interfaces that provide cancellation controls for tasks (2016-12-10).
|
||||
* i.MX6 interrupt handling: Additional logic needed to handle nested
|
||||
interrupts when an interrupt stack is used (2016-12-13).
|
||||
* SAMV7 MCAN: Prevent Interrupt-Flooding of ACKE when not connected to
|
||||
CAN-BUS. An Acknowledge-Error will occur every time no other CAN Node
|
||||
acknowledges the message sent. This will also occur if the device is
|
||||
not connected to the can-bus. The CAN-Standard declares, that the Chip
|
||||
has to retry a given message as long as it is not sent successfully (or
|
||||
it is not cancelled by the application). Every time the chip tries to
|
||||
resend the message an Acknowledge-Error-Interrupt is generated. At high
|
||||
baud rates this can lead in extremely high CPU load just for handling
|
||||
the interrupts (and possibly the error handling in the application). To
|
||||
prevent this Interrupt-Flooding we disable the ACKE once it is seen as
|
||||
long we didn't transfer at least one message successfully. From Frank
|
||||
Benkert (2016-12-13).
|
||||
* i.MX6: Remove non-cached, inter-cpu memory region. Not a useful
|
||||
concept (2016-12-13).
|
||||
* minnsh Configurations: Remove minnsh configurations and support logic:
|
||||
up_getc() and lowinstream. This was an interesting exercise to see
|
||||
just how small you could get NuttX, but otherwise it was not useful:
|
||||
(1) the NSH code violated the OS interface layer by callup up_getc and
|
||||
up_putc directly, and (2) while waiting for character input, NSH would
|
||||
call up_getc() which would hog all of the CPU. Not a reasonable
|
||||
solution other than as a proof of concept (2016-12-13).
|
||||
* Calypso Boards: Remove all Calypso board configurations (2016-12-13).
|
||||
* Calypso: Remove Calypso architecture support and support for Calypso
|
||||
SERCOMM driver (2016-12-13).
|
||||
* ESP32 core v2: Two changes (1) flushes the UART TX buffer in the esp32
|
||||
serial shutdown routine. The ROM bootloader does not flush the FIFO
|
||||
before handing over to user code, so some of this output is not
|
||||
currently seen when the UART is reconfigured in early stages of
|
||||
startup. And changes the openocd config file's default flash voltage
|
||||
from 1.8V to 3.3V. This is not necessary right now, but may save some
|
||||
hard-to-debug moments down the track (3.3V-only flash running at 1.8V
|
||||
often half-works and does weird things...). From Angus Gratton
|
||||
(2016-12-14).
|
||||
* Xtensa ESP32: Add missing ENTRY() and RET() macros in C callable
|
||||
assembly language. At one time I though the that the ESP32 support the
|
||||
CALL0 ABI. I was mistaken so there may be a few more like this
|
||||
(2016-12-14).
|
||||
* Xtensa ESP32: Fix a couple of bugs associated with handling of CPU
|
||||
interrupts (2016-12-14).
|
||||
* Xtensa ESP32: Fix several build-related issues associated with vector
|
||||
section (2016-12-15).
|
||||
* Xtensa ESP32: Fix missing CALL0 ABI condition (2016-12-15).
|
||||
* Xtensa EPS32: Make sure that all C callable assembly functions includes
|
||||
ENTRY prologue and RET epilogue (2016-12-15).
|
||||
* Xtensa ESP32: Fix windowspill register handling + Use r6, not r2 when
|
||||
passing paramters with call4 (2016-12-16).
|
||||
* Xtensa ESP32: Use r6, not r2 when passing paramters with call4
|
||||
(2016-12-16).
|
||||
* Xtensa ESP32: Correct a logic problem the prevented dumping the IDLE
|
||||
thread's stack on an assertion (2016-12-16).
|
||||
* Xtensa ESP32: Fix some missing SMP logic (2016-12-16).
|
||||
* Xtensa ESP32: Basically a redesign of the interrupt dispatch logic
|
||||
(2016-12-16).
|
||||
* Xtensa ESP32: Level 1 interrupts should return via RFE (2016-12-17).
|
||||
* Xtensa ESP32: One register getting clobber on context save (2016-12-17).
|
||||
* STM32 F7: Fix some STM32F7 copy paste errors. From David Sidrane
|
||||
(2016-12-17).
|
||||
* CDC/ACM Device Class: uart_ops_s portion of cdcacm will not be
|
||||
initalized with correct functions if CONFIG_SERIAL_DMA is lit
|
||||
(2016-12-17).
|
||||
* Xtensa ESP32: Using wrong register to disable interrupts (2016-12-17).
|
||||
* Xtensa ESP32: Fix clobbered a9 in co-processor context save/restore
|
||||
(2016-12-17).
|
||||
* Xtensa ESP32: Need to clone some logic for synchronous context switch.
|
||||
Window spill logic in the conmon restores logic is inappropriate in
|
||||
this context (2016-12-17).
|
||||
* sscanf(): Add scansets to the scanf function. Enabled
|
||||
CONFIG_LIBC_SCANSET option. From Aleksandr Vyhovanec (2016-12-17).
|
||||
* Xtensa ESP32: Fix context save logic when called in window ABI
|
||||
configuration. Add an IDLE stack. Don't depend on the mystery stack
|
||||
received from the bootloader (2016-12-18).
|
||||
* Xtensa ESP32: Need to spill registers to memory as the last dying
|
||||
action before switching to a new thread (2016-12-18).
|
||||
* ESP32 Serial: Add logic to prevent infinite loops in interrupt handler
|
||||
(2016-12-18).
|
||||
* Xtensa ESP32: Automatically mount /proc at start-up (2016-12-19).
|
||||
* Xtensa ESP32: Corrects timer initialization and timer input frequency
|
||||
(2016-12-19).
|
||||
* Tiva PWM: Support PWM_PULSECOUNT feature for TI tiva. From Young.Mu
|
||||
(2016-12-20).
|
||||
* Xtensa ESP32: Missing prologue/epilogue macros on C callable function
|
||||
(2016-12-20).
|
||||
* Xtensa ESP32: Update APP CPU startup logic to match current Expressif
|
||||
example code. Fix errors APP CPU startup (2016-12-20).
|
||||
* fs/procfs: Fix procfs status for SMP case (2016-12-20).
|
||||
* Xtensa ESP32: Clock frequency is different if running from IRAM or is
|
||||
booting from FLASH. This is a booltloader issue (2016-12-20).
|
||||
* Xtensa ESP32: Basic port is function in both single CPU and dual CPU
|
||||
SMP configurations. There is an NSH configuration for each CPU
|
||||
configuration (2016-12-21).
|
||||
* STM32 F4: Merge in support for the Olimex STM32 P407 board (2016-12-21).
|
||||
* Xtensa ESP32: Add an OS test to verify the port (2016-12-22).
|
||||
* Xtensa ESP32: Corrects a problem with dispatching to signal handlers:
|
||||
Cannot vector directly to the signal handling function as in other ABIs
|
||||
under the Xtensa Window ABI. In that case, we need to go through a
|
||||
tiny hook when performs the correct window call (call4) otherwise
|
||||
registers will be scrambled in the signal handler (2016-12-22).
|
||||
* SAMV7 CAN: Make delete_filter functions more robust. From Frank
|
||||
Benkert (2016-12-23).
|
||||
* Xtensa ESP32: Add stack checking logic (2016-12-23).
|
||||
* sched note: record ID enumeration now results on constant values; ID
|
||||
values do not change with configuration. This makes writing
|
||||
post-processing software much easier (2016-12-24).
|
||||
* STM32 F3: Forgot to update chip.h for STM32F303x[BC]'s 4 ADCs
|
||||
(2016-12-24).
|
||||
* STM32 F4: Allow dma in 1 bit mode in STM32F4xxx. From David Sidrane
|
||||
(2016-12-24).
|
||||
* termios.h: Fix CRTSCTS define to include input and output flow.
|
||||
From Lorenz Meier (2016-12-26).
|
||||
* SMP: Enforce this rule: Tasks which are normally restored when
|
||||
sched_unlock() is called must remain pending (1) if we are in a
|
||||
critical section, i.e., g_cpu_irqlock is locked , or (2) other CPUs
|
||||
still have pre-emption disabled, i.e., g_cpu_schedlock is locked. In
|
||||
those cases, the release of the pending tasks must be deferred until
|
||||
those conditions are met (2016-12-26).
|
||||
|
||||
7.19 2016-xx-xx Gregory Nutt <gnutt@nuttx.org>
|
||||
7.20 2017-xx-xx Gregory Nutt <gnutt@nuttx.org>
|
||||
|
||||
+117
-15
@@ -8,7 +8,7 @@
|
||||
<tr align="center" bgcolor="#e4e4e4">
|
||||
<td>
|
||||
<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
|
||||
<p>Last Updated: October 8, 2016</p>
|
||||
<p>Last Updated: December 26, 2016</p>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
@@ -317,7 +317,7 @@
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<li>POSIX/ANSI-like task controls, named message queues, counting semaphores, clocks/timers, signals, pthreads, environment variables, filesystem.</li>
|
||||
<li>POSIX/ANSI-like task controls, named message queues, counting semaphores, clocks/timers, signals, pthreads, cancellation points, environment variables, filesystem.</li>
|
||||
</p>
|
||||
</tr>
|
||||
|
||||
@@ -1339,11 +1339,11 @@
|
||||
<h2>Released Versions</h2>
|
||||
<p>
|
||||
In addition to the ever-changing GIT repository, there are frozen released versions of NuttX available.
|
||||
The current release is NuttX 7.18.
|
||||
NuttX 7.18 is the 118<sup>th</sup> release of NuttX.
|
||||
It was released on October 8, 2016, and is available for download from the
|
||||
The current release is NuttX 7.19.
|
||||
NuttX 7.19 is the 119<sup>th</sup> release of NuttX.
|
||||
It was released on December 26, 2016, and is available for download from the
|
||||
<a href="https://bitbucket.org/nuttx/nuttx/downloads/">Bitbucket.org</a> website.
|
||||
Note that the release consists of two tarballs: <code>nuttx-7.18.tar.gz</code> and <code>apps-7.18.tar.gz</code>.
|
||||
Note that the release consists of two tarballs: <code>nuttx-7.19.tar.gz</code> and <code>apps-7.19.tar.gz</code>.
|
||||
Both may be needed (see the top-level <code>nuttx/README.txt</code> file for build information).
|
||||
</p>
|
||||
|
||||
@@ -1352,7 +1352,7 @@
|
||||
<ul>
|
||||
<li><b>nuttx</b>.
|
||||
<ul><p>
|
||||
Release notes for NuttX 7.18 are available <a href="https://bitbucket.org/nuttx/nuttx/downloads/">here</a>.
|
||||
Release notes for NuttX 7.19 are available <a href="https://bitbucket.org/nuttx/nuttx/downloads/">here</a>.
|
||||
Release notes for all released versions on NuttX are available in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ReleaseNotes" target="_blank">Bitbucket GIT</a>.
|
||||
The ChangeLog for all releases of NuttX is available in the ChangeLog file that can viewed in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ChangeLog" target="_blank">Bitbucket GIT</a>.
|
||||
The ChangeLog for the current release is at the bottom of that file.
|
||||
@@ -1360,7 +1360,7 @@
|
||||
</li></ul>
|
||||
<li><b>apps</b>.
|
||||
<ul><p>
|
||||
Release notes for NuttX 7.18 are available <a href="https://bitbucket.org/nuttx/apps/downloads/">here</a>.
|
||||
Release notes for NuttX 7.19 are available <a href="https://bitbucket.org/nuttx/apps/downloads/">here</a>.
|
||||
Release notes for all released versions on NuttX are available in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ReleaseNotes" target="_blank">Bitbucket GIT</a>
|
||||
The ChangeLog for the all releases of <code>apps/</code> is available in the ChangeLog file that can viewed in the <a href="https://bitbucket.org/nuttx/apps/src/master/ChangeLog.txt" target="_blank">Bitbucket GIT</a>.
|
||||
The ChangeLog for the current release is at the bottom of that file.
|
||||
@@ -1418,7 +1418,7 @@
|
||||
<li><a href="#armcortexr4">ARM Cortex-R4</a> (1)</li>
|
||||
<li><a href="#armcortexm0">ARM Cortex-M0/M0+</a> (7)</li>
|
||||
<li><a href="#armcortexm3">ARM Cortex-M3</a> (35)</li>
|
||||
<li><a href="#armcortexm4">ARM Cortex-M4</a> (31)</li>
|
||||
<li><a href="#armcortexm4">ARM Cortex-M4</a> (32)</li>
|
||||
<li><a href="#armcortexm7">ARM Cortex-M7</a> (7)</li>
|
||||
</ul>
|
||||
<li>Atmel AVR
|
||||
@@ -1445,6 +1445,10 @@
|
||||
<li><a href="#pic32mzmips">PIC32MZ</a> (MIPS M14K) (1)</li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Misoc
|
||||
<ul>
|
||||
<li><a href="#misoclm32">LM32</a> (1)</li>
|
||||
</ul>
|
||||
<li>Renesas/Hitachi:
|
||||
<ul>
|
||||
<li><a href="#superh">Renesas/Hitachi SuperH</a> (1/2)</li>
|
||||
@@ -1453,6 +1457,15 @@
|
||||
</li>
|
||||
</td>
|
||||
<td bgcolor="#e4e4e4" valign="top" width="33%">
|
||||
<li><a href="#riscv">RISC-V</a> (1)
|
||||
<ul>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Xtensa LX6:
|
||||
<ul>
|
||||
<li><a href="#esp32">ESP32</a> (1)</li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>ZiLOG
|
||||
<ul>
|
||||
<li><a href="#zilogz16f">ZiLOG ZNEO Z16F</a> (2)</li>
|
||||
@@ -1502,6 +1515,11 @@
|
||||
<li><a href="#at91sama5d4">Atmel SAMA5D4</a> <small>(ARM Cortex-A5)</small></li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Expressif
|
||||
<ul>
|
||||
<li><a href="#esp32">ESP32</a> <small>(Dual Xtensa LX6)</small</li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Freescale
|
||||
<ul>
|
||||
<li><a href="#m68hcs12">M68HCS12</a></li>
|
||||
@@ -1533,13 +1551,13 @@
|
||||
<li><a href="#pic32mzec">PIC32MZEC Family</a> <small>(MIPS32 M14K)</small></li>
|
||||
</ul>
|
||||
</li>
|
||||
</td>
|
||||
<td bgcolor="#e4e4e4" valign="top" width="33%">
|
||||
<li>Moxa
|
||||
<ul>
|
||||
<li><a href="#moxart">Moxa NP51x0</a> <small>(ARMv4)</small></li>
|
||||
</ul>
|
||||
</li>
|
||||
</td>
|
||||
<td bgcolor="#e4e4e4" valign="top" width="33%">
|
||||
<li>nuvoTon
|
||||
<ul>
|
||||
<li><a href="#nuvotonnu120">nuvoTon NUC120</a> <small>(ARM Cortex-M0)</small></li>
|
||||
@@ -3134,7 +3152,7 @@ nsh>
|
||||
<li>
|
||||
<p>
|
||||
<b>Kamami STM32 Butterfly 2</b>
|
||||
Support for the <a href="https://kamami.pl/zestawy-uruchomieniowe-stm32/178507-stm32butterfly2.html">Kamami STM32 Butterfly 2</a> was contributed by Michał Łyszczek in NuttX-7/18. That port features the STMicro STM32F107VC MCU.
|
||||
Support for the <a href="https://kamami.pl/zestawy-uruchomieniowe-stm32/178507-stm32butterfly2.html">Kamami STM32 Butterfly 2</a> was contributed by Michał Łyszczek in NuttX-7.18. That port features the STMicro STM32F107VC MCU.
|
||||
</p>
|
||||
<p>
|
||||
<b>STATUS:</b>
|
||||
@@ -3717,11 +3735,14 @@ nsh>
|
||||
<li><b>NuttX-7.3</b>
|
||||
Support for the Olimex STM32 H405 board was added in NuttX-7.3.
|
||||
</li>
|
||||
<li>
|
||||
Refer to the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/stm3240g-eval/README.txt" target="_blank">README</a> file for further information.
|
||||
<li><b>NuttX-7.19</b>
|
||||
Support for the Olimex STM32 P405 board was added in NuttX-7.19.
|
||||
</li>
|
||||
</ul>
|
||||
</p>
|
||||
<p>
|
||||
Refer to the STM3240G-EVAL board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/stm3240g-eval/README.txt" target="_blank">README</a> file for further information.
|
||||
</p>
|
||||
<p>
|
||||
<b>STMicro STM32F4-Discovery</b>.
|
||||
This port uses the STMicro STM32F4-Discovery board featuring the STM32F407VGT6 MCU.
|
||||
@@ -3791,6 +3812,11 @@ nsh>
|
||||
Networking configurations were added in NuttX-7.18.
|
||||
See the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/olimex-stm32-e407/README.txt" target="_blank">README</a> file for further information about the NuttX port.
|
||||
</p>
|
||||
<p>
|
||||
<b>Olimex STM32 P407</b>.
|
||||
Support for the Olimex STM32 P407 development board appeared in NuttX-7.19.
|
||||
See the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/olimex-stm32-p407/README.txt" target="_blank">README</a> file for further information about the NuttX port.
|
||||
</p>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
@@ -4306,7 +4332,7 @@ Mem: 29232 5920 23312 23312
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<a name="at91sam4c"><b>Atmel SAM4C</b>.</a>
|
||||
<a name="at91sam4c"><b>Atmel SAM4CM</b>.</a>
|
||||
General architectural support was provided for SAM4CM family in NuttX 7.3
|
||||
This was <i>architecture-only</i> support, meaning that support for the boards with these chips is available, but no support for any publicly available boards was included.
|
||||
The SAM4CM port should be compatible with most of the SAM3/4 drivers (like HSMCI, DMAC, etc.) but those have not be verified on hardware as of this writing.
|
||||
@@ -4314,6 +4340,18 @@ Mem: 29232 5920 23312 23312
|
||||
</p>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<b>Atmel SAM4CMP-DB</b>.
|
||||
Support for the SAM4CMP-DB board was contributed to NuttX by Masayuki Ishikawa in NuttX-7.19.
|
||||
The SAM4CM is a dual-CPU part and SMP was included for the ARMv7-M and SAM3/4 families.
|
||||
The SAM4CMP-DB board support includes an NSH configuration that operates in an SMP configuration.
|
||||
Refer to the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/sam4cmp-db/README.txt" target="_blank">README</a> file for further information.
|
||||
</p>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td><hr></td>
|
||||
@@ -4830,6 +4868,23 @@ Mem: 29232 5920 23312 23312
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td valign="top"><img height="20" width="20" src="favicon.ico"></td>
|
||||
<td bgcolor="#5eaee1">
|
||||
<a name="misoclm32"><b>Misoc LM32</b>.</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<b>Misoc LM32 Architectural Support</b>.
|
||||
Architectural support for the Misoc LM32 was contributed by Ramtin Amin in NuttX 7.19. Driver support is basic in this initial release: Serial, Timer, and Ethernet. "Board" support is a available for developing with Misoc LM32 under Qemu or on your custom FPGA.
|
||||
</p>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td valign="top"><img height="20" width="20" src="favicon.ico"></td>
|
||||
<td bgcolor="#5eaee1">
|
||||
@@ -5196,6 +5251,53 @@ BFD_ASSERT (*plt_offset != (bfd_vma) -1);
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
|
||||
<tr>
|
||||
<td valign="top"><img height="20" width="20" src="favicon.ico"></td>
|
||||
<td bgcolor="#5eaee1">
|
||||
<a name="riscv"><b>RISC-V</b>.</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<b>RISC-V Architectural Support</b>.
|
||||
Basic support for the RISC-V architecture was contributed by Ken Pettit in NuttX-7.19. The initial release is <i>thin</i> but a great starting point for anyone interested in RISC-V development with NuttX.
|
||||
</p>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td valign="top"><img height="20" width="20" src="favicon.ico"></td>
|
||||
<td bgcolor="#5eaee1">
|
||||
<a name="esp32"><b>ESP32 <small>(Dual Xtensa LX6)</small></b>.</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<b>Xtensa LX6 ESP32 Architectural Support</b>.
|
||||
Basic architectural support for Xtensa LX6 processors and the port for the Expressif ESP32 were added in NuttX-7.19.
|
||||
The basic ESP32 port is function in both single CPU and dual CPU SMP configurations.
|
||||
</p>
|
||||
<p>
|
||||
<b>Expressif ESP32 Core v2 Board</b>
|
||||
The NuttX release includes support for Expressif ESP32 Core v2 board.
|
||||
There is an NSH configuration for each CPU configuration and an OS test configuration for verificatin of the port.
|
||||
</p>
|
||||
<p>
|
||||
<b>STATUS</b>.
|
||||
ESP32 support in NuttX-7.19 is functional, but very preliminary.
|
||||
There is little yet in the way of device driver support.
|
||||
Outstanding issues include missing clock configuration logic, missing partition tables to support correct configuration from FLASH, and some serial driver pin configuration issues.
|
||||
The configuration is usable despite these limitations.
|
||||
Refer to the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/esp32-core/README.txt" target="_blank">README</a> file for further information.
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td valign="top"><img height="20" width="20" src="favicon.ico"></td>
|
||||
<td bgcolor="#5eaee1">
|
||||
|
||||
+791
File diff suppressed because it is too large
Load Diff
@@ -115,10 +115,6 @@ static void up_output_compare(uint32_t sr, uint32_t of)
|
||||
|
||||
if ((sr & of) != 0)
|
||||
{
|
||||
/* Clear the pending output compare interrupt */
|
||||
|
||||
putreg32(of, IMX_GPT_SR);
|
||||
|
||||
/* Process timer interrupt event */
|
||||
|
||||
sched_process_timer();
|
||||
@@ -140,9 +136,16 @@ static void up_output_compare(uint32_t sr, uint32_t of)
|
||||
|
||||
int up_timerisr(int irq, uint32_t *regs)
|
||||
{
|
||||
/* Sample the SR (once) and process all pending output compare interrupt */
|
||||
/* Sample the SR (once) */
|
||||
|
||||
uint32_t sr = getreg32(IMX_GPT_SR);
|
||||
|
||||
/* Clear GPT status register */
|
||||
|
||||
putreg32(sr, IMX_GPT_SR);
|
||||
|
||||
/* Process all pending output compare interrupt */
|
||||
|
||||
up_output_compare(sr, GPT_INT_OF1);
|
||||
up_output_compare(sr, GPT_INT_OF2);
|
||||
up_output_compare(sr, GPT_INT_OF3);
|
||||
|
||||
@@ -198,8 +198,8 @@
|
||||
#define GPIO_USART1_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_USART1_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
#if defined(CONFIG_STM32_USART1_REMAP)
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7)
|
||||
#else
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
|
||||
@@ -237,8 +237,8 @@
|
||||
/* USART */
|
||||
|
||||
#if defined(CONFIG_STM32_USART1_REMAP)
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7)
|
||||
#else
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
|
||||
@@ -370,8 +370,8 @@
|
||||
#define GPIO_USART1_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_USART1_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
#if defined(CONFIG_STM32_USART1_REMAP)
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7)
|
||||
#else
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
|
||||
@@ -272,8 +272,8 @@
|
||||
/* USART */
|
||||
|
||||
#if defined(CONFIG_STM32_USART1_REMAP)
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7)
|
||||
#else
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
|
||||
@@ -280,8 +280,8 @@
|
||||
#define GPIO_USART1_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_USART1_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
#if defined(CONFIG_STM32_USART1_REMAP)
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7)
|
||||
#else
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
|
||||
@@ -314,8 +314,8 @@
|
||||
#define GPIO_USART1_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_USART1_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
#if defined(CONFIG_STM32_USART1_REMAP)
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7)
|
||||
#else
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
|
||||
@@ -315,7 +315,7 @@ CONFIG_USER_ENTRYPOINT="nsh_main"
|
||||
CONFIG_RR_INTERVAL=200
|
||||
# CONFIG_SCHED_SPORADIC is not set
|
||||
CONFIG_TASK_NAME_SIZE=31
|
||||
CONFIG_MAX_TASKS=16
|
||||
CONFIG_MAX_TASKS=32
|
||||
# CONFIG_SCHED_HAVE_PARENT is not set
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
|
||||
@@ -324,6 +324,8 @@ CONFIG_SCHED_WAITPID=y
|
||||
#
|
||||
# CONFIG_MUTEX_TYPES is not set
|
||||
CONFIG_NPTHREAD_KEYS=4
|
||||
# CONFIG_PTHREAD_CLEANUP is not set
|
||||
# CONFIG_CANCELLATION_POINTS is not set
|
||||
|
||||
#
|
||||
# Performance Monitoring
|
||||
@@ -647,6 +649,8 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512
|
||||
# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
|
||||
CONFIG_ARCH_HAVE_TLS=y
|
||||
# CONFIG_TLS is not set
|
||||
# CONFIG_LIBC_IPv4_ADDRCONV is not set
|
||||
# CONFIG_LIBC_IPv6_ADDRCONV is not set
|
||||
# CONFIG_LIBC_NETDB is not set
|
||||
# CONFIG_NETDB_HOSTFILE is not set
|
||||
|
||||
@@ -730,7 +734,10 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
|
||||
# CONFIG_EXAMPLES_SLCD is not set
|
||||
# CONFIG_EXAMPLES_SMART is not set
|
||||
# CONFIG_EXAMPLES_SMART_TEST is not set
|
||||
# CONFIG_EXAMPLES_SMP is not set
|
||||
CONFIG_EXAMPLES_SMP=y
|
||||
CONFIG_EXAMPLES_SMP_NBARRIER_THREADS=8
|
||||
CONFIG_EXAMPLES_SMP_PRIORITY=100
|
||||
CONFIG_EXAMPLES_SMP_STACKSIZE=2048
|
||||
# CONFIG_EXAMPLES_TCPECHO is not set
|
||||
# CONFIG_EXAMPLES_TELNETD is not set
|
||||
# CONFIG_EXAMPLES_TIFF is not set
|
||||
@@ -858,6 +865,7 @@ CONFIG_NSH_MMCSDMINOR=0
|
||||
# Configure Command Options
|
||||
#
|
||||
# CONFIG_NSH_CMDOPT_DF_H is not set
|
||||
# CONFIG_NSH_CMDOPT_DD_STATS is not set
|
||||
CONFIG_NSH_CODECS_BUFSIZE=128
|
||||
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
|
||||
CONFIG_NSH_PROC_MOUNTPOINT="/proc"
|
||||
|
||||
@@ -330,7 +330,7 @@ void spin_unlockr(FAR struct spinlock_s *lock);
|
||||
* Input Parameters:
|
||||
* set - A reference to the bitset to set the CPU bit in
|
||||
* cpu - The bit number to be set
|
||||
* setlock - A reference to the lock lock protecting the set
|
||||
* setlock - A reference to the lock protecting the set
|
||||
* orlock - Will be set to SP_LOCKED while holding setlock
|
||||
*
|
||||
* Returned Value:
|
||||
@@ -351,7 +351,7 @@ void spin_setbit(FAR volatile cpu_set_t *set, unsigned int cpu,
|
||||
* Input Parameters:
|
||||
* set - A reference to the bitset to set the CPU bit in
|
||||
* cpu - The bit number to be set
|
||||
* setlock - A reference to the lock lock protecting the set
|
||||
* setlock - A reference to the lock protecting the set
|
||||
* orlock - Will be set to SP_UNLOCKED if all bits become cleared in set
|
||||
*
|
||||
* Returned Value:
|
||||
|
||||
+1
-1
@@ -110,8 +110,8 @@
|
||||
#define HUPCL (1 << 6) /* Bit 6: Hang up on last close */
|
||||
#define CLOCAL (1 << 7) /* Bit 7: Ignore modem status lines */
|
||||
#define CCTS_OFLOW (1 << 8) /* Bit 8: CTS flow control of output */
|
||||
#define CRTSCTS CCTS_OFLOW
|
||||
#define CRTS_IFLOW (1 << 9) /* Bit 9: RTS flow control of input */
|
||||
#define CRTSCTS (CRTS_IFLOW | CCTS_OFLOW)
|
||||
|
||||
/* Local Modes (c_lflag in the termios structure) */
|
||||
|
||||
|
||||
@@ -44,6 +44,7 @@
|
||||
#include <nuttx/compiler.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/irq.h>
|
||||
@@ -106,6 +107,33 @@ void weak_function irq_initialize(void);
|
||||
|
||||
int irq_unexpected_isr(int irq, FAR void *context);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: irq_cpu_locked
|
||||
*
|
||||
* Description:
|
||||
* Test if the IRQ lock set OR if this CPU holds the IRQ lock
|
||||
* There is an interaction with pre-emption controls and IRQ locking:
|
||||
* Even if the pre-emption is enabled, tasks will be forced to pend if
|
||||
* the IRQ lock is also set UNLESS the CPU starting the task is the
|
||||
* holder of the IRQ lock.
|
||||
*
|
||||
* Inputs:
|
||||
* rtcb - Points to the blocked TCB that is ready-to-run
|
||||
*
|
||||
* Return Value:
|
||||
* true - IRQs are locked by a different CPU.
|
||||
* false - IRQs are unlocked OR if they are locked BUT this CPU
|
||||
* is the holder of the lock.
|
||||
*
|
||||
* Warning: This values are volatile at only valid at the instance that
|
||||
* the CPU set was queried.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
bool irq_cpu_locked(int cpu);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -504,9 +504,41 @@ void leave_critical_section(irqstate_t flags)
|
||||
DEBUGASSERT(spin_islocked(&g_cpu_irqlock) &&
|
||||
(g_cpu_irqset & (1 << cpu)) != 0);
|
||||
|
||||
/* Check if releasing the lock held by this CPU will unlock the
|
||||
* critical section.
|
||||
*/
|
||||
|
||||
if ((g_cpu_irqset & ~(1 << cpu)) == 0)
|
||||
{
|
||||
/* Yes.. Check if there are pending tasks and that pre-emption
|
||||
* is also enabled. This is necessary because we may have
|
||||
* deferred the up_release_pending() call in sched_unlock()
|
||||
* because we were within a critical section then.
|
||||
*/
|
||||
|
||||
if (g_pendingtasks.head != NULL &&
|
||||
!spin_islocked(&g_cpu_schedlock))
|
||||
{
|
||||
/* Release any ready-to-run tasks that have collected
|
||||
* in g_pendingtasks. NOTE: This operation has a very
|
||||
* high likelihood of causing this task to be switched
|
||||
* out!
|
||||
*/
|
||||
|
||||
up_release_pending();
|
||||
}
|
||||
}
|
||||
|
||||
/* Now, possibly on return from a context switch, clear our
|
||||
* count on the lock. If all CPUs have released the lock,
|
||||
* then unlock the global IRQ spinlock.
|
||||
*/
|
||||
|
||||
rtcb->irqcount = 0;
|
||||
spin_clrbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock,
|
||||
&g_cpu_irqlock);
|
||||
|
||||
/* Have all CPUs released the lock? */
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -540,4 +572,78 @@ void leave_critical_section(irqstate_t flags)
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: irq_cpu_locked
|
||||
*
|
||||
* Description:
|
||||
* Test if the IRQ lock set OR if this CPU holds the IRQ lock
|
||||
* There is an interaction with pre-emption controls and IRQ locking:
|
||||
* Even if the pre-emption is enabled, tasks will be forced to pend if
|
||||
* the IRQ lock is also set UNLESS the CPU starting the task is the
|
||||
* holder of the IRQ lock.
|
||||
*
|
||||
* Inputs:
|
||||
* rtcb - Points to the blocked TCB that is ready-to-run
|
||||
*
|
||||
* Return Value:
|
||||
* true - IRQs are locked by a different CPU.
|
||||
* false - IRQs are unlocked OR if they are locked BUT this CPU
|
||||
* is the holder of the lock.
|
||||
*
|
||||
* Warning: This values are volatile at only valid at the instance that
|
||||
* the CPU set was queried.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
bool irq_cpu_locked(int cpu)
|
||||
{
|
||||
cpu_set_t irqset;
|
||||
|
||||
/* g_cpu_irqset is not valid in early phases of initialization */
|
||||
|
||||
if (g_os_initstate < OSINIT_OSREADY)
|
||||
{
|
||||
/* We are still single threaded. In either state of g_cpu_irqlock,
|
||||
* the correct return value should always be false.
|
||||
*/
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Test if g_cpu_irqlock is locked. We don't really need to use check
|
||||
* g_cpu_irqlock to do this, we can use the g_cpu_set.
|
||||
*
|
||||
* Sample the g_cpu_irqset once. That is an atomic operation. All
|
||||
* subsequent operations will operate on the sampled cpu set.
|
||||
*/
|
||||
|
||||
irqset = (cpu_set_t)g_cpu_irqset;
|
||||
if (irqset != 0)
|
||||
{
|
||||
/* Some CPU holds the lock. So g_cpu_irqlock should be locked.
|
||||
* Return false if the 'cpu' is the holder of the lock; return
|
||||
* true if g_cpu_irqlock is locked, but this CPU is not the
|
||||
* holder of the lock.
|
||||
*/
|
||||
|
||||
return ((irqset & (1 << cpu)) == 0);
|
||||
}
|
||||
|
||||
/* No CPU holds the lock */
|
||||
|
||||
else
|
||||
{
|
||||
/* In this case g_cpu_irqlock should be unlocked. However, if
|
||||
* the lock was established in the interrupt handler AND there are
|
||||
* no bits set in g_cpu_irqset, that probabaly means only that
|
||||
* critical section was established from an interrupt handler.
|
||||
* Return false in either case.
|
||||
*/
|
||||
|
||||
return false;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_SMP || CONFIG_SCHED_INSTRUMENTATION_CSECTION */
|
||||
|
||||
@@ -167,10 +167,11 @@ bool sched_addreadytorun(FAR struct tcb_s *btcb)
|
||||
{
|
||||
FAR struct tcb_s *rtcb;
|
||||
FAR dq_queue_t *tasklist;
|
||||
int task_state;
|
||||
int cpu;
|
||||
bool switched;
|
||||
bool doswitch;
|
||||
int task_state;
|
||||
int cpu;
|
||||
int me;
|
||||
|
||||
/* Check if the blocked TCB is locked to this CPU */
|
||||
|
||||
@@ -226,9 +227,17 @@ bool sched_addreadytorun(FAR struct tcb_s *btcb)
|
||||
* disabled. If the selected state is TSTATE_TASK_READYTORUN, then it
|
||||
* should also go to the pending task list so that it will have a chance
|
||||
* to be restarted when the scheduler is unlocked.
|
||||
*
|
||||
* There is an interaction here with IRQ locking. Even if the pre-
|
||||
* emption is enabled, tasks will be forced to pend if the IRQ lock
|
||||
* is also set UNLESS the CPU starting the thread is also the holder of
|
||||
* the IRQ lock. irq_cpu_locked() performs an atomic check for that
|
||||
* situation.
|
||||
*/
|
||||
|
||||
if (spin_islocked(&g_cpu_schedlock) && task_state != TSTATE_TASK_ASSIGNED)
|
||||
me = this_cpu();
|
||||
if ((spin_islocked(&g_cpu_schedlock) || irq_cpu_locked(me)) &&
|
||||
task_state != TSTATE_TASK_ASSIGNED)
|
||||
{
|
||||
/* Add the new ready-to-run task to the g_pendingtasks task list for
|
||||
* now.
|
||||
@@ -255,10 +264,8 @@ bool sched_addreadytorun(FAR struct tcb_s *btcb)
|
||||
}
|
||||
else /* (task_state == TSTATE_TASK_ASSIGNED || task_state == TSTATE_TASK_RUNNING) */
|
||||
{
|
||||
int me = this_cpu();
|
||||
|
||||
/* If we are modifying some assigned task list other than our own, we will
|
||||
* need to stop that CPU.
|
||||
/* If we are modifying some assigned task list other than our own, we
|
||||
* will need to stop that CPU.
|
||||
*/
|
||||
|
||||
if (cpu != me)
|
||||
@@ -273,7 +280,8 @@ bool sched_addreadytorun(FAR struct tcb_s *btcb)
|
||||
tasklist = (FAR dq_queue_t *)&g_assignedtasks[cpu];
|
||||
switched = sched_addprioritized(btcb, tasklist);
|
||||
|
||||
/* If the selected task was the g_assignedtasks[] list, then a context
|
||||
/* If the selected task list was the g_assignedtasks[] list and if the
|
||||
* new tasks is the highest priority (RUNNING) task, then a context
|
||||
* switch will occur.
|
||||
*/
|
||||
|
||||
@@ -367,7 +375,14 @@ bool sched_addreadytorun(FAR struct tcb_s *btcb)
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No context switch. Assign the CPU and set the assigned state */
|
||||
/* No context switch. Assign the CPU and set the assigned state.
|
||||
*
|
||||
* REVISIT: I have seen this assertion fire. Apparently another
|
||||
* CPU may add another, higher prioirity task to the same
|
||||
* g_assignedtasks[] list sometime after sched_cpu_select() was
|
||||
* called above, leaving this TCB in the wrong task list if task_state
|
||||
* is TSTATE_TASK_ASSIGNED).
|
||||
*/
|
||||
|
||||
DEBUGASSERT(task_state == TSTATE_TASK_ASSIGNED);
|
||||
|
||||
|
||||
@@ -48,6 +48,7 @@
|
||||
# include <nuttx/spinlock.h>
|
||||
#endif
|
||||
|
||||
#include "irq/irq.h"
|
||||
#include "sched/sched.h"
|
||||
|
||||
/****************************************************************************
|
||||
@@ -196,15 +197,16 @@ bool sched_mergepending(void)
|
||||
FAR struct tcb_s *tcb;
|
||||
bool ret = false;
|
||||
int cpu;
|
||||
int me;
|
||||
|
||||
/* Remove and process every TCB in the g_pendingtasks list.
|
||||
*
|
||||
* This function is only called in the context where locking is known to
|
||||
* disabled on one CPU. However, we must do nothing if pre-emption is
|
||||
* still locked because of actions of other CPUs.
|
||||
* Do nothing if (1) pre-emption is still disabled (by any CPU), or (2) if
|
||||
* some CPU other than this one is in a critical section.
|
||||
*/
|
||||
|
||||
if (!spin_islocked(&g_cpu_schedlock))
|
||||
me = this_cpu();
|
||||
if (!spin_islocked(&g_cpu_schedlock) && !irq_cpu_locked(me))
|
||||
{
|
||||
/* Find the CPU that is executing the lowest priority task */
|
||||
|
||||
@@ -243,7 +245,7 @@ bool sched_mergepending(void)
|
||||
* Check if that happened.
|
||||
*/
|
||||
|
||||
if (spin_islocked(&g_cpu_schedlock))
|
||||
if (spin_islocked(&g_cpu_schedlock) || irq_cpu_locked(me))
|
||||
{
|
||||
/* Yes.. then we may have incorrectly placed some TCBs in the
|
||||
* g_readytorun list (unlikely, but possible). We will have to
|
||||
|
||||
@@ -165,7 +165,7 @@ bool sched_removereadytorun(FAR struct tcb_s *rtcb)
|
||||
if (rtcb->blink == NULL && TLIST_ISRUNNABLE(rtcb->task_state))
|
||||
{
|
||||
FAR struct tcb_s *nxttcb;
|
||||
FAR struct tcb_s *rtrtcb;
|
||||
FAR struct tcb_s *rtrtcb = NULL;
|
||||
int me;
|
||||
|
||||
/* There must always be at least one task in the list (the IDLE task)
|
||||
@@ -198,14 +198,21 @@ bool sched_removereadytorun(FAR struct tcb_s *rtcb)
|
||||
* g_readytorun list. We can only select a task from that list if
|
||||
* the affinity mask includes the current CPU.
|
||||
*
|
||||
* REVISIT: What should we do, if anything, if pre-emption is locked
|
||||
* by the another CPU? Should just used nxttcb? Should we select
|
||||
* from the pending task list instead of the g_readytorun list?
|
||||
* If pre-emption is locked or another CPU is in a critical section,
|
||||
* then use the 'nxttcb' which will probably be the IDLE thread.
|
||||
* REVISIT: What if it is not the IDLE thread?
|
||||
*/
|
||||
|
||||
for (rtrtcb = (FAR struct tcb_s *)g_readytorun.head;
|
||||
rtrtcb != NULL && !CPU_ISSET(cpu, &rtrtcb->affinity);
|
||||
rtrtcb = (FAR struct tcb_s *)rtrtcb->flink);
|
||||
if (!spin_islocked(&g_cpu_schedlock) && !irq_cpu_locked(me))
|
||||
{
|
||||
/* Search for the highest priority task that can run on this
|
||||
* CPU.
|
||||
*/
|
||||
|
||||
for (rtrtcb = (FAR struct tcb_s *)g_readytorun.head;
|
||||
rtrtcb != NULL && !CPU_ISSET(cpu, &rtrtcb->affinity);
|
||||
rtrtcb = (FAR struct tcb_s *)rtrtcb->flink);
|
||||
}
|
||||
|
||||
/* Did we find a task in the g_readytorun list? Which task should
|
||||
* we use? We decide strictly by the priority of the two tasks:
|
||||
|
||||
@@ -52,6 +52,64 @@
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sched_nexttcb
|
||||
*
|
||||
* Description:
|
||||
* Get the next highest priority ready-to-run task.
|
||||
*
|
||||
* Inputs:
|
||||
* tcb - the TCB of task to reprioritize.
|
||||
*
|
||||
* Return Value:
|
||||
* TCB of the next highest priority ready-to-run task.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static FAR struct tcb_s *sched_nexttcb(FAR struct tcb_s *tcb)
|
||||
{
|
||||
FAR struct tcb_s *nxttcb = (FAR struct tcb_s *)tcb->flink;
|
||||
FAR struct tcb_s *rtrtcb;
|
||||
int cpu = this_cpu();
|
||||
|
||||
/* Which task should run next? It will be either the next tcb in the
|
||||
* assigned task list (nxttcb) or a TCB in the g_readytorun list. We can
|
||||
* only select a task from that list if the affinity mask includes the
|
||||
* current CPU.
|
||||
*
|
||||
* If pre-emption is locked or another CPU is in a critical section,
|
||||
* then use the 'nxttcb' which will probably be the IDLE thread.
|
||||
*/
|
||||
|
||||
if (!spin_islocked(&g_cpu_schedlock) && !irq_cpu_locked(cpu))
|
||||
{
|
||||
/* Search for the highest priority task that can run on this CPU. */
|
||||
|
||||
for (rtrtcb = (FAR struct tcb_s *)g_readytorun.head;
|
||||
rtrtcb != NULL && !CPU_ISSET(cpu, &rtrtcb->affinity);
|
||||
rtrtcb = (FAR struct tcb_s *)rtrtcb->flink);
|
||||
|
||||
/* Return the TCB from the readyt-to-run list if it is the next
|
||||
* highest priority task.
|
||||
*/
|
||||
|
||||
if (rtrtcb != NULL &&
|
||||
rtrtcb->sched_priority >= nxttcb->sched_priority)
|
||||
{
|
||||
return rtrtcb;
|
||||
}
|
||||
}
|
||||
|
||||
/* Otherwise, return the next TCB in the g_assignedtasks[] list...
|
||||
* probably the TCB of the IDLE thread.
|
||||
* REVISIT: What if it is not the IDLE thread?
|
||||
*/
|
||||
|
||||
return nxttcb;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sched_running_setpriority
|
||||
*
|
||||
@@ -77,12 +135,24 @@
|
||||
static inline void sched_running_setpriority(FAR struct tcb_s *tcb,
|
||||
int sched_priority)
|
||||
{
|
||||
FAR struct tcb_s *nxttcb;
|
||||
|
||||
/* Get the TCB of the next highest priority, ready to run task */
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
nxttcb = sched_nexttcb(tcb);
|
||||
#else
|
||||
nxttcb = (FAR struct tcb_s *)tcb->flink;
|
||||
#endif
|
||||
|
||||
DEBUGASSERT(nxttcb != NULL);
|
||||
|
||||
/* A context switch will occur if the new priority of the running
|
||||
* task becomes less than OR EQUAL TO the next highest priority
|
||||
* ready to run task.
|
||||
*/
|
||||
|
||||
if (sched_priority <= tcb->flink->sched_priority)
|
||||
if (sched_priority <= nxttcb->sched_priority)
|
||||
{
|
||||
/* A context switch will occur. */
|
||||
|
||||
|
||||
@@ -44,6 +44,7 @@
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/sched_note.h>
|
||||
|
||||
#include "irq/irq.h"
|
||||
#include "sched/sched.h"
|
||||
|
||||
/****************************************************************************
|
||||
@@ -66,6 +67,10 @@
|
||||
int sched_unlock(void)
|
||||
{
|
||||
FAR struct tcb_s *rtcb = this_task();
|
||||
int cpu;
|
||||
|
||||
cpu = this_cpu();
|
||||
rtcb = current_task(cpu);
|
||||
|
||||
/* Check for some special cases: (1) rtcb may be NULL only during
|
||||
* early boot-up phases, and (2) sched_unlock() should have no
|
||||
@@ -102,29 +107,54 @@ int sched_unlock(void)
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
/* The lockcount has decremented to zero and we need to perform
|
||||
* release our hold on the lock. Pre-emption may still be locked
|
||||
* from other CPUs.
|
||||
* release our hold on the lock.
|
||||
*/
|
||||
|
||||
DEBUGASSERT(g_cpu_schedlock == SP_LOCKED &&
|
||||
(g_cpu_lockset & (1 << this_cpu())) != 0);
|
||||
(g_cpu_lockset & (1 << cpu)) != 0);
|
||||
|
||||
spin_clrbit(&g_cpu_lockset, this_cpu(), &g_cpu_locksetlock,
|
||||
spin_clrbit(&g_cpu_lockset, cpu, &g_cpu_locksetlock,
|
||||
&g_cpu_schedlock);
|
||||
#endif
|
||||
|
||||
/* Release any ready-to-run tasks that have collected in
|
||||
* g_pendingtasks. In the SMP case, the scheduler remains
|
||||
* locked if interrupts are disabled.
|
||||
* g_pendingtasks.
|
||||
*
|
||||
* NOTE: This operation has a very high likelihood of causing
|
||||
* this task to be switched out!
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
/* In the SMP case, the tasks remains pend(1) if we are
|
||||
* in a critical section, i.e., g_cpu_irqlock is locked by other
|
||||
* CPUs, or (2) other CPUs still have pre-emption disabled, i.e.,
|
||||
* g_cpu_schedlock is locked. In those cases, the release of the
|
||||
* pending tasks must be deferred until those conditions are met.
|
||||
*
|
||||
* NOTE: In SMP mode, pre-emption may still be locked due to
|
||||
* operations on other CPUs.
|
||||
* There are certain conditions that we must avoid by preventing
|
||||
* releasing the pending tasks while within the critical section
|
||||
* of other CPUs. This logic does that and there is matching
|
||||
* logic in sched_addreadytorun to avoid starting new tasks within
|
||||
* the critical section (unless the CPU is the holder of the lock).
|
||||
*
|
||||
* REVISIT: If this CPU is only one that holds the IRQ lock, then
|
||||
* we should go ahead and release the pending tasks. See the logic
|
||||
* leave_critical_section(): It will call up_release_pending()
|
||||
* BEFORE it clears IRQ lock.
|
||||
* BEFORE it clears IRQ lock.
|
||||
*/
|
||||
|
||||
if (!spin_islocked(&g_cpu_schedlock) && !irq_cpu_locked(cpu) &&
|
||||
g_pendingtasks.head != NULL)
|
||||
#else
|
||||
/* In the single CPU case, decrementing irqcount to zero is
|
||||
* sufficient to release the pending tasks. Further, in that
|
||||
* configuration, critical sections and pre-emption can operate
|
||||
* fully independently.
|
||||
*/
|
||||
|
||||
if (g_pendingtasks.head != NULL)
|
||||
#endif
|
||||
{
|
||||
up_release_pending();
|
||||
}
|
||||
|
||||
@@ -390,7 +390,7 @@ void spin_unlockr(FAR struct spinlock_s *lock)
|
||||
* Input Parameters:
|
||||
* set - A reference to the bitset to set the CPU bit in
|
||||
* cpu - The bit number to be set
|
||||
* setlock - A reference to the lock lock protecting the set
|
||||
* setlock - A reference to the lock protecting the set
|
||||
* orlock - Will be set to SP_LOCKED while holding setlock
|
||||
*
|
||||
* Returned Value:
|
||||
@@ -441,7 +441,7 @@ void spin_setbit(FAR volatile cpu_set_t *set, unsigned int cpu,
|
||||
* Input Parameters:
|
||||
* set - A reference to the bitset to set the CPU bit in
|
||||
* cpu - The bit number to be set
|
||||
* setlock - A reference to the lock lock protecting the set
|
||||
* setlock - A reference to the lock protecting the set
|
||||
* orlock - Will be set to SP_UNLOCKED if all bits become cleared in set
|
||||
*
|
||||
* Returned Value:
|
||||
|
||||
Reference in New Issue
Block a user