diff --git a/ChangeLog b/ChangeLog index 4c5c42b1341..3653cd3ec47 100755 --- a/ChangeLog +++ b/ChangeLog @@ -3130,7 +3130,7 @@ point numbers. * lib/stdio/lib_libdtoa.c and lib_libvsprintf.c: Correct some floating point options. - * arch/arm/lpc43xx/lpc32_usb0dev.c: Add framework for development of + * arch/arm/lpc43xx/lpc43_usb0dev.c: Add framework for development of an USB0, device-side driver for the LPC43XX. The initial check-in, however, is simply for the LPC31xx driver with name changes. The LPC31xx has the same USB IP, but will require some additional initialization @@ -4440,7 +4440,7 @@ * binfmt/binfmt_execmodule.c: Here is a place where I forget to update the call to sched_releasetcb() to pass the thread type as the second parameter (2013-03-23). - * arch/arm/src/lm, kinetis, lpc32, and nuc1xx: Add kernel build + * arch/arm/src/lm, kinetis, lpc43, and nuc1xx: Add kernel build support to all ARMv7-M and ARMv6-M chips. There are no configurations in place to to verify these additions! (2013-03-24). @@ -10964,7 +10964,7 @@ (2015-09-09). * configs/nucleo-f303re: Support for the STMicro Nucleo F303RE board from Paul Alexander Patience (2015-09-10). - * arch/arm/src/lpc43xx/lpc32_ehci.c and .h: LPC43xx EHCI driver from + * arch/arm/src/lpc43xx/lpc43_ehci.c and .h: LPC43xx EHCI driver from Ilya Averyanov (2015-09-10). * ARMv7-M, all "lazy" interrupt stack logic. Assembly instruction that fetches the saved value is incorrect; replace with more @@ -12348,7 +12348,7 @@ adds DEBUGASSERT for invalid geometry and additional memory debug logic. Also fixes the dangling pointer on error bug. From Ken Pettit (2016-07-14). - * arch/arm/src/lpc32xx: Extend LPC43xx EMC code to support SDRAM on a + * arch/arm/src/lpc43xx: Extend LPC43xx EMC code to support SDRAM on a dynamic memory interface. From Vytautas Lukenskas (2016-07-19). * arch/sim/src: Add the simulated QSPI (N25Q) flash to the simulation and modify sim up_spiflash.c to enable it to run with different MTD @@ -12772,6 +12772,9 @@ * STM32 DMA2D: fix an error in up_dma2dcreatelayer where an invalid pointer was returned when a certain underlying function failed. From Jens Gräf (2016-10-07). + +7.19 2016-12-26 Gregory Nutt + * include/nuttx/fs/nxffs.h: Needs forward reference to struct mtd_dev_s and needs to include stdbool.h (2016-10-09). * STM32F103 Minimum: Note in Kconfig that the board supports buttons. @@ -12844,16 +12847,16 @@ (2016-10-19). * libc/locale: Allows c++ code to compile with or without CONFIG_LIBC_LOCALE and will generate a link error if CONFIG_LIBC_LOCALE - is not defined and setlocale is referneced. With CONFIG_LIBC_LOCALE + is not defined and setlocale is referenced. With CONFIG_LIBC_LOCALE defined setlocale will act as if MB string is not supported and return "C" for POSIX. C and "". From David Sidrane (2016-10-19). - * Add vectors for interrupt levels 2-6 (2016-10-20). - * strtof: Add strtof() as simply a copy of strtod with types and + * Xtensa ESP32: Add vectors for interrupt levels 2-6 (2016-10-20). + * strtof(): Add strtof() as simply a copy of strtod with types and limits changed (2016-10-20). * arch/arm/src/stm32v7: Register the watchdog device at the configured device path CONFIG_WATCHDOG_DEVPATH vs. hard-coded /dev/wdt. From Frank Benkert (2016-10-21). - * configs/*/defdonf The buttons example was changed to archbuttons. As + * configs/*/defconfig: The buttons example was changed to archbuttons. As a result all of the button configurations are broken and need some renaming in the defconfig files. Noted by Frank Berkert (2016-10-21). * configs/stm32f103-minimum: Add support to PWM on STM32F103-Minimum @@ -12909,7 +12912,7 @@ found in the F4. From David Sidrane (2016-10-26). * arch/arm/src/stm32f7: stm32f76xx77xx_pinmap.h Missed one. From David Sidrane (2016-10-26). - * LPC32xx serial: Fix a typo in ioctl TIOCSRS485 ioctl. From Vytautas + * LPC43xx serial: Fix a typo in ioctl TIOCSRS485 ioctl. From Vytautas Lukenskas (2016-10-27). * sched/clock: Correct clock initialization. The correct range for the month is 0-11 but is entered as 1-12 in the .config file @@ -12919,7 +12922,7 @@ * sched/Kconfig: Add ranges to START_YEAR, MONTH, and DAY (2016-10-28). * configs/nucleo-f303re: Add STM32 F303RE hello configuration; remove duplicate setting from board.h. From Marc Rechté (2016-10-18). - * arch/arm/src/lpc32xx: Restore RS485 mode on serial port open (if + * arch/arm/src/lpc43xx: Restore RS485 mode on serial port open (if RS485 is enabled via menuconfig). From Vytautas Lukenskas (2016-10-28). * arch/arm/src/stm32f7: otgdev fixed typo. From David Sidrane (2016-10-28). @@ -12949,14 +12952,12 @@ From Paul A. Patience (2016-11-02). * drivers/ and drivers/spi: Fix Kconfig warning. This commit moves the ARCH_HAVE_SPI options outside the check for SPI. Those options don't - depend on SPI, and Kconfig files in arch/ enable them even if SPI isn't - enabled. - - Sourcing the driver's Kconfig in drivers/Kconfig only if support for - the driver is enabled prevents us from defining these ARCH_HAVE options - in the driver's Kconfig. We should probably remove the other checks in - drivers/Kconfig and check if the drivers are enabled only in their - Kconfig. From Paul A. Patience (2016-11-02). + depend on SPI, and Kconfig files in arch/ enable them even if SPI + isn't enabled. Source the driver's Kconfig in drivers/Kconfig only + if support for the driver is enabled prevents us from defining these + ARCH_HAVE options in the driver's Kconfig. We should probably remove + the other checks in drivers/Kconfig and check if the drivers are + enabled only in their Kconfig. From Paul A. Patience (2016-11-02). * Move protoypes for the non-standard include/semaphore.h file to the non-standard include/nuttx/semaphore.h with the other non-standard semaphore interfaces (2016-11-02). @@ -13100,7 +13101,7 @@ argument so that there can be additional usage. From Sebastien Lorquet (2016-11-17). * All timer lower half drivers. Port Sebastien's changes to all all - other implementations of the timer lower half. Very many just and + other implementations of the timer lower half. Many changes and untested. Expect some problems. (2016-11-17). * sched/irq: irq_csection() has a bad assumption in the SMP case. It assumed that the state of certain variables. That was true on entry @@ -13236,7 +13237,7 @@ and execute "make" it will not detect that Pin.cxx was modified. I think there is some other place I should modify, but I didn't find it. From Alan Carvalho de Assis (2016-11-27). - * ARMv7-A/i.MX6 SMP: Move SMP coherernt cache setup to earlier in + * ARMv7-A/i.MX6 SMP: Move SMP coherent cache setup to earlier in initialization of CPUn, n>0 (2016-11-27). * ARMv7 GIC: SGIs are non-maskable but go through the same path as other, maskable interrupts. Added logic to serialize SGI processing when @@ -13356,5 +13357,122 @@ * Add task_setcancelstate(), task_setcanceltype(), and task_testcancel(). These are non-standard interfaces analogous to the correponding pthread_ interfaces that provide cancellation controls for tasks (2016-12-10). + * i.MX6 interrupt handling: Additional logic needed to handle nested + interrupts when an interrupt stack is used (2016-12-13). + * SAMV7 MCAN: Prevent Interrupt-Flooding of ACKE when not connected to + CAN-BUS. An Acknowledge-Error will occur every time no other CAN Node + acknowledges the message sent. This will also occur if the device is + not connected to the can-bus. The CAN-Standard declares, that the Chip + has to retry a given message as long as it is not sent successfully (or + it is not cancelled by the application). Every time the chip tries to + resend the message an Acknowledge-Error-Interrupt is generated. At high + baud rates this can lead in extremely high CPU load just for handling + the interrupts (and possibly the error handling in the application). To + prevent this Interrupt-Flooding we disable the ACKE once it is seen as + long we didn't transfer at least one message successfully. From Frank + Benkert (2016-12-13). + * i.MX6: Remove non-cached, inter-cpu memory region. Not a useful + concept (2016-12-13). + * minnsh Configurations: Remove minnsh configurations and support logic: + up_getc() and lowinstream. This was an interesting exercise to see + just how small you could get NuttX, but otherwise it was not useful: + (1) the NSH code violated the OS interface layer by callup up_getc and + up_putc directly, and (2) while waiting for character input, NSH would + call up_getc() which would hog all of the CPU. Not a reasonable + solution other than as a proof of concept (2016-12-13). + * Calypso Boards: Remove all Calypso board configurations (2016-12-13). + * Calypso: Remove Calypso architecture support and support for Calypso + SERCOMM driver (2016-12-13). + * ESP32 core v2: Two changes (1) flushes the UART TX buffer in the esp32 + serial shutdown routine. The ROM bootloader does not flush the FIFO + before handing over to user code, so some of this output is not + currently seen when the UART is reconfigured in early stages of + startup. And changes the openocd config file's default flash voltage + from 1.8V to 3.3V. This is not necessary right now, but may save some + hard-to-debug moments down the track (3.3V-only flash running at 1.8V + often half-works and does weird things...). From Angus Gratton + (2016-12-14). + * Xtensa ESP32: Add missing ENTRY() and RET() macros in C callable + assembly language. At one time I though the that the ESP32 support the + CALL0 ABI. I was mistaken so there may be a few more like this + (2016-12-14). + * Xtensa ESP32: Fix a couple of bugs associated with handling of CPU + interrupts (2016-12-14). + * Xtensa ESP32: Fix several build-related issues associated with vector + section (2016-12-15). + * Xtensa ESP32: Fix missing CALL0 ABI condition (2016-12-15). + * Xtensa EPS32: Make sure that all C callable assembly functions includes + ENTRY prologue and RET epilogue (2016-12-15). + * Xtensa ESP32: Fix windowspill register handling + Use r6, not r2 when + passing paramters with call4 (2016-12-16). + * Xtensa ESP32: Use r6, not r2 when passing paramters with call4 + (2016-12-16). + * Xtensa ESP32: Correct a logic problem the prevented dumping the IDLE + thread's stack on an assertion (2016-12-16). + * Xtensa ESP32: Fix some missing SMP logic (2016-12-16). + * Xtensa ESP32: Basically a redesign of the interrupt dispatch logic + (2016-12-16). + * Xtensa ESP32: Level 1 interrupts should return via RFE (2016-12-17). + * Xtensa ESP32: One register getting clobber on context save (2016-12-17). + * STM32 F7: Fix some STM32F7 copy paste errors. From David Sidrane + (2016-12-17). + * CDC/ACM Device Class: uart_ops_s portion of cdcacm will not be + initalized with correct functions if CONFIG_SERIAL_DMA is lit + (2016-12-17). + * Xtensa ESP32: Using wrong register to disable interrupts (2016-12-17). + * Xtensa ESP32: Fix clobbered a9 in co-processor context save/restore + (2016-12-17). + * Xtensa ESP32: Need to clone some logic for synchronous context switch. + Window spill logic in the conmon restores logic is inappropriate in + this context (2016-12-17). + * sscanf(): Add scansets to the scanf function. Enabled + CONFIG_LIBC_SCANSET option. From Aleksandr Vyhovanec (2016-12-17). + * Xtensa ESP32: Fix context save logic when called in window ABI + configuration. Add an IDLE stack. Don't depend on the mystery stack + received from the bootloader (2016-12-18). + * Xtensa ESP32: Need to spill registers to memory as the last dying + action before switching to a new thread (2016-12-18). + * ESP32 Serial: Add logic to prevent infinite loops in interrupt handler + (2016-12-18). + * Xtensa ESP32: Automatically mount /proc at start-up (2016-12-19). + * Xtensa ESP32: Corrects timer initialization and timer input frequency + (2016-12-19). + * Tiva PWM: Support PWM_PULSECOUNT feature for TI tiva. From Young.Mu + (2016-12-20). + * Xtensa ESP32: Missing prologue/epilogue macros on C callable function + (2016-12-20). + * Xtensa ESP32: Update APP CPU startup logic to match current Expressif + example code. Fix errors APP CPU startup (2016-12-20). + * fs/procfs: Fix procfs status for SMP case (2016-12-20). + * Xtensa ESP32: Clock frequency is different if running from IRAM or is + booting from FLASH. This is a booltloader issue (2016-12-20). + * Xtensa ESP32: Basic port is function in both single CPU and dual CPU + SMP configurations. There is an NSH configuration for each CPU + configuration (2016-12-21). + * STM32 F4: Merge in support for the Olimex STM32 P407 board (2016-12-21). + * Xtensa ESP32: Add an OS test to verify the port (2016-12-22). + * Xtensa ESP32: Corrects a problem with dispatching to signal handlers: + Cannot vector directly to the signal handling function as in other ABIs + under the Xtensa Window ABI. In that case, we need to go through a + tiny hook when performs the correct window call (call4) otherwise + registers will be scrambled in the signal handler (2016-12-22). + * SAMV7 CAN: Make delete_filter functions more robust. From Frank + Benkert (2016-12-23). + * Xtensa ESP32: Add stack checking logic (2016-12-23). + * sched note: record ID enumeration now results on constant values; ID + values do not change with configuration. This makes writing + post-processing software much easier (2016-12-24). + * STM32 F3: Forgot to update chip.h for STM32F303x[BC]'s 4 ADCs + (2016-12-24). + * STM32 F4: Allow dma in 1 bit mode in STM32F4xxx. From David Sidrane + (2016-12-24). + * termios.h: Fix CRTSCTS define to include input and output flow. + From Lorenz Meier (2016-12-26). + * SMP: Enforce this rule: Tasks which are normally restored when + sched_unlock() is called must remain pending (1) if we are in a + critical section, i.e., g_cpu_irqlock is locked , or (2) other CPUs + still have pre-emption disabled, i.e., g_cpu_schedlock is locked. In + those cases, the release of the pending tasks must be deferred until + those conditions are met (2016-12-26). -7.19 2016-xx-xx Gregory Nutt +7.20 2017-xx-xx Gregory Nutt diff --git a/Documentation/NuttX.html b/Documentation/NuttX.html index ca35c859ed6..decdfae6349 100644 --- a/Documentation/NuttX.html +++ b/Documentation/NuttX.html @@ -8,7 +8,7 @@

NuttX RTOS

-

Last Updated: October 8, 2016

+

Last Updated: December 26, 2016

@@ -317,7 +317,7 @@

-

  • POSIX/ANSI-like task controls, named message queues, counting semaphores, clocks/timers, signals, pthreads, environment variables, filesystem.
    • +
  • POSIX/ANSI-like task controls, named message queues, counting semaphores, clocks/timers, signals, pthreads, cancellation points, environment variables, filesystem.

    • @@ -1339,11 +1339,11 @@

    Released Versions

    In addition to the ever-changing GIT repository, there are frozen released versions of NuttX available. - The current release is NuttX 7.18. - NuttX 7.18 is the 118th release of NuttX. - It was released on October 8, 2016, and is available for download from the + The current release is NuttX 7.19. + NuttX 7.19 is the 119th release of NuttX. + It was released on December 26, 2016, and is available for download from the Bitbucket.org website. - Note that the release consists of two tarballs: nuttx-7.18.tar.gz and apps-7.18.tar.gz. + Note that the release consists of two tarballs: nuttx-7.19.tar.gz and apps-7.19.tar.gz. Both may be needed (see the top-level nuttx/README.txt file for build information).

    @@ -1352,7 +1352,7 @@
    • nuttx.

        - Release notes for NuttX 7.18 are available here. + Release notes for NuttX 7.19 are available here. Release notes for all released versions on NuttX are available in the Bitbucket GIT. The ChangeLog for all releases of NuttX is available in the ChangeLog file that can viewed in the Bitbucket GIT. The ChangeLog for the current release is at the bottom of that file. @@ -1360,7 +1360,7 @@

    • apps.
    • Atmel AVR @@ -1445,6 +1445,10 @@
    • PIC32MZ (MIPS M14K) (1)
    +
  • Misoc +
  • Renesas/Hitachi:
    • Renesas/Hitachi SuperH (1/2)
      • @@ -1453,6 +1457,15 @@ +
    • RISC-V (1) +
        +
      +
      • +
    • Xtensa LX6: + +
    • ZiLOG
      • +
    • Expressif +
        +
      • ESP32 (Dual Xtensa LX6) +
      +
    • Freescale
      • - -
    • Moxa
      • + +
    • nuvoTon
      • nuvoTon NUC120 (ARM Cortex-M0)
        • @@ -3134,7 +3152,7 @@ nsh>

      • Kamami STM32 Butterfly 2 - Support for the Kamami STM32 Butterfly 2 was contributed by Michał Łyszczek in NuttX-7/18. That port features the STMicro STM32F107VC MCU. + Support for the Kamami STM32 Butterfly 2 was contributed by Michał Łyszczek in NuttX-7.18. That port features the STMicro STM32F107VC MCU.

        STATUS: @@ -3717,11 +3735,14 @@ nsh>

      • NuttX-7.3 Support for the Olimex STM32 H405 board was added in NuttX-7.3.
        • -
      • - Refer to the NuttX board README file for further information. +
      • NuttX-7.19 + Support for the Olimex STM32 P405 board was added in NuttX-7.19.

      +

      + Refer to the STM3240G-EVAL board README file for further information. +

      STMicro STM32F4-Discovery. This port uses the STMicro STM32F4-Discovery board featuring the STM32F407VGT6 MCU. @@ -3791,6 +3812,11 @@ nsh> Networking configurations were added in NuttX-7.18. See the NuttX board README file for further information about the NuttX port.

      +

      + Olimex STM32 P407. + Support for the Olimex STM32 P407 development board appeared in NuttX-7.19. + See the NuttX board README file for further information about the NuttX port. +

      @@ -4306,7 +4332,7 @@ Mem: 29232 5920 23312 23312

      - Atmel SAM4C. + Atmel SAM4CM. General architectural support was provided for SAM4CM family in NuttX 7.3 This was architecture-only support, meaning that support for the boards with these chips is available, but no support for any publicly available boards was included. The SAM4CM port should be compatible with most of the SAM3/4 drivers (like HSMCI, DMAC, etc.) but those have not be verified on hardware as of this writing. @@ -4314,6 +4340,18 @@ Mem: 29232 5920 23312 23312

      + +
      + +

      + Atmel SAM4CMP-DB. + Support for the SAM4CMP-DB board was contributed to NuttX by Masayuki Ishikawa in NuttX-7.19. + The SAM4CM is a dual-CPU part and SMP was included for the ARMv7-M and SAM3/4 families. + The SAM4CMP-DB board support includes an NSH configuration that operates in an SMP configuration. + Refer to the NuttX board README file for further information. +

      + +
      @@ -4830,6 +4868,23 @@ Mem: 29232 5920 23312 23312
    + + + + + Misoc LM32. + + + +
    + +

    + Misoc LM32 Architectural Support. + Architectural support for the Misoc LM32 was contributed by Ramtin Amin in NuttX 7.19. Driver support is basic in this initial release: Serial, Timer, and Ethernet. "Board" support is a available for developing with Misoc LM32 under Qemu or on your custom FPGA. +

    + + + @@ -5196,6 +5251,53 @@ BFD_ASSERT (*plt_offset != (bfd_vma) -1); + + + + + + RISC-V. + + + +
    + +

    + RISC-V Architectural Support. + Basic support for the RISC-V architecture was contributed by Ken Pettit in NuttX-7.19. The initial release is thin but a great starting point for anyone interested in RISC-V development with NuttX. +

    + + + + + + + ESP32 (Dual Xtensa LX6). + + + +
    + +

    + Xtensa LX6 ESP32 Architectural Support. + Basic architectural support for Xtensa LX6 processors and the port for the Expressif ESP32 were added in NuttX-7.19. + The basic ESP32 port is function in both single CPU and dual CPU SMP configurations. +

    +

    + Expressif ESP32 Core v2 Board + The NuttX release includes support for Expressif ESP32 Core v2 board. + There is an NSH configuration for each CPU configuration and an OS test configuration for verificatin of the port. +

    +

    + STATUS. + ESP32 support in NuttX-7.19 is functional, but very preliminary. + There is little yet in the way of device driver support. + Outstanding issues include missing clock configuration logic, missing partition tables to support correct configuration from FLASH, and some serial driver pin configuration issues. + The configuration is usable despite these limitations. + Refer to the NuttX board README file for further information. + + + diff --git a/ReleaseNotes b/ReleaseNotes index 18b20f8b148..e7d50a40532 100644 --- a/ReleaseNotes +++ b/ReleaseNotes @@ -12294,3 +12294,794 @@ detailed bugfix information): - apps/examples/oneshot: If the requested delay is > max_delay, then break the delay up into several pieces. + +NuttX-7.19 Release Notes +------------------------ + +The 119th release of NuttX, Version 7.19, was made on December 26, 2016, +and is available for download from the Bitbucket.org website. Note +that release consists of two tarballs: nuttx-7.19.tar.gz and +apps-7.19.tar.gz. These are available from: + + https://bitbucket.org/nuttx/nuttx/downloads + https://bitbucket.org/nuttx/apps/downloads + +Both may be needed (see the top-level nuttx/README.txt file for build +information). + +Additional new features and extended functionality: + + * Core OS: + + - sched/semaphore, sched/phread/, libc/semaphore, libc/pthread: Add + pthread_mutexattr_get/set_protocol and non-standard + sem_get/set_protocol. These may use to enable or disable priority + inheritance on a single semaphore. + - Spinlocks: Added capability to provide architecture-specific memory + barriers. + - SMP: Add spin_trylock(). Use this in conditions where other CPUs need + to stopped but we cannot call enter_critical_section(). + - sched note: Extend OS instrumentation to include some SMP events. + Also add spinlock instrumentation; In SMP configurations, add a + filter mask to log only notes from certain CPUs. + - sched note: Permit spinlock and critical section notes in in-memory + buffer iff sched_not_get() interfaces is disabled. + - sched note: Add additional note to see if/when CPU is started in SMP + mode. + - sched note: Record ID enumeration now results on constant values; ID + values do not change with configuration. This makes writing post-processing software much easier. + - boardctl: Add new boardctl() command, BOARDIOC_NX_START, to start the + NX server as a kernel thread. + - pthreads: Add pthread_cleanup_push() and pthread_cleanup_pop(). + - pthreads: Added pthread_setcanceltype() and pthread_testcancel(). + - pthreads: Add support for cancellation points. + - task_delete() now obeys all cancellation point semantics. + - Add task_setcancelstate(), task_setcanceltype(), and + task_testcancel(). These are non-standard interfaces analogous to the + correponding pthread_ interfaces that provide cancellation controls + for tasks. + + * Graphics/Display Drivers: + + - boardctl: Add new boardctl() command, BOARDIOC_NX_START, to start the + NX server as a kernel thread. + + * Networking/Network Drivers: + + - Network drivers: Add option to use low-priority work queue to all + Ethernet and MAC level drivers. + - Network Drivers: Adapt all Ethernet (and other MAC) drivers to work + as though CONFIG_NET_MULTIBUFFER were set. Remove all references to + CONFIG_NET_MULTIBUFFER. + - Eliminate CONFIG_NO_NOINTS. There is no longer any support for + interrupt level processing of the network stack. Lots of files changed. + + * Other Common Device Drivers: + + - Vishay VEML6070: Add Vishay VEML6070 driver. From Alan Carvalho de + Assis. + + * ARMv7-A + + - ARMv7-A/i.MX6: Add SCU register definitions. Add some controls to + enable SMP cache coherency in SMP mode. Makes no difference, however + -- cache still incoherent on i.MX6. + - ARMv7 GIC: SGIs are non-maskable but go through the same path as + other, maskable interrupts. Added logic to serialize SGI processing + when necessary. + + * Atmel SAM3/4: + + - SAM3/4: Add SMP support for the dual-core SAM4CM. From Masayuki + Ishikawa. + + * Atmel SAM3/4 Drivers: + + - Add support for the SAM5CMP-DB board. From Masayuki Ishikawa. + + * Atmel SAM3/4 Boards: + + - SAM4CMP-DB: Add support for the Atmel SAM4CMP-DB board running in an + SMP configuration. From Masayuki Ishikawa. + - SAM4CMP-DB: Add hooks to auto-mount the procfs file system on startup + in board bring-up logic. + + * Atmel SAMV7 Drivers: + + - SAMv7: Register the watchdog device at the configured device path + CONFIG_WATCHDOG_DEVPATH vs. hard-coded /dev/wdt. From Frank Benkert. + + * Calypso + + - Calyps: Remove all Calypso board configurations. Remove Calypso + architecture support and support for Calypso SERCOMM driver. + + * Misoc LM32: + + - Misoc LM32: Adds basic support for the Misoc procoessors and the LM32 + in particular. From Ramtin Amin. + - Misoc LM32: Add signal handling logic. From Ramtin Amin. + - Misoc LM32: Add logic to flush/invalidate caches. From Ramtin Amin. + + * Misoc LM32 Drivers: + + - Misoc LM32 Serial: Add interrupting Misoc serial driver. From Ramtin + Amin. + - Misoc LM32 Timer: Add timer driver. From Ramtin Amin. + - Misoc LM32: Add Misoc Ethernet driver From Ramtin Amin. + + * Misoc LM32 Boards: + + - Misoc LM32 Qemu: Board support for testing Misoc LM32 with Qemu. From + Ramtin Amin. + - Misoc LM32 Qemu: Integrate network support into configs/misoc/hello. + From Ramtin Amin. + - Misoc LM32 Qemu: Remove configs/misoc/include/generated directory. I + suppose the the intent now is that this is a symbolic link? DANGER! + This means that you cannot compile this code with first generating + these files a providing a symbolic link to this location! There is a + sample directory containing generated sources. This is really only + useful for performing test builds. You really must generate the Misoc + architecture for a real-life build. From Ramtin Amin. + + * NXP Freescale i.MX6 Drivers: + + - i.MX6: Add an untested SPI driver taken directly from the i.MX1 port. + + * NXP Freescale Kinetis: + + - Kinetis: Added missing headers. Kinetis broke out SPI to + kinetis/kinetis_spi.h. Broke out DMA to use the modern Nuttx chip + inclusion - still STUBS. Add Kinetis support for ARMV7-M Common + Vector and FPU. Allow CONFIG_ARMV7M_CMNVECTOR, + CONFIG_STACK_COLORATION, CONFIG_ARCH_FPU. Fix i2c driver offset + swapped for value in kinetis_i2c_putreg. From David Sidrane. + + * NXP Freescale Kinetis Drivers: + + - Kinetis: Add UID Unique ID. From Neil Hancock. + + * NXP Freescale Kinetis Boards: + + - Freedom-K64F board: Add support for UID Unique ID. From Neil Hancock. + + * NXP Freescale LPC17xx Boards: + + - Olimex-LPC1766-STK: Enable procfs in NSH configuration. Automount + /proc on startup. + + * NXP Freescale LPC43xx Drivers: + + - LPC43xx: Add timer driver: From Alan Carvalho de Assis. + - LPC43xx GPDMA driver: The GPDMA block is basically the same as the + LPC17xx. Only the clock configuration is different and LPC43xx has + four different DMA request sources, where LPC17xx has only two. From + Alan Carvalho de Assis. + + * NXP Freescale LPC43xx Boards: + + - Bambino 200E: Add basic support to Micromint Bambino 200E board. + This includes contributions from Jim Wolfman. From Alan Carvalho de + Assis. + - Bambino 200E: Add support for timer driver. From Alan Carvalho de + Assis. + + * RGMP: + + - Remove RGMP and RGMP drivers. + + * RISC-V: + + - RISC-V: Add support for the RISC-V architecture and + configs/nr5m100-nexys4 board. The board support on this is pretty + thin, but it seems like maybe a good idea to get the base RISC-V stuff + in since there are people interested in it. From Ken Pettit. + + * STMicro STM32 Drivers: + + - STM32 F3: Implemention of the STM32 F37xx SDADC module. There are + also changes to ADC, DAC modules. SDADC has only been tested in DMA + mode and does not support external TIMER triggers. This is a work in + progress. From Marc Recht. + - STM32 F3: Add PWM driver support for STMF37xx. The changes have been + tested successfuly for TIM4 and TIM17 (different IPs). From Marc + Recht. + - STM32 F4: Support oversampling by 8 for the STM32 F4. From David + Sidrane. + - STM32 F4: Added Timers 2-5 and control of SAI and I2S PLLs. Added + support for stmf469 SAI and I2S PLL configuration and STM446 fixes. + From David Sidrane. + - STM32 F4: Expanded OTGFS support to stm32F469 and stm32f446. Added + missing bit definitions, Used stm32F469 and stm32f446 bit + definitions, Removed unsed header file. From David Sidrane. + - STM32 F4: Allow dma in 1 bit mode in STM32F4xxx. From David Sidrane. + - STM32 F7: Allow the config to override the clock edge setting. From + David Sidrane. + - STM32 L4: Support Complementary PWM outputs on STM32L4. From + Sebastien Lorquet. + - STM32 L4: Add implementation of dumpgpio for stm32l4, was required + for pwm debug. From Sebastien Lorquet. + + * STMicro STM32 Boards: + + - STM32F103 Minimum: Add button support. From Alan Carvalho de Assis. + - STM32F103 Minimum: Add support to PWM on STM32F103-Minimum board. + From Alan Carvalho de Assis. + - STM32F103 Minimum: Add RGB LED support on STM32F103 Minimum board. + From Alan Carvalho de Assis. + - STM32F103 Minimum: Add Vishay VEML6070 driver support to the + STM32F103-Minimum board. From Alan Carvalho de Assis. + - Nucleo-F303RE: Add STM32 F303RE hello configuration. From Marc + Recht. + - Nucleo-L476: Support PWM testing on board Nucleo L476. From + Sebastien Lorquet. + - Nucleo L476: Add support for timers to Nucleo L476. From Sebastien + Lorquet. + - Hymini STM32v: Enable CONFIG_RTC in the hymini-stm32v/nsh2 + (kitchensink) config. From Maciej Wjcik. + - Olimex STM32-p407: Add support for the Olimex STM32 P407 board. + + * TI Tiva Drivers: + + - Tiva PWM: Support PWM_PULSECOUNT feature for TI tiva. From Young.Mu. + + * Xtensa/ESP32 + + - Xtensa ESP32: Basic architectural support for Xtensa processors and + the Expressif. ESP32 added. + - Xtensa ESP32: Add EXPERIMENTAL hooks to support lazy Xtensa + co-processor state restore in the future. + - Xtensa ESP32: Basic port is function in both single CPU and dual CPU + SMP configurations. There is an NSH configuration for each CPU + configuration. Outstanding issues include missing clock configuration + logic, missing partition tables to support correct configuration from + FLASH, and some serial driver pin configuration issues. + - Xtensa ESP32: Add stack checking logic. + + * Xtensa/ESP32 Boards: + + - ESP32 Core v2: Basic support for Expressif ESP32 Core v2 board + added. The initial release includes an NSH and an SMP test + configuration. + - ESP32 Core v2: Add configuration to support linking NuttX for + execution out of IRAM. + - ESP32 Core v2: Automatically mount /proc at start-up. + - ESP32 Core v2: Add an OS test to verify the port. + + * C Library/Header Files: + + - libc/locale: Add a dummy setlocale() function to avoid drawing the + function from newlib. Add clocale header file. + - include/locale.h: Modify locale.h to add localeconv() and lconv + structure. From Alan Carvalho de Assis. + - libc/locale: Allows c++ code to compile with or without + CONFIG_LIBC_LOCALE and will generate a link error if + CONFIG_LIBC_LOCALE is not defined and setlocale is referenced. With + CONFIG_LIBC_LOCALE defined setlocale will act as if MB string is not + supported and return "C" for POSIX. C and "". From David Sidrane. + - libc/wchar: Add wcslen, wmemchr, wmemcmp, wmemcpy wmemset, btowc, + mbrtowc, mbtowc, wcscmp, wcscoll, and wmemmove to NuttX. From Alan + Carvalho de Assis. + - libc/wctype: Add functions wcrtomb, wcslcpy, wcsxfrm, wctob, wctomb, + wctype, localeconv, strcoll, strxfrm, swctype, towlower, towupper and + wcsftime. Add wctype.h; Move lib_wctype.c to libc/wctype. From Alan + Carvalho de Assis. + - include/ctype.h : Add isblank() macro to ctype.h. From Alan Carvalho + de Assis. + - lic/stdlib: Add strtof() and strtold() as simply a copy of strtod + with types and limits changed. + - sscanf(): Use strtof() instead of strtod() if a short floating point + value was requested. The should help performance with MCUs with + 32-bit FPU support with some additional code size. + - sscanf(): Add scansets to the scanf function. Enabled + CONFIG_LIBC_SCANSET option. From Aleksandr Vyhovanec. + - include/inttypes.h: Add architecture-specific inttypes.h. From Paul + A. Patience. + - C Library: Allow option to enable IP address conversions even when + the IP address family is not supported. + + * Build/Configuration System: + + - The Smoothie project needs to compile C++ inside config/boardname/src/ + to use with High Priority Interruption, then I modified the board + configs Makefile to support it. It works fine for the first time + compilation, but if we execute "touch config/boardname/src/Pin.cxx" + and execute "make" it will not detect that Pin.cxx was modified. I + think there is some other place I should modify, but I didn't find + it. From Alan Carvalho de Assis. + + * Tools: + + - tools/: Add tools/showsize.sh. + + * NSH: apps/nshlib: + + - NSH: dd command will show statistics. From Masayuki Ishikawa. + + * Applications: apps/system: + + - apps/system/sched_note: Extend to include additions to instumentation + for SMP. + - apps/system/sched_note: Add support for spinlock notes. + - apps/system/sched_note: Add support for new scheduler instrumentation. + + * Platforms: apps/platform: + + - ESP32 Core v2: Add platform support for the ESP32 core v2 board. + - Olimex STM32-p407: Add platform support for the Olimex STM32 P407. + + * Graphics: apps/graphics + + - graphics/traveler/tcledit and libwld: Add an X11 Tcl/Tk tool that can + be used to edit Traveler world files. + - Graphics: Remove all NX server taks. Instead, call boardctl() to the + NX server kernel thread. + + * Applications: apps/examples: + + - examples/buttons: Add a new buttons example that uses the button + character driver instead of the architecture buttons directly. From + Alan Carvalho de Assis. + - examples/cctype: Add an example to verify cctype functions. + - Remove RGMP example. + - examples/ostest: Extend the pthread cancellation test to exercise + pthread_cleanup_push() (and pthread_cleanup_pop() indirectly via + pthread_cancel() and pthread_exit(). + - examples/ostest: enhance pthread cancellation test some. + +Works-In-Progress: + + * IEEE802.14.5/6LowPAN. Hooks and framework for this effort were + introduced in NuttX-7.15. Work has continued on this effort on + forks from the main repositories, albeit with many interruptions. + The completion of this wireless feature will postponed until at + least NuttX-7.20. + +Bugfixes. Only the most critical bugfixes are listed here (see the +ChangeLog for the complete list of bugfixes and for additional, more +detailed bugfix information): + + * Core OS: + + - sched/semaphore: Within the OS, when a thread obtains a semaphore + count it must call sem_addholder() if CONFIG_PRIORITY_INHERITANCE is + enabled. If a count is available, then sem_wait() calls + sem_addholder(), otherwise it waited for the semaphore and called + sem_addholder() when it eventually received the count. This caused a + problem when the thread calling sem_wait() was very low priority. + When it received the count, there may be higher priority threads + "hogging" the CPU that prevent the lower priority task from running + and, as a result, the sem_addholder() may be delayed indefinitely. + The fix was to have sem_post() call sem_addholder() just before + restarting the thread waiting for the semaphore count. This problem + was noted by Benix Vincent who also suggested the solution. + - Many files: Make sure that priority inheritance is not enabled for + semaphores whose primary use is signaling (vs locking of resources) by + calling sem_setprotocol(). + - sched/semaphore: sem_trywait() no longer modifies the errno value + UNLESS an error occurs. This allows these functions to be used + internally without clobbering the errno value. From Freddie Chopin. + - sched/clock: Correct clock initialization. The correct range for the + month is 0-11 but is entered as 1-12 in the .config file. Add ranges + to START_YEAR, MONTH, and DAY in sched/Kconfig. + - sched/clock: Correct calculation for the case of Tickless mode with a + 32-bit timer. In that case, the calculation was returning millisecond + accuracy. That is not good when the timer accuracy is < 1 msec. From + Rajan Gill. + - Work Queue: When queuing new LP work, don't signal any threads if + they are all busy. From Heesub Shin. + - Work Queue: Signal sent from work_signal() may interrupt the low + priority worker thread that is already running. For example, the + worker thread that is waiting for a semaphore could be woken up by the + signal and break any synchronization assumption as a result. It also + does not make any sense to send signal if it is already running and + busy. This change fixes it. From Heesub Shin. + - Fix DEBUGASSERT() in group_signal.c. From Masayuki Ishikawa. + - Eliminate bad boardctl() commands: Remove all references to + BOARDIOC_PWMSETUP and board_pwm_setup(). Remove all references to + BOARDIOC_ADCSETUP and board_adc_setup(). Remove + BOARDIOC_CAN_INITIALIZE. CAN initialization is now done in the board + initialization logic just like every other device driver. + - pthreads: Fix an error in pthread_mutex_destroy(). An error could + occur while destroying a mutex after a pthread has been canceled while + holding the mutex. + - task_restart: Make sure new task starts with pre-emption disabled and + not in a critical section. + - Enter/leave Critical Sections. Major redeign to + enter/leave_critical_section logic to deal with the case where + interrupts are disabled only on the local CPU. In this case, some + rather complex spinlocks must be used to maintain the critical section + accross all CPUs. + - SMP Critical Sections: Fixes for the SMP case: (1) Change order for + SMP case in enter_critical_section: (1) Disable local interrupts + BEFORE taking spinlock and (2) If SMP is enabled, if any interrupt + handler calls enter_critical_section(), it should take the spinlock. + - SMP wdogs: Wdog timers use a tasking interface that to manipulate + wdogs, and a different interface in the timer interrupt handling logic + to manage wdog expirations. In the single CPU case, this is fine. + Since the tasking level code calls enter_critical_section, interrupts + are disabled and no conflicts can occur. But that may not be the case + in the SMP case. Most architectures do not permit disabling + interrupts on other CPUs so enter_critical_section must work + differently: Locks are required to protect code. this change adds + locking (via enter_critical section) to wdog expiration logic for the + the case if the SMP configuration. + - SMP vfork(): Fix a race condition in the SMP case. Existing logic + depended on the fact that the child would not run until waitpid was + called because the child had the same priority as the parent. BUT in + the SMP case that is not true... the child may run immediately on a + different CPU. + - SMP: This change adds a new internal interfaces and fixes a problem + with three APIs in the SMP configuration. The new internal interface + is sched_cpu_pause(tcb). This function will pause a CPU if the task + associated with 'tcb' is running on that CPU. This allows a different + CPU to modify that OS data stuctures associated with the CPU. When + the other CPU is resumed, those modifications can safely take place. + The three fixes are to handle cases in the SMP configuration where one + CPU does need to make modifications to TCB and data structures on a + task that could be running running on another CPU. Those three cases + are task_delete(), task_restart(), and execution of signal handlers. + In all three cases the solutions is basically the same: (1) Call + sched_cpu_pause(tcb) to pause the CPU on which the task is running, + (2) perform the necessary operations, then (3) call up_cpu_resume() to + restart the paused CPU. + - SMP: Add logic to avoid a deadlock condition when CPU1 is hung waiting + for g_cpu_irqlock with interrupts interrupts and CPU0 is waiting for + g_cpu_paused. + - SMP: Enforce this rule: Tasks which are normally restored when + sched_unlock() is called must remain pending (1) if we are in a + critical section, i.e., g_cpu_irqlock is locked , or (2) other CPUs + still have pre-emption disabled, i.e., g_cpu_schedlock is locked. In + those cases, the release of the pending tasks must be deferred until + those conditions are met. + + * File System/Block Drivers/MTD Drivers: + + - AT24XX EEPROM MTD driver: Added EEPROM timeout. Fromo Aleksandr + Vyhovanec. + - fs/procfs: Fix procfs status for SMP case. + + * Graphics/Graphic Drivers: + + - Fonts: Correct some default font IDs. From Pierre-Noel Bouteville. + + * Common Drivers: + + - usbhost/enumerate: Fix possible buffer overwrite. From Janne Rosberg. + - usbhost/composite: Fix compile; missing semicolons. From Jann Rosberg. + - syslog: Fixes required for file syslog output. From Max Kriegleder. + - SPI configuration: Fix Kconfig warning. This change moves the + ARCH_HAVE_SPI options outside the check for SPI. Those options don't + depend on SPI, and Kconfig files in arch/ enable them even if SPI + isn't enabled. Source the driver's Kconfig in drivers/Kconfig only + if support for the driver is enabled prevents us from defining these + ARCH_HAVE options in the driver's Kconfig. We should probably remove + the other checks in drivers/Kconfig and check if the drivers are + enabled only in their Kconfig. From Paul A. Patience. + - drivers/timer: Remove the timer driver TIOC_SETHANDLER IOCTL call. + This calls directly from the timer driver into application code. That + is non-standard, non-portable, and cannot be supported. Instead, add + timer driver hooks to support signal notification of timer + expiration. Signal notification logic added by Sebastien Lorquet. + - All timer lower half drivers. Port Sebastien's changes to all other + implementations of the timer lower half. + - USB MSC Device: Fix length of mode6 sense reply packet. From + Wolfgang Reinegger. + - USB Composite Host: Fix end offset in usbhost_copyinterface(). From + Janne Rosberg. + - USB CDC/ACM Host: Add CDC_SUBCLASS_ACM and CDC_PROTO_ATM to + supported class and proto. From Janne Rosberg. + - SSD1306: Fix errors in SPI mode configuration. From Gong Darcy. + - CDC/ACM Device Class: uart_ops_s portion of cdcacm will not be + initalized with correct functions if CONFIG_SERIAL_DMA is selected. + + * Networking/Network Drivers: + + - drivers/net/tun.c: Fix bug in TUN interface driver. From Max Nekludov. + + * ARMv7-A: + + - ARMv7-A SMP: Add SMP logic to signal handling. + + * ARMv7-M: + + - ARMv7-M: Fix double allocation of MPU region in mmu.h. + + * ARMv7-R: + + - ARMv7-R: Fix compilation error. This change fixes compilation errors + on MPU support for ARMv7-R. From Heesub Shin. + - ARMv7-R: fix invalid drbar handling. In ARMv7-R, [31:5] bits of DRBAR + is physical base address and other bits are reserved and SBZ. Thus, + there is no point in passing other than the base address. From Heesub + Shin. + - ARMv7-R: Remove the redundant update on SCTLR. mpu_control() is + invoking cp15_wrsctlr() around SCTLR update redundantly. From Heesub + Shin. + - ARMv7-R: add new Kconfig entries for d/i-cache. Unlike in ARMv7-A/M, + Kconfig entries for data and instruction caches are currently missing + in ARMv7-R. This change adds those missing Kconfig entries. Actual + implmenetation for those functions will be added in the subsequent + patches. From Heesub Shin. + - ARMv7-R: Add cache handling functions. This change adds functions for + enabling and disabling d/i-caches which were missing for ARMv7-R. + From Heesub Shin. + - ARMv7-R: Fix typo in mpu support. s/ARMV7M/ARMV7R/g. From Heesub Shin. + - ARMv7-R: Fix CPSR corruption after exception handling. A sporadic + hang with consequent crash was observed when booting. It seemed to be + caused by the corrupted or wrong CPSR restored on return from + exception. NuttX restores the context using code like this: msr spsr, + r1. GCC translates this to: msr spsr_fc, r1. As a result, not all + SPSR fields are updated on exception return. This should be: msr + spsr_fsxc, r1. On some evaluation boards, spsr_svc may have totally + invalid value at power-on-reset. As it is not initialized at boot, the + code above may result in the corruption of cpsr and thus unexpected + behavior. From Heesub Shin. + - ARMv7-R: Fix to restore the Thumb flag in CPSR. Thumb flag in CPSR is + not restored back when the context switch occurs while executing thumb + instruction. From Heesub Shin. + + * Atmel SAM3/4 Drivers: + + - SAM3/4 UDP: Add delay between setting and clearing the endpoint RESET + bit in sam_ep_resume(). We need to add a delay between setting and + clearing the endpoint reset bit in SAM_UDP_RSTEP. Without the delay + the USB controller will (may?) not reset the endpoint. If the + endpoint is not being reset, the Data Toggle (DTGLE) bit will not to + be cleared which will cause the next transaction to fail if DTGLE is + 1. If that happens the host will time-out and reset the bus. Adding + this delay may also fix the USBMSC_STALL_RACEWAR in usbmsc_scsi.c, + however this has not been verified yet. From Wolfgang Reinegger. + - SAM3/4: Remove unused 'halted' flag from UDP driver. From Wolfgang + Reinegger. + - SAM3/4: Remove 'stalled' flag from the UDP driver. This flag is not + necessary because the state of the endpoint can be determined using + 'epstate' instead. From Wolfgang Reinegger. + + * Atmel SAM3/4 Boards: + + - SAM4S Xplained Pro: Configuration uses old, improper timer interface. + CONFIG_TIMER disabled in configuration. Remove obsolete timer + initialization logic. + + * Atmel SAMV7 Drivers: + + - SAMv7 USBDEVHS: A problem occurred with the SAMV7 USBDEVHS driver if + the USB cable is unplugged while a large amount of data is send over + an IN endpoint using DMA. If the USB cable is plugged in again after a + few seconds it is not possible to send data over this IN endpoint + again, all other endpoints work as expected. The problem occurs + because if the USB cable is unplugged while an DMA transfer is in + flight the transfer is canceled but the register SAM_USBHS_DEVDMACTRL + is left in an undefined state. The problem was fixed the problem by + resetting the register SAM_USBHS_DEVDMACTRL to a known state. + Additionally all pending interrupts are cleared. From Stefan Kolb. + - SAMV7 MCAN: Prevent Interrupt-Flooding of ACKE when not connected to + CAN-BUS. An Acknowledge-Error will occur every time no other CAN Node + acknowledges the message sent. This will also occur if the device is + not connected to the can-bus. The CAN-Standard declares, that the Chip + has to retry a given message as long as it is not sent successfully + (or it is not cancelled by the application). Every time the chip tries + to resend the message an Acknowledge-Error-Interrupt is generated. At + high baud rates this can lead in extremely high CPU load just for + handling the interrupts (and possibly the error handling in the + application). To prevent this Interrupt-Flooding we disable the ACKE + once it is seen as long we didn't transfer at least one message + successfully. From Frank Benkert. + - SAMV7 MCAN: Make delete_filter functions more robust. From Frank + Benkert. + + * Atmel SAMA5 Drivers: + + - SAMA5 PWM: Driver does not build when executing from SDRAM before + board frequencies are not constant. Rather, the bootloader configures + the clocking and we must derive the clocking from the MCK left by the + bootloader. This means lots more computations. This is untested on + initial change because I don't have a good PWM test setup right now. + + * Misoc LM32: + + - Misoc LM32: Corrects a bug that never occured in qemu on simulation or + real fpga. The error was that the r1 register was being modified out + of context switching and not restoring it. From Ramtin Amin + + * NXP Freescale i.MX6: + + - i.MX6 interrupt handling: Additional logic needed to handle nested + interrupts when an interrupt stack is used. Nesting can occur because + SGI interrupts are non-maskable. + + * NXP Freescale LPC43xx Drivers: + + - LPC43xx serial: Fix a typo in ioctl TIOCSRS485 ioctl. From Vytautas + Lukenskas. + - LPC43xx serial: Restore RS485 mode on serial port open (if RS485 is + enabled via menuconfig). From Vytautas Lukenskas. + - LPC43xx SD/MMC: Correct some definitions on SMMC control register in + lpc43_sdmmc.h. From Alan Carvalho de Assis. + - LPC43xx SD card: Correct pin configuration options needed for SD card + pins. From Alan Carvalho de Assis. + + * SiLabs EFM32: + + - EFM32: Fix a compilation error. From Pierre-noel Bouteville. + + * STMicro STM32 Drivers: + + - STM32 CHxN channels are always outputs. From Sebastien Lorquet. + - STM32 DAC: Fix shift value whenever there are is a DAC2 and, hence, + up to three interfaces. From Marc Recht. + - STM32 F1: Add TIM8 to STM32F103V pinmap. From Maciej Wjcik. + - STM32 F1: Fix for F1 RTC Clock, tested on F103. From Maciej Wjcik. + - STM32 F3: STM32F303xB and STM32F303xC chips have 4 ADCs. From Paul + A. Patience. + - STM32 F4: A new implementation of the STM32 F4 I2C bottom half. The + common I2C as this did not handled correctly in the current + implementation (see also https://github.com/PX4/NuttX/issues/54). The + changes almost exclusively affect the ISR. From Max Kriegleder. + - STM32 F4 OTGHS Host: If STM32F446 increase number of channels to + 16. From Janne Rosberg. + - STM32 F4: I think, that Size is (highest address+1 - Base address). + Base address has been removed and if address+count >= size we are + outside of the Flash. From David Sidrane. + - STM32 F4: Fix ADC compilation error when DMA isn't enabled. From Paul + A. Patience. + - STM32 F4: STM32F427 was rebooting. Over reached family. From David + Sidrane. + - STM32 F4: Added STM32F469 RAM size and deliberated STM32F446 size. + From David Sidrane. + - STM32 F4: Typo in stm32f76xxxx_pinmap.h edited online with + Bitbucket. From David Sidrane. + - STM32 F7: stm32_i2c.c Dejavu. Fixes a bug previously found in the + F4. From David Sidrane. + - STM32 F7: OTGDEV fixed typo. From David Sidrane. + - STM32 F7: Fix to SPI-Master driver. Without this the chip select + decoding feature will not work properly. From Michael Spahlinger. + - STM32 F7: STM32F7 SD/MMC driver depends on CONFIG_SDIO_DMA which is + only defined in stm32/Kconfig. Changed to CONFIG_STM32F7_SDMMC_DMA + and defined in stm32f7/Kconfig. + - STM32 F7: Fix some STM32F7 copy paste errors. From David Sidrane. + - STM32 L4: Complementary PWM outputs on STM32L4" (1) too many + parentheses when calculating max chan count and (2) channel 4 does not + have a complementary output. From Sebastien Lorquet. + - STM32 L4: Fix I2C devices RCC registers. From Sebastien Lorquet. + - STM32 L4: Enable and renaming for 32l4 UARTs 4 and 5. From Sebastien + Lorquet. + - STM32 L4: Change the way to configure quadrature encoder prescalers. + From Sebastien Lorquet. + - STM32 L4: Correct USART1/2 definitions. Use default mbed UART4 + settings. From Sebastien Lorquet. + + * STMicro STM32 Boards: + + - STM32F103 Minimum: Fix Timers 2 to 7 clock frequencies. From Alan + Carvalho de Assis. + - Nucleo-F303RE: Remove duplicate setting from board.h. From Marc + Recht. + - Nucleo F303RE: Various fixes to get the ADC configuration building + again after PR. Refresh all configurations. + - Nucleo L476RG: Add better selection of timer. + + * TI Tiva Boards: + + - DK-TM4C129x: Typo fix. From Wolfgang Reinegger. + + * Xtensa ESP32: + + - ESP32 core v2: Flush the UART TX buffer in the esp32 serial shutdown + routine. The ROM bootloader does not flush the FIFO before handing + over to user code, so some of this output is not currently seen when + the UART is reconfigured in early stages of startup. From Angus + Gratton. + - Xtensa ESP32: Corrects a problem with dispatching to signal + handlers: Cannot vector directly to the signal handling function as + in other ABIs under the Xtensa Window ABI. In that case, we need to + go through a tiny hook when performs the correct window call (call4) + otherwise registers will be scrambled in the signal handler. + + * Xtensa ESP32 Boards: + + - ESP32 core v2: Changes the openocd config file's default flash + voltage from 1.8V to 3.3V. This is not necessary right now, but may + save some hard-to-debug moments down the track (3.3V-only flash + running at 1.8V often half-works and does weird things...). From + Angus Gratton. + + * C Library/Header Files: + + - libc/stdio: Fixes sscanf() %sn where strlen(data) < n. From David + Sidrane. + - libc/stdio: Include wchar.h in lib_libvsprintf.c to fix compilation + error. From Alan Carvalho de Assis. + - include/sys/time.h: timersub macro modified per recommendations of + phreakuencies. + - include/ctype.h and cxx/cctype: Implement ctype.h functions as inline + if possible. cctype can then properly select namespace. + - include/: Fix a number of header files with mismatched 'extern C {' + and '}'. + - libc/unisted: Change brings strtol() and related functions more + conformant with POSIX. Corner cases like strtol(-2147483648, NULL, + 10) now pass clang -fsanitize=integer without warnings. From Juha + Niskanen. + - libc/unistd: sleep() was returning remaining nanoseconds (kind of), + instead the remaining seconds. From Eunbong Song. + - termios.h: Fix CRTSCTS define to include input and output flow. From + Lorenz Meier. + + * Build/Configuration System: + + - configs/*/defconfig: The buttons example was changed to archbuttons. + As a result all of the button configurations are broken and need some + renaming in the defconfig files. Noted by Frank Berkert. + - config/*/defconfgs: More fallout from name change of + apps/examples/buttons to archbuttons. + - configs: All QE encoder files. Last change made timer hard-coded to + 3. Make configurable. + - configs: Remove all traces of the no-longer existent ARCHBUTTONS + example. Remove all button configurations that depended on the + obsoleted ARCHBUTTON example. + - minnsh Configurations: Remove minnsh configurations and support + logic: up_getc() and lowinstream. This was an interesting exercise + to see just how small you could get NuttX, but otherwise it was not + useful: (1) the NSH code violated the OS interface layer by callup + up_getc() and up_putc() directly, and (2) while waiting for character + input, NSH would call up_getc() which would hog all of the CPU. Not a + reasonable solution other than as a proof of concept. + + * Application Build/Configuration System: + + - Make.defs: Using wrong link script if native window tool used with + Cygwin. + + * apps/platform: + + - ESP32 Core v2 Platform: Fix some naming that prevented building the + C++ support. + + * apps/nshlib: + + - NSH Library: nsh_getdirpath(), use snprint instead of sprintf to + avoid possibility of buffer overrun. Noted by Chung Hwan Kim. + + * apps/system: + + - Remove std_readline(). This called up_getc() and up_putc() directly, + violating the POSIX OS interface. + + * apps/netutils: + + - FTPD: Fixed bug that didn't free ftpd ressources on exit. From Pascal + Speck. + - NTP client: Fix missing left parenthesis. From Pierre-Noel Bouteville. + - cJSON: Import patch to fix:cJSON_PrintUnformatted() behaves unexpected + if an empty array shall be printed to text. from Jerome Lang + 2012-04-19. From Pierre-Noel Bouteville. + - esp8266 update cosmetic and many bug fix. From Pierre-Noel Bouteville. + - FTPD: Fix bug un ftpd file or socket may be not closed. From + Pierre-Noel Bouteville. + + * apps/modbus: + + - Modbus Master is missing many files and doesn't compile at all. More + details in + https://groups.yahoo.com/neo/groups/nuttx/conversations/topics/13734. + From Vytautas Lukenskas. + + * apps/examples: + + - The examples/qencoder app was trying to init the encoder by a direct + call into the board, cheating in a local header to declare the + normally unavailable function prototype. From Sebastien Lorquet. + - apps/examples/timer: Should detach signal handler before exiting. + - examples/qencode: The examples/qencoder app was trying to init the + encoder by a direct call into the board, cheating in a local header to + declare the normally unavailable function prototype. From Sebastien + Lorquet. + - apps/examples/archbuttons: Removed becaue it violates OS interface + principles. + - examples/adc, pwm, can: Remove all usage of BOARDIOC_ADCTEST_SETUP, + BIOARDIOC_PWMSETUP. Remove BOARDIOC_CAN_INITIALIZE. CAN + initialization is now done in the board initialization logic just like + every other device driver. + - examples/ostest: Add some delays to the pthread cancellation test. + With deferred cancellation enabled, things happen more asynchronously. diff --git a/arch/arm/src/imx6/imx_timerisr.c b/arch/arm/src/imx6/imx_timerisr.c index 60f8864177f..4c766664937 100644 --- a/arch/arm/src/imx6/imx_timerisr.c +++ b/arch/arm/src/imx6/imx_timerisr.c @@ -115,10 +115,6 @@ static void up_output_compare(uint32_t sr, uint32_t of) if ((sr & of) != 0) { - /* Clear the pending output compare interrupt */ - - putreg32(of, IMX_GPT_SR); - /* Process timer interrupt event */ sched_process_timer(); @@ -140,9 +136,16 @@ static void up_output_compare(uint32_t sr, uint32_t of) int up_timerisr(int irq, uint32_t *regs) { - /* Sample the SR (once) and process all pending output compare interrupt */ + /* Sample the SR (once) */ uint32_t sr = getreg32(IMX_GPT_SR); + + /* Clear GPT status register */ + + putreg32(sr, IMX_GPT_SR); + + /* Process all pending output compare interrupt */ + up_output_compare(sr, GPT_INT_OF1); up_output_compare(sr, GPT_INT_OF2); up_output_compare(sr, GPT_INT_OF3); diff --git a/arch/arm/src/stm32/chip/stm32f102_pinmap.h b/arch/arm/src/stm32/chip/stm32f102_pinmap.h index d2911da8645..20cecf5b7cc 100644 --- a/arch/arm/src/stm32/chip/stm32f102_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f102_pinmap.h @@ -198,8 +198,8 @@ #define GPIO_USART1_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12) #define GPIO_USART1_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8) #if defined(CONFIG_STM32_USART1_REMAP) -# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6) -# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7) +# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6) +# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7) #else # define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9) # define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10) diff --git a/arch/arm/src/stm32/chip/stm32f103r_pinmap.h b/arch/arm/src/stm32/chip/stm32f103r_pinmap.h index de73b1acb10..e654104e0e9 100644 --- a/arch/arm/src/stm32/chip/stm32f103r_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f103r_pinmap.h @@ -237,8 +237,8 @@ /* USART */ #if defined(CONFIG_STM32_USART1_REMAP) -# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9) -# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10) +# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6) +# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7) #else # define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9) # define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10) diff --git a/arch/arm/src/stm32/chip/stm32f103v_pinmap.h b/arch/arm/src/stm32/chip/stm32f103v_pinmap.h index 17492579f73..c4feb129612 100644 --- a/arch/arm/src/stm32/chip/stm32f103v_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f103v_pinmap.h @@ -370,8 +370,8 @@ #define GPIO_USART1_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12) #define GPIO_USART1_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8) #if defined(CONFIG_STM32_USART1_REMAP) -# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6) -# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7) +# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6) +# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7) #else # define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9) # define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10) diff --git a/arch/arm/src/stm32/chip/stm32f103z_pinmap.h b/arch/arm/src/stm32/chip/stm32f103z_pinmap.h index 54b09d23350..993708a5ecf 100644 --- a/arch/arm/src/stm32/chip/stm32f103z_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f103z_pinmap.h @@ -272,8 +272,8 @@ /* USART */ #if defined(CONFIG_STM32_USART1_REMAP) -# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9) -# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10) +# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6) +# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7) #else # define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9) # define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10) diff --git a/arch/arm/src/stm32/chip/stm32f105r_pinmap.h b/arch/arm/src/stm32/chip/stm32f105r_pinmap.h index ffd3ef35c45..0f82dc3ffd6 100644 --- a/arch/arm/src/stm32/chip/stm32f105r_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f105r_pinmap.h @@ -280,8 +280,8 @@ #define GPIO_USART1_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12) #define GPIO_USART1_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8) #if defined(CONFIG_STM32_USART1_REMAP) -# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9) -# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10) +# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6) +# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7) #else # define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9) # define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10) diff --git a/arch/arm/src/stm32/chip/stm32f105v_pinmap.h b/arch/arm/src/stm32/chip/stm32f105v_pinmap.h index 5fd7029e2c1..7850a3cc359 100644 --- a/arch/arm/src/stm32/chip/stm32f105v_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f105v_pinmap.h @@ -314,8 +314,8 @@ #define GPIO_USART1_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12) #define GPIO_USART1_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8) #if defined(CONFIG_STM32_USART1_REMAP) -# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9) -# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10) +# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6) +# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7) #else # define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9) # define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10) diff --git a/configs/sabre-6quad/smp/defconfig b/configs/sabre-6quad/smp/defconfig index e9e22fc45fd..d470592436e 100644 --- a/configs/sabre-6quad/smp/defconfig +++ b/configs/sabre-6quad/smp/defconfig @@ -315,7 +315,7 @@ CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_RR_INTERVAL=200 # CONFIG_SCHED_SPORADIC is not set CONFIG_TASK_NAME_SIZE=31 -CONFIG_MAX_TASKS=16 +CONFIG_MAX_TASKS=32 # CONFIG_SCHED_HAVE_PARENT is not set CONFIG_SCHED_WAITPID=y @@ -324,6 +324,8 @@ CONFIG_SCHED_WAITPID=y # # CONFIG_MUTEX_TYPES is not set CONFIG_NPTHREAD_KEYS=4 +# CONFIG_PTHREAD_CLEANUP is not set +# CONFIG_CANCELLATION_POINTS is not set # # Performance Monitoring @@ -647,6 +649,8 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set CONFIG_ARCH_HAVE_TLS=y # CONFIG_TLS is not set +# CONFIG_LIBC_IPv4_ADDRCONV is not set +# CONFIG_LIBC_IPv6_ADDRCONV is not set # CONFIG_LIBC_NETDB is not set # CONFIG_NETDB_HOSTFILE is not set @@ -730,7 +734,10 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_SLCD is not set # CONFIG_EXAMPLES_SMART is not set # CONFIG_EXAMPLES_SMART_TEST is not set -# CONFIG_EXAMPLES_SMP is not set +CONFIG_EXAMPLES_SMP=y +CONFIG_EXAMPLES_SMP_NBARRIER_THREADS=8 +CONFIG_EXAMPLES_SMP_PRIORITY=100 +CONFIG_EXAMPLES_SMP_STACKSIZE=2048 # CONFIG_EXAMPLES_TCPECHO is not set # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_TIFF is not set @@ -858,6 +865,7 @@ CONFIG_NSH_MMCSDMINOR=0 # Configure Command Options # # CONFIG_NSH_CMDOPT_DF_H is not set +# CONFIG_NSH_CMDOPT_DD_STATS is not set CONFIG_NSH_CODECS_BUFSIZE=128 # CONFIG_NSH_CMDOPT_HEXDUMP is not set CONFIG_NSH_PROC_MOUNTPOINT="/proc" diff --git a/include/nuttx/spinlock.h b/include/nuttx/spinlock.h index 6f3409ca905..3798e177ff5 100644 --- a/include/nuttx/spinlock.h +++ b/include/nuttx/spinlock.h @@ -330,7 +330,7 @@ void spin_unlockr(FAR struct spinlock_s *lock); * Input Parameters: * set - A reference to the bitset to set the CPU bit in * cpu - The bit number to be set - * setlock - A reference to the lock lock protecting the set + * setlock - A reference to the lock protecting the set * orlock - Will be set to SP_LOCKED while holding setlock * * Returned Value: @@ -351,7 +351,7 @@ void spin_setbit(FAR volatile cpu_set_t *set, unsigned int cpu, * Input Parameters: * set - A reference to the bitset to set the CPU bit in * cpu - The bit number to be set - * setlock - A reference to the lock lock protecting the set + * setlock - A reference to the lock protecting the set * orlock - Will be set to SP_UNLOCKED if all bits become cleared in set * * Returned Value: diff --git a/include/termios.h b/include/termios.h index 00ff32e5c66..8427cbf5991 100644 --- a/include/termios.h +++ b/include/termios.h @@ -110,8 +110,8 @@ #define HUPCL (1 << 6) /* Bit 6: Hang up on last close */ #define CLOCAL (1 << 7) /* Bit 7: Ignore modem status lines */ #define CCTS_OFLOW (1 << 8) /* Bit 8: CTS flow control of output */ -#define CRTSCTS CCTS_OFLOW #define CRTS_IFLOW (1 << 9) /* Bit 9: RTS flow control of input */ +#define CRTSCTS (CRTS_IFLOW | CCTS_OFLOW) /* Local Modes (c_lflag in the termios structure) */ diff --git a/sched/irq/irq.h b/sched/irq/irq.h index 69b3d344b39..40473a60108 100644 --- a/sched/irq/irq.h +++ b/sched/irq/irq.h @@ -44,6 +44,7 @@ #include #include +#include #include #include @@ -106,6 +107,33 @@ void weak_function irq_initialize(void); int irq_unexpected_isr(int irq, FAR void *context); +/**************************************************************************** + * Name: irq_cpu_locked + * + * Description: + * Test if the IRQ lock set OR if this CPU holds the IRQ lock + * There is an interaction with pre-emption controls and IRQ locking: + * Even if the pre-emption is enabled, tasks will be forced to pend if + * the IRQ lock is also set UNLESS the CPU starting the task is the + * holder of the IRQ lock. + * + * Inputs: + * rtcb - Points to the blocked TCB that is ready-to-run + * + * Return Value: + * true - IRQs are locked by a different CPU. + * false - IRQs are unlocked OR if they are locked BUT this CPU + * is the holder of the lock. + * + * Warning: This values are volatile at only valid at the instance that + * the CPU set was queried. + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +bool irq_cpu_locked(int cpu); +#endif + #undef EXTERN #ifdef __cplusplus } diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 5b517de8bbf..bf226bf6217 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -504,9 +504,41 @@ void leave_critical_section(irqstate_t flags) DEBUGASSERT(spin_islocked(&g_cpu_irqlock) && (g_cpu_irqset & (1 << cpu)) != 0); + /* Check if releasing the lock held by this CPU will unlock the + * critical section. + */ + + if ((g_cpu_irqset & ~(1 << cpu)) == 0) + { + /* Yes.. Check if there are pending tasks and that pre-emption + * is also enabled. This is necessary because we may have + * deferred the up_release_pending() call in sched_unlock() + * because we were within a critical section then. + */ + + if (g_pendingtasks.head != NULL && + !spin_islocked(&g_cpu_schedlock)) + { + /* Release any ready-to-run tasks that have collected + * in g_pendingtasks. NOTE: This operation has a very + * high likelihood of causing this task to be switched + * out! + */ + + up_release_pending(); + } + } + + /* Now, possibly on return from a context switch, clear our + * count on the lock. If all CPUs have released the lock, + * then unlock the global IRQ spinlock. + */ + rtcb->irqcount = 0; spin_clrbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock, &g_cpu_irqlock); + + /* Have all CPUs released the lock? */ } } } @@ -540,4 +572,78 @@ void leave_critical_section(irqstate_t flags) } #endif +/**************************************************************************** + * Name: irq_cpu_locked + * + * Description: + * Test if the IRQ lock set OR if this CPU holds the IRQ lock + * There is an interaction with pre-emption controls and IRQ locking: + * Even if the pre-emption is enabled, tasks will be forced to pend if + * the IRQ lock is also set UNLESS the CPU starting the task is the + * holder of the IRQ lock. + * + * Inputs: + * rtcb - Points to the blocked TCB that is ready-to-run + * + * Return Value: + * true - IRQs are locked by a different CPU. + * false - IRQs are unlocked OR if they are locked BUT this CPU + * is the holder of the lock. + * + * Warning: This values are volatile at only valid at the instance that + * the CPU set was queried. + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +bool irq_cpu_locked(int cpu) +{ + cpu_set_t irqset; + + /* g_cpu_irqset is not valid in early phases of initialization */ + + if (g_os_initstate < OSINIT_OSREADY) + { + /* We are still single threaded. In either state of g_cpu_irqlock, + * the correct return value should always be false. + */ + + return false; + } + + /* Test if g_cpu_irqlock is locked. We don't really need to use check + * g_cpu_irqlock to do this, we can use the g_cpu_set. + * + * Sample the g_cpu_irqset once. That is an atomic operation. All + * subsequent operations will operate on the sampled cpu set. + */ + + irqset = (cpu_set_t)g_cpu_irqset; + if (irqset != 0) + { + /* Some CPU holds the lock. So g_cpu_irqlock should be locked. + * Return false if the 'cpu' is the holder of the lock; return + * true if g_cpu_irqlock is locked, but this CPU is not the + * holder of the lock. + */ + + return ((irqset & (1 << cpu)) == 0); + } + + /* No CPU holds the lock */ + + else + { + /* In this case g_cpu_irqlock should be unlocked. However, if + * the lock was established in the interrupt handler AND there are + * no bits set in g_cpu_irqset, that probabaly means only that + * critical section was established from an interrupt handler. + * Return false in either case. + */ + + return false; + } +} +#endif + #endif /* CONFIG_SMP || CONFIG_SCHED_INSTRUMENTATION_CSECTION */ diff --git a/sched/sched/sched_addreadytorun.c b/sched/sched/sched_addreadytorun.c index 77b1492c535..c5f86e2a807 100644 --- a/sched/sched/sched_addreadytorun.c +++ b/sched/sched/sched_addreadytorun.c @@ -167,10 +167,11 @@ bool sched_addreadytorun(FAR struct tcb_s *btcb) { FAR struct tcb_s *rtcb; FAR dq_queue_t *tasklist; - int task_state; - int cpu; bool switched; bool doswitch; + int task_state; + int cpu; + int me; /* Check if the blocked TCB is locked to this CPU */ @@ -226,9 +227,17 @@ bool sched_addreadytorun(FAR struct tcb_s *btcb) * disabled. If the selected state is TSTATE_TASK_READYTORUN, then it * should also go to the pending task list so that it will have a chance * to be restarted when the scheduler is unlocked. + * + * There is an interaction here with IRQ locking. Even if the pre- + * emption is enabled, tasks will be forced to pend if the IRQ lock + * is also set UNLESS the CPU starting the thread is also the holder of + * the IRQ lock. irq_cpu_locked() performs an atomic check for that + * situation. */ - if (spin_islocked(&g_cpu_schedlock) && task_state != TSTATE_TASK_ASSIGNED) + me = this_cpu(); + if ((spin_islocked(&g_cpu_schedlock) || irq_cpu_locked(me)) && + task_state != TSTATE_TASK_ASSIGNED) { /* Add the new ready-to-run task to the g_pendingtasks task list for * now. @@ -255,10 +264,8 @@ bool sched_addreadytorun(FAR struct tcb_s *btcb) } else /* (task_state == TSTATE_TASK_ASSIGNED || task_state == TSTATE_TASK_RUNNING) */ { - int me = this_cpu(); - - /* If we are modifying some assigned task list other than our own, we will - * need to stop that CPU. + /* If we are modifying some assigned task list other than our own, we + * will need to stop that CPU. */ if (cpu != me) @@ -273,7 +280,8 @@ bool sched_addreadytorun(FAR struct tcb_s *btcb) tasklist = (FAR dq_queue_t *)&g_assignedtasks[cpu]; switched = sched_addprioritized(btcb, tasklist); - /* If the selected task was the g_assignedtasks[] list, then a context + /* If the selected task list was the g_assignedtasks[] list and if the + * new tasks is the highest priority (RUNNING) task, then a context * switch will occur. */ @@ -367,7 +375,14 @@ bool sched_addreadytorun(FAR struct tcb_s *btcb) } else { - /* No context switch. Assign the CPU and set the assigned state */ + /* No context switch. Assign the CPU and set the assigned state. + * + * REVISIT: I have seen this assertion fire. Apparently another + * CPU may add another, higher prioirity task to the same + * g_assignedtasks[] list sometime after sched_cpu_select() was + * called above, leaving this TCB in the wrong task list if task_state + * is TSTATE_TASK_ASSIGNED). + */ DEBUGASSERT(task_state == TSTATE_TASK_ASSIGNED); diff --git a/sched/sched/sched_mergepending.c b/sched/sched/sched_mergepending.c index 863eb73c275..15e87ce99c6 100644 --- a/sched/sched/sched_mergepending.c +++ b/sched/sched/sched_mergepending.c @@ -48,6 +48,7 @@ # include #endif +#include "irq/irq.h" #include "sched/sched.h" /**************************************************************************** @@ -196,15 +197,16 @@ bool sched_mergepending(void) FAR struct tcb_s *tcb; bool ret = false; int cpu; + int me; /* Remove and process every TCB in the g_pendingtasks list. * - * This function is only called in the context where locking is known to - * disabled on one CPU. However, we must do nothing if pre-emption is - * still locked because of actions of other CPUs. + * Do nothing if (1) pre-emption is still disabled (by any CPU), or (2) if + * some CPU other than this one is in a critical section. */ - if (!spin_islocked(&g_cpu_schedlock)) + me = this_cpu(); + if (!spin_islocked(&g_cpu_schedlock) && !irq_cpu_locked(me)) { /* Find the CPU that is executing the lowest priority task */ @@ -243,7 +245,7 @@ bool sched_mergepending(void) * Check if that happened. */ - if (spin_islocked(&g_cpu_schedlock)) + if (spin_islocked(&g_cpu_schedlock) || irq_cpu_locked(me)) { /* Yes.. then we may have incorrectly placed some TCBs in the * g_readytorun list (unlikely, but possible). We will have to diff --git a/sched/sched/sched_removereadytorun.c b/sched/sched/sched_removereadytorun.c index 5b6b663d97c..be80d3ad0fe 100644 --- a/sched/sched/sched_removereadytorun.c +++ b/sched/sched/sched_removereadytorun.c @@ -165,7 +165,7 @@ bool sched_removereadytorun(FAR struct tcb_s *rtcb) if (rtcb->blink == NULL && TLIST_ISRUNNABLE(rtcb->task_state)) { FAR struct tcb_s *nxttcb; - FAR struct tcb_s *rtrtcb; + FAR struct tcb_s *rtrtcb = NULL; int me; /* There must always be at least one task in the list (the IDLE task) @@ -198,14 +198,21 @@ bool sched_removereadytorun(FAR struct tcb_s *rtcb) * g_readytorun list. We can only select a task from that list if * the affinity mask includes the current CPU. * - * REVISIT: What should we do, if anything, if pre-emption is locked - * by the another CPU? Should just used nxttcb? Should we select - * from the pending task list instead of the g_readytorun list? + * If pre-emption is locked or another CPU is in a critical section, + * then use the 'nxttcb' which will probably be the IDLE thread. + * REVISIT: What if it is not the IDLE thread? */ - for (rtrtcb = (FAR struct tcb_s *)g_readytorun.head; - rtrtcb != NULL && !CPU_ISSET(cpu, &rtrtcb->affinity); - rtrtcb = (FAR struct tcb_s *)rtrtcb->flink); + if (!spin_islocked(&g_cpu_schedlock) && !irq_cpu_locked(me)) + { + /* Search for the highest priority task that can run on this + * CPU. + */ + + for (rtrtcb = (FAR struct tcb_s *)g_readytorun.head; + rtrtcb != NULL && !CPU_ISSET(cpu, &rtrtcb->affinity); + rtrtcb = (FAR struct tcb_s *)rtrtcb->flink); + } /* Did we find a task in the g_readytorun list? Which task should * we use? We decide strictly by the priority of the two tasks: diff --git a/sched/sched/sched_setpriority.c b/sched/sched/sched_setpriority.c index 9e2c9384aa9..2dfd1c1417d 100644 --- a/sched/sched/sched_setpriority.c +++ b/sched/sched/sched_setpriority.c @@ -52,6 +52,64 @@ * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: sched_nexttcb + * + * Description: + * Get the next highest priority ready-to-run task. + * + * Inputs: + * tcb - the TCB of task to reprioritize. + * + * Return Value: + * TCB of the next highest priority ready-to-run task. + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +static FAR struct tcb_s *sched_nexttcb(FAR struct tcb_s *tcb) +{ + FAR struct tcb_s *nxttcb = (FAR struct tcb_s *)tcb->flink; + FAR struct tcb_s *rtrtcb; + int cpu = this_cpu(); + + /* Which task should run next? It will be either the next tcb in the + * assigned task list (nxttcb) or a TCB in the g_readytorun list. We can + * only select a task from that list if the affinity mask includes the + * current CPU. + * + * If pre-emption is locked or another CPU is in a critical section, + * then use the 'nxttcb' which will probably be the IDLE thread. + */ + + if (!spin_islocked(&g_cpu_schedlock) && !irq_cpu_locked(cpu)) + { + /* Search for the highest priority task that can run on this CPU. */ + + for (rtrtcb = (FAR struct tcb_s *)g_readytorun.head; + rtrtcb != NULL && !CPU_ISSET(cpu, &rtrtcb->affinity); + rtrtcb = (FAR struct tcb_s *)rtrtcb->flink); + + /* Return the TCB from the readyt-to-run list if it is the next + * highest priority task. + */ + + if (rtrtcb != NULL && + rtrtcb->sched_priority >= nxttcb->sched_priority) + { + return rtrtcb; + } + } + + /* Otherwise, return the next TCB in the g_assignedtasks[] list... + * probably the TCB of the IDLE thread. + * REVISIT: What if it is not the IDLE thread? + */ + + return nxttcb; +} +#endif + /**************************************************************************** * Name: sched_running_setpriority * @@ -77,12 +135,24 @@ static inline void sched_running_setpriority(FAR struct tcb_s *tcb, int sched_priority) { + FAR struct tcb_s *nxttcb; + + /* Get the TCB of the next highest priority, ready to run task */ + +#ifdef CONFIG_SMP + nxttcb = sched_nexttcb(tcb); +#else + nxttcb = (FAR struct tcb_s *)tcb->flink; +#endif + + DEBUGASSERT(nxttcb != NULL); + /* A context switch will occur if the new priority of the running * task becomes less than OR EQUAL TO the next highest priority * ready to run task. */ - if (sched_priority <= tcb->flink->sched_priority) + if (sched_priority <= nxttcb->sched_priority) { /* A context switch will occur. */ diff --git a/sched/sched/sched_unlock.c b/sched/sched/sched_unlock.c index df783dee7b7..885e0c778ce 100644 --- a/sched/sched/sched_unlock.c +++ b/sched/sched/sched_unlock.c @@ -44,6 +44,7 @@ #include #include +#include "irq/irq.h" #include "sched/sched.h" /**************************************************************************** @@ -66,6 +67,10 @@ int sched_unlock(void) { FAR struct tcb_s *rtcb = this_task(); + int cpu; + + cpu = this_cpu(); + rtcb = current_task(cpu); /* Check for some special cases: (1) rtcb may be NULL only during * early boot-up phases, and (2) sched_unlock() should have no @@ -102,29 +107,54 @@ int sched_unlock(void) #ifdef CONFIG_SMP /* The lockcount has decremented to zero and we need to perform - * release our hold on the lock. Pre-emption may still be locked - * from other CPUs. + * release our hold on the lock. */ DEBUGASSERT(g_cpu_schedlock == SP_LOCKED && - (g_cpu_lockset & (1 << this_cpu())) != 0); + (g_cpu_lockset & (1 << cpu)) != 0); - spin_clrbit(&g_cpu_lockset, this_cpu(), &g_cpu_locksetlock, + spin_clrbit(&g_cpu_lockset, cpu, &g_cpu_locksetlock, &g_cpu_schedlock); #endif /* Release any ready-to-run tasks that have collected in - * g_pendingtasks. In the SMP case, the scheduler remains - * locked if interrupts are disabled. + * g_pendingtasks. * * NOTE: This operation has a very high likelihood of causing * this task to be switched out! + */ + +#ifdef CONFIG_SMP + /* In the SMP case, the tasks remains pend(1) if we are + * in a critical section, i.e., g_cpu_irqlock is locked by other + * CPUs, or (2) other CPUs still have pre-emption disabled, i.e., + * g_cpu_schedlock is locked. In those cases, the release of the + * pending tasks must be deferred until those conditions are met. * - * NOTE: In SMP mode, pre-emption may still be locked due to - * operations on other CPUs. + * There are certain conditions that we must avoid by preventing + * releasing the pending tasks while within the critical section + * of other CPUs. This logic does that and there is matching + * logic in sched_addreadytorun to avoid starting new tasks within + * the critical section (unless the CPU is the holder of the lock). + * + * REVISIT: If this CPU is only one that holds the IRQ lock, then + * we should go ahead and release the pending tasks. See the logic + * leave_critical_section(): It will call up_release_pending() + * BEFORE it clears IRQ lock. + * BEFORE it clears IRQ lock. + */ + + if (!spin_islocked(&g_cpu_schedlock) && !irq_cpu_locked(cpu) && + g_pendingtasks.head != NULL) +#else + /* In the single CPU case, decrementing irqcount to zero is + * sufficient to release the pending tasks. Further, in that + * configuration, critical sections and pre-emption can operate + * fully independently. */ if (g_pendingtasks.head != NULL) +#endif { up_release_pending(); } diff --git a/sched/semaphore/spinlock.c b/sched/semaphore/spinlock.c index ec0e406d86e..349cdec57fc 100644 --- a/sched/semaphore/spinlock.c +++ b/sched/semaphore/spinlock.c @@ -390,7 +390,7 @@ void spin_unlockr(FAR struct spinlock_s *lock) * Input Parameters: * set - A reference to the bitset to set the CPU bit in * cpu - The bit number to be set - * setlock - A reference to the lock lock protecting the set + * setlock - A reference to the lock protecting the set * orlock - Will be set to SP_LOCKED while holding setlock * * Returned Value: @@ -441,7 +441,7 @@ void spin_setbit(FAR volatile cpu_set_t *set, unsigned int cpu, * Input Parameters: * set - A reference to the bitset to set the CPU bit in * cpu - The bit number to be set - * setlock - A reference to the lock lock protecting the set + * setlock - A reference to the lock protecting the set * orlock - Will be set to SP_UNLOCKED if all bits become cleared in set * * Returned Value: