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Correct some spacing issues

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This commit is contained in:
Gregory Nutt
2015-10-07 11:39:06 -06:00
parent 90b7cdcdaf
commit b6638315a4
173 changed files with 1711 additions and 1639 deletions
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arch/arm/src/arm/up_assert.c
+1 -1
View File
@@ -313,7 +313,7 @@ static void _up_assert(int errorcode)
if (current_regs || ((struct tcb_s *)g_readytorun.head)->pid == 0)
{
(void)irqsave();
for (;;)
for (; ; )
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
arch/arm/src/armv6-m/up_assert.c
+2 -2
View File
@@ -226,7 +226,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
return ret;
}
static int assert_tracecallback(FAR struct usbtrace_s *trace,FAR void *arg)
static int assert_tracecallback(FAR struct usbtrace_s *trace, FAR void *arg)
{
usbtrace_trprintf(usbtrace_syslog, trace->event, trace->value);
return 0;
@@ -368,7 +368,7 @@ static void _up_assert(int errorcode)
if (current_regs || ((struct tcb_s *)g_readytorun.head)->pid == 0)
{
(void)irqsave();
for (;;)
for (; ; )
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
arch/arm/src/armv6-m/up_reprioritizertr.c
+1 -1
View File
@@ -136,7 +136,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
sched_suspend_scheduler(rtcb);
/* Are we in an interrupt handler? */
/* Are we in an interrupt handler? */
if (current_regs)
{
arch/arm/src/armv6-m/up_systemreset.c
+1 -1
View File
@@ -76,7 +76,7 @@ void up_systemreset(void)
/* Wait for the reset */
for (;;);
for (; ; );
}
arch/arm/src/armv7-a/arm_assert.c
+1 -1
View File
@@ -368,7 +368,7 @@ static void _up_assert(int errorcode)
if (current_regs || ((struct tcb_s *)g_readytorun.head)->pid == 0)
{
(void)irqsave();
for (;;)
for (; ; )
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
arch/arm/src/armv7-a/arm_pgalloc.c
+1 -1
View File
@@ -293,7 +293,7 @@ uintptr_t pgalloc(uintptr_t brkaddr, unsigned int npages)
index = (brkaddr & 0x000ff000) >> 12;
/* Map the .text region virtual address to this physical address */
/* Map the .text region virtual address to this physical address */
DEBUGASSERT(l2table[index] == 0);
l2table[index] = paddr | MMU_L2_UDATAFLAGS;
arch/arm/src/armv7-a/arm_reprioritizertr.c
+1 -1
View File
@@ -136,7 +136,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
sched_suspend_scheduler(rtcb);
/* Are we in an interrupt handler? */
/* Are we in an interrupt handler? */
if (current_regs)
{
arch/arm/src/armv7-m/up_assert.c
+1 -1
View File
@@ -377,7 +377,7 @@ static void _up_assert(int errorcode)
if (current_regs || ((struct tcb_s *)g_readytorun.head)->pid == 0)
{
(void)irqsave();
for (;;)
for (; ; )
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
arch/arm/src/armv7-m/up_itm_syslog.c
+4 -4
View File
@@ -101,10 +101,10 @@ void itm_syslog_initialize(void)
regval |= NVIC_DEMCR_TRCENA;
putreg32(regval, NVIC_DEMCR);
putreg32(0xc5acce55,ITM_LAR);
putreg32(0, ITM_TER);
putreg32(0, ITM_TCR);
putreg32(2, TPI_SPPR); /* Pin protocol: 2=> Manchester (USART) */
putreg32(0xc5acce55, ITM_LAR);
putreg32(0, ITM_TER);
putreg32(0, ITM_TCR);
putreg32(2, TPI_SPPR); /* Pin protocol: 2=> Manchester (USART) */
/* Default 880kbps */
arch/arm/src/armv7-m/up_reprioritizertr.c
+1 -1
View File
@@ -136,7 +136,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
sched_suspend_scheduler(rtcb);
/* Are we in an interrupt handler? */
/* Are we in an interrupt handler? */
if (current_regs)
{
arch/arm/src/armv7-m/up_systemreset.c
+1 -1
View File
@@ -77,7 +77,7 @@ void up_systemreset(void)
/* Wait for the reset */
for (;;);
for (; ; );
}
arch/arm/src/c5471/c5471_ethernet.c
+2 -2
View File
@@ -1058,7 +1058,7 @@ static void c5471_rxstatus(struct c5471_driver_s *c5471)
/* Walk that last packet we just received to collect xmit status bits. */
rxstatus = 0;
for (;;)
for (; ; )
{
if (EIM_TXDESC_OWN_HOST & getreg32(desc))
{
@@ -1405,7 +1405,7 @@ static void c5471_txstatus(struct c5471_driver_s *c5471)
txstatus = 0;
if (c5471->c_lastdescstart && c5471->c_lastdescend)
{
for (;;)
for (; ; )
{
txstatus |= (getreg32(desc) & EIM_RXDESC_STATUSMASK);
if (desc == c5471->c_lastdescend)
arch/arm/src/dm320/dm320_serial.c
+1 -1
View File
@@ -495,7 +495,7 @@ static int up_interrupt(int irq, void *context)
* until we have been looping for a long time.
*/
for (;;)
for (; ; )
{
/* Get the current UART status and check for loop
* termination conditions
arch/arm/src/dm320/dm320_usbdev.c
+2 -2
View File
@@ -960,7 +960,7 @@ static int dm320_wrrequest(struct dm320_ep_s *privep)
* may be resuming transfer already in progress.
*/
for (;;)
for (; ; )
{
/* Get the number of bytes left to be sent in the packet */
@@ -2251,7 +2251,7 @@ static FAR struct usbdev_ep_s *dm320_allocep(FAR struct usbdev_s *dev, uint8_t e
if (g_epinfo[ndx].attr == eptype)
{
/* Success! */
/* Success! */
return &priv->eplist[ndx].ep;
}
arch/arm/src/efm32/efm32_adc.c
+1 -1
View File
@@ -784,7 +784,7 @@ static void adc_startconv(struct efm32_dev_s *priv, bool enable)
regval &= ~ADC_CR2_SWSTART;
}
adc_putreg(priv, EFM32_ADC_CR2_OFFSET,regval);
adc_putreg(priv, EFM32_ADC_CR2_OFFSET, regval);
}
#endif
arch/arm/src/efm32/efm32_flash.c
+29 -29
View File
@@ -134,11 +134,11 @@ void efm32_flash_unlock(void)
/* Unlock the EFM32_MSC */
putreg32(MSC_UNLOCK_CODE,EFM32_MSC_LOCK);
putreg32(MSC_UNLOCK_CODE, EFM32_MSC_LOCK);
/* Disable writing to the flash */
bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WREN_SHIFT,0);
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 0);
#if defined(_MSC_TIMEBASE_MASK)
@@ -178,7 +178,7 @@ void efm32_flash_unlock(void)
regval |= (cycles << _MSC_TIMEBASE_BASE_SHIFT);
}
putreg32(regval,EFM32_MSC_TIMEBASE);
putreg32(regval, EFM32_MSC_TIMEBASE);
#endif
}
@@ -230,8 +230,8 @@ int __ramfunc__ msc_load_verify_address(uint32_t *address)
/* Load address */
putreg32((uint32_t) (address),EFM32_MSC_ADDRB);
putreg32(MSC_WRITECMD_LADDRIM,EFM32_MSC_WRITECMD);
putreg32((uint32_t) (address), EFM32_MSC_ADDRB);
putreg32(MSC_WRITECMD_LADDRIM, EFM32_MSC_WRITECMD);
status = getreg32(EFM32_MSC_STATUS);
if (status & (MSC_STATUS_INVADDR | MSC_STATUS_LOCKED))
@@ -320,12 +320,12 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words,
/* Clear double word option, in order to write one single word. */
bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WDOUBLE_SHIFT,0);
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WDOUBLE_SHIFT, 0);
/* Write first data word. */
putreg32(*data++,EFM32_MSC_WDATA);
putreg32(MSC_WRITECMD_WRITEONCE,EFM32_MSC_WRITECMD);
putreg32(*data++, EFM32_MSC_WDATA);
putreg32(MSC_WRITECMD_WRITEONCE, EFM32_MSC_WRITECMD);
/* Wait for the operation to finish. It may be required to change the
* WDOUBLE config after the initial write. It should not be changed
@@ -355,7 +355,7 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words,
* data phase.
*/
bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WDOUBLE_SHIFT,1);
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WDOUBLE_SHIFT, 1);
words_per_data_phase = 2;
}
else
@@ -380,7 +380,7 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words,
word_index = 0;
while (word_index < num_words)
{
putreg32(*data++,EFM32_MSC_WDATA);
putreg32(*data++, EFM32_MSC_WDATA);
word_index++;
if (words_per_data_phase == 2)
{
@@ -388,11 +388,11 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words,
{
}
putreg32(*data++,EFM32_MSC_WDATA);
putreg32(*data++, EFM32_MSC_WDATA);
word_index++;
}
putreg32(MSC_WRITECMD_WRITEONCE,EFM32_MSC_WRITECMD);
putreg32(MSC_WRITECMD_WRITEONCE, EFM32_MSC_WRITECMD);
/* Wait for the transaction to finish. */
@@ -412,13 +412,13 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words,
}
#if defined(CONFIG_EFM32_EFM32G)
putreg32(getreg32(EFM32_MSC_ADDRB)+4,EFM32_MSC_ADDRB);
putreg32(MSC_WRITECMD_LADDRIM,EFM32_MSC_WRITECMD);
putreg32(getreg32(EFM32_MSC_ADDRB)+4, EFM32_MSC_ADDRB);
putreg32(MSC_WRITECMD_LADDRIM, EFM32_MSC_WRITECMD);
#endif
}
}
/* Write strategy: msc_write_fast */
/* Write strategy: msc_write_fast */
else
{
@@ -461,15 +461,15 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words,
regval &= MSC_STATUS_WDATAREADY;
if (regval == MSC_STATUS_WORDTIMEOUT)
{
putreg32(MSC_WRITECMD_WRITETRIG,EFM32_MSC_WRITECMD);
putreg32(MSC_WRITECMD_WRITETRIG, EFM32_MSC_WRITECMD);
}
}
putreg32(*data,EFM32_MSC_WDATA);
putreg32(*data, EFM32_MSC_WDATA);
if ((words_per_data_phase == 1) || \
((words_per_data_phase == 2) && (word_index & 0x1)))
{
putreg32(MSC_WRITECMD_WRITETRIG,EFM32_MSC_WRITECMD);
putreg32(MSC_WRITECMD_WRITETRIG, EFM32_MSC_WRITECMD);
}
data++;
@@ -498,7 +498,7 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words,
/* Clear double word option, which should not be left on when returning. */
bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WDOUBLE_SHIFT,0);
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WDOUBLE_SHIFT, 0);
#endif
@@ -509,11 +509,11 @@ void efm32_flash_lock(void)
{
/* Disable writing to the flash */
bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WREN_SHIFT,0);
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 0);
/* Unlock the EFM32_MSC */
putreg32(0,EFM32_MSC_LOCK);
putreg32(0, EFM32_MSC_LOCK);
}
#ifndef EFM32_FLASH_SIZE
@@ -649,12 +649,12 @@ ssize_t __ramfunc__ up_progmem_erasepage(size_t page)
/* enable writing to the flash */
bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WREN_SHIFT,1);
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 1);
/* Load address */
putreg32((uint32_t)up_progmem_getaddress(page),EFM32_MSC_ADDRB);
putreg32(MSC_WRITECMD_LADDRIM,EFM32_MSC_WRITECMD);
putreg32((uint32_t)up_progmem_getaddress(page), EFM32_MSC_ADDRB);
putreg32(MSC_WRITECMD_LADDRIM, EFM32_MSC_WRITECMD);
regval = getreg32(EFM32_MSC_STATUS);
@@ -676,7 +676,7 @@ ssize_t __ramfunc__ up_progmem_erasepage(size_t page)
if (ret == 0)
{
putreg32(MSC_WRITECMD_ERASEPAGE,EFM32_MSC_WRITECMD);
putreg32(MSC_WRITECMD_ERASEPAGE, EFM32_MSC_WRITECMD);
/* Wait for the erase to complete */
@@ -694,7 +694,7 @@ ssize_t __ramfunc__ up_progmem_erasepage(size_t page)
/* Disable writing to the MSC */
bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WREN_SHIFT,0);
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 0);
if (ret == 0)
{
@@ -772,7 +772,7 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size)
/* enable writing to the flash */
bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WREN_SHIFT,1);
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 1);
/* Convert bytes to words */
@@ -783,7 +783,7 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size)
* increments the address internally for each data load inside a page.
*/
for (word_count = 0, p_data = (uint32_t *)buf; word_count < num_words;)
for (word_count = 0, p_data = (uint32_t *)buf; word_count < num_words; )
{
int page_bytes;
ssize_t page_idx;
@@ -841,7 +841,7 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size)
/* Disable writing to the MSC */
bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WREN_SHIFT,0);
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 0);
#if (defined(CONFIG_EFM32_EFM32GG) || defined(CONFIG_EFM32_EFM32WG)) && (2==WORDS_PER_DATA_PHASE)
arch/arm/src/efm32/efm32_gpioirq.c
+3 -3
View File
@@ -287,7 +287,7 @@ void efm32_gpioirqenable(int irq)
putreg32(regval, EFM32_GPIO_IEN);
irqrestore(flags);
#else
bitband_set_peripheral(EFM32_GPIO_IEN,(irq - EFM32_IRQ_EXTI0),1);
bitband_set_peripheral(EFM32_GPIO_IEN, (irq - EFM32_IRQ_EXTI0), 1);
#endif
}
}
@@ -318,7 +318,7 @@ void efm32_gpioirqdisable(int irq)
putreg32(regval, EFM32_GPIO_IEN);
irqrestore(flags);
#else
bitband_set_peripheral(EFM32_GPIO_IEN,(irq - EFM32_IRQ_EXTI0),0);
bitband_set_peripheral(EFM32_GPIO_IEN, (irq - EFM32_IRQ_EXTI0), 0);
#endif
}
}
@@ -349,7 +349,7 @@ void efm32_gpioirqclear(int irq)
putreg32(regval, EFM32_GPIO_IFC);
irqrestore(flags);
#else
bitband_set_peripheral(EFM32_GPIO_IFC,(irq - EFM32_IRQ_EXTI0),1);
bitband_set_peripheral(EFM32_GPIO_IFC, (irq - EFM32_IRQ_EXTI0), 1);
#endif
}
}
arch/arm/src/efm32/efm32_i2c.c
+5 -5
View File
@@ -422,13 +422,13 @@ static const struct i2c_ops_s efm32_i2c_ops =
.write = efm32_i2c_write,
.read = efm32_i2c_read
#ifdef CONFIG_I2C_WRITEREAD
,.writeread = efm32_i2c_writeread
, .writeread = efm32_i2c_writeread
#endif
#ifdef CONFIG_I2C_TRANSFER
,.transfer = efm32_i2c_transfer
, .transfer = efm32_i2c_transfer
#endif
#ifdef CONFIG_I2C_SLAVE
,.setownaddress = efm32_i2c_setownaddress,
, .setownaddress = efm32_i2c_setownaddress,
.registercallback = efm32_i2c_registercallback
#endif
};
@@ -903,7 +903,7 @@ static void efm32_i2c_setclock(FAR struct efm32_i2c_priv_s *priv,
static int efm32_i2c_isr(struct efm32_i2c_priv_s *priv)
{
for (;;)
for (; ; )
{
int regval;
@@ -1253,7 +1253,7 @@ static int efm32_i2c_isr(struct efm32_i2c_priv_s *priv)
* now, before receiving the last byte.
*/
efm32_i2c_putreg(priv,EFM32_I2C_CMD_OFFSET,I2C_CMD_NACK);
efm32_i2c_putreg(priv, EFM32_I2C_CMD_OFFSET, I2C_CMD_NACK);
}
}
}
arch/arm/src/efm32/efm32_pwm.c
+9 -8
View File
@@ -325,7 +325,8 @@ static void pwm_putreg(struct efm32_pwmtimer_s *priv, int offset, uint32_t value
#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE)
static void pwm_dumpregs(struct efm32_pwmtimer_s *priv, FAR const char *msg)
{
/* TODO debug pwm_dumpregs */
/* TODO debug pwm_dumpregs */
#if 0
pwmvdbg("%s:\n", msg);
pwmvdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
@@ -410,7 +411,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
#error "Not implemented ! Sorry"
#endif
if (efm32_timer_set_freq(priv->base,priv->pclk,info->frequency) < 0)
if (efm32_timer_set_freq(priv->base, priv->pclk, info->frequency) < 0)
{
pwmdbg("Cannot set TIMER frequency %dHz from clock %dHz\n",
info->frequency, priv->pclk);
@@ -440,7 +441,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
pwm_putreg(priv, EFM32_TIMER_ROUTE_OFFSET, regval);
regval = (info->duty * pwm_getreg(priv, EFM32_TIMER_TOP_OFFSET)) >> 16;
pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CCV_OFFSET , regval);
pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CCV_OFFSET, regval);
//pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CCVB_OFFSET, regval);
regval = (_TIMER_CC_CTRL_MODE_PWM << _TIMER_CC_CTRL_MODE_SHIFT) | \
@@ -677,19 +678,19 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
switch (priv->timid)
{
case 0:
modifyreg32(EFM32_CMU_HFPERCLKEN0,0,CMU_HFPERCLKEN0_TIMER0);
modifyreg32(EFM32_CMU_HFPERCLKEN0, 0, CMU_HFPERCLKEN0_TIMER0);
break;
case 1:
modifyreg32(EFM32_CMU_HFPERCLKEN0,0,CMU_HFPERCLKEN0_TIMER1);
modifyreg32(EFM32_CMU_HFPERCLKEN0, 0, CMU_HFPERCLKEN0_TIMER1);
break;
case 2:
modifyreg32(EFM32_CMU_HFPERCLKEN0,0,CMU_HFPERCLKEN0_TIMER2);
modifyreg32(EFM32_CMU_HFPERCLKEN0, 0, CMU_HFPERCLKEN0_TIMER2);
break;
case 3:
modifyreg32(EFM32_CMU_HFPERCLKEN0,0,CMU_HFPERCLKEN0_TIMER3);
modifyreg32(EFM32_CMU_HFPERCLKEN0, 0, CMU_HFPERCLKEN0_TIMER3);
break;
default:
@@ -698,7 +699,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
}
efm32_configgpio(priv->pincfg);
pwm_putreg(priv,EFM32_TIMER_ROUTE_OFFSET,BOARD_PWM_TIMER0_PINLOC);
pwm_putreg(priv, EFM32_TIMER_ROUTE_OFFSET, BOARD_PWM_TIMER0_PINLOC);
pwm_dumpgpio(priv->pincfg, "PWM setup");
return OK;
}
arch/arm/src/efm32/efm32_rmu.c
+6 -6
View File
@@ -237,7 +237,7 @@ void efm32_rmu_initialize(void)
/* Now clear reset cause */
putreg32(RMU_CMD_RCCLR,EFM32_RMU_CMD);
putreg32(RMU_CMD_RCCLR, EFM32_RMU_CMD);
/* Clear some reset causes not cleared with RMU CMD register
* (If EMU registers locked, they must be unlocked first)
@@ -248,22 +248,22 @@ void efm32_rmu_initialize(void)
{
/* EMU unlock */
putreg32(EMU_LOCK_LOCKKEY_LOCK,EMU_LOCK_LOCKKEY_UNLOCK);
putreg32(EMU_LOCK_LOCKKEY_LOCK, EMU_LOCK_LOCKKEY_UNLOCK);
}
modifyreg32(EFM32_EMU_AUXCTRL,0,EMU_AUXCTRL_HRCCLR);
modifyreg32(EFM32_EMU_AUXCTRL,EMU_AUXCTRL_HRCCLR,0);
modifyreg32(EFM32_EMU_AUXCTRL, 0, EMU_AUXCTRL_HRCCLR);
modifyreg32(EFM32_EMU_AUXCTRL, EMU_AUXCTRL_HRCCLR, 0);
if (locked)
{
/* EMU lock */
putreg32(EMU_LOCK_LOCKKEY_LOCK,EMU_LOCK_LOCKKEY_LOCK);
putreg32(EMU_LOCK_LOCKKEY_LOCK, EMU_LOCK_LOCKKEY_LOCK);
}
#ifdef CONFIG_EFM32_RMU_DEBUG
rmudbg("RMU => reg = 0x%08X\n", g_efm32_rstcause);
for (;;)
for (; ; )
{
const char *str;
arch/arm/src/efm32/efm32_serial.c
+1 -1
View File
@@ -1019,7 +1019,7 @@ static int efm32_ioctl(struct file *filep, int cmd, unsigned long arg)
/* Just speed is yet implemented */
efm32_disableuartint(priv,&ien);
efm32_disableuartint(priv, &ien);
efm32_uartconfigure(config->uartbase, config->baud, config->parity,
config->bits, config->stop2);
arch/arm/src/efm32/efm32_spi.c
+2 -2
View File
@@ -1288,7 +1288,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
{
/* 16-bit mode */
const uint16_t *src = (const uint16_t *)txbuffer;;
const uint16_t *src = (const uint16_t *)txbuffer;
uint16_t *dest = (uint16_t *)rxbuffer;
uint16_t word;
@@ -1342,7 +1342,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
{
/* 8-bit mode */
const uint8_t *src = (const uint8_t *)txbuffer;;
const uint8_t *src = (const uint8_t *)txbuffer;
uint8_t *dest = (uint8_t *)rxbuffer;
uint8_t word;
arch/arm/src/efm32/efm32_start.c
+1 -1
View File
@@ -312,6 +312,6 @@ void __start(void)
/* Shouldn't get here */
for (;;);
for (; ; );
#endif
}
arch/arm/src/efm32/efm32_timer.c
+5 -5
View File
@@ -215,11 +215,11 @@ void efm32_timer_reset(uintptr_t base)
putreg32(TIMER_DTLOCK_LOCKKEY_UNLOCK, base + EFM32_TIMER_DTLOCK_OFFSET);
putreg32(_TIMER_DTCTRL_RESETVALUE,base + EFM32_TIMER_DTCTRL_OFFSET );
putreg32(_TIMER_DTTIME_RESETVALUE,base + EFM32_TIMER_DTTIME_OFFSET );
putreg32(_TIMER_DTFC_RESETVALUE, base + EFM32_TIMER_DTFC_OFFSET );
putreg32(_TIMER_DTOGEN_RESETVALUE,base + EFM32_TIMER_DTOGEN_OFFSET );
putreg32(_TIMER_DTFAULTC_MASK, base + EFM32_TIMER_DTFAULTC_OFFSET );
putreg32(_TIMER_DTCTRL_RESETVALUE, base + EFM32_TIMER_DTCTRL_OFFSET);
putreg32(_TIMER_DTTIME_RESETVALUE, base + EFM32_TIMER_DTTIME_OFFSET);
putreg32(_TIMER_DTFC_RESETVALUE, base + EFM32_TIMER_DTFC_OFFSET);
putreg32(_TIMER_DTOGEN_RESETVALUE,base + EFM32_TIMER_DTOGEN_OFFSET);
putreg32(_TIMER_DTFAULTC_MASK, base + EFM32_TIMER_DTFAULTC_OFFSET);
#endif
}
arch/arm/src/efm32/efm32_usbdev.c
+12 -10
View File
@@ -1007,7 +1007,7 @@ static void efm32_ep0out_ctrlsetup(FAR struct efm32_usbdev_s *priv)
regval = (USB_SIZEOF_CTRLREQ * 3 << _USB_DOEP0TSIZ_XFERSIZE_SHIFT) |
(USB_DOEP0TSIZ_PKTCNT) |
(3 << _USB_DOEP0TSIZ_SUPCNT_SHIFT);
efm32_putreg(regval,EFM32_USB_DOEP0TSIZ);
efm32_putreg(regval, EFM32_USB_DOEP0TSIZ);
/* Then clear NAKing and enable the transfer */
@@ -1672,7 +1672,7 @@ static void efm32_epout_request(FAR struct efm32_usbdev_s *priv,
* read request is encountered.
*/
for (;;)
for (; ; )
{
/* Get a reference to the request at the head of the endpoint's request queue */
@@ -3475,9 +3475,9 @@ static inline void efm32_otginterrupt(FAR struct efm32_usbdev_s *priv)
regval = efm32_getreg(EFM32_USB_GOTGINT);
if ((regval & OTGFS_GOTGINT_SEDET) != 0)
{
{
#warning "Missing logic"
}
}
/* Clear OTG interrupt */
@@ -3516,7 +3516,7 @@ static int efm32_usbinterrupt(int irq, FAR void *context)
* events.
*/
for (;;)
for (; ; )
{
/* Get the set of pending, un-masked interrupts */
@@ -3531,6 +3531,7 @@ static int efm32_usbinterrupt(int irq, FAR void *context)
{
break;
}
usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_INTPENDING), (uint16_t)regval);
/* OUT endpoint interrupt. The core sets this bit to indicate that an
@@ -3572,7 +3573,7 @@ static int efm32_usbinterrupt(int irq, FAR void *context)
efm32_putreg(USB_GINTSTS_WKUPINT, EFM32_USB_GINTSTS);
}
/* USB suspend interrupt */
/* USB suspend interrupt */
if ((regval & USB_GINTSTS_USBSUSP) != 0)
{
@@ -4757,7 +4758,7 @@ static FAR struct usbdev_ep_s *efm32_ep_alloc(FAR struct usbdev_s *dev,
irqrestore(flags);
return in ? &priv->epin[epno].ep : &priv->epout[epno].ep;
}
}
}
/* We should not get here */
}
@@ -4839,7 +4840,7 @@ static int efm32_wakeup(struct usbdev_s *dev)
regval = efm32_getreg(EFM32_USB_DSTS);
if ((regval & USB_DSTS_SUSPSTS) != 0)
{
/* Re-start the PHY clock and un-gate USB core clock (HCLK) */
/* Re-start the PHY clock and un-gate USB core clock (HCLK) */
#ifdef CONFIG_USBDEV_LOWPOWER
regval = efm32_getreg(EFM32_USB_PCGCCTL);
@@ -5188,7 +5189,7 @@ static void efm32_hwinitialize(FAR struct efm32_usbdev_s *priv)
/* First Turn on USB clocking */
modifyreg32(EFM32_CMU_HFCORECLKEN0,0,
modifyreg32(EFM32_CMU_HFCORECLKEN0, 0,
CMU_HFCORECLKEN0_USB | CMU_HFCORECLKEN0_USBC);
/* At start-up the core is in FS mode. */
@@ -5271,7 +5272,8 @@ static void efm32_hwinitialize(FAR struct efm32_usbdev_s *priv)
/* Set Rx FIFO size */
efm32_putreg(EFM32_RXFIFO_WORDS << _USB_GRXFSIZ_RXFDEP_SHIFT,EFM32_USB_GRXFSIZ);
efm32_putreg(EFM32_RXFIFO_WORDS << _USB_GRXFSIZ_RXFDEP_SHIFT,
EFM32_USB_GRXFSIZ);
/* EP0 TX */
arch/arm/src/efm32/efm32_usbhost.c
+10 -10
View File
@@ -1728,7 +1728,7 @@ static int efm32_ctrl_sendsetup(FAR struct efm32_usbhost_s *priv,
return ret;
}
/* Get the elapsed time (in frames) */
/* Get the elapsed time (in frames) */
elapsed = clock_systimer() - start;
}
@@ -1949,7 +1949,7 @@ static ssize_t efm32_in_transfer(FAR struct efm32_usbhost_s *priv, int chidx,
if (ret < 0)
{
usbhost_trace1(USBHOST_TRACE1_TRNSFRFAILED,ret);
usbhost_trace1(USBHOST_TRACE1_TRNSFRFAILED, ret);
/* Check for a special case: If (1) the transfer was NAKed and (2)
* no Tx FIFO empty or Rx FIFO not-empty event occurred, then we
@@ -2194,7 +2194,7 @@ static ssize_t efm32_out_transfer(FAR struct efm32_usbhost_s *priv, int chidx,
ret = efm32_chan_waitsetup(priv, chan);
if (ret < 0)
{
usbhost_trace1(USBHOST_TRACE1_DEVDISCONN,0);
usbhost_trace1(USBHOST_TRACE1_DEVDISCONN, 0);
return (ssize_t)ret;
}
@@ -2207,7 +2207,7 @@ static ssize_t efm32_out_transfer(FAR struct efm32_usbhost_s *priv, int chidx,
return (ssize_t)ret;
}
/* Wait for the transfer to complete and get the result */
/* Wait for the transfer to complete and get the result */
ret = efm32_chan_wait(priv, chan);
@@ -2215,7 +2215,7 @@ static ssize_t efm32_out_transfer(FAR struct efm32_usbhost_s *priv, int chidx,
if (ret < 0)
{
usbhost_trace1(USBHOST_TRACE1_TRNSFRFAILED,ret);
usbhost_trace1(USBHOST_TRACE1_TRNSFRFAILED, ret);
/* Check for a special case: If (1) the transfer was NAKed and (2)
* no Tx FIFO empty or Rx FIFO not-empty event occurred, then we
@@ -2899,7 +2899,7 @@ static void efm32_gint_connected(FAR struct efm32_usbhost_s *priv)
{
/* Yes.. then now we are connected */
usbhost_vtrace1(USBHOST_VTRACE1_CONNECTED,0);
usbhost_vtrace1(USBHOST_VTRACE1_CONNECTED, 0);
priv->connected = true;
priv->change = true;
DEBUGASSERT(priv->smstate == SMSTATE_DETACHED);
@@ -2931,7 +2931,7 @@ static void efm32_gint_disconnected(FAR struct efm32_usbhost_s *priv)
{
/* Yes.. then we no longer connected */
usbhost_vtrace1(USBHOST_VTRACE1_DISCONNECTED,0);
usbhost_vtrace1(USBHOST_VTRACE1_DISCONNECTED, 0);
/* Are we bound to a class driver? */
@@ -3514,7 +3514,7 @@ static int efm32_gint_isr(int irq, FAR void *context)
* little interrupt handling overhead.
*/
for (;;)
for (; ; )
{
/* Get the unmasked bits in the GINT status */
@@ -3807,7 +3807,7 @@ static int efm32_wait(FAR struct usbhost_connection_s *conn,
/* Loop until a change in connection state is detected */
flags = irqsave();
for (;;)
for (; ; )
{
/* Is there a change in the connection state of the single root hub
* port?
@@ -3901,7 +3901,7 @@ static int efm32_rh_enumerate(FAR struct efm32_usbhost_s *priv,
{
/* No, return an error */
usbhost_trace1(USBHOST_TRACE1_DEVDISCONN,0);
usbhost_trace1(USBHOST_TRACE1_DEVDISCONN, 0);
return -ENODEV;
}
arch/arm/src/imx/imx_serial.c
+1 -1
View File
@@ -834,7 +834,7 @@ static int up_interrupt(int irq, void *context)
* until we have been looping for a long time.
*/
for (;;)
for (; ; )
{
/* Get the current UART status and check for loop
* termination conditions
arch/arm/src/kinetis/kinetis_enet.c
+1 -1
View File
@@ -680,7 +680,7 @@ static void kinetis_txdone(FAR struct kinetis_driver_s *priv)
priv->txtail = 0;
}
/* Update statistics */
/* Update statistics */
EMAC_STAT(priv, tx_done);
}
arch/arm/src/kinetis/kinetis_sdhc.c
+5 -5
View File
@@ -832,9 +832,9 @@ static void kinetis_transmit(struct kinetis_dev_s *priv)
priv->remaining = 0;
}
/* Put the word in the FIFO */
/* Put the word in the FIFO */
putreg32(data.w, KINETIS_SDHC_DATPORT);
putreg32(data.w, KINETIS_SDHC_DATPORT);
}
fllvdbg("Exit: remaining: %d IRQSTAT: %08x\n",
@@ -2426,7 +2426,7 @@ static sdio_eventset_t kinetis_eventwait(FAR struct sdio_dev_s *dev,
* may have already occurred before this function was called!
*/
for (;;)
for (; ; )
{
/* Wait for an event in event set to occur. If this the event has already
* occurred, then the semaphore will already have been incremented and
@@ -2706,8 +2706,8 @@ static void kinetis_callback(void *arg)
/* Media is present. Is the media inserted event enabled? */
if ((priv->cbevents & SDIOMEDIA_INSERTED) == 0)
{
/* No... return without performing the callback */
{
/* No... return without performing the callback */
return;
}
arch/arm/src/kinetis/kinetis_start.c
+1 -1
View File
@@ -165,5 +165,5 @@ void __start(void)
/* Shouldn't get here */
for (;;);
for (; ; );
}
arch/arm/src/kl/kl_lowputc.c
+35 -35
View File
@@ -154,62 +154,62 @@ void kl_lowputc(uint32_t ch)
****************************************************************************/
void kl_lowsetup(void)
{
uint32_t regval;
uint8_t regval8;
uint32_t regval;
uint8_t regval8;
#if 0
regval = getreg32(KL_SIM_SOPT2);
regval |= SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_UART0SRC_MCGCLK ;
putreg32(regval, KL_SIM_SOPT2);
regval = getreg32(KL_SIM_SOPT2);
regval |= SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_UART0SRC_MCGCLK ;
putreg32(regval, KL_SIM_SOPT2);
#endif
regval = getreg32(KL_SIM_SCGC4);
regval = getreg32(KL_SIM_SCGC4);
#ifdef CONFIG_KL_UART0
regval |= SIM_SCGC4_UART0;
regval |= SIM_SCGC4_UART0;
#endif
#ifdef CONFIG_KL_UART1
regval |= SIM_SCGC4_UART1;
regval |= SIM_SCGC4_UART1;
#endif
#ifdef CONFIG_KL_UART2
regval |= SIM_SCGC4_UART2;
regval |= SIM_SCGC4_UART2;
#endif
putreg32(regval, KL_SIM_SCGC4);
putreg32(regval, KL_SIM_SCGC4);
regval = getreg32(KL_SIM_SOPT2);
regval &= ~(SIM_SOPT2_UART0SRC_MASK);
putreg32(regval, KL_SIM_SOPT2);
regval = getreg32(KL_SIM_SOPT2);
regval &= ~(SIM_SOPT2_UART0SRC_MASK);
putreg32(regval, KL_SIM_SOPT2);
regval = getreg32(KL_SIM_SOPT2);
regval |= SIM_SOPT2_UART0SRC_MCGCLK;
putreg32(regval, KL_SIM_SOPT2);
regval = getreg32(KL_SIM_SOPT2);
regval |= SIM_SOPT2_UART0SRC_MCGCLK;
putreg32(regval, KL_SIM_SOPT2);
putreg32((PORT_PCR_MUX_ALT2), KL_PORTA_PCR1);
putreg32((PORT_PCR_MUX_ALT2), KL_PORTA_PCR2);
putreg32((PORT_PCR_MUX_ALT2), KL_PORTA_PCR1);
putreg32((PORT_PCR_MUX_ALT2), KL_PORTA_PCR2);
/* Disable UART before changing registers */
/* Disable UART before changing registers */
putreg8(0, KL_UART0_C2);
putreg8(0, KL_UART0_C1);
putreg8(0, KL_UART0_C3);
putreg8(0, KL_UART0_S2);
putreg8(0, KL_UART0_C2);
putreg8(0, KL_UART0_C1);
putreg8(0, KL_UART0_C3);
putreg8(0, KL_UART0_S2);
/* Set the baud rate divisor */
/* Set the baud rate divisor */
uint16_t divisor = (CONSOLE_FREQ / OVER_SAMPLE) / CONSOLE_BAUD;
regval8 = OVER_SAMPLE - 1;
putreg8(regval8, KL_UART0_C4);
uint16_t divisor = (CONSOLE_FREQ / OVER_SAMPLE) / CONSOLE_BAUD;
regval8 = OVER_SAMPLE - 1;
putreg8(regval8, KL_UART0_C4);
regval8 = (divisor >> 8) & UART_BDH_SBR_MASK;
putreg8(regval8, KL_UART0_BDH);
regval8 = (divisor >> 8) & UART_BDH_SBR_MASK;
putreg8(regval8, KL_UART0_BDH);
regval8 = (divisor & UART_BDL_SBR_MASK);
putreg8(regval8, KL_UART0_BDL);
regval8 = (divisor & UART_BDL_SBR_MASK);
putreg8(regval8, KL_UART0_BDL);
/* Enable UART before changing registers */
/* Enable UART before changing registers */
regval8 = getreg8(KL_UART0_C2);
regval8 |= (UART_C2_RE | UART_C2_TE);
putreg8(regval8, KL_UART0_C2);
regval8 = getreg8(KL_UART0_C2);
regval8 |= (UART_C2_RE | UART_C2_TE);
putreg8(regval8, KL_UART0_C2);
/* Configure the console (only) now. Other UARTs will be configured
* when the serial driver is opened.
arch/arm/src/kl/kl_start.c
+1 -1
View File
@@ -181,6 +181,6 @@ void __start(void)
/* Shoulnd't get here */
for (;;);
for (; ; );
}
arch/arm/src/lpc11xx/lpc11_gpioint.c
+1 -1
View File
@@ -454,7 +454,7 @@ static int lpc11_gpiointerrupt(int irq, void *context)
void lpc11_gpioirqinitialize(void)
{
/* Disable all GPIO interrupts */
/* Disable all GPIO interrupts */
putreg32(0, LPC17_GPIOINT0_INTENR);
putreg32(0, LPC17_GPIOINT0_INTENF);
arch/arm/src/lpc11xx/lpc11_spi.c
+1 -1
View File
@@ -485,7 +485,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
while ((getreg32(LPC11_SPI_SR) & SPI_SR_SPIF) == 0);
/* Read the SPI Status Register again to clear the status bit */
/* Read the SPI Status Register again to clear the status bit */
(void)getreg32(LPC11_SPI_SR);
nwords--;
arch/arm/src/lpc11xx/lpc11_start.c
+1 -1
View File
@@ -171,5 +171,5 @@ void __start(void)
/* Shouldn't get here */
for (;;);
for (; ; );
}
arch/arm/src/lpc11xx/lpc11_timer.c
+15 -15
View File
@@ -400,24 +400,24 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev)
regval = getreg32(LPC17_SYSCON_PCLKSEL0);
regval &= ~(0x3 << 2);
regval |= (0x1 << 2); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */
regval |= (0x1 << 2); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */
regval &= ~(0x3 << 4);
regval |= (0x1 << 4); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */
regval |= (0x1 << 4); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */
putreg32(regval, LPC17_SYSCON_PCLKSEL0);
regval = getreg32(LPC17_SYSCON_PCLKSEL1);
regval &= ~(0x3 << 12);
regval |= (0x1 << 12); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */
regval |= (0x1 << 12); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */
regval &= ~(0x3 << 14);
regval |= (0x1 << 14); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */
regval |= (0x1 << 14); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */
putreg32(regval, LPC17_SYSCON_PCLKSEL1);
priv->pclk = (0x1 << 12) | (0x1 << 4);
putreg32(1000, LPC17_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */
putreg32(1000, LPC17_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */
putreg32(1, LPC17_TMR0_PR); /* Prescaler count frequency: Fpclk/1 */
putreg32(~(0x3 << 0), LPC17_TMR0_CCR); /* Prescaler count frequency: Fpclk/1 */
putreg32(~(0x3 << 0), LPC17_TMR0_CTCR);/* Prescaler count frequency: Fpclk/1 */
putreg32((2 << 3), LPC17_TMR0_MCR); /* Reset on match register MR1 */
putreg32(1, LPC17_TMR0_PR); /* Prescaler count frequency: Fpclk/1 */
putreg32(~(0x3 << 0), LPC17_TMR0_CCR); /* Prescaler count frequency: Fpclk/1 */
putreg32(~(0x3 << 0), LPC17_TMR0_CTCR); /* Prescaler count frequency: Fpclk/1 */
putreg32((2 << 3), LPC17_TMR0_MCR); /* Reset on match register MR1 */
/* Output bit toggle on external match event External match on MR1, Toggle
* external bit
@@ -430,14 +430,14 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev)
lpc11_configgpio(GPIO_MAT0p1_2);
putreg32(500, LPC17_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */
putreg32(500, LPC17_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */
putreg32(1, LPC17_TMR1_PR); /* Prescaler count frequency:Fpclk/1 */
putreg32(~(0x3 << 0), LPC17_TMR1_CCR); /* Prescaler count frequency:Fpclk/1 */
putreg32(~(0x3 << 0), LPC17_TMR1_CTCR);/* Prescaler count frequency:Fpclk/1 */
putreg32((2 << 0), LPC17_TMR1_MCR); /* Reset on match register MR0 */
putreg32(1, LPC17_TMR1_PR); /* Prescaler count frequency:Fpclk/1 */
putreg32(~(0x3 << 0), LPC17_TMR1_CCR); /* Prescaler count frequency:Fpclk/1 */
putreg32(~(0x3 << 0), LPC17_TMR1_CTCR); /* Prescaler count frequency:Fpclk/1 */
putreg32((2 << 0), LPC17_TMR1_MCR); /* Reset on match register MR0 */
// putreg32(((1 << 0) | (3 << 4)), LPC17_TMR1_EMR); /* Output bit toggle on external match event MAT0 */
putreg32((1 << 0), LPC17_TMR1_TCR); /* Start timer1 */
putreg32((1 << 0), LPC17_TMR1_TCR); /* Start timer1 */
/* configure the output pins GPIO3.26 */
// lpc11_configgpio(GPIO_MAT0p1_2);
arch/arm/src/lpc17xx/lpc176x_clockconfig.c
+6 -7
View File
@@ -138,14 +138,14 @@ void lpc17_clockconfig(void)
/* Enable and connect PLL0 */
putreg32(SYSCON_PLLCON_PLLE|SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL0CON);
putreg32(SYSCON_PLLCON_PLLE | SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL0CON);
putreg32(0xaa, LPC17_SYSCON_PLL0FEED);
putreg32(0x55, LPC17_SYSCON_PLL0FEED);
/* Wait for PLL to report that it is connected and enabled */
while ((getreg32(LPC17_SYSCON_PLL0STAT) & (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC))
!= (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC));
while ((getreg32(LPC17_SYSCON_PLL0STAT) & (SYSCON_PLL0STAT_PLLE | SYSCON_PLL0STAT_PLLC))
!= (SYSCON_PLL0STAT_PLLE | SYSCON_PLL0STAT_PLLC));
#endif /* CONFIG_LPC17_PLL0 */
@@ -178,14 +178,14 @@ void lpc17_clockconfig(void)
/* Enable and connect PLL1 */
putreg32(SYSCON_PLLCON_PLLE|SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL1CON);
putreg32(SYSCON_PLLCON_PLLE | SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL1CON);
putreg32(0xaa, LPC17_SYSCON_PLL1FEED);
putreg32(0x55, LPC17_SYSCON_PLL1FEED);
/* Wait for PLL to report that it is connected and enabled */
while ((getreg32(LPC17_SYSCON_PLL1STAT) & (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC))
!= (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC));
while ((getreg32(LPC17_SYSCON_PLL1STAT) & (SYSCON_PLL1STAT_PLLE | SYSCON_PLL1STAT_PLLC))
!= (SYSCON_PLL1STAT_PLLE | SYSCON_PLL1STAT_PLLC));
#else /* CONFIG_LPC17_PLL1 */
@@ -218,4 +218,3 @@ void lpc17_clockconfig(void)
putreg32(BOARD_FLASHCFG_VALUE, LPC17_SYSCON_FLASHCFG);
#endif
}
arch/arm/src/lpc17xx/lpc178x_gpio.c
+2 -1
View File
@@ -217,7 +217,8 @@ static uint32_t lpc17_getioconmask(unsigned int port, unsigned int pin)
*
****************************************************************************/
static void lpc17_seti2cmode(unsigned int port,unsigned int pin, uint32_t value)
static void lpc17_seti2cmode(unsigned int port, unsigned int pin,
uint32_t value)
{
uint32_t regaddr;
uint32_t regval;
arch/arm/src/lpc17xx/lpc17_adc.c
+4 -4
View File
@@ -383,7 +383,7 @@ static int adc_interrupt(int irq, void *context)
{
value = priv->buf[ch] / priv->count[ch];
value <<= 15;
adc_receive(&g_adcdev,ch,value);
adc_receive(&g_adcdev, ch, value);
priv->buf[ch] = 0;
priv->count[ch] = 0;
}
@@ -408,7 +408,7 @@ static int adc_interrupt(int irq, void *context)
{
value = priv->buf[ch] / priv->count[ch];
value <<= 15;
adc_receive(&g_adcdev,ch,value);
adc_receive(&g_adcdev, ch, value);
priv->buf[ch] = 0;
priv->count[ch] = 0;
}
@@ -424,7 +424,7 @@ static int adc_interrupt(int irq, void *context)
/* Verify that an interrupt has actually occured */
regVal2 = getreg32(LPC17_ADC_STAT); /* Read ADSTAT will clear the interrupt flag */
if ((regVal2) & (1<<16))
if ((regVal2) & (1 << 16))
{
if ((priv->mask & 0x01) != 0)
{
@@ -563,7 +563,7 @@ static int adc_interrupt(int irq, void *context)
regVal3 = getreg32(LPC17_ADC_GDR); /* Read ADGDR clear the DONE and OVERRUN bits */
putreg32((priv->mask) | /* Select channels 0 to 7 on ADC0 */
((32) << 8) | /* CLKDIV = 16 */
(32 << 8) | /* CLKDIV = 16 */
(0 << 16) | /* BURST = 1, BURST capture all selected channels */
(1 << 17) | /* Reserved bit = 0 */
(1 << 21) | /* PDN = 1, normal operation */
arch/arm/src/lpc17xx/lpc17_allocateheap.c
+6 -6
View File
@@ -250,7 +250,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)ubase;
*heap_start = (FAR void *)ubase;
*heap_size = usize;
/* Allow user-mode access to the user heap memory */
@@ -261,7 +261,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif
}
@@ -305,7 +305,7 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
* that was not dedicated to the user heap).
*/
*heap_start = (FAR void*)USERSPACE->us_bssend;
*heap_start = (FAR void *)USERSPACE->us_bssend;
*heap_size = ubase - (uintptr_t)USERSPACE->us_bssend;
}
#endif
@@ -345,17 +345,17 @@ void up_addregion(void)
/* Add the AHB SRAM user heap region. */
kumm_addregion((FAR void*)LPC17_AHB_HEAPBASE, LPC17_AHB_HEAPSIZE);
kumm_addregion((FAR void *)LPC17_AHB_HEAPBASE, LPC17_AHB_HEAPSIZE);
#endif
#if CONFIG_MM_REGIONS >= 3
#if defined(CONFIG_LPC17_EXTDRAM) && defined(CONFIG_LPC17_EXTDRAMHEAP)
kmm_addregion((FAR void*)LPC17_EXTDRAM_CS0, CONFIG_LPC17_EXTDRAMSIZE);
kmm_addregion((FAR void *)LPC17_EXTDRAM_CS0, CONFIG_LPC17_EXTDRAMSIZE);
#endif
#if !defined(CONFIG_LPC17_EXTDRAMHEAP) || (CONFIG_MM_REGIONS >= 4)
#if defined(CONFIG_LPC17_EXTSRAM0) && defined(CONFIG_LPC17_EXTSRAM0HEAP)
kmm_addregion((FAR void*)LPC17_EXTSRAM_CS0, CONFIG_LPC17_EXTSRAM0SIZE);
kmm_addregion((FAR void *)LPC17_EXTSRAM_CS0, CONFIG_LPC17_EXTSRAM0SIZE);
#endif
#endif
#endif
arch/arm/src/lpc17xx/lpc17_can.c
+16 -15
View File
@@ -335,20 +335,20 @@ static void can_printreg(uint32_t addr, uint32_t value)
else
{
/* Did we print "..." for the previous value? */
/* Did we print "..." for the previous value? */
if (count > 3)
{
/* Yes.. then show how many times the value repeated */
if (count > 3)
{
/* Yes.. then show how many times the value repeated */
lldbg("[repeats %d more times]\n", count-3);
}
lldbg("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
/* Save the new address, value, and count */
prevaddr = addr;
preval = value;
count = 1;
prevaddr = addr;
preval = value;
count = 1;
}
/* Show the register value read */
@@ -616,9 +616,9 @@ static void can_rxint(FAR struct can_dev_s *dev, bool enable)
canvdbg("CAN%d enable: %d\n", priv->port, enable);
/* The EIR register is also modifed from the interrupt handler, so we have
* to protect this code section.
*/
/* The EIR register is also modifed from the interrupt handler, so we have
* to protect this code section.
*/
flags = irqsave();
regval = can_getreg(priv, LPC17_CAN_IER_OFFSET);
@@ -630,6 +630,7 @@ static void can_rxint(FAR struct can_dev_s *dev, bool enable)
{
regval &= ~CAN_IER_RIE;
}
can_putreg(priv, LPC17_CAN_IER_OFFSET, regval);
irqrestore(flags);
}
@@ -829,7 +830,7 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
regval |= CAN_IER_TIE2;
can_putreg(priv, LPC17_CAN_IER_OFFSET, regval);
/* Set up the transfer */
/* Set up the transfer */
can_putreg(priv, LPC17_CAN_TFI2_OFFSET, tfi);
can_putreg(priv, LPC17_CAN_TID2_OFFSET, tid);
@@ -1185,7 +1186,7 @@ static int can_bittiming(struct up_dev_s *priv)
{
ts1 = CONFIG_CAN_TSEG1;
ts2 = CONFIG_CAN_TSEG2;
brp = (nclks + (CAN_BIT_QUANTA/2)) / CAN_BIT_QUANTA;
brp = (nclks + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA;
DEBUGASSERT(brp >=1 && brp <= CAN_BTR_BRP_MAX);
}
arch/arm/src/lpc17xx/lpc17_dac.c
+6 -6
View File
@@ -91,12 +91,12 @@ static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg);
static const struct dac_ops_s g_dacops =
{
.ao_reset =dac_reset,
.ao_setup = dac_setup,
.ao_reset = dac_reset,
.ao_setup = dac_setup,
.ao_shutdown = dac_shutdown,
.ao_txint = dac_txint,
.ao_send = dac_send,
.ao_ioctl = dac_ioctl,
.ao_txint = dac_txint,
.ao_send = dac_send,
.ao_ioctl = dac_ioctl,
};
static struct dac_dev_s g_dacdev =
@@ -124,7 +124,7 @@ static void dac_reset(FAR struct dac_dev_s *dev)
regval |= (SYSCON_PCLKSEL_CCLK8 << SYSCON_PCLKSEL0_DAC_SHIFT);
putreg32(regval, LPC17_SYSCON_PCLKSEL0);
//putreg32(DAC_CTRL_DBLBUFEN,LPC17_DAC_CTRL); ?
//putreg32(DAC_CTRL_DBLBUFEN, LPC17_DAC_CTRL); ?
lpc17_configgpio(GPIO_AOUT);
arch/arm/src/lpc17xx/lpc17_ethernet.c
+19 -19
View File
@@ -599,7 +599,7 @@ static int lpc17_txdesc(struct lpc17_driver_s *priv)
prodidx = lpc17_getreg(LPC17_ETH_TXPRODIDX) & ETH_TXPRODIDX_MASK;
if (++prodidx >= CONFIG_NET_NTXDESC)
{
/* Wrap back to index zero */
/* Wrap back to index zero */
prodidx = 0;
}
@@ -659,8 +659,8 @@ static int lpc17_transmit(struct lpc17_driver_s *priv)
* fields.
*/
txdesc = (uint32_t*)(LPC17_TXDESC_BASE + (prodidx << 3));
txbuffer = (void*)*txdesc++;
txdesc = (uint32_t *)(LPC17_TXDESC_BASE + (prodidx << 3));
txbuffer = (void *)*txdesc++;
*txdesc = TXDESC_CONTROL_INT | TXDESC_CONTROL_LAST | TXDESC_CONTROL_CRC |
(priv->lp_dev.d_len - 1);
@@ -682,7 +682,7 @@ static int lpc17_transmit(struct lpc17_driver_s *priv)
if (++prodidx >= CONFIG_NET_NTXDESC)
{
/* Wrap back to index zero */
/* Wrap back to index zero */
prodidx = 0;
}
@@ -873,7 +873,7 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv)
/* Get the Rx status and packet length (-4+1) */
rxstat = (uint32_t*)(LPC17_RXSTAT_BASE + (considx << 3));
rxstat = (uint32_t *)(LPC17_RXSTAT_BASE + (considx << 3));
pktlen = (*rxstat & RXSTAT_INFO_RXSIZE_MASK) - 3;
/* Check for errors. NOTE: The DMA engine reports bogus length errors,
@@ -920,8 +920,8 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv)
/* Get the Rx buffer address from the Rx descriptor */
rxdesc = (uint32_t*)(LPC17_RXDESC_BASE + (considx << 3));
rxbuffer = (void*)*rxdesc;
rxdesc = (uint32_t *)(LPC17_RXDESC_BASE + (considx << 3));
rxbuffer = (void *)*rxdesc;
/* Copy the data data from the EMAC DMA RAM to priv->lp_dev.d_buf.
* Set amount of data in priv->lp_dev.d_len
@@ -1059,8 +1059,8 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv)
*/
if (++considx >= CONFIG_NET_NRXDESC)
{
/* Wrap back to index zero */
{
/* Wrap back to index zero */
considx = 0;
}
@@ -1245,7 +1245,7 @@ static int lpc17_interrupt(int irq, void *context)
* error.
*/
if ((status & (ETH_INT_RXOVR|ETH_INT_TXUNR)) != 0)
if ((status & (ETH_INT_RXOVR | ETH_INT_TXUNR)) != 0)
{
if ((status & ETH_INT_RXOVR) != 0)
{
@@ -1259,7 +1259,7 @@ static int lpc17_interrupt(int irq, void *context)
EMAC_STAT(priv, tx_underrun);
}
/* ifup() will reset the EMAC and bring it back up */
/* ifup() will reset the EMAC and bring it back up */
(void)lpc17_ifup(&priv->lp_dev);
}
@@ -2334,8 +2334,8 @@ static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac)
#if defined(CONFIG_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO)
static void lpc17_showpins(void)
{
lpc17_dumpgpio(GPIO_PORT1|GPIO_PIN0, "P1[1-15]");
lpc17_dumpgpio(GPIO_PORT1|GPIO_PIN16, "P1[16-31]");
lpc17_dumpgpio(GPIO_PORT1 | GPIO_PIN0, "P1[1-15]");
lpc17_dumpgpio(GPIO_PORT1 | GPIO_PIN16, "P1[16-31]");
}
#endif
@@ -2449,7 +2449,7 @@ static uint16_t lpc17_phyread(uint8_t phyaddr, uint8_t regaddr)
/* Wait for the PHY command to complete */
while ((lpc17_getreg(LPC17_ETH_MIND) & (ETH_MIND_BUSY|ETH_MIND_NVALID)) != 0);
while ((lpc17_getreg(LPC17_ETH_MIND) & (ETH_MIND_BUSY | ETH_MIND_NVALID)) != 0);
lpc17_putreg(0, LPC17_ETH_MCMD);
/* Return the PHY register data */
@@ -2970,7 +2970,7 @@ static inline void lpc17_txdescinit(struct lpc17_driver_s *priv)
/* Initialize Tx descriptors and link to packet buffers */
txdesc = (uint32_t*)LPC17_TXDESC_BASE;
txdesc = (uint32_t *)LPC17_TXDESC_BASE;
pktaddr = LPC17_TXBUFFER_BASE;
for (i = 0; i < CONFIG_NET_NTXDESC; i++)
@@ -2982,7 +2982,7 @@ static inline void lpc17_txdescinit(struct lpc17_driver_s *priv)
/* Initialize Tx status */
txstat = (uint32_t*)LPC17_TXSTAT_BASE;
txstat = (uint32_t *)LPC17_TXSTAT_BASE;
for (i = 0; i < CONFIG_NET_NTXDESC; i++)
{
*txstat++ = 0;
@@ -3026,7 +3026,7 @@ static inline void lpc17_rxdescinit(struct lpc17_driver_s *priv)
/* Initialize Rx descriptors and link to packet buffers */
rxdesc = (uint32_t*)LPC17_RXDESC_BASE;
rxdesc = (uint32_t *)LPC17_RXDESC_BASE;
pktaddr = LPC17_RXBUFFER_BASE;
for (i = 0; i < CONFIG_NET_NRXDESC; i++)
@@ -3038,7 +3038,7 @@ static inline void lpc17_rxdescinit(struct lpc17_driver_s *priv)
/* Initialize Rx status */
rxstat = (uint32_t*)LPC17_RXSTAT_BASE;
rxstat = (uint32_t *)LPC17_RXSTAT_BASE;
for (i = 0; i < CONFIG_NET_NRXDESC; i++)
{
*rxstat++ = 0;
@@ -3264,7 +3264,7 @@ static inline int lpc17_ethinitialize(int intf)
priv->lp_dev.d_addmac = lpc17_addmac; /* Add multicast MAC address */
priv->lp_dev.d_rmmac = lpc17_rmmac; /* Remove multicast MAC address */
#endif
priv->lp_dev.d_private = (void*)priv; /* Used to recover private state from dev */
priv->lp_dev.d_private = (void *)priv; /* Used to recover private state from dev */
#if CONFIG_LPC17_NINTERFACES > 1
# error "A mechanism to associate base address an IRQ with an interface is needed"
arch/arm/src/lpc17xx/lpc17_gpdma.c
+2 -2
View File
@@ -519,7 +519,7 @@ int lpc17_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config,
* interrupt enable bit which is controlled by the driver.
*/
regval = control & ~(DMACH_CONTROL_XFRSIZE_MASK|DMACH_CONTROL_I);
regval = control & ~(DMACH_CONTROL_XFRSIZE_MASK | DMACH_CONTROL_I);
regval |= ((uint32_t)nxfrs << DMACH_CONTROL_XFRSIZE_SHIFT);
putreg32(regval, base + LPC17_DMACH_CONTROL_OFFSET);
@@ -535,7 +535,7 @@ int lpc17_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config,
* are provided by the caller. Little endian is assumed.
*/
regval = config & (DMACH_CONFIG_SRCPER_MASK|DMACH_CONFIG_DSTPER_MASK|
regval = config & (DMACH_CONFIG_SRCPER_MASK | DMACH_CONFIG_DSTPER_MASK |
DMACH_CONFIG_XFRTYPE_MASK);
putreg32(regval, base + LPC17_DMACH_CONFIG_OFFSET);
arch/arm/src/lpc17xx/lpc17_gpioint.c
+1 -1
View File
@@ -454,7 +454,7 @@ static int lpc17_gpiointerrupt(int irq, void *context)
void lpc17_gpioirqinitialize(void)
{
/* Disable all GPIO interrupts */
/* Disable all GPIO interrupts */
putreg32(0, LPC17_GPIOINT0_INTENR);
putreg32(0, LPC17_GPIOINT0_INTENF);
arch/arm/src/lpc17xx/lpc17_i2c.c
+10 -10
View File
@@ -223,7 +223,7 @@ static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int bufle
priv->wrcnt = 0;
priv->rdcnt = 0;
priv->msg.addr &= ~0x01;
priv->msg.buffer = (uint8_t*)buffer;
priv->msg.buffer = (uint8_t *)buffer;
priv->msg.length = buflen;
ret = i2c_start(priv);
@@ -344,21 +344,21 @@ static int i2c_interrupt(int irq, FAR void *context)
#ifdef CONFIG_LPC17_I2C0
if (irq == LPC17_IRQ_I2C0)
{
priv=&i2cdevices[0];
priv = &i2cdevices[0];
}
else
#endif
#ifdef CONFIG_LPC17_I2C1
if (irq == LPC17_IRQ_I2C1)
{
priv=&i2cdevices[1];
priv = &i2cdevices[1];
}
else
#endif
#ifdef CONFIG_LPC17_I2C2
if (irq == LPC17_IRQ_I2C2)
{
priv=&i2cdevices[2];
priv = &i2cdevices[2];
}
else
#endif
@@ -366,7 +366,7 @@ static int i2c_interrupt(int irq, FAR void *context)
PANIC();
}
/* Reference UM10360 19.10.5 */
/* Reference UM10360 19.10.5 */
state = getreg32(priv->base + LPC17_I2C_STAT_OFFSET);
putreg32(I2C_CONCLR_SIC, priv->base + LPC17_I2C_CONCLR_OFFSET);
@@ -396,7 +396,7 @@ static int i2c_interrupt(int irq, FAR void *context)
case 0x28:
priv->wrcnt++;
if (priv->wrcnt<priv->msg.length)
if (priv->wrcnt < priv->msg.length)
{
putreg32(priv->msg.buffer[priv->wrcnt], priv->base + LPC17_I2C_DAT_OFFSET);
}
@@ -462,11 +462,11 @@ struct i2c_dev_s *up_i2cinitialize(int port)
flags = irqsave();
priv= &i2cdevices[port];
priv = &i2cdevices[port];
#ifdef CONFIG_LPC17_I2C0
if (port == 0)
{
priv= (FAR struct lpc17_i2cdev_s *)&i2cdevices[0];
priv = (FAR struct lpc17_i2cdev_s *)&i2cdevices[0];
priv->base = LPC17_I2C0_BASE;
priv->irqid = LPC17_IRQ_I2C0;
@@ -490,7 +490,7 @@ struct i2c_dev_s *up_i2cinitialize(int port)
#ifdef CONFIG_LPC17_I2C1
if (port == 1)
{
priv= (FAR struct lpc17_i2cdev_s *)&i2cdevices[1];
priv = (FAR struct lpc17_i2cdev_s *)&i2cdevices[1];
priv->base = LPC17_I2C1_BASE;
priv->irqid = LPC17_IRQ_I2C1;
@@ -514,7 +514,7 @@ struct i2c_dev_s *up_i2cinitialize(int port)
#ifdef CONFIG_LPC17_I2C2
if (port == 2)
{
priv= (FAR struct lpc17_i2cdev_s *)&i2cdevices[2];
priv = (FAR struct lpc17_i2cdev_s *)&i2cdevices[2];
priv->base = LPC17_I2C2_BASE;
priv->irqid = LPC17_IRQ_I2C2;
arch/arm/src/lpc17xx/lpc17_irq.c
+4 -4
View File
@@ -60,9 +60,9 @@
/* Get a 32-bit version of the default priority */
#define DEFPRIORITY32 \
(NVIC_SYSH_PRIORITY_DEFAULT << 24 |\
NVIC_SYSH_PRIORITY_DEFAULT << 16 |\
NVIC_SYSH_PRIORITY_DEFAULT << 8 |\
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | \
NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
NVIC_SYSH_PRIORITY_DEFAULT << 8 | \
NVIC_SYSH_PRIORITY_DEFAULT)
/* Given the address of a NVIC ENABLE register, this is the offset to
@@ -373,7 +373,7 @@ void up_irqinitialize(void)
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(LPC17_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
/* up_prioritize_irq(LPC17_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
#ifdef CONFIG_ARMV7M_USEBASEPRI
lpc17_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
arch/arm/src/lpc17xx/lpc17_lcd.c
+2 -2
View File
@@ -780,14 +780,14 @@ void lpc17_lcdclear(nxgl_mxpixel_t color)
{
int i;
#if LPC17_BPP > 16
uint32_t *dest = (uint32_t*)CONFIG_LPC17_LCD_VRAMBASE;
uint32_t *dest = (uint32_t *)CONFIG_LPC17_LCD_VRAMBASE;
gvdbg("Clearing display: color=%08x VRAM=%08x size=%d\n",
color, CONFIG_LPC17_LCD_VRAMBASE,
CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT * sizeof(uint32_t));
#else
uint16_t *dest = (uint16_t*)CONFIG_LPC17_LCD_VRAMBASE;
uint16_t *dest = (uint16_t *)CONFIG_LPC17_LCD_VRAMBASE;
gvdbg("Clearing display: color=%08x VRAM=%08x size=%d\n",
color, CONFIG_LPC17_LCD_VRAMBASE,
arch/arm/src/lpc17xx/lpc17_lowputc.c
+16 -13
View File
@@ -314,8 +314,8 @@ void lpc17_lowsetup(void)
*/
regval = getreg32(LPC17_SYSCON_PCONP);
regval &= ~(SYSCON_PCONP_PCUART0|SYSCON_PCONP_PCUART1|
SYSCON_PCONP_PCUART2|SYSCON_PCONP_PCUART3);
regval &= ~(SYSCON_PCONP_PCUART0 | SYSCON_PCONP_PCUART1 |
SYSCON_PCONP_PCUART2 | SYSCON_PCONP_PCUART3);
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
regval |= SYSCON_PCONP_PCUART0;
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
@@ -333,7 +333,7 @@ void lpc17_lowsetup(void)
#ifdef LPC176x
regval = getreg32(LPC17_SYSCON_PCLKSEL0);
regval &= ~(SYSCON_PCLKSEL0_UART0_MASK|SYSCON_PCLKSEL0_UART1_MASK);
regval &= ~(SYSCON_PCLKSEL0_UART0_MASK | SYSCON_PCLKSEL0_UART1_MASK);
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
regval |= (CONSOLE_CCLKDIV << SYSCON_PCLKSEL0_UART0_SHIFT);
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
@@ -342,7 +342,7 @@ void lpc17_lowsetup(void)
putreg32(regval, LPC17_SYSCON_PCLKSEL0);
regval = getreg32(LPC17_SYSCON_PCLKSEL1);
regval &= ~(SYSCON_PCLKSEL1_UART2_MASK|SYSCON_PCLKSEL1_UART3_MASK);
regval &= ~(SYSCON_PCLKSEL1_UART2_MASK | SYSCON_PCLKSEL1_UART3_MASK);
#if defined(CONFIG_UART2_SERIAL_CONSOLE)
regval |= (CONSOLE_CCLKDIV << SYSCON_PCLKSEL1_UART2_SHIFT);
#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
@@ -381,31 +381,34 @@ void lpc17_lowsetup(void)
/* Clear fifos */
putreg32(UART_FCR_RXRST|UART_FCR_TXRST, CONSOLE_BASE+LPC17_UART_FCR_OFFSET);
putreg32(UART_FCR_RXRST | UART_FCR_TXRST,
CONSOLE_BASE + LPC17_UART_FCR_OFFSET);
/* Set trigger */
putreg32(UART_FCR_FIFOEN|UART_FCR_RXTRIGGER_8, CONSOLE_BASE+LPC17_UART_FCR_OFFSET);
putreg32(UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8,
CONSOLE_BASE + LPC17_UART_FCR_OFFSET);
/* Set up the LCR and set DLAB=1 */
putreg32(CONSOLE_LCR_VALUE|UART_LCR_DLAB, CONSOLE_BASE+LPC17_UART_LCR_OFFSET);
putreg32(CONSOLE_LCR_VALUE | UART_LCR_DLAB,
CONSOLE_BASE + LPC17_UART_LCR_OFFSET);
/* Set the BAUD divisor */
putreg32(CONSOLE_DL >> 8, CONSOLE_BASE+LPC17_UART_DLM_OFFSET);
putreg32(CONSOLE_DL & 0xff, CONSOLE_BASE+LPC17_UART_DLL_OFFSET);
putreg32(CONSOLE_DL >> 8, CONSOLE_BASE + LPC17_UART_DLM_OFFSET);
putreg32(CONSOLE_DL & 0xff, CONSOLE_BASE + LPC17_UART_DLL_OFFSET);
/* Clear DLAB */
putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE+LPC17_UART_LCR_OFFSET);
putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE + LPC17_UART_LCR_OFFSET);
/* Configure the FIFOs */
putreg32(UART_FCR_RXTRIGGER_8|UART_FCR_TXRST|UART_FCR_RXRST|UART_FCR_FIFOEN,
CONSOLE_BASE+LPC17_UART_FCR_OFFSET);
putreg32(UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST | UART_FCR_RXRST |
UART_FCR_FIFOEN,
CONSOLE_BASE + LPC17_UART_FCR_OFFSET);
#endif
#endif /* HAVE_UART */
}
arch/arm/src/lpc17xx/lpc17_mcpwm.c
+37 -37
View File
@@ -179,7 +179,7 @@ static struct lpc17_mcpwmtimer_s g_pwm1dev =
.timtype = TIMTYPE_TIM1,
.base = LPC17_MCPWM_BASE,
.pincfg = GPIO_MCPWM_MCOA0,
.pclk = (0x1<<12),
.pclk = (1 << 12),
};
#endif
@@ -435,22 +435,22 @@ static int mcpwm_setup(FAR struct pwm_lowerhalf_s *dev)
regval = getreg32(LPC17_SYSCON_PCLKSEL1);
regval &= ~(0x3 << 30);
regval |= (0x2 << 30); /* PCLK_MC peripheral clk = CCLK/2 = 50 MHz */
regval |= (0x2 << 30); /* PCLK_MC peripheral clk = CCLK/2 = 50 MHz */
putreg32(regval, LPC17_SYSCON_PCLKSEL1);
priv->pclk = (0x1 << 12) | (0x1 << 4);
putreg32((1 << 15), LPC17_MCPWM_INTENCLR); /* Disable MCABORT pin interrupt */
putreg32((1 << 0), LPC17_MCPWM_INTENCLR); /* Disable ILIM0 interrupt */
putreg32((1 << 1), LPC17_MCPWM_INTENCLR); /* Disable IMAT0 interrupt */
putreg32((1 << 2), LPC17_MCPWM_INTENCLR); /* Disable ICAP0 interrupt */
putreg32((1 << 4), LPC17_MCPWM_INTENCLR); /* Disable ILIM1 interrupt */
putreg32((1 << 5), LPC17_MCPWM_INTENCLR); /* Disable IMAT1 interrupt */
putreg32((1 << 6), LPC17_MCPWM_INTENCLR); /* Disable ICAP1 interrupt */
putreg32((1 << 8), LPC17_MCPWM_INTENCLR); /* Disable ILIM2 interrupt */
putreg32((1 << 9), LPC17_MCPWM_INTENCLR); /* Disable IMAT2 interrupt */
putreg32((1 << 10), LPC17_MCPWM_INTENCLR); /* Disable ICAP2 interrupt */
putreg32((1 << 15), LPC17_MCPWM_INTENCLR); /* Disable MCABORT pin interrupt */
putreg32((1 << 0), LPC17_MCPWM_INTENCLR); /* Disable ILIM0 interrupt */
putreg32((1 << 1), LPC17_MCPWM_INTENCLR); /* Disable IMAT0 interrupt */
putreg32((1 << 2), LPC17_MCPWM_INTENCLR); /* Disable ICAP0 interrupt */
putreg32((1 << 4), LPC17_MCPWM_INTENCLR); /* Disable ILIM1 interrupt */
putreg32((1 << 5), LPC17_MCPWM_INTENCLR); /* Disable IMAT1 interrupt */
putreg32((1 << 6), LPC17_MCPWM_INTENCLR); /* Disable ICAP1 interrupt */
putreg32((1 << 8), LPC17_MCPWM_INTENCLR); /* Disable ILIM2 interrupt */
putreg32((1 << 9), LPC17_MCPWM_INTENCLR); /* Disable IMAT2 interrupt */
putreg32((1 << 10), LPC17_MCPWM_INTENCLR); /* Disable ICAP2 interrupt */
putreg32((0xFFFFFFFF), LPC17_MCPWM_CAPCLR);/* Clear all event capture */
putreg32((0xFFFFFFFF), LPC17_MCPWM_CAPCLR); /* Clear all event capture */
/* Configure the output pins */
@@ -459,39 +459,39 @@ static int mcpwm_setup(FAR struct pwm_lowerhalf_s *dev)
/* Program the timing registers */
putreg32((1 << 0), LPC17_MCPWM_CONCLR); /* Stop MCPWM timer0 */
putreg32((1 << 8), LPC17_MCPWM_CONCLR); /* Stop MCPWM timer1 */
putreg32((1 << 16), LPC17_MCPWM_CONCLR); /* Stop MCPWM timer2 */
putreg32((1 << 0), LPC17_MCPWM_CONCLR); /* Stop MCPWM timer0 */
putreg32((1 << 8), LPC17_MCPWM_CONCLR); /* Stop MCPWM timer1 */
putreg32((1 << 16), LPC17_MCPWM_CONCLR); /* Stop MCPWM timer2 */
putreg32((1 << 30), LPC17_MCPWM_CONCLR); /* MCPWM not in AC mode */
putreg32((1 << 30), LPC17_MCPWM_CONCLR); /* MCPWM not in AC mode */
putreg32(1000, LPC17_MCPWM_TC0); /* Count frequency: Fpclk/1000 = 50 MHz/1000 = 50 KHz */
putreg32(400, LPC17_MCPWM_LIM0); /* Set the starting duty cycle to 0.25 */
putreg32(0, LPC17_MCPWM_MAT0); /* Reset the timer */
putreg32(1000, LPC17_MCPWM_TC0); /* Count frequency: Fpclk/1000 = 50 MHz/1000 = 50 KHz */
putreg32(400, LPC17_MCPWM_LIM0); /* Set the starting duty cycle to 0.25 */
putreg32(0, LPC17_MCPWM_MAT0); /* Reset the timer */
putreg32(100000, LPC17_MCPWM_TC1); /* Count frequency:Fpclk/100000 = 50 MHz/100000 = 500 Hz */
putreg32(50000, LPC17_MCPWM_LIM1); /* Set the starting duty cycle to 0.5 */
putreg32(0, LPC17_MCPWM_MAT1); /* Reset the timer */
putreg32(100000, LPC17_MCPWM_TC1); /* Count frequency:Fpclk/100000 = 50 MHz/100000 = 500 Hz */
putreg32(50000, LPC17_MCPWM_LIM1); /* Set the starting duty cycle to 0.5 */
putreg32(0, LPC17_MCPWM_MAT1); /* Reset the timer */
putreg32(1000, LPC17_MCPWM_TC2); /* Count frequency:Fpclk/1000 = 50 MHz/1000 = 50 KHz */
putreg32(400, LPC17_MCPWM_LIM2); /* Set the starting duty cycle to 0.25 */
putreg32(0, LPC17_MCPWM_MAT2); /* Reset the timer */
putreg32(1000, LPC17_MCPWM_TC2); /* Count frequency:Fpclk/1000 = 50 MHz/1000 = 50 KHz */
putreg32(400, LPC17_MCPWM_LIM2); /* Set the starting duty cycle to 0.25 */
putreg32(0, LPC17_MCPWM_MAT2); /* Reset the timer */
putreg32((1 << 2), LPC17_MCPWM_CONCLR); /* Channel 0 polarity set to default */
putreg32((1 << 10), LPC17_MCPWM_CONCLR); /* Channel 1 polarity set to default */
putreg32((1 << 18), LPC17_MCPWM_CONCLR); /* Channel 2 polarity set to default */
putreg32((1 << 2), LPC17_MCPWM_CONCLR); /* Channel 0 polarity set to default */
putreg32((1 << 10), LPC17_MCPWM_CONCLR); /* Channel 1 polarity set to default */
putreg32((1 << 18), LPC17_MCPWM_CONCLR); /* Channel 2 polarity set to default */
putreg32((1 << 3), LPC17_MCPWM_CONCLR); /* Channel 0 dead time disabled */
putreg32((1 << 11), LPC17_MCPWM_CONCLR); /* Channel 1 dead time disabled */
putreg32((1 << 19), LPC17_MCPWM_CONCLR); /* Channel 2 dead time disabled */
putreg32((1 << 3), LPC17_MCPWM_CONCLR); /* Channel 0 dead time disabled */
putreg32((1 << 11), LPC17_MCPWM_CONCLR); /* Channel 1 dead time disabled */
putreg32((1 << 19), LPC17_MCPWM_CONCLR); /* Channel 2 dead time disabled */
putreg32((1 << 1), LPC17_MCPWM_CONCLR); /* Channel 0 edge aligned */
putreg32((1 << 9), LPC17_MCPWM_CONCLR); /* Channel 1 edge aligned */
putreg32((1 << 17), LPC17_MCPWM_CONCLR); /* Channel 2 edge aligned */
putreg32((1 << 1), LPC17_MCPWM_CONCLR); /* Channel 0 edge aligned */
putreg32((1 << 9), LPC17_MCPWM_CONCLR); /* Channel 1 edge aligned */
putreg32((1 << 17), LPC17_MCPWM_CONCLR); /* Channel 2 edge aligned */
putreg32((0xFFFFFFFF), LPC17_MCPWM_CNTCONCLR);/* All channels in counter mode on PCLK */
putreg32((0xFFFFFFFF), LPC17_MCPWM_CNTCONCLR); /* All channels in counter mode on PCLK */
putreg32((1 << 0), LPC17_MCPWM_CONSET); /* Start MCPWM timer0 */
putreg32((1 << 0), LPC17_MCPWM_CONSET); /* Start MCPWM timer0 */
irqrestore(flags);
pwm_dumpgpio(priv->pincfg, "PWM setup");

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