diff --git a/arch/arm/src/arm/up_assert.c b/arch/arm/src/arm/up_assert.c index 7f0d33b8483..f8cd706fa56 100644 --- a/arch/arm/src/arm/up_assert.c +++ b/arch/arm/src/arm/up_assert.c @@ -313,7 +313,7 @@ static void _up_assert(int errorcode) if (current_regs || ((struct tcb_s *)g_readytorun.head)->pid == 0) { (void)irqsave(); - for (;;) + for (; ; ) { #ifdef CONFIG_ARCH_LEDS board_led_on(LED_PANIC); diff --git a/arch/arm/src/armv6-m/up_assert.c b/arch/arm/src/armv6-m/up_assert.c index 558351dc4a9..4c570637a5e 100644 --- a/arch/arm/src/armv6-m/up_assert.c +++ b/arch/arm/src/armv6-m/up_assert.c @@ -226,7 +226,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...) return ret; } -static int assert_tracecallback(FAR struct usbtrace_s *trace,FAR void *arg) +static int assert_tracecallback(FAR struct usbtrace_s *trace, FAR void *arg) { usbtrace_trprintf(usbtrace_syslog, trace->event, trace->value); return 0; @@ -368,7 +368,7 @@ static void _up_assert(int errorcode) if (current_regs || ((struct tcb_s *)g_readytorun.head)->pid == 0) { (void)irqsave(); - for (;;) + for (; ; ) { #ifdef CONFIG_ARCH_LEDS board_led_on(LED_PANIC); diff --git a/arch/arm/src/armv6-m/up_reprioritizertr.c b/arch/arm/src/armv6-m/up_reprioritizertr.c index 4fa1dd24259..b1c4f7a5d40 100644 --- a/arch/arm/src/armv6-m/up_reprioritizertr.c +++ b/arch/arm/src/armv6-m/up_reprioritizertr.c @@ -136,7 +136,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) sched_suspend_scheduler(rtcb); - /* Are we in an interrupt handler? */ + /* Are we in an interrupt handler? */ if (current_regs) { diff --git a/arch/arm/src/armv6-m/up_systemreset.c b/arch/arm/src/armv6-m/up_systemreset.c index 61060286150..c5cafd9b816 100644 --- a/arch/arm/src/armv6-m/up_systemreset.c +++ b/arch/arm/src/armv6-m/up_systemreset.c @@ -76,7 +76,7 @@ void up_systemreset(void) /* Wait for the reset */ - for (;;); + for (; ; ); } diff --git a/arch/arm/src/armv7-a/arm_assert.c b/arch/arm/src/armv7-a/arm_assert.c index 3c66d64c1d3..19630740eb6 100644 --- a/arch/arm/src/armv7-a/arm_assert.c +++ b/arch/arm/src/armv7-a/arm_assert.c @@ -368,7 +368,7 @@ static void _up_assert(int errorcode) if (current_regs || ((struct tcb_s *)g_readytorun.head)->pid == 0) { (void)irqsave(); - for (;;) + for (; ; ) { #ifdef CONFIG_ARCH_LEDS board_led_on(LED_PANIC); diff --git a/arch/arm/src/armv7-a/arm_pgalloc.c b/arch/arm/src/armv7-a/arm_pgalloc.c index 8c355664b60..82ad115660d 100644 --- a/arch/arm/src/armv7-a/arm_pgalloc.c +++ b/arch/arm/src/armv7-a/arm_pgalloc.c @@ -293,7 +293,7 @@ uintptr_t pgalloc(uintptr_t brkaddr, unsigned int npages) index = (brkaddr & 0x000ff000) >> 12; - /* Map the .text region virtual address to this physical address */ + /* Map the .text region virtual address to this physical address */ DEBUGASSERT(l2table[index] == 0); l2table[index] = paddr | MMU_L2_UDATAFLAGS; diff --git a/arch/arm/src/armv7-a/arm_reprioritizertr.c b/arch/arm/src/armv7-a/arm_reprioritizertr.c index a799329f446..93c9cd0b090 100644 --- a/arch/arm/src/armv7-a/arm_reprioritizertr.c +++ b/arch/arm/src/armv7-a/arm_reprioritizertr.c @@ -136,7 +136,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) sched_suspend_scheduler(rtcb); - /* Are we in an interrupt handler? */ + /* Are we in an interrupt handler? */ if (current_regs) { diff --git a/arch/arm/src/armv7-m/up_assert.c b/arch/arm/src/armv7-m/up_assert.c index cd9ba9c3536..0a264cb8cb2 100644 --- a/arch/arm/src/armv7-m/up_assert.c +++ b/arch/arm/src/armv7-m/up_assert.c @@ -377,7 +377,7 @@ static void _up_assert(int errorcode) if (current_regs || ((struct tcb_s *)g_readytorun.head)->pid == 0) { (void)irqsave(); - for (;;) + for (; ; ) { #ifdef CONFIG_ARCH_LEDS board_led_on(LED_PANIC); diff --git a/arch/arm/src/armv7-m/up_itm_syslog.c b/arch/arm/src/armv7-m/up_itm_syslog.c index 749d03f1f6c..94b499879a7 100644 --- a/arch/arm/src/armv7-m/up_itm_syslog.c +++ b/arch/arm/src/armv7-m/up_itm_syslog.c @@ -101,10 +101,10 @@ void itm_syslog_initialize(void) regval |= NVIC_DEMCR_TRCENA; putreg32(regval, NVIC_DEMCR); - putreg32(0xc5acce55,ITM_LAR); - putreg32(0, ITM_TER); - putreg32(0, ITM_TCR); - putreg32(2, TPI_SPPR); /* Pin protocol: 2=> Manchester (USART) */ + putreg32(0xc5acce55, ITM_LAR); + putreg32(0, ITM_TER); + putreg32(0, ITM_TCR); + putreg32(2, TPI_SPPR); /* Pin protocol: 2=> Manchester (USART) */ /* Default 880kbps */ diff --git a/arch/arm/src/armv7-m/up_reprioritizertr.c b/arch/arm/src/armv7-m/up_reprioritizertr.c index 10245657011..11a40e30084 100644 --- a/arch/arm/src/armv7-m/up_reprioritizertr.c +++ b/arch/arm/src/armv7-m/up_reprioritizertr.c @@ -136,7 +136,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) sched_suspend_scheduler(rtcb); - /* Are we in an interrupt handler? */ + /* Are we in an interrupt handler? */ if (current_regs) { diff --git a/arch/arm/src/armv7-m/up_systemreset.c b/arch/arm/src/armv7-m/up_systemreset.c index 96f1b92089b..509f7707afe 100644 --- a/arch/arm/src/armv7-m/up_systemreset.c +++ b/arch/arm/src/armv7-m/up_systemreset.c @@ -77,7 +77,7 @@ void up_systemreset(void) /* Wait for the reset */ - for (;;); + for (; ; ); } diff --git a/arch/arm/src/c5471/c5471_ethernet.c b/arch/arm/src/c5471/c5471_ethernet.c index 6391ec857f8..761802337b4 100644 --- a/arch/arm/src/c5471/c5471_ethernet.c +++ b/arch/arm/src/c5471/c5471_ethernet.c @@ -1058,7 +1058,7 @@ static void c5471_rxstatus(struct c5471_driver_s *c5471) /* Walk that last packet we just received to collect xmit status bits. */ rxstatus = 0; - for (;;) + for (; ; ) { if (EIM_TXDESC_OWN_HOST & getreg32(desc)) { @@ -1405,7 +1405,7 @@ static void c5471_txstatus(struct c5471_driver_s *c5471) txstatus = 0; if (c5471->c_lastdescstart && c5471->c_lastdescend) { - for (;;) + for (; ; ) { txstatus |= (getreg32(desc) & EIM_RXDESC_STATUSMASK); if (desc == c5471->c_lastdescend) diff --git a/arch/arm/src/dm320/dm320_serial.c b/arch/arm/src/dm320/dm320_serial.c index 07f5ce91df0..5f56d6a349f 100644 --- a/arch/arm/src/dm320/dm320_serial.c +++ b/arch/arm/src/dm320/dm320_serial.c @@ -495,7 +495,7 @@ static int up_interrupt(int irq, void *context) * until we have been looping for a long time. */ - for (;;) + for (; ; ) { /* Get the current UART status and check for loop * termination conditions diff --git a/arch/arm/src/dm320/dm320_usbdev.c b/arch/arm/src/dm320/dm320_usbdev.c index f2d5307ad14..ea7b808cb58 100644 --- a/arch/arm/src/dm320/dm320_usbdev.c +++ b/arch/arm/src/dm320/dm320_usbdev.c @@ -960,7 +960,7 @@ static int dm320_wrrequest(struct dm320_ep_s *privep) * may be resuming transfer already in progress. */ - for (;;) + for (; ; ) { /* Get the number of bytes left to be sent in the packet */ @@ -2251,7 +2251,7 @@ static FAR struct usbdev_ep_s *dm320_allocep(FAR struct usbdev_s *dev, uint8_t e if (g_epinfo[ndx].attr == eptype) { - /* Success! */ + /* Success! */ return &priv->eplist[ndx].ep; } diff --git a/arch/arm/src/efm32/efm32_adc.c b/arch/arm/src/efm32/efm32_adc.c index c79daba3bbc..c156ec7872f 100644 --- a/arch/arm/src/efm32/efm32_adc.c +++ b/arch/arm/src/efm32/efm32_adc.c @@ -784,7 +784,7 @@ static void adc_startconv(struct efm32_dev_s *priv, bool enable) regval &= ~ADC_CR2_SWSTART; } - adc_putreg(priv, EFM32_ADC_CR2_OFFSET,regval); + adc_putreg(priv, EFM32_ADC_CR2_OFFSET, regval); } #endif diff --git a/arch/arm/src/efm32/efm32_flash.c b/arch/arm/src/efm32/efm32_flash.c index 11bc4d07f20..1fb041dc50f 100644 --- a/arch/arm/src/efm32/efm32_flash.c +++ b/arch/arm/src/efm32/efm32_flash.c @@ -134,11 +134,11 @@ void efm32_flash_unlock(void) /* Unlock the EFM32_MSC */ - putreg32(MSC_UNLOCK_CODE,EFM32_MSC_LOCK); + putreg32(MSC_UNLOCK_CODE, EFM32_MSC_LOCK); /* Disable writing to the flash */ - bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WREN_SHIFT,0); + bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 0); #if defined(_MSC_TIMEBASE_MASK) @@ -178,7 +178,7 @@ void efm32_flash_unlock(void) regval |= (cycles << _MSC_TIMEBASE_BASE_SHIFT); } - putreg32(regval,EFM32_MSC_TIMEBASE); + putreg32(regval, EFM32_MSC_TIMEBASE); #endif } @@ -230,8 +230,8 @@ int __ramfunc__ msc_load_verify_address(uint32_t *address) /* Load address */ - putreg32((uint32_t) (address),EFM32_MSC_ADDRB); - putreg32(MSC_WRITECMD_LADDRIM,EFM32_MSC_WRITECMD); + putreg32((uint32_t) (address), EFM32_MSC_ADDRB); + putreg32(MSC_WRITECMD_LADDRIM, EFM32_MSC_WRITECMD); status = getreg32(EFM32_MSC_STATUS); if (status & (MSC_STATUS_INVADDR | MSC_STATUS_LOCKED)) @@ -320,12 +320,12 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words, /* Clear double word option, in order to write one single word. */ - bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WDOUBLE_SHIFT,0); + bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WDOUBLE_SHIFT, 0); /* Write first data word. */ - putreg32(*data++,EFM32_MSC_WDATA); - putreg32(MSC_WRITECMD_WRITEONCE,EFM32_MSC_WRITECMD); + putreg32(*data++, EFM32_MSC_WDATA); + putreg32(MSC_WRITECMD_WRITEONCE, EFM32_MSC_WRITECMD); /* Wait for the operation to finish. It may be required to change the * WDOUBLE config after the initial write. It should not be changed @@ -355,7 +355,7 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words, * data phase. */ - bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WDOUBLE_SHIFT,1); + bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WDOUBLE_SHIFT, 1); words_per_data_phase = 2; } else @@ -380,7 +380,7 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words, word_index = 0; while (word_index < num_words) { - putreg32(*data++,EFM32_MSC_WDATA); + putreg32(*data++, EFM32_MSC_WDATA); word_index++; if (words_per_data_phase == 2) { @@ -388,11 +388,11 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words, { } - putreg32(*data++,EFM32_MSC_WDATA); + putreg32(*data++, EFM32_MSC_WDATA); word_index++; } - putreg32(MSC_WRITECMD_WRITEONCE,EFM32_MSC_WRITECMD); + putreg32(MSC_WRITECMD_WRITEONCE, EFM32_MSC_WRITECMD); /* Wait for the transaction to finish. */ @@ -412,13 +412,13 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words, } #if defined(CONFIG_EFM32_EFM32G) - putreg32(getreg32(EFM32_MSC_ADDRB)+4,EFM32_MSC_ADDRB); - putreg32(MSC_WRITECMD_LADDRIM,EFM32_MSC_WRITECMD); + putreg32(getreg32(EFM32_MSC_ADDRB)+4, EFM32_MSC_ADDRB); + putreg32(MSC_WRITECMD_LADDRIM, EFM32_MSC_WRITECMD); #endif } } - /* Write strategy: msc_write_fast */ + /* Write strategy: msc_write_fast */ else { @@ -461,15 +461,15 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words, regval &= MSC_STATUS_WDATAREADY; if (regval == MSC_STATUS_WORDTIMEOUT) { - putreg32(MSC_WRITECMD_WRITETRIG,EFM32_MSC_WRITECMD); + putreg32(MSC_WRITECMD_WRITETRIG, EFM32_MSC_WRITECMD); } } - putreg32(*data,EFM32_MSC_WDATA); + putreg32(*data, EFM32_MSC_WDATA); if ((words_per_data_phase == 1) || \ ((words_per_data_phase == 2) && (word_index & 0x1))) { - putreg32(MSC_WRITECMD_WRITETRIG,EFM32_MSC_WRITECMD); + putreg32(MSC_WRITECMD_WRITETRIG, EFM32_MSC_WRITECMD); } data++; @@ -498,7 +498,7 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words, /* Clear double word option, which should not be left on when returning. */ - bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WDOUBLE_SHIFT,0); + bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WDOUBLE_SHIFT, 0); #endif @@ -509,11 +509,11 @@ void efm32_flash_lock(void) { /* Disable writing to the flash */ - bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WREN_SHIFT,0); + bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 0); /* Unlock the EFM32_MSC */ - putreg32(0,EFM32_MSC_LOCK); + putreg32(0, EFM32_MSC_LOCK); } #ifndef EFM32_FLASH_SIZE @@ -649,12 +649,12 @@ ssize_t __ramfunc__ up_progmem_erasepage(size_t page) /* enable writing to the flash */ - bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WREN_SHIFT,1); + bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 1); /* Load address */ - putreg32((uint32_t)up_progmem_getaddress(page),EFM32_MSC_ADDRB); - putreg32(MSC_WRITECMD_LADDRIM,EFM32_MSC_WRITECMD); + putreg32((uint32_t)up_progmem_getaddress(page), EFM32_MSC_ADDRB); + putreg32(MSC_WRITECMD_LADDRIM, EFM32_MSC_WRITECMD); regval = getreg32(EFM32_MSC_STATUS); @@ -676,7 +676,7 @@ ssize_t __ramfunc__ up_progmem_erasepage(size_t page) if (ret == 0) { - putreg32(MSC_WRITECMD_ERASEPAGE,EFM32_MSC_WRITECMD); + putreg32(MSC_WRITECMD_ERASEPAGE, EFM32_MSC_WRITECMD); /* Wait for the erase to complete */ @@ -694,7 +694,7 @@ ssize_t __ramfunc__ up_progmem_erasepage(size_t page) /* Disable writing to the MSC */ - bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WREN_SHIFT,0); + bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 0); if (ret == 0) { @@ -772,7 +772,7 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size) /* enable writing to the flash */ - bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WREN_SHIFT,1); + bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 1); /* Convert bytes to words */ @@ -783,7 +783,7 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size) * increments the address internally for each data load inside a page. */ - for (word_count = 0, p_data = (uint32_t *)buf; word_count < num_words;) + for (word_count = 0, p_data = (uint32_t *)buf; word_count < num_words; ) { int page_bytes; ssize_t page_idx; @@ -841,7 +841,7 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size) /* Disable writing to the MSC */ - bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WREN_SHIFT,0); + bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 0); #if (defined(CONFIG_EFM32_EFM32GG) || defined(CONFIG_EFM32_EFM32WG)) && (2==WORDS_PER_DATA_PHASE) diff --git a/arch/arm/src/efm32/efm32_gpioirq.c b/arch/arm/src/efm32/efm32_gpioirq.c index 0c21c912cbe..f778bc894c3 100644 --- a/arch/arm/src/efm32/efm32_gpioirq.c +++ b/arch/arm/src/efm32/efm32_gpioirq.c @@ -287,7 +287,7 @@ void efm32_gpioirqenable(int irq) putreg32(regval, EFM32_GPIO_IEN); irqrestore(flags); #else - bitband_set_peripheral(EFM32_GPIO_IEN,(irq - EFM32_IRQ_EXTI0),1); + bitband_set_peripheral(EFM32_GPIO_IEN, (irq - EFM32_IRQ_EXTI0), 1); #endif } } @@ -318,7 +318,7 @@ void efm32_gpioirqdisable(int irq) putreg32(regval, EFM32_GPIO_IEN); irqrestore(flags); #else - bitband_set_peripheral(EFM32_GPIO_IEN,(irq - EFM32_IRQ_EXTI0),0); + bitband_set_peripheral(EFM32_GPIO_IEN, (irq - EFM32_IRQ_EXTI0), 0); #endif } } @@ -349,7 +349,7 @@ void efm32_gpioirqclear(int irq) putreg32(regval, EFM32_GPIO_IFC); irqrestore(flags); #else - bitband_set_peripheral(EFM32_GPIO_IFC,(irq - EFM32_IRQ_EXTI0),1); + bitband_set_peripheral(EFM32_GPIO_IFC, (irq - EFM32_IRQ_EXTI0), 1); #endif } } diff --git a/arch/arm/src/efm32/efm32_i2c.c b/arch/arm/src/efm32/efm32_i2c.c index 495b920cd91..8fa05ae4fb0 100644 --- a/arch/arm/src/efm32/efm32_i2c.c +++ b/arch/arm/src/efm32/efm32_i2c.c @@ -422,13 +422,13 @@ static const struct i2c_ops_s efm32_i2c_ops = .write = efm32_i2c_write, .read = efm32_i2c_read #ifdef CONFIG_I2C_WRITEREAD - ,.writeread = efm32_i2c_writeread + , .writeread = efm32_i2c_writeread #endif #ifdef CONFIG_I2C_TRANSFER - ,.transfer = efm32_i2c_transfer + , .transfer = efm32_i2c_transfer #endif #ifdef CONFIG_I2C_SLAVE - ,.setownaddress = efm32_i2c_setownaddress, + , .setownaddress = efm32_i2c_setownaddress, .registercallback = efm32_i2c_registercallback #endif }; @@ -903,7 +903,7 @@ static void efm32_i2c_setclock(FAR struct efm32_i2c_priv_s *priv, static int efm32_i2c_isr(struct efm32_i2c_priv_s *priv) { - for (;;) + for (; ; ) { int regval; @@ -1253,7 +1253,7 @@ static int efm32_i2c_isr(struct efm32_i2c_priv_s *priv) * now, before receiving the last byte. */ - efm32_i2c_putreg(priv,EFM32_I2C_CMD_OFFSET,I2C_CMD_NACK); + efm32_i2c_putreg(priv, EFM32_I2C_CMD_OFFSET, I2C_CMD_NACK); } } } diff --git a/arch/arm/src/efm32/efm32_pwm.c b/arch/arm/src/efm32/efm32_pwm.c index 43fcb6971a8..343dba865c4 100644 --- a/arch/arm/src/efm32/efm32_pwm.c +++ b/arch/arm/src/efm32/efm32_pwm.c @@ -325,7 +325,8 @@ static void pwm_putreg(struct efm32_pwmtimer_s *priv, int offset, uint32_t value #if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE) static void pwm_dumpregs(struct efm32_pwmtimer_s *priv, FAR const char *msg) { - /* TODO debug pwm_dumpregs */ + /* TODO debug pwm_dumpregs */ + #if 0 pwmvdbg("%s:\n", msg); pwmvdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", @@ -410,7 +411,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv, #error "Not implemented ! Sorry" #endif - if (efm32_timer_set_freq(priv->base,priv->pclk,info->frequency) < 0) + if (efm32_timer_set_freq(priv->base, priv->pclk, info->frequency) < 0) { pwmdbg("Cannot set TIMER frequency %dHz from clock %dHz\n", info->frequency, priv->pclk); @@ -440,7 +441,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv, pwm_putreg(priv, EFM32_TIMER_ROUTE_OFFSET, regval); regval = (info->duty * pwm_getreg(priv, EFM32_TIMER_TOP_OFFSET)) >> 16; - pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CCV_OFFSET , regval); + pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CCV_OFFSET, regval); //pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CCVB_OFFSET, regval); regval = (_TIMER_CC_CTRL_MODE_PWM << _TIMER_CC_CTRL_MODE_SHIFT) | \ @@ -677,19 +678,19 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) switch (priv->timid) { case 0: - modifyreg32(EFM32_CMU_HFPERCLKEN0,0,CMU_HFPERCLKEN0_TIMER0); + modifyreg32(EFM32_CMU_HFPERCLKEN0, 0, CMU_HFPERCLKEN0_TIMER0); break; case 1: - modifyreg32(EFM32_CMU_HFPERCLKEN0,0,CMU_HFPERCLKEN0_TIMER1); + modifyreg32(EFM32_CMU_HFPERCLKEN0, 0, CMU_HFPERCLKEN0_TIMER1); break; case 2: - modifyreg32(EFM32_CMU_HFPERCLKEN0,0,CMU_HFPERCLKEN0_TIMER2); + modifyreg32(EFM32_CMU_HFPERCLKEN0, 0, CMU_HFPERCLKEN0_TIMER2); break; case 3: - modifyreg32(EFM32_CMU_HFPERCLKEN0,0,CMU_HFPERCLKEN0_TIMER3); + modifyreg32(EFM32_CMU_HFPERCLKEN0, 0, CMU_HFPERCLKEN0_TIMER3); break; default: @@ -698,7 +699,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) } efm32_configgpio(priv->pincfg); - pwm_putreg(priv,EFM32_TIMER_ROUTE_OFFSET,BOARD_PWM_TIMER0_PINLOC); + pwm_putreg(priv, EFM32_TIMER_ROUTE_OFFSET, BOARD_PWM_TIMER0_PINLOC); pwm_dumpgpio(priv->pincfg, "PWM setup"); return OK; } diff --git a/arch/arm/src/efm32/efm32_rmu.c b/arch/arm/src/efm32/efm32_rmu.c index 9996ec117a3..6b77564b24d 100644 --- a/arch/arm/src/efm32/efm32_rmu.c +++ b/arch/arm/src/efm32/efm32_rmu.c @@ -237,7 +237,7 @@ void efm32_rmu_initialize(void) /* Now clear reset cause */ - putreg32(RMU_CMD_RCCLR,EFM32_RMU_CMD); + putreg32(RMU_CMD_RCCLR, EFM32_RMU_CMD); /* Clear some reset causes not cleared with RMU CMD register * (If EMU registers locked, they must be unlocked first) @@ -248,22 +248,22 @@ void efm32_rmu_initialize(void) { /* EMU unlock */ - putreg32(EMU_LOCK_LOCKKEY_LOCK,EMU_LOCK_LOCKKEY_UNLOCK); + putreg32(EMU_LOCK_LOCKKEY_LOCK, EMU_LOCK_LOCKKEY_UNLOCK); } - modifyreg32(EFM32_EMU_AUXCTRL,0,EMU_AUXCTRL_HRCCLR); - modifyreg32(EFM32_EMU_AUXCTRL,EMU_AUXCTRL_HRCCLR,0); + modifyreg32(EFM32_EMU_AUXCTRL, 0, EMU_AUXCTRL_HRCCLR); + modifyreg32(EFM32_EMU_AUXCTRL, EMU_AUXCTRL_HRCCLR, 0); if (locked) { /* EMU lock */ - putreg32(EMU_LOCK_LOCKKEY_LOCK,EMU_LOCK_LOCKKEY_LOCK); + putreg32(EMU_LOCK_LOCKKEY_LOCK, EMU_LOCK_LOCKKEY_LOCK); } #ifdef CONFIG_EFM32_RMU_DEBUG rmudbg("RMU => reg = 0x%08X\n", g_efm32_rstcause); - for (;;) + for (; ; ) { const char *str; diff --git a/arch/arm/src/efm32/efm32_serial.c b/arch/arm/src/efm32/efm32_serial.c index 7f3517f2c27..bfcef819fa5 100644 --- a/arch/arm/src/efm32/efm32_serial.c +++ b/arch/arm/src/efm32/efm32_serial.c @@ -1019,7 +1019,7 @@ static int efm32_ioctl(struct file *filep, int cmd, unsigned long arg) /* Just speed is yet implemented */ - efm32_disableuartint(priv,&ien); + efm32_disableuartint(priv, &ien); efm32_uartconfigure(config->uartbase, config->baud, config->parity, config->bits, config->stop2); diff --git a/arch/arm/src/efm32/efm32_spi.c b/arch/arm/src/efm32/efm32_spi.c index f6396bffee6..888ea06248f 100644 --- a/arch/arm/src/efm32/efm32_spi.c +++ b/arch/arm/src/efm32/efm32_spi.c @@ -1288,7 +1288,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, { /* 16-bit mode */ - const uint16_t *src = (const uint16_t *)txbuffer;; + const uint16_t *src = (const uint16_t *)txbuffer; uint16_t *dest = (uint16_t *)rxbuffer; uint16_t word; @@ -1342,7 +1342,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, { /* 8-bit mode */ - const uint8_t *src = (const uint8_t *)txbuffer;; + const uint8_t *src = (const uint8_t *)txbuffer; uint8_t *dest = (uint8_t *)rxbuffer; uint8_t word; diff --git a/arch/arm/src/efm32/efm32_start.c b/arch/arm/src/efm32/efm32_start.c index 9326700d591..ec0171f2307 100644 --- a/arch/arm/src/efm32/efm32_start.c +++ b/arch/arm/src/efm32/efm32_start.c @@ -312,6 +312,6 @@ void __start(void) /* Shouldn't get here */ - for (;;); + for (; ; ); #endif } diff --git a/arch/arm/src/efm32/efm32_timer.c b/arch/arm/src/efm32/efm32_timer.c index b00adb35a20..19c50b56c20 100644 --- a/arch/arm/src/efm32/efm32_timer.c +++ b/arch/arm/src/efm32/efm32_timer.c @@ -215,11 +215,11 @@ void efm32_timer_reset(uintptr_t base) putreg32(TIMER_DTLOCK_LOCKKEY_UNLOCK, base + EFM32_TIMER_DTLOCK_OFFSET); - putreg32(_TIMER_DTCTRL_RESETVALUE,base + EFM32_TIMER_DTCTRL_OFFSET ); - putreg32(_TIMER_DTTIME_RESETVALUE,base + EFM32_TIMER_DTTIME_OFFSET ); - putreg32(_TIMER_DTFC_RESETVALUE, base + EFM32_TIMER_DTFC_OFFSET ); - putreg32(_TIMER_DTOGEN_RESETVALUE,base + EFM32_TIMER_DTOGEN_OFFSET ); - putreg32(_TIMER_DTFAULTC_MASK, base + EFM32_TIMER_DTFAULTC_OFFSET ); + putreg32(_TIMER_DTCTRL_RESETVALUE, base + EFM32_TIMER_DTCTRL_OFFSET); + putreg32(_TIMER_DTTIME_RESETVALUE, base + EFM32_TIMER_DTTIME_OFFSET); + putreg32(_TIMER_DTFC_RESETVALUE, base + EFM32_TIMER_DTFC_OFFSET); + putreg32(_TIMER_DTOGEN_RESETVALUE,base + EFM32_TIMER_DTOGEN_OFFSET); + putreg32(_TIMER_DTFAULTC_MASK, base + EFM32_TIMER_DTFAULTC_OFFSET); #endif } diff --git a/arch/arm/src/efm32/efm32_usbdev.c b/arch/arm/src/efm32/efm32_usbdev.c index 3d34ec7029b..308cd49022a 100644 --- a/arch/arm/src/efm32/efm32_usbdev.c +++ b/arch/arm/src/efm32/efm32_usbdev.c @@ -1007,7 +1007,7 @@ static void efm32_ep0out_ctrlsetup(FAR struct efm32_usbdev_s *priv) regval = (USB_SIZEOF_CTRLREQ * 3 << _USB_DOEP0TSIZ_XFERSIZE_SHIFT) | (USB_DOEP0TSIZ_PKTCNT) | (3 << _USB_DOEP0TSIZ_SUPCNT_SHIFT); - efm32_putreg(regval,EFM32_USB_DOEP0TSIZ); + efm32_putreg(regval, EFM32_USB_DOEP0TSIZ); /* Then clear NAKing and enable the transfer */ @@ -1672,7 +1672,7 @@ static void efm32_epout_request(FAR struct efm32_usbdev_s *priv, * read request is encountered. */ - for (;;) + for (; ; ) { /* Get a reference to the request at the head of the endpoint's request queue */ @@ -3475,9 +3475,9 @@ static inline void efm32_otginterrupt(FAR struct efm32_usbdev_s *priv) regval = efm32_getreg(EFM32_USB_GOTGINT); if ((regval & OTGFS_GOTGINT_SEDET) != 0) - { + { #warning "Missing logic" - } + } /* Clear OTG interrupt */ @@ -3516,7 +3516,7 @@ static int efm32_usbinterrupt(int irq, FAR void *context) * events. */ - for (;;) + for (; ; ) { /* Get the set of pending, un-masked interrupts */ @@ -3531,6 +3531,7 @@ static int efm32_usbinterrupt(int irq, FAR void *context) { break; } + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_INTPENDING), (uint16_t)regval); /* OUT endpoint interrupt. The core sets this bit to indicate that an @@ -3572,7 +3573,7 @@ static int efm32_usbinterrupt(int irq, FAR void *context) efm32_putreg(USB_GINTSTS_WKUPINT, EFM32_USB_GINTSTS); } - /* USB suspend interrupt */ + /* USB suspend interrupt */ if ((regval & USB_GINTSTS_USBSUSP) != 0) { @@ -4757,7 +4758,7 @@ static FAR struct usbdev_ep_s *efm32_ep_alloc(FAR struct usbdev_s *dev, irqrestore(flags); return in ? &priv->epin[epno].ep : &priv->epout[epno].ep; } - } + } /* We should not get here */ } @@ -4839,7 +4840,7 @@ static int efm32_wakeup(struct usbdev_s *dev) regval = efm32_getreg(EFM32_USB_DSTS); if ((regval & USB_DSTS_SUSPSTS) != 0) { - /* Re-start the PHY clock and un-gate USB core clock (HCLK) */ + /* Re-start the PHY clock and un-gate USB core clock (HCLK) */ #ifdef CONFIG_USBDEV_LOWPOWER regval = efm32_getreg(EFM32_USB_PCGCCTL); @@ -5188,7 +5189,7 @@ static void efm32_hwinitialize(FAR struct efm32_usbdev_s *priv) /* First Turn on USB clocking */ - modifyreg32(EFM32_CMU_HFCORECLKEN0,0, + modifyreg32(EFM32_CMU_HFCORECLKEN0, 0, CMU_HFCORECLKEN0_USB | CMU_HFCORECLKEN0_USBC); /* At start-up the core is in FS mode. */ @@ -5271,7 +5272,8 @@ static void efm32_hwinitialize(FAR struct efm32_usbdev_s *priv) /* Set Rx FIFO size */ - efm32_putreg(EFM32_RXFIFO_WORDS << _USB_GRXFSIZ_RXFDEP_SHIFT,EFM32_USB_GRXFSIZ); + efm32_putreg(EFM32_RXFIFO_WORDS << _USB_GRXFSIZ_RXFDEP_SHIFT, + EFM32_USB_GRXFSIZ); /* EP0 TX */ diff --git a/arch/arm/src/efm32/efm32_usbhost.c b/arch/arm/src/efm32/efm32_usbhost.c index b9cc9e6af85..022ccd3553e 100644 --- a/arch/arm/src/efm32/efm32_usbhost.c +++ b/arch/arm/src/efm32/efm32_usbhost.c @@ -1728,7 +1728,7 @@ static int efm32_ctrl_sendsetup(FAR struct efm32_usbhost_s *priv, return ret; } - /* Get the elapsed time (in frames) */ + /* Get the elapsed time (in frames) */ elapsed = clock_systimer() - start; } @@ -1949,7 +1949,7 @@ static ssize_t efm32_in_transfer(FAR struct efm32_usbhost_s *priv, int chidx, if (ret < 0) { - usbhost_trace1(USBHOST_TRACE1_TRNSFRFAILED,ret); + usbhost_trace1(USBHOST_TRACE1_TRNSFRFAILED, ret); /* Check for a special case: If (1) the transfer was NAKed and (2) * no Tx FIFO empty or Rx FIFO not-empty event occurred, then we @@ -2194,7 +2194,7 @@ static ssize_t efm32_out_transfer(FAR struct efm32_usbhost_s *priv, int chidx, ret = efm32_chan_waitsetup(priv, chan); if (ret < 0) { - usbhost_trace1(USBHOST_TRACE1_DEVDISCONN,0); + usbhost_trace1(USBHOST_TRACE1_DEVDISCONN, 0); return (ssize_t)ret; } @@ -2207,7 +2207,7 @@ static ssize_t efm32_out_transfer(FAR struct efm32_usbhost_s *priv, int chidx, return (ssize_t)ret; } - /* Wait for the transfer to complete and get the result */ + /* Wait for the transfer to complete and get the result */ ret = efm32_chan_wait(priv, chan); @@ -2215,7 +2215,7 @@ static ssize_t efm32_out_transfer(FAR struct efm32_usbhost_s *priv, int chidx, if (ret < 0) { - usbhost_trace1(USBHOST_TRACE1_TRNSFRFAILED,ret); + usbhost_trace1(USBHOST_TRACE1_TRNSFRFAILED, ret); /* Check for a special case: If (1) the transfer was NAKed and (2) * no Tx FIFO empty or Rx FIFO not-empty event occurred, then we @@ -2899,7 +2899,7 @@ static void efm32_gint_connected(FAR struct efm32_usbhost_s *priv) { /* Yes.. then now we are connected */ - usbhost_vtrace1(USBHOST_VTRACE1_CONNECTED,0); + usbhost_vtrace1(USBHOST_VTRACE1_CONNECTED, 0); priv->connected = true; priv->change = true; DEBUGASSERT(priv->smstate == SMSTATE_DETACHED); @@ -2931,7 +2931,7 @@ static void efm32_gint_disconnected(FAR struct efm32_usbhost_s *priv) { /* Yes.. then we no longer connected */ - usbhost_vtrace1(USBHOST_VTRACE1_DISCONNECTED,0); + usbhost_vtrace1(USBHOST_VTRACE1_DISCONNECTED, 0); /* Are we bound to a class driver? */ @@ -3514,7 +3514,7 @@ static int efm32_gint_isr(int irq, FAR void *context) * little interrupt handling overhead. */ - for (;;) + for (; ; ) { /* Get the unmasked bits in the GINT status */ @@ -3807,7 +3807,7 @@ static int efm32_wait(FAR struct usbhost_connection_s *conn, /* Loop until a change in connection state is detected */ flags = irqsave(); - for (;;) + for (; ; ) { /* Is there a change in the connection state of the single root hub * port? @@ -3901,7 +3901,7 @@ static int efm32_rh_enumerate(FAR struct efm32_usbhost_s *priv, { /* No, return an error */ - usbhost_trace1(USBHOST_TRACE1_DEVDISCONN,0); + usbhost_trace1(USBHOST_TRACE1_DEVDISCONN, 0); return -ENODEV; } diff --git a/arch/arm/src/imx/imx_serial.c b/arch/arm/src/imx/imx_serial.c index 4e6775fc155..c134c134957 100644 --- a/arch/arm/src/imx/imx_serial.c +++ b/arch/arm/src/imx/imx_serial.c @@ -834,7 +834,7 @@ static int up_interrupt(int irq, void *context) * until we have been looping for a long time. */ - for (;;) + for (; ; ) { /* Get the current UART status and check for loop * termination conditions diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c index 9359681580d..50a24bd8c3e 100644 --- a/arch/arm/src/kinetis/kinetis_enet.c +++ b/arch/arm/src/kinetis/kinetis_enet.c @@ -680,7 +680,7 @@ static void kinetis_txdone(FAR struct kinetis_driver_s *priv) priv->txtail = 0; } - /* Update statistics */ + /* Update statistics */ EMAC_STAT(priv, tx_done); } diff --git a/arch/arm/src/kinetis/kinetis_sdhc.c b/arch/arm/src/kinetis/kinetis_sdhc.c index e97863ae5cb..f457c5c8955 100644 --- a/arch/arm/src/kinetis/kinetis_sdhc.c +++ b/arch/arm/src/kinetis/kinetis_sdhc.c @@ -832,9 +832,9 @@ static void kinetis_transmit(struct kinetis_dev_s *priv) priv->remaining = 0; } - /* Put the word in the FIFO */ + /* Put the word in the FIFO */ - putreg32(data.w, KINETIS_SDHC_DATPORT); + putreg32(data.w, KINETIS_SDHC_DATPORT); } fllvdbg("Exit: remaining: %d IRQSTAT: %08x\n", @@ -2426,7 +2426,7 @@ static sdio_eventset_t kinetis_eventwait(FAR struct sdio_dev_s *dev, * may have already occurred before this function was called! */ - for (;;) + for (; ; ) { /* Wait for an event in event set to occur. If this the event has already * occurred, then the semaphore will already have been incremented and @@ -2706,8 +2706,8 @@ static void kinetis_callback(void *arg) /* Media is present. Is the media inserted event enabled? */ if ((priv->cbevents & SDIOMEDIA_INSERTED) == 0) - { - /* No... return without performing the callback */ + { + /* No... return without performing the callback */ return; } diff --git a/arch/arm/src/kinetis/kinetis_start.c b/arch/arm/src/kinetis/kinetis_start.c index df5b6adec33..425a6c6b4b0 100644 --- a/arch/arm/src/kinetis/kinetis_start.c +++ b/arch/arm/src/kinetis/kinetis_start.c @@ -165,5 +165,5 @@ void __start(void) /* Shouldn't get here */ - for (;;); + for (; ; ); } diff --git a/arch/arm/src/kl/kl_lowputc.c b/arch/arm/src/kl/kl_lowputc.c index 597b687a747..cb08623a5cf 100644 --- a/arch/arm/src/kl/kl_lowputc.c +++ b/arch/arm/src/kl/kl_lowputc.c @@ -154,62 +154,62 @@ void kl_lowputc(uint32_t ch) ****************************************************************************/ void kl_lowsetup(void) { - uint32_t regval; - uint8_t regval8; + uint32_t regval; + uint8_t regval8; #if 0 - regval = getreg32(KL_SIM_SOPT2); - regval |= SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_UART0SRC_MCGCLK ; - putreg32(regval, KL_SIM_SOPT2); + regval = getreg32(KL_SIM_SOPT2); + regval |= SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_UART0SRC_MCGCLK ; + putreg32(regval, KL_SIM_SOPT2); #endif - regval = getreg32(KL_SIM_SCGC4); + regval = getreg32(KL_SIM_SCGC4); #ifdef CONFIG_KL_UART0 - regval |= SIM_SCGC4_UART0; + regval |= SIM_SCGC4_UART0; #endif #ifdef CONFIG_KL_UART1 - regval |= SIM_SCGC4_UART1; + regval |= SIM_SCGC4_UART1; #endif #ifdef CONFIG_KL_UART2 - regval |= SIM_SCGC4_UART2; + regval |= SIM_SCGC4_UART2; #endif - putreg32(regval, KL_SIM_SCGC4); + putreg32(regval, KL_SIM_SCGC4); - regval = getreg32(KL_SIM_SOPT2); - regval &= ~(SIM_SOPT2_UART0SRC_MASK); - putreg32(regval, KL_SIM_SOPT2); + regval = getreg32(KL_SIM_SOPT2); + regval &= ~(SIM_SOPT2_UART0SRC_MASK); + putreg32(regval, KL_SIM_SOPT2); - regval = getreg32(KL_SIM_SOPT2); - regval |= SIM_SOPT2_UART0SRC_MCGCLK; - putreg32(regval, KL_SIM_SOPT2); + regval = getreg32(KL_SIM_SOPT2); + regval |= SIM_SOPT2_UART0SRC_MCGCLK; + putreg32(regval, KL_SIM_SOPT2); - putreg32((PORT_PCR_MUX_ALT2), KL_PORTA_PCR1); - putreg32((PORT_PCR_MUX_ALT2), KL_PORTA_PCR2); + putreg32((PORT_PCR_MUX_ALT2), KL_PORTA_PCR1); + putreg32((PORT_PCR_MUX_ALT2), KL_PORTA_PCR2); - /* Disable UART before changing registers */ + /* Disable UART before changing registers */ - putreg8(0, KL_UART0_C2); - putreg8(0, KL_UART0_C1); - putreg8(0, KL_UART0_C3); - putreg8(0, KL_UART0_S2); + putreg8(0, KL_UART0_C2); + putreg8(0, KL_UART0_C1); + putreg8(0, KL_UART0_C3); + putreg8(0, KL_UART0_S2); - /* Set the baud rate divisor */ + /* Set the baud rate divisor */ - uint16_t divisor = (CONSOLE_FREQ / OVER_SAMPLE) / CONSOLE_BAUD; - regval8 = OVER_SAMPLE - 1; - putreg8(regval8, KL_UART0_C4); + uint16_t divisor = (CONSOLE_FREQ / OVER_SAMPLE) / CONSOLE_BAUD; + regval8 = OVER_SAMPLE - 1; + putreg8(regval8, KL_UART0_C4); - regval8 = (divisor >> 8) & UART_BDH_SBR_MASK; - putreg8(regval8, KL_UART0_BDH); + regval8 = (divisor >> 8) & UART_BDH_SBR_MASK; + putreg8(regval8, KL_UART0_BDH); - regval8 = (divisor & UART_BDL_SBR_MASK); - putreg8(regval8, KL_UART0_BDL); + regval8 = (divisor & UART_BDL_SBR_MASK); + putreg8(regval8, KL_UART0_BDL); - /* Enable UART before changing registers */ + /* Enable UART before changing registers */ - regval8 = getreg8(KL_UART0_C2); - regval8 |= (UART_C2_RE | UART_C2_TE); - putreg8(regval8, KL_UART0_C2); + regval8 = getreg8(KL_UART0_C2); + regval8 |= (UART_C2_RE | UART_C2_TE); + putreg8(regval8, KL_UART0_C2); /* Configure the console (only) now. Other UARTs will be configured * when the serial driver is opened. diff --git a/arch/arm/src/kl/kl_start.c b/arch/arm/src/kl/kl_start.c index c87f65b7c36..63491ac74d7 100644 --- a/arch/arm/src/kl/kl_start.c +++ b/arch/arm/src/kl/kl_start.c @@ -181,6 +181,6 @@ void __start(void) /* Shoulnd't get here */ - for (;;); + for (; ; ); } diff --git a/arch/arm/src/lpc11xx/lpc11_gpioint.c b/arch/arm/src/lpc11xx/lpc11_gpioint.c index 71075d5275e..764d5e3135b 100644 --- a/arch/arm/src/lpc11xx/lpc11_gpioint.c +++ b/arch/arm/src/lpc11xx/lpc11_gpioint.c @@ -454,7 +454,7 @@ static int lpc11_gpiointerrupt(int irq, void *context) void lpc11_gpioirqinitialize(void) { - /* Disable all GPIO interrupts */ + /* Disable all GPIO interrupts */ putreg32(0, LPC17_GPIOINT0_INTENR); putreg32(0, LPC17_GPIOINT0_INTENF); diff --git a/arch/arm/src/lpc11xx/lpc11_spi.c b/arch/arm/src/lpc11xx/lpc11_spi.c index 43f81afd43b..734923bac9d 100644 --- a/arch/arm/src/lpc11xx/lpc11_spi.c +++ b/arch/arm/src/lpc11xx/lpc11_spi.c @@ -485,7 +485,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, while ((getreg32(LPC11_SPI_SR) & SPI_SR_SPIF) == 0); - /* Read the SPI Status Register again to clear the status bit */ + /* Read the SPI Status Register again to clear the status bit */ (void)getreg32(LPC11_SPI_SR); nwords--; diff --git a/arch/arm/src/lpc11xx/lpc11_start.c b/arch/arm/src/lpc11xx/lpc11_start.c index 6ec8f727fc1..78429691490 100644 --- a/arch/arm/src/lpc11xx/lpc11_start.c +++ b/arch/arm/src/lpc11xx/lpc11_start.c @@ -171,5 +171,5 @@ void __start(void) /* Shouldn't get here */ - for (;;); + for (; ; ); } diff --git a/arch/arm/src/lpc11xx/lpc11_timer.c b/arch/arm/src/lpc11xx/lpc11_timer.c index 6f867202e2d..56aafb69593 100644 --- a/arch/arm/src/lpc11xx/lpc11_timer.c +++ b/arch/arm/src/lpc11xx/lpc11_timer.c @@ -400,24 +400,24 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev) regval = getreg32(LPC17_SYSCON_PCLKSEL0); regval &= ~(0x3 << 2); - regval |= (0x1 << 2); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ + regval |= (0x1 << 2); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ regval &= ~(0x3 << 4); - regval |= (0x1 << 4); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ + regval |= (0x1 << 4); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ putreg32(regval, LPC17_SYSCON_PCLKSEL0); regval = getreg32(LPC17_SYSCON_PCLKSEL1); regval &= ~(0x3 << 12); - regval |= (0x1 << 12); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ + regval |= (0x1 << 12); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ regval &= ~(0x3 << 14); - regval |= (0x1 << 14); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ + regval |= (0x1 << 14); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ putreg32(regval, LPC17_SYSCON_PCLKSEL1); priv->pclk = (0x1 << 12) | (0x1 << 4); - putreg32(1000, LPC17_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */ + putreg32(1000, LPC17_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */ - putreg32(1, LPC17_TMR0_PR); /* Prescaler count frequency: Fpclk/1 */ - putreg32(~(0x3 << 0), LPC17_TMR0_CCR); /* Prescaler count frequency: Fpclk/1 */ - putreg32(~(0x3 << 0), LPC17_TMR0_CTCR);/* Prescaler count frequency: Fpclk/1 */ - putreg32((2 << 3), LPC17_TMR0_MCR); /* Reset on match register MR1 */ + putreg32(1, LPC17_TMR0_PR); /* Prescaler count frequency: Fpclk/1 */ + putreg32(~(0x3 << 0), LPC17_TMR0_CCR); /* Prescaler count frequency: Fpclk/1 */ + putreg32(~(0x3 << 0), LPC17_TMR0_CTCR); /* Prescaler count frequency: Fpclk/1 */ + putreg32((2 << 3), LPC17_TMR0_MCR); /* Reset on match register MR1 */ /* Output bit toggle on external match event External match on MR1, Toggle * external bit @@ -430,14 +430,14 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev) lpc11_configgpio(GPIO_MAT0p1_2); - putreg32(500, LPC17_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */ + putreg32(500, LPC17_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */ - putreg32(1, LPC17_TMR1_PR); /* Prescaler count frequency:Fpclk/1 */ - putreg32(~(0x3 << 0), LPC17_TMR1_CCR); /* Prescaler count frequency:Fpclk/1 */ - putreg32(~(0x3 << 0), LPC17_TMR1_CTCR);/* Prescaler count frequency:Fpclk/1 */ - putreg32((2 << 0), LPC17_TMR1_MCR); /* Reset on match register MR0 */ + putreg32(1, LPC17_TMR1_PR); /* Prescaler count frequency:Fpclk/1 */ + putreg32(~(0x3 << 0), LPC17_TMR1_CCR); /* Prescaler count frequency:Fpclk/1 */ + putreg32(~(0x3 << 0), LPC17_TMR1_CTCR); /* Prescaler count frequency:Fpclk/1 */ + putreg32((2 << 0), LPC17_TMR1_MCR); /* Reset on match register MR0 */ // putreg32(((1 << 0) | (3 << 4)), LPC17_TMR1_EMR); /* Output bit toggle on external match event MAT0 */ - putreg32((1 << 0), LPC17_TMR1_TCR); /* Start timer1 */ + putreg32((1 << 0), LPC17_TMR1_TCR); /* Start timer1 */ /* configure the output pins GPIO3.26 */ // lpc11_configgpio(GPIO_MAT0p1_2); diff --git a/arch/arm/src/lpc17xx/lpc176x_clockconfig.c b/arch/arm/src/lpc17xx/lpc176x_clockconfig.c index 4befd375912..d74e2b8dc83 100644 --- a/arch/arm/src/lpc17xx/lpc176x_clockconfig.c +++ b/arch/arm/src/lpc17xx/lpc176x_clockconfig.c @@ -138,14 +138,14 @@ void lpc17_clockconfig(void) /* Enable and connect PLL0 */ - putreg32(SYSCON_PLLCON_PLLE|SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL0CON); + putreg32(SYSCON_PLLCON_PLLE | SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL0CON); putreg32(0xaa, LPC17_SYSCON_PLL0FEED); putreg32(0x55, LPC17_SYSCON_PLL0FEED); /* Wait for PLL to report that it is connected and enabled */ - while ((getreg32(LPC17_SYSCON_PLL0STAT) & (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC)) - != (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC)); + while ((getreg32(LPC17_SYSCON_PLL0STAT) & (SYSCON_PLL0STAT_PLLE | SYSCON_PLL0STAT_PLLC)) + != (SYSCON_PLL0STAT_PLLE | SYSCON_PLL0STAT_PLLC)); #endif /* CONFIG_LPC17_PLL0 */ @@ -178,14 +178,14 @@ void lpc17_clockconfig(void) /* Enable and connect PLL1 */ - putreg32(SYSCON_PLLCON_PLLE|SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL1CON); + putreg32(SYSCON_PLLCON_PLLE | SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL1CON); putreg32(0xaa, LPC17_SYSCON_PLL1FEED); putreg32(0x55, LPC17_SYSCON_PLL1FEED); /* Wait for PLL to report that it is connected and enabled */ - while ((getreg32(LPC17_SYSCON_PLL1STAT) & (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC)) - != (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC)); + while ((getreg32(LPC17_SYSCON_PLL1STAT) & (SYSCON_PLL1STAT_PLLE | SYSCON_PLL1STAT_PLLC)) + != (SYSCON_PLL1STAT_PLLE | SYSCON_PLL1STAT_PLLC)); #else /* CONFIG_LPC17_PLL1 */ @@ -218,4 +218,3 @@ void lpc17_clockconfig(void) putreg32(BOARD_FLASHCFG_VALUE, LPC17_SYSCON_FLASHCFG); #endif } - diff --git a/arch/arm/src/lpc17xx/lpc178x_gpio.c b/arch/arm/src/lpc17xx/lpc178x_gpio.c index 4a27945c15f..a30b7d42558 100644 --- a/arch/arm/src/lpc17xx/lpc178x_gpio.c +++ b/arch/arm/src/lpc17xx/lpc178x_gpio.c @@ -217,7 +217,8 @@ static uint32_t lpc17_getioconmask(unsigned int port, unsigned int pin) * ****************************************************************************/ -static void lpc17_seti2cmode(unsigned int port,unsigned int pin, uint32_t value) +static void lpc17_seti2cmode(unsigned int port, unsigned int pin, + uint32_t value) { uint32_t regaddr; uint32_t regval; diff --git a/arch/arm/src/lpc17xx/lpc17_adc.c b/arch/arm/src/lpc17xx/lpc17_adc.c index 0587e3085b4..220691ebfa4 100644 --- a/arch/arm/src/lpc17xx/lpc17_adc.c +++ b/arch/arm/src/lpc17xx/lpc17_adc.c @@ -383,7 +383,7 @@ static int adc_interrupt(int irq, void *context) { value = priv->buf[ch] / priv->count[ch]; value <<= 15; - adc_receive(&g_adcdev,ch,value); + adc_receive(&g_adcdev, ch, value); priv->buf[ch] = 0; priv->count[ch] = 0; } @@ -408,7 +408,7 @@ static int adc_interrupt(int irq, void *context) { value = priv->buf[ch] / priv->count[ch]; value <<= 15; - adc_receive(&g_adcdev,ch,value); + adc_receive(&g_adcdev, ch, value); priv->buf[ch] = 0; priv->count[ch] = 0; } @@ -424,7 +424,7 @@ static int adc_interrupt(int irq, void *context) /* Verify that an interrupt has actually occured */ regVal2 = getreg32(LPC17_ADC_STAT); /* Read ADSTAT will clear the interrupt flag */ - if ((regVal2) & (1<<16)) + if ((regVal2) & (1 << 16)) { if ((priv->mask & 0x01) != 0) { @@ -563,7 +563,7 @@ static int adc_interrupt(int irq, void *context) regVal3 = getreg32(LPC17_ADC_GDR); /* Read ADGDR clear the DONE and OVERRUN bits */ putreg32((priv->mask) | /* Select channels 0 to 7 on ADC0 */ - ((32) << 8) | /* CLKDIV = 16 */ + (32 << 8) | /* CLKDIV = 16 */ (0 << 16) | /* BURST = 1, BURST capture all selected channels */ (1 << 17) | /* Reserved bit = 0 */ (1 << 21) | /* PDN = 1, normal operation */ diff --git a/arch/arm/src/lpc17xx/lpc17_allocateheap.c b/arch/arm/src/lpc17xx/lpc17_allocateheap.c index b9b524d1eb2..e6969326b65 100644 --- a/arch/arm/src/lpc17xx/lpc17_allocateheap.c +++ b/arch/arm/src/lpc17xx/lpc17_allocateheap.c @@ -250,7 +250,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ board_led_on(LED_HEAPALLOCATE); - *heap_start = (FAR void*)ubase; + *heap_start = (FAR void *)ubase; *heap_size = usize; /* Allow user-mode access to the user heap memory */ @@ -261,7 +261,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the heap settings */ board_led_on(LED_HEAPALLOCATE); - *heap_start = (FAR void*)g_idle_topstack; + *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; #endif } @@ -305,7 +305,7 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) * that was not dedicated to the user heap). */ - *heap_start = (FAR void*)USERSPACE->us_bssend; + *heap_start = (FAR void *)USERSPACE->us_bssend; *heap_size = ubase - (uintptr_t)USERSPACE->us_bssend; } #endif @@ -345,17 +345,17 @@ void up_addregion(void) /* Add the AHB SRAM user heap region. */ - kumm_addregion((FAR void*)LPC17_AHB_HEAPBASE, LPC17_AHB_HEAPSIZE); + kumm_addregion((FAR void *)LPC17_AHB_HEAPBASE, LPC17_AHB_HEAPSIZE); #endif #if CONFIG_MM_REGIONS >= 3 #if defined(CONFIG_LPC17_EXTDRAM) && defined(CONFIG_LPC17_EXTDRAMHEAP) - kmm_addregion((FAR void*)LPC17_EXTDRAM_CS0, CONFIG_LPC17_EXTDRAMSIZE); + kmm_addregion((FAR void *)LPC17_EXTDRAM_CS0, CONFIG_LPC17_EXTDRAMSIZE); #endif #if !defined(CONFIG_LPC17_EXTDRAMHEAP) || (CONFIG_MM_REGIONS >= 4) #if defined(CONFIG_LPC17_EXTSRAM0) && defined(CONFIG_LPC17_EXTSRAM0HEAP) - kmm_addregion((FAR void*)LPC17_EXTSRAM_CS0, CONFIG_LPC17_EXTSRAM0SIZE); + kmm_addregion((FAR void *)LPC17_EXTSRAM_CS0, CONFIG_LPC17_EXTSRAM0SIZE); #endif #endif #endif diff --git a/arch/arm/src/lpc17xx/lpc17_can.c b/arch/arm/src/lpc17xx/lpc17_can.c index f1e8209deb4..2cd55626c44 100644 --- a/arch/arm/src/lpc17xx/lpc17_can.c +++ b/arch/arm/src/lpc17xx/lpc17_can.c @@ -335,20 +335,20 @@ static void can_printreg(uint32_t addr, uint32_t value) else { - /* Did we print "..." for the previous value? */ + /* Did we print "..." for the previous value? */ - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ - lldbg("[repeats %d more times]\n", count-3); - } + lldbg("[repeats %d more times]\n", count-3); + } - /* Save the new address, value, and count */ + /* Save the new address, value, and count */ - prevaddr = addr; - preval = value; - count = 1; + prevaddr = addr; + preval = value; + count = 1; } /* Show the register value read */ @@ -616,9 +616,9 @@ static void can_rxint(FAR struct can_dev_s *dev, bool enable) canvdbg("CAN%d enable: %d\n", priv->port, enable); - /* The EIR register is also modifed from the interrupt handler, so we have - * to protect this code section. - */ + /* The EIR register is also modifed from the interrupt handler, so we have + * to protect this code section. + */ flags = irqsave(); regval = can_getreg(priv, LPC17_CAN_IER_OFFSET); @@ -630,6 +630,7 @@ static void can_rxint(FAR struct can_dev_s *dev, bool enable) { regval &= ~CAN_IER_RIE; } + can_putreg(priv, LPC17_CAN_IER_OFFSET, regval); irqrestore(flags); } @@ -829,7 +830,7 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) regval |= CAN_IER_TIE2; can_putreg(priv, LPC17_CAN_IER_OFFSET, regval); - /* Set up the transfer */ + /* Set up the transfer */ can_putreg(priv, LPC17_CAN_TFI2_OFFSET, tfi); can_putreg(priv, LPC17_CAN_TID2_OFFSET, tid); @@ -1185,7 +1186,7 @@ static int can_bittiming(struct up_dev_s *priv) { ts1 = CONFIG_CAN_TSEG1; ts2 = CONFIG_CAN_TSEG2; - brp = (nclks + (CAN_BIT_QUANTA/2)) / CAN_BIT_QUANTA; + brp = (nclks + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA; DEBUGASSERT(brp >=1 && brp <= CAN_BTR_BRP_MAX); } diff --git a/arch/arm/src/lpc17xx/lpc17_dac.c b/arch/arm/src/lpc17xx/lpc17_dac.c index 3f2fa5a700e..adc9db849c5 100644 --- a/arch/arm/src/lpc17xx/lpc17_dac.c +++ b/arch/arm/src/lpc17xx/lpc17_dac.c @@ -91,12 +91,12 @@ static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg); static const struct dac_ops_s g_dacops = { - .ao_reset =dac_reset, - .ao_setup = dac_setup, + .ao_reset = dac_reset, + .ao_setup = dac_setup, .ao_shutdown = dac_shutdown, - .ao_txint = dac_txint, - .ao_send = dac_send, - .ao_ioctl = dac_ioctl, + .ao_txint = dac_txint, + .ao_send = dac_send, + .ao_ioctl = dac_ioctl, }; static struct dac_dev_s g_dacdev = @@ -124,7 +124,7 @@ static void dac_reset(FAR struct dac_dev_s *dev) regval |= (SYSCON_PCLKSEL_CCLK8 << SYSCON_PCLKSEL0_DAC_SHIFT); putreg32(regval, LPC17_SYSCON_PCLKSEL0); - //putreg32(DAC_CTRL_DBLBUFEN,LPC17_DAC_CTRL); ? + //putreg32(DAC_CTRL_DBLBUFEN, LPC17_DAC_CTRL); ? lpc17_configgpio(GPIO_AOUT); diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.c b/arch/arm/src/lpc17xx/lpc17_ethernet.c index 0e1e34253e1..41fe4e7f9f0 100644 --- a/arch/arm/src/lpc17xx/lpc17_ethernet.c +++ b/arch/arm/src/lpc17xx/lpc17_ethernet.c @@ -599,7 +599,7 @@ static int lpc17_txdesc(struct lpc17_driver_s *priv) prodidx = lpc17_getreg(LPC17_ETH_TXPRODIDX) & ETH_TXPRODIDX_MASK; if (++prodidx >= CONFIG_NET_NTXDESC) { - /* Wrap back to index zero */ + /* Wrap back to index zero */ prodidx = 0; } @@ -659,8 +659,8 @@ static int lpc17_transmit(struct lpc17_driver_s *priv) * fields. */ - txdesc = (uint32_t*)(LPC17_TXDESC_BASE + (prodidx << 3)); - txbuffer = (void*)*txdesc++; + txdesc = (uint32_t *)(LPC17_TXDESC_BASE + (prodidx << 3)); + txbuffer = (void *)*txdesc++; *txdesc = TXDESC_CONTROL_INT | TXDESC_CONTROL_LAST | TXDESC_CONTROL_CRC | (priv->lp_dev.d_len - 1); @@ -682,7 +682,7 @@ static int lpc17_transmit(struct lpc17_driver_s *priv) if (++prodidx >= CONFIG_NET_NTXDESC) { - /* Wrap back to index zero */ + /* Wrap back to index zero */ prodidx = 0; } @@ -873,7 +873,7 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv) /* Get the Rx status and packet length (-4+1) */ - rxstat = (uint32_t*)(LPC17_RXSTAT_BASE + (considx << 3)); + rxstat = (uint32_t *)(LPC17_RXSTAT_BASE + (considx << 3)); pktlen = (*rxstat & RXSTAT_INFO_RXSIZE_MASK) - 3; /* Check for errors. NOTE: The DMA engine reports bogus length errors, @@ -920,8 +920,8 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv) /* Get the Rx buffer address from the Rx descriptor */ - rxdesc = (uint32_t*)(LPC17_RXDESC_BASE + (considx << 3)); - rxbuffer = (void*)*rxdesc; + rxdesc = (uint32_t *)(LPC17_RXDESC_BASE + (considx << 3)); + rxbuffer = (void *)*rxdesc; /* Copy the data data from the EMAC DMA RAM to priv->lp_dev.d_buf. * Set amount of data in priv->lp_dev.d_len @@ -1059,8 +1059,8 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv) */ if (++considx >= CONFIG_NET_NRXDESC) - { - /* Wrap back to index zero */ + { + /* Wrap back to index zero */ considx = 0; } @@ -1245,7 +1245,7 @@ static int lpc17_interrupt(int irq, void *context) * error. */ - if ((status & (ETH_INT_RXOVR|ETH_INT_TXUNR)) != 0) + if ((status & (ETH_INT_RXOVR | ETH_INT_TXUNR)) != 0) { if ((status & ETH_INT_RXOVR) != 0) { @@ -1259,7 +1259,7 @@ static int lpc17_interrupt(int irq, void *context) EMAC_STAT(priv, tx_underrun); } - /* ifup() will reset the EMAC and bring it back up */ + /* ifup() will reset the EMAC and bring it back up */ (void)lpc17_ifup(&priv->lp_dev); } @@ -2334,8 +2334,8 @@ static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac) #if defined(CONFIG_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO) static void lpc17_showpins(void) { - lpc17_dumpgpio(GPIO_PORT1|GPIO_PIN0, "P1[1-15]"); - lpc17_dumpgpio(GPIO_PORT1|GPIO_PIN16, "P1[16-31]"); + lpc17_dumpgpio(GPIO_PORT1 | GPIO_PIN0, "P1[1-15]"); + lpc17_dumpgpio(GPIO_PORT1 | GPIO_PIN16, "P1[16-31]"); } #endif @@ -2449,7 +2449,7 @@ static uint16_t lpc17_phyread(uint8_t phyaddr, uint8_t regaddr) /* Wait for the PHY command to complete */ - while ((lpc17_getreg(LPC17_ETH_MIND) & (ETH_MIND_BUSY|ETH_MIND_NVALID)) != 0); + while ((lpc17_getreg(LPC17_ETH_MIND) & (ETH_MIND_BUSY | ETH_MIND_NVALID)) != 0); lpc17_putreg(0, LPC17_ETH_MCMD); /* Return the PHY register data */ @@ -2970,7 +2970,7 @@ static inline void lpc17_txdescinit(struct lpc17_driver_s *priv) /* Initialize Tx descriptors and link to packet buffers */ - txdesc = (uint32_t*)LPC17_TXDESC_BASE; + txdesc = (uint32_t *)LPC17_TXDESC_BASE; pktaddr = LPC17_TXBUFFER_BASE; for (i = 0; i < CONFIG_NET_NTXDESC; i++) @@ -2982,7 +2982,7 @@ static inline void lpc17_txdescinit(struct lpc17_driver_s *priv) /* Initialize Tx status */ - txstat = (uint32_t*)LPC17_TXSTAT_BASE; + txstat = (uint32_t *)LPC17_TXSTAT_BASE; for (i = 0; i < CONFIG_NET_NTXDESC; i++) { *txstat++ = 0; @@ -3026,7 +3026,7 @@ static inline void lpc17_rxdescinit(struct lpc17_driver_s *priv) /* Initialize Rx descriptors and link to packet buffers */ - rxdesc = (uint32_t*)LPC17_RXDESC_BASE; + rxdesc = (uint32_t *)LPC17_RXDESC_BASE; pktaddr = LPC17_RXBUFFER_BASE; for (i = 0; i < CONFIG_NET_NRXDESC; i++) @@ -3038,7 +3038,7 @@ static inline void lpc17_rxdescinit(struct lpc17_driver_s *priv) /* Initialize Rx status */ - rxstat = (uint32_t*)LPC17_RXSTAT_BASE; + rxstat = (uint32_t *)LPC17_RXSTAT_BASE; for (i = 0; i < CONFIG_NET_NRXDESC; i++) { *rxstat++ = 0; @@ -3264,7 +3264,7 @@ static inline int lpc17_ethinitialize(int intf) priv->lp_dev.d_addmac = lpc17_addmac; /* Add multicast MAC address */ priv->lp_dev.d_rmmac = lpc17_rmmac; /* Remove multicast MAC address */ #endif - priv->lp_dev.d_private = (void*)priv; /* Used to recover private state from dev */ + priv->lp_dev.d_private = (void *)priv; /* Used to recover private state from dev */ #if CONFIG_LPC17_NINTERFACES > 1 # error "A mechanism to associate base address an IRQ with an interface is needed" diff --git a/arch/arm/src/lpc17xx/lpc17_gpdma.c b/arch/arm/src/lpc17xx/lpc17_gpdma.c index a8c77281b05..dbecb2ec3ae 100644 --- a/arch/arm/src/lpc17xx/lpc17_gpdma.c +++ b/arch/arm/src/lpc17xx/lpc17_gpdma.c @@ -519,7 +519,7 @@ int lpc17_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config, * interrupt enable bit which is controlled by the driver. */ - regval = control & ~(DMACH_CONTROL_XFRSIZE_MASK|DMACH_CONTROL_I); + regval = control & ~(DMACH_CONTROL_XFRSIZE_MASK | DMACH_CONTROL_I); regval |= ((uint32_t)nxfrs << DMACH_CONTROL_XFRSIZE_SHIFT); putreg32(regval, base + LPC17_DMACH_CONTROL_OFFSET); @@ -535,7 +535,7 @@ int lpc17_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config, * are provided by the caller. Little endian is assumed. */ - regval = config & (DMACH_CONFIG_SRCPER_MASK|DMACH_CONFIG_DSTPER_MASK| + regval = config & (DMACH_CONFIG_SRCPER_MASK | DMACH_CONFIG_DSTPER_MASK | DMACH_CONFIG_XFRTYPE_MASK); putreg32(regval, base + LPC17_DMACH_CONFIG_OFFSET); diff --git a/arch/arm/src/lpc17xx/lpc17_gpioint.c b/arch/arm/src/lpc17xx/lpc17_gpioint.c index 9a656172016..1fa18a36819 100644 --- a/arch/arm/src/lpc17xx/lpc17_gpioint.c +++ b/arch/arm/src/lpc17xx/lpc17_gpioint.c @@ -454,7 +454,7 @@ static int lpc17_gpiointerrupt(int irq, void *context) void lpc17_gpioirqinitialize(void) { - /* Disable all GPIO interrupts */ + /* Disable all GPIO interrupts */ putreg32(0, LPC17_GPIOINT0_INTENR); putreg32(0, LPC17_GPIOINT0_INTENF); diff --git a/arch/arm/src/lpc17xx/lpc17_i2c.c b/arch/arm/src/lpc17xx/lpc17_i2c.c index fc566876cfb..6298dcb6886 100644 --- a/arch/arm/src/lpc17xx/lpc17_i2c.c +++ b/arch/arm/src/lpc17xx/lpc17_i2c.c @@ -223,7 +223,7 @@ static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int bufle priv->wrcnt = 0; priv->rdcnt = 0; priv->msg.addr &= ~0x01; - priv->msg.buffer = (uint8_t*)buffer; + priv->msg.buffer = (uint8_t *)buffer; priv->msg.length = buflen; ret = i2c_start(priv); @@ -344,21 +344,21 @@ static int i2c_interrupt(int irq, FAR void *context) #ifdef CONFIG_LPC17_I2C0 if (irq == LPC17_IRQ_I2C0) { - priv=&i2cdevices[0]; + priv = &i2cdevices[0]; } else #endif #ifdef CONFIG_LPC17_I2C1 if (irq == LPC17_IRQ_I2C1) { - priv=&i2cdevices[1]; + priv = &i2cdevices[1]; } else #endif #ifdef CONFIG_LPC17_I2C2 if (irq == LPC17_IRQ_I2C2) { - priv=&i2cdevices[2]; + priv = &i2cdevices[2]; } else #endif @@ -366,7 +366,7 @@ static int i2c_interrupt(int irq, FAR void *context) PANIC(); } -/* Reference UM10360 19.10.5 */ + /* Reference UM10360 19.10.5 */ state = getreg32(priv->base + LPC17_I2C_STAT_OFFSET); putreg32(I2C_CONCLR_SIC, priv->base + LPC17_I2C_CONCLR_OFFSET); @@ -396,7 +396,7 @@ static int i2c_interrupt(int irq, FAR void *context) case 0x28: priv->wrcnt++; - if (priv->wrcntmsg.length) + if (priv->wrcnt < priv->msg.length) { putreg32(priv->msg.buffer[priv->wrcnt], priv->base + LPC17_I2C_DAT_OFFSET); } @@ -462,11 +462,11 @@ struct i2c_dev_s *up_i2cinitialize(int port) flags = irqsave(); - priv= &i2cdevices[port]; + priv = &i2cdevices[port]; #ifdef CONFIG_LPC17_I2C0 if (port == 0) { - priv= (FAR struct lpc17_i2cdev_s *)&i2cdevices[0]; + priv = (FAR struct lpc17_i2cdev_s *)&i2cdevices[0]; priv->base = LPC17_I2C0_BASE; priv->irqid = LPC17_IRQ_I2C0; @@ -490,7 +490,7 @@ struct i2c_dev_s *up_i2cinitialize(int port) #ifdef CONFIG_LPC17_I2C1 if (port == 1) { - priv= (FAR struct lpc17_i2cdev_s *)&i2cdevices[1]; + priv = (FAR struct lpc17_i2cdev_s *)&i2cdevices[1]; priv->base = LPC17_I2C1_BASE; priv->irqid = LPC17_IRQ_I2C1; @@ -514,7 +514,7 @@ struct i2c_dev_s *up_i2cinitialize(int port) #ifdef CONFIG_LPC17_I2C2 if (port == 2) { - priv= (FAR struct lpc17_i2cdev_s *)&i2cdevices[2]; + priv = (FAR struct lpc17_i2cdev_s *)&i2cdevices[2]; priv->base = LPC17_I2C2_BASE; priv->irqid = LPC17_IRQ_I2C2; diff --git a/arch/arm/src/lpc17xx/lpc17_irq.c b/arch/arm/src/lpc17xx/lpc17_irq.c index fcf816f802b..5fae6bf708b 100644 --- a/arch/arm/src/lpc17xx/lpc17_irq.c +++ b/arch/arm/src/lpc17xx/lpc17_irq.c @@ -60,9 +60,9 @@ /* Get a 32-bit version of the default priority */ #define DEFPRIORITY32 \ - (NVIC_SYSH_PRIORITY_DEFAULT << 24 |\ - NVIC_SYSH_PRIORITY_DEFAULT << 16 |\ - NVIC_SYSH_PRIORITY_DEFAULT << 8 |\ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | \ NVIC_SYSH_PRIORITY_DEFAULT) /* Given the address of a NVIC ENABLE register, this is the offset to @@ -373,7 +373,7 @@ void up_irqinitialize(void) /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO -/* up_prioritize_irq(LPC17_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + /* up_prioritize_irq(LPC17_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif #ifdef CONFIG_ARMV7M_USEBASEPRI lpc17_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); diff --git a/arch/arm/src/lpc17xx/lpc17_lcd.c b/arch/arm/src/lpc17xx/lpc17_lcd.c index 2d2ca6b5c0e..03f3e4e6b5a 100644 --- a/arch/arm/src/lpc17xx/lpc17_lcd.c +++ b/arch/arm/src/lpc17xx/lpc17_lcd.c @@ -780,14 +780,14 @@ void lpc17_lcdclear(nxgl_mxpixel_t color) { int i; #if LPC17_BPP > 16 - uint32_t *dest = (uint32_t*)CONFIG_LPC17_LCD_VRAMBASE; + uint32_t *dest = (uint32_t *)CONFIG_LPC17_LCD_VRAMBASE; gvdbg("Clearing display: color=%08x VRAM=%08x size=%d\n", color, CONFIG_LPC17_LCD_VRAMBASE, CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT * sizeof(uint32_t)); #else - uint16_t *dest = (uint16_t*)CONFIG_LPC17_LCD_VRAMBASE; + uint16_t *dest = (uint16_t *)CONFIG_LPC17_LCD_VRAMBASE; gvdbg("Clearing display: color=%08x VRAM=%08x size=%d\n", color, CONFIG_LPC17_LCD_VRAMBASE, diff --git a/arch/arm/src/lpc17xx/lpc17_lowputc.c b/arch/arm/src/lpc17xx/lpc17_lowputc.c index 05bc2c2c2d6..bef1be6887b 100644 --- a/arch/arm/src/lpc17xx/lpc17_lowputc.c +++ b/arch/arm/src/lpc17xx/lpc17_lowputc.c @@ -314,8 +314,8 @@ void lpc17_lowsetup(void) */ regval = getreg32(LPC17_SYSCON_PCONP); - regval &= ~(SYSCON_PCONP_PCUART0|SYSCON_PCONP_PCUART1| - SYSCON_PCONP_PCUART2|SYSCON_PCONP_PCUART3); + regval &= ~(SYSCON_PCONP_PCUART0 | SYSCON_PCONP_PCUART1 | + SYSCON_PCONP_PCUART2 | SYSCON_PCONP_PCUART3); #if defined(CONFIG_UART0_SERIAL_CONSOLE) regval |= SYSCON_PCONP_PCUART0; #elif defined(CONFIG_UART1_SERIAL_CONSOLE) @@ -333,7 +333,7 @@ void lpc17_lowsetup(void) #ifdef LPC176x regval = getreg32(LPC17_SYSCON_PCLKSEL0); - regval &= ~(SYSCON_PCLKSEL0_UART0_MASK|SYSCON_PCLKSEL0_UART1_MASK); + regval &= ~(SYSCON_PCLKSEL0_UART0_MASK | SYSCON_PCLKSEL0_UART1_MASK); #if defined(CONFIG_UART0_SERIAL_CONSOLE) regval |= (CONSOLE_CCLKDIV << SYSCON_PCLKSEL0_UART0_SHIFT); #elif defined(CONFIG_UART1_SERIAL_CONSOLE) @@ -342,7 +342,7 @@ void lpc17_lowsetup(void) putreg32(regval, LPC17_SYSCON_PCLKSEL0); regval = getreg32(LPC17_SYSCON_PCLKSEL1); - regval &= ~(SYSCON_PCLKSEL1_UART2_MASK|SYSCON_PCLKSEL1_UART3_MASK); + regval &= ~(SYSCON_PCLKSEL1_UART2_MASK | SYSCON_PCLKSEL1_UART3_MASK); #if defined(CONFIG_UART2_SERIAL_CONSOLE) regval |= (CONSOLE_CCLKDIV << SYSCON_PCLKSEL1_UART2_SHIFT); #elif defined(CONFIG_UART3_SERIAL_CONSOLE) @@ -381,31 +381,34 @@ void lpc17_lowsetup(void) /* Clear fifos */ - putreg32(UART_FCR_RXRST|UART_FCR_TXRST, CONSOLE_BASE+LPC17_UART_FCR_OFFSET); + putreg32(UART_FCR_RXRST | UART_FCR_TXRST, + CONSOLE_BASE + LPC17_UART_FCR_OFFSET); /* Set trigger */ - putreg32(UART_FCR_FIFOEN|UART_FCR_RXTRIGGER_8, CONSOLE_BASE+LPC17_UART_FCR_OFFSET); + putreg32(UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8, + CONSOLE_BASE + LPC17_UART_FCR_OFFSET); /* Set up the LCR and set DLAB=1 */ - putreg32(CONSOLE_LCR_VALUE|UART_LCR_DLAB, CONSOLE_BASE+LPC17_UART_LCR_OFFSET); + putreg32(CONSOLE_LCR_VALUE | UART_LCR_DLAB, + CONSOLE_BASE + LPC17_UART_LCR_OFFSET); /* Set the BAUD divisor */ - putreg32(CONSOLE_DL >> 8, CONSOLE_BASE+LPC17_UART_DLM_OFFSET); - putreg32(CONSOLE_DL & 0xff, CONSOLE_BASE+LPC17_UART_DLL_OFFSET); + putreg32(CONSOLE_DL >> 8, CONSOLE_BASE + LPC17_UART_DLM_OFFSET); + putreg32(CONSOLE_DL & 0xff, CONSOLE_BASE + LPC17_UART_DLL_OFFSET); /* Clear DLAB */ - putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE+LPC17_UART_LCR_OFFSET); + putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE + LPC17_UART_LCR_OFFSET); /* Configure the FIFOs */ - putreg32(UART_FCR_RXTRIGGER_8|UART_FCR_TXRST|UART_FCR_RXRST|UART_FCR_FIFOEN, - CONSOLE_BASE+LPC17_UART_FCR_OFFSET); + putreg32(UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST | UART_FCR_RXRST | + UART_FCR_FIFOEN, + CONSOLE_BASE + LPC17_UART_FCR_OFFSET); #endif #endif /* HAVE_UART */ } - diff --git a/arch/arm/src/lpc17xx/lpc17_mcpwm.c b/arch/arm/src/lpc17xx/lpc17_mcpwm.c index 7afe8610797..26fe1410960 100644 --- a/arch/arm/src/lpc17xx/lpc17_mcpwm.c +++ b/arch/arm/src/lpc17xx/lpc17_mcpwm.c @@ -179,7 +179,7 @@ static struct lpc17_mcpwmtimer_s g_pwm1dev = .timtype = TIMTYPE_TIM1, .base = LPC17_MCPWM_BASE, .pincfg = GPIO_MCPWM_MCOA0, - .pclk = (0x1<<12), + .pclk = (1 << 12), }; #endif @@ -435,22 +435,22 @@ static int mcpwm_setup(FAR struct pwm_lowerhalf_s *dev) regval = getreg32(LPC17_SYSCON_PCLKSEL1); regval &= ~(0x3 << 30); - regval |= (0x2 << 30); /* PCLK_MC peripheral clk = CCLK/2 = 50 MHz */ + regval |= (0x2 << 30); /* PCLK_MC peripheral clk = CCLK/2 = 50 MHz */ putreg32(regval, LPC17_SYSCON_PCLKSEL1); priv->pclk = (0x1 << 12) | (0x1 << 4); - putreg32((1 << 15), LPC17_MCPWM_INTENCLR); /* Disable MCABORT pin interrupt */ - putreg32((1 << 0), LPC17_MCPWM_INTENCLR); /* Disable ILIM0 interrupt */ - putreg32((1 << 1), LPC17_MCPWM_INTENCLR); /* Disable IMAT0 interrupt */ - putreg32((1 << 2), LPC17_MCPWM_INTENCLR); /* Disable ICAP0 interrupt */ - putreg32((1 << 4), LPC17_MCPWM_INTENCLR); /* Disable ILIM1 interrupt */ - putreg32((1 << 5), LPC17_MCPWM_INTENCLR); /* Disable IMAT1 interrupt */ - putreg32((1 << 6), LPC17_MCPWM_INTENCLR); /* Disable ICAP1 interrupt */ - putreg32((1 << 8), LPC17_MCPWM_INTENCLR); /* Disable ILIM2 interrupt */ - putreg32((1 << 9), LPC17_MCPWM_INTENCLR); /* Disable IMAT2 interrupt */ - putreg32((1 << 10), LPC17_MCPWM_INTENCLR); /* Disable ICAP2 interrupt */ + putreg32((1 << 15), LPC17_MCPWM_INTENCLR); /* Disable MCABORT pin interrupt */ + putreg32((1 << 0), LPC17_MCPWM_INTENCLR); /* Disable ILIM0 interrupt */ + putreg32((1 << 1), LPC17_MCPWM_INTENCLR); /* Disable IMAT0 interrupt */ + putreg32((1 << 2), LPC17_MCPWM_INTENCLR); /* Disable ICAP0 interrupt */ + putreg32((1 << 4), LPC17_MCPWM_INTENCLR); /* Disable ILIM1 interrupt */ + putreg32((1 << 5), LPC17_MCPWM_INTENCLR); /* Disable IMAT1 interrupt */ + putreg32((1 << 6), LPC17_MCPWM_INTENCLR); /* Disable ICAP1 interrupt */ + putreg32((1 << 8), LPC17_MCPWM_INTENCLR); /* Disable ILIM2 interrupt */ + putreg32((1 << 9), LPC17_MCPWM_INTENCLR); /* Disable IMAT2 interrupt */ + putreg32((1 << 10), LPC17_MCPWM_INTENCLR); /* Disable ICAP2 interrupt */ - putreg32((0xFFFFFFFF), LPC17_MCPWM_CAPCLR);/* Clear all event capture */ + putreg32((0xFFFFFFFF), LPC17_MCPWM_CAPCLR); /* Clear all event capture */ /* Configure the output pins */ @@ -459,39 +459,39 @@ static int mcpwm_setup(FAR struct pwm_lowerhalf_s *dev) /* Program the timing registers */ - putreg32((1 << 0), LPC17_MCPWM_CONCLR); /* Stop MCPWM timer0 */ - putreg32((1 << 8), LPC17_MCPWM_CONCLR); /* Stop MCPWM timer1 */ - putreg32((1 << 16), LPC17_MCPWM_CONCLR); /* Stop MCPWM timer2 */ + putreg32((1 << 0), LPC17_MCPWM_CONCLR); /* Stop MCPWM timer0 */ + putreg32((1 << 8), LPC17_MCPWM_CONCLR); /* Stop MCPWM timer1 */ + putreg32((1 << 16), LPC17_MCPWM_CONCLR); /* Stop MCPWM timer2 */ - putreg32((1 << 30), LPC17_MCPWM_CONCLR); /* MCPWM not in AC mode */ + putreg32((1 << 30), LPC17_MCPWM_CONCLR); /* MCPWM not in AC mode */ - putreg32(1000, LPC17_MCPWM_TC0); /* Count frequency: Fpclk/1000 = 50 MHz/1000 = 50 KHz */ - putreg32(400, LPC17_MCPWM_LIM0); /* Set the starting duty cycle to 0.25 */ - putreg32(0, LPC17_MCPWM_MAT0); /* Reset the timer */ + putreg32(1000, LPC17_MCPWM_TC0); /* Count frequency: Fpclk/1000 = 50 MHz/1000 = 50 KHz */ + putreg32(400, LPC17_MCPWM_LIM0); /* Set the starting duty cycle to 0.25 */ + putreg32(0, LPC17_MCPWM_MAT0); /* Reset the timer */ - putreg32(100000, LPC17_MCPWM_TC1); /* Count frequency:Fpclk/100000 = 50 MHz/100000 = 500 Hz */ - putreg32(50000, LPC17_MCPWM_LIM1); /* Set the starting duty cycle to 0.5 */ - putreg32(0, LPC17_MCPWM_MAT1); /* Reset the timer */ + putreg32(100000, LPC17_MCPWM_TC1); /* Count frequency:Fpclk/100000 = 50 MHz/100000 = 500 Hz */ + putreg32(50000, LPC17_MCPWM_LIM1); /* Set the starting duty cycle to 0.5 */ + putreg32(0, LPC17_MCPWM_MAT1); /* Reset the timer */ - putreg32(1000, LPC17_MCPWM_TC2); /* Count frequency:Fpclk/1000 = 50 MHz/1000 = 50 KHz */ - putreg32(400, LPC17_MCPWM_LIM2); /* Set the starting duty cycle to 0.25 */ - putreg32(0, LPC17_MCPWM_MAT2); /* Reset the timer */ + putreg32(1000, LPC17_MCPWM_TC2); /* Count frequency:Fpclk/1000 = 50 MHz/1000 = 50 KHz */ + putreg32(400, LPC17_MCPWM_LIM2); /* Set the starting duty cycle to 0.25 */ + putreg32(0, LPC17_MCPWM_MAT2); /* Reset the timer */ - putreg32((1 << 2), LPC17_MCPWM_CONCLR); /* Channel 0 polarity set to default */ - putreg32((1 << 10), LPC17_MCPWM_CONCLR); /* Channel 1 polarity set to default */ - putreg32((1 << 18), LPC17_MCPWM_CONCLR); /* Channel 2 polarity set to default */ + putreg32((1 << 2), LPC17_MCPWM_CONCLR); /* Channel 0 polarity set to default */ + putreg32((1 << 10), LPC17_MCPWM_CONCLR); /* Channel 1 polarity set to default */ + putreg32((1 << 18), LPC17_MCPWM_CONCLR); /* Channel 2 polarity set to default */ - putreg32((1 << 3), LPC17_MCPWM_CONCLR); /* Channel 0 dead time disabled */ - putreg32((1 << 11), LPC17_MCPWM_CONCLR); /* Channel 1 dead time disabled */ - putreg32((1 << 19), LPC17_MCPWM_CONCLR); /* Channel 2 dead time disabled */ + putreg32((1 << 3), LPC17_MCPWM_CONCLR); /* Channel 0 dead time disabled */ + putreg32((1 << 11), LPC17_MCPWM_CONCLR); /* Channel 1 dead time disabled */ + putreg32((1 << 19), LPC17_MCPWM_CONCLR); /* Channel 2 dead time disabled */ - putreg32((1 << 1), LPC17_MCPWM_CONCLR); /* Channel 0 edge aligned */ - putreg32((1 << 9), LPC17_MCPWM_CONCLR); /* Channel 1 edge aligned */ - putreg32((1 << 17), LPC17_MCPWM_CONCLR); /* Channel 2 edge aligned */ + putreg32((1 << 1), LPC17_MCPWM_CONCLR); /* Channel 0 edge aligned */ + putreg32((1 << 9), LPC17_MCPWM_CONCLR); /* Channel 1 edge aligned */ + putreg32((1 << 17), LPC17_MCPWM_CONCLR); /* Channel 2 edge aligned */ - putreg32((0xFFFFFFFF), LPC17_MCPWM_CNTCONCLR);/* All channels in counter mode on PCLK */ + putreg32((0xFFFFFFFF), LPC17_MCPWM_CNTCONCLR); /* All channels in counter mode on PCLK */ - putreg32((1 << 0), LPC17_MCPWM_CONSET); /* Start MCPWM timer0 */ + putreg32((1 << 0), LPC17_MCPWM_CONSET); /* Start MCPWM timer0 */ irqrestore(flags); pwm_dumpgpio(priv->pincfg, "PWM setup"); diff --git a/arch/arm/src/lpc17xx/lpc17_sdcard.c b/arch/arm/src/lpc17xx/lpc17_sdcard.c index b020d901b80..80ab3727ffd 100644 --- a/arch/arm/src/lpc17xx/lpc17_sdcard.c +++ b/arch/arm/src/lpc17xx/lpc17_sdcard.c @@ -120,10 +120,10 @@ * SDCARD_MMCXFR_CLKDIV, and SDCARD_SDXFR_CLKDIV. */ -#define LPC17_CLCKCR_INIT (SDCARD_INIT_CLKDIV|SDCARD_CLOCK_WIDBUS_D1) -#define SDCARD_CLOCK_MMCXFR (SDCARD_MMCXFR_CLKDIV|SDCARD_CLOCK_WIDBUS_D1) -#define SDCARD_CLOCK_SDXFR (SDCARD_SDXFR_CLKDIV|SDCARD_CLOCK_WIDBUS_D1) -#define SDCARD_CLOCK_SDWIDEXFR (SDCARD_SDXFR_CLKDIV|SDCARD_CLOCK_WIDBUS_D4) +#define LPC17_CLCKCR_INIT (SDCARD_INIT_CLKDIV | SDCARD_CLOCK_WIDBUS_D1) +#define SDCARD_CLOCK_MMCXFR (SDCARD_MMCXFR_CLKDIV | SDCARD_CLOCK_WIDBUS_D1) +#define SDCARD_CLOCK_SDXFR (SDCARD_SDXFR_CLKDIV | SDCARD_CLOCK_WIDBUS_D1) +#define SDCARD_CLOCK_SDWIDEXFR (SDCARD_SDXFR_CLKDIV | SDCARD_CLOCK_WIDBUS_D4) /* Timing */ @@ -149,19 +149,19 @@ * controlled by the driver. */ -#define SDCARD_RXDMA32_CONTROL (DMACH_CONTROL_SBSIZE_8|DMACH_CONTROL_DBSIZE_8|\ - DMACH_CONTROL_SWIDTH_32BIT|DMACH_CONTROL_DWIDTH_32BIT|\ +#define SDCARD_RXDMA32_CONTROL (DMACH_CONTROL_SBSIZE_8 | DMACH_CONTROL_DBSIZE_8 | \ + DMACH_CONTROL_SWIDTH_32BIT | DMACH_CONTROL_DWIDTH_32BIT | \ DMACH_CONTROL_DI) -#define SDCARD_TXDMA32_CONTROL (DMACH_CONTROL_SBSIZE_8|DMACH_CONTROL_DBSIZE_8|\ - DMACH_CONTROL_SWIDTH_32BIT|DMACH_CONTROL_DWIDTH_32BIT|\ +#define SDCARD_TXDMA32_CONTROL (DMACH_CONTROL_SBSIZE_8 | DMACH_CONTROL_DBSIZE_8 | \ + DMACH_CONTROL_SWIDTH_32BIT | DMACH_CONTROL_DWIDTH_32BIT | \ DMACH_CONTROL_SI) /* DMA configuration register settings. Only the SRCPER, DSTPER, and * XFRTTYPE fields of the CONFIG register need be specified. */ -#define SDCARD_RXDMA32_CONFIG (DMACH_CONFIG_SRCPER_SDCARD|DMACH_CONFIG_XFRTYPE_P2M_SC) -#define SDCARD_TXDMA32_CONFIG (DMACH_CONFIG_DSTPER_SDCARD|DMACH_CONFIG_XFRTYPE_M2P_DC) +#define SDCARD_RXDMA32_CONFIG (DMACH_CONFIG_SRCPER_SDCARD | DMACH_CONFIG_XFRTYPE_P2M_SC) +#define SDCARD_TXDMA32_CONFIG (DMACH_CONFIG_DSTPER_SDCARD | DMACH_CONFIG_XFRTYPE_M2P_DC) /* FIFO sizes */ @@ -170,39 +170,39 @@ /* Data transfer interrupt mask bits */ -#define SDCARD_RECV_MASK (SDCARD_MASK0_DCRCFAILIE|SDCARD_MASK0_DTIMEOUTIE|\ - SDCARD_MASK0_DATAENDIE|SDCARD_MASK0_RXOVERRIE|\ - SDCARD_MASK0_RXFIFOHFIE|SDCARD_MASK0_STBITERRIE) -#define SDCARD_SEND_MASK (SDCARD_MASK0_DCRCFAILIE|SDCARD_MASK0_DTIMEOUTIE|\ - SDCARD_MASK0_DATAENDIE|SDCARD_MASK0_TXUNDERRIE|\ - SDCARD_MASK0_TXFIFOHEIE|SDCARD_MASK0_STBITERRIE) -#define SDCARD_DMARECV_MASK (SDCARD_MASK0_DCRCFAILIE|SDCARD_MASK0_DTIMEOUTIE|\ - SDCARD_MASK0_DATAENDIE|SDCARD_MASK0_RXOVERRIE|\ +#define SDCARD_RECV_MASK (SDCARD_MASK0_DCRCFAILIE | SDCARD_MASK0_DTIMEOUTIE | \ + SDCARD_MASK0_DATAENDIE | SDCARD_MASK0_RXOVERRIE | \ + SDCARD_MASK0_RXFIFOHFIE | SDCARD_MASK0_STBITERRIE) +#define SDCARD_SEND_MASK (SDCARD_MASK0_DCRCFAILIE | SDCARD_MASK0_DTIMEOUTIE | \ + SDCARD_MASK0_DATAENDIE | SDCARD_MASK0_TXUNDERRIE | \ + SDCARD_MASK0_TXFIFOHEIE | SDCARD_MASK0_STBITERRIE) +#define SDCARD_DMARECV_MASK (SDCARD_MASK0_DCRCFAILIE | SDCARD_MASK0_DTIMEOUTIE | \ + SDCARD_MASK0_DATAENDIE | SDCARD_MASK0_RXOVERRIE | \ SDCARD_MASK0_STBITERRIE) -#define SDCARD_DMASEND_MASK (SDCARD_MASK0_DCRCFAILIE|SDCARD_MASK0_DTIMEOUTIE|\ - SDCARD_MASK0_DATAENDIE|SDCARD_MASK0_TXUNDERRIE|\ +#define SDCARD_DMASEND_MASK (SDCARD_MASK0_DCRCFAILIE | SDCARD_MASK0_DTIMEOUTIE | \ + SDCARD_MASK0_DATAENDIE | SDCARD_MASK0_TXUNDERRIE | \ SDCARD_MASK0_STBITERRIE) /* Event waiting interrupt mask bits */ #define SDCARD_CMDDONE_STA (SDCARD_STATUS_CMDSENT) -#define SDCARD_RESPDONE_STA (SDCARD_STATUS_CTIMEOUT|SDCARD_STATUS_CCRCFAIL|\ +#define SDCARD_RESPDONE_STA (SDCARD_STATUS_CTIMEOUT | SDCARD_STATUS_CCRCFAIL | \ SDCARD_STATUS_CMDREND) #define SDCARD_XFRDONE_STA (0) #define SDCARD_CMDDONE_MASK (SDCARD_MASK0_CMDSENTIE) -#define SDCARD_RESPDONE_MASK (SDCARD_MASK0_CCRCFAILIE|SDCARD_MASK0_CTIMEOUTIE|\ +#define SDCARD_RESPDONE_MASK (SDCARD_MASK0_CCRCFAILIE | SDCARD_MASK0_CTIMEOUTIE | \ SDCARD_MASK0_CMDRENDIE) #define SDCARD_XFRDONE_MASK (0) #define SDCARD_CMDDONE_ICR (SDCARD_CLEAR_CMDSENTC) -#define SDCARD_RESPDONE_ICR (SDCARD_CLEAR_CTIMEOUTC|SDCARD_CLEAR_CCRCFAILC|\ +#define SDCARD_RESPDONE_ICR (SDCARD_CLEAR_CTIMEOUTC | SDCARD_CLEAR_CCRCFAILC | \ SDCARD_CLEAR_CMDRENDC) -#define SDCARD_XFRDONE_ICR (SDCARD_CLEAR_DATAENDC|SDCARD_CLEAR_DCRCFAILC|\ - SDCARD_CLEAR_DTIMEOUTC|SDCARD_CLEAR_RXOVERRC|\ - SDCARD_CLEAR_TXUNDERRC|SDCARD_CLEAR_STBITERRC) +#define SDCARD_XFRDONE_ICR (SDCARD_CLEAR_DATAENDC | SDCARD_CLEAR_DCRCFAILC | \ + SDCARD_CLEAR_DTIMEOUTC | SDCARD_CLEAR_RXOVERRC | \ + SDCARD_CLEAR_TXUNDERRC | SDCARD_CLEAR_STBITERRC) -#define SDCARD_WAITALL_ICR (SDCARD_CMDDONE_ICR|SDCARD_RESPDONE_ICR|\ +#define SDCARD_WAITALL_ICR (SDCARD_CMDDONE_ICR | SDCARD_RESPDONE_ICR | \ SDCARD_XFRDONE_ICR) /* Let's wait until we have both SD card transfer complete and DMA complete. */ @@ -516,13 +516,15 @@ static inline void lpc17_setclock(uint32_t clkcr) /* Clear CLKDIV, PWRSAV, BYPASS, and WIDBUS bits */ - regval &= ~(SDCARD_CLOCK_CLKDIV_MASK|SDCARD_CLOCK_PWRSAV|SDCARD_CLOCK_BYPASS| - SDCARD_CLOCK_WIDBUS|SDCARD_CLOCK_CLKEN); + regval &= ~(SDCARD_CLOCK_CLKDIV_MASK | SDCARD_CLOCK_PWRSAV | + SDCARD_CLOCK_BYPASS | SDCARD_CLOCK_WIDBUS | + SDCARD_CLOCK_CLKEN); /* Replace with user provided settings */ - clkcr &= (SDCARD_CLOCK_CLKDIV_MASK|SDCARD_CLOCK_PWRSAV|SDCARD_CLOCK_BYPASS| - SDCARD_CLOCK_WIDBUS|SDCARD_CLOCK_CLKEN); + clkcr &= (SDCARD_CLOCK_CLKDIV_MASK | SDCARD_CLOCK_PWRSAV | + SDCARD_CLOCK_BYPASS | SDCARD_CLOCK_WIDBUS | + SDCARD_CLOCK_CLKEN); regval |= clkcr; putreg32(regval, LPC17_SDCARD_CLOCK); @@ -617,7 +619,7 @@ static void lpc17_setpwrctrl(uint32_t pwrctrl) */ regval = getreg32(LPC17_SDCARD_PWR); - regval &= ~(SDCARD_PWR_CTRL_MASK | SDCARD_PWR_OPENDRAIN | SDCARD_PWR_ROD); + regval &= ~(SDCARD_PWR_CTRL_MASK | SDCARD_PWR_OPENDRAIN | SDCARD_PWR_ROD); regval |= pwrctrl; putreg32(regval, LPC17_SDCARD_PWR); } @@ -805,7 +807,7 @@ static void lpc17_dmacallback(DMA_HANDLE handle, void *arg, int status) * Transfer. */ - lpc17_sample((struct lpc17_dev_s*)arg, SAMPLENDX_DMA_CALLBACK); + lpc17_sample((struct lpc17_dev_s *)arg, SAMPLENDX_DMA_CALLBACK); /* Get the result of the DMA transfer */ @@ -890,9 +892,11 @@ static void lpc17_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl) */ regval = getreg32(LPC17_SDCARD_DCTRL); - regval &= ~(SDCARD_DCTRL_DTDIR|SDCARD_DCTRL_DTMODE|SDCARD_DCTRL_DBLOCKSIZE_MASK); - dctrl &= (SDCARD_DCTRL_DTDIR|SDCARD_DCTRL_DTMODE|SDCARD_DCTRL_DBLOCKSIZE_MASK); - regval |= (dctrl|SDCARD_DCTRL_DTEN); + regval &= ~(SDCARD_DCTRL_DTDIR | SDCARD_DCTRL_DTMODE | + SDCARD_DCTRL_DBLOCKSIZE_MASK); + dctrl &= (SDCARD_DCTRL_DTDIR | SDCARD_DCTRL_DTMODE | + SDCARD_DCTRL_DBLOCKSIZE_MASK); + regval |= (dctrl | SDCARD_DCTRL_DTEN); putreg32(regval, LPC17_SDCARD_DCTRL); } @@ -917,8 +921,8 @@ static void lpc17_datadisable(void) /* Reset DCTRL DTEN, DTDIR, DTMODE, DMAEN, and DBLOCKSIZE fields */ regval = getreg32(LPC17_SDCARD_DCTRL); - regval &= ~(SDCARD_DCTRL_DTEN|SDCARD_DCTRL_DTDIR|SDCARD_DCTRL_DTMODE| - SDCARD_DCTRL_DMAEN|SDCARD_DCTRL_DBLOCKSIZE_MASK); + regval &= ~(SDCARD_DCTRL_DTEN | SDCARD_DCTRL_DTDIR | SDCARD_DCTRL_DTMODE | + SDCARD_DCTRL_DMAEN | SDCARD_DCTRL_DBLOCKSIZE_MASK); putreg32(regval, LPC17_SDCARD_DCTRL); } @@ -1027,7 +1031,7 @@ static void lpc17_recvfifo(struct lpc17_dev_s *priv) { /* Transfer any trailing fractional word */ - uint8_t *ptr = (uint8_t*)priv->buffer; + uint8_t *ptr = (uint8_t *)priv->buffer; int i; for (i = 0; i < priv->remaining; i++) @@ -1216,30 +1220,30 @@ static int lpc17_interrupt(int irq, void *context) #ifdef CONFIG_SDIO_DMA if (!priv->dmamode) #endif - { - /* Is the RX FIFO half full or more? Is so then we must be - * processing a receive transaction. - */ - - if ((pending & SDCARD_STATUS_RXFIFOHF) != 0) - { - /* Receive data from the RX FIFO */ - - lpc17_recvfifo(priv); - } - - /* Otherwise, Is the transmit FIFO half empty or less? If so we must - * be processing a send transaction. NOTE: We can't be processing - * both! + { + /* Is the RX FIFO half full or more? Is so then we must be + * processing a receive transaction. */ - else if ((pending & SDCARD_STATUS_TXFIFOHE) != 0) - { - /* Send data via the TX FIFO */ + if ((pending & SDCARD_STATUS_RXFIFOHF) != 0) + { + /* Receive data from the RX FIFO */ - lpc17_sendfifo(priv); - } - } + lpc17_recvfifo(priv); + } + + /* Otherwise, Is the transmit FIFO half empty or less? If so we must + * be processing a send transaction. NOTE: We can't be processing + * both! + */ + + else if ((pending & SDCARD_STATUS_TXFIFOHE) != 0) + { + /* Send data via the TX FIFO */ + + lpc17_sendfifo(priv); + } + } /* Handle data end events */ @@ -1294,7 +1298,7 @@ static int lpc17_interrupt(int irq, void *context) /* Terminate the transfer with an error */ flldbg("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining); - lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_ERROR); + lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } /* Handle data timeout error */ @@ -1304,7 +1308,7 @@ static int lpc17_interrupt(int irq, void *context) /* Terminate the transfer with an error */ flldbg("ERROR: Data timeout, remaining: %d\n", priv->remaining); - lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_TIMEOUT); + lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT); } /* Handle RX FIFO overrun error */ @@ -1314,7 +1318,7 @@ static int lpc17_interrupt(int irq, void *context) /* Terminate the transfer with an error */ flldbg("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining); - lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_ERROR); + lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } /* Handle TX FIFO underrun error */ @@ -1324,7 +1328,7 @@ static int lpc17_interrupt(int irq, void *context) /* Terminate the transfer with an error */ flldbg("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining); - lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_ERROR); + lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } /* Handle start bit error */ @@ -1334,8 +1338,8 @@ static int lpc17_interrupt(int irq, void *context) /* Terminate the transfer with an error */ flldbg("ERROR: Start bit, remaining: %d\n", priv->remaining); - lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_ERROR); - } + lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } } /* Handle wait events *************************************************/ @@ -1353,7 +1357,7 @@ static int lpc17_interrupt(int irq, void *context) { /* Yes.. wake the thread up */ - putreg32(SDCARD_RESPDONE_ICR|SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); + putreg32(SDCARD_RESPDONE_ICR | SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); lpc17_endwait(priv, SDIOWAIT_RESPONSEDONE); } } @@ -1472,7 +1476,7 @@ static void lpc17_reset(FAR struct sdio_dev_s *dev) /* Configure and enable the SD card peripheral */ - lpc17_setclock(LPC17_CLCKCR_INIT|SDCARD_CLOCK_CLKEN); + lpc17_setclock(LPC17_CLCKCR_INIT | SDCARD_CLOCK_CLKEN); lpc17_setpwrctrl(SDCARD_PWR_CTRL_ON); irqrestore(flags); @@ -1653,8 +1657,9 @@ static int lpc17_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg) /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, and CPSMEN bits */ regval = getreg32(LPC17_SDCARD_CMD); - regval &= ~(SDCARD_CMD_INDEX_MASK|SDCARD_CMD_WAITRESP_MASK| - SDCARD_CMD_WAITINT|SDCARD_CMD_WAITPEND|SDCARD_CMD_CPSMEN); + regval &= ~(SDCARD_CMD_INDEX_MASK | SDCARD_CMD_WAITRESP_MASK | + SDCARD_CMD_WAITINT | SDCARD_CMD_WAITPEND | + SDCARD_CMD_CPSMEN); /* Set WAITRESP bits */ @@ -1688,7 +1693,7 @@ static int lpc17_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg) /* Write the SD card CMD */ - putreg32(SDCARD_RESPDONE_ICR|SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); + putreg32(SDCARD_RESPDONE_ICR | SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); putreg32(regval, LPC17_SDCARD_CMD); return OK; } @@ -1731,7 +1736,7 @@ static int lpc17_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, /* Save the destination buffer information for use by the interrupt handler */ - priv->buffer = (uint32_t*)buffer; + priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; #ifdef CONFIG_SDIO_DMA priv->dmamode = false; @@ -1740,7 +1745,8 @@ static int lpc17_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, /* Then set up the SD card data path */ dblocksize = lpc17_log2(nbytes) << SDCARD_DCTRL_DBLOCKSIZE_SHIFT; - lpc17_dataconfig(SDCARD_DTIMER_DATATIMEOUT, nbytes, dblocksize|SDCARD_DCTRL_DTDIR); + lpc17_dataconfig(SDCARD_DTIMER_DATATIMEOUT, nbytes, + dblocksize | SDCARD_DCTRL_DTDIR); /* And enable interrupts */ @@ -1785,7 +1791,7 @@ static int lpc17_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer /* Save the source buffer information for use by the interrupt handler */ - priv->buffer = (uint32_t*)buffer; + priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; #ifdef CONFIG_SDIO_DMA priv->dmamode = false; @@ -1822,7 +1828,7 @@ static int lpc17_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer static int lpc17_cancel(FAR struct sdio_dev_s *dev) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s*)dev; + struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev; /* Disable all transfer- and event- related interrupts */ @@ -2027,7 +2033,7 @@ static int lpc17_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t /* Clear all pending message completion events and return the R1/R6 response */ - putreg32(SDCARD_RESPDONE_ICR|SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); + putreg32(SDCARD_RESPDONE_ICR | SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); *rshort = getreg32(LPC17_SDCARD_RESP0); return ret; } @@ -2074,7 +2080,7 @@ static int lpc17_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo /* Return the long response */ - putreg32(SDCARD_RESPDONE_ICR|SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); + putreg32(SDCARD_RESPDONE_ICR | SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); if (rlong) { rlong[0] = getreg32(LPC17_SDCARD_RESP0); @@ -2123,7 +2129,7 @@ static int lpc17_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r } } - putreg32(SDCARD_RESPDONE_ICR|SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); + putreg32(SDCARD_RESPDONE_ICR | SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); if (rshort) { *rshort = getreg32(LPC17_SDCARD_RESP0); @@ -2135,7 +2141,7 @@ static int lpc17_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r static int lpc17_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rnotimpl) { - putreg32(SDCARD_RESPDONE_ICR|SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); + putreg32(SDCARD_RESPDONE_ICR | SDCARD_CMDDONE_ICR, LPC17_SDCARD_CLEAR); return -ENOSYS; } @@ -2166,7 +2172,7 @@ static int lpc17_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t static void lpc17_waitenable(FAR struct sdio_dev_s *dev, sdio_eventset_t eventset) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s*)dev; + struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev; uint32_t waitmask; DEBUGASSERT(priv != NULL); @@ -2225,7 +2231,7 @@ static void lpc17_waitenable(FAR struct sdio_dev_s *dev, static sdio_eventset_t lpc17_eventwait(FAR struct sdio_dev_s *dev, uint32_t timeout) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s*)dev; + struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev; sdio_eventset_t wkupevent = 0; irqstate_t flags; int ret; @@ -2250,10 +2256,10 @@ static sdio_eventset_t lpc17_eventwait(FAR struct sdio_dev_s *dev, if (!timeout) { - /* Then just tell the caller that we already timed out */ + /* Then just tell the caller that we already timed out */ - wkupevent = SDIOWAIT_TIMEOUT; - goto errout; + wkupevent = SDIOWAIT_TIMEOUT; + goto errout; } /* Start the watchdog timer */ @@ -2263,8 +2269,8 @@ static sdio_eventset_t lpc17_eventwait(FAR struct sdio_dev_s *dev, 1, (uint32_t)priv); if (ret != OK) { - fdbg("ERROR: wd_start failed: %d\n", ret); - } + fdbg("ERROR: wd_start failed: %d\n", ret); + } } /* Loop until the event (or the timeout occurs). Race conditions are avoided @@ -2273,7 +2279,7 @@ static sdio_eventset_t lpc17_eventwait(FAR struct sdio_dev_s *dev, * may have already occurred before this function was called! */ - for (;;) + for (; ; ) { /* Wait for an event in event set to occur. If this the event has already * occurred, then the semaphore will already have been incremented and @@ -2333,7 +2339,7 @@ errout: static void lpc17_callbackenable(FAR struct sdio_dev_s *dev, sdio_eventset_t eventset) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s*)dev; + struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev; fvdbg("eventset: %02x\n", eventset); DEBUGASSERT(priv != NULL); @@ -2367,7 +2373,7 @@ static void lpc17_callbackenable(FAR struct sdio_dev_s *dev, static int lpc17_registercallback(FAR struct sdio_dev_s *dev, worker_t callback, void *arg) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s*)dev; + struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev; /* Disable callbacks and register this callback and is argument */ @@ -2445,14 +2451,15 @@ static int lpc17_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, /* Save the destination buffer information for use by the interrupt handler */ - priv->buffer = (uint32_t*)buffer; + priv->buffer = (uint32_t *)buffer; priv->remaining = buflen; priv->dmamode = true; /* Then set up the SD card data path */ dblocksize = lpc17_log2(buflen) << SDCARD_DCTRL_DBLOCKSIZE_SHIFT; - lpc17_dataconfig(SDCARD_DTIMER_DATATIMEOUT, buflen, dblocksize|SDCARD_DCTRL_DTDIR); + lpc17_dataconfig(SDCARD_DTIMER_DATATIMEOUT, buflen, + dblocksize | SDCARD_DCTRL_DTDIR); /* Configure the RX DMA */ @@ -2523,7 +2530,7 @@ static int lpc17_dmasendsetup(FAR struct sdio_dev_s *dev, /* Save the source buffer information for use by the interrupt handler */ - priv->buffer = (uint32_t*)buffer; + priv->buffer = (uint32_t *)buffer; priv->remaining = buflen; priv->dmamode = true; @@ -2578,7 +2585,7 @@ static int lpc17_dmasendsetup(FAR struct sdio_dev_s *dev, static void lpc17_callback(void *arg) { - struct lpc17_dev_s *priv = (struct lpc17_dev_s*)arg; + struct lpc17_dev_s *priv = (struct lpc17_dev_s *)arg; /* Is a callback registered? */ @@ -2595,8 +2602,8 @@ static void lpc17_callback(void *arg) /* Media is present. Is the media inserted event enabled? */ if ((priv->cbevents & SDIOMEDIA_INSERTED) == 0) - { - /* No... return without performing the callback */ + { + /* No... return without performing the callback */ return; } diff --git a/arch/arm/src/lpc17xx/lpc17_serial.c b/arch/arm/src/lpc17xx/lpc17_serial.c index 4ffa10cc976..2c2e773502b 100644 --- a/arch/arm/src/lpc17xx/lpc17_serial.c +++ b/arch/arm/src/lpc17xx/lpc17_serial.c @@ -877,17 +877,17 @@ static inline uint32_t lpc17_uartdl(uint32_t baud) static int up_setup(struct uart_dev_s *dev) { #ifndef CONFIG_SUPPRESS_UART_CONFIG - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint16_t dl; uint32_t lcr; /* Clear fifos */ - up_serialout(priv, LPC17_UART_FCR_OFFSET, (UART_FCR_RXRST|UART_FCR_TXRST)); + up_serialout(priv, LPC17_UART_FCR_OFFSET, (UART_FCR_RXRST | UART_FCR_TXRST)); /* Set trigger */ - up_serialout(priv, LPC17_UART_FCR_OFFSET, (UART_FCR_FIFOEN|UART_FCR_RXTRIGGER_8)); + up_serialout(priv, LPC17_UART_FCR_OFFSET, (UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8)); /* Set up the IER */ @@ -913,11 +913,11 @@ static int up_setup(struct uart_dev_s *dev) if (priv->parity == 1) { - lcr |= (UART_LCR_PE|UART_LCR_PS_ODD); + lcr |= (UART_LCR_PE | UART_LCR_PS_ODD); } else if (priv->parity == 2) { - lcr |= (UART_LCR_PE|UART_LCR_PS_EVEN); + lcr |= (UART_LCR_PE | UART_LCR_PS_EVEN); } /* Enter DLAB=1 */ @@ -941,7 +941,8 @@ static int up_setup(struct uart_dev_s *dev) /* Configure the FIFOs */ up_serialout(priv, LPC17_UART_FCR_OFFSET, - (UART_FCR_RXTRIGGER_8|UART_FCR_TXRST|UART_FCR_RXRST|UART_FCR_FIFOEN)); + (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST | UART_FCR_RXRST | + UART_FCR_FIFOEN)); /* Enable Auto-RTS and Auto-CS Flow Control in the Modem Control Register */ @@ -949,7 +950,7 @@ static int up_setup(struct uart_dev_s *dev) if (priv->uartbase == LPC17_UART1_BASE) { #if defined(CONFIG_UART1_IFLOWCONTROL) && defined(CONFIG_UART1_OFLOWCONTROL) - up_serialout(priv, LPC17_UART_MCR_OFFSET, (UART_MCR_RTSEN|UART_MCR_CTSEN)); + up_serialout(priv, LPC17_UART_MCR_OFFSET, (UART_MCR_RTSEN | UART_MCR_CTSEN)); #elif defined(CONFIG_UART1_IFLOWCONTROL) up_serialout(priv, LPC17_UART_MCR_OFFSET, UART_MCR_RTSEN); #else @@ -972,7 +973,7 @@ static int up_setup(struct uart_dev_s *dev) static void up_shutdown(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; up_disableuartint(priv, NULL); } @@ -993,7 +994,7 @@ static void up_shutdown(struct uart_dev_s *dev) static int up_attach(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -1001,11 +1002,11 @@ static int up_attach(struct uart_dev_s *dev) ret = irq_attach(priv->irq, up_interrupt); if (ret == OK) { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the UART - */ + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ - up_enable_irq(priv->irq); + up_enable_irq(priv->irq); } return ret; @@ -1023,7 +1024,7 @@ static int up_attach(struct uart_dev_s *dev) static void up_detach(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -1078,7 +1079,7 @@ static int up_interrupt(int irq, void *context) { PANIC(); } - priv = (struct up_dev_s*)dev->priv; + priv = (struct up_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, * until we have been looping for a long time. @@ -1172,7 +1173,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; int ret = OK; switch (cmd) @@ -1180,7 +1181,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct up_dev_s *user = (struct up_dev_s*)arg; + struct up_dev_s *user = (struct up_dev_s *)arg; if (!user) { ret = -EINVAL; @@ -1213,7 +1214,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_TERMIOS case TCGETS: { - struct termios *termiosp = (struct termios*)arg; + struct termios *termiosp = (struct termios *)arg; if (!termiosp) { @@ -1233,7 +1234,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) case TCSETS: { - struct termios *termiosp = (struct termios*)arg; + struct termios *termiosp = (struct termios *)arg; uint32_t lcr; /* Holds current values of line control register */ uint16_t dl; /* Divisor latch */ @@ -1302,7 +1303,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) static int up_receive(struct uart_dev_s *dev, uint32_t *status) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint32_t rbr; *status = up_serialin(priv, LPC17_UART_LSR_OFFSET); @@ -1320,7 +1321,7 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status) static void up_rxint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; if (enable) { #ifndef CONFIG_SUPPRESS_SERIAL_INTS @@ -1345,7 +1346,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) static bool up_rxavailable(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return ((up_serialin(priv, LPC17_UART_LSR_OFFSET) & UART_LSR_RDR) != 0); } @@ -1359,7 +1360,7 @@ static bool up_rxavailable(struct uart_dev_s *dev) static void up_send(struct uart_dev_s *dev, int ch) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; up_serialout(priv, LPC17_UART_THR_OFFSET, (uint32_t)ch); } @@ -1373,7 +1374,7 @@ static void up_send(struct uart_dev_s *dev, int ch) static void up_txint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; flags = irqsave(); @@ -1409,7 +1410,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) static bool up_txready(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return ((up_serialin(priv, LPC17_UART_LSR_OFFSET) & UART_LSR_THRE) != 0); } @@ -1423,7 +1424,7 @@ static bool up_txready(struct uart_dev_s *dev) static bool up_txempty(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return ((up_serialin(priv, LPC17_UART_LSR_OFFSET) & UART_LSR_THRE) != 0); } @@ -1536,7 +1537,7 @@ void up_serialinit(void) int up_putc(int ch) { #ifdef HAVE_CONSOLE - struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv; + struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv; uint32_t ier; up_disableuartint(priv, &ier); #endif diff --git a/arch/arm/src/lpc17xx/lpc17_spi.c b/arch/arm/src/lpc17xx/lpc17_spi.c index 58fbb7de9bb..dfc35251d6e 100644 --- a/arch/arm/src/lpc17xx/lpc17_spi.c +++ b/arch/arm/src/lpc17xx/lpc17_spi.c @@ -264,7 +264,9 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) divisor = SPI_CLOCK / frequency; - /* The SPI CCR register must contain an even number greater than or equal to 8. */ + /* The SPI CCR register must contain an even number greater than or equal + * to 8. + */ if (divisor < 8) { @@ -325,7 +327,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) /* Yes... Set CR appropriately */ regval = getreg32(LPC17_SPI_CR); - regval &= ~(SPI_CR_CPOL|SPI_CR_CPHA); + regval &= ~(SPI_CR_CPOL | SPI_CR_CPHA); switch (mode) { @@ -341,7 +343,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) break; case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ - regval |= (SPI_CR_CPOL|SPI_CR_CPHA); + regval |= (SPI_CR_CPOL | SPI_CR_CPHA); break; default: @@ -458,7 +460,7 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords) { - FAR uint8_t *ptr = (FAR uint8_t*)buffer; + FAR uint8_t *ptr = (FAR uint8_t *)buffer; uint8_t data; spidbg("nwords: %d\n", nwords); @@ -504,7 +506,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords) { - FAR uint8_t *ptr = (FAR uint8_t*)buffer; + FAR uint8_t *ptr = (FAR uint8_t *)buffer; spidbg("nwords: %d\n", nwords); while (nwords) @@ -520,16 +522,16 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw * data transfer. */ - while ((getreg32(LPC17_SPI_SR) & SPI_SR_SPIF) == 0); + while ((getreg32(LPC17_SPI_SR) & SPI_SR_SPIF) == 0); - /* Read the SPI Status Register again to clear the status bit */ + /* Read the SPI Status Register again to clear the status bit */ - (void)getreg32(LPC17_SPI_SR); + (void)getreg32(LPC17_SPI_SR); - /* Read the received data from the SPI Data Register */ + /* Read the received data from the SPI Data Register */ - *ptr++ = (uint8_t)getreg32(LPC17_SPI_DR); - nwords--; + *ptr++ = (uint8_t)getreg32(LPC17_SPI_DR); + nwords--; } } @@ -587,7 +589,8 @@ FAR struct spi_dev_s *lpc17_spiinitialize(int port) /* Configure 8-bit SPI mode and master mode */ - putreg32(SPI_CR_BITS_8BITS|SPI_CR_BITENABLE|SPI_CR_MSTR, LPC17_SPI_CR); + putreg32(SPI_CR_BITS_8BITS | SPI_CR_BITENABLE | SPI_CR_MSTR, + LPC17_SPI_CR); /* Set the initial SPI configuration */ diff --git a/arch/arm/src/lpc17xx/lpc17_ssp.c b/arch/arm/src/lpc17xx/lpc17_ssp.c index dc44e95a254..60366784231 100644 --- a/arch/arm/src/lpc17xx/lpc17_ssp.c +++ b/arch/arm/src/lpc17xx/lpc17_ssp.c @@ -514,7 +514,7 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) /* Yes... Set CR0 appropriately */ regval = ssp_getreg(priv, LPC17_SSP_CR0_OFFSET); - regval &= ~(SSP_CR0_CPOL|SSP_CR0_CPHA); + regval &= ~(SSP_CR0_CPOL | SSP_CR0_CPHA); switch (mode) { @@ -530,7 +530,7 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) break; case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ - regval |= (SSP_CR0_CPOL|SSP_CR0_CPHA); + regval |= (SSP_CR0_CPOL | SSP_CR0_CPHA); break; default: @@ -1001,7 +1001,7 @@ FAR struct spi_dev_s *lpc17_sspinitialize(int port) /* Configure 8-bit SPI mode */ - ssp_putreg(priv, LPC17_SSP_CR0_OFFSET, SSP_CR0_DSS_8BIT|SSP_CR0_FRF_SPI); + ssp_putreg(priv, LPC17_SSP_CR0_OFFSET, SSP_CR0_DSS_8BIT | SSP_CR0_FRF_SPI); /* Disable the SSP and all interrupts (we'll poll for all data) */ diff --git a/arch/arm/src/lpc17xx/lpc17_start.c b/arch/arm/src/lpc17xx/lpc17_start.c index 82cb30be122..8d95518d02d 100644 --- a/arch/arm/src/lpc17xx/lpc17_start.c +++ b/arch/arm/src/lpc17xx/lpc17_start.c @@ -257,5 +257,5 @@ void __start(void) /* Shouldn't get here */ - for (;;); + for (; ; ); } diff --git a/arch/arm/src/lpc17xx/lpc17_timer.c b/arch/arm/src/lpc17xx/lpc17_timer.c index bc177f16857..5869a3188d0 100644 --- a/arch/arm/src/lpc17xx/lpc17_timer.c +++ b/arch/arm/src/lpc17xx/lpc17_timer.c @@ -400,44 +400,44 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev) regval = getreg32(LPC17_SYSCON_PCLKSEL0); regval &= ~(0x3 << 2); - regval |= (0x1 << 2); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ + regval |= (0x1 << 2); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ regval &= ~(0x3 << 4); - regval |= (0x1 << 4); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ + regval |= (0x1 << 4); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ putreg32(regval, LPC17_SYSCON_PCLKSEL0); regval = getreg32(LPC17_SYSCON_PCLKSEL1); regval &= ~(0x3 << 12); - regval |= (0x1 << 12); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ + regval |= (0x1 << 12); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ regval &= ~(0x3 << 14); - regval |= (0x1 << 14); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ + regval |= (0x1 << 14); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ putreg32(regval, LPC17_SYSCON_PCLKSEL1); priv->pclk = (0x1 << 12) | (0x1 << 4); - putreg32(1000, LPC17_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */ + putreg32(1000, LPC17_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */ - putreg32(1, LPC17_TMR0_PR); /* Prescaler count frequency: Fpclk/1 */ - putreg32(~(0x3 << 0), LPC17_TMR0_CCR); /* Prescaler count frequency: Fpclk/1 */ - putreg32(~(0x3 << 0), LPC17_TMR0_CTCR);/* Prescaler count frequency: Fpclk/1 */ - putreg32((2 << 3), LPC17_TMR0_MCR); /* Reset on match register MR1 */ + putreg32(1, LPC17_TMR0_PR); /* Prescaler count frequency: Fpclk/1 */ + putreg32(~(0x3 << 0), LPC17_TMR0_CCR); /* Prescaler count frequency: Fpclk/1 */ + putreg32(~(0x3 << 0), LPC17_TMR0_CTCR); /* Prescaler count frequency: Fpclk/1 */ + putreg32((2 << 3), LPC17_TMR0_MCR); /* Reset on match register MR1 */ /* Output bit toggle on external match event External match on MR1, Toggle * external bit */ - putreg32(((1 << 1)|(3 << 6)), LPC17_TMR0_EMR); - putreg32((1 << 0), LPC17_TMR0_TCR); /* Start timer0 */ + putreg32(((1 << 1) | (3 << 6)), LPC17_TMR0_EMR); + putreg32((1 << 0), LPC17_TMR0_TCR); /* Start timer0 */ /* Configure the output pins GPIO3.26 */ lpc17_configgpio(GPIO_MAT0p1_2); - putreg32(500, LPC17_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */ + putreg32(500, LPC17_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */ - putreg32(1, LPC17_TMR1_PR); /* Prescaler count frequency:Fpclk/1 */ - putreg32(~(0x3 << 0), LPC17_TMR1_CCR); /* Prescaler count frequency:Fpclk/1 */ - putreg32(~(0x3 << 0), LPC17_TMR1_CTCR);/* Prescaler count frequency:Fpclk/1 */ - putreg32((2 << 0), LPC17_TMR1_MCR); /* Reset on match register MR0 */ -// putreg32(((1 << 0)|(3 << 4)), LPC17_TMR1_EMR); /* Output bit toggle on external match event MAT0 */ - putreg32((1 << 0), LPC17_TMR1_TCR); /* Start timer1 */ + putreg32(1, LPC17_TMR1_PR); /* Prescaler count frequency:Fpclk/1 */ + putreg32(~(0x3 << 0), LPC17_TMR1_CCR); /* Prescaler count frequency:Fpclk/1 */ + putreg32(~(0x3 << 0), LPC17_TMR1_CTCR); /* Prescaler count frequency:Fpclk/1 */ + putreg32((2 << 0), LPC17_TMR1_MCR); /* Reset on match register MR0 */ +// putreg32(((1 << 0 )| (3 << 4)), LPC17_TMR1_EMR); /* Output bit toggle on external match event MAT0 */ + putreg32((1 << 0), LPC17_TMR1_TCR); /* Start timer1 */ /* configure the output pins GPIO3.26 */ // lpc17_configgpio(GPIO_MAT0p1_2); diff --git a/arch/arm/src/lpc17xx/lpc17_timerisr.c b/arch/arm/src/lpc17xx/lpc17_timerisr.c index f61cf58073b..d0f48a57d1d 100644 --- a/arch/arm/src/lpc17xx/lpc17_timerisr.c +++ b/arch/arm/src/lpc17xx/lpc17_timerisr.c @@ -143,7 +143,8 @@ void up_timer_initialize(void) /* Enable SysTick interrupts */ - putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); + putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | + NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); /* And enable the timer interrupt */ diff --git a/arch/arm/src/lpc17xx/lpc17_usbdev.c b/arch/arm/src/lpc17xx/lpc17_usbdev.c index d53a28e94c7..5463f28935e 100644 --- a/arch/arm/src/lpc17xx/lpc17_usbdev.c +++ b/arch/arm/src/lpc17xx/lpc17_usbdev.c @@ -660,7 +660,7 @@ static uint32_t lpc17_usbcmd(uint16_t cmd, uint8_t data) /* Disable interrupt and clear CDFULL and CCEMPTY interrupt status */ flags = irqsave(); - lpc17_putreg(USBDEV_INT_CDFULL|USBDEV_INT_CCEMPTY, LPC17_USBDEV_INTCLR); + lpc17_putreg(USBDEV_INT_CDFULL | USBDEV_INT_CCEMPTY, LPC17_USBDEV_INTCLR); /* Shift the command in position and mask out extra bits */ @@ -870,7 +870,7 @@ static void lpc17_epwrite(uint8_t epphy, const uint8_t *data, uint32_t nbytes) { if (aligned) { - value = *(uint32_t*)data; + value = *(uint32_t *)data; } else { @@ -919,11 +919,11 @@ static int lpc17_epread(uint8_t epphy, uint8_t *data, uint32_t nbytes) if (data) { - if (((uint32_t)data & 3) == 0) + if (((uint32_t)data & 3) == 0) { aligned = 1; } - else + else { aligned = 2; } @@ -951,7 +951,7 @@ static int lpc17_epread(uint8_t epphy, uint8_t *data, uint32_t nbytes) value = lpc17_getreg(LPC17_USBDEV_RXDATA); if (aligned == 1) { - *(uint32_t*)data = value; + *(uint32_t *)data = value; data += 4; } else if (aligned == 2) @@ -1331,7 +1331,7 @@ static void lpc17_eprealize(struct lpc17_ep_s *privep, bool prio, uint32_t packe /* Clear realize interrupt bit */ - lpc17_putreg(USBDEV_INT_EPRLZED,LPC17_USBDEV_INTCLR); + lpc17_putreg(USBDEV_INT_EPRLZED, LPC17_USBDEV_INTCLR); } /**************************************************************************** @@ -1487,7 +1487,8 @@ static void lpc17_usbreset(struct lpc17_usbdev_s *priv) /* Enable Device interrupts */ - lpc17_putreg(USB_SLOW_INT|USB_DEVSTATUS_INT|USB_FAST_INT|USB_FRAME_INT|USB_ERROR_INT, + lpc17_putreg(USB_SLOW_INT | USB_DEVSTATUS_INT | USB_FAST_INT | + USB_FRAME_INT | USB_ERROR_INT, LPC17_USBDEV_INTEN); /* Tell the class driver that we are disconnected. The class @@ -1580,7 +1581,7 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) /* Read EP0 data */ - ret = lpc17_epread(LPC17_EP0_OUT, (uint8_t*)&ctrl, USB_SIZEOF_CTRLREQ); + ret = lpc17_epread(LPC17_EP0_OUT, (uint8_t *)&ctrl, USB_SIZEOF_CTRLREQ); if (ret <= 0) { return; @@ -1638,7 +1639,8 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv) } else { - if ((lpc17_usbcmd(CMD_USBDEV_EPSELECT|privep->epphy, 0) & CMD_EPSELECT_ST) != 0) + if ((lpc17_usbcmd(CMD_USBDEV_EPSELECT | privep->epphy, 0) & + CMD_EPSELECT_ST) != 0) { response[0] = 1; /* Stalled */ } @@ -2070,7 +2072,7 @@ static int lpc17_usbinterrupt(int irq, FAR void *context) /* Check for low priority and high priority (non-DMA) interrupts */ usbintstatus = lpc17_getreg(LPC17_SYSCON_USBINTST); - if ((usbintstatus & (SYSCON_USBINTST_REQLP|SYSCON_USBINTST_REQHP)) != 0) + if ((usbintstatus & (SYSCON_USBINTST_REQLP | SYSCON_USBINTST_REQHP)) != 0) { #endif #ifdef CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT @@ -2080,10 +2082,10 @@ static int lpc17_usbinterrupt(int irq, FAR void *context) { /* Clear Fast EP interrupt */ - lpc17_putreg(USBDEV_INT_EPFAST, LPC17_USBDEV_INTCLR); - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_EPFAST), 0); + lpc17_putreg(USBDEV_INT_EPFAST, LPC17_USBDEV_INTCLR); + usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_EPFAST), 0); - /* Do what? */ + /* Do what? */ } #endif @@ -2143,31 +2145,31 @@ static int lpc17_usbinterrupt(int irq, FAR void *context) (uint16_t)g_usbdev.devstatus); if (DEVSTATUS_CONNECT(g_usbdev.devstatus)) { - /* Host is connected */ + /* Host is connected */ - if (!priv->attached) - { - /* We have a transition from unattached to attached */ + if (!priv->attached) + { + /* We have a transition from unattached to attached */ - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_CONNECTED), - (uint16_t)g_usbdev.devstatus); - priv->usbdev.speed = USB_SPEED_UNKNOWN; - lpc17_usbcmd(CMD_USBDEV_CONFIG, 0); - priv->attached = 1; + usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_CONNECTED), + (uint16_t)g_usbdev.devstatus); + priv->usbdev.speed = USB_SPEED_UNKNOWN; + lpc17_usbcmd(CMD_USBDEV_CONFIG, 0); + priv->attached = 1; } - } + } - /* Otherwise the host is not attached */ + /* Otherwise the host is not attached */ - else if (priv->attached) - { - usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_DISCONNECTED), - (uint16_t)g_usbdev.devstatus); - priv->usbdev.speed = USB_SPEED_UNKNOWN; - lpc17_usbcmd(CMD_USBDEV_CONFIG, 0); - priv->attached = 0; - priv->paddrset = 0; - } + else if (priv->attached) + { + usbtrace(TRACE_INTDECODE(LPC17_TRACEINTID_DISCONNECTED), + (uint16_t)g_usbdev.devstatus); + priv->usbdev.speed = USB_SPEED_UNKNOWN; + lpc17_usbcmd(CMD_USBDEV_CONFIG, 0); + priv->attached = 0; + priv->paddrset = 0; + } } /* Device suspend status */ @@ -2275,7 +2277,7 @@ static int lpc17_usbinterrupt(int irq, FAR void *context) if ((pending & 1) != 0) { - /* Yes.. clear the endpoint interrupt */ + /* Yes.. clear the endpoint interrupt */ (void)lpc17_epclrinterrupt(epphy); @@ -2304,7 +2306,7 @@ static int lpc17_usbinterrupt(int irq, FAR void *context) privep->txbusy = 0; lpc17_wrrequest(privep); - } + } else { /* OUT: host-to-device */ @@ -2313,8 +2315,8 @@ static int lpc17_usbinterrupt(int irq, FAR void *context) /* Read host data into the current read request */ - if (!lpc17_rqempty(privep)) - { + if (!lpc17_rqempty(privep)) + { lpc17_rdrequest(privep); } else @@ -2590,7 +2592,8 @@ static int lpc17_epconfigure(FAR struct usbdev_ep_s *ep, { lpc17_usbcmd(CMD_USBDEV_CONFIG, 1); } - return OK; + + return OK; } /**************************************************************************** @@ -3334,8 +3337,8 @@ void up_usbinitialize(void) /* Enable EP0 for OUT (host-to-device) */ - lpc17_usbcmd(CMD_USBDEV_SETADDRESS, CMD_USBDEV_SETADDRESS_DEVEN|0); - lpc17_usbcmd(CMD_USBDEV_SETADDRESS, CMD_USBDEV_SETADDRESS_DEVEN|0); + lpc17_usbcmd(CMD_USBDEV_SETADDRESS, CMD_USBDEV_SETADDRESS_DEVEN | 0); + lpc17_usbcmd(CMD_USBDEV_SETADDRESS, CMD_USBDEV_SETADDRESS_DEVEN | 0); /* Reset/Re-initialize the USB hardware */ diff --git a/arch/arm/src/lpc17xx/lpc17_usbhost.c b/arch/arm/src/lpc17xx/lpc17_usbhost.c index 237882eee46..0c13c7be3b0 100644 --- a/arch/arm/src/lpc17xx/lpc17_usbhost.c +++ b/arch/arm/src/lpc17xx/lpc17_usbhost.c @@ -664,7 +664,7 @@ static struct lpc17_gtd_s *lpc17_tdalloc(void) ret = (struct lpc17_gtd_s *)g_tdfree; if (ret) { - g_tdfree = ((struct lpc17_list_s*)ret)->flink; + g_tdfree = ((struct lpc17_list_s *)ret)->flink; } irqrestore(flags); @@ -715,7 +715,7 @@ static uint8_t *lpc17_tballoc(void) uint8_t *ret = (uint8_t *)g_tbfree; if (ret) { - g_tbfree = ((struct lpc17_list_s*)ret)->flink; + g_tbfree = ((struct lpc17_list_s *)ret)->flink; } return ret; } @@ -763,7 +763,7 @@ static uint8_t *lpc17_allocio(void) ret = (uint8_t *)g_iofree; if (ret) { - g_iofree = ((struct lpc17_list_s*)ret)->flink; + g_iofree = ((struct lpc17_list_s *)ret)->flink; } irqrestore(flags); @@ -818,7 +818,7 @@ static struct lpc17_xfrinfo_s *lpc17_alloc_xfrinfo(void) ret = (struct lpc17_xfrinfo_s *)g_xfrfree; if (ret) { - g_xfrfree = ((struct lpc17_list_s*)ret)->flink; + g_xfrfree = ((struct lpc17_list_s *)ret)->flink; } irqrestore(flags); @@ -1943,7 +1943,7 @@ static int lpc17_wait(struct usbhost_connection_s *conn, irqstate_t flags; flags = irqsave(); - for (;;) + for (; ; ) { /* Is there a change in the connection state of the single root hub * port? @@ -2208,11 +2208,11 @@ static int lpc17_epalloc(struct usbhost_driver_s *drvr, { /* Remove the ED from the freelist */ - g_edfree = ((struct lpc17_list_s*)ed)->flink; + g_edfree = ((struct lpc17_list_s *)ed)->flink; /* Configure the endpoint descriptor. */ - memset((void*)ed, 0, sizeof(struct lpc17_ed_s)); + memset((void *)ed, 0, sizeof(struct lpc17_ed_s)); hport = epdesc->hport; ed->hw.ctrl = (uint32_t)(hport->funcaddr) << ED_CONTROL_FA_SHIFT | @@ -2606,7 +2606,7 @@ static int lpc17_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, uint16_t len; int ret; - DEBUGASSERT(priv != NULL && ed != NULL && req!= NULL); + DEBUGASSERT(priv != NULL && ed != NULL && req != NULL); uvdbg("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n", req->type, req->req, req->value[1], req->value[0], @@ -2617,7 +2617,7 @@ static int lpc17_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, lpc17_takesem(&priv->exclsem); len = lpc17_getle16(req->len); - ret = lpc17_ctrltd(priv, ed, GTD_STATUS_DP_SETUP, (uint8_t*)req, USB_SIZEOF_CTRLREQ); + ret = lpc17_ctrltd(priv, ed, GTD_STATUS_DP_SETUP, (uint8_t *)req, USB_SIZEOF_CTRLREQ); if (ret == OK) { if (len) @@ -2644,7 +2644,7 @@ static int lpc17_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, uint16_t len; int ret; - DEBUGASSERT(priv != NULL && ed != NULL && req!= NULL); + DEBUGASSERT(priv != NULL && ed != NULL && req != NULL); uvdbg("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n", req->type, req->req, req->value[1], req->value[0], @@ -2655,12 +2655,12 @@ static int lpc17_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, lpc17_takesem(&priv->exclsem); len = lpc17_getle16(req->len); - ret = lpc17_ctrltd(priv, ed, GTD_STATUS_DP_SETUP, (uint8_t*)req, USB_SIZEOF_CTRLREQ); + ret = lpc17_ctrltd(priv, ed, GTD_STATUS_DP_SETUP, (uint8_t *)req, USB_SIZEOF_CTRLREQ); if (ret == OK) { if (len) { - ret = lpc17_ctrltd(priv, ed, GTD_STATUS_DP_OUT, (uint8_t*)buffer, len); + ret = lpc17_ctrltd(priv, ed, GTD_STATUS_DP_OUT, (uint8_t *)buffer, len); } if (ret == OK) @@ -3013,7 +3013,7 @@ static ssize_t lpc17_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep, /* Return the number of bytes successfully transferred */ nbytes = xfrinfo->xfrd; - DEBUGASSERT(nbytes >=0 && nbytes <= buflen); + DEBUGASSERT(nbytes >= 0 && nbytes <= buflen); } else { @@ -3392,7 +3392,7 @@ static int lpc17_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) lpc17_givesem(&ed->wdhsem); xfrinfo->wdhwait = false; - /* And free the transfer structure */ + /* And free the transfer structure */ lpc17_free_xfrinfo(xfrinfo); ed->xfrinfo = NULL; @@ -3408,7 +3408,7 @@ static int lpc17_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) } else { - /* Just free the transfer structure */ + /* Just free the transfer structure */ lpc17_free_xfrinfo(xfrinfo); ed->xfrinfo = NULL; @@ -3712,9 +3712,9 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller) /* Initialize all the TDs, EDs and HCCA to 0 */ - memset((void*)HCCA, 0, sizeof(struct ohci_hcca_s)); - memset((void*)TDTAIL, 0, sizeof(struct ohci_gtd_s)); - memset((void*)EDCTRL, 0, sizeof(struct lpc17_ed_s)); + memset((void *)HCCA, 0, sizeof(struct ohci_hcca_s)); + memset((void *)TDTAIL, 0, sizeof(struct ohci_gtd_s)); + memset((void *)EDCTRL, 0, sizeof(struct lpc17_ed_s)); sem_init(&EDCTRL->wdhsem, 0, 0); /* Initialize user-configurable EDs */ @@ -3819,7 +3819,7 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller) /* Enable OHCI interrupts */ - lpc17_putreg((LPC17_ALL_INTS|OHCI_INT_MIE), LPC17_USBHOST_INTEN); + lpc17_putreg((LPC17_ALL_INTS | OHCI_INT_MIE), LPC17_USBHOST_INTEN); /* Attach USB host controller interrupt handler */ diff --git a/arch/arm/src/lpc17xx/lpc17_userspace.c b/arch/arm/src/lpc17xx/lpc17_userspace.c index 3e8f4e7744b..ed433eab7ed 100644 --- a/arch/arm/src/lpc17xx/lpc17_userspace.c +++ b/arch/arm/src/lpc17xx/lpc17_userspace.c @@ -87,8 +87,8 @@ void lpc17_userspace(void) DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && USERSPACE->us_bssstart <= USERSPACE->us_bssend); - dest = (uint8_t*)USERSPACE->us_bssstart; - end = (uint8_t*)USERSPACE->us_bssend; + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; while (dest != end) { @@ -101,9 +101,9 @@ void lpc17_userspace(void) USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && USERSPACE->us_datastart <= USERSPACE->us_dataend); - src = (uint8_t*)USERSPACE->us_datasource; - dest = (uint8_t*)USERSPACE->us_datastart; - end = (uint8_t*)USERSPACE->us_dataend; + src = (uint8_t *)USERSPACE->us_datasource; + dest = (uint8_t *)USERSPACE->us_datastart; + end = (uint8_t *)USERSPACE->us_dataend; while (dest != end) { diff --git a/arch/arm/src/lpc214x/lpc214x_decodeirq.c b/arch/arm/src/lpc214x/lpc214x_decodeirq.c index b5cd57f2af5..08da50a32c6 100644 --- a/arch/arm/src/lpc214x/lpc214x_decodeirq.c +++ b/arch/arm/src/lpc214x/lpc214x_decodeirq.c @@ -150,7 +150,7 @@ static void lpc214x_decodeirq(uint32_t *regs) * current_regs is also used to manage interrupt level context switches. */ - savestate = (uint32_t*)current_regs; + savestate = (uint32_t *)current_regs; current_regs = regs; /* Deliver the IRQ */ diff --git a/arch/arm/src/lpc214x/lpc214x_serial.c b/arch/arm/src/lpc214x/lpc214x_serial.c index a911a2c1a30..4da47327573 100644 --- a/arch/arm/src/lpc214x/lpc214x_serial.c +++ b/arch/arm/src/lpc214x/lpc214x_serial.c @@ -296,19 +296,19 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable) static int up_setup(struct uart_dev_s *dev) { #ifndef CONFIG_SUPPRESS_UART_CONFIG - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint16_t baud; uint8_t lcr; /* Clear fifos */ up_serialout(priv, LPC214X_UART_FCR_OFFSET, - (LPC214X_FCR_RX_FIFO_RESET|LPC214X_FCR_TX_FIFO_RESET)); + (LPC214X_FCR_RX_FIFO_RESET | LPC214X_FCR_TX_FIFO_RESET)); /* Set trigger */ up_serialout(priv, LPC214X_UART_FCR_OFFSET, - (LPC214X_FCR_FIFO_ENABLE|LPC214X_FCR_FIFO_TRIG14)); + (LPC214X_FCR_FIFO_ENABLE | LPC214X_FCR_FIFO_TRIG14)); /* Set up the IER */ @@ -359,8 +359,8 @@ static int up_setup(struct uart_dev_s *dev) /* Configure the FIFOs */ up_serialout(priv, LPC214X_UART_FCR_OFFSET, - (LPC214X_FCR_FIFO_TRIG8|LPC214X_FCR_TX_FIFO_RESET|\ - LPC214X_FCR_RX_FIFO_RESET|LPC214X_FCR_FIFO_ENABLE)); + (LPC214X_FCR_FIFO_TRIG8 | LPC214X_FCR_TX_FIFO_RESET | + LPC214X_FCR_RX_FIFO_RESET | LPC214X_FCR_FIFO_ENABLE)); /* The NuttX serial driver waits for the first THRE interrupt before * sending serial data... However, it appears that the lpc214x hardware @@ -385,7 +385,7 @@ static int up_setup(struct uart_dev_s *dev) static void up_shutdown(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; up_disableuartint(priv, NULL); } @@ -406,7 +406,7 @@ static void up_shutdown(struct uart_dev_s *dev) static int up_attach(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -414,12 +414,13 @@ static int up_attach(struct uart_dev_s *dev) ret = irq_attach(priv->irq, up_interrupt); if (ret == OK) { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the UART - */ + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ - up_enable_irq(priv->irq); + up_enable_irq(priv->irq); } + return ret; } @@ -435,7 +436,7 @@ static int up_attach(struct uart_dev_s *dev) static void up_detach(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -472,7 +473,7 @@ static int up_interrupt(int irq, void *context) { PANIC(); } - priv = (struct up_dev_s*)dev->priv; + priv = (struct up_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, * until we have been looping for a long time. @@ -566,7 +567,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; int ret = OK; switch (cmd) @@ -574,7 +575,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct up_dev_s *user = (struct up_dev_s*)arg; + struct up_dev_s *user = (struct up_dev_s *)arg; if (!user) { ret = -EINVAL; @@ -624,7 +625,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) static int up_receive(struct uart_dev_s *dev, uint32_t *status) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint8_t rbr; *status = up_serialin(priv, LPC214X_UART_LSR_OFFSET); @@ -642,7 +643,7 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status) static void up_rxint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; if (enable) { #ifndef CONFIG_SUPPRESS_SERIAL_INTS @@ -666,7 +667,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) static bool up_rxavailable(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & LPC214X_LSR_RDR) != 0); } @@ -680,7 +681,7 @@ static bool up_rxavailable(struct uart_dev_s *dev) static void up_send(struct uart_dev_s *dev, int ch) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; up_serialout(priv, LPC214X_UART_THR_OFFSET, (uint8_t)ch); } @@ -694,7 +695,7 @@ static void up_send(struct uart_dev_s *dev, int ch) static void up_txint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; if (enable) { #ifndef CONFIG_SUPPRESS_SERIAL_INTS @@ -718,7 +719,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) static bool up_txready(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & LPC214X_LSR_THRE) != 0); } @@ -732,7 +733,7 @@ static bool up_txready(struct uart_dev_s *dev) static bool up_txempty(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & LPC214X_LSR_THRE) != 0); } @@ -755,8 +756,8 @@ void up_earlyserialinit(void) /* Enable UART0 and 1 */ uint32_t pinsel = getreg32(LPC214X_PINSEL0); - pinsel &= ~(LPC214X_UART0_PINMASK|LPC214X_UART1_PINMASK); - pinsel |= (LPC214X_UART0_PINSEL|LPC214X_UART1_PINSEL); + pinsel &= ~(LPC214X_UART0_PINMASK | LPC214X_UART1_PINMASK); + pinsel |= (LPC214X_UART0_PINSEL | LPC214X_UART1_PINSEL); putreg32(pinsel, LPC214X_PINSEL0); /* Disable both UARTS */ @@ -796,7 +797,7 @@ void up_serialinit(void) int up_putc(int ch) { - struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv; + struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv; uint8_t ier; up_disableuartint(priv, &ier); diff --git a/arch/arm/src/lpc214x/lpc214x_usbdev.c b/arch/arm/src/lpc214x/lpc214x_usbdev.c index 6320ac9ec14..1ceb9c807e2 100644 --- a/arch/arm/src/lpc214x/lpc214x_usbdev.c +++ b/arch/arm/src/lpc214x/lpc214x_usbdev.c @@ -217,7 +217,7 @@ * assocated DMA buffer. */ -#define USB_UDCA (uint32_t*)LPC214X_USBDEV_RAMBASE) +#define USB_UDCA (uint32_t *)LPC214X_USBDEV_RAMBASE) #define USB_USCASIZE (LPC214X_NPHYSENDPOINTS*sizeof(uint32_t)) /* Each descriptor must be aligned to a 128 address boundary */ @@ -529,7 +529,7 @@ static uint32_t lpc214x_getreg(uint32_t addr) uint32_t val = getreg32(addr); - /* Is this the same value that we read from the same registe last time? Are + /* Is this the same value that we read from the same register last time? Are * we polling the register? If so, suppress some of the output. */ @@ -550,20 +550,20 @@ static uint32_t lpc214x_getreg(uint32_t addr) else { - /* Did we print "..." for the previous value? */ + /* Did we print "..." for the previous value? */ - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ - lldbg("[repeats %d more times]\n", count-3); - } + lldbg("[repeats %d more times]\n", count-3); + } - /* Save the new address, value, and count */ + /* Save the new address, value, and count */ - prevaddr = addr; - preval = val; - count = 1; + prevaddr = addr; + preval = val; + count = 1; } /* Show the register value read */ @@ -610,7 +610,8 @@ static uint32_t lpc214x_usbcmd(uint16_t cmd, uint8_t data) /* Disable interrupt and clear CDFULL and CCEMPTY interrupt status */ flags = irqsave(); - lpc214x_putreg(USBDEV_DEVINT_CDFULL|USBDEV_DEVINT_CCEMTY, LPC214X_USBDEV_DEVINTCLR); + lpc214x_putreg(USBDEV_DEVINT_CDFULL | USBDEV_DEVINT_CCEMTY, + LPC214X_USBDEV_DEVINTCLR); /* Load command + WR in command code register */ @@ -814,7 +815,7 @@ static void lpc214x_epwrite(uint8_t epphy, const uint8_t *data, uint32_t nbytes) { if (aligned) { - value = *(uint32_t*)data; + value = *(uint32_t *)data; } else { @@ -863,11 +864,11 @@ static int lpc214x_epread(uint8_t epphy, uint8_t *data, uint32_t nbytes) if (data) { - if (((uint32_t)data & 3) == 0) + if (((uint32_t)data & 3) == 0) { aligned = 1; } - else + else { aligned = 2; } @@ -895,7 +896,7 @@ static int lpc214x_epread(uint8_t epphy, uint8_t *data, uint32_t nbytes) value = lpc214x_getreg(LPC214X_USBDEV_RXDATA); if (aligned == 1) { - *(uint32_t*)data = value; + *(uint32_t *)data = value; data += 4; } else if (aligned == 2) @@ -1275,7 +1276,7 @@ static void lpc214x_eprealize(struct lpc214x_ep_s *privep, bool prio, uint32_t p /* Clear realize interrupt bit */ - lpc214x_putreg(USBDEV_DEVINT_EPRLZED,LPC214X_USBDEV_DEVINTCLR); + lpc214x_putreg(USBDEV_DEVINT_EPRLZED, LPC214X_USBDEV_DEVINTCLR); } /**************************************************************************** @@ -1454,7 +1455,8 @@ static void lpc214x_usbreset(struct lpc214x_usbdev_s *priv) /* Enable Device interrupts */ - lpc214x_putreg(USB_SLOW_INT|USB_DEVSTATUS_INT|USB_FAST_INT|USB_FRAME_INT|USB_ERROR_INT, + lpc214x_putreg(USB_SLOW_INT | USB_DEVSTATUS_INT | USB_FAST_INT | + USB_FRAME_INT | USB_ERROR_INT, LPC214X_USBDEV_DEVINTEN); } @@ -1538,7 +1540,7 @@ static inline void lpc214x_ep0setup(struct lpc214x_usbdev_s *priv) /* Read EP0 data */ - ret = lpc214x_epread(LPC214X_EP0_OUT, (uint8_t*)&ctrl, USB_SIZEOF_CTRLREQ); + ret = lpc214x_epread(LPC214X_EP0_OUT, (uint8_t *)&ctrl, USB_SIZEOF_CTRLREQ); if (ret <= 0) { return; @@ -1596,7 +1598,7 @@ static inline void lpc214x_ep0setup(struct lpc214x_usbdev_s *priv) } else { - if ((lpc214x_usbcmd(CMD_USB_EP_SELECT|privep->epphy, 0) & CMD_USB_EPSELECT_ST) != 0) + if ((lpc214x_usbcmd(CMD_USB_EP_SELECT | privep->epphy, 0) & CMD_USB_EPSELECT_ST) != 0) { response[0] = 1; /* Stalled */ } @@ -2035,7 +2037,7 @@ static int lpc214x_usbinterrupt(int irq, FAR void *context) #ifdef CONFIG_LPC214X_USBDEV_DMA /* Check for low priority and high priority (non-DMA) interrupts */ - if ((lpc214x_getreg(LPC214X_USBDEV_INTST) & (USBDEV_INTST_REQLP|USBDEV_INTST_REQHP)) != 0) + if ((lpc214x_getreg(LPC214X_USBDEV_INTST) & (USBDEV_INTST_REQLP | USBDEV_INTST_REQHP)) != 0) { #endif #ifdef CONFIG_LPC214X_USBDEV_EPFAST_INTERRUPT @@ -2045,10 +2047,10 @@ static int lpc214x_usbinterrupt(int irq, FAR void *context) { /* Clear Fast EP interrupt */ - lpc214x_putreg(USBDEV_DEVINT_EPFAST, LPC214X_USBDEV_DEVINTCLR); - usbtrace(TRACE_INTDECODE(LPC214X_TRACEINTID_EPFAST), 0); + lpc214x_putreg(USBDEV_DEVINT_EPFAST, LPC214X_USBDEV_DEVINTCLR); + usbtrace(TRACE_INTDECODE(LPC214X_TRACEINTID_EPFAST), 0); - /* Do what? */ + /* Do what? */ } #endif @@ -2109,31 +2111,31 @@ static int lpc214x_usbinterrupt(int irq, FAR void *context) (uint16_t)g_usbdev.devstatus); if (DEVSTATUS_CONNECT(g_usbdev.devstatus)) { - /* Host is connected */ + /* Host is connected */ - if (!priv->attached) - { - /* We have a transition from unattached to attached */ + if (!priv->attached) + { + /* We have a transition from unattached to attached */ - usbtrace(TRACE_INTDECODE(LPC214X_TRACEINTID_CONNECTED), - (uint16_t)g_usbdev.devstatus); - priv->usbdev.speed = USB_SPEED_UNKNOWN; - lpc214x_usbcmd(CMD_USB_DEV_CONFIG, 0); - priv->attached = 1; + usbtrace(TRACE_INTDECODE(LPC214X_TRACEINTID_CONNECTED), + (uint16_t)g_usbdev.devstatus); + priv->usbdev.speed = USB_SPEED_UNKNOWN; + lpc214x_usbcmd(CMD_USB_DEV_CONFIG, 0); + priv->attached = 1; } - } + } - /* Otherwise the host is not attached */ + /* Otherwise the host is not attached */ - else if (priv->attached) - { - usbtrace(TRACE_INTDECODE(LPC214X_TRACEINTID_DISCONNECTED), - (uint16_t)g_usbdev.devstatus); - priv->usbdev.speed = USB_SPEED_UNKNOWN; - lpc214x_usbcmd(CMD_USB_DEV_CONFIG, 0); - priv->attached = 0; - priv->paddrset = 0; - } + else if (priv->attached) + { + usbtrace(TRACE_INTDECODE(LPC214X_TRACEINTID_DISCONNECTED), + (uint16_t)g_usbdev.devstatus); + priv->usbdev.speed = USB_SPEED_UNKNOWN; + lpc214x_usbcmd(CMD_USB_DEV_CONFIG, 0); + priv->attached = 0; + priv->paddrset = 0; + } } /* Device suspend status */ @@ -2241,7 +2243,7 @@ static int lpc214x_usbinterrupt(int irq, FAR void *context) if ((pending & 1) != 0) { - /* Yes.. clear the endpoint interrupt */ + /* Yes.. clear the endpoint interrupt */ (void)lpc214x_epclrinterrupt(epphy); @@ -2270,7 +2272,7 @@ static int lpc214x_usbinterrupt(int irq, FAR void *context) privep->txbusy = 0; lpc214x_wrrequest(privep); - } + } else { /* OUT: host-to-device */ @@ -2279,8 +2281,8 @@ static int lpc214x_usbinterrupt(int irq, FAR void *context) /* Read host data into the current read request */ - if (!lpc214x_rqempty(privep)) - { + if (!lpc214x_rqempty(privep)) + { lpc214x_rdrequest(privep); } else @@ -2556,7 +2558,8 @@ static int lpc214x_epconfigure(FAR struct usbdev_ep_s *ep, { lpc214x_usbcmd(CMD_USB_DEV_CONFIG, 1); } - return OK; + + return OK; } /**************************************************************************** @@ -3250,8 +3253,8 @@ void up_usbinitialize(void) /* Enable EP0 for OUT (host-to-device) */ - lpc214x_usbcmd(CMD_USB_DEV_SETADDRESS, CMD_USB_SETADDRESS_DEVEN|0); - lpc214x_usbcmd(CMD_USB_DEV_SETADDRESS, CMD_USB_SETADDRESS_DEVEN|0); + lpc214x_usbcmd(CMD_USB_DEV_SETADDRESS, CMD_USB_SETADDRESS_DEVEN | 0); + lpc214x_usbcmd(CMD_USB_DEV_SETADDRESS, CMD_USB_SETADDRESS_DEVEN | 0); /* Reset/Re-initialize the USB hardware */ diff --git a/arch/arm/src/lpc2378/lpc23xx_decodeirq.c b/arch/arm/src/lpc2378/lpc23xx_decodeirq.c index 57334f7b99a..0a311b55268 100644 --- a/arch/arm/src/lpc2378/lpc23xx_decodeirq.c +++ b/arch/arm/src/lpc2378/lpc23xx_decodeirq.c @@ -136,7 +136,7 @@ static void lpc23xx_decodeirq(uint32_t *regs) * current_regs is also used to manage interrupt level context switches. */ - savestate = (uint32_t*)current_regs; + savestate = (uint32_t *)current_regs; current_regs = regs; /* Acknowledge the interrupt */ diff --git a/arch/arm/src/lpc2378/lpc23xx_i2c.c b/arch/arm/src/lpc2378/lpc23xx_i2c.c index 35567fdd522..565a0cc5ca9 100644 --- a/arch/arm/src/lpc2378/lpc23xx_i2c.c +++ b/arch/arm/src/lpc2378/lpc23xx_i2c.c @@ -229,12 +229,12 @@ static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int bufle priv->wrcnt = 0; priv->rdcnt = 0; priv->msg.addr &= ~0x01; - priv->msg.buffer = (uint8_t*)buffer; + priv->msg.buffer = (uint8_t *)buffer; priv->msg.length = buflen; ret = i2c_start (priv); - return ret >0 ? OK : -ETIMEDOUT; + return ret > 0 ? OK : -ETIMEDOUT; } /**************************************************************************** @@ -290,11 +290,11 @@ static int i2c_start (struct lpc23xx_i2cdev_s *priv) if (priv-> state == 0x18 || priv->state == 0x28) { - ret=priv->wrcnt; + ret = priv->wrcnt; } else if (priv-> state == 0x50 || priv->state == 0x58) { - ret=priv->rdcnt; + ret = priv->rdcnt; } return ret; @@ -397,15 +397,15 @@ static int i2c_interrupt (int irq, FAR void *context) break; case 0x18: - priv->wrcnt=0; + priv->wrcnt = 0; putreg32(priv->msg.buffer[0], priv->base + I2C_DAT_OFFSET); break; case 0x28: priv->wrcnt++; - if (priv->wrcntmsg.length) + if (priv->wrcnt < priv->msg.length) { - putreg32(priv->msg.buffer[priv->wrcnt],priv->base+I2C_DAT_OFFSET); + putreg32(priv->msg.buffer[priv->wrcnt], priv->base + I2C_DAT_OFFSET); } else { @@ -421,12 +421,12 @@ static int i2c_interrupt (int irq, FAR void *context) case 0x50: priv->rdcnt++; - if (priv->rdcntmsg.length) + if (priv->rdcnt < priv->msg.length) { priv->msg.buffer[priv->rdcnt] = getreg32(priv->base + I2C_DAT_OFFSET); } - if (priv->rdcnt>=priv->msg.length-1) + if (priv->rdcnt >= priv->msg.length-1) { putreg32(I2C_CONCLR_AAC | I2C_CONCLR_SIC, priv->base + I2C_CONCLR_OFFSET); } @@ -501,7 +501,7 @@ struct i2c_dev_s *up_i2cinitialize(int port) #ifdef CONFIG_LPC2378_I2C1 if (port == 1) { - priv= (FAR struct lpc23xx_i2cdev_s *)&i2cdevices[1]; + priv = (FAR struct lpc23xx_i2cdev_s *)&i2cdevices[1]; priv->base = I2C1_BASE_ADDR; priv->irqid = I2C1_IRQ; @@ -529,7 +529,7 @@ struct i2c_dev_s *up_i2cinitialize(int port) #ifdef CONFIG_LPC2378_I2C2 if (port == 2) { - priv= (FAR struct lpc23xx_i2cdev_s *)&i2cdevices[2]; + priv = (FAR struct lpc23xx_i2cdev_s *)&i2cdevices[2]; priv->base = I2C2_BASE_ADDR; priv->irqid = I2C2_IRQ; @@ -559,7 +559,7 @@ struct i2c_dev_s *up_i2cinitialize(int port) return NULL; } - putreg32(I2C_CONSET_I2EN,priv->base+I2C_CONSET_OFFSET); + putreg32(I2C_CONSET_I2EN, priv->base + I2C_CONSET_OFFSET); sem_init (&priv->mutex, 0, 1); sem_init (&priv->wait, 0, 0); @@ -598,7 +598,7 @@ int up_i2cuninitialize(FAR struct i2c_dev_s * dev) { struct lpc23xx_i2cdev_s *priv = (struct lpc23xx_i2cdev_s *)dev; - putreg32(I2C_CONCLRT_I2ENC,priv->base+I2C_CONCLR_OFFSET); + putreg32(I2C_CONCLRT_I2ENC, priv->base + I2C_CONCLR_OFFSET); up_disable_irq(priv->irqid); irq_detach(priv->irqid); return OK; diff --git a/arch/arm/src/lpc2378/lpc23xx_spi.c b/arch/arm/src/lpc2378/lpc23xx_spi.c index 0ce06502bbf..afc6f5860d0 100644 --- a/arch/arm/src/lpc2378/lpc23xx_spi.c +++ b/arch/arm/src/lpc2378/lpc23xx_spi.c @@ -335,7 +335,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) /* Yes... Set CR appropriately */ regval = getreg32(SPI_CR); - regval &= ~(SPI_CR_CPOL|SPI_CR_CPHA); + regval &= ~(SPI_CR_CPOL | SPI_CR_CPHA); switch (mode) { @@ -351,7 +351,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) break; case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ - regval |= (SPI_CR_CPOL|SPI_CR_CPHA); + regval |= (SPI_CR_CPOL | SPI_CR_CPHA); break; default: @@ -472,7 +472,7 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords) { - FAR uint8_t *ptr = (FAR uint8_t*)buffer; + FAR uint8_t *ptr = (FAR uint8_t *)buffer; uint8_t data; spidbg("nwords: %d\n", nwords); @@ -518,7 +518,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords) { - FAR uint8_t *ptr = (FAR uint8_t*)buffer; + FAR uint8_t *ptr = (FAR uint8_t *)buffer; spidbg("nwords: %d\n", nwords); while (nwords) @@ -605,7 +605,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port) /* Configure 8-bit SPI mode and master mode */ - putreg32(SPI_CR_BITS_8BITS|SPI_CR_BITENABLE|SPI_CR_MSTR, SPI_CR); + putreg32(SPI_CR_BITS_8BITS | SPI_CR_BITENABLE | SPI_CR_MSTR, SPI_CR); /* Set the initial SPI configuration */ diff --git a/arch/arm/src/lpc31xx/lpc31_allocateheap.c b/arch/arm/src/lpc31xx/lpc31_allocateheap.c index f46f3466d69..b6d77b190a1 100644 --- a/arch/arm/src/lpc31xx/lpc31_allocateheap.c +++ b/arch/arm/src/lpc31xx/lpc31_allocateheap.c @@ -181,7 +181,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { board_led_on(LED_HEAPALLOCATE); - *heap_start = (FAR void*)g_idle_topstack; + *heap_start = (FAR void *)g_idle_topstack; *heap_size = LPC31_HEAP_VEND - g_idle_topstack; } @@ -198,15 +198,15 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) void up_addregion(void) { #if defined(CONFIG_LPC31_EXTSRAM0) && defined(CONFIG_LPC31_EXTSRAM0HEAP) - kmm_addregion((FAR void*)LPC31_EXTSRAM0_VSECTION, CONFIG_LPC31_EXTSRAM0SIZE); + kmm_addregion((FAR void *)LPC31_EXTSRAM0_VSECTION, CONFIG_LPC31_EXTSRAM0SIZE); #endif #if defined(CONFIG_LPC31_EXTSRAM1) && defined(CONFIG_LPC31_EXTSRAM1HEAP) - kmm_addregion((FAR void*)LPC31_EXTSRAM1_VSECTION, CONFIG_LPC31_EXTSRAM1SIZE); + kmm_addregion((FAR void *)LPC31_EXTSRAM1_VSECTION, CONFIG_LPC31_EXTSRAM1SIZE); #endif #if defined(CONFIG_LPC31_EXTDRAM) && defined(CONFIG_LPC31_EXTDRAMHEAP) - kmm_addregion((FAR void*)LPC31_EXTSDRAM_VSECTION, CONFIG_LPC31_EXTDRAMSIZE); + kmm_addregion((FAR void *)LPC31_EXTSDRAM_VSECTION, CONFIG_LPC31_EXTDRAMSIZE); #endif } #endif diff --git a/arch/arm/src/lpc31xx/lpc31_boot.c b/arch/arm/src/lpc31xx/lpc31_boot.c index cbf7a1e5714..643c4131fd9 100644 --- a/arch/arm/src/lpc31xx/lpc31_boot.c +++ b/arch/arm/src/lpc31xx/lpc31_boot.c @@ -141,7 +141,7 @@ static const struct section_mapping_s section_mapping[] = #ifndef CONFIG_ARCH_ROMPGTABLE static inline void up_setlevel1entry(uint32_t paddr, uint32_t vaddr, uint32_t mmuflags) { - uint32_t *pgtable = (uint32_t*)PGTABLE_BASE_VADDR; + uint32_t *pgtable = (uint32_t *)PGTABLE_BASE_VADDR; uint32_t index = vaddr >> 20; /* Save the page table entry */ @@ -157,7 +157,7 @@ static inline void up_setlevel1entry(uint32_t paddr, uint32_t vaddr, uint32_t mm static inline void up_setlevel2coarseentry(uint32_t ctabvaddr, uint32_t paddr, uint32_t vaddr, uint32_t mmuflags) { - uint32_t *ctable = (uint32_t*)ctabvaddr; + uint32_t *ctable = (uint32_t *)ctabvaddr; uint32_t index; /* The coarse table divides a 1Mb address space up into 256 entries, each @@ -210,7 +210,7 @@ static void up_vectorpermissions(uint32_t mmuflags) { /* The PTE for the beginning of ISRAM is at the base of the L2 page table */ - uint32_t *ptr = (uint32_t*)PG_L2_VECT_VADDR; + uint32_t *ptr = (uint32_t *)PG_L2_VECT_VADDR; uint32_t pte; /* The pte might be zero the first time this function is called. */ @@ -305,9 +305,9 @@ static void up_copyvectorblock(void) * LPC31_VECTOR_VADDR - Virtual address of vector table (0x00000000 or 0xffff0000) */ - src = (uint32_t*)&_vector_start; - end = (uint32_t*)&_vector_end; - dest = (uint32_t*)LPC31_VECTOR_VSRAM; + src = (uint32_t *)&_vector_start; + end = (uint32_t *)&_vector_end; + dest = (uint32_t *)LPC31_VECTOR_VSRAM; while (src < end) { diff --git a/arch/arm/src/lpc31xx/lpc31_clkfreq.c b/arch/arm/src/lpc31xx/lpc31_clkfreq.c index 1151f42df5d..0273bca72be 100644 --- a/arch/arm/src/lpc31xx/lpc31_clkfreq.c +++ b/arch/arm/src/lpc31xx/lpc31_clkfreq.c @@ -167,7 +167,7 @@ uint32_t lpc31_clkfreq(enum lpc31_clockid_e clkid, return 0; } - /* Finally, calculate the frequency based on m and n values */ + /* Finally, calculate the frequency based on m and n values */ freq = (freq * n) / m ; } diff --git a/arch/arm/src/lpc31xx/lpc31_clkinit.c b/arch/arm/src/lpc31xx/lpc31_clkinit.c index f0cdd44103f..39bab98db31 100644 --- a/arch/arm/src/lpc31xx/lpc31_clkinit.c +++ b/arch/arm/src/lpc31xx/lpc31_clkinit.c @@ -64,7 +64,7 @@ struct lpc31_domainconfig_s uint32_t nclks; /* Number of clocks in the domain */ uint32_t fdiv1; /* First frequency divider in the domain */ uint32_t nfdiv; /* Number of frequency dividers in the domain */ - const struct lpc31_subdomainconfig_s* sub; /* Sub=domain array */ + const struct lpc31_subdomainconfig_s *sub; /* Sub=domain array */ }; /************************************************************************************ @@ -87,7 +87,7 @@ struct lpc31_domainconfig_s * ************************************************************************************/ -static void lpc31_domaininit(struct lpc31_domainconfig_s* dmn) +static void lpc31_domaininit(struct lpc31_domainconfig_s *dmn) { const struct lpc31_subdomainconfig_s * sub = dmn->sub; uint32_t fdivcfg; @@ -158,7 +158,7 @@ static void lpc31_domaininit(struct lpc31_domainconfig_s* dmn) putreg32(CGU_BCR_FDRUN, regaddr); } - /* Select input base clock for domain */ + /* Select input base clock for domain */ lpc31_selectfreqin(dmn->dmnid, dmn->finsel); } @@ -175,7 +175,7 @@ static void lpc31_domaininit(struct lpc31_domainconfig_s* dmn) * ************************************************************************************/ -void lpc31_clkinit(const struct lpc31_clkinit_s* cfg) +void lpc31_clkinit(const struct lpc31_clkinit_s *cfg) { struct lpc31_domainconfig_s domain; diff --git a/arch/arm/src/lpc31xx/lpc31_decodeirq.c b/arch/arm/src/lpc31xx/lpc31_decodeirq.c index 8401fc75ace..a2794b575d4 100644 --- a/arch/arm/src/lpc31xx/lpc31_decodeirq.c +++ b/arch/arm/src/lpc31xx/lpc31_decodeirq.c @@ -131,7 +131,7 @@ void up_decodeirq(uint32_t *regs) #ifdef CONFIG_ARCH_FPU /* Restore floating point registers */ - up_restorefpu((uint32_t*)current_regs); + up_restorefpu((uint32_t *)current_regs); #endif #ifdef CONFIG_ARCH_ADDRENV diff --git a/arch/arm/src/lpc31xx/lpc31_ehci.c b/arch/arm/src/lpc31xx/lpc31_ehci.c index 3daa79210cf..0f4bbed663d 100644 --- a/arch/arm/src/lpc31xx/lpc31_ehci.c +++ b/arch/arm/src/lpc31xx/lpc31_ehci.c @@ -3451,7 +3451,7 @@ static int lpc31_wait(FAR struct usbhost_connection_s *conn, */ flags = irqsave(); - for (;;) + for (; ; ) { /* Check for a change in the connection state on any root hub port */ diff --git a/arch/arm/src/lpc31xx/lpc31_i2c.c b/arch/arm/src/lpc31xx/lpc31_i2c.c index bb70f7b6aaa..1f966c5008e 100644 --- a/arch/arm/src/lpc31xx/lpc31_i2c.c +++ b/arch/arm/src/lpc31xx/lpc31_i2c.c @@ -290,7 +290,7 @@ static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int bufle DEBUGASSERT(dev != NULL); priv->msg.flags &= ~I2C_M_READ; - priv->msg.buffer = (uint8_t*)buffer; + priv->msg.buffer = (uint8_t *)buffer; priv->msg.length = buflen; ret = i2c_transfer(dev, &priv->msg, 1); diff --git a/arch/arm/src/lpc31xx/lpc31_irq.c b/arch/arm/src/lpc31xx/lpc31_irq.c index 05108d78bb2..f0ad81bc4fb 100644 --- a/arch/arm/src/lpc31xx/lpc31_irq.c +++ b/arch/arm/src/lpc31xx/lpc31_irq.c @@ -111,8 +111,9 @@ void up_irqinitialize(void) */ uint32_t address = LPC31_INTC_REQUEST(irq+1); - putreg32(INTC_REQUEST_WEACTLOW|INTC_REQUEST_WEENABLE|INTC_REQUEST_TARGET_IRQ| - INTC_REQUEST_PRIOLEVEL(1)|INTC_REQUEST_WEPRIO, address); + putreg32(INTC_REQUEST_WEACTLOW | INTC_REQUEST_WEENABLE | + INTC_REQUEST_TARGET_IRQ | INTC_REQUEST_PRIOLEVEL(1) | + INTC_REQUEST_WEPRIO, address); } @@ -170,7 +171,7 @@ void up_enable_irq(int irq) * preserved because WE_TARGET is zero. */ - putreg32(INTC_REQUEST_ENABLE|INTC_REQUEST_WEENABLE, address); + putreg32(INTC_REQUEST_ENABLE | INTC_REQUEST_WEENABLE, address); } /**************************************************************************** @@ -194,8 +195,8 @@ void up_ack_irq(int irq) * will be preserved because WE_TARGET is zero. */ - putreg32(INTC_REQUEST_CLRSWINT|INTC_REQUEST_ENABLE|INTC_REQUEST_WEENABLE, - address); + putreg32(INTC_REQUEST_CLRSWINT | INTC_REQUEST_ENABLE | + INTC_REQUEST_WEENABLE, address); } /**************************************************************************** diff --git a/arch/arm/src/lpc31xx/lpc31_lowputc.c b/arch/arm/src/lpc31xx/lpc31_lowputc.c index d5a33c307e6..6ab86a5b8bd 100644 --- a/arch/arm/src/lpc31xx/lpc31_lowputc.c +++ b/arch/arm/src/lpc31xx/lpc31_lowputc.c @@ -67,9 +67,9 @@ # ifdef CONFIG_UART_SERIAL_CONSOLE # define HAVE_CONSOLE 1 - /* Is initialization performed by up_earlyserialinit()? Or is UART - * initialization suppressed? - */ +/* Is initialization performed by up_earlyserialinit()? Or is UART + * initialization suppressed? + */ # if defined(USE_EARLYSERIALINIT) || defined(CONFIG_SUPPRESS_UART_CONFIG) # undef NEED_LOWSETUP @@ -187,7 +187,7 @@ static inline void up_configbaud(void) /* Calculate the divisor with these fractional divider settings */ uint32_t tmp = (tmulval * qtrclk) / ((tmulval + tdivaddval)); - tdiv = (tmp + (CONFIG_UART_BAUD>>1)) / CONFIG_UART_BAUD; + tdiv = (tmp + (CONFIG_UART_BAUD >> 1)) / CONFIG_UART_BAUD; /* Check if this candidate divisor is within a valid range */ @@ -221,45 +221,45 @@ static inline void up_configbaud(void) } } - /* Set the Divisor Latch Access Bit (DLAB) to enable DLL/DLM access */ + /* Set the Divisor Latch Access Bit (DLAB) to enable DLL/DLM access */ - regval = getreg32(LPC31_UART_LCR); - regval |= UART_LCR_DLAB; - putreg32(regval, LPC31_UART_LCR); + regval = getreg32(LPC31_UART_LCR); + regval |= UART_LCR_DLAB; + putreg32(regval, LPC31_UART_LCR); - /* Configure the MS and LS DLAB registers */ + /* Configure the MS and LS DLAB registers */ - putreg32(div & UART_DLL_MASK, LPC31_UART_DLL); - putreg32((div >> 8) & UART_DLL_MASK, LPC31_UART_DLM); + putreg32(div & UART_DLL_MASK, LPC31_UART_DLL); + putreg32((div >> 8) & UART_DLL_MASK, LPC31_UART_DLM); - regval &= ~UART_LCR_DLAB; - putreg32(regval, LPC31_UART_LCR); + regval &= ~UART_LCR_DLAB; + putreg32(regval, LPC31_UART_LCR); - /* Configure the Fractional Divider Register (FDR) */ + /* Configure the Fractional Divider Register (FDR) */ - putreg32((mulval << UART_FDR_MULVAL_SHIFT) | - (divaddval << UART_FDR_DIVADDVAL_SHIFT), - LPC31_UART_FDR); + putreg32((mulval << UART_FDR_MULVAL_SHIFT) | + (divaddval << UART_FDR_DIVADDVAL_SHIFT), + LPC31_UART_FDR); #else - /* Set the Divisor Latch Access Bit (DLAB) to enable DLL/DLM access */ + /* Set the Divisor Latch Access Bit (DLAB) to enable DLL/DLM access */ - regval = getreg32(LPC31_UART_LCR); - regval |= UART_LCR_DLAB; - putreg32(regval, LPC31_UART_LCR); + regval = getreg32(LPC31_UART_LCR); + regval |= UART_LCR_DLAB; + putreg32(regval, LPC31_UART_LCR); - /* Configure the MS and LS DLAB registers */ + /* Configure the MS and LS DLAB registers */ - putreg32(CONFIG_LPC31_UART_DIVISOR & UART_DLL_MASK, LPC31_UART_DLL); - putreg32((CONFIG_LPC31_UART_DIVISOR >> 8) & UART_DLL_MASK, LPC31_UART_DLM); + putreg32(CONFIG_LPC31_UART_DIVISOR & UART_DLL_MASK, LPC31_UART_DLL); + putreg32((CONFIG_LPC31_UART_DIVISOR >> 8) & UART_DLL_MASK, LPC31_UART_DLM); - regval &= ~UART_LCR_DLAB; - putreg32(regval, LPC31_UART_LCR); + regval &= ~UART_LCR_DLAB; + putreg32(regval, LPC31_UART_LCR); - /* Configure the Fractional Divider Register (FDR) */ + /* Configure the Fractional Divider Register (FDR) */ - putreg32((CONFIG_LPC31_UART_MULVAL << UART_FDR_MULVAL_SHIFT) | - (CONFIG_LPC31_UART_DIVADDVAL << UART_FDR_DIVADDVAL_SHIFT), - LPC31_UART_FDR); + putreg32((CONFIG_LPC31_UART_MULVAL << UART_FDR_MULVAL_SHIFT) | + (CONFIG_LPC31_UART_DIVADDVAL << UART_FDR_DIVADDVAL_SHIFT), + LPC31_UART_FDR); #endif } #endif @@ -287,11 +287,11 @@ void lpc31_lowsetup(void) /* Clear fifos */ - putreg32((UART_FCR_RXFIFORST|UART_FCR_TXFIFORST), LPC31_UART_FCR); + putreg32((UART_FCR_RXFIFORST | UART_FCR_TXFIFORST), LPC31_UART_FCR); /* Set trigger */ - putreg32((UART_FCR_FIFOENABLE|UART_FCR_RXTRIGLEVEL_16), LPC31_UART_FCR); + putreg32((UART_FCR_FIFOENABLE | UART_FCR_RXTRIGLEVEL_16), LPC31_UART_FCR); /* Set up the LCR */ @@ -314,7 +314,7 @@ void lpc31_lowsetup(void) #if CONFIG_UART_PARITY == 1 regval |= UART_LCR_PAREN; #elif CONFIG_UART_PARITY == 2 - regval |= (UART_LCR_PAREVEN|UART_LCR_PAREN); + regval |= (UART_LCR_PAREVEN | UART_LCR_PAREN); #endif putreg32(regval, LPC31_UART_LCR); @@ -324,8 +324,8 @@ void lpc31_lowsetup(void) /* Configure the FIFOs */ - putreg32((UART_FCR_RXTRIGLEVEL_16|UART_FCR_TXFIFORST| - UART_FCR_RXFIFORST|UART_FCR_FIFOENABLE), + putreg32((UART_FCR_RXTRIGLEVEL_16 | UART_FCR_TXFIFORST | + UART_FCR_RXFIFORST | UART_FCR_FIFOENABLE), LPC31_UART_FCR); /* The NuttX serial driver waits for the first THRE interrupt before diff --git a/arch/arm/src/lpc31xx/lpc31_pllconfig.c b/arch/arm/src/lpc31xx/lpc31_pllconfig.c index a39d21d1381..1ab391a446c 100644 --- a/arch/arm/src/lpc31xx/lpc31_pllconfig.c +++ b/arch/arm/src/lpc31xx/lpc31_pllconfig.c @@ -114,7 +114,7 @@ lpc31_switchdomains(const struct lpc31_pllconfig_s * const cfg) * * Description: * Restore the PLL reference clock to the domains that were temporarily - switched to FFAST by lpc31_switchdomains. + * switched to FFAST by lpc31_switchdomains. * ****************************************************************************/ diff --git a/arch/arm/src/lpc31xx/lpc31_serial.c b/arch/arm/src/lpc31xx/lpc31_serial.c index 21c69bca635..ea046e81fe5 100644 --- a/arch/arm/src/lpc31xx/lpc31_serial.c +++ b/arch/arm/src/lpc31xx/lpc31_serial.c @@ -258,7 +258,7 @@ static inline void up_configbaud(void) /* Calculate the divisor with these fractional divider settings */ uint32_t tmp = (tmulval * qtrclk) / ((tmulval + tdivaddval)); - tdiv = (tmp + (CONFIG_UART_BAUD>>1)) / CONFIG_UART_BAUD; + tdiv = (tmp + (CONFIG_UART_BAUD >> 1)) / CONFIG_UART_BAUD; /* Check if this candidate divisor is within a valid range */ @@ -292,45 +292,45 @@ static inline void up_configbaud(void) } } - /* Set the Divisor Latch Access Bit (DLAB) to enable DLL/DLM access */ + /* Set the Divisor Latch Access Bit (DLAB) to enable DLL/DLM access */ - regval = getreg32(LPC31_UART_LCR); - regval |= UART_LCR_DLAB; - putreg32(regval, LPC31_UART_LCR); + regval = getreg32(LPC31_UART_LCR); + regval |= UART_LCR_DLAB; + putreg32(regval, LPC31_UART_LCR); - /* Configure the MS and LS DLAB registers */ + /* Configure the MS and LS DLAB registers */ - putreg32(div & UART_DLL_MASK, LPC31_UART_DLL); - putreg32((div >> 8) & UART_DLL_MASK, LPC31_UART_DLM); + putreg32(div & UART_DLL_MASK, LPC31_UART_DLL); + putreg32((div >> 8) & UART_DLL_MASK, LPC31_UART_DLM); - regval &= ~UART_LCR_DLAB; - putreg32(regval, LPC31_UART_LCR); + regval &= ~UART_LCR_DLAB; + putreg32(regval, LPC31_UART_LCR); - /* Configure the Fractional Divider Register (FDR) */ + /* Configure the Fractional Divider Register (FDR) */ - putreg32((mulval << UART_FDR_MULVAL_SHIFT) | - (divaddval << UART_FDR_DIVADDVAL_SHIFT), - LPC31_UART_FDR); + putreg32((mulval << UART_FDR_MULVAL_SHIFT) | + (divaddval << UART_FDR_DIVADDVAL_SHIFT), + LPC31_UART_FDR); #else - /* Set the Divisor Latch Access Bit (DLAB) to enable DLL/DLM access */ + /* Set the Divisor Latch Access Bit (DLAB) to enable DLL/DLM access */ - regval = getreg32(LPC31_UART_LCR); - regval |= UART_LCR_DLAB; - putreg32(regval, LPC31_UART_LCR); + regval = getreg32(LPC31_UART_LCR); + regval |= UART_LCR_DLAB; + putreg32(regval, LPC31_UART_LCR); - /* Configure the MS and LS DLAB registers */ + /* Configure the MS and LS DLAB registers */ - putreg32(CONFIG_LPC31_UART_DIVISOR & UART_DLL_MASK, LPC31_UART_DLL); - putreg32((CONFIG_LPC31_UART_DIVISOR >> 8) & UART_DLL_MASK, LPC31_UART_DLM); + putreg32(CONFIG_LPC31_UART_DIVISOR & UART_DLL_MASK, LPC31_UART_DLL); + putreg32((CONFIG_LPC31_UART_DIVISOR >> 8) & UART_DLL_MASK, LPC31_UART_DLM); - regval &= ~UART_LCR_DLAB; - putreg32(regval, LPC31_UART_LCR); + regval &= ~UART_LCR_DLAB; + putreg32(regval, LPC31_UART_LCR); - /* Configure the Fractional Divider Register (FDR) */ + /* Configure the Fractional Divider Register (FDR) */ - putreg32((CONFIG_LPC31_UART_MULVAL << UART_FDR_MULVAL_SHIFT) | - (CONFIG_LPC31_UART_DIVADDVAL << UART_FDR_DIVADDVAL_SHIFT), - LPC31_UART_FDR); + putreg32((CONFIG_LPC31_UART_MULVAL << UART_FDR_MULVAL_SHIFT) | + (CONFIG_LPC31_UART_DIVADDVAL << UART_FDR_DIVADDVAL_SHIFT), + LPC31_UART_FDR); #endif } @@ -346,16 +346,16 @@ static inline void up_configbaud(void) static int up_setup(struct uart_dev_s *dev) { #ifndef CONFIG_SUPPRESS_UART_CONFIG - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint32_t regval; /* Clear fifos */ - putreg32((UART_FCR_RXFIFORST|UART_FCR_TXFIFORST), LPC31_UART_FCR); + putreg32((UART_FCR_RXFIFORST | UART_FCR_TXFIFORST), LPC31_UART_FCR); /* Set trigger */ - putreg32((UART_FCR_FIFOENABLE|UART_FCR_RXTRIGLEVEL_16), LPC31_UART_FCR); + putreg32((UART_FCR_FIFOENABLE | UART_FCR_RXTRIGLEVEL_16), LPC31_UART_FCR); /* Set up the IER */ @@ -382,7 +382,7 @@ static int up_setup(struct uart_dev_s *dev) #if CONFIG_UART_PARITY == 1 regval |= UART_LCR_PAREN; #elif CONFIG_UART_PARITY == 2 - regval |= (UART_LCR_PAREVEN|UART_LCR_PAREN); + regval |= (UART_LCR_PAREVEN | UART_LCR_PAREN); #endif putreg32(regval, LPC31_UART_LCR); @@ -392,8 +392,8 @@ static int up_setup(struct uart_dev_s *dev) /* Configure the FIFOs */ - putreg32((UART_FCR_RXTRIGLEVEL_16|UART_FCR_TXFIFORST| - UART_FCR_RXFIFORST|UART_FCR_FIFOENABLE), + putreg32((UART_FCR_RXTRIGLEVEL_16 | UART_FCR_TXFIFORST | + UART_FCR_RXFIFORST | UART_FCR_FIFOENABLE), LPC31_UART_FCR); /* The NuttX serial driver waits for the first THRE interrupt before @@ -418,7 +418,7 @@ static int up_setup(struct uart_dev_s *dev) static void up_shutdown(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; up_disableuartint(priv, NULL); } @@ -447,11 +447,11 @@ static int up_attach(struct uart_dev_s *dev) ret = irq_attach(LPC31_IRQ_UART, up_interrupt); if (ret == OK) { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the UART - */ + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ - up_enable_irq(LPC31_IRQ_UART); + up_enable_irq(LPC31_IRQ_UART); } return ret; } @@ -589,7 +589,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct up_dev_s *user = (struct up_dev_s*)arg; + struct up_dev_s *user = (struct up_dev_s *)arg; if (!user) { ret = -EINVAL; @@ -657,7 +657,7 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status) static void up_rxint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; if (enable) { #ifndef CONFIG_SUPPRESS_SERIAL_INTS @@ -707,7 +707,7 @@ static void up_send(struct uart_dev_s *dev, int ch) static void up_txint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; if (enable) { #ifndef CONFIG_SUPPRESS_SERIAL_INTS diff --git a/arch/arm/src/lpc31xx/lpc31_setfreqin.c b/arch/arm/src/lpc31xx/lpc31_setfreqin.c index bbac382409a..e70e08acc6d 100644 --- a/arch/arm/src/lpc31xx/lpc31_setfreqin.c +++ b/arch/arm/src/lpc31xx/lpc31_setfreqin.c @@ -88,7 +88,7 @@ void lpc31_selectfreqin(enum lpc31_domainid_e dmnid, uint32_t finsel) * for this domain. */ - scrbits = getreg32(scraddr) & ~(CGU_SCR_ENF1|CGU_SCR_ENF2); + scrbits = getreg32(scraddr) & ~(CGU_SCR_ENF1 | CGU_SCR_ENF2); /* If FS1 is currently enabled set the reference clock to FS2 and enable FS2 */ diff --git a/arch/arm/src/lpc31xx/lpc31_softreset.c b/arch/arm/src/lpc31xx/lpc31_softreset.c index 386cb3710de..b3d32e548b4 100644 --- a/arch/arm/src/lpc31xx/lpc31_softreset.c +++ b/arch/arm/src/lpc31xx/lpc31_softreset.c @@ -82,7 +82,7 @@ void lpc31_softreset(enum lpc31_resetid_e resetid) /* Delay a bit */ - for (i = 0;i < 1000; i++); + for (i = 0; i < 1000; i++); /* Then set the soft reset bit */ diff --git a/arch/arm/src/lpc31xx/lpc31_spi.c b/arch/arm/src/lpc31xx/lpc31_spi.c index cf282088f71..6b64863d052 100644 --- a/arch/arm/src/lpc31xx/lpc31_spi.c +++ b/arch/arm/src/lpc31xx/lpc31_spi.c @@ -616,7 +616,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) { case SPIDEV_MODE0: /* SPO=0; SPH=0 */ setbits = 0; - clrbits = SPI_SLV_2_SPO|SPI_SLV_2_SPH; + clrbits = SPI_SLV_2_SPO | SPI_SLV_2_SPH; break; case SPIDEV_MODE1: /* SPO=0; SPH=1 */ @@ -630,7 +630,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) break; case SPIDEV_MODE3: /* SPO=1; SPH=1 */ - setbits = SPI_SLV_2_SPO|SPI_SLV_2_SPH; + setbits = SPI_SLV_2_SPO | SPI_SLV_2_SPH; clrbits = 0; break; @@ -754,8 +754,8 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, { /* 16-bit mode */ - const uint16_t *src = (const uint16_t*)txbuffer;; - uint16_t *dest = (uint16_t*)rxbuffer; + const uint16_t *src = (const uint16_t *)txbuffer; + uint16_t *dest = (uint16_t *)rxbuffer; uint16_t word; while (nwords > 0) @@ -794,8 +794,8 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, { /* 8-bit mode */ - const uint8_t *src = (const uint8_t*)txbuffer;; - uint8_t *dest = (uint8_t*)rxbuffer; + const uint8_t *src = (const uint8_t *)txbuffer; + uint8_t *dest = (uint8_t *)rxbuffer; uint8_t word; while (nwords > 0) diff --git a/arch/arm/src/lpc31xx/lpc31_timerisr.c b/arch/arm/src/lpc31xx/lpc31_timerisr.c index a6ec4186051..1b7c489667b 100644 --- a/arch/arm/src/lpc31xx/lpc31_timerisr.c +++ b/arch/arm/src/lpc31xx/lpc31_timerisr.c @@ -133,7 +133,7 @@ void up_timer_initialize(void) freq >>= 4; } - load =((freq * (uint64_t)10000) / 1000000); + load = ((freq * (uint64_t)10000) / 1000000); putreg32((uint32_t)load, LPC31_TIMER0_LOAD); /* Set periodic mode */ diff --git a/arch/arm/src/lpc31xx/lpc31_usbdev.c b/arch/arm/src/lpc31xx/lpc31_usbdev.c index 6c2c110d01f..bfde5058ab2 100644 --- a/arch/arm/src/lpc31xx/lpc31_usbdev.c +++ b/arch/arm/src/lpc31xx/lpc31_usbdev.c @@ -512,20 +512,20 @@ static uint32_t lpc31_getreg(uint32_t addr) else { - /* Did we print "..." for the previous value? */ + /* Did we print "..." for the previous value? */ - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ - lldbg("[repeats %d more times]\n", count-3); - } + lldbg("[repeats %d more times]\n", count-3); + } - /* Save the new address, value, and count */ + /* Save the new address, value, and count */ - prevaddr = addr; - preval = val; - count = 1; + prevaddr = addr; + preval = val; + count = 1; } /* Show the register value read */ @@ -817,18 +817,24 @@ static int lpc31_progressep(struct lpc31_ep_s *privep) if (privreq->req.len == 0) { - /* If the class driver is responding to a setup packet, then wait for the - * host to illicit thr response */ + /* If the class driver is responding to a setup packet, then wait for the + * host to illicit thr response */ - if (privep->epphy == LPC31_EP0_IN && privep->dev->ep0state == EP0STATE_SETUP_OUT) - lpc31_ep0state (privep->dev, EP0STATE_WAIT_NAK_IN); - else - { - if (LPC31_EPPHYIN(privep->epphy)) - usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_EPINNULLPACKET), 0); - else - usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_EPOUTNULLPACKET), 0); - } + if (privep->epphy == LPC31_EP0_IN && privep->dev->ep0state == EP0STATE_SETUP_OUT) + { + lpc31_ep0state (privep->dev, EP0STATE_WAIT_NAK_IN); + } + else + { + if (LPC31_EPPHYIN(privep->epphy)) + { + usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_EPINNULLPACKET), 0); + } + else + { + usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_EPOUTNULLPACKET), 0); + } + } lpc31_reqcomplete(privep, lpc31_rqdequeue(privep), OK); return OK; @@ -1027,12 +1033,12 @@ static void lpc31_ep0configure(struct lpc31_usbdev_s *priv) DQH_CAPABILITY_IOS | DQH_CAPABILITY_ZLT); - g_qh[LPC31_EP0_IN ].capability = (DQH_CAPABILITY_MAX_PACKET(CONFIG_LPC31_USBDEV_EP0_MAXSIZE) | + g_qh[LPC31_EP0_IN].capability = (DQH_CAPABILITY_MAX_PACKET(CONFIG_LPC31_USBDEV_EP0_MAXSIZE) | DQH_CAPABILITY_IOS | DQH_CAPABILITY_ZLT); g_qh[LPC31_EP0_OUT].currdesc = DTD_NEXTDESC_INVALID; - g_qh[LPC31_EP0_IN ].currdesc = DTD_NEXTDESC_INVALID; + g_qh[LPC31_EP0_IN].currdesc = DTD_NEXTDESC_INVALID; /* Enable EP0 */ lpc31_setbits (USBDEV_ENDPTCTRL0_RXE | USBDEV_ENDPTCTRL0_TXE, LPC31_USBDEV_ENDPTCTRL0); @@ -1185,91 +1191,94 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv) lpc31_dispatchrequest(priv, &ctrl); else { - /* Handle standard request. Pick off the things of interest to the USB - * device controller driver; pass what is left to the class driver */ - switch (ctrl.req) - { - case USB_REQ_GETSTATUS: + /* Handle standard request. Pick off the things of interest to the USB + * device controller driver; pass what is left to the class driver + */ + + switch (ctrl.req) { - /* type: device-to-host; recipient = device, interface, endpoint - * value: 0 - * index: zero interface endpoint - * len: 2; data = status - */ + case USB_REQ_GETSTATUS: + { + /* type: device-to-host; recipient = device, interface, endpoint + * value: 0 + * index: zero interface endpoint + * len: 2; data = status + */ - usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_GETSTATUS), 0); - if (!priv->paddrset || len != 2 || - (ctrl.type & USB_REQ_DIR_IN) == 0 || value != 0) - { - priv->stalled = true; - } - else - { - switch (ctrl.type & USB_REQ_RECIPIENT_MASK) - { - case USB_REQ_RECIPIENT_ENDPOINT: + usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_GETSTATUS), 0); + if (!priv->paddrset || len != 2 || + (ctrl.type & USB_REQ_DIR_IN) == 0 || value != 0) + { + priv->stalled = true; + } + else + { + switch (ctrl.type & USB_REQ_RECIPIENT_MASK) { - usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_EPGETSTATUS), 0); - privep = lpc31_epfindbyaddr(priv, index); - if (!privep) - { - usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_BADEPGETSTATUS), 0); - priv->stalled = true; - } - else - { - if (privep->stalled) - priv->ep0buf[0] = 1; /* Stalled */ - else - priv->ep0buf[0] = 0; /* Not stalled */ - priv->ep0buf[1] = 0; + case USB_REQ_RECIPIENT_ENDPOINT: + { + usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_EPGETSTATUS), 0); + privep = lpc31_epfindbyaddr(priv, index); + if (!privep) + { + usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_BADEPGETSTATUS), 0); + priv->stalled = true; + } + else + { + if (privep->stalled) + priv->ep0buf[0] = 1; /* Stalled */ + else + priv->ep0buf[0] = 0; /* Not stalled */ - lpc31_ep0xfer (LPC31_EP0_IN, priv->ep0buf, 2); - lpc31_ep0state (priv, EP0STATE_SHORTWRITE); - } + priv->ep0buf[1] = 0; + + lpc31_ep0xfer (LPC31_EP0_IN, priv->ep0buf, 2); + lpc31_ep0state (priv, EP0STATE_SHORTWRITE); + } } - break; + break; - case USB_REQ_RECIPIENT_DEVICE: - { - if (index == 0) - { - usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_DEVGETSTATUS), 0); + case USB_REQ_RECIPIENT_DEVICE: + { + if (index == 0) + { + usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_DEVGETSTATUS), 0); - /* Features: Remote Wakeup=YES; selfpowered=? */ + /* Features: Remote Wakeup=YES; selfpowered=? */ - priv->ep0buf[0] = (priv->selfpowered << USB_FEATURE_SELFPOWERED) | - (1 << USB_FEATURE_REMOTEWAKEUP); - priv->ep0buf[1] = 0; + priv->ep0buf[0] = (priv->selfpowered << USB_FEATURE_SELFPOWERED) | + (1 << USB_FEATURE_REMOTEWAKEUP); + priv->ep0buf[1] = 0; - lpc31_ep0xfer(LPC31_EP0_IN, priv->ep0buf, 2); - lpc31_ep0state (priv, EP0STATE_SHORTWRITE); - } - else - { - usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_BADDEVGETSTATUS), 0); - priv->stalled = true; - } - } - break; + lpc31_ep0xfer(LPC31_EP0_IN, priv->ep0buf, 2); + lpc31_ep0state (priv, EP0STATE_SHORTWRITE); + } + else + { + usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_BADDEVGETSTATUS), 0); + priv->stalled = true; + } + } + break; - case USB_REQ_RECIPIENT_INTERFACE: - { - usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_IFGETSTATUS), 0); - priv->ep0buf[0] = 0; - priv->ep0buf[1] = 0; + case USB_REQ_RECIPIENT_INTERFACE: + { + usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_IFGETSTATUS), 0); + priv->ep0buf[0] = 0; + priv->ep0buf[1] = 0; - lpc31_ep0xfer(LPC31_EP0_IN, priv->ep0buf, 2); - lpc31_ep0state (priv, EP0STATE_SHORTWRITE); - } - break; + lpc31_ep0xfer(LPC31_EP0_IN, priv->ep0buf, 2); + lpc31_ep0state (priv, EP0STATE_SHORTWRITE); + } + break; - default: - { - usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_BADGETSTATUS), 0); - priv->stalled = true; - } - break; + default: + { + usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_BADGETSTATUS), 0); + priv->stalled = true; + } + break; } } } @@ -1601,13 +1610,18 @@ bool lpc31_epcomplete(struct lpc31_usbdev_s *priv, uint8_t epphy) struct lpc31_dtd_s *dtd = &g_td[epphy]; if (privreq == NULL) /* This shouldn't really happen */ - { - if (LPC31_EPPHYOUT(privep->epphy)) - usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_EPINQEMPTY), 0); - else - usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_EPOUTQEMPTY), 0); - return true; - } + { + if (LPC31_EPPHYOUT(privep->epphy)) + { + usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_EPINQEMPTY), 0); + } + else + { + usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_EPOUTQEMPTY), 0); + } + + return true; + } int xfrd = dtd->xfer_len - (dtd->config >> 16); @@ -1677,7 +1691,7 @@ static int lpc31_usbinterrupt(int irq, FAR void *context) if (disr & USBDEV_USBSTS_URI) { - usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_DEVRESET),0); + usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_DEVRESET), 0); lpc31_usbreset(priv); @@ -1691,7 +1705,7 @@ static int lpc31_usbinterrupt(int irq, FAR void *context) if (!priv->suspended && (disr & USBDEV_USBSTS_SLI) != 0) { - usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_SUSPENDED),0); + usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_SUSPENDED), 0); /* Inform the Class driver of the suspend event */ @@ -1710,7 +1724,7 @@ static int lpc31_usbinterrupt(int irq, FAR void *context) else if (priv->suspended && (disr & USBDEV_USBSTS_SLI) == 0) { - usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_RESUMED),0); + usbtrace(TRACE_INTDECODE(LPC31_TRACEINTID_RESUMED), 0); /* Inform the Class driver of the resume event */ @@ -1777,10 +1791,15 @@ static int lpc31_usbinterrupt(int irq, FAR void *context) for (n = 1; n < LPC31_NLOGENDPOINTS; n++) { - if (mask & LPC31_ENDPTMASK((n<<1))) - lpc31_epcomplete (priv, (n<<1)); - if (mask & LPC31_ENDPTMASK((n<<1)+1)) - lpc31_epcomplete(priv, (n<<1)+1); + if (mask & LPC31_ENDPTMASK((n << 1))) + { + lpc31_epcomplete (priv, (n << 1)); + } + + if (mask & LPC31_ENDPTMASK((n << 1) + 1)) + { + lpc31_epcomplete(priv, (n << 1) + 1); + } } } diff --git a/arch/arm/src/lpc43xx/lpc43_adc.c b/arch/arm/src/lpc43xx/lpc43_adc.c index 71f1181e64e..43f3006c7f4 100644 --- a/arch/arm/src/lpc43xx/lpc43_adc.c +++ b/arch/arm/src/lpc43xx/lpc43_adc.c @@ -113,24 +113,24 @@ static int adc_interrupt(int irq, void *context); static const struct adc_ops_s g_adcops = { - .ao_reset =adc_reset, - .ao_setup = adc_setup, + .ao_reset = adc_reset, + .ao_setup = adc_setup, .ao_shutdown = adc_shutdown, - .ao_rxint = adc_rxint, - .ao_ioctl = adc_ioctl, + .ao_rxint = adc_rxint, + .ao_ioctl = adc_ioctl, }; static struct up_dev_s g_adcpriv = { - .sps = CONFIG_ADC0_SPS, - .mask = CONFIG_ADC0_MASK, - .irq = LPC43_IRQ_ADC, + .sps = CONFIG_ADC0_SPS, + .mask = CONFIG_ADC0_MASK, + .irq = LPC43_IRQ_ADC, }; static struct adc_dev_s g_adcdev = { - .ad_ops = &g_adcops, - .ad_priv= &g_adcpriv, + .ad_ops = &g_adcops, + .ad_priv = &g_adcpriv, }; /**************************************************************************** @@ -153,34 +153,50 @@ static void adc_reset(FAR struct adc_dev_s *dev) regval |= SYSCON_PCONP_PCADC; putreg32(regval, LPC43_SYSCON_PCONP); - putreg32(ADC_CR_PDN,LPC43_ADC_CR); + putreg32(ADC_CR_PDN, LPC43_ADC_CR); regval = getreg32(LPC43_SYSCON_PCLKSEL0); regval &= ~SYSCON_PCLKSEL0_ADC_MASK; regval |= (SYSCON_PCLKSEL_CCLK8 << SYSCON_PCLKSEL0_ADC_SHIFT); putreg32(regval, LPC43_SYSCON_PCLKSEL0); - uint32_t clkdiv=LPC43_CCLK/8/65/priv->sps; - clkdiv<<=8; - clkdiv&=0xff00; - putreg32(ADC_CR_PDN|ADC_CR_BURST|clkdiv|priv->mask,LPC43_ADC_CR); + uint32_t clkdiv = LPC43_CCLK / 8 / 65 / priv->sps; + clkdiv <<= 8; + clkdiv &= 0xff00; + putreg32(ADC_CR_PDN | ADC_CR_BURST | clkdiv | priv->mask, LPC43_ADC_CR); if (priv->mask&0x01) - lpc43_configgpio(GPIO_AD0p0); + { + lpc43_configgpio(GPIO_AD0p0); + } else if (priv->mask&0x02) - lpc43_configgpio(GPIO_AD0p1); + { + lpc43_configgpio(GPIO_AD0p1); + } else if (priv->mask&0x04) - lpc43_configgpio(GPIO_AD0p2); + { + lpc43_configgpio(GPIO_AD0p2); + } else if (priv->mask&0x08) - lpc43_configgpio(GPIO_AD0p3); + { + lpc43_configgpio(GPIO_AD0p3); + } else if (priv->mask&0x10) - lpc43_configgpio(GPIO_AD0p4); + { + lpc43_configgpio(GPIO_AD0p4); + } else if (priv->mask&0x20) - lpc43_configgpio(GPIO_AD0p5); + { + lpc43_configgpio(GPIO_AD0p5); + } else if (priv->mask&0x40) - lpc43_configgpio(GPIO_AD0p6); + { + lpc43_configgpio(GPIO_AD0p6); + } else if (priv->mask&0x80) - lpc43_configgpio(GPIO_AD0p7); + { + lpc43_configgpio(GPIO_AD0p7); + } irqrestore(flags); } @@ -196,15 +212,18 @@ static int adc_setup(FAR struct adc_dev_s *dev) int i; FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->ad_priv; int ret = irq_attach(priv->irq, adc_interrupt); + if (ret == OK) { for (i = 0; i < 8; i++) { - priv->buf[i]=0; - priv->count[i]=0; + priv->buf[i] = 0; + priv->count[i] = 0; } + up_enable_irq(priv->irq); } + return ret; } @@ -253,7 +272,7 @@ static int adc_interrupt(int irq, void *context) { value = priv->buf[ch] / priv->count[ch]; value <<= 15; - adc_receive(&g_adcdev,ch,value); + adc_receive(&g_adcdev, ch, value); priv->buf[ch] = 0; priv->count[ch] = 0; } diff --git a/arch/arm/src/lpc43xx/lpc43_allocateheap.c b/arch/arm/src/lpc43xx/lpc43_allocateheap.c index 6201ff659af..b914b4d8bb7 100644 --- a/arch/arm/src/lpc43xx/lpc43_allocateheap.c +++ b/arch/arm/src/lpc43xx/lpc43_allocateheap.c @@ -249,7 +249,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Start with the first SRAM region */ board_led_on(LED_HEAPALLOCATE); - *heap_start = (FAR void*)g_idle_topstack; + *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; } @@ -268,7 +268,7 @@ void up_addregion(void) #if CONFIG_MM_REGIONS > 1 /* Add the next SRAM region (which should exist) */ - kmm_addregion((FAR void*)MM_REGION2_BASE, MM_REGION2_SIZE); + kmm_addregion((FAR void *)MM_REGION2_BASE, MM_REGION2_SIZE); #ifdef MM_REGION3_BASE /* Add the third SRAM region (which will not exist in configuration B) */ @@ -276,12 +276,12 @@ void up_addregion(void) #if CONFIG_MM_REGIONS > 2 /* Add the third SRAM region (which may not exist) */ - kmm_addregion((FAR void*)MM_REGION3_BASE, MM_REGION3_SIZE); + kmm_addregion((FAR void *)MM_REGION3_BASE, MM_REGION3_SIZE); #if CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) /* Add the DMA region (which may not be available) */ - kmm_addregion((FAR void*)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE); + kmm_addregion((FAR void *)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE); #endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */ #endif /* CONFIG_MM_REGIONS > 2 */ @@ -290,7 +290,7 @@ void up_addregion(void) #if CONFIG_MM_REGIONS > 2 && defined(MM_DMAHEAP_BASE) /* Add the DMA region (which may not be available) */ - kmm_addregion((FAR void*)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE); + kmm_addregion((FAR void *)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE); #endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */ #endif /* MM_REGION3_BASE */ diff --git a/arch/arm/src/lpc43xx/lpc43_dac.c b/arch/arm/src/lpc43xx/lpc43_dac.c index ba102c185f2..196d4512198 100644 --- a/arch/arm/src/lpc43xx/lpc43_dac.c +++ b/arch/arm/src/lpc43xx/lpc43_dac.c @@ -96,17 +96,17 @@ static int dac_interrupt(int irq, void *context); static const struct dac_ops_s g_dacops = { - .ao_reset =dac_reset, - .ao_setup = dac_setup, + .ao_reset = dac_reset, + .ao_setup = dac_setup, .ao_shutdown = dac_shutdown, - .ao_txint = dac_txint, - .ao_send = dac_send, - .ao_ioctl = dac_ioctl, + .ao_txint = dac_txint, + .ao_send = dac_send, + .ao_ioctl = dac_ioctl, }; static struct dac_dev_s g_dacdev = { - .ad_ops = &g_dacops, + .ad_ops = &g_dacops, }; /**************************************************************************** @@ -129,7 +129,7 @@ static void dac_reset(FAR struct dac_dev_s *dev) regval |= (SYSCON_PCLKSEL_CCLK8 << SYSCON_PCLKSEL0_DAC_SHIFT); putreg32(regval, LPC43_SYSCON_PCLKSEL0); - //putreg32(DAC_CTRL_DBLBUFEN,LPC43_DAC_CTRL); ? + //putreg32(DAC_CTRL_DBLBUFEN, LPC43_DAC_CTRL); ? lpc43_configgpio(GPIO_AOUT); @@ -163,7 +163,7 @@ static void dac_txint(FAR struct dac_dev_s *dev, bool enable) static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg) { - putreg32((msg->am_data>>16)&0xfffff,LPC43_DAC_CR); + putreg32((msg->am_data >> 16) & 0xfffff, LPC43_DAC_CR); dac_txdone(&g_dacdev); return 0; } @@ -201,4 +201,3 @@ FAR struct dac_dev_s *lpc43_dacinitialize(void) } #endif /* CONFIG_LPC43_DAC */ - diff --git a/arch/arm/src/lpc43xx/lpc43_ehci.c b/arch/arm/src/lpc43xx/lpc43_ehci.c index 868a26a4982..f9ef7799dab 100644 --- a/arch/arm/src/lpc43xx/lpc43_ehci.c +++ b/arch/arm/src/lpc43xx/lpc43_ehci.c @@ -3281,7 +3281,7 @@ static int lpc43_wait(FAR struct usbhost_connection_s *conn, */ flags = irqsave(); - for (;;) + for (; ; ) { /* Check for a change in the connection state on any root hub port */ diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c index 18310a27011..aec78c7b5a6 100644 --- a/arch/arm/src/lpc43xx/lpc43_ethernet.c +++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c @@ -475,7 +475,7 @@ */ #define ETH_DMAINT_NORMAL \ - (ETH_DMAINT_TI | ETH_DMAINT_TU |ETH_DMAINT_RI | ETH_DMAINT_ERI) + (ETH_DMAINT_TI | ETH_DMAINT_TU | ETH_DMAINT_RI | ETH_DMAINT_ERI) #define ETH_DMAINT_ABNORMAL \ (ETH_DMAINT_TPS | ETH_DMAINT_TJT | ETH_DMAINT_OVF | ETH_DMAINT_UNF | \ @@ -713,20 +713,20 @@ static uint32_t lpc43_getreg(uint32_t addr) else { - /* Did we print "..." for the previous value? */ + /* Did we print "..." for the previous value? */ - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ - lldbg("[repeats %d more times]\n", count-3); - } + lldbg("[repeats %d more times]\n", count-3); + } - /* Save the new address, value, and count */ + /* Save the new address, value, and count */ - prevaddr = addr; - preval = val; - count = 1; + prevaddr = addr; + preval = val; + count = 1; } /* Show the register value read */ @@ -1467,7 +1467,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv) /* Check if this is an intermediate segment in the frame */ - else if (((rxdesc->rdes0 & ETH_RDES0_LS) == 0)&& + else if (((rxdesc->rdes0 & ETH_RDES0_LS) == 0) && ((rxdesc->rdes0 & ETH_RDES0_FS) == 0)) { priv->segments++; @@ -1519,14 +1519,14 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv) */ DEBUGASSERT(dev->d_buf == NULL); - dev->d_buf = (uint8_t*)rxcurr->rdes2; + dev->d_buf = (uint8_t *)rxcurr->rdes2; rxcurr->rdes2 = (uint32_t)buffer; /* Return success, remembering where we should re-start scanning * and resetting the segment scanning logic */ - priv->rxhead = (struct eth_rxdesc_s*)rxdesc->rdes3; + priv->rxhead = (struct eth_rxdesc_s *)rxdesc->rdes3; lpc43_freesegment(priv, rxcurr, priv->segments); nllvdbg("rxhead: %p d_buf: %p d_len: %d\n", @@ -1547,7 +1547,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv) /* Try the next descriptor */ - rxdesc = (struct eth_rxdesc_s*)rxdesc->rdes3; + rxdesc = (struct eth_rxdesc_s *)rxdesc->rdes3; } /* We get here after all of the descriptors have been scanned or when rxdesc points @@ -1676,7 +1676,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv) */ if (priv->dev.d_len > 0) - { + { /* Update the Ethernet header with the correct MAC address */ #ifdef CONFIG_NET_IPv4 @@ -1788,7 +1788,7 @@ static void lpc43_freeframe(FAR struct lpc43_ethmac_s *priv) { /* Yes.. Free the buffer */ - lpc43_freebuffer(priv, (uint8_t*)txdesc->tdes2); + lpc43_freebuffer(priv, (uint8_t *)txdesc->tdes2); } /* In any event, make sure that TDES2 is nullified. */ @@ -1821,7 +1821,7 @@ static void lpc43_freeframe(FAR struct lpc43_ethmac_s *priv) /* Try the next descriptor in the TX chain */ - txdesc = (struct eth_txdesc_s*)txdesc->tdes3; + txdesc = (struct eth_txdesc_s *)txdesc->tdes3; } /* We get here if (1) there are still frames "in-flight". Remember @@ -3954,7 +3954,7 @@ static inline int lpc43_ethinitialize(void) #ifdef CONFIG_NETDEV_PHY_IOCTL priv->dev.d_ioctl = lpc43_ioctl; /* Support PHY ioctl() calls */ #endif - priv->dev.d_private = (void*)&g_lpc43ethmac; /* Used to recover private state from dev */ + priv->dev.d_private = (void *)&g_lpc43ethmac; /* Used to recover private state from dev */ /* Create a watchdog for timing polling for and timing of transmisstions */ diff --git a/arch/arm/src/lpc43xx/lpc43_i2c.c b/arch/arm/src/lpc43xx/lpc43_i2c.c index 040f1744cbd..8a188df978c 100644 --- a/arch/arm/src/lpc43xx/lpc43_i2c.c +++ b/arch/arm/src/lpc43xx/lpc43_i2c.c @@ -232,7 +232,7 @@ static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, priv->wrcnt = 0; priv->rdcnt = 0; priv->msg.addr &= ~0x01; - priv->msg.buffer = (uint8_t*)buffer; + priv->msg.buffer = (uint8_t *)buffer; priv->msg.length = buflen; priv->nmsg = 1; @@ -293,8 +293,8 @@ static int i2c_start(struct lpc43_i2cdev_s *priv) sem_wait(&priv->mutex); - putreg32(I2C_CONCLR_STAC|I2C_CONCLR_SIC,priv->base+LPC43_I2C_CONCLR_OFFSET); - putreg32(I2C_CONSET_STA,priv->base+LPC43_I2C_CONSET_OFFSET); + putreg32(I2C_CONCLR_STAC | I2C_CONCLR_SIC, priv->base + LPC43_I2C_CONCLR_OFFSET); + putreg32(I2C_CONSET_STA, priv->base + LPC43_I2C_CONSET_OFFSET); wd_start(priv->timeout, I2C_TIMEOUT, i2c_timeout, 1, (uint32_t)priv); sem_wait(&priv->wait); @@ -320,7 +320,7 @@ static void i2c_stop(struct lpc43_i2cdev_s *priv) { if (priv->state != 0x38) { - putreg32(I2C_CONSET_STO|I2C_CONSET_AA,priv->base+LPC43_I2C_CONSET_OFFSET); + putreg32(I2C_CONSET_STO | I2C_CONSET_AA, priv->base + LPC43_I2C_CONSET_OFFSET); } sem_post(&priv->wait); @@ -359,10 +359,10 @@ static int i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, i DEBUGASSERT(dev != NULL); - priv->wrcnt=0; - priv->rdcnt=0; - priv->msgs = msgs; - priv->nmsg = count; + priv->wrcnt = 0; + priv->rdcnt = 0; + priv->msgs = msgs; + priv->nmsg = count; ret = count - i2c_start(priv); @@ -376,7 +376,7 @@ void startStopNextMessage(struct lpc43_i2cdev_s *priv) if (priv->nmsg > 0) { priv->msgs++; - putreg32(I2C_CONSET_STA,priv->base+LPC43_I2C_CONSET_OFFSET); + putreg32(I2C_CONSET_STA, priv->base + LPC43_I2C_CONSET_OFFSET); } else { @@ -418,7 +418,7 @@ static int i2c_interrupt(int irq, FAR void *context) /* Reference UM10360 19.10.5 */ - state = getreg32(priv->base+LPC43_I2C_STAT_OFFSET); + state = getreg32(priv->base + LPC43_I2C_STAT_OFFSET); msg = priv->msgs; priv->state = state; @@ -435,7 +435,7 @@ static int i2c_interrupt(int irq, FAR void *context) /* Write cases */ case 0x18: /* SLA+W has been transmitted; ACK has been received */ - priv->wrcnt=0; + priv->wrcnt = 0; putreg32(msg->buffer[0], priv->base + LPC43_I2C_DAT_OFFSET); /* put first byte */ break; @@ -444,7 +444,7 @@ static int i2c_interrupt(int irq, FAR void *context) if (priv->wrcnt < msg->length) { - putreg32(msg->buffer[priv->wrcnt],priv->base+LPC43_I2C_DAT_OFFSET); /* Put next byte */ + putreg32(msg->buffer[priv->wrcnt], priv->base + LPC43_I2C_DAT_OFFSET); /* Put next byte */ } else { @@ -462,22 +462,22 @@ static int i2c_interrupt(int irq, FAR void *context) } else { - putreg32(I2C_CONCLR_AAC,priv->base + LPC43_I2C_CONCLR_OFFSET); /* Do not ACK because only one byte */ + putreg32(I2C_CONCLR_AAC, priv->base + LPC43_I2C_CONCLR_OFFSET); /* Do not ACK because only one byte */ } break; case 0x50: /* Data byte has been received; ACK has been returned. */ priv->rdcnt++; - msg->buffer[priv->rdcnt-1 ] = getreg32(priv->base+LPC43_I2C_BUFR_OFFSET); + msg->buffer[priv->rdcnt - 1] = getreg32(priv->base + LPC43_I2C_BUFR_OFFSET); - if (priv->rdcnt >= (msg->length - 1)) { - putreg32(I2C_CONCLR_AAC,priv->base+LPC43_I2C_CONCLR_OFFSET); /* Do not ACK any more */ - - } + if (priv->rdcnt >= (msg->length - 1)) + { + putreg32(I2C_CONCLR_AAC, priv->base + LPC43_I2C_CONCLR_OFFSET); /* Do not ACK any more */ + } break; case 0x58: /* Data byte has been received; NACK has been returned. */ - msg->buffer[priv->rdcnt ] = getreg32(priv->base+LPC43_I2C_BUFR_OFFSET); + msg->buffer[priv->rdcnt] = getreg32(priv->base + LPC43_I2C_BUFR_OFFSET); startStopNextMessage(priv); break; @@ -582,7 +582,7 @@ struct i2c_dev_s *up_i2cinitialize(int port) irqrestore(flags); - putreg32(I2C_CONSET_I2EN,priv->base+LPC43_I2C_CONSET_OFFSET); + putreg32(I2C_CONSET_I2EN, priv->base + LPC43_I2C_CONSET_OFFSET); sem_init(&priv->mutex, 0, 1); sem_init(&priv->wait, 0, 0); @@ -618,7 +618,7 @@ int up_i2cuninitialize(FAR struct i2c_dev_s * dev) { struct lpc43_i2cdev_s *priv = (struct lpc43_i2cdev_s *) dev; - putreg32(I2C_CONCLRT_I2ENC,priv->base+LPC43_I2C_CONCLR_OFFSET); + putreg32(I2C_CONCLRT_I2ENC, priv->base + LPC43_I2C_CONCLR_OFFSET); up_disable_irq(priv->irqid); irq_detach(priv->irqid); return OK; diff --git a/arch/arm/src/lpc43xx/lpc43_irq.c b/arch/arm/src/lpc43xx/lpc43_irq.c index a5961a7d56d..bb78263abdf 100644 --- a/arch/arm/src/lpc43xx/lpc43_irq.c +++ b/arch/arm/src/lpc43xx/lpc43_irq.c @@ -61,9 +61,9 @@ /* Get a 32-bit version of the default priority */ #define DEFPRIORITY32 \ - (LPC43M4_SYSH_PRIORITY_DEFAULT << 24 |\ - LPC43M4_SYSH_PRIORITY_DEFAULT << 16 |\ - LPC43M4_SYSH_PRIORITY_DEFAULT << 8 |\ + (LPC43M4_SYSH_PRIORITY_DEFAULT << 24 | \ + LPC43M4_SYSH_PRIORITY_DEFAULT << 16 | \ + LPC43M4_SYSH_PRIORITY_DEFAULT << 8 | \ LPC43M4_SYSH_PRIORITY_DEFAULT) /* Given the address of a NVIC ENABLE register, this is the offset to diff --git a/arch/arm/src/lpc43xx/lpc43_pinconfig.c b/arch/arm/src/lpc43xx/lpc43_pinconfig.c index bde44b3f3c1..0a274dd6a89 100644 --- a/arch/arm/src/lpc43xx/lpc43_pinconfig.c +++ b/arch/arm/src/lpc43xx/lpc43_pinconfig.c @@ -110,16 +110,16 @@ int lpc43_pin_config(uint32_t pinconf) /* Enable/disable glitch filtering */ if (!PINCONF_GLITCH_ENABLE(pinconf)) - { - regval |= SCU_PIN_ZIF; /* Set bit to disable */ - } + { + regval |= SCU_PIN_ZIF; /* Set bit to disable */ + } /* Only normal and high speed pins support the slew rate setting */ if (PINCONF_IS_SLEW_FAST(pinconf)) - { - regval |= SCU_NDPIN_EHS; /* 0=slow; 1=fast */ - } + { + regval |= SCU_NDPIN_EHS; /* 0=slow; 1=fast */ + } /* Only high drive pins suppose drive strength */ diff --git a/arch/arm/src/lpc43xx/lpc43_rit.c b/arch/arm/src/lpc43xx/lpc43_rit.c index 42e76dbd63f..8eec814ac3a 100644 --- a/arch/arm/src/lpc43xx/lpc43_rit.c +++ b/arch/arm/src/lpc43xx/lpc43_rit.c @@ -91,7 +91,7 @@ static int lpc43_RIT_isr(int irq, FAR void *context) flags = irqsave(); - putreg32(RIT_CTRL_INT,LPC43_RIT_CTRL); + putreg32(RIT_CTRL_INT, LPC43_RIT_CTRL); internal_timer += (uint64_t)RIT_TIMER_RESOLUTION; if (alarm > 0 && internal_timer >= alarm) @@ -201,7 +201,7 @@ void up_timer_initialize(void) } lldbg("mask_bits = %d, mask = %X, ticks_per_int = %d\r\n", - mask_bits, (0xFFFFFFFF<<(32 - mask_bits)), ticks_per_int); + mask_bits, (0xffffffff << (32 - mask_bits)), ticks_per_int); /* Set the mask and compare value so we get interrupts every * RIT_TIMER_RESOLUTION cycles. diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c index d4d84a4acd9..0cd0ae9a159 100644 --- a/arch/arm/src/lpc43xx/lpc43_serial.c +++ b/arch/arm/src/lpc43xx/lpc43_serial.c @@ -563,16 +563,16 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable) static int up_setup(struct uart_dev_s *dev) { #ifndef CONFIG_SUPPRESS_UART_CONFIG - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint32_t lcr; /* Clear fifos */ - up_serialout(priv, LPC43_UART_FCR_OFFSET, (UART_FCR_RXRST|UART_FCR_TXRST)); + up_serialout(priv, LPC43_UART_FCR_OFFSET, (UART_FCR_RXRST | UART_FCR_TXRST)); /* Set trigger */ - up_serialout(priv, LPC43_UART_FCR_OFFSET, (UART_FCR_FIFOEN|UART_FCR_RXTRIGGER_8)); + up_serialout(priv, LPC43_UART_FCR_OFFSET, (UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8)); /* Set up the IER */ @@ -598,11 +598,11 @@ static int up_setup(struct uart_dev_s *dev) if (priv->parity == 1) { - lcr |= (UART_LCR_PE|UART_LCR_PS_ODD); + lcr |= (UART_LCR_PE | UART_LCR_PS_ODD); } else if (priv->parity == 2) { - lcr |= (UART_LCR_PE|UART_LCR_PS_EVEN); + lcr |= (UART_LCR_PE | UART_LCR_PS_EVEN); } /* Save the LCR */ @@ -616,14 +616,15 @@ static int up_setup(struct uart_dev_s *dev) /* Configure the FIFOs */ up_serialout(priv, LPC43_UART_FCR_OFFSET, - (UART_FCR_RXTRIGGER_8|UART_FCR_TXRST|UART_FCR_RXRST|UART_FCR_FIFOEN)); + (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST | UART_FCR_RXRST | + UART_FCR_FIFOEN)); /* Enable Auto-RTS and Auto-CS Flow Control in the Modem Control Register */ #ifdef CONFIG_UART1_FLOWCONTROL if (priv->id == 1) { - up_serialout(priv, LPC43_UART_MCR_OFFSET, (UART_MCR_RTSEN|UART_MCR_CTSEN)); + up_serialout(priv, LPC43_UART_MCR_OFFSET, (UART_MCR_RTSEN | UART_MCR_CTSEN)); } #endif @@ -641,7 +642,7 @@ static int up_setup(struct uart_dev_s *dev) static void up_shutdown(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Disable further interrupts from the U[S]ART */ @@ -697,7 +698,7 @@ static void up_shutdown(struct uart_dev_s *dev) static int up_attach(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -705,11 +706,11 @@ static int up_attach(struct uart_dev_s *dev) ret = irq_attach(priv->irq, up_interrupt); if (ret == OK) { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the UART - */ + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ - up_enable_irq(priv->irq); + up_enable_irq(priv->irq); } return ret; } @@ -726,7 +727,7 @@ static int up_attach(struct uart_dev_s *dev) static void up_detach(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -781,7 +782,7 @@ static int up_interrupt(int irq, void *context) { PANIC(); } - priv = (struct up_dev_s*)dev->priv; + priv = (struct up_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, * until we have been looping for a long time. @@ -1077,7 +1078,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; int ret = OK; switch (cmd) @@ -1085,7 +1086,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct up_dev_s *user = (struct up_dev_s*)arg; + struct up_dev_s *user = (struct up_dev_s *)arg; if (!user) { ret = -EINVAL; @@ -1101,7 +1102,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_TERMIOS case TCGETS: { - struct termios *termiosp = (struct termios*)arg; + struct termios *termiosp = (struct termios *)arg; if (!termiosp) { @@ -1120,7 +1121,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) case TCSETS: { - struct termios *termiosp = (struct termios*)arg; + struct termios *termiosp = (struct termios *)arg; if (!termiosp) { @@ -1192,7 +1193,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) static int up_receive(struct uart_dev_s *dev, uint32_t *status) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint32_t rbr; *status = up_serialin(priv, LPC43_UART_LSR_OFFSET); @@ -1210,7 +1211,7 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status) static void up_rxint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; if (enable) { #ifndef CONFIG_SUPPRESS_SERIAL_INTS @@ -1235,7 +1236,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) static bool up_rxavailable(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return ((up_serialin(priv, LPC43_UART_LSR_OFFSET) & UART_LSR_RDR) != 0); } @@ -1249,7 +1250,7 @@ static bool up_rxavailable(struct uart_dev_s *dev) static void up_send(struct uart_dev_s *dev, int ch) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; up_serialout(priv, LPC43_UART_THR_OFFSET, (uint32_t)ch); } @@ -1263,7 +1264,7 @@ static void up_send(struct uart_dev_s *dev, int ch) static void up_txint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; flags = irqsave(); @@ -1298,7 +1299,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) static bool up_txready(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return ((up_serialin(priv, LPC43_UART_LSR_OFFSET) & UART_LSR_THRE) != 0); } @@ -1312,7 +1313,7 @@ static bool up_txready(struct uart_dev_s *dev) static bool up_txempty(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return ((up_serialin(priv, LPC43_UART_LSR_OFFSET) & UART_LSR_THRE) != 0); } @@ -1412,7 +1413,7 @@ void up_serialinit(void) int up_putc(int ch) { #ifdef HAVE_CONSOLE - struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv; + struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv; uint32_t ier; up_disableuartint(priv, &ier); #endif diff --git a/arch/arm/src/lpc43xx/lpc43_spi.c b/arch/arm/src/lpc43xx/lpc43_spi.c index fe71636cfe4..f1ae4bbf4f2 100644 --- a/arch/arm/src/lpc43xx/lpc43_spi.c +++ b/arch/arm/src/lpc43xx/lpc43_spi.c @@ -253,7 +253,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) divisor = SPI_CLOCK / frequency; - /* The SPI CCR register must contain an even number greater than or equal to 8. */ + /* The SPI CCR register must contain an even number greater than or equal to 8. */ if (divisor < 8) { @@ -314,7 +314,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) /* Yes... Set CR appropriately */ regval = getreg32(LPC43_SPI_CR); - regval &= ~(SPI_CR_CPOL|SPI_CR_CPHA); + regval &= ~(SPI_CR_CPOL | SPI_CR_CPHA); switch (mode) { @@ -330,7 +330,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) break; case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ - regval |= (SPI_CR_CPOL|SPI_CR_CPHA); + regval |= (SPI_CR_CPOL | SPI_CR_CPHA); break; default: @@ -447,7 +447,7 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords) { - FAR uint8_t *ptr = (FAR uint8_t*)buffer; + FAR uint8_t *ptr = (FAR uint8_t *)buffer; uint8_t data; spidbg("nwords: %d\n", nwords); @@ -493,7 +493,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords) { - FAR uint8_t *ptr = (FAR uint8_t*)buffer; + FAR uint8_t *ptr = (FAR uint8_t *)buffer; spidbg("nwords: %d\n", nwords); while (nwords) @@ -509,16 +509,16 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw * data transfer. */ - while ((getreg32(LPC43_SPI_SR) & SPI_SR_SPIF) == 0); + while ((getreg32(LPC43_SPI_SR) & SPI_SR_SPIF) == 0); - /* Read the SPI Status Register again to clear the status bit */ + /* Read the SPI Status Register again to clear the status bit */ - (void)getreg32(LPC43_SPI_SR); + (void)getreg32(LPC43_SPI_SR); - /* Read the received data from the SPI Data Register */ + /* Read the received data from the SPI Data Register */ - *ptr++ = (uint8_t)getreg32(LPC43_SPI_DR); - nwords--; + *ptr++ = (uint8_t)getreg32(LPC43_SPI_DR); + nwords--; } } @@ -559,7 +559,7 @@ FAR struct spi_dev_s *lpc43_spiinitialize(int port) /* Configure 8-bit SPI mode and master mode */ - putreg32(SPI_CR_BITS_8BITS|SPI_CR_BITENABLE|SPI_CR_MSTR, LPC43_SPI_CR); + putreg32(SPI_CR_BITS_8BITS | SPI_CR_BITENABLE | SPI_CR_MSTR, LPC43_SPI_CR); /* Set the initial SPI configuration */ diff --git a/arch/arm/src/lpc43xx/lpc43_ssp.c b/arch/arm/src/lpc43xx/lpc43_ssp.c index 49a4673a7d7..8fbc2ad7923 100644 --- a/arch/arm/src/lpc43xx/lpc43_ssp.c +++ b/arch/arm/src/lpc43xx/lpc43_ssp.c @@ -348,7 +348,7 @@ static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) divisor = priv->sspbasefreq / frequency; - /* "In master mode, CPSDVSRmin = 2 or larger (even numbers only)" */ + /* "In master mode, CPSDVSRmin = 2 or larger (even numbers only)" */ if (divisor < 2) { @@ -409,7 +409,7 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) /* Yes... Set CR0 appropriately */ regval = ssp_getreg(priv, LPC43_SSP_CR0_OFFSET); - regval &= ~(SSP_CR0_CPOL|SSP_CR0_CPHA); + regval &= ~(SSP_CR0_CPOL | SSP_CR0_CPHA); switch (mode) { @@ -425,7 +425,7 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) break; case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ - regval |= (SSP_CR0_CPOL|SSP_CR0_CPHA); + regval |= (SSP_CR0_CPOL | SSP_CR0_CPHA); break; default: @@ -840,7 +840,7 @@ FAR struct spi_dev_s *lpc43_sspinitialize(int port) /* Configure 8-bit SPI mode */ - ssp_putreg(priv, LPC43_SSP_CR0_OFFSET, SSP_CR0_DSS_8BIT|SSP_CR0_FRF_SPI); + ssp_putreg(priv, LPC43_SSP_CR0_OFFSET, SSP_CR0_DSS_8BIT | SSP_CR0_FRF_SPI); /* Disable the SSP and all interrupts (we'll poll for all data) */ diff --git a/arch/arm/src/lpc43xx/lpc43_start.c b/arch/arm/src/lpc43xx/lpc43_start.c index 0f3163881ef..80ffb581ee8 100644 --- a/arch/arm/src/lpc43xx/lpc43_start.c +++ b/arch/arm/src/lpc43xx/lpc43_start.c @@ -1,6 +1,5 @@ /**************************************************************************** * arch/arm/src/lpc43xx/lpc43_start.c - * arch/arm/src/chip/lpc43_start.c * * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -357,5 +356,5 @@ void __start(void) /* Shouldn't get here */ - for (;;); + for (; ; ); } diff --git a/arch/arm/src/lpc43xx/lpc43_timerisr.c b/arch/arm/src/lpc43xx/lpc43_timerisr.c index 12f3be83883..2b728f7fb43 100644 --- a/arch/arm/src/lpc43xx/lpc43_timerisr.c +++ b/arch/arm/src/lpc43xx/lpc43_timerisr.c @@ -142,7 +142,7 @@ void up_timer_initialize(void) /* Enable SysTick interrupts */ - putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT| + putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); /* And enable the timer interrupt */ diff --git a/arch/arm/src/lpc43xx/lpc43_uart.c b/arch/arm/src/lpc43xx/lpc43_uart.c index 95c5aeb9042..c0775265c2f 100644 --- a/arch/arm/src/lpc43xx/lpc43_uart.c +++ b/arch/arm/src/lpc43xx/lpc43_uart.c @@ -232,15 +232,17 @@ void lpc43_lowsetup(void) /* Clear fifos */ - putreg32(UART_FCR_RXRST|UART_FCR_TXRST, CONSOLE_BASE+LPC43_UART_FCR_OFFSET); + putreg32(UART_FCR_RXRST | UART_FCR_TXRST, + CONSOLE_BASE + LPC43_UART_FCR_OFFSET); /* Set trigger */ - putreg32(UART_FCR_FIFOEN|UART_FCR_RXTRIGGER_8, CONSOLE_BASE+LPC43_UART_FCR_OFFSET); + putreg32(UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8, + CONSOLE_BASE + LPC43_UART_FCR_OFFSET); /* Set up the LCR */ - putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE+LPC43_UART_LCR_OFFSET); + putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE + LPC43_UART_LCR_OFFSET); /* Set the BAUD divisor */ @@ -248,8 +250,8 @@ void lpc43_lowsetup(void) /* Configure the FIFOs */ - putreg32(UART_FCR_RXTRIGGER_8|UART_FCR_TXRST|UART_FCR_RXRST|UART_FCR_FIFOEN, - CONSOLE_BASE+LPC43_UART_FCR_OFFSET); + putreg32(UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST | UART_FCR_RXRST | + UART_FCR_FIFOEN, CONSOLE_BASE + LPC43_UART_FCR_OFFSET); #endif #endif /* HAVE_UART */ } diff --git a/arch/arm/src/lpc43xx/lpc43_usb0dev.c b/arch/arm/src/lpc43xx/lpc43_usb0dev.c index 90344a4898d..849f90626ea 100644 --- a/arch/arm/src/lpc43xx/lpc43_usb0dev.c +++ b/arch/arm/src/lpc43xx/lpc43_usb0dev.c @@ -527,20 +527,20 @@ static uint32_t lpc43_getreg(uint32_t addr) else { - /* Did we print "..." for the previous value? */ + /* Did we print "..." for the previous value? */ - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ - lldbg("[repeats %d more times]\n", count-3); - } + lldbg("[repeats %d more times]\n", count-3); + } - /* Save the new address, value, and count */ + /* Save the new address, value, and count */ - prevaddr = addr; - preval = val; - count = 1; + prevaddr = addr; + preval = val; + count = 1; } /* Show the register value read */ @@ -1054,15 +1054,13 @@ static void lpc43_ep0configure(struct lpc43_usbdev_s *priv) /* Enable ep0 IN and ep0 OUT */ g_qh[LPC43_EP0_OUT].capability = (DQH_CAPABILITY_MAX_PACKET(CONFIG_USBDEV_EP0_MAXSIZE) | - DQH_CAPABILITY_IOS | - DQH_CAPABILITY_ZLT); + DQH_CAPABILITY_IOS | DQH_CAPABILITY_ZLT); - g_qh[LPC43_EP0_IN ].capability = (DQH_CAPABILITY_MAX_PACKET(CONFIG_USBDEV_EP0_MAXSIZE) | - DQH_CAPABILITY_IOS | - DQH_CAPABILITY_ZLT); + g_qh[LPC43_EP0_IN].capability = (DQH_CAPABILITY_MAX_PACKET(CONFIG_USBDEV_EP0_MAXSIZE) | + DQH_CAPABILITY_IOS | DQH_CAPABILITY_ZLT); g_qh[LPC43_EP0_OUT].currdesc = DTD_NEXTDESC_INVALID; - g_qh[LPC43_EP0_IN ].currdesc = DTD_NEXTDESC_INVALID; + g_qh[LPC43_EP0_IN].currdesc = DTD_NEXTDESC_INVALID; /* Enable EP0 */ @@ -1752,7 +1750,7 @@ static int lpc43_usbinterrupt(int irq, FAR void *context) if (disr & USBDEV_USBSTS_URI) { - usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_DEVRESET),0); + usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_DEVRESET), 0); lpc43_usbreset(priv); @@ -1766,7 +1764,7 @@ static int lpc43_usbinterrupt(int irq, FAR void *context) if (!priv->suspended && (disr & USBDEV_USBSTS_SLI) != 0) { - usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_SUSPENDED),0); + usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_SUSPENDED), 0); /* Inform the Class driver of the suspend event */ @@ -1785,7 +1783,7 @@ static int lpc43_usbinterrupt(int irq, FAR void *context) else if (priv->suspended && (disr & USBDEV_USBSTS_SLI) == 0) { - usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_RESUMED),0); + usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_RESUMED), 0); /* Inform the Class driver of the resume event */ diff --git a/arch/arm/src/lpc43xx/lpc43_userspace.c b/arch/arm/src/lpc43xx/lpc43_userspace.c index 822381b2491..43ded6b4abe 100644 --- a/arch/arm/src/lpc43xx/lpc43_userspace.c +++ b/arch/arm/src/lpc43xx/lpc43_userspace.c @@ -87,8 +87,8 @@ void lpc43_userspace(void) DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && USERSPACE->us_bssstart <= USERSPACE->us_bssend); - dest = (uint8_t*)USERSPACE->us_bssstart; - end = (uint8_t*)USERSPACE->us_bssend; + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; while (dest != end) { @@ -101,9 +101,9 @@ void lpc43_userspace(void) USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && USERSPACE->us_datastart <= USERSPACE->us_dataend); - src = (uint8_t*)USERSPACE->us_datasource; - dest = (uint8_t*)USERSPACE->us_datastart; - end = (uint8_t*)USERSPACE->us_dataend; + src = (uint8_t *)USERSPACE->us_datasource; + dest = (uint8_t *)USERSPACE->us_datastart; + end = (uint8_t *)USERSPACE->us_dataend; while (dest != end) { diff --git a/arch/arm/src/moxart/moxart_16550.c b/arch/arm/src/moxart/moxart_16550.c index d2008f945cb..1078e920f30 100644 --- a/arch/arm/src/moxart/moxart_16550.c +++ b/arch/arm/src/moxart/moxart_16550.c @@ -98,7 +98,7 @@ int uart_ioctl(struct file *filep, int cmd, unsigned long arg) { struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; - struct u16550_s *priv = (struct u16550_s*)dev->priv; + struct u16550_s *priv = (struct u16550_s *)dev->priv; int ret = -ENOTTY; uint32_t vmode; unsigned int opmode; diff --git a/arch/arm/src/moxart/moxart_systemreset.c b/arch/arm/src/moxart/moxart_systemreset.c index de671edb233..6e3e6704721 100644 --- a/arch/arm/src/moxart/moxart_systemreset.c +++ b/arch/arm/src/moxart/moxart_systemreset.c @@ -76,7 +76,7 @@ void up_systemreset(void) /* Wait for the reset */ - for (;;); + for (; ; ); } /**************************************************************************** diff --git a/arch/arm/src/nuc1xx/nuc_irq.c b/arch/arm/src/nuc1xx/nuc_irq.c index e10c65effef..8e2b4a2c90c 100644 --- a/arch/arm/src/nuc1xx/nuc_irq.c +++ b/arch/arm/src/nuc1xx/nuc_irq.c @@ -59,7 +59,7 @@ /* Get a 32-bit version of the default priority */ #define DEFPRIORITY32 \ - (NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 |\ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT) /**************************************************************************** diff --git a/arch/arm/src/nuc1xx/nuc_lowputc.c b/arch/arm/src/nuc1xx/nuc_lowputc.c index e9248ac7804..be949b2c9a1 100644 --- a/arch/arm/src/nuc1xx/nuc_lowputc.c +++ b/arch/arm/src/nuc1xx/nuc_lowputc.c @@ -161,7 +161,7 @@ void nuc_lowsetup(void) #ifdef CONFIG_NUC_UART0 #ifdef CONFIG_UART0_FLOWCONTROL - regval |= (GCR_GPB_MFP0 | GCR_GPB_MFP1 | GCR_GPB_MFP2| GCR_GPB_MFP3); + regval |= (GCR_GPB_MFP0 | GCR_GPB_MFP1 | GCR_GPB_MFP2 | GCR_GPB_MFP3); #else regval |= (GCR_GPB_MFP0 | GCR_GPB_MFP1); #endif @@ -174,7 +174,7 @@ void nuc_lowsetup(void) #ifdef CONFIG_NUC_UART1 #ifdef CONFIG_UART1_FLOWCONTROL - regval |= (GCR_GPB_MFP4 | GCR_GPB_MFP5 | GCR_GPB_MFP6| GCR_GPB_MFP7) + regval |= (GCR_GPB_MFP4 | GCR_GPB_MFP5 | GCR_GPB_MFP6 | GCR_GPB_MFP7) #else regval |= (GCR_GPB_MFP4 | GCR_GPB_MFP5); #endif @@ -365,7 +365,7 @@ void nuc_setbaud(uintptr_t base, uint32_t baud) regval = getreg32(base + NUC_UART_BAUD_OFFSET); - /* Mode 0: Source Clock mod 16 < 3 => Using Divider X = 16 */ + /* Mode 0: Source Clock mod 16 < 3 => Using Divider X = 16 */ clksperbit = (NUC_UART_CLK + (baud >> 1)) / baud; if ((clksperbit & 15) < 3) diff --git a/arch/arm/src/nuc1xx/nuc_serial.c b/arch/arm/src/nuc1xx/nuc_serial.c index 8fe9c6f14e8..d31bcf3bedb 100644 --- a/arch/arm/src/nuc1xx/nuc_serial.c +++ b/arch/arm/src/nuc1xx/nuc_serial.c @@ -449,7 +449,7 @@ static void up_rxto_enable(struct nuc_dev_s *priv) static int up_setup(struct uart_dev_s *dev) { #ifndef CONFIG_SUPPRESS_UART_CONFIG - struct nuc_dev_s *priv = (struct nuc_dev_s*)dev->priv; + struct nuc_dev_s *priv = (struct nuc_dev_s *)dev->priv; uint32_t regval; /* Reset the TX FIFO */ @@ -542,7 +542,7 @@ static int up_setup(struct uart_dev_s *dev) static void up_shutdown(struct uart_dev_s *dev) { - struct nuc_dev_s *priv = (struct nuc_dev_s*)dev->priv; + struct nuc_dev_s *priv = (struct nuc_dev_s *)dev->priv; up_disableuartint(priv, NULL); } @@ -563,7 +563,7 @@ static void up_shutdown(struct uart_dev_s *dev) static int up_attach(struct uart_dev_s *dev) { - struct nuc_dev_s *priv = (struct nuc_dev_s*)dev->priv; + struct nuc_dev_s *priv = (struct nuc_dev_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -571,11 +571,11 @@ static int up_attach(struct uart_dev_s *dev) ret = irq_attach(priv->irq, up_interrupt); if (ret == OK) { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the UART - */ + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ - up_enable_irq(priv->irq); + up_enable_irq(priv->irq); } return ret; @@ -593,7 +593,7 @@ static int up_attach(struct uart_dev_s *dev) static void up_detach(struct uart_dev_s *dev) { - struct nuc_dev_s *priv = (struct nuc_dev_s*)dev->priv; + struct nuc_dev_s *priv = (struct nuc_dev_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -644,7 +644,7 @@ static int up_interrupt(int irq, void *context) { PANIC(); } - priv = (struct nuc_dev_s*)dev->priv; + priv = (struct nuc_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, * until we have been looping for a long time. @@ -700,7 +700,7 @@ static int up_interrupt(int irq, void *context) * data in the RX FIFO when we entered the interrupt handler? */ - else if ((priv->ier & (UART_IER_RTO_IEN|UART_IER_RDA_IEN)) == UART_IER_RDA_IEN && !rxfe) + else if ((priv->ier & (UART_IER_RTO_IEN | UART_IER_RDA_IEN)) == UART_IER_RDA_IEN && !rxfe) { /* We are receiving data and the RX timeout is not enabled. * Set the RX FIFO threshold so that RX interrupts will only be @@ -757,7 +757,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; - struct nuc_dev_s *priv = (struct nuc_dev_s*)dev->priv; + struct nuc_dev_s *priv = (struct nuc_dev_s *)dev->priv; int ret = OK; switch (cmd) @@ -765,7 +765,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct nuc_dev_s *user = (struct nuc_dev_s*)arg; + struct nuc_dev_s *user = (struct nuc_dev_s *)arg; if (!user) { ret = -EINVAL; @@ -786,7 +786,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_TERMIOS case TCGETS: { - struct termios *termiosp = (struct termios*)arg; + struct termios *termiosp = (struct termios *)arg; if (!termiosp) { @@ -806,7 +806,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) case TCSETS: { - struct termios *termiosp = (struct termios*)arg; + struct termios *termiosp = (struct termios *)arg; uint32_t lcr; /* Holds current values of line control register */ uint16_t dl; /* Divisor latch */ @@ -853,7 +853,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) static int up_receive(struct uart_dev_s *dev, uint32_t *status) { - struct nuc_dev_s *priv = (struct nuc_dev_s*)dev->priv; + struct nuc_dev_s *priv = (struct nuc_dev_s *)dev->priv; uint32_t rbr; *status = up_serialin(priv, NUC_UART_FSR_OFFSET); @@ -871,7 +871,7 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status) static void up_rxint(struct uart_dev_s *dev, bool enable) { - struct nuc_dev_s *priv = (struct nuc_dev_s*)dev->priv; + struct nuc_dev_s *priv = (struct nuc_dev_s *)dev->priv; if (enable) { @@ -929,7 +929,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) static bool up_rxavailable(struct uart_dev_s *dev) { - struct nuc_dev_s *priv = (struct nuc_dev_s*)dev->priv; + struct nuc_dev_s *priv = (struct nuc_dev_s *)dev->priv; return ((up_serialin(priv, NUC_UART_FSR_OFFSET) & UART_FSR_RX_EMPTY) == 0); } @@ -943,7 +943,7 @@ static bool up_rxavailable(struct uart_dev_s *dev) static void up_send(struct uart_dev_s *dev, int ch) { - struct nuc_dev_s *priv = (struct nuc_dev_s*)dev->priv; + struct nuc_dev_s *priv = (struct nuc_dev_s *)dev->priv; up_serialout(priv, NUC_UART_THR_OFFSET, (uint32_t)ch); } @@ -957,7 +957,7 @@ static void up_send(struct uart_dev_s *dev, int ch) static void up_txint(struct uart_dev_s *dev, bool enable) { - struct nuc_dev_s *priv = (struct nuc_dev_s*)dev->priv; + struct nuc_dev_s *priv = (struct nuc_dev_s *)dev->priv; if (enable) { @@ -993,7 +993,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) static bool up_txready(struct uart_dev_s *dev) { - struct nuc_dev_s *priv = (struct nuc_dev_s*)dev->priv; + struct nuc_dev_s *priv = (struct nuc_dev_s *)dev->priv; uint32_t regval; int depth; @@ -1012,7 +1012,7 @@ static bool up_txready(struct uart_dev_s *dev) static bool up_txempty(struct uart_dev_s *dev) { - struct nuc_dev_s *priv = (struct nuc_dev_s*)dev->priv; + struct nuc_dev_s *priv = (struct nuc_dev_s *)dev->priv; return ((up_serialin(priv, NUC_UART_FSR_OFFSET) & UART_FSR_TE_FLAG) != 0); } @@ -1079,7 +1079,7 @@ void up_serialinit(void) int up_putc(int ch) { #ifdef HAVE_CONSOLE - struct nuc_dev_s *priv = (struct nuc_dev_s*)CONSOLE_DEV.priv; + struct nuc_dev_s *priv = (struct nuc_dev_s *)CONSOLE_DEV.priv; uint32_t ier; up_disableuartint(priv, &ier); #endif diff --git a/arch/arm/src/nuc1xx/nuc_start.c b/arch/arm/src/nuc1xx/nuc_start.c index e7cf1b4b1f4..3cbb5becdee 100644 --- a/arch/arm/src/nuc1xx/nuc_start.c +++ b/arch/arm/src/nuc1xx/nuc_start.c @@ -174,5 +174,5 @@ void __start(void) /* Shoulnd't get here */ - for (;;); + for (; ; ); } diff --git a/arch/arm/src/nuc1xx/nuc_userspace.c b/arch/arm/src/nuc1xx/nuc_userspace.c index 2ace6184b76..e0fc09cbcd1 100644 --- a/arch/arm/src/nuc1xx/nuc_userspace.c +++ b/arch/arm/src/nuc1xx/nuc_userspace.c @@ -86,8 +86,8 @@ void nuc_userspace(void) DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && USERSPACE->us_bssstart <= USERSPACE->us_bssend); - dest = (uint8_t*)USERSPACE->us_bssstart; - end = (uint8_t*)USERSPACE->us_bssend; + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; while (dest != end) { @@ -100,9 +100,9 @@ void nuc_userspace(void) USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && USERSPACE->us_datastart <= USERSPACE->us_dataend); - src = (uint8_t*)USERSPACE->us_datasource; - dest = (uint8_t*)USERSPACE->us_datastart; - end = (uint8_t*)USERSPACE->us_dataend; + src = (uint8_t *)USERSPACE->us_datasource; + dest = (uint8_t *)USERSPACE->us_datastart; + end = (uint8_t *)USERSPACE->us_dataend; while (dest != end) { diff --git a/arch/arm/src/sam34/sam4l_clockconfig.c b/arch/arm/src/sam34/sam4l_clockconfig.c index 17e04acda04..657f0b919d0 100644 --- a/arch/arm/src/sam34/sam4l_clockconfig.c +++ b/arch/arm/src/sam34/sam4l_clockconfig.c @@ -1067,9 +1067,9 @@ static inline void sam_flash_config(uint32_t cpuclock, uint32_t psm, bool fastwk } } - /* The is below the threshold that requires one wait state. But we - * have to check a few more things. - */ + /* The is below the threshold that requires one wait state. But we + * have to check a few more things. + */ else { diff --git a/arch/arm/src/sam34/sam4l_periphclks.c b/arch/arm/src/sam34/sam4l_periphclks.c index b344992f337..9230b0f7110 100644 --- a/arch/arm/src/sam34/sam4l_periphclks.c +++ b/arch/arm/src/sam34/sam4l_periphclks.c @@ -530,14 +530,14 @@ void sam_pba_disableperipheral(uint32_t bitset) sam_hsb_disableperipheral(PM_HSBMASK_APBA); } - /* Disable PBA UART divided clock if none of the UARTS are in use */ + /* Disable PBA UART divided clock if none of the UARTS are in use */ if ((getreg32(SAM_PM_PBAMASK) & PM_PBAMASK_UARTS) == 0) { sam_pba_disabledivmask(PM_PBADIVMASK_CLK_USART); } - /* Disable PBA TIMER divided clocks if none of the UARTS are in use */ + /* Disable PBA TIMER divided clocks if none of the UARTS are in use */ if ((getreg32(SAM_PM_PBAMASK) & PM_PBAMASK_TIMERS) == 0) { diff --git a/arch/arm/src/sam34/sam_aes.c b/arch/arm/src/sam34/sam_aes.c index b39c8f45aa4..29634e69c77 100644 --- a/arch/arm/src/sam34/sam_aes.c +++ b/arch/arm/src/sam34/sam_aes.c @@ -100,15 +100,15 @@ static void aes_memcpy(void *out, const void *in, size_t size) { size_t i; size_t wcount = size / 4; - for (i = 0; i < wcount; i++, out = (uint8_t*)out + 4, in = (uint8_t*)in + 4) + for (i = 0; i < wcount; i++, out = (uint8_t *)out + 4, in = (uint8_t *)in + 4) { - *(uint32_t*)out = *(uint32_t*)in; + *(uint32_t *)out = *(uint32_t *)in; } } static void aes_encryptblock(void *out, const void *in) { - aes_memcpy((void*)SAM_AES_IDATAR, in, AES_BLOCK_SIZE); + aes_memcpy((void *)SAM_AES_IDATAR, in, AES_BLOCK_SIZE); putreg32(AES_CR_START, SAM_AES_CR); @@ -116,7 +116,7 @@ static void aes_encryptblock(void *out, const void *in) if (out) { - aes_memcpy(out, (void*)SAM_AES_ODATAR, AES_BLOCK_SIZE); + aes_memcpy(out, (void *)SAM_AES_ODATAR, AES_BLOCK_SIZE); } } @@ -193,10 +193,10 @@ int aes_cypher(void *out, const void *in, uint32_t size, const void *iv, return res; } - aes_memcpy((void*)SAM_AES_KEYWR, key, keysize); + aes_memcpy((void *)SAM_AES_KEYWR, key, keysize); if (iv) { - aes_memcpy((void*)SAM_AES_IVR, iv, AES_BLOCK_SIZE); + aes_memcpy((void *)SAM_AES_IVR, iv, AES_BLOCK_SIZE); } while (size) @@ -204,7 +204,7 @@ int aes_cypher(void *out, const void *in, uint32_t size, const void *iv, if ((mode & AES_MODE_MAC) == 0) { aes_encryptblock(out, in); - out = (char*)out + AES_BLOCK_SIZE; + out = (char *)out + AES_BLOCK_SIZE; } else if (size == AES_BLOCK_SIZE) { @@ -215,7 +215,7 @@ int aes_cypher(void *out, const void *in, uint32_t size, const void *iv, aes_encryptblock(NULL, in); } - in = (char*)in + AES_BLOCK_SIZE; + in = (char *)in + AES_BLOCK_SIZE; size -= AES_BLOCK_SIZE; } diff --git a/arch/arm/src/sam34/sam_allocateheap.c b/arch/arm/src/sam34/sam_allocateheap.c index 8c40a7d5844..0f0b981ee48 100644 --- a/arch/arm/src/sam34/sam_allocateheap.c +++ b/arch/arm/src/sam34/sam_allocateheap.c @@ -231,7 +231,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ board_led_on(LED_HEAPALLOCATE); - *heap_start = (FAR void*)ubase; + *heap_start = (FAR void *)ubase; *heap_size = usize; /* Allow user-mode access to the user heap memory */ @@ -242,7 +242,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the heap settings */ board_led_on(LED_HEAPALLOCATE); - *heap_start = (FAR void*)g_idle_topstack; + *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; #endif } @@ -286,7 +286,7 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) * that was not dedicated to the user heap). */ - *heap_start = (FAR void*)USERSPACE->us_bssend; + *heap_start = (FAR void *)USERSPACE->us_bssend; *heap_size = ubase - (uintptr_t)USERSPACE->us_bssend; } #endif @@ -314,7 +314,7 @@ void up_addregion(void) /* Add the region */ - kumm_addregion((FAR void*)SAM_INTSRAM1_BASE, SAM34_SRAM1_SIZE); + kumm_addregion((FAR void *)SAM_INTSRAM1_BASE, SAM34_SRAM1_SIZE); #endif /* HAVE_SRAM1_REGION */ @@ -334,7 +334,7 @@ void up_addregion(void) /* Add the region */ - kumm_addregion((FAR void*)SAM_NFCSRAM_BASE, SAM34_NFCSRAM_SIZE); + kumm_addregion((FAR void *)SAM_NFCSRAM_BASE, SAM34_NFCSRAM_SIZE); #endif /* HAVE_NFCSRAM_REGION */ @@ -345,7 +345,7 @@ void up_addregion(void) /* Add the region */ - kumm_addregion((FAR void*)SAM_EXTCS0_BASE, CONFIG_SAM34_EXTSRAM0SIZE); + kumm_addregion((FAR void *)SAM_EXTCS0_BASE, CONFIG_SAM34_EXTSRAM0SIZE); #endif /* HAVE_EXTSRAM0_REGION */ @@ -356,7 +356,7 @@ void up_addregion(void) /* Add the region */ - kumm_addregion((FAR void*)SAM_EXTCS1_BASE, CONFIG_SAM34_EXTSRAM1SIZE); + kumm_addregion((FAR void *)SAM_EXTCS1_BASE, CONFIG_SAM34_EXTSRAM1SIZE); #endif /* HAVE_EXTSRAM0_REGION */ @@ -367,7 +367,7 @@ void up_addregion(void) /* Add the region */ - kumm_addregion((FAR void*)SAM_EXTCS2_BASE, CONFIG_SAM34_EXTSRAM2SIZE); + kumm_addregion((FAR void *)SAM_EXTCS2_BASE, CONFIG_SAM34_EXTSRAM2SIZE); #endif /* HAVE_EXTSRAM0_REGION */ @@ -378,7 +378,7 @@ void up_addregion(void) /* Add the region */ - kumm_addregion((FAR void*)SAM_EXTCS3_BASE, CONFIG_SAM34_EXTSRAM3SIZE); + kumm_addregion((FAR void *)SAM_EXTCS3_BASE, CONFIG_SAM34_EXTSRAM3SIZE); #endif /* HAVE_EXTSRAM0_REGION */ } diff --git a/arch/arm/src/sam34/sam_clockconfig.c b/arch/arm/src/sam34/sam_clockconfig.c index 66e37d09e30..3dce96b02e5 100644 --- a/arch/arm/src/sam34/sam_clockconfig.c +++ b/arch/arm/src/sam34/sam_clockconfig.c @@ -151,7 +151,7 @@ static inline void sam_supcsetup(void) { uint32_t delay; - putreg32((SUPC_CR_XTALSEL|SUPR_CR_KEY), SAM_SUPC_CR); + putreg32((SUPC_CR_XTALSEL | SUPR_CR_KEY), SAM_SUPC_CR); for (delay = 0; (getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0 && delay < UINT32_MAX; delay++); @@ -310,19 +310,19 @@ static inline void sam_enabledefaultmaster(void) /* Set default master: SRAM0 -> Cortex-M3 System */ regval = getreg32(SAM_MATRIX_SCFG0); - regval |= (MATRIX_SCFG0_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED); + regval |= (MATRIX_SCFG0_FIXEDDEFMSTR_ARMS | MATRIX_SCFG_DEFMSTRTYPE_FIXED); putreg32(regval, SAM_MATRIX_SCFG0); /* Set default master: SRAM1 -> Cortex-M3 System */ regval = getreg32(SAM_MATRIX_SCFG1); - regval |= (MATRIX_SCFG1_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED); + regval |= (MATRIX_SCFG1_FIXEDDEFMSTR_ARMS | MATRIX_SCFG_DEFMSTRTYPE_FIXED); putreg32(regval, SAM_MATRIX_SCFG1); /* Set default master: Internal flash0 -> Cortex-M3 Instruction/Data */ regval = getreg32(SAM_MATRIX_SCFG3); - regval |= (MATRIX_SCFG3_FIXEDDEFMSTR_ARMC|MATRIX_SCFG_DEFMSTRTYPE_FIXED); + regval |= (MATRIX_SCFG3_FIXEDDEFMSTR_ARMC | MATRIX_SCFG_DEFMSTRTYPE_FIXED); putreg32(regval, SAM_MATRIX_SCFG3); } diff --git a/arch/arm/src/sam34/sam_dmac.c b/arch/arm/src/sam34/sam_dmac.c index d9f31eb52db..28c4c5ecc43 100644 --- a/arch/arm/src/sam34/sam_dmac.c +++ b/arch/arm/src/sam34/sam_dmac.c @@ -1307,7 +1307,7 @@ static int sam_dmainterrupt(int irq, void *context) if ((regval & DMAC_EBC_ERR(chndx)) != 0) { - /* Yes... Terminate the transfer with an error? */ + /* Yes... Terminate the transfer with an error? */ sam_dmaterminate(dmach, -EIO); } @@ -1315,7 +1315,7 @@ static int sam_dmainterrupt(int irq, void *context) /* Is the transfer complete? */ else if ((regval & DMAC_EBC_CBTC(chndx)) != 0) - { + { /* Yes.. Terminate the transfer with success */ sam_dmaterminate(dmach, OK); diff --git a/arch/arm/src/sam34/sam_emac.c b/arch/arm/src/sam34/sam_emac.c index abb2f4a8f19..afb7406c88f 100644 --- a/arch/arm/src/sam34/sam_emac.c +++ b/arch/arm/src/sam34/sam_emac.c @@ -1268,7 +1268,7 @@ static void sam_receive(struct sam_emac_s *priv) */ if (priv->dev.d_len > 0) - { + { /* Update the Ethernet header with the correct MAC address */ #ifdef CONFIG_NET_IPv4 @@ -2434,7 +2434,7 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac) if (regval == 0 && sam_getreg(priv, regaddr2) == 0) { - /* Yes.. disable all address matching */ + /* Yes.. disable all address matching */ regval = sam_getreg(priv, SAM_EMAC_NCFGR); regval &= ~(EMAC_NCFGR_UNIHEN | EMAC_NCFGR_MTIHEN); @@ -3110,7 +3110,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv) /* Check AutoNegotiate complete */ timeout = 0; - for (;;) + for (; ; ) { ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr); if (ret < 0) @@ -3429,14 +3429,14 @@ static void sam_txreset(struct sam_emac_s *priv) priv->txtail = 0; for (ndx = 0; ndx < CONFIG_SAM34_EMAC_NTXBUFFERS; ndx++) - { - bufaddr = (uint32_t)(&(txbuffer[ndx * EMAC_TX_UNITSIZE])); + { + bufaddr = (uint32_t)(&(txbuffer[ndx * EMAC_TX_UNITSIZE])); - /* Set the buffer address and mark the descriptor as in used by firmware */ + /* Set the buffer address and mark the descriptor as in used by firmware */ - txdesc[ndx].addr = bufaddr; - txdesc[ndx].status = EMACTXD_STA_USED; - } + txdesc[ndx].addr = bufaddr; + txdesc[ndx].status = EMACTXD_STA_USED; + } /* Mark the final descriptor in the list */ @@ -3482,17 +3482,17 @@ static void sam_rxreset(struct sam_emac_s *priv) priv->rxndx = 0; for (ndx = 0; ndx < CONFIG_SAM34_EMAC_NRXBUFFERS; ndx++) - { - bufaddr = (uintptr_t)(&(rxbuffer[ndx * EMAC_RX_UNITSIZE])); - DEBUGASSERT((bufaddr & ~EMACRXD_ADDR_MASK) == 0); + { + bufaddr = (uintptr_t)(&(rxbuffer[ndx * EMAC_RX_UNITSIZE])); + DEBUGASSERT((bufaddr & ~EMACRXD_ADDR_MASK) == 0); - /* Set the buffer address and remove EMACRXD_ADDR_OWNER and - * EMACRXD_ADDR_WRAP. - */ + /* Set the buffer address and remove EMACRXD_ADDR_OWNER and + * EMACRXD_ADDR_WRAP. + */ - rxdesc[ndx].addr = bufaddr; - rxdesc[ndx].status = 0; - } + rxdesc[ndx].addr = bufaddr; + rxdesc[ndx].status = 0; + } /* Mark the final descriptor in the list */ @@ -3703,7 +3703,7 @@ static int sam_emac_configure(struct sam_emac_s *priv) sam_emac_enableclk(); - /* Disable TX, RX, clear statistics. Disable all interrupts. */ + /* Disable TX, RX, clear statistics. Disable all interrupts. */ sam_putreg(priv, SAM_EMAC_NCR, EMAC_NCR_CLRSTAT); sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_ALL); @@ -3793,17 +3793,17 @@ void up_netinitialize(void) /* Initialize the driver structure */ memset(priv, 0, sizeof(struct sam_emac_s)); - priv->dev.d_ifup = sam_ifup; /* I/F up (new IP address) callback */ - priv->dev.d_ifdown = sam_ifdown; /* I/F down callback */ - priv->dev.d_txavail = sam_txavail; /* New TX data callback */ + priv->dev.d_ifup = sam_ifup; /* I/F up (new IP address) callback */ + priv->dev.d_ifdown = sam_ifdown; /* I/F down callback */ + priv->dev.d_txavail = sam_txavail; /* New TX data callback */ #ifdef CONFIG_NET_IGMP - priv->dev.d_addmac = sam_addmac; /* Add multicast MAC address */ - priv->dev.d_rmmac = sam_rmmac; /* Remove multicast MAC address */ + priv->dev.d_addmac = sam_addmac; /* Add multicast MAC address */ + priv->dev.d_rmmac = sam_rmmac; /* Remove multicast MAC address */ #endif #ifdef CONFIG_NETDEV_PHY_IOCTL - priv->dev.d_ioctl = sam_ioctl; /* Support PHY ioctl() calls */ + priv->dev.d_ioctl = sam_ioctl; /* Support PHY ioctl() calls */ #endif - priv->dev.d_private = (void*)&g_emac; /* Used to recover private state from dev */ + priv->dev.d_private = (void *)&g_emac; /* Used to recover private state from dev */ /* Create a watchdog for timing polling for and timing of transmissions */ @@ -3814,7 +3814,7 @@ void up_netinitialize(void) return; } - priv->txtimeout = wd_create(); /* Create TX timeout timer */ + priv->txtimeout = wd_create(); /* Create TX timeout timer */ if (!priv->txtimeout) { nlldbg("ERROR: Failed to create periodic poll timer\n"); diff --git a/arch/arm/src/sam34/sam_gpioirq.c b/arch/arm/src/sam34/sam_gpioirq.c index ef6df44985f..4367e814634 100644 --- a/arch/arm/src/sam34/sam_gpioirq.c +++ b/arch/arm/src/sam34/sam_gpioirq.c @@ -441,10 +441,10 @@ void sam_gpioirqenable(int irq) if (sam_irqbase(irq, &base, &pin) == OK) { - /* Clear (all) pending interrupts and enable this pin interrupt */ + /* Clear (all) pending interrupts and enable this pin interrupt */ - //(void)getreg32(base + SAM_PIO_ISR_OFFSET); - putreg32((1 << pin), base + SAM_PIO_IER_OFFSET); + //(void)getreg32(base + SAM_PIO_ISR_OFFSET); + putreg32((1 << pin), base + SAM_PIO_IER_OFFSET); } } @@ -463,9 +463,9 @@ void sam_gpioirqdisable(int irq) if (sam_irqbase(irq, &base, &pin) == OK) { - /* Disable this pin interrupt */ + /* Disable this pin interrupt */ - putreg32((1 << pin), base + SAM_PIO_IDR_OFFSET); + putreg32((1 << pin), base + SAM_PIO_IDR_OFFSET); } } diff --git a/arch/arm/src/sam34/sam_hsmci.c b/arch/arm/src/sam34/sam_hsmci.c index 4e7db3cf756..0a5548cb976 100644 --- a/arch/arm/src/sam34/sam_hsmci.c +++ b/arch/arm/src/sam34/sam_hsmci.c @@ -1042,7 +1042,7 @@ static void sam_dmacallback(DMA_HANDLE handle, void *arg, int result) priv->dmabusy = false; - sam_xfrsample((struct sam_dev_s*)arg, SAMPLENDX_DMA_CALLBACK); + sam_xfrsample((struct sam_dev_s *)arg, SAMPLENDX_DMA_CALLBACK); } #endif @@ -1250,7 +1250,7 @@ static int sam_interrupt(int irq, void *context) /* Loop while there are pending interrupts. */ - for (;;) + for (; ; ) { /* Check the HSMCI status register. Mask out all bits that don't * correspond to enabled interrupts. (This depends on the fact that @@ -1283,13 +1283,13 @@ static int sam_interrupt(int irq, void *context) { /* Yes.. Terminate with a timeout. */ - sam_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_TIMEOUT); + sam_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT); } else { /* No.. Terminate with an I/O error. */ - sam_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_ERROR); + sam_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } } else @@ -1327,25 +1327,27 @@ static int sam_interrupt(int irq, void *context) { /* Yes.. signal a timeout error */ - wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE|SDIOWAIT_TIMEOUT; + wkupevent = SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE | + SDIOWAIT_TIMEOUT; } else { /* No.. signal some generic I/O error */ - wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE|SDIOWAIT_ERROR; + wkupevent = SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE | + SDIOWAIT_ERROR; } } else { /* The Command-Response sequence ended with no error */ - wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE; + wkupevent = SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE; } - /* Yes.. Is there a thread waiting for this event set? */ + /* Yes.. Is there a thread waiting for this event set? */ - wkupevent &= priv->waitevents; + wkupevent &= priv->waitevents; if (wkupevent != 0) { /* Yes.. wake the thread up */ @@ -1650,13 +1652,13 @@ static int sam_attach(FAR struct sdio_dev_s *dev) static int sam_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; uint32_t regval; uint32_t cmdidx; sam_cmdsampleinit(); - /* Set the HSMCI Argument value */ + /* Set the HSMCI Argument value */ putreg32(arg, SAM_HSMCI_ARGR); @@ -1824,7 +1826,7 @@ static void sam_blocksetup(FAR struct sdio_dev_s *dev, unsigned int blocklen, static int sam_cancel(FAR struct sdio_dev_s *dev) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; /* Disable all transfer- and event- related interrupts */ @@ -1883,7 +1885,7 @@ static int sam_cancel(FAR struct sdio_dev_s *dev) static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; uint32_t sr; uint32_t pending; int32_t timeout; @@ -1913,7 +1915,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) /* Then wait for the response (or timeout) */ - for (;;) + for (; ; ) { /* Did a Command-Response sequence termination evernt occur? */ @@ -1938,14 +1940,16 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { /* Yes.. return a timeout error */ - priv->wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE|SDIOWAIT_TIMEOUT; + priv->wkupevent = SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE | + SDIOWAIT_TIMEOUT; return -ETIMEDOUT; } else { /* No.. return some generic I/O error */ - priv->wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE|SDIOWAIT_ERROR; + priv->wkupevent = SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE | + SDIOWAIT_ERROR; return -EIO; } } @@ -1953,7 +1957,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { /* The Command-Response sequence ended with no error */ - priv->wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE; + priv->wkupevent = SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE; return OK; } } @@ -1993,7 +1997,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) static int sam_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; int ret = OK; /* These responses could have CRC errors: @@ -2079,7 +2083,7 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev, static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong[4]) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; int ret = OK; /* R2 CID, CSD register (136-bit) @@ -2135,7 +2139,7 @@ static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong static int sam_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rnotimpl) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; priv->wkupevent = 0; return -ENOSYS; } @@ -2178,7 +2182,7 @@ static int sam_recvnotimpl(FAR struct sdio_dev_s *dev, static void sam_waitenable(FAR struct sdio_dev_s *dev, sdio_eventset_t eventset) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; uint32_t waitmask; DEBUGASSERT(priv != NULL); @@ -2192,7 +2196,7 @@ static void sam_waitenable(FAR struct sdio_dev_s *dev, */ waitmask = 0; - if ((eventset & (SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE)) != 0) + if ((eventset & (SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE)) != 0) { waitmask |= priv->cmdrmask; } @@ -2237,7 +2241,7 @@ static void sam_waitenable(FAR struct sdio_dev_s *dev, static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev, uint32_t timeout) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; sdio_eventset_t wkupevent = 0; int ret; @@ -2278,8 +2282,8 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev, 1, (uint32_t)priv); if (ret != OK) { - fdbg("ERROR: wd_start failed: %d\n", ret); - } + fdbg("ERROR: wd_start failed: %d\n", ret); + } } /* Loop until the event (or the timeout occurs). Race conditions are avoided @@ -2288,7 +2292,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev, * may have already occurred before this function was called! */ - for (;;) + for (; ; ) { /* Wait for an event in event set to occur. If this the event has already * occurred, then the semaphore will already have been incremented and @@ -2342,7 +2346,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev, static void sam_callbackenable(FAR struct sdio_dev_s *dev, sdio_eventset_t eventset) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; fvdbg("eventset: %02x\n", eventset); DEBUGASSERT(priv != NULL); @@ -2376,7 +2380,7 @@ static void sam_callbackenable(FAR struct sdio_dev_s *dev, static int sam_registercallback(FAR struct sdio_dev_s *dev, worker_t callback, void *arg) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; /* Disable callbacks and register this callback and is argument */ @@ -2572,7 +2576,7 @@ static int sam_dmasendsetup(FAR struct sdio_dev_s *dev, static void sam_callback(void *arg) { - struct sam_dev_s *priv = (struct sam_dev_s*)arg; + struct sam_dev_s *priv = (struct sam_dev_s *)arg; /* Is a callback registered? */ @@ -2589,8 +2593,8 @@ static void sam_callback(void *arg) /* Media is present. Is the media inserted event enabled? */ if ((priv->cbevents & SDIOMEDIA_INSERTED) == 0) - { - /* No... return without performing the callback */ + { + /* No... return without performing the callback */ return; } diff --git a/arch/arm/src/sam34/sam_irq.c b/arch/arm/src/sam34/sam_irq.c index 6624c0378a0..efc2ad38f56 100644 --- a/arch/arm/src/sam34/sam_irq.c +++ b/arch/arm/src/sam34/sam_irq.c @@ -62,9 +62,9 @@ /* Get a 32-bit version of the default priority */ #define DEFPRIORITY32 \ - (NVIC_SYSH_PRIORITY_DEFAULT << 24 |\ - NVIC_SYSH_PRIORITY_DEFAULT << 16 |\ - NVIC_SYSH_PRIORITY_DEFAULT << 8 |\ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | \ NVIC_SYSH_PRIORITY_DEFAULT) /* Given the address of a NVIC ENABLE register, this is the offset to @@ -310,8 +310,8 @@ static int sam_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { - *regaddr = NVIC_SYSHCON; - if (irq == SAM_IRQ_MEMFAULT) + *regaddr = NVIC_SYSHCON; + if (irq == SAM_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } diff --git a/arch/arm/src/sam34/sam_lowputc.c b/arch/arm/src/sam34/sam_lowputc.c index 54cda81b400..11548c6ef5d 100644 --- a/arch/arm/src/sam34/sam_lowputc.c +++ b/arch/arm/src/sam34/sam_lowputc.c @@ -283,7 +283,7 @@ void up_lowputc(char ch) #ifdef HAVE_CONSOLE irqstate_t flags; - for (;;) + for (; ; ) { /* Wait for the transmitter to be available */ diff --git a/arch/arm/src/sam34/sam_rtc.c b/arch/arm/src/sam34/sam_rtc.c index 405a3d40ca9..1ad734789b0 100644 --- a/arch/arm/src/sam34/sam_rtc.c +++ b/arch/arm/src/sam34/sam_rtc.c @@ -415,7 +415,7 @@ int up_rtcinitialize(void) #endif #if defined(CONFIG_RTC_HIRES) && defined(CONFIG_SAM34_RTT) - /* Using the RTT for subsecond ticks. */ + /* Using the RTT for subsecond ticks. */ sam_rtt_enableclk(); diff --git a/arch/arm/src/sam34/sam_rtt.c b/arch/arm/src/sam34/sam_rtt.c index 577f15ea9a6..5a7415f6f2d 100644 --- a/arch/arm/src/sam34/sam_rtt.c +++ b/arch/arm/src/sam34/sam_rtt.c @@ -223,20 +223,20 @@ static uint32_t sam34_getreg(uint32_t addr) else { - /* Did we print "..." for the previous value? */ + /* Did we print "..." for the previous value? */ - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ - lldbg("[repeats %d more times]\n", count-3); - } + lldbg("[repeats %d more times]\n", count-3); + } - /* Save the new address, value, and count */ + /* Save the new address, value, and count */ - prevaddr = addr; - preval = val; - count = 1; + prevaddr = addr; + preval = val; + count = 1; } /* Show the register value read */ @@ -317,7 +317,7 @@ static int sam34_interrupt(int irq, FAR void *context) */ lateticks = vr - priv->val; - if (lateticks <= (priv->clkticks>>1)) + if (lateticks <= (priv->clkticks >> 1)) { priv->clkticks -= lateticks; } diff --git a/arch/arm/src/sam34/sam_serial.c b/arch/arm/src/sam34/sam_serial.c index 1b2a00e56d5..b5381015d76 100644 --- a/arch/arm/src/sam34/sam_serial.c +++ b/arch/arm/src/sam34/sam_serial.c @@ -692,7 +692,7 @@ static void up_disableallints(struct up_dev_s *priv, uint32_t *imr) static int up_setup(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t regval; uint32_t imr; @@ -818,7 +818,7 @@ static int up_setup(struct uart_dev_s *dev) /* Enable receiver & transmitter */ - up_serialout(priv, SAM_UART_CR_OFFSET, (UART_CR_RXEN|UART_CR_TXEN)); + up_serialout(priv, SAM_UART_CR_OFFSET, (UART_CR_RXEN | UART_CR_TXEN)); up_restoreusartint(priv, imr); #endif @@ -837,12 +837,13 @@ static int up_setup(struct uart_dev_s *dev) static void up_shutdown(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Reset and disable receiver and transmitter */ up_serialout(priv, SAM_UART_CR_OFFSET, - (UART_CR_RSTRX|UART_CR_RSTTX|UART_CR_RXDIS|UART_CR_TXDIS)); + (UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | + UART_CR_TXDIS)); /* Disable all interrupts */ @@ -866,7 +867,7 @@ static void up_shutdown(struct uart_dev_s *dev) static int up_attach(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -874,11 +875,11 @@ static int up_attach(struct uart_dev_s *dev) ret = irq_attach(priv->irq, up_interrupt); if (ret == OK) { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the USART - */ + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the USART + */ - up_enable_irq(priv->irq); + up_enable_irq(priv->irq); } return ret; } @@ -895,7 +896,7 @@ static int up_attach(struct uart_dev_s *dev) static void up_detach(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -967,7 +968,7 @@ static int up_interrupt(int irq, void *context) PANIC(); } - priv = (struct up_dev_s*)dev->priv; + priv = (struct up_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, until we have * been looping for a long time. @@ -990,10 +991,10 @@ static int up_interrupt(int irq, void *context) if ((pending & UART_INT_RXRDY) != 0) { - /* Received data ready... process incoming bytes */ + /* Received data ready... process incoming bytes */ - uart_recvchars(dev); - handled = true; + uart_recvchars(dev); + handled = true; } /* Handle outgoing, transmit bytes. TXRDY: There is no character in the @@ -1002,10 +1003,10 @@ static int up_interrupt(int irq, void *context) if ((pending & UART_INT_TXRDY) != 0) { - /* Transmit data register empty ... process outgoing bytes */ + /* Transmit data register empty ... process outgoing bytes */ - uart_xmitchars(dev); - handled = true; + uart_xmitchars(dev); + handled = true; } } @@ -1033,7 +1034,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct up_dev_s *user = (struct up_dev_s*)arg; + struct up_dev_s *user = (struct up_dev_s *)arg; if (!user) { ret = -EINVAL; @@ -1049,7 +1050,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_TERMIOS case TCGETS: { - struct termios *termiosp = (struct termios*)arg; + struct termios *termiosp = (struct termios *)arg; struct up_dev_s *priv = (struct up_dev_s *)dev->priv; if (!termiosp) @@ -1106,7 +1107,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) case TCSETS: { - struct termios *termiosp = (struct termios*)arg; + struct termios *termiosp = (struct termios *)arg; struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint32_t baud; uint32_t imr; @@ -1225,7 +1226,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) static int up_receive(struct uart_dev_s *dev, uint32_t *status) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Return the error information in the saved status */ @@ -1247,7 +1248,7 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status) static void up_rxint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; if (enable) { @@ -1275,7 +1276,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) static bool up_rxavailable(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return ((up_serialin(priv, SAM_UART_SR_OFFSET) & UART_INT_RXRDY) != 0); } @@ -1289,7 +1290,7 @@ static bool up_rxavailable(struct uart_dev_s *dev) static void up_send(struct uart_dev_s *dev, int ch) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; up_serialout(priv, SAM_UART_THR_OFFSET, (uint32_t)ch); } @@ -1303,7 +1304,7 @@ static void up_send(struct uart_dev_s *dev, int ch) static void up_txint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; flags = irqsave(); @@ -1344,7 +1345,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) static bool up_txready(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return ((up_serialin(priv, SAM_UART_SR_OFFSET) & UART_INT_TXRDY) != 0); } @@ -1358,7 +1359,7 @@ static bool up_txready(struct uart_dev_s *dev) static bool up_txempty(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return ((up_serialin(priv, SAM_UART_SR_OFFSET) & UART_INT_TXEMPTY) != 0); } diff --git a/arch/arm/src/sam34/sam_spi.c b/arch/arm/src/sam34/sam_spi.c index 709330e7ffc..706178c9259 100644 --- a/arch/arm/src/sam34/sam_spi.c +++ b/arch/arm/src/sam34/sam_spi.c @@ -1302,8 +1302,8 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, if (spics->nbits > 8) { - rxptr16 = (uint16_t*)rxbuffer; - txptr16 = (uint16_t*)txbuffer; + rxptr16 = (uint16_t *)rxbuffer; + txptr16 = (uint16_t *)txbuffer; rxptr8 = NULL; txptr8 = NULL; } @@ -1311,8 +1311,8 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, { rxptr16 = NULL; txptr16 = NULL; - rxptr8 = (uint8_t*)rxbuffer; - txptr8 = (uint8_t*)txbuffer; + rxptr8 = (uint8_t *)rxbuffer; + txptr8 = (uint8_t *)txbuffer; } /* Make sure that any previous transfer is flushed from the hardware */ @@ -1823,7 +1823,7 @@ struct spi_dev_s *up_spiinitialize(int port) } #endif - /* Select the SPI operations */ + /* Select the SPI operations */ #if defined(CONFIG_SAM34_SPI0) && defined(CONFIG_SAM34_SPI1) spics->spidev.ops = spino ? &g_spi1ops : &g_spi0ops; diff --git a/arch/arm/src/sam34/sam_start.c b/arch/arm/src/sam34/sam_start.c index 7b754c2a32e..dc1d449808a 100644 --- a/arch/arm/src/sam34/sam_start.c +++ b/arch/arm/src/sam34/sam_start.c @@ -67,7 +67,7 @@ static inline void sam_fpuconfig(void); #endif #ifdef CONFIG_STACK_COLORATION static void go_os_start(void *pv, unsigned int nbytes) - __attribute__ ((naked,no_instrument_function,noreturn)); + __attribute__ ((naked, no_instrument_function, noreturn)); #endif #ifdef CONFIG_ARMV7M_STACKCHECK @@ -339,6 +339,6 @@ void __start(void) /* Shouldn't get here */ - for (;;); + for (; ; ); #endif } diff --git a/arch/arm/src/sam34/sam_tc.c b/arch/arm/src/sam34/sam_tc.c index 881dff0c0e7..4ab135da3c7 100644 --- a/arch/arm/src/sam34/sam_tc.c +++ b/arch/arm/src/sam34/sam_tc.c @@ -205,20 +205,20 @@ static uint32_t sam34_getreg(uint32_t addr) else { - /* Did we print "..." for the previous value? */ + /* Did we print "..." for the previous value? */ - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ - lldbg("[repeats %d more times]\n", count-3); - } + lldbg("[repeats %d more times]\n", count-3); + } - /* Save the new address, value, and count */ + /* Save the new address, value, and count */ - prevaddr = addr; - preval = val; - count = 1; + prevaddr = addr; + preval = val; + count = 1; } /* Show the register value read */ diff --git a/arch/arm/src/sam34/sam_timerisr.c b/arch/arm/src/sam34/sam_timerisr.c index 9efd73a6ada..6ebdc2ffd4c 100644 --- a/arch/arm/src/sam34/sam_timerisr.c +++ b/arch/arm/src/sam34/sam_timerisr.c @@ -171,7 +171,8 @@ void up_timer_initialize(void) /* Enable SysTick interrupts */ - putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); + putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | + NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); /* And enable the timer interrupt */ diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c index 2ff77f237ca..bc78542d178 100644 --- a/arch/arm/src/sam34/sam_udp.c +++ b/arch/arm/src/sam34/sam_udp.c @@ -3008,7 +3008,7 @@ static struct usbdev_req_s *sam_ep_allocreq(struct usbdev_ep_s *ep) static void sam_ep_freereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct sam_req_s *privreq = (struct sam_req_s*)req; + struct sam_req_s *privreq = (struct sam_req_s *)req; #ifdef CONFIG_DEBUG if (!ep || !req) diff --git a/arch/arm/src/sam34/sam_userspace.c b/arch/arm/src/sam34/sam_userspace.c index 7443e602f64..a399d84a720 100644 --- a/arch/arm/src/sam34/sam_userspace.c +++ b/arch/arm/src/sam34/sam_userspace.c @@ -87,8 +87,8 @@ void sam_userspace(void) DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && USERSPACE->us_bssstart <= USERSPACE->us_bssend); - dest = (uint8_t*)USERSPACE->us_bssstart; - end = (uint8_t*)USERSPACE->us_bssend; + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; while (dest != end) { @@ -101,9 +101,9 @@ void sam_userspace(void) USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && USERSPACE->us_datastart <= USERSPACE->us_dataend); - src = (uint8_t*)USERSPACE->us_datasource; - dest = (uint8_t*)USERSPACE->us_datastart; - end = (uint8_t*)USERSPACE->us_dataend; + src = (uint8_t *)USERSPACE->us_datasource; + dest = (uint8_t *)USERSPACE->us_datastart; + end = (uint8_t *)USERSPACE->us_dataend; while (dest != end) { diff --git a/arch/arm/src/sam34/sam_wdt.c b/arch/arm/src/sam34/sam_wdt.c index f34289af4fb..eebb503785b 100644 --- a/arch/arm/src/sam34/sam_wdt.c +++ b/arch/arm/src/sam34/sam_wdt.c @@ -207,20 +207,20 @@ static uint32_t sam34_getreg(uint32_t addr) else { - /* Did we print "..." for the previous value? */ + /* Did we print "..." for the previous value? */ - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ - lldbg("[repeats %d more times]\n", count-3); - } + lldbg("[repeats %d more times]\n", count-3); + } - /* Save the new address, value, and count */ + /* Save the new address, value, and count */ - prevaddr = addr; - preval = val; - count = 1; + prevaddr = addr; + preval = val; + count = 1; } /* Show the register value read */ diff --git a/arch/arm/src/sama5/sam_allocateheap.c b/arch/arm/src/sama5/sam_allocateheap.c index 0922556ed42..33e4fe1c6a8 100644 --- a/arch/arm/src/sama5/sam_allocateheap.c +++ b/arch/arm/src/sama5/sam_allocateheap.c @@ -259,7 +259,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) */ board_led_on(LED_HEAPALLOCATE); - *heap_start = (FAR void*)&_ebss; + *heap_start = (FAR void *)&_ebss; *heap_size = SAMA5_PRIMARY_HEAP_END - (size_t)&_ebss; #else @@ -268,7 +268,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) */ board_led_on(LED_HEAPALLOCATE); - *heap_start = (FAR void*)g_idle_topstack; + *heap_start = (FAR void *)g_idle_topstack; *heap_size = SAMA5_PRIMARY_HEAP_END - g_idle_topstack; #endif } diff --git a/arch/arm/src/sama5/sam_boot.c b/arch/arm/src/sama5/sam_boot.c index 8459bd2c130..58cae338248 100644 --- a/arch/arm/src/sama5/sam_boot.c +++ b/arch/arm/src/sama5/sam_boot.c @@ -277,9 +277,9 @@ static void sam_copyvectorblock(void) * 0xffff0000) */ - src = (uint32_t*)&_vector_start; - end = (uint32_t*)&_vector_end; - dest = (uint32_t*)SAM_VECTOR_VSRAM; + src = (uint32_t *)&_vector_start; + end = (uint32_t *)&_vector_end; + dest = (uint32_t *)SAM_VECTOR_VSRAM; while (src < end) { diff --git a/arch/arm/src/sama5/sam_can.c b/arch/arm/src/sama5/sam_can.c index 9c242e123c3..36893a1a380 100644 --- a/arch/arm/src/sama5/sam_can.c +++ b/arch/arm/src/sama5/sam_can.c @@ -397,20 +397,20 @@ static uint32_t can_getreg(FAR struct sam_can_s *priv, int offset) else { - /* Did we print "..." for the previous value? */ + /* Did we print "..." for the previous value? */ - if (priv->count > 3) - { - /* Yes.. then show how many times the value repeated */ + if (priv->count > 3) + { + /* Yes.. then show how many times the value repeated */ - lldbg("[repeats %d more times]\n", priv->count - 3); - } + lldbg("[repeats %d more times]\n", priv->count - 3); + } - /* Save the new address, value, and count */ + /* Save the new address, value, and count */ - priv->regaddr = regaddr; - priv->regval = regval; - priv->count = 1; + priv->regaddr = regaddr; + priv->regval = regval; + priv->count = 1; } /* Show the register value read */ diff --git a/arch/arm/src/sama5/sam_dbgu.c b/arch/arm/src/sama5/sam_dbgu.c index 2474cc11a87..e232d03009a 100644 --- a/arch/arm/src/sama5/sam_dbgu.c +++ b/arch/arm/src/sama5/sam_dbgu.c @@ -290,11 +290,11 @@ static int dbgu_attach(struct uart_dev_s *dev) ret = irq_attach(SAM_IRQ_DBGU, dbgu_interrupt); if (ret == OK) { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the DBGU - */ + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the DBGU + */ - up_enable_irq(SAM_IRQ_DBGU); + up_enable_irq(SAM_IRQ_DBGU); } return ret; @@ -331,7 +331,7 @@ static void dbgu_detach(struct uart_dev_s *dev) static int dbgu_interrupt(int irq, void *context) { struct uart_dev_s *dev = &g_dbgu_port; - struct dbgu_dev_s *priv = (struct dbgu_dev_s*)dev->priv; + struct dbgu_dev_s *priv = (struct dbgu_dev_s *)dev->priv; uint32_t pending; uint32_t imr; int passes; @@ -358,10 +358,10 @@ static int dbgu_interrupt(int irq, void *context) if ((pending & DBGU_INT_RXRDY) != 0) { - /* Received data ready... process incoming bytes */ + /* Received data ready... process incoming bytes */ - uart_recvchars(dev); - handled = true; + uart_recvchars(dev); + handled = true; } /* Handle outgoing, transmit bytes. XRDY: There is no character in the @@ -370,10 +370,10 @@ static int dbgu_interrupt(int irq, void *context) if ((pending & DBGU_INT_TXRDY) != 0) { - /* Transmit data register empty ... process outgoing bytes */ + /* Transmit data register empty ... process outgoing bytes */ - uart_xmitchars(dev); - handled = true; + uart_xmitchars(dev); + handled = true; } } @@ -401,15 +401,15 @@ static int dbgu_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct dbgu_dev_s *user = (struct dbgu_dev_s*)arg; - if (!user) - { - ret = -EINVAL; - } - else - { - memcpy(user, dev, sizeof(struct dbgu_dev_s)); - } + struct dbgu_dev_s *user = (struct dbgu_dev_s *)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct dbgu_dev_s)); + } } break; #endif @@ -434,7 +434,7 @@ static int dbgu_ioctl(struct file *filep, int cmd, unsigned long arg) static int dbgu_receive(struct uart_dev_s *dev, uint32_t *status) { - struct dbgu_dev_s *priv = (struct dbgu_dev_s*)dev->priv; + struct dbgu_dev_s *priv = (struct dbgu_dev_s *)dev->priv; /* Return the error information in the saved status */ diff --git a/arch/arm/src/sama5/sam_dmac.c b/arch/arm/src/sama5/sam_dmac.c index 5230ba3ff63..645ec3b0312 100644 --- a/arch/arm/src/sama5/sam_dmac.c +++ b/arch/arm/src/sama5/sam_dmac.c @@ -1895,7 +1895,7 @@ void sam_dmainitialize(struct sam_dmac_s *dmac) /* Enable the DMA controller */ - sam_putdmac(dmac,DMAC_EN_ENABLE, SAM_DMAC_EN_OFFSET); + sam_putdmac(dmac, DMAC_EN_ENABLE, SAM_DMAC_EN_OFFSET); /* Initialize semaphores */ @@ -2032,7 +2032,7 @@ DMA_HANDLE sam_dmachannel(uint8_t dmacno, uint32_t chflags) * disable register */ - sam_putdmac(dmac,DMAC_CHDR_DIS(chndx), SAM_DMAC_CHDR_OFFSET); + sam_putdmac(dmac, DMAC_CHDR_DIS(chndx), SAM_DMAC_CHDR_OFFSET); /* Set the DMA channel flags. */ diff --git a/arch/arm/src/sama5/sam_ehci.c b/arch/arm/src/sama5/sam_ehci.c index cf622bd039e..47b98cb21cd 100644 --- a/arch/arm/src/sama5/sam_ehci.c +++ b/arch/arm/src/sama5/sam_ehci.c @@ -3235,16 +3235,17 @@ static int sam_ehci_tophalf(int irq, FAR void *context) #ifdef CONFIG_SAMA5_OHCI static int sam_uhphs_interrupt(int irq, FAR void *context) { - int ohci; - int ehci; + int ohci; + int ehci; - /* Provide the interrupting event to both the EHCI and OHCI top half */ - ohci = sam_ohci_tophalf(irq, context); - ehci = sam_ehci_tophalf(irq, context); + /* Provide the interrupting event to both the EHCI and OHCI top half */ - /* Return OK only if both handlers returned OK */ + ohci = sam_ohci_tophalf(irq, context); + ehci = sam_ehci_tophalf(irq, context); - return ohci == OK ? ehci : ohci; + /* Return OK only if both handlers returned OK */ + + return ohci == OK ? ehci : ohci; } #endif @@ -3287,7 +3288,7 @@ static int sam_wait(FAR struct usbhost_connection_s *conn, */ flags = irqsave(); - for (;;) + for (; ; ) { /* Check for a change in the connection state on any root hub port */ diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c index bb4af13a93f..a6b01eb8d33 100644 --- a/arch/arm/src/sama5/sam_emaca.c +++ b/arch/arm/src/sama5/sam_emaca.c @@ -2115,7 +2115,7 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac) if (regval == 0 && sam_getreg(priv, regaddr2) == 0) { - /* Yes.. disable all address matching */ + /* Yes.. disable all address matching */ regval = sam_getreg(priv, SAM_EMAC_NCFGR); regval &= ~(EMAC_NCFGR_UNIHEN | EMAC_NCFGR_MTIHEN); @@ -2773,7 +2773,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv) /* Check AutoNegotiate complete */ timeout = 0; - for (;;) + for (; ; ) { ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr); if (ret < 0) @@ -3102,15 +3102,15 @@ static void sam_txreset(struct sam_emac_s *priv) priv->txtail = 0; for (ndx = 0; ndx < CONFIG_SAMA5_EMAC_NTXBUFFERS; ndx++) - { - bufaddr = (uint32_t)(&(txbuffer[ndx * EMAC_TX_UNITSIZE])); + { + bufaddr = (uint32_t)(&(txbuffer[ndx * EMAC_TX_UNITSIZE])); - /* Set the buffer address and mark the descriptor as in used by firmware */ + /* Set the buffer address and mark the descriptor as in used by firmware */ - physaddr = sam_physramaddr(bufaddr); - txdesc[ndx].addr = physaddr; - txdesc[ndx].status = EMACTXD_STA_USED; - } + physaddr = sam_physramaddr(bufaddr); + txdesc[ndx].addr = physaddr; + txdesc[ndx].status = EMACTXD_STA_USED; + } /* Mark the final descriptor in the list */ @@ -3164,18 +3164,18 @@ static void sam_rxreset(struct sam_emac_s *priv) priv->rxndx = 0; for (ndx = 0; ndx < CONFIG_SAMA5_EMAC_NRXBUFFERS; ndx++) - { - bufaddr = (uintptr_t)(&(rxbuffer[ndx * EMAC_RX_UNITSIZE])); - DEBUGASSERT((bufaddr & ~EMACRXD_ADDR_MASK) == 0); + { + bufaddr = (uintptr_t)(&(rxbuffer[ndx * EMAC_RX_UNITSIZE])); + DEBUGASSERT((bufaddr & ~EMACRXD_ADDR_MASK) == 0); - /* Set the buffer address and remove EMACRXD_ADDR_OWNER and - * EMACRXD_ADDR_WRAP. - */ + /* Set the buffer address and remove EMACRXD_ADDR_OWNER and + * EMACRXD_ADDR_WRAP. + */ - physaddr = sam_physramaddr(bufaddr); - rxdesc[ndx].addr = physaddr; - rxdesc[ndx].status = 0; - } + physaddr = sam_physramaddr(bufaddr); + rxdesc[ndx].addr = physaddr; + rxdesc[ndx].status = 0; + } /* Mark the final descriptor in the list */ @@ -3480,17 +3480,17 @@ int sam_emac_initialize(void) /* Initialize the driver structure */ memset(priv, 0, sizeof(struct sam_emac_s)); - priv->dev.d_ifup = sam_ifup; /* I/F up (new IP address) callback */ - priv->dev.d_ifdown = sam_ifdown; /* I/F down callback */ - priv->dev.d_txavail = sam_txavail; /* New TX data callback */ + priv->dev.d_ifup = sam_ifup; /* I/F up (new IP address) callback */ + priv->dev.d_ifdown = sam_ifdown; /* I/F down callback */ + priv->dev.d_txavail = sam_txavail; /* New TX data callback */ #ifdef CONFIG_NET_IGMP - priv->dev.d_addmac = sam_addmac; /* Add multicast MAC address */ - priv->dev.d_rmmac = sam_rmmac; /* Remove multicast MAC address */ + priv->dev.d_addmac = sam_addmac; /* Add multicast MAC address */ + priv->dev.d_rmmac = sam_rmmac; /* Remove multicast MAC address */ #endif #ifdef CONFIG_NETDEV_PHY_IOCTL - priv->dev.d_ioctl = sam_ioctl; /* Support PHY ioctl() calls */ + priv->dev.d_ioctl = sam_ioctl; /* Support PHY ioctl() calls */ #endif - priv->dev.d_private = (void*)&g_emac; /* Used to recover private state from dev */ + priv->dev.d_private = (void *)&g_emac; /* Used to recover private state from dev */ /* Create a watchdog for timing polling for and timing of transmissions */ @@ -3502,7 +3502,7 @@ int sam_emac_initialize(void) goto errout; } - priv->txtimeout = wd_create(); /* Create TX timeout timer */ + priv->txtimeout = wd_create(); /* Create TX timeout timer */ if (!priv->txtimeout) { ndbg("ERROR: Failed to create periodic poll timer\n"); diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c index a8ae8b0b495..a84f3bf2e70 100644 --- a/arch/arm/src/sama5/sam_emacb.c +++ b/arch/arm/src/sama5/sam_emacb.c @@ -1517,15 +1517,15 @@ static int sam_recvframe(struct sam_emac_s *priv) priv->rxndx = rxndx; } - /* Process the next buffer */ + /* Process the next buffer */ - rxdesc = &priv->rxdesc[rxndx]; + rxdesc = &priv->rxdesc[rxndx]; - /* Invalidate the RX descriptor to force re-fetching from RAM */ + /* Invalidate the RX descriptor to force re-fetching from RAM */ - arch_invalidate_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); - } + arch_invalidate_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); + } /* No packet was found */ @@ -1636,7 +1636,7 @@ static void sam_receive(struct sam_emac_s *priv) */ if (priv->dev.d_len > 0) - { + { /* Update the Ethernet header with the correct MAC address */ #ifdef CONFIG_NET_IPv4 @@ -2860,7 +2860,7 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac) if (regval == 0 && sam_getreg(priv, regoffset2) == 0) { - /* Yes.. disable all address matching */ + /* Yes.. disable all address matching */ regval = sam_getreg(priv, SAM_EMAC_NCFGR_OFFSET); regval &= ~(EMAC_NCFGR_UNIHEN | EMAC_NCFGR_MTIHEN); @@ -3637,7 +3637,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv) /* Check AutoNegotiate complete */ timeout = 0; - for (;;) + for (; ; ) { ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr); if (ret < 0) @@ -3998,9 +3998,9 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv) } else #endif - { - nvdbg("ERROR: emac=%d\n", priv->attr->emac); - } + { + nvdbg("ERROR: emac=%d\n", priv->attr->emac); + } } /**************************************************************************** @@ -4040,15 +4040,15 @@ static void sam_txreset(struct sam_emac_s *priv) priv->txtail = 0; for (ndx = 0; ndx < priv->attr->ntxbuffers; ndx++) - { - bufaddr = (uint32_t)(&(txbuffer[ndx * EMAC_TX_UNITSIZE])); + { + bufaddr = (uint32_t)(&(txbuffer[ndx * EMAC_TX_UNITSIZE])); - /* Set the buffer address and mark the descriptor as in used by firmware */ + /* Set the buffer address and mark the descriptor as in used by firmware */ - physaddr = sam_physramaddr(bufaddr); - txdesc[ndx].addr = physaddr; - txdesc[ndx].status = EMACTXD_STA_USED; - } + physaddr = sam_physramaddr(bufaddr); + txdesc[ndx].addr = physaddr; + txdesc[ndx].status = EMACTXD_STA_USED; + } /* Mark the final descriptor in the list */ @@ -4102,18 +4102,18 @@ static void sam_rxreset(struct sam_emac_s *priv) priv->rxndx = 0; for (ndx = 0; ndx < priv->attr->nrxbuffers; ndx++) - { - bufaddr = (uintptr_t)(&(rxbuffer[ndx * EMAC_RX_UNITSIZE])); - DEBUGASSERT((bufaddr & ~EMACRXD_ADDR_MASK) == 0); + { + bufaddr = (uintptr_t)(&(rxbuffer[ndx * EMAC_RX_UNITSIZE])); + DEBUGASSERT((bufaddr & ~EMACRXD_ADDR_MASK) == 0); - /* Set the buffer address and remove EMACRXD_ADDR_OWNER and - * EMACRXD_ADDR_WRAP. - */ + /* Set the buffer address and remove EMACRXD_ADDR_OWNER and + * EMACRXD_ADDR_WRAP. + */ - physaddr = sam_physramaddr(bufaddr); - rxdesc[ndx].addr = physaddr; - rxdesc[ndx].status = 0; - } + physaddr = sam_physramaddr(bufaddr); + rxdesc[ndx].addr = physaddr; + rxdesc[ndx].status = 0; + } /* Mark the final descriptor in the list */ diff --git a/arch/arm/src/sama5/sam_flexcom_serial.c b/arch/arm/src/sama5/sam_flexcom_serial.c index 97d11e0dbff..d377fdae56d 100644 --- a/arch/arm/src/sama5/sam_flexcom_serial.c +++ b/arch/arm/src/sama5/sam_flexcom_serial.c @@ -558,7 +558,7 @@ static int flexus_interrupt(struct uart_dev_s *dev) bool handled; DEBUGASSERT(dev != NULL && dev->priv != NULL); - priv = (struct flexus_dev_s*)dev->priv; + priv = (struct flexus_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, until we have * been looping for a long time. @@ -581,10 +581,10 @@ static int flexus_interrupt(struct uart_dev_s *dev) if ((pending & FLEXUS_INT_RXRDY) != 0) { - /* Received data ready... process incoming bytes */ + /* Received data ready... process incoming bytes */ - uart_recvchars(dev); - handled = true; + uart_recvchars(dev); + handled = true; } /* Handle outgoing, transmit bytes. XRDY: There is no character in the @@ -593,10 +593,10 @@ static int flexus_interrupt(struct uart_dev_s *dev) if ((pending & FLEXUS_INT_TXRDY) != 0) { - /* Transmit data register empty ... process outgoing bytes */ + /* Transmit data register empty ... process outgoing bytes */ - uart_xmitchars(dev); - handled = true; + uart_xmitchars(dev); + handled = true; } } @@ -655,7 +655,7 @@ static int flexus4_interrupt(int irq, void *context) static int flexus_setup(struct uart_dev_s *dev) { - struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + struct flexus_dev_s *priv = (struct flexus_dev_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t regval; @@ -768,7 +768,7 @@ static int flexus_setup(struct uart_dev_s *dev) static void flexus_shutdown(struct uart_dev_s *dev) { - struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + struct flexus_dev_s *priv = (struct flexus_dev_s *)dev->priv; /* Reset and disable receiver and transmitter */ @@ -798,7 +798,7 @@ static void flexus_shutdown(struct uart_dev_s *dev) static int flexus_attach(struct uart_dev_s *dev) { - struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + struct flexus_dev_s *priv = (struct flexus_dev_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -806,11 +806,11 @@ static int flexus_attach(struct uart_dev_s *dev) ret = irq_attach(priv->irq, priv->handler); if (ret == OK) { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the USART - */ + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the USART + */ - up_enable_irq(priv->irq); + up_enable_irq(priv->irq); } return ret; @@ -828,7 +828,7 @@ static int flexus_attach(struct uart_dev_s *dev) static void flexus_detach(struct uart_dev_s *dev) { - struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + struct flexus_dev_s *priv = (struct flexus_dev_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -854,7 +854,7 @@ static int flexus_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct flexus_dev_s *user = (struct flexus_dev_s*)arg; + struct flexus_dev_s *user = (struct flexus_dev_s *)arg; if (!user) { ret = -EINVAL; @@ -870,8 +870,8 @@ static int flexus_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_TERMIOS case TCGETS: { - struct termios *termiosp = (struct termios*)arg; - struct flexus_dev_s *priv = (struct flexus_dev_s *)dev->priv; + struct termios *termiosp = (struct termios *)arg; + struct flexus_dev_s *priv = (struct flexus_dev_s *)dev->priv; if (!termiosp) { @@ -927,8 +927,8 @@ static int flexus_ioctl(struct file *filep, int cmd, unsigned long arg) case TCSETS: { - struct termios *termiosp = (struct termios*)arg; - struct flexus_dev_s *priv = (struct flexus_dev_s *)dev->priv; + struct termios *termiosp = (struct termios *)arg; + struct flexus_dev_s *priv = (struct flexus_dev_s *)dev->priv; uint32_t baud; uint32_t imr; uint8_t parity; @@ -1046,7 +1046,7 @@ static int flexus_ioctl(struct file *filep, int cmd, unsigned long arg) static int flexus_receive(struct uart_dev_s *dev, uint32_t *status) { - struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + struct flexus_dev_s *priv = (struct flexus_dev_s *)dev->priv; /* Return the error information in the saved status */ @@ -1068,7 +1068,7 @@ static int flexus_receive(struct uart_dev_s *dev, uint32_t *status) static void flexus_rxint(struct uart_dev_s *dev, bool enable) { - struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + struct flexus_dev_s *priv = (struct flexus_dev_s *)dev->priv; if (enable) { @@ -1096,7 +1096,7 @@ static void flexus_rxint(struct uart_dev_s *dev, bool enable) static bool flexus_rxavailable(struct uart_dev_s *dev) { - struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + struct flexus_dev_s *priv = (struct flexus_dev_s *)dev->priv; return ((flexus_serialin(priv, SAM_FLEXUS_CSR_OFFSET) & FLEXUS_INT_RXRDY) != 0); } @@ -1110,7 +1110,7 @@ static bool flexus_rxavailable(struct uart_dev_s *dev) static void flexus_send(struct uart_dev_s *dev, int ch) { - struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + struct flexus_dev_s *priv = (struct flexus_dev_s *)dev->priv; flexus_serialout(priv, SAM_FLEXUS_THR_OFFSET, (uint32_t)ch); } @@ -1124,7 +1124,7 @@ static void flexus_send(struct uart_dev_s *dev, int ch) static void flexus_txint(struct uart_dev_s *dev, bool enable) { - struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + struct flexus_dev_s *priv = (struct flexus_dev_s *)dev->priv; irqstate_t flags; flags = irqsave(); @@ -1165,7 +1165,7 @@ static void flexus_txint(struct uart_dev_s *dev, bool enable) static bool flexus_txready(struct uart_dev_s *dev) { - struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + struct flexus_dev_s *priv = (struct flexus_dev_s *)dev->priv; return ((flexus_serialin(priv, SAM_FLEXUS_CSR_OFFSET) & FLEXUS_INT_TXRDY) != 0); } @@ -1179,7 +1179,7 @@ static bool flexus_txready(struct uart_dev_s *dev) static bool flexus_txempty(struct uart_dev_s *dev) { - struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + struct flexus_dev_s *priv = (struct flexus_dev_s *)dev->priv; return ((flexus_serialin(priv, SAM_FLEXUS_CSR_OFFSET) & FLEXUS_INT_TXEMPTY) != 0); } diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c index ce6eaeb69be..0313f5b6bbe 100644 --- a/arch/arm/src/sama5/sam_gmac.c +++ b/arch/arm/src/sama5/sam_gmac.c @@ -1093,7 +1093,7 @@ static int sam_recvframe(struct sam_gmac_s *priv) arch_invalidate_dcache((uintptr_t)rxdesc, (uintptr_t)rxdesc + sizeof(struct gmac_rxdesc_s)); - } + } /* No packet was found */ @@ -1204,7 +1204,7 @@ static void sam_receive(struct sam_gmac_s *priv) */ if (priv->dev.d_len > 0) - { + { /* Update the Ethernet header with the correct MAC address */ #ifdef CONFIG_NET_IPv4 @@ -1685,9 +1685,9 @@ static int sam_ifup(struct net_driver_s *dev) return ret; } #else - /* Just force the configured link speed */ + /* Just force the configured link speed */ - sam_linkspeed(priv); + sam_linkspeed(priv); #endif /* Enable normal MAC operation */ @@ -2070,7 +2070,7 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac) if (regval == 0 && sam_getreg(priv, regaddr2) == 0) { - /* Yes.. disable all address matching */ + /* Yes.. disable all address matching */ regval = sam_getreg(priv, SAM_GMAC_NCFGR); regval &= ~(GMAC_NCFGR_UNIHEN | GMAC_NCFGR_MTIHEN); @@ -2778,7 +2778,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv) /* Wait for autonegotion to complete */ timeout = 0; - for (;;) + for (; ; ) { ret = sam_phyread(priv, priv->phyaddr, GMII_MSR, &phyval); if (ret < 0) @@ -2813,7 +2813,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv) linkmode = 0; /* 10Base-T Half-Duplex */ timeout = 0; - for (;;) + for (; ; ) { ret = sam_phyread(priv, priv->phyaddr, GMII_1000BTSR, &btsr); if (ret < 0) @@ -3212,18 +3212,18 @@ static void sam_rxreset(struct sam_gmac_s *priv) priv->rxndx = 0; for (ndx = 0; ndx < CONFIG_SAMA5_GMAC_NRXBUFFERS; ndx++) - { - bufaddr = (uintptr_t)(&(rxbuffer[ndx * GMAC_RX_UNITSIZE])); - DEBUGASSERT((bufaddr & ~GMACRXD_ADDR_MASK) == 0); + { + bufaddr = (uintptr_t)(&(rxbuffer[ndx * GMAC_RX_UNITSIZE])); + DEBUGASSERT((bufaddr & ~GMACRXD_ADDR_MASK) == 0); - /* Set the buffer address and remove GMACRXD_ADDR_OWNER and - * GMACRXD_ADDR_WRAP. - */ + /* Set the buffer address and remove GMACRXD_ADDR_OWNER and + * GMACRXD_ADDR_WRAP. + */ - physaddr = sam_physramaddr(bufaddr); - rxdesc[ndx].addr = physaddr; - rxdesc[ndx].status = 0; - } + physaddr = sam_physramaddr(bufaddr); + rxdesc[ndx].addr = physaddr; + rxdesc[ndx].status = 0; + } /* Mark the final descriptor in the list */ @@ -3552,17 +3552,17 @@ int sam_gmac_initialize(void) /* Initialize the driver structure */ memset(priv, 0, sizeof(struct sam_gmac_s)); - priv->dev.d_ifup = sam_ifup; /* I/F up (new IP address) callback */ - priv->dev.d_ifdown = sam_ifdown; /* I/F down callback */ - priv->dev.d_txavail = sam_txavail; /* New TX data callback */ + priv->dev.d_ifup = sam_ifup; /* I/F up (new IP address) callback */ + priv->dev.d_ifdown = sam_ifdown; /* I/F down callback */ + priv->dev.d_txavail = sam_txavail; /* New TX data callback */ #ifdef CONFIG_NET_IGMP - priv->dev.d_addmac = sam_addmac; /* Add multicast MAC address */ - priv->dev.d_rmmac = sam_rmmac; /* Remove multicast MAC address */ + priv->dev.d_addmac = sam_addmac; /* Add multicast MAC address */ + priv->dev.d_rmmac = sam_rmmac; /* Remove multicast MAC address */ #endif #ifdef CONFIG_NETDEV_PHY_IOCTL - priv->dev.d_ioctl = sam_ioctl; /* Support PHY ioctl() calls */ + priv->dev.d_ioctl = sam_ioctl; /* Support PHY ioctl() calls */ #endif - priv->dev.d_private = (void*)&g_gmac; /* Used to recover private state from dev */ + priv->dev.d_private = (void *)&g_gmac; /* Used to recover private state from dev */ /* Create a watchdog for timing polling for and timing of transmisstions */ @@ -3574,7 +3574,7 @@ int sam_gmac_initialize(void) goto errout; } - priv->txtimeout = wd_create(); /* Create TX timeout timer */ + priv->txtimeout = wd_create(); /* Create TX timeout timer */ if (!priv->txtimeout) { nlldbg("ERROR: Failed to create periodic poll timer\n"); diff --git a/arch/arm/src/sama5/sam_hsmci.c b/arch/arm/src/sama5/sam_hsmci.c index d90176cb8a7..84a654f1516 100644 --- a/arch/arm/src/sama5/sam_hsmci.c +++ b/arch/arm/src/sama5/sam_hsmci.c @@ -1509,7 +1509,7 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv) /* Loop while there are pending interrupts. */ - for (;;) + for (; ; ) { /* Check the HSMCI status register. Mask out all bits that don't * correspond to enabled interrupts. (This depends on the fact that @@ -1634,9 +1634,9 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv) wkupevent = SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE; } - /* Yes.. Is there a thread waiting for this event set? */ + /* Yes.. Is there a thread waiting for this event set? */ - wkupevent &= priv->waitevents; + wkupevent &= priv->waitevents; if (wkupevent != 0) { /* Yes.. wake the thread up */ @@ -1849,10 +1849,10 @@ static void sam_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) regval = sam_getreg(priv, SAM_HSMCI_MR_OFFSET); regval &= ~(HSMCI_MR_CLKDIV_MASK | HSMCI_MR_PWSDIV_MASK | HSMCI_MR_CLKODD); - /* These clock devisor values that must be defined in the board-specific - * board.h header file: HSMCI_INIT_CLKDIV, HSMCI_MMCXFR_CLKDIV, - * HSMCI_SDXFR_CLKDIV, and HSMCI_SDWIDEXFR_CLKDIV. - */ + /* These clock devisor values that must be defined in the board-specific + * board.h header file: HSMCI_INIT_CLKDIV, HSMCI_MMCXFR_CLKDIV, + * HSMCI_SDXFR_CLKDIV, and HSMCI_SDWIDEXFR_CLKDIV. + */ switch (rate) { @@ -1988,13 +1988,13 @@ static int sam_attach(FAR struct sdio_dev_s *dev) static int sam_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; uint32_t regval; uint32_t cmdidx; sam_cmdsampleinit(priv); - /* Set the HSMCI Argument value */ + /* Set the HSMCI Argument value */ sam_putreg(priv, arg, SAM_HSMCI_ARGR_OFFSET); @@ -2182,7 +2182,7 @@ static int sam_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, /* Save the destination buffer information for use by the interrupt handler */ - priv->buffer = (uint32_t*)buffer; + priv->buffer = (uint32_t *)buffer; priv->remaining = buflen; /* And enable interrupts */ @@ -2287,7 +2287,7 @@ static int sam_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, static int sam_cancel(FAR struct sdio_dev_s *dev) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; /* Disable all transfer- and event- related interrupts */ @@ -2340,7 +2340,7 @@ static int sam_cancel(FAR struct sdio_dev_s *dev) static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; uint32_t sr; uint32_t pending; int32_t timeout; @@ -2370,7 +2370,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) /* Then wait for the response (or timeout) */ - for (;;) + for (; ; ) { /* Did a Command-Response sequence termination evernt occur? */ @@ -2452,7 +2452,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) static int sam_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; int ret = OK; /* These responses could have CRC errors: @@ -2538,17 +2538,17 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev, static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong[4]) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; int ret = OK; - /* R2 CID, CSD register (136-bit) - * 135 0 Start bit - * 134 0 Transmission bit (0=from card) - * 133:128 bit5 - bit0 Reserved - * 127:1 bit127 - bit1 127-bit CID or CSD register - * (including internal CRC) - * 0 1 End bit - */ + /* R2 CID, CSD register (136-bit) + * 135 0 Start bit + * 134 0 Transmission bit (0=from card) + * 133:128 bit5 - bit0 Reserved + * 127:1 bit127 - bit1 127-bit CID or CSD register + * (including internal CRC) + * 0 1 End bit + */ #ifdef CONFIG_DEBUG /* Check that R1 is the correct response to this command */ @@ -2594,7 +2594,7 @@ static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong static int sam_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rnotimpl) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; priv->wkupevent = 0; return -ENOSYS; } @@ -2637,7 +2637,7 @@ static int sam_recvnotimpl(FAR struct sdio_dev_s *dev, static void sam_waitenable(FAR struct sdio_dev_s *dev, sdio_eventset_t eventset) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; uint32_t waitmask; DEBUGASSERT(priv != NULL); @@ -2696,7 +2696,7 @@ static void sam_waitenable(FAR struct sdio_dev_s *dev, static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev, uint32_t timeout) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; sdio_eventset_t wkupevent = 0; int ret; @@ -2756,7 +2756,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev, * may have already occurred before this function was called! */ - for (;;) + for (; ; ) { /* Wait for an event in event set to occur. If this the event has already * occurred, then the semaphore will already have been incremented and @@ -2810,7 +2810,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev, static void sam_callbackenable(FAR struct sdio_dev_s *dev, sdio_eventset_t eventset) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; fvdbg("eventset: %02x\n", eventset); DEBUGASSERT(priv != NULL); @@ -2844,7 +2844,7 @@ static void sam_callbackenable(FAR struct sdio_dev_s *dev, static int sam_registercallback(FAR struct sdio_dev_s *dev, worker_t callback, void *arg) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; /* Disable callbacks and register this callback and is argument */ @@ -2949,7 +2949,7 @@ static int sam_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, paddr += sizeof(uint32_t); maddr += blocksize; - } + } /* Enable DMA handshaking */ @@ -3045,7 +3045,7 @@ static int sam_dmasendsetup(FAR struct sdio_dev_s *dev, paddr += sizeof(uint32_t); maddr += blocksize; - } + } /* Enable DMA handshaking */ @@ -3088,7 +3088,7 @@ static int sam_dmasendsetup(FAR struct sdio_dev_s *dev, static void sam_callback(void *arg) { - struct sam_dev_s *priv = (struct sam_dev_s*)arg; + struct sam_dev_s *priv = (struct sam_dev_s *)arg; irqstate_t flags; int ret; @@ -3108,8 +3108,8 @@ static void sam_callback(void *arg) /* Media is present. Is the media inserted event enabled? */ if ((priv->cbevents & SDIOMEDIA_INSERTED) == 0) - { - /* No... return without performing the callback */ + { + /* No... return without performing the callback */ return; } @@ -3135,7 +3135,7 @@ static void sam_callback(void *arg) /* This function is called either from (1) the context of the calling * thread or from the the context of (2) card detection logic. The * caller may or may not have interrupts disabled (we have them - & disabled here!). + * disabled here!). * * So to minimize the possibility of recursive behavior and to assure * that callback is always performed outside of the interrupt handling diff --git a/arch/arm/src/sama5/sam_lcd.c b/arch/arm/src/sama5/sam_lcd.c index 9ea92e0451b..c41d880d546 100644 --- a/arch/arm/src/sama5/sam_lcd.c +++ b/arch/arm/src/sama5/sam_lcd.c @@ -1409,7 +1409,7 @@ static int sam_setclut(struct sam_layer_s *layer, end = offset + len; if (end > (layer->offset + layer->nclut)) { - layer->nclut = end - layer->offset;offset + layer->nclut = end - layer->offset; } /* Get the offset address to the first CLUT entry to modify */ @@ -3041,7 +3041,7 @@ void fb_uninitialize(void) void sam_lcdclear(nxgl_mxpixel_t color) { #if SAMA5_LCDC_BASE_BPP == 16 - uint16_t *dest = (uint16_t*)LAYER_BASE.framebuffer; + uint16_t *dest = (uint16_t *)LAYER_BASE.framebuffer; int i; gvdbg("Clearing display: BPP=16 color=%04x framebuffer=%08x size=%d\n", @@ -3052,7 +3052,7 @@ void sam_lcdclear(nxgl_mxpixel_t color) *dest++ = (uint16_t)color; } #elif SAMA5_LCDC_BASE_BPP == 24 - uint8_t *dest = (uint8_t*)LAYER_BASE.framebuffer; + uint8_t *dest = (uint8_t *)LAYER_BASE.framebuffer; uint8_t r; uint8_t g; uint8_t b; @@ -3072,7 +3072,7 @@ void sam_lcdclear(nxgl_mxpixel_t color) *dest++ = r; } #elif SAMA5_LCDC_BASE_BPP == 32 - uint32_t *dest = (uint32_t*)LAYER_BASE.framebuffer; + uint32_t *dest = (uint32_t *)LAYER_BASE.framebuffer; int i; gvdbg("Clearing display: BPP=32 color=%08x framebuffer=%08x size=%d\n", diff --git a/arch/arm/src/sama5/sam_lowputc.c b/arch/arm/src/sama5/sam_lowputc.c index e169ce59e12..c0413c259f5 100644 --- a/arch/arm/src/sama5/sam_lowputc.c +++ b/arch/arm/src/sama5/sam_lowputc.c @@ -241,7 +241,7 @@ void up_lowputc(char ch) #if defined(SAMA5_HAVE_UART_CONSOLE) || defined(SAMA5_HAVE_USART_CONSOLE) irqstate_t flags; - for (;;) + for (; ; ) { /* Wait for the transmitter to be available */ @@ -269,7 +269,7 @@ void up_lowputc(char ch) #elif defined(SAMA5_HAVE_FLEXCOM_CONSOLE) irqstate_t flags; - for (;;) + for (; ; ) { /* Wait for the transmitter to be available */ @@ -297,7 +297,7 @@ void up_lowputc(char ch) #elif defined(CONFIG_SAMA5_DBGU_CONSOLE) irqstate_t flags; - for (;;) + for (; ; ) { /* Wait for the transmitter to be available */ diff --git a/arch/arm/src/sama5/sam_nand.c b/arch/arm/src/sama5/sam_nand.c index c6d5e8e1d38..3a5e90afc7b 100644 --- a/arch/arm/src/sama5/sam_nand.c +++ b/arch/arm/src/sama5/sam_nand.c @@ -1098,11 +1098,11 @@ static int hsmc_interrupt(int irq, void *context) nand_putreg(SAM_HSMC_IDR, HSMC_NFCINT_CMDDONE); } - /* If set to one, the RBEDGE0 flag indicates that an edge has been detected - * on the Ready/Busy Line x. Depending on the EDGE CTRL field located in the - * SMC_CFG register, only rising or falling edge is detected. This flag is - * reset after the status read. - */ + /* If set to one, the RBEDGE0 flag indicates that an edge has been detected + * on the Ready/Busy Line x. Depending on the EDGE CTRL field located in the + * SMC_CFG register, only rising or falling edge is detected. This flag is + * reset after the status read. + */ if (g_nand.rbedge && (imr & HSMC_NFCINT_RBEDGE0) != 0) { @@ -2267,7 +2267,7 @@ static int nand_writepage_noecc(struct sam_nandcs_s *priv, off_t block, { nand_nfc_cleale(priv, HSMC_CLE_WRITE_EN | HSMC_ALE_COL_EN | HSMC_ALE_ROW_EN, - COMMAND_WRITE_1,0, pagesize, rowaddr); + COMMAND_WRITE_1, 0, pagesize, rowaddr); ret = nand_write(priv, (uint8_t *)spare, sparesize, 0); if (ret < 0) diff --git a/arch/arm/src/sama5/sam_ohci.c b/arch/arm/src/sama5/sam_ohci.c index acb5492519d..986a29f8912 100644 --- a/arch/arm/src/sama5/sam_ohci.c +++ b/arch/arm/src/sama5/sam_ohci.c @@ -704,7 +704,7 @@ static struct sam_ed_s *sam_edalloc(void) ed = (struct sam_ed_s *)g_edfree; if (ed) { - g_edfree = ((struct sam_list_s*)ed)->flink; + g_edfree = ((struct sam_list_s *)ed)->flink; } return ed; @@ -755,7 +755,7 @@ static struct sam_gtd_s *sam_tdalloc(void) ret = (struct sam_gtd_s *)g_tdfree; if (ret) { - g_tdfree = ((struct sam_list_s*)ret)->flink; + g_tdfree = ((struct sam_list_s *)ret)->flink; } irqrestore(flags); @@ -800,7 +800,7 @@ static uint8_t *sam_tballoc(void) uint8_t *ret = (uint8_t *)g_tbfree; if (ret) { - g_tbfree = ((struct sam_list_s*)ret)->flink; + g_tbfree = ((struct sam_list_s *)ret)->flink; } return ret; @@ -2025,10 +2025,10 @@ static void sam_rhsc_bottomhalf(void) rhport->connected = false; - /* Set the port speed to the default (FULL). We cannot - * yet free the function address. That has to be done - * by the class when responds to the disconnection. - */ + /* Set the port speed to the default (FULL). We cannot + * yet free the function address. That has to be done + * by the class when responds to the disconnection. + */ rhport->hport.hport.speed = USB_SPEED_FULL; @@ -2341,7 +2341,7 @@ static int sam_wait(struct usbhost_connection_s *conn, */ flags = irqsave(); - for (;;) + for (; ; ) { /* Check for a change in the connection state on any root hub port */ @@ -2697,7 +2697,7 @@ static int sam_epalloc(struct usbhost_driver_s *drvr, /* Configure the endpoint descriptor. */ - memset((void*)ed, 0, sizeof(struct sam_ed_s)); + memset((void *)ed, 0, sizeof(struct sam_ed_s)); ed->hw.ctrl = (uint32_t)(hport->funcaddr) << ED_CONTROL_FA_SHIFT | (uint32_t)(epdesc->addr) << ED_CONTROL_EN_SHIFT | @@ -3114,7 +3114,7 @@ static int sam_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, sam_takesem(&g_ohci.exclsem); len = sam_getle16(req->len); - ret = sam_ctrltd(rhport, eplist, GTD_STATUS_DP_SETUP, (uint8_t*)req, + ret = sam_ctrltd(rhport, eplist, GTD_STATUS_DP_SETUP, (uint8_t *)req, USB_SIZEOF_CTRLREQ); if (ret == OK) { @@ -3163,14 +3163,14 @@ static int sam_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, sam_takesem(&g_ohci.exclsem); len = sam_getle16(req->len); - ret = sam_ctrltd(rhport, eplist, GTD_STATUS_DP_SETUP, (uint8_t*)req, + ret = sam_ctrltd(rhport, eplist, GTD_STATUS_DP_SETUP, (uint8_t *)req, USB_SIZEOF_CTRLREQ); if (ret == OK) { if (len) { ret = sam_ctrltd(rhport, eplist, GTD_STATUS_DP_OUT, - (uint8_t*)buffer, len); + (uint8_t *)buffer, len); } if (ret == OK) @@ -3193,7 +3193,7 @@ static int sam_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, * Input Parameters: * rhport - Internal driver root hub port state structure. * eplist - The internal representation of the device endpoint on which - * to perform the transfer. + * to perform the transfer. * buffer - A buffer containing the data to be sent (OUT endpoint) or received * (IN endpoint). buffer must have been allocated using DRVR_ALLOC * buflen - The length of the data to be sent or received. @@ -3973,7 +3973,7 @@ struct usbhost_connection_s *sam_ohci_initialize(int controller) /* Initialize all the HCCA to 0 */ - memset((void*)&g_hcca, 0, sizeof(struct ohci_hcca_s)); + memset((void *)&g_hcca, 0, sizeof(struct ohci_hcca_s)); arch_clean_dcache((uint32_t)&g_hcca, (uint32_t)&g_hcca + sizeof(struct ohci_hcca_s)); diff --git a/arch/arm/src/sama5/sam_pioirq.c b/arch/arm/src/sama5/sam_pioirq.c index de4eec38ad1..2d9950168ed 100644 --- a/arch/arm/src/sama5/sam_pioirq.c +++ b/arch/arm/src/sama5/sam_pioirq.c @@ -406,57 +406,57 @@ void sam_pioirq(pio_pinset_t pinset) regval = getreg32(base + SAM_PIO_ISLR_OFFSET); if ((pinset & PIO_INT_SECURE) != 0) - { - /* Yes.. make sure that the corresponding bit in ISLR is cleared */ + { + /* Yes.. make sure that the corresponding bit in ISLR is cleared */ - regval &= ~pin; - } - else - { - /* Yes.. make sure that the corresponding bit in ISLR is set */ + regval &= ~pin; + } + else + { + /* Yes.. make sure that the corresponding bit in ISLR is set */ - regval |= pin; - } + regval |= pin; + } - putreg32(regval, base + SAM_PIO_ISLR_OFFSET); + putreg32(regval, base + SAM_PIO_ISLR_OFFSET); #endif - /* Are any additional interrupt modes selected? */ + /* Are any additional interrupt modes selected? */ - if ((pinset & _PIO_INT_AIM) != 0) - { - /* Yes.. Enable additional interrupt mode */ + if ((pinset & _PIO_INT_AIM) != 0) + { + /* Yes.. Enable additional interrupt mode */ - putreg32(pin, base + SAM_PIO_AIMER_OFFSET); + putreg32(pin, base + SAM_PIO_AIMER_OFFSET); - /* Level or edge detected interrupt? */ + /* Level or edge detected interrupt? */ - if ((pinset & _PIO_INT_LEVEL) != 0) - { - putreg32(pin, base + SAM_PIO_LSR_OFFSET); /* Level */ - } - else - { - putreg32(pin, base + SAM_PIO_ESR_OFFSET); /* Edge */ - } + if ((pinset & _PIO_INT_LEVEL) != 0) + { + putreg32(pin, base + SAM_PIO_LSR_OFFSET); /* Level */ + } + else + { + putreg32(pin, base + SAM_PIO_ESR_OFFSET); /* Edge */ + } /* High level/rising edge or low level /falling edge? */ - if ((pinset & _PIO_INT_RH) != 0) - { - putreg32(pin, base + SAM_PIO_REHLSR_OFFSET); /* High level/Rising edge */ - } - else - { - putreg32(pin, base + SAM_PIO_FELLSR_OFFSET); /* Low level/Falling edge */ - } - } - else - { - /* No.. Disable additional interrupt mode */ + if ((pinset & _PIO_INT_RH) != 0) + { + putreg32(pin, base + SAM_PIO_REHLSR_OFFSET); /* High level/Rising edge */ + } + else + { + putreg32(pin, base + SAM_PIO_FELLSR_OFFSET); /* Low level/Falling edge */ + } + } + else + { + /* No.. Disable additional interrupt mode */ - putreg32(pin, base + SAM_PIO_AIMDR_OFFSET); - } + putreg32(pin, base + SAM_PIO_AIMDR_OFFSET); + } #if defined(SAM_PIO_ISLR_OFFSET) /* Disable writing to PIO registers */ @@ -480,10 +480,10 @@ void sam_pioirqenable(int irq) if (sam_irqbase(irq, &base, &pin) == OK) { - /* Clear (all) pending interrupts and enable this pin interrupt */ + /* Clear (all) pending interrupts and enable this pin interrupt */ - //(void)getreg32(base + SAM_PIO_ISR_OFFSET); - putreg32((1 << pin), base + SAM_PIO_IER_OFFSET); + //(void)getreg32(base + SAM_PIO_ISR_OFFSET); + putreg32((1 << pin), base + SAM_PIO_IER_OFFSET); } } @@ -502,9 +502,9 @@ void sam_pioirqdisable(int irq) if (sam_irqbase(irq, &base, &pin) == OK) { - /* Disable this pin interrupt */ + /* Disable this pin interrupt */ - putreg32((1 << pin), base + SAM_PIO_IDR_OFFSET); + putreg32((1 << pin), base + SAM_PIO_IDR_OFFSET); } } diff --git a/arch/arm/src/sama5/sam_pmecc.c b/arch/arm/src/sama5/sam_pmecc.c index b1f24333ab9..8dfee40e3a6 100644 --- a/arch/arm/src/sama5/sam_pmecc.c +++ b/arch/arm/src/sama5/sam_pmecc.c @@ -493,11 +493,11 @@ static uint32_t pmecc_getsigma(void) /* Check if one operand of the multiplier is null, its index is -1 */ - else if (g_pmecc.desc.smu[i+1][k] && si[ 2 * (i - 1) + 3 - k]) + else if (g_pmecc.desc.smu[i + 1][k] && si[2 * (i - 1) + 3 - k]) { dmu[i + 1] = - g_pmecc.desc.alphato[(g_pmecc.desc.indexof[g_pmecc.desc.smu[ i + 1 ][ k ]] + - g_pmecc.desc.indexof[si[ 2 * (i - 1) + 3 - k]]) % g_pmecc.desc.nn] ^ dmu[ i + 1]; + g_pmecc.desc.alphato[(g_pmecc.desc.indexof[g_pmecc.desc.smu[i + 1][k]] + + g_pmecc.desc.indexof[si[2 * (i - 1) + 3 - k]]) % g_pmecc.desc.nn] ^ dmu[i + 1]; } } } @@ -635,24 +635,24 @@ static uint32_t pmecc_errorcorrection(uintptr_t sectorbase, fdbg("Correct error bit @[Byte %d, Bit %d]\n", (int)bytepos, (int)bitpos); - if (*(uint8_t*)(sectorbase + bytepos) & (1 << bitpos)) + if (*(uint8_t *)(sectorbase + bytepos) & (1 << bitpos)) { - *(uint8_t*)(sectorbase + bytepos) &= (0xff ^ (1 << bitpos)); + *(uint8_t *)(sectorbase + bytepos) &= (0xff ^ (1 << bitpos)); } else { - *(uint8_t*)(sectorbase + bytepos) |= (1 << bitpos); + *(uint8_t *)(sectorbase + bytepos) |= (1 << bitpos); } } else { - if (*(uint8_t*)(sectorbase + bytepos + eccsize) & (1 << bitpos)) + if (*(uint8_t *)(sectorbase + bytepos + eccsize) & (1 << bitpos)) { - *(uint8_t*)(sectorbase + bytepos + eccsize) &= (0xff ^ (1 << bitpos)); + *(uint8_t *)(sectorbase + bytepos + eccsize) &= (0xff ^ (1 << bitpos)); } else { - *(uint8_t*)(sectorbase + bytepos + eccsize) |= (1 << bitpos); + *(uint8_t *)(sectorbase + bytepos + eccsize) |= (1 << bitpos); } } } @@ -1442,8 +1442,8 @@ void pmecc_buildgf(uint32_t mm, int16_t *indexof, int16_t *alphato) /* Second * * Build elements from 0 to mm - 1. Very easy because degree is less than - * mm so it is just a logical shift ! (only the remainder) - */ + * mm so it is just a logical shift ! (only the remainder) + */ mask = 1; for (i = 0; i < mm; i++) diff --git a/arch/arm/src/sama5/sam_serial.c b/arch/arm/src/sama5/sam_serial.c index f007e69810e..fb384e0a291 100644 --- a/arch/arm/src/sama5/sam_serial.c +++ b/arch/arm/src/sama5/sam_serial.c @@ -998,7 +998,7 @@ static int up_interrupt(struct uart_dev_s *dev) bool handled; DEBUGASSERT(dev != NULL && dev->priv != NULL); - priv = (struct up_dev_s*)dev->priv; + priv = (struct up_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, until we have * been looping for a long time. @@ -1021,10 +1021,10 @@ static int up_interrupt(struct uart_dev_s *dev) if ((pending & UART_INT_RXRDY) != 0) { - /* Received data ready... process incoming bytes */ + /* Received data ready... process incoming bytes */ - uart_recvchars(dev); - handled = true; + uart_recvchars(dev); + handled = true; } /* Handle outgoing, transmit bytes. XRDY: There is no character in the @@ -1033,10 +1033,10 @@ static int up_interrupt(struct uart_dev_s *dev) if ((pending & UART_INT_TXRDY) != 0) { - /* Transmit data register empty ... process outgoing bytes */ + /* Transmit data register empty ... process outgoing bytes */ - uart_xmitchars(dev); - handled = true; + uart_xmitchars(dev); + handled = true; } } @@ -1115,7 +1115,7 @@ static int up_usart4_interrupt(int irq, void *context) static int up_setup(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t regval; @@ -1259,7 +1259,7 @@ static int up_setup(struct uart_dev_s *dev) static void up_shutdown(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Reset and disable receiver and transmitter */ @@ -1289,7 +1289,7 @@ static void up_shutdown(struct uart_dev_s *dev) static int up_attach(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -1297,11 +1297,11 @@ static int up_attach(struct uart_dev_s *dev) ret = irq_attach(priv->irq, priv->handler); if (ret == OK) { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the USART - */ + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the USART + */ - up_enable_irq(priv->irq); + up_enable_irq(priv->irq); } return ret; @@ -1319,7 +1319,7 @@ static int up_attach(struct uart_dev_s *dev) static void up_detach(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -1345,7 +1345,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct up_dev_s *user = (struct up_dev_s*)arg; + struct up_dev_s *user = (struct up_dev_s *)arg; if (!user) { ret = -EINVAL; @@ -1361,7 +1361,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_TERMIOS case TCGETS: { - struct termios *termiosp = (struct termios*)arg; + struct termios *termiosp = (struct termios *)arg; struct up_dev_s *priv = (struct up_dev_s *)dev->priv; if (!termiosp) @@ -1418,7 +1418,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) case TCSETS: { - struct termios *termiosp = (struct termios*)arg; + struct termios *termiosp = (struct termios *)arg; struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint32_t baud; uint32_t imr; @@ -1537,7 +1537,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) static int up_receive(struct uart_dev_s *dev, uint32_t *status) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Return the error information in the saved status */ @@ -1559,7 +1559,7 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status) static void up_rxint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; if (enable) { @@ -1587,7 +1587,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) static bool up_rxavailable(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return ((up_serialin(priv, SAM_UART_SR_OFFSET) & UART_INT_RXRDY) != 0); } @@ -1601,7 +1601,7 @@ static bool up_rxavailable(struct uart_dev_s *dev) static void up_send(struct uart_dev_s *dev, int ch) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; up_serialout(priv, SAM_UART_THR_OFFSET, (uint32_t)ch); } @@ -1615,7 +1615,7 @@ static void up_send(struct uart_dev_s *dev, int ch) static void up_txint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; flags = irqsave(); @@ -1656,7 +1656,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) static bool up_txready(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return ((up_serialin(priv, SAM_UART_SR_OFFSET) & UART_INT_TXRDY) != 0); } @@ -1670,7 +1670,7 @@ static bool up_txready(struct uart_dev_s *dev) static bool up_txempty(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; return ((up_serialin(priv, SAM_UART_SR_OFFSET) & UART_INT_TXEMPTY) != 0); } diff --git a/arch/arm/src/sama5/sam_serialinit.c b/arch/arm/src/sama5/sam_serialinit.c index 0e2bd8eeb30..59c25ed285f 100644 --- a/arch/arm/src/sama5/sam_serialinit.c +++ b/arch/arm/src/sama5/sam_serialinit.c @@ -101,7 +101,7 @@ void up_serialinit(void) flexus_serialinit(); #endif -/* Register the DBGU as well */ + /* Register the DBGU as well */ #ifdef CONFIG_SAMA5_DBGU sam_dbgu_register(); diff --git a/arch/arm/src/sama5/sam_spi.c b/arch/arm/src/sama5/sam_spi.c index 0cba1bf66d7..812120d04c3 100644 --- a/arch/arm/src/sama5/sam_spi.c +++ b/arch/arm/src/sama5/sam_spi.c @@ -1284,8 +1284,8 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, { struct sam_spics_s *spics = (struct sam_spics_s *)dev; struct sam_spidev_s *spi = spi_device(spics); - uint8_t *rxptr = (uint8_t*)rxbuffer; - uint8_t *txptr = (uint8_t*)txbuffer; + uint8_t *rxptr = (uint8_t *)rxbuffer; + uint8_t *txptr = (uint8_t *)txbuffer; uint32_t pcs; uint32_t data; @@ -1754,7 +1754,7 @@ struct spi_dev_s *up_spiinitialize(int port) } #endif - /* Select the SPI operations */ + /* Select the SPI operations */ #if defined(CONFIG_SAMA5_SPI0) && defined(CONFIG_SAMA5_SPI1) spics->spidev.ops = spino ? &g_spi1ops : &g_spi0ops; diff --git a/arch/arm/src/sama5/sam_ssc.c b/arch/arm/src/sama5/sam_ssc.c index bc5fa8fe4e7..c04e23d3d56 100644 --- a/arch/arm/src/sama5/sam_ssc.c +++ b/arch/arm/src/sama5/sam_ssc.c @@ -3359,7 +3359,7 @@ static void ssc1_configure(struct sam_ssc_s *priv) #if defined(CONFIG_SAMA5_SSC1_TX_TKOUTPUT_CONT) priv->txout = SSC_CLKOUT_CONT; /* Continuous */ #elif defined(CONFIG_SAMA5_SSC1_TX_TKOUTPUT_XFR) - priv->txout = SSC_CLKOUT_XFER;/* Only output clock during transfers */ + priv->txout = SSC_CLKOUT_XFER; /* Only output clock during transfers */ #else /* if defined(CONFIG_SAMA5_SSC1_TX_TKOUTPUT_NONE) */ priv->txout = SSC_CLKOUT_NONE; /* No output clock */ #endif diff --git a/arch/arm/src/sama5/sam_trng.c b/arch/arm/src/sama5/sam_trng.c index 0480d2e6e48..1be5585bc4b 100644 --- a/arch/arm/src/sama5/sam_trng.c +++ b/arch/arm/src/sama5/sam_trng.c @@ -100,7 +100,7 @@ static const struct file_operations g_trngops = 0, /* seek */ 0 /* ioctl */ #ifndef CONFIG_DISABLE_POLL - ,0 /* poll */ + , 0 /* poll */ #endif }; @@ -130,7 +130,7 @@ static int sam_interrupt(int irq, void *context) * that we will loop here. */ - for (;;) + for (; ; ) { /* Read the random sample (before checking DATRDY -- but probably not * necessary) diff --git a/arch/arm/src/sama5/sam_tsd.c b/arch/arm/src/sama5/sam_tsd.c index 2f930effe6c..818de965997 100644 --- a/arch/arm/src/sama5/sam_tsd.c +++ b/arch/arm/src/sama5/sam_tsd.c @@ -334,7 +334,7 @@ static int sam_tsd_sample(struct sam_tsd_s *priv, struct sam_sample_s *sample) /* First report -- next report will be a movement */ priv->sample.contact = CONTACT_MOVE; - } + } priv->penchange = false; ret = OK; @@ -399,7 +399,7 @@ static int sam_tsd_waitsample(struct sam_tsd_s *priv, struct sam_sample_s *sampl ivdbg("Sampled\n"); - /* Re-acquire the semaphore that manages mutually exclusive access to + /* Re-acquire the semaphore that manages mutually exclusive access to * the device structure. We may have to wait here. But we have our sample. * Interrupts and pre-emption will be re-enabled while we wait. */ @@ -571,15 +571,15 @@ static void sam_tsd_bottomhalf(void *arg) priv->sample.contact = CONTACT_UP; - /* Stop periodic trigger & enable pen */ + /* Stop periodic trigger & enable pen */ - sam_tsd_setaverage(priv, ADC_TSMR_TSAV_NOFILTER); - sam_tsd_debounce(priv, BOARD_TSD_DEBOUNCE); + sam_tsd_setaverage(priv, ADC_TSMR_TSAV_NOFILTER); + sam_tsd_debounce(priv, BOARD_TSD_DEBOUNCE); - regval = sam_adc_getreg(priv->adc, SAM_ADC_TRGR); - regval &= ~ADC_TRGR_TRGMOD_MASK; - regval |= ADC_TRGR_TRGMOD_PEN; - sam_adc_putreg(priv->adc, SAM_ADC_TRGR, regval); + regval = sam_adc_getreg(priv->adc, SAM_ADC_TRGR); + regval &= ~ADC_TRGR_TRGMOD_MASK; + regval |= ADC_TRGR_TRGMOD_PEN; + sam_adc_putreg(priv->adc, SAM_ADC_TRGR, regval); } /* It is a pen down event. If the last loss-of-contact event has not been @@ -697,7 +697,7 @@ static void sam_tsd_bottomhalf(void *arg) priv->threshx = x; priv->threshy = y; - /* Update the x/y position in the sample data */ + /* Update the x/y position in the sample data */ priv->sample.x = MIN(x, UINT16_MAX); priv->sample.y = MIN(y, UINT16_MAX); @@ -958,7 +958,7 @@ static ssize_t sam_tsd_read(struct file *filep, char *buffer, size_t len) { ret = -EAGAIN; goto errout; - } + } /* Wait for sample data */ @@ -990,10 +990,10 @@ static ssize_t sam_tsd_read(struct file *filep, char *buffer, size_t len) if (sample.contact == CONTACT_UP) { - /* Pen is now up. Is the positional data valid? This is important - * to know because the release will be sent to the window based on - * its last positional data. - */ + /* Pen is now up. Is the positional data valid? This is important + * to know because the release will be sent to the window based on + * its last positional data. + */ if (sample.valid) { @@ -1441,10 +1441,10 @@ static void sam_tsd_debounce(struct sam_tsd_s *priv, uint32_t time) div = 1000000000; while (div > 1 && (time % 10) == 0) - { + { time /= 10; div /= 10; - } + } clk = BOARD_ADCCLK_FREQUENCY; while (div > 1 && (clk % 10) == 0) diff --git a/arch/arm/src/sama5/sam_udphs.c b/arch/arm/src/sama5/sam_udphs.c index 6394c389b38..54aa82d63bd 100644 --- a/arch/arm/src/sama5/sam_udphs.c +++ b/arch/arm/src/sama5/sam_udphs.c @@ -4557,7 +4557,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) sam_pullup(&priv->usbdev, true); priv->usbdev.speed = USB_SPEED_FULL; - } + } return ret; } diff --git a/arch/arm/src/sama5/sam_wdt.c b/arch/arm/src/sama5/sam_wdt.c index cf4cda81108..7bac126f090 100644 --- a/arch/arm/src/sama5/sam_wdt.c +++ b/arch/arm/src/sama5/sam_wdt.c @@ -209,20 +209,20 @@ static uint32_t sam_getreg(uintptr_t regaddr) else { - /* Did we print "..." for the previous value? */ + /* Did we print "..." for the previous value? */ - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ - lldbg("[repeats %d more times]\n", count-3); - } + lldbg("[repeats %d more times]\n", count-3); + } - /* Save the new address, value, and count */ + /* Save the new address, value, and count */ - prevaddr = regaddr; - preval = regval; - count = 1; + prevaddr = regaddr; + preval = regval; + count = 1; } /* Show the register value read */ diff --git a/arch/arm/src/sama5/sam_xdmac.c b/arch/arm/src/sama5/sam_xdmac.c index 2936dec8d95..69fed83d0ca 100644 --- a/arch/arm/src/sama5/sam_xdmac.c +++ b/arch/arm/src/sama5/sam_xdmac.c @@ -1859,10 +1859,10 @@ static int sam_xdmac_interrupt(struct sam_xdmac_s *xdmac) if ((chpending & XDMAC_CHINT_ERRORS) != 0) { - /* Yes... Terminate the transfer with an error? */ + /* Yes... Terminate the transfer with an error? */ - dmalldbg("ERROR: DMA failed: %08x\n", chpending); - sam_dmaterminate(xdmach, -EIO); + dmalldbg("ERROR: DMA failed: %08x\n", chpending); + sam_dmaterminate(xdmach, -EIO); } /* Is the transfer complete? */ diff --git a/arch/arm/src/sama5/sama5d2x_memorymap.c b/arch/arm/src/sama5/sama5d2x_memorymap.c index 8eeb4b34ac1..e73281cabd2 100644 --- a/arch/arm/src/sama5/sama5d2x_memorymap.c +++ b/arch/arm/src/sama5/sama5d2x_memorymap.c @@ -81,7 +81,7 @@ const struct section_mapping_s g_section_mapping[] = * 0x0000:00000. VBAR == 0x0000:0000. * * This method is used when booting from ISRAM or NOR FLASH. In - & that case, vectors must lie at the beginning of NOFR FLASH. + * that case, vectors must lie at the beginning of NOFR FLASH. * * 3. Set the Cortex-A5 VBAR register so that the vector table address * is moved to a location other than 0x0000:0000. @@ -180,7 +180,7 @@ const struct section_mapping_s g_section_mapping[] = }, #endif -/* SAMA5 CS1-3 External Memories */ + /* SAMA5 CS1-3 External Memories */ #ifdef CONFIG_SAMA5_EBICS1 { SAM_EBICS1_PSECTION, SAM_EBICS1_VSECTION, @@ -251,13 +251,13 @@ const struct section_mapping_s g_section_mapping[] = SAM_PERIPHC_MMUFLAGS, SAM_PERIPHC_NSECTIONS }, -/* LCDC Framebuffer. This entry reprograms a part of one of the above - * regions, making it non-cacheable and non-buffereable. - * - * If SDRAM will be reconfigured, then we will defer setup of the framebuffer - * until after the SDRAM remapping (since the framebuffer problem resides) in - * SDRAM. - */ + /* LCDC Framebuffer. This entry reprograms a part of one of the above + * regions, making it non-cacheable and non-buffereable. + * + * If SDRAM will be reconfigured, then we will defer setup of the framebuffer + * until after the SDRAM remapping (since the framebuffer problem resides) in + * SDRAM. + */ #if defined(CONFIG_SAMA5_LCDC) && !defined(NEED_SDRAM_REMAPPING) { CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE, diff --git a/arch/arm/src/sama5/sama5d3x_memorymap.c b/arch/arm/src/sama5/sama5d3x_memorymap.c index f21b3c1312d..229d2e81327 100644 --- a/arch/arm/src/sama5/sama5d3x_memorymap.c +++ b/arch/arm/src/sama5/sama5d3x_memorymap.c @@ -81,7 +81,7 @@ const struct section_mapping_s g_section_mapping[] = * 0x0000:00000. VBAR == 0x0000:0000. * * This method is used when booting from ISRAM or NOR FLASH. In - & that case, vectors must lie at the beginning of NOFR FLASH. + * that case, vectors must lie at the beginning of NOFR FLASH. * * 3. Set the Cortex-A5 VBAR register so that the vector table address * is moved to a location other than 0x0000:0000. @@ -177,7 +177,7 @@ const struct section_mapping_s g_section_mapping[] = }, #endif -/* SAMA5 CS1-3 External Memories */ + /* SAMA5 CS1-3 External Memories */ #ifdef CONFIG_SAMA5_EBICS1 { SAM_EBICS1_PSECTION, SAM_EBICS1_VSECTION, @@ -220,13 +220,13 @@ const struct section_mapping_s g_section_mapping[] = SAM_SYSC_MMUFLAGS, SAM_SYSC_NSECTIONS }, -/* LCDC Framebuffer. This entry reprograms a part of one of the above - * regions, making it non-cacheable and non-buffereable. - * - * If SDRAM will be reconfigured, then we will defer setup of the framebuffer - * until after the SDRAM remapping (since the framebuffer problem resides) in - * SDRAM. - */ + /* LCDC Framebuffer. This entry reprograms a part of one of the above + * regions, making it non-cacheable and non-buffereable. + * + * If SDRAM will be reconfigured, then we will defer setup of the framebuffer + * until after the SDRAM remapping (since the framebuffer problem resides) in + * SDRAM. + */ #if defined(CONFIG_SAMA5_LCDC) && !defined(NEED_SDRAM_REMAPPING) { CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE, diff --git a/arch/arm/src/sama5/sama5d4x_memorymap.c b/arch/arm/src/sama5/sama5d4x_memorymap.c index 3c3854e0370..8d63ea70d53 100644 --- a/arch/arm/src/sama5/sama5d4x_memorymap.c +++ b/arch/arm/src/sama5/sama5d4x_memorymap.c @@ -81,7 +81,7 @@ const struct section_mapping_s g_section_mapping[] = * 0x0000:00000. VBAR == 0x0000:0000. * * This method is used when booting from ISRAM or NOR FLASH. In - & that case, vectors must lie at the beginning of NOFR FLASH. + * that case, vectors must lie at the beginning of NOFR FLASH. * * 3. Set the Cortex-A5 VBAR register so that the vector table address * is moved to a location other than 0x0000:0000. @@ -183,7 +183,7 @@ const struct section_mapping_s g_section_mapping[] = }, #endif -/* SAMA5 CS1-3 External Memories */ + /* SAMA5 CS1-3 External Memories */ #ifdef CONFIG_SAMA5_EBICS1 { SAM_EBICS1_PSECTION, SAM_EBICS1_VSECTION, @@ -224,13 +224,13 @@ const struct section_mapping_s g_section_mapping[] = SAM_PERIPHC_MMUFLAGS, SAM_PERIPHC_NSECTIONS }, -/* LCDC Framebuffer. This entry reprograms a part of one of the above - * regions, making it non-cacheable and non-buffereable. - * - * If SDRAM will be reconfigured, then we will defer setup of the framebuffer - * until after the SDRAM remapping (since the framebuffer problem resides) in - * SDRAM. - */ + /* LCDC Framebuffer. This entry reprograms a part of one of the above + * regions, making it non-cacheable and non-buffereable. + * + * If SDRAM will be reconfigured, then we will defer setup of the framebuffer + * until after the SDRAM remapping (since the framebuffer problem resides) in + * SDRAM. + */ #if defined(CONFIG_SAMA5_LCDC) && !defined(NEED_SDRAM_REMAPPING) { CONFIG_SAMA5_LCDC_FB_PBASE, CONFIG_SAMA5_LCDC_FB_VBASE, diff --git a/arch/arm/src/samdl/sam_dmac.c b/arch/arm/src/samdl/sam_dmac.c index b79b2f5778d..0085b173963 100644 --- a/arch/arm/src/samdl/sam_dmac.c +++ b/arch/arm/src/samdl/sam_dmac.c @@ -122,7 +122,7 @@ static int sam_dmainterrupt(int irq, void *context); static struct dma_desc_s *sam_alloc_desc(struct sam_dmach_s *dmach); static struct dma_desc_s *sam_append_desc(struct sam_dmach_s *dmach, uint16_t btctrl, uint16_t btcnt, - uint32_t srcaddr,uint32_t dstaddr); + uint32_t srcaddr, uint32_t dstaddr); static void sam_free_desc(struct sam_dmach_s *dmach); static size_t sam_maxtransfer(struct sam_dmach_s *dmach); static uint16_t sam_bytes2beats(struct sam_dmach_s *dmach, size_t nbytes); @@ -153,7 +153,7 @@ static struct sam_dmach_s g_dmach[SAMDL_NDMACHAN]; */ static struct dma_desc_s g_base_desc[SAMDL_NDMACHAN] - __attribute__ ((section(".lpram"),aligned(16))); + __attribute__ ((section(".lpram"), aligned(16))); #define g_writeback_desc g_base_desc #if CONFIG_SAMDL_DMAC_NDESC > 0 @@ -162,7 +162,7 @@ static struct dma_desc_s g_base_desc[SAMDL_NDMACHAN] */ static struct dma_desc_s g_dma_desc[CONFIG_SAMDL_DMAC_NDESC] - __attribute__ ((section(".lpram"),aligned(16))); + __attribute__ ((section(".lpram"), aligned(16))); #endif /**************************************************************************** diff --git a/arch/arm/src/samdl/sam_serial.c b/arch/arm/src/samdl/sam_serial.c index ea8e9affc6d..a3352796b2a 100644 --- a/arch/arm/src/samdl/sam_serial.c +++ b/arch/arm/src/samdl/sam_serial.c @@ -557,7 +557,7 @@ static void sam_disableallints(struct sam_dev_s *priv) static int sam_interrupt(struct uart_dev_s *dev) { - struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv;; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; uint8_t pending; uint8_t intflag; uint8_t inten; @@ -591,9 +591,9 @@ static int sam_interrupt(struct uart_dev_s *dev) if ((pending & USART_INT_DRE) != 0) { - /* Transmit data register empty ... process outgoing bytes */ + /* Transmit data register empty ... process outgoing bytes */ - uart_xmitchars(dev); + uart_xmitchars(dev); } return OK; @@ -729,11 +729,11 @@ static int sam_attach(struct uart_dev_s *dev) ret = irq_attach(config->irq, priv->handler); if (ret == OK) { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the USART - */ + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the USART + */ - up_enable_irq(config->irq); + up_enable_irq(config->irq); } return ret; diff --git a/arch/arm/src/samdl/sam_spi.c b/arch/arm/src/samdl/sam_spi.c index afd51e98c44..cce36cf9e85 100644 --- a/arch/arm/src/samdl/sam_spi.c +++ b/arch/arm/src/samdl/sam_spi.c @@ -799,7 +799,7 @@ static void spi_dumpregs(struct sam_spidev_s *priv, const char *msg) #if 0 /* Not used */ static int spi_interrupt(struct sam_spidev_s *dev) { - struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv;; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; uint8_t pending; uint8_t intflag; uint8_t inten; @@ -832,7 +832,7 @@ static int spi_interrupt(struct sam_spidev_s *dev) if ((pending & SPI_INT_DRE) != 0) { - /* Transmit data register empty ... process outgoing bytes */ + /* Transmit data register empty ... process outgoing bytes */ #warning Missing logic } diff --git a/arch/arm/src/samdl/sam_start.c b/arch/arm/src/samdl/sam_start.c index ef2d81dc7f4..e31a1b274df 100644 --- a/arch/arm/src/samdl/sam_start.c +++ b/arch/arm/src/samdl/sam_start.c @@ -174,5 +174,5 @@ void __start(void) /* Shoulnd't get here */ - for (;;); + for (; ; ); } diff --git a/arch/arm/src/samv7/sam_allocateheap.c b/arch/arm/src/samv7/sam_allocateheap.c index f092d0767f6..65ba3f425ff 100644 --- a/arch/arm/src/samv7/sam_allocateheap.c +++ b/arch/arm/src/samv7/sam_allocateheap.c @@ -293,7 +293,7 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) * that was not dedicated to the user heap). */ - *heap_start = (FAR void*)USERSPACE->us_bssend; + *heap_start = (FAR void *)USERSPACE->us_bssend; *heap_size = ubase - (uintptr_t)USERSPACE->us_bssend; } #endif @@ -317,7 +317,7 @@ void up_addregion(void) /* Add the region */ - kumm_addregion((FAR void*)SAM_SDRAMCS_BASE, CONFIG_SAMV7_SDRAMSIZE); + kumm_addregion((FAR void *)SAM_SDRAMCS_BASE, CONFIG_SAMV7_SDRAMSIZE); #endif /* HAVE_SDRAM_REGION */ diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c index 2807714af49..b7eab4a95ce 100644 --- a/arch/arm/src/samv7/sam_emac.c +++ b/arch/arm/src/samv7/sam_emac.c @@ -1827,17 +1827,17 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid) xfrq->rxndx = rxndx; } - /* Set-up to process the next fragment. Get the RX descriptor - * associated with the next fragment. - */ + /* Set-up to process the next fragment. Get the RX descriptor + * associated with the next fragment. + */ - rxdesc = &xfrq->rxdesc[rxndx]; + rxdesc = &xfrq->rxdesc[rxndx]; - /* Invalidate the RX descriptor to force re-fetching from RAM */ + /* Invalidate the RX descriptor to force re-fetching from RAM */ - arch_invalidate_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); - } + arch_invalidate_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); + } /* No packet was found */ @@ -1949,7 +1949,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid) */ if (priv->dev.d_len > 0) - { + { /* Update the Ethernet header with the correct MAC address */ #ifdef CONFIG_NET_IPv4 @@ -3290,7 +3290,7 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac) if (regval == 0 && sam_getreg(priv, regoffset2) == 0) { - /* Yes.. disable all address matching */ + /* Yes.. disable all address matching */ regval = sam_getreg(priv, SAM_EMAC_NCFGR_OFFSET); regval &= ~(EMAC_NCFGR_UNIHEN | EMAC_NCFGR_MTIHEN); @@ -4072,7 +4072,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv) /* Check AutoNegotiate complete */ timeout = 0; - for (;;) + for (; ; ) { ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr); if (ret < 0) @@ -4446,9 +4446,9 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv) } else #endif - { - nvdbg("ERROR: emac=%d\n", priv->attr->emac); - } + { + nvdbg("ERROR: emac=%d\n", priv->attr->emac); + } } /**************************************************************************** diff --git a/arch/arm/src/samv7/sam_gpioirq.c b/arch/arm/src/samv7/sam_gpioirq.c index d7e235c58b8..8929d175779 100644 --- a/arch/arm/src/samv7/sam_gpioirq.c +++ b/arch/arm/src/samv7/sam_gpioirq.c @@ -398,10 +398,10 @@ void sam_gpioirqenable(int irq) if (sam_irqbase(irq, &base, &pin) == OK) { - /* Clear (all) pending interrupts and enable this pin interrupt */ + /* Clear (all) pending interrupts and enable this pin interrupt */ - //(void)getreg32(base + SAM_PIO_ISR_OFFSET); - putreg32((1 << pin), base + SAM_PIO_IER_OFFSET); + //(void)getreg32(base + SAM_PIO_ISR_OFFSET); + putreg32((1 << pin), base + SAM_PIO_IER_OFFSET); } } @@ -420,9 +420,9 @@ void sam_gpioirqdisable(int irq) if (sam_irqbase(irq, &base, &pin) == OK) { - /* Disable this pin interrupt */ + /* Disable this pin interrupt */ - putreg32((1 << pin), base + SAM_PIO_IDR_OFFSET); + putreg32((1 << pin), base + SAM_PIO_IDR_OFFSET); } } diff --git a/arch/arm/src/samv7/sam_hsmci.c b/arch/arm/src/samv7/sam_hsmci.c index 20db5da509b..563c302adff 100644 --- a/arch/arm/src/samv7/sam_hsmci.c +++ b/arch/arm/src/samv7/sam_hsmci.c @@ -1441,7 +1441,7 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv) /* Loop while there are pending interrupts. */ - for (;;) + for (; ; ) { /* Check the HSMCI status register. Mask out all bits that don't * correspond to enabled interrupts. (This depends on the fact that @@ -1911,7 +1911,7 @@ static int sam_sendcmd(FAR struct sdio_dev_s *dev, sam_cmdsampleinit(priv); - /* Set the HSMCI Argument value */ + /* Set the HSMCI Argument value */ sam_putreg(priv, arg, SAM_HSMCI_ARGR_OFFSET); @@ -2287,7 +2287,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) /* Then wait for the response (or timeout) */ - for (;;) + for (; ; ) { /* Did a Command-Response sequence termination evernt occur? */ @@ -2648,7 +2648,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev, if (!timeout) { - return SDIOWAIT_TIMEOUT; + return SDIOWAIT_TIMEOUT; } /* Start the watchdog timer. I am not sure why this is, but I am @@ -2677,7 +2677,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev, * may have already occurred before this function was called! */ - for (;;) + for (; ; ) { /* Wait for an event in event set to occur. If this the event has already * occurred, then the semaphore will already have been incremented and @@ -2870,7 +2870,7 @@ static int sam_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, regaddr += sizeof(uint32_t); memaddr += blocksize; - } + } /* Enable DMA handshaking */ @@ -2966,7 +2966,7 @@ static int sam_dmasendsetup(FAR struct sdio_dev_s *dev, regaddr += sizeof(uint32_t); memaddr += blocksize; - } + } /* Enable DMA handshaking */ @@ -3029,8 +3029,8 @@ static void sam_callback(void *arg) /* Media is present. Is the media inserted event enabled? */ if ((priv->cbevents & SDIOMEDIA_INSERTED) == 0) - { - /* No... return without performing the callback */ + { + /* No... return without performing the callback */ return; } @@ -3056,7 +3056,7 @@ static void sam_callback(void *arg) /* This function is called either from (1) the context of the calling * thread or from the the context of (2) card detection logic. The * caller may or may not have interrupts disabled (we have them - & disabled here!). + * disabled here!). * * So to minimize the possibility of recursive behavior and to assure * that callback is always performed outside of the interrupt handling diff --git a/arch/arm/src/samv7/sam_lowputc.c b/arch/arm/src/samv7/sam_lowputc.c index 52d167cd0fd..1897cd17f85 100644 --- a/arch/arm/src/samv7/sam_lowputc.c +++ b/arch/arm/src/samv7/sam_lowputc.c @@ -208,7 +208,7 @@ void up_lowputc(char ch) #ifdef HAVE_SERIAL_CONSOLE irqstate_t flags; - for (;;) + for (; ; ) { /* Wait for the transmitter to be available */ diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c index 5f729cbdb82..74f59877db9 100644 --- a/arch/arm/src/samv7/sam_mcan.c +++ b/arch/arm/src/samv7/sam_mcan.c @@ -1202,20 +1202,20 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset) else { - /* Did we print "..." for the previous value? */ + /* Did we print "..." for the previous value? */ - if (priv->count > 3) - { - /* Yes.. then show how many times the value repeated */ + if (priv->count > 3) + { + /* Yes.. then show how many times the value repeated */ - lldbg("[repeats %d more times]\n", priv->count - 3); - } + lldbg("[repeats %d more times]\n", priv->count - 3); + } - /* Save the new address, value, and count */ + /* Save the new address, value, and count */ - priv->regaddr = regaddr; - priv->regval = regval; - priv->count = 1; + priv->regaddr = regaddr; + priv->regval = regval; + priv->count = 1; } /* Show the register value read */ @@ -1440,7 +1440,7 @@ static void mcan_buffer_reserve(FAR struct sam_mcan_s *priv) * be incremented and, hence, to be too low. */ - for (;;) + for (; ; ) { /* Get the current queue status and semaphore count. */ @@ -3272,7 +3272,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev) * FIFO0. */ - for (;;) + for (; ; ) { /* Check if there is anything in RX FIFO1 */ diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index ff57917a68b..e886d7356c3 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -1788,7 +1788,7 @@ struct qspi_dev_s *sam_qspi_initialize(int intf) if (priv->candma) { - priv->dmach = sam_dmachannel(0,0); + priv->dmach = sam_dmachannel(0, 0); if (!priv->dmach) { qspidbg("ERROR: Failed to allocate the DMA channel\n"); diff --git a/arch/arm/src/samv7/sam_serial.c b/arch/arm/src/samv7/sam_serial.c index 352501a7d1f..47f7d8e9265 100644 --- a/arch/arm/src/samv7/sam_serial.c +++ b/arch/arm/src/samv7/sam_serial.c @@ -901,7 +901,7 @@ static int sam_setup(struct uart_dev_s *dev) /* Enable receiver & transmitter */ - sam_serialout(priv, SAM_UART_CR_OFFSET, (UART_CR_RXEN|UART_CR_TXEN)); + sam_serialout(priv, SAM_UART_CR_OFFSET, (UART_CR_RXEN | UART_CR_TXEN)); #endif return OK; @@ -923,7 +923,8 @@ static void sam_shutdown(struct uart_dev_s *dev) /* Reset and disable receiver and transmitter */ sam_serialout(priv, SAM_UART_CR_OFFSET, - (UART_CR_RSTRX|UART_CR_RSTTX|UART_CR_RXDIS|UART_CR_TXDIS)); + (UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | + UART_CR_TXDIS)); /* Disable all interrupts */ @@ -955,11 +956,11 @@ static int sam_attach(struct uart_dev_s *dev) ret = irq_attach(priv->irq, priv->handler); if (ret == OK) { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the USART - */ + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the USART + */ - up_enable_irq(priv->irq); + up_enable_irq(priv->irq); } return ret; @@ -1025,10 +1026,10 @@ static int sam_interrupt(struct uart_dev_s *dev) if ((pending & UART_INT_RXRDY) != 0) { - /* Received data ready... process incoming bytes */ + /* Received data ready... process incoming bytes */ - uart_recvchars(dev); - handled = true; + uart_recvchars(dev); + handled = true; } /* Handle outgoing, transmit bytes. TXRDY: There is no character in the @@ -1037,10 +1038,10 @@ static int sam_interrupt(struct uart_dev_s *dev) if ((pending & UART_INT_TXRDY) != 0) { - /* Transmit data register empty ... process outgoing bytes */ + /* Transmit data register empty ... process outgoing bytes */ - uart_xmitchars(dev); - handled = true; + uart_xmitchars(dev); + handled = true; } } @@ -1150,8 +1151,8 @@ static int sam_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_TERMIOS case TCGETS: { - struct termios *termiosp = (struct termios*)arg; - struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; + struct termios *termiosp = (struct termios *)arg; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; if (!termiosp) { @@ -1207,8 +1208,8 @@ static int sam_ioctl(struct file *filep, int cmd, unsigned long arg) case TCSETS: { - struct termios *termiosp = (struct termios*)arg; - struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; + struct termios *termiosp = (struct termios *)arg; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; uint32_t baud; uint32_t imr; uint8_t parity; diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c index 7ab71ec3c42..a97ced37dd5 100644 --- a/arch/arm/src/samv7/sam_spi.c +++ b/arch/arm/src/samv7/sam_spi.c @@ -1801,7 +1801,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port) } #endif - /* Select the SPI operations */ + /* Select the SPI operations */ #if defined(CONFIG_SAMV7_SPI0_MASTER) && defined(CONFIG_SAMV7_SPI1_MASTER) spics->spidev.ops = spino ? &g_spi1ops : &g_spi0ops; diff --git a/arch/arm/src/samv7/sam_spi_slave.c b/arch/arm/src/samv7/sam_spi_slave.c index a156254b19c..70ac3e0f9f5 100644 --- a/arch/arm/src/samv7/sam_spi_slave.c +++ b/arch/arm/src/samv7/sam_spi_slave.c @@ -425,7 +425,7 @@ static int spi_interrupt(struct sam_spidev_s *priv) * execution. */ - for (;;) + for (; ; ) { /* Get the current set of pending/enabled interrupts */ diff --git a/arch/arm/src/samv7/sam_ssc.c b/arch/arm/src/samv7/sam_ssc.c index fb9fed17733..d2ce566d044 100644 --- a/arch/arm/src/samv7/sam_ssc.c +++ b/arch/arm/src/samv7/sam_ssc.c @@ -3333,7 +3333,7 @@ static void ssc1_configure(struct sam_ssc_s *priv) #if defined(CONFIG_SAMV7_SSC1_TX_TKOUTPUT_CONT) priv->txout = SSC_CLKOUT_CONT; /* Continuous */ #elif defined(CONFIG_SAMV7_SSC1_TX_TKOUTPUT_XFR) - priv->txout = SSC_CLKOUT_XFER;/* Only output clock during transfers */ + priv->txout = SSC_CLKOUT_XFER; /* Only output clock during transfers */ #else /* if defined(CONFIG_SAMV7_SSC1_TX_TKOUTPUT_NONE) */ priv->txout = SSC_CLKOUT_NONE; /* No output clock */ #endif diff --git a/arch/arm/src/samv7/sam_start.c b/arch/arm/src/samv7/sam_start.c index c587db5e750..ec12b7ef87c 100644 --- a/arch/arm/src/samv7/sam_start.c +++ b/arch/arm/src/samv7/sam_start.c @@ -103,7 +103,7 @@ static inline void sam_fpuconfig(void); #endif #ifdef CONFIG_STACK_COLORATION static void go_os_start(void *pv, unsigned int nbytes) - __attribute__ ((naked,no_instrument_function,noreturn)); + __attribute__ ((naked, no_instrument_function, noreturn)); #endif /**************************************************************************** @@ -401,6 +401,6 @@ void __start(void) /* Shouldn't get here */ - for (;;); + for (; ; ); #endif } diff --git a/arch/arm/src/samv7/sam_xdmac.c b/arch/arm/src/samv7/sam_xdmac.c index a0b99f68bdf..b65b2f6eeff 100644 --- a/arch/arm/src/samv7/sam_xdmac.c +++ b/arch/arm/src/samv7/sam_xdmac.c @@ -1541,10 +1541,10 @@ static int sam_xdmac_interrupt(int irq, void *context) if ((chpending & XDMAC_CHINT_ERRORS) != 0) { - /* Yes... Terminate the transfer with an error? */ + /* Yes... Terminate the transfer with an error? */ - dmalldbg("ERROR: DMA failed: %08x\n", chpending); - sam_dmaterminate(xdmach, -EIO); + dmalldbg("ERROR: DMA failed: %08x\n", chpending); + sam_dmaterminate(xdmach, -EIO); } /* Is the transfer complete? */