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Merged nuttx/nuttx/master into master

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This commit is contained in:
Masayuki Ishikawa
2017-03-01 13:19:57 +09:00
parent 6fe94b5724 5987db47e5
commit b118fb4387
777 changed files with 24266 additions and 6808 deletions
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.gitignore
+1 -1
View File
@@ -9,7 +9,7 @@ Make.dep
.*.swp
core
.gdbinit
cscope.out
/cscope.*
/.config
/.config.old
/.version
ChangeLog
+1 -1
View File
@@ -12483,7 +12483,7 @@
to unregister a signal handler (2016-08-01).
* configs/sim: Add simulator-based test support for apps/examples/gpio
2016-08-01).
* drivers/sensors: Add KXJT9 Accelerometer driver from the Motorola
* drivers/sensors: Add KXTJ9 Accelerometer driver from the Motorola
Moto Z MDK (2016-08-02).
* arch/arm/sim: Add a simulated I/O Expander driver (2016-08-03).
* configs/sim: Add logic to set the simulated I/O expander for testing
Documentation/README.html
+3 -1
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@@ -8,7 +8,7 @@
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
<p>Last Updated: February 14, 2017</p>
<p>Last Updated: February 19, 2017</p>
</td>
</tr>
</table>
@@ -287,6 +287,8 @@ nuttx/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/tm4c1294-launchpad/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- twr-k60n512/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/twr-k60n512/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- twr-k64f120m/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/twr-k64f120m/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- "u-blox-c027/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/u-blox-c027/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- ubw32/
Kconfig
+4 -4
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@@ -859,21 +859,21 @@ config DEBUG_IRQ
if DEBUG_IRQ
config DEBUG_IRQ_ERROR
bool "DMA Error Output"
bool "Interrupt Controller Error Output"
default n
depends on DEBUG_ERROR
---help---
Enable interrupt controller error output to SYSLOG.
config DEBUG_IRQ_WARN
bool "DMA Warnings Output"
bool "Interrupt Controller Warnings Output"
default n
depends on DEBUG_WARN
---help---
Enable interrupt controller warning output to SYSLOG.
config DEBUG_IRQ_INFO
bool "DMA Informational Output"
bool "Interrupt Controller Informational Output"
default n
depends on DEBUG_INFO
---help---
@@ -1277,7 +1277,7 @@ endif # DEBUG_RTC
config DEBUG_MEMCARD
bool "Memory Card Driver Debug Features"
default n
depends on MMCSD_SDIO
depends on MMCSD
---help---
Enable MMC/SD memory card Driver debug features.
README.txt
+2
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@@ -1671,6 +1671,8 @@ nuttx/
| | `- README.txt
| |- twr-k60n512/
| | `- README.txt
| |- twr-k64f120m/
| | `- README.txt
| |- u-blox-co27/
| | `- README.txt
| |- ubw32/
ReleaseNotes
+1 -1
View File
@@ -11813,7 +11813,7 @@ Additional new features and extended functionality:
* Sensor Drivers:
- Add KXJT9 Accelerometer driver from the Motorola Moto Z MDK.
- Add KXTJ9 Accelerometer driver from the Motorola Moto Z MDK.
- Add MFRC522 RFID ISO14443 and Mifare transceiver driver. From Alan
Carvalho de Assis.
- Add driver for the LIS3MDL 3 axis magnetometer. From Alexander
TODO
+1 -1
View File
@@ -438,7 +438,7 @@ o pthreads (sched/pthreads)
serve as cancellation points. They are, however, simple wrappers around nanosleep
which is a true cancellation point.
NOTE 02: system() is actually implemented in apps/ as part of NSH. It cannot be
a cancellation point either.
a cancellation point.
NOTE 03: sigpause() is a user-space function in the C library and cannot serve as
cancellation points. It is, however, a simple wrapper around sigsuspend()
which is a true cancellation point.
arch/arm/include/kinetis/chip.h
+4 -1
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@@ -43,6 +43,8 @@
#include <nuttx/config.h>
#include <arch/kinetis/kinetis_mcg.h>
#include <arch/kinetis/kinetis_sim.h>
#include <arch/kinetis/kinetis_pmc.h>
/************************************************************************************
* Pre-processor Definitions
@@ -1425,7 +1427,8 @@
# define KINETIS_NUSBDEV 1 /* One USB device controller */
# define KINETIS_NSDHC 1 /* SD host controller */
# define KINETIS_NI2C 4 /* Four I2C modules */
# define KINETIS_NUART 5 /* Five UART modues */
# define KINETIS_NUART 5 /* Five UART modules */
# define KINETIS_NLPUART 1 /* One LPUART modules */
# define KINETIS_NSPI 3 /* Three SPI modules */
# define KINETIS_NCAN 2 /* Two CAN controllers */
# define KINETIS_NI2S 1 /* One I2S modules */
arch/arm/include/kinetis/kinetis_mcg.h
+6 -6
View File
@@ -76,7 +76,7 @@
* KINETIS_MCG_HAS_PLL_INTERNAL_MODE - Has PEI mode or PBI mode
* KINETIS_MCG_HAS_RESET_IS_BLPI - Has Reset clock mode is BLPI
*
* MCD Register Configuration
* MCG Register Configuration
*
* KINETIS_MCG_HAS_C1 - SoC has C1 Register
* KINETIS_MCG_HAS_C1_IREFS - SoC has C1[IREFS]
@@ -289,7 +289,7 @@
# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */
# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */
/* MCD Register Configuration */
/* MCG Register Configuration */
# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */
# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */
@@ -371,7 +371,7 @@
# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */
# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */
/* MCD Register Configuration */
/* MCG Register Configuration */
# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */
# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */
@@ -448,7 +448,7 @@
/* Verified to Document Number: Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */
# define KINETIS_MCG_VERSION KINETIS_K_MCG_VERSION_06
# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_06
/* MCG Configuration Parameters */
@@ -463,7 +463,7 @@
# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */
# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */
/* MCD Register Configuration */
/* MCG Register Configuration */
# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */
# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */
@@ -544,7 +544,7 @@
# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */
# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */
/* MCD Register Configuration */
/* MCG Register Configuration */
# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */
# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */
arch/arm/include/kinetis/kinetis_pmc.h
+324
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@@ -0,0 +1,324 @@
/************************************************************************************
* arch/arm/include/kinetis/kinetis_pmc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_PMC_H
#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_PMC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Note: It is envisioned that in the long term as a chip is added. The author of
* the new chip definitions will either find the exact configuration in an existing
* chip define and add the new chip to it Or add the PMC feature configuration
* #defines to the chip ifdef list below. In either case the author should mark
* it as "Verified to Document Number:" taken from the reference manual.
*
* To maintain backward compatibility to the version of NuttX prior to
* 2/22/2017, the catch all KINETIS_PMC_VERSION_UKN configuration is assigned
* to all the chips that did not have any conditional compilation based on
* KINETIS_K64 or KINETIS_K66. This is a "No worse" than the original code solution.
* N.B. Each original chip "if"definitions have been left intact so that the
* complete legacy definitions prior to 2/22/2017 may be filled in completely when
* vetted.
*/
/* PMC Register Configuration
*
* KINETIS_PMC_HAS_REGSC - SoC has REGSC Register
* KINETIS_PMC_HAS_REGSC_ACKISO - SoC has REGSC[ACKISO]
* KINETIS_PMC_HAS_REGSC_VLPRS - SoC has REGSC[VLPRS]
* KINETIS_PMC_HAS_REGSC_VLPO - SoC has REGSC[VLPO]
* KINETIS_PMC_HAS_REGSC_REGFPM - SoC has REGSC[REGFPM]
* KINETIS_PMC_HAS_REGSC_BGEN - SoC has REGSC[BGEN]
* KINETIS_PMC_HAS_REGSC_TRAMPO - SoC has REGSC[TRAMPO]
* KINETIS_PMC_HAS_REGSC_REGONS - SoC has REGSC[REGONS]
*/
/* Describe the version of the PMC
*
* These defines are not related to any NXP reference but are merely
* a way to label the versions we are using
*/
#define KINETIS_PMC_VERSION_UKN -1 /* What was in nuttx prior to 2/22/2017 */
#define KINETIS_PMC_VERSION_01 1 /* Verified Document Number: K60P144M150SF3RM Rev. 3, November 2014 */
#define KINETIS_PMC_VERSION_04 4 /* Verified to Document Numbers:
* K20P64M72SF1RM Rev. 1.1, Dec 2012
* K64P144M120SF5RM Rev. 2, January 2014
* K66P144M180SF5RMV2 Rev. 2, May 2015 */
/* MK20DX/DN---VLH5
*
* ------------- ------ --- ------- ------ ------- ------ ----- ----
* PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
* FREQ CNT FLASH FLASH
* ------------- ------ --- ------- ------ ------- ------ ----- ----
* MK20DN32VLH5 50 MHz 64 LQFP 32 KB 32 KB — 8 KB 40
* MK20DX32VLH5 50 MHz 64 LQFP 64 KB 32 KB 2 KB 8 KB 40
* MK20DN64VLH5 50 MHz 64 LQFP 64 KB 64 KB — 16 KB 40
* MK20DX64VLH5 50 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40
* MK20DN128VLH5 50 MHz 64 LQFP 128 KB 128 KB — 16 KB 40
* MK20DX128VLH5 50 MHz 64 LQFP 160 KB 128 KB 2 KB 16 KB 40
*/
#if defined(CONFIG_ARCH_CHIP_MK20DN32VLH5) || \
defined(CONFIG_ARCH_CHIP_MK20DX32VLH5) || \
defined(CONFIG_ARCH_CHIP_MK20DN64VLH5) || \
defined(CONFIG_ARCH_CHIP_MK20DX64VLH5) || \
defined(CONFIG_ARCH_CHIP_MK20DN128VLH5) || \
defined(CONFIG_ARCH_CHIP_MK20DX128VLH5)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
/* MK20DX---VLH7
*
* ------------- ------ --- ------- ------ ------- ------ ----- ----
* PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
* FREQ CNT FLASH FLASH
* ------------- ------ --- ------- ------ ------- ------ ----- ----
* MK20DX64VLH7 72 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40
* MK20DX128VLH7 72 MHz 64 LQFP 160 KB 128 KB 2 KB 32 KB 40
* MK20DX256VLH7 72 MHz 64 LQFP 288 KB 256 KB 2 KB 64 KB 40
* ------------- ------ --- ------- ------ ------- ------ ----- ----
*/
#elif defined(CONFIG_ARCH_CHIP_MK20DX64VLH7) || defined(CONFIG_ARCH_CHIP_MK20DX128VLH7) || \
defined(CONFIG_ARCH_CHIP_MK20DX256VLH7)
/* Verified to Document Number: K20P64M72SF1RM Rev. 1.1, Dec 2012 */
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_04
/* PMC Register Configuration */
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */
# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
#elif defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \
defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK40X128VFX50) || defined(CONFIG_ARCH_CHIP_MK40X128VLH50) || \
defined(CONFIG_ARCH_CHIP_MK40X128VLK50) || defined(CONFIG_ARCH_CHIP_MK40X128VMB50) || \
defined(CONFIG_ARCH_CHIP_MK40X128VLL50) || defined(CONFIG_ARCH_CHIP_MK40X128VML50) || \
defined(CONFIG_ARCH_CHIP_MK40X128VFX72) || defined(CONFIG_ARCH_CHIP_MK40X128VLH72) || \
defined(CONFIG_ARCH_CHIP_MK40X128VLK72) || defined(CONFIG_ARCH_CHIP_MK40X128VMB72) || \
defined(CONFIG_ARCH_CHIP_MK40X128VLL72) || defined(CONFIG_ARCH_CHIP_MK40X128VML72)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK40X256VLK72) || defined(CONFIG_ARCH_CHIP_MK40X256VMB72) || \
defined(CONFIG_ARCH_CHIP_MK40X256VLL72) || defined(CONFIG_ARCH_CHIP_MK40X256VML72)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK40N512VLK100) || defined(CONFIG_ARCH_CHIP_MK40N512VMB100) || \
defined(CONFIG_ARCH_CHIP_MK40N512VLL100) || defined(CONFIG_ARCH_CHIP_MK40N512VML100) || \
defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
#elif defined(CONFIG_ARCH_CHIP_MK60FN1M0VLQ12)
/* Verified to Document Number: K60P144M100SF2V2RM Rev. 2 Jun 2012 */
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_01
/* PMC Register Configuration */
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
# undef KINETIS_PMC_HAS_REGSC_BGEN /* SoC has REGSC[BGEN] */
# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || \
defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \
defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || \
defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12)
/* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_04
/* PMC Register Configuration */
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */
# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
/* MK66F N/X 1M0/2M0 V MD/LQ 18
*
* --------------- ------- --- ------- ------- ------ ------ ------ -----
* PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
* FREQ CNT FLASH FLASH
* --------------- ------- --- ------- ------- ------ ------ ------ -----
* MK66FN2M0VMD18 180 MHz 144 MAPBGA 2 MB — — KB 260 KB 100
* MK66FX1M0VMD18 180 MHz 144 MAPBGA 1.25 MB 1 MB 4 KB 256 KB 100
* MK66FN2M0VLQ18 180 MHz 144 LQFP 2 MB — — KB 260 KB 100
* MK66FX1M0VLQ18 180 MHz 144 LQFP 1.25 MB 1 MB 4 KB 256 KB 100
*/
#elif defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \
defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18)
/* Verified to Document Number: Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_04
/* PMC Register Configuration */
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */
# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
#else
# error "Unsupported Kinetis chip"
#endif
/* Use the catch all configuration for the PMC based on the implementations in nuttx prior 2/3/2017 */
#if KINETIS_PMC_VERSION == KINETIS_PMC_VERSION_UKN
/* PMC Register Configuration */
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
# undef KINETIS_PMC_HAS_REGSC_ACKISO /* SoC has REGSC[ACKISO] */
# define KINETIS_PMC_HAS_REGSC_VLPRS 1 /* SoC has REGSC[VLPRS] */
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
# undef KINETIS_PMC_HAS_REGSC_BGEN /* SoC has REGSC[BGEN] */
# define KINETIS_PMC_HAS_REGSC_TRAMPO 1 /* SoC has REGSC[TRAMPO] */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
#endif
#if !defined(KINETIS_PMC_VERSION)
# error "No KINETIS_PMC_VERSION defined!"
#endif
#if defined(KINETIS_PMC_HAS_C5_PRDIV)
# define KINETIS_PMC_C5_PRDIV_MASK ((1 << (KINETIS_PMC_C5_PRDIV_BITS))-1)
#endif
#if defined(KINETIS_PMC_HAS_C7_OSCSEL)
# define KINETIS_PMC_C7_OSCSEL_MASK ((1 << (KINETIS_PMC_C7_OSCSEL_BITS))-1)
#endif
#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_PMC_H */
arch/arm/include/kinetis/kinetis_sim.h
+1322
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arch/arm/include/stm32/chip.h
+191 -2
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File diff suppressed because it is too large Load Diff
arch/arm/include/stm32/dma2d.h
+2 -2
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/include/stm32/dma2d.h
* arch/arm/include/stm32/dma2d.h
*
* Copyright (C) 2015 Marco Krahl. All rights reserved.
* Author: Marco Krahl <ocram.lhark@gmail.com>
@@ -345,7 +345,7 @@ struct dma2d_layer_s
*
****************************************************************************/
FAR struct dma2d_layer_s * up_dma2dgetlayer(int lid);
FAR struct dma2d_layer_s *up_dma2dgetlayer(int lid);
/****************************************************************************
* Name: up_dma2dcreatelayer
arch/arm/include/stm32/irq.h
+4 -2
View File
@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/include/stm32s/irq.h
* arch/arm/include/stm32/irq.h
*
* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2012, 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -85,6 +85,8 @@
# include <arch/stm32/stm32f20xxx_irq.h>
#elif defined(CONFIG_STM32_STM32F30XX)
# include <arch/stm32/stm32f30xxx_irq.h>
#elif defined(CONFIG_STM32_STM32F33XX)
# include <arch/stm32/stm32f33xxx_irq.h>
#elif defined(CONFIG_STM32_STM32F37XX)
# include <arch/stm32/stm32f37xxx_irq.h>
#elif defined(CONFIG_STM32_STM32F40XX)
arch/arm/include/stm32/ltdc.h
+1 -1
View File
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/include/stm32/ltdc.h
* arch/arm/include/stm32/ltdc.h
*
* Copyright (C) 2014-2015 Marco Krahl. All rights reserved.
* Author: Marco Krahl <ocram.lhark@gmail.com>
arch/arm/include/stm32/stm32f10xxx_irq.h
+1 -1
View File
@@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/include/stm32s/stm32f10xxx_irq.h
* arch/arm/include/stm32/stm32f10xxx_irq.h
*
* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/include/stm32/stm32f20xxx_irq.h
+1 -1
View File
@@ -1,5 +1,5 @@
/****************************************************************************************************
* arch/arm/include/stm32s/stm32f20xxx_irq.h
* arch/arm/include/stm32/stm32f20xxx_irq.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/include/stm32/stm32f30xxx_irq.h
+1 -1
View File
@@ -1,5 +1,5 @@
/****************************************************************************************************
* arch/arm/include/stm32s/stm32f30xxx_irq.h
* arch/arm/include/stm32/stm32f30xxx_irq.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/include/stm32/stm32f33xxx_irq.h
+185
View File
@@ -0,0 +1,185 @@
/****************************************************************************************************
* arch/arm/include/stm32/stm32f33xxx_irq.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Modified for STM32F334 by Mateusz Szafoni <raiden00@railab.me>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */
#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F33XXX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32_STM32F33XXX_IRQ_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in nuttx/arch/arm/include/stm32/irq.h
*
* External interrupts (vectors >= 16)
*/
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper interrupt, or */
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Time stamp interrupt */
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt, or */
#define STM32_IRQ_TSC (STM32_IRQ_FIRST+8) /* 8: TSC interrupt */
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST+11) /* 11: DMA1 channel 1 global interrupt */
#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST+12) /* 12: DMA1 channel 2 global interrupt */
#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST+13) /* 13: DMA1 channel 3 global interrupt */
#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST+14) /* 14: DMA1 channel 4 global interrupt */
#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST+15) /* 15: DMA1 channel 5 global interrupt */
#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST+16) /* 16: DMA1 channel 6 global interrupt */
#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST+17) /* 17: DMA1 channel 7 global interrupt */
#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST+18) /* 18: ADC1/ADC2 global interrupt */
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts*/
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt, or */
#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST+24) /* 24: TIM15 global interrupt */
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt, or */
#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST+25) /* 25: TIM16 global interrupt */
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts, or */
#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST+26) /* 26: TIM17 global interrupt */
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
#define STM32_IRQ_RESERVED30 (STM32_IRQ_FIRST+30) /* 30: Reserved */
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
#define STM32_IRQ_RESERVED33 (STM32_IRQ_FIRST+33) /* 33: Reserved */
#define STM32_IRQ_RESERVED34 (STM32_IRQ_FIRST+34) /* 34: Reserved */
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
#define STM32_IRQ_RESERVED36 (STM32_IRQ_FIRST+36) /* 36: Reserved */
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32_IRQ_RESERVED42 (STM32_IRQ_FIRST+42) /* 42: Reserved */
#define STM32_IRQ_RESERVED43 (STM32_IRQ_FIRST+43) /* 43: Reserved */
#define STM32_IRQ_RESERVED44 (STM32_IRQ_FIRST+44) /* 44: Reserved */
#define STM32_IRQ_RESERVED45 (STM32_IRQ_FIRST+45) /* 45: Reserved */
#define STM32_IRQ_RESERVED46 (STM32_IRQ_FIRST+46) /* 46: Reserved */
#define STM32_IRQ_RESERVED47 (STM32_IRQ_FIRST+47) /* 47: Reserved */
#define STM32_IRQ_RESERVED48 (STM32_IRQ_FIRST+48) /* 48: Reserved */
#define STM32_IRQ_RESERVED49 (STM32_IRQ_FIRST+49) /* 49: Reserved */
#define STM32_IRQ_RESERVED50 (STM32_IRQ_FIRST+50) /* 50: Reserved */
#define STM32_IRQ_RESERVED51 (STM32_IRQ_FIRST+51) /* 51: Reserved */
#define STM32_IRQ_RESERVED52 (STM32_IRQ_FIRST+52) /* 52: Reserved */
#define STM32_IRQ_RESERVED53 (STM32_IRQ_FIRST+53) /* 53: Reserved */
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt, or */
#define STM32_IRQ_DAC1 (STM32_IRQ_FIRST+54) /* 54: DAC1 underrun error interrupts */
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt, or */
#define STM32_IRQ_DAC2 (STM32_IRQ_FIRST+54) /* 55: DAC2 underrun error interrupts */
#define STM32_IRQ_RESERVED56 (STM32_IRQ_FIRST+56) /* 56: Reserved */
#define STM32_IRQ_RESERVED57 (STM32_IRQ_FIRST+57) /* 57: Reserved */
#define STM32_IRQ_RESERVED58 (STM32_IRQ_FIRST+58) /* 58: Reserved */
#define STM32_IRQ_RESERVED59 (STM32_IRQ_FIRST+59) /* 59: Reserved */
#define STM32_IRQ_RESERVED60 (STM32_IRQ_FIRST+60) /* 60: Reserved */
#define STM32_IRQ_RESERVED61 (STM32_IRQ_FIRST+61) /* 61: Reserved */
#define STM32_IRQ_RESERVED62 (STM32_IRQ_FIRST+62) /* 62: Reserved */
#define STM32_IRQ_RESERVED63 (STM32_IRQ_FIRST+63) /* 63: Reserved */
#define STM32_IRQ_COMP2 (STM32_IRQ_FIRST+64) /* 64: COMP2 interrupts, or */
#define STM32_IRQ_EXTI2129 (STM32_IRQ_FIRST+64) /* 64: EXTI Lines 21, 22 and 29 interrupts */
#define STM32_IRQ_COMP46 (STM32_IRQ_FIRST+65) /* 65: COMP4 & COMP6 interrupts, or */
#define STM32_IRQ_EXTI3012 (STM32_IRQ_FIRST+65) /* 65: EXTI Lines 30, 31 and 32 interrupts */
#define STM32_IRQ_RESERVED66 (STM32_IRQ_FIRST+66) /* 66: Reserved */
#define STM32_IRQ_HRTIMTM (STM32_IRQ_FIRST+67) /* 67: HRTIM master timer interrupt */
#define STM32_IRQ_HRTIMTA (STM32_IRQ_FIRST+68) /* 68: HRTIM timer A interrupt */
#define STM32_IRQ_HRTIMTB (STM32_IRQ_FIRST+69) /* 69: HRTIM timer B interrupt */
#define STM32_IRQ_HRTIMTC (STM32_IRQ_FIRST+70) /* 70: HRTIM timer C interrupt */
#define STM32_IRQ_HRTIMTD (STM32_IRQ_FIRST+71) /* 71: HRTIM timer D interrupt */
#define STM32_IRQ_HRTIMTE (STM32_IRQ_FIRST+72) /* 72: HRTIM timer E interrupt */
#define STM32_IRQ_HRTIMFLT (STM32_IRQ_FIRST+73) /* 73: HRTIM fault interrupt */
#define STM32_IRQ_RESERVED74 (STM32_IRQ_FIRST+74) /* 74: Reserved */
#define STM32_IRQ_RESERVED75 (STM32_IRQ_FIRST+75) /* 75: Reserved */
#define STM32_IRQ_RESERVED76 (STM32_IRQ_FIRST+76) /* 76: Reserved */
#define STM32_IRQ_RESERVED77 (STM32_IRQ_FIRST+77) /* 77: Reserved */
#define STM32_IRQ_RESERVED78 (STM32_IRQ_FIRST+78) /* 78: Reserved */
#define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST+79) /* 79: Reserved */
#define STM32_IRQ_RESERVED80 (STM32_IRQ_FIRST+80) /* 80: Reserved */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define NR_VECTORS (STM32_IRQ_FIRST+82)
#define NR_IRQS (STM32_IRQ_FIRST+82)
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32F30XXX_IRQ_H */
arch/arm/include/stm32/stm32f37xxx_irq.h
+1 -1
View File
@@ -1,5 +1,5 @@
/****************************************************************************************************
* arch/arm/include/stm32s/stm32f37xxx_irq.h
* arch/arm/include/stm32/stm32f37xxx_irq.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/include/stm32/stm32f40xxx_irq.h
+1 -1
View File
@@ -1,5 +1,5 @@
/****************************************************************************************************
* arch/arm/include/stm32s/stm32f40xxx_irq.h
* arch/arm/include/stm32/stm32f40xxx_irq.h
*
* Copyright (C) 2009, 2014-2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
arch/arm/include/stm32/stm32l15xxx_irq.h
+1 -1
View File
@@ -1,5 +1,5 @@
/****************************************************************************************************
* arch/arm/include/stm32s/stm32l15xxx_irq.h
* arch/arm/include/stm32/stm32l15xxx_irq.h
* For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based 32-bit MCUs
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
arch/arm/src/a1x/a1x_serial.c
+8 -95
View File
@@ -93,7 +93,6 @@ struct up_dev_s
uint32_t uartbase; /* Base address of UART registers */
uint32_t baud; /* Configured baud */
uint32_t ier; /* Saved IER value */
xcpt_t handler; /* UART interrupt handler */
uint8_t irq; /* IRQ associated with this UART */
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (7 or 8) */
@@ -108,31 +107,7 @@ static int up_setup(struct uart_dev_s *dev);
static void up_shutdown(struct uart_dev_s *dev);
static int up_attach(struct uart_dev_s *dev);
static void up_detach(struct uart_dev_s *dev);
static int uart_interrupt(struct uart_dev_s *dev);
#ifdef CONFIG_A1X_UART0
static int uart0_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_A1X_UART1
static int uart1_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_A1X_UART2
static int uart2_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_A1X_UART3
static int uart3_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_A1X_UART4
static int uart4_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_A1X_UART5
static int uart5_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_A1X_UART6
static int uart6_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_A1X_UART7
static int uart7_interrupt(int irq, void *context);
#endif
static int uart_interrupt(int irq, void *context, void *arg);
static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
static int up_receive(struct uart_dev_s *dev, uint32_t *status);
static void up_rxint(struct uart_dev_s *dev, bool enable);
@@ -214,7 +189,6 @@ static struct up_dev_s g_uart0priv =
{
.uartbase = A1X_UART0_VADDR,
.baud = CONFIG_UART0_BAUD,
.handler = uart0_interrupt,
.irq = A1X_IRQ_UART0,
.parity = CONFIG_UART0_PARITY,
.bits = CONFIG_UART0_BITS,
@@ -245,7 +219,6 @@ static struct up_dev_s g_uart1priv =
{
.uartbase = A1X_UART1_VADDR,
.baud = CONFIG_UART1_BAUD,
.handler = uart1_interrupt,
.irq = A1X_IRQ_UART1,
.parity = CONFIG_UART1_PARITY,
.bits = CONFIG_UART1_BITS,
@@ -276,7 +249,6 @@ static struct up_dev_s g_uart2priv =
{
.uartbase = A1X_UART2_VADDR,
.baud = CONFIG_UART2_BAUD,
.handler = uart2_interrupt,
.irq = A1X_IRQ_UART2,
.parity = CONFIG_UART2_PARITY,
.bits = CONFIG_UART2_BITS,
@@ -307,7 +279,6 @@ static struct up_dev_s g_uart3priv =
{
.uartbase = A1X_UART3_VADDR,
.baud = CONFIG_UART3_BAUD,
.handler = uart3_interrupt,
.irq = A1X_IRQ_UART3,
.parity = CONFIG_UART3_PARITY,
.bits = CONFIG_UART3_BITS,
@@ -338,7 +309,6 @@ static struct up_dev_s g_uart4priv =
{
.uartbase = A1X_UART4_VADDR,
.baud = CONFIG_UART4_BAUD,
.handler = uart4_interrupt,
.irq = A1X_IRQ_UART4,
.parity = CONFIG_UART4_PARITY,
.bits = CONFIG_UART4_BITS,
@@ -369,7 +339,6 @@ static struct up_dev_s g_uart5priv =
{
.uartbase = A1X_UART5_VADDR,
.baud = CONFIG_UART5_BAUD,
.handler = uart5_interrupt,
.irq = A1X_IRQ_UART5,
.parity = CONFIG_UART5_PARITY,
.bits = CONFIG_UART5_BITS,
@@ -400,7 +369,6 @@ static struct up_dev_s g_uart6priv =
{
.uartbase = A1X_UART6_VADDR,
.baud = CONFIG_UART6_BAUD,
.handler = uart6_interrupt,
.irq = A1X_IRQ_UART6,
.parity = CONFIG_UART6_PARITY,
.bits = CONFIG_UART6_BITS,
@@ -431,7 +399,6 @@ static struct up_dev_s g_uart7priv =
{
.uartbase = A1X_UART7_VADDR,
.baud = CONFIG_UART7_BAUD,
.handler = uart7_interrupt,
.irq = A1X_IRQ_UART7,
.parity = CONFIG_UART7_PARITY,
.bits = CONFIG_UART7_BITS,
@@ -1068,7 +1035,7 @@ static int up_attach(struct uart_dev_s *dev)
/* Attach and enable the IRQ */
ret = irq_attach(priv->irq, priv->handler);
ret = irq_attach(priv->irq, uart_interrupt, priv);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled
@@ -1110,12 +1077,14 @@ static void up_detach(struct uart_dev_s *dev)
*
****************************************************************************/
static int uart_interrupt(struct uart_dev_s *dev)
static int uart_interrupt(int irq, void *context, void *arg)
{
struct up_dev_s *priv;
uint32_t status;
int passes;
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
struct up_dev_s *priv = (struct up_dev_s *)arg;
uint32_t status;
int passes;
DEBUGASSERT(dev != NULL && dev->priv != NULL);
priv = (struct up_dev_s *)dev->priv;
/* Loop until there are no characters to be transferred or,
@@ -1201,62 +1170,6 @@ static int uart_interrupt(struct uart_dev_s *dev)
return OK;
}
#ifdef CONFIG_A1X_UART0
static int uart0_interrupt(int irq, void *context)
{
return uart_interrupt(&g_uart0port);
}
#endif
#ifdef CONFIG_A1X_UART1
static int uart1_interrupt(int irq, void *context)
{
return uart_interrupt(&g_uart1port);
}
#endif
#ifdef CONFIG_A1X_UART2
static int uart2_interrupt(int irq, void *context)
{
return uart_interrupt(&g_uart2port);
}
#endif
#ifdef CONFIG_A1X_UART3
static int uart3_interrupt(int irq, void *context)
{
return uart_interrupt(&g_uart3port);
}
#endif
#ifdef CONFIG_A1X_UART4
static int uart4_interrupt(int irq, void *context)
{
return uart_interrupt(&g_uart4port);
}
#endif
#ifdef CONFIG_A1X_UART5
static int uart5_interrupt(int irq, void *context)
{
return uart_interrupt(&g_uart5port);
}
#endif
#ifdef CONFIG_A1X_UART6
static int uart6_interrupt(int irq, void *context)
{
return uart_interrupt(&g_uart6port);
}
#endif
#ifdef CONFIG_A1X_UART7
static int uart7_interrupt(int irq, void *context)
{
return uart_interrupt(&g_uart7port);
}
#endif
/****************************************************************************
* Name: up_ioctl
*
arch/arm/src/a1x/a1x_timerisr.c
+2 -2
View File
@@ -82,7 +82,7 @@
*
****************************************************************************/
static int a1x_timerisr(int irq, uint32_t *regs)
static int a1x_timerisr(int irq, uint32_t *regs, void *arg)
{
/* Only a TIMER0 interrupt is expected here */
@@ -138,7 +138,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
(void)irq_attach(A1X_IRQ_TIMER0, (xcpt_t)a1x_timerisr);
(void)irq_attach(A1X_IRQ_TIMER0, (xcpt_t)a1x_timerisr, NULL);
/* Enable interrupts from the TIMER 0 port */
arch/arm/src/armv6-m/up_hardfault.c
+2 -2
View File
@@ -75,7 +75,7 @@
*
****************************************************************************/
int up_hardfault(int irq, FAR void *context)
int up_hardfault(int irq, FAR void *context, FAR void *arg)
{
uint32_t *regs = (uint32_t *)context;
@@ -115,7 +115,7 @@ int up_hardfault(int irq, FAR void *context)
if (insn == INSN_SVC0)
{
hfinfo("Forward SVCall\n");
return up_svcall(irq, context);
return up_svcall(irq, context, NULL);
}
}
arch/arm/src/armv6-m/up_svcall.c
+1 -1
View File
@@ -130,7 +130,7 @@ static void dispatch_syscall(void)
*
****************************************************************************/
int up_svcall(int irq, FAR void *context)
int up_svcall(int irq, FAR void *context, FAR void *arg)
{
uint32_t *regs = (uint32_t *)context;
uint32_t cmd;
arch/arm/src/armv7-a/arm_cpupause.c
+1 -1
View File
@@ -202,7 +202,7 @@ int up_cpu_paused(int cpu)
*
****************************************************************************/
int arm_pause_handler(int irq, FAR void *context)
int arm_pause_handler(int irq, FAR void *context, FAR void *arg)
{
int cpu = this_cpu();
arch/arm/src/armv7-a/arm_cpustart.c
+1 -1
View File
@@ -103,7 +103,7 @@ static inline void arm_registerdump(FAR struct tcb_s *tcb)
*
****************************************************************************/
int arm_start_handler(int irq, FAR void *context)
int arm_start_handler(int irq, FAR void *context, FAR void *arg)
{
FAR struct tcb_s *tcb = this_task();
arch/arm/src/armv7-a/arm_gicv2.c
+2 -2
View File
@@ -124,8 +124,8 @@ void arm_gic0_initialize(void)
#ifdef CONFIG_SMP
/* Attach SGI interrupt handlers. This attaches the handler for all CPUs. */
DEBUGVERIFY(irq_attach(GIC_IRQ_SGI1, arm_start_handler));
DEBUGVERIFY(irq_attach(GIC_IRQ_SGI2, arm_pause_handler));
DEBUGVERIFY(irq_attach(GIC_IRQ_SGI1, arm_start_handler, NULL));
DEBUGVERIFY(irq_attach(GIC_IRQ_SGI2, arm_pause_handler, NULL));
#endif
arm_gic_dump("Exit arm_gic0_initialize", true, 0);
arch/arm/src/armv7-a/gic.h
+2 -2
View File
@@ -759,7 +759,7 @@ uint32_t *arm_decodeirq(uint32_t *regs);
****************************************************************************/
#ifdef CONFIG_SMP
int arm_start_handler(int irq, FAR void *context);
int arm_start_handler(int irq, FAR void *context, FAR void *arg);
#endif
/****************************************************************************
@@ -783,7 +783,7 @@ int arm_start_handler(int irq, FAR void *context);
****************************************************************************/
#ifdef CONFIG_SMP
int arm_pause_handler(int irq, FAR void *context);
int arm_pause_handler(int irq, FAR void *context, FAR void *arg);
#endif
/****************************************************************************
arch/arm/src/armv7-m/up_hardfault.c
+2 -2
View File
@@ -80,7 +80,7 @@
*
****************************************************************************/
int up_hardfault(int irq, FAR void *context)
int up_hardfault(int irq, FAR void *context, FAR void *arg)
{
#if defined(CONFIG_DEBUG_HARDFAULT) || !defined(CONFIG_ARMV7M_USEBASEPRI)
uint32_t *regs = (uint32_t *)context;
@@ -124,7 +124,7 @@ int up_hardfault(int irq, FAR void *context)
if (insn == INSN_SVC0)
{
hfalert("Forward SVCall\n");
return up_svcall(irq, context);
return up_svcall(irq, context, arg);
}
}
#endif
arch/arm/src/armv7-m/up_memfault.c
+1 -1
View File
@@ -77,7 +77,7 @@
*
****************************************************************************/
int up_memfault(int irq, FAR void *context)
int up_memfault(int irq, FAR void *context, FAR void *arg)
{
/* Dump some memory management fault info */
arch/arm/src/armv7-m/up_svcall.c
+1 -1
View File
@@ -125,7 +125,7 @@ static void dispatch_syscall(void)
*
****************************************************************************/
int up_svcall(int irq, FAR void *context)
int up_svcall(int irq, FAR void *context, FAR void *arg)
{
uint32_t *regs = (uint32_t *)context;
uint32_t cmd;
arch/arm/src/c5471/c5471_ethernet.c
+3 -3
View File
@@ -401,7 +401,7 @@ static void c5471_txstatus(struct c5471_driver_s *priv);
static void c5471_txdone(struct c5471_driver_s *priv);
static void c5471_interrupt_work(FAR void *arg);
static int c5471_interrupt(int irq, FAR void *context);
static int c5471_interrupt(int irq, FAR void *context, FAR void *arg);
/* Watchdog timer expirations */
@@ -1634,7 +1634,7 @@ static void c5471_interrupt_work(FAR void *arg)
*
****************************************************************************/
static int c5471_interrupt(int irq, FAR void *context)
static int c5471_interrupt(int irq, FAR void *context, FAR void *arg)
{
#if CONFIG_C5471_NET_NINTERFACES == 1
register struct c5471_driver_s *priv = &g_c5471[0];
@@ -2449,7 +2449,7 @@ void up_netinitialize(void)
{
/* Attach the IRQ to the driver */
if (irq_attach(C5471_IRQ_ETHER, c5471_interrupt))
if (irq_attach(C5471_IRQ_ETHER, c5471_interrupt, NULL))
{
/* We could not attach the ISR to the ISR */
arch/arm/src/c5471/c5471_serial.c
+5 -16
View File
@@ -108,7 +108,7 @@ static int up_setup(struct uart_dev_s *dev);
static void up_shutdown(struct uart_dev_s *dev);
static int up_attach(struct uart_dev_s *dev);
static void up_detach(struct uart_dev_s *dev);
static int up_interrupt(int irq, void *context);
static int up_interrupt(int irq, void *context, void *arg);
static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
static int up_receive(struct uart_dev_s *dev, unsigned int *status);
static void up_rxint(struct uart_dev_s *dev, bool enable);
@@ -491,7 +491,7 @@ static int up_attach(struct uart_dev_s *dev)
/* Attach and enable the IRQ */
ret = irq_attach(priv->irq, up_interrupt);
ret = irq_attach(priv->irq, up_interrupt, dev);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled
@@ -534,24 +534,13 @@ static void up_detach(struct uart_dev_s *dev)
*
****************************************************************************/
static int up_interrupt(int irq, void *context)
static int up_interrupt(int irq, void *context, void *arg)
{
struct uart_dev_s *dev = NULL;
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
struct up_dev_s *priv;
volatile uint32_t cause;
if (g_irdapriv.irq == irq)
{
dev = &g_irdaport;
}
else if (g_modempriv.irq == irq)
{
dev = &g_modemport;
}
else
{
PANIC();
}
DEBUGASSERT(dev != NULL && dev->priv != NULL);
priv = (struct up_dev_s *)dev->priv;
cause = up_inserial(priv, UART_ISR_OFFS) & 0x0000003f;
arch/arm/src/c5471/c5471_timerisr.c
+2 -2
View File
@@ -82,7 +82,7 @@
*
****************************************************************************/
static int c5471_timerisr(int irq, uint32_t *regs)
static int c5471_timerisr(int irq, uint32_t *regs, FAR void *arg)
{
/* Process timer interrupt */
@@ -118,6 +118,6 @@ void arm_timer_initialize(void)
/* Attach and enable the timer interrupt */
irq_attach(C5471_IRQ_SYSTIMER, (xcpt_t)c5471_timerisr);
irq_attach(C5471_IRQ_SYSTIMER, (xcpt_t)c5471_timerisr, NULL);
up_enable_irq(C5471_IRQ_SYSTIMER);
}
arch/arm/src/c5471/c5471_watchdog.c
+3 -3
View File
@@ -95,7 +95,7 @@
static inline unsigned int wdt_prescaletoptv(unsigned int prescale);
static int wdt_setusec(uint32_t usec);
static int wdt_interrupt(int irq, void *context);
static int wdt_interrupt(int irq, void *context, FAR void *arg);
static int wdt_open(struct file *filep);
static int wdt_close(struct file *filep);
@@ -232,7 +232,7 @@ static int wdt_setusec(uint32_t usec)
* Name: wdt_interrupt
****************************************************************************/
static int wdt_interrupt(int irq, void *context)
static int wdt_interrupt(int irq, void *context, FAR void *arg)
{
wdinfo("expired\n");
@@ -382,7 +382,7 @@ int up_wdtinit(void)
/* Request the interrupt. */
ret = irq_attach(C5471_IRQ_WATCHDOG, wdt_interrupt);
ret = irq_attach(C5471_IRQ_WATCHDOG, wdt_interrupt, NULL);
if (ret)
{
unregister_driver("/dev/wdt");
arch/arm/src/common/up_internal.h
+3 -3
View File
@@ -374,13 +374,13 @@ uint32_t *up_doirq(int irq, uint32_t *regs);
/* Exception Handlers */
int up_svcall(int irq, FAR void *context);
int up_hardfault(int irq, FAR void *context);
int up_svcall(int irq, FAR void *context, FAR void *arg);
int up_hardfault(int irq, FAR void *context, FAR void *arg);
# if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4) || \
defined(CONFIG_ARCH_CORTEXM7)
int up_memfault(int irq, FAR void *context);
int up_memfault(int irq, FAR void *context, FAR void *arg);
# endif /* CONFIG_ARCH_CORTEXM3,4,7 */
arch/arm/src/dm320/dm320_serial.c
+6 -18
View File
@@ -1,8 +1,7 @@
/****************************************************************************
* arch/arm/src/dm320/dm320_serial.c
* arch/arm/src/chip/dm320_serial.c
*
* Copyright (C) 2007-2009, 2012-2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2009, 2012-2013, 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -89,7 +88,7 @@ static int up_setup(struct uart_dev_s *dev);
static void up_shutdown(struct uart_dev_s *dev);
static int up_attach(struct uart_dev_s *dev);
static void up_detach(struct uart_dev_s *dev);
static int up_interrupt(int irq, void *context);
static int up_interrupt(int irq, void *context, void *arg);
static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
static int up_receive(struct uart_dev_s *dev, uint32_t *status);
static void up_rxint(struct uart_dev_s *dev, bool enable);
@@ -430,7 +429,7 @@ static int up_attach(struct uart_dev_s *dev)
/* Attach and enable the IRQ */
ret = irq_attach(priv->irq, up_interrupt);
ret = irq_attach(priv->irq, up_interrupt, dev);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled
@@ -472,25 +471,14 @@ static void up_detach(struct uart_dev_s *dev)
*
****************************************************************************/
static int up_interrupt(int irq, void *context)
static int up_interrupt(int irq, void *context, void *arg)
{
struct uart_dev_s *dev = NULL;
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
struct up_dev_s *priv;
uint16_t status;
int passes = 0;
if (g_uart1priv.irq == irq)
{
dev = &g_uart1port;
}
else if (g_uart0priv.irq == irq)
{
dev = &g_uart0port;
}
else
{
PANIC();
}
DEBUGASSERT(dev != NULL && dev->priv != NULL);
priv = (struct up_dev_s *)dev->priv;
/* Loop until there are no characters to be transferred or,
arch/arm/src/dm320/dm320_timerisr.c
+2 -2
View File
@@ -109,7 +109,7 @@
*
****************************************************************************/
static int dm320_timerisr(int irq, uint32_t *regs)
static int dm320_timerisr(int irq, uint32_t *regs, FAR void *arg)
{
/* Process timer interrupt */
@@ -147,7 +147,7 @@ void arm_timer_initialize(void)
/* Attach and enable the timer interrupt */
irq_attach(DM320_IRQ_SYSTIMER, (xcpt_t)dm320_timerisr);
irq_attach(DM320_IRQ_SYSTIMER, (xcpt_t)dm320_timerisr, NULL);
up_enable_irq(DM320_IRQ_SYSTIMER);
}
arch/arm/src/dm320/dm320_usbdev.c
+6 -6
View File
@@ -309,8 +309,8 @@ static void dm320_dispatchrequest(struct dm320_usbdev_s *priv,
const struct usb_ctrlreq_s *ctrl);
static inline void dm320_ep0setup(struct dm320_usbdev_s *priv);
static inline uint32_t dm320_highestpriinterrupt(int intstatus);
static int dm320_ctlrinterrupt(int irq, FAR void *context);
static int dm320_attachinterrupt(int irq, FAR void *context);
static int dm320_ctlrinterrupt(int irq, FAR void *context, FAR void *arg);
static int dm320_attachinterrupt(int irq, FAR void *context, FAR void *arg);
/* Initialization operations */
@@ -1513,7 +1513,7 @@ static inline uint32_t dm320_highestpriinterrupt(int intstatus)
*
****************************************************************************/
static int dm320_ctlrinterrupt(int irq, FAR void *context)
static int dm320_ctlrinterrupt(int irq, FAR void *context, FAR void *arg)
{
struct dm320_usbdev_s *priv = &g_usbdev;
struct dm320_ep_s *privep ;
@@ -1680,7 +1680,7 @@ static int dm320_ctlrinterrupt(int irq, FAR void *context)
*
****************************************************************************/
static int dm320_attachinterrupt(int irq, FAR void *context)
static int dm320_attachinterrupt(int irq, FAR void *context, FAR void *arg)
{
struct dm320_usbdev_s *priv = &g_usbdev;
uint16_t gio;
@@ -2438,7 +2438,7 @@ void up_usbinitialize(void)
/* Attach host attach GIO interrupt */
if (irq_attach(IRQ_USBATTACH, dm320_attachinterrupt) != 0)
if (irq_attach(IRQ_USBATTACH, dm320_attachinterrupt, NULL) != 0)
{
usbtrace(TRACE_DEVERROR(DM320_TRACEERR_ATTACHIRQREG), 0);
goto errout;
@@ -2448,7 +2448,7 @@ void up_usbinitialize(void)
* enabled when the driver is bound
*/
if (irq_attach(DM320_IRQ_USB1, dm320_ctlrinterrupt) != 0)
if (irq_attach(DM320_IRQ_USB1, dm320_ctlrinterrupt, NULL) != 0)
{
usbtrace(TRACE_DEVERROR(DM320_TRACEERR_COREIRQREG), 0);
goto errout;
arch/arm/src/efm32/efm32_adc.c
+3 -3
View File
@@ -123,7 +123,7 @@ static void adc_hw_reset(struct efm32_dev_s *priv, bool reset);
/* ADC Interrupt Handler */
static int adc_interrupt(FAR struct adc_dev_s *dev);
static int adc_interrupt(int irq, FAR void *context, FAR struct adc_dev_s *dev);
/* ADC Driver Methods */
@@ -1072,7 +1072,7 @@ static int adc_setup(FAR struct adc_dev_s *dev)
/* Attach the ADC interrupt */
ret = irq_attach(priv->irq, priv->isr);
ret = irq_attach(priv->irq, priv->isr, dev);
if (ret == OK)
{
/* Make sure that the ADC device is in the powered up, reset state */
@@ -1180,7 +1180,7 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
*
****************************************************************************/
static int adc_interrupt(FAR struct adc_dev_s *dev)
static int adc_interrupt(int irq, FAR void *context, FAR struct adc_dev_s *dev)
{
FAR struct efm32_dev_s *priv = (FAR struct efm32_dev_s *)dev->ad_priv;
uint32_t adcsr;
arch/arm/src/efm32/efm32_dma.c
+2 -2
View File
@@ -204,7 +204,7 @@ efm32_get_descriptor(struct dma_channel_s *dmach, bool alt)
*
****************************************************************************/
static int efm32_dmac_interrupt(int irq, void *context)
static int efm32_dmac_interrupt(int irq, void *context, FAR void *arg)
{
struct dma_channel_s *dmach;
unsigned int chndx;
@@ -297,7 +297,7 @@ void weak_function up_dmainitialize(void)
/* Attach DMA interrupt vector */
(void)irq_attach(EFM32_IRQ_DMA, efm32_dmac_interrupt);
(void)irq_attach(EFM32_IRQ_DMA, efm32_dmac_interrupt, NULL);
/* Enable the DMA controller */
arch/arm/src/efm32/efm32_gpioirq.c
+4 -4
View File
@@ -133,7 +133,7 @@ static int efm32_gpio_interrupt(uint32_t mask, void *context)
*
************************************************************************************/
static int efm32_even_interrupt(int irq, void *context)
static int efm32_even_interrupt(int irq, void *context, FAR void *arg)
{
return efm32_gpio_interrupt(0x00005555, context);
}
@@ -146,7 +146,7 @@ static int efm32_even_interrupt(int irq, void *context)
*
************************************************************************************/
static int efm32_odd_interrupt(int irq, void *context)
static int efm32_odd_interrupt(int irq, void *context, FAR void *arg)
{
return efm32_gpio_interrupt(0x0000aaaa, context);
}
@@ -173,8 +173,8 @@ void efm32_gpioirqinitialize(void)
/* Attach the even and odd interrupt handlers */
DEBUGVERIFY(irq_attach(EFM32_IRQ_GPIO_EVEN, efm32_even_interrupt));
DEBUGVERIFY(irq_attach(EFM32_IRQ_GPIO_ODD, efm32_odd_interrupt));
DEBUGVERIFY(irq_attach(EFM32_IRQ_GPIO_EVEN, efm32_even_interrupt, NULL));
DEBUGVERIFY(irq_attach(EFM32_IRQ_GPIO_ODD, efm32_odd_interrupt, NULL));
/* Enable GPIO even and odd interrupts at the NVIC */
arch/arm/src/efm32/efm32_i2c.c
+6 -6
View File
@@ -220,7 +220,7 @@ struct efm32_i2c_config_s
uint32_t scl_pin; /* GPIO configuration for SCL as SCL */
uint32_t sda_pin; /* GPIO configuration for SDA as SDA */
#ifndef CONFIG_I2C_POLLED
int (*isr) (int, void *); /* Interrupt handler */
int (*isr) (int, void *, void *); /* Interrupt handler */
uint32_t irq; /* Event IRQ */
#endif
};
@@ -298,10 +298,10 @@ static int efm32_i2c_isr(struct efm32_i2c_priv_s *priv);
#ifndef CONFIG_I2C_POLLED
#ifdef CONFIG_EFM32_I2C0
static int efm32_i2c0_isr(int irq, void *context);
static int efm32_i2c0_isr(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_EFM32_I2C1
static int efm32_i2c1_isr(int irq, void *context);
static int efm32_i2c1_isr(int irq, void *context, FAR void *arg);
#endif
#endif /* !CONFIG_I2C_POLLED */
@@ -1290,7 +1290,7 @@ done:
****************************************************************************/
#ifdef CONFIG_EFM32_I2C0
static int efm32_i2c0_isr(int irq, void *context)
static int efm32_i2c0_isr(int irq, void *context, FAR void *arg)
{
return efm32_i2c_isr(&efm32_i2c0_priv);
}
@@ -1305,7 +1305,7 @@ static int efm32_i2c0_isr(int irq, void *context)
****************************************************************************/
#ifdef CONFIG_EFM32_I2C1
static int efm32_i2c1_isr(int irq, void *context)
static int efm32_i2c1_isr(int irq, void *context, FAR void *arg)
{
return efm32_i2c_isr(&efm32_i2c1_priv);
}
@@ -1389,7 +1389,7 @@ static int efm32_i2c_init(FAR struct efm32_i2c_priv_s *priv)
/* Attach ISRs */
#ifndef CONFIG_I2C_POLLED
irq_attach(priv->config->irq, priv->config->isr);
irq_attach(priv->config->irq, priv->config->isr, NULL);
up_enable_irq(priv->config->irq);
#endif
arch/arm/src/efm32/efm32_irq.c
+16 -16
View File
@@ -163,7 +163,7 @@ static void efm32_dumpnvic(const char *msg, int irq)
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
static int efm32_nmi(int irq, FAR void *context)
static int efm32_nmi(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! NMI received\n");
@@ -171,7 +171,7 @@ static int efm32_nmi(int irq, FAR void *context)
return 0;
}
static int efm32_busfault(int irq, FAR void *context)
static int efm32_busfault(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
@@ -179,7 +179,7 @@ static int efm32_busfault(int irq, FAR void *context)
return 0;
}
static int efm32_usagefault(int irq, FAR void *context)
static int efm32_usagefault(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
@@ -187,7 +187,7 @@ static int efm32_usagefault(int irq, FAR void *context)
return 0;
}
static int efm32_pendsv(int irq, FAR void *context)
static int efm32_pendsv(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! PendSV received\n");
@@ -195,7 +195,7 @@ static int efm32_pendsv(int irq, FAR void *context)
return 0;
}
static int efm32_dbgmonitor(int irq, FAR void *context)
static int efm32_dbgmonitor(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! Debug Monitor received\n");
@@ -203,7 +203,7 @@ static int efm32_dbgmonitor(int irq, FAR void *context)
return 0;
}
static int efm32_reserved(int irq, FAR void *context)
static int efm32_reserved(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
@@ -382,8 +382,8 @@ void up_irqinitialize(void)
* under certain conditions.
*/
irq_attach(EFM32_IRQ_SVCALL, up_svcall);
irq_attach(EFM32_IRQ_HARDFAULT, up_hardfault);
irq_attach(EFM32_IRQ_SVCALL, up_svcall, NULL);
irq_attach(EFM32_IRQ_HARDFAULT, up_hardfault, NULL);
/* Set the priority of the SVCall interrupt */
@@ -396,22 +396,22 @@ void up_irqinitialize(void)
*/
#ifdef CONFIG_ARM_MPU
irq_attach(EFM32_IRQ_MEMFAULT, up_memfault);
irq_attach(EFM32_IRQ_MEMFAULT, up_memfault, NULL);
up_enable_irq(EFM32_IRQ_MEMFAULT);
#endif
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG_FEATURES
irq_attach(EFM32_IRQ_NMI, efm32_nmi);
irq_attach(EFM32_IRQ_NMI, efm32_nmi, NULL);
#ifndef CONFIG_ARM_MPU
irq_attach(EFM32_IRQ_MEMFAULT, up_memfault);
irq_attach(EFM32_IRQ_MEMFAULT, up_memfault, NULL);
#endif
irq_attach(EFM32_IRQ_BUSFAULT, efm32_busfault);
irq_attach(EFM32_IRQ_USAGEFAULT, efm32_usagefault);
irq_attach(EFM32_IRQ_PENDSV, efm32_pendsv);
irq_attach(EFM32_IRQ_DBGMONITOR, efm32_dbgmonitor);
irq_attach(EFM32_IRQ_RESERVED, efm32_reserved);
irq_attach(EFM32_IRQ_BUSFAULT, efm32_busfault, NULL);
irq_attach(EFM32_IRQ_USAGEFAULT, efm32_usagefault, NULL);
irq_attach(EFM32_IRQ_PENDSV, efm32_pendsv, NULL);
irq_attach(EFM32_IRQ_DBGMONITOR, efm32_dbgmonitor, NULL);
irq_attach(EFM32_IRQ_RESERVED, efm32_reserved, NULL);
#endif
efm32_dumpnvic("initial", NR_VECTORS);
arch/arm/src/efm32/efm32_leserial.c
+7 -28
View File
@@ -134,7 +134,6 @@
struct efm32_config_s
{
uintptr_t uartbase; /* Base address of UART registers */
xcpt_t handler; /* Interrupt handler */
uint32_t baud; /* Configured baud */
uint8_t irq; /* IRQ associated with this LEUART (for enable) */
uint8_t parity; /* 0=none, 1=odd, 2=even */
@@ -163,13 +162,7 @@ static int efm32_setup(struct uart_dev_s *dev);
static void efm32_shutdown(struct uart_dev_s *dev);
static int efm32_attach(struct uart_dev_s *dev);
static void efm32_detach(struct uart_dev_s *dev);
static int efm32_interrupt(struct uart_dev_s *dev);
#if defined(CONFIG_EFM32_LEUART0)
static int efm32_leuart0_interrupt(int irq, void *context);
#endif
#if defined(CONFIG_EFM32_LEUART1)
static int efm32_leuart1_interrupt(int irq, void *context);
#endif
static int efm32_interrupt(int irq, void *context, FAR void *arg);
static int efm32_ioctl(struct file *filep, int cmd, unsigned long arg);
static int efm32_receive(struct uart_dev_s *dev, uint32_t *status);
static void efm32_rxint(struct uart_dev_s *dev, bool enable);
@@ -219,7 +212,6 @@ static char g_leuart1txbuffer[CONFIG_LEUART1_TXBUFSIZE];
static const struct efm32_config_s g_leuart0config =
{
.uartbase = EFM32_LEUART0_BASE,
.handler = efm32_leuart0_interrupt,
.baud = CONFIG_LEUART0_BAUD,
.irq = EFM32_IRQ_LEUART0,
.parity = CONFIG_LEUART0_PARITY,
@@ -255,7 +247,6 @@ static struct uart_dev_s g_leuart0port =
static struct efm32_config_s g_leuart1config =
{
.uartbase = EFM32_LEUART1_BASE,
.handler = efm32_leuart1_interrupt,
.baud = CONFIG_LEUART1_BAUD,
.irq = EFM32_IRQ_LEUART1,
.parity = CONFIG_LEUART1_PARITY,
@@ -429,7 +420,7 @@ static int efm32_attach(struct uart_dev_s *dev)
* disabled in the C2 register.
*/
ret = irq_attach(config->irq, config->handler);
ret = irq_attach(config->irq, efm32_interrupt, dev);
if (ret >= 0)
{
up_enable_irq(config->irq);
@@ -471,12 +462,14 @@ static void efm32_detach(struct uart_dev_s *dev)
*
****************************************************************************/
static int efm32_interrupt(struct uart_dev_s *dev)
static int efm32_interrupt(int irq, void *context, FAR void *arg)
{
struct efm32_leuart_s *priv = (struct efm32_leuart_s *)dev->priv;
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
struct efm32_leuart_s *priv;
uint32_t intflags;
DEBUGASSERT(priv);
DEBUGASSERT(dev != NULL && dev->priv != NULL);
priv = (struct efm32_leuart_s *)dev->priv;
/* Read the interrupt flags register */
@@ -534,20 +527,6 @@ static int efm32_interrupt(struct uart_dev_s *dev)
return OK;
}
#if defined(CONFIG_EFM32_LEUART0)
static int efm32_leuart0_interrupt(int irq, void *context)
{
return efm32_interrupt(&g_leuart0port);
}
#endif
#if defined(CONFIG_EFM32_LEUART1)
static int efm32_leuart1_interrupt(int irq, void *context)
{
return efm32_interrupt(&g_leuart1port);
}
#endif
/****************************************************************************
* Name: efm32_ioctl
*
arch/arm/src/efm32/efm32_pwm.c
+13 -85
View File
@@ -133,19 +133,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
defined(CONFIG_EFM32_TIMER2_PWM) || \
defined(CONFIG_EFM32_TIMER3_PWM) \
)
static int pwm_interrupt(struct efm32_pwmtimer_s *priv);
#if defined(CONFIG_EFM32_TIMER0_PWM)
static int pwm_timer0_interrupt(int irq, void *context);
#endif
#if defined(CONFIG_EFM32_TIMER1_PWM)
static int pwm_timer1_interrupt(int irq, void *context);
#endif
#if defined(CONFIG_EFM32_TIMER2_PWM)
static int pwm_timer2_interrupt(int irq, void *context);
#endif
#if defined(CONFIG_EFM32_TIMER3_PWM)
static int pwm_timer3_interrupt(int irq, void *context);
#endif
static int pwm_interrupt(int irq, void *context, FAR void *arg);
static uint8_t pwm_pulsecount(uint32_t count);
#endif
@@ -446,7 +434,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
* Handle timer interrupts.
*
* Input parameters:
* priv - A reference to the lower half PWM driver state structure
* Standard interrupt handler arguments.
*
* Returned Value:
* Zero on success; a negated errno value on failure
@@ -459,12 +447,15 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
defined(CONFIG_EFM32_TIMER3_PWM) \
)
#warning "not yet implemented"
static int pwm_interrupt(struct efm32_pwmtimer_s *priv)
static int pwm_interrupt(int irq, void *context, FAR void *arg)
{
/* TODO pwm_interrupt */
#if 0
struct efm32_pwmtimer_s *priv = (struct efm32_pwmtimer_s *)arg;
uint32_t regval;
DEBUGASSERT(priv != NULL);
/* Verify that this is an update interrupt. Nothing else is expected. */
regval = pwm_getreg(priv, STM32_ATIM_SR_OFFSET);
@@ -532,48 +523,6 @@ static int pwm_interrupt(struct efm32_pwmtimer_s *priv)
}
#endif
/****************************************************************************
* Name: pwm_timer1/3_interrupt
*
* Description:
* Handle timer 1..3 interrupts.
*
* Input parameters:
* Standard NuttX interrupt inputs
*
* Returned Value:
* Zero on success; a negated errno value on failure
*
****************************************************************************/
#if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_EFM32_TIMER0_PWM)
static int pwm_timer0_interrupt(int irq, void *context)
{
return pwm_interrupt(&g_pwm0dev);
}
#endif
#if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_EFM32_TIMER1_PWM)
static int pwm_timer1_interrupt(int irq, void *context)
{
return pwm_interrupt(&g_pwm1dev);
}
#endif
#if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_EFM32_TIMER2_PWM)
static int pwm_timer2_interrupt(int irq, void *context)
{
return pwm_interrupt(&g_pwm2dev);
}
#endif
#if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_EFM32_TIMER3_PWM)
static int pwm_timer3_interrupt(int irq, void *context)
{
return pwm_interrupt(&g_pwm3dev);
}
#endif
/****************************************************************************
* Name: pwm_pulsecount
*
@@ -866,50 +815,22 @@ FAR struct pwm_lowerhalf_s *efm32_pwminitialize(int timer)
#ifdef CONFIG_EFM32_TIMER0_PWM
case 0:
lower = &g_pwm0dev;
/* Attach but disable the TIM1 update interrupt */
#ifdef CONFIG_PWM_PULSECOUNT
irq_attach(lower->irq, pwm_timer0_interrupt);
up_disable_irq(lower->irq);
#endif
break;
#endif
#ifdef CONFIG_EFM32_TIMER1_PWM
case 1:
lower = &g_pwm1dev;
/* Attach but disable the TIM1 update interrupt */
#ifdef CONFIG_PWM_PULSECOUNT
irq_attach(lower->irq, pwm_timer0_interrupt);
up_disable_irq(lower->irq);
#endif
break;
#endif
#ifdef CONFIG_EFM32_TIMER2_PWM
case 2:
lower = &g_pwm2dev;
/* Attach but disable the TIM1 update interrupt */
#ifdef CONFIG_PWM_PULSECOUNT
irq_attach(lower->irq, pwm_timer2_interrupt);
up_disable_irq(lower->irq);
#endif
break;
#endif
#ifdef CONFIG_EFM32_TIMER3_PWM
case 3:
lower = &g_pwm3dev;
/* Attach but disable the TIM1 update interrupt */
#ifdef CONFIG_PWM_PULSECOUNT
irq_attach(lower->irq, pwm_timer3_interrupt);
up_disable_irq(lower->irq);
#endif
break;
#endif
@@ -918,6 +839,13 @@ FAR struct pwm_lowerhalf_s *efm32_pwminitialize(int timer)
return NULL;
}
/* Attach but disable the timer update interrupt */
#ifdef CONFIG_PWM_PULSECOUNT
irq_attach(lower->irq, pwm_interrupt, lower);
up_disable_irq(lower->irq);
#endif
return (FAR struct pwm_lowerhalf_s *)lower;
}
arch/arm/src/efm32/efm32_rtc_burtc.c
+2 -2
View File
@@ -175,7 +175,7 @@ volatile bool g_rtc_enabled = false;
*
************************************************************************************/
static int efm32_rtc_burtc_interrupt(int irq, void *context)
static int efm32_rtc_burtc_interrupt(int irq, void *context, FAR void *arg)
{
uint32_t source = getreg32(EFM32_BURTC_IF);
@@ -378,7 +378,7 @@ int up_rtc_initialize(void)
/* Configure RTC interrupt to catch overflow and alarm interrupts. */
irq_attach(EFM32_IRQ_BURTC, efm32_rtc_burtc_interrupt);
irq_attach(EFM32_IRQ_BURTC, efm32_rtc_burtc_interrupt, NULL);
up_enable_irq(EFM32_IRQ_BURTC);
g_rtc_enabled = true;
arch/arm/src/efm32/efm32_serial.c
+14 -122
View File
@@ -220,8 +220,6 @@
struct efm32_config_s
{
uintptr_t uartbase; /* Base address of UART registers */
xcpt_t rxhandler; /* RX interrupt handler */
xcpt_t txhandler; /* TX interrupt handler */
uint32_t baud; /* Configured baud */
uint8_t rxirq; /* RX IRQ associated with this UART (for enable) */
uint8_t txirq; /* TX IRQ associated with this UART (for enable) */
@@ -257,38 +255,8 @@ static int efm32_setup(struct uart_dev_s *dev);
static void efm32_shutdown(struct uart_dev_s *dev);
static int efm32_attach(struct uart_dev_s *dev);
static void efm32_detach(struct uart_dev_s *dev);
static int efm32_rxinterrupt(struct uart_dev_s *dev);
#if defined(CONFIG_EFM32_USART0_ISUART)
static int efm32_usart0_rxinterrupt(int irq, void *context);
#endif
#if defined(CONFIG_EFM32_USART1_ISUART)
static int efm32_usart1_rxinterrupt(int irq, void *context);
#endif
#if defined(CONFIG_EFM32_USART2_ISUART)
static int efm32_usart2_rxinterrupt(int irq, void *context);
#endif
#if defined(CONFIG_EFM32_UART0)
static int efm32_uart0_rxinterrupt(int irq, void *context);
#endif
#if defined(CONFIG_EFM32_UART1)
static int efm32_uart1_rxinterrupt(int irq, void *context);
#endif
static int efm32_txinterrupt(struct uart_dev_s *dev);
#if defined(CONFIG_EFM32_USART0_ISUART)
static int efm32_usart0_txinterrupt(int irq, void *context);
#endif
#if defined(CONFIG_EFM32_USART1_ISUART)
static int efm32_usart1_txinterrupt(int irq, void *context);
#endif
#if defined(CONFIG_EFM32_USART2_ISUART)
static int efm32_usart2_txinterrupt(int irq, void *context);
#endif
#if defined(CONFIG_EFM32_UART0)
static int efm32_uart0_txinterrupt(int irq, void *context);
#endif
#if defined(CONFIG_EFM32_UART1)
static int efm32_uart1_txinterrupt(int irq, void *context);
#endif
static int efm32_rxinterrupt(int irq, void *context, void *arg);
static int efm32_txinterrupt((int irq, void *context, void *arg);
static int efm32_ioctl(struct file *filep, int cmd, unsigned long arg);
static int efm32_receive(struct uart_dev_s *dev, uint32_t *status);
static void efm32_rxint(struct uart_dev_s *dev, bool enable);
@@ -350,8 +318,6 @@ static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
static const struct efm32_usart_s g_usart0config =
{
.uartbase = EFM32_USART0_BASE,
.rxhandler = efm32_usart0_rxinterrupt,
.txhandler = efm32_usart0_txinterrupt,
.baud = CONFIG_USART0_BAUD,
.rxirq = EFM32_IRQ_USART0_RX,
.txirq = EFM32_IRQ_USART0_TX,
@@ -388,8 +354,6 @@ static struct uart_dev_s g_usart0port =
static struct efm32_config_s g_usart1config =
{
.uartbase = EFM32_USART1_BASE,
.rxhandler = efm32_usart1_rxinterrupt,
.txhandler = efm32_usart1_txinterrupt,
.baud = CONFIG_USART1_BAUD,
.rxirq = EFM32_IRQ_USART1_RX,
.txirq = EFM32_IRQ_USART1_TX,
@@ -426,8 +390,6 @@ static struct uart_dev_s g_usart1port =
static struct efm32_config_s g_usart2config =
{
.uartbase = EFM32_USART2_BASE,
.rxhandler = efm32_usart2_rxinterrupt,
.txhandler = efm32_usart2_txinterrupt,
.baud = CONFIG_USART2_BAUD,
.rxirq = EFM32_IRQ_USART2_RX,
.txirq = EFM32_IRQ_USART2_TX,
@@ -464,8 +426,6 @@ static struct uart_dev_s g_usart2port =
static struct efm32_config_s g_uart0config =
{
.uartbase = EFM32_UART0_BASE,
.rxhandler = efm32_uart0_rxinterrupt,
.txhandler = efm32_uart0_txinterrupt,
.baud = CONFIG_UART0_BAUD,
.rxirq = EFM32_IRQ_UART0_RX,
.txirq = EFM32_IRQ_UART0_TX,
@@ -502,8 +462,6 @@ static struct uart_dev_s g_uart0port =
static struct efm32_usart_s g_uart1config =
{
.uartbase = EFM32_UART1_BASE,
.rxhandler = efm32_uart1_rxinterrupt,
.txhandler = efm32_uart1_txinterrupt,
.baud = CONFIG_UART1_BAUD,
.rxirq = EFM32_IRQ_UART1_RX,
.txirq = EFM32_IRQ_UART1_TX,
@@ -689,13 +647,13 @@ static int efm32_attach(struct uart_dev_s *dev)
* disabled in the C2 register.
*/
ret = irq_attach(config->rxirq, config->rxhandler);
ret = irq_attach(config->rxirq, efm32_rxinterrupt, dev);
if (ret < 0)
{
return ret;
}
ret = irq_attach(config->txirq, config->txhandler);
ret = irq_attach(config->txirq, efm32_txinterrupt, dev);
if (ret < 0)
{
irq_detach(config->rxirq);
@@ -742,12 +700,14 @@ static void efm32_detach(struct uart_dev_s *dev)
*
****************************************************************************/
static int efm32_rxinterrupt(struct uart_dev_s *dev)
static int efm32_rxinterrupt(int irq, void *context, void *arg)
{
struct efm32_usart_s *priv = (struct efm32_usart_s *)dev->priv;
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
struct efm32_usart_s *priv;
uint32_t intflags;
DEBUGASSERT(priv);
DEBUGASSERT(dev != NULL && dev->priv != NULL);
priv = (struct efm32_usart_s *)dev->priv;
/* Read the interrupt flags register */
@@ -787,41 +747,6 @@ static int efm32_rxinterrupt(struct uart_dev_s *dev)
return OK;
}
#if defined(CONFIG_EFM32_USART0_ISUART)
static int efm32_usart0_rxinterrupt(int irq, void *context)
{
return efm32_rxinterrupt(&g_usart0port);
}
#endif
#if defined(CONFIG_EFM32_USART1_ISUART)
static int efm32_usart1_rxinterrupt(int irq, void *context)
{
return efm32_rxinterrupt(&g_usart1port);
}
#endif
#if defined(CONFIG_EFM32_USART2_ISUART)
static int efm32_usart2_rxinterrupt(int irq, void *context)
{
return efm32_rxinterrupt(&g_usart2port);
}
#endif
#if defined(CONFIG_EFM32_UART0)
static int efm32_uart0_rxinterrupt(int irq, void *context)
{
return efm32_rxinterrupt(&g_uart0port);
}
#endif
#if defined(CONFIG_EFM32_UART1)
static int efm32_uart1_rxinterrupt(int irq, void *context)
{
return efm32_rxinterrupt(&g_uart1port);
}
#endif
/****************************************************************************
* Name: efm32_txinterrupt
*
@@ -830,12 +755,14 @@ static int efm32_uart1_rxinterrupt(int irq, void *context)
*
****************************************************************************/
static int efm32_txinterrupt(struct uart_dev_s *dev)
static int efm32_txinterrupt((int irq, void *context, void *arg)
{
struct efm32_usart_s *priv = (struct efm32_usart_s *)dev->priv;
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
struct efm32_usart_s *priv;
uint32_t intflags;
DEBUGASSERT(priv);
DEBUGASSERT(dev != NULL && dev->priv != NULL);
priv = (struct efm32_usart_s *)dev->priv;
/* Read the interrupt flags register */
@@ -870,41 +797,6 @@ static int efm32_txinterrupt(struct uart_dev_s *dev)
return OK;
}
#if defined(CONFIG_EFM32_USART0_ISUART)
static int efm32_usart0_txinterrupt(int irq, void *context)
{
return efm32_txinterrupt(&g_usart0port);
}
#endif
#if defined(CONFIG_EFM32_USART1_ISUART)
static int efm32_usart1_txinterrupt(int irq, void *context)
{
return efm32_txinterrupt(&g_usart1port);
}
#endif
#if defined(CONFIG_EFM32_USART2_ISUART)
static int efm32_usart2_txinterrupt(int irq, void *context)
{
return efm32_txinterrupt(&g_usart2port);
}
#endif
#if defined(CONFIG_EFM32_UART0)
static int efm32_uart0_txinterrupt(int irq, void *context)
{
return efm32_txinterrupt(&g_uart0port);
}
#endif
#if defined(CONFIG_EFM32_UART1)
static int efm32_uart1_txinterrupt(int irq, void *context)
{
return efm32_txinterrupt(&g_uart1port);
}
#endif
/****************************************************************************
* Name: efm32_ioctl
*

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