diff --git a/.gitignore b/.gitignore index 3ec700458d0..42240bd35d4 100644 --- a/.gitignore +++ b/.gitignore @@ -9,7 +9,7 @@ Make.dep .*.swp core .gdbinit -cscope.out +/cscope.* /.config /.config.old /.version diff --git a/ChangeLog b/ChangeLog index 7c4a4b00981..f541f393d56 100755 --- a/ChangeLog +++ b/ChangeLog @@ -12483,7 +12483,7 @@ to unregister a signal handler (2016-08-01). * configs/sim: Add simulator-based test support for apps/examples/gpio 2016-08-01). - * drivers/sensors: Add KXJT9 Accelerometer driver from the Motorola + * drivers/sensors: Add KXTJ9 Accelerometer driver from the Motorola Moto Z MDK (2016-08-02). * arch/arm/sim: Add a simulated I/O Expander driver (2016-08-03). * configs/sim: Add logic to set the simulated I/O expander for testing diff --git a/Documentation/README.html b/Documentation/README.html index d3c0315bc4f..2f9ba9066b2 100644 --- a/Documentation/README.html +++ b/Documentation/README.html @@ -8,7 +8,7 @@

NuttX README Files

-

Last Updated: February 14, 2017

+

Last Updated: February 19, 2017

@@ -287,6 +287,8 @@ nuttx/ | | `- README.txt | |- twr-k60n512/ | | `- README.txt + | |- twr-k64f120m/ + | | `- README.txt | |- "u-blox-c027/ | | `- README.txt | |- ubw32/ diff --git a/Kconfig b/Kconfig index 188f9d007b0..4d7949d4e31 100644 --- a/Kconfig +++ b/Kconfig @@ -859,21 +859,21 @@ config DEBUG_IRQ if DEBUG_IRQ config DEBUG_IRQ_ERROR - bool "DMA Error Output" + bool "Interrupt Controller Error Output" default n depends on DEBUG_ERROR ---help--- Enable interrupt controller error output to SYSLOG. config DEBUG_IRQ_WARN - bool "DMA Warnings Output" + bool "Interrupt Controller Warnings Output" default n depends on DEBUG_WARN ---help--- Enable interrupt controller warning output to SYSLOG. config DEBUG_IRQ_INFO - bool "DMA Informational Output" + bool "Interrupt Controller Informational Output" default n depends on DEBUG_INFO ---help--- @@ -1277,7 +1277,7 @@ endif # DEBUG_RTC config DEBUG_MEMCARD bool "Memory Card Driver Debug Features" default n - depends on MMCSD_SDIO + depends on MMCSD ---help--- Enable MMC/SD memory card Driver debug features. diff --git a/README.txt b/README.txt index 1a0d2620a52..ed3d41c30f8 100644 --- a/README.txt +++ b/README.txt @@ -1671,6 +1671,8 @@ nuttx/ | | `- README.txt | |- twr-k60n512/ | | `- README.txt + | |- twr-k64f120m/ + | | `- README.txt | |- u-blox-co27/ | | `- README.txt | |- ubw32/ diff --git a/ReleaseNotes b/ReleaseNotes index e7d50a40532..f7dc36cdd4f 100644 --- a/ReleaseNotes +++ b/ReleaseNotes @@ -11813,7 +11813,7 @@ Additional new features and extended functionality: * Sensor Drivers: - - Add KXJT9 Accelerometer driver from the Motorola Moto Z MDK. + - Add KXTJ9 Accelerometer driver from the Motorola Moto Z MDK. - Add MFRC522 RFID ISO14443 and Mifare transceiver driver. From Alan Carvalho de Assis. - Add driver for the LIS3MDL 3 axis magnetometer. From Alexander diff --git a/TODO b/TODO index e3efaa81df6..53030779480 100644 --- a/TODO +++ b/TODO @@ -438,7 +438,7 @@ o pthreads (sched/pthreads) serve as cancellation points. They are, however, simple wrappers around nanosleep which is a true cancellation point. NOTE 02: system() is actually implemented in apps/ as part of NSH. It cannot be - a cancellation point either. + a cancellation point. NOTE 03: sigpause() is a user-space function in the C library and cannot serve as cancellation points. It is, however, a simple wrapper around sigsuspend() which is a true cancellation point. diff --git a/arch/arm/include/kinetis/chip.h b/arch/arm/include/kinetis/chip.h index 2da386c3daa..5c6cc76a082 100644 --- a/arch/arm/include/kinetis/chip.h +++ b/arch/arm/include/kinetis/chip.h @@ -43,6 +43,8 @@ #include #include +#include +#include /************************************************************************************ * Pre-processor Definitions @@ -1425,7 +1427,8 @@ # define KINETIS_NUSBDEV 1 /* One USB device controller */ # define KINETIS_NSDHC 1 /* SD host controller */ # define KINETIS_NI2C 4 /* Four I2C modules */ -# define KINETIS_NUART 5 /* Five UART modues */ +# define KINETIS_NUART 5 /* Five UART modules */ +# define KINETIS_NLPUART 1 /* One LPUART modules */ # define KINETIS_NSPI 3 /* Three SPI modules */ # define KINETIS_NCAN 2 /* Two CAN controllers */ # define KINETIS_NI2S 1 /* One I2S modules */ diff --git a/arch/arm/include/kinetis/kinetis_mcg.h b/arch/arm/include/kinetis/kinetis_mcg.h index 7b46c686322..bca6b188836 100644 --- a/arch/arm/include/kinetis/kinetis_mcg.h +++ b/arch/arm/include/kinetis/kinetis_mcg.h @@ -76,7 +76,7 @@ * KINETIS_MCG_HAS_PLL_INTERNAL_MODE - Has PEI mode or PBI mode * KINETIS_MCG_HAS_RESET_IS_BLPI - Has Reset clock mode is BLPI * - * MCD Register Configuration + * MCG Register Configuration * * KINETIS_MCG_HAS_C1 - SoC has C1 Register * KINETIS_MCG_HAS_C1_IREFS - SoC has C1[IREFS] @@ -289,7 +289,7 @@ # undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */ # undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */ -/* MCD Register Configuration */ +/* MCG Register Configuration */ # define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */ # define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */ @@ -371,7 +371,7 @@ # undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */ # undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */ -/* MCD Register Configuration */ +/* MCG Register Configuration */ # define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */ # define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */ @@ -448,7 +448,7 @@ /* Verified to Document Number: Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */ -# define KINETIS_MCG_VERSION KINETIS_K_MCG_VERSION_06 +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_06 /* MCG Configuration Parameters */ @@ -463,7 +463,7 @@ # undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */ # undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */ -/* MCD Register Configuration */ +/* MCG Register Configuration */ # define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */ # define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */ @@ -544,7 +544,7 @@ # undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */ # undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */ -/* MCD Register Configuration */ +/* MCG Register Configuration */ # define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */ # define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */ diff --git a/arch/arm/include/kinetis/kinetis_pmc.h b/arch/arm/include/kinetis/kinetis_pmc.h new file mode 100644 index 00000000000..03bc8958426 --- /dev/null +++ b/arch/arm/include/kinetis/kinetis_pmc.h @@ -0,0 +1,324 @@ +/************************************************************************************ + * arch/arm/include/kinetis/kinetis_pmc.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_PMC_H +#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_PMC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Note: It is envisioned that in the long term as a chip is added. The author of + * the new chip definitions will either find the exact configuration in an existing + * chip define and add the new chip to it Or add the PMC feature configuration + * #defines to the chip ifdef list below. In either case the author should mark + * it as "Verified to Document Number:" taken from the reference manual. + * + * To maintain backward compatibility to the version of NuttX prior to + * 2/22/2017, the catch all KINETIS_PMC_VERSION_UKN configuration is assigned + * to all the chips that did not have any conditional compilation based on + * KINETIS_K64 or KINETIS_K66. This is a "No worse" than the original code solution. + * N.B. Each original chip "if"definitions have been left intact so that the + * complete legacy definitions prior to 2/22/2017 may be filled in completely when + * vetted. + */ + +/* PMC Register Configuration + * + * KINETIS_PMC_HAS_REGSC - SoC has REGSC Register + * KINETIS_PMC_HAS_REGSC_ACKISO - SoC has REGSC[ACKISO] + * KINETIS_PMC_HAS_REGSC_VLPRS - SoC has REGSC[VLPRS] + * KINETIS_PMC_HAS_REGSC_VLPO - SoC has REGSC[VLPO] + * KINETIS_PMC_HAS_REGSC_REGFPM - SoC has REGSC[REGFPM] + * KINETIS_PMC_HAS_REGSC_BGEN - SoC has REGSC[BGEN] + * KINETIS_PMC_HAS_REGSC_TRAMPO - SoC has REGSC[TRAMPO] + * KINETIS_PMC_HAS_REGSC_REGONS - SoC has REGSC[REGONS] + */ + +/* Describe the version of the PMC + * + * These defines are not related to any NXP reference but are merely + * a way to label the versions we are using + */ + +#define KINETIS_PMC_VERSION_UKN -1 /* What was in nuttx prior to 2/22/2017 */ +#define KINETIS_PMC_VERSION_01 1 /* Verified Document Number: K60P144M150SF3RM Rev. 3, November 2014 */ +#define KINETIS_PMC_VERSION_04 4 /* Verified to Document Numbers: + * K20P64M72SF1RM Rev. 1.1, Dec 2012 + * K64P144M120SF5RM Rev. 2, January 2014 + * K66P144M180SF5RMV2 Rev. 2, May 2015 */ + +/* MK20DX/DN---VLH5 + * + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO + * FREQ CNT FLASH FLASH + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * MK20DN32VLH5 50 MHz 64 LQFP 32 KB 32 KB — 8 KB 40 + * MK20DX32VLH5 50 MHz 64 LQFP 64 KB 32 KB 2 KB 8 KB 40 + * MK20DN64VLH5 50 MHz 64 LQFP 64 KB 64 KB — 16 KB 40 + * MK20DX64VLH5 50 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40 + * MK20DN128VLH5 50 MHz 64 LQFP 128 KB 128 KB — 16 KB 40 + * MK20DX128VLH5 50 MHz 64 LQFP 160 KB 128 KB 2 KB 16 KB 40 + */ + +#if defined(CONFIG_ARCH_CHIP_MK20DN32VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DX32VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DN64VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DX64VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DN128VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DX128VLH5) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +/* MK20DX---VLH7 + * + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO + * FREQ CNT FLASH FLASH + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * MK20DX64VLH7 72 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40 + * MK20DX128VLH7 72 MHz 64 LQFP 160 KB 128 KB 2 KB 32 KB 40 + * MK20DX256VLH7 72 MHz 64 LQFP 288 KB 256 KB 2 KB 64 KB 40 + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + */ + +#elif defined(CONFIG_ARCH_CHIP_MK20DX64VLH7) || defined(CONFIG_ARCH_CHIP_MK20DX128VLH7) || \ + defined(CONFIG_ARCH_CHIP_MK20DX256VLH7) + +/* Verified to Document Number: K20P64M72SF1RM Rev. 1.1, Dec 2012 */ + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_04 + +/* PMC Register Configuration */ + +# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */ +# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */ +# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */ +# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */ +# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */ +# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */ +# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */ +# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */ + +#elif defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \ + defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X128VFX50) || defined(CONFIG_ARCH_CHIP_MK40X128VLH50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLK50) || defined(CONFIG_ARCH_CHIP_MK40X128VMB50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLL50) || defined(CONFIG_ARCH_CHIP_MK40X128VML50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VFX72) || defined(CONFIG_ARCH_CHIP_MK40X128VLH72) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLK72) || defined(CONFIG_ARCH_CHIP_MK40X128VMB72) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLL72) || defined(CONFIG_ARCH_CHIP_MK40X128VML72) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X256VLK72) || defined(CONFIG_ARCH_CHIP_MK40X256VMB72) || \ + defined(CONFIG_ARCH_CHIP_MK40X256VLL72) || defined(CONFIG_ARCH_CHIP_MK40X256VML72) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40N512VLK100) || defined(CONFIG_ARCH_CHIP_MK40N512VMB100) || \ + defined(CONFIG_ARCH_CHIP_MK40N512VLL100) || defined(CONFIG_ARCH_CHIP_MK40N512VML100) || \ + defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60FN1M0VLQ12) + +/* Verified to Document Number: K60P144M100SF2V2RM Rev. 2 Jun 2012 */ + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_01 + +/* PMC Register Configuration */ + +# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */ +# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */ +# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */ +# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */ +# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */ +# undef KINETIS_PMC_HAS_REGSC_BGEN /* SoC has REGSC[BGEN] */ +# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */ +# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */ + +#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || \ + defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \ + defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || \ + defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12) + +/* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */ + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_04 + +/* PMC Register Configuration */ + +# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */ +# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */ +# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */ +# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */ +# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */ +# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */ +# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */ +# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */ + +/* MK66F N/X 1M0/2M0 V MD/LQ 18 + * + * --------------- ------- --- ------- ------- ------ ------ ------ ----- + * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO + * FREQ CNT FLASH FLASH + * --------------- ------- --- ------- ------- ------ ------ ------ ----- + * MK66FN2M0VMD18 180 MHz 144 MAPBGA 2 MB — — KB 260 KB 100 + * MK66FX1M0VMD18 180 MHz 144 MAPBGA 1.25 MB 1 MB 4 KB 256 KB 100 + * MK66FN2M0VLQ18 180 MHz 144 LQFP 2 MB — — KB 260 KB 100 + * MK66FX1M0VLQ18 180 MHz 144 LQFP 1.25 MB 1 MB 4 KB 256 KB 100 + */ + +#elif defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \ + defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18) + +/* Verified to Document Number: Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */ + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_04 + +/* PMC Register Configuration */ + +# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */ +# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */ +# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */ +# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */ +# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */ +# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */ +# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */ +# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */ + +#else +# error "Unsupported Kinetis chip" +#endif + +/* Use the catch all configuration for the PMC based on the implementations in nuttx prior 2/3/2017 */ + +#if KINETIS_PMC_VERSION == KINETIS_PMC_VERSION_UKN + +/* PMC Register Configuration */ + +# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */ +# undef KINETIS_PMC_HAS_REGSC_ACKISO /* SoC has REGSC[ACKISO] */ +# define KINETIS_PMC_HAS_REGSC_VLPRS 1 /* SoC has REGSC[VLPRS] */ +# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */ +# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */ +# undef KINETIS_PMC_HAS_REGSC_BGEN /* SoC has REGSC[BGEN] */ +# define KINETIS_PMC_HAS_REGSC_TRAMPO 1 /* SoC has REGSC[TRAMPO] */ +# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */ + +#endif + +#if !defined(KINETIS_PMC_VERSION) +# error "No KINETIS_PMC_VERSION defined!" +#endif + +#if defined(KINETIS_PMC_HAS_C5_PRDIV) +# define KINETIS_PMC_C5_PRDIV_MASK ((1 << (KINETIS_PMC_C5_PRDIV_BITS))-1) +#endif + +#if defined(KINETIS_PMC_HAS_C7_OSCSEL) +# define KINETIS_PMC_C7_OSCSEL_MASK ((1 << (KINETIS_PMC_C7_OSCSEL_BITS))-1) +#endif + +#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_PMC_H */ diff --git a/arch/arm/include/kinetis/kinetis_sim.h b/arch/arm/include/kinetis/kinetis_sim.h new file mode 100644 index 00000000000..224e8b0d787 --- /dev/null +++ b/arch/arm/include/kinetis/kinetis_sim.h @@ -0,0 +1,1322 @@ +/************************************************************************************ + * arch/arm/include/kinetis/kinetis_sim.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_SIM_H +#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_SIM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Note: It is envisioned that in the long term as a chip is added. The author of + * the new chip definitions will either find the exact configuration in an existing + * chip define and add the new chip to it Or add the SIM feature configuration + * #defines to the chip ifdef list below. In either case the author should mark + * it as "Verified to Document Number:" taken from the reference manual. + * + * To maintain backward compatibility to the version of NuttX prior to + * 2/16/2017, the catch all KINETIS_SIM_VERSION_UKN configuration is assigned + * to all the chips that did not have any conditional compilation based on + * KINETIS_K64 or KINETIS_K66. This is a "No worse" than the original code solution. + * N.B. Each original chip "if"definitions have been left intact so that the + * complete legacy definitions prior to 2/16/2017 may be filled in completely when + * vetted. + */ + +/* SIM Register Configuration + * + * KINETIS_SIM_HAS_SOPT1 - SoC has SOPT1 Register + * KINETIS_SIM_HAS_SOPT1_OSC32KOUT - SoC has SOPT1[OSC32KOUT] + * KINETIS_SIM_HAS_SOPT1_OSC32KSEL - SoC has SOPT1[OSC32KSEL] + * KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS - SoC has n bits SOPT1[OSC32KSEL] + * KINETIS_SIM_HAS_SOPT1_RAMSIZE - SoC has SOPT1[RAMSIZE] + * KINETIS_SIM_HAS_SOPT1_USBREGEN - SoC has SOPT1[USBREGEN] + * KINETIS_SIM_HAS_SOPT1_USBSSTBY - SoC has SOPT1[USBSSTBY] + * KINETIS_SIM_HAS_SOPT1_USBVSTBY - SoC has SOPT1[USBVSTBY] + * KINETIS_SIM_HAS_SOPT1CFG - SoC has SOPT1CFG Register + * KINETIS_SIM_HAS_SOPT1CFG_URWE - SoC has SOPT1CFG[URWE] + * KINETIS_SIM_HAS_SOPT1CFG_USSWE - SoC has SOPT1CFG[USSWE] + * KINETIS_SIM_HAS_SOPT1CFG_UVSWE - SoC has SOPT1CFG[UVSWE] + * KINETIS_SIM_HAS_USBPHYCTL - SoC has USBPHYCTL Register + * KINETIS_SIM_HAS_USBPHYCTL_USB3VOUTTRG - SoC has USBPHYCTL[USB3VOUTTRG] + * KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM - SoC has USBPHYCTL[USBDISILIM] + * KINETIS_SIM_HAS_USBPHYCTL_USBVREGPD - SoC has USBPHYCTL[USBVREGPD] + * KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL - SoC has USBPHYCTL[USBVREGSEL] + * KINETIS_SIM_HAS_SOPT2 - SoC has SOPT2 Register + * KINETIS_SIM_HAS_SOPT2_CMTUARTPAD - SoC has SOPT2[CMTUARTPAD] + * KINETIS_SIM_HAS_SOPT2_FBSL - SoC has SOPT2[FBSL] + * KINETIS_SIM_HAS_SOPT2_FLEXIOSRC - SoC has SOPT2[FLEXIOSRC] + * KINETIS_SIM_HAS_SOPT2_LPUARTSRC - SoC has SOPT2[LPUARTSRC] + * KINETIS_SIM_HAS_SOPT2_PLLFLLSEL - SoC has SOPT2[PLLFLLSEL] + * KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS - SoC has n bits SOPT2[PLLFLLSEL] + * KINETIS_SIM_HAS_SOPT2_PTD7PAD - SoC has SOPT2[PTD7PAD] + * KINETIS_SIM_HAS_SOPT2_RMIISRC - SoC has SOPT2[RMIISRC] + * KINETIS_SIM_HAS_SOPT2_RTCCLKOUTSEL - SoC has SOPT2[RTCCLKOUTSEL] + * KINETIS_SIM_HAS_SOPT2_CLKOUTSEL - SoC has SOPT2[CLKOUTSEL] + * KINETIS_SIM_HAS_SOPT2_SDHCSRC - SoC has SOPT2[SDHCSRC] + * KINETIS_SIM_HAS_SOPT2_NFCSRC - SoC has SOPT2[NFCSRC] + * KINETIS_SIM_HAS_SOPT2_I2SSRC - SoC has SOPT2[I2SSRC] + * KINETIS_SIM_HAS_SOPT2_TIMESRC - SoC has SOPT2[TIMESRC] + * KINETIS_SIM_HAS_SOPT2_TPMSRC - SoC has SOPT2[TPMSRC] + * KINETIS_SIM_HAS_SOPT2_USBFSRC - SoC has SOPT2[USBFSRC] + * KINETIS_SIM_HAS_SOPT2_TRACECLKSEL - SoC has SOPT2[TRACECLKSEL] + * KINETIS_SIM_HAS_SOPT2_USBREGEN - SoC has SOPT2[USBREGEN] + * KINETIS_SIM_HAS_SOPT2_USBSLSRC - SoC has SOPT2[USBSLSRC] + * KINETIS_SIM_HAS_SOPT2_USBHSRC - SoC has SOPT2[USBHSRC] + * KINETIS_SIM_HAS_SOPT2_USBSRC - SoC has SOPT2[USBSRC] + * KINETIS_SIM_HAS_SOPT2_MCGCLKSEL - SoC has SOPT2[MCGCLKSEL] + * KINETIS_SIM_HAS_SOPT4 - SoC has SOPT4 Register + * KINETIS_SIM_HAS_SOPT4_FTM0FLT0 - SoC has SOPT4[FTM0FLT0] + * KINETIS_SIM_HAS_SOPT4_FTM0FLT1 - SoC has SOPT4[FTM0FLT1] + * KINETIS_SIM_HAS_SOPT4_FTM0FLT2 - SoC has SOPT4[FTM0FLT2] + * KINETIS_SIM_HAS_SOPT4_FTM0FLT3 - SoC has SOPT4[FTM0FLT3] + * KINETIS_SIM_HAS_SOPT4_FTM0TRG0SRC - SoC has SOPT4[FTM0TRG0SRC] + * KINETIS_SIM_HAS_SOPT4_FTM0TRG1SRC - SoC has SOPT4[FTM0TRG1SRC] + * KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC - SoC has SOPT4[FTM1CH0SRC] 1, 3 if SOF + * KINETIS_SIM_HAS_SOPT4_FTM1FLT0 - SoC has SOPT4[FTM1FLT0] + * KINETIS_SIM_HAS_SOPT4_FTM1FLT1 - SoC has SOPT4[FTM1FLT1] + * KINETIS_SIM_HAS_SOPT4_FTM1FLT2 - SoC has SOPT4[FTM1FLT2] + * KINETIS_SIM_HAS_SOPT4_FTM1FLT3 - SoC has SOPT4[FTM1FLT3] + * KINETIS_SIM_HAS_SOPT4_FTM2CH0SRC - SoC has SOPT4[FTM2CH0SRC] + * KINETIS_SIM_HAS_SOPT4_FTM2CH1SRC - SoC has SOPT4[FTM2CH1SRC] + * KINETIS_SIM_HAS_SOPT4_FTM2FLT0 - SoC has SOPT4[FTM2FLT0] + * KINETIS_SIM_HAS_SOPT4_FTM2FLT1 - SoC has SOPT4[FTM2FLT1] + * KINETIS_SIM_HAS_SOPT4_FTM2FLT2 - SoC has SOPT4[FTM2FLT2] + * KINETIS_SIM_HAS_SOPT4_FTM2FLT3 - SoC has SOPT4[FTM2FLT3] + * KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC - SoC has SOPT4[FTM3CH0SRC] + * KINETIS_SIM_HAS_SOPT4_FTM3FLT0 - SoC has SOPT4[FTM3FLT0] + * KINETIS_SIM_HAS_SOPT4_FTM3FLT1 - SoC has SOPT4[FTM3FLT1] + * KINETIS_SIM_HAS_SOPT4_FTM3FLT2 - SoC has SOPT4[FTM3FLT2] + * KINETIS_SIM_HAS_SOPT4_FTM3FLT3 - SoC has SOPT4[FTM3FLT3] + * KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC - SoC has SOPT4[FTM3TRG0SRC] + * KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC - SoC has SOPT4[FTM3TRG1SRC] + * KINETIS_SIM_HAS_SOPT4_TPM0CLKSEL - SoC has SOPT4[TPM0CLKSEL] + * KINETIS_SIM_HAS_SOPT4_TPM1CH0SRC - SoC has SOPT4[TPM1CH0SRC] + * KINETIS_SIM_HAS_SOPT4_TPM1CLKSEL - SoC has SOPT4[TPM1CLKSEL] + * KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC - SoC has SOPT4[TPM2CH0SRC] + * KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL - SoC has SOPT4[TPM2CLKSEL] + * KINETIS_SIM_HAS_SOPT5 - SoC has SOPT5 Register + * KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC - SoC has SOPT5[LPUART0RXSRC] + * KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC - SoC has SOPT5[LPUART0TXSRC] + * KINETIS_SIM_HAS_SOPT6 - SoC has SOPT6 Register + * KINETIS_SIM_HAS_SOPT6_MCC - SoC has SOPT6[MCC] + * KINETIS_SIM_HAS_SOPT6_PCR - SoC has SOPT6[PCR] + * KINETIS_SIM_HAS_SOPT6_RSTFLTSEL - SoC has SOPT6[RSTFLTSEL] + * KINETIS_SIM_HAS_SOPT6_RSTFLTEN - SoC has SOPT6[RSTFLTEN] + * KINETIS_SIM_HAS_SOPT7 - SoC has SOPT7 Register + * KINETIS_SIM_HAS_SOPT7_ADC0ALTTRGSEL - SoC has SOPT7[ADC0ALTTRGSEL] + * KINETIS_SIM_HAS_SOPT7_ADC1ALTTRGSEL - SoC has SOPT7[ADC1ALTTRGSEL] + * KINETIS_SIM_HAS_SOPT7_ADC0PRETRGSEL - SoC has SOPT7[ADC0PRETRGSEL] + * KINETIS_SIM_HAS_SOPT7_ADC1PRETRGSEL - SoC has SOPT7[ADC1PRETRGSEL] + * KINETIS_SIM_HAS_SOPT7_ADC2PRETRGSEL - SoC has SOPT7[ADC2PRETRGSEL] + * KINETIS_SIM_HAS_SOPT7_ADC3PRETRGSEL - SoC has SOPT7[ADC3PRETRGSEL] + * KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL - SoC has n SOPT7[ADC0TRGSEL] + * KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL - SoC has n SOPT7[ADC1TRGSEL] + * KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL - SoC has n SOPT7[ADC2TRGSEL] + * KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL - SoC has n SOPT7[ADC3TRGSEL] + * KINETIS_SIM_SOPT7_ADC0ALTTRGEN - SoC has ADC0 alternate trigger enable + * KINETIS_SIM_SOPT7_ADC1ALTTRGEN - SoC has ADC1 alternate trigger enable + * KINETIS_SIM_SOPT7_ADC2ALTTRGEN - SoC has ADC2 alternate trigger enable + * KINETIS_SIM_SOPT7_ADC3ALTTRGEN - SoC has ADC3 alternate trigger enable + * KINETIS_SIM_HAS_SOPT8 - SoC has SOPT8 Register + * KINETIS_SIM_HAS_SOPT8_FTM0SYNCBIT - SoC has SOPT8[FTM0SYNCBIT] + * KINETIS_SIM_HAS_SOPT8_FTM1SYNCBIT - SoC has SOPT8[FTM1SYNCBIT] + * KINETIS_SIM_HAS_SOPT8_FTM2SYNCBIT - SoC has SOPT8[FTM2SYNCBIT] + * KINETIS_SIM_HAS_SOPT8_FTM3SYNCBIT - SoC has SOPT8[FTM3SYNCBIT] + * KINETIS_SIM_HAS_SOPT8_FTM0OCH0SRC - SoC has SOPT8[FTM0OCH0SRC] + * KINETIS_SIM_HAS_SOPT8_FTM0OCH1SRC - SoC has SOPT8[FTM0OCH1SRC] + * KINETIS_SIM_HAS_SOPT8_FTM0OCH2SRC - SoC has SOPT8[FTM0OCH2SRC] + * KINETIS_SIM_HAS_SOPT8_FTM0OCH3SRC - SoC has SOPT8[FTM0OCH3SRC] + * KINETIS_SIM_HAS_SOPT8_FTM0OCH4SRC - SoC has SOPT8[FTM0OCH4SRC] + * KINETIS_SIM_HAS_SOPT8_FTM0OCH5SRC - SoC has SOPT8[FTM0OCH5SRC] + * KINETIS_SIM_HAS_SOPT8_FTM0OCH6SRC - SoC has SOPT8[FTM0OCH6SRC] + * KINETIS_SIM_HAS_SOPT8_FTM0OCH7SRC - SoC has SOPT8[FTM0OCH7SRC] + * KINETIS_SIM_HAS_SOPT8_FTM3OCH0SRC - SoC has SOPT8[FTM3OCH0SRC] + * KINETIS_SIM_HAS_SOPT8_FTM3OCH1SRC - SoC has SOPT8[FTM3OCH1SRC] + * KINETIS_SIM_HAS_SOPT8_FTM3OCH2SRC - SoC has SOPT8[FTM3OCH2SRC] + * KINETIS_SIM_HAS_SOPT8_FTM3OCH3SRC - SoC has SOPT8[FTM3OCH3SRC] + * KINETIS_SIM_HAS_SOPT8_FTM3OCH4SRC - SoC has SOPT8[FTM3OCH4SRC] + * KINETIS_SIM_HAS_SOPT8_FTM3OCH5SRC - SoC has SOPT8[FTM3OCH5SRC] + * KINETIS_SIM_HAS_SOPT8_FTM3OCH6SRC - SoC has SOPT8[FTM3OCH6SRC] + * KINETIS_SIM_HAS_SOPT8_FTM3OCH7SRC - SoC has SOPT8[FTM3OCH7SRC] + * KINETIS_SIM_HAS_SOPT9 - SoC has SOPT9 Register + * KINETIS_SIM_HAS_SOPT9_TPM1CH0SRC - SoC has SOPT9[TPM1CH0SRC] + * KINETIS_SIM_HAS_SOPT9_TPM2CH0SRC - SoC has SOPT9[TPM2CH0SRC] + * KINETIS_SIM_HAS_SOPT9_TPM1CLKSEL - SoC has SOPT9[TPM1CLKSEL] + * KINETIS_SIM_HAS_SOPT9_TPM2CLKSEL - SoC has SOPT9[TPM2CLKSEL] + * KINETIS_SIM_HAS_SDID - SoC has SDID Register + * KINETIS_SIM_HAS_SDID_DIEID - SoC has SDID[DIEID] + * KINETIS_SIM_HAS_SDID_FAMID - SoC has SDID[FAMID] + * KINETIS_SIM_HAS_SDID_FAMILYID - SoC has SDID[FAMILYID] + * KINETIS_SIM_HAS_SDID_SERIESID - SoC has SDID[SERIESID] + * KINETIS_SIM_HAS_SDID_SRAMSIZE - SoC has SDID[SRAMSIZE] + * KINETIS_SIM_HAS_SDID_SUBFAMID - SoC has SDID[SUBFAMID] + * KINETIS_SIM_HAS_SCGC1 - SoC has _SCGC1 Register + * KINETIS_SIM_HAS_SCGC1_UART5 - SoC has SCGC1[UART5] + * KINETIS_SIM_HAS_SCGC1_UART4 - SoC has SCGC1[UART4] + * KINETIS_SIM_HAS_SCGC1_I2C3 - SoC has SCGC1[I2C3] + * KINETIS_SIM_HAS_SCGC1_I2C2 - SoC has SCGC1[I2C2] + * KINETIS_SIM_HAS_SCGC1_OSC1 - SoC has SCGC1[OSC1] + * KINETIS_SIM_HAS_SCGC2 - SoC has SCGC2 Register + * KINETIS_SIM_HAS_SCGC2_ENET - SoC has SCGC2[ENET] + * KINETIS_SIM_HAS_SCGC2_LPUART0 - SoC has SCGC2[LPUART0] + * KINETIS_SIM_HAS_SCGC2_TPM1 - SoC has SCGC2[TPM1] + * KINETIS_SIM_HAS_SCGC2_TPM2 - SoC has SCGC2[TPM2] + * KINETIS_SIM_HAS_SCGC3 - SoC has SCGC3 Register + * KINETIS_SIM_HAS_SCGC3 - SoC has SCGC3 Register + * KINETIS_SIM_HAS_SCGC3_RNGA - SoC has SCGC3[RNGA] + * KINETIS_SIM_HAS_SCGC3_USBHS - SoC has SCGC3[USBHS] + * KINETIS_SIM_HAS_SCGC3_USBHSPHY - SoC has SCGC3[USBHSPHY] + * KINETIS_SIM_HAS_SCGC3_USBHSDCD - SoC has SCGC3[USBHSDCD] + * KINETIS_SIM_HAS_SCGC3_FLEXCAN1 - SoC has SCGC3[FLEXCAN1] + * KINETIS_SIM_HAS_SCGC3_NFC - SoC has SCGC3[NFC] + * KINETIS_SIM_HAS_SCGC3_SPI2 - SoC has SCGC3[SPI2] + * KINETIS_SIM_HAS_SCGC3_SAI1 - SoC has SCGC3[SAI1] + * KINETIS_SIM_HAS_SCGC3_SDHC - SoC has SCGC3[SDHC] + * KINETIS_SIM_HAS_SCGC3_FTM2 - SoC has SCGC3[FTM2] + * KINETIS_SIM_HAS_SCGC3_FTM3 - SoC has SCGC3[FTM3] + * KINETIS_SIM_HAS_SCGC3_ADC1 - SoC has SCGC3[ADC1] + * KINETIS_SIM_HAS_SCGC3_ADC3 - SoC has SCGC3[ADC3] + * KINETIS_SIM_HAS_SCGC3_SLCD - SoC has SCGC3[SLCD] + * KINETIS_SIM_HAS_SCGC4 - SoC has SCGC4 Register + * KINETIS_SIM_HAS_SCGC4_LLWU - SoC has SCGC4[LLWU] clock gate + * KINETIS_SIM_HAS_SCGC4_UART0 - SoC has SCGC4[UART0] + * KINETIS_SIM_HAS_SCGC4_UART1 - SoC has SCGC4[UART1] + * KINETIS_SIM_HAS_SCGC4_UART2 - SoC has SCGC4[UART2] + * KINETIS_SIM_HAS_SCGC4_UART3 - SoC has SCGC4[UART3] + * KINETIS_SIM_HAS_SCGC5 - SoC has _SCGC5 Register + * KINETIS_SIM_HAS_SCGC5_REGFILE - SoC has SCGC5[REGFILE] + * KINETIS_SIM_HAS_SCGC5_TSI - SoC has SCGC5[TSI] + * KINETIS_SIM_HAS_SCGC5_PORTF - SoC has SCGC5[PORTf] + * KINETIS_SIM_HAS_SCGC6 - SoC has SCGC6 Register + * KINETIS_SIM_HAS_SCGC6_FTFL - SoC has SCGC6[FTFL] + * KINETIS_SIM_HAS_SCGC6_DMAMUX1 - SoC has SCGC6[DEMUX1] + * KINETIS_SIM_HAS_SCGC6_USBHS - SoC has SCGC6[USBHS] + * KINETIS_SIM_HAS_SCGC6_RNGA - SoC has SCGC6[RNGA] + * KINETIS_SIM_HAS_SCGC6_FTM2 - SoC has SCGC6[FTM2] + * KINETIS_SIM_HAS_SCGC6_ADC2 - SoC has SCGC6[ADC2] + * KINETIS_SIM_HAS_SCGC6_DAC0 - SoC has SCGC6[DAC0] + * KINETIS_SIM_HAS_SCGC7 - SoC has SCGC7 Register + * KINETIS_SIM_HAS_SCGC7_FLEXBUS - SoC has SCGC7[FLEXBUS] + * KINETIS_SIM_HAS_SCGC7_DMA - SoC has SCGC7[DMS] + * KINETIS_SIM_HAS_SCGC7_MPU - SoC has SCGC7[MPU] + * KINETIS_SIM_HAS_SCGC7_SDRAMC - SoC has SCGC7[SDRAMC] + * KINETIS_SIM_HAS_CLKDIV1 - SoC has CLKDIV1 Register + * KINETIS_SIM_HAS_CLKDIV1_OUTDIV2 - SoC has CLKDIV1[OUTDIV2] + * KINETIS_SIM_HAS_CLKDIV1_OUTDIV3 - SoC has CLKDIV1[OUTDIV3] + * KINETIS_SIM_HAS_CLKDIV1_OUTDIV4 - SoC has CLKDIV1[OUTDIV4] + * KINETIS_SIM_HAS_CLKDIV1_OUTDIV5 - SoC has CLKDIV1[OUTDIV5] + * KINETIS_SIM_HAS_CLKDIV2 - SoC has CLKDIV2 Register + * KINETIS_SIM_HAS_CLKDIV2_USBDIV - SoC has CLKDIV2[USBDIV] + * KINETIS_SIM_HAS_CLKDIV2_USBFRAC - SoC has CLKDIV2[USBFRAC] + * KINETIS_SIM_HAS_CLKDIV2_I2SDIV - SoC has CLKDIV2[I2SDIV] + * KINETIS_SIM_HAS_CLKDIV2_I2SFRAC - SoC has CLKDIV2[I2SFRAC] + * KINETIS_SIM_HAS_CLKDIV2_USBHSDIV - SoC has CLKDIV2[USBHSDIV] + * KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC - SoC has CLKDIV2[USBHSFRAC] + * KINETIS_SIM_HAS_FCFG1 - SoC has FCFG1 Register + * KINETIS_SIM_HAS_FCFG1_DEPART - SoC has FCFG1[DEPART] + * KINETIS_SIM_HAS_FCFG1_EESIZE - SoC has FCFG1[EESIZE] + * KINETIS_SIM_HAS_FCFG1_FLASHDIS - SoC has FCFG1[FLASHDIS] + * KINETIS_SIM_HAS_FCFG1_FLASHDOZE - SoC has FCFG1[FLASHDOZE] + * KINETIS_SIM_HAS_FCFG1_FTFDIS - SoC has FCFG1[FTFDIS] + * KINETIS_SIM_HAS_FCFG1_NVMSIZE - SoC has FCFG1[NVMSIZE] + * KINETIS_SIM_HAS_FCFG2 - SoC has FCFG2 Register + * KINETIS_SIM_HAS_FCFG2_MAXADDR0 - SoC has n bit of FCFG2[MAXADDR0] + * KINETIS_SIM_HAS_FCFG2_MAXADDR1 - SoC has n bit of FCFG2[MAXADDR1] + * KINETIS_SIM_HAS_FCFG2_PFLSH - SoC has FCFG2[PFLSH] + * KINETIS_SIM_HAS_FCFG2_SWAPPFLSH - SoC has FCFG2[SWAPPFLSH] + * KINETIS_SIM_HAS_UIDH - SoC has UIDH Register + * KINETIS_SIM_HAS_UIDMH - SoC has UIDMH Register + * KINETIS_SIM_HAS_UIDML - SoC has UIDML Register + * KINETIS_SIM_HAS_UIDL - SoC has UIDL Register + * KINETIS_SIM_HAS_CLKDIV3 - SoC has CLKDIV3 Register + * KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV - SoC has CLKDIV3[PLLFLLDIV] + * KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC - SoC has CLKDIV3[PLLFLLFRAC] + * KINETIS_SIM_HAS_CLKDIV4 - SoC has CLKDIV4 Register + * KINETIS_SIM_HAS_CLKDIV4_TRACEDIV - SoC has CLKDIV4[TRACEDIV] + * KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC - SoC has CLKDIV4[TRACEFRAC] + * KINETIS_SIM_HAS_CLKDIV4_NFCEDIV - SoC has CLKDIV4[NFCDIV] + * KINETIS_SIM_HAS_CLKDIV4_NFCFRAC - SoC has CLKDIV4[NFCFRAC] + * KINETIS_SIM_HAS_MCR - SoC has MCR Register + */ + +/* Describe the version of the SIM + * + * These defines are not related to any NXP reference but are merely + * a way to label the versions we are using + */ + +#define KINETIS_SIM_VERSION_UKN -1 /* What was in nuttx prior to 2/16/2017 */ +#define KINETIS_SIM_VERSION_01 1 /* Verified Document Number: K60P144M150SF3RM Rev. 3, November 2014 */ +#define KINETIS_SIM_VERSION_04 4 /* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */ +#define KINETIS_SIM_VERSION_06 6 /* Verified to Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */ + +/* MK20DX/DN---VLH5 + * + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO + * FREQ CNT FLASH FLASH + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * MK20DN32VLH5 50 MHz 64 LQFP 32 KB 32 KB — 8 KB 40 + * MK20DX32VLH5 50 MHz 64 LQFP 64 KB 32 KB 2 KB 8 KB 40 + * MK20DN64VLH5 50 MHz 64 LQFP 64 KB 64 KB — 16 KB 40 + * MK20DX64VLH5 50 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40 + * MK20DN128VLH5 50 MHz 64 LQFP 128 KB 128 KB — 16 KB 40 + * MK20DX128VLH5 50 MHz 64 LQFP 160 KB 128 KB 2 KB 16 KB 40 + */ + +#if defined(CONFIG_ARCH_CHIP_MK20DN32VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DX32VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DN64VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DX64VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DN128VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DX128VLH5) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +/* MK20DX---VLH7 + * + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO + * FREQ CNT FLASH FLASH + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * MK20DX64VLH7 72 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40 + * MK20DX128VLH7 72 MHz 64 LQFP 160 KB 128 KB 2 KB 32 KB 40 + * MK20DX256VLH7 72 MHz 64 LQFP 288 KB 256 KB 2 KB 64 KB 40 + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + */ + +#elif defined(CONFIG_ARCH_CHIP_MK20DX64VLH7) || defined(CONFIG_ARCH_CHIP_MK20DX128VLH7) || \ + defined(CONFIG_ARCH_CHIP_MK20DX256VLH7) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \ + defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X128VFX50) || defined(CONFIG_ARCH_CHIP_MK40X128VLH50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLK50) || defined(CONFIG_ARCH_CHIP_MK40X128VMB50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLL50) || defined(CONFIG_ARCH_CHIP_MK40X128VML50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VFX72) || defined(CONFIG_ARCH_CHIP_MK40X128VLH72) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLK72) || defined(CONFIG_ARCH_CHIP_MK40X128VMB72) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLL72) || defined(CONFIG_ARCH_CHIP_MK40X128VML72) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X256VLK72) || defined(CONFIG_ARCH_CHIP_MK40X256VMB72) || \ + defined(CONFIG_ARCH_CHIP_MK40X256VLL72) || defined(CONFIG_ARCH_CHIP_MK40X256VML72) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40N512VLK100) || defined(CONFIG_ARCH_CHIP_MK40N512VMB100) || \ + defined(CONFIG_ARCH_CHIP_MK40N512VLL100) || defined(CONFIG_ARCH_CHIP_MK40N512VML100) || \ + defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60FN1M0VLQ12) + +/* Verified to Document Number: K60P144M100SF2V2RM Rev. 2 Jun 2012 */ + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_01 + +/* SIM Register Configuration */ + +# define KINETIS_SIM_HAS_SOPT1 1 /* SoC has SOPT1 Register */ +# undef KINETIS_SIM_HAS_SOPT1_OSC32KOUT /* SoC has SOPT1[OSC32KOUT] */ +# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL 1 /* SoC has SOPT1[OSC32KSEL] */ +# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS 1 /* SoC has 1 bit SOPT1[OSC32KSEL] */ +# define KINETIS_SIM_HAS_SOPT1_RAMSIZE 1 /* SoC has SOPT1[RAMSIZE] */ +# define KINETIS_SIM_HAS_SOPT1_USBREGEN 1 /* SoC has SOPT1[USBREGEN] */ +# define KINETIS_SIM_HAS_SOPT1_USBSSTBY 1 /* SoC has SOPT1[USBSSTBY] */ +# define KINETIS_SIM_HAS_SOPT1_USBVSTBY 1 /* SoC has SOPT1[USBVSTBY] */ +# define KINETIS_SIM_HAS_SOPT1CFG /* SoC has SOPT1CFG Register */ +# define KINETIS_SIM_HAS_SOPT1CFG_URWE 1 /* SoC has SOPT1CFG[URWE] */ +# define KINETIS_SIM_HAS_SOPT1CFG_USSWE 1 /* SoC has SOPT1CFG[USSWE] */ +# define KINETIS_SIM_HAS_SOPT1CFG_UVSWE 1 /* SoC has SOPT1CFG[UVSWE] */ +# undef KINETIS_SIM_HAS_USBPHYCTL /* SoC has USBPHYCTL Register */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USB3VOUTTRG /* SoC has USBPHYCTL[USB3VOUTTRG] */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM /* SoC has USBPHYCTL[USBDISILIM] */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USBVREGPD /* SoC has USBPHYCTL[USBVREGPD] */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL /* SoC has USBPHYCTL[USBVREGSEL] */ +# define KINETIS_SIM_HAS_SOPT2 1 /* SoC has SOPT2 Register */ +# define KINETIS_SIM_HAS_SOPT2_FBSL 1 /* SoC has SOPT2[FBSL] */ +# define KINETIS_SIM_HAS_SOPT2_CMTUARTPAD 1 /* SoC has SOPT2[CMTUARTPAD] */ +# define KINETIS_SIM_HAS_SOPT2_FLEXIOSRC 1 /* SoC has SOPT2[FLEXIOSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_LPUARTSRC /* SoC has SOPT2[LPUARTSRC] */ +# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL 1 /* SoC has SOPT2[PLLFLLSEL] */ +# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS 2 /* SoC has 2 bits of SOPT2[PLLFLLSEL] */ +# undef KINETIS_SIM_HAS_SOPT2_PTD7PAD /* SoC has SOPT2[PTD7PAD] */ +# undef KINETIS_SIM_HAS_SOPT2_RMIISRC /* SoC has SOPT2[RMIISRC] */ +# define KINETIS_SIM_HAS_SOPT2_RTCCLKOUTSEL 1 /* SoC has SOPT2[RTCCLKOUTSEL] */ +# define KINETIS_SIM_HAS_SOPT2_CLKOUTSEL 1 /* SoC has SOPT2[CLKOUTSEL] */ +# define KINETIS_SIM_HAS_SOPT2_SDHCSRC 1 /* SoC has SOPT2[SDHCSRC] */ +# define KINETIS_SIM_HAS_SOPT2_NFCSRC 1 /* SoC has SOPT2[NFCSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_I2SSRC /* SoC has SOPT2[I2SSRC] */ +# define KINETIS_SIM_HAS_SOPT2_TIMESRC 1 /* SoC has SOPT2[TIMESRC] */ +# undef KINETIS_SIM_HAS_SOPT2_TPMSRC /* SoC has SOPT2[TPMSRC] */ +# define KINETIS_SIM_HAS_SOPT2_USBFSRC 1 /* SoC has SOPT2[USBFSRC] */ +# define KINETIS_SIM_HAS_SOPT2_TRACECLKSEL 1 /* SoC has SOPT2[TRACECLKSEL] */ +# undef KINETIS_SIM_HAS_SOPT2_USBREGEN /* SoC has SOPT2[USBREGEN] */ +# undef KINETIS_SIM_HAS_SOPT2_USBSLSRC /* SoC has SOPT2[USBSLSRC] */ +# define KINETIS_SIM_HAS_SOPT2_USBHSRC 1 /* SoC has SOPT2[USBHSRC] */ +# define KINETIS_SIM_HAS_SOPT2_USBSRC 1 /* SoC has SOPT2[USBSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_MCGCLKSEL /* SoC has SOPT2[MCGCLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4 1 /* SoC has SOPT4 Register */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT0 1 /* SoC has SOPT4[FTM0FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT1 1 /* SoC has SOPT4[FTM0FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT2 1 /* SoC has SOPT4[FTM0FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT3 1 /* SoC has SOPT4[FTM0FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0TRG0SRC 1 /* SoC has SOPT4[FTM0TRG0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0TRG1SRC 1 /* SoC has SOPT4[FTM0TRG1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC 3 /* SoC has SOPT4[FTM1CH0SRC] 1, 3 if SOF */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT0 1 /* SoC has SOPT4[FTM1FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT1 1 /* SoC has SOPT4[FTM1FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT2 1 /* SoC has SOPT4[FTM1FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT3 1 /* SoC has SOPT4[FTM1FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2CH0SRC 1 /* SoC has SOPT4[FTM2CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM2CH1SRC /* SoC has SOPT4[FTM2CH1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT0 1 /* SoC has SOPT4[FTM2FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT1 1 /* SoC has SOPT4[FTM2FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT2 1 /* SoC has SOPT4[FTM2FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT3 1 /* SoC has SOPT4[FTM2FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC 1 /* SoC has SOPT4[FTM3CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT0 1 /* SoC has SOPT4[FTM3FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT1 1 /* SoC has SOPT4[FTM3FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT2 1 /* SoC has SOPT4[FTM3FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT3 1 /* SoC has SOPT4[FTM3FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC 1 /* SoC has SOPT4[FTM3TRG0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC 1 /* SoC has SOPT4[FTM3TRG1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_TPM0CLKSEL 1 /* SoC has SOPT4[TPM0CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4_TPM1CH0SRC 1 /* SoC has SOPT4[TPM1CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_TPM1CLKSEL 1 /* SoC has SOPT4[TPM1CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC 1 /* SoC has SOPT4[TPM2CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL 1 /* SoC has SOPT4[TPM2CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT5 1 /* SoC has SOPT5 Register */ +# undef KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC /* SoC has SOPT5[LPUART0RXSRC] */ +# undef KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC /* SoC has SOPT5[LPUART0TXSRC] */ +# define KINETIS_SIM_HAS_SOPT6 1 /* SoC has SOPT6 Register */ +# define KINETIS_SIM_HAS_SOPT6_MCC 1 /* SoC has SOPT6[MCC] */ +# define KINETIS_SIM_HAS_SOPT6_PCR 1 /* SoC has SOPT6[PCR] */ +# undef KINETIS_SIM_HAS_SOPT6_RSTFLTSEL /* SoC has SOPT6[RSTFLTSEL] */ +# undef KINETIS_SIM_HAS_SOPT6_RSTFLTEN /* SoC has SOPT6[RSTFLTEN] */ +# define KINETIS_SIM_HAS_SOPT7 1 /* SoC has SOPT7 Register */ +# define KINETIS_SIM_HAS_SOPT7_ADC0ALTTRGSEL 1 /* SoC has SOPT7[ADC0ALTTRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1ALTTRGSEL 1 /* SoC has SOPT7[ADC1ALTTRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC0PRETRGSEL 1 /* SoC has SOPT7[ADC0PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1PRETRGSEL 1 /* SoC has SOPT7[ADC1PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC2PRETRGSEL 1 /* SoC has SOPT7[ADC2PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC3PRETRGSEL 1 /* SoC has SOPT7[ADC3PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL 15 /* SoC has 15 SOPT7[ADC0TRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL 15 /* SoC has 15 SOPT7[ADC1TRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL 15 /* SoC has 15 SOPT7[ADC2TRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL 15 /* SoC has 15 SOPT7[ADC3TRGSEL] */ +# define KINETIS_SIM_SOPT7_ADC0ALTTRGEN 1 /* ADC0 alternate trigger enable */ +# define KINETIS_SIM_SOPT7_ADC1ALTTRGEN 1 /* ADC1 alternate trigger enable */ +# define KINETIS_SIM_SOPT7_ADC2ALTTRGEN 1 /* ADC2 alternate trigger enable */ +# define KINETIS_SIM_SOPT7_ADC3ALTTRGEN 1 /* ADC3 alternate trigger enable */ +# undef KINETIS_SIM_HAS_SOPT8 /* SoC has SOPT8 Register */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0SYNCBIT /* SoC has SOPT8[FTM0SYNCBIT] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM1SYNCBIT /* SoC has SOPT8[FTM1SYNCBIT] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM2SYNCBIT /* SoC has SOPT8[FTM2SYNCBIT] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3SYNCBIT /* SoC has SOPT8[FTM3SYNCBIT] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH0SRC /* SoC has SOPT8[FTM0OCH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH1SRC /* SoC has SOPT8[FTM0OCH1SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH2SRC /* SoC has SOPT8[FTM0OCH2SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH3SRC /* SoC has SOPT8[FTM0OCH3SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH4SRC /* SoC has SOPT8[FTM0OCH4SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH5SRC /* SoC has SOPT8[FTM0OCH5SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH6SRC /* SoC has SOPT8[FTM0OCH6SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH7SRC /* SoC has SOPT8[FTM0OCH7SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH0SRC /* SoC has SOPT8[FTM3OCH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH1SRC /* SoC has SOPT8[FTM3OCH1SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH2SRC /* SoC has SOPT8[FTM3OCH2SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH3SRC /* SoC has SOPT8[FTM3OCH3SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH4SRC /* SoC has SOPT8[FTM3OCH4SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH5SRC /* SoC has SOPT8[FTM3OCH5SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH6SRC /* SoC has SOPT8[FTM3OCH6SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH7SRC /* SoC has SOPT8[FTM3OCH7SRC] */ +# undef KINETIS_SIM_HAS_SOPT9 /* SoC has SOPT9 Register */ +# undef KINETIS_SIM_HAS_SOPT9_TPM1CH0SRC /* SoC has SOPT9[TPM1CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT9_TPM2CH0SRC /* SoC has SOPT9[TPM2CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT9_TPM1CLKSEL /* SoC has SOPT9[TPM1CLKSEL] */ +# undef KINETIS_SIM_HAS_SOPT9_TPM2CLKSEL /* SoC has SOPT9[TPM2CLKSEL] */ +# define KINETIS_SIM_HAS_SDID 1 /* SoC has SDID Register */ +# undef KINETIS_SIM_HAS_SDID_DIEID /* SoC has SDID[DIEID] */ +# define KINETIS_SIM_HAS_SDID_FAMID 1 /* SoC has SDID[FAMID] */ +# undef KINETIS_SIM_HAS_SDID_FAMILYID /* SoC has SDID[FAMILYID] */ +# undef KINETIS_SIM_HAS_SDID_SERIESID /* SoC has SDID[SERIESID] */ +# undef KINETIS_SIM_HAS_SDID_SRAMSIZE /* SoC has SDID[SRAMSIZE] */ +# undef KINETIS_SIM_HAS_SDID_SUBFAMID /* SoC has SDID[SUBFAMID] */ +# define KINETIS_SIM_HAS_SCGC1 1 /* SoC has _SCGC1 Register */ +# define KINETIS_SIM_HAS_SCGC1_UART5 1 /* SoC has SCGC1[UART5] */ +# define KINETIS_SIM_HAS_SCGC1_UART4 1 /* SoC has SCGC1[UART4] */ +# undef KINETIS_SIM_HAS_SCGC1_I2C3 /* SoC has SCGC1[I2C3] */ +# undef KINETIS_SIM_HAS_SCGC1_I2C2 /* SoC has SCGC1[I2C2] */ +# define KINETIS_SIM_HAS_SCGC1_OSC1 1 /* SoC has SCGC1[OSC1] */ +# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has _SCGC2 Register */ +# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has SCGC2 Register */ +# define KINETIS_SIM_HAS_SCGC2_ENET 1 /* SoC has SCGC2[ENET] */ +# undef KINETIS_SIM_HAS_SCGC2_LPUART0 /* SoC has SCGC2[LPUART0] */ +# undef KINETIS_SIM_HAS_SCGC2_TPM1 /* SoC has SCGC2[TPM1] */ +# undef KINETIS_SIM_HAS_SCGC2_TPM2 /* SoC has SCGC2[TPM2] */ +# define KINETIS_SIM_HAS_SCGC3 1 /* SoC has SCGC3 Register */ +# define KINETIS_SIM_HAS_SCGC3_RNGA 1 /* SoC has SCGC3[RNGA] */ +# undef KINETIS_SIM_HAS_SCGC3_USBHS /* SoC has SCGC3[USBHS] */ +# undef KINETIS_SIM_HAS_SCGC3_USBHSPHY /* SoC has SCGC3[USBHSPHY] */ +# undef KINETIS_SIM_HAS_SCGC3_USBHSDCD /* SoC has SCGC3[USBHSDCD] */ +# define KINETIS_SIM_HAS_SCGC3_FLEXCAN1 1 /* SoC has SCGC3[FLEXCAN1] */ +# define KINETIS_SIM_HAS_SCGC3_NFC 1 /* SoC has SCGC3[NFC] */ +# define KINETIS_SIM_HAS_SCGC3_SPI2 1 /* SoC has SCGC3[SPI2] */ +# define KINETIS_SIM_HAS_SCGC3_SAI1 1 /* SoC has SCGC3[SAI1] */ +# define KINETIS_SIM_HAS_SCGC3_SDHC 1 /* SoC has SCGC3[SDHC] */ +# define KINETIS_SIM_HAS_SCGC3_FTM2 1 /* SoC has SCGC3[FTM2] */ +# define KINETIS_SIM_HAS_SCGC3_FTM3 1 /* SoC has SCGC3[FTM3] */ +# define KINETIS_SIM_HAS_SCGC3_ADC1 1 /* SoC has SCGC3[ADC1] */ +# define KINETIS_SIM_HAS_SCGC3_ADC3 1 /* SoC has SCGC3[ADC3] */ +# undef KINETIS_SIM_HAS_SCGC3_SLCD /* SoC has SCGC3[SLCD] */ +# define KINETIS_SIM_HAS_SCGC4 1 /* SoC has SCGC4 Register */ +# define KINETIS_SIM_HAS_SCGC4_LLWU 1 /* SoC has SCGC4[LLWU] clock gate */ +# define KINETIS_SIM_HAS_SCGC4_UART0 1 /* SoC has SCGC4[UART0] */ +# define KINETIS_SIM_HAS_SCGC4_UART1 1 /* SoC has SCGC4[UART1] */ +# define KINETIS_SIM_HAS_SCGC4_UART2 1 /* SoC has SCGC4[UART2] */ +# define KINETIS_SIM_HAS_SCGC4_UART3 1 /* SoC has SCGC4[UART3] */ +# define KINETIS_SIM_HAS_SCGC5 1 /* SoC has _SCGC5 Register */ +# undef KINETIS_SIM_HAS_SCGC5_REGFILE /* SoC has SCGC5[REGFILE] */ +# define KINETIS_SIM_HAS_SCGC5_TSI 1 /* SoC has SCGC5[TSI] */ +# define KINETIS_SIM_HAS_SCGC5_PORTF 1 /* SoC has SCGC5[PORTF] */ +# define KINETIS_SIM_HAS_SCGC6 1 /* SoC has SCGC6 Register */ +# undef KINETIS_SIM_HAS_SCGC6_FTFL /* SoC has SCGC6[FTFL] */ +# define KINETIS_SIM_HAS_SCGC6_DMAMUX1 1 /* SoC has SCGC6[DEMUX1] */ +# define KINETIS_SIM_HAS_SCGC6_USBHS 1 /* SoC has SCGC6[USBHS] */ +# define KINETIS_SIM_HAS_SCGC6_RNGA 1 /* SoC has SCGC6[RNGA] */ +# undef KINETIS_SIM_HAS_SCGC6_FTM2 /* SoC has SCGC6[FTM2] */ +# define KINETIS_SIM_HAS_SCGC6_ADC2 1 /* SoC has SCGC6[ADC2] */ +# undef KINETIS_SIM_HAS_SCGC6_DAC0 /* SoC has SCGC6[DAC0] */ +# define KINETIS_SIM_HAS_SCGC7 1 /* SoC has SCGC7 Register */ +# define KINETIS_SIM_HAS_SCGC7_FLEXBUS 1 /* SoC has SCGC7[FLEXBUS] */ +# define KINETIS_SIM_HAS_SCGC7_DMA 1 /* SoC has SCGC7[DMS] */ +# define KINETIS_SIM_HAS_SCGC7_MPU 1 /* SoC has SCGC7[MPU] */ +# undef KINETIS_SIM_HAS_SCGC7_SDRAMC /* SoC has SCGC7[SDRAMC] */ +# define KINETIS_SIM_HAS_CLKDIV1 1 /* SoC has CLKDIV1 Register */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV2 1 /* SoC has CLKDIV1[OUTDIV2] */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV3 1 /* SoC has CLKDIV1[OUTDIV3] */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV4 1 /* SoC has CLKDIV1[OUTDIV4] */ +# undef KINETIS_SIM_HAS_CLKDIV1_OUTDIV5 /* SoC has CLKDIV1[OUTDIV5] */ +# define KINETIS_SIM_HAS_CLKDIV2 1 /* SoC has CLKDIV2 Register */ +# define KINETIS_SIM_HAS_CLKDIV2_USBDIV 1 /* SoC has CLKDIV2[USBDIV] */ +# define KINETIS_SIM_HAS_CLKDIV2_USBFRAC 1 /* SoC has CLKDIV2[USBFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBFSDIV /* SoC has CLKDIV2[USBFSDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBFSFRAC /* SoC has CLKDIV2[USBFSFRAC] */ +# define KINETIS_SIM_HAS_CLKDIV2_USBHSDIV 1 /* SoC has CLKDIV2[USBHSDIV] */ +# define KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC 1 /* SoC has CLKDIV2[USBHSFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_I2SDIV /* SoC has CLKDIV2[I2SDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_I2SFRAC /* SoC has CLKDIV2[I2SFRAC] */ +# define KINETIS_SIM_HAS_FCFG1 1 /* SoC has FCFG1 Register */ +# define KINETIS_SIM_HAS_FCFG1_DEPART 1 /* SoC has FCFG1[DEPART] */ +# define KINETIS_SIM_HAS_FCFG1_EESIZE 1 /* SoC has FCFG1[EESIZE] */ +# undef KINETIS_SIM_HAS_FCFG1_FLASHDIS /* SoC has FCFG1[FLASHDIS] */ +# undef KINETIS_SIM_HAS_FCFG1_FLASHDOZE /* SoC has FCFG1[FLASHDOZE] */ +# define KINETIS_SIM_HAS_FCFG1_FTFDIS 1 /* SoC has FCFG1[FTFDIS] */ +# define KINETIS_SIM_HAS_FCFG1_NVMSIZE 1 /* SoC has FCFG1[NVMSIZE] */ +# define KINETIS_SIM_HAS_FCFG2 1 /* SoC has FCFG2 Register */ +# define KINETIS_SIM_HAS_FCFG2_MAXADDR0 6 /* SoC has n bit of FCFG2[MAXADDR0] */ +# define KINETIS_SIM_HAS_FCFG2_MAXADDR1 6 /* SoC has n bit of FCFG2[MAXADDR1] */ +# define KINETIS_SIM_HAS_FCFG2_PFLSH 1 /* SoC has FCFG2[PFLSH] */ +# define KINETIS_SIM_HAS_FCFG2_SWAPPFLSH 1 /* SoC has FCFG2[SWAPPFLSH] */ +# define KINETIS_SIM_HAS_UIDH 1 /* SoC has UIDH Register */ +# define KINETIS_SIM_HAS_UIDMH 1 /* SoC has UIDMH Register */ +# define KINETIS_SIM_HAS_UIDML 1 /* SoC has UIDML Register */ +# define KINETIS_SIM_HAS_UIDL 1 /* SoC has UIDL Register */ +# undef KINETIS_SIM_HAS_CLKDIV3 /* SoC has CLKDIV3 Register */ +# undef KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV /* SoC has CLKDIV3[PLLFLLDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC /* SoC has CLKDIV3[PLLFLLFRAC] */ +# define KINETIS_SIM_HAS_CLKDIV4 1 /* SoC has CLKDIV4 Register */ +# define KINETIS_SIM_HAS_CLKDIV4_TRACEDIV 1 /* SoC has CLKDIV4[TRACEDIV] */ +# define KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC 1 /* SoC has CLKDIV4[TRACEFRAC] */ +# define KINETIS_SIM_HAS_CLKDIV4_NFCDIV 1 /* SoC has CLKDIV4[NFCDIV] */ +# define KINETIS_SIM_HAS_CLKDIV4_NFCFRAC 1 /* SoC has CLKDIV4[NFCFRAC] */ +# define KINETIS_SIM_HAS_MCR 1 /* SoC has MCR Register */ + +#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || \ + defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \ + defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || \ + defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12) + +/* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */ + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_04 + +/* SIM Register Configuration */ + +# define KINETIS_SIM_HAS_SOPT1 1 /* SoC has SOPT1 Register */ +# undef KINETIS_SIM_HAS_SOPT1_OSC32KOUT /* SoC has SOPT1[OSC32KOUT] */ +# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL 1 /* SoC has SOPT1[OSC32KSEL] */ +# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS 2 /* SoC has 2 bits of SOPT1[OSC32KSEL] */ +# define KINETIS_SIM_HAS_SOPT1_RAMSIZE 1 /* SoC has SOPT1[RAMSIZE] */ +# define KINETIS_SIM_HAS_SOPT1_USBREGEN 1 /* SoC has SOPT1[USBREGEN] */ +# define KINETIS_SIM_HAS_SOPT1_USBSSTBY 1 /* SoC has SOPT1[USBSSTBY] */ +# define KINETIS_SIM_HAS_SOPT1_USBVSTBY 1 /* SoC has SOPT1[USBVSTBY] */ +# define KINETIS_SIM_HAS_SOPT1CFG /* SoC has SOPT1CFG Register */ +# define KINETIS_SIM_HAS_SOPT1CFG_URWE 1 /* SoC has SOPT1CFG[URWE] */ +# define KINETIS_SIM_HAS_SOPT1CFG_USSWE 1 /* SoC has SOPT1CFG[USSWE] */ +# define KINETIS_SIM_HAS_SOPT1CFG_UVSWE 1 /* SoC has SOPT1CFG[UVSWE] */ +# undef KINETIS_SIM_HAS_USBPHYCTL /* SoC has USBPHYCTL Register */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USB3VOUTTRG /* SoC has USBPHYCTL[USB3VOUTTRG] */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM /* SoC has USBPHYCTL[USBDISILIM] */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USBVREGPD /* SoC has USBPHYCTL[USBVREGPD] */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL /* SoC has USBPHYCTL[USBVREGSEL] */ +# define KINETIS_SIM_HAS_SOPT2 1 /* SoC has SOPT2 Register */ +# define KINETIS_SIM_HAS_SOPT2_FBSL 1 /* SoC has SOPT2[FBSL] */ +# undef KINETIS_SIM_HAS_SOPT2_CMTUARTPAD /* SoC has SOPT2[CMTUARTPAD] */ +# define KINETIS_SIM_HAS_SOPT2_FLEXIOSRC 1 /* SoC has SOPT2[FLEXIOSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_LPUARTSRC /* SoC has SOPT2[LPUARTSRC] */ +# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL 1 /* SoC has SOPT2[PLLFLLSEL] */ +# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS 2 /* SoC has 2 bits of SOPT2[PLLFLLSEL] */ +# define KINETIS_SIM_HAS_SOPT2_PTD7PAD 1 /* SoC has SOPT2[PTD7PAD] */ +# define KINETIS_SIM_HAS_SOPT2_RMIISRC 1 /* SoC has SOPT2[RMIISRC] */ +# define KINETIS_SIM_HAS_SOPT2_RTCCLKOUTSEL 1 /* SoC has SOPT2[RTCCLKOUTSEL] */ +# define KINETIS_SIM_HAS_SOPT2_CLKOUTSEL 1 /* SoC has SOPT2[CLKOUTSEL] */ +# define KINETIS_SIM_HAS_SOPT2_SDHCSRC 1 /* SoC has SOPT2[SDHCSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_NFCSRC /* SoC has SOPT2[NFCSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_I2SSRC /* SoC has SOPT2[I2SSRC] */ +# define KINETIS_SIM_HAS_SOPT2_TIMESRC 1 /* SoC has SOPT2[TIMESRC] */ +# undef KINETIS_SIM_HAS_SOPT2_TPMSRC /* SoC has SOPT2[TPMSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_USBFSRC /* SoC has SOPT2[USBFSRC] */ +# define KINETIS_SIM_HAS_SOPT2_TRACECLKSEL 1 /* SoC has SOPT2[TRACECLKSEL] */ +# undef KINETIS_SIM_HAS_SOPT2_USBREGEN /* SoC has SOPT2[USBREGEN] */ +# undef KINETIS_SIM_HAS_SOPT2_USBSLSRC /* SoC has SOPT2[USBSLSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_USBHSRC /* SoC has SOPT2[USBHSRC] */ +# define KINETIS_SIM_HAS_SOPT2_USBSRC 1 /* SoC has SOPT2[USBSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_MCGCLKSEL /* SoC has SOPT2[MCGCLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4 1 /* SoC has SOPT4 Register */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT0 1 /* SoC has SOPT4[FTM0FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT1 1 /* SoC has SOPT4[FTM0FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT2 1 /* SoC has SOPT4[FTM0FLT2] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM0FLT3 /* SoC has SOPT4[FTM0FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0TRG0SRC 1 /* SoC has SOPT4[FTM0TRG0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0TRG1SRC 1 /* SoC has SOPT4[FTM0TRG1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC 3 /* SoC has SOPT4[FTM1CH0SRC] 1, 3 if SOF */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT0 1 /* SoC has SOPT4[FTM1FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT1 1 /* SoC has SOPT4[FTM1FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT2 1 /* SoC has SOPT4[FTM1FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT3 1 /* SoC has SOPT4[FTM1FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2CH0SRC 1 /* SoC has SOPT4[FTM2CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM2CH1SRC /* SoC has SOPT4[FTM2CH1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT0 1 /* SoC has SOPT4[FTM2FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT1 1 /* SoC has SOPT4[FTM2FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT2 1 /* SoC has SOPT4[FTM2FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT3 1 /* SoC has SOPT4[FTM2FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC 1 /* SoC has SOPT4[FTM3CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT0 1 /* SoC has SOPT4[FTM3FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT1 1 /* SoC has SOPT4[FTM3FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT2 1 /* SoC has SOPT4[FTM3FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT3 1 /* SoC has SOPT4[FTM3FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC 1 /* SoC has SOPT4[FTM3TRG0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC 1 /* SoC has SOPT4[FTM3TRG1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_TPM0CLKSEL 1 /* SoC has SOPT4[TPM0CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4_TPM1CH0SRC 1 /* SoC has SOPT4[TPM1CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_TPM1CLKSEL 1 /* SoC has SOPT4[TPM1CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC 1 /* SoC has SOPT4[TPM2CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL 1 /* SoC has SOPT4[TPM2CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT5 1 /* SoC has SOPT5 Register */ +# undef KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC /* SoC has SOPT5[LPUART0RXSRC] */ +# undef KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC /* SoC has SOPT5[LPUART0TXSRC] */ +# undef KINETIS_SIM_HAS_SOPT6 /* SoC has SOPT6 Register */ +# undef KINETIS_SIM_HAS_SOPT6_MCC /* SoC has SOPT6[MCC] */ +# undef KINETIS_SIM_HAS_SOPT6_PCR /* SoC has SOPT6[PCR] */ +# undef KINETIS_SIM_HAS_SOPT6_RSTFLTSEL /* SoC has SOPT6[RSTFLTSEL] */ +# undef KINETIS_SIM_HAS_SOPT6_RSTFLTEN /* SoC has SOPT6[RSTFLTEN] */ +# define KINETIS_SIM_HAS_SOPT7 1 /* SoC has SOPT7 Register */ +# define KINETIS_SIM_HAS_SOPT7_ADC0ALTTRGSEL 1 /* SoC has SOPT7[ADC0ALTTRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1ALTTRGSEL 1 /* SoC has SOPT7[ADC1ALTTRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC0PRETRGSEL 1 /* SoC has SOPT7[ADC0PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1PRETRGSEL 1 /* SoC has SOPT7[ADC1PRETRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC2PRETRGSEL /* SoC has SOPT7[ADC2PRETRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC3PRETRGSEL /* SoC has SOPT7[ADC3PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL 14 /* SoC has 10 SOPT7[ADC0TRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL 14 /* SoC has 10 SOPT7[ADC1TRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL /* SoC has 10 SOPT7[ADC2TRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL /* SoC has 10 SOPT7[ADC3TRGSEL] */ +# define KINETIS_SIM_SOPT7_ADC0ALTTRGEN 1 /* ADC0 alternate trigger enable */ +# define KINETIS_SIM_SOPT7_ADC1ALTTRGEN 1 /* ADC1 alternate trigger enable */ +# undef KINETIS_SIM_SOPT7_ADC2ALTTRGEN /* ADC2 alternate trigger enable */ +# undef KINETIS_SIM_SOPT7_ADC3ALTTRGEN /* ADC3 alternate trigger enable */ +# undef KINETIS_SIM_HAS_SOPT8 /* SoC has SOPT8 Register */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0SYNCBIT /* SoC has SOPT8[FTM0SYNCBIT] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM1SYNCBIT /* SoC has SOPT8[FTM1SYNCBIT] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM2SYNCBIT /* SoC has SOPT8[FTM2SYNCBIT] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3SYNCBIT /* SoC has SOPT8[FTM3SYNCBIT] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH0SRC /* SoC has SOPT8[FTM0OCH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH1SRC /* SoC has SOPT8[FTM0OCH1SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH2SRC /* SoC has SOPT8[FTM0OCH2SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH3SRC /* SoC has SOPT8[FTM0OCH3SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH4SRC /* SoC has SOPT8[FTM0OCH4SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH5SRC /* SoC has SOPT8[FTM0OCH5SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH6SRC /* SoC has SOPT8[FTM0OCH6SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH7SRC /* SoC has SOPT8[FTM0OCH7SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH0SRC /* SoC has SOPT8[FTM3OCH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH1SRC /* SoC has SOPT8[FTM3OCH1SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH2SRC /* SoC has SOPT8[FTM3OCH2SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH3SRC /* SoC has SOPT8[FTM3OCH3SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH4SRC /* SoC has SOPT8[FTM3OCH4SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH5SRC /* SoC has SOPT8[FTM3OCH5SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH6SRC /* SoC has SOPT8[FTM3OCH6SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH7SRC /* SoC has SOPT8[FTM3OCH7SRC] */ +# undef KINETIS_SIM_HAS_SOPT9 /* SoC has SOPT9 Register */ +# undef KINETIS_SIM_HAS_SOPT9_TPM1CH0SRC /* SoC has SOPT9[TPM1CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT9_TPM2CH0SRC /* SoC has SOPT9[TPM2CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT9_TPM1CLKSEL /* SoC has SOPT9[TPM1CLKSEL] */ +# undef KINETIS_SIM_HAS_SOPT9_TPM2CLKSEL /* SoC has SOPT9[TPM2CLKSEL] */ +# define KINETIS_SIM_HAS_SDID 1 /* SoC has SDID Register */ +# define KINETIS_SIM_HAS_SDID_DIEID 1 /* SoC has SDID[DIEID] */ +# define KINETIS_SIM_HAS_SDID_FAMID 1 /* SoC has SDID[FAMID] */ +# define KINETIS_SIM_HAS_SDID_FAMILYID 1 /* SoC has SDID[FAMILYID] */ +# define KINETIS_SIM_HAS_SDID_SERIESID 1 /* SoC has SDID[SERIESID] */ +# undef KINETIS_SIM_HAS_SDID_SRAMSIZE /* SoC has SDID[SRAMSIZE] */ +# define KINETIS_SIM_HAS_SDID_SUBFAMID 1 /* SoC has SDID[SUBFAMID] */ +# define KINETIS_SIM_HAS_SCGC1 1 /* SoC has _SCGC1 Register */ +# define KINETIS_SIM_HAS_SCGC1_UART5 1 /* SoC has SCGC1[UART5] */ +# define KINETIS_SIM_HAS_SCGC1_UART4 1 /* SoC has SCGC1[UART4] */ +# undef KINETIS_SIM_HAS_SCGC1_I2C3 /* SoC has SCGC1[I2C3] */ +# define KINETIS_SIM_HAS_SCGC1_I2C2 1 /* SoC has SCGC1[I2C2] */ +# undef KINETIS_SIM_HAS_SCGC1_OSC1 /* SoC has SCGC1[OSC1] */ +# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has _SCGC2 Register */ +# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has SCGC2 Register */ +# define KINETIS_SIM_HAS_SCGC2_ENET 1 /* SoC has SCGC2[ENET] */ +# undef KINETIS_SIM_HAS_SCGC2_LPUART0 /* SoC has SCGC2[LPUART0] */ +# undef KINETIS_SIM_HAS_SCGC2_TPM1 /* SoC has SCGC2[TPM1] */ +# undef KINETIS_SIM_HAS_SCGC2_TPM2 /* SoC has SCGC2[TPM2] */ +# define KINETIS_SIM_HAS_SCGC3 1 /* SoC has SCGC3 Register */ +# define KINETIS_SIM_HAS_SCGC3_RNGA 1 /* SoC has SCGC3[RNGA] */ +# undef KINETIS_SIM_HAS_SCGC3_USBHS /* SoC has SCGC3[USBHS] */ +# undef KINETIS_SIM_HAS_SCGC3_USBHSPHY /* SoC has SCGC3[USBHSPHY] */ +# undef KINETIS_SIM_HAS_SCGC3_USBHSDCD /* SoC has SCGC3[USBHSDCD] */ +# undef KINETIS_SIM_HAS_SCGC3_FLEXCAN1 /* SoC has SCGC3[FLEXCAN1] */ +# undef KINETIS_SIM_HAS_SCGC3_NFC /* SoC has SCGC3[NFC] */ +# define KINETIS_SIM_HAS_SCGC3_SPI2 1 /* SoC has SCGC3[SPI2] */ +# undef KINETIS_SIM_HAS_SCGC3_SAI1 /* SoC has SCGC3[SAI1] */ +# define KINETIS_SIM_HAS_SCGC3_SDHC 1 /* SoC has SCGC3[SDHC] */ +# define KINETIS_SIM_HAS_SCGC3_FTM2 1 /* SoC has SCGC3[FTM2] */ +# define KINETIS_SIM_HAS_SCGC3_FTM3 1 /* SoC has SCGC3[FTM3] */ +# define KINETIS_SIM_HAS_SCGC3_ADC1 1 /* SoC has SCGC3[ADC1] */ +# undef KINETIS_SIM_HAS_SCGC3_ADC3 /* SoC has SCGC3[ADC3] */ +# undef KINETIS_SIM_HAS_SCGC3_SLCD /* SoC has SCGC3[SLCD] */ +# define KINETIS_SIM_HAS_SCGC4 1 /* SoC has SCGC4 Register */ +# undef KINETIS_SIM_HAS_SCGC4_LLWU /* SoC has SCGC4[LLWU] clock gate */ +# define KINETIS_SIM_HAS_SCGC4_UART0 1 /* SoC has SCGC4[UART0] */ +# define KINETIS_SIM_HAS_SCGC4_UART1 1 /* SoC has SCGC4[UART1] */ +# define KINETIS_SIM_HAS_SCGC4_UART2 1 /* SoC has SCGC4[UART2] */ +# define KINETIS_SIM_HAS_SCGC4_UART3 1 /* SoC has SCGC4[UART3] */ +# define KINETIS_SIM_HAS_SCGC5 1 /* SoC has _SCGC5 Register */ +# undef KINETIS_SIM_HAS_SCGC5_REGFILE /* SoC has SCGC5[REGFILE] */ +# undef KINETIS_SIM_HAS_SCGC5_TSI /* SoC has SCGC5[TSI] */ +# undef KINETIS_SIM_HAS_SCGC5_PORTF /* SoC has SCGC5[PORTF] */ +# define KINETIS_SIM_HAS_SCGC6 1 /* SoC has SCGC6 Register */ +# define KINETIS_SIM_HAS_SCGC6_FTFL 1 /* SoC has SCGC6[FTFL] */ +# undef KINETIS_SIM_HAS_SCGC6_DMAMUX1 /* SoC has SCGC6[DEMUX1] */ +# undef KINETIS_SIM_HAS_SCGC6_USBHS /* SoC has SCGC6[USBHS] */ +# define KINETIS_SIM_HAS_SCGC6_RNGA 1 /* SoC has SCGC6[RNGA] */ +# define KINETIS_SIM_HAS_SCGC6_FTM2 1 /* SoC has SCGC6[FTM2] */ +# undef KINETIS_SIM_HAS_SCGC6_ADC2 /* SoC has SCGC6[ADC2] */ +# define KINETIS_SIM_HAS_SCGC6_DAC0 1 /* SoC has SCGC6[DAC0] */ +# define KINETIS_SIM_HAS_SCGC7 1 /* SoC has SCGC7 Register */ +# define KINETIS_SIM_HAS_SCGC7_FLEXBUS 1 /* SoC has SCGC7[FLEXBUS] */ +# define KINETIS_SIM_HAS_SCGC7_DMA 1 /* SoC has SCGC7[DMS] */ +# define KINETIS_SIM_HAS_SCGC7_MPU 1 /* SoC has SCGC7[MPU] */ +# undef KINETIS_SIM_HAS_SCGC7_SDRAMC /* SoC has SCGC7[SDRAMC] */ +# define KINETIS_SIM_HAS_CLKDIV1 1 /* SoC has CLKDIV1 Register */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV2 1 /* SoC has CLKDIV1[OUTDIV2] */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV3 1 /* SoC has CLKDIV1[OUTDIV3] */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV4 1 /* SoC has CLKDIV1[OUTDIV4] */ +# undef KINETIS_SIM_HAS_CLKDIV1_OUTDIV5 /* SoC has CLKDIV1[OUTDIV5] */ +# define KINETIS_SIM_HAS_CLKDIV2 1 /* SoC has CLKDIV2 Register */ +# define KINETIS_SIM_HAS_CLKDIV2_USBDIV 1 /* SoC has CLKDIV2[USBDIV] */ +# define KINETIS_SIM_HAS_CLKDIV2_USBFRAC 1 /* SoC has CLKDIV2[USBFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBFSDIV /* SoC has CLKDIV2[USBFSDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBFSFRAC /* SoC has CLKDIV2[USBFSFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBHSDIV /* SoC has CLKDIV2[USBHSDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC /* SoC has CLKDIV2[USBHSFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_I2SDIV /* SoC has CLKDIV2[I2SDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_I2SFRAC /* SoC has CLKDIV2[I2SFRAC] */ +# define KINETIS_SIM_HAS_FCFG1 1 /* SoC has FCFG1 Register */ +# define KINETIS_SIM_HAS_FCFG1_DEPART 1 /* SoC has FCFG1[DEPART] */ +# define KINETIS_SIM_HAS_FCFG1_EESIZE 1 /* SoC has FCFG1[EESIZE] */ +# define KINETIS_SIM_HAS_FCFG1_FLASHDIS 1 /* SoC has FCFG1[FLASHDIS] */ +# define KINETIS_SIM_HAS_FCFG1_FLASHDOZE 1 /* SoC has FCFG1[FLASHDOZE] */ +# undef KINETIS_SIM_HAS_FCFG1_FTFDIS /* SoC has FCFG1[FTFDIS] */ +# define KINETIS_SIM_HAS_FCFG1_NVMSIZE 1 /* SoC has FCFG1[NVMSIZE] */ +# define KINETIS_SIM_HAS_FCFG2 1 /* SoC has FCFG2 Register */ +# define KINETIS_SIM_HAS_FCFG2_MAXADDR0 7 /* SoC has n bit of FCFG2[MAXADDR0] */ +# define KINETIS_SIM_HAS_FCFG2_MAXADDR1 7 /* SoC has n bit of FCFG2[MAXADDR1] */ +# define KINETIS_SIM_HAS_FCFG2_PFLSH 1 /* SoC has FCFG2[PFLSH] */ +# undef KINETIS_SIM_HAS_FCFG2_SWAPPFLSH /* SoC has FCFG2[SWAPPFLSH] */ +# define KINETIS_SIM_HAS_UIDH 1 /* SoC has UIDH Register */ +# define KINETIS_SIM_HAS_UIDMH 1 /* SoC has UIDMH Register */ +# define KINETIS_SIM_HAS_UIDML 1 /* SoC has UIDML Register */ +# define KINETIS_SIM_HAS_UIDL 1 /* SoC has UIDL Register */ +# undef KINETIS_SIM_HAS_CLKDIV3 /* SoC has CLKDIV3 Register */ +# undef KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV /* SoC has CLKDIV3[PLLFLLDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC /* SoC has CLKDIV3[PLLFLLFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV4 /* SoC has CLKDIV4 Register */ +# undef KINETIS_SIM_HAS_CLKDIV4_TRACEDIV /* SoC has CLKDIV4[TRACEDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC /* SoC has CLKDIV4[TRACEFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV4_NFCDIV /* SoC has CLKDIV4[NFCDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV4_NFCFRAC /* SoC has CLKDIV4[NFCFRAC] */ +# undef KINETIS_SIM_HAS_MCR /* SoC has MCR Register */ + +/* MK66F N/X 1M0/2M0 V MD/LQ 18 + * + * --------------- ------- --- ------- ------- ------ ------ ------ ----- + * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO + * FREQ CNT FLASH FLASH + * --------------- ------- --- ------- ------- ------ ------ ------ ----- + * MK66FN2M0VMD18 180 MHz 144 MAPBGA 2 MB — — KB 260 KB 100 + * MK66FX1M0VMD18 180 MHz 144 MAPBGA 1.25 MB 1 MB 4 KB 256 KB 100 + * MK66FN2M0VLQ18 180 MHz 144 LQFP 2 MB — — KB 260 KB 100 + * MK66FX1M0VLQ18 180 MHz 144 LQFP 1.25 MB 1 MB 4 KB 256 KB 100 + */ + +#elif defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \ + defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18) + +/* Verified to Document Number: Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */ + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_06 + +/* SIM Register Configuration */ + +# define KINETIS_SIM_HAS_SOPT1 1 /* SoC has SOPT1 Register */ +# undef KINETIS_SIM_HAS_SOPT1_OSC32KOUT /* SoC has SOPT1[OSC32KOUT] */ +# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL 1 /* SoC has SOPT1[OSC32KSEL] */ +# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS 2 /* SoC has 1 bit SOPT1[OSC32KSEL] */ +# define KINETIS_SIM_HAS_SOPT1_RAMSIZE 1 /* SoC has SOPT1[RAMSIZE] */ +# define KINETIS_SIM_HAS_SOPT1_USBREGEN 1 /* SoC has SOPT1[USBREGEN] */ +# define KINETIS_SIM_HAS_SOPT1_USBSSTBY 1 /* SoC has SOPT1[USBSSTBY] */ +# define KINETIS_SIM_HAS_SOPT1_USBVSTBY 1 /* SoC has SOPT1[USBVSTBY] */ +# define KINETIS_SIM_HAS_SOPT1CFG /* SoC has SOPT1CFG Register */ +# define KINETIS_SIM_HAS_SOPT1CFG_URWE 1 /* SoC has SOPT1CFG[URWE] */ +# define KINETIS_SIM_HAS_SOPT1CFG_USSWE 1 /* SoC has SOPT1CFG[USSWE] */ +# define KINETIS_SIM_HAS_SOPT1CFG_UVSWE 1 /* SoC has SOPT1CFG[UVSWE] */ +# define KINETIS_SIM_HAS_USBPHYCTL 1 /* SoC has USBPHYCTL Register */ +# define KINETIS_SIM_HAS_USBPHYCTL_USB3VOUTTRG 1 /* SoC has USBPHYCTL[USB3VOUTTRG] */ +# define KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM 1 /* SoC has USBPHYCTL[USBDISILIM] */ +# define KINETIS_SIM_HAS_USBPHYCTL_USBVREGPD 1 /* SoC has USBPHYCTL[USBVREGPD] */ +# define KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL 1 /* SoC has USBPHYCTL[USBVREGSEL] */ +# define KINETIS_SIM_HAS_SOPT2 1 /* SoC has SOPT2 Register */ +# define KINETIS_SIM_HAS_SOPT2_FBSL 1 /* SoC has SOPT2[FBSL] */ +# undef KINETIS_SIM_HAS_SOPT2_CMTUARTPAD /* SoC has SOPT2[CMTUARTPAD] */ +# define KINETIS_SIM_HAS_SOPT2_FLEXIOSRC 1 /* SoC has SOPT2[FLEXIOSRC] */ +# define KINETIS_SIM_HAS_SOPT2_LPUARTSRC 1 /* SoC has SOPT2[LPUARTSRC] */ +# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL 1 /* SoC has SOPT2[PLLFLLSEL] */ +# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS 2 /* SoC has 2 bits of SOPT2[PLLFLLSEL] */ +# undef KINETIS_SIM_HAS_SOPT2_PTD7PAD /* SoC has SOPT2[PTD7PAD] */ +# define KINETIS_SIM_HAS_SOPT2_RMIISRC 1 /* SoC has SOPT2[RMIISRC] */ +# define KINETIS_SIM_HAS_SOPT2_RTCCLKOUTSEL 1 /* SoC has SOPT2[RTCCLKOUTSEL] */ +# define KINETIS_SIM_HAS_SOPT2_CLKOUTSEL 1 /* SoC has SOPT2[CLKOUTSEL] */ +# define KINETIS_SIM_HAS_SOPT2_SDHCSRC 1 /* SoC has SOPT2[SDHCSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_NFCSRC /* SoC has SOPT2[NFCSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_I2SSRC /* SoC has SOPT2[I2SSRC] */ +# define KINETIS_SIM_HAS_SOPT2_TIMESRC 1 /* SoC has SOPT2[TIMESRC] */ +# define KINETIS_SIM_HAS_SOPT2_TPMSRC 1 /* SoC has SOPT2[TPMSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_USBFSRC /* SoC has SOPT2[USBFSRC] */ +# define KINETIS_SIM_HAS_SOPT2_TRACECLKSEL 1 /* SoC has SOPT2[TRACECLKSEL] */ +# define KINETIS_SIM_HAS_SOPT2_USBREGEN 1 /* SoC has SOPT2[USBREGEN] */ +# define KINETIS_SIM_HAS_SOPT2_USBSLSRC 1 /* SoC has SOPT2[USBSLSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_USBHSRC /* SoC has SOPT2[USBHSRC] */ +# define KINETIS_SIM_HAS_SOPT2_USBSRC 1 /* SoC has SOPT2[USBSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_MCGCLKSEL /* SoC has SOPT2[MCGCLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4 1 /* SoC has SOPT4 Register */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT0 1 /* SoC has SOPT4[FTM0FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT1 1 /* SoC has SOPT4[FTM0FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT2 1 /* SoC has SOPT4[FTM0FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT3 1 /* SoC has SOPT4[FTM0FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0TRG0SRC 1 /* SoC has SOPT4[FTM0TRG0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0TRG1SRC 1 /* SoC has SOPT4[FTM0TRG1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC 3 /* SoC has SOPT4[FTM1CH0SRC] 1, 3 if SOF */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT0 1 /* SoC has SOPT4[FTM1FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT1 1 /* SoC has SOPT4[FTM1FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT2 1 /* SoC has SOPT4[FTM1FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT3 1 /* SoC has SOPT4[FTM1FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2CH0SRC 1 /* SoC has SOPT4[FTM2CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2CH1SRC 1 /* SoC has SOPT4[FTM2CH1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT0 1 /* SoC has SOPT4[FTM2FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT1 1 /* SoC has SOPT4[FTM2FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT2 1 /* SoC has SOPT4[FTM2FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT3 1 /* SoC has SOPT4[FTM2FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC 1 /* SoC has SOPT4[FTM3CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT0 1 /* SoC has SOPT4[FTM3FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT1 1 /* SoC has SOPT4[FTM3FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT2 1 /* SoC has SOPT4[FTM3FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT3 1 /* SoC has SOPT4[FTM3FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC 1 /* SoC has SOPT4[FTM3TRG0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC 1 /* SoC has SOPT4[FTM3TRG1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_TPM0CLKSEL 1 /* SoC has SOPT4[TPM0CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4_TPM1CH0SRC 1 /* SoC has SOPT4[TPM1CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_TPM1CLKSEL 1 /* SoC has SOPT4[TPM1CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC 1 /* SoC has SOPT4[TPM2CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL 1 /* SoC has SOPT4[TPM2CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT5 1 /* SoC has SOPT5 Register */ +# define KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC 1 /* SoC has SOPT5[LPUART0RXSRC] */ +# define KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC 1 /* SoC has SOPT5[LPUART0TXSRC] */ +# undef KINETIS_SIM_HAS_SOPT6 /* SoC has SOPT6 Register */ +# undef KINETIS_SIM_HAS_SOPT6_MCC /* SoC has SOPT6[MCC] */ +# undef KINETIS_SIM_HAS_SOPT6_PCR /* SoC has SOPT6[PCR] */ +# undef KINETIS_SIM_HAS_SOPT6_RSTFLTSEL /* SoC has SOPT6[RSTFLTSEL] */ +# undef KINETIS_SIM_HAS_SOPT6_RSTFLTEN /* SoC has SOPT6[RSTFLTEN] */ +# define KINETIS_SIM_HAS_SOPT7 1 /* SoC has SOPT7 Register */ +# define KINETIS_SIM_HAS_SOPT7_ADC0ALTTRGSEL 1 /* SoC has SOPT7[ADC0ALTTRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1ALTTRGSEL 1 /* SoC has SOPT7[ADC1ALTTRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC0PRETRGSEL 1 /* SoC has SOPT7[ADC0PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1PRETRGSEL 1 /* SoC has SOPT7[ADC1PRETRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC2PRETRGSEL /* SoC has SOPT7[ADC2PRETRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC3PRETRGSEL /* SoC has SOPT7[ADC3PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL 15 /* SoC has 10 SOPT7[ADC0TRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL 15 /* SoC has 10 SOPT7[ADC1TRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL /* SoC has 10 SOPT7[ADC2TRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL /* SoC has 10 SOPT7[ADC3TRGSEL] */ +# define KINETIS_SIM_SOPT7_ADC0ALTTRGEN 1 /* ADC0 alternate trigger enable */ +# define KINETIS_SIM_SOPT7_ADC1ALTTRGEN 1 /* ADC1 alternate trigger enable */ +# undef KINETIS_SIM_SOPT7_ADC2ALTTRGEN /* ADC2 alternate trigger enable */ +# undef KINETIS_SIM_SOPT7_ADC3ALTTRGEN /* ADC3 alternate trigger enable */ +# define KINETIS_SIM_HAS_SOPT8 1 /* SoC has SOPT8 Register */ +# define KINETIS_SIM_HAS_SOPT8_FTM0SYNCBIT 1 /* SoC has SOPT8[FTM0SYNCBIT] */ +# define KINETIS_SIM_HAS_SOPT8_FTM1SYNCBIT 1 /* SoC has SOPT8[FTM1SYNCBIT] */ +# define KINETIS_SIM_HAS_SOPT8_FTM2SYNCBIT 1 /* SoC has SOPT8[FTM2SYNCBIT] */ +# define KINETIS_SIM_HAS_SOPT8_FTM3SYNCBIT 1 /* SoC has SOPT8[FTM3SYNCBIT] */ +# define KINETIS_SIM_HAS_SOPT8_FTM0OCH0SRC 1 /* SoC has SOPT8[FTM0OCH0SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM0OCH1SRC 1 /* SoC has SOPT8[FTM0OCH1SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM0OCH2SRC 1 /* SoC has SOPT8[FTM0OCH2SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM0OCH3SRC 1 /* SoC has SOPT8[FTM0OCH3SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM0OCH4SRC 1 /* SoC has SOPT8[FTM0OCH4SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM0OCH5SRC 1 /* SoC has SOPT8[FTM0OCH5SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM0OCH6SRC 1 /* SoC has SOPT8[FTM0OCH6SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM0OCH7SRC 1 /* SoC has SOPT8[FTM0OCH7SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM3OCH0SRC 1 /* SoC has SOPT8[FTM3OCH0SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM3OCH1SRC 1 /* SoC has SOPT8[FTM3OCH1SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM3OCH2SRC 1 /* SoC has SOPT8[FTM3OCH2SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM3OCH3SRC 1 /* SoC has SOPT8[FTM3OCH3SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM3OCH4SRC 1 /* SoC has SOPT8[FTM3OCH4SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM3OCH5SRC 1 /* SoC has SOPT8[FTM3OCH5SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM3OCH6SRC 1 /* SoC has SOPT8[FTM3OCH6SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM3OCH7SRC 1 /* SoC has SOPT8[FTM3OCH7SRC] */ +# define KINETIS_SIM_HAS_SOPT9 1 /* SoC has SOPT9 Register */ +# define KINETIS_SIM_HAS_SOPT9_TPM1CH0SRC 1 /* SoC has SOPT9[TPM1CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT9_TPM2CH0SRC 1 /* SoC has SOPT9[TPM2CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT9_TPM1CLKSEL 1 /* SoC has SOPT9[TPM1CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT9_TPM2CLKSEL 1 /* SoC has SOPT9[TPM2CLKSEL] */ +# define KINETIS_SIM_HAS_SDID 1 /* SoC has SDID Register */ +# define KINETIS_SIM_HAS_SDID_DIEID 1 /* SoC has SDID[DIEID] */ +# define KINETIS_SIM_HAS_SDID_FAMID 1 /* SoC has SDID[FAMID] */ +# define KINETIS_SIM_HAS_SDID_FAMILYID 1 /* SoC has SDID[FAMILYID] */ +# define KINETIS_SIM_HAS_SDID_SERIESID 1 /* SoC has SDID[SERIESID] */ +# undef KINETIS_SIM_HAS_SDID_SRAMSIZE /* SoC has SDID[SRAMSIZE] */ +# define KINETIS_SIM_HAS_SDID_SUBFAMID 1 /* SoC has SDID[SUBFAMID] */ +# define KINETIS_SIM_HAS_SCGC1 1 /* SoC has _SCGC1 Register */ +# undef KINETIS_SIM_HAS_SCGC1_UART5 /* SoC has SCGC1[UART5] */ +# define KINETIS_SIM_HAS_SCGC1_UART4 1 /* SoC has SCGC1[UART4] */ +# define KINETIS_SIM_HAS_SCGC1_I2C3 1 /* SoC has SCGC1[I2C3] */ +# define KINETIS_SIM_HAS_SCGC1_I2C2 1 /* SoC has SCGC1[I2C2] */ +# undef KINETIS_SIM_HAS_SCGC1_OSC1 /* SoC has SCGC1[OSC1] */ +# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has _SCGC2 Register */ +# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has SCGC2 Register */ +# define KINETIS_SIM_HAS_SCGC2_ENET 1 /* SoC has SCGC2[ENET] */ +# define KINETIS_SIM_HAS_SCGC2_LPUART0 1 /* SoC has SCGC2[LPUART0] */ +# define KINETIS_SIM_HAS_SCGC2_TPM1 1 /* SoC has SCGC2[TPM1] */ +# define KINETIS_SIM_HAS_SCGC2_TPM2 1 /* SoC has SCGC2[TPM2] */ +# define KINETIS_SIM_HAS_SCGC3 1 /* SoC has SCGC3 Register */ +# define KINETIS_SIM_HAS_SCGC3_RNGA 1 /* SoC has SCGC3[RNGA] */ +# define KINETIS_SIM_HAS_SCGC3_USBHS 1 /* SoC has SCGC3[USBHS] */ +# define KINETIS_SIM_HAS_SCGC3_USBHSPHY 1 /* SoC has SCGC3[USBHSPHY] */ +# define KINETIS_SIM_HAS_SCGC3_USBHSDCD 1 /* SoC has SCGC3[USBHSDCD] */ +# define KINETIS_SIM_HAS_SCGC3_FLEXCAN1 1 /* SoC has SCGC3[FLEXCAN1] */ +# undef KINETIS_SIM_HAS_SCGC3_NFC /* SoC has SCGC3[NFC] */ +# define KINETIS_SIM_HAS_SCGC3_SPI2 1 /* SoC has SCGC3[SPI2] */ +# undef KINETIS_SIM_HAS_SCGC3_SAI1 /* SoC has SCGC3[SAI1] */ +# define KINETIS_SIM_HAS_SCGC3_SDHC 1 /* SoC has SCGC3[SDHC] */ +# define KINETIS_SIM_HAS_SCGC3_FTM2 1 /* SoC has SCGC3[FTM2] */ +# define KINETIS_SIM_HAS_SCGC3_FTM3 1 /* SoC has SCGC3[FTM3] */ +# define KINETIS_SIM_HAS_SCGC3_ADC1 1 /* SoC has SCGC3[ADC1] */ +# undef KINETIS_SIM_HAS_SCGC3_ADC3 /* SoC has SCGC3[ADC3] */ +# undef KINETIS_SIM_HAS_SCGC3_SLCD /* SoC has SCGC3[SLCD] */ +# define KINETIS_SIM_HAS_SCGC4 1 /* SoC has SCGC4 Register */ +# undef KINETIS_SIM_HAS_SCGC4_LLWU /* SoC has SCGC4[LLWU] clock gate */ +# define KINETIS_SIM_HAS_SCGC4_UART0 1 /* SoC has SCGC4[UART0] */ +# define KINETIS_SIM_HAS_SCGC4_UART1 1 /* SoC has SCGC4[UART1] */ +# define KINETIS_SIM_HAS_SCGC4_UART2 1 /* SoC has SCGC4[UART2] */ +# define KINETIS_SIM_HAS_SCGC4_UART3 1 /* SoC has SCGC4[UART3] */ +# define KINETIS_SIM_HAS_SCGC5 1 /* SoC has _SCGC5 Register */ +# undef KINETIS_SIM_HAS_SCGC5_REGFILE /* SoC has SCGC5[REGFILE] */ +# define KINETIS_SIM_HAS_SCGC5_TSI 1 /* SoC has SCGC5[TSI] */ +# undef KINETIS_SIM_HAS_SCGC5_PORTF /* SoC has SCGC5[PORTF] */ +# define KINETIS_SIM_HAS_SCGC6 1 /* SoC has SCGC6 Register */ +# define KINETIS_SIM_HAS_SCGC6_FTFL 1 /* SoC has SCGC6[FTFL] */ +# undef KINETIS_SIM_HAS_SCGC6_DMAMUX1 /* SoC has SCGC6[DEMUX1] */ +# undef KINETIS_SIM_HAS_SCGC6_USBHS /* SoC has SCGC6[USBHS] */ +# define KINETIS_SIM_HAS_SCGC6_RNGA 1 /* SoC has SCGC6[RNGA] */ +# define KINETIS_SIM_HAS_SCGC6_FTM2 1 /* SoC has SCGC6[FTM2] */ +# undef KINETIS_SIM_HAS_SCGC6_ADC2 /* SoC has SCGC6[ADC2] */ +# define KINETIS_SIM_HAS_SCGC6_DAC0 1 /* SoC has SCGC6[DAC0] */ +# define KINETIS_SIM_HAS_SCGC7 1 /* SoC has SCGC7 Register */ +# define KINETIS_SIM_HAS_SCGC7_FLEXBUS 1 /* SoC has SCGC7[FLEXBUS] */ +# define KINETIS_SIM_HAS_SCGC7_DMA 1 /* SoC has SCGC7[DMS] */ +# define KINETIS_SIM_HAS_SCGC7_MPU 1 /* SoC has SCGC7[MPU] */ +# define KINETIS_SIM_HAS_SCGC7_SDRAMC 1 /* SoC has SCGC7[SDRAMC] */ +# define KINETIS_SIM_HAS_CLKDIV1 1 /* SoC has CLKDIV1 Register */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV2 1 /* SoC has CLKDIV1[OUTDIV2] */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV3 1 /* SoC has CLKDIV1[OUTDIV3] */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV4 1 /* SoC has CLKDIV1[OUTDIV4] */ +# undef KINETIS_SIM_HAS_CLKDIV1_OUTDIV5 /* SoC has CLKDIV1[OUTDIV5] */ +# define KINETIS_SIM_HAS_CLKDIV2 1 /* SoC has CLKDIV2 Register */ +# define KINETIS_SIM_HAS_CLKDIV2_USBDIV 1 /* SoC has CLKDIV2[USBDIV] */ +# define KINETIS_SIM_HAS_CLKDIV2_USBFRAC 1 /* SoC has CLKDIV2[USBFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBFSDIV /* SoC has CLKDIV2[USBFSDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBFSFRAC /* SoC has CLKDIV2[USBFSFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBHSDIV /* SoC has CLKDIV2[USBHSDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC /* SoC has CLKDIV2[USBHSFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_I2SDIV /* SoC has CLKDIV2[I2SDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_I2SFRAC /* SoC has CLKDIV2[I2SFRAC] */ +# define KINETIS_SIM_HAS_FCFG1 1 /* SoC has FCFG1 Register */ +# define KINETIS_SIM_HAS_FCFG1_DEPART 1 /* SoC has FCFG1[DEPART] */ +# define KINETIS_SIM_HAS_FCFG1_EESIZE 1 /* SoC has FCFG1[EESIZE] */ +# define KINETIS_SIM_HAS_FCFG1_FLASHDIS 1 /* SoC has FCFG1[FLASHDIS] */ +# define KINETIS_SIM_HAS_FCFG1_FLASHDOZE 1 /* SoC has FCFG1[FLASHDOZE] */ +# undef KINETIS_SIM_HAS_FCFG1_FTFDIS /* SoC has FCFG1[FTFDIS] */ +# define KINETIS_SIM_HAS_FCFG1_NVMSIZE 1 /* SoC has FCFG1[NVMSIZE] */ +# define KINETIS_SIM_HAS_FCFG2 1 /* SoC has FCFG2 Register */ +# define KINETIS_SIM_HAS_FCFG2_MAXADDR0 7 /* SoC has n bit of FCFG2[MAXADDR0] */ +# define KINETIS_SIM_HAS_FCFG2_MAXADDR1 7 /* SoC has n bit of FCFG2[MAXADDR1] */ +# define KINETIS_SIM_HAS_FCFG2_PFLSH 1 /* SoC has FCFG2[PFLSH] */ +# define KINETIS_SIM_HAS_FCFG2_SWAPPFLSH 1 /* SoC has FCFG2[SWAPPFLSH] */ +# define KINETIS_SIM_HAS_UIDH 1 /* SoC has UIDH Register */ +# define KINETIS_SIM_HAS_UIDMH 1 /* SoC has UIDMH Register */ +# define KINETIS_SIM_HAS_UIDML 1 /* SoC has UIDML Register */ +# define KINETIS_SIM_HAS_UIDL 1 /* SoC has UIDL Register */ +# define KINETIS_SIM_HAS_CLKDIV3 1 /* SoC has CLKDIV3 Register */ +# define KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV 1 /* SoC has CLKDIV3[PLLFLLDIV] */ +# define KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC 1 /* SoC has CLKDIV3[PLLFLLFRAC] */ +# define KINETIS_SIM_HAS_CLKDIV4 1 /* SoC has CLKDIV4 Register */ +# define KINETIS_SIM_HAS_CLKDIV4_TRACEDIV 1 /* SoC has CLKDIV4[TRACEDIV] */ +# define KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC 1 /* SoC has CLKDIV4[TRACEFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV4_NFCDIV /* SoC has CLKDIV4[NFCDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV4_NFCFRAC /* SoC has CLKDIV4[NFCFRAC] */ +# undef KINETIS_SIM_HAS_MCR /* SoC has MCR Register */ +#else +# error "Unsupported Kinetis chip" +#endif + +/* Use the catch all configuration for the SIM based on the implementations in nuttx prior 2/16/2017 */ + +#if KINETIS_SIM_VERSION == KINETIS_SIM_VERSION_UKN + +/* SIM Register Configuration */ + +# define KINETIS_SIM_HAS_SOPT1 1 /* SoC has SOPT1 Register */ +# undef KINETIS_SIM_HAS_SOPT1_OSC32KOUT /* SoC has SOPT1[OSC32KOUT] */ +# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL 1 /* SoC has SOPT1[OSC32KSEL] */ +# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS 1 /* SoC has 1 bit SOPT1[OSC32KSEL] */ +# define KINETIS_SIM_HAS_SOPT1_RAMSIZE 1 /* SoC has SOPT1[RAMSIZE] */ +# define KINETIS_SIM_HAS_SOPT1_USBREGEN 1 /* SoC has SOPT1[USBREGEN] */ +# define KINETIS_SIM_HAS_SOPT1_USBSSTBY 1 /* SoC has SOPT1[USBSSTBY] */ +# undef KINETIS_SIM_HAS_SOPT1_USBVSTBY /* SoC has SOPT1[USBVSTBY] */ +# undef KINETIS_SIM_HAS_SOPT1CFG /* SoC has SOPT1CFG Register */ +# undef KINETIS_SIM_HAS_SOPT1CFG_URWE /* SoC has SOPT1CFG[URWE] */ +# undef KINETIS_SIM_HAS_SOPT1CFG_USSWE /* SoC has SOPT1CFG[USSWE] */ +# undef KINETIS_SIM_HAS_SOPT1CFG_UVSWE /* SoC has SOPT1CFG[UVSWE] */ +# undef KINETIS_SIM_HAS_USBPHYCTL /* SoC has USBPHYCTL Register */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USB3VOUTTRG /* SoC has USBPHYCTL[USB3VOUTTRG] */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM /* SoC has USBPHYCTL[USBDISILIM] */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USBVREGPD /* SoC has USBPHYCTL[USBVREGPD] */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL /* SoC has USBPHYCTL[USBVREGSEL] */ +# define KINETIS_SIM_HAS_SOPT2 1 /* SoC has SOPT2 Register */ +# define KINETIS_SIM_HAS_SOPT2_CMTUARTPAD 1 /* SoC has SOPT2[CMTUARTPAD] */ +# define KINETIS_SIM_HAS_SOPT2_FBSL 1 /* SoC has SOPT2[FBSL] */ +# undef KINETIS_SIM_HAS_SOPT2_FLEXIOSRC /* SoC has SOPT2[FLEXIOSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_LPUARTSRC /* SoC has SOPT2[LPUARTSRC] */ +# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL 1 /* SoC has SOPT2[PLLFLLSEL] */ +# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS 1 /* SoC has 1 bit of SOPT2[PLLFLLSEL] */ +# undef KINETIS_SIM_HAS_SOPT2_PTD7PAD /* SoC has SOPT2[PTD7PAD] */ +# undef KINETIS_SIM_HAS_SOPT2_RMIISRC /* SoC has SOPT2[RMIISRC] */ +# undef KINETIS_SIM_HAS_SOPT2_RTCCLKOUTSEL /* SoC has SOPT2[RTCCLKOUTSEL] */ +# undef KINETIS_SIM_HAS_SOPT2_CLKOUTSEL /* SoC has SOPT2[CLKOUTSEL] */ +# define KINETIS_SIM_HAS_SOPT2_SDHCSRC 1 /* SoC has SOPT2[SDHCSRC] */ +# define KINETIS_SIM_HAS_SOPT2_TIMESRC 1 /* SoC has SOPT2[TIMESRC] */ +# undef KINETIS_SIM_HAS_SOPT2_TPMSRC /* SoC has SOPT2[TPMSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_USBFSRC /* SoC has SOPT2[USBFSRC] */ +# define KINETIS_SIM_HAS_SOPT2_I2SSRC 1 /* SoC has SOPT2[I2SSRC] */ +# define KINETIS_SIM_HAS_SOPT2_TRACECLKSEL 1 /* SoC has SOPT2[TRACECLKSEL] */ +# undef KINETIS_SIM_HAS_SOPT2_USBREGEN /* SoC has SOPT2[USBREGEN] */ +# undef KINETIS_SIM_HAS_SOPT2_USBSLSRC /* SoC has SOPT2[USBSLSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_USBHSRC /* SoC has SOPT2[USBHSRC] */ +# define KINETIS_SIM_HAS_SOPT2_USBSRC 1 /* SoC has SOPT2[USBSRC] */ +# define KINETIS_SIM_HAS_SOPT2_MCGCLKSEL 1 /* SoC has SOPT2[MCGCLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4 1 /* SoC has SOPT4 Register */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT0 1 /* SoC has SOPT4[FTM0FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT1 1 /* SoC has SOPT4[FTM0FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT2 1 /* SoC has SOPT4[FTM0FLT2] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM0FLT3 /* SoC has SOPT4[FTM0FLT3] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM0TRG0SRC /* SoC has SOPT4[FTM0TRG0SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM0TRG1SRC /* SoC has SOPT4[FTM0TRG1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC 1 /* SoC has SOPT4[FTM1CH0SRC] No OF */ +# undef KINETIS_SIM_HAS_SOPT4_FTM1FLT0 /* SoC has SOPT4[FTM1FLT0] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM1FLT1 /* SoC has SOPT4[FTM1FLT1] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM1FLT2 /* SoC has SOPT4[FTM1FLT2] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM1FLT3 /* SoC has SOPT4[FTM1FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2CH0SRC 1 /* SoC has SOPT4[FTM2CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM2CH1SRC /* SoC has SOPT4[FTM2CH1SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM2FLT0 /* SoC has SOPT4[FTM2FLT0] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM2FLT1 /* SoC has SOPT4[FTM2FLT1] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM2FLT2 /* SoC has SOPT4[FTM2FLT2] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM2FLT3 /* SoC has SOPT4[FTM2FLT3] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC /* SoC has SOPT4[FTM3CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM3FLT0 /* SoC has SOPT4[FTM3FLT0] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM3FLT1 /* SoC has SOPT4[FTM3FLT1] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM3FLT2 /* SoC has SOPT4[FTM3FLT2] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM3FLT3 /* SoC has SOPT4[FTM3FLT3] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC /* SoC has SOPT4[FTM3TRG0SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC /* SoC has SOPT4[FTM3TRG1SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_TPM0CLKSEL /* SoC has SOPT4[TPM0CLKSEL] */ +# undef KINETIS_SIM_HAS_SOPT4_TPM1CH0SRC /* SoC has SOPT4[TPM1CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_TPM1CLKSEL /* SoC has SOPT4[TPM1CLKSEL] */ +# undef KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC /* SoC has SOPT4[TPM2CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL /* SoC has SOPT4[TPM2CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT5 /* SoC has SOPT5 Register */ +# undef KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC /* SoC has SOPT5[LPUART0RXSRC] */ +# undef KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC /* SoC has SOPT5[LPUART0TXSRC] */ +# define KINETIS_SIM_HAS_SOPT6 1 /* SoC has SOPT6 Register */ +# undef KINETIS_SIM_HAS_SOPT6_MCC /* SoC has SOPT6[MCC] */ +# undef KINETIS_SIM_HAS_SOPT6_PCR /* SoC has SOPT6[PCR] */ +# define KINETIS_SIM_HAS_SOPT6_RSTFLTSEL 1 /* SoC has SOPT6[RSTFLTSEL] */ +# define KINETIS_SIM_HAS_SOPT6_RSTFLTEN 1 /* SoC has SOPT6[RSTFLTEN] */ +# define KINETIS_SIM_HAS_SOPT7 1 /* SoC has SOPT7 Register */ +# define KINETIS_SIM_HAS_SOPT7_ADC0ALTTRGSEL 1 /* SoC has SOPT7[ADC0ALTTRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1ALTTRGSEL 1 /* SoC has SOPT7[ADC1ALTTRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC0PRETRGSEL 1 /* SoC has SOPT7[ADC0PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1PRETRGSEL 1 /* SoC has SOPT7[ADC1PRETRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC2PRETRGSEL /* SoC has SOPT7[ADC2PRETRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC3PRETRGSEL /* SoC has SOPT7[ADC3PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL 14 /* SoC has 10 SOPT7[ADC0TRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL 14 /* SoC has 10 SOPT7[ADC1TRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL /* SoC has 10 SOPT7[ADC2TRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL /* SoC has 10 SOPT7[ADC3TRGSEL] */ +# define KINETIS_SIM_SOPT7_ADC0ALTTRGEN 1 /* ADC0 alternate trigger enable */ +# define KINETIS_SIM_SOPT7_ADC1ALTTRGEN 1 /* ADC1 alternate trigger enable */ +# undef KINETIS_SIM_SOPT7_ADC2ALTTRGEN /* ADC2 alternate trigger enable */ +# undef KINETIS_SIM_SOPT7_ADC3ALTTRGEN /* ADC3 alternate trigger enable */ +# undef KINETIS_SIM_HAS_SOPT8 /* SoC has SOPT8 Register */ +# undef KINETIS_SIM_HAS_SOPT9 /* SoC has SOPT9 Register */ +# define KINETIS_SIM_HAS_SDID 1 /* SoC has SDID Register */ +# undef KINETIS_SIM_HAS_SDID_DIEID /* SoC has SDID[DIEID] */ +# define KINETIS_SIM_HAS_SDID_FAMID 1 /* SoC has SDID[FAMID] */ +# undef KINETIS_SIM_HAS_SDID_FAMILYID /* SoC has SDID[FAMILYID] */ +# undef KINETIS_SIM_HAS_SDID_SERIESID /* SoC has SDID[SERIESID] */ +# undef KINETIS_SIM_HAS_SDID_SRAMSIZE /* SoC has SDID[SRAMSIZE] */ +# undef KINETIS_SIM_HAS_SDID_SUBFAMID /* SoC has SDID[SUBFAMID] */ +# define KINETIS_SIM_HAS_SCGC1 1 /* SoC has SCGC1 Register */ +# define KINETIS_SIM_HAS_SCGC1_UART5 1 /* SoC has SCGC1[UART5] */ +# define KINETIS_SIM_HAS_SCGC1_UART4 1 /* SoC has SCGC1[UART4] */ +# undef KINETIS_SIM_HAS_SCGC1_I2C3 /* SoC has SCGC1[I2C3] */ +# undef KINETIS_SIM_HAS_SCGC1_I2C2 /* SoC has SCGC1[I2C2] */ +# undef KINETIS_SIM_HAS_SCGC1_OSC1 /* SoC has SCGC1[OSC1] */ +# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has SCGC2 Register */ +# define KINETIS_SIM_HAS_SCGC2_ENET 1 /* SoC has SCGC2[ENET] */ +# undef KINETIS_SIM_HAS_SCGC2_LPUART0 /* SoC has SCGC2[LPUART0] */ +# undef KINETIS_SIM_HAS_SCGC2_TPM1 /* SoC has SCGC2[TPM1] */ +# undef KINETIS_SIM_HAS_SCGC2_TPM2 /* SoC has SCGC2[TPM2] */ +# define KINETIS_SIM_HAS_SCGC3 1 /* SoC has SCGC3 Register */ +# define KINETIS_SIM_HAS_SCGC3_RNGA 1 /* SoC has SCGC3[RNGA] */ +# undef KINETIS_SIM_HAS_SCGC3_USBHS /* SoC has SCGC3[USBHS] */ +# undef KINETIS_SIM_HAS_SCGC3_USBHSPHY /* SoC has SCGC3[USBHSPHY] */ +# undef KINETIS_SIM_HAS_SCGC3_USBHSDCD /* SoC has SCGC3[USBHSDCD] */ +# define KINETIS_SIM_HAS_SCGC3_FLEXCAN1 1 /* SoC has SCGC3[FLEXCAN1] */ +# undef KINETIS_SIM_HAS_SCGC3_NFC /* SoC has SCGC3[NFC] */ +# define KINETIS_SIM_HAS_SCGC3_SPI2 1 /* SoC has SCGC3[SPI2] */ +# undef KINETIS_SIM_HAS_SCGC3_SAI1 /* SoC has SCGC3[SAI1] */ +# define KINETIS_SIM_HAS_SCGC3_SDHC 1 /* SoC has SCGC3[SDHC] */ +# define KINETIS_SIM_HAS_SCGC3_FTM2 1 /* SoC has SCGC3[FTM2] */ +# define KINETIS_SIM_HAS_SCGC3_FTM3 1 /* SoC has SCGC3[FTM3] */ +# define KINETIS_SIM_HAS_SCGC3_ADC1 1 /* SoC has SCGC3[ADC1] */ +# undef KINETIS_SIM_HAS_SCGC3_ADC3 /* SoC has SCGC3[ADC3] */ +# define KINETIS_SIM_HAS_SCGC3_SLCD 1 /* SoC has SCGC3[SLCD] */ +# define KINETIS_SIM_HAS_SCGC4 1 /* SoC has SCGC4 Register */ +# define KINETIS_SIM_HAS_SCGC4_LLWU 1 /* SoC has SCGC4[LLWU] clock gate */ +# define KINETIS_SIM_HAS_SCGC4_UART0 1 /* SoC has SCGC4[UART0] */ +# define KINETIS_SIM_HAS_SCGC4_UART1 1 /* SoC has SCGC4[UART1] */ +# define KINETIS_SIM_HAS_SCGC4_UART2 1 /* SoC has SCGC4[UART2] */ +# define KINETIS_SIM_HAS_SCGC4_UART3 1 /* SoC has SCGC4[UART3] */ +# define KINETIS_SIM_HAS_SCGC5 1 /* SoC has SCGC5 Register */ +# define KINETIS_SIM_HAS_SCGC5_REGFILE 1 /* SoC has SCGC5[REGFILE] */ +# define KINETIS_SIM_HAS_SCGC5_TSI 1 /* SoC has SCGC5[TSI] */ +# undef KINETIS_SIM_HAS_SCGC5_PORTF /* SoC has SCGC5[PORTF] */ +# define KINETIS_SIM_HAS_SCGC6 1 /* SoC has SCGC6 Register */ +# define KINETIS_SIM_HAS_SCGC6_FTFL 1 /* SoC has SCGC6[FTFL] */ +# undef KINETIS_SIM_HAS_SCGC6_DMAMUX1 /* SoC has SCGC6[DEMUX1] */ +# undef KINETIS_SIM_HAS_SCGC6_USBHS /* SoC has SCGC6[USBHS] */ +# undef KINETIS_SIM_HAS_SCGC6_RNGA /* SoC has SCGC6[RNGA] */ +# undef KINETIS_SIM_HAS_SCGC6_FTM2 /* SoC has SCGC6[FTM2] */ +# undef KINETIS_SIM_HAS_SCGC6_ADC2 /* SoC has SCGC6[ADC2] */ +# undef KINETIS_SIM_HAS_SCGC6_DAC0 /* SoC has SCGC6[DAC0] */ +# define KINETIS_SIM_HAS_SCGC7 1 /* SoC has SCGC7 Register */ +# define KINETIS_SIM_HAS_SCGC7_FLEXBUS 1 /* SoC has SCGC7[FLEXBUS] */ +# define KINETIS_SIM_HAS_SCGC7_DMA 1 /* SoC has SCGC7[DMS] */ +# define KINETIS_SIM_HAS_SCGC7_MPU 1 /* SoC has SCGC7[MPU] */ +# undef KINETIS_SIM_HAS_SCGC7_SDRAMC /* SoC has SCGC7[SDRAMC] */ +# define KINETIS_SIM_HAS_CLKDIV1 1 /* SoC has CLKDIV1 Register */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV2 1 /* SoC has CLKDIV1[OUTDIV2] */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV3 1 /* SoC has CLKDIV1[OUTDIV3] */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV4 1 /* SoC has CLKDIV1[OUTDIV4] */ +# undef KINETIS_SIM_HAS_CLKDIV1_OUTDIV5 /* SoC has CLKDIV1[OUTDIV5] */ +# define KINETIS_SIM_HAS_CLKDIV2 1 /* SoC has CLKDIV2 Register */ +# define KINETIS_SIM_HAS_CLKDIV2_USBDIV 1 /* SoC has CLKDIV2[USBDIV] */ +# define KINETIS_SIM_HAS_CLKDIV2_USBFRAC 1 /* SoC has CLKDIV2[USBFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBFSDIV /* SoC has CLKDIV2[USBFSDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBFSFRAC /* SoC has CLKDIV2[USBFSFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBHSDIV /* SoC has CLKDIV2[USBHSDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC /* SoC has CLKDIV2[USBHSFRAC] */ +# define KINETIS_SIM_HAS_CLKDIV2_I2SDIV 1 /* SoC has CLKDIV2[I2SDIV] */ +# define KINETIS_SIM_HAS_CLKDIV2_I2SFRAC 1 /* SoC has CLKDIV2[I2SFRAC] */ +# define KINETIS_SIM_HAS_FCFG1 1 /* SoC has FCFG1 Register */ +# define KINETIS_SIM_HAS_FCFG1_DEPART 1 /* SoC has FCFG1[DEPART] */ +# define KINETIS_SIM_HAS_FCFG1_EESIZE 1 /* SoC has FCFG1[EESIZE] */ +# undef KINETIS_SIM_HAS_FCFG1_FLASHDIS /* SoC has FCFG1[FLASHDIS] */ +# undef KINETIS_SIM_HAS_FCFG1_FLASHDOZE /* SoC has FCFG1[FLASHDOZE] */ +# undef KINETIS_SIM_HAS_FCFG1_FTFDIS /* SoC has FCFG1[FTFDIS] */ +# define KINETIS_SIM_HAS_FCFG1_NVMSIZE 1 /* SoC has FCFG1[NVMSIZE] */ +# define KINETIS_SIM_HAS_FCFG2 1 /* SoC has FCFG2 Register */ +# define KINETIS_SIM_HAS_FCFG2_MAXADDR0 6 /* SoC has n bit of FCFG2[MAXADDR0] */ +# define KINETIS_SIM_HAS_FCFG2_MAXADDR1 6 /* SoC has n bit of FCFG2[MAXADDR1] */ +# define KINETIS_SIM_HAS_FCFG2_PFLSH 1 /* SoC has FCFG2[PFLSH] */ +# define KINETIS_SIM_HAS_FCFG2_SWAPPFLSH 1 /* SoC has FCFG2[SWAPPFLSH] */ +# define KINETIS_SIM_HAS_UIDH 1 /* SoC has UIDH Register */ +# define KINETIS_SIM_HAS_UIDMH 1 /* SoC has UIDMH Register */ +# define KINETIS_SIM_HAS_UIDML 1 /* SoC has UIDML Register */ +# define KINETIS_SIM_HAS_UIDL 1 /* SoC has UIDL Register */ +# undef KINETIS_SIM_HAS_CLKDIV3 /* SoC has CLKDIV3 Register */ +# undef KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV /* SoC has CLKDIV3[PLLFLLDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC /* SoC has CLKDIV3[PLLFLLFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV4 /* SoC has CLKDIV4 Register */ +# undef KINETIS_SIM_HAS_CLKDIV4_TRACEDIV /* SoC has CLKDIV4[TRACEDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC /* SoC has CLKDIV4[TRACEFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV4_NFCDIV /* SoC has CLKDIV4[NFCDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV4_NFCFRAC /* SoC has CLKDIV4[NFCFRAC] */ +# undef KINETIS_SIM_HAS_MCR /* SoC has MCR Register */ +#endif + +#if !defined(KINETIS_SIM_VERSION) +# error "No KINETIS_SIM_VERSION defined!" +#endif + +#if defined(KINETIS_SIM_HAS_SOPT1_OSC32KSEL) +# define KINETIS_SIM_SOPT1_OSC32KSEL_MASK ((1 << (KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS))-1) +#endif + +#if defined(KINETIS_SIM_HAS_SOPT2_PLLFLLSEL) +# define KINETIS_SIM_SOPT2_PLLFLLSEL_MASK ((1 << (KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS))-1) +#endif + +#if defined(KINETIS_SIM_HAS_FCFG2_MAXADDR0) +# define KINETIS_SIM_FCFG2_MAXADDR0_MASK ((1 << (KINETIS_SIM_HAS_FCFG2_MAXADDR0))-1) +#endif + +#if defined(KINETIS_SIM_HAS_FCFG2_MAXADDR1) +# define KINETIS_SIM_FCFG2_MAXADDR1_MASK ((1 << (KINETIS_SIM_HAS_FCFG2_MAXADDR1))-1) +#endif + +#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_SIM_H */ diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h index 137383bb093..0844c5a09fb 100644 --- a/arch/arm/include/stm32/chip.h +++ b/arch/arm/include/stm32/chip.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/include/stm32/chip.h * - * Copyright (C) 2009, 2011-2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2011-2014, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -86,6 +86,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ @@ -126,6 +127,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ @@ -166,6 +168,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ @@ -206,6 +209,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ @@ -246,6 +250,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ @@ -286,6 +291,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ @@ -404,6 +410,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ @@ -442,6 +449,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* FSMC */ @@ -483,6 +491,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* FSMC */ @@ -522,6 +531,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 1 /* FSMC */ @@ -600,6 +610,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* FSMC */ @@ -638,6 +649,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ @@ -676,6 +688,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ @@ -714,6 +727,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ @@ -757,6 +771,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ @@ -798,6 +813,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 1 /* FSMC */ @@ -839,6 +855,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 1 /* FSMC */ @@ -878,6 +895,7 @@ # define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ @@ -915,6 +933,7 @@ # define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ @@ -952,6 +971,7 @@ # define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ @@ -991,6 +1011,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # define CONFIG_STM32_STM32F20XX 1 /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ @@ -1029,6 +1050,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # define CONFIG_STM32_STM32F20XX 1 /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ @@ -1067,6 +1089,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # define CONFIG_STM32_STM32F20XX 1 /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ @@ -1097,7 +1120,7 @@ /* Part Numbering: STM32Fssscfxxx * * Where - * sss = 302/303 or 372/373 + * sss = 302/303, 334 or 372/373 * c = C (48pins) R (68 pins) V (100 pins) * c = K (32 pins), C (48 pins), R (68 pins), V (100 pins) * f = 6 (32KB FLASH), 8 (64KB FLASH), B (128KB FLASH), C (256KB FLASH) @@ -1154,6 +1177,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ @@ -1194,6 +1218,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ @@ -1234,6 +1259,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ @@ -1274,6 +1300,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ @@ -1314,6 +1341,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ @@ -1354,6 +1382,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ @@ -1394,6 +1423,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ @@ -1434,6 +1464,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ @@ -1474,6 +1505,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ @@ -1502,6 +1534,138 @@ # define STM32_NRNG 0 /* (0) No random number generator (RNG) */ # define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ +#elif defined(CONFIG_ARCH_CHIP_STM32F334K4) || defined(CONFIG_ARCH_CHIP_STM32F334K6) || defined(CONFIG_ARCH_CHIP_STM32F334K8) +# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */ +# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */ +# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */ +# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */ +# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ +# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */ +# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ +# undef CONFIG_STM32_VALUELINE /* STM32F100x */ +# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ +# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# define CONFIG_STM32_STM32F33XX 1 /* STM32F33xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ +# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ +# define STM32_NFSMC 0 /* No FSMC */ + +# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ +# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 1 /* (2) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (3) SPI1 */ +# define STM32_NI2S 0 /* (0) I2S1 */ +# define STM32_NUSART 2 /* (2) USART1-2 */ +# define STM32_NI2C 1 /* (2) I2C1 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* (0) No USB */ +# define STM32_NGPIO 25 /* GPIOA-F */ +# define STM32_NADC 2 /* (3) 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */ +# define STM32_NCMP 2 /* (2) Ultra-fast analog comparators: COMP2 and COMP4 */ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 14 /* (14) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F334C4) || defined(CONFIG_ARCH_CHIP_STM32F334C6) || defined(CONFIG_ARCH_CHIP_STM32F334C8) +# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */ +# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */ +# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */ +# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */ +# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ +# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */ +# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ +# undef CONFIG_STM32_VALUELINE /* STM32F100x */ +# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ +# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# define CONFIG_STM32_STM32F33XX 1 /* STM32F33xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ +# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ +# define STM32_NFSMC 0 /* No FSMC */ + +# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ +# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 1 /* (2) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (3) SPI1 */ +# define STM32_NI2S 0 /* (0) I2S1 */ +# define STM32_NUSART 3 /* (2) USART1-3 */ +# define STM32_NI2C 1 /* (2) I2C1 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* (0) No USB */ +# define STM32_NGPIO 37 /* GPIOA-F */ +# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */ +# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 17 /* (17) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F334R4) || defined(CONFIG_ARCH_CHIP_STM32F334R6) || defined(CONFIG_ARCH_CHIP_STM32F334R8) +# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */ +# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */ +# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */ +# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */ +# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ +# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */ +# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ +# undef CONFIG_STM32_VALUELINE /* STM32F100x */ +# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ +# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# define CONFIG_STM32_STM32F33XX 1 /* STM32F33xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ +# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ +# define STM32_NFSMC 0 /* No FSMC */ + +# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ +# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 1 /* (2) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (3) SPI1 */ +# define STM32_NI2S 0 /* (0) I2S1 */ +# define STM32_NUSART 3 /* (2) USART1-3 */ +# define STM32_NI2C 1 /* (2) I2C1 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* (0) No USB */ +# define STM32_NGPIO 51 /* GPIOA-F */ +# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */ +# define STM32_NDAC 2 /* (3) 12-bit DAC1-2 */ +# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 18 /* (18) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + #elif defined(CONFIG_ARCH_CHIP_STM32F373C8) || defined(CONFIG_ARCH_CHIP_STM32F373CB) || defined(CONFIG_ARCH_CHIP_STM32F373CC) # undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */ # undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */ @@ -1513,6 +1677,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # define CONFIG_STM32_STM32F37XX 1 /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ @@ -1558,6 +1723,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ @@ -1596,6 +1762,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ @@ -1634,6 +1801,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ @@ -1672,6 +1840,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ @@ -1710,6 +1879,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ @@ -1748,6 +1918,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ @@ -1786,6 +1957,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ @@ -1824,6 +1996,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ @@ -1862,6 +2035,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ @@ -1900,6 +2074,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ @@ -1938,6 +2113,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ @@ -1976,6 +2152,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ @@ -2014,6 +2191,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */ # define STM32_NFSMC 1 /* FSMC */ @@ -2052,6 +2230,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */ # define STM32_NFSMC 1 /* FSMC */ @@ -2090,6 +2269,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */ # define STM32_NFSMC 1 /* FSMC */ @@ -2128,6 +2308,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */ # define STM32_NFSMC 1 /* FSMC */ @@ -2166,6 +2347,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437/429/439 */ # define STM32_NFSMC 1 /* FSMC */ @@ -2204,6 +2386,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */ # define STM32_NFSMC 1 /* FSMC */ @@ -2242,6 +2425,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */ # define STM32_NFSMC 0 /* FSMC */ @@ -2280,6 +2464,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */ # define STM32_NFSMC 0 /* FSMC */ @@ -2318,6 +2503,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */ # define STM32_NFSMC 1 /* FSMC */ @@ -2356,6 +2542,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */ # define STM32_NFSMC 1 /* FSMC */ @@ -2394,6 +2581,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */ # define STM32_NFSMC 1 /* FSMC */ @@ -2435,6 +2623,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */ # undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */ # define STM32_NFSMC 1 /* FSMC */ diff --git a/arch/arm/include/stm32/dma2d.h b/arch/arm/include/stm32/dma2d.h index 349944148f9..be807de31dc 100644 --- a/arch/arm/include/stm32/dma2d.h +++ b/arch/arm/include/stm32/dma2d.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/include/stm32/dma2d.h + * arch/arm/include/stm32/dma2d.h * * Copyright (C) 2015 Marco Krahl. All rights reserved. * Author: Marco Krahl @@ -345,7 +345,7 @@ struct dma2d_layer_s * ****************************************************************************/ -FAR struct dma2d_layer_s * up_dma2dgetlayer(int lid); +FAR struct dma2d_layer_s *up_dma2dgetlayer(int lid); /**************************************************************************** * Name: up_dma2dcreatelayer diff --git a/arch/arm/include/stm32/irq.h b/arch/arm/include/stm32/irq.h index 2c9b188f025..ed369355a14 100644 --- a/arch/arm/include/stm32/irq.h +++ b/arch/arm/include/stm32/irq.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/include/stm32s/irq.h + * arch/arm/include/stm32/irq.h * - * Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2012, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -85,6 +85,8 @@ # include #elif defined(CONFIG_STM32_STM32F30XX) # include +#elif defined(CONFIG_STM32_STM32F33XX) +# include #elif defined(CONFIG_STM32_STM32F37XX) # include #elif defined(CONFIG_STM32_STM32F40XX) diff --git a/arch/arm/include/stm32/ltdc.h b/arch/arm/include/stm32/ltdc.h index 70f978058aa..704b578a996 100644 --- a/arch/arm/include/stm32/ltdc.h +++ b/arch/arm/include/stm32/ltdc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/include/stm32/ltdc.h + * arch/arm/include/stm32/ltdc.h * * Copyright (C) 2014-2015 Marco Krahl. All rights reserved. * Author: Marco Krahl diff --git a/arch/arm/include/stm32/stm32f10xxx_irq.h b/arch/arm/include/stm32/stm32f10xxx_irq.h index beed4952541..e56df1338e9 100644 --- a/arch/arm/include/stm32/stm32f10xxx_irq.h +++ b/arch/arm/include/stm32/stm32f10xxx_irq.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/include/stm32s/stm32f10xxx_irq.h + * arch/arm/include/stm32/stm32f10xxx_irq.h * * Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/include/stm32/stm32f20xxx_irq.h b/arch/arm/include/stm32/stm32f20xxx_irq.h index 43a2e218eb9..1c5bc9480e1 100644 --- a/arch/arm/include/stm32/stm32f20xxx_irq.h +++ b/arch/arm/include/stm32/stm32f20xxx_irq.h @@ -1,5 +1,5 @@ /**************************************************************************************************** - * arch/arm/include/stm32s/stm32f20xxx_irq.h + * arch/arm/include/stm32/stm32f20xxx_irq.h * * Copyright (C) 2012 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/include/stm32/stm32f30xxx_irq.h b/arch/arm/include/stm32/stm32f30xxx_irq.h index 74c8a279a65..f109c8b85d7 100644 --- a/arch/arm/include/stm32/stm32f30xxx_irq.h +++ b/arch/arm/include/stm32/stm32f30xxx_irq.h @@ -1,5 +1,5 @@ /**************************************************************************************************** - * arch/arm/include/stm32s/stm32f30xxx_irq.h + * arch/arm/include/stm32/stm32f30xxx_irq.h * * Copyright (C) 2012 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/include/stm32/stm32f33xxx_irq.h b/arch/arm/include/stm32/stm32f33xxx_irq.h new file mode 100644 index 00000000000..7170959ec93 --- /dev/null +++ b/arch/arm/include/stm32/stm32f33xxx_irq.h @@ -0,0 +1,185 @@ +/**************************************************************************************************** + * arch/arm/include/stm32/stm32f33xxx_irq.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Modified for STM32F334 by Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */ + +#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F33XXX_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32_STM32F33XXX_IRQ_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in the IRQ + * to handle mapping tables. + * + * Processor Exceptions (vectors 0-15). These common definitions can be found + * in nuttx/arch/arm/include/stm32/irq.h + * + * External interrupts (vectors >= 16) + */ + +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper interrupt, or */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Time stamp interrupt */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt, or */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST+8) /* 8: TSC interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST+11) /* 11: DMA1 channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST+12) /* 12: DMA1 channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST+13) /* 13: DMA1 channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST+14) /* 14: DMA1 channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST+15) /* 15: DMA1 channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST+16) /* 16: DMA1 channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST+17) /* 17: DMA1 channel 7 global interrupt */ +#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST+18) /* 18: ADC1/ADC2 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts*/ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt, or */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST+24) /* 24: TIM15 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt, or */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST+25) /* 25: TIM16 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts, or */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST+26) /* 26: TIM17 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_RESERVED30 (STM32_IRQ_FIRST+30) /* 30: Reserved */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_RESERVED33 (STM32_IRQ_FIRST+33) /* 33: Reserved */ +#define STM32_IRQ_RESERVED34 (STM32_IRQ_FIRST+34) /* 34: Reserved */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_RESERVED36 (STM32_IRQ_FIRST+36) /* 36: Reserved */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_RESERVED42 (STM32_IRQ_FIRST+42) /* 42: Reserved */ +#define STM32_IRQ_RESERVED43 (STM32_IRQ_FIRST+43) /* 43: Reserved */ +#define STM32_IRQ_RESERVED44 (STM32_IRQ_FIRST+44) /* 44: Reserved */ +#define STM32_IRQ_RESERVED45 (STM32_IRQ_FIRST+45) /* 45: Reserved */ +#define STM32_IRQ_RESERVED46 (STM32_IRQ_FIRST+46) /* 46: Reserved */ +#define STM32_IRQ_RESERVED47 (STM32_IRQ_FIRST+47) /* 47: Reserved */ +#define STM32_IRQ_RESERVED48 (STM32_IRQ_FIRST+48) /* 48: Reserved */ +#define STM32_IRQ_RESERVED49 (STM32_IRQ_FIRST+49) /* 49: Reserved */ +#define STM32_IRQ_RESERVED50 (STM32_IRQ_FIRST+50) /* 50: Reserved */ +#define STM32_IRQ_RESERVED51 (STM32_IRQ_FIRST+51) /* 51: Reserved */ +#define STM32_IRQ_RESERVED52 (STM32_IRQ_FIRST+52) /* 52: Reserved */ +#define STM32_IRQ_RESERVED53 (STM32_IRQ_FIRST+53) /* 53: Reserved */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt, or */ +#define STM32_IRQ_DAC1 (STM32_IRQ_FIRST+54) /* 54: DAC1 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt, or */ +#define STM32_IRQ_DAC2 (STM32_IRQ_FIRST+54) /* 55: DAC2 underrun error interrupts */ +#define STM32_IRQ_RESERVED56 (STM32_IRQ_FIRST+56) /* 56: Reserved */ +#define STM32_IRQ_RESERVED57 (STM32_IRQ_FIRST+57) /* 57: Reserved */ +#define STM32_IRQ_RESERVED58 (STM32_IRQ_FIRST+58) /* 58: Reserved */ +#define STM32_IRQ_RESERVED59 (STM32_IRQ_FIRST+59) /* 59: Reserved */ +#define STM32_IRQ_RESERVED60 (STM32_IRQ_FIRST+60) /* 60: Reserved */ +#define STM32_IRQ_RESERVED61 (STM32_IRQ_FIRST+61) /* 61: Reserved */ +#define STM32_IRQ_RESERVED62 (STM32_IRQ_FIRST+62) /* 62: Reserved */ +#define STM32_IRQ_RESERVED63 (STM32_IRQ_FIRST+63) /* 63: Reserved */ +#define STM32_IRQ_COMP2 (STM32_IRQ_FIRST+64) /* 64: COMP2 interrupts, or */ +#define STM32_IRQ_EXTI2129 (STM32_IRQ_FIRST+64) /* 64: EXTI Lines 21, 22 and 29 interrupts */ +#define STM32_IRQ_COMP46 (STM32_IRQ_FIRST+65) /* 65: COMP4 & COMP6 interrupts, or */ +#define STM32_IRQ_EXTI3012 (STM32_IRQ_FIRST+65) /* 65: EXTI Lines 30, 31 and 32 interrupts */ +#define STM32_IRQ_RESERVED66 (STM32_IRQ_FIRST+66) /* 66: Reserved */ +#define STM32_IRQ_HRTIMTM (STM32_IRQ_FIRST+67) /* 67: HRTIM master timer interrupt */ +#define STM32_IRQ_HRTIMTA (STM32_IRQ_FIRST+68) /* 68: HRTIM timer A interrupt */ +#define STM32_IRQ_HRTIMTB (STM32_IRQ_FIRST+69) /* 69: HRTIM timer B interrupt */ +#define STM32_IRQ_HRTIMTC (STM32_IRQ_FIRST+70) /* 70: HRTIM timer C interrupt */ +#define STM32_IRQ_HRTIMTD (STM32_IRQ_FIRST+71) /* 71: HRTIM timer D interrupt */ +#define STM32_IRQ_HRTIMTE (STM32_IRQ_FIRST+72) /* 72: HRTIM timer E interrupt */ +#define STM32_IRQ_HRTIMFLT (STM32_IRQ_FIRST+73) /* 73: HRTIM fault interrupt */ +#define STM32_IRQ_RESERVED74 (STM32_IRQ_FIRST+74) /* 74: Reserved */ +#define STM32_IRQ_RESERVED75 (STM32_IRQ_FIRST+75) /* 75: Reserved */ +#define STM32_IRQ_RESERVED76 (STM32_IRQ_FIRST+76) /* 76: Reserved */ +#define STM32_IRQ_RESERVED77 (STM32_IRQ_FIRST+77) /* 77: Reserved */ +#define STM32_IRQ_RESERVED78 (STM32_IRQ_FIRST+78) /* 78: Reserved */ +#define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST+79) /* 79: Reserved */ +#define STM32_IRQ_RESERVED80 (STM32_IRQ_FIRST+80) /* 80: Reserved */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */ + +#define NR_VECTORS (STM32_IRQ_FIRST+82) +#define NR_IRQS (STM32_IRQ_FIRST+82) + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data +****************************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************************************** + * Public Functions + ****************************************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_STM32F30XXX_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32f37xxx_irq.h b/arch/arm/include/stm32/stm32f37xxx_irq.h index 22456683bc3..4f8a431bf9d 100644 --- a/arch/arm/include/stm32/stm32f37xxx_irq.h +++ b/arch/arm/include/stm32/stm32f37xxx_irq.h @@ -1,5 +1,5 @@ /**************************************************************************************************** - * arch/arm/include/stm32s/stm32f37xxx_irq.h + * arch/arm/include/stm32/stm32f37xxx_irq.h * * Copyright (C) 2012 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/include/stm32/stm32f40xxx_irq.h b/arch/arm/include/stm32/stm32f40xxx_irq.h index b0499b6ba32..64df1a6fe57 100644 --- a/arch/arm/include/stm32/stm32f40xxx_irq.h +++ b/arch/arm/include/stm32/stm32f40xxx_irq.h @@ -1,5 +1,5 @@ /**************************************************************************************************** - * arch/arm/include/stm32s/stm32f40xxx_irq.h + * arch/arm/include/stm32/stm32f40xxx_irq.h * * Copyright (C) 2009, 2014-2015 Gregory Nutt. All rights reserved. * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. diff --git a/arch/arm/include/stm32/stm32l15xxx_irq.h b/arch/arm/include/stm32/stm32l15xxx_irq.h index ca692932f9b..d0c1380c878 100644 --- a/arch/arm/include/stm32/stm32l15xxx_irq.h +++ b/arch/arm/include/stm32/stm32l15xxx_irq.h @@ -1,5 +1,5 @@ /**************************************************************************************************** - * arch/arm/include/stm32s/stm32l15xxx_irq.h + * arch/arm/include/stm32/stm32l15xxx_irq.h * For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based 32-bit MCUs * * Copyright (C) 2013 Gregory Nutt. All rights reserved. diff --git a/arch/arm/src/a1x/a1x_serial.c b/arch/arm/src/a1x/a1x_serial.c index 7dae40aa997..ec8de5e0090 100644 --- a/arch/arm/src/a1x/a1x_serial.c +++ b/arch/arm/src/a1x/a1x_serial.c @@ -93,7 +93,6 @@ struct up_dev_s uint32_t uartbase; /* Base address of UART registers */ uint32_t baud; /* Configured baud */ uint32_t ier; /* Saved IER value */ - xcpt_t handler; /* UART interrupt handler */ uint8_t irq; /* IRQ associated with this UART */ uint8_t parity; /* 0=none, 1=odd, 2=even */ uint8_t bits; /* Number of bits (7 or 8) */ @@ -108,31 +107,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int uart_interrupt(struct uart_dev_s *dev); -#ifdef CONFIG_A1X_UART0 -static int uart0_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_A1X_UART1 -static int uart1_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_A1X_UART2 -static int uart2_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_A1X_UART3 -static int uart3_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_A1X_UART4 -static int uart4_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_A1X_UART5 -static int uart5_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_A1X_UART6 -static int uart6_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_A1X_UART7 -static int uart7_interrupt(int irq, void *context); -#endif +static int uart_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -214,7 +189,6 @@ static struct up_dev_s g_uart0priv = { .uartbase = A1X_UART0_VADDR, .baud = CONFIG_UART0_BAUD, - .handler = uart0_interrupt, .irq = A1X_IRQ_UART0, .parity = CONFIG_UART0_PARITY, .bits = CONFIG_UART0_BITS, @@ -245,7 +219,6 @@ static struct up_dev_s g_uart1priv = { .uartbase = A1X_UART1_VADDR, .baud = CONFIG_UART1_BAUD, - .handler = uart1_interrupt, .irq = A1X_IRQ_UART1, .parity = CONFIG_UART1_PARITY, .bits = CONFIG_UART1_BITS, @@ -276,7 +249,6 @@ static struct up_dev_s g_uart2priv = { .uartbase = A1X_UART2_VADDR, .baud = CONFIG_UART2_BAUD, - .handler = uart2_interrupt, .irq = A1X_IRQ_UART2, .parity = CONFIG_UART2_PARITY, .bits = CONFIG_UART2_BITS, @@ -307,7 +279,6 @@ static struct up_dev_s g_uart3priv = { .uartbase = A1X_UART3_VADDR, .baud = CONFIG_UART3_BAUD, - .handler = uart3_interrupt, .irq = A1X_IRQ_UART3, .parity = CONFIG_UART3_PARITY, .bits = CONFIG_UART3_BITS, @@ -338,7 +309,6 @@ static struct up_dev_s g_uart4priv = { .uartbase = A1X_UART4_VADDR, .baud = CONFIG_UART4_BAUD, - .handler = uart4_interrupt, .irq = A1X_IRQ_UART4, .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, @@ -369,7 +339,6 @@ static struct up_dev_s g_uart5priv = { .uartbase = A1X_UART5_VADDR, .baud = CONFIG_UART5_BAUD, - .handler = uart5_interrupt, .irq = A1X_IRQ_UART5, .parity = CONFIG_UART5_PARITY, .bits = CONFIG_UART5_BITS, @@ -400,7 +369,6 @@ static struct up_dev_s g_uart6priv = { .uartbase = A1X_UART6_VADDR, .baud = CONFIG_UART6_BAUD, - .handler = uart6_interrupt, .irq = A1X_IRQ_UART6, .parity = CONFIG_UART6_PARITY, .bits = CONFIG_UART6_BITS, @@ -431,7 +399,6 @@ static struct up_dev_s g_uart7priv = { .uartbase = A1X_UART7_VADDR, .baud = CONFIG_UART7_BAUD, - .handler = uart7_interrupt, .irq = A1X_IRQ_UART7, .parity = CONFIG_UART7_PARITY, .bits = CONFIG_UART7_BITS, @@ -1068,7 +1035,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, priv->handler); + ret = irq_attach(priv->irq, uart_interrupt, priv); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -1110,12 +1077,14 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int uart_interrupt(struct uart_dev_s *dev) +static int uart_interrupt(int irq, void *context, void *arg) { - struct up_dev_s *priv; - uint32_t status; - int passes; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct up_dev_s *priv = (struct up_dev_s *)arg; + uint32_t status; + int passes; + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct up_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, @@ -1201,62 +1170,6 @@ static int uart_interrupt(struct uart_dev_s *dev) return OK; } -#ifdef CONFIG_A1X_UART0 -static int uart0_interrupt(int irq, void *context) -{ - return uart_interrupt(&g_uart0port); -} -#endif - -#ifdef CONFIG_A1X_UART1 -static int uart1_interrupt(int irq, void *context) -{ - return uart_interrupt(&g_uart1port); -} -#endif - -#ifdef CONFIG_A1X_UART2 -static int uart2_interrupt(int irq, void *context) -{ - return uart_interrupt(&g_uart2port); -} -#endif - -#ifdef CONFIG_A1X_UART3 -static int uart3_interrupt(int irq, void *context) -{ - return uart_interrupt(&g_uart3port); -} -#endif - -#ifdef CONFIG_A1X_UART4 -static int uart4_interrupt(int irq, void *context) -{ - return uart_interrupt(&g_uart4port); -} -#endif - -#ifdef CONFIG_A1X_UART5 -static int uart5_interrupt(int irq, void *context) -{ - return uart_interrupt(&g_uart5port); -} -#endif - -#ifdef CONFIG_A1X_UART6 -static int uart6_interrupt(int irq, void *context) -{ - return uart_interrupt(&g_uart6port); -} -#endif - -#ifdef CONFIG_A1X_UART7 -static int uart7_interrupt(int irq, void *context) -{ - return uart_interrupt(&g_uart7port); -} -#endif - /**************************************************************************** * Name: up_ioctl * diff --git a/arch/arm/src/a1x/a1x_timerisr.c b/arch/arm/src/a1x/a1x_timerisr.c index 04407d10511..d5ef7508f41 100644 --- a/arch/arm/src/a1x/a1x_timerisr.c +++ b/arch/arm/src/a1x/a1x_timerisr.c @@ -82,7 +82,7 @@ * ****************************************************************************/ -static int a1x_timerisr(int irq, uint32_t *regs) +static int a1x_timerisr(int irq, uint32_t *regs, void *arg) { /* Only a TIMER0 interrupt is expected here */ @@ -138,7 +138,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(A1X_IRQ_TIMER0, (xcpt_t)a1x_timerisr); + (void)irq_attach(A1X_IRQ_TIMER0, (xcpt_t)a1x_timerisr, NULL); /* Enable interrupts from the TIMER 0 port */ diff --git a/arch/arm/src/armv6-m/up_hardfault.c b/arch/arm/src/armv6-m/up_hardfault.c index b3c24d88515..6b4f69760e1 100644 --- a/arch/arm/src/armv6-m/up_hardfault.c +++ b/arch/arm/src/armv6-m/up_hardfault.c @@ -75,7 +75,7 @@ * ****************************************************************************/ -int up_hardfault(int irq, FAR void *context) +int up_hardfault(int irq, FAR void *context, FAR void *arg) { uint32_t *regs = (uint32_t *)context; @@ -115,7 +115,7 @@ int up_hardfault(int irq, FAR void *context) if (insn == INSN_SVC0) { hfinfo("Forward SVCall\n"); - return up_svcall(irq, context); + return up_svcall(irq, context, NULL); } } diff --git a/arch/arm/src/armv6-m/up_svcall.c b/arch/arm/src/armv6-m/up_svcall.c index 1cd7e3a33b0..fd61de1906f 100644 --- a/arch/arm/src/armv6-m/up_svcall.c +++ b/arch/arm/src/armv6-m/up_svcall.c @@ -130,7 +130,7 @@ static void dispatch_syscall(void) * ****************************************************************************/ -int up_svcall(int irq, FAR void *context) +int up_svcall(int irq, FAR void *context, FAR void *arg) { uint32_t *regs = (uint32_t *)context; uint32_t cmd; diff --git a/arch/arm/src/armv7-a/arm_cpupause.c b/arch/arm/src/armv7-a/arm_cpupause.c index 6f92343c149..8a1499c2976 100644 --- a/arch/arm/src/armv7-a/arm_cpupause.c +++ b/arch/arm/src/armv7-a/arm_cpupause.c @@ -202,7 +202,7 @@ int up_cpu_paused(int cpu) * ****************************************************************************/ -int arm_pause_handler(int irq, FAR void *context) +int arm_pause_handler(int irq, FAR void *context, FAR void *arg) { int cpu = this_cpu(); diff --git a/arch/arm/src/armv7-a/arm_cpustart.c b/arch/arm/src/armv7-a/arm_cpustart.c index d63c035db68..3226153f5c1 100644 --- a/arch/arm/src/armv7-a/arm_cpustart.c +++ b/arch/arm/src/armv7-a/arm_cpustart.c @@ -103,7 +103,7 @@ static inline void arm_registerdump(FAR struct tcb_s *tcb) * ****************************************************************************/ -int arm_start_handler(int irq, FAR void *context) +int arm_start_handler(int irq, FAR void *context, FAR void *arg) { FAR struct tcb_s *tcb = this_task(); diff --git a/arch/arm/src/armv7-a/arm_gicv2.c b/arch/arm/src/armv7-a/arm_gicv2.c index dce0b621ed9..ec32fa52710 100644 --- a/arch/arm/src/armv7-a/arm_gicv2.c +++ b/arch/arm/src/armv7-a/arm_gicv2.c @@ -124,8 +124,8 @@ void arm_gic0_initialize(void) #ifdef CONFIG_SMP /* Attach SGI interrupt handlers. This attaches the handler for all CPUs. */ - DEBUGVERIFY(irq_attach(GIC_IRQ_SGI1, arm_start_handler)); - DEBUGVERIFY(irq_attach(GIC_IRQ_SGI2, arm_pause_handler)); + DEBUGVERIFY(irq_attach(GIC_IRQ_SGI1, arm_start_handler, NULL)); + DEBUGVERIFY(irq_attach(GIC_IRQ_SGI2, arm_pause_handler, NULL)); #endif arm_gic_dump("Exit arm_gic0_initialize", true, 0); diff --git a/arch/arm/src/armv7-a/gic.h b/arch/arm/src/armv7-a/gic.h index 87740651350..8c882ad6ddc 100644 --- a/arch/arm/src/armv7-a/gic.h +++ b/arch/arm/src/armv7-a/gic.h @@ -759,7 +759,7 @@ uint32_t *arm_decodeirq(uint32_t *regs); ****************************************************************************/ #ifdef CONFIG_SMP -int arm_start_handler(int irq, FAR void *context); +int arm_start_handler(int irq, FAR void *context, FAR void *arg); #endif /**************************************************************************** @@ -783,7 +783,7 @@ int arm_start_handler(int irq, FAR void *context); ****************************************************************************/ #ifdef CONFIG_SMP -int arm_pause_handler(int irq, FAR void *context); +int arm_pause_handler(int irq, FAR void *context, FAR void *arg); #endif /**************************************************************************** diff --git a/arch/arm/src/armv7-m/up_hardfault.c b/arch/arm/src/armv7-m/up_hardfault.c index fe133cc4f37..a68996836e1 100644 --- a/arch/arm/src/armv7-m/up_hardfault.c +++ b/arch/arm/src/armv7-m/up_hardfault.c @@ -80,7 +80,7 @@ * ****************************************************************************/ -int up_hardfault(int irq, FAR void *context) +int up_hardfault(int irq, FAR void *context, FAR void *arg) { #if defined(CONFIG_DEBUG_HARDFAULT) || !defined(CONFIG_ARMV7M_USEBASEPRI) uint32_t *regs = (uint32_t *)context; @@ -124,7 +124,7 @@ int up_hardfault(int irq, FAR void *context) if (insn == INSN_SVC0) { hfalert("Forward SVCall\n"); - return up_svcall(irq, context); + return up_svcall(irq, context, arg); } } #endif diff --git a/arch/arm/src/armv7-m/up_memfault.c b/arch/arm/src/armv7-m/up_memfault.c index f883209b769..f4f642e4def 100644 --- a/arch/arm/src/armv7-m/up_memfault.c +++ b/arch/arm/src/armv7-m/up_memfault.c @@ -77,7 +77,7 @@ * ****************************************************************************/ -int up_memfault(int irq, FAR void *context) +int up_memfault(int irq, FAR void *context, FAR void *arg) { /* Dump some memory management fault info */ diff --git a/arch/arm/src/armv7-m/up_svcall.c b/arch/arm/src/armv7-m/up_svcall.c index 8e78de3a432..e16a6f104c2 100644 --- a/arch/arm/src/armv7-m/up_svcall.c +++ b/arch/arm/src/armv7-m/up_svcall.c @@ -125,7 +125,7 @@ static void dispatch_syscall(void) * ****************************************************************************/ -int up_svcall(int irq, FAR void *context) +int up_svcall(int irq, FAR void *context, FAR void *arg) { uint32_t *regs = (uint32_t *)context; uint32_t cmd; diff --git a/arch/arm/src/c5471/c5471_ethernet.c b/arch/arm/src/c5471/c5471_ethernet.c index a163cecaabe..83259650c01 100644 --- a/arch/arm/src/c5471/c5471_ethernet.c +++ b/arch/arm/src/c5471/c5471_ethernet.c @@ -401,7 +401,7 @@ static void c5471_txstatus(struct c5471_driver_s *priv); static void c5471_txdone(struct c5471_driver_s *priv); static void c5471_interrupt_work(FAR void *arg); -static int c5471_interrupt(int irq, FAR void *context); +static int c5471_interrupt(int irq, FAR void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -1634,7 +1634,7 @@ static void c5471_interrupt_work(FAR void *arg) * ****************************************************************************/ -static int c5471_interrupt(int irq, FAR void *context) +static int c5471_interrupt(int irq, FAR void *context, FAR void *arg) { #if CONFIG_C5471_NET_NINTERFACES == 1 register struct c5471_driver_s *priv = &g_c5471[0]; @@ -2449,7 +2449,7 @@ void up_netinitialize(void) { /* Attach the IRQ to the driver */ - if (irq_attach(C5471_IRQ_ETHER, c5471_interrupt)) + if (irq_attach(C5471_IRQ_ETHER, c5471_interrupt, NULL)) { /* We could not attach the ISR to the ISR */ diff --git a/arch/arm/src/c5471/c5471_serial.c b/arch/arm/src/c5471/c5471_serial.c index 935bc46871d..44d0dc7fd25 100644 --- a/arch/arm/src/c5471/c5471_serial.c +++ b/arch/arm/src/c5471/c5471_serial.c @@ -108,7 +108,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); +static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -491,7 +491,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, up_interrupt); + ret = irq_attach(priv->irq, up_interrupt, dev); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -534,24 +534,13 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt(int irq, void *context) +static int up_interrupt(int irq, void *context, void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct up_dev_s *priv; volatile uint32_t cause; - if (g_irdapriv.irq == irq) - { - dev = &g_irdaport; - } - else if (g_modempriv.irq == irq) - { - dev = &g_modemport; - } - else - { - PANIC(); - } + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct up_dev_s *)dev->priv; cause = up_inserial(priv, UART_ISR_OFFS) & 0x0000003f; diff --git a/arch/arm/src/c5471/c5471_timerisr.c b/arch/arm/src/c5471/c5471_timerisr.c index 1720a13bf92..3933e5252bb 100644 --- a/arch/arm/src/c5471/c5471_timerisr.c +++ b/arch/arm/src/c5471/c5471_timerisr.c @@ -82,7 +82,7 @@ * ****************************************************************************/ -static int c5471_timerisr(int irq, uint32_t *regs) +static int c5471_timerisr(int irq, uint32_t *regs, FAR void *arg) { /* Process timer interrupt */ @@ -118,6 +118,6 @@ void arm_timer_initialize(void) /* Attach and enable the timer interrupt */ - irq_attach(C5471_IRQ_SYSTIMER, (xcpt_t)c5471_timerisr); + irq_attach(C5471_IRQ_SYSTIMER, (xcpt_t)c5471_timerisr, NULL); up_enable_irq(C5471_IRQ_SYSTIMER); } diff --git a/arch/arm/src/c5471/c5471_watchdog.c b/arch/arm/src/c5471/c5471_watchdog.c index d1381f45d46..baa7dd77496 100644 --- a/arch/arm/src/c5471/c5471_watchdog.c +++ b/arch/arm/src/c5471/c5471_watchdog.c @@ -95,7 +95,7 @@ static inline unsigned int wdt_prescaletoptv(unsigned int prescale); static int wdt_setusec(uint32_t usec); -static int wdt_interrupt(int irq, void *context); +static int wdt_interrupt(int irq, void *context, FAR void *arg); static int wdt_open(struct file *filep); static int wdt_close(struct file *filep); @@ -232,7 +232,7 @@ static int wdt_setusec(uint32_t usec) * Name: wdt_interrupt ****************************************************************************/ -static int wdt_interrupt(int irq, void *context) +static int wdt_interrupt(int irq, void *context, FAR void *arg) { wdinfo("expired\n"); @@ -382,7 +382,7 @@ int up_wdtinit(void) /* Request the interrupt. */ - ret = irq_attach(C5471_IRQ_WATCHDOG, wdt_interrupt); + ret = irq_attach(C5471_IRQ_WATCHDOG, wdt_interrupt, NULL); if (ret) { unregister_driver("/dev/wdt"); diff --git a/arch/arm/src/common/up_internal.h b/arch/arm/src/common/up_internal.h index a634c86df65..31d264828d3 100644 --- a/arch/arm/src/common/up_internal.h +++ b/arch/arm/src/common/up_internal.h @@ -374,13 +374,13 @@ uint32_t *up_doirq(int irq, uint32_t *regs); /* Exception Handlers */ -int up_svcall(int irq, FAR void *context); -int up_hardfault(int irq, FAR void *context); +int up_svcall(int irq, FAR void *context, FAR void *arg); +int up_hardfault(int irq, FAR void *context, FAR void *arg); # if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4) || \ defined(CONFIG_ARCH_CORTEXM7) -int up_memfault(int irq, FAR void *context); +int up_memfault(int irq, FAR void *context, FAR void *arg); # endif /* CONFIG_ARCH_CORTEXM3,4,7 */ diff --git a/arch/arm/src/dm320/dm320_serial.c b/arch/arm/src/dm320/dm320_serial.c index 19e5c9d7bdf..964e8923f07 100644 --- a/arch/arm/src/dm320/dm320_serial.c +++ b/arch/arm/src/dm320/dm320_serial.c @@ -1,8 +1,7 @@ /**************************************************************************** * arch/arm/src/dm320/dm320_serial.c - * arch/arm/src/chip/dm320_serial.c * - * Copyright (C) 2007-2009, 2012-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2012-2013, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -89,7 +88,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); +static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -430,7 +429,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, up_interrupt); + ret = irq_attach(priv->irq, up_interrupt, dev); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -472,25 +471,14 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt(int irq, void *context) +static int up_interrupt(int irq, void *context, void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct up_dev_s *priv; uint16_t status; int passes = 0; - if (g_uart1priv.irq == irq) - { - dev = &g_uart1port; - } - else if (g_uart0priv.irq == irq) - { - dev = &g_uart0port; - } - else - { - PANIC(); - } + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct up_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, diff --git a/arch/arm/src/dm320/dm320_timerisr.c b/arch/arm/src/dm320/dm320_timerisr.c index 33ed932666c..735af0460da 100644 --- a/arch/arm/src/dm320/dm320_timerisr.c +++ b/arch/arm/src/dm320/dm320_timerisr.c @@ -109,7 +109,7 @@ * ****************************************************************************/ -static int dm320_timerisr(int irq, uint32_t *regs) +static int dm320_timerisr(int irq, uint32_t *regs, FAR void *arg) { /* Process timer interrupt */ @@ -147,7 +147,7 @@ void arm_timer_initialize(void) /* Attach and enable the timer interrupt */ - irq_attach(DM320_IRQ_SYSTIMER, (xcpt_t)dm320_timerisr); + irq_attach(DM320_IRQ_SYSTIMER, (xcpt_t)dm320_timerisr, NULL); up_enable_irq(DM320_IRQ_SYSTIMER); } diff --git a/arch/arm/src/dm320/dm320_usbdev.c b/arch/arm/src/dm320/dm320_usbdev.c index df25123b09e..18dce86dbf1 100644 --- a/arch/arm/src/dm320/dm320_usbdev.c +++ b/arch/arm/src/dm320/dm320_usbdev.c @@ -309,8 +309,8 @@ static void dm320_dispatchrequest(struct dm320_usbdev_s *priv, const struct usb_ctrlreq_s *ctrl); static inline void dm320_ep0setup(struct dm320_usbdev_s *priv); static inline uint32_t dm320_highestpriinterrupt(int intstatus); -static int dm320_ctlrinterrupt(int irq, FAR void *context); -static int dm320_attachinterrupt(int irq, FAR void *context); +static int dm320_ctlrinterrupt(int irq, FAR void *context, FAR void *arg); +static int dm320_attachinterrupt(int irq, FAR void *context, FAR void *arg); /* Initialization operations */ @@ -1513,7 +1513,7 @@ static inline uint32_t dm320_highestpriinterrupt(int intstatus) * ****************************************************************************/ -static int dm320_ctlrinterrupt(int irq, FAR void *context) +static int dm320_ctlrinterrupt(int irq, FAR void *context, FAR void *arg) { struct dm320_usbdev_s *priv = &g_usbdev; struct dm320_ep_s *privep ; @@ -1680,7 +1680,7 @@ static int dm320_ctlrinterrupt(int irq, FAR void *context) * ****************************************************************************/ -static int dm320_attachinterrupt(int irq, FAR void *context) +static int dm320_attachinterrupt(int irq, FAR void *context, FAR void *arg) { struct dm320_usbdev_s *priv = &g_usbdev; uint16_t gio; @@ -2438,7 +2438,7 @@ void up_usbinitialize(void) /* Attach host attach GIO interrupt */ - if (irq_attach(IRQ_USBATTACH, dm320_attachinterrupt) != 0) + if (irq_attach(IRQ_USBATTACH, dm320_attachinterrupt, NULL) != 0) { usbtrace(TRACE_DEVERROR(DM320_TRACEERR_ATTACHIRQREG), 0); goto errout; @@ -2448,7 +2448,7 @@ void up_usbinitialize(void) * enabled when the driver is bound */ - if (irq_attach(DM320_IRQ_USB1, dm320_ctlrinterrupt) != 0) + if (irq_attach(DM320_IRQ_USB1, dm320_ctlrinterrupt, NULL) != 0) { usbtrace(TRACE_DEVERROR(DM320_TRACEERR_COREIRQREG), 0); goto errout; diff --git a/arch/arm/src/efm32/efm32_adc.c b/arch/arm/src/efm32/efm32_adc.c index c9e339e6ea2..e79c2a61ef5 100644 --- a/arch/arm/src/efm32/efm32_adc.c +++ b/arch/arm/src/efm32/efm32_adc.c @@ -123,7 +123,7 @@ static void adc_hw_reset(struct efm32_dev_s *priv, bool reset); /* ADC Interrupt Handler */ -static int adc_interrupt(FAR struct adc_dev_s *dev); +static int adc_interrupt(int irq, FAR void *context, FAR struct adc_dev_s *dev); /* ADC Driver Methods */ @@ -1072,7 +1072,7 @@ static int adc_setup(FAR struct adc_dev_s *dev) /* Attach the ADC interrupt */ - ret = irq_attach(priv->irq, priv->isr); + ret = irq_attach(priv->irq, priv->isr, dev); if (ret == OK) { /* Make sure that the ADC device is in the powered up, reset state */ @@ -1180,7 +1180,7 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) * ****************************************************************************/ -static int adc_interrupt(FAR struct adc_dev_s *dev) +static int adc_interrupt(int irq, FAR void *context, FAR struct adc_dev_s *dev) { FAR struct efm32_dev_s *priv = (FAR struct efm32_dev_s *)dev->ad_priv; uint32_t adcsr; diff --git a/arch/arm/src/efm32/efm32_dma.c b/arch/arm/src/efm32/efm32_dma.c index 4bf901500b6..d568626b295 100644 --- a/arch/arm/src/efm32/efm32_dma.c +++ b/arch/arm/src/efm32/efm32_dma.c @@ -204,7 +204,7 @@ efm32_get_descriptor(struct dma_channel_s *dmach, bool alt) * ****************************************************************************/ -static int efm32_dmac_interrupt(int irq, void *context) +static int efm32_dmac_interrupt(int irq, void *context, FAR void *arg) { struct dma_channel_s *dmach; unsigned int chndx; @@ -297,7 +297,7 @@ void weak_function up_dmainitialize(void) /* Attach DMA interrupt vector */ - (void)irq_attach(EFM32_IRQ_DMA, efm32_dmac_interrupt); + (void)irq_attach(EFM32_IRQ_DMA, efm32_dmac_interrupt, NULL); /* Enable the DMA controller */ diff --git a/arch/arm/src/efm32/efm32_gpioirq.c b/arch/arm/src/efm32/efm32_gpioirq.c index 8c3527e9f55..1b317582811 100644 --- a/arch/arm/src/efm32/efm32_gpioirq.c +++ b/arch/arm/src/efm32/efm32_gpioirq.c @@ -133,7 +133,7 @@ static int efm32_gpio_interrupt(uint32_t mask, void *context) * ************************************************************************************/ -static int efm32_even_interrupt(int irq, void *context) +static int efm32_even_interrupt(int irq, void *context, FAR void *arg) { return efm32_gpio_interrupt(0x00005555, context); } @@ -146,7 +146,7 @@ static int efm32_even_interrupt(int irq, void *context) * ************************************************************************************/ -static int efm32_odd_interrupt(int irq, void *context) +static int efm32_odd_interrupt(int irq, void *context, FAR void *arg) { return efm32_gpio_interrupt(0x0000aaaa, context); } @@ -173,8 +173,8 @@ void efm32_gpioirqinitialize(void) /* Attach the even and odd interrupt handlers */ - DEBUGVERIFY(irq_attach(EFM32_IRQ_GPIO_EVEN, efm32_even_interrupt)); - DEBUGVERIFY(irq_attach(EFM32_IRQ_GPIO_ODD, efm32_odd_interrupt)); + DEBUGVERIFY(irq_attach(EFM32_IRQ_GPIO_EVEN, efm32_even_interrupt, NULL)); + DEBUGVERIFY(irq_attach(EFM32_IRQ_GPIO_ODD, efm32_odd_interrupt, NULL)); /* Enable GPIO even and odd interrupts at the NVIC */ diff --git a/arch/arm/src/efm32/efm32_i2c.c b/arch/arm/src/efm32/efm32_i2c.c index 1c10e5b14c1..59ad3aa2f84 100644 --- a/arch/arm/src/efm32/efm32_i2c.c +++ b/arch/arm/src/efm32/efm32_i2c.c @@ -220,7 +220,7 @@ struct efm32_i2c_config_s uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ #ifndef CONFIG_I2C_POLLED - int (*isr) (int, void *); /* Interrupt handler */ + int (*isr) (int, void *, void *); /* Interrupt handler */ uint32_t irq; /* Event IRQ */ #endif }; @@ -298,10 +298,10 @@ static int efm32_i2c_isr(struct efm32_i2c_priv_s *priv); #ifndef CONFIG_I2C_POLLED #ifdef CONFIG_EFM32_I2C0 -static int efm32_i2c0_isr(int irq, void *context); +static int efm32_i2c0_isr(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_EFM32_I2C1 -static int efm32_i2c1_isr(int irq, void *context); +static int efm32_i2c1_isr(int irq, void *context, FAR void *arg); #endif #endif /* !CONFIG_I2C_POLLED */ @@ -1290,7 +1290,7 @@ done: ****************************************************************************/ #ifdef CONFIG_EFM32_I2C0 -static int efm32_i2c0_isr(int irq, void *context) +static int efm32_i2c0_isr(int irq, void *context, FAR void *arg) { return efm32_i2c_isr(&efm32_i2c0_priv); } @@ -1305,7 +1305,7 @@ static int efm32_i2c0_isr(int irq, void *context) ****************************************************************************/ #ifdef CONFIG_EFM32_I2C1 -static int efm32_i2c1_isr(int irq, void *context) +static int efm32_i2c1_isr(int irq, void *context, FAR void *arg) { return efm32_i2c_isr(&efm32_i2c1_priv); } @@ -1389,7 +1389,7 @@ static int efm32_i2c_init(FAR struct efm32_i2c_priv_s *priv) /* Attach ISRs */ #ifndef CONFIG_I2C_POLLED - irq_attach(priv->config->irq, priv->config->isr); + irq_attach(priv->config->irq, priv->config->isr, NULL); up_enable_irq(priv->config->irq); #endif diff --git a/arch/arm/src/efm32/efm32_irq.c b/arch/arm/src/efm32/efm32_irq.c index db5992dea7b..859860d0725 100644 --- a/arch/arm/src/efm32/efm32_irq.c +++ b/arch/arm/src/efm32/efm32_irq.c @@ -163,7 +163,7 @@ static void efm32_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int efm32_nmi(int irq, FAR void *context) +static int efm32_nmi(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -171,7 +171,7 @@ static int efm32_nmi(int irq, FAR void *context) return 0; } -static int efm32_busfault(int irq, FAR void *context) +static int efm32_busfault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); @@ -179,7 +179,7 @@ static int efm32_busfault(int irq, FAR void *context) return 0; } -static int efm32_usagefault(int irq, FAR void *context) +static int efm32_usagefault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); @@ -187,7 +187,7 @@ static int efm32_usagefault(int irq, FAR void *context) return 0; } -static int efm32_pendsv(int irq, FAR void *context) +static int efm32_pendsv(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -195,7 +195,7 @@ static int efm32_pendsv(int irq, FAR void *context) return 0; } -static int efm32_dbgmonitor(int irq, FAR void *context) +static int efm32_dbgmonitor(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -203,7 +203,7 @@ static int efm32_dbgmonitor(int irq, FAR void *context) return 0; } -static int efm32_reserved(int irq, FAR void *context) +static int efm32_reserved(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -382,8 +382,8 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(EFM32_IRQ_SVCALL, up_svcall); - irq_attach(EFM32_IRQ_HARDFAULT, up_hardfault); + irq_attach(EFM32_IRQ_SVCALL, up_svcall, NULL); + irq_attach(EFM32_IRQ_HARDFAULT, up_hardfault, NULL); /* Set the priority of the SVCall interrupt */ @@ -396,22 +396,22 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(EFM32_IRQ_MEMFAULT, up_memfault); + irq_attach(EFM32_IRQ_MEMFAULT, up_memfault, NULL); up_enable_irq(EFM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(EFM32_IRQ_NMI, efm32_nmi); + irq_attach(EFM32_IRQ_NMI, efm32_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(EFM32_IRQ_MEMFAULT, up_memfault); + irq_attach(EFM32_IRQ_MEMFAULT, up_memfault, NULL); #endif - irq_attach(EFM32_IRQ_BUSFAULT, efm32_busfault); - irq_attach(EFM32_IRQ_USAGEFAULT, efm32_usagefault); - irq_attach(EFM32_IRQ_PENDSV, efm32_pendsv); - irq_attach(EFM32_IRQ_DBGMONITOR, efm32_dbgmonitor); - irq_attach(EFM32_IRQ_RESERVED, efm32_reserved); + irq_attach(EFM32_IRQ_BUSFAULT, efm32_busfault, NULL); + irq_attach(EFM32_IRQ_USAGEFAULT, efm32_usagefault, NULL); + irq_attach(EFM32_IRQ_PENDSV, efm32_pendsv, NULL); + irq_attach(EFM32_IRQ_DBGMONITOR, efm32_dbgmonitor, NULL); + irq_attach(EFM32_IRQ_RESERVED, efm32_reserved, NULL); #endif efm32_dumpnvic("initial", NR_VECTORS); diff --git a/arch/arm/src/efm32/efm32_leserial.c b/arch/arm/src/efm32/efm32_leserial.c index 8a5de937888..de8d157c8ab 100644 --- a/arch/arm/src/efm32/efm32_leserial.c +++ b/arch/arm/src/efm32/efm32_leserial.c @@ -134,7 +134,6 @@ struct efm32_config_s { uintptr_t uartbase; /* Base address of UART registers */ - xcpt_t handler; /* Interrupt handler */ uint32_t baud; /* Configured baud */ uint8_t irq; /* IRQ associated with this LEUART (for enable) */ uint8_t parity; /* 0=none, 1=odd, 2=even */ @@ -163,13 +162,7 @@ static int efm32_setup(struct uart_dev_s *dev); static void efm32_shutdown(struct uart_dev_s *dev); static int efm32_attach(struct uart_dev_s *dev); static void efm32_detach(struct uart_dev_s *dev); -static int efm32_interrupt(struct uart_dev_s *dev); -#if defined(CONFIG_EFM32_LEUART0) -static int efm32_leuart0_interrupt(int irq, void *context); -#endif -#if defined(CONFIG_EFM32_LEUART1) -static int efm32_leuart1_interrupt(int irq, void *context); -#endif +static int efm32_interrupt(int irq, void *context, FAR void *arg); static int efm32_ioctl(struct file *filep, int cmd, unsigned long arg); static int efm32_receive(struct uart_dev_s *dev, uint32_t *status); static void efm32_rxint(struct uart_dev_s *dev, bool enable); @@ -219,7 +212,6 @@ static char g_leuart1txbuffer[CONFIG_LEUART1_TXBUFSIZE]; static const struct efm32_config_s g_leuart0config = { .uartbase = EFM32_LEUART0_BASE, - .handler = efm32_leuart0_interrupt, .baud = CONFIG_LEUART0_BAUD, .irq = EFM32_IRQ_LEUART0, .parity = CONFIG_LEUART0_PARITY, @@ -255,7 +247,6 @@ static struct uart_dev_s g_leuart0port = static struct efm32_config_s g_leuart1config = { .uartbase = EFM32_LEUART1_BASE, - .handler = efm32_leuart1_interrupt, .baud = CONFIG_LEUART1_BAUD, .irq = EFM32_IRQ_LEUART1, .parity = CONFIG_LEUART1_PARITY, @@ -429,7 +420,7 @@ static int efm32_attach(struct uart_dev_s *dev) * disabled in the C2 register. */ - ret = irq_attach(config->irq, config->handler); + ret = irq_attach(config->irq, efm32_interrupt, dev); if (ret >= 0) { up_enable_irq(config->irq); @@ -471,12 +462,14 @@ static void efm32_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int efm32_interrupt(struct uart_dev_s *dev) +static int efm32_interrupt(int irq, void *context, FAR void *arg) { - struct efm32_leuart_s *priv = (struct efm32_leuart_s *)dev->priv; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct efm32_leuart_s *priv; uint32_t intflags; - DEBUGASSERT(priv); + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct efm32_leuart_s *)dev->priv; /* Read the interrupt flags register */ @@ -534,20 +527,6 @@ static int efm32_interrupt(struct uart_dev_s *dev) return OK; } -#if defined(CONFIG_EFM32_LEUART0) -static int efm32_leuart0_interrupt(int irq, void *context) -{ - return efm32_interrupt(&g_leuart0port); -} -#endif - -#if defined(CONFIG_EFM32_LEUART1) -static int efm32_leuart1_interrupt(int irq, void *context) -{ - return efm32_interrupt(&g_leuart1port); -} -#endif - /**************************************************************************** * Name: efm32_ioctl * diff --git a/arch/arm/src/efm32/efm32_pwm.c b/arch/arm/src/efm32/efm32_pwm.c index f07a3eed4b7..180fe04e00c 100644 --- a/arch/arm/src/efm32/efm32_pwm.c +++ b/arch/arm/src/efm32/efm32_pwm.c @@ -133,19 +133,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv, defined(CONFIG_EFM32_TIMER2_PWM) || \ defined(CONFIG_EFM32_TIMER3_PWM) \ ) -static int pwm_interrupt(struct efm32_pwmtimer_s *priv); -#if defined(CONFIG_EFM32_TIMER0_PWM) -static int pwm_timer0_interrupt(int irq, void *context); -#endif -#if defined(CONFIG_EFM32_TIMER1_PWM) -static int pwm_timer1_interrupt(int irq, void *context); -#endif -#if defined(CONFIG_EFM32_TIMER2_PWM) -static int pwm_timer2_interrupt(int irq, void *context); -#endif -#if defined(CONFIG_EFM32_TIMER3_PWM) -static int pwm_timer3_interrupt(int irq, void *context); -#endif +static int pwm_interrupt(int irq, void *context, FAR void *arg); static uint8_t pwm_pulsecount(uint32_t count); #endif @@ -446,7 +434,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv, * Handle timer interrupts. * * Input parameters: - * priv - A reference to the lower half PWM driver state structure + * Standard interrupt handler arguments. * * Returned Value: * Zero on success; a negated errno value on failure @@ -459,12 +447,15 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv, defined(CONFIG_EFM32_TIMER3_PWM) \ ) #warning "not yet implemented" -static int pwm_interrupt(struct efm32_pwmtimer_s *priv) +static int pwm_interrupt(int irq, void *context, FAR void *arg) { /* TODO pwm_interrupt */ #if 0 + struct efm32_pwmtimer_s *priv = (struct efm32_pwmtimer_s *)arg; uint32_t regval; + DEBUGASSERT(priv != NULL); + /* Verify that this is an update interrupt. Nothing else is expected. */ regval = pwm_getreg(priv, STM32_ATIM_SR_OFFSET); @@ -532,48 +523,6 @@ static int pwm_interrupt(struct efm32_pwmtimer_s *priv) } #endif -/**************************************************************************** - * Name: pwm_timer1/3_interrupt - * - * Description: - * Handle timer 1..3 interrupts. - * - * Input parameters: - * Standard NuttX interrupt inputs - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -#if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_EFM32_TIMER0_PWM) -static int pwm_timer0_interrupt(int irq, void *context) -{ - return pwm_interrupt(&g_pwm0dev); -} -#endif - -#if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_EFM32_TIMER1_PWM) -static int pwm_timer1_interrupt(int irq, void *context) -{ - return pwm_interrupt(&g_pwm1dev); -} -#endif - -#if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_EFM32_TIMER2_PWM) -static int pwm_timer2_interrupt(int irq, void *context) -{ - return pwm_interrupt(&g_pwm2dev); -} -#endif - -#if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_EFM32_TIMER3_PWM) -static int pwm_timer3_interrupt(int irq, void *context) -{ - return pwm_interrupt(&g_pwm3dev); -} -#endif - /**************************************************************************** * Name: pwm_pulsecount * @@ -866,50 +815,22 @@ FAR struct pwm_lowerhalf_s *efm32_pwminitialize(int timer) #ifdef CONFIG_EFM32_TIMER0_PWM case 0: lower = &g_pwm0dev; - - /* Attach but disable the TIM1 update interrupt */ - -#ifdef CONFIG_PWM_PULSECOUNT - irq_attach(lower->irq, pwm_timer0_interrupt); - up_disable_irq(lower->irq); -#endif break; #endif #ifdef CONFIG_EFM32_TIMER1_PWM case 1: lower = &g_pwm1dev; - - /* Attach but disable the TIM1 update interrupt */ - -#ifdef CONFIG_PWM_PULSECOUNT - irq_attach(lower->irq, pwm_timer0_interrupt); - up_disable_irq(lower->irq); -#endif break; #endif #ifdef CONFIG_EFM32_TIMER2_PWM case 2: lower = &g_pwm2dev; - - /* Attach but disable the TIM1 update interrupt */ - -#ifdef CONFIG_PWM_PULSECOUNT - irq_attach(lower->irq, pwm_timer2_interrupt); - up_disable_irq(lower->irq); -#endif break; #endif #ifdef CONFIG_EFM32_TIMER3_PWM case 3: lower = &g_pwm3dev; - - /* Attach but disable the TIM1 update interrupt */ - -#ifdef CONFIG_PWM_PULSECOUNT - irq_attach(lower->irq, pwm_timer3_interrupt); - up_disable_irq(lower->irq); -#endif break; #endif @@ -918,6 +839,13 @@ FAR struct pwm_lowerhalf_s *efm32_pwminitialize(int timer) return NULL; } + /* Attach but disable the timer update interrupt */ + +#ifdef CONFIG_PWM_PULSECOUNT + irq_attach(lower->irq, pwm_interrupt, lower); + up_disable_irq(lower->irq); +#endif + return (FAR struct pwm_lowerhalf_s *)lower; } diff --git a/arch/arm/src/efm32/efm32_rtc_burtc.c b/arch/arm/src/efm32/efm32_rtc_burtc.c index 52c8811ae50..d0028b6a11f 100644 --- a/arch/arm/src/efm32/efm32_rtc_burtc.c +++ b/arch/arm/src/efm32/efm32_rtc_burtc.c @@ -175,7 +175,7 @@ volatile bool g_rtc_enabled = false; * ************************************************************************************/ -static int efm32_rtc_burtc_interrupt(int irq, void *context) +static int efm32_rtc_burtc_interrupt(int irq, void *context, FAR void *arg) { uint32_t source = getreg32(EFM32_BURTC_IF); @@ -378,7 +378,7 @@ int up_rtc_initialize(void) /* Configure RTC interrupt to catch overflow and alarm interrupts. */ - irq_attach(EFM32_IRQ_BURTC, efm32_rtc_burtc_interrupt); + irq_attach(EFM32_IRQ_BURTC, efm32_rtc_burtc_interrupt, NULL); up_enable_irq(EFM32_IRQ_BURTC); g_rtc_enabled = true; diff --git a/arch/arm/src/efm32/efm32_serial.c b/arch/arm/src/efm32/efm32_serial.c index 52848fcd03d..a13bfe4d588 100644 --- a/arch/arm/src/efm32/efm32_serial.c +++ b/arch/arm/src/efm32/efm32_serial.c @@ -220,8 +220,6 @@ struct efm32_config_s { uintptr_t uartbase; /* Base address of UART registers */ - xcpt_t rxhandler; /* RX interrupt handler */ - xcpt_t txhandler; /* TX interrupt handler */ uint32_t baud; /* Configured baud */ uint8_t rxirq; /* RX IRQ associated with this UART (for enable) */ uint8_t txirq; /* TX IRQ associated with this UART (for enable) */ @@ -257,38 +255,8 @@ static int efm32_setup(struct uart_dev_s *dev); static void efm32_shutdown(struct uart_dev_s *dev); static int efm32_attach(struct uart_dev_s *dev); static void efm32_detach(struct uart_dev_s *dev); -static int efm32_rxinterrupt(struct uart_dev_s *dev); -#if defined(CONFIG_EFM32_USART0_ISUART) -static int efm32_usart0_rxinterrupt(int irq, void *context); -#endif -#if defined(CONFIG_EFM32_USART1_ISUART) -static int efm32_usart1_rxinterrupt(int irq, void *context); -#endif -#if defined(CONFIG_EFM32_USART2_ISUART) -static int efm32_usart2_rxinterrupt(int irq, void *context); -#endif -#if defined(CONFIG_EFM32_UART0) -static int efm32_uart0_rxinterrupt(int irq, void *context); -#endif -#if defined(CONFIG_EFM32_UART1) -static int efm32_uart1_rxinterrupt(int irq, void *context); -#endif -static int efm32_txinterrupt(struct uart_dev_s *dev); -#if defined(CONFIG_EFM32_USART0_ISUART) -static int efm32_usart0_txinterrupt(int irq, void *context); -#endif -#if defined(CONFIG_EFM32_USART1_ISUART) -static int efm32_usart1_txinterrupt(int irq, void *context); -#endif -#if defined(CONFIG_EFM32_USART2_ISUART) -static int efm32_usart2_txinterrupt(int irq, void *context); -#endif -#if defined(CONFIG_EFM32_UART0) -static int efm32_uart0_txinterrupt(int irq, void *context); -#endif -#if defined(CONFIG_EFM32_UART1) -static int efm32_uart1_txinterrupt(int irq, void *context); -#endif +static int efm32_rxinterrupt(int irq, void *context, void *arg); +static int efm32_txinterrupt((int irq, void *context, void *arg); static int efm32_ioctl(struct file *filep, int cmd, unsigned long arg); static int efm32_receive(struct uart_dev_s *dev, uint32_t *status); static void efm32_rxint(struct uart_dev_s *dev, bool enable); @@ -350,8 +318,6 @@ static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; static const struct efm32_usart_s g_usart0config = { .uartbase = EFM32_USART0_BASE, - .rxhandler = efm32_usart0_rxinterrupt, - .txhandler = efm32_usart0_txinterrupt, .baud = CONFIG_USART0_BAUD, .rxirq = EFM32_IRQ_USART0_RX, .txirq = EFM32_IRQ_USART0_TX, @@ -388,8 +354,6 @@ static struct uart_dev_s g_usart0port = static struct efm32_config_s g_usart1config = { .uartbase = EFM32_USART1_BASE, - .rxhandler = efm32_usart1_rxinterrupt, - .txhandler = efm32_usart1_txinterrupt, .baud = CONFIG_USART1_BAUD, .rxirq = EFM32_IRQ_USART1_RX, .txirq = EFM32_IRQ_USART1_TX, @@ -426,8 +390,6 @@ static struct uart_dev_s g_usart1port = static struct efm32_config_s g_usart2config = { .uartbase = EFM32_USART2_BASE, - .rxhandler = efm32_usart2_rxinterrupt, - .txhandler = efm32_usart2_txinterrupt, .baud = CONFIG_USART2_BAUD, .rxirq = EFM32_IRQ_USART2_RX, .txirq = EFM32_IRQ_USART2_TX, @@ -464,8 +426,6 @@ static struct uart_dev_s g_usart2port = static struct efm32_config_s g_uart0config = { .uartbase = EFM32_UART0_BASE, - .rxhandler = efm32_uart0_rxinterrupt, - .txhandler = efm32_uart0_txinterrupt, .baud = CONFIG_UART0_BAUD, .rxirq = EFM32_IRQ_UART0_RX, .txirq = EFM32_IRQ_UART0_TX, @@ -502,8 +462,6 @@ static struct uart_dev_s g_uart0port = static struct efm32_usart_s g_uart1config = { .uartbase = EFM32_UART1_BASE, - .rxhandler = efm32_uart1_rxinterrupt, - .txhandler = efm32_uart1_txinterrupt, .baud = CONFIG_UART1_BAUD, .rxirq = EFM32_IRQ_UART1_RX, .txirq = EFM32_IRQ_UART1_TX, @@ -689,13 +647,13 @@ static int efm32_attach(struct uart_dev_s *dev) * disabled in the C2 register. */ - ret = irq_attach(config->rxirq, config->rxhandler); + ret = irq_attach(config->rxirq, efm32_rxinterrupt, dev); if (ret < 0) { return ret; } - ret = irq_attach(config->txirq, config->txhandler); + ret = irq_attach(config->txirq, efm32_txinterrupt, dev); if (ret < 0) { irq_detach(config->rxirq); @@ -742,12 +700,14 @@ static void efm32_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int efm32_rxinterrupt(struct uart_dev_s *dev) +static int efm32_rxinterrupt(int irq, void *context, void *arg) { - struct efm32_usart_s *priv = (struct efm32_usart_s *)dev->priv; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct efm32_usart_s *priv; uint32_t intflags; - DEBUGASSERT(priv); + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct efm32_usart_s *)dev->priv; /* Read the interrupt flags register */ @@ -787,41 +747,6 @@ static int efm32_rxinterrupt(struct uart_dev_s *dev) return OK; } -#if defined(CONFIG_EFM32_USART0_ISUART) -static int efm32_usart0_rxinterrupt(int irq, void *context) -{ - return efm32_rxinterrupt(&g_usart0port); -} -#endif - -#if defined(CONFIG_EFM32_USART1_ISUART) -static int efm32_usart1_rxinterrupt(int irq, void *context) -{ - return efm32_rxinterrupt(&g_usart1port); -} -#endif - -#if defined(CONFIG_EFM32_USART2_ISUART) -static int efm32_usart2_rxinterrupt(int irq, void *context) -{ - return efm32_rxinterrupt(&g_usart2port); -} -#endif - -#if defined(CONFIG_EFM32_UART0) -static int efm32_uart0_rxinterrupt(int irq, void *context) -{ - return efm32_rxinterrupt(&g_uart0port); -} -#endif - -#if defined(CONFIG_EFM32_UART1) -static int efm32_uart1_rxinterrupt(int irq, void *context) -{ - return efm32_rxinterrupt(&g_uart1port); -} -#endif - /**************************************************************************** * Name: efm32_txinterrupt * @@ -830,12 +755,14 @@ static int efm32_uart1_rxinterrupt(int irq, void *context) * ****************************************************************************/ -static int efm32_txinterrupt(struct uart_dev_s *dev) +static int efm32_txinterrupt((int irq, void *context, void *arg) { - struct efm32_usart_s *priv = (struct efm32_usart_s *)dev->priv; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct efm32_usart_s *priv; uint32_t intflags; - DEBUGASSERT(priv); + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct efm32_usart_s *)dev->priv; /* Read the interrupt flags register */ @@ -870,41 +797,6 @@ static int efm32_txinterrupt(struct uart_dev_s *dev) return OK; } -#if defined(CONFIG_EFM32_USART0_ISUART) -static int efm32_usart0_txinterrupt(int irq, void *context) -{ - return efm32_txinterrupt(&g_usart0port); -} -#endif - -#if defined(CONFIG_EFM32_USART1_ISUART) -static int efm32_usart1_txinterrupt(int irq, void *context) -{ - return efm32_txinterrupt(&g_usart1port); -} -#endif - -#if defined(CONFIG_EFM32_USART2_ISUART) -static int efm32_usart2_txinterrupt(int irq, void *context) -{ - return efm32_txinterrupt(&g_usart2port); -} -#endif - -#if defined(CONFIG_EFM32_UART0) -static int efm32_uart0_txinterrupt(int irq, void *context) -{ - return efm32_txinterrupt(&g_uart0port); -} -#endif - -#if defined(CONFIG_EFM32_UART1) -static int efm32_uart1_txinterrupt(int irq, void *context) -{ - return efm32_txinterrupt(&g_uart1port); -} -#endif - /**************************************************************************** * Name: efm32_ioctl * diff --git a/arch/arm/src/efm32/efm32_timerisr.c b/arch/arm/src/efm32/efm32_timerisr.c index 095143482b7..2fdd5a6661f 100644 --- a/arch/arm/src/efm32/efm32_timerisr.c +++ b/arch/arm/src/efm32/efm32_timerisr.c @@ -86,7 +86,7 @@ * ****************************************************************************/ -static int efm32_timerisr(int irq, uint32_t *regs) +static int efm32_timerisr(int irq, uint32_t *regs, FAR void *arg) { /* Process timer interrupt */ @@ -125,7 +125,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(EFM32_IRQ_SYSTICK, (xcpt_t)efm32_timerisr); + (void)irq_attach(EFM32_IRQ_SYSTICK, (xcpt_t)efm32_timerisr, NULL); /* Enable SysTick interrupts */ diff --git a/arch/arm/src/efm32/efm32_usbdev.c b/arch/arm/src/efm32/efm32_usbdev.c index 26753dd3ff4..8f598342806 100644 --- a/arch/arm/src/efm32/efm32_usbdev.c +++ b/arch/arm/src/efm32/efm32_usbdev.c @@ -574,7 +574,7 @@ static inline void efm32_otginterrupt(FAR struct efm32_usbdev_s *priv); /* First level interrupt processing */ -static int efm32_usbinterrupt(int irq, FAR void *context); +static int efm32_usbinterrupt(int irq, FAR void *context, FAR void *arg); /* Endpoint operations *********************************************************/ /* Global OUT NAK controls */ @@ -3498,7 +3498,7 @@ static inline void efm32_otginterrupt(FAR struct efm32_usbdev_s *priv) * ****************************************************************************/ -static int efm32_usbinterrupt(int irq, FAR void *context) +static int efm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) { /* At present, there is only a single OTG FS device support. Hence it is * pre-allocated as g_otgfsdev. However, in most code, the private data @@ -5485,7 +5485,7 @@ void up_usbinitialize(void) /* Attach the OTG FS interrupt handler */ - ret = irq_attach(EFM32_IRQ_USB, efm32_usbinterrupt); + ret = irq_attach(EFM32_IRQ_USB, efm32_usbinterrupt, NULL); if (ret < 0) { uerr("ERROR: irq_attach failed\n", ret); diff --git a/arch/arm/src/efm32/efm32_usbhost.c b/arch/arm/src/efm32/efm32_usbhost.c index be9bbccf23f..3d5a6888baa 100644 --- a/arch/arm/src/efm32/efm32_usbhost.c +++ b/arch/arm/src/efm32/efm32_usbhost.c @@ -417,7 +417,7 @@ static inline void efm32_gint_ipxfrisr(FAR struct efm32_usbhost_s *priv); /* First level, global interrupt handler */ -static int efm32_gint_isr(int irq, FAR void *context); +static int efm32_gint_isr(int irq, FAR void *context, FAR void *arg); /* Interrupt controls */ @@ -3495,7 +3495,7 @@ static inline void efm32_gint_ipxfrisr(FAR struct efm32_usbhost_s *priv) * ****************************************************************************/ -static int efm32_gint_isr(int irq, FAR void *context) +static int efm32_gint_isr(int irq, FAR void *context, FAR void *arg) { /* At present, there is only support for a single OTG FS host. Hence it is * pre-allocated as g_usbhost. However, in most code, the private data @@ -5374,7 +5374,7 @@ FAR struct usbhost_connection_s *efm32_usbhost_initialize(int controller) /* Attach USB host controller interrupt handler */ - if (irq_attach(EFM32_IRQ_USB, efm32_gint_isr) != 0) + if (irq_attach(EFM32_IRQ_USB, efm32_gint_isr, NULL) != 0) { usbhost_trace1(USBHOST_TRACE1_IRQATTACH, 0); return NULL; diff --git a/arch/arm/src/imx1/imx_serial.c b/arch/arm/src/imx1/imx_serial.c index e3826192b22..ebe996e81b4 100644 --- a/arch/arm/src/imx1/imx_serial.c +++ b/arch/arm/src/imx1/imx_serial.c @@ -112,7 +112,7 @@ static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static inline struct uart_dev_s *up_mapirq(int irq); -static int up_interrupt(int irq, void *context); +static int up_interrupt(int irq, void *context, FAR void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -753,13 +753,13 @@ static int up_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ #if defined(CONFIG_ARCH_CHIP_IMX1) || defined(CONFIG_ARCH_CHIP_IMXL) - ret = irq_attach(priv->rxirq, up_interrupt); + ret = irq_attach(priv->rxirq, up_interrupt, NULL); if (ret < 0) { return ret; } - ret = irq_attach(priv->txirq, up_interrupt); + ret = irq_attach(priv->txirq, up_interrupt, NULL); if (ret < 0) { irq_detach(priv->rxirq); @@ -772,7 +772,7 @@ static int up_attach(struct uart_dev_s *dev) up_enable_irq(priv->txirq); #else - ret = irq_attach(priv->irq, up_interrupt); + ret = irq_attach(priv->irq, up_interrupt, NULL); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -877,7 +877,7 @@ static inline struct uart_dev_s *up_mapirq(int irq) * ****************************************************************************/ -static int up_interrupt(int irq, void *context) +static int up_interrupt(int irq, void *context, FAR void *arg) { struct uart_dev_s *dev; struct up_dev_s *priv; diff --git a/arch/arm/src/imx1/imx_spi.c b/arch/arm/src/imx1/imx_spi.c index d63c65ed2ea..695d6b358f8 100644 --- a/arch/arm/src/imx1/imx_spi.c +++ b/arch/arm/src/imx1/imx_spi.c @@ -165,7 +165,7 @@ static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer, #ifndef CONFIG_SPI_POLLWAIT static inline struct imx_spidev_s *spi_mapirq(int irq); -static int spi_interrupt(int irq, void *context); +static int spi_interrupt(int irq, void *context, FAR void *arg, FAR void *arg); #endif /* SPI methods */ @@ -653,7 +653,7 @@ static inline struct imx_spidev_s *spi_mapirq(int irq) ****************************************************************************/ #ifndef CONFIG_SPI_POLLWAIT -static int spi_interrupt(int irq, void *context) +static int spi_interrupt(int irq, void *context, FAR void *arg, FAR void *arg) { struct imx_spidev_s *priv = spi_mapirq(irq); int ntxd; @@ -1168,7 +1168,7 @@ FAR struct spi_dev_s *imx_spibus_initialize(int port) /* Attach the interrupt */ #ifndef CONFIG_SPI_POLLWAIT - irq_attach(priv->irq, (xcpt_t)spi_interrupt); + irq_attach(priv->irq, (xcpt_t)spi_interrupt, NULL); #endif /* Enable SPI */ diff --git a/arch/arm/src/imx1/imx_timerisr.c b/arch/arm/src/imx1/imx_timerisr.c index c18f72efabd..2b021e08565 100644 --- a/arch/arm/src/imx1/imx_timerisr.c +++ b/arch/arm/src/imx1/imx_timerisr.c @@ -64,7 +64,7 @@ * ****************************************************************************/ -static int imx_timerisr(int irq, uint32_t *regs) +static int imx_timerisr(int irq, uint32_t *regs, FAR void *arg) { uint32_t tstat; int ret = -EIO; @@ -150,7 +150,7 @@ void arm_timer_initialize(void) /* Attach and enable the timer interrupt */ - irq_attach(IMX_IRQ_SYSTIMER, (xcpt_t)imx_timerisr); + irq_attach(IMX_IRQ_SYSTIMER, (xcpt_t)imx_timerisr, NULL); up_enable_irq(IMX_IRQ_SYSTIMER); } diff --git a/arch/arm/src/imx6/imx_ecspi.c b/arch/arm/src/imx6/imx_ecspi.c index 15c602a7c96..01994196817 100644 --- a/arch/arm/src/imx6/imx_ecspi.c +++ b/arch/arm/src/imx6/imx_ecspi.c @@ -186,7 +186,6 @@ struct imx_spidev_s uint8_t spindx; /* SPI index */ #ifndef CONFIG_SPI_POLLWAIT uint8_t irq; /* SPI IRQ number */ - xcpt_t handler; /* ECSPI interrupt handler */ #endif /* Per SPI callouts to board-specific logic */ @@ -223,22 +222,7 @@ static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer, /* Interrupt handling */ #ifndef CONFIG_SPI_POLLWAIT -static int spi_interrupt(struct imx_spidev_s *priv); -#ifdef CONFIG_IMX6_ECSPI1 -static int ecspi1_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_IMX6_ECSPI2 -static int ecspi2_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_IMX6_ECSPI3 -static int ecspi3_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_IMX6_ECSPI4 -static int ecspi4_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_IMX6_ECSPI5 -static int ecspi5_interrupt(int irq, void *context); -#endif +static int spi_interrupt(int irq, void *context, FAR void *arg); #endif /* SPI methods */ @@ -307,7 +291,6 @@ static struct imx_spidev_s g_spidev[] = .spindx = SPI1_NDX, #ifndef CONFIG_SPI_POLLWAIT .irq = IMX_IRQ_ECSPI1, - .handler = ecspi1_interrupt, #endif .select = imx_spi1select, .status = imx_spi1status, @@ -324,7 +307,6 @@ static struct imx_spidev_s g_spidev[] = .spindx = SPI2_NDX, #ifndef CONFIG_SPI_POLLWAIT .irq = IMX_IRQ_ECSPI2, - .handler = ecspi2_interrupt, #endif .select = imx_spi2select, .status = imx_spi2status, @@ -341,7 +323,6 @@ static struct imx_spidev_s g_spidev[] = .spindx = SPI3_NDX, #ifndef CONFIG_SPI_POLLWAIT .irq = IMX_IRQ_ECSPI3, - .handler = ecspi3_interrupt, #endif .select = imx_spi3select, .status = imx_spi3status, @@ -358,7 +339,6 @@ static struct imx_spidev_s g_spidev[] = .spindx = SPI4_NDX, #ifndef CONFIG_SPI_POLLWAIT .irq = IMX_IRQ_ECSPI4, - .handler = ecspi4_interrupt, #endif .select = imx_spi4select, .status = imx_spi4status, @@ -375,7 +355,6 @@ static struct imx_spidev_s g_spidev[] = .spindx = SPI5_NDX, #ifndef CONFIG_SPI_POLLWAIT .irq = IMX_IRQ_ECSPI5, - .handler = ecspi5_interrupt, #endif .select = imx_spi5select, .status = imx_spi5status, @@ -759,8 +738,9 @@ static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer, ****************************************************************************/ #ifndef CONFIG_SPI_POLLWAIT -static int spi_interrupt(struct imx_spidev_s *priv) +static int spi_interrupt(int irq, void *context, FAR void *arg) { + struct imx_spidev_s *priv = (struct imx_spidev_s *)arg; int ntxd; DEBUGASSERT(priv != NULL); @@ -790,57 +770,6 @@ static int spi_interrupt(struct imx_spidev_s *priv) } #endif -/**************************************************************************** - * Name: ecspiN_interrupt, N=1..5 - * - * Description: - * Individual ECPSI interrupt handlers. - * - * Input Parameters: - * Standard interrupt handler inputs - * - * Returned Value: - * 0: success, <0:Negated error number on failure - * - ****************************************************************************/ - -#ifndef CONFIG_SPI_POLLWAIT -#ifdef CONFIG_IMX6_ECSPI1 -static int ecspi1_interrupt(int irq, void *context) -{ - return spi_interrupt(&g_spidev[SPI1_NDX]); -} -#endif - -#ifdef CONFIG_IMX6_ECSPI2 -static int ecspi2_interrupt(int irq, void *context) -{ - return spi_interrupt(&g_spidev[SPI2_NDX]); -} -#endif - -#ifdef CONFIG_IMX6_ECSPI3 -static int ecspi3_interrupt(int irq, void *context) -{ - return spi_interrupt(&g_spidev[SPI3_NDX]); -} -#endif - -#ifdef CONFIG_IMX6_ECSPI4 -static int ecspi4_interrupt(int irq, void *context) -{ - return spi_interrupt(&g_spidev[SPI4_NDX]); -} -#endif - -#ifdef CONFIG_IMX6_ECSPI5 -static int ecspi5_interrupt(int irq, void *context) -{ - return spi_interrupt(&g_spidev[SPI5_NDX]); -} -#endif -#endif - /**************************************************************************** * Name: spi_lock * @@ -1425,7 +1354,7 @@ FAR struct spi_dev_s *imx_spibus_initialize(int port) /* Attach the interrupt */ #ifndef CONFIG_SPI_POLLWAIT - DEBUGVERIFY(irq_attach(priv->irq, priv->handler)); + DEBUGVERIFY(irq_attach(priv->irq, spi_interrupt, priv)); #endif /* Enable SPI */ diff --git a/arch/arm/src/imx6/imx_serial.c b/arch/arm/src/imx6/imx_serial.c index a34d2f988ad..8ae64136b52 100644 --- a/arch/arm/src/imx6/imx_serial.c +++ b/arch/arm/src/imx6/imx_serial.c @@ -199,7 +199,6 @@ struct imx_uart_s { - xcpt_t handler; /* Interrupt handler */ uint32_t uartbase; /* Base address of UART registers */ uint32_t baud; /* Configured baud */ uint32_t ucr1; /* Saved UCR1 value */ @@ -229,24 +228,7 @@ static int imx_setup(struct uart_dev_s *dev); static void imx_shutdown(struct uart_dev_s *dev); static int imx_attach(struct uart_dev_s *dev); static void imx_detach(struct uart_dev_s *dev); - -static int imx_interrupt(struct uart_dev_s *dev); -#ifdef CONFIG_IMX6_UART1 -static int imx_uart1_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_IMX6_UART2 -static int imx_uart2_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_IMX6_UART3 -static int imx_uart3_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_IMX6_UART4 -static int imx_uart4_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_IMX6_UART5 -static int imx_uart5_interrupt(int irq, void *context); -#endif - +static int imx_interrupt(int irq, void *context, FAR void *arg); static int imx_ioctl(struct file *filep, int cmd, unsigned long arg); static int imx_receive(struct uart_dev_s *dev, uint32_t *status); static void imx_rxint(struct uart_dev_s *dev, bool enable); @@ -317,7 +299,6 @@ static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; #ifdef CONFIG_IMX6_UART1 static struct imx_uart_s g_uart1priv = { - .handler = imx_uart1_interrupt, .uartbase = IMX_UART1_VBASE, .baud = CONFIG_UART1_BAUD, .irq = IMX_IRQ_UART1, @@ -348,7 +329,6 @@ static struct uart_dev_s g_uart1port = #ifdef CONFIG_IMX6_UART2 static struct imx_uart_s g_uart2priv = { - .handler = imx_uart2_interrupt, .uartbase = IMX_UART2_VBASE, .baud = CONFIG_UART2_BAUD, .irq = IMX_IRQ_UART2, @@ -377,7 +357,6 @@ static struct uart_dev_s g_uart2port = #ifdef CONFIG_IMX6_UART3 static struct imx_uart_s g_uart3priv = { - .handler = imx_uart3_interrupt, .uartbase = IMX_UART3_REGISTER_BASE, .baud = IMX_UART3_VBASE, .irq = IMX_IRQ_UART3, @@ -406,7 +385,6 @@ static struct uart_dev_s g_uart3port = #ifdef CONFIG_IMX6_UART4 static struct imx_uart_s g_uart4priv = { - .handler = imx_uart4_interrupt, .uartbase = IMX_UART4_REGISTER_BASE, .baud = IMX_UART4_VBASE, .irq = IMX_IRQ_UART4, @@ -435,7 +413,6 @@ static struct uart_dev_s g_uart4port = #ifdef CONFIG_IMX6_UART5 static struct imx_uart_s g_uart5priv = { - .handler = imx_uart5_interrupt, .uartbase = IMX_UART5_REGISTER_BASE, .baud = IMX_UART5_VBASE, .irq = IMX_IRQ_UART5, @@ -618,7 +595,7 @@ static int imx_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, priv->handler); + ret = irq_attach(priv->irq, imx_interrupt, priv); if (ret == OK) { /* Configure as a (high) level interrupt */ @@ -663,12 +640,16 @@ static void imx_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int imx_interrupt(struct uart_dev_s *dev) +static int imx_interrupt(int irq, void *context, FAR void *arg) { - struct imx_uart_s *priv = (struct imx_uart_s *)dev->priv; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct imx_uart_s *priv; uint32_t usr1; int passes = 0; + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct imx_uart_s *)dev->priv; + /* Loop until there are no characters to be transferred or, * until we have been looping for a long time. */ @@ -710,46 +691,6 @@ static int imx_interrupt(struct uart_dev_s *dev) } } -/**************************************************************************** - * Name: imx_uart[n]_interrupt - * - * Description: - * UART-specific interrupt handlers just transfer control to the common - * UART interrupt handler, passing the relevant driver state structure. - * - ****************************************************************************/ - -#ifdef CONFIG_IMX6_UART1 -static int imx_uart1_interrupt(int irq, void *context) -{ - return imx_interrupt(&g_uart1port); -} -#endif -#ifdef CONFIG_IMX6_UART2 -static int imx_uart2_interrupt(int irq, void *context) -{ - return imx_interrupt(&g_uart2port); -} -#endif -#ifdef CONFIG_IMX6_UART3 -static int imx_uart3_interrupt(int irq, void *context) -{ - return imx_interrupt(&g_uart3port); -} -#endif -#ifdef CONFIG_IMX6_UART4 -static int imx_uart4_interrupt(int irq, void *context) -{ - return imx_interrupt(&g_uart4port); -} -#endif -#ifdef CONFIG_IMX6_UART5 -static int imx_uart5_interrupt(int irq, void *context) -{ - return imx_interrupt(&g_uart5port); -} -#endif - /**************************************************************************** * Name: imx_ioctl * diff --git a/arch/arm/src/imx6/imx_timerisr.c b/arch/arm/src/imx6/imx_timerisr.c index dbfc878eb89..36cd8cced00 100644 --- a/arch/arm/src/imx6/imx_timerisr.c +++ b/arch/arm/src/imx6/imx_timerisr.c @@ -130,7 +130,7 @@ static void imx_output_compare(uint32_t sr, uint32_t of) * ****************************************************************************/ -static int imx_timerisr(int irq, uint32_t *regs) +static int imx_timerisr(int irq, uint32_t *regs, FAR void *arg) { /* Sample the SR (once) */ @@ -260,7 +260,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(IMX_IRQ_GPT, (xcpt_t)imx_timerisr); + (void)irq_attach(IMX_IRQ_GPT, (xcpt_t)imx_timerisr, NULL); /* Enable all three GPT output compare interrupts */ diff --git a/arch/arm/src/kinetis/Kconfig b/arch/arm/src/kinetis/Kconfig index 04d0df453be..271921a9ef6 100644 --- a/arch/arm/src/kinetis/Kconfig +++ b/arch/arm/src/kinetis/Kconfig @@ -220,27 +220,60 @@ config ARCH_CHIP_MK66FN2M0VLQ18 endchoice +# These "hidden" settings determine is a peripheral option is available for +# the selection MCU + +config KINETIS_HAVE_UART5 + bool + default n + +config KINETIS_HAVE_LPUART0 + bool + default n + +config KINETIS_HAVE_LPUART1 + bool + default n + +# When there are multiple instances of a device, these "hidden" settings +# will automatically be selected and will represent the 'OR' of the +# instances selected. + +config KINETIS_LPUART + bool + default n + +config KINETIS_UART + bool + default n + select MCU_SERIAL + # Chip families config ARCH_FAMILY_K20 bool default n + select KINETIS_HAVE_UART5 config ARCH_FAMILY_K40 bool default n + select KINETIS_HAVE_UART5 config ARCH_FAMILY_K60 bool default n + select KINETIS_HAVE_UART5 config ARCH_FAMILY_K64 bool default n + select KINETIS_HAVE_UART5 config ARCH_FAMILY_K66 bool default n + select KINETIS_HAVE_LPUART0 menu "Kinetis Peripheral Support" @@ -280,6 +313,7 @@ config KINETIS_UART0 bool "UART0" default n select UART0_SERIALDRIVER + select KINETIS_UART ---help--- Support UART0 @@ -287,6 +321,7 @@ config KINETIS_UART1 bool "UART1" default n select UART1_SERIALDRIVER + select KINETIS_UART ---help--- Support UART1 @@ -294,6 +329,7 @@ config KINETIS_UART2 bool "UART2" default n select UART2_SERIALDRIVER + select KINETIS_UART ---help--- Support UART2 @@ -301,6 +337,7 @@ config KINETIS_UART3 bool "UART3" default n select UART3_SERIALDRIVER + select KINETIS_UART ---help--- Support UART3 @@ -308,16 +345,37 @@ config KINETIS_UART4 bool "UART4" default n select UART4_SERIALDRIVER + select KINETIS_UART ---help--- Support UART4 config KINETIS_UART5 bool "UART5" default n + depends on KINETIS_HAVE_UART5 select UART5_SERIALDRIVER + select KINETIS_UART ---help--- Support UART5 +config KINETIS_LPUART0 + bool "Low power LPUART0" + default n + depends on KINETIS_HAVE_LPUART0 + select OTHER_UART_SERIALDRIVER + select KINETIS_LPUART + ---help--- + Support the low power UART0 + +config KINETIS_LPUART1 + bool "Low power LPUART1" + default n + depends on KINETIS_HAVE_LPUART1 + select OTHER_UART_SERIALDRIVER + select KINETIS_LPUART + ---help--- + Support the low power UART1 + config KINETIS_ENET bool "Ethernet" default n @@ -574,10 +632,11 @@ config KINETIS_FTM0_PWM ---help--- Reserve timer 0 for use by PWM - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If KINETIS_FTM0 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. + Timer devices may be used for different purposes. One special + purpose is to generate modulated outputs for such things as motor + control. If KINETIS_FTM0 is defined then THIS following may also be + defined to indicate that the timer is intended to be used for pulsed + output modulation. config KINETIS_FTM0_CHANNEL int "FTM0 PWM Output Channel" @@ -839,6 +898,10 @@ config KINETIS_SD4BIT_FREQ endif endmenu # Kinetis SDHC Configuration +# +# MCU serial peripheral driver? +# + menu "Kinetis UART Configuration" config KINETIS_UARTFIFOS @@ -847,3 +910,179 @@ config KINETIS_UARTFIFOS depends on KINETIS_UART0 endmenu # Kinetis UART Configuration + +menu "Kinetis LPUART0 Configuration" + depends on KINETIS_LPUART0 + +config LPUART0_RXBUFSIZE + int "Receive buffer size" + default 256 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. + +config LPUART0_TXBUFSIZE + int "Transmit buffer size" + default 256 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. + +config LPUART0_BAUD + int "BAUD rate" + default 115200 + ---help--- + The configured BAUD of the UART. + +config LPUART0_BITS + int "Character size" + default 8 + ---help--- + The number of bits. Must be either 7 or 8. + +config LPUART0_PARITY + int "Parity setting" + range 0 2 + default 0 + ---help--- + 0=no parity, 1=odd parity, 2=even parity + +config LPUART0_2STOP + int "use 2 stop bits" + default 0 + ---help--- + 1=Two stop bits + +config LPUART0_IFLOWCONTROL + bool "LPUART0 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable LPUART0 RTS flow control + +config LPUART0_OFLOWCONTROL + bool "LPUART0 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable LPUART0 CTS flow control + +config LPUART0_DMA + bool "LPUART0 DMA support" + default n + select SERIAL_DMA + ---help--- + Enable DMA transfers on LPUART0 + +endmenu # Kinetis LPUART0 Configuration + +menu "Kinetis LPUART1 Configuration" + depends on KINETIS_LPUART1 + +config LPUART1_RXBUFSIZE + int "Receive buffer size" + default 256 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. + +config LPUART1_TXBUFSIZE + int "Transmit buffer size" + default 256 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. + +config LPUART1_BAUD + int "BAUD rate" + default 115200 + ---help--- + The configured BAUD of the UART. + +config LPUART1_BITS + int "Character size" + default 8 + ---help--- + The number of bits. Must be either 7 or 8. + +config LPUART1_PARITY + int "Parity setting" + range 0 2 + default 0 + ---help--- + 0=no parity, 1=odd parity, 2=even parity + +config LPUART1_2STOP + int "use 2 stop bits" + default 0 + ---help--- + 1=Two stop bits + +config LPUART1_IFLOWCONTROL + bool "LPUART1 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable LPUART1 RTS flow control + +config LPUART1_OFLOWCONTROL + bool "LPUART1 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable LPUART1 CTS flow control + +config LPUART1_DMA + bool "LPUART1 DMA support" + default n + select SERIAL_DMA + ---help--- + Enable DMA transfers on LPUART1 + +endmenu # Kinetis LPUART1 Configuration + +choice + prompt "Kinetis LPUART Serial Console" + default NO_LPUART_SERIAL_CONSOLE + depends on DEV_CONSOLE && KINETIS_LPUART + +config LPUART0_SERIAL_CONSOLE + bool "Use LPUART0 as the serial console" + depends on KINETIS_LPUART0 + select OTHER_SERIAL_CONSOLE + ---help--- + Use the LPUART0 device as the serial console + +config LPUART1_SERIAL_CONSOLE + bool "Use LPUART1 as the serial console" + depends on KINETIS_LPUART1 + select OTHER_SERIAL_CONSOLE + ---help--- + Use the LPUART1 device as the serial console + +config NO_LPUART_SERIAL_CONSOLE + bool "No LPUART serial console" + ---help--- + No serial LPUART based console OR some other serial device provides + the serial console + +endchoice # Kinetis LPUART Serial Console + +config KINETIS_MERGE_TTY + bool "Kinetis Merge TTY names for LPUARTS" + default n + depends on KINETIS_LPUART + ---help--- + Enable the merging of the TTY names when both LPUARTs and UARTs + are defined. When enabled, all both LPUARTS and UART types will be + listed as dev/ttySn. When disabled, LPUARTS willbe listed as + /dev/ttyLPn and UARTs as /dev/ttySn see also (KINETS_LPUART_LOWEST) + +config KINETS_LPUART_LOWEST + bool "Kinetis Order ttySn LPUARTs before UARTS" + default n + depends on KINETIS_LPUART && KINETIS_UART + depends on KINETIS_MERGE_TTY + ---help--- + Used with KINETIS_MERGE_TTY, will set the order of ttySn assignments + Enabled will order the LPUART's before the UARTS. diff --git a/arch/arm/src/kinetis/Make.defs b/arch/arm/src/kinetis/Make.defs index bd4eed06484..6ee494c6526 100644 --- a/arch/arm/src/kinetis/Make.defs +++ b/arch/arm/src/kinetis/Make.defs @@ -113,7 +113,8 @@ CHIP_ASRCS = CHIP_CSRCS = kinetis_allocateheap.c kinetis_clockconfig.c CHIP_CSRCS += kinetis_clrpend.c kinetis_idle.c kinetis_irq.c CHIP_CSRCS += kinetis_lowputc.c kinetis_pin.c kinetis_pingpio.c -CHIP_CSRCS += kinetis_serial.c kinetis_start.c kinetis_uid.c kinetis_wdog.c +CHIP_CSRCS += kinetis_serialinit.c kinetis_serial.c +CHIP_CSRCS += kinetis_start.c kinetis_uid.c kinetis_wdog.c CHIP_CSRCS += kinetis_cfmconfig.c # Configuration-dependent Kinetis files @@ -162,6 +163,10 @@ ifeq ($(CONFIG_I2C),y) CHIP_CSRCS += kinetis_i2c.c endif +ifeq ($(CONFIG_KINETIS_LPUART),y) +CHIP_CSRCS += kinetis_lpserial.c +endif + ifeq ($(CONFIG_RTC),y) CHIP_CSRCS += kinetis_rtc.c ifeq ($(CONFIG_RTC_DRIVER),y) diff --git a/arch/arm/src/kinetis/chip/kinetis_llwu.h b/arch/arm/src/kinetis/chip/kinetis_llwu.h index ae5c6c8b04c..c4abaa74ddf 100644 --- a/arch/arm/src/kinetis/chip/kinetis_llwu.h +++ b/arch/arm/src/kinetis/chip/kinetis_llwu.h @@ -232,7 +232,9 @@ /* LLWU Control and Status Register */ -#define LLWU_CS_ACKISO (1 << 7) /* Bit 7: Acknowledge Isolation */ +#if !defined(KINETIS_PMC_HAS_REGSC_ACKISO) +# define LLWU_CS_ACKISO (1 << 7) /* Bit 7: Acknowledge Isolation */ +#endif /* Bits 2-6: Reserved */ #define LLWU_CS_FLTEP (1 << 1) /* Bit 1: Digital Filter on External Pin */ #define LLWU_CS_FLTR (1 << 0) /* Bit 0: Digital Filter on RESET Pin */ diff --git a/arch/arm/src/kinetis/chip/kinetis_lpuart.h b/arch/arm/src/kinetis/chip/kinetis_lpuart.h new file mode 100644 index 00000000000..eafd18f122c --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_lpuart.h @@ -0,0 +1,222 @@ +/**************************************************************************************************** + * arch/arm/src/kinetis/chip/kinetis_lpuart.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LPUART_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LPUART_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define KINETIS_LPUART_BAUD_OFFSET 0x0000 /* Low Power UART Baud Rate Register */ +#define KINETIS_LPUART_STAT_OFFSET 0x0004 /* Low Power UART Status Register */ +#define KINETIS_LPUART_CTRL_OFFSET 0x0008 /* Low Power UART Control Register */ +#define KINETIS_LPUART_DATA_OFFSET 0x000c /* Low Power UART Data Register */ +#define KINETIS_LPUART_MATCH_OFFSET 0x000c /* Low Power UART Match Address Register */ +#define KINETIS_LPUART_MODIR_OFFSET 0x000c /* Low Power UART Modem IrDA Register */ + +/* Register Addresses *******************************************************************************/ + +#define KINETIS_LPUART0_BAUD (KINETIS_LPUART0_BASE+KINETIS_LPUART_BAUD_OFFSET) +#define KINETIS_LPUART0_STAT (KINETIS_LPUART0_BASE+KINETIS_LPUART_STAT_OFFSET) +#define KINETIS_LPUART0_CTRL (KINETIS_LPUART0_BASE+KINETIS_LPUART_CTRL_OFFSET) +#define KINETIS_LPUART0_DATA (KINETIS_LPUART0_BASE+KINETIS_LPUART_DATA_OFFSET) +#define KINETIS_LPUART0_MATCH (KINETIS_LPUART0_BASE+KINETIS_LPUART_MATCH_OFFSET) +#define KINETIS_LPUART0_MODIR (KINETIS_LPUART0_BASE+KINETIS_LPUART_MODIR_OFFSET) + +/* Register Bit Definitions *************************************************************************/ + +/* Low Power UART Baud Rate Register */ + +#define LPUART_BAUD_SBR_SHIFT (0) /* Bits 0-12: Baud Rate Modulo Divisor */ +#define LPUART_BAUD_SBR_MASK (0x1fff << LPUART_BAUD_SBR_SHIFT) +# define LPUART_BAUD_SBR(n) (((n) & 0x1fff) << LPUART_BAUD_SBR_SHIFT) /* n= 1..8191*/ +#define LPUART_BAUD_SBNS (1 << 13) /* Bit 13: Stop Bit Number Select */ +#define LPUART_BAUD_RXEDGIE (1 << 14) /* Bit 14: RX Input Active Edge Interrupt Enable */ +#define LPUART_BAUD_LBKDIE (1 << 15) /* Bit 15: LIN Break Detect Interrupt Enable */ +#define LPUART_BAUD_RESYNCDIS (1 << 16) /* Bit 16: Resynchronizations Disable */ +#define LPUART_BAUD_BOTHEDGE (1 << 17) /* Bit 17: Both Edge Sampling */ +#define LPUART_BAUD_MATCFG_SHIFT (18) /* Bits 18-19: Match Configuration */ +#define LPUART_BAUD_MATCFG_MASK (3 << LPUART_BAUD_MATCFG_SHIFT) +# define LPUART_BAUD_MATCFG_AMW (0 << LPUART_BAUD_MATCFG_SHIFT) /* Address Match Wakeup */ +# define LPUART_BAUD_MATCFG_IMW (1 << LPUART_BAUD_MATCFG_SHIFT) /* Idle Match Wakeup */ +# define LPUART_BAUD_MATCFG_MONOFF (2 << LPUART_BAUD_MATCFG_SHIFT) /* Match On and Match Off */ +# define LPUART_BAUD_MATCFG_RWU (3 << LPUART_BAUD_MATCFG_SHIFT) /* Enables RWU on Data Match and Match On/Off for transmitter CTS input */ + /* Bit 20: Reserved */ +#define LPUART_BAUD_RDMAE (1 << 21) /* Bit 21: Receiver Full DMA Enable */ + /* Bit 22: Reserved */ +#define LPUART_BAUD_TDMAE (1 << 23) /* Bit 23: Transmitter DMA Enable */ +#define LPUART_BAUD_OSR_SHIFT (24) /* Bits 24-28: Over Sampling Ratio */ +#define LPUART_BAUD_OSR_MASK (0x1f << LPUART_BAUD_OSR_SHIFT) +#define LPUART_BAUD_OSR(n) ((((n)-1) & 0x1f) << LPUART_BAUD_OSR_SHIFT) /* n=4..32 */ +#define LPUART_BAUD_M10 (1 << 29) /* Bit 29: 10-bit Mode select */ +#define LPUART_BAUD_MAEN2 (1 << 30) /* Bit 30: Match Address Mode Enable 2 */ +#define LPUART_BAUD_MAEN1 (1 << 31) /* Bit 31: Match Address Mode Enable 1 */ + +/* Low Power UART Status Register */ + + /* Bits 0-13: Reserved */ +#define LPUART_STAT_MA2F (1 << 14) /* Match 2 Flag */ +#define LPUART_STAT_MA1F (1 << 15) /* Match 1 Flag */ +#define LPUART_STAT_PF (1 << 16) /* Parity Error Flag */ +#define LPUART_STAT_FE (1 << 17) /* Framing Error Flag */ +#define LPUART_STAT_NF (1 << 18) /* Noise Flag */ +#define LPUART_STAT_OR (1 << 19) /* Receiver Overrun Flag */ +#define LPUART_STAT_IDLE (1 << 20) /* Idle Line Flag */ +#define LPUART_STAT_RDRF (1 << 21) /* Receive Data Register Full Flag */ +#define LPUART_STAT_TC (1 << 22) /* Transmission Complete Flag */ +#define LPUART_STAT_TDRE (1 << 23) /* Transmit Data Register Empty Flag */ +#define LPUART_STAT_RAF (1 << 24) /* Receiver Active Flag */ +#define LPUART_STAT_LBKDE (1 << 25) /* LIN Break Detection Enable */ +#define LPUART_STAT_BRK13 (1 << 26) /* Break Character Generation Length */ +#define LPUART_STAT_RWUID (1 << 27) /* Receive Wake Up Idle Detect */ +#define LPUART_STAT_RXINV (1 << 28) /* Receive Data Inversion */ +#define LPUART_STAT_MSBF (1 << 29) /* MSB First */ +#define LPUART_STAT_RXEDGIF (1 << 30) /* LPUART_RX Pin Active Edge Interrupt Flag */ +#define LPUART_STAT_LBKDIF (1 << 31) /* LIN Break Detect Interrupt Flag */ + +/* Low Power UART Control Register */ + +#define LPUART_CTRL_PT (1 << 0) /* Bit 0: Parity Type */ +#define LPUART_CTRL_PE (1 << 1) /* Bit 1: Parity Enable */ +#define LPUART_CTRL_ILT (1 << 2) /* Bit 2: Idle Line Type Select */ +#define LPUART_CTRL_WAKE (1 << 3) /* Bit 3: Receiver Wakeup Method Select */ +#define LPUART_CTRL_M (1 << 4) /* Bit 4: 9-Bit or 8-Bit Mode Select */ +#define LPUART_CTRL_RSRC (1 << 5) /* Bit 5: Receiver Source Select */ +#define LPUART_CTRL_DOZEEN (1 << 6) /* Bit 6: Doze Enable */ +#define LPUART_CTRL_LOOPS (1 << 7) /* Bit 7: Loop Mode Select */ +#define LPUART_CTRL_IDLECFG_SHIFT (8) /* Bits 8-10: Idle Configuration */ +#define LPUART_CTRL_IDLECFG_MASK (3 << LPUART_CTRL_IDLECFG_SHIFT) +# define LPUART_CTRL_IDLECFG_1 (0 << LPUART_CTRL_IDLECFG_SHIFT) /* 1 idle character */ +# define LPUART_CTRL_IDLECFG_2 (1 << LPUART_CTRL_IDLECFG_SHIFT) /* 2 idle characters */ +# define LPUART_CTRL_IDLECFG_4 (2 << LPUART_CTRL_IDLECFG_SHIFT) /* 4 idle characters */ +# define LPUART_CTRL_IDLECFG_8 (3 << LPUART_CTRL_IDLECFG_SHIFT) /* 8 idle characters */ +# define LPUART_CTRL_IDLECFG_16 (4 << LPUART_CTRL_IDLECFG_SHIFT) /* 16 idle characters */ +# define LPUART_CTRL_IDLECFG_32 (5 << LPUART_CTRL_IDLECFG_SHIFT) /* 32 idle characters */ +# define LPUART_CTRL_IDLECFG_64 (6 << LPUART_CTRL_IDLECFG_SHIFT) /* 64 idle characters */ +# define LPUART_CTRL_IDLECFG_128 (7 << LPUART_CTRL_IDLECFG_SHIFT) /* 128 idle characters */ + /* Bits 11-13: Reserved */ +#define LPUART_CTRL_MA2IE (1 << 14) /* Bit 14: Match 2 Interrupt Enable */ +#define LPUART_CTRL_MA1IE (1 << 15) /* Bit 15: Match 1 Interrupt Enable */ +#define LPUART_CTRL_SBK (1 << 16) /* Bit 16: Send Break */ +#define LPUART_CTRL_RWU (1 << 17) /* Bit 17: Receiver Wakeup Control */ +#define LPUART_CTRL_RE (1 << 18) /* Bit 18: Receiver Enable */ +#define LPUART_CTRL_TE (1 << 19) /* Bit 19: Transmitter Enable */ +#define LPUART_CTRL_ILIE (1 << 20) /* Bit 20: Idle Line Interrupt Enable */ +#define LPUART_CTRL_RIE (1 << 21) /* Bit 21: Receiver Interrupt Enable */ +#define LPUART_CTRL_TCIE (1 << 22) /* Bit 22: Transmission Complete Interrupt Enable for */ +#define LPUART_CTRL_TIE (1 << 23) /* Bit 23: Transmit Interrupt Enable */ +#define LPUART_CTRL_PEIE (1 << 24) /* Bit 24: Parity Error Interrupt Enable */ +#define LPUART_CTRL_FEIE (1 << 25) /* Bit 25: Framing Error Interrupt Enable */ +#define LPUART_CTRL_NEIE (1 << 26) /* Bit 26: Noise Error Interrupt Enable */ +#define LPUART_CTRL_ORIE (1 << 27) /* Bit 27: Overrun Interrupt Enable */ +#define LPUART_CTRL_TXINV (1 << 28) /* Bit 28: Transmit Data Inversion */ +#define LPUART_CTRL_TXDIR (1 << 29) /* Bit 29: LPUART_TX Pin Direction in Single-Wire Mode */ +#define LPUART_CTRL_R9T8 (1 << 30) /* Bit 30: Receive Bit 9 / Transmit Bit 8 */ +#define LPUART_CTRL_R8T9 (1 << 31) /* Bit 31: Receive Bit 8 / Transmit Bit 9 */ + +/* Low Power UART Data Register */ + +#define LPUART_DATA_SHIFT (0) /* Bits 0-9: Read receive/ write transmit data */ +#define LPUART_DATA_MASK (0x3ff << LPUART_DATA_SHIFT) +#define LPUART_DATA8(n) (((n) & 0xff) << LPUART_DATA_SHIFT) +#define LPUART_DATA9(n) (((n) & 0x1ff) << LPUART_DATA_SHIFT) +#define LPUART_DATA10(n) (((n) & 0x3ff) << LPUART_DATA_SHIFT) +#define LPUART_DATA_R0T0 (1 << 0) /* Bit 0: Read receive data buffer 0 or write transmit data buffer 0 */ +#define LPUART_DATA_R1T1 (1 << 1) /* Bit 1: Read receive data buffer 1 or write transmit data buffer 1 */ +#define LPUART_DATA_R2T2 (1 << 2) /* Bit 2: Read receive data buffer 2 or write transmit data buffer 2 */ +#define LPUART_DATA_R3T3 (1 << 3) /* Bit 3: Read receive data buffer 3 or write transmit data buffer 3 */ +#define LPUART_DATA_R4T4 (1 << 4) /* Bit 4: Read receive data buffer 4 or write transmit data buffer 4 */ +#define LPUART_DATA_R5T5 (1 << 5) /* Bit 5: Read receive data buffer 5 or write transmit data buffer 5 */ +#define LPUART_DATA_R6T6 (1 << 6) /* Bit 6: Read receive data buffer 6 or write transmit data buffer 6 */ +#define LPUART_DATA_R7T7 (1 << 7) /* Bit 7: Read receive data buffer 7 or write transmit data buffer 7 */ +#define LPUART_DATA_R8T8 (1 << 8) /* Bit 8: Read receive data buffer 8 or write transmit data buffer 8 */ +#define LPUART_DATA_R9T9 (1 << 9) /* Bit 9: Read receive data buffer 9 or write transmit data buffer 9 */ + /* Bit 10: Reserved */ +#define LPUART_DATA_IDLINE (1 << 11) /* Bit 11: Idle Line */ +#define LPUART_DATA_RXEMPT (1 << 12) /* Bit 12: Receive Buffer Empty */ +#define LPUART_DATA_FRETSC (1 << 13) /* Bit 13: Frame Error / Transmit Special Character */ +#define LPUART_DATA_PARITYE (1 << 14) /* Bit 14: The current received dataword contained in DATA[R9:R0] was received with a parity error */ +#define LPUART_DATA_NOISY (1 << 15) /* Bit 15: The current received dataword contained in DATA[R9:R0] was received with noise */ + /* Bits 16-31: This field is reserved */ + +/* Low Power UART Match Address Register */ + +#define LPUART_MATCH_MA1_SHIFT (0) /* Bits 0-9: Match Address 1 */ +#define LPUART_MATCH_MA1_MASK (0x3ff << LPUART_MATCH_MA1_SHIFT) + /* Bits 10-15: Reserved */ +#define LPUART_MATCH_MA2_SHIFT (16) /* Bits 16-25: Match Address 2 */ +#define LPUART_MATCH_MA2_MASK (0x3ff << LPUART_MATCH_MA2_SHIFT) + /* Bits 26-31: Reserved */ + +/* Low Power UART Modem IrDA Register */ + +#define LPUART_MODIR_TXCTSE (1 << 0) /* Bit 0: Transmitter clear-to-send enable */ +#define LPUART_MODIR_TXRTSE (1 << 1) /* Bit 1: Transmitter request-to-send enable */ +#define LPUART_MODIR_TXRTSPOL (1 << 2) /* Bit 2: Transmitter request-to-send polarity */ +#define LPUART_MODIR_RXRTSE (1 << 3) /* Bit 3: Receiver request-to-send enable */ +#define LPUART_MODIR_TXCTSC (1 << 4) /* Bit 4: Transmit CTS Configuration */ +#define LPUART_MODIR_TXCTSSRC (1 << 5) /* Bit 5: Transmit CTS Source */ + /* Bits 6-15: Reserved */ +#define LPUART_MODIR_TNP_SHIFT (16) /* Bits 16-17: Transmitter narrow pulse */ +#define LPUART_MODIR_TNP_MASK (3 << LPUART_MODIR_TNP_SHIFT) +# define LPUART_MODIR_TNP(n) (((n)-1) << LPUART_MODIR_TNP_SHIFT) /* n=1-4 */ +#define LPUART_MODIR_IREN (1 << 18) /* Bit 18: Infrared enable */ + /* Bits 19-31: Reserved */ + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Functions + ****************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LPUART_H */ diff --git a/arch/arm/src/kinetis/chip/kinetis_pmc.h b/arch/arm/src/kinetis/chip/kinetis_pmc.h index c0ffe575b36..be346bf67fe 100644 --- a/arch/arm/src/kinetis/chip/kinetis_pmc.h +++ b/arch/arm/src/kinetis/chip/kinetis_pmc.h @@ -78,22 +78,33 @@ #define PMC_LVDSC2_LVWV_SHIFT (0) /* Bits 0-1: Low-Voltage Warning Voltage Select */ #define PMC_LVDSC2_LVWV_MASK (3 << PMC_LVDSC2_LVWV_SHIFT) -# define PMC_LVDSC2_LVWV_ LOW (0 << PMC_LVDSC2_LVWV_SHIFT) /* Low trip point selected (VLVW = VLVW1H/L) */ -# define PMC_LVDSC2_LVWV_ MID1 (1 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 1 trip point selected (VLVW = VLVW2H/L) */ -# define PMC_LVDSC2_LVWV_ MID2 (2 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 2 trip point selected (VLVW = VLVW3H/L) */ -# define PMC_LVDSC2_LVWV_ HIGH (3 << PMC_LVDSC2_LVWV_SHIFT) /* High trip point selected (VLVW = VLVW4H/L) */ +# define PMC_LVDSC2_LVWV_LOW (0 << PMC_LVDSC2_LVWV_SHIFT) /* Low trip point selected (VLVW = VLVW1H/L) */ +# define PMC_LVDSC2_LVWV_MID1 (1 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 1 trip point selected (VLVW = VLVW2H/L) */ +# define PMC_LVDSC2_LVWV_MID2 (2 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 2 trip point selected (VLVW = VLVW3H/L) */ +# define PMC_LVDSC2_LVWV_HIGH (3 << PMC_LVDSC2_LVWV_SHIFT) /* High trip point selected (VLVW = VLVW4H/L) */ /* Bits 2-4: Reserved */ #define PMC_LVDSC2_LVWIE (1 << 5) /* Bit 5: Low-Voltage Warning Interrupt Enable */ #define PMC_LVDSC2_LVWACK (1 << 6) /* Bit 6: Low-Voltage Warning Acknowledge */ #define PMC_LVDSC2_LVWF (1 << 7) /* Bit 7: Low-Voltage Warning Flag */ /* Regulator Status and Control Register */ - #define PMC_REGSC_BGBE (1 << 0) /* Bit 0: Bandgap Buffer Enable */ /* Bit 1: Reserved */ -#define PMC_REGSC_REGONS (1 << 2) /* Bit 2: Regulator in Run Regulation Status */ -#define PMC_REGSC_VLPRS (1 << 3) /* Bit 3: Very Low Power Run Status */ -#define PMC_REGSC_TRAMPO (1 << 4) /* Bit 4: For devices with FlexNVM: Traditional RAM Power Option */ +#if defined(KINETIS_PMC_HAS_REGSC_REGONS) +# define PMC_REGSC_REGONS (1 << 2) /* Bit 2: Regulator in Run Regulation Status */ +#endif +#if defined(KINETIS_PMC_HAS_REGSC_ACKISO) +# define PMC_REGSC_ACKISO (1 << 3) /* Bit 3: Acknowledge Isolation */ +#endif +#if defined(KINETIS_PMC_HAS_REGSC_VLPRS) +# define PMC_REGSC_VLPRS (1 << 3) /* Bit 3: Very Low Power Run Status */ +#endif +#if defined(KINETIS_PMC_HAS_REGSC_BGEN) +# define PMC_REGSC_BGEN (1 << 4) /* Bit 4: Bandgap Enable In VLPx Operation */ +#endif +#if defined(KINETIS_PMC_HAS_REGSC_TRAMPO) +# define PMC_REGSC_TRAMPO (1 << 4) /* Bit 4: For devices with FlexNVM: Traditional RAM Power Option */ +#endif /* Bits 5-7: Reserved */ /************************************************************************************ diff --git a/arch/arm/src/kinetis/chip/kinetis_sim.h b/arch/arm/src/kinetis/chip/kinetis_sim.h index 4898c589604..3e6cb6a6efb 100644 --- a/arch/arm/src/kinetis/chip/kinetis_sim.h +++ b/arch/arm/src/kinetis/chip/kinetis_sim.h @@ -51,513 +51,1264 @@ /* Register Offsets *****************************************************************/ -#define KINETIS_SIM_SOPT1_OFFSET 0x0000 /* System Options Register 1 */ -#define KINETIS_SIM_SOPT2_OFFSET 0x0004 /* System Options Register 2 */ -#define KINETIS_SIM_SOPT4_OFFSET 0x000c /* System Options Register 4 */ -#define KINETIS_SIM_SOPT5_OFFSET 0x0010 /* System Options Register 5 */ -#define KINETIS_SIM_SOPT6_OFFSET 0x0014 /* System Options Register 6 */ -#define KINETIS_SIM_SOPT7_OFFSET 0x0018 /* System Options Register 7 */ -#define KINETIS_SIM_SDID_OFFSET 0x0024 /* System Device Identification Register */ -#define KINETIS_SIM_SCGC1_OFFSET 0x0028 /* System Clock Gating Control Register 1 */ -#define KINETIS_SIM_SCGC2_OFFSET 0x002c /* System Clock Gating Control Register 2 */ -#define KINETIS_SIM_SCGC3_OFFSET 0x0030 /* System Clock Gating Control Register 3 */ -#define KINETIS_SIM_SCGC4_OFFSET 0x0034 /* System Clock Gating Control Register 4 */ -#define KINETIS_SIM_SCGC5_OFFSET 0x0038 /* System Clock Gating Control Register 5 */ -#define KINETIS_SIM_SCGC6_OFFSET 0x003c /* System Clock Gating Control Register 6 */ -#define KINETIS_SIM_SCGC7_OFFSET 0x0040 /* System Clock Gating Control Register 7 */ -#define KINETIS_SIM_CLKDIV1_OFFSET 0x0044 /* System Clock Divider Register 1 */ -#define KINETIS_SIM_CLKDIV2_OFFSET 0x0048 /* System Clock Divider Register 2 */ -#define KINETIS_SIM_FCFG1_OFFSET 0x004c /* Flash Configuration Register 1 */ -#define KINETIS_SIM_FCFG2_OFFSET 0x0050 /* Flash Configuration Register 2 */ -#define KINETIS_SIM_UIDH_OFFSET 0x0054 /* Unique Identification Register High */ -#define KINETIS_SIM_UIDMH_OFFSET 0x0058 /* Unique Identification Register Mid-High */ -#define KINETIS_SIM_UIDML_OFFSET 0x005c /* Unique Identification Register Mid Low */ -#define KINETIS_SIM_UIDL_OFFSET 0x0060 /* Unique Identification Register Low */ +#define KINETIS_SIM_SOPT1_OFFSET 0x0000 /* System Options Register 1 */ +#if defined (KINETIS_SIM_HAS_SOPT1CFG) +# define KINETIS_SIM_SOPT1CFG_OFFSET 0x0004 /* SOPT1 Configuration Register */ +#endif +#if defined(KINETIS_SIM_HAS_USBPHYCTL) +# define KINETIS_SIM_USBPHYCTL_OFFSET 0x0008 /* USB PHY Control Register */ +#endif +#define KINETIS_SIM_SOPT2_OFFSET 0x0004 /* System Options Register 2 */ +#define KINETIS_SIM_SOPT4_OFFSET 0x000c /* System Options Register 4 */ +#define KINETIS_SIM_SOPT5_OFFSET 0x0010 /* System Options Register 5 */ +#define KINETIS_SIM_SOPT6_OFFSET 0x0014 /* System Options Register 6 */ +#define KINETIS_SIM_SOPT7_OFFSET 0x0018 /* System Options Register 7 */ +#if defined(KINETIS_SIM_HAS_SOPT8) +# define KINETIS_SIM_SOPT8_OFFSET 0x001c /* System Options Register 8 */ +#endif +#if defined(KINETIS_SIM_HAS_SOPT9) +# define KINETIS_SIM_SOPT9_OFFSET 0x0020 /* System Options Register 9 */ +#endif +#define KINETIS_SIM_SDID_OFFSET 0x0024 /* System Device Identification Register */ +#define KINETIS_SIM_SCGC1_OFFSET 0x0028 /* System Clock Gating Control Register 1 */ +#define KINETIS_SIM_SCGC2_OFFSET 0x002c /* System Clock Gating Control Register 2 */ +#define KINETIS_SIM_SCGC3_OFFSET 0x0030 /* System Clock Gating Control Register 3 */ +#define KINETIS_SIM_SCGC4_OFFSET 0x0034 /* System Clock Gating Control Register 4 */ +#define KINETIS_SIM_SCGC5_OFFSET 0x0038 /* System Clock Gating Control Register 5 */ +#define KINETIS_SIM_SCGC6_OFFSET 0x003c /* System Clock Gating Control Register 6 */ +#define KINETIS_SIM_SCGC7_OFFSET 0x0040 /* System Clock Gating Control Register 7 */ +#define KINETIS_SIM_CLKDIV1_OFFSET 0x0044 /* System Clock Divider Register 1 */ +#define KINETIS_SIM_CLKDIV2_OFFSET 0x0048 /* System Clock Divider Register 2 */ +#define KINETIS_SIM_FCFG1_OFFSET 0x004c /* Flash Configuration Register 1 */ +#define KINETIS_SIM_FCFG2_OFFSET 0x0050 /* Flash Configuration Register 2 */ +#define KINETIS_SIM_UIDH_OFFSET 0x0054 /* Unique Identification Register High */ +#define KINETIS_SIM_UIDMH_OFFSET 0x0058 /* Unique Identification Register Mid-High */ +#define KINETIS_SIM_UIDML_OFFSET 0x005c /* Unique Identification Register Mid Low */ +#define KINETIS_SIM_UIDL_OFFSET 0x0060 /* Unique Identification Register Low */ +#if defined(KINETIS_SIM_HAS_CLKDIV3) +# define KINETIS_SIM_CLKDIV3_OFFSET 0x0064 /* System Clock Divider Register 3 */ +#endif +#if defined(KINETIS_SIM_HAS_CLKDIV4) +# define KINETIS_SIM_CLKDIV4_OFFSET 0x0068 /* System Clock Divider Register 4 */ +#endif /* Register Addresses ***************************************************************/ -/* NOTE: The SIM_SOPT1 register is located at a different base address than the - * other SIM registers. +/* NOTE: The SIM_SOPT1, SIM_SOPT1CFG and SIM_USBPHYCTL registers are located at a + * different base address than the other SIM registers. */ -#define KINETIS_SIM_SOPT1 (KINETIS_SIMLP_BASE+KINETIS_SIM_SOPT1_OFFSET) -#define KINETIS_SIM_SOPT2 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT2_OFFSET) -#define KINETIS_SIM_SOPT4 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT4_OFFSET) -#define KINETIS_SIM_SOPT5 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT5_OFFSET) -#define KINETIS_SIM_SOPT6 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT6_OFFSET) -#define KINETIS_SIM_SOPT7 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT7_OFFSET) -#define KINETIS_SIM_SDID (KINETIS_SIM_BASE+KINETIS_SIM_SDID_OFFSET) -#define KINETIS_SIM_SCGC1 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC1_OFFSET) -#define KINETIS_SIM_SCGC2 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC2_OFFSET) -#define KINETIS_SIM_SCGC3 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC3_OFFSET) -#define KINETIS_SIM_SCGC4 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC4_OFFSET) -#define KINETIS_SIM_SCGC5 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC5_OFFSET) -#define KINETIS_SIM_SCGC6 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC6_OFFSET) -#define KINETIS_SIM_SCGC7 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC7_OFFSET) -#define KINETIS_SIM_CLKDIV1 (KINETIS_SIM_BASE+KINETIS_SIM_CLKDIV1_OFFSET) -#define KINETIS_SIM_CLKDIV2 (KINETIS_SIM_BASE+KINETIS_SIM_CLKDIV2_OFFSET) -#define KINETIS_SIM_FCFG1 (KINETIS_SIM_BASE+KINETIS_SIM_FCFG1_OFFSET) -#define KINETIS_SIM_FCFG2 (KINETIS_SIM_BASE+KINETIS_SIM_FCFG2_OFFSET) -#define KINETIS_SIM_UIDH (KINETIS_SIM_BASE+KINETIS_SIM_UIDH_OFFSET) -#define KINETIS_SIM_UIDMH (KINETIS_SIM_BASE+KINETIS_SIM_UIDMH_OFFSET) -#define KINETIS_SIM_UIDML (KINETIS_SIM_BASE+KINETIS_SIM_UIDML_OFFSET) -#define KINETIS_SIM_UIDL (KINETIS_SIM_BASE+KINETIS_SIM_UIDL_OFFSET) +#define KINETIS_SIM_SOPT1 (KINETIS_SIMLP_BASE+KINETIS_SIM_SOPT1_OFFSET) +#if defined(KINETIS_SIM_HAS_SOPT1CFG) +# define KINETIS_SIM_SOPT1CFG (KINETIS_SIMLP_BASE+KINETIS_SIM_SOPT1CFG_OFFSET) +#endif +#if defined(KINETIS_SIM_HAS_USBPHYCTL) +# define KINETIS_SIM_USBPHYCTL (KINETIS_SIMLP_BASE+KINETIS_SIM_USBPHYCTL_OFFSET) +#endif +#define KINETIS_SIM_SOPT2 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT2_OFFSET) +#define KINETIS_SIM_SOPT4 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT4_OFFSET) +#define KINETIS_SIM_SOPT5 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT5_OFFSET) +#define KINETIS_SIM_SOPT6 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT6_OFFSET) +#define KINETIS_SIM_SOPT7 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT7_OFFSET) +#if defined(KINETIS_SIM_HAS_SOPT8) +# define KINETIS_SIM_SOPT8 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT8_OFFSET) +#endif +#if defined(KINETIS_SIM_HAS_SOPT9) +# define KINETIS_SIM_SOPT9 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT8_OFFSET) +#endif +#define KINETIS_SIM_SDID (KINETIS_SIM_BASE+KINETIS_SIM_SDID_OFFSET) +#define KINETIS_SIM_SCGC1 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC1_OFFSET) +#define KINETIS_SIM_SCGC2 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC2_OFFSET) +#define KINETIS_SIM_SCGC3 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC3_OFFSET) +#define KINETIS_SIM_SCGC4 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC4_OFFSET) +#define KINETIS_SIM_SCGC5 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC5_OFFSET) +#define KINETIS_SIM_SCGC6 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC6_OFFSET) +#define KINETIS_SIM_SCGC7 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC7_OFFSET) +#define KINETIS_SIM_CLKDIV1 (KINETIS_SIM_BASE+KINETIS_SIM_CLKDIV1_OFFSET) +#define KINETIS_SIM_CLKDIV2 (KINETIS_SIM_BASE+KINETIS_SIM_CLKDIV2_OFFSET) +#define KINETIS_SIM_FCFG1 (KINETIS_SIM_BASE+KINETIS_SIM_FCFG1_OFFSET) +#define KINETIS_SIM_FCFG2 (KINETIS_SIM_BASE+KINETIS_SIM_FCFG2_OFFSET) +#define KINETIS_SIM_UIDH (KINETIS_SIM_BASE+KINETIS_SIM_UIDH_OFFSET) +#define KINETIS_SIM_UIDMH (KINETIS_SIM_BASE+KINETIS_SIM_UIDMH_OFFSET) +#define KINETIS_SIM_UIDML (KINETIS_SIM_BASE+KINETIS_SIM_UIDML_OFFSET) +#define KINETIS_SIM_UIDL (KINETIS_SIM_BASE+KINETIS_SIM_UIDL_OFFSET) +#if defined(KINETIS_SIM_HAS_CLKDIV3) +# define KINETIS_SIM_CLKDIV3 (KINETIS_SIM_BASE+KINETIS_SIM_CLKDIV3_OFFSET) +#endif +#if defined(KINETIS_SIM_HAS_CLKDIV4) +# define KINETIS_SIM_CLKDIV4 (KINETIS_SIM_BASE+KINETIS_SIM_CLKDIV4_OFFSET) +#endif /* Register Bit Definitions *********************************************************/ /* System Options Register 1 */ - /* Bits 0-11: Reserved */ -#define SIM_SOPT1_RAMSIZE_SHIFT (12) /* Bits 12-15: RAM size */ -#define SIM_SOPT1_RAMSIZE_MASK (15 << SIM_SOPT1_RAMSIZE_SHIFT) -# define SIM_SOPT1_RAMSIZE_32KB (5 << SIM_SOPT1_RAMSIZE_SHIFT) /* 32 KBytes */ -# define SIM_SOPT1_RAMSIZE_64KB (7 << SIM_SOPT1_RAMSIZE_SHIFT) /* 64 KBytes */ -# define SIM_SOPT1_RAMSIZE_96KB (8 << SIM_SOPT1_RAMSIZE_SHIFT) /* 96 KBytes */ -# define SIM_SOPT1_RAMSIZE_128KB (9 << SIM_SOPT1_RAMSIZE_SHIFT) /* 128 KBytes */ - /* Bits 16-18: Reserved */ -#define SIM_SOPT1_OSC32KSEL (1 << 19) /* Bit 19: 32K oscillator clock select */ - /* Bits 20-22: Reserved */ -#define SIM_SOPT1_MS (1 << 23) /* Bit 23: EzPort chip select pin state */ - /* Bits 24-29: Reserved */ -#define SIM_SOPT1_USBSTBY (1 << 30) /* Bit 30: USB voltage regulator in standby mode */ -#define SIM_SOPT1_USBREGEN (1 << 31) /* Bit 31: USB voltage regulator enable */ + /* Bits 0-11: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT1_RAMSIZE) +# define SIM_SOPT1_RAMSIZE_SHIFT (12) /* Bits 12-15: RAM size */ +# define SIM_SOPT1_RAMSIZE_MASK (15 << SIM_SOPT1_RAMSIZE_SHIFT) +# define SIM_SOPT1_RAMSIZE_32KB (5 << SIM_SOPT1_RAMSIZE_SHIFT) /* 32 KBytes */ +# define SIM_SOPT1_RAMSIZE_64KB (7 << SIM_SOPT1_RAMSIZE_SHIFT) /* 64 KBytes */ +# define SIM_SOPT1_RAMSIZE_96KB (8 << SIM_SOPT1_RAMSIZE_SHIFT) /* 96 KBytes */ +# define SIM_SOPT1_RAMSIZE_128KB (9 << SIM_SOPT1_RAMSIZE_SHIFT) /* 128 KBytes */ +# define SIM_SOPT1_RAMSIZE_256KB (10 << SIM_SOPT1_RAMSIZE_SHIFT) /* 256 KBytes */ +#endif + /* Bits 16-18: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT1_OSC32KSEL) +# define SIM_SOPT1_OSC32KSEL_SHIFT (20-KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS) /* Bit 19 or 18: 32K oscillator clock select */ +# define SIM_SOPT1_OSC32KSEL_MASK (KINETIS_SIM_SOPT1_OSC32KSEL_MASK << SIM_SOPT1_OSC32KSEL_SHIFT) +# define SIM_SOPT1_OSC32KSEL(n) ((((n) & KINETIS_SIM_SOPT1_OSC32KSEL_MASK)) << SIM_SOPT1_OSC32KSEL_SHIFT) +# if KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS == 1 +# define SIM_SOPT1_OSC32KSEL_OSC32KCLK (((0 & KINETIS_SIM_SOPT1_OSC32KSEL_MASK)) << SIM_SOPT1_OSC32KSEL_SHIFT) +# define SIM_SOPT1_OSC32KSEL_RTC (((1 & KINETIS_SIM_SOPT1_OSC32KSEL_MASK)) << SIM_SOPT1_OSC32KSEL_SHIFT) +# endif +# if KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS == 2 +# define SIM_SOPT1_OSC32KSEL_OSC32KCLK (((0 & KINETIS_SIM_SOPT1_OSC32KSEL_MASK)) << SIM_SOPT1_OSC32KSEL_SHIFT) +# define SIM_SOPT1_OSC32KSEL_RTC (((2 & KINETIS_SIM_SOPT1_OSC32KSEL_MASK)) << SIM_SOPT1_OSC32KSEL_SHIFT) +# define SIM_SOPT1_OSC32KSEL_LPO1KZ (((3 & KINETIS_SIM_SOPT1_OSC32KSEL_MASK)) << SIM_SOPT1_OSC32KSEL_SHIFT) +# endif +#endif + /* Bits 20-28: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT1_USBVSTBY) + /* Bits 24-28: Reserved */ +# define SIM_SOPT1_USBVSTBY (1 << 29) /* Bit 29: USB voltage regulator in standby mode during VLPR and VLPW modes */ +#endif +#if defined(KINETIS_SIM_HAS_SOPT1_USBSSTBY) +# define SIM_SOPT1_USBSTBY (1 << 30) /* Bit 30: USB voltage regulator in standby mode */ +#endif +#if defined(KINETIS_SIM_HAS_SOPT1_USBREGEN) +# define SIM_SOPT1_USBREGEN (1 << 31) /* Bit 31: USB voltage regulator enable */ +#endif + +#if defined(KINETIS_SIM_HAS_SOPT1CFG) +/* SOPT1 Configuration Register */ + + /* Bits 0-22: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT1CFG_URWE) +# define SIM_SOPT1CFG_URWE (1 << 24) /* Bit 24: USB voltage regulator enable write enable */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT1CFG_USSWE) +# define SIM_SOPT1CFG_USSWE (1 << 25) /* Bit 25: USB voltage regulator VLP standby write enable */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT1CFG_UVSWE) +# define SIM_SOPT1CFG_UVSWE (1 << 26) /* Bit 26: USB voltage regulator stop standby write enable */ +# endif + /* Bits 27-31: Reserved */ +#endif + + +#if defined(KINETIS_SIM_HAS_USBPHYCTL) +/* USB PHY Control Register */ + + /* Bits 0-7: Reserved */ +# if defined(KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL) +# define SIM_USBPHYCTL_USBVREGSEL (1 << 8) /* Bit 8: Selects the default input voltage source */ +# endif +# if defined(KINETIS_SIM_HAS_USBPHYCTL_USBVREGPD) +# define SIM_USBPHYCTL_USBVREGPD (1 << 9) /* Bit 9: Enables the pulldown on the output of the USB Regulator */ +# endif + /* Bits 10-19: Reserved */ +# if defined(KINETIS_SIM_HAS_USBPHYCTL_USB3VOUTTRG) +# define SIM_USBPHYCTL_USB3VOUTTRG_SHIFT (20) /* Bit 20-22: USB 3.3V Output Target */ +# define SIM_USBPHYCTL_USB3VOUTTRG_MASK (7 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) +# define SIM_USBPHYCTL_USB3VOUTTRG_2V733 (0 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) /* 2.733V */ +# define SIM_USBPHYCTL_USB3VOUTTRG_3V020 (1 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) /* 3.020V */ +# define SIM_USBPHYCTL_USB3VOUTTRG_3V074 (2 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) /* 3.074V */ +# define SIM_USBPHYCTL_USB3VOUTTRG_3V130 (3 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) /* 3.130V */ +# define SIM_USBPHYCTL_USB3VOUTTRG_3V188 (4 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) /* 3.188V */ +# define SIM_USBPHYCTL_USB3VOUTTRG_3V248 (5 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) /* 3.248V */ +# define SIM_USBPHYCTL_USB3VOUTTRG_3V310 (6 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) /* 3.310V (default) */ +# define SIM_USBPHYCTL_USB3VOUTTRG_3V662 (7 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) /* 3.662V (For Freescale use only, not for customer use) */ +# endif +# if defined(KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM) +# define SIM_USBPHYCTL_USBDISILIM (1 << 23) /* Bit 23: USB Disable Inrush Current Limit */ +# endif + /* Bits 24-31: Reserved */ +#endif /* System Options Register 2 */ -#define SIM_SOPT2_MCGCLKSEL (1 << 0) /* Bit 0: MCG clock select */ - /* Bits 1-7: Reserved */ -#define SIM_SOPT2_FBSL_SHIFT (8) /* Bits 8-9: FlexBus security level */ -#define SIM_SOPT2_FBSL_MASK (3 << SIM_SOPT2_FBSL_SHIFT) -# define SIM_SOPT2_FBSL_NONE (0 << SIM_SOPT2_FBSL_SHIFT) /* All off-chip accesses disallowed */ -# define SIM_SOPT2_FBSL_DATA (2 << SIM_SOPT2_FBSL_SHIFT) /* Off-chip data accesses are allowed */ -# define SIM_SOPT2_FBSL_ALL (3 << SIM_SOPT2_FBSL_SHIFT) /* All Off-chip accesses allowed */ - /* Bit 10: Reserved */ -#define SIM_SOPT2_CMTUARTPAD (1 << 11) /* Bit 11: CMT/UART pad drive strength */ -#define SIM_SOPT2_TRACECLKSEL (1 << 12) /* Bit 12: Debug trace clock select */ - /* Bits 13-15: Reserved */ -#define SIM_SOPT2_PLLFLLSEL (1 << 16) /* Bit 16: PLL/FLL clock select */ - /* Bit 17: Reserved */ -#define SIM_SOPT2_USBSRC (1 << 18) /* Bit 18: USB clock source select */ - /* Bit 19: Reserved */ -#if defined(KINETIS_K60) || defined(KINETIS_K64) || defined(KINETIS_K66) -# define SIM_SOPT2_RMIISRC_SHIFT (19) /* Bit 19: RMII clock source select */ -# define SIM_SOPT2_RMIISRC_EXTAL (0 << SIM_SOPT2_RMIISRC_SHIFT) /* EXTAL clock */ -# define SIM_SOPT2_RMIISRC_EXTBYP (1 << SIM_SOPT2_RMIISRC_SHIFT) /* External bypass clock (ENET_1588_CLKIN) */ -# define SIM_SOPT2_TIMESRC_SHIFT (20) /* Bit 20-21: IEEE 1588 timestamp clock source select (K60) */ -# define SIM_SOPT2_TIMESRC_MASK (3 << SIM_SOPT2_TIMESRC_SHIFT) -# define SIM_SOPT2_TIMESRC_CORE (0 << SIM_SOPT2_TIMESRC_SHIFT) /* Core/system clock */ -# define SIM_SOPT2_TIMESRC_PLLSEL (1 << SIM_SOPT2_TIMESRC_SHIFT) /* MCGFLLCLK,MCGPLLCLK,IRC48M,USB1 PFD - clock as selected by SOPT2[PLLFLLSEL] */ -# define SIM_SOPT2_TIMESRC_OSCERCLK (2 << SIM_SOPT2_TIMESRC_SHIFT) /* OSCERCLK clock */ -# define SIM_SOPT2_TIMESRC_EXTBYP (0 << SIM_SOPT2_TIMESRC_SHIFT) /* External bypass clock (ENET_1588_CLKIN) */ +#if defined(KINETIS_SIM_HAS_SOPT2) +# if defined(KINETIS_SIM_HAS_SOPT2_MCGCLKSEL) +# define SIM_SOPT2_MCGCLKSEL (1 << 0) /* Bit 0: MCG clock select */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_USBSLSRC) +# define SIM_SOPT2_USBSLSRC (1 << 0) /* Bit 0: USB Slow Clock Source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_USBREGEN) +# define SIM_SOPT2_USBREGEN (1 << 1) /* Bit 1: USB PHY PLL Regulator Enable */ +# endif + /* Bits 2-3: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT2_USBHSRC) +# define SIM_SOPT2_USBSHSRC_SHIFT (2) /* Bit 2-3: USB HS clock source select */ +# define SIM_SOPT2_USBSHSRC_MASK (3 << SIM_SOPT2_USBSHSRC_SHIFT) +# define SIM_SOPT2_USBSHSRC_BUSCLK (0 << SIM_SOPT2_USBSHSRC_SHIFT) +# define SIM_SOPT2_USBSHSRC_MCGPLL0CLK (1 << SIM_SOPT2_USBSHSRC_SHIFT) +# define SIM_SOPT2_USBSHSRC_MCGPLL1CLK (2 << SIM_SOPT2_USBSHSRC_SHIFT) +# define SIM_SOPT2_USBSHSRC_OSC0ERCLK (3 << SIM_SOPT2_USBSHSRC_SHIFT) +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_RTCCLKOUTSEL) +# define SIM_SOPT2_RTCCLKOUTSEL (1 << 4) /* Bit 4: RTC clock out select */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_CLKOUTSEL) +# define SIM_SOPT2_CLKOUTSEL_SHIFT (5) /* Bits 5-7: CLKOUT select */ +# define SIM_SOPT2_CLKOUTSEL_MASK (7 << SIM_SOPT2_CLKOUTSEL_SHIFT) +# define SIM_SOPT2_CLKOUTSEL_FBCLKOUT (0 << SIM_SOPT2_CLKOUTSEL_SHIFT) +# define SIM_SOPT2_CLKOUTSEL_FLSHCLK (2 << SIM_SOPT2_CLKOUTSEL_SHIFT) +# define SIM_SOPT2_CLKOUTSEL_LPO1KHZ (3 << SIM_SOPT2_CLKOUTSEL_SHIFT) +# define SIM_SOPT2_CLKOUTSEL_MCGIRCLK (4 << SIM_SOPT2_CLKOUTSEL_SHIFT) +# define SIM_SOPT2_CLKOUTSEL_RTC32768KHZ (5 << SIM_SOPT2_CLKOUTSEL_SHIFT) +# define SIM_SOPT2_CLKOUTSEL_OSCERCLK0 (6 << SIM_SOPT2_CLKOUTSEL_SHIFT) +# define SIM_SOPT2_CLKOUTSEL_IRC48MHZ (7 << SIM_SOPT2_CLKOUTSEL_SHIFT) +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_FBSL) +# define SIM_SOPT2_FBSL_SHIFT (8) /* Bits 8-9: FlexBus security level */ +# define SIM_SOPT2_FBSL_MASK (3 << SIM_SOPT2_FBSL_SHIFT) +# define SIM_SOPT2_FBSL_NONE (0 << SIM_SOPT2_FBSL_SHIFT) /* All off-chip accesses disallowed */ +# define SIM_SOPT2_FBSL_DATA (2 << SIM_SOPT2_FBSL_SHIFT) /* Off-chip data accesses are allowed */ +# define SIM_SOPT2_FBSL_ALL (3 << SIM_SOPT2_FBSL_SHIFT) /* All Off-chip accesses allowed */ +# endif + /* Bit 10: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT2_CMTUARTPAD) +# define SIM_SOPT2_CMTUARTPAD (1 << 11) /* Bit 11: CMT/UART pad drive strength */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_PTD7PAD) +# define SIM_SOPT2_PTD7PAD (1 << 11) /* Bit 11: PTD7P pad drive strength */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_TRACECLKSEL) +# define SIM_SOPT2_TRACECLKSEL (1 << 12) /* Bit 12: Debug trace clock select */ +# endif + /* Bits 13-15: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT2_PLLFLLSEL) +# define SIM_SOPT2_PLLFLLSEL_SHIFT (16) /* Bits 16-[17]: PLL/FLL clock select */ +# define SIM_SOPT2_PLLFLLSEL_MASK (KINETIS_SIM_SOPT2_PLLFLLSEL_MASK << SIM_SOPT2_PLLFLLSEL_SHIFT) +# define SIM_SOPT2_PLLFLLSEL(n) (((n) & KINETIS_SIM_SOPT2_PLLFLLSEL_MASK) << SIM_SOPT2_PLLFLLSEL_SHIFT) +# define SIM_SOPT2_PLLFLLSEL_MCGFLLCLK ((0 & KINETIS_SIM_SOPT2_PLLFLLSEL_MASK) << SIM_SOPT2_PLLFLLSEL_SHIFT) +# define SIM_SOPT2_PLLFLLSEL_MCGPLLCLK ((1 & KINETIS_SIM_SOPT2_PLLFLLSEL_MASK) << SIM_SOPT2_PLLFLLSEL_SHIFT) +# if KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS > 1 +# define SIM_SOPT2_PLLFLLSEL_USB1PFD ((2 & KINETIS_SIM_SOPT2_PLLFLLSEL_MASK) << SIM_SOPT2_PLLFLLSEL_SHIFT) +# define SIM_SOPT2_PLLFLLSEL_IRC48MHZ ((3 & KINETIS_SIM_SOPT2_PLLFLLSEL_MASK) << SIM_SOPT2_PLLFLLSEL_SHIFT) +# endif +# endif + /* Bit 17: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT2_USBSRC) +# define SIM_SOPT2_USBSRC (1 << 18) /* Bit 18: USB clock source select */ +# endif + /* Bit 19: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT2_RMIISRC) +# define SIM_SOPT2_RMIISRC_SHIFT (19) /* Bit 19: RMII clock source select */ +# define SIM_SOPT2_RMIISRC_EXTAL (0 << SIM_SOPT2_RMIISRC_SHIFT) /* EXTAL clock */ +# define SIM_SOPT2_RMIISRC_EXTBYP (1 << SIM_SOPT2_RMIISRC_SHIFT) /* External bypass clock (ENET_1588_CLKIN) */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_TIMESRC) +# define SIM_SOPT2_TIMESRC_SHIFT (20) /* Bit 20-21: IEEE 1588 timestamp clock source select */ +# define SIM_SOPT2_TIMESRC_MASK (3 << SIM_SOPT2_TIMESRC_SHIFT) +# define SIM_SOPT2_TIMESRC_CORE (0 << SIM_SOPT2_TIMESRC_SHIFT) /* Core/system clock */ +# define SIM_SOPT2_TIMESRC_PLLSEL (1 << SIM_SOPT2_TIMESRC_SHIFT) /* MCGFLLCLK,MCGPLLCLK,IRC48M,USB1 PFD + clock as selected by SOPT2[PLLFLLSEL] */ +# define SIM_SOPT2_TIMESRC_OSCERCLK (2 << SIM_SOPT2_TIMESRC_SHIFT) /* OSCERCLK clock */ +# define SIM_SOPT2_TIMESRC_EXTBYP (3 << SIM_SOPT2_TIMESRC_SHIFT) /* External bypass clock (ENET_1588_CLKIN) */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_FLEXIOSRC) + /* TBD */ +# endif + /* Bits 22-23: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT2_USBFSRC) +# define SIM_SOPT2_USBFSRC_SHIFT (22) /* Bits 22-23: USB FS clock source select */ +# define SIM_SOPT2_USBFSRC_MASK (3 << SIM_SOPT2_USBFSRC_SHIFT) +# define SIM_SOPT2_USBFSRC_MCGCLK (0 << SIM_SOPT2_USBFSRC_SHIFT) /* MCGFLLCLK,MCGPLLCLK clock as selected by SOPT2[PLLFLLSEL] */ +# define SIM_SOPT2_USBFSRC_MCGPLL0CLK (1 << SIM_SOPT2_USBFSRC_SHIFT) /* MCGPLL0CLK clock */ +# define SIM_SOPT2_USBFSRC_MCGPLL1CLK (2 << SIM_SOPT2_USBFSRC_SHIFT) /* MCGPLL1CLK clock */ +# define SIM_SOPT2_USBFSRC_OCS0ERCLK (3 << SIM_SOPT2_USBFSRC_SHIFT) /* OSC0ERCLK clock */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_TPMSRC) +# define SIM_SOPT2_TPMSRC_SHIFT (24) /* Bits 24-25: TPM clock source select */ +# define SIM_SOPT2_TPMSRC_MASK (3 << SIM_SOPT2_TPMSRC_SHIFT) +# define SIM_SOPT2_TPMSRC_CORE (0 << SIM_SOPT2_TPMSRC_SHIFT) /* Clock disabled */ +# define SIM_SOPT2_TPMSRC_MCGCLK (1 << SIM_SOPT2_TPMSRC_SHIFT) /* MCGFLLCLK,MCGPLLCLK,IRC48M,USB1 PFD + clock as selected by SOPT2[PLLFLLSEL] and then + divided by the PLLFLLCLK fractional divider + as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV] */ +# define SIM_SOPT2_TPMSRC_OCSERCLK (2 << SIM_SOPT2_TPMSRC_SHIFT) /* OSCERCLK clock */ +# define SIM_SOPT2_TPMSRC_EXTBYP (3 << SIM_SOPT2_TPMSRC_SHIFT) /* MCGIRCLK clock */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_I2SSRC) +# define SIM_SOPT2_I2SSRC_SHIFT (24) /* Bits 24-25: I2S master clock source select */ +# define SIM_SOPT2_I2SSRC_MASK (3 << SIM_SOPT2_I2SSRC_SHIFT) +# define SIM_SOPT2_I2SCSRC_CORE (0 << SIM_SOPT2_I2SSRC_SHIFT) /* Core/system clock / I2S fractional divider */ +# define SIM_SOPT2_I2SCSRC_MCGCLK (1 << SIM_SOPT2_I2SSRC_SHIFT) /* MCGPLLCLK/MCGFLLCLK clock/ I2S fractional divider */ +# define SIM_SOPT2_I2SCSRC_OCSERCLK (2 << SIM_SOPT2_I2SSRC_SHIFT) /* OSCERCLK clock */ +# define SIM_SOPT2_I2SCSRC_EXTBYP (3 << SIM_SOPT2_I2SSRC_SHIFT) /* External bypass clock (I2S0_CLKIN) */ +# endif + /* Bits 26-27: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT2_LPUARTSRC) +# define SIM_SOPT2_LPUARTSRC_SHIFT (26) /* Bits 26-27: LPUART clock source select */ +# define SIM_SOPT2_LPUARTSRC_MASK (3 << SIM_SOPT2_LPUARTSRC_SHIFT) +# define SIM_SOPT2_LPUARTSRC_CORE (0 << SIM_SOPT2_LPUARTSRC_SHIFT) /* Clock disabled */ +# define SIM_SOPT2_LPUARTSRC_MCGCLK (1 << SIM_SOPT2_LPUARTSRC_SHIFT) /* MCGFLLCLK,MCGPLLCLK,IRC48M,USB1 PFD + clock as selected by SOPT2[PLLFLLSEL] and then + divided by the PLLFLLCLK fractional divider + as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV] */ +# define SIM_SOPT2_LPUARTSRC_OCSERCLK (2 << SIM_SOPT2_LPUARTSRC_SHIFT) /* OSCERCLK clock */ +# define SIM_SOPT2_LPUARTSRC_EXTBYP (3 << SIM_SOPT2_LPUARTSRC_SHIFT) /* MCGIRCLK clock */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_SDHCSRC) +# define SIM_SOPT2_SDHCSRC_SHIFT (28) /* Bits 28-29: SDHC clock source select */ +# define SIM_SOPT2_SDHCSRC_MASK (3 << SIM_SOPT2_SDHCSRC_SHIFT) +# define SIM_SOPT2_SDHCSRC_CORE (0 << SIM_SOPT2_SDHCSRC_SHIFT) /* Core/system clock */ +# define SIM_SOPT2_SDHCSRC_MCGCLK (1 << SIM_SOPT2_SDHCSRC_SHIFT) /* MCGPLLCLK/MCGFLLCLK clock */ +# define SIM_SOPT2_SDHCSRC_OCSERCLK (2 << SIM_SOPT2_SDHCSRC_SHIFT) /* OSCERCLK clock */ +# define SIM_SOPT2_SDHCSRC_EXTBYP (3 << SIM_SOPT2_SDHCSRC_SHIFT) /* External bypass clock (SDHC0_CLKIN) */ + /* Bits 30-31: Reserved */ +# endif + /* Bits 30-31: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT2_NFCSRC) +# define SIM_SOPT2_NFCSRC_SHIFT (30) /* Bits 30-31: NFC Flash clock source select */ +# define SIM_SOPT2_NFCSRC_MASK (3 << SIM_SOPT2_NFCSRC_SHIFT) +# define SIM_SOPT2_NFCSRC_BUS (0 << SIM_SOPT2_NFCSRC_SHIFT) /* BUS clock */ +# define SIM_SOPT2_NFCSRC_MCGPLL0CLK (1 << SIM_SOPT2_NFCSRC_SHIFT) /* MCGPLL0CLK clock */ +# define SIM_SOPT2_NFCSRC_MCGPLL1CLK (2 << SIM_SOPT2_NFCSRC_SHIFT) /* MCGPLL1CLK clock */ +# define SIM_SOPT2_NFCSRC_OCS0ERCLK (3 << SIM_SOPT2_NFCSRC_SHIFT) /* OSC0ERCLK clock */ +# endif #endif - /* Bits 12-23: Reserved */ -#define SIM_SOPT2_I2SSRC_SHIFT (24) /* Bits 24-25: I2S master clock source select */ -#define SIM_SOPT2_I2SSRC_MASK (3 << SIM_SOPT2_I2SSRC_SHIFT) -# define SIM_SOPT2_I2SCSRC_CORE (0 << SIM_SOPT2_I2SSRC_SHIFT) /* Core/system clock / I2S fractional divider*/ -# define SIM_SOPT2_I2SCSRC_MCGCLK (1 << SIM_SOPT2_I2SSRC_SHIFT) /* MCGPLLCLK/MCGFLLCLK clock/ I2S fractional divider */ -# define SIM_SOPT2_I2SCSRC_OCSERCLK (2 << SIM_SOPT2_I2SSRC_SHIFT) /* OSCERCLK clock */ -# define SIM_SOPT2_I2SCSRC_EXTBYP (3 << SIM_SOPT2_I2SSRC_SHIFT) /* External bypass clock (I2S0_CLKIN) */ - /* Bits 26-27: Reserved */ -#define SIM_SOPT2_SDHCSRC_SHIFT (28) /* Bits 28-29: SDHC clock source select*/ -#define SIM_SOPT2_SDHCSRC_MASK (3 << SIM_SOPT2_SDHCSRC_SHIFT) -# define SIM_SOPT2_SDHCSRC_CORE (0 << SIM_SOPT2_SDHCSRC_SHIFT) /* Core/system clock */ -# define SIM_SOPT2_SDHCSRC_MCGCLK (1 << SIM_SOPT2_SDHCSRC_SHIFT) /* MCGPLLCLK/MCGFLLCLK clock */ -# define SIM_SOPT2_SDHCSRC_OCSERCLK (2 << SIM_SOPT2_SDHCSRC_SHIFT) /* OSCERCLK clock */ -# define SIM_SOPT2_SDHCSRC_EXTBYP (3 << SIM_SOPT2_SDHCSRC_SHIFT) /* External bypass clock (SDHC0_CLKIN) */ /* Bits 30-31: Reserved */ /* System Options Register 4 */ -#define SIM_SOPT4_FTM0FLT0 (1 << 0) /* Bit 0: FTM0 Fault 0 Select */ -#define SIM_SOPT4_FTM0FLT1 (1 << 1) /* Bit 1: FTM0 Fault 1 Select */ -#define SIM_SOPT4_FTM0FLT2 (1 << 2) /* Bit 2: FTM0 Fault 2 Select */ - /* Bit 3: Reserved */ -#define SIM_SOPT4_FTM1FLT0 (1 << 4) /* Bit 4: FTM1 Fault 0 Select */ - /* Bits 5-7: Reserved */ -#define SIM_SOPT4_FTM2FLT0 (1 << 8) /* Bit 8: FTM2 Fault 0 Select */ - /* Bits 9-17: Reserved */ -#if defined(CONFIG_KINETIS_FTM3) - /* Bits 9-11,13-17: Reserved */ -# define SIM_SOPT4_FTM3FLT0 (1 << 12) /* Bit 12: FTM3 Fault 0 Select */ +#define SIM_SOPT4_FTM0FLT0 (1 << 0) /* Bit 0: FTM0 Fault 0 Select */ +#define SIM_SOPT4_FTM0FLT1 (1 << 1) /* Bit 1: FTM0 Fault 1 Select */ +#define SIM_SOPT4_FTM0FLT2 (1 << 2) /* Bit 2: FTM0 Fault 2 Select */ + /* Bit 3: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT4_FTM0FLT3) +# define SIM_SOPT4_FTM0FLT3 (1 << 3) /* Bit 3: FTM0 Fault 3 Select */ #endif -#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18) /* Bits 18-19: FTM1 channel 0 input capture source select */ -#define SIM_SOPT4_FTM1CH0SRC_MASK (3 << SIM_SOPT4_FTM1CH0SRC_SHIFT) -# define SIM_SOPT4_FTM1CH0SRC_CH0 (0 << SIM_SOPT4_FTM1CH0SRC_SHIFT) /* FTM1_CH0 signal */ -# define SIM_SOPT4_FTM1CH0SRC_CMP0 (1 << SIM_SOPT4_FTM1CH0SRC_SHIFT) /* CMP0 output */ -# define SIM_SOPT4_FTM1CH0SRC_CMP1 (2 << SIM_SOPT4_FTM1CH0SRC_SHIFT) /* CMP1 output */ -#define SIM_SOPT4_FTM2CH0SRC_SHIFT (20) /* Bits 20-21: FTM2 channel 0 input capture source select */ -#define SIM_SOPT4_FTM2CH0SRC_MASK (3 << SIM_SOPT4_FTM2CH0SRC_SHIFT) -# define SIM_SOPT4_FTM2CH0SRC_CH0 (0 << SIM_SOPT4_FTM2CH0SRC_SHIFT) /* FTM2_CH0 signal */ -# define SIM_SOPT4_FTM2CH0SRC_CMP0 (1 << SIM_SOPT4_FTM2CH0SRC_SHIFT) /* CMP0 output */ -# define SIM_SOPT4_FTM2CH0SRC_CMP1 (2 << SIM_SOPT4_FTM2CH0SRC_SHIFT) /* CMP1 output */ - /* Bits 22-23: Reserved */ -#define SIM_SOPT4_FTM0CLKSEL (1 << 24) /* Bit 24: FlexTimer 0 External Clock Pin Select */ -#define SIM_SOPT4_FTM1CLKSEL (1 << 25) /* Bit 25: FTM1 External Clock Pin Select */ -#define SIM_SOPT4_FTM2CLKSEL (1 << 26) /* Bit 26: FlexTimer 2 External Clock Pin Select */ - /* Bits 27-31: Reserved */ -#if defined(CONFIG_KINETIS_FTM3) -# define SIM_SOPT4_FTM3CLKSEL (1 << 27) /* Bit 27: FlexTimer 3 External Clock Pin Select */ -# define SIM_SOPT4_FTM3TRG0SRC (1 << 30) /* Bit 30: FlexTimer 3 Hardware Trigger 0 Source Select */ -# define SIM_SOPT4_FTM3TRG1SRC (1 << 31) /* Bit 31: FlexTimer 3 Hardware Trigger 1 Source Select */ +#define SIM_SOPT4_FTM1FLT0 (1 << 4) /* Bit 4: FTM1 Fault 0 Select */ + /* Bits 5-7: Reserved */ +#define SIM_SOPT4_FTM2FLT0 (1 << 8) /* Bit 8: FTM2 Fault 0 Select */ + /* Bits 9-17: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT4_FTM3FLT0) + /* Bits 9-11,13-17: Reserved */ +# define SIM_SOPT4_FTM3FLT0 (1 << 12) /* Bit 12: FTM3 Fault 0 Select */ +#endif +#if defined(KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC) +# define SIM_SOPT4_FTM1CH0SRC_SHIFT (18) /* Bits 18-19: FTM1 channel 0 input capture source select */ +# define SIM_SOPT4_FTM1CH0SRC_MASK (3 << SIM_SOPT4_FTM1CH0SRC_SHIFT) +# define SIM_SOPT4_FTM1CH0SRC_CH0 (0 << SIM_SOPT4_FTM1CH0SRC_SHIFT) /* FTM1_CH0 signal */ +# define SIM_SOPT4_FTM1CH0SRC_CMP0 (1 << SIM_SOPT4_FTM1CH0SRC_SHIFT) /* CMP0 output */ +# define SIM_SOPT4_FTM1CH0SRC_CMP1 (2 << SIM_SOPT4_FTM1CH0SRC_SHIFT) /* CMP1 output */ +# if KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC > 2 +# define SIM_SOPT4_FTM1CH0SRC_USBSOF (3 << SIM_SOPT4_FTM1CH0SRC_SHIFT) /* USB start of frame pulse */ +# endif +#endif +#if defined(KINETIS_SIM_HAS_SOPT4_FTM2CH0SRC) +# define SIM_SOPT4_FTM2CH0SRC_SHIFT (20) /* Bits 20-21: FTM2 channel 0 input capture source select */ +# define SIM_SOPT4_FTM2CH0SRC_MASK (3 << SIM_SOPT4_FTM2CH0SRC_SHIFT) +# define SIM_SOPT4_FTM2CH0SRC_CH0 (0 << SIM_SOPT4_FTM2CH0SRC_SHIFT) /* FTM2_CH0 signal */ +# define SIM_SOPT4_FTM2CH0SRC_CMP0 (1 << SIM_SOPT4_FTM2CH0SRC_SHIFT) /* CMP0 output */ +# define SIM_SOPT4_FTM2CH0SRC_CMP1 (2 << SIM_SOPT4_FTM2CH0SRC_SHIFT) /* CMP1 output */ +#endif + /* Bits 22-23: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT4_FTM2CH1SRC) + /* Bit 23: Reserved */ + #define SIM_SOPT4_FTM2CH1SRC (1 << 22) /* Bit 22: FTM2 channel 1 input capture source select */ +#endif +#define SIM_SOPT4_FTM0CLKSEL (1 << 24) /* Bit 24: FlexTimer 0 External Clock Pin Select */ +#define SIM_SOPT4_FTM1CLKSEL (1 << 25) /* Bit 25: FTM1 External Clock Pin Select */ +#define SIM_SOPT4_FTM2CLKSEL (1 << 26) /* Bit 26: FlexTimer 2 External Clock Pin Select */ + /* Bits 27-31: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC) || defined(KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC) +# define SIM_SOPT4_FTM3CLKSEL (1 << 27) /* Bit 27: FlexTimer 3 External Clock Pin Select */ +#endif +#if defined(KINETIS_SIM_HAS_SOPT4_FTM0TRG0SRC) + /* Bits 27,30-31: Reserved */ +# define SIM_SOPT4_FTM0TRG0SRC (1 << 28) /* Bit 28: FlexTimer 0 Hardware Trigger 0 Source Select */ +#endif +#if defined(KINETIS_SIM_HAS_SOPT4_FTM0TRG1SRC) + /* Bits 27,30-31: Reserved */ +# define SIM_SOPT4_FTM0TRG1SRC (1 << 29) /* Bit 29: FlexTimer 0 Hardware Trigger 1 Source Select */ +#endif +#if defined(KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC) +# define SIM_SOPT4_FTM3TRG0SRC (1 << 30) /* Bit 30: FlexTimer 3 Hardware Trigger 0 Source Select */ +#endif +#if defined(KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC) +# define SIM_SOPT4_FTM3TRG1SRC (1 << 31) /* Bit 31: FlexTimer 3 Hardware Trigger 1 Source Select */ #endif /* System Options Register 5 */ -#define SIM_SOPT5_UART0TXSRC_SHIFT (0) /* Bits 0-1: UART 0 transmit data source select */ -#define SIM_SOPT5_UART0TXSRC_MASK (3 << SIM_SOPT5_UART0TXSRC_SHIFT) -# define SIM_SOPT5_UART0TXSRC_TX (0 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX pin */ -# define SIM_SOPT5_UART0TXSRC_FTM1 (1 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX modulated with FTM1 ch0 output */ -# define SIM_SOPT5_UART0TXSRC_FTM2 (2 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX modulated with FTM2 ch0 output */ -#define SIM_SOPT5_UART0RXSRC_SHIFT (2) /* Bits 2-3: UART 0 receive data source select */ -#define SIM_SOPT5_UART0RXSRC_MASK (3 << SIM_SOPT5_UART0RXSRC_SHIFT) -# define SIM_SOPT5_UART0RXSRC_RX (0 << SIM_SOPT5_UART0RXSRC_SHIFT) /* UART0_RX pin */ -# define SIM_SOPT5_UART0RXSRC_CMP0 (1 << SIM_SOPT5_UART0RXSRC_SHIFT) /* CMP0 */ -# define SIM_SOPT5_UART0RXSRC_CMP1 (2 << SIM_SOPT5_UART0RXSRC_SHIFT) /* CMP1 */ -#define SIM_SOPT5_UART1TXSRC_SHIFT (4) /* Bits 4-5: UART 1 transmit data source select */ -#define SIM_SOPT5_UART1TXSRC_MASK (3 << SIM_SOPT5_UART1TXSRC_SHIFT) -# define SIM_SOPT5_UART1TXSRC_TX (0 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX pin */ -# define SIM_SOPT5_UART1TXSRC_FTM1 (1 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX modulated with FTM1 ch0 output */ -# define SIM_SOPT5_UART1TXSRC_FTM2 (2 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX modulated with FTM2 ch0 output */ -#define SIM_SOPT5_UART1RXSRC_SHIFT (6) /* Bits 6-7: UART 1 receive data source select */ -#define SIM_SOPT5_UART1RXSRC_MASK (3 << SIM_SOPT5_UART1RXSRC_SHIFT) -# define SIM_SOPT5_UART1RXSRC_RX (0 << SIM_SOPT5_UART1RXSRC_SHIFT) /* UART1_RX pin */ -# define SIM_SOPT5_UART1RXSRC_CMP0 (1 << SIM_SOPT5_UART1RXSRC_SHIFT) /* CMP0 */ -# define SIM_SOPT5_UART1RXSRC_CMP1 (2 << SIM_SOPT5_UART1RXSRC_SHIFT) /* CMP1 */ - /* Bits 8-31: Reserved */ +#define SIM_SOPT5_UART0TXSRC_SHIFT (0) /* Bits 0-1: UART 0 transmit data source select */ +#define SIM_SOPT5_UART0TXSRC_MASK (3 << SIM_SOPT5_UART0TXSRC_SHIFT) +# define SIM_SOPT5_UART0TXSRC_TX (0 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX pin */ +# define SIM_SOPT5_UART0TXSRC_FTM1 (1 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX modulated with FTM1 ch0 output */ +# define SIM_SOPT5_UART0TXSRC_FTM2 (2 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX modulated with FTM2 ch0 output */ +#define SIM_SOPT5_UART0RXSRC_SHIFT (2) /* Bits 2-3: UART 0 receive data source select */ +#define SIM_SOPT5_UART0RXSRC_MASK (3 << SIM_SOPT5_UART0RXSRC_SHIFT) +# define SIM_SOPT5_UART0RXSRC_RX (0 << SIM_SOPT5_UART0RXSRC_SHIFT) /* UART0_RX pin */ +# define SIM_SOPT5_UART0RXSRC_CMP0 (1 << SIM_SOPT5_UART0RXSRC_SHIFT) /* CMP0 */ +# define SIM_SOPT5_UART0RXSRC_CMP1 (2 << SIM_SOPT5_UART0RXSRC_SHIFT) /* CMP1 */ +#define SIM_SOPT5_UART1TXSRC_SHIFT (4) /* Bits 4-5: UART 1 transmit data source select */ +#define SIM_SOPT5_UART1TXSRC_MASK (3 << SIM_SOPT5_UART1TXSRC_SHIFT) +# define SIM_SOPT5_UART1TXSRC_TX (0 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX pin */ +# define SIM_SOPT5_UART1TXSRC_FTM1 (1 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX modulated with FTM1 ch0 output */ +# define SIM_SOPT5_UART1TXSRC_FTM2 (2 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX modulated with FTM2 ch0 output */ +#define SIM_SOPT5_UART1RXSRC_SHIFT (6) /* Bits 6-7: UART 1 receive data source select */ +#define SIM_SOPT5_UART1RXSRC_MASK (3 << SIM_SOPT5_UART1RXSRC_SHIFT) +# define SIM_SOPT5_UART1RXSRC_RX (0 << SIM_SOPT5_UART1RXSRC_SHIFT) /* UART1_RX pin */ +# define SIM_SOPT5_UART1RXSRC_CMP0 (1 << SIM_SOPT5_UART1RXSRC_SHIFT) /* CMP0 */ +# define SIM_SOPT5_UART1RXSRC_CMP1 (2 << SIM_SOPT5_UART1RXSRC_SHIFT) /* CMP1 */ + /* Bits 8-31: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC) + /* Bits 8-15, 18-31: Reserved */ +# define SIM_SOPT5_LPUART0TXSRC_SHIFT (16) /* Bit 16: LPUART0 transmit data source select */ +# define SIM_SOPT5_LPUART0TXSRC_MASK (3 << SIM_SOPT5_LPUART0TXSRC_SHIFT) +# define SIM_SOPT5_LPUART0TXSRC_TX (0 << SIM_SOPT5_LPUART0TXSRC_SHIFT) /* LPUART0_TX pin */ +# define SIM_SOPT5_LPUART0TXSRC_TXTMP1CH0 (1 << SIM_SOPT5_LPUART0TXSRC_SHIFT) /* LPUART0_TX pin modulated with TPM1 channel 0 output */ +# define SIM_SOPT5_LPUART0TXSRC_TXTMP2CH0 (2 << SIM_SOPT5_LPUART0TXSRC_SHIFT) /* LPUART0_TX pin modulated with TPM2 channel 0 output */ +#endif + /* Bits 8-15, 18-31: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC) + /* Bits 8-15, 20-31: Reserved */ +# define SIM_SOPT5_LPUART0RXSRC_SHIFT (18) /* Bit 18: LPUART0 receive data source select */ +# define SIM_SOPT5_LPUART0RXSRC_MASK (3 << SIM_SOPT5_LPUART0RXSRC_SHIFT) +# define SIM_SOPT5_LPUART0RXSRC_TX (0 << SIM_SOPT5_LPUART0RXSRC_SHIFT) /* LPUART0_RX pin */ +# define SIM_SOPT5_LPUART0RXSRC_TXTMP1CH0 (1 << SIM_SOPT5_LPUART0RXSRC_SHIFT) /* CMP0 output */ +# define SIM_SOPT5_LPUART0RXSRC_TXTMP2CH0 (2 << SIM_SOPT5_LPUART0RXSRC_SHIFT) /* CMP1 output */ +#endif + +#if defined(KINETIS_SIM_HAS_SOPT6) /* System Options Register 6 */ - /* Bits 0-23: Reserved */ -#define SIM_SOPT6_RSTFLTSEL_SHIFT (24) /* Bits 24-28: Reset pin filter select */ -#define SIM_SOPT6_RSTFLTSEL_MASK (31 << SIM_SOPT6_RSTFLTSEL_SHIFT) -# define SIM_SOPT6_RSTFLTSEL(n) ((uint32_t)((n)-1) << SIM_SOPT6_RSTFLTSEL_SHIFT) /* n=1..32 */ -#define SIM_SOPT6_RSTFLTEN_SHIFT (29) /* Bits 29-31: Reset pin filter enable */ -#define SIM_SOPT6_RSTFLTEN_MASK (7 << SIM_SOPT6_RSTFLTEN_SHIFT) -#define SIM_SOPT6_RSTFLTEN_DISABLED (0 << SIM_SOPT6_RSTFLTEN_SHIFT) /* All filtering disabled */ -# define SIM_SOPT6_RSTFLTEN_BUSCLK1 (1 << SIM_SOPT6_RSTFLTEN_SHIFT) /* Bus clock filter enabled (normal); LPO clock filter enabled (stop) */ -# define SIM_SOPT6_RSTFLTEN_LPO1 (2 << SIM_SOPT6_RSTFLTEN_SHIFT) /* LPO clock filter enabled */ -# define SIM_SOPT6_RSTFLTEN_BUSCLK2 (3 << SIM_SOPT6_RSTFLTEN_SHIFT) /* Bus clock filter enabled (normal); All filtering disabled (stop) */ -# define SIM_SOPT6_RSTFLTEN_LPO2 (4 << SIM_SOPT6_RSTFLTEN_SHIFT) /* PO clock filter enabled (normal); All filtering disabled (stop) */ + + /* Bits 0-23: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT6_MCC) + /* Bits 16-23: Reserved */ +# define SIM_SOPT6_MCC_SHIFT (0) /* Bits 0-15: NFC hold cycle in case FlexBus request while NFC is granted */ +# define SIM_SOPT6_MCC_MASK (0xffff << SIM_SOPT6_MCC_SHIFT) +# define SIM_SOPT6_MCC(n) (((n) & 0xffff) << SIM_SOPT6_MCC_SHIFT) +# endif + /* Bits 16-23: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT6_PCR) + /* Bits 20-23: Reserved */ +# define SIM_SOPT6_PCR_SHIFT (16) /* Bits 16-19: FlexBus hold cycles before FlexBus can release bus to NFC or to IDLE */ +# define SIM_SOPT6_PCR_MASK (7 << SIM_SOPT6_PCR_SHIFT) +# define SIM_SOPT6_PCR(n) (((n) & 7) << SIM_SOPT6_PCR_SHIFT) +# endif +# if defined(KINETIS_SIM_HAS_SOPT6_RSTFLTSEL) +# define SIM_SOPT6_RSTFLTSEL_SHIFT (24) /* Bits 24-28: Reset pin filter select */ +# define SIM_SOPT6_RSTFLTSEL_MASK (31 << SIM_SOPT6_RSTFLTSEL_SHIFT) +# define SIM_SOPT6_RSTFLTSEL(n) ((uint32_t)((n)-1) << SIM_SOPT6_RSTFLTSEL_SHIFT) /* n=1..32 */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT6_RSTFLTEN) +# define SIM_SOPT6_RSTFLTEN_SHIFT (29) /* Bits 29-31: Reset pin filter enable */ +# define SIM_SOPT6_RSTFLTEN_MASK (7 << SIM_SOPT6_RSTFLTEN_SHIFT) +# define SIM_SOPT6_RSTFLTEN_DISABLED (0 << SIM_SOPT6_RSTFLTEN_SHIFT) /* All filtering disabled */ +# define SIM_SOPT6_RSTFLTEN_BUSCLK1 (1 << SIM_SOPT6_RSTFLTEN_SHIFT) /* Bus clock filter enabled (normal); LPO clock filter enabled (stop) */ +# define SIM_SOPT6_RSTFLTEN_LPO1 (2 << SIM_SOPT6_RSTFLTEN_SHIFT) /* LPO clock filter enabled */ +# define SIM_SOPT6_RSTFLTEN_BUSCLK2 (3 << SIM_SOPT6_RSTFLTEN_SHIFT) /* Bus clock filter enabled (normal); All filtering disabled (stop) */ +# define SIM_SOPT6_RSTFLTEN_LPO2 (4 << SIM_SOPT6_RSTFLTEN_SHIFT) /* PO clock filter enabled (normal); All filtering disabled (stop) */ +# endif +#endif /* System Options Register 7 */ -#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0) /* Bits 0-3: ADC0 trigger select */ -#define SIM_SOPT7_ADC0TRGSEL_MASK (15 << SIM_SOPT7_ADC0TRGSEL_SHIFT) -# define SIM_SOPT7_ADC0TRGSEL_PDB (0 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PDB external trigger (PDB0_EXTRG) */ -# define SIM_SOPT7_ADC0TRGSEL_CMP0 (1 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* High speed comparator 0 output */ -# define SIM_SOPT7_ADC0TRGSEL_CMP1 (2 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* High speed comparator 1 output */ -# define SIM_SOPT7_ADC0TRGSEL_CMP2 (3 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* High speed comparator 2 output */ -# define SIM_SOPT7_ADC0TRGSEL_PIT0 (4 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 0 */ -# define SIM_SOPT7_ADC0TRGSEL_PIT1 (5 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 1 */ -# define SIM_SOPT7_ADC0TRGSEL_PIT2 (6 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 2 */ -# define SIM_SOPT7_ADC0TRGSEL_PIT3 (7 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 3 */ -# define SIM_SOPT7_ADC0TRGSEL_FTM0 (8 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM0 trigger */ -# define SIM_SOPT7_ADC0TRGSEL_FTM1 (9 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM1 trigger */ -# define SIM_SOPT7_ADC0TRGSEL_FTM2 (10 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM2 trigger */ -#if defined(CONFIG_KINETIS_FTM3) -# define SIM_SOPT7_ADC0TRGSEL_FTM3 (11 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM3 trigger */ +#if defined(KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL) +# define SIM_SOPT7_ADC0TRGSEL_SHIFT (0) /* Bits 0-3: ADC0 trigger select */ +# define SIM_SOPT7_ADC0TRGSEL_MASK (15 << SIM_SOPT7_ADC0TRGSEL_SHIFT) +# define SIM_SOPT7_ADC0TRGSEL_PDB (0 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PDB external trigger (PDB0_EXTRG) */ +# define SIM_SOPT7_ADC0TRGSEL_CMP0 (1 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* High speed comparator 0 output */ +# define SIM_SOPT7_ADC0TRGSEL_CMP1 (2 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* High speed comparator 1 output */ +# define SIM_SOPT7_ADC0TRGSEL_CMP2 (3 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* High speed comparator 2 output */ +# define SIM_SOPT7_ADC0TRGSEL_PIT0 (4 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 0 */ +# define SIM_SOPT7_ADC0TRGSEL_PIT1 (5 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 1 */ +# define SIM_SOPT7_ADC0TRGSEL_PIT2 (6 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 2 */ +# define SIM_SOPT7_ADC0TRGSEL_PIT3 (7 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 3 */ +# define SIM_SOPT7_ADC0TRGSEL_FTM0 (8 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM0 trigger */ +# define SIM_SOPT7_ADC0TRGSEL_FTM1 (9 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM1 trigger */ +# define SIM_SOPT7_ADC0TRGSEL_FTM2 (10 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM2 trigger */ +# if KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL > 10 && defined(KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC) +# define SIM_SOPT7_ADC0TRGSEL_FTM3 (11 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM3 trigger */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL > 11 +# define SIM_SOPT7_ADC0TRGSEL_ALARM (12 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* RTC alarm */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL > 12 +# define SIM_SOPT7_ADC0TRGSEL_SECS (13 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* RTC seconds */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL > 13 +# define SIM_SOPT7_ADC0TRGSEL_LPTMR (14 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* Low-power timer trigger */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL > 14 +# define SIM_SOPT7_ADC0TRGSEL_TPM1CH0 (15 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* TPM1 channel 0 (A pretrigger) and channel 1 (B pretrigger) */ +# endif #endif -# define SIM_SOPT7_ADC0TRGSEL_ALARM (12 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* RTC alarm */ -# define SIM_SOPT7_ADC0TRGSEL_SECS (13 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* RTC seconds */ -# define SIM_SOPT7_ADC0TRGSEL_LPTMR (14 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* Low-power timer trigger */ -#define SIM_SOPT7_ADC0PRETRGSEL (1 << 4) /* Bit 4: ADC0 pretrigger select */ - /* Bits 5-6: Reserved */ -#define SIM_SOPT7_ADC0ALTTRGEN (1 << 7) /* Bit 7: ADC0 alternate trigger enable */ -#define SIM_SOPT7_ADC1TRGSEL_SHIFT (8) /* Bits 8-11: ADC1 trigger select */ -#define SIM_SOPT7_ADC1TRGSEL_MASK (15 << SIM_SOPT7_ADC1TRGSEL_SHIFT) -# define SIM_SOPT7_ADC1TRGSEL_PDB (0 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PDB external trigger (PDB0_EXTRG) */ -# define SIM_SOPT7_ADC1TRGSEL_CMP0 (1 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* High speed comparator 0 output */ -# define SIM_SOPT7_ADC1TRGSEL_CMP1 (2 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* High speed comparator 1 output */ -# define SIM_SOPT7_ADC1TRGSEL_CMP2 (3 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* High speed comparator 2 output */ -# define SIM_SOPT7_ADC1TRGSEL_PIT0 (4 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 0 */ -# define SIM_SOPT7_ADC1TRGSEL_PIT1 (5 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 1 */ -# define SIM_SOPT7_ADC1TRGSEL_PIT2 (6 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 2 */ -# define SIM_SOPT7_ADC1TRGSEL_PIT3 (7 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 3 */ -# define SIM_SOPT7_ADC1TRGSEL_FTM0 (8 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM0 trigger */ -# define SIM_SOPT7_ADC1TRGSEL_FTM1 (9 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM1 trigger */ -# define SIM_SOPT7_ADC1TRGSEL_FTM2 (10 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM2 trigger */ -# define SIM_SOPT7_ADC1TRGSEL_ALARM (12 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* RTC alarm */ -#if defined(CONFIG_KINETIS_FTM3) -# define SIM_SOPT7_ADC1TRGSEL_FTM3 (11 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM3 trigger */ +#if defined(KINETIS_SIM_HAS_SOPT7_ADC0PRETRGSEL) +# define SIM_SOPT7_ADC0PRETRGSEL (1 << 4) /* Bit 4: ADC0 pretrigger select */ #endif -# define SIM_SOPT7_ADC1TRGSEL_SECS (13 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* RTC seconds */ -# define SIM_SOPT7_ADC1TRGSEL_LPTMR (14 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* Low-power timer trigger */ -#define SIM_SOPT7_ADC1PRETRGSEL (1 << 12) /* Bit 12: ADC1 pre-trigger select */ - /* Bits 13-14: Reserved */ -#define SIM_SOPT7_ADC1ALTTRGEN (1 << 15) /* Bit 15: ADC1 alternate trigger enable */ - /* Bits 16-31: Reserved */ + /* Bits 5-6: Reserved */ +#if defined(KINETIS_SIM_SOPT7_ADC0ALTTRGEN) +# define SIM_SOPT7_ADC0ALTTRGEN (1 << 7) /* Bit 7: ADC0 alternate trigger enable */ +#endif + +#if defined(KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL) +# define SIM_SOPT7_ADC1TRGSEL_SHIFT (8) /* Bits 8-11: ADC1 trigger select */ +# define SIM_SOPT7_ADC1TRGSEL_MASK (15 << SIM_SOPT7_ADC1TRGSEL_SHIFT) +# define SIM_SOPT7_ADC1TRGSEL_PDB (0 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PDB external trigger (PDB0_EXTRG) */ +# define SIM_SOPT7_ADC1TRGSEL_CMP0 (1 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* High speed comparator 0 output */ +# define SIM_SOPT7_ADC1TRGSEL_CMP1 (2 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* High speed comparator 1 output */ +# define SIM_SOPT7_ADC1TRGSEL_CMP2 (3 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* High speed comparator 2 output */ +# define SIM_SOPT7_ADC1TRGSEL_PIT0 (4 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 0 */ +# define SIM_SOPT7_ADC1TRGSEL_PIT1 (5 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 1 */ +# define SIM_SOPT7_ADC1TRGSEL_PIT2 (6 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 2 */ +# define SIM_SOPT7_ADC1TRGSEL_PIT3 (7 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 3 */ +# define SIM_SOPT7_ADC1TRGSEL_FTM0 (8 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM0 trigger */ +# define SIM_SOPT7_ADC1TRGSEL_FTM1 (9 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM1 trigger */ +# define SIM_SOPT7_ADC1TRGSEL_FTM2 (10 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM2 trigger */ +# define SIM_SOPT7_ADC1TRGSEL_ALARM (12 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* RTC alarm */ +# if KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL > 10 && defined(KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC) +# define SIM_SOPT7_ADC1TRGSEL_FTM3 (11 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM3 trigger */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL > 11 +# define SIM_SOPT7_ADC1TRGSEL_ALARM (12 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* RTC alarm */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL > 12 +# define SIM_SOPT7_ADC1TRGSEL_SECS (13 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* RTC seconds */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL > 13 +# define SIM_SOPT7_ADC1TRGSEL_LPTMR (14 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* Low-power timer trigger */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL > 14 +# define SIM_SOPT7_ADC1TRGSEL_TPM2CH0 (15 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* TPM2 channel 0 (A pretrigger) and channel 1 (B pretrigger) */ +# endif +#endif +#if defined(KINETIS_SIM_HAS_SOPT7_ADC1PRETRGSEL) +# define SIM_SOPT7_ADC1PRETRGSEL (1 << 12) /* Bit 12: ADC1 pre-trigger select */ +#endif + /* Bits 13-14: Reserved */ +#if defined(KINETIS_SIM_SOPT7_ADC1ALTTRGEN) +# define SIM_SOPT7_ADC1ALTTRGEN (1 << 15) /* Bit 15: ADC1 alternate trigger enable */ +#endif + /* Bits 16-31: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL) +# define SIM_SOPT7_ADC2TRGSEL_SHIFT (16) /* Bits 16-19: ADC2 trigger select */ +# define SIM_SOPT7_ADC2TRGSEL_MASK (15 << SIM_SOPT7_ADC2TRGSEL_SHIFT) +# define SIM_SOPT7_ADC2TRGSEL_PDB (0 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* PDB external trigger (PDB0_EXTRG) */ +# define SIM_SOPT7_ADC2TRGSEL_CMP0 (1 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* High speed comparator 0 output */ +# define SIM_SOPT7_ADC2TRGSEL_CMP1 (2 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* High speed comparator 1 output */ +# define SIM_SOPT7_ADC2TRGSEL_CMP2 (3 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* High speed comparator 2 output */ +# define SIM_SOPT7_ADC2TRGSEL_PIT0 (4 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* PIT trigger 0 */ +# define SIM_SOPT7_ADC2TRGSEL_PIT1 (5 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* PIT trigger 1 */ +# define SIM_SOPT7_ADC2TRGSEL_PIT2 (6 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* PIT trigger 2 */ +# define SIM_SOPT7_ADC2TRGSEL_PIT3 (7 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* PIT trigger 3 */ +# define SIM_SOPT7_ADC2TRGSEL_FTM0 (8 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* FTM0 trigger */ +# define SIM_SOPT7_ADC2TRGSEL_FTM1 (9 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* FTM1 trigger */ +# define SIM_SOPT7_ADC2TRGSEL_FTM2 (10 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* FTM2 trigger */ +# if KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL > 10 && defined(KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC) +# define SIM_SOPT7_ADC2TRGSEL_FTM3 (11 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* FTM3 trigger */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL > 11 +# define SIM_SOPT7_ADC2TRGSEL_ALARM (12 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* RTC alarm */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL > 12 +# define SIM_SOPT7_ADC2TRGSEL_SECS (13 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* RTC seconds */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL > 13 +# define SIM_SOPT7_ADC2TRGSEL_LPTMR (14 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* Low-power timer trigger */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL > 14 +# define SIM_SOPT7_ADC2TRGSEL_CMP3 (15 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* High speed comparator 3 asynchronous interrupt */ +# endif +#endif +#if defined(KINETIS_SIM_HAS_SOPT7_ADC2PRETRGSEL) +# define SIM_SOPT7_ADC2PRETRGSEL (1 << 20) /* Bit 20: ADC2 pretrigger select */ +#endif + /* Bits 21-22: Reserved */ +#if defined(KINETIS_SIM_SOPT7_ADC2ALTTRGEN) +# define SIM_SOPT7_ADC2ALTTRGEN (1 << 23) /* Bit 23: ADC2 alternate trigger enable */ +#endif + /* Bits 23-27: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL) +# define SIM_SOPT7_ADC3TRGSEL_SHIFT (24) /* Bits 24-27: ADC3 trigger select */ +# define SIM_SOPT7_ADC3TRGSEL_MASK (15 << SIM_SOPT7_ADC3TRGSEL_SHIFT) +# define SIM_SOPT7_ADC3TRGSEL_PDB (0 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* PDB external trigger (PDB0_EXTRG) */ +# define SIM_SOPT7_ADC3TRGSEL_CMP0 (1 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* High speed comparator 0 output */ +# define SIM_SOPT7_ADC3TRGSEL_CMP1 (2 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* High speed comparator 1 output */ +# define SIM_SOPT7_ADC3TRGSEL_CMP2 (3 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* High speed comparator 2 output */ +# define SIM_SOPT7_ADC3TRGSEL_PIT0 (4 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* PIT trigger 0 */ +# define SIM_SOPT7_ADC3TRGSEL_PIT1 (5 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* PIT trigger 1 */ +# define SIM_SOPT7_ADC3TRGSEL_PIT2 (6 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* PIT trigger 2 */ +# define SIM_SOPT7_ADC3TRGSEL_PIT3 (7 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* PIT trigger 3 */ +# define SIM_SOPT7_ADC3TRGSEL_FTM0 (8 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* FTM0 trigger */ +# define SIM_SOPT7_ADC3TRGSEL_FTM1 (9 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* FTM1 trigger */ +# define SIM_SOPT7_ADC3TRGSEL_FTM2 (10 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* FTM2 trigger */ +# if KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL > 10 && defined(KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC) +# define SIM_SOPT7_ADC3TRGSEL_FTM3 (11 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* FTM3 trigger */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL > 11 +# define SIM_SOPT7_ADC3TRGSEL_ALARM (12 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* RTC alarm */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL > 12 +# define SIM_SOPT7_ADC3TRGSEL_SECS (13 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* RTC seconds */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL > 13 +# define SIM_SOPT7_ADC3TRGSEL_LPTMR (14 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* Low-power timer trigger */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL > 14 +# define SIM_SOPT7_ADC3TRGSEL_CMP3 (15 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* High speed comparator 3 asynchronous interrupt */ +# endif +#endif +#if defined(KINETIS_SIM_HAS_SOPT7_ADC3PRETRGSEL) +# define SIM_SOPT7_ADC3PRETRGSEL (1 << 28) /* Bit 28: ADC3 pretrigger select */ +#endif + /* Bits 29-30: Reserved */ +#if defined(KINETIS_SIM_SOPT7_ADC3ALTTRGEN) +# define SIM_SOPT7_ADC3ALTTRGEN (1 << 31) /* Bit 31: ADC3 alternate trigger enable */ +#endif + +#if defined(KINETIS_SIM_HAS_SOPT8) +/* System Options Register 8 */ + +# if defined(KINETIS_SIM_HAS_SOPT8_FTM0SYNCBIT) +# define SIM_SOPT8_FTM0SYNCBIT (1 << 0) /* Bit 0: FTM0 Hardware Trigger 0 Software Synchronization */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM1SYNCBIT) +# define SIM_SOPT8_FTM1SYNCBIT (1 << 1) /* Bit 1: FTM1 Hardware Trigger 0 Software Synchronization */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM2SYNCBIT) +# define SIM_SOPT8_FTM2SYNCBIT (1 << 2) /* Bit 2: FTM2 Hardware Trigger 0 Software Synchronization */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM3SYNCBIT) +# define SIM_SOPT8_FTM3SYNCBIT (1 << 3) /* Bit 3: FTM3 Hardware Trigger 0 Software Synchronization */ +# endif + /* Bits 4-15: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT8_FTM0OCH0SRC) +# define SIM_SOPT8_FTM0OCH0SRC (1 << 16) /* Bit 16: FTM0 channel 0 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM0OCH1SRC) +# define SIM_SOPT8_FTM0OCH1SRC (1 << 17) /* Bit 17: FTM0 channel 1 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM0OCH2SRC) +# define SIM_SOPT8_FTM0OCH2SRC (1 << 18) /* Bit 18: FTM0 channel 2 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM0OCH3SRC) +# define SIM_SOPT8_FTM0OCH3SRC (1 << 19) /* Bit 19: FTM0 channel 3 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM0OCH4SRC) +# define SIM_SOPT8_FTM0OCH4SRC (1 << 20) /* Bit 20: FTM0 channel 4 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM0OCH5SRC) +# define SIM_SOPT8_FTM0OCH5SRC (1 << 21) /* Bit 21: FTM0 channel 5 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM0OCH6SRC) +# define SIM_SOPT8_FTM0OCH6SRC (1 << 22) /* Bit 22: FTM0 channel 6 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM0OCH7SRC) +# define SIM_SOPT8_FTM0OCH7SRC (1 << 23) /* Bit 23: FTM0 channel 7 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM3OCH0SRC) +# define SIM_SOPT8_FTM3OCH0SRC (1 << 24) /* Bit 24: FTM3 channel 0 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM3OCH1SRC) +# define SIM_SOPT8_FTM3OCH1SRC (1 << 25) /* Bit 25: FTM3 channel 1 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM3OCH2SRC) +# define SIM_SOPT8_FTM3OCH2SRC (1 << 26) /* Bit 26: FTM3 channel 2 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM3OCH3SRC) +# define SIM_SOPT8_FTM3OCH3SRC (1 << 27) /* Bit 27: FTM3 channel 3 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM3OCH4SRC) +# define SIM_SOPT8_FTM3OCH4SRC (1 << 28) /* Bit 28: FTM3 channel 4 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM3OCH5SRC) +# define SIM_SOPT8_FTM3OCH5SRC (1 << 29) /* Bit 29: FTM3 channel 5 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM3OCH6SRC) +# define SIM_SOPT8_FTM3OCH6SRC (1 << 30) /* Bit 30: FTM3 channel 6 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM3OCH7SRC) +# define SIM_SOPT8_FTM3OCH7SRC (1 << 31) /* Bit 31: FTM3 channel 7 output source */ +# endif +#endif + +#if defined(KINETIS_SIM_HAS_SOPT9) +/* System Options Register 9 */ + + /* Bits 0-17: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT9_TPM1CH0SRC) +# define SIM_SOPT9_TPM1CH0SRC_SHIFT (18) /* Bits 18-19: TPM1 channel 0 input capture source select */ +# define SIM_SOPT9_TPM1CH0SRC_MASK (3 << SIM_SOPT9_TPM1CH0SRC_SHIFT) +# define SIM_SOPT9_TPM1CH0SRC_TMP1CH0 (0 << SIM_SOPT9_TPM1CH0SRC_SHIFT) +# define SIM_SOPT9_TPM1CH0SRC_CMP0 (1 << SIM_SOPT9_TPM1CH0SRC_SHIFT) +# define SIM_SOPT9_TPM1CH0SRC_CMP1 (2 << SIM_SOPT9_TPM1CH0SRC_SHIFT) +# endif +# if defined(KINETIS_SIM_HAS_SOPT9_TPM2CH0SRC) +# define SIM_SOPT9_TPM2CH0SRC_SHIFT (20) /* Bits 20-21 TPM2 channel 0 input capture source select */ +# define SIM_SOPT9_TPM2CH0SRC_MASK (3 << SIM_SOPT9_TPM2CH0SRC_SHIFT) +# define SIM_SOPT9_TPM2CH0SRC_TMP1CH0 (0 << SIM_SOPT9_TPM2CH0SRC_SHIFT) +# define SIM_SOPT9_TPM2CH0SRC_CMP0 (1 << SIM_SOPT9_TPM2CH0SRC_SHIFT) +# define SIM_SOPT9_TPM2CH0SRC_CMP1 (2 << SIM_SOPT9_TPM2CH0SRC_SHIFT) +# endif + /* Bits 22-24: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT9_TPM1CLKSEL) +# define SIM_SOPT9_TPM1CLKSEL (1 << 25) /* Bit 25: TPM1 External Clock Pin Select */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT9_TPM2CLKSEL) +# define SIM_SOPT9_TPM2CLKSEL (1 << 26) /* Bit 26: TPM2 External Clock Pin Select */ +# endif + /* Bits 27-31: Reserved */ +#endif + /* System Device Identification Register */ -#define SIM_SDID_PINID_SHIFT (0) /* Bits 0-3: Pincount identification */ -#define SIM_SDID_PINID_MASK (15 << SIM_SDID_PINID_SHIFT) -# define SIM_SDID_PINID_32PIN (2 << SIM_SDID_PINID_SHIFT) /* 32-pin */ -# define SIM_SDID_PINID_48PIN (4 << SIM_SDID_PINID_SHIFT) /* 48-pin */ -# define SIM_SDID_PINID_64PIN (5 << SIM_SDID_PINID_SHIFT) /* 64-pin */ -# define SIM_SDID_PINID_80PIN (6 << SIM_SDID_PINID_SHIFT) /* 80-pin */ -# define SIM_SDID_PINID_81PIN (7 << SIM_SDID_PINID_SHIFT) /* 81-pin */ -# define SIM_SDID_PINID_100PIN (8 << SIM_SDID_PINID_SHIFT) /* 100-pin */ -# define SIM_SDID_PINID_121PIN (9 << SIM_SDID_PINID_SHIFT) /* 121-pin */ -# define SIM_SDID_PINID_144PIN (10 << SIM_SDID_PINID_SHIFT) /* 144-pin */ -# define SIM_SDID_PINID_196PIN (12 << SIM_SDID_PINID_SHIFT) /* 196-pin */ -# define SIM_SDID_PINID_256PIN (14 << SIM_SDID_PINID_SHIFT) /* 256-pin */ -#define SIM_SDID_FAMID_SHIFT (4) /* Bits 4-6: Kinetis family identification */ -#define SIM_SDID_FAMID_MASK (7 << SIM_SDID_FAMID_SHIFT) -# define SIM_SDID_FAMID_K10 (0 << SIM_SDID_FAMID_SHIFT) /* K10 */ -# define SIM_SDID_FAMID_K20 (1 << SIM_SDID_FAMID_SHIFT)) /* K20 */ -# define SIM_SDID_FAMID_K30 (2 << SIM_SDID_FAMID_SHIFT)) /* K30 */ -# define SIM_SDID_FAMID_K40 (3 << SIM_SDID_FAMID_SHIFT)) /* K40 */ -# define SIM_SDID_FAMID_K60 (4 << SIM_SDID_FAMID_SHIFT)) /* K60 */ -# define SIM_SDID_FAMID_K70 (5 << SIM_SDID_FAMID_SHIFT)) /* K70 */ -# define SIM_SDID_FAMID_K50 (6 << SIM_SDID_FAMID_SHIFT)) /* K50 and K52 */ -# define SIM_SDID_FAMID_K51 (7 << SIM_SDID_FAMID_SHIFT)) /* K51 and K53 */ - /* Bits 7-11: Reserved */ -#define SIM_SDID_REVID_SHIFT (12) /* Bits 12-15: Device revision number */ -#define SIM_SDID_REVID_MASK (15 << SIM_SDID_REVID_SHIFT) - /* Bits 16-31: Reserved */ +#define SIM_SDID_PINID_SHIFT (0) /* Bits 0-3: Pincount identification */ +#define SIM_SDID_PINID_MASK (15 << SIM_SDID_PINID_SHIFT) +# define SIM_SDID_PINID_32PIN (2 << SIM_SDID_PINID_SHIFT) /* 32-pin */ +# define SIM_SDID_PINID_48PIN (4 << SIM_SDID_PINID_SHIFT) /* 48-pin */ +# define SIM_SDID_PINID_64PIN (5 << SIM_SDID_PINID_SHIFT) /* 64-pin */ +# define SIM_SDID_PINID_80PIN (6 << SIM_SDID_PINID_SHIFT) /* 80-pin */ +# define SIM_SDID_PINID_81PIN (7 << SIM_SDID_PINID_SHIFT) /* 81-pin */ +# define SIM_SDID_PINID_100PIN (8 << SIM_SDID_PINID_SHIFT) /* 100-pin */ +# define SIM_SDID_PINID_121PIN (9 << SIM_SDID_PINID_SHIFT) /* 121-pin */ +# define SIM_SDID_PINID_144PIN (10 << SIM_SDID_PINID_SHIFT) /* 144-pin */ +# define SIM_SDID_PINID_196PIN (12 << SIM_SDID_PINID_SHIFT) /* 196-pin */ +# define SIM_SDID_PINID_256PIN (14 << SIM_SDID_PINID_SHIFT) /* 256-pin */ +#if defined(KINETIS_SIM_HAS_SDID_FAMID) +# if !defined(KINETIS_SIM_HAS_SDID_FAMILYID) +# define SIM_SDID_FAMID_SHIFT (4) /* Bits 4-6: Kinetis family identification */ +# define SIM_SDID_FAMID_MASK (7 << SIM_SDID_FAMID_SHIFT) +# define SIM_SDID_FAMID_K10 (0 << SIM_SDID_FAMID_SHIFT) /* K10 */ +# define SIM_SDID_FAMID_K20 (1 << SIM_SDID_FAMID_SHIFT)) /* K20 */ +# define SIM_SDID_FAMID_K30 (2 << SIM_SDID_FAMID_SHIFT)) /* K30 */ +# define SIM_SDID_FAMID_K40 (3 << SIM_SDID_FAMID_SHIFT)) /* K40 */ +# define SIM_SDID_FAMID_K60 (4 << SIM_SDID_FAMID_SHIFT)) /* K60 */ +# define SIM_SDID_FAMID_K70 (5 << SIM_SDID_FAMID_SHIFT)) /* K70 */ +# define SIM_SDID_FAMID_K50 (6 << SIM_SDID_FAMID_SHIFT)) /* K50 and K52 */ +# define SIM_SDID_FAMID_K51 (7 << SIM_SDID_FAMID_SHIFT)) /* K51 and K53 */ +# else +# define SIM_SDID_FAMID_K1X (0 << SIM_SDID_FAMID_SHIFT) /* K1X */ +# define SIM_SDID_FAMID_K2X (1 << SIM_SDID_FAMID_SHIFT)) /* K2X */ +# define SIM_SDID_FAMID_K3X (2 << SIM_SDID_FAMID_SHIFT)) /* K3X */ +# define SIM_SDID_FAMID_K4X (3 << SIM_SDID_FAMID_SHIFT)) /* K4X */ +# define SIM_SDID_FAMID_K6X (4 << SIM_SDID_FAMID_SHIFT)) /* K6X */ +# define SIM_SDID_FAMID_K7X (5 << SIM_SDID_FAMID_SHIFT)) /* K7X */ +# endif +#endif + /* Bits 7-11: Reserved */ +#if defined(KINETIS_SIM_HAS_SDID_DIEID) +# define SIM_SDID_DIEID_SHIFT (7) /* Bits 7-11: Device Die ID */ +# define SIM_SDID_DIEID_MASK (31 < SIM_SDID_DIEID_SHIFT) +#endif + +#define SIM_SDID_REVID_SHIFT (12) /* Bits 12-15: Device revision number */ +#define SIM_SDID_REVID_MASK (15 << SIM_SDID_REVID_SHIFT) + /* Bits 16-31: Reserved */ +#if defined(KINETIS_SIM_HAS_SDID_SRAMSIZE) +# define SIM_SDID_SRAMSIZE_SHIFT (16) /* Bits 16-19: SRAM Size */ +# define SIM_SDID_SRAMSIZE_MASK (15 < SIM_SDID_SRAMSIZE_SHIFT) +#endif +#if defined(KINETIS_SIM_HAS_SDID_SERIESID) +# define SIM_SDID_SERIESID_SHIFT (20) /* Bits 20-23: Kinetis Series ID */ +# define SIM_SDID_SERIESID_MASK (15 << SIM_SDID_SERIESID_SHIFT) +# define SIM_SDID_SERIESID_K (0 << SIM_SDID_SERIESID_SHIFT) /* Kinetis K series */ +# define SIM_SDID_SERIESID_L (1 << SIM_SDID_SERIESID_SHIFT) /* Kinetis L series */ +# define SIM_SDID_SERIESID_W (5 << SIM_SDID_SERIESID_SHIFT) /* Kinetis W series */ +# define SIM_SDID_SERIESID_V (6 << SIM_SDID_SERIESID_SHIFT) /* Kinetis V series */ +#endif +#if defined(KINETIS_SIM_HAS_SDID_SUBFAMID) +# define SIM_SDID_SUBFAMID_SHIFT (24) /* Bits 24-27: Kinetis Sub-Family ID */ +# define SIM_SDID_SUBFAMID_MASK (15 << SIM_SDID_SUBFAMID_SHIFT) +# define SIM_SDID_SUBFAMID_KX0 (0 << SIM_SDID_SUBFAMID_SHIFT) /* Kx0 Subfamily */ +# define SIM_SDID_SUBFAMID_KX1 (1 << SIM_SDID_SUBFAMID_SHIFT) /* Kx1 Subfamily (tamper detect) */ +# define SIM_SDID_SUBFAMID_KX2 (2 << SIM_SDID_SUBFAMID_SHIFT) /* Kx2 Subfamily */ +# define SIM_SDID_SUBFAMID_KX3 (3 << SIM_SDID_SUBFAMID_SHIFT) /* Kx3 Subfamily (tamper detect) */ +# define SIM_SDID_SUBFAMID_KX4 (4 << SIM_SDID_SUBFAMID_SHIFT) /* Kx4 Subfamily */ +# define SIM_SDID_SUBFAMID_KX5 (5 << SIM_SDID_SUBFAMID_SHIFT) /* Kx5 Subfamily (tamper detect) */ +# define SIM_SDID_SUBFAMID_KX6 (6 << SIM_SDID_SUBFAMID_SHIFT) /* Kx6 Subfamily */ +#endif +#if defined(KINETIS_SIM_HAS_SDID_FAMILYID) +# define SIM_SDID_FAMILYID_SHIFT (28) /* Bits 28-31: Kinetis Family ID */ +# define SIM_SDID_FAMILYID_MASK (15 << SIM_SDID_FAMILYID_SHIFT) +# define SIM_SDID_FAMILYID_K0X (0 << SIM_SDID_FAMILYID_SHIFT) /* K0x Family */ +# define SIM_SDID_FAMILYID_K1X (1 << SIM_SDID_FAMILYID_SHIFT) /* K1x Family */ +# define SIM_SDID_FAMILYID_K2X (2 << SIM_SDID_FAMILYID_SHIFT) /* K2x Family */ +# define SIM_SDID_FAMILYID_K3X (3 << SIM_SDID_FAMILYID_SHIFT) /* K3x Family */ +# define SIM_SDID_FAMILYID_K4X (4 << SIM_SDID_FAMILYID_SHIFT) /* K4x Family */ +# define SIM_SDID_FAMILYID_K6X (6 << SIM_SDID_FAMILYID_SHIFT) /* K6x Family */ +# define SIM_SDID_FAMILYID_K7X (7 << SIM_SDID_FAMILYID_SHIFT) /* K7x Family */ +# define SIM_SDID_FAMILYID_K8X (8 << SIM_SDID_FAMILYID_SHIFT) /* K8x Family */ +#endif + + /* System Clock Gating Control Register 1 */ - /* Bits 0-9: Reserved */ -#define SIM_SCGC1_UART4 (1 << 10) /* Bit 10: UART4 Clock Gate Control */ -#define SIM_SCGC1_UART5 (1 << 11) /* Bit 11: UART5 Clock Gate Control */ - /* Bits 12-31: Reserved */ + +#if defined(KINETIS_SIM_HAS_SCGC1) + /* Bits 0-9: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC1_OSC1) + /* Bits 0-4: Reserved */ +# define SIM_SCGC1_OSC1 (1 << 5) /* OSC1 clock gate control */ +# endif + /* Bits 6-9: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC1_I2C2) +# define SIM_SCGC1_I2C2 (1 << 6) /* Bit 6: I2C2 Clock Gate Control */ +# endif + /* Bits 7-9: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC1_I2C3) +# define SIM_SCGC1_I2C3 (1 << 7) /* Bit 7: I2C3 Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC1_UART4) +# define SIM_SCGC1_UART4 (1 << 10) /* Bit 10: UART4 Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC1_UART5) +# define SIM_SCGC1_UART5 (1 << 11) /* Bit 11: UART5 Clock Gate Control */ +# endif + /* Bits 12-31: Reserved */ +#endif + +#if defined(KINETIS_SIM_HAS_SCGC2) /* System Clock Gating Control Register 2 */ -#if defined(KINETIS_NENET) && KINETIS_NENET > 0 -# define SIM_SCGC2_ENET (1 << 0) /* Bit 0: ENET Clock Gate Control (K60) */ +# if defined(KINETIS_SIM_HAS_SCGC2_ENET) && defined(KINETIS_NENET) && KINETIS_NENET > 0 +# define SIM_SCGC2_ENET (1 << 0) /* Bit 0: ENET Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC2_LPUART0) +# define SIM_SCGC2_LPUART0 (1 << 4) /* Bit 4: LPUART0 Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC2_TPM1) +# define SIM_SCGC2_TPM1 (1 << 9) /* Bit 9: TPM1 Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC2_TPM2) +# define SIM_SCGC2_TPM2 (1 << 10) /* Bit 10: TPM2 Clock Gate Control */ +# endif +# define SIM_SCGC2_DAC0 (1 << 12) /* Bit 12: DAC0 Clock Gate Control */ +# define SIM_SCGC2_DAC1 (1 << 13) /* Bit 13: DAC1 Clock Gate Control */ + /* Bits 14-31: Reserved */ #endif - /* Bits 1-11: Reserved */ -#define SIM_SCGC2_DAC0 (1 << 12) /* Bit 12: DAC0 Clock Gate Control */ -#define SIM_SCGC2_DAC1 (1 << 13) /* Bit 13: DAC1 Clock Gate Control */ - /* Bits 14-31: Reserved */ + +#if defined(KINETIS_SIM_HAS_SCGC3) /* System Clock Gating Control Register 3 */ -#if defined(KINETIS_NRNG) && KINETIS_NRNG > 0 -# define SIM_SCGC3_RNGB (1 << 0) /* Bit 0: RNGB Clock Gate Control (K60) */ +# if defined(KINETIS_SIM_HAS_SCGC3_RNGA) && defined(KINETIS_NRNG) && KINETIS_NRNG > 0 +# define SIM_SCGC3_RNGA (1 << 0) /* Bit 0: RNGB Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC3_USBHS) +# define SIM_SCGC3_USBHS (1 << 1) /* Bit 1: USBHS Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC3_USBHSPHY) +# define SIM_SCGC3_USBHSPHY (1 << 2) /* Bit 2: USBHS PHY Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC3_USBHSDCD) +# define SIM_SCGC3_USBHSDCD (1 << 3) /* Bit 3: USBHS DCD Clock Gate Control */ +# endif + /* Bits 5-11: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC3_FLEXCAN1) +# define SIM_SCGC3_FLEXCAN1 (1 << 4) /* Bit 4: FlexCAN1 Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC3_NFC) +# define SIM_SCGC3_FLEXCAN1 (1 << 8) /* Bit 8: NFC Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC3_SPI2) +# define SIM_SCGC3_SPI2 (1 << 12) /* Bit 12: SPI2 Clock Gate Control */ +# endif + /* Bits 13-14: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC3_SAI1) +# define SIM_SCGC3_SAI1 (1 << 15) /* Bit 15: SAI1 clock Gate control */ +# endif + /* Bit 16: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC3_SDHC) +# define SIM_SCGC3_SDHC (1 << 17) /* Bit 17: SDHC Clock Gate Control */ +# endif + /* Bits 18-23: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC3_FTM2) +# define SIM_SCGC3_FTM2 (1 << 24) /* Bit 24: FTM2 Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC3_FTM3) && defined(KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC) +# define SIM_SCGC3_FTM3 (1 << 25) /* Bit 25: RFTM3 Clock Gate Control */ +# endif + /* Bit 26: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC3_ADC1) +# define SIM_SCGC3_ADC1 (1 << 27) /* Bit 27: ADC1 Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC3_ADC3) +# define SIM_SCGC3_ADC3 (1 << 28) /* Bit 28: ADC3 Clock Gate Control */ +# endif + /* Bit 29: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC3_SLCD) && defined(KINETIS_NSLCD) && KINETIS_NSLCD > 0 +# define SIM_SCGC3_SLCD (1 << 30) /* Bit 30: Segment LCD Clock Gate Control */ +# endif + /* Bit 31: Reserved */ #endif - /* Bits 1-3: Reserved */ -#define SIM_SCGC3_FLEXCAN1 (1 << 4) /* Bit 4: FlexCAN1 Clock Gate Control */ - /* Bits 5-11: Reserved */ -#define SIM_SCGC3_SPI2 (1 << 12) /* Bit 12: SPI2 Clock Gate Control */ - /* Bits 13-16: Reserved */ -#define SIM_SCGC3_SDHC (1 << 17) /* Bit 17: SDHC Clock Gate Control */ - /* Bits 18-23: Reserved */ -#define SIM_SCGC3_FTM2 (1 << 24) /* Bit 24: FTM2 Clock Gate Control */ - /* Bits 25-26: Reserved */ -#if defined(CONFIG_KINETIS_FTM3) -# define SIM_SCGC3_FTM3 (1 << 25) /* Bit 25: FTM3 Clock Gate Control */ -#endif -#define SIM_SCGC3_ADC1 (1 << 27) /* Bit 27: ADC1 Clock Gate Control */ - /* Bits 28-29: Reserved */ -#if defined(KINETIS_NSLCD) && KINETIS_NSLCD > 0 -# define SIM_SCGC3_SLCD (1 << 30) /* Bit 30: Segment LCD Clock Gate Control (K40) */ -#endif - /* Bit 31: Reserved */ + /* System Clock Gating Control Register 4 */ - /* Bit 0: Reserved */ -#define SIM_SCGC4_EWM (1 << 1) /* Bit 1: EWM Clock Gate Control */ -#define SIM_SCGC4_CMT (1 << 2) /* Bit 2: CMT Clock Gate Control */ - /* Bits 3-5: Reserved */ -#define SIM_SCGC4_I2C0 (1 << 6) /* Bit 6: I2C0 Clock Gate Control */ -#define SIM_SCGC4_I2C1 (1 << 7) /* Bit 7: I2C1 Clock Gate Control */ - /* Bits 8-9: Reserved */ -#define SIM_SCGC4_UART0 (1 << 10) /* Bit 10: UART0 Clock Gate Control */ -#define SIM_SCGC4_UART1 (1 << 11) /* Bit 11: UART1 Clock Gate Control */ -#define SIM_SCGC4_UART2 (1 << 12) /* Bit 12: UART2 Clock Gate Control */ -#define SIM_SCGC4_UART3 (1 << 13) /* Bit 13: UART3 Clock Gate Control */ - /* Bits 14-17: Reserved */ -#define SIM_SCGC4_USBOTG (1 << 18) /* Bit 18: USB Clock Gate Control */ -#define SIM_SCGC4_CMP (1 << 19) /* Bit 19: Comparator Clock Gate Control */ -#define SIM_SCGC4_VREF (1 << 20) /* Bit 20: VREF Clock Gate Control */ - /* Bits 21-17: Reserved */ -#define SIM_SCGC4_LLWU (1 << 28) /* Bit 28: LLWU Clock Gate Control */ + + /* Bit 0: Reserved */ +#define SIM_SCGC4_EWM (1 << 1) /* Bit 1: EWM Clock Gate Control */ +#define SIM_SCGC4_CMT (1 << 2) /* Bit 2: CMT Clock Gate Control */ + /* Bits 3-5: Reserved */ +#define SIM_SCGC4_I2C0 (1 << 6) /* Bit 6: I2C0 Clock Gate Control */ +#define SIM_SCGC4_I2C1 (1 << 7) /* Bit 7: I2C1 Clock Gate Control */ + /* Bits 8-9: Reserved */ +#if defined(KINETIS_SIM_HAS_SCGC4_UART0) +# define SIM_SCGC4_UART0 (1 << 10) /* Bit 10: UART0 Clock Gate Control */ +#endif +#if defined(KINETIS_SIM_HAS_SCGC4_UART1) +# define SIM_SCGC4_UART1 (1 << 11) /* Bit 11: UART1 Clock Gate Control */ +#endif +#if defined(KINETIS_SIM_HAS_SCGC4_UART2) +# define SIM_SCGC4_UART2 (1 << 12) /* Bit 12: UART2 Clock Gate Control */ +#endif +#if defined(KINETIS_SIM_HAS_SCGC4_UART3) +# define SIM_SCGC4_UART3 (1 << 13) /* Bit 13: UART3 Clock Gate Control */ +#endif + /* Bits 14-17: Reserved */ +#define SIM_SCGC4_USBOTG (1 << 18) /* Bit 18: USB Clock Gate Control */ +#define SIM_SCGC4_CMP (1 << 19) /* Bit 19: Comparator Clock Gate Control */ +#define SIM_SCGC4_VREF (1 << 20) /* Bit 20: VREF Clock Gate Control */ + /* Bits 21-17: Reserved */ +#if defined(KINETIS_SIM_HAS_SCGC4_LLWU) +# define SIM_SCGC4_LLWU (1 << 28) /* Bit 28: LLWU Clock Gate Control */ +#endif /* Bits 29-31: Reserved */ + /* System Clock Gating Control Register 5 */ -#define SIM_SCGC5_LPTIMER (1 << 0) /* Bit 0: Low Power Timer Clock Gate Control */ -#define SIM_SCGC5_REGFILE (1 << 1) /* Bit 1: Register File Clock Gate Control */ - /* Bits 2-4: Reserved */ -#define SIM_SCGC5_TSI (1 << 5) /* Bit 5: TSI Clock Gate Control */ - /* Bits 6-8: Reserved */ -#define SIM_SCGC5_PORTA (1 << 9) /* Bit 9: Port A Clock Gate Control */ -#define SIM_SCGC5_PORTB (1 << 10) /* Bit 10: Port B Clock Gate Control */ -#define SIM_SCGC5_PORTC (1 << 11) /* Bit 11: Port C Clock Gate Control */ -#define SIM_SCGC5_PORTD (1 << 12) /* Bit 12: Port D Clock Gate Control */ -#define SIM_SCGC5_PORTE (1 << 13) /* Bit 13: Port E Clock Gate Control */ +#define SIM_SCGC5_LPTIMER (1 << 0) /* Bit 0: Low Power Timer Clock Gate Control */ +#if defined(KINETIS_SIM_HAS_SCGC5_REGFILE) +# define SIM_SCGC5_REGFILE (1 << 1) /* Bit 1: Register File Clock Gate Control */ +#endif + /* Bits 2-4: Reserved */ +#if defined(KINETIS_SIM_HAS_SCGC5_TSI) +# define SIM_SCGC5_TSI (1 << 5) /* Bit 5: TSI Clock Gate Control */ +#endif + /* Bits 6-8: Reserved */ +#define SIM_SCGC5_PORTA (1 << 9) /* Bit 9: Port A Clock Gate Control */ +#define SIM_SCGC5_PORTB (1 << 10) /* Bit 10: Port B Clock Gate Control */ +#define SIM_SCGC5_PORTC (1 << 11) /* Bit 11: Port C Clock Gate Control */ +#define SIM_SCGC5_PORTD (1 << 12) /* Bit 12: Port D Clock Gate Control */ +#define SIM_SCGC5_PORTE (1 << 13) /* Bit 13: Port E Clock Gate Control */ +#if defined(KINETIS_SIM_HAS_SCGC5_PORTF) +# define SIM_SCGC5_PORTF (1 << 14) /* Bit 14: Port F Clock Gate Control */ +#endif /* Bits 14-31: Reserved */ /* System Clock Gating Control Register 6 */ +#if defined(KINETIS_SIM_HAS_SCGC6_FTFL) +# define SIM_SCGC6_FTFL (1 << 0) /* Bit 0: Flash Memory Clock Gate Control */ +#endif +#define SIM_SCGC6_DMAMUX0 (1 << 1) /* Bit 1: DMA Mux 0 Clock Gate Control */ + /* Bits 2-3: Reserved */ +#if defined(KINETIS_SIM_HAS_SCGC6_DMAMUX1) +# define SIM_SCGC6_DMAMUX1 (1 << 2) /* Bit 2: DMA Mux 1 Clock Gate Control */ +#endif +#define SIM_SCGC6_FLEXCAN0 (1 << 4) /* Bit 4: FlexCAN0 Clock Gate Control */ + /* Bits 5-9: Reserved */ -#define SIM_SCGC6_FTFL (1 << 0) /* Bit 0: Flash Memory Clock Gate Control */ -#define SIM_SCGC6_DMAMUX (1 << 1) /* Bit 1: DMA Mux Clock Gate Control */ - /* Bits 2-3: Reserved */ -#define SIM_SCGC6_FLEXCAN0 (1 << 4) /* Bit 4: FlexCAN0 Clock Gate Control */ - /* Bits 5-11: Reserved */ -#define SIM_SCGC6_SPI0 (1 << 12) /* Bit 12: SPI0 Clock Gate Control */ -#define SIM_SCGC6_SPI1 (1 << 13) /* Bit 13: SPI1 Clock Gate Control */ - /* Bit 14: Reserved */ -#define SIM_SCGC6_I2S (1 << 15) /* Bit 15: I2S Clock Gate Control */ - /* Bits 16-17: Reserved */ -#define SIM_SCGC6_CRC (1 << 18) /* Bit 18: CRC Clock Gate Control */ - /* Bits 19-20: Reserved */ -#define SIM_SCGC6_USBDCD (1 << 21) /* Bit 21: USB DCD Clock Gate Control */ -#define SIM_SCGC6_PDB (1 << 22) /* Bit 22: PDB Clock Gate Control */ -#define SIM_SCGC6_PIT (1 << 23) /* Bit 23: PIT Clock Gate Control */ -#define SIM_SCGC6_FTM0 (1 << 24) /* Bit 24: FTM0 Clock Gate Control */ -#define SIM_SCGC6_FTM1 (1 << 25) /* Bit 25: FTM1 Clock Gate Control */ - /* Bit 26: Reserved */ -#define SIM_SCGC6_ADC0 (1 << 27) /* Bit 27: ADC0 Clock Gate Control */ - /* Bit 28: Reserved */ -#define SIM_SCGC6_RTC (1 << 29) /* Bit 29: RTC Clock Gate Control */ - /* Bits 30-31: Reserved */ +#if defined(KINETIS_SIM_HAS_SCGC6_RNGA) +# define SIM_SCGC6_RNGA (1 << 9) /* Bit 9: SPI0 Clock Gate Control */ +#endif + /* Bits 10-11: Reserved */ +#define SIM_SCGC6_SPI0 (1 << 12) /* Bit 12: SPI0 Clock Gate Control */ +#define SIM_SCGC6_SPI1 (1 << 13) /* Bit 13: SPI1 Clock Gate Control */ + /* Bit 14: Reserved */ +#define SIM_SCGC6_I2S (1 << 15) /* Bit 15: I2S Clock Gate Control */ + /* Bits 16-17: Reserved */ +#define SIM_SCGC6_CRC (1 << 18) /* Bit 18: CRC Clock Gate Control */ + /* Bits 19-20: Reserved */ +#if defined(KINETIS_SIM_HAS_SCGC6_USBHS) +# define SIM_SCGC6_USBHS (1 << 20) /* Bit 20: USB HS Clock Gate Control */ +#endif +#define SIM_SCGC6_USBDCD (1 << 21) /* Bit 21: USB DCD Clock Gate Control */ +#define SIM_SCGC6_PDB (1 << 22) /* Bit 22: PDB Clock Gate Control */ +#define SIM_SCGC6_PIT (1 << 23) /* Bit 23: PIT Clock Gate Control */ +#define SIM_SCGC6_FTM0 (1 << 24) /* Bit 24: FTM0 Clock Gate Control */ +#define SIM_SCGC6_FTM1 (1 << 25) /* Bit 25: FTM1 Clock Gate Control */ + /* Bit 26: Reserved */ +#if defined(KINETIS_SIM_HAS_SCGC6_FTM2) +# define SIM_SCGC6_FTM2 (1 << 26) /* Bit 26: FTM2 Clock Gate Control */ +#endif +#define SIM_SCGC6_ADC0 (1 << 27) /* Bit 27: ADC0 Clock Gate Control */ + /* Bit 28: Reserved */ +#if defined(KINETIS_SIM_HAS_SCGC6_ADC2) +# define SIM_SCGC6_ADC2 (1 << 28) /* Bit 28: ADC2 Clock Gate Control */ +#endif +#define SIM_SCGC6_RTC (1 << 29) /* Bit 29: RTC Clock Gate Control */ + /* Bits 30-31: Reserved */ +#if defined(KINETIS_SIM_HAS_SCGC6_DAC0) +# define SIM_SCGC6_DAC0 (1 << 31) /* Bit 31: RTC Clock Gate Control */ +#endif + +#if defined(KINETIS_SIM_HAS_SCGC7) /* System Clock Gating Control Register 7 */ -#define SIM_SCGC7_FLEXBUS (1 << 0) /* Bit 0: FlexBus Clock Gate Control */ -#define SIM_SCGC7_DMA (1 << 1) /* Bit 1: DMA Clock Gate Control */ -#define SIM_SCGC7_MPU (1 << 2) /* Bit 2: MPU Clock Gate Control */ - /* Bits 3-31: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC7_FLEXBUS) +# define SIM_SCGC7_FLEXBUS (1 << 0) /* Bit 0: FlexBus Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC7_DMA) +# define SIM_SCGC7_DMA (1 << 1) /* Bit 1: DMA Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC7_MPU) +# define SIM_SCGC7_MPU (1 << 2) /* Bit 2: MPU Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC7_SDRAMC) +# define SIM_SCGC7_SDRAMC (1 << 3) /* Bit 3: SDRAMC Clock Gate Control */ +# endif + /* Bits 4-31: Reserved */ +# endif + /* System Clock Divider Register 1 */ - /* Bits 0-15: Reserved */ -#define SIM_CLKDIV1_OUTDIV4_SHIFT (16) /* Bits 16-19: Clock 4 output divider value */ -#define SIM_CLKDIV1_OUTDIV4_MASK (15 << SIM_CLKDIV1_OUTDIV4_SHIFT) -# define SIM_CLKDIV1_OUTDIV4(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV4_SHIFT) /* n=1..16 */ -# define SIM_CLKDIV1_OUTDIV4_1 (0 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 1 */ -# define SIM_CLKDIV1_OUTDIV4_2 (1 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 2 */ -# define SIM_CLKDIV1_OUTDIV4_3 (2 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 3 */ -# define SIM_CLKDIV1_OUTDIV4_4 (3 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 4 */ -# define SIM_CLKDIV1_OUTDIV4_5 (4 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 5 */ -# define SIM_CLKDIV1_OUTDIV4_6 (5 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 6 */ -# define SIM_CLKDIV1_OUTDIV4_7 (6 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 7 */ -# define SIM_CLKDIV1_OUTDIV4_8 (7 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 8 */ -# define SIM_CLKDIV1_OUTDIV4_9 (8 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 9 */ -# define SIM_CLKDIV1_OUTDIV4_10 (9 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 10 */ -# define SIM_CLKDIV1_OUTDIV4_11 (10 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 11 */ -# define SIM_CLKDIV1_OUTDIV4_12 (11 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 12 */ -# define SIM_CLKDIV1_OUTDIV4_13 (12 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 13 */ -# define SIM_CLKDIV1_OUTDIV4_14 (13 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 14 */ -# define SIM_CLKDIV1_OUTDIV4_15 (14 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 15 */ -# define SIM_CLKDIV1_OUTDIV4_16 (15 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 16 */ -#define SIM_CLKDIV1_OUTDIV3_SHIFT (20) /* Bits 20-23: Clock 3 output divider value */ -#define SIM_CLKDIV1_OUTDIV3_MASK (15 << SIM_CLKDIV1_OUTDIV3_SHIFT) -# define SIM_CLKDIV1_OUTDIV3(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV3_SHIFT) /* n=1..16 */ -# define SIM_CLKDIV1_OUTDIV3_1 (0 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 1 */ -# define SIM_CLKDIV1_OUTDIV3_2 (1 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 2 */ -# define SIM_CLKDIV1_OUTDIV3_3 (2 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 3 */ -# define SIM_CLKDIV1_OUTDIV3_4 (3 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 4 */ -# define SIM_CLKDIV1_OUTDIV3_5 (4 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 5 */ -# define SIM_CLKDIV1_OUTDIV3_6 (5 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 6 */ -# define SIM_CLKDIV1_OUTDIV3_7 (6 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 7 */ -# define SIM_CLKDIV1_OUTDIV3_8 (7 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 8 */ -# define SIM_CLKDIV1_OUTDIV3_9 (8 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 9 */ -# define SIM_CLKDIV1_OUTDIV3_10 (9 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 10 */ -# define SIM_CLKDIV1_OUTDIV3_11 (10 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 11 */ -# define SIM_CLKDIV1_OUTDIV3_12 (11 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 12 */ -# define SIM_CLKDIV1_OUTDIV3_13 (12 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 13 */ -# define SIM_CLKDIV1_OUTDIV3_14 (13 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 14 */ -# define SIM_CLKDIV1_OUTDIV3_15 (14 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 15 */ -# define SIM_CLKDIV1_OUTDIV3_16 (15 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 16 */ -#define SIM_CLKDIV1_OUTDIV2_SHIFT (24) /* Bits 24-27: Clock 2 output divider value */ -#define SIM_CLKDIV1_OUTDIV2_MASK (15 << SIM_CLKDIV1_OUTDIV2_SHIFT) -# define SIM_CLKDIV1_OUTDIV2(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV2_SHIFT) /* n=1..16 */ -# define SIM_CLKDIV1_OUTDIV2_1 (0 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 1 */ -# define SIM_CLKDIV1_OUTDIV2_2 (1 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 2 */ -# define SIM_CLKDIV1_OUTDIV2_3 (2 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 3 */ -# define SIM_CLKDIV1_OUTDIV2_4 (3 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 4 */ -# define SIM_CLKDIV1_OUTDIV2_5 (4 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 5 */ -# define SIM_CLKDIV1_OUTDIV2_6 (5 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 6 */ -# define SIM_CLKDIV1_OUTDIV2_7 (6 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 7 */ -# define SIM_CLKDIV1_OUTDIV2_8 (7 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 8 */ -# define SIM_CLKDIV1_OUTDIV2_9 (8 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 9 */ -# define SIM_CLKDIV1_OUTDIV2_10 (9 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 10 */ -# define SIM_CLKDIV1_OUTDIV2_11 (10 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 11 */ -# define SIM_CLKDIV1_OUTDIV2_12 (11 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 12 */ -# define SIM_CLKDIV1_OUTDIV2_13 (12 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 13 */ -# define SIM_CLKDIV1_OUTDIV2_14 (13 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 14 */ -# define SIM_CLKDIV1_OUTDIV2_15 (14 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 15 */ -# define SIM_CLKDIV1_OUTDIV2_16 (15 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 16 */ -#define SIM_CLKDIV1_OUTDIV1_SHIFT (28) /* Bits 28-31: Clock 1 output divider value */ -#define SIM_CLKDIV1_OUTDIV1_MASK (15 << SIM_CLKDIV1_OUTDIV1_SHIFT) -# define SIM_CLKDIV1_OUTDIV1(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV1_SHIFT) /* n=1..16 */ -# define SIM_CLKDIV1_OUTDIV1_1 (0 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 1 */ -# define SIM_CLKDIV1_OUTDIV1_2 (1 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 2 */ -# define SIM_CLKDIV1_OUTDIV1_3 (2 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 3 */ -# define SIM_CLKDIV1_OUTDIV1_4 (3 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 4 */ -# define SIM_CLKDIV1_OUTDIV1_5 (4 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 5 */ -# define SIM_CLKDIV1_OUTDIV1_6 (5 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 6 */ -# define SIM_CLKDIV1_OUTDIV1_7 (6 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 7 */ -# define SIM_CLKDIV1_OUTDIV1_8 (7 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 8 */ -# define SIM_CLKDIV1_OUTDIV1_9 (8 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 9 */ -# define SIM_CLKDIV1_OUTDIV1_10 (9 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 10 */ -# define SIM_CLKDIV1_OUTDIV1_11 (10 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 11 */ -# define SIM_CLKDIV1_OUTDIV1_12 (11 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 12 */ -# define SIM_CLKDIV1_OUTDIV1_13 (12 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 13 */ -# define SIM_CLKDIV1_OUTDIV1_14 (13 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 14 */ -# define SIM_CLKDIV1_OUTDIV1_15 (14 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 15 */ -# define SIM_CLKDIV1_OUTDIV1_16 (15 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 16 */ + +#if defined(KINETIS_SIM_HAS_CLKDIV1_OUTDIV5) + /* Bits 0-15: Reserved */ +#endif +#if defined(KINETIS_SIM_HAS_CLKDIV1_OUTDIV4) +# define SIM_CLKDIV1_OUTDIV4_SHIFT (16) /* Bits 16-19: Clock 4 output divider value */ +# define SIM_CLKDIV1_OUTDIV4_MASK (15 << SIM_CLKDIV1_OUTDIV4_SHIFT) +# define SIM_CLKDIV1_OUTDIV4(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV4_SHIFT) /* n=1..16 */ +# define SIM_CLKDIV1_OUTDIV4_1 (0 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 1 */ +# define SIM_CLKDIV1_OUTDIV4_2 (1 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 2 */ +# define SIM_CLKDIV1_OUTDIV4_3 (2 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 3 */ +# define SIM_CLKDIV1_OUTDIV4_4 (3 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 4 */ +# define SIM_CLKDIV1_OUTDIV4_5 (4 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 5 */ +# define SIM_CLKDIV1_OUTDIV4_6 (5 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 6 */ +# define SIM_CLKDIV1_OUTDIV4_7 (6 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 7 */ +# define SIM_CLKDIV1_OUTDIV4_8 (7 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 8 */ +# define SIM_CLKDIV1_OUTDIV4_9 (8 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 9 */ +# define SIM_CLKDIV1_OUTDIV4_10 (9 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 10 */ +# define SIM_CLKDIV1_OUTDIV4_11 (10 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 11 */ +# define SIM_CLKDIV1_OUTDIV4_12 (11 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 12 */ +# define SIM_CLKDIV1_OUTDIV4_13 (12 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 13 */ +# define SIM_CLKDIV1_OUTDIV4_14 (13 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 14 */ +# define SIM_CLKDIV1_OUTDIV4_15 (14 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 15 */ +# define SIM_CLKDIV1_OUTDIV4_16 (15 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 16 */ +#endif +#if defined(KINETIS_SIM_HAS_CLKDIV1_OUTDIV3) +# define SIM_CLKDIV1_OUTDIV3_SHIFT (20) /* Bits 20-23: Clock 3 output divider value */ +# define SIM_CLKDIV1_OUTDIV3_MASK (15 << SIM_CLKDIV1_OUTDIV3_SHIFT) +# define SIM_CLKDIV1_OUTDIV3(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV3_SHIFT) /* n=1..16 */ +# define SIM_CLKDIV1_OUTDIV3_1 (0 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 1 */ +# define SIM_CLKDIV1_OUTDIV3_2 (1 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 2 */ +# define SIM_CLKDIV1_OUTDIV3_3 (2 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 3 */ +# define SIM_CLKDIV1_OUTDIV3_4 (3 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 4 */ +# define SIM_CLKDIV1_OUTDIV3_5 (4 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 5 */ +# define SIM_CLKDIV1_OUTDIV3_6 (5 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 6 */ +# define SIM_CLKDIV1_OUTDIV3_7 (6 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 7 */ +# define SIM_CLKDIV1_OUTDIV3_8 (7 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 8 */ +# define SIM_CLKDIV1_OUTDIV3_9 (8 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 9 */ +# define SIM_CLKDIV1_OUTDIV3_10 (9 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 10 */ +# define SIM_CLKDIV1_OUTDIV3_11 (10 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 11 */ +# define SIM_CLKDIV1_OUTDIV3_12 (11 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 12 */ +# define SIM_CLKDIV1_OUTDIV3_13 (12 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 13 */ +# define SIM_CLKDIV1_OUTDIV3_14 (13 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 14 */ +# define SIM_CLKDIV1_OUTDIV3_15 (14 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 15 */ +# define SIM_CLKDIV1_OUTDIV3_16 (15 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 16 */ +#endif +#if defined(KINETIS_SIM_HAS_CLKDIV1_OUTDIV2) +# define SIM_CLKDIV1_OUTDIV2_SHIFT (24) /* Bits 24-27: Clock 2 output divider value */ +# define SIM_CLKDIV1_OUTDIV2_MASK (15 << SIM_CLKDIV1_OUTDIV2_SHIFT) +# define SIM_CLKDIV1_OUTDIV2(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV2_SHIFT) /* n=1..16 */ +# define SIM_CLKDIV1_OUTDIV2_1 (0 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 1 */ +# define SIM_CLKDIV1_OUTDIV2_2 (1 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 2 */ +# define SIM_CLKDIV1_OUTDIV2_3 (2 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 3 */ +# define SIM_CLKDIV1_OUTDIV2_4 (3 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 4 */ +# define SIM_CLKDIV1_OUTDIV2_5 (4 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 5 */ +# define SIM_CLKDIV1_OUTDIV2_6 (5 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 6 */ +# define SIM_CLKDIV1_OUTDIV2_7 (6 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 7 */ +# define SIM_CLKDIV1_OUTDIV2_8 (7 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 8 */ +# define SIM_CLKDIV1_OUTDIV2_9 (8 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 9 */ +# define SIM_CLKDIV1_OUTDIV2_10 (9 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 10 */ +# define SIM_CLKDIV1_OUTDIV2_11 (10 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 11 */ +# define SIM_CLKDIV1_OUTDIV2_12 (11 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 12 */ +# define SIM_CLKDIV1_OUTDIV2_13 (12 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 13 */ +# define SIM_CLKDIV1_OUTDIV2_14 (13 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 14 */ +# define SIM_CLKDIV1_OUTDIV2_15 (14 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 15 */ +# define SIM_CLKDIV1_OUTDIV2_16 (15 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 16 */ +#endif +#define SIM_CLKDIV1_OUTDIV1_SHIFT (28) /* Bits 28-31: Clock 1 output divider value */ +#define SIM_CLKDIV1_OUTDIV1_MASK (15 << SIM_CLKDIV1_OUTDIV1_SHIFT) +# define SIM_CLKDIV1_OUTDIV1(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV1_SHIFT) /* n=1..16 */ +# define SIM_CLKDIV1_OUTDIV1_1 (0 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 1 */ +# define SIM_CLKDIV1_OUTDIV1_2 (1 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 2 */ +# define SIM_CLKDIV1_OUTDIV1_3 (2 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 3 */ +# define SIM_CLKDIV1_OUTDIV1_4 (3 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 4 */ +# define SIM_CLKDIV1_OUTDIV1_5 (4 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 5 */ +# define SIM_CLKDIV1_OUTDIV1_6 (5 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 6 */ +# define SIM_CLKDIV1_OUTDIV1_7 (6 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 7 */ +# define SIM_CLKDIV1_OUTDIV1_8 (7 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 8 */ +# define SIM_CLKDIV1_OUTDIV1_9 (8 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 9 */ +# define SIM_CLKDIV1_OUTDIV1_10 (9 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 10 */ +# define SIM_CLKDIV1_OUTDIV1_11 (10 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 11 */ +# define SIM_CLKDIV1_OUTDIV1_12 (11 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 12 */ +# define SIM_CLKDIV1_OUTDIV1_13 (12 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 13 */ +# define SIM_CLKDIV1_OUTDIV1_14 (13 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 14 */ +# define SIM_CLKDIV1_OUTDIV1_15 (14 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 15 */ +# define SIM_CLKDIV1_OUTDIV1_16 (15 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 16 */ /* System Clock Divider Register 2 */ -#define SIM_CLKDIV2_USBFRAC (1 << 0) /* Bit 0: USB clock divider fraction */ -#define SIM_CLKDIV2_USBDIV_SHIFT (1) /* Bits 1-3: USB clock divider divisor */ -#define SIM_CLKDIV2_USBDIV_MASK (7 << SIM_CLKDIV2_USBDIV_SHIFT) - /* Bits 4-7: Reserved */ -#define SIM_CLKDIV2_I2SFRAC_SHIFT (8) /* Bits 8-15: I2S clock divider fraction */ -#define SIM_CLKDIV2_I2SFRAC_MASK (0xff << SIM_CLKDIV2_I2SFRAC_SHIFT) - /* Bits 16-19: Reserved */ -#define SIM_CLKDIV2_I2SDIV_SHIFT (20) /* Bits 20-31: I2S clock divider value */ -#define SIM_CLKDIV2_I2SDIV_MASK (0xfff << SIM_CLKDIV2_I2SDIV_SHIFT) - -/* Flash Configuration Register 1 */ - /* Bits 0-7: Reserved */ -#define SIM_FCFG1_DEPART_SHIFT (8) /* Bits 8-11: FlexNVM partition */ -#define SIM_FCFG1_DEPART_MASK (15 << SIM_FCFG1_DEPART_SHIFT) - /* Bits 12-15: Reserved */ -#define SIM_FCFG1_EESIZE_SHIFT (16) /* Bits 16-19: EEPROM size*/ -#define SIM_FCFG1_EESIZE_MASK (15 << SIM_FCFG1_EESIZE_SHIFT) -# define SIM_FCFG1_EESIZE_4KB (2 << SIM_FCFG1_EESIZE_SHIFT) /* 4 KB */ -# define SIM_FCFG1_EESIZE_2KB (3 << SIM_FCFG1_EESIZE_SHIFT) /* 2 KB */ -# define SIM_FCFG1_EESIZE_1KB (4 << SIM_FCFG1_EESIZE_SHIFT) /* 1 KB */ -# define SIM_FCFG1_EESIZE_512B (5 << SIM_FCFG1_EESIZE_SHIFT) /* 512 Bytes */ -# define SIM_FCFG1_EESIZE_256B (6 << SIM_FCFG1_EESIZE_SHIFT) /* 256 Bytes */ -# define SIM_FCFG1_EESIZE_128B (7 << SIM_FCFG1_EESIZE_SHIFT) /* 128 Bytes */ -# define SIM_FCFG1_EESIZE_64B (8 << SIM_FCFG1_EESIZE_SHIFT) /* 64 Bytes */ -# define SIM_FCFG1_EESIZE_32B (9 << SIM_FCFG1_EESIZE_SHIFT) /* 32 Bytes */ -# define SIM_FCFG1_EESIZE_NONE (15 << SIM_FCFG1_EESIZE_SHIFT) /* 0 Bytes */ - /* Bits 20-23: Reserved */ -#if defined(KINETIS_K40) || defined(KINETIS_K64) -# define SIM_FCFG1_PFSIZE_SHIFT (24) /* Bits 24-27: Program flash size (K40) */ -# define SIM_FCFG1_PFSIZE_MASK (15 << SIM_FCFG1_PFSIZE_SHIFT) -# define SIM_FCFG1_PFSIZE_128KB (7 << SIM_FCFG1_PFSIZE_SHIFT) /* 128KB program flash, 4KB protection region */ -# define SIM_FCFG1_PFSIZE_256KB (9 << SIM_FCFG1_PFSIZE_SHIFT) /* 256KB program flash, 8KB protection region */ -# define SIM_FCFG1_PFSIZE_512KB (11 << SIM_FCFG1_PFSIZE_SHIFT) /* 512KB program flash, 16KB protection region */ -# define SIM_FCFG1_PFSIZE_512KB2 (15 << SIM_FCFG1_PFSIZE_SHIFT) /* 512KB program flash, 16KB protection region */ -# define SIM_FCFG1_NVMSIZE_SHIFT (28) /* Bits 28-31: FlexNVM size (K40)*/ -# define SIM_FCFG1_NVMSIZE_MASK (15 << SIM_FCFG1_NVMSIZE_SHIFT) -# define SIM_FCFG1_NVMSIZE_NONE (0 << SIM_FCFG1_NVMSIZE_SHIFT) /* 0KB FlexNVM */ -# define SIM_FCFG1_NVMSIZE_128KB (7 << SIM_FCFG1_NVMSIZE_SHIFT) /* 128KB FlexNVM, 16KB protection region */ -# define SIM_FCFG1_NVMSIZE_256KB (9 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */ -# define SIM_FCFG1_NVMSIZE_256KB2 (15 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */ +#if defined(KINETIS_SIM_HAS_CLKDIV2_USBFRAC) +# define SIM_CLKDIV2_USBFRAC_SHIFT (0) /* Bit 0: USB clock divider fraction */ +# define SIM_CLKDIV2_USBFRAC_MASK (1 << SIM_CLKDIV2_USBFRAC_SHIFT) +# define SIM_CLKDIV2_USBFRAC(n) ((((n)-1) & 1) << SIM_CLKDIV2_USBFRAC_SHIFT) /* n=1..2 */ +#endif +#if defined(KINETIS_SIM_HAS_CLKDIV2_USBDIV) +# define SIM_CLKDIV2_USBDIV_SHIFT (1) /* Bits 1-3: USB clock divider divisor */ +# define SIM_CLKDIV2_USBDIV_MASK (7 << SIM_CLKDIV2_USBDIV_SHIFT) +# define SIM_CLKDIV2_USBDIV(n) ((((n)-1) & 7) << SIM_CLKDIV2_USBDIV_SHIFT) /* n=1..8 */ +#endif + /* Bits 4-7: Reserved */ +#if defined(KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC) +# define SIM_CLKDIV2_USBHSFRAC_SHIFT (8) /* Bit 8: USB HS clock divider fraction */ +# define SIM_CLKDIV2_USBHSFRAC_MASK (1 << SIM_CLKDIV2_USBHSFRAC_SHIFT) +# define SIM_CLKDIV2_USBHSFRAC(n) ((((n)-1) & 1) << SIM_CLKDIV2_USBHSFRAC_SHIFT) /* n=1..2 */ +#endif +#if defined(KINETIS_SIM_HAS_CLKDIV2_USBHSDIV) +# define SIM_CLKDIV2_USBHSDIV_SHIFT (9) /* Bits 1-3: USB HS clock divider divisor */ +# define SIM_CLKDIV2_USBHSDIV_MASK (7 << SIM_CLKDIV2_USBHSDIV_SHIFT) +# define SIM_CLKDIV2_USBHSDIV(n) ((((n)-1) & 7) << SIM_CLKDIV2_USBHSDIV_SHIFT) /* n=1..8 */ +#endif +#if defined(KINETIS_SIM_HAS_CLKDIV2_I2SFRAC) +# define SIM_CLKDIV2_I2SFRAC_SHIFT (8) /* Bits 8-15: I2S clock divider fraction */ +# define SIM_CLKDIV2_I2SFRAC_MASK (0xff << SIM_CLKDIV2_I2SFRAC_SHIFT) +#endif + /* Bits 16-19: Reserved */ +#if defined(KINETIS_SIM_HAS_CLKDIV2_I2SDIV) +# define SIM_CLKDIV2_I2SDIV_SHIFT (20) /* Bits 20-31: I2S clock divider value */ +# define SIM_CLKDIV2_I2SDIV_MASK (0xfff << SIM_CLKDIV2_I2SDIV_SHIFT) #endif -#ifdef KINETIS_K60 -# define SIM_FCFG1_FSIZE_SHIFT (24) /* Bits 24-31: Flash size (K60)*/ -# define SIM_FCFG1_FSIZE_MASK (0xff << SIM_FCFG1_FSIZE_SHIFT) -# define SIM_FCFG1_FSIZE_32KB (2 << SIM_FCFG1_FSIZE_SHIFT) /* 32KB program flash, 1KB protection region */ -# define SIM_FCFG1_FSIZE_64KB (4 << SIM_FCFG1_FSIZE_SHIFT) /* 64KB program flash, 2KB protection region */ -# define SIM_FCFG1_FSIZE_128KB (6 << SIM_FCFG1_FSIZE_SHIFT) /* 128KB program flash, 4KB protection region */ -# define SIM_FCFG1_FSIZE_256KB (8 << SIM_FCFG1_FSIZE_SHIFT) /* 256KB program flash, 8KB protection region */ -# define SIM_FCFG1_FSIZE_512KB (12 << SIM_FCFG1_FSIZE_SHIFT) /* 512KB program flash, 16KB protection region */ +/* Flash Configuration Register 1 */ + +#if defined(KINETIS_SIM_HAS_FCFG1_FTFDIS) +# define SIM_FCFG1_FTFDIS (1 << 0) /* Bit 0: Disable FTFE */ +#endif +#if defined(KINETIS_SIM_HAS_FCFG1_FLASHDIS) +# define SIM_FCFG1_FLASHDIS (1 << 0) /* Bit 0: Flash Disable */ +#endif +#if defined(KINETIS_SIM_HAS_FCFG1_FLASHDOZE) +# define SIM_FCFG1_FLASHDOZE (1 << 1) /* Bit 1: Flash Doze */ +#endif + /* Bits 0-7: Reserved */ +#if defined(KINETIS_SIM_HAS_FCFG1_DEPART) +# define SIM_FCFG1_DEPART_SHIFT (8) /* Bits 8-11: FlexNVM partition */ +# define SIM_FCFG1_DEPART_MASK (15 << SIM_FCFG1_DEPART_SHIFT) +#endif + /* Bits 12-15: Reserved */ +#if defined(KINETIS_SIM_HAS_FCFG1_EESIZE) +# define SIM_FCFG1_EESIZE_SHIFT (16) /* Bits 16-19: EEPROM size */ +# define SIM_FCFG1_EESIZE_MASK (15 << SIM_FCFG1_EESIZE_SHIFT) +# define SIM_FCFG1_EESIZE_16KB (0 << SIM_FCFG1_EESIZE_SHIFT) /* 16 KB */ +# define SIM_FCFG1_EESIZE_8KB (1 << SIM_FCFG1_EESIZE_SHIFT) /* 8 KB */ +# define SIM_FCFG1_EESIZE_4KB (2 << SIM_FCFG1_EESIZE_SHIFT) /* 4 KB */ +# define SIM_FCFG1_EESIZE_2KB (3 << SIM_FCFG1_EESIZE_SHIFT) /* 2 KB */ +# define SIM_FCFG1_EESIZE_1KB (4 << SIM_FCFG1_EESIZE_SHIFT) /* 1 KB */ +# define SIM_FCFG1_EESIZE_512B (5 << SIM_FCFG1_EESIZE_SHIFT) /* 512 Bytes */ +# define SIM_FCFG1_EESIZE_256B (6 << SIM_FCFG1_EESIZE_SHIFT) /* 256 Bytes */ +# define SIM_FCFG1_EESIZE_128B (7 << SIM_FCFG1_EESIZE_SHIFT) /* 128 Bytes */ +# define SIM_FCFG1_EESIZE_64B (8 << SIM_FCFG1_EESIZE_SHIFT) /* 64 Bytes */ +# define SIM_FCFG1_EESIZE_32B (9 << SIM_FCFG1_EESIZE_SHIFT) /* 32 Bytes */ +# define SIM_FCFG1_EESIZE_NONE (15 << SIM_FCFG1_EESIZE_SHIFT) /* 0 Bytes */ +#endif + /* Bits 20-23: Reserved */ +#define SIM_FCFG1_PFSIZE_SHIFT (24) /* Bits 24-27: Program flash size */ +#define SIM_FCFG1_PFSIZE_MASK (15 << SIM_FCFG1_PFSIZE_SHIFT) +# if defined(KINETIS_K40) +# define SIM_FCFG1_PFSIZE_128KB (7 << SIM_FCFG1_PFSIZE_SHIFT) /* 128KB program flash, 4KB protection region */ +# define SIM_FCFG1_PFSIZE_256KB (9 << SIM_FCFG1_PFSIZE_SHIFT) /* 256KB program flash, 8KB protection region */ +# define SIM_FCFG1_PFSIZE_512KB (11 << SIM_FCFG1_PFSIZE_SHIFT) /* 512KB program flash, 16KB protection region */ +# define SIM_FCFG1_PFSIZE_512KB2 (15 << SIM_FCFG1_PFSIZE_SHIFT) /* 512KB program flash, 16KB protection region */ +# endif +# if defined(KINETIS_K60) +# define SIM_FCFG1_PFSIZE_512KB (11 << SIM_FCFG1_PFSIZE_SHIFT) /* 512 KB, 16 KB protection size */ +# define SIM_FCFG1_PFSIZE_1024KB (13 << SIM_FCFG1_PFSIZE_SHIFT) /* 1024 KB, 32 KB protection size */ +# define SIM_FCFG1_PFSIZE_2048KB (15 << SIM_FCFG1_PFSIZE_SHIFT) /* 1024 KB, 32 KB protection size */ +# endif +# if defined(KINETIS_K64) || defined(KINETIS_K66) +# define SIM_FCFG1_PFSIZE_32KB (3 << SIM_FCFG1_PFSIZE_SHIFT) /* 32 KB of program flash memory */ +# define SIM_FCFG1_PFSIZE_64KB (5 << SIM_FCFG1_PFSIZE_SHIFT) /* 64 KB of program flash memory */ +# define SIM_FCFG1_PFSIZE_128KB (7 << SIM_FCFG1_PFSIZE_SHIFT) /* 128 KB of program flash memory */ +# define SIM_FCFG1_PFSIZE_256KB (9 << SIM_FCFG1_PFSIZE_SHIFT) /* 256 KB of program flash memory */ +# define SIM_FCFG1_PFSIZE_512KB (11 << SIM_FCFG1_PFSIZE_SHIFT) /* 512 KB of program flash memory */ +# define SIM_FCFG1_PFSIZE_1024KB (13 << SIM_FCFG1_PFSIZE_SHIFT) /* 1024 KB of program flash memory */ +# define SIM_FCFG1_PFSIZE_2048KB (15 << SIM_FCFG1_PFSIZE_SHIFT) /* 2048 KB of program flash memory */ +# endif + +#if defined(KINETIS_SIM_HAS_FCFG1_NVMSIZE) +# define SIM_FCFG1_NVMSIZE_SHIFT (28) /* Bits 28-31: FlexNVM size */ +# define SIM_FCFG1_NVMSIZE_MASK (15 << SIM_FCFG1_NVMSIZE_SHIFT) +# define SIM_FCFG1_NVMSIZE_NONE (0 << SIM_FCFG1_NVMSIZE_SHIFT) /* 0KB FlexNVM */ +# define SIM_FCFG1_NVMSIZE_128KB (7 << SIM_FCFG1_NVMSIZE_SHIFT) /* 128KB FlexNVM, 16KB protection region */ +# define SIM_FCFG1_NVMSIZE_256KB (9 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */ +# define SIM_FCFG1_NVMSIZE_256KB2 (15 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */ #endif /* Flash Configuration Register 2 */ /* Bits 0-15: Reserved */ -#define SIM_FCFG2_MAXADDR1_SHIFT (16) /* Bits 16-21: Max address block 1 */ -#define SIM_FCFG2_MAXADDR1_MASK (nn << SIM_FCFG2_MAXADDR1_SHIFT) - /* Bit 22: Reserved */ -#define SIM_FCFG2_PFLSH (1 << 23) /* Bit 23: Program flash */ -#define SIM_FCFG2_MAXADDR0_SHIFT (24) /* Bits 24-29: Max address block 0 */ -#define SIM_FCFG2_MAXADDR0_MASK (nn << SIM_FCFG2_MAXADDR0_SHIFT) - /* Bit 30: Reserved */ -#define SIM_FCFG2_SWAPPFLSH (1 << 31) /* Bit 31: Swap program flash */ +#if (KINETIS_SIM_HAS_FCFG2_MAXADDR1) +# define SIM_FCFG2_MAXADDR1_SHIFT (16) /* Bits 16-[21|22]: Max address block 1 */ +# define SIM_FCFG2_MAXADDR1_MASK (KINETIS_SIM_FCFG2_MAXADDR1_MASK << SIM_FCFG2_MAXADDR1_SHIFT) +# define SIM_FCFG2_MAXADDR1(n) (((n) & KINETIS_SIM_FCFG2_MAXADDR1_MASK) << SIM_FCFG2_MAXADDR1_SHIFT) +#endif + /* Bit 22: Reserved */ +#if defined(KINETIS_SIM_HAS_FCFG2_PFLSH) +# define SIM_FCFG2_PFLSH (1 << 23) /* Bit 23: Program flash */ +#endif +#if defined(KINETIS_SIM_HAS_FCFG2_MAXADDR0) +# define SIM_FCFG2_MAXADDR0_SHIFT (24) /* Bits 24-[29|30]: Max address block 0 */ +# define SIM_FCFG2_MAXADDR0_MASK (KINETIS_SIM_FCFG2_MAXADDR0_MASK << SIM_FCFG2_MAXADDR0_SHIFT) +# define SIM_FCFG2_MAXADDR0(n) (((n) & KINETIS_SIM_FCFG2_MAXADDR0_MASK) << SIM_FCFG2_MAXADDR0_SHIFT) + /* Bit 30: Reserved */ +#endif +#if defined(KINETIS_SIM_HAS_FCFG2_SWAPPFLSH) +# define SIM_FCFG2_SWAPPFLSH (1 << 31) /* Bit 31: Swap program flash */ +#endif /* Unique Identification Register High. 32-bit Unique Identification. */ /* Unique Identification Register Mid-High. 32-bit Unique Identification. */ /* Unique Identification Register Mid Low. 32-bit Unique Identification. */ /* Unique Identification Register Low. 32-bit Unique Identification. */ +#if defined(KINETIS_SIM_HAS_CLKDIV3) +/* System Clock Divider Register 3 */ + +# if defined(KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC) +# define SIM_CLKDIV3_PLLFLLFRAC_SHIFT (0) /* Bit 0: PLLFLL clock divider fraction */ +# define SIM_CLKDIV3_PLLFLLFRAC_MASK (1 << SIM_CLKDIV3_PLLFLLFRAC_SHIFT) +# define SIM_CLKDIV3_PLLFLLFRAC(n) ((((n)-1) & 1) << SIM_CLKDIV3_PLLFLLFRAC_SHIFT) /* n=1..2 */ +# endif +# if defined(KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV) +# define SIM_CLKDIV3_PLLFLLDIV_SHIFT (1) /* Bits 1-3: PLLFLL clock divider divisor */ +# define SIM_CLKDIV3_PLLFLLDIV_MASK (7 << SIM_CLKDIV3_PLLFLLDIV_SHIFT) +# define SIM_CLKDIV3_PLLFLLDIV(n) ((((n)-1) & 7) << SIM_CLKDIV3_PLLFLLDIV_SHIFT) /* n=1..8 */ +# endif +#endif +#if defined(KINETIS_SIM_HAS_CLKDIV4) +/* System Clock Divider Register 4 */ + +# if defined(KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC) +# define SIM_CLKDIV4_TRACEFRAC_SHIFTS (0) /* Bit 0: Trace clock divider fraction */ +# define SIM_CLKDIV4_TRACEFRAC_MASK (1 << SIM_CLKDIV4_TRACEFRAC_SHIFTS) +# define SIM_CLKDIV4_TRACEFRAC(n) ((((n)-1) & 1) << SIM_CLKDIV4_TRACEFRAC_SHIFTS) /* n=1..2 */ +# endif +# if defined(KINETIS_SIM_HAS_CLKDIV4_TRACEDIV) +# define SIM_CLKDIV4_TRACEDIV_SHIFT (1) /* Bits 1-3: Trace clock divider divisor */ +# define SIM_CLKDIV4_TRACEDIV_MASK (7 << SIM_CLKDIV3_TRACEDIV_SHIFT) +# define SIM_CLKDIV4_TRACEDIV(n) ((((n)-1) & 7) << SIM_CLKDIV4_TRACEDIV_SHIFT) /* n=1..8 */ +# endif +# if defined(KINETIS_SIM_HAS_CLKDIV4_NFCFRAC) +# define SIM_CLKDIV4_NFCFRAC_SHIFT (24) /* Bits 24-26: NFC clock divider fraction */ +# define SIM_CLKDIV4_NFCFRAC_MASK (7 << SIM_CLKDIV4_NFCFRAC_SHIFT) +# define SIM_CLKDIV4_NFCFRAC(n) ((((n)-1) & 7) << SIM_CLKDIV4_NFCFRAC_SHIFT) /* n=1..8 */ +# endif +# if defined(KINETIS_SIM_HAS_CLKDIV4_NFCDIV) +# define SIM_CLKDIV4_NFCDIV_SHIFT (27) /* Bits 27-31: NFC clock divider divisor */ +# define SIM_CLKDIV4_NFCDIV_MASK (31 << SIM_CLKDIV3_NFCDIV_SHIFT) +# define SIM_CLKDIV4_NFCDIV(n) ((((n)-1) & 31) << SIM_CLKDIV4_NFCDIV_SHIFT) /* n=1..32 */ +# endif +#endif + +#if defined(KINETIS_SIM_HAS_MCR) +/* Misc Control Register */ + + /* Bits 0-28: Reserved */ +# define SIM_MCR_PDBLOOP (1<< 29) /* Bit 29: PDB Loop Mode */ + /* Bit 30: Reserved */ +# define SIM_MCR_TRACECLKDIS (1<< 31) /* Bit 31: Trace clock disable. */ +#endif + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/src/kinetis/chip/kinetis_uart.h b/arch/arm/src/kinetis/chip/kinetis_uart.h index 537332ee786..d7296ce7066 100644 --- a/arch/arm/src/kinetis/chip/kinetis_uart.h +++ b/arch/arm/src/kinetis/chip/kinetis_uart.h @@ -1,8 +1,9 @@ /************************************************************************************ * arch/arm/src/kinetis/chip/kinetis_uart.h * - * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -293,7 +294,7 @@ #define UART_BDH_SBR_SHIFT (0) /* Bits 0-4: MS Bits 8-13 of the UART Baud Rate Bits */ #define UART_BDH_SBR_MASK (31 << UART_BDH_SBR_SHIFT) - /* Bit 5: Reserved */ +#define UART_BDH_SBNS (1 << 5) /* Bit 5: Stop Bit Number Select */ #define UART_BDH_RXEDGIE (1 << 6) /* Bit 6: RxD Input Active Edge Interrupt Enable */ #define UART_BDH_LBKDIE (1 << 7) /* Bit 7: LIN Break Detect Interrupt Enable */ diff --git a/arch/arm/src/kinetis/kinetis.h b/arch/arm/src/kinetis/kinetis.h index b4832274c33..f70f69a0e16 100644 --- a/arch/arm/src/kinetis/kinetis.h +++ b/arch/arm/src/kinetis/kinetis.h @@ -1,8 +1,9 @@ /************************************************************************************ * arch/arm/src/kinetis/kinetis.h * - * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2011, 2013, 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -340,6 +341,48 @@ extern "C" void kinetis_clockconfig(void); +/**************************************************************************** + * Name: kinetis_earlyserialinit + * + * Description: + * Performs the low level UART/LPUART initialization early in debug so that + * the serial console will be available during bootup. This must be called + * before up_serialinit. + * + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT +void kinetis_earlyserialinit(void); +#endif + +/**************************************************************************** + * Name: kinetis_uart_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before up_serialinit. + * + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT +void kinetis_uart_earlyserialinit(void); +#endif + +/**************************************************************************** + * Name: kinetis_lpuart_earlyserialinit + * + * Description: + * Performs the low level LPUART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before up_serialinit. + * + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT +void kinetis_lpuart_earlyserialinit(void); +#endif + /************************************************************************************ * Name: kinetis_lowsetup * @@ -352,6 +395,44 @@ void kinetis_clockconfig(void); void kinetis_lowsetup(void); +/**************************************************************************** + * Name: kinetis_uart_serialinit + * + * Description: + * Register all UART based serial console and serial ports. This assumes + * that kinetis_earlyserialinit was called previously. + * + * Input Parameters: + * first: - First TTY number to assign + * + * Returns Value: + * The next TTY number available for assignment + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +unsigned int kinetis_uart_serialinit(unsigned int first); +#endif + +/**************************************************************************** + * Name: kinetis_lpuart_serialinit + * + * Description: + * Register all LPUART based serial console and serial ports. This assumes + * that kinetis_earlyserialinit was called previously. + * + * Input Parameters: + * first: - First TTY number to assign + * + * Returns Value: + * The next TTY number available for assignment + * + ****************************************************************************/ + +#ifdef HAVE_LPUART_DEVICE +unsigned int kinetis_lpuart_serialinit(unsigned int first); +#endif + /**************************************************************************** * Name: kinetis_uartreset * @@ -364,6 +445,18 @@ void kinetis_lowsetup(void); void kinetis_uartreset(uintptr_t uart_base); #endif +/**************************************************************************** + * Name: kinetis_lpuartreset + * + * Description: + * Reset a UART. + * + ****************************************************************************/ + +#ifdef HAVE_LPUART_DEVICE +void kinetis_lpuartreset(uintptr_t uart_base); +#endif + /**************************************************************************** * Name: kinetis_uartconfigure * @@ -374,7 +467,22 @@ void kinetis_uartreset(uintptr_t uart_base); #ifdef HAVE_UART_DEVICE void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud, uint32_t clock, - unsigned int parity, unsigned int nbits); + unsigned int parity, unsigned int nbits, + unsigned int stop2); +#endif + +/**************************************************************************** + * Name: kinetis_lpuartconfigure + * + * Description: + * Configure a UART as a RS-232 UART. + * + ****************************************************************************/ + +#ifdef HAVE_LPUART_DEVICE +void kinetis_lpuartconfigure(uintptr_t uart_base, uint32_t baud, uint32_t clock, + unsigned int parity, unsigned int nbits, + unsigned int stop2); #endif /************************************************************************************ @@ -404,7 +512,7 @@ int kinetis_pinconfig(uint32_t cfgset); * Configure the digital filter associated with a port. The digital filter * capabilities of the PORT module are available in all digital pin muxing modes. * - * Input parmeters: + * Input Parameters: * port - See KINETIS_PORTn definitions in kinetis_port.h * lpo - true: Digital Filters are clocked by the bus clock * false: Digital Filters are clocked by the 1 kHz LPO clock @@ -460,17 +568,19 @@ void kinetis_pinirqinitialize(void); * 3. Call kinetis_pinirqenable() to enable interrupts on the pin. * * Parameters: - * - pinset: Pin configuration - * - pinisr: Pin interrupt service routine + * pinset - Pin configuration + * pinisr -:wq +:wq: Pin interrupt service routine + * arg:r - And argument that will be provided to the interrupt service routine. * - * Returns: + * Return Value: * The previous value of the interrupt handler function pointer. This value may, * for example, be used to restore the previous handler when multiple handlers are * used. * ************************************************************************************/ -xcpt_t kinetis_pinirqattach(uint32_t pinset, xcpt_t pinisr); +xcpt_t kinetis_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg); /************************************************************************************ * Name: kinetis_pinirqenable @@ -555,7 +665,7 @@ void kinetis_clrpend(int irq); * Description: * Initialize SDIO for operation. * - * Input Parameters: + * Input parameters: * slotno - Not used. * * Returned Values: diff --git a/arch/arm/src/kinetis/kinetis_clockconfig.c b/arch/arm/src/kinetis/kinetis_clockconfig.c index 8080fbd11b3..b954f33be2e 100644 --- a/arch/arm/src/kinetis/kinetis_clockconfig.c +++ b/arch/arm/src/kinetis/kinetis_clockconfig.c @@ -2,7 +2,8 @@ * arch/arm/src/kinetis/kinetis_clockconfig.c * * Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,6 +46,7 @@ #include "chip/kinetis_mcg.h" #include "chip/kinetis_sim.h" #include "chip/kinetis_fmc.h" +#include "chip/kinetis_pmc.h" #include "chip/kinetis_llwu.h" #include "chip/kinetis_pinmux.h" @@ -191,7 +193,10 @@ static inline void kinesis_portclocks(void) void kinetis_pllconfig(void) { +#if defined(SIM_SCGC4_LLWU) || defined(BOARD_SOPT2_PLLFLLSEL) || \ + defined(BOARD_SIM_CLKDIV3_FREQ) uint32_t regval32; +#endif uint8_t regval8; #if defined(BOARD_MCG_C2) @@ -228,16 +233,25 @@ void kinetis_pllconfig(void) MCG_C2_RANGE_VHIGH | MCG_C2_EREFS, KINETIS_MCG_C2); # endif #endif /* defined(BOARD_MCG_C2) */ - +#if defined(SIM_SCGC4_LLWU) /* Released latched state of oscillator and GPIO */ regval32 = getreg32(KINETIS_SIM_SCGC4); regval32 |= SIM_SCGC4_LLWU; putreg32(regval32, KINETIS_SIM_SCGC4); +#endif +#if defined(LLWU_CS_ACKISO) regval8 = getreg8(KINETIS_LLWU_CS); regval8 |= LLWU_CS_ACKISO; putreg8(regval8, KINETIS_LLWU_CS); +#endif + +#if defined(PMC_REGSC_ACKISO) + regval8 = getreg8(KINETIS_PMC_REGSC); + regval8 |= PMC_REGSC_ACKISO; + putreg8(regval8, KINETIS_PMC_REGSC); +#endif /* Select external oscillator and Reference Divider and clear IREFS to * start the external oscillator. @@ -334,6 +348,37 @@ void kinetis_pllconfig(void) while ((getreg8(KINETIS_MCG_S) & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL); /* We are now running in PLL Engaged External (PEE) mode. */ + + /* Do we have BOARD_SOPT2_PLLFLLSEL */ + +#if defined(BOARD_SOPT2_PLLFLLSEL) + /* Set up the SOPT2[PLLFLLSEL] */ + + regval32 = getreg32(KINETIS_SIM_SOPT2); + regval32 &= ~SIM_SOPT2_PLLFLLSEL_MASK; + regval32 |= BOARD_SOPT2_PLLFLLSEL; + putreg32(regval32, KINETIS_SIM_SOPT2); +#endif + +#if defined(BOARD_SIM_CLKDIV2_FREQ) + /* Set up the SIM_CLKDIV2[USBFRAC, USBDIV] */ + + regval32 = getreg32(KINETIS_SIM_CLKDIV2); + regval32 &= ~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK); + regval32 |= (SIM_CLKDIV2_USBFRAC(BOARD_SIM_CLKDIV2_USBFRAC) | + SIM_CLKDIV2_USBDIV(BOARD_SIM_CLKDIV2_USBDIV)); + putreg32(regval32, KINETIS_SIM_CLKDIV2); +#endif + +#if defined(BOARD_SIM_CLKDIV3_FREQ) + /* Set up the SIM_CLKDIV3 [PLLFLLFRAC, PLLFLLDIV] */ + + regval32 = getreg32(KINETIS_SIM_CLKDIV3); + regval32 &= ~(SIM_CLKDIV3_PLLFLLFRAC_MASK | SIM_CLKDIV3_PLLFLLDIV_MASK); + regval32 |= (SIM_CLKDIV3_PLLFLLFRAC(BOARD_SIM_CLKDIV3_PLLFLLFRAC) | + SIM_CLKDIV3_PLLFLLDIV(BOARD_SIM_CLKDIV3_PLLFLLDIV)); + putreg32(regval32, KINETIS_SIM_CLKDIV3); +#endif } /**************************************************************************** diff --git a/arch/arm/src/kinetis/kinetis_config.h b/arch/arm/src/kinetis/kinetis_config.h index daa15e5ff69..732dd403c43 100644 --- a/arch/arm/src/kinetis/kinetis_config.h +++ b/arch/arm/src/kinetis/kinetis_config.h @@ -1,8 +1,9 @@ /************************************************************************************ * arch/arm/src/kinetis/kinetis_config.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2011, 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -50,7 +51,11 @@ ************************************************************************************/ /* Configuration *********************************************************************/ -/* Make that no unsupported UARTs are enabled */ +/* Make sure that no unsupported UARTs are enabled */ + +#ifndef KINETIS_NLPUART +# define KINETIS_NLPUART 0 +#endif #ifndef KINETIS_NISO7816 # define KINETIS_NISO7816 0 @@ -75,7 +80,11 @@ # endif #endif -/* Are any UARTs enabled? */ +#if KINETIS_NLPUART < 1 +# undef CONFIG_KINETIS_LPUART0 +#endif + +/* Are any UARTs or LPUARTs enabled? */ #undef HAVE_UART_DEVICE #if defined(CONFIG_KINETIS_UART0) || defined(CONFIG_KINETIS_UART1) || \ @@ -84,60 +93,138 @@ # define HAVE_UART_DEVICE 1 #endif +#undef HAVE_LPUART_DEVICE +#if defined(CONFIG_KINETIS_LPUART0) || defined(CONFIG_KINETIS_LPUART1) +# define HAVE_LPUART_DEVICE 1 +#endif + /* Is there a serial console? There should be at most one defined. It could be on * any UARTn, n=0,1,2,3,4,5 */ -#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART0) -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_UART5_SERIAL_CONSOLE -# define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART1) -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_UART5_SERIAL_CONSOLE -# define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART2) -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_UART5_SERIAL_CONSOLE -# define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART3) -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_UART5_SERIAL_CONSOLE -# define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART4) -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# undef CONFIG_UART5_SERIAL_CONSOLE -# define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART5) -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# define HAVE_SERIAL_CONSOLE 1 +#undef HAVE_UART_CONSOLE +#undef HAVE_LPUART_CONSOLE + +#if defined(CONFIG_CONSOLE_SYSLOG) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_LPUART0_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE #else -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_UART5_SERIAL_CONSOLE -# undef HAVE_SERIAL_CONSOLE +# if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_LPUART0_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_LPUART0_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +# elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_LPUART0_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +# elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART3) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_LPUART0_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +# elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART4) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_LPUART0_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +# elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART5) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_LPUART0_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +# elif defined(CONFIG_LPUART0_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_LPUART0) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# define HAVE_LPUART_CONSOLE 1 +# elif defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_LPUART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_LPUART0_SERIAL_CONSOLE +# define HAVE_LPUART_CONSOLE 1 +# else +# ifdef CONFIG_DEV_CONSOLE +# warning "No valid CONFIG_[LP]UART[n]_SERIAL_CONSOLE Setting" +# endif +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_LPUART0_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# endif +#endif + +/* Which version of up_putc() should be built? + * + * --------------------+-------------------+-----------------+------------------ + * HAVE_UART_DEVICE && HAVE_UART_DEVICE HAVE_LPUART_DEVICE + * HAVE_LPUART_DEVICE (only) (only) + * --------------------+-------------------+-----------------+------------------ + * HAVE_UART_CONSOLE kinetis_serial kinetis_serial (impossible) + * HAVE_LPUART_CONSOLE kinetis_lpserial (impossible) kinetis_lpserial + * No serial console kinetis_serial kinetis_serial kinetis_lpserial + * --------------------+-------------------+-----------------+------------------ + */ + +#undef HAVE_UART_PUTC +#undef HAVE_LPUART_PUTC + +#if defined(HAVE_LPUART_CONSOLE) +# define HAVE_LPUART_PUTC 1 +#elif defined(HAVE_UART_CONSOLE) +# define HAVE_UART_PUTC 1 +#elif defined(HAVE_UART_DEVICE) +# define HAVE_UART_PUTC 1 +#elif defined(HAVE_LPUART_DEVICE) +# define HAVE_LPUART_PUTC 1 #endif /* Check UART flow control (Not yet supported) */ @@ -148,6 +235,8 @@ # undef CONFIG_UART3_FLOWCONTROL # undef CONFIG_UART4_FLOWCONTROL # undef CONFIG_UART5_FLOWCONTROL +# undef CONFIG_LPUART0_FLOWCONTROL +# undef CONFIG_LPUART1_FLOWCONTROL /* UART FIFO support is not fully implemented. * @@ -183,6 +272,12 @@ #ifndef CONFIG_KINETIS_UART5PRIO # define CONFIG_KINETIS_UART5PRIO NVIC_SYSH_PRIORITY_DEFAULT #endif +#ifndef CONFIG_KINETIS_LPUART0PRIO +# define CONFIG_KINETIS_LPUART0PRIO NVIC_SYSH_PRIORITY_DEFAULT +#endif +#ifndef CONFIG_KINETIS_LPUART1PRIO +# define CONFIG_KINETIS_LPUART1PRIO NVIC_SYSH_PRIORITY_DEFAULT +#endif /* Ethernet controller configuration */ @@ -197,8 +292,8 @@ # define CONFIG_ENET_PHYADDR 1 #endif -#ifndef CONFIG_ENET_NETHIFS -# define CONFIG_ENET_NETHIFS 1 +#ifndef CONFIG_ENETNETHIFS +# define CONFIG_ENETNETHIFS 1 #endif /* EMAC Default Interrupt Priorities */ diff --git a/arch/arm/src/kinetis/kinetis_dma.h b/arch/arm/src/kinetis/kinetis_dma.h index bea26498334..38f03f87a36 100644 --- a/arch/arm/src/kinetis/kinetis_dma.h +++ b/arch/arm/src/kinetis/kinetis_dma.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/kenetis/kinetis_dma.h + * arch/arm/src/kinetis/kinetis_dma.h * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c index b1d83352a69..ac39c53cc91 100644 --- a/arch/arm/src/kinetis/kinetis_enet.c +++ b/arch/arm/src/kinetis/kinetis_enet.c @@ -127,6 +127,7 @@ #define KINETIS_TXTIMEOUT (60*CLK_TCK) #define MII_MAXPOLLS (0x1ffff) #define LINK_WAITUS (500*1000) +#define LINK_NLOOPS (10) /* PHY definitions. * @@ -156,34 +157,31 @@ # define BOARD_PHYID1 MII_PHYID1_KSZ8041 # define BOARD_PHYID2 MII_PHYID2_KSZ8041 # define BOARD_PHY_STATUS MII_KSZ8041_PHYCTRL2 -# define BOARD_PHY_ISDUPLEX(s) (((s) & (4 << MII_PHYCTRL2_MODE_SHIFT)) != 0) -# define BOARD_PHY_10BASET(s) (((s) & (1 << MII_PHYCTRL2_MODE_SHIFT)) != 0) -# define BOARD_PHY_100BASET(s) (((s) & (2 << MII_PHYCTRL2_MODE_SHIFT)) != 0) #elif defined(CONFIG_ETH0_PHY_KSZ8081) # define BOARD_PHY_NAME "KSZ8081" # define BOARD_PHYID1 MII_PHYID1_KSZ8081 # define BOARD_PHYID2 MII_PHYID2_KSZ8081 # define BOARD_PHY_STATUS MII_KSZ8081_PHYCTRL2 -# define BOARD_PHY_ISDUPLEX(s) (((s) & (4 << MII_PHYCTRL2_MODE_SHIFT)) != 0) -# define BOARD_PHY_10BASET(s) (((s) & (1 << MII_PHYCTRL2_MODE_SHIFT)) != 0) -# define BOARD_PHY_100BASET(s) (((s) & (2 << MII_PHYCTRL2_MODE_SHIFT)) != 0) #else # error "Unrecognized or missing PHY selection" #endif -/* Estimate the hold time to use based on the peripheral (bus) clock: +#define BOARD_PHY_10BASET(s) (((s) & (1 << MII_PHYCTRL2_MODE_SHIFT)) != 0) +#define BOARD_PHY_100BASET(s) (((s) & (2 << MII_PHYCTRL2_MODE_SHIFT)) != 0) +#define BOARD_PHY_ISDUPLEX(s) (((s) & (4 << MII_PHYCTRL2_MODE_SHIFT)) != 0) + +/* Estimate the MII_SPEED in order to get an MDC close to 2.5MHz, + based on the internal module (ENET) clock: * - * HOLD_TIME = (2*BUS_FREQ_MHZ)/5 + 1 - * = (BUS_FREQ)/2500000 + 1 + * MII_SPEED = ENET_FREQ/5000000 -1 * - * For example, if BUS_FREQ_MHZ=48 (MHz): + * For example, if ENET_FREQ_MHZ=120 (MHz): * - * HOLD_TIME = 48Mhz, hold time clocks - * = 48000000/2500000 + 1 - * = 20 + * MII_SPEED = 120000000/5000000 -1 + * = 23 */ -#define KINETIS_MII_SPEED (BOARD_BUS_FREQ/2500000 + 1) +#define KINETIS_MII_SPEED (BOARD_CORECLK_FREQ/5000000 - 1) #if KINETIS_MII_SPEED > 63 # error "KINETIS_MII_SPEED is out-of-range" #endif @@ -211,7 +209,6 @@ # define SIM_SOPT2_RMIISRC SIM_SOPT2_RMIISRC_EXTBYP #endif - /**************************************************************************** * Private Types ****************************************************************************/ @@ -287,7 +284,7 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv); static void kinetis_txdone(FAR struct kinetis_driver_s *priv); static void kinetis_interrupt_work(FAR void *arg); -static int kinetis_interrupt(int irq, FAR void *context); +static int kinetis_interrupt(int irq, FAR void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -924,7 +921,7 @@ static void kinetis_interrupt_work(FAR void *arg) * ****************************************************************************/ -static int kinetis_interrupt(int irq, FAR void *context) +static int kinetis_interrupt(int irq, FAR void *context, FAR void *arg) { register FAR struct kinetis_driver_s *priv = &g_enet[0]; @@ -1602,7 +1599,7 @@ static int kinetis_writemii(struct kinetis_driver_s *priv, uint8_t phyaddr, } /**************************************************************************** - * Function: kinetis_writemii + * Function: kinetis_reademii * * Description: * Read a 16-bit value from a PHY register. @@ -1761,15 +1758,14 @@ static inline int kinetis_initphy(struct kinetis_driver_s *priv) /* Start auto negotiation */ - ninfo("%s: Start autonegotiation...\n", BOARD_PHY_NAME); + ninfo("%s: Start Autonegotiation...\n", BOARD_PHY_NAME); kinetis_writemii(priv, phyaddr, MII_MCR, (MII_MCR_ANRESTART | MII_MCR_ANENABLE)); - /* Wait (potentially forever) for auto negotiation to complete */ + /* Wait for auto negotiation to complete */ - do + for (retries = 0; retries < LINK_NLOOPS; retries++) { - usleep(LINK_WAITUS); ret = kinetis_readmii(priv, phyaddr, MII_MSR, &phydata); if (ret < 0) { @@ -1777,24 +1773,45 @@ static inline int kinetis_initphy(struct kinetis_driver_s *priv) BOARD_PHY_NAME, ret); return ret; } + + if (phydata & MII_MSR_ANEGCOMPLETE) + { + break; + } + + usleep(LINK_WAITUS); } - while ((phydata & MII_MSR_ANEGCOMPLETE) == 0); - ninfo("%s: Autonegotiation complete\n", BOARD_PHY_NAME); - ninfo("%s: MII_MSR: %04x\n", BOARD_PHY_NAME, phydata); + if (phydata & MII_MSR_ANEGCOMPLETE) + { + ninfo("%s: Autonegotiation complete\n", BOARD_PHY_NAME); + ninfo("%s: MII_MSR: %04x\n", BOARD_PHY_NAME, phydata); + } + else + { + /* TODO: Autonegotitation has right now failed. Maybe the Eth cable is not connected. + PHY chip have mechanisms to configure link OK. We should leave autconf on, + and find a way to re-configure MCU whenever the link is ready. */ - /* When we get here we have a link - Find the negotiated speed and duplex. */ + ninfo("%s: Autonegotiation failed [%d] (is cable plugged-in ?), default to 10Mbs mode\n", \ + BOARD_PHY_NAME, retries); + + /* Stop auto negotiation */ + + kinetis_writemii(priv, phyaddr, MII_MCR, 0); + } + + /* When we get here we have a (negotiated) speed and duplex. */ phydata = 0; ret = kinetis_readmii(priv, phyaddr, BOARD_PHY_STATUS, &phydata); if (ret < 0) { - nerr("ERROR: Failed to read %s BOARD_PHY_STATUS{%02x]: %d\n", + nerr("ERROR: Failed to read %s BOARD_PHY_STATUS[%02x]: %d\n", BOARD_PHY_NAME, BOARD_PHY_STATUS, ret); return ret; } - ninfo("%s: BOARD_PHY_STATUS: %04x\n", BOARD_PHY_NAME, phydata); /* Set up the transmit and receive control registers based on the @@ -1802,7 +1819,7 @@ static inline int kinetis_initphy(struct kinetis_driver_s *priv) */ #ifdef CONFIG_KINETIS_ENETUSEMII - rcr = ENET_RCR_MII_MODE | ENET_RCR_CRCFWD | + rcr = ENET_RCR_CRCFWD | CONFIG_NET_ETH_MTU << ENET_RCR_MAX_FL_SHIFT | ENET_RCR_MII_MODE; #else @@ -1839,7 +1856,7 @@ static inline int kinetis_initphy(struct kinetis_driver_s *priv) ninfo("%s: 10 Base-T\n", BOARD_PHY_NAME); rcr |= ENET_RCR_RMII_10T; } - else if (!BOARD_PHY_100BASET(phydata)) + else if (BOARD_PHY_100BASET(phydata)) { /* 100 Mbps */ @@ -1847,7 +1864,7 @@ static inline int kinetis_initphy(struct kinetis_driver_s *priv) } else { - /* This might happen if autonegotiation did not complete(?) */ + /* This might happen if Autonegotiation did not complete(?) */ nerr("ERROR: Neither 10- nor 100-BaseT reported: PHY STATUS=%04x\n", phydata); @@ -1994,6 +2011,11 @@ static void kinetis_reset(struct kinetis_driver_s *priv) int kinetis_netinitialize(int intf) { struct kinetis_driver_s *priv; +#ifdef CONFIG_NET_ETHERNET + uint32_t uidl; + uint32_t uidml; + uint8_t *mac; +#endif uint32_t regval; /* Get the interface structure associated with this interface number. */ @@ -2075,7 +2097,7 @@ int kinetis_netinitialize(int intf) /* Attach the Ethernet MAC IEEE 1588 timer interrupt handler */ #if 0 - if (irq_attach(KINETIS_IRQ_EMACTMR, kinetis_tmrinterrupt)) + if (irq_attach(KINETIS_IRQ_EMACTMR, kinetis_tmrinterrupt, NULL)) { /* We could not attach the ISR to the interrupt */ @@ -2086,7 +2108,7 @@ int kinetis_netinitialize(int intf) /* Attach the Ethernet MAC transmit interrupt handler */ - if (irq_attach(KINETIS_IRQ_EMACTX, kinetis_interrupt)) + if (irq_attach(KINETIS_IRQ_EMACTX, kinetis_interrupt, NULL)) { /* We could not attach the ISR to the interrupt */ @@ -2096,7 +2118,7 @@ int kinetis_netinitialize(int intf) /* Attach the Ethernet MAC receive interrupt handler */ - if (irq_attach(KINETIS_IRQ_EMACRX, kinetis_interrupt)) + if (irq_attach(KINETIS_IRQ_EMACRX, kinetis_interrupt, NULL)) { /* We could not attach the ISR to the interrupt */ @@ -2106,7 +2128,7 @@ int kinetis_netinitialize(int intf) /* Attach the Ethernet MAC error and misc interrupt handler */ - if (irq_attach(KINETIS_IRQ_EMACMISC, kinetis_interrupt)) + if (irq_attach(KINETIS_IRQ_EMACMISC, kinetis_interrupt, NULL)) { /* We could not attach the ISR to the interrupt */ @@ -2134,6 +2156,28 @@ int kinetis_netinitialize(int intf) priv->txpoll = wd_create(); /* Create periodic poll timer */ priv->txtimeout = wd_create(); /* Create TX timeout timer */ +#ifdef CONFIG_NET_ETHERNET + /* Determine a semi-unique MAC address from MCU UID + * We use UID Low and Mid Low registers to get 64 bits, from which we keep + * 48 bits. We then force unicast and locally administered bits (b0 and b1, + * 1st octet) + */ + + uidl = getreg32(KINETIS_SIM_UIDL); + uidml = getreg32(KINETIS_SIM_UIDML); + mac = priv->dev.d_mac.ether_addr_octet; + + uidml |= 0x00000200; + uidml &= 0x0000FEFF; + + mac[0] = (uidml & 0x0000ff00) >> 8; + mac[1] = (uidml & 0x000000ff); + mac[2] = (uidl & 0xff000000) >> 24; + mac[3] = (uidl & 0x00ff0000) >> 16; + mac[4] = (uidl & 0x0000ff00) >> 8; + mac[5] = (uidl & 0x000000ff); +#endif + /* Put the interface in the down state. This usually amounts to resetting * the device and/or calling kinetis_ifdown(). */ diff --git a/arch/arm/src/kinetis/kinetis_i2c.c b/arch/arm/src/kinetis/kinetis_i2c.c index 337e24b4d39..6350b18f346 100644 --- a/arch/arm/src/kinetis/kinetis_i2c.c +++ b/arch/arm/src/kinetis/kinetis_i2c.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/kinetis/kinetis_i2c.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. * Author: Matias v01d * * Redistribution and use in source and binary forms, with or without @@ -129,16 +129,7 @@ static void kinetis_i2c_setfrequency(struct kinetis_i2cdev_s *priv, uint32_t frequency); static int kinetis_i2c_start(struct kinetis_i2cdev_s *priv); static void kinetis_i2c_stop(struct kinetis_i2cdev_s *priv); -static int kinetis_i2c_interrupt(struct kinetis_i2cdev_s *priv); -#ifdef CONFIG_KINETIS_I2C0 -static int kinetis_i2c0_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_KINETIS_I2C1 -static int kinetis_i2c1_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_KINETIS_I2C2 -static int kinetis_i2c2_interrupt(int irq, void *context); -#endif +static int kinetis_i2c_interrupt(int irq, void *context, void *arg); static void kinetis_i2c_timeout(int argc, uint32_t arg, ...); static void kinetis_i2c_setfrequency(struct kinetis_i2cdev_s *priv, uint32_t frequency); @@ -638,14 +629,17 @@ void kinetis_i2c_nextmsg(struct kinetis_i2cdev_s *priv) * ****************************************************************************/ -static int kinetis_i2c_interrupt(struct kinetis_i2cdev_s *priv) +static int kinetis_i2c_interrupt(int irq, void *context, void *arg) { + struct kinetis_i2cdev_s *priv = (struct kinetis_i2cdev_s *)arg; struct i2c_msg_s *msg; uint32_t state; int regval; int dummy; UNUSED(dummy); + DEBUGASSERT(priv != NULL); + /* Get current state */ state = kinetis_i2c_getreg(priv, KINETIS_I2C_S_OFFSET); @@ -811,38 +805,6 @@ static int kinetis_i2c_interrupt(struct kinetis_i2cdev_s *priv) return OK; } -/**************************************************************************** - * Name: kinetis_i2cN_interrupt - * - * Description: - * The I2CN interrupt handlers - * - ****************************************************************************/ - -#ifdef CONFIG_KINETIS_I2C0 -static int kinetis_i2c0_interrupt(int irq, void *context) -{ - i2cinfo("I2C0 Interrupt...\n"); - return kinetis_i2c_interrupt(&g_i2c0_dev); -} -#endif - -#ifdef CONFIG_KINETIS_I2C1 -static int kinetis_i2c1_interrupt(int irq, void *context) -{ - i2cinfo("I2C1 Interrupt...\n"); - return kinetis_i2c_interrupt(&g_i2c1_dev); -} -#endif - -#ifdef CONFIG_KINETIS_I2C2 -static int kinetis_i2c2_interrupt(int irq, void *context) -{ - i2cinfo("I2C2 Interrupt...\n"); - return kinetis_i2c_interrupt(&g_i2c2_dev); -} -#endif - /**************************************************************************** * Name: kinetis_i2c_transfer * @@ -988,7 +950,6 @@ static int kinetis_i2c_reset(struct i2c_master_s *dev) struct i2c_master_s *kinetis_i2cbus_initialize(int port) { struct kinetis_i2cdev_s *priv; - xcpt_t handler; i2cinfo("port=%d\n", port); @@ -1011,8 +972,6 @@ struct i2c_master_s *kinetis_i2cbus_initialize(int port) priv->irqid = KINETIS_IRQ_I2C0; priv->basefreq = BOARD_BUS_FREQ; - handler = kinetis_i2c0_interrupt; - /* Enable clock */ regval = getreg32(KINETIS_SIM_SCGC4); @@ -1038,8 +997,6 @@ struct i2c_master_s *kinetis_i2cbus_initialize(int port) priv->irqid = KINETIS_IRQ_I2C1; priv->basefreq = BOARD_BUS_FREQ; - handler = kinetis_i2c1_interrupt; - /* Enable clock */ regval = getreg32(KINETIS_SIM_SCGC4); @@ -1065,8 +1022,6 @@ struct i2c_master_s *kinetis_i2cbus_initialize(int port) priv->irqid = KINETIS_IRQ_I2C2; priv->basefreq = BOARD_BUS_FREQ; - handler = kinetis_i2c2_interrupt; - /* Enable clock */ regval = getreg32(KINETIS_SIM_SCGC4); @@ -1124,7 +1079,7 @@ struct i2c_master_s *kinetis_i2cbus_initialize(int port) /* Attach Interrupt Handler */ - irq_attach(priv->irqid, handler); + irq_attach(priv->irqid, kinetis_i2c_interrupt, priv); /* Enable Interrupt Handler */ diff --git a/arch/arm/src/kinetis/kinetis_irq.c b/arch/arm/src/kinetis/kinetis_irq.c index 7830d8756e2..f75085d7b55 100644 --- a/arch/arm/src/kinetis/kinetis_irq.c +++ b/arch/arm/src/kinetis/kinetis_irq.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lpc17/kinetis_irq.c + * arch/arm/src/kinetis/kinetis_irq.c * * Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -170,7 +170,7 @@ static void kinetis_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int kinetis_nmi(int irq, FAR void *context) +static int kinetis_nmi(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -178,7 +178,7 @@ static int kinetis_nmi(int irq, FAR void *context) return 0; } -static int kinetis_busfault(int irq, FAR void *context) +static int kinetis_busfault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Bus fault recived\n"); @@ -186,7 +186,7 @@ static int kinetis_busfault(int irq, FAR void *context) return 0; } -static int kinetis_usagefault(int irq, FAR void *context) +static int kinetis_usagefault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Usage fault received\n"); @@ -194,7 +194,7 @@ static int kinetis_usagefault(int irq, FAR void *context) return 0; } -static int kinetis_pendsv(int irq, FAR void *context) +static int kinetis_pendsv(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -202,7 +202,7 @@ static int kinetis_pendsv(int irq, FAR void *context) return 0; } -static int kinetis_dbgmonitor(int irq, FAR void *context) +static int kinetis_dbgmonitor(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -210,7 +210,7 @@ static int kinetis_dbgmonitor(int irq, FAR void *context) return 0; } -static int kinetis_reserved(int irq, FAR void *context) +static int kinetis_reserved(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -398,8 +398,8 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(KINETIS_IRQ_SVCALL, up_svcall); - irq_attach(KINETIS_IRQ_HARDFAULT, up_hardfault); + irq_attach(KINETIS_IRQ_SVCALL, up_svcall, NULL); + irq_attach(KINETIS_IRQ_HARDFAULT, up_hardfault, NULL); /* Set the priority of the SVCall interrupt */ @@ -415,22 +415,22 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(KINETIS_IRQ_MEMFAULT, up_memfault); + irq_attach(KINETIS_IRQ_MEMFAULT, up_memfault, NULL); up_enable_irq(KINETIS_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(KINETIS_IRQ_NMI, kinetis_nmi); + irq_attach(KINETIS_IRQ_NMI, kinetis_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(KINETIS_IRQ_MEMFAULT, up_memfault); + irq_attach(KINETIS_IRQ_MEMFAULT, up_memfault, NULL); #endif - irq_attach(KINETIS_IRQ_BUSFAULT, kinetis_busfault); - irq_attach(KINETIS_IRQ_USAGEFAULT, kinetis_usagefault); - irq_attach(KINETIS_IRQ_PENDSV, kinetis_pendsv); - irq_attach(KINETIS_IRQ_DBGMONITOR, kinetis_dbgmonitor); - irq_attach(KINETIS_IRQ_RESERVED, kinetis_reserved); + irq_attach(KINETIS_IRQ_BUSFAULT, kinetis_busfault, NULL); + irq_attach(KINETIS_IRQ_USAGEFAULT, kinetis_usagefault, NULL); + irq_attach(KINETIS_IRQ_PENDSV, kinetis_pendsv, NULL); + irq_attach(KINETIS_IRQ_DBGMONITOR, kinetis_dbgmonitor, NULL); + irq_attach(KINETIS_IRQ_RESERVED, kinetis_reserved, NULL); #endif kinetis_dumpnvic("initial", NR_IRQS); diff --git a/arch/arm/src/kinetis/kinetis_lowputc.c b/arch/arm/src/kinetis/kinetis_lowputc.c index ec85713c933..31bb32f697b 100644 --- a/arch/arm/src/kinetis/kinetis_lowputc.c +++ b/arch/arm/src/kinetis/kinetis_lowputc.c @@ -1,8 +1,9 @@ /**************************************************************************** * arch/arm/src/kinetis/kinetis_lowputc.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2011, 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -50,6 +51,7 @@ #include "kinetis_config.h" #include "kinetis.h" #include "chip/kinetis_uart.h" +#include "chip/kinetis_lpuart.h" #include "chip/kinetis_sim.h" #include "chip/kinetis_pinmux.h" @@ -59,58 +61,85 @@ /* Select UART parameters for the selected console */ -#if defined(CONFIG_UART0_SERIAL_CONSOLE) -# define CONSOLE_BASE KINETIS_UART0_BASE -# define CONSOLE_FREQ BOARD_CORECLK_FREQ -# define CONSOLE_BAUD CONFIG_UART0_BAUD -# define CONSOLE_BITS CONFIG_UART0_BITS -# define CONSOLE_PARITY CONFIG_UART0_PARITY -#elif defined(CONFIG_UART1_SERIAL_CONSOLE) -# define CONSOLE_BASE KINETIS_UART1_BASE -# define CONSOLE_FREQ BOARD_CORECLK_FREQ -# define CONSOLE_BAUD CONFIG_UART1_BAUD -# define CONSOLE_BITS CONFIG_UART1_BITS -# define CONSOLE_PARITY CONFIG_UART1_PARITY -#elif defined(CONFIG_UART2_SERIAL_CONSOLE) -# define CONSOLE_BASE KINETIS_UART2_BASE -# define CONSOLE_FREQ BOARD_BUS_FREQ -# define CONSOLE_BAUD CONFIG_UART2_BAUD -# define CONSOLE_BITS CONFIG_UART2_BITS -# define CONSOLE_PARITY CONFIG_UART2_PARITY -#elif defined(CONFIG_UART3_SERIAL_CONSOLE) -# define CONSOLE_BASE KINETIS_UART3_BASE -# define CONSOLE_FREQ BOARD_BUS_FREQ -# define CONSOLE_BAUD CONFIG_UART3_BAUD -# define CONSOLE_BITS CONFIG_UART3_BITS -# define CONSOLE_PARITY CONFIG_UART3_PARITY -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) -# define CONSOLE_BASE KINETIS_UART4_BASE -# define CONSOLE_FREQ BOARD_BUS_FREQ -# define CONSOLE_BAUD CONFIG_UART4_BAUD -# define CONSOLE_BITS CONFIG_UART4_BITS -# define CONSOLE_PARITY CONFIG_UART4_PARITY -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) -# define CONSOLE_BASE KINETIS_UART5_BASE -# define CONSOLE_FREQ BOARD_BUS_FREQ -# define CONSOLE_BAUD CONFIG_UART5_BAUD -# define CONSOLE_BITS CONFIG_UART5_BITS -# define CONSOLE_PARITY CONFIG_UART5_PARITY -#elif defined(HAVE_SERIAL_CONSOLE) -# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting" +#if defined(HAVE_UART_CONSOLE) +# if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_BASE KINETIS_UART0_BASE +# define CONSOLE_FREQ BOARD_CORECLK_FREQ +# define CONSOLE_BAUD CONFIG_UART0_BAUD +# define CONSOLE_BITS CONFIG_UART0_BITS +# define CONSOLE_2STOP CONFIG_UART0_2STOP +# define CONSOLE_PARITY CONFIG_UART0_PARITY +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_BASE KINETIS_UART1_BASE +# define CONSOLE_FREQ BOARD_CORECLK_FREQ +# define CONSOLE_BAUD CONFIG_UART1_BAUD +# define CONSOLE_BITS CONFIG_UART1_BITS +# define CONSOLE_2STOP CONFIG_UART1_2STOP +# define CONSOLE_PARITY CONFIG_UART1_PARITY +# elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define CONSOLE_BASE KINETIS_UART2_BASE +# define CONSOLE_FREQ BOARD_BUS_FREQ +# define CONSOLE_BAUD CONFIG_UART2_BAUD +# define CONSOLE_BITS CONFIG_UART2_BITS +# define CONSOLE_2STOP CONFIG_UART2_2STOP +# define CONSOLE_PARITY CONFIG_UART2_PARITY +# elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define CONSOLE_BASE KINETIS_UART3_BASE +# define CONSOLE_FREQ BOARD_BUS_FREQ +# define CONSOLE_BAUD CONFIG_UART3_BAUD +# define CONSOLE_BITS CONFIG_UART3_BITS +# define CONSOLE_2STOP CONFIG_UART3_2STOP +# define CONSOLE_PARITY CONFIG_UART3_PARITY +# elif defined(CONFIG_UART4_SERIAL_CONSOLE) +# define CONSOLE_BASE KINETIS_UART4_BASE +# define CONSOLE_FREQ BOARD_BUS_FREQ +# define CONSOLE_BAUD CONFIG_UART4_BAUD +# define CONSOLE_BITS CONFIG_UART4_BITS +# define CONSOLE_2STOP CONFIG_UART4_2STOP +# define CONSOLE_PARITY CONFIG_UART4_PARITY +# elif defined(CONFIG_UART5_SERIAL_CONSOLE) +# define CONSOLE_BASE KINETIS_UART5_BASE +# define CONSOLE_FREQ BOARD_BUS_FREQ +# define CONSOLE_BAUD CONFIG_UART5_BAUD +# define CONSOLE_BITS CONFIG_UART5_BITS +# define CONSOLE_2STOP CONFIG_UART5_2STOP +# define CONSOLE_PARITY CONFIG_UART5_PARITY +# elif defined(HAVE_UART_CONSOLE) +# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting" +# endif +#elif defined(HAVE_LPUART_CONSOLE) +# if defined(CONFIG_LPUART0_SERIAL_CONSOLE) +# define CONSOLE_BASE KINETIS_LPUART0_BASE +# define CONSOLE_FREQ BOARD_LPUART0_FREQ +# define CONSOLE_BAUD CONFIG_LPUART0_BAUD +# define CONSOLE_PARITY CONFIG_LPUART0_PARITY +# define CONSOLE_BITS CONFIG_LPUART0_BITS +# define CONSOLE_2STOP CONFIG_LPUART0_2STOP +# elif defined(CONFIG_LPUART1_SERIAL_CONSOLE) +# define CONSOLE_BASE KINETIS_LPUART1_BASE +# define CONSOLE_FREQ BOARD_LPUART1_FREQ +# define CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define CONSOLE_BITS CONFIG_LPUART1_BITS +# define CONSOLE_2STOP CONFIG_LPUART1_2STOP +# else +# error "No LPUART console is selected" +# endif +#endif /* HAVE_UART_CONSOLE */ + +#if defined(HAVE_LPUART_CONSOLE) +# if ((CONSOLE_FREQ / (CONSOLE_BAUD * 32)) > (LPUART_BAUD_SBR_MASK >> LPUART_BAUD_SBR_SHIFT)) +# error "LPUART Console: Baud rate not obtainable with this input clock!" +# endif +# define LPUART_BAUD_INIT (LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS | \ + LPUART_BAUD_RXEDGIE | LPUART_BAUD_LBKDIE | \ + LPUART_BAUD_RESYNCDIS |LPUART_BAUD_BOTHEDGE | \ + LPUART_BAUD_MATCFG_MASK | LPUART_BAUD_RDMAE | \ + LPUART_BAUD_TDMAE | LPUART_BAUD_OSR_MASK | \ + LPUART_BAUD_M10 | LPUART_BAUD_MAEN2 | \ + LPUART_BAUD_MAEN2) #endif -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - /**************************************************************************** * Private Data ****************************************************************************/ @@ -120,13 +149,12 @@ */ #ifdef CONFIG_KINETIS_UARTFIFOS -static uint8_t g_sizemap[8] = {1, 4, 8, 16, 32, 64, 128, 0}; +static uint8_t g_sizemap[8] = +{ + 1, 4, 8, 16, 32, 64, 128, 0 +}; #endif -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -141,20 +169,20 @@ static uint8_t g_sizemap[8] = {1, 4, 8, 16, 32, 64, 128, 0}; void up_lowputc(char ch) { -#if defined HAVE_UART_DEVICE && defined HAVE_SERIAL_CONSOLE -#ifdef CONFIG_KINETIS_UARTFIFOS +#if defined(HAVE_UART_CONSOLE) +# ifdef CONFIG_KINETIS_UARTFIFOS /* Wait until there is space in the TX FIFO: Read the number of bytes * currently in the FIFO and compare that to the size of the FIFO. If * there are fewer bytes in the FIFO than the size of the FIFO, then we * are able to transmit. */ -# error "Missing logic" -#else +# error "Missing logic" +# else /* Wait until the transmit data register is "empty" (TDRE). This state * depends on the TX watermark setting and may not mean that the transmit * buffer is truly empty. It just means that we can now add another - * characterto the transmit buffer without exceeding the watermark. + * character to the transmit buffer without exceeding the watermark. * * NOTE: UART0 has an 8-byte deep FIFO; the other UARTs have no FIFOs * (1-deep). There appears to be no way to know when the FIFO is not @@ -167,11 +195,18 @@ void up_lowputc(char ch) */ while ((getreg8(CONSOLE_BASE+KINETIS_UART_S1_OFFSET) & UART_S1_TDRE) == 0); -#endif +# endif /* Then write the character to the UART data register */ putreg8((uint8_t)ch, CONSOLE_BASE+KINETIS_UART_D_OFFSET); + +#elif defined(HAVE_LPUART_CONSOLE) + while ((getreg32(CONSOLE_BASE + KINETIS_LPUART_STAT_OFFSET) & LPUART_STAT_TDRE) == 0); + + /* Then send the character */ + + putreg32((uint32_t)ch, CONSOLE_BASE + KINETIS_LPUART_DATA_OFFSET); #endif } @@ -180,92 +215,131 @@ void up_lowputc(char ch) * * Description: * This performs basic initialization of the UART used for the serial - * console. Its purpose is to get the console output availabe as soon + * console. Its purpose is to get the console output available as soon * as possible. * ****************************************************************************/ void kinetis_lowsetup(void) { -#ifdef HAVE_UART_DEVICE +#if defined(HAVE_UART_DEVICE) ||defined(HAVE_LUART_DEVICE) uint32_t regval; +#endif +#ifdef HAVE_UART_DEVICE /* Enable peripheral clocking for all enabled UARTs. Clocking for UARTs * 0-3 is enabled in the SCGC4 register. */ -#if defined(CONFIG_KINETIS_UART0) || defined(CONFIG_KINETIS_UART1) || \ - defined(CONFIG_KINETIS_UART2) || defined(CONFIG_KINETIS_UART3) +# if defined(CONFIG_KINETIS_UART0) || defined(CONFIG_KINETIS_UART1) || \ + defined(CONFIG_KINETIS_UART2) || defined(CONFIG_KINETIS_UART3) regval = getreg32(KINETIS_SIM_SCGC4); -# ifdef CONFIG_KINETIS_UART0 +# ifdef CONFIG_KINETIS_UART0 regval |= SIM_SCGC4_UART0; -# endif -# ifdef CONFIG_KINETIS_UART1 +# endif +# ifdef CONFIG_KINETIS_UART1 regval |= SIM_SCGC4_UART1; -# endif -# ifdef CONFIG_KINETIS_UART2 +# endif +# ifdef CONFIG_KINETIS_UART2 regval |= SIM_SCGC4_UART2; -# endif -# ifdef CONFIG_KINETIS_UART3 +# endif +# ifdef CONFIG_KINETIS_UART3 regval |= SIM_SCGC4_UART3; -# endif +# endif putreg32(regval, KINETIS_SIM_SCGC4); -#endif +# endif /* Clocking for UARTs 4-5 is enabled in the SCGC1 register. */ -#if defined(CONFIG_KINETIS_UART4) || defined(CONFIG_KINETIS_UART5) +# if defined(CONFIG_KINETIS_UART4) || defined(CONFIG_KINETIS_UART5) regval = getreg32(KINETIS_SIM_SCGC1); -# ifdef CONFIG_KINETIS_UART4 +# ifdef CONFIG_KINETIS_UART4 regval |= SIM_SCGC1_UART4; -# endif -# ifdef CONFIG_KINETIS_UART5 +# endif +# ifdef CONFIG_KINETIS_UART5 regval |= SIM_SCGC1_UART5; -# endif +# endif putreg32(regval, KINETIS_SIM_SCGC1); -#endif +# endif /* Configure UART pins for the all enabled UARTs */ -#ifdef CONFIG_KINETIS_UART0 +# ifdef CONFIG_KINETIS_UART0 kinetis_pinconfig(PIN_UART0_TX); kinetis_pinconfig(PIN_UART0_RX); -#endif -#ifdef CONFIG_KINETIS_UART1 +# endif +# ifdef CONFIG_KINETIS_UART1 kinetis_pinconfig(PIN_UART1_TX); kinetis_pinconfig(PIN_UART1_RX); -#endif -#ifdef CONFIG_KINETIS_UART2 +# endif +# ifdef CONFIG_KINETIS_UART2 kinetis_pinconfig(PIN_UART2_TX); kinetis_pinconfig(PIN_UART2_RX); -#endif -#ifdef CONFIG_KINETIS_UART3 +# endif +# ifdef CONFIG_KINETIS_UART3 kinetis_pinconfig(PIN_UART3_TX); kinetis_pinconfig(PIN_UART3_RX); -#endif -#ifdef CONFIG_KINETIS_UART4 +# endif +# ifdef CONFIG_KINETIS_UART4 kinetis_pinconfig(PIN_UART4_TX); kinetis_pinconfig(PIN_UART4_RX); -#endif -#ifdef CONFIG_KINETIS_UART5 +# endif +# ifdef CONFIG_KINETIS_UART5 kinetis_pinconfig(PIN_UART5_TX); kinetis_pinconfig(PIN_UART5_RX); -#endif +# endif /* Configure the console (only) now. Other UARTs will be configured * when the serial driver is opened. */ -#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) +# if defined(HAVE_UART_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) - kinetis_uartconfigure(CONSOLE_BASE, CONSOLE_BAUD, CONSOLE_FREQ, - CONSOLE_PARITY, CONSOLE_BITS); -#endif + kinetis_uartconfigure(CONSOLE_BASE, CONSOLE_BAUD, CONSOLE_FREQ, \ + CONSOLE_PARITY, CONSOLE_BITS, CONSOLE_2STOP); +# endif #endif /* HAVE_UART_DEVICE */ + +#ifdef HAVE_LPUART_DEVICE + + /* Clocking Source for LPUARTs 0 selected in SIM_SOPT2 */ + +# if defined(CONFIG_KINETIS_LPUART0) + regval = getreg32(KINETIS_SIM_SOPT2); + regval &= ~(SIM_SOPT2_LPUARTSRC_MASK); + regval |= BOARD_LPUART0_CLKSRC; + putreg32(regval, KINETIS_SIM_SOPT2); + + /* Clocking for LPUARTs 0-1 is enabled in the SCGC2 register. */ + + regval = getreg32(KINETIS_SIM_SCGC2); + regval |= SIM_SCGC2_LPUART0; + putreg32(regval, KINETIS_SIM_SCGC2); + +# endif + + /* Configure UART pins for the all enabled UARTs */ + +# ifdef CONFIG_KINETIS_LPUART0 + kinetis_pinconfig(PIN_LPUART0_TX); + kinetis_pinconfig(PIN_LPUART0_RX); +# endif + +# ifdef CONFIG_KINETIS_LPUART1 + kinetis_pinconfig(PIN_LPUART1_TX); + kinetis_pinconfig(PIN_LPUART1_RX); +# endif + +# if defined(HAVE_LPUART_CONSOLE) && !defined(CONFIG_SUPPRESS_LPUART_CONFIG) + + kinetis_lpuartconfigure(CONSOLE_BASE, CONSOLE_BAUD, CONSOLE_FREQ, \ + CONSOLE_PARITY, CONSOLE_BITS, CONSOLE_2STOP); +# endif +#endif /* HAVE_LPUART_DEVICE */ } /**************************************************************************** @@ -289,6 +363,27 @@ void kinetis_uartreset(uintptr_t uart_base) } #endif +/**************************************************************************** + * Name: kinetis_lpuartreset + * + * Description: + * Reset a UART. + * + ****************************************************************************/ + +#ifdef HAVE_LPUART_DEVICE +void kinetis_lpuartreset(uintptr_t uart_base) +{ + uint32_t regval; + + /* Just disable the transmitter and receiver */ + + regval = getreg32(uart_base+KINETIS_LPUART_CTRL_OFFSET); + regval &= ~(LPUART_CTRL_RE | LPUART_CTRL_TE); + putreg32(regval, uart_base+KINETIS_LPUART_CTRL_OFFSET); +} +#endif + /**************************************************************************** * Name: kinetis_uartconfigure * @@ -300,7 +395,7 @@ void kinetis_uartreset(uintptr_t uart_base) #ifdef HAVE_UART_DEVICE void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud, uint32_t clock, unsigned int parity, - unsigned int nbits) + unsigned int nbits, unsigned int stop2) { uint32_t sbr; uint32_t brfa; @@ -362,11 +457,16 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud, sbr = clock / (baud << 4); DEBUGASSERT(sbr < 0x2000); - /* Save the new baud divisor, retaining other bits in the UARTx_BDH - * register. + /* Save the new baud divisor and stop bits, retaining other bits in the + * UARTx_BDH register. */ - regval = getreg8(uart_base+KINETIS_UART_BDH_OFFSET) & UART_BDH_SBR_MASK; + regval = getreg8(uart_base+KINETIS_UART_BDH_OFFSET); + regval &= ~(UART_BDH_SBR_MASK | UART_BDH_SBNS); + if (stop2) + { + regval |= UART_BDH_SBNS; + } tmp = sbr >> 8; regval |= (((uint8_t)tmp) << UART_BDH_SBR_SHIFT) & UART_BDH_SBR_MASK; putreg8(regval, uart_base+KINETIS_UART_BDH_OFFSET); @@ -378,7 +478,7 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud, * The fractional divider, BRFA, is a 5 bit fractional value that is * logically added to the SBR: * - * UART baud rate = clock / (16 × (SBR + BRFD)) + * UART baud rate = clock / (16 � (SBR + BRFD)) * * The BRFA the remainder. This will be a non-negative value since the SBR * was calculated by truncation. @@ -411,6 +511,7 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud, { depth = (3 * depth) >> 2; } + putreg8(depth , uart_base+KINETIS_UART_RWFIFO_OFFSET); depth = g_sizemap[(regval & UART_PFIFO_TXFIFOSIZE_MASK) >> UART_PFIFO_TXFIFOSIZE_SHIFT]; @@ -418,6 +519,7 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud, { depth = (depth >> 2); } + putreg8(depth, uart_base+KINETIS_UART_TWFIFO_OFFSET); /* Enable RX and TX FIFOs */ @@ -442,9 +544,176 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud, /* Now we can (re-)enable the transmitter and receiver */ - regval = getreg8(uart_base+KINETIS_UART_C2_OFFSET); + regval = getreg8(uart_base+KINETIS_UART_C2_OFFSET); regval |= (UART_C2_RE | UART_C2_TE); putreg8(regval, uart_base+KINETIS_UART_C2_OFFSET); } #endif +/**************************************************************************** + * Name: kinetis_lpuartconfigure + * + * Description: + * Configure a LPUART as a RS-232 UART. + * + ****************************************************************************/ + +#ifdef HAVE_LPUART_DEVICE +void kinetis_lpuartconfigure(uintptr_t uart_base, uint32_t baud, + uint32_t clock, unsigned int parity, + unsigned int nbits, unsigned int stop2) +{ + uint32_t sbrreg; + uint32_t osrreg; + uint32_t sbr; + uint32_t osr; + uint32_t actual_baud; + uint32_t current_baud; + uint32_t baud_error; + uint32_t min_baud_error; + uint32_t regval; + + /* General note: LPART block input clock can be sourced by + * SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV] since this can be shared with TPM, we + * would ideally want to maximize the input frequency. This also helps to + * maximize the oversampling. + * + * We would like to maximize oversample and minimize the baud rate error + * + * USART baud is generated according to: + * + * baud = clock / (SBR[0:12] * (OSR +1 )) + * + * Or, equivalently: + * + * SBR = clock / (baud * (OSR + 1)) + * OSR = clock / (baud * SBR) -1 + * + * SBR must be 1..8191 + * OSR must be 3..31 (macro value 4..32) + */ + + min_baud_error = baud; + sbrreg = 0; + osrreg = 0; + + /* While maximizing OSR look for a SBR that minimizes the difference + * between actual baud and requested baud rate + */ + + for (osr = 32; osr >= 4; osr--) + { + sbr = clock / (baud * osr); + + /* Ensure the minimum SBR */ + + if (sbr == 0) + { + sbr++; + } + + /* Calculate the actual baud rate */ + + current_baud = clock / (sbr * osr); + + /* look at the deviation of current baud to requested */ + + baud_error = current_baud - baud; + if (baud_error <= min_baud_error) + { + min_baud_error = baud_error; + actual_baud = current_baud; + sbrreg = sbr; + osrreg = osr; + } + } + + UNUSED(actual_baud); + DEBUGASSERT(actual_baud-baud < (baud /100) * 2); + DEBUGASSERT(sbrreg != 0 && sbrreg < 8192); + DEBUGASSERT(osrreg != 0); + + /* Disable the transmitter and receiver throughout the reconfiguration */ + + regval = getreg32(uart_base+KINETIS_LPUART_CTRL_OFFSET); + regval &= ~(LPUART_CTRL_RE | LPUART_CTRL_TE); + putreg32(regval, uart_base+KINETIS_LPUART_CTRL_OFFSET); + + /* Reset the BAUD register */ + + regval = getreg32(uart_base+KINETIS_LPUART_BAUD_OFFSET); + regval &= ~(LPUART_BAUD_INIT); + + /* Set the Baud rate, nbits and stop bits */ + + regval |= LPUART_BAUD_OSR(osrreg); + regval |= LPUART_BAUD_SBR(sbrreg); + + /* Set the 10 bit mode */ + + if (nbits == 10) + { + regval |= LPUART_BAUD_M10; + } + + /* Set the 2 stop bit mode */ + + if (stop2) + { + regval |= LPUART_BAUD_SBNS; + } + + /* BOTHEDG needs to be turned on for 4X-7X */ + + if (osrreg >= 4 && osrreg <= 7) + { + regval |= LPUART_BAUD_BOTHEDGE; + } + + putreg32(regval, uart_base+KINETIS_LPUART_BAUD_OFFSET); + + /* Configure number of bits and parity */ + + regval = 0; + + /* Check for odd parity */ + + if (parity == 1) + { + regval |= (LPUART_CTRL_PE | LPUART_CTRL_PT); /* Enable + odd parity type */ + } + + /* Check for even parity */ + + else if (parity == 2) + { + regval |= LPUART_CTRL_PE; /* Enable (even parity default) */ + } + + /* The only other option is no parity */ + + else + { + DEBUGASSERT(parity == 0); + } + + /* Check for 9-bit operation */ + + if (nbits == 9) + { + regval |= LPUART_CTRL_M; + } + + /* The only other option is 8-bit operation */ + + else + { + DEBUGASSERT(nbits == 8); + } + + /* Now we can (re-)enable the transmitter and receiver */ + + regval |= (LPUART_CTRL_RE | LPUART_CTRL_TE); + putreg32(regval, uart_base+KINETIS_LPUART_CTRL_OFFSET); +} +#endif diff --git a/arch/arm/src/kinetis/kinetis_lpserial.c b/arch/arm/src/kinetis/kinetis_lpserial.c new file mode 100644 index 00000000000..2980f18b8d4 --- /dev/null +++ b/arch/arm/src/kinetis/kinetis_lpserial.c @@ -0,0 +1,911 @@ +/**************************************************************************** + * arch/arm/src/kinetis/kinetis_lpserial.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "kinetis_config.h" +#include "chip.h" +#include "chip/kinetis_lpuart.h" +#include "kinetis.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some sanity checks *******************************************************/ +/* Is there at least one LPUART enabled and configured as a RS-232 device? */ + +#ifndef HAVE_LPUART_DEVICE +# warning "No LPUARTs enabled" +#endif + +/* If we are not using the serial driver for the console, then we still must + * provide some minimal implementation of up_putc. + */ + +#if defined(HAVE_LPUART_DEVICE) && defined(USE_SERIALDRIVER) + +/* Which LPUART with be tty0/console and which tty1? The console will always + * be ttyS0. If there is no console then will use the lowest numbered LPUART. + */ + +/* First pick the console and ttys0. This could be any of LPUART0-1 */ + +#if defined(CONFIG_LPUART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_lpuart0port /* LPUART0 is console */ +# define TTYS0_DEV g_lpuart0port /* LPUART0 is ttyS0 */ +# define LPUART0_ASSIGNED 1 +#elif defined(CONFIG_LPUART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_lpuart1port /* LPUART1 is console */ +# define TTYS0_DEV g_lpuart1port /* LPUART1 is ttyS0 */ +# define LPUART1_ASSIGNED 1 +#else +# undef CONSOLE_DEV /* No console */ +# if defined(CONFIG_KINETIS_LPUART0) +# define TTYS0_DEV g_lpuart0port /* LPUART0 is ttyS0 */ +# define LPUART0_ASSIGNED 1 +# elif defined(CONFIG_KINETIS_LPUART1) +# define TTYS0_DEV g_lpuart1port /* LPUART1 is ttyS0 */ +# define LPUART1_ASSIGNED 1 +# endif +#endif + +/* Pick ttys1. This could be any of LPUART0-1 excluding the console LPUART. */ + +#if defined(CONFIG_KINETIS_LPUART0) && !defined(LPUART0_ASSIGNED) +# define TTYS1_DEV g_lpuart0port /* LPUART0 is ttyS1 */ +# define LPUART0_ASSIGNED 1 +#elif defined(CONFIG_KINETIS_LPUART1) && !defined(LPUART1_ASSIGNED) +# define TTYS1_DEV g_lpuart1port /* LPUART1 is ttyS1 */ +# define LPUART1_ASSIGNED 1 +#endif + +#define LPUART_CTRL_ERROR_INTS (LPUART_CTRL_ORIE | LPUART_CTRL_FEIE | \ + LPUART_CTRL_NEIE | LPUART_CTRL_PEIE) + +#define LPUART_CTRL_RX_INTS LPUART_CTRL_RIE + +#define LPUART_CTRL_TX_INTS LPUART_CTRL_TIE + +#define LPUART_CTRL_ALL_INTS (LPUART_CTRL_TX_INTS | LPUART_CTRL_RX_INTS | \ + LPUART_CTRL_MA1IE | LPUART_CTRL_MA1IE | \ + LPUART_CTRL_ILIE | LPUART_CTRL_TCIE) + +#define LPUART_STAT_ERRORS (LPUART_STAT_OR | LPUART_STAT_FE | \ + LPUART_STAT_PF | LPUART_STAT_NF) + + +/* The LPUART does not have an common set of aligned bits for the interrupt + * enable and the status. So map the ctrl to the stat bits + */ + +#define LPUART_CTRL_TR_INTS (LPUART_CTRL_TX_INTS | LPUART_CTRL_RX_INTS) +#define LPUART_CTRL2STAT(c) ((((c) & LPUART_CTRL_ERROR_INTS) >> 8) | \ + ((c) & (LPUART_CTRL_TR_INTS))) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct kinetis_dev_s +{ + uintptr_t uartbase; /* Base address of LPUART registers */ + uint32_t baud; /* Configured baud */ + uint32_t clock; /* Clocking frequency of the LPUART module */ + uint32_t ie; /* Interrupts enabled */ + uint8_t irq; /* IRQ associated with this LPUART (for enable) */ + uint8_t irqprio; /* Interrupt priority */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (8 or 9) */ + uint8_t stop2; /* Use 2 stop bits */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int kinetis_setup(struct uart_dev_s *dev); +static void kinetis_shutdown(struct uart_dev_s *dev); +static int kinetis_attach(struct uart_dev_s *dev); +static void kinetis_detach(struct uart_dev_s *dev); +static int kinetis_interrupt(int irq, void *context, void *arg); +static int kinetis_ioctl(struct file *filep, int cmd, unsigned long arg); +static int kinetis_receive(struct uart_dev_s *dev, uint32_t *status); +static void kinetis_rxint(struct uart_dev_s *dev, bool enable); +static bool kinetis_rxavailable(struct uart_dev_s *dev); +static void kinetis_send(struct uart_dev_s *dev, int ch); +static void kinetis_txint(struct uart_dev_s *dev, bool enable); +static bool kinetis_txready(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_lpuart_ops = +{ + .setup = kinetis_setup, + .shutdown = kinetis_shutdown, + .attach = kinetis_attach, + .detach = kinetis_detach, + .ioctl = kinetis_ioctl, + .receive = kinetis_receive, + .rxint = kinetis_rxint, + .rxavailable = kinetis_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = kinetis_send, + .txint = kinetis_txint, + .txready = kinetis_txready, + .txempty = kinetis_txready, +}; + +/* I/O buffers */ + +#ifdef CONFIG_KINETIS_LPUART0 +static char g_lpuart0rxbuffer[CONFIG_LPUART0_RXBUFSIZE]; +static char g_lpuart0txbuffer[CONFIG_LPUART0_TXBUFSIZE]; +#endif +#ifdef CONFIG_KINETIS_LPUART1 +static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; +static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; +#endif + +/* This describes the state of the Kinetis LPUART0 port. */ + +#ifdef CONFIG_KINETIS_LPUART0 +static struct kinetis_dev_s g_lpuart0priv = +{ + .uartbase = KINETIS_LPUART0_BASE, + .clock = BOARD_LPUART0_FREQ, + .baud = CONFIG_LPUART0_BAUD, + .irq = KINETIS_IRQ_LPUART0, + .irqprio = CONFIG_KINETIS_LPUART0PRIO, + .parity = CONFIG_LPUART0_PARITY, + .bits = CONFIG_LPUART0_BITS, + .stop2 = CONFIG_LPUART0_2STOP, +}; + +static uart_dev_t g_lpuart0port = +{ + .recv = + { + .size = CONFIG_LPUART0_RXBUFSIZE, + .buffer = g_lpuart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART0_TXBUFSIZE, + .buffer = g_lpuart0txbuffer, + }, + .ops = &g_lpuart_ops, + .priv = &g_lpuart0priv, +}; +#endif + +/* This describes the state of the Kinetis LPUART1 port. */ + +#ifdef CONFIG_KINETIS_LPUART1 +static struct kinetis_dev_s g_lpuart1priv = +{ + .uartbase = KINETIS_LPUART1_BASE, + .clock = BOARD_CORECLK_FREQ, + .baud = BOARD_LPUART1_FREQ, + .irq = KINETIS_IRQ_LPUART1, + .irqprio = CONFIG_KINETIS_LPUART1PRIO, + .parity = CONFIG_LPUART1_PARITY, + .bits = CONFIG_LPUART1_BITS, + .stop2 = CONFIG_LPUART1_2STOP, +}; + +static uart_dev_t g_lpuart1port = +{ + .recv = + { + .size = CONFIG_LPUART1_RXBUFSIZE, + .buffer = g_lpuart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART1_TXBUFSIZE, + .buffer = g_lpuart1txbuffer, + }, + .ops = &g_lpuart_ops, + .priv = &g_lpuart1priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: kinetis_serialin + ****************************************************************************/ + +static inline uint32_t kinetis_serialin(struct kinetis_dev_s *priv, + int offset) +{ + return getreg32(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: kinetis_serialout + ****************************************************************************/ + +static inline void kinetis_serialout(struct kinetis_dev_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: kinetis_setuartint + ****************************************************************************/ + +static void kinetis_setuartint(struct kinetis_dev_s *priv) +{ + irqstate_t flags; + uint32_t regval; + + /* Re-enable/re-disable interrupts corresponding to the state of bits in ie */ + + flags = enter_critical_section(); + regval = kinetis_serialin(priv, KINETIS_LPUART_CTRL_OFFSET); + regval &= ~LPUART_CTRL_ALL_INTS; + regval |= priv->ie; + kinetis_serialout(priv, KINETIS_LPUART_CTRL_OFFSET, regval); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: kinetis_restoreuartint + ****************************************************************************/ + +static void kinetis_restoreuartint(struct kinetis_dev_s *priv, uint32_t ie) +{ + irqstate_t flags; + + /* Re-enable/re-disable interrupts corresponding to the state of bits in ie */ + + flags = enter_critical_section(); + priv->ie = ie & LPUART_CTRL_ALL_INTS; + kinetis_setuartint(priv); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: kinetis_disableuartint + ****************************************************************************/ + +static void kinetis_disableuartint(struct kinetis_dev_s *priv, uint32_t *ie) +{ + irqstate_t flags; + + flags = enter_critical_section(); + if (ie) + { + *ie = priv->ie; + } + + kinetis_restoreuartint(priv, 0); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: kinetis_setup + * + * Description: + * Configure the LPUART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int kinetis_setup(struct uart_dev_s *dev) +{ +#ifndef CONFIG_SUPPRESS_LPUART_CONFIG + struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev->priv; + + /* Configure the LPUART as an RS-232 UART */ + + kinetis_lpuartconfigure(priv->uartbase, priv->baud, priv->clock, + priv->parity, priv->bits, priv->stop2); +#endif + + /* Make sure that all interrupts are disabled */ + + kinetis_restoreuartint(priv, 0); + +#ifdef CONFIG_ARCH_IRQPRIO + /* Set up the interrupt priority */ + + up_prioritize_irq(priv->irq, priv->irqprio); +#endif + + return OK; +} + +/**************************************************************************** + * Name: kinetis_shutdown + * + * Description: + * Disable the LPUART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void kinetis_shutdown(struct uart_dev_s *dev) +{ + struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev->priv; + + /* Disable interrupts */ + + kinetis_restoreuartint(priv, 0); + + /* Reset hardware and disable Rx and Tx */ + + kinetis_lpuartreset(priv->uartbase); +} + +/**************************************************************************** + * Name: kinetis_attach + * + * Description: + * Configure the LPUART to operation in interrupt driven mode. This + * method is called when the serial port is opened. Normally, this is + * just after the the setup() method is called, however, the serial + * console may operate in a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. + * + ****************************************************************************/ + +static int kinetis_attach(struct uart_dev_s *dev) +{ + struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev->priv; + int ret; + + /* Attach and enable the IRQ(s). The interrupts are (probably) still + * disabled in the LPUART_CTRL register. + */ + + ret = irq_attach(priv->irq, kinetis_interrupt, dev); + if (ret == OK) + { + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: kinetis_detach + * + * Description: + * Detach LPUART interrupts. This method is called when the serial port + * is closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void kinetis_detach(struct uart_dev_s *dev) +{ + struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev->priv; + + /* Disable interrupts */ + + kinetis_restoreuartint(priv, 0); + up_disable_irq(priv->irq); + + /* Detach from the interrupt(s) */ + + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: kinetis_interrupts + * + * Description: + * This is the LPUART status interrupt handler. It will be invoked when + * an interrupt received on the 'irq' It should call uart_transmitchars + * or uart_receivechar to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * Appropriate uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int kinetis_interrupt(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct kinetis_dev_s *priv; + uint32_t stat; + uint32_t ctrl; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct kinetis_dev_s *)dev->priv; + + /* Read status register and qualify it with STAT bit corresponding CTRL IE bits */ + + stat = kinetis_serialin(priv, KINETIS_LPUART_STAT_OFFSET); + ctrl = kinetis_serialin(priv, KINETIS_LPUART_CTRL_OFFSET); + stat &= LPUART_CTRL2STAT(ctrl); + do + { + + /* Handle errors. This interrupt may be caused by: + * + * OR: Receiver Overrun Flag. To clear OR, when STAT read with OR set, + * write STAT with OR set; + * FE: Framing error. To clear FE, when STAT read with FE set, read the + * data to discard it and write STAT with FE set; + * NF: Noise flag. To clear NF, when STAT read with EE set, read the + * data to discard it and write STAT with NE set; + * PF: Parity error flag. To clear PF, when STAT read with PE set, read + * the data to discard it and write STAT with PE set; + */ + + if (stat & LPUART_STAT_ERRORS) + { + + /* Only Overrun error does not need a read operation */ + + if ((stat & LPUART_STAT_OR) != LPUART_STAT_OR) + { + (void) kinetis_serialin(priv, KINETIS_LPUART_DATA_OFFSET); + } + + /* Reset any Errors */ + + kinetis_serialout(priv, KINETIS_LPUART_STAT_OFFSET, stat & LPUART_STAT_ERRORS); + return OK; + } + + /* Handle incoming, receive bytes + * + * Check if the receive data register is full (RDRF). + * + * The RDRF status indication is cleared when the data is read from + * the RX data register. + */ + + if (stat & LPUART_STAT_RDRF) + { + uart_recvchars(dev); + } + + /* Handle outgoing, transmit bytes + * + * Check if the transmit data register is "empty." + * + * The TDRE status indication is cleared when the data is written to + * the TX data register. + */ + + if (stat & LPUART_STAT_TDRE) + { + uart_xmitchars(dev); + } + + /* Read status register and requalify it with STAT bit corresponding CTRL IE bits */ + + stat = kinetis_serialin(priv, KINETIS_LPUART_STAT_OFFSET); + ctrl = kinetis_serialin(priv, KINETIS_LPUART_CTRL_OFFSET); + stat &= LPUART_CTRL2STAT(ctrl); + } while(stat != 0); + + return OK; +} + +/**************************************************************************** + * Name: kinetis_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int kinetis_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#if 0 /* Reserved for future growth */ + struct inode *inode; + struct uart_dev_s *dev; + struct kinetis_dev_s *priv; + int ret = OK; + + DEBUGASSERT(filep, filep->f_inode); + inode = filep->f_inode; + dev = inode->i_private; + + DEBUGASSERT(dev, dev->priv); + priv = (struct kinetis_dev_s *)dev->priv; + + switch (cmd) + { + case xxx: /* Add commands here */ + break; + + default: + ret = -ENOTTY; + break; + } + + return ret; +#else + return -ENOTTY; +#endif +} + +/**************************************************************************** + * Name: kinetis_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the LPUART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int kinetis_receive(struct uart_dev_s *dev, uint32_t *status) +{ + struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev->priv; + uint32_t regval; + int data; + + /* Get error status information: + * + * OR: Receiver Overrun Flag. To clear OR, when STAT read with OR set, + * write STAT with OR set; + * FE: Framing error. To clear FE, when STAT read with FE set, read the + * data to discard it and write STAT with FE set; + * NF: Noise flag. To clear NF, when STAT read with EE set, read the + * data to discard it and write STAT with NE set; + * PF: Parity error flag. To clear PF, when STAT read with PE set, read + * the data to discard it and write STAT with PE set; + */ + + regval = kinetis_serialin(priv, KINETIS_LPUART_STAT_OFFSET); + + /* Return status information */ + + if (status) + { + *status = regval; + } + + /* Then return the actual received byte. Read DATA. Then if + * there were any errors write 1 to them to clear the RX errors. + */ + + data = (int)kinetis_serialin(priv, KINETIS_LPUART_DATA_OFFSET); + regval &= LPUART_STAT_ERRORS; + if (regval) + { + kinetis_serialout(priv, KINETIS_LPUART_STAT_OFFSET, regval); + } + + return data; +} + +/**************************************************************************** + * Name: kinetis_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void kinetis_rxint(struct uart_dev_s *dev, bool enable) +{ + struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev->priv; + irqstate_t flags; + + flags = enter_critical_section(); + if (enable) + { + /* Receive an interrupt when their is anything in the Rx data register + * (or an Rx related error occurs). + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ie |= (LPUART_CTRL_RX_INTS | LPUART_CTRL_ERROR_INTS); + kinetis_setuartint(priv); +#endif + } + else + { + priv->ie &= ~(LPUART_CTRL_RX_INTS | LPUART_CTRL_ERROR_INTS); + kinetis_setuartint(priv); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: kinetis_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +static bool kinetis_rxavailable(struct uart_dev_s *dev) +{ + struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev->priv; + + /* Return true if the receive data register is full (RDRF). + */ + + return (kinetis_serialin(priv, KINETIS_LPUART_STAT_OFFSET) & LPUART_STAT_RDRF) != 0; +} + +/**************************************************************************** + * Name: kinetis_send + * + * Description: + * This method will send one byte on the LPUART. + * + ****************************************************************************/ + +static void kinetis_send(struct uart_dev_s *dev, int ch) +{ + struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev->priv; + kinetis_serialout(priv, KINETIS_LPUART_DATA_OFFSET, ch); +} + +/**************************************************************************** + * Name: kinetis_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void kinetis_txint(struct uart_dev_s *dev, bool enable) +{ + struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev->priv; + irqstate_t flags; + + flags = enter_critical_section(); + if (enable) + { + /* Enable the TX interrupt */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ie |= LPUART_CTRL_TX_INTS; + kinetis_setuartint(priv); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); +#endif + } + else + { + /* Disable the TX interrupt */ + + priv->ie &= ~LPUART_CTRL_TX_INTS; + kinetis_setuartint(priv); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: kinetis_txready + * + * Description: + * Return true if the transmit data register is empty + * + ****************************************************************************/ + +static bool kinetis_txready(struct uart_dev_s *dev) +{ + struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev->priv; + + /* Return true if the transmit data register is "empty." */ + + return (kinetis_serialin(priv, KINETIS_LPUART_STAT_OFFSET) & LPUART_STAT_TDRE) != 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: kinetis_lpuart_earlyserialinit + * + * Description: + * Performs the low level LPUART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before up_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in kinetis_lowsetup() and main clock initialization + * performed in up_clkinitialize(). + * + ****************************************************************************/ + +void kinetis_lpuart_earlyserialinit(void) +{ + /* Disable interrupts from all LPUARTS. The console is enabled in + * kinetis_setup() + */ + + kinetis_restoreuartint(TTYS0_DEV.priv, 0); +#ifdef TTYS1_DEV + kinetis_restoreuartint(TTYS1_DEV.priv, 0); +#endif + + /* Configuration whichever one is the console */ + +#ifdef HAVE_LPUART_CONSOLE + CONSOLE_DEV.isconsole = true; + kinetis_setup(&CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: kinetis_lpuart_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that up_earlyserialinit was called previously. + * + * Input Parameters: + * first: - First TTY number to assign + * + * Returns Value: + * The next TTY number available for assignment + * + ****************************************************************************/ + +unsigned int kinetis_lpuart_serialinit(unsigned int first) +{ +#if defined(CONFIG_KINETIS_MERGE_TTY) + char devname[] = "/dev/ttySx"; +#endif + +/* Register the console */ + +#ifdef HAVE_LPUART_CONSOLE + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif +#if !defined(CONFIG_KINETIS_MERGE_TTY) + /* Register all LPUARTs as LPn devices */ + + (void)uart_register("/dev/ttyLP0", &TTYS0_DEV); +# ifdef TTYS1_DEV + (void)uart_register("/dev/ttyLP1", &TTYS1_DEV); +# endif +#else + devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + (void)uart_register(devname, &TTYS0_DEV); +# ifdef TTYS1_DEV + devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + (void)uart_register(devname, &TTYS1_DEV); +# endif +#endif + return first; +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +#ifdef HAVE_LPUART_PUTC +int up_putc(int ch) +{ +#ifdef HAVE_LPUART_CONSOLE + struct kinetis_dev_s *priv = (struct kinetis_dev_s *)CONSOLE_DEV.priv; + uint32_t ie; + + kinetis_disableuartint(priv, &ie); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); + kinetis_restoreuartint(priv, ie); +#endif + return ch; +} +#endif + +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +#ifdef HAVE_LPUART_PUTC +int up_putc(int ch) +{ +#ifdef HAVE_LPUART_CONSOLE + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); +#endif + return ch; +} +#endif + +#endif /* HAVE_LPUART_DEVICE && USE_SERIALDRIVER) */ diff --git a/arch/arm/src/kinetis/kinetis_pinirq.c b/arch/arm/src/kinetis/kinetis_pinirq.c index cc5933e715a..c8adac1f0aa 100644 --- a/arch/arm/src/kinetis/kinetis_pinirq.c +++ b/arch/arm/src/kinetis/kinetis_pinirq.c @@ -73,6 +73,12 @@ * Private Types ****************************************************************************/ +struct kinetis_pinirq_s +{ + xcpt_t handler; + void *arg; +}; + /**************************************************************************** * Private Data ****************************************************************************/ @@ -84,19 +90,19 @@ */ #ifdef CONFIG_KINETIS_PORTAINTS -static xcpt_t g_portaisrs[32]; +static struct kinetis_pinirq_s g_portaisrs[32]; #endif #ifdef CONFIG_KINETIS_PORTBINTS -static xcpt_t g_portbisrs[32]; +static struct kinetis_pinirq_s g_portbisrs[32]; #endif #ifdef CONFIG_KINETIS_PORTCINTS -static xcpt_t g_portcisrs[32]; +static struct kinetis_pinirq_s g_portcisrs[32]; #endif #ifdef CONFIG_KINETIS_PORTDINTS -static xcpt_t g_portdisrs[32]; +static struct kinetis_pinirq_s g_portdisrs[32]; #endif #ifdef CONFIG_KINETIS_PORTEINTS -static xcpt_t g_porteisrs[32]; +static struct kinetis_pinirq_s g_porteisrs[32]; #endif /**************************************************************************** @@ -113,7 +119,7 @@ static xcpt_t g_porteisrs[32]; #ifdef HAVE_PORTINTS static int kinetis_portinterrupt(int irq, FAR void *context, - uintptr_t addr, xcpt_t *isrtab) + uintptr_t addr, struct kinetis_pinirq_s *isrtab) { uint32_t isfr = getreg32(addr); int i; @@ -136,11 +142,14 @@ static int kinetis_portinterrupt(int irq, FAR void *context, * interrupt handler for the pin. */ - if (isrtab[i]) + if (isrtab[i].handler != NULL) { + xcpt_t handler = isrtab[i].handler; + void *arg = isrtab[i].arg; + /* There is a registered interrupt handler... invoke it */ - (void)isrtab[i](irq, context); + (void)handler(irq, context, arg); } /* Writing a one to the ISFR register will clear the pending @@ -169,31 +178,31 @@ static int kinetis_portinterrupt(int irq, FAR void *context, ****************************************************************************/ #ifdef CONFIG_KINETIS_PORTAINTS -static int kinetis_portainterrupt(int irq, FAR void *context) +static int kinetis_portainterrupt(int irq, FAR void *context, FAR void *arg) { return kinetis_portinterrupt(irq, context, KINETIS_PORTA_ISFR, g_portaisrs); } #endif #ifdef CONFIG_KINETIS_PORTBINTS -static int kinetis_portbinterrupt(int irq, FAR void *context) +static int kinetis_portbinterrupt(int irq, FAR void *context, FAR void *arg) { return kinetis_portinterrupt(irq, context, KINETIS_PORTB_ISFR, g_portbisrs); } #endif #ifdef CONFIG_KINETIS_PORTCINTS -static int kinetis_portcinterrupt(int irq, FAR void *context) +static int kinetis_portcinterrupt(int irq, FAR void *context, FAR void *arg) { return kinetis_portinterrupt(irq, context, KINETIS_PORTC_ISFR, g_portcisrs); } #endif #ifdef CONFIG_KINETIS_PORTDINTS -static int kinetis_portdinterrupt(int irq, FAR void *context) +static int kinetis_portdinterrupt(int irq, FAR void *context, FAR void *arg) { return kinetis_portinterrupt(irq, context, KINETIS_PORTD_ISFR, g_portdisrs); } #endif #ifdef CONFIG_KINETIS_PORTEINTS -static int kinetis_porteinterrupt(int irq, FAR void *context) +static int kinetis_porteinterrupt(int irq, FAR void *context, FAR void *arg) { return kinetis_portinterrupt(irq, context, KINETIS_PORTE_ISFR, g_porteisrs); } @@ -215,27 +224,27 @@ static int kinetis_porteinterrupt(int irq, FAR void *context) void kinetis_pinirqinitialize(void) { #ifdef CONFIG_KINETIS_PORTAINTS - (void)irq_attach(KINETIS_IRQ_PORTA, kinetis_portainterrupt); + (void)irq_attach(KINETIS_IRQ_PORTA, kinetis_portainterrupt, NULL); putreg32(0xffffffff, KINETIS_PORTA_ISFR); up_enable_irq(KINETIS_IRQ_PORTA); #endif #ifdef CONFIG_KINETIS_PORTBINTS - (void)irq_attach(KINETIS_IRQ_PORTB, kinetis_portbinterrupt); + (void)irq_attach(KINETIS_IRQ_PORTB, kinetis_portbinterrupt, NULL); putreg32(0xffffffff, KINETIS_PORTB_ISFR); up_enable_irq(KINETIS_IRQ_PORTB); #endif #ifdef CONFIG_KINETIS_PORTCINTS - (void)irq_attach(KINETIS_IRQ_PORTC, kinetis_portcinterrupt); + (void)irq_attach(KINETIS_IRQ_PORTC, kinetis_portcinterrupt, NULL); putreg32(0xffffffff, KINETIS_PORTC_ISFR); up_enable_irq(KINETIS_IRQ_PORTC); #endif #ifdef CONFIG_KINETIS_PORTDINTS - (void)irq_attach(KINETIS_IRQ_PORTD, kinetis_portdinterrupt); + (void)irq_attach(KINETIS_IRQ_PORTD, kinetis_portdinterrupt, NULL); putreg32(0xffffffff, KINETIS_PORTD_ISFR); up_enable_irq(KINETIS_IRQ_PORTD); #endif #ifdef CONFIG_KINETIS_PORTEINTS - (void)irq_attach(KINETIS_IRQ_PORTE, kinetis_porteinterrupt); + (void)irq_attach(KINETIS_IRQ_PORTE, kinetis_porteinterrupt, NULL); putreg32(0xffffffff, KINETIS_PORTE_ISFR); up_enable_irq(KINETIS_IRQ_PORTE); #endif @@ -263,12 +272,12 @@ void kinetis_pinirqinitialize(void) * ****************************************************************************/ -xcpt_t kinetis_pinirqattach(uint32_t pinset, xcpt_t pinisr) +xcpt_t kinetis_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg) { #ifdef HAVE_PORTINTS - xcpt_t *isrtab; - xcpt_t oldisr; - irqstate_t flags; + struct kinetis_pinirq_s *isrtab; + xcpt_t oldisr; + irqstate_t flags; unsigned int port; unsigned int pin; @@ -322,8 +331,9 @@ xcpt_t kinetis_pinirqattach(uint32_t pinset, xcpt_t pinisr) /* Get the old PIN ISR and set the new PIN ISR */ - oldisr = isrtab[pin]; - isrtab[pin] = pinisr; + oldisr = isrtab[pin].handler; + isrtab[pin].handler = pinisr; + isrtab[pin].arg = arg; /* And return the old PIN isr address */ diff --git a/arch/arm/src/kinetis/kinetis_rtc.c b/arch/arm/src/kinetis/kinetis_rtc.c index 19db2796b44..824a72245d6 100644 --- a/arch/arm/src/kinetis/kinetis_rtc.c +++ b/arch/arm/src/kinetis/kinetis_rtc.c @@ -172,7 +172,7 @@ static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg) ****************************************************************************/ #if defined(CONFIG_RTC_ALARM) -static int kinetis_rtc_interrupt(int irq, void *context) +static int kinetis_rtc_interrupt(int irq, void *context, FAR void *arg) { uint16_t rtc_sr; @@ -279,7 +279,7 @@ int up_rtc_irq_attach(void) * KINETIS_IRQ_RTCS is a separate interrupt for seconds if needed */ - irq_attach(KINETIS_IRQ_RTC, kinetis_rtc_interrupt); + irq_attach(KINETIS_IRQ_RTC, kinetis_rtc_interrupt, NULL); up_enable_irq(KINETIS_IRQ_RTC); } diff --git a/arch/arm/src/kinetis/kinetis_sdhc.c b/arch/arm/src/kinetis/kinetis_sdhc.c index f9708256c62..a1d1e847c5e 100644 --- a/arch/arm/src/kinetis/kinetis_sdhc.c +++ b/arch/arm/src/kinetis/kinetis_sdhc.c @@ -271,7 +271,7 @@ static void kinetis_endtransfer(struct kinetis_dev_s *priv, sdio_eventset_t wkup /* Interrupt Handling *******************************************************/ -static int kinetis_interrupt(int irq, void *context); +static int kinetis_interrupt(int irq, void *context, FAR void *arg); /* SDIO interface methods ***************************************************/ @@ -1065,7 +1065,7 @@ static void kinetis_endtransfer(struct kinetis_dev_s *priv, sdio_eventset_t wkup * ****************************************************************************/ -static int kinetis_interrupt(int irq, void *context) +static int kinetis_interrupt(int irq, void *context, FAR void *arg) { struct kinetis_dev_s *priv = &g_sdhcdev; uint32_t enabled; @@ -1681,7 +1681,7 @@ static int kinetis_attach(FAR struct sdio_dev_s *dev) /* Attach the SDIO interrupt handler */ - ret = irq_attach(KINETIS_IRQ_SDHC, kinetis_interrupt); + ret = irq_attach(KINETIS_IRQ_SDHC, kinetis_interrupt, NULL); if (ret == OK) { diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c index 94966f72a27..63873ecab5f 100644 --- a/arch/arm/src/kinetis/kinetis_serial.c +++ b/arch/arm/src/kinetis/kinetis_serial.c @@ -1,8 +1,9 @@ /**************************************************************************** - * arch/mips/src/kinetis/kinetis_serial.c + * arch/arm/src/kinetis/kinetis_serial.c * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2011-2012, 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -76,7 +77,7 @@ * provide some minimal implementation of up_putc. */ -#ifdef USE_SERIALDRIVER +#if defined(HAVE_UART_DEVICE) && defined(USE_SERIALDRIVER) /* Which UART with be tty0/console and which tty1-4? The console will always * be ttyS0. If there is no console then will use the lowest numbered UART. @@ -240,6 +241,7 @@ struct up_dev_s uint8_t ie; /* Interrupts enabled */ uint8_t parity; /* 0=none, 1=odd, 2=even */ uint8_t bits; /* Number of bits (8 or 9) */ + uint8_t stop2; /* Use 2 stop bits */ }; /**************************************************************************** @@ -251,9 +253,9 @@ static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); #ifdef CONFIG_DEBUG_FEATURES -static int up_interrupt(int irq, void *context); +static int up_interrupt(int irq, void *context, FAR void *arg); #endif -static int up_interrupts(int irq, void *context); +static int up_interrupts(int irq, void *context, FAR void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -334,6 +336,7 @@ static struct up_dev_s g_uart0priv = .irqprio = CONFIG_KINETIS_UART0PRIO, .parity = CONFIG_UART0_PARITY, .bits = CONFIG_UART0_BITS, + .stop2 = CONFIG_UART0_2STOP, }; static uart_dev_t g_uart0port = @@ -368,6 +371,7 @@ static struct up_dev_s g_uart1priv = .irqprio = CONFIG_KINETIS_UART1PRIO, .parity = CONFIG_UART1_PARITY, .bits = CONFIG_UART1_BITS, + .stop2 = CONFIG_UART1_2STOP, }; static uart_dev_t g_uart1port = @@ -402,6 +406,7 @@ static struct up_dev_s g_uart2priv = .irqprio = CONFIG_KINETIS_UART2PRIO, .parity = CONFIG_UART2_PARITY, .bits = CONFIG_UART2_BITS, + .stop2 = CONFIG_UART2_2STOP, }; static uart_dev_t g_uart2port = @@ -436,6 +441,7 @@ static struct up_dev_s g_uart3priv = .irqprio = CONFIG_KINETIS_UART3PRIO, .parity = CONFIG_UART3_PARITY, .bits = CONFIG_UART3_BITS, + .stop2 = CONFIG_UART3_2STOP, }; static uart_dev_t g_uart3port = @@ -470,6 +476,7 @@ static struct up_dev_s g_uart4priv = .irqprio = CONFIG_KINETIS_UART4PRIO, .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, + .stop2 = CONFIG_UART4_2STOP, }; static uart_dev_t g_uart4port = @@ -504,6 +511,7 @@ static struct up_dev_s g_uart5priv = .irqprio = CONFIG_KINETIS_UART5PRIO, .parity = CONFIG_UART5_PARITY, .bits = CONFIG_UART5_BITS, + .stop2 = CONFIG_UART5_2STOP, }; static uart_dev_t g_uart5port = @@ -615,7 +623,7 @@ static int up_setup(struct uart_dev_s *dev) /* Configure the UART as an RS-232 UART */ kinetis_uartconfigure(priv->uartbase, priv->baud, priv->clock, - priv->parity, priv->bits); + priv->parity, priv->bits, priv->stop2); #endif /* Make sure that all interrupts are disabled */ @@ -680,11 +688,11 @@ static int up_attach(struct uart_dev_s *dev) * disabled in the C2 register. */ - ret = irq_attach(priv->irqs, up_interrupts); + ret = irq_attach(priv->irqs, up_interrupts, dev); #ifdef CONFIG_DEBUG_FEATURES if (ret == OK) { - ret = irq_attach(priv->irqe, up_interrupt); + ret = irq_attach(priv->irqe, up_interrupt, dev); } #endif @@ -739,60 +747,14 @@ static void up_detach(struct uart_dev_s *dev) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int up_interrupt(int irq, void *context) +static int up_interrupt(int irq, void *context, FAR void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct up_dev_s *priv; uint8_t regval; -#ifdef CONFIG_KINETIS_UART0 - if (g_uart0priv.irqe == irq) - { - dev = &g_uart0port; - } - else -#endif -#ifdef CONFIG_KINETIS_UART1 - if (g_uart1priv.irqe == irq) - { - dev = &g_uart1port; - } - else -#endif -#ifdef CONFIG_KINETIS_UART2 - if (g_uart2priv.irqe == irq) - { - dev = &g_uart2port; - } - else -#endif -#ifdef CONFIG_KINETIS_UART3 - if (g_uart3priv.irqe == irq) - { - dev = &g_uart3port; - } - else -#endif -#ifdef CONFIG_KINETIS_UART4 - if (g_uart4priv.irqe == irq) - { - dev = &g_uart4port; - } - else -#endif -#ifdef CONFIG_KINETIS_UART5 - if (g_uart5priv.irqe == irq) - { - dev = &g_uart5port; - } - else -#endif - { - PANIC(); - } - + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct up_dev_s *)dev->priv; - DEBUGASSERT(priv); /* Handle error interrupts. This interrupt may be caused by: * @@ -827,9 +789,9 @@ static int up_interrupt(int irq, void *context) * ****************************************************************************/ -static int up_interrupts(int irq, void *context) +static int up_interrupts(int irq, void *context, FAR void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct up_dev_s *priv; int passes; #ifdef CONFIG_KINETIS_UARTFIFOS @@ -839,53 +801,8 @@ static int up_interrupts(int irq, void *context) #endif bool handled; -#ifdef CONFIG_KINETIS_UART0 - if (g_uart0priv.irqs == irq) - { - dev = &g_uart0port; - } - else -#endif -#ifdef CONFIG_KINETIS_UART1 - if (g_uart1priv.irqs == irq) - { - dev = &g_uart1port; - } - else -#endif -#ifdef CONFIG_KINETIS_UART2 - if (g_uart2priv.irqs == irq) - { - dev = &g_uart2port; - } - else -#endif -#ifdef CONFIG_KINETIS_UART3 - if (g_uart3priv.irqs == irq) - { - dev = &g_uart3port; - } - else -#endif -#ifdef CONFIG_KINETIS_UART4 - if (g_uart4priv.irqs == irq) - { - dev = &g_uart4port; - } - else -#endif -#ifdef CONFIG_KINETIS_UART5 - if (g_uart5priv.irqs == irq) - { - dev = &g_uart5port; - } - else -#endif - { - PANIC(); - } + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct up_dev_s *)dev->priv; - DEBUGASSERT(priv); /* Loop until there are no characters to be transferred or, * until we have been looping for a long time. @@ -1071,9 +988,9 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) { #ifdef CONFIG_DEBUG_FEATURES # warning "Revisit: How are errors enabled?" - priv->ie |= UART_C2_RIE; + priv->ie &= ~UART_C2_RIE; #else - priv->ie |= UART_C2_RIE; + priv->ie &= ~UART_C2_RIE; #endif up_setuartint(priv); } @@ -1220,7 +1137,7 @@ static bool up_txempty(struct uart_dev_s *dev) ****************************************************************************/ /**************************************************************************** - * Name: up_earlyserialinit + * Name: kinetis_uart_earlyserialinit * * Description: * Performs the low level UART initialization early in debug so that the @@ -1231,7 +1148,8 @@ static bool up_txempty(struct uart_dev_s *dev) * ****************************************************************************/ -void up_earlyserialinit(void) +#if defined(USE_EARLYSERIALINIT) +void kinetis_uart_earlyserialinit(void) { /* Disable interrupts from all UARTS. The console is enabled in * pic32mx_consoleinit() @@ -1256,47 +1174,63 @@ void up_earlyserialinit(void) /* Configuration whichever one is the console */ -#ifdef HAVE_SERIAL_CONSOLE +#ifdef HAVE_UART_CONSOLE CONSOLE_DEV.isconsole = true; up_setup(&CONSOLE_DEV); #endif } +#endif /**************************************************************************** - * Name: up_serialinit + * Name: kinetis_uart_serialinit * * Description: * Register serial console and serial ports. This assumes * that up_earlyserialinit was called previously. * + * Input Parameters: + * first: - First TTY number to assign + * + * Returns Value: + * The next TTY number available for assignment + * ****************************************************************************/ -void up_serialinit(void) +unsigned int kinetis_uart_serialinit(unsigned int first) { + char devname[] = "/dev/ttySx"; + /* Register the console */ -#ifdef HAVE_SERIAL_CONSOLE +#ifdef HAVE_UART_CONSOLE (void)uart_register("/dev/console", &CONSOLE_DEV); #endif /* Register all UARTs */ - (void)uart_register("/dev/ttyS0", &TTYS0_DEV); + devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + (void)uart_register(devname, &TTYS0_DEV); #ifdef TTYS1_DEV - (void)uart_register("/dev/ttyS1", &TTYS1_DEV); + devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + (void)uart_register(devname, &TTYS1_DEV); #endif #ifdef TTYS2_DEV - (void)uart_register("/dev/ttyS2", &TTYS2_DEV); + devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + (void)uart_register(devname, &TTYS2_DEV); #endif #ifdef TTYS3_DEV - (void)uart_register("/dev/ttyS3", &TTYS3_DEV); + devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + (void)uart_register(devname, &TTYS3_DEV); #endif #ifdef TTYS4_DEV - (void)uart_register("/dev/ttyS4", &TTYS4_DEV); + devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + (void)uart_register(devname, &TTYS4_DEV); #endif #ifdef TTYS5_DEV - (void)uart_register("/dev/ttyS5", &TTYS5_DEV); + devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + (void)uart_register(devname, &TTYS5_DEV); #endif + return first; } /**************************************************************************** @@ -1307,9 +1241,10 @@ void up_serialinit(void) * ****************************************************************************/ +#ifdef HAVE_UART_PUTC int up_putc(int ch) { -#ifdef HAVE_SERIAL_CONSOLE +#ifdef HAVE_UART_CONSOLE struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv; uint8_t ie; @@ -1329,6 +1264,7 @@ int up_putc(int ch) #endif return ch; } +#endif #else /* USE_SERIALDRIVER */ @@ -1340,9 +1276,10 @@ int up_putc(int ch) * ****************************************************************************/ +#ifdef HAVE_UART_PUTC int up_putc(int ch) { -#ifdef HAVE_SERIAL_CONSOLE +#ifdef HAVE_UART_CONSOLE /* Check for LF */ if (ch == '\n') @@ -1356,6 +1293,7 @@ int up_putc(int ch) #endif return ch; } +#endif -#endif /* USE_SERIALDRIVER */ +#endif /* HAVE_UART_DEVICE && USE_SERIALDRIVER) */ diff --git a/arch/arm/src/kinetis/kinetis_serialinit.c b/arch/arm/src/kinetis/kinetis_serialinit.c new file mode 100644 index 00000000000..c23a060935f --- /dev/null +++ b/arch/arm/src/kinetis/kinetis_serialinit.c @@ -0,0 +1,126 @@ +/**************************************************************************** + * arch/arm/src/kinetis/kinetis_serialinit.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "kinetis_config.h" +#include "kinetis.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(HAVE_UART_DEVICE) && !defined(HAVE_LPUART_DEVICE) +# undef CONFIG_KINETS_LPUART_LOWEST +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: kinetis_earlyserialinit + * + * Description: + * Performs the low level UART and LPUART initialization early in debug + * so that the serial console will be available during bootup. This must + * be called before up_serialinit. NOTE: This function depends on GPIO + * pin configuration performed in up_consoleinit() and main clock + * initialization performed in up_clkinitialize(). + * + ****************************************************************************/ + +void kinetis_earlyserialinit(void) +{ +#if defined(HAVE_UART_DEVICE) + /* Initialize UART drivers */ + + kinetis_uart_earlyserialinit(); +#endif + +#if defined(HAVE_LPUART_DEVICE) + /* Initialize LPUART drivers */ + + kinetis_lpuart_earlyserialinit(); +#endif +} + +#ifdef USE_SERIALDRIVER + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register all the serial console and serial ports. This assumes + * that kinetis_earlyserialinit was called previously. + * + ****************************************************************************/ + +void up_serialinit(void) +{ +#if defined(HAVE_UART_DEVICE) ||defined(HAVE_LUART_DEVICE) + uint32_t start = 0; +#endif + + /* Register the console and drivers */ + +#if defined(HAVE_LPUART_DEVICE) && defined(CONFIG_KINETS_LPUART_LOWEST) + /* Register LPUART drivers in starting positions */ + + start = kinetis_lpuart_serialinit(start); +#endif + +#if defined(HAVE_UART_DEVICE) + /* Register UART drivers */ + + start = kinetis_uart_serialinit(start); +#endif + +#if defined(HAVE_LPUART_DEVICE) && !defined(CONFIG_KINETS_LPUART_LOWEST) + /* Register LPUART drivers in last positions */ + + start = kinetis_lpuart_serialinit(start); +#endif + +} +#endif /* USE_SERIALDRIVER */ + diff --git a/arch/arm/src/kinetis/kinetis_start.c b/arch/arm/src/kinetis/kinetis_start.c index 7f209b1351b..6747ce24e88 100644 --- a/arch/arm/src/kinetis/kinetis_start.c +++ b/arch/arm/src/kinetis/kinetis_start.c @@ -63,7 +63,7 @@ ****************************************************************************/ #ifdef CONFIG_ARCH_FPU -static inline void stm32_fpuconfig(void); +static inline void kinetis_fpuconfig(void); #endif #ifdef CONFIG_STACK_COLORATION static void go_os_start(void *pv, unsigned int nbytes) @@ -128,7 +128,7 @@ void __start(void) __attribute__ ((no_instrument_function)); #endif /**************************************************************************** - * Name: stm32_fpuconfig + * Name: kinetis_fpuconfig * * Description: * Configure the FPU. Relative bit settings: @@ -153,7 +153,7 @@ void __start(void) __attribute__ ((no_instrument_function)); #ifdef CONFIG_ARCH_FPU #if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) -static inline void stm32_fpuconfig(void) +static inline void kinetis_fpuconfig(void) { uint32_t regval; @@ -183,7 +183,7 @@ static inline void stm32_fpuconfig(void) #else -static inline void stm32_fpuconfig(void) +static inline void kinetis_fpuconfig(void) { uint32_t regval; @@ -214,7 +214,7 @@ static inline void stm32_fpuconfig(void) #endif #else -# define stm32_fpuconfig() +# define kinetis_fpuconfig() #endif /**************************************************************************** @@ -327,10 +327,10 @@ void __start(void) * can get debug output as soon as possible (This depends on clock * configuration). */ - stm32_fpuconfig(); + kinetis_fpuconfig(); kinetis_lowsetup(); #ifdef USE_EARLYSERIALINIT - up_earlyserialinit(); + kinetis_earlyserialinit(); #endif /* For the case of the separate user-/kernel-space build, perform whatever diff --git a/arch/arm/src/kinetis/kinetis_timerisr.c b/arch/arm/src/kinetis/kinetis_timerisr.c index 48e411dcf5a..44f7e3e9be5 100644 --- a/arch/arm/src/kinetis/kinetis_timerisr.c +++ b/arch/arm/src/kinetis/kinetis_timerisr.c @@ -90,7 +90,7 @@ * ****************************************************************************/ -static int kinetis_timerisr(int irq, uint32_t *regs) +static int kinetis_timerisr(int irq, uint32_t *regs, FAR void *arg) { /* Process timer interrupt */ @@ -139,7 +139,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(KINETIS_IRQ_SYSTICK, (xcpt_t)kinetis_timerisr); + (void)irq_attach(KINETIS_IRQ_SYSTICK, (xcpt_t)kinetis_timerisr, NULL); /* Enable SysTick interrupts */ diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c index 231fc014303..c550fbd3252 100644 --- a/arch/arm/src/kinetis/kinetis_usbdev.c +++ b/arch/arm/src/kinetis/kinetis_usbdev.c @@ -133,8 +133,6 @@ #define KHCI_ENDP_BIT(ep) (1 << (ep)) #define KHCI_ENDP_ALLSET 0xffff -#define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1) - /* BDT Table Indexing. The BDT is addressed in the hardware as follows: * * Bits 9-31: These come the BDT address bits written into the BDTP3, @@ -564,7 +562,7 @@ static void khci_ep0outcomplete(struct khci_usbdev_s *priv); static void khci_ep0incomplete(struct khci_usbdev_s *priv); static void khci_ep0transfer(struct khci_usbdev_s *priv, uint16_t ustat); -static int khci_interrupt(int irq, void *context); +static int khci_interrupt(int irq, void *context, FAR void *arg); /* Endpoint helpers *********************************************************/ @@ -2715,7 +2713,7 @@ static void khci_ep0transfer(struct khci_usbdev_s *priv, uint16_t ustat) * Name: khci_interrupt ****************************************************************************/ -static int khci_interrupt(int irq, void *context) +static int khci_interrupt(int irq, void *context, FAR void *arg) { /* For now there is only one USB controller, but we will always refer to * it using a pointer to make any future ports to multiple USB controllers @@ -4395,33 +4393,24 @@ void up_usbinitialize(void) * it using a pointer to make any future ports to multiple USB controllers * easier. */ -#if 1 - /* 1: Select clock source */ + + /* Select clock source: + * SIM_SOPT2[PLLFLLSEL] and SIM_CLKDIV2[USBFRAC, USBDIV] will have been + * configured in kinetis_pllconfig. So here we select between USB_CLKIN + * or the output of SIM_CLKDIV2[USBFRAC, USBDIV] + */ regval = getreg32(KINETIS_SIM_SOPT2); - regval |= SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_USBSRC; + regval &= ~(SIM_SOPT2_USBSRC); + regval |= BOARD_USB_CLKSRC; putreg32(regval, KINETIS_SIM_SOPT2); - regval = getreg32(KINETIS_SIM_CLKDIV2); -#if defined(CONFIG_TEENSY_3X_OVERCLOCK) - /* (USBFRAC + 0)/(USBDIV + 1) = (1 + 0)/(1 + 1) = 1/2 for 96Mhz clock */ - - regval = SIM_CLKDIV2_USBDIV(1); -#else - /* 72Mhz */ - - regval = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC; -#endif - putreg32(regval, KINETIS_SIM_CLKDIV2); - /* 2: Gate USB clock */ regval = getreg32(KINETIS_SIM_SCGC4); regval |= SIM_SCGC4_USBOTG; putreg32(regval, KINETIS_SIM_SCGC4); -#endif - usbtrace(TRACE_DEVINIT, 0); /* Initialize the driver state structure */ @@ -4442,7 +4431,7 @@ void up_usbinitialize(void) * them when we need them later. */ - if (irq_attach(KINETIS_IRQ_USBOTG, khci_interrupt) != 0) + if (irq_attach(KINETIS_IRQ_USBOTG, khci_interrupt, NULL) != 0) { usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_IRQREGISTRATION), (uint16_t)KINETIS_IRQ_USBOTG); diff --git a/arch/arm/src/kl/kl_gpioirq.c b/arch/arm/src/kl/kl_gpioirq.c index 61331343ccd..7db288321fe 100644 --- a/arch/arm/src/kl/kl_gpioirq.c +++ b/arch/arm/src/kl/kl_gpioirq.c @@ -164,14 +164,14 @@ static int kl_portinterrupt(int irq, FAR void *context, ****************************************************************************/ #ifdef CONFIG_KL_PORTAINTS -static int kl_portainterrupt(int irq, FAR void *context) +static int kl_portainterrupt(int irq, FAR void *context, FAR void *arg) { return kl_portinterrupt(irq, context, KL_PORTA_ISFR, g_portaisrs); } #endif #ifdef CONFIG_KL_PORTDINTS -static int kl_portdinterrupt(int irq, FAR void *context) +static int kl_portdinterrupt(int irq, FAR void *context, FAR void *arg) { return kl_portinterrupt(irq, context, KL_PORTD_ISFR, g_portdisrs); } @@ -193,13 +193,13 @@ static int kl_portdinterrupt(int irq, FAR void *context) void kl_gpioirqinitialize(void) { #ifdef CONFIG_KL_PORTAINTS - (void)irq_attach(KL_IRQ_PORTA, kl_portainterrupt); + (void)irq_attach(KL_IRQ_PORTA, kl_portainterrupt, NULL); putreg32(0xffffffff, KL_PORTA_ISFR); up_enable_irq(KL_IRQ_PORTA); #endif #ifdef CONFIG_KL_PORTDINTS - (void)irq_attach(KL_IRQ_PORTD, kl_portdinterrupt); + (void)irq_attach(KL_IRQ_PORTD, kl_portdinterrupt, NULL); putreg32(0xffffffff, KL_PORTD_ISFR); up_enable_irq(KL_IRQ_PORTD); #endif diff --git a/arch/arm/src/kl/kl_irq.c b/arch/arm/src/kl/kl_irq.c index 94628f26bf7..f8466ac4f50 100644 --- a/arch/arm/src/kl/kl_irq.c +++ b/arch/arm/src/kl/kl_irq.c @@ -138,7 +138,7 @@ static void kl_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int kl_nmi(int irq, FAR void *context) +static int kl_nmi(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -146,7 +146,7 @@ static int kl_nmi(int irq, FAR void *context) return 0; } -static int kl_pendsv(int irq, FAR void *context) +static int kl_pendsv(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -154,7 +154,7 @@ static int kl_pendsv(int irq, FAR void *context) return 0; } -static int kl_reserved(int irq, FAR void *context) +static int kl_reserved(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -231,15 +231,15 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(KL_IRQ_SVCALL, up_svcall); - irq_attach(KL_IRQ_HARDFAULT, up_hardfault); + irq_attach(KL_IRQ_SVCALL, up_svcall, NULL); + irq_attach(KL_IRQ_HARDFAULT, up_hardfault, NULL); /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(KL_IRQ_NMI, kl_nmi); - irq_attach(KL_IRQ_PENDSV, kl_pendsv); - irq_attach(KL_IRQ_RESERVED, kl_reserved); + irq_attach(KL_IRQ_NMI, kl_nmi, NULL); + irq_attach(KL_IRQ_PENDSV, kl_pendsv, NULL); + irq_attach(KL_IRQ_RESERVED, kl_reserved, NULL); #endif kl_dumpnvic("initial", NR_IRQS); diff --git a/arch/arm/src/kl/kl_serial.c b/arch/arm/src/kl/kl_serial.c index fab56a34d5e..a35328345ee 100644 --- a/arch/arm/src/kl/kl_serial.c +++ b/arch/arm/src/kl/kl_serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/kl/kl_serial.c * - * Copyright (C) 2013-2012, 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2012, 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -171,7 +171,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupts(int irq, void *context); +static int up_interrupts(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -455,7 +455,7 @@ static int up_attach(struct uart_dev_s *dev) * disabled in the C2 register. */ - ret = irq_attach(priv->irq, up_interrupts); + ret = irq_attach(priv->irq, up_interrupts, dev); if (ret == OK) { up_enable_irq(priv->irq); @@ -500,40 +500,16 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupts(int irq, void *context) +static int up_interrupts(int irq, void *context, void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct up_dev_s *priv; int passes; uint8_t s1; bool handled; -#ifdef CONFIG_KL_UART0 - if (g_uart0priv.irq == irq) - { - dev = &g_uart0port; - } - else -#endif -#ifdef CONFIG_KL_UART1 - if (g_uart1priv.irq == irq) - { - dev = &g_uart1port; - } - else -#endif -#ifdef CONFIG_KL_UART2 - if (g_uart2priv.irq == irq) - { - dev = &g_uart2port; - } - else -#endif - { - PANIC(); - } + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct up_dev_s *)dev->priv; - DEBUGASSERT(priv); /* Loop until there are no characters to be transferred or, * until we have been looping for a long time. diff --git a/arch/arm/src/kl/kl_timerisr.c b/arch/arm/src/kl/kl_timerisr.c index bf406102753..eed3f5d9baf 100644 --- a/arch/arm/src/kl/kl_timerisr.c +++ b/arch/arm/src/kl/kl_timerisr.c @@ -105,7 +105,7 @@ * ****************************************************************************/ -static int kl_timerisr(int irq, uint32_t *regs) +static int kl_timerisr(int irq, uint32_t *regs, FAR void *arg) { /* Process timer interrupt */ @@ -143,7 +143,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(KL_IRQ_SYSTICK, (xcpt_t)kl_timerisr); + (void)irq_attach(KL_IRQ_SYSTICK, (xcpt_t)kl_timerisr, NULL); /* Enable SysTick interrupts. "The CLKSOURCE bit in SysTick Control and * Status register selects either the core clock (when CLKSOURCE = 1) or diff --git a/arch/arm/src/lpc11xx/lpc11_gpioint.c b/arch/arm/src/lpc11xx/lpc11_gpioint.c index 8aaefed1497..5327b9e9ff8 100644 --- a/arch/arm/src/lpc11xx/lpc11_gpioint.c +++ b/arch/arm/src/lpc11xx/lpc11_gpioint.c @@ -402,7 +402,7 @@ static void lpc11_gpiodemux(uint32_t intbase, uint32_t intmask, * ****************************************************************************/ -static int lpc11_gpiointerrupt(int irq, void *context) +static int lpc11_gpiointerrupt(int irq, void *context, FAR void *arg) { /* Get the GPIO interrupt status */ @@ -468,7 +468,7 @@ void lpc11_gpioirqinitialize(void) * position in the NVIC with External Interrupt 3 */ - (void)irq_attach(LPC11_IRQ_EINT3, lpc11_gpiointerrupt); + (void)irq_attach(LPC11_IRQ_EINT3, lpc11_gpiointerrupt, NULL); up_enable_irq(LPC11_IRQ_EINT3); #elif defined(LPC178x) @@ -476,7 +476,7 @@ void lpc11_gpioirqinitialize(void) * GPIO2. */ - (void)irq_attach(LPC11_IRQ_GPIO, lpc11_gpiointerrupt); + (void)irq_attach(LPC11_IRQ_GPIO, lpc11_gpiointerrupt, NULL); up_enable_irq(LPC11_IRQ_GPIO); #endif diff --git a/arch/arm/src/lpc11xx/lpc11_i2c.c b/arch/arm/src/lpc11xx/lpc11_i2c.c index b8f91daee71..b9d2d107434 100644 --- a/arch/arm/src/lpc11xx/lpc11_i2c.c +++ b/arch/arm/src/lpc11xx/lpc11_i2c.c @@ -129,7 +129,7 @@ struct lpc11_i2cdev_s static int lpc11_i2c_start(struct lpc11_i2cdev_s *priv); static void lpc11_i2c_stop(struct lpc11_i2cdev_s *priv); -static int lpc11_i2c_interrupt(int irq, FAR void *context); +static int lpc11_i2c_interrupt(int irq, FAR void *context, void *arg); static void lpc11_i2c_timeout(int argc, uint32_t arg, ...); static void lpc11_i2c_setfrequency(struct lpc11_i2cdev_s *priv, uint32_t frequency); @@ -304,7 +304,7 @@ static int lpc11_i2c_transfer(FAR struct i2c_master_s *dev, } /**************************************************************************** - * Name: lpc11_i2c_interrupt + * Name: lpc11_stopnext * * Description: * Check if we need to issue STOP at the next message @@ -334,36 +334,13 @@ static void lpc11_stopnext(struct lpc11_i2cdev_s *priv) * ****************************************************************************/ -static int lpc11_i2c_interrupt(int irq, FAR void *context) +static int lpc11_i2c_interrupt(int irq, FAR void *context, void *arg) { - struct lpc11_i2cdev_s *priv; + struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *)arg; struct i2c_msg_s *msg; uint32_t state; -#ifdef CONFIG_LPC11_I2C0 - if (irq == LPC11_IRQ_I2C0) - { - priv = &g_i2c0dev; - } - else -#endif -#ifdef CONFIG_LPC11_I2C1 - if (irq == LPC11_IRQ_I2C1) - { - priv = &g_i2c1dev; - } - else -#endif -#ifdef CONFIG_LPC11_I2C2 - if (irq == LPC11_IRQ_I2C2) - { - priv = &g_i2c2dev; - } - else -#endif - { - PANIC(); - } + DEBUGASSERT(priv != NULL); /* Reference UM10360 19.10.5 */ @@ -603,7 +580,7 @@ struct i2c_master_s *lpc11_i2cbus_initialize(int port) /* Attach Interrupt Handler */ - irq_attach(priv->irqid, lpc11_i2c_interrupt); + irq_attach(priv->irqid, lpc11_i2c_interrupt, priv); /* Enable Interrupt Handler */ diff --git a/arch/arm/src/lpc11xx/lpc11_irq.c b/arch/arm/src/lpc11xx/lpc11_irq.c index 4399c582003..df2fde8405c 100644 --- a/arch/arm/src/lpc11xx/lpc11_irq.c +++ b/arch/arm/src/lpc11xx/lpc11_irq.c @@ -134,7 +134,7 @@ static void lpc11_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int lpc11_nmi(int irq, FAR void *context) +static int lpc11_nmi(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -142,7 +142,7 @@ static int lpc11_nmi(int irq, FAR void *context) return 0; } -static int lpc11_pendsv(int irq, FAR void *context) +static int lpc11_pendsv(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -150,7 +150,7 @@ static int lpc11_pendsv(int irq, FAR void *context) return 0; } -static int lpc11_reserved(int irq, FAR void *context) +static int lpc11_reserved(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -227,15 +227,15 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(LPC11_IRQ_SVCALL, up_svcall); - irq_attach(LPC11_IRQ_HARDFAULT, up_hardfault); + irq_attach(LPC11_IRQ_SVCALL, up_svcall, NULL); + irq_attach(LPC11_IRQ_HARDFAULT, up_hardfault, NULL); /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(LPC11_IRQ_NMI, lpc11_nmi); - irq_attach(LPC11_IRQ_PENDSV, lpc11_pendsv); - irq_attach(LPC11_IRQ_RESERVED, lpc11_reserved); + irq_attach(LPC11_IRQ_NMI, lpc11_nmi, NULL); + irq_attach(LPC11_IRQ_PENDSV, lpc11_pendsv, NULL); + irq_attach(LPC11_IRQ_RESERVED, lpc11_reserved, NULL); #endif lpc11_dumpnvic("initial", NR_IRQS); diff --git a/arch/arm/src/lpc11xx/lpc11_serial.c b/arch/arm/src/lpc11xx/lpc11_serial.c index 55c05ac5172..cbef799afe9 100644 --- a/arch/arm/src/lpc11xx/lpc11_serial.c +++ b/arch/arm/src/lpc11xx/lpc11_serial.c @@ -104,7 +104,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); +static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -515,7 +515,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, up_interrupt); + ret = irq_attach(priv->irq, up_interrupt, dev); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -557,24 +557,14 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt(int irq, void *context) +static int up_interrupt(int irq, void *context, void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct up_dev_s *priv; uint32_t status; int passes; -#ifdef CONFIG_LPC11_UART0 - if (g_uart0priv.irq == irq) - { - dev = &g_uart0port; - } - else -#endif - { - PANIC(); - } - + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct up_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, diff --git a/arch/arm/src/lpc11xx/lpc11_timerisr.c b/arch/arm/src/lpc11xx/lpc11_timerisr.c index b5054c79ca2..f334b625820 100644 --- a/arch/arm/src/lpc11xx/lpc11_timerisr.c +++ b/arch/arm/src/lpc11xx/lpc11_timerisr.c @@ -105,7 +105,7 @@ * ****************************************************************************/ -static int lpc11_timerisr(int irq, uint32_t *regs) +static int lpc11_timerisr(int irq, uint32_t *regs, FAR void *arg) { /* Process timer interrupt */ @@ -143,7 +143,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(LPC11_IRQ_SYSTICK, (xcpt_t)lpc11_timerisr); + (void)irq_attach(LPC11_IRQ_SYSTICK, (xcpt_t)lpc11_timerisr, NULL); /* Enable SysTick interrupts. "The CLKSOURCE bit in SysTick Control and * Status register selects either the core clock (when CLKSOURCE = 1) or diff --git a/arch/arm/src/lpc17xx/lpc176x_rtc.c b/arch/arm/src/lpc17xx/lpc176x_rtc.c index 8e04d2f2eba..82549159685 100644 --- a/arch/arm/src/lpc17xx/lpc176x_rtc.c +++ b/arch/arm/src/lpc17xx/lpc176x_rtc.c @@ -227,7 +227,7 @@ static int rtc_resume(void) ************************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int rtc_interrupt(int irq, void *context) +static int rtc_interrupt(int irq, void *context, FAR void *arg) { #warning "Missing logic" return OK; @@ -262,7 +262,7 @@ int up_rtc_initialize(void) /* Attach the RTC interrupt handler */ #ifdef CONFIG_RTC_ALARM - ret = irq_attach(LPC17_IRQ_RTC, rtc_interrupt); + ret = irq_attach(LPC17_IRQ_RTC, rtc_interrupt, NULL); if (ret == OK) { up_enable_irq(LPC17_IRQ_RTC); diff --git a/arch/arm/src/lpc17xx/lpc17_adc.c b/arch/arm/src/lpc17xx/lpc17_adc.c index 490b25bf800..54d05933152 100644 --- a/arch/arm/src/lpc17xx/lpc17_adc.c +++ b/arch/arm/src/lpc17xx/lpc17_adc.c @@ -112,7 +112,7 @@ static int adc_setup(FAR struct adc_dev_s *dev); static void adc_shutdown(FAR struct adc_dev_s *dev); static void adc_rxint(FAR struct adc_dev_s *dev, bool enable); static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg); -static int adc_interrupt(int irq, void *context); +static int adc_interrupt(int irq, void *context, FAR void *arg); /**************************************************************************** * Private Data @@ -304,7 +304,7 @@ static int adc_setup(FAR struct adc_dev_s *dev) FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->ad_priv; int i; - int ret = irq_attach(priv->irq, adc_interrupt); + int ret = irq_attach(priv->irq, adc_interrupt, NULL); if (ret == OK) { for (i = 0; i < 8; i++) @@ -406,7 +406,7 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) * ****************************************************************************/ -static int adc_interrupt(int irq, void *context) +static int adc_interrupt(int irq, void *context, FAR void *arg) { #ifndef CONFIG_ADC_BURSTMODE #ifdef CONFIG_ADC_CHANLIST diff --git a/arch/arm/src/lpc17xx/lpc17_can.c b/arch/arm/src/lpc17xx/lpc17_can.c index f961bef5493..11ac88cc04d 100644 --- a/arch/arm/src/lpc17xx/lpc17_can.c +++ b/arch/arm/src/lpc17xx/lpc17_can.c @@ -217,7 +217,7 @@ static bool can_txempty(FAR struct can_dev_s *dev); /* CAN interrupts */ static void can_interrupt(FAR struct can_dev_s *dev); -static int can12_interrupt(int irq, void *context); +static int can12_interrupt(int irq, void *context, FAR void *arg); /* Initialization */ @@ -543,7 +543,7 @@ static int can_setup(FAR struct can_dev_s *dev) caninfo("CAN%d\n", priv->port); - ret = irq_attach(LPC17_IRQ_CAN, can12_interrupt); + ret = irq_attach(LPC17_IRQ_CAN, can12_interrupt, NULL); if (ret == OK) { up_enable_irq(LPC17_IRQ_CAN); @@ -1045,7 +1045,7 @@ static void can_interrupt(FAR struct can_dev_s *dev) * ****************************************************************************/ -static int can12_interrupt(int irq, void *context) +static int can12_interrupt(int irq, void *context, FAR void *arg) { /* Handle CAN1/2 interrupts */ diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.c b/arch/arm/src/lpc17xx/lpc17_ethernet.c index fa9b65a95f5..897acb237f7 100644 --- a/arch/arm/src/lpc17xx/lpc17_ethernet.c +++ b/arch/arm/src/lpc17xx/lpc17_ethernet.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/lpc17xx/lpc17_ethernet.c * - * Copyright (C) 2010-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2010-2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -335,7 +335,7 @@ static void lpc17_response(struct lpc17_driver_s *priv); static void lpc17_txdone_work(FAR void *arg); static void lpc17_rxdone_work(FAR void *arg); -static int lpc17_interrupt(int irq, void *context); +static int lpc17_interrupt(int irq, void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -1123,7 +1123,7 @@ static void lpc17_txdone_work(FAR void *arg) * ****************************************************************************/ -static int lpc17_interrupt(int irq, void *context) +static int lpc17_interrupt(int irq, void *context, FAR void *arg) { register struct lpc17_driver_s *priv; uint32_t status; @@ -1262,6 +1262,8 @@ static int lpc17_interrupt(int irq, void *context) if ((status & ETH_INT_TXDONE) != 0) { + int delay; + NETDEV_TXDONE(&priv->lp_dev); /* A packet transmission just completed */ @@ -1283,14 +1285,28 @@ static int lpc17_interrupt(int irq, void *context) work_cancel(ETHWORK, &priv->lp_txwork); - /* Then make sure that the TX poll timer is running (if it is - * already running, the following would restart it). This is - * necessary to avoid certain race conditions where the polling - * sequence can be interrupted. + /* Check if the poll timer is running. If it is not, then + * start it now. There is a race condition here: We may test + * the time remaining on the poll timer and determine that it + * is still running, but then the timer expires immiately. + * That should not be problem, however, the poll timer is + * queued for processing should be in the work queue and + * should execute immediately after we complete the TX poll. + * Inefficient, but not fatal. */ - (void)wd_start(priv->lp_txpoll, LPC17_WDDELAY, lpc17_poll_expiry, - 1, priv); + delay = wd_gettime(priv->lp_txpoll); + if (delay <= 0) + { + /* The poll timer is not running .. restart it. This is + * necessary to avoid certain race conditions where the + * polling sequence can be interrupted. + */ + + + (void)wd_start(priv->lp_txpoll, LPC17_WDDELAY, + lpc17_poll_expiry, 1, priv); + } /* Schedule TX-related work to be performed on the work thread */ @@ -3095,9 +3111,9 @@ static inline int lpc17_ethinitialize(int intf) /* Attach the IRQ to the driver */ #if CONFIG_LPC17_NINTERFACES > 1 - ret = irq_attach(priv->irq, lpc17_interrupt); + ret = irq_attach(priv->irq, lpc17_interrupt, NULL); #else - ret = irq_attach(LPC17_IRQ_ETH, lpc17_interrupt); + ret = irq_attach(LPC17_IRQ_ETH, lpc17_interrupt, NULL); #endif if (ret != 0) { diff --git a/arch/arm/src/lpc17xx/lpc17_gpdma.c b/arch/arm/src/lpc17xx/lpc17_gpdma.c index 2eb2edf16ab..8fba6cbaad4 100644 --- a/arch/arm/src/lpc17xx/lpc17_gpdma.c +++ b/arch/arm/src/lpc17xx/lpc17_gpdma.c @@ -190,7 +190,7 @@ static void lpc17_dmadone(struct lpc17_dmach_s *dmach) * ****************************************************************************/ -static int gpdma_interrupt(int irq, FAR void *context) +static int gpdma_interrupt(int irq, FAR void *context, FAR void *arg) { struct lpc17_dmach_s *dmach; uint32_t regval; @@ -315,7 +315,7 @@ void weak_function up_dmainitialize(void) /* Attach and enable the common interrupt handler */ - ret = irq_attach(LPC17_IRQ_GPDMA, gpdma_interrupt); + ret = irq_attach(LPC17_IRQ_GPDMA, gpdma_interrupt, NULL); if (ret == OK) { up_enable_irq(LPC17_IRQ_GPDMA); diff --git a/arch/arm/src/lpc17xx/lpc17_gpioint.c b/arch/arm/src/lpc17xx/lpc17_gpioint.c index 0c1ca613625..fded5b5b51c 100644 --- a/arch/arm/src/lpc17xx/lpc17_gpioint.c +++ b/arch/arm/src/lpc17xx/lpc17_gpioint.c @@ -402,7 +402,7 @@ static void lpc17_gpiodemux(uint32_t intbase, uint32_t intmask, * ****************************************************************************/ -static int lpc17_gpiointerrupt(int irq, void *context) +static int lpc17_gpiointerrupt(int irq, void *context, FAR void *arg) { /* Get the GPIO interrupt status */ @@ -468,7 +468,7 @@ void lpc17_gpioirqinitialize(void) * position in the NVIC with External Interrupt 3 */ - (void)irq_attach(LPC17_IRQ_EINT3, lpc17_gpiointerrupt); + (void)irq_attach(LPC17_IRQ_EINT3, lpc17_gpiointerrupt, NULL); up_enable_irq(LPC17_IRQ_EINT3); #elif defined(LPC178x) @@ -476,7 +476,7 @@ void lpc17_gpioirqinitialize(void) * GPIO2. */ - (void)irq_attach(LPC17_IRQ_GPIO, lpc17_gpiointerrupt); + (void)irq_attach(LPC17_IRQ_GPIO, lpc17_gpiointerrupt, NULL); up_enable_irq(LPC17_IRQ_GPIO); #endif diff --git a/arch/arm/src/lpc17xx/lpc17_i2c.c b/arch/arm/src/lpc17xx/lpc17_i2c.c index 554659818f5..30763fe177a 100644 --- a/arch/arm/src/lpc17xx/lpc17_i2c.c +++ b/arch/arm/src/lpc17xx/lpc17_i2c.c @@ -129,7 +129,7 @@ struct lpc17_i2cdev_s static int lpc17_i2c_start(struct lpc17_i2cdev_s *priv); static void lpc17_i2c_stop(struct lpc17_i2cdev_s *priv); -static int lpc17_i2c_interrupt(int irq, FAR void *context); +static int lpc17_i2c_interrupt(int irq, FAR void *context, void *arg); static void lpc17_i2c_timeout(int argc, uint32_t arg, ...); static void lpc17_i2c_setfrequency(struct lpc17_i2cdev_s *priv, uint32_t frequency); @@ -304,7 +304,7 @@ static int lpc17_i2c_transfer(FAR struct i2c_master_s *dev, } /**************************************************************************** - * Name: lpc17_i2c_interrupt + * Name: lpc17_stopnext * * Description: * Check if we need to issue STOP at the next message @@ -334,36 +334,13 @@ static void lpc17_stopnext(struct lpc17_i2cdev_s *priv) * ****************************************************************************/ -static int lpc17_i2c_interrupt(int irq, FAR void *context) +static int lpc17_i2c_interrupt(int irq, FAR void *context, void *arg) { - struct lpc17_i2cdev_s *priv; + struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *)arg; struct i2c_msg_s *msg; uint32_t state; -#ifdef CONFIG_LPC17_I2C0 - if (irq == LPC17_IRQ_I2C0) - { - priv = &g_i2c0dev; - } - else -#endif -#ifdef CONFIG_LPC17_I2C1 - if (irq == LPC17_IRQ_I2C1) - { - priv = &g_i2c1dev; - } - else -#endif -#ifdef CONFIG_LPC17_I2C2 - if (irq == LPC17_IRQ_I2C2) - { - priv = &g_i2c2dev; - } - else -#endif - { - PANIC(); - } + DEBUGASSERT(priv != NULL); /* Reference UM10360 19.10.5 */ @@ -608,7 +585,7 @@ struct i2c_master_s *lpc17_i2cbus_initialize(int port) /* Attach Interrupt Handler */ - irq_attach(priv->irqid, lpc17_i2c_interrupt); + irq_attach(priv->irqid, lpc17_i2c_interrupt, priv); /* Enable Interrupt Handler */ diff --git a/arch/arm/src/lpc17xx/lpc17_irq.c b/arch/arm/src/lpc17xx/lpc17_irq.c index ac8fb8855cd..01475fe5722 100644 --- a/arch/arm/src/lpc17xx/lpc17_irq.c +++ b/arch/arm/src/lpc17xx/lpc17_irq.c @@ -149,7 +149,7 @@ static void lpc17_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int lpc17_nmi(int irq, FAR void *context) +static int lpc17_nmi(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -157,7 +157,7 @@ static int lpc17_nmi(int irq, FAR void *context) return 0; } -static int lpc17_busfault(int irq, FAR void *context) +static int lpc17_busfault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Bus fault recived\n"); @@ -165,7 +165,7 @@ static int lpc17_busfault(int irq, FAR void *context) return 0; } -static int lpc17_usagefault(int irq, FAR void *context) +static int lpc17_usagefault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Usage fault received\n"); @@ -173,7 +173,7 @@ static int lpc17_usagefault(int irq, FAR void *context) return 0; } -static int lpc17_pendsv(int irq, FAR void *context) +static int lpc17_pendsv(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -181,7 +181,7 @@ static int lpc17_pendsv(int irq, FAR void *context) return 0; } -static int lpc17_dbgmonitor(int irq, FAR void *context) +static int lpc17_dbgmonitor(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -189,7 +189,7 @@ static int lpc17_dbgmonitor(int irq, FAR void *context) return 0; } -static int lpc17_reserved(int irq, FAR void *context) +static int lpc17_reserved(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -371,8 +371,8 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(LPC17_IRQ_SVCALL, up_svcall); - irq_attach(LPC17_IRQ_HARDFAULT, up_hardfault); + irq_attach(LPC17_IRQ_SVCALL, up_svcall, NULL); + irq_attach(LPC17_IRQ_HARDFAULT, up_hardfault, NULL); /* Set the priority of the SVCall interrupt */ @@ -388,22 +388,22 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(LPC17_IRQ_MEMFAULT, up_memfault); + irq_attach(LPC17_IRQ_MEMFAULT, up_memfault, NULL); up_enable_irq(LPC17_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(LPC17_IRQ_NMI, lpc17_nmi); + irq_attach(LPC17_IRQ_NMI, lpc17_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(LPC17_IRQ_MEMFAULT, up_memfault); + irq_attach(LPC17_IRQ_MEMFAULT, up_memfault, NULL); #endif - irq_attach(LPC17_IRQ_BUSFAULT, lpc17_busfault); - irq_attach(LPC17_IRQ_USAGEFAULT, lpc17_usagefault); - irq_attach(LPC17_IRQ_PENDSV, lpc17_pendsv); - irq_attach(LPC17_IRQ_DBGMONITOR, lpc17_dbgmonitor); - irq_attach(LPC17_IRQ_RESERVED, lpc17_reserved); + irq_attach(LPC17_IRQ_BUSFAULT, lpc17_busfault, NULL); + irq_attach(LPC17_IRQ_USAGEFAULT, lpc17_usagefault, NULL); + irq_attach(LPC17_IRQ_PENDSV, lpc17_pendsv, NULL); + irq_attach(LPC17_IRQ_DBGMONITOR, lpc17_dbgmonitor, NULL); + irq_attach(LPC17_IRQ_RESERVED, lpc17_reserved, NULL); #endif lpc17_dumpnvic("initial", LPC17_IRQ_NIRQS); diff --git a/arch/arm/src/lpc17xx/lpc17_pwm.c b/arch/arm/src/lpc17xx/lpc17_pwm.c index c284934570c..df3be30a74a 100644 --- a/arch/arm/src/lpc17xx/lpc17_pwm.c +++ b/arch/arm/src/lpc17xx/lpc17_pwm.c @@ -350,7 +350,7 @@ static int pwm_interrupt(struct lpc17_pwmtimer_s *priv) * ****************************************************************************/ -static int pwm_tim1interrupt(int irq, void *context) +static int pwm_tim1interrupt(int irq, void *context, FAR void *arg) { return pwm_interrupt(&g_pwm1dev); } diff --git a/arch/arm/src/lpc17xx/lpc17_sdcard.c b/arch/arm/src/lpc17xx/lpc17_sdcard.c index adf268f9d47..56ab0965780 100644 --- a/arch/arm/src/lpc17xx/lpc17_sdcard.c +++ b/arch/arm/src/lpc17xx/lpc17_sdcard.c @@ -345,7 +345,7 @@ static void lpc17_endtransfer(struct lpc17_dev_s *priv, sdio_eventset_t wkupeven /* Interrupt Handling *******************************************************/ -static int lpc17_interrupt(int irq, void *context); +static int lpc17_interrupt(int irq, void *context, FAR void *arg); /* SD Card Interface Methods ************************************************/ @@ -1203,7 +1203,7 @@ static void lpc17_endtransfer(struct lpc17_dev_s *priv, sdio_eventset_t wkupeven * ****************************************************************************/ -static int lpc17_interrupt(int irq, void *context) +static int lpc17_interrupt(int irq, void *context, FAR void *arg) { struct lpc17_dev_s *priv = &g_scard_dev; uint32_t enabled; @@ -1642,7 +1642,7 @@ static int lpc17_attach(FAR struct sdio_dev_s *dev) /* Attach the SD card interrupt handler */ - ret = irq_attach(LPC17_IRQ_MCI, lpc17_interrupt); + ret = irq_attach(LPC17_IRQ_MCI, lpc17_interrupt, NULL); if (ret == OK) { diff --git a/arch/arm/src/lpc17xx/lpc17_serial.c b/arch/arm/src/lpc17xx/lpc17_serial.c index 7062c521f48..9c13a06d4a1 100644 --- a/arch/arm/src/lpc17xx/lpc17_serial.c +++ b/arch/arm/src/lpc17xx/lpc17_serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/lpc17xx/lpc17_serial.c * - * Copyright (C) 2010-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2010-2013, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -104,7 +104,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); +static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -999,7 +999,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, up_interrupt); + ret = irq_attach(priv->irq, up_interrupt, dev); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -1041,44 +1041,14 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt(int irq, void *context) +static int up_interrupt(int irq, void *context, void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct up_dev_s *priv; uint32_t status; int passes; -#ifdef CONFIG_LPC17_UART0 - if (g_uart0priv.irq == irq) - { - dev = &g_uart0port; - } - else -#endif -#ifdef CONFIG_LPC17_UART1 - if (g_uart1priv.irq == irq) - { - dev = &g_uart1port; - } - else -#endif -#ifdef CONFIG_LPC17_UART2 - if (g_uart2priv.irq == irq) - { - dev = &g_uart2port; - } - else -#endif -#ifdef CONFIG_LPC17_UART3 - if (g_uart3priv.irq == irq) - { - dev = &g_uart3port; - } - else -#endif - { - PANIC(); - } + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct up_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, diff --git a/arch/arm/src/lpc17xx/lpc17_timerisr.c b/arch/arm/src/lpc17xx/lpc17_timerisr.c index 4f6d318642b..bb98e712ae3 100644 --- a/arch/arm/src/lpc17xx/lpc17_timerisr.c +++ b/arch/arm/src/lpc17xx/lpc17_timerisr.c @@ -91,7 +91,7 @@ * ****************************************************************************/ -static int lpc17_timerisr(int irq, uint32_t *regs) +static int lpc17_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -135,7 +135,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(LPC17_IRQ_SYSTICK, (xcpt_t)lpc17_timerisr); + (void)irq_attach(LPC17_IRQ_SYSTICK, (xcpt_t)lpc17_timerisr, NULL); /* Enable SysTick interrupts */ diff --git a/arch/arm/src/lpc17xx/lpc17_usbdev.c b/arch/arm/src/lpc17xx/lpc17_usbdev.c index ca4d5f90d80..5bcf3735b70 100644 --- a/arch/arm/src/lpc17xx/lpc17_usbdev.c +++ b/arch/arm/src/lpc17xx/lpc17_usbdev.c @@ -421,7 +421,7 @@ static void lpc17_dispatchrequest(struct lpc17_usbdev_s *priv, static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv); static inline void lpc17_ep0dataoutinterrupt(struct lpc17_usbdev_s *priv); static inline void lpc17_ep0dataininterrupt(struct lpc17_usbdev_s *priv); -static int lpc17_usbinterrupt(int irq, FAR void *context); +static int lpc17_usbinterrupt(int irq, FAR void *context, FAR void *arg); #ifdef CONFIG_LPC17_USBDEV_DMA static int lpc17_dmasetup(struct lpc17_usbdev_s *priv, uint8_t epphy, @@ -2051,7 +2051,7 @@ static inline void lpc17_ep0dataininterrupt(struct lpc17_usbdev_s *priv) * ****************************************************************************/ -static int lpc17_usbinterrupt(int irq, FAR void *context) +static int lpc17_usbinterrupt(int irq, FAR void *context, FAR void *arg) { struct lpc17_usbdev_s *priv = &g_usbdev; struct lpc17_ep_s *privep ; @@ -3321,7 +3321,7 @@ void up_usbinitialize(void) /* Attach USB controller interrupt handler */ - if (irq_attach(LPC17_IRQ_USB, lpc17_usbinterrupt) != 0) + if (irq_attach(LPC17_IRQ_USB, lpc17_usbinterrupt, NULL) != 0) { usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_IRQREGISTRATION), (uint16_t)LPC17_IRQ_USB); diff --git a/arch/arm/src/lpc17xx/lpc17_usbhost.c b/arch/arm/src/lpc17xx/lpc17_usbhost.c index e81f9f676ef..42825b02132 100644 --- a/arch/arm/src/lpc17xx/lpc17_usbhost.c +++ b/arch/arm/src/lpc17xx/lpc17_usbhost.c @@ -347,7 +347,7 @@ static int lpc17_ctrltd(struct lpc17_usbhost_s *priv, struct lpc17_ed_s *ed, /* Interrupt handling **********************************************************/ -static int lpc17_usbinterrupt(int irq, void *context); +static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg); /* USB host controller operations **********************************************/ @@ -1633,7 +1633,7 @@ errout_with_xfrinfo: * ****************************************************************************/ -static int lpc17_usbinterrupt(int irq, void *context) +static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg) { struct lpc17_usbhost_s *priv = &g_usbhost; struct lpc17_ed_s *ed; @@ -3844,7 +3844,7 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller) /* Attach USB host controller interrupt handler */ - if (irq_attach(LPC17_IRQ_USB, lpc17_usbinterrupt) != 0) + if (irq_attach(LPC17_IRQ_USB, lpc17_usbinterrupt, NULL) != 0) { uerr("ERROR: Failed to attach IRQ\n"); return NULL; diff --git a/arch/arm/src/lpc214x/lpc214x_serial.c b/arch/arm/src/lpc214x/lpc214x_serial.c index e1b3511f9ca..92675a538be 100644 --- a/arch/arm/src/lpc214x/lpc214x_serial.c +++ b/arch/arm/src/lpc214x/lpc214x_serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/lpc214x/lpc214x_serial.c * - * Copyright (C) 2007-2009, 2012-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2012-2013, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -88,7 +88,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); +static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -413,7 +413,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, up_interrupt); + ret = irq_attach(priv->irq, up_interrupt, dev); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -456,25 +456,14 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt(int irq, void *context) +static int up_interrupt(int irq, void *context, void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct up_dev_s *priv; uint8_t status; int passes; - if (g_uart1priv.irq == irq) - { - dev = &g_uart1port; - } - else if (g_uart0priv.irq == irq) - { - dev = &g_uart0port; - } - else - { - PANIC(); - } + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct up_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, diff --git a/arch/arm/src/lpc214x/lpc214x_timerisr.c b/arch/arm/src/lpc214x/lpc214x_timerisr.c index 027dfa6e7e6..1d756d37d64 100644 --- a/arch/arm/src/lpc214x/lpc214x_timerisr.c +++ b/arch/arm/src/lpc214x/lpc214x_timerisr.c @@ -87,7 +87,7 @@ #ifdef CONFIG_VECTORED_INTERRUPTS static int lpc214x_timerisr(uint32_t *regs) #else -static int lpc214x_timerisr(int irq, uint32_t *regs) +static int lpc214x_timerisr(int irq, uint32_t *regs, void *arg) #endif { /* Process timer interrupt */ @@ -157,7 +157,7 @@ void arm_timer_initialize(void) up_attach_vector(LPC214X_IRQ_SYSTIMER, LPC214X_SYSTIMER_VEC, (vic_vector_t)lpc214x_timerisr); #else - (void)irq_attach(LPC214X_IRQ_SYSTIMER, (xcpt_t)lpc214x_timerisr); + (void)irq_attach(LPC214X_IRQ_SYSTIMER, (xcpt_t)lpc214x_timerisr, NULL); #endif /* And enable the timer interrupt */ diff --git a/arch/arm/src/lpc214x/lpc214x_usbdev.c b/arch/arm/src/lpc214x/lpc214x_usbdev.c index 636c7391251..c39324dc5ae 100644 --- a/arch/arm/src/lpc214x/lpc214x_usbdev.c +++ b/arch/arm/src/lpc214x/lpc214x_usbdev.c @@ -428,7 +428,7 @@ static void lpc214x_dispatchrequest(struct lpc214x_usbdev_s *priv, static inline void lpc214x_ep0setup(struct lpc214x_usbdev_s *priv); static inline void lpc214x_ep0dataoutinterrupt(struct lpc214x_usbdev_s *priv); static inline void lpc214x_ep0dataininterrupt(struct lpc214x_usbdev_s *priv); -static int lpc214x_usbinterrupt(int irq, FAR void *context); +static int lpc214x_usbinterrupt(int irq, FAR void *context, FAR void *arg); #ifdef CONFIG_LPC214X_USBDEV_DMA static int lpc214x_dmasetup(struct lpc214x_usbdev_s *priv, uint8_t epphy, @@ -2014,7 +2014,7 @@ static inline void lpc214x_ep0dataininterrupt(struct lpc214x_usbdev_s *priv) * ****************************************************************************/ -static int lpc214x_usbinterrupt(int irq, FAR void *context) +static int lpc214x_usbinterrupt(int irq, FAR void *context, FAR void *arg) { struct lpc214x_usbdev_s *priv = &g_usbdev; struct lpc214x_ep_s *privep ; @@ -3235,7 +3235,7 @@ void up_usbinitialize(void) /* Attach USB controller interrupt handler */ - if (irq_attach(LPC214X_USB_IRQ, lpc214x_usbinterrupt) != 0) + if (irq_attach(LPC214X_USB_IRQ, lpc214x_usbinterrupt, NULL) != 0) { usbtrace(TRACE_DEVERROR(LPC214X_TRACEERR_IRQREGISTRATION), (uint16_t)LPC214X_USB_IRQ); diff --git a/arch/arm/src/lpc2378/lpc23xx_i2c.c b/arch/arm/src/lpc2378/lpc23xx_i2c.c index 5de046a39f9..8191179f110 100644 --- a/arch/arm/src/lpc2378/lpc23xx_i2c.c +++ b/arch/arm/src/lpc2378/lpc23xx_i2c.c @@ -134,7 +134,7 @@ struct lpc2378_i2cdev_s static int lpc2378_i2c_start(struct lpc2378_i2cdev_s *priv); static void lpc2378_i2c_stop(struct lpc2378_i2cdev_s *priv); -static int lpc2378_i2c_interrupt(int irq, FAR void *context); +static int lpc2378_i2c_interrupt(int irq, FAR void *context, FAR void *arg); static void lpc2378_i2c_timeout(int argc, uint32_t arg, ...); static void lpc2378_i2c_setfrequency(struct lpc2378_i2cdev_s *priv, uint32_t frequency); @@ -296,36 +296,13 @@ static void lpc2378_stopnext(struct lpc2378_i2cdev_s *priv) * ****************************************************************************/ -static int lpc2378_i2c_interrupt(int irq, FAR void *context) +static int lpc2378_i2c_interrupt(int irq, FAR void *context, FAR void *arg) { - struct lpc2378_i2cdev_s *priv; + struct lpc2378_i2cdev_s *priv = (struct lpc2378_i2cdev_s *)arg; struct i2c_msg_s *msg; uint32_t state; -#ifdef CONFIG_LPC2378_I2C0 - if (irq == I2C0_IRQ) - { - priv = &g_i2c0dev; - } - else -#endif -#ifdef CONFIG_LPC2378_I2C1 - if (irq == I2C1_IRQ) - { - priv = &g_i2c1dev; - } - else -#endif -#ifdef CONFIG_LPC2378_I2C2 - if (irq == I2C2_IRQ) - { - priv = &g_i2c2dev; - } - else -#endif - { - PANIC(); - } + DEBUGASSERT(priv != NULL); /* Reference UM10360 19.10.5 */ @@ -619,7 +596,7 @@ struct i2c_master_s *lpc2378_i2cbus_initialize(int port) /* Attach Interrupt Handler */ - irq_attach(priv->irqid, lpc2378_i2c_interrupt); + irq_attach(priv->irqid, lpc2378_i2c_interrupt, priv); /* Enable Interrupt Handler */ diff --git a/arch/arm/src/lpc2378/lpc23xx_serial.c b/arch/arm/src/lpc2378/lpc23xx_serial.c index 48e322ec15a..c927b07a2c0 100644 --- a/arch/arm/src/lpc2378/lpc23xx_serial.c +++ b/arch/arm/src/lpc2378/lpc23xx_serial.c @@ -96,7 +96,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); +static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t * status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -533,7 +533,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, up_interrupt); + ret = irq_attach(priv->irq, up_interrupt, dev); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled in the @@ -581,25 +581,14 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt(int irq, void *context) +static int up_interrupt(int irq, void *context, void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct up_dev_s *priv; uint8_t status; int passes; - if (g_uart0priv.irq == irq) - { - dev = &g_uart0port; - } - else if (g_uart2priv.irq == irq) - { - dev = &g_uart2port; - } - else - { - PANIC(); - } + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct up_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, until we have diff --git a/arch/arm/src/lpc2378/lpc23xx_timerisr.c b/arch/arm/src/lpc2378/lpc23xx_timerisr.c index 6d85b07c0f2..1cbd4b650de 100644 --- a/arch/arm/src/lpc2378/lpc23xx_timerisr.c +++ b/arch/arm/src/lpc2378/lpc23xx_timerisr.c @@ -96,7 +96,7 @@ #ifdef CONFIG_VECTORED_INTERRUPTS static int lpc23xx_timerisr(uint32_t * regs) #else -static int lpc23xx_timerisr(int irq, uint32_t * regs) +static int lpc23xx_timerisr(int irq, uint32_t * regs, FAR void *arg) #endif { static uint32_t tick; @@ -189,7 +189,7 @@ void arm_timer_initialize(void) #ifdef CONFIG_VECTORED_INTERRUPTS up_attach_vector(IRQ_SYSTIMER, ???, (vic_vector_t) lpc23xx_timerisr); #else - (void)irq_attach(IRQ_SYSTIMER, (xcpt_t)lpc23xx_timerisr); + (void)irq_attach(IRQ_SYSTIMER, (xcpt_t)lpc23xx_timerisr, NULL); #ifdef CONFIG_ARCH_IRQPRIO up_prioritize_irq(IRQ_SYSTIMER, PRIORITY_HIGHEST); #endif diff --git a/arch/arm/src/lpc31xx/lpc31_cgudrvr.h b/arch/arm/src/lpc31xx/lpc31_cgudrvr.h index 47a2e3917fa..8fbe96b88bf 100644 --- a/arch/arm/src/lpc31xx/lpc31_cgudrvr.h +++ b/arch/arm/src/lpc31xx/lpc31_cgudrvr.h @@ -672,7 +672,7 @@ void lpc31_setfdiv(enum lpc31_domainid_e dmnid, enum lpc31_clockid_e clkid, * **************************************************************************************************/ -void lpc31_pllconfig(const struct lpc31_pllconfig_s * const cfg); +void lpc31_pllconfig(const struct lpc31_pllconfig_s *const cfg); /********************************************************************************************** * Name: lpc31_hp0pllconfig diff --git a/arch/arm/src/lpc31xx/lpc31_ehci.c b/arch/arm/src/lpc31xx/lpc31_ehci.c index 345ec24dc63..475c4dea89d 100644 --- a/arch/arm/src/lpc31xx/lpc31_ehci.c +++ b/arch/arm/src/lpc31xx/lpc31_ehci.c @@ -514,7 +514,7 @@ static inline void lpc31_portsc_bottomhalf(void); static inline void lpc31_syserr_bottomhalf(void); static inline void lpc31_async_advance_bottomhalf(void); static void lpc31_ehci_bottomhalf(FAR void *arg); -static int lpc31_ehci_interrupt(int irq, FAR void *context); +static int lpc31_ehci_interrupt(int irq, FAR void *context, FAR void *arg); /* USB Host Controller Operations **********************************************/ @@ -3357,7 +3357,7 @@ static void lpc31_ehci_bottomhalf(FAR void *arg) * ****************************************************************************/ -static int lpc31_ehci_interrupt(int irq, FAR void *context) +static int lpc31_ehci_interrupt(int irq, FAR void *context, FAR void *arg) { uint32_t usbsts; uint32_t pending; @@ -5282,7 +5282,7 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller) /* Interrupt Configuration ***************************************************/ - ret = irq_attach(LPC31_IRQ_USBOTG, lpc31_ehci_interrupt); + ret = irq_attach(LPC31_IRQ_USBOTG, lpc31_ehci_interrupt, NULL); if (ret != 0) { usbhost_trace1(EHCI_TRACE1_IRQATTACH_FAILED, LPC31_IRQ_USBOTG); diff --git a/arch/arm/src/lpc31xx/lpc31_i2c.c b/arch/arm/src/lpc31xx/lpc31_i2c.c index 1f27c4d1ff2..8d79ac56e3d 100644 --- a/arch/arm/src/lpc31xx/lpc31_i2c.c +++ b/arch/arm/src/lpc31xx/lpc31_i2c.c @@ -3,7 +3,7 @@ * * Author: David Hewson * - * Copyright (C) 2010-2011, 2014, 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2010-2011, 2014, 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -112,7 +112,7 @@ static struct lpc31_i2cdev_s i2cdevices[2]; * Private Function Prototypes ****************************************************************************/ -static int i2c_interrupt(int irq, FAR void *context); +static int i2c_interrupt(int irq, FAR void *context, FAR void *arg); static void i2c_progress(struct lpc31_i2cdev_s *priv); static void i2c_timeout(int argc, uint32_t arg, ...); static void i2c_hwreset(struct lpc31_i2cdev_s *priv); @@ -184,18 +184,12 @@ static void i2c_setfrequency(struct lpc31_i2cdev_s *priv, uint32_t frequency) * ****************************************************************************/ -static int i2c_interrupt(int irq, FAR void *context) +static int i2c_interrupt(int irq, FAR void *context, FAR void *arg) { - if (irq == LPC31_IRQ_I2C0) - { - i2c_progress(&i2cdevices[0]); - } - - if (irq == LPC31_IRQ_I2C1) - { - i2c_progress(&i2cdevices[1]); - } + struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *)arg; + DEBUGASSERT(priv != NULL); + i2c_progress(priv); return OK; } @@ -585,7 +579,7 @@ struct i2c_master_s *lpc31_i2cbus_initialize(int port) /* Attach Interrupt Handler */ - irq_attach(priv->irqid, i2c_interrupt); + irq_attach(priv->irqid, i2c_interrupt, priv); /* Enable Interrupt Handler */ diff --git a/arch/arm/src/lpc31xx/lpc31_serial.c b/arch/arm/src/lpc31xx/lpc31_serial.c index bf5ac8cd586..fa5f3b4563f 100644 --- a/arch/arm/src/lpc31xx/lpc31_serial.c +++ b/arch/arm/src/lpc31xx/lpc31_serial.c @@ -88,7 +88,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); +static int up_interrupt(int irq, void *context, FAR void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -444,7 +444,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(LPC31_IRQ_UART, up_interrupt); + ret = irq_attach(LPC31_IRQ_UART, up_interrupt, NULL); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -482,7 +482,7 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt(int irq, void *context) +static int up_interrupt(int irq, void *context, FAR void *arg) { struct uart_dev_s *dev = &g_uartport; uint8_t status; diff --git a/arch/arm/src/lpc31xx/lpc31_timerisr.c b/arch/arm/src/lpc31xx/lpc31_timerisr.c index ab01f01ced3..9a4932b7a69 100644 --- a/arch/arm/src/lpc31xx/lpc31_timerisr.c +++ b/arch/arm/src/lpc31xx/lpc31_timerisr.c @@ -66,7 +66,7 @@ * ****************************************************************************/ -static int lpc31_timerisr(int irq, uint32_t *regs) +static int lpc31_timerisr(int irq, uint32_t *regs, void *arg) { /* Clear the lattched timer interrupt (Writing any value to the CLEAR register * clears the interrupt generated by the counter timer @@ -135,7 +135,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(LPC31_IRQ_TMR0, (xcpt_t)lpc31_timerisr); + (void)irq_attach(LPC31_IRQ_TMR0, (xcpt_t)lpc31_timerisr, NULL); /* Clear any latched timer interrupt (Writing any value to the CLEAR register * clears the latched interrupt generated by the counter timer) diff --git a/arch/arm/src/lpc31xx/lpc31_usbdev.c b/arch/arm/src/lpc31xx/lpc31_usbdev.c index 1cc9ec0d38b..90f877a1897 100644 --- a/arch/arm/src/lpc31xx/lpc31_usbdev.c +++ b/arch/arm/src/lpc31xx/lpc31_usbdev.c @@ -396,7 +396,7 @@ static void lpc31_ep0complete(struct lpc31_usbdev_s *priv, uint8_t epphy) static void lpc31_ep0nak(struct lpc31_usbdev_s *priv, uint8_t epphy); static bool lpc31_epcomplete(struct lpc31_usbdev_s *priv, uint8_t epphy); -static int lpc31_usbinterrupt(int irq, FAR void *context); +static int lpc31_usbinterrupt(int irq, FAR void *context, FAR void *arg); /* Endpoint operations *********************************************************/ @@ -1677,7 +1677,7 @@ bool lpc31_epcomplete(struct lpc31_usbdev_s *priv, uint8_t epphy) * ****************************************************************************/ -static int lpc31_usbinterrupt(int irq, FAR void *context) +static int lpc31_usbinterrupt(int irq, FAR void *context, FAR void *arg) { struct lpc31_usbdev_s *priv = &g_usbdev; uint32_t disr, portsc1, n; @@ -2572,7 +2572,7 @@ void up_usbinitialize(void) /* Attach USB controller interrupt handler */ - if (irq_attach(LPC31_IRQ_USBOTG, lpc31_usbinterrupt) != 0) + if (irq_attach(LPC31_IRQ_USBOTG, lpc31_usbinterrupt, NULL) != 0) { usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_IRQREGISTRATION), (uint16_t)LPC31_IRQ_USBOTG); diff --git a/arch/arm/src/lpc43xx/lpc43_adc.c b/arch/arm/src/lpc43xx/lpc43_adc.c index 2a9db4297d9..42bfbac817b 100644 --- a/arch/arm/src/lpc43xx/lpc43_adc.c +++ b/arch/arm/src/lpc43xx/lpc43_adc.c @@ -141,7 +141,7 @@ static int adc_setup(FAR struct adc_dev_s *dev); static void adc_shutdown(FAR struct adc_dev_s *dev); static void adc_rxint(FAR struct adc_dev_s *dev, bool enable); static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg); -static int adc_interrupt(int irq, void *context); +static int adc_interrupt(int irq, void *context, FAR void *arg); /**************************************************************************** * Private Data @@ -351,7 +351,7 @@ static int adc_setup(FAR struct adc_dev_s *dev) { FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->ad_priv; - int ret = irq_attach(priv->irq, adc_interrupt); + int ret = irq_attach(priv->irq, adc_interrupt, NULL); if (ret == OK) { up_enable_irq(priv->irq); @@ -457,7 +457,7 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) * ****************************************************************************/ -static int adc_interrupt(int irq, void *context) +static int adc_interrupt(int irq, void *context, FAR void *arg) { FAR struct up_dev_s *priv = (FAR struct up_dev_s *)g_adcdev.ad_priv; diff --git a/arch/arm/src/lpc43xx/lpc43_dac.c b/arch/arm/src/lpc43xx/lpc43_dac.c index 51b7000def9..0a81e41b2c5 100644 --- a/arch/arm/src/lpc43xx/lpc43_dac.c +++ b/arch/arm/src/lpc43xx/lpc43_dac.c @@ -89,7 +89,7 @@ static void dac_shutdown(FAR struct dac_dev_s *dev); static void dac_txint(FAR struct dac_dev_s *dev, bool enable); static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg); static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg); -static int dac_interrupt(int irq, void *context); +static int dac_interrupt(int irq, void *context, FAR void *arg); /**************************************************************************** * Private Data @@ -177,7 +177,7 @@ static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg) return 0; } -static int dac_interrupt(int irq, void *context) +static int dac_interrupt(int irq, void *context, FAR void *arg) { } diff --git a/arch/arm/src/lpc43xx/lpc43_ehci.c b/arch/arm/src/lpc43xx/lpc43_ehci.c index 2893369cede..5af61fa9394 100644 --- a/arch/arm/src/lpc43xx/lpc43_ehci.c +++ b/arch/arm/src/lpc43xx/lpc43_ehci.c @@ -505,7 +505,7 @@ static inline void lpc43_portsc_bottomhalf(void); static inline void lpc43_syserr_bottomhalf(void); static inline void lpc43_async_advance_bottomhalf(void); static void lpc43_ehci_bottomhalf(FAR void *arg); -static int lpc43_ehci_interrupt(int irq, FAR void *context); +static int lpc43_ehci_interrupt(int irq, FAR void *context, FAR void *arg); /* USB Host Controller Operations **********************************************/ @@ -3194,7 +3194,7 @@ static void lpc43_ehci_bottomhalf(FAR void *arg) * ****************************************************************************/ -static int lpc43_ehci_interrupt(int irq, FAR void *context) +static int lpc43_ehci_interrupt(int irq, FAR void *context, FAR void *arg) { uint32_t usbsts; uint32_t pending; @@ -5089,7 +5089,7 @@ FAR struct usbhost_connection_s *lpc43_ehci_initialize(int controller) /* Interrupt Configuration ***************************************************/ - ret = irq_attach(LPC43M4_IRQ_USB0, lpc43_ehci_interrupt); + ret = irq_attach(LPC43M4_IRQ_USB0, lpc43_ehci_interrupt, NULL); if (ret != 0) { usbhost_trace1(EHCI_TRACE1_IRQATTACH_FAILED, LPC43M4_IRQ_USB0); diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c index f6f666c7ca5..425c8a867b0 100644 --- a/arch/arm/src/lpc43xx/lpc43_ethernet.c +++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/lpc43/lpc43_eth.c * - * Copyright (C) 2011-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -594,7 +594,7 @@ static void lpc43_freeframe(FAR struct lpc43_ethmac_s *priv); static void lpc43_txdone(FAR struct lpc43_ethmac_s *priv); static void lpc43_interrupt_work(FAR void *arg); -static int lpc43_interrupt(int irq, FAR void *context); +static int lpc43_interrupt(int irq, FAR void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -1862,17 +1862,32 @@ static void lpc43_txdone(FAR struct lpc43_ethmac_s *priv) if (priv->inflight <= 0) { + int delay; + /* Cancel the TX timeout */ wd_cancel(priv->txtimeout); - /* Then make sure that the TX poll timer is running (if it is already - * running, the following would restart it). This is necessary to - * avoid certain race conditions where the polling sequence can be - * interrupted. + /* Check if the poll timer is running. If it is not, then start it + * now. There is a race condition here: We may test the time + * remaining on the poll timer and determine that it is still running, + * but then the timer expires immiately. That should not be problem, + * however, the poll timer processing should be in the work queue and + * should execute immediately after we complete the TX poll. + * Inefficient, but not fatal. */ - (void)wd_start(priv->txpoll, LPC43_WDDELAY, lpc43_poll_expiry, 1, priv); + delay = wd_gettime(priv->txpoll); + if (delay <= 0) + { + /* The poll timer is not running .. restart it. This is necessary + * to avoid certain race conditions where the polling sequence can + * be interrupted. + */ + + (void)wd_start(priv->txpoll, LPC43_WDDELAY, lpc43_poll_expiry, + 1, priv); + } /* And disable further TX interrupts. */ @@ -2004,7 +2019,7 @@ static void lpc43_interrupt_work(FAR void *arg) * ****************************************************************************/ -static int lpc43_interrupt(int irq, FAR void *context) +static int lpc43_interrupt(int irq, FAR void *context, FAR void *arg) { FAR struct lpc43_ethmac_s *priv = &g_lpc43ethmac; uint32_t dmasr; @@ -3861,7 +3876,7 @@ static inline int lpc43_ethinitialize(void) /* Attach the IRQ to the driver */ - if (irq_attach(LPC43M4_IRQ_ETHERNET, lpc43_interrupt)) + if (irq_attach(LPC43M4_IRQ_ETHERNET, lpc43_interrupt, NULL)) { /* We could not attach the ISR to the interrupt */ diff --git a/arch/arm/src/lpc43xx/lpc43_gpdma.c b/arch/arm/src/lpc43xx/lpc43_gpdma.c index ab2942189cd..22c5213c2ef 100644 --- a/arch/arm/src/lpc43xx/lpc43_gpdma.c +++ b/arch/arm/src/lpc43xx/lpc43_gpdma.c @@ -190,7 +190,7 @@ static void lpc43_dmadone(struct lpc43_dmach_s *dmach) * ****************************************************************************/ -static int gpdma_interrupt(int irq, FAR void *context) +static int gpdma_interrupt(int irq, FAR void *context, FAR void *arg) { struct lpc43_dmach_s *dmach; uint32_t regval; @@ -315,7 +315,7 @@ void weak_function up_dmainitialize(void) /* Attach and enable the common interrupt handler */ - ret = irq_attach(LPC43M4_IRQ_DMA, gpdma_interrupt); + ret = irq_attach(LPC43M4_IRQ_DMA, gpdma_interrupt, NULL); if (ret == OK) { up_enable_irq(LPC43M4_IRQ_DMA); diff --git a/arch/arm/src/lpc43xx/lpc43_i2c.c b/arch/arm/src/lpc43xx/lpc43_i2c.c index 49a77bb8b51..2c8fcb63bee 100644 --- a/arch/arm/src/lpc43xx/lpc43_i2c.c +++ b/arch/arm/src/lpc43xx/lpc43_i2c.c @@ -130,7 +130,7 @@ static struct lpc43_i2cdev_s g_i2c1dev; static int lpc43_i2c_start(struct lpc43_i2cdev_s *priv); static void lpc43_i2c_stop(struct lpc43_i2cdev_s *priv); -static int lpc43_i2c_interrupt(int irq, FAR void *context); +static int lpc43_i2c_interrupt(int irq, FAR void *context, FAR void *arg); static void lpc43_i2c_timeout(int argc, uint32_t arg, ...); static void lpc43_i2c_setfrequency(struct lpc43_i2cdev_s *priv, uint32_t frequency); @@ -277,29 +277,13 @@ void lpc32_i2c_nextmsg(struct lpc43_i2cdev_s *priv) * ****************************************************************************/ -static int lpc43_i2c_interrupt(int irq, FAR void *context) +static int lpc43_i2c_interrupt(int irq, FAR void *context, FAR void *arg) { - struct lpc43_i2cdev_s *priv; + struct lpc43_i2cdev_s *priv = (struct lpc43_i2cdev_s *)arg; struct i2c_msg_s *msg; uint32_t state; -#ifdef CONFIG_LPC43_I2C0 - if (irq == LPC43M0_IRQ_I2C0) - { - priv = &g_i2c0dev; - } - else -#endif -#ifdef CONFIG_LPC43_I2C1 - if (irq == LPC43_IRQ_I2C1) - { - priv = &g_i2c1dev; - } - else -#endif - { - PANIC(); - } + DEBUGASSERT(priv != NULL); /* Reference UM10360 19.10.5 */ @@ -558,7 +542,7 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port) /* Attach Interrupt Handler */ - irq_attach(priv->irqid, lpc43_i2c_interrupt); + irq_attach(priv->irqid, lpc43_i2c_interrupt, priv); /* Enable Interrupt Handler */ diff --git a/arch/arm/src/lpc43xx/lpc43_irq.c b/arch/arm/src/lpc43xx/lpc43_irq.c index 09680bd9e91..d51a8e48f71 100644 --- a/arch/arm/src/lpc43xx/lpc43_irq.c +++ b/arch/arm/src/lpc43xx/lpc43_irq.c @@ -154,7 +154,7 @@ static void lpc43_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int lpc43_nmi(int irq, FAR void *context) +static int lpc43_nmi(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -162,7 +162,7 @@ static int lpc43_nmi(int irq, FAR void *context) return 0; } -static int lpc43_busfault(int irq, FAR void *context) +static int lpc43_busfault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Bus fault recived\n"); @@ -170,7 +170,7 @@ static int lpc43_busfault(int irq, FAR void *context) return 0; } -static int lpc43_usagefault(int irq, FAR void *context) +static int lpc43_usagefault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Usage fault received\n"); @@ -178,7 +178,7 @@ static int lpc43_usagefault(int irq, FAR void *context) return 0; } -static int lpc43_pendsv(int irq, FAR void *context) +static int lpc43_pendsv(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -186,7 +186,7 @@ static int lpc43_pendsv(int irq, FAR void *context) return 0; } -static int lpc43_dbgmonitor(int irq, FAR void *context) +static int lpc43_dbgmonitor(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -194,7 +194,7 @@ static int lpc43_dbgmonitor(int irq, FAR void *context) return 0; } -static int lpc43_reserved(int irq, FAR void *context) +static int lpc43_reserved(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -364,8 +364,8 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(LPC43_IRQ_SVCALL, up_svcall); - irq_attach(LPC43_IRQ_HARDFAULT, up_hardfault); + irq_attach(LPC43_IRQ_SVCALL, up_svcall, NULL); + irq_attach(LPC43_IRQ_HARDFAULT, up_hardfault, NULL); /* Set the priority of the SVCall interrupt */ @@ -381,22 +381,22 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(LPC43_IRQ_MEMFAULT, up_memfault); + irq_attach(LPC43_IRQ_MEMFAULT, up_memfault, NULL); up_enable_irq(LPC43_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(LPC43_IRQ_NMI, lpc43_nmi); + irq_attach(LPC43_IRQ_NMI, lpc43_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(LPC43_IRQ_MEMFAULT, up_memfault); + irq_attach(LPC43_IRQ_MEMFAULT, up_memfault, NULL); #endif - irq_attach(LPC43_IRQ_BUSFAULT, lpc43_busfault); - irq_attach(LPC43_IRQ_USAGEFAULT, lpc43_usagefault); - irq_attach(LPC43_IRQ_PENDSV, lpc43_pendsv); - irq_attach(LPC43_IRQ_DBGMONITOR, lpc43_dbgmonitor); - irq_attach(LPC43_IRQ_RESERVED, lpc43_reserved); + irq_attach(LPC43_IRQ_BUSFAULT, lpc43_busfault, NULL); + irq_attach(LPC43_IRQ_USAGEFAULT, lpc43_usagefault, NULL); + irq_attach(LPC43_IRQ_PENDSV, lpc43_pendsv, NULL); + irq_attach(LPC43_IRQ_DBGMONITOR, lpc43_dbgmonitor, NULL); + irq_attach(LPC43_IRQ_RESERVED, lpc43_reserved, NULL); #endif lpc43_dumpnvic("initial", LPC43M4_IRQ_NIRQS); diff --git a/arch/arm/src/lpc43xx/lpc43_rit.c b/arch/arm/src/lpc43xx/lpc43_rit.c index c0bf633256f..c39e4b7a383 100644 --- a/arch/arm/src/lpc43xx/lpc43_rit.c +++ b/arch/arm/src/lpc43xx/lpc43_rit.c @@ -86,7 +86,7 @@ struct timespec g_ts; * Private Functions ****************************************************************************/ -static int lpc43_RIT_isr(int irq, FAR void *context) +static int lpc43_RIT_isr(int irq, FAR void *context, FAR void *arg) { irqstate_t flags; @@ -166,7 +166,7 @@ void arm_timer_initialize(void) /* Set up the IRQ here */ - irq_attach(LPC43M4_IRQ_RITIMER, lpc43_RIT_isr); + irq_attach(LPC43M4_IRQ_RITIMER, lpc43_RIT_isr, NULL); /* Compute how many seconds per tick we have on the main clock. If it is * 204MHz for example, then there should be about 4.90ns per tick diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c index 7fb42ee0353..bf3e9613bfb 100644 --- a/arch/arm/src/lpc43xx/lpc43_serial.c +++ b/arch/arm/src/lpc43xx/lpc43_serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/lpc43xx/lpc43_serial.c * - * Copyright (C) 2012-2013, 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013, 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -106,7 +106,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); +static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); #ifdef HAVE_RS485 static inline int up_set_rs485_mode(struct up_dev_s *priv, @@ -661,7 +661,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, up_interrupt); + ret = irq_attach(priv->irq, up_interrupt, dev); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -702,44 +702,14 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt(int irq, void *context) +static int up_interrupt(int irq, void *context, void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct up_dev_s *priv; uint32_t status; int passes; -#ifdef CONFIG_LPC43_USART0 - if (g_usart0priv.irq == irq) - { - dev = &g_usart0port; - } - else -#endif -#ifdef CONFIG_LPC43_UART1 - if (g_uart1priv.irq == irq) - { - dev = &g_uart1port; - } - else -#endif -#ifdef CONFIG_LPC43_USART2 - if (g_usart2priv.irq == irq) - { - dev = &g_usart2port; - } - else -#endif -#ifdef CONFIG_LPC43_USART3 - if (g_usart3priv.irq == irq) - { - dev = &g_usart3port; - } - else -#endif - { - PANIC(); - } + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct up_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, diff --git a/arch/arm/src/lpc43xx/lpc43_tickless_rit.c b/arch/arm/src/lpc43xx/lpc43_tickless_rit.c index ce0f7d63759..cacfb47c91b 100644 --- a/arch/arm/src/lpc43xx/lpc43_tickless_rit.c +++ b/arch/arm/src/lpc43xx/lpc43_tickless_rit.c @@ -536,7 +536,7 @@ static inline void lpc43_tl_alarm(uint32_t curr) /* Interrupt handler */ -static int lpc43_tl_isr(int irq, FAR void *context) +static int lpc43_tl_isr(int irq, FAR void *context, FAR void *arg) { lpc43_tl_sync_up(); @@ -624,7 +624,7 @@ void arm_timer_initialize(void) lpc43_tl_set_reset_on_match(false); lpc43_tl_clear_interrupt(); - irq_attach(LPC43M4_IRQ_RITIMER, lpc43_tl_isr); + irq_attach(LPC43M4_IRQ_RITIMER, lpc43_tl_isr, NULL); up_enable_irq(LPC43M4_IRQ_RITIMER); lpc43_tl_init_timer_vars(); diff --git a/arch/arm/src/lpc43xx/lpc43_timer.c b/arch/arm/src/lpc43xx/lpc43_timer.c index 0d8b35c9110..decc110dd49 100644 --- a/arch/arm/src/lpc43xx/lpc43_timer.c +++ b/arch/arm/src/lpc43xx/lpc43_timer.c @@ -113,7 +113,7 @@ static void lpc43_putreg(uint32_t val, uint32_t addr); /* Interrupt handling *******************************************************/ -static int lpc43_interrupt(int irq, FAR void *context); +static int lpc43_interrupt(int irq, FAR void *context, FAR void *arg); /* "Lower half" driver methods **********************************************/ @@ -336,7 +336,7 @@ void tmr_clk_disable(uint16_t tmrid) * ****************************************************************************/ -static int lpc43_interrupt(int irq, FAR void *context) +static int lpc43_interrupt(int irq, FAR void *context, FAR void *arg) { uint8_t chan_int = 0x0f; FAR struct lpc43_lowerhalf_s *priv = &g_tmrdevs[irq-LPC43M4_IRQ_TIMER0]; @@ -757,7 +757,7 @@ void lpc43_tmrinitialize(FAR const char *devpath, int irq) priv->ops = &g_tmrops; - (void)irq_attach(irq, lpc43_interrupt); + (void)irq_attach(irq, lpc43_interrupt, NULL); /* Enable NVIC interrupt. */ diff --git a/arch/arm/src/lpc43xx/lpc43_timerisr.c b/arch/arm/src/lpc43xx/lpc43_timerisr.c index 8b02b4c0991..a76cd54dc36 100644 --- a/arch/arm/src/lpc43xx/lpc43_timerisr.c +++ b/arch/arm/src/lpc43xx/lpc43_timerisr.c @@ -90,7 +90,7 @@ * ****************************************************************************/ -static int lpc43_timerisr(int irq, uint32_t *regs) +static int lpc43_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -134,7 +134,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(LPC43_IRQ_SYSTICK, (xcpt_t)lpc43_timerisr); + (void)irq_attach(LPC43_IRQ_SYSTICK, (xcpt_t)lpc43_timerisr, NULL); /* Enable SysTick interrupts */ diff --git a/arch/arm/src/lpc43xx/lpc43_usb0dev.c b/arch/arm/src/lpc43xx/lpc43_usb0dev.c index c583dd30a18..26bb600270b 100644 --- a/arch/arm/src/lpc43xx/lpc43_usb0dev.c +++ b/arch/arm/src/lpc43xx/lpc43_usb0dev.c @@ -415,7 +415,7 @@ static void lpc43_ep0complete(struct lpc43_usbdev_s *priv, uint8_t epphy) static void lpc43_ep0nak(struct lpc43_usbdev_s *priv, uint8_t epphy); static bool lpc43_epcomplete(struct lpc43_usbdev_s *priv, uint8_t epphy); -static int lpc43_usbinterrupt(int irq, FAR void *context); +static int lpc43_usbinterrupt(int irq, FAR void *context, FAR void *arg); /* Endpoint operations *********************************************************/ @@ -1766,7 +1766,7 @@ bool lpc43_epcomplete(struct lpc43_usbdev_s *priv, uint8_t epphy) * ****************************************************************************/ -static int lpc43_usbinterrupt(int irq, FAR void *context) +static int lpc43_usbinterrupt(int irq, FAR void *context, FAR void *arg) { struct lpc43_usbdev_s *priv = &g_usbdev; uint32_t disr, portsc1, n; @@ -2722,7 +2722,7 @@ void up_usbinitialize(void) /* Attach USB controller interrupt handler */ - irq_attach(LPC43M4_IRQ_USB0, lpc43_usbinterrupt); + irq_attach(LPC43M4_IRQ_USB0, lpc43_usbinterrupt, NULL); up_enable_irq(LPC43M4_IRQ_USB0); leave_critical_section(flags); diff --git a/arch/arm/src/moxart/moxart_irq.c b/arch/arm/src/moxart/moxart_irq.c index 31ed83c80fb..b81baeab21b 100644 --- a/arch/arm/src/moxart/moxart_irq.c +++ b/arch/arm/src/moxart/moxart_irq.c @@ -138,7 +138,7 @@ void up_irqinitialize(void) /* Setup UART shared interrupt */ - irq_attach(CONFIG_UART_MOXA_SHARED_IRQ, uart_decodeirq); + irq_attach(CONFIG_UART_MOXA_SHARED_IRQ, uart_decodeirq, NULL); up_enable_irq(CONFIG_UART_MOXA_SHARED_IRQ); /* And finally, enable interrupts */ diff --git a/arch/arm/src/moxart/moxart_timer.c b/arch/arm/src/moxart/moxart_timer.c index 1b281f05dd0..afc79e4d513 100644 --- a/arch/arm/src/moxart/moxart_timer.c +++ b/arch/arm/src/moxart/moxart_timer.c @@ -98,7 +98,7 @@ static uint32_t cmp = BOARD_32KOSC_FREQUENCY / 100; * ****************************************************************************/ -static int moxart_timerisr(int irq, uint32_t *regs) +static int moxart_timerisr(int irq, uint32_t *regs, void *arg) { uint32_t state; @@ -148,7 +148,7 @@ void arm_timer_initialize(void) /* Attach and enable the timer interrupt */ - irq_attach(IRQ_SYSTIMER, (xcpt_t)moxart_timerisr); + irq_attach(IRQ_SYSTIMER, (xcpt_t)moxart_timerisr, NULL); up_enable_irq(IRQ_SYSTIMER); ftintc010_set_trig_mode(IRQ_SYSTIMER, 1); ftintc010_set_trig_level(IRQ_SYSTIMER, 0); diff --git a/arch/arm/src/nuc1xx/nuc_irq.c b/arch/arm/src/nuc1xx/nuc_irq.c index 66f6d78044d..6fc6db1d2f5 100644 --- a/arch/arm/src/nuc1xx/nuc_irq.c +++ b/arch/arm/src/nuc1xx/nuc_irq.c @@ -138,7 +138,7 @@ static void nuc_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int nuc_nmi(int irq, FAR void *context) +static int nuc_nmi(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -146,7 +146,7 @@ static int nuc_nmi(int irq, FAR void *context) return 0; } -static int nuc_pendsv(int irq, FAR void *context) +static int nuc_pendsv(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -154,7 +154,7 @@ static int nuc_pendsv(int irq, FAR void *context) return 0; } -static int nuc_reserved(int irq, FAR void *context) +static int nuc_reserved(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -231,15 +231,15 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(NUC_IRQ_SVCALL, up_svcall); - irq_attach(NUC_IRQ_HARDFAULT, up_hardfault); + irq_attach(NUC_IRQ_SVCALL, up_svcall, NULL); + irq_attach(NUC_IRQ_HARDFAULT, up_hardfault, NULL); /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(NUC_IRQ_NMI, nuc_nmi); - irq_attach(NUC_IRQ_PENDSV, nuc_pendsv); - irq_attach(NUC_IRQ_RESERVED, nuc_reserved); + irq_attach(NUC_IRQ_NMI, nuc_nmi, NULL); + irq_attach(NUC_IRQ_PENDSV, nuc_pendsv, NULL); + irq_attach(NUC_IRQ_RESERVED, nuc_reserved, NULL); #endif nuc_dumpnvic("initial", NR_IRQS); diff --git a/arch/arm/src/nuc1xx/nuc_serial.c b/arch/arm/src/nuc1xx/nuc_serial.c index a098db77ce3..0932cfaf99d 100644 --- a/arch/arm/src/nuc1xx/nuc_serial.c +++ b/arch/arm/src/nuc1xx/nuc_serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/nuc1xx/nuc_serial.c * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -101,7 +101,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); +static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -568,7 +568,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, up_interrupt); + ret = irq_attach(priv->irq, up_interrupt, dev); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -610,9 +610,9 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt(int irq, void *context) +static int up_interrupt(int irq, void *context, void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct nuc_dev_s *priv; uint32_t isr; uint32_t regval; @@ -620,30 +620,7 @@ static int up_interrupt(int irq, void *context) bool rxto; bool rxfe; -#ifdef CONFIG_NUC_UART0 - if (g_uart0priv.irq == irq) - { - dev = &g_uart0port; - } - else -#endif -#ifdef CONFIG_NUC_UART1 - if (g_uart1priv.irq == irq) - { - dev = &g_uart1port; - } - else -#endif -#ifdef CONFIG_NUC_UART2 - if (g_uart2priv.irq == irq) - { - dev = &g_uart2port; - } - else -#endif - { - PANIC(); - } + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct nuc_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, diff --git a/arch/arm/src/nuc1xx/nuc_timerisr.c b/arch/arm/src/nuc1xx/nuc_timerisr.c index c32dcc66c03..02b99ba9ae7 100644 --- a/arch/arm/src/nuc1xx/nuc_timerisr.c +++ b/arch/arm/src/nuc1xx/nuc_timerisr.c @@ -156,7 +156,7 @@ static inline void nuc_lock(void) * ****************************************************************************/ -static int nuc_timerisr(int irq, uint32_t *regs) +static int nuc_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -226,7 +226,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(NUC_IRQ_SYSTICK, (xcpt_t)nuc_timerisr); + (void)irq_attach(NUC_IRQ_SYSTICK, (xcpt_t)nuc_timerisr, NULL); /* Enable SysTick interrupts. We need to select the core clock here if * we are not using one of the alternative clock sources above. diff --git a/arch/arm/src/sam34/sam4cm_cpupause.c b/arch/arm/src/sam34/sam4cm_cpupause.c index daf6fd76b4e..f2587811276 100644 --- a/arch/arm/src/sam34/sam4cm_cpupause.c +++ b/arch/arm/src/sam34/sam4cm_cpupause.c @@ -203,7 +203,7 @@ int up_cpu_paused(int cpu) * ****************************************************************************/ -int arm_pause_handler(int irq, void *c) +int arm_pause_handler(int irq, void *c, FAR void *arg) { int cpu = up_cpu_index(); diff --git a/arch/arm/src/sam34/sam4cm_cpustart.c b/arch/arm/src/sam34/sam4cm_cpustart.c index f8544abf7fc..3f6a4c6a194 100644 --- a/arch/arm/src/sam34/sam4cm_cpustart.c +++ b/arch/arm/src/sam34/sam4cm_cpustart.c @@ -80,7 +80,7 @@ ****************************************************************************/ volatile static spinlock_t g_cpu1_boot; -extern int arm_pause_handler(int irq, void *c); +extern int arm_pause_handler(int irq, void *c, FAR void *arg); /**************************************************************************** * Name: cpu1_boot @@ -120,7 +120,7 @@ static void cpu1_boot(void) /* Enable : write-only */ putreg32(0x1, SAM_IPC1_IECR); - irq_attach(SAM_IRQ_IPC1, arm_pause_handler); + irq_attach(SAM_IRQ_IPC1, arm_pause_handler, NULL); up_enable_irq(SAM_IRQ_IPC1); } @@ -229,7 +229,7 @@ int up_cpu_start(int cpu) sam_ipc0_enableclk(); putreg32(0x1, SAM_IPC0_ICCR); /* clear : write-only */ putreg32(0x1, SAM_IPC0_IECR); /* enable : write-only */ - irq_attach(SAM_IRQ_IPC0, arm_pause_handler); + irq_attach(SAM_IRQ_IPC0, arm_pause_handler, NULL); up_enable_irq(SAM_IRQ_IPC0); spin_lock(&g_cpu1_boot); diff --git a/arch/arm/src/sam34/sam4cm_tc.c b/arch/arm/src/sam34/sam4cm_tc.c index d10ac331012..c366118f4d0 100644 --- a/arch/arm/src/sam34/sam4cm_tc.c +++ b/arch/arm/src/sam34/sam4cm_tc.c @@ -147,8 +147,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, /* Interrupt Handling *******************************************************/ -static int sam_tc_interrupt(struct sam_chan_s *tc); -static int sam_raw_interrupt(int irq, void *context); +static int sam_tc_interrupt(int irq, void *context, FAR void *arg); /* Initialization ***********************************************************/ @@ -535,14 +534,17 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset, * ****************************************************************************/ -static int sam_tc_interrupt(struct sam_chan_s *chan) +static int sam_tc_interrupt(int irq, void *context, FAR void *arg) { + struct sam_chan_s *chan = (struct sam_chan_s *)arg; uint32_t sr; uint32_t imr; uint32_t pending; /* Process interrupts */ + DEBUGASSERT(chan != NULL); + /* Get the interrupt status for this channel */ sr = sam_chan_getreg(chan, SAM_TC_SR_OFFSET); @@ -575,41 +577,10 @@ static int sam_tc_interrupt(struct sam_chan_s *chan) return OK; } -/**************************************************************************** - * Name: sam_raw_interrupt - * - * Description: - * Timer block interrupt handlers - * - * Input Parameters: - * irq - * context - * - * Returned Value: - * - ****************************************************************************/ - -static int sam_raw_interrupt(int irq, void *context) -{ - int i; - struct sam_chan_s *chan; - - for (i = 0; i < ENABLED_CHANNELS; i++) - { - chan = &g_channels[i]; - - if (chan->irq == irq) - { - return sam_tc_interrupt(chan); - } - } - - return OK; -} - /**************************************************************************** * Initialization ****************************************************************************/ + /**************************************************************************** * Name: sam_tc_mckdivider * @@ -816,7 +787,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel) /* Attach the timer interrupt handler and enable the timer interrupts */ - (void)irq_attach(chan->irq, sam_raw_interrupt); + (void)irq_attach(chan->irq, sam_tc_interrupt, chan); up_enable_irq(chan->irq); /* Now the channel is initialized */ diff --git a/arch/arm/src/sam34/sam4s_gpio.h b/arch/arm/src/sam34/sam4s_gpio.h index 34ffc0aa314..082fad42a99 100644 --- a/arch/arm/src/sam34/sam4s_gpio.h +++ b/arch/arm/src/sam34/sam4s_gpio.h @@ -83,11 +83,11 @@ #define GPIO_CFG_SHIFT (12) /* Bits 12-16: GPIO configuration bits */ #define GPIO_CFG_MASK (31 << GPIO_CFG_SHIFT) # define GPIO_CFG_DEFAULT (0 << GPIO_CFG_SHIFT) /* Default, no attribute */ -# define GPIO_CFG_PULLUP (1 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-up */ -# define GPIO_CFG_PULLDOWN (2 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-down */ -# define GPIO_CFG_DEGLITCH (4 << GPIO_CFG_SHIFT) /* Bit 12: Internal glitch filter */ -# define GPIO_CFG_OPENDRAIN (8 << GPIO_CFG_SHIFT) /* Bit 13: Open drain */ -# define GPIO_CFG_SCHMITT (16 << GPIO_CFG_SHIFT) /* Bit 13: Schmitt trigger */ +# define GPIO_CFG_PULLUP (1 << GPIO_CFG_SHIFT) /* Bit 12: Internal pull-up */ +# define GPIO_CFG_PULLDOWN (2 << GPIO_CFG_SHIFT) /* Bit 13: Internal pull-down */ +# define GPIO_CFG_DEGLITCH (4 << GPIO_CFG_SHIFT) /* Bit 14: Internal glitch filter */ +# define GPIO_CFG_OPENDRAIN (8 << GPIO_CFG_SHIFT) /* Bit 15: Open drain */ +# define GPIO_CFG_SCHMITT (16 << GPIO_CFG_SHIFT) /* Bit 16: Schmitt trigger */ /* Additional interrupt modes: * @@ -99,7 +99,7 @@ # define _GIO_INT_AIM (1 << 10) /* Bit 10: Additional Interrupt modes */ # define _GPIO_INT_LEVEL (1 << 9) /* Bit 9: Level detection interrupt */ # define _GPIO_INT_EDGE (0) /* (vs. Edge detection interrupt) */ -# define _GPIO_INT_RH (1 << 8) /* Bit 9: Rising edge/High level detection interrupt */ +# define _GPIO_INT_RH (1 << 8) /* Bit 8: Rising edge/High level detection interrupt */ # define _GPIO_INT_FL (0) /* (vs. Falling edge/Low level detection interrupt) */ # define GPIO_INT_HIGHLEVEL (_GIO_INT_AIM | _GPIO_INT_LEVEL | _GPIO_INT_RH) diff --git a/arch/arm/src/sam34/sam_dmac.c b/arch/arm/src/sam34/sam_dmac.c index 7cf1cff3499..6cd36cacf82 100644 --- a/arch/arm/src/sam34/sam_dmac.c +++ b/arch/arm/src/sam34/sam_dmac.c @@ -1276,7 +1276,7 @@ static void sam_dmaterminate(struct sam_dma_s *dmach, int result) * ****************************************************************************/ -static int sam_dmainterrupt(int irq, void *context) +static int sam_dmainterrupt(int irq, void *context, FAR void *arg) { struct sam_dma_s *dmach; unsigned int chndx; @@ -1370,7 +1370,7 @@ void weak_function up_dmainitialize(void) /* Attach DMA interrupt vector */ - (void)irq_attach(SAM_IRQ_DMAC, sam_dmainterrupt); + (void)irq_attach(SAM_IRQ_DMAC, sam_dmainterrupt, NULL); /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ diff --git a/arch/arm/src/sam34/sam_emac.c b/arch/arm/src/sam34/sam_emac.c index 7ce3b0c3165..e00fa8c6d99 100644 --- a/arch/arm/src/sam34/sam_emac.c +++ b/arch/arm/src/sam34/sam_emac.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/sam34/sam_emac.c * - * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2014-2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * This logic derives from the SAM34D3 Ethernet driver. @@ -381,7 +381,7 @@ static void sam_receive(struct sam_emac_s *priv); static void sam_txdone(struct sam_emac_s *priv); static void sam_interrupt_work(FAR void *arg); -static int sam_emac_interrupt(int irq, void *context); +static int sam_emac_interrupt(int irq, void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -1614,7 +1614,7 @@ static void sam_interrupt_work(FAR void *arg) * ****************************************************************************/ -static int sam_emac_interrupt(int irq, void *context) +static int sam_emac_interrupt(int irq, void *context, FAR void *arg) { struct sam_emac_s *priv = &g_emac; @@ -1638,6 +1638,8 @@ static int sam_emac_interrupt(int irq, void *context) tsr = sam_getreg(priv, SAM_EMAC_TSR); if ((tsr & EMAC_TSR_TXCOMP) != 0) { + int delay; + /* If a TX transfer just completed, then cancel the TX timeout so * there will be do race condition between any subsequent timeout * expiration and the deferred interrupt processing. @@ -1645,13 +1647,26 @@ static int sam_emac_interrupt(int irq, void *context) wd_cancel(priv->txtimeout); - /* Make sure that the TX poll timer is running (if it is already - * running, the following would restart it). This is necessary to - * avoid certain race conditions where the polling sequence can be - * interrupted. + /* Check if the poll timer is running. If it is not, then start it + * now. There is a race condition here: We may test the time + * remaining on the poll timer and determine that it is still running, + * but then the timer expires immiately. That should not be problem, + * however, the poll timer processing should be in the work queue and + * should execute immediately after we complete the TX poll. + * Inefficient, but not fatal. */ - (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, priv); + delay = wd_gettime(priv->txpoll); + if (delay <= 0) + { + /* The poll timer is not running .. restart it. This is necessary + * to avoid certain race conditions where the polling sequence can + * be interrupted. + */ + + (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, + 1, priv); + } } /* Cancel any pending poll work */ @@ -3700,7 +3715,7 @@ void up_netinitialize(void) * the interface is in the 'up' state. */ - ret = irq_attach(SAM_IRQ_EMAC, sam_emac_interrupt); + ret = irq_attach(SAM_IRQ_EMAC, sam_emac_interrupt, NULL); if (ret < 0) { nerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_EMAC); diff --git a/arch/arm/src/sam34/sam_gpioirq.c b/arch/arm/src/sam34/sam_gpioirq.c index 4367e814634..e6091ee5110 100644 --- a/arch/arm/src/sam34/sam_gpioirq.c +++ b/arch/arm/src/sam34/sam_gpioirq.c @@ -210,42 +210,42 @@ static int sam_gpiointerrupt(uint32_t base, int irq0, void *context) } #ifdef CONFIG_SAM34_GPIOA_IRQ -static int sam_gpioainterrupt(int irq, void *context) +static int sam_gpioainterrupt(int irq, void *context, FAR void *arg) { return sam_gpiointerrupt(SAM_PIOA_BASE, SAM_IRQ_PA0, context); } #endif #ifdef CONFIG_SAM34_GPIOB_IRQ -static int sam_gpiobinterrupt(int irq, void *context) +static int sam_gpiobinterrupt(int irq, void *context, FAR void *arg) { return sam_gpiointerrupt(SAM_PIOB_BASE, SAM_IRQ_PB0, context); } #endif #ifdef CONFIG_SAM34_GPIOC_IRQ -static int sam_gpiocinterrupt(int irq, void *context) +static int sam_gpiocinterrupt(int irq, void *context, FAR void *arg) { return sam_gpiointerrupt(SAM_PIOC_BASE, SAM_IRQ_PC0, context); } #endif #ifdef CONFIG_SAM34_GPIOD_IRQ -static int sam_gpiodinterrupt(int irq, void *context) +static int sam_gpiodinterrupt(int irq, void *context, FAR void *arg) { return sam_gpiointerrupt(SAM_PIOD_BASE, SAM_IRQ_PD0, context); } #endif #ifdef CONFIG_SAM34_GPIOE_IRQ -static int sam_gpioeinterrupt(int irq, void *context) +static int sam_gpioeinterrupt(int irq, void *context, FAR void *arg) { return sam_gpiointerrupt(SAM_PIOE_BASE, SAM_IRQ_PE0, context); } #endif #ifdef CONFIG_SAM34_GPIOF_IRQ -static int sam_gpiofinterrupt(int irq, void *context) +static int sam_gpiofinterrupt(int irq, void *context, FAR void *arg) { return sam_gpiointerrupt(SAM_PIOF_BASE, SAM_IRQ_PF0, context); } @@ -280,7 +280,7 @@ void sam_gpioirqinitialize(void) /* Attach and enable the GPIOA IRQ */ - (void)irq_attach(SAM_IRQ_PIOA, sam_gpioainterrupt); + (void)irq_attach(SAM_IRQ_PIOA, sam_gpioainterrupt, NULL); up_enable_irq(SAM_IRQ_PIOA); #endif @@ -298,7 +298,7 @@ void sam_gpioirqinitialize(void) /* Attach and enable the GPIOB IRQ */ - (void)irq_attach(SAM_IRQ_PIOB, sam_gpiobinterrupt); + (void)irq_attach(SAM_IRQ_PIOB, sam_gpiobinterrupt, NULL); up_enable_irq(SAM_IRQ_PIOB); #endif @@ -316,7 +316,7 @@ void sam_gpioirqinitialize(void) /* Attach and enable the GPIOC IRQ */ - (void)irq_attach(SAM_IRQ_PIOC, sam_gpiocinterrupt); + (void)irq_attach(SAM_IRQ_PIOC, sam_gpiocinterrupt, NULL); up_enable_irq(SAM_IRQ_PIOC); #endif @@ -334,7 +334,7 @@ void sam_gpioirqinitialize(void) /* Attach and enable the GPIOC IRQ */ - (void)irq_attach(SAM_IRQ_PIOD, sam_gpiodinterrupt); + (void)irq_attach(SAM_IRQ_PIOD, sam_gpiodinterrupt, NULL); up_enable_irq(SAM_IRQ_PIOD); #endif @@ -352,7 +352,7 @@ void sam_gpioirqinitialize(void) /* Attach and enable the GPIOE IRQ */ - (void)irq_attach(SAM_IRQ_PIOE, sam_gpioeinterrupt); + (void)irq_attach(SAM_IRQ_PIOE, sam_gpioeinterrupt, NULL); up_enable_irq(SAM_IRQ_PIOE); #endif @@ -370,7 +370,7 @@ void sam_gpioirqinitialize(void) /* Attach and enable the GPIOF IRQ */ - (void)irq_attach(SAM_IRQ_PIOF, sam_gpiofinterrupt); + (void)irq_attach(SAM_IRQ_PIOF, sam_gpiofinterrupt, NULL); up_enable_irq(SAM_IRQ_PIOF); #endif } diff --git a/arch/arm/src/sam34/sam_hsmci.c b/arch/arm/src/sam34/sam_hsmci.c index 2e831c0cb97..e59d558fe4e 100644 --- a/arch/arm/src/sam34/sam_hsmci.c +++ b/arch/arm/src/sam34/sam_hsmci.c @@ -463,7 +463,7 @@ static void sam_notransfer(struct sam_dev_s *priv); /* Interrupt Handling *******************************************************/ -static int sam_interrupt(int irq, void *context); +static int sam_interrupt(int irq, void *context, FAR void *arg); /* SDIO interface methods ***************************************************/ @@ -1248,7 +1248,7 @@ static void sam_notransfer(struct sam_dev_s *priv) * ****************************************************************************/ -static int sam_interrupt(int irq, void *context) +static int sam_interrupt(int irq, void *context, FAR void *arg) { struct sam_dev_s *priv = &g_sdiodev; uint32_t sr; @@ -1638,7 +1638,7 @@ static int sam_attach(FAR struct sdio_dev_s *dev) /* Attach the HSMCI interrupt handler */ - ret = irq_attach(SAM_IRQ_HSMCI, sam_interrupt); + ret = irq_attach(SAM_IRQ_HSMCI, sam_interrupt, NULL); if (ret == OK) { diff --git a/arch/arm/src/sam34/sam_irq.c b/arch/arm/src/sam34/sam_irq.c index 0b3286d0cac..eb6b1747059 100644 --- a/arch/arm/src/sam34/sam_irq.c +++ b/arch/arm/src/sam34/sam_irq.c @@ -178,7 +178,7 @@ static void sam_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int sam_nmi(int irq, FAR void *context) +static int sam_nmi(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -186,7 +186,7 @@ static int sam_nmi(int irq, FAR void *context) return 0; } -static int sam_busfault(int irq, FAR void *context) +static int sam_busfault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); @@ -194,7 +194,7 @@ static int sam_busfault(int irq, FAR void *context) return 0; } -static int sam_usagefault(int irq, FAR void *context) +static int sam_usagefault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); @@ -202,7 +202,7 @@ static int sam_usagefault(int irq, FAR void *context) return 0; } -static int sam_pendsv(int irq, FAR void *context) +static int sam_pendsv(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -210,7 +210,7 @@ static int sam_pendsv(int irq, FAR void *context) return 0; } -static int sam_dbgmonitor(int irq, FAR void *context) +static int sam_dbgmonitor(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -218,7 +218,7 @@ static int sam_dbgmonitor(int irq, FAR void *context) return 0; } -static int sam_reserved(int irq, FAR void *context) +static int sam_reserved(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -439,8 +439,8 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(SAM_IRQ_SVCALL, up_svcall); - irq_attach(SAM_IRQ_HARDFAULT, up_hardfault); + irq_attach(SAM_IRQ_SVCALL, up_svcall, NULL); + irq_attach(SAM_IRQ_HARDFAULT, up_hardfault, NULL); /* Set the priority of the SVCall interrupt */ @@ -456,22 +456,22 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(SAM_IRQ_MEMFAULT, up_memfault); + irq_attach(SAM_IRQ_MEMFAULT, up_memfault, NULL); up_enable_irq(SAM_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(SAM_IRQ_NMI, sam_nmi); + irq_attach(SAM_IRQ_NMI, sam_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(SAM_IRQ_MEMFAULT, up_memfault); + irq_attach(SAM_IRQ_MEMFAULT, up_memfault, NULL); #endif - irq_attach(SAM_IRQ_BUSFAULT, sam_busfault); - irq_attach(SAM_IRQ_USAGEFAULT, sam_usagefault); - irq_attach(SAM_IRQ_PENDSV, sam_pendsv); - irq_attach(SAM_IRQ_DBGMONITOR, sam_dbgmonitor); - irq_attach(SAM_IRQ_RESERVED, sam_reserved); + irq_attach(SAM_IRQ_BUSFAULT, sam_busfault, NULL); + irq_attach(SAM_IRQ_USAGEFAULT, sam_usagefault, NULL); + irq_attach(SAM_IRQ_PENDSV, sam_pendsv, NULL); + irq_attach(SAM_IRQ_DBGMONITOR, sam_dbgmonitor, NULL); + irq_attach(SAM_IRQ_RESERVED, sam_reserved, NULL); #endif sam_dumpnvic("initial", SAM_IRQ_NIRQS); diff --git a/arch/arm/src/sam34/sam_rtc.c b/arch/arm/src/sam34/sam_rtc.c index c4c548cc9f9..83739923ce8 100644 --- a/arch/arm/src/sam34/sam_rtc.c +++ b/arch/arm/src/sam34/sam_rtc.c @@ -264,7 +264,7 @@ static void rtc_worker(FAR void *arg) ************************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int rtc_interrupt(int irq, void *context) +static int rtc_interrupt(int irq, void *context, FAR void *arg) { int ret; @@ -364,7 +364,7 @@ int up_rtc_initialize(void) #ifdef CONFIG_RTC_ALARM /* Then attach the ALARM interrupt handler */ - irq_attach(SAM_IRQ_RTC, rtc_interrupt); + irq_attach(SAM_IRQ_RTC, rtc_interrupt, NULL); /* Should RTC alarm interrupt be enabled at the peripheral? Let's assume so * for now. Let's say yes if the time is valid and a valid alarm has been diff --git a/arch/arm/src/sam34/sam_rtt.c b/arch/arm/src/sam34/sam_rtt.c index f29e7ac8ee7..7978b01bf38 100644 --- a/arch/arm/src/sam34/sam_rtt.c +++ b/arch/arm/src/sam34/sam_rtt.c @@ -116,7 +116,7 @@ static void sam34_putreg(uint32_t val, uint32_t addr); /* Interrupt handling *******************************************************/ -static int sam34_interrupt(int irq, FAR void *context); +static int sam34_interrupt(int irq, FAR void *context, FAR void *arg); /* "Lower half" driver methods **********************************************/ @@ -275,12 +275,12 @@ static void sam34_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -static int sam34_interrupt(int irq, FAR void *context) +static int sam34_interrupt(int irq, FAR void *context, FAR void *arg) { - FAR struct sam34_lowerhalf_s *priv = &g_tcdev; + FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)arg; tmrinfo("Entry\n"); - DEBUGASSERT(irq == SAM_IRQ_RTT); + DEBUGASSERT(priv != NULL); /* Check if the interrupt is really pending */ @@ -650,7 +650,7 @@ void sam_rttinitialize(FAR const char *devpath) priv->ops = &g_tcops; - (void)irq_attach(SAM_IRQ_RTT, sam34_interrupt); + (void)irq_attach(SAM_IRQ_RTT, sam34_interrupt, priv); /* Enable NVIC interrupt. */ diff --git a/arch/arm/src/sam34/sam_serial.c b/arch/arm/src/sam34/sam_serial.c index 36043e9deb8..60f074dbf53 100644 --- a/arch/arm/src/sam34/sam_serial.c +++ b/arch/arm/src/sam34/sam_serial.c @@ -370,7 +370,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); +static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -872,7 +872,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, up_interrupt); + ret = irq_attach(priv->irq, up_interrupt, dev); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -913,61 +913,16 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt(int irq, void *context) +static int up_interrupt(int irq, void *context, void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct up_dev_s *priv; uint32_t pending; uint32_t imr; int passes; bool handled; -#ifdef CONFIG_SAM34_UART0 - if (g_uart0priv.irq == irq) - { - dev = &g_uart0port; - } - else -#endif -#ifdef CONFIG_SAM34_UART1 - if (g_uart1priv.irq == irq) - { - dev = &g_uart1port; - } - else -#endif -#ifdef CONFIG_SAM34_USART0 - if (g_usart0priv.irq == irq) - { - dev = &g_usart0port; - } - else -#endif -#ifdef CONFIG_SAM34_USART1 - if (g_usart1priv.irq == irq) - { - dev = &g_usart1port; - } - else -#endif -#ifdef CONFIG_SAM34_USART2 - if (g_usart2priv.irq == irq) - { - dev = &g_usart2port; - } - else -#endif -#ifdef CONFIG_SAM34_USART3 - if (g_usart3priv.irq == irq) - { - dev = &g_usart3port; - } - else -#endif - { - PANIC(); - } - + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct up_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, until we have diff --git a/arch/arm/src/sam34/sam_tc.c b/arch/arm/src/sam34/sam_tc.c index 4a1b2abf79d..1faab8b159f 100644 --- a/arch/arm/src/sam34/sam_tc.c +++ b/arch/arm/src/sam34/sam_tc.c @@ -115,7 +115,7 @@ static void sam34_putreg(uint32_t val, uint32_t addr); /* Interrupt handling *******************************************************/ -static int sam34_interrupt(int irq, FAR void *context); +static int sam34_interrupt(int irq, FAR void *context, FAR void *arg); /* "Lower half" driver methods **********************************************/ @@ -255,7 +255,7 @@ static void sam34_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -static int sam34_interrupt(int irq, FAR void *context) +static int sam34_interrupt(int irq, FAR void *context, FAR void *arg) { FAR struct sam34_lowerhalf_s *priv = &g_tcdevs[irq-SAM_IRQ_TC0]; @@ -647,7 +647,7 @@ void sam_tcinitialize(FAR const char *devpath, int irq) priv->ops = &g_tcops; - (void)irq_attach(irq, sam34_interrupt); + (void)irq_attach(irq, sam34_interrupt, NULL); /* Enable NVIC interrupt. */ diff --git a/arch/arm/src/sam34/sam_timerisr.c b/arch/arm/src/sam34/sam_timerisr.c index 00dde9aa7cf..46661de57b5 100644 --- a/arch/arm/src/sam34/sam_timerisr.c +++ b/arch/arm/src/sam34/sam_timerisr.c @@ -112,7 +112,7 @@ * ****************************************************************************/ -static int sam_timerisr(int irq, uint32_t *regs) +static int sam_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -163,7 +163,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(SAM_IRQ_SYSTICK, (xcpt_t)sam_timerisr); + (void)irq_attach(SAM_IRQ_SYSTICK, (xcpt_t)sam_timerisr, NULL); /* Enable SysTick interrupts */ diff --git a/arch/arm/src/sam34/sam_twi.c b/arch/arm/src/sam34/sam_twi.c index 1ed9c03f647..7242f4744d6 100644 --- a/arch/arm/src/sam34/sam_twi.c +++ b/arch/arm/src/sam34/sam_twi.c @@ -162,13 +162,7 @@ static inline void twi_putrel(struct twi_dev_s *priv, unsigned int offset, static int twi_wait(struct twi_dev_s *priv); static void twi_wakeup(struct twi_dev_s *priv, int result); -static int twi_interrupt(struct twi_dev_s *priv); -#ifdef CONFIG_SAM34_TWI0 -static int twi0_interrupt(int irq, FAR void *context); -#endif -#ifdef CONFIG_SAM34_TWI1 -static int twi1_interrupt(int irq, FAR void *context); -#endif +static int twi_interrupt(int irq, FAR void *context, FAR void *arg); static void twi_timeout(int argc, uint32_t arg, ...); static void twi_startread(struct twi_dev_s *priv, struct i2c_msg_s *msg); @@ -436,14 +430,17 @@ static void twi_wakeup(struct twi_dev_s *priv, int result) * ****************************************************************************/ -static int twi_interrupt(struct twi_dev_s *priv) +static int twi_interrupt(int irq, FAR void *context, FAR void *arg); { + struct twi_dev_s *priv = (struct twi_dev_s *)arg; struct i2c_msg_s *msg; uint32_t sr; uint32_t imr; uint32_t pending; uint32_t regval; + DEBUGASSERT(priv != NULL); + /* Retrieve masked interrupt status */ sr = twi_getrel(priv, SAM_TWI_SR_OFFSET); @@ -554,20 +551,6 @@ static int twi_interrupt(struct twi_dev_s *priv) return OK; } -#ifdef CONFIG_SAM34_TWI0 -static int twi0_interrupt(int irq, FAR void *context) -{ - return twi_interrupt(&g_twi0); -} -#endif - -#ifdef CONFIG_SAM34_TWI1 -static int twi1_interrupt(int irq, FAR void *context) -{ - return twi_interrupt(&g_twi1); -} -#endif - /**************************************************************************** * Name: twi_timeout * @@ -910,7 +893,6 @@ static void twi_hw_initialize(struct twi_dev_s *priv, unsigned int pid, struct i2c_master_s *sam_i2cbus_initialize(int bus) { struct twi_dev_s *priv; - xcpt_t handler; irqstate_t flags; uint32_t frequency; unsigned int pid; @@ -938,9 +920,8 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus) sam_configgpio(GPIO_TWI0_CK); sam_configgpio(GPIO_TWI0_D); - /* Select the interrupt handler, TWI frequency, and peripheral ID */ + /* Select the TWI frequency, and peripheral ID */ - handler = twi0_interrupt; frequency = CONFIG_SAM34_TWI0_FREQUENCY; pid = SAM_PID_TWI0; } @@ -965,9 +946,8 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus) sam_configgpio(GPIO_TWI1_CK); sam_configgpio(GPIO_TWI1_D); - /* Select the interrupt handler, TWI frequency, and peripheral ID */ + /* Select the TWI frequency, and peripheral ID */ - handler = twi1_interrupt; frequency = CONFIG_SAMA5_TWI1_FREQUENCY; pid = SAM_PID_TWI1; } @@ -1006,7 +986,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus) /* Attach Interrupt Handler */ - irq_attach(priv->irq, handler); + irq_attach(priv->irq, twi_interrupt, priv); /* Enable Interrupts */ diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c index 9e644c7631e..839a7bfdbad 100644 --- a/arch/arm/src/sam34/sam_udp.c +++ b/arch/arm/src/sam34/sam_udp.c @@ -395,7 +395,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv); static void sam_ep_bankinterrupt(struct sam_usbdev_s *priv, struct sam_ep_s *privep, uint32_t csr, int bank); static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno); -static int sam_udp_interrupt(int irq, void *context); +static int sam_udp_interrupt(int irq, void *context, FAR void *arg); /* Endpoint helpers *********************************************************/ @@ -2218,7 +2218,7 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno) * ****************************************************************************/ -static int sam_udp_interrupt(int irq, void *context) +static int sam_udp_interrupt(int irq, void *context, FAR void *arg) { /* For now there is only one USB controller, but we will always refer to * it using a pointer to make any future ports to multiple UDP controllers @@ -3915,7 +3915,7 @@ void up_usbinitialize(void) * them when we need them later. */ - if (irq_attach(SAM_IRQ_UDP, sam_udp_interrupt) != 0) + if (irq_attach(SAM_IRQ_UDP, sam_udp_interrupt, NULL) != 0) { usbtrace(TRACE_DEVERROR(SAM_TRACEERR_IRQREGISTRATION), (uint16_t)SAM_IRQ_UDP); diff --git a/arch/arm/src/sam34/sam_wdt.c b/arch/arm/src/sam34/sam_wdt.c index a75f63097bd..cf88b37fec1 100644 --- a/arch/arm/src/sam34/sam_wdt.c +++ b/arch/arm/src/sam34/sam_wdt.c @@ -118,7 +118,7 @@ static void sam34_putreg(uint32_t val, uint32_t addr); /* Interrupt handling *******************************************************/ -static int sam34_interrupt(int irq, FAR void *context); +static int sam34_interrupt(int irq, FAR void *context, FAR void *arg); /* "Lower half" driver methods **********************************************/ @@ -256,7 +256,7 @@ static void sam34_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -static int sam34_interrupt(int irq, FAR void *context) +static int sam34_interrupt(int irq, FAR void *context, FAR void *arg) { FAR struct sam34_lowerhalf_s *priv = &g_wdgdev; uint16_t regval; @@ -275,7 +275,7 @@ static int sam34_interrupt(int irq, FAR void *context) * upon return. */ - priv->handler(irq, context); + priv->handler(irq, context, NULL); } /* The EWI interrupt is cleared by the WDT_SR register. */ @@ -681,7 +681,7 @@ void sam_wdtinitialize(FAR const char *devpath) /* Attach our EWI interrupt handler (But don't enable it yet) */ - (void)irq_attach(SAM_IRQ_WDT, sam34_interrupt); + (void)irq_attach(SAM_IRQ_WDT, sam34_interrupt, NULL); /* Select an arbitrary initial timeout value. But don't start the watchdog * yet. NOTE: If the "Hardware watchdog" feature is enabled through the diff --git a/arch/arm/src/sama5/sam_adc.c b/arch/arm/src/sama5/sam_adc.c index dcf82b1f6d9..2f9e4ee406e 100644 --- a/arch/arm/src/sama5/sam_adc.c +++ b/arch/arm/src/sama5/sam_adc.c @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/sama5/sam_adc.c * - * Copyright (C) 2013, 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2014, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -65,6 +65,7 @@ #include #include #include +#include #include "up_internal.h" #include "up_arch.h" @@ -447,7 +448,7 @@ static void sam_adc_dmastart(struct sam_adc_s *priv); static void sam_adc_endconversion(void *arg); #endif -static int sam_adc_interrupt(int irq, void *context); +static int sam_adc_interrupt(int irq, void *context, FAR void *arg); /* ADC methods */ @@ -906,7 +907,7 @@ static void sam_adc_endconversion(void *arg) * ****************************************************************************/ -static int sam_adc_interrupt(int irq, void *context) +static int sam_adc_interrupt(int irq, void *context, FAR void *arg) { struct sam_adc_s *priv = &g_adcpriv; uint32_t isr; @@ -2109,7 +2110,7 @@ struct adc_dev_s *sam_adc_initialize(void) /* Attach the ADC interrupt */ - ret = irq_attach(SAM_IRQ_ADC, sam_adc_interrupt); + ret = irq_attach(SAM_IRQ_ADC, sam_adc_interrupt, NULL); if (ret < 0) { aerr("ERROR: Failed to attach IRQ %d: %d\n", SAM_IRQ_ADC, ret); diff --git a/arch/arm/src/sama5/sam_can.c b/arch/arm/src/sama5/sam_can.c index f801e6e8341..4020055e89a 100644 --- a/arch/arm/src/sama5/sam_can.c +++ b/arch/arm/src/sama5/sam_can.c @@ -150,7 +150,6 @@ struct sam_config_s uint8_t port; /* CAN port number (1 or 2) */ uint8_t pid; /* CAN periperal ID/IRQ number */ uint8_t nrecvmb; /* Number of receive mailboxes */ - xcpt_t handler; /* CAN interrupt handler */ uintptr_t base; /* Base address of the CAN control registers */ uint32_t baud; /* Configured baud */ pio_pinset_t rxpinset; /* RX pin configuration */ @@ -225,13 +224,7 @@ static inline void can_rxinterrupt(FAR struct can_dev_s *dev, int mbndx, uint32_t msr); static inline void can_txinterrupt(FAR struct can_dev_s *dev, int mbndx); static inline void can_mbinterrupt(FAR struct can_dev_s *dev, int mbndx); -static void can_interrupt(FAR struct can_dev_s *dev); -#ifdef CONFIG_SAMA5_CAN0 -static int can0_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_SAMA5_CAN1 -static int can1_interrupt(int irq, void *context); -#endif +static void can_interrupt(int irq, void *context, FAR void *arg); /* Hardware initialization */ @@ -265,7 +258,6 @@ static const struct sam_config_s g_can0const = .port = 0, .pid = SAM_PID_CAN0, .nrecvmb = CONFIG_SAMA5_CAN0_NRECVMB, - .handler = can0_interrupt, .base = SAM_CAN0_VBASE, .baud = CONFIG_SAMA5_CAN0_BAUD, .rxpinset = PIO_CAN0_RX, @@ -301,7 +293,6 @@ static const struct sam_config_s g_can1const = .port = 1, .pid = SAM_PID_CAN1, .nrecvmb = CONFIG_SAMA5_CAN1_NRECVMB, - .handler = can1_interrupt, .base = SAM_CAN1_VBASE, .baud = CONFIG_SAMA5_CAN1_BAUD, .rxpinset = PIO_CAN1_RX, @@ -860,7 +851,7 @@ static int can_setup(FAR struct can_dev_s *dev) /* Attach the CAN interrupt handler */ - ret = irq_attach(config->pid, config->handler); + ret = irq_attach(config->pid, can_interrupt, dev); if (ret < 0) { canerr("ERROR: Failed to attach CAN%d IRQ (%d)", config->port, config->pid); @@ -1437,21 +1428,24 @@ static inline void can_mbinterrupt(FAR struct can_dev_s *dev, int mbndx) * Common CAN interrupt handler * * Input Parameters: - * priv - CAN-specific private data + * Standard interrupt handler inputs * * Returned Value: * None * ****************************************************************************/ -static void can_interrupt(FAR struct can_dev_s *dev) +static void can_interrupt(int irq, void *context, FAR void *arg) { - FAR struct sam_can_s *priv = dev->cd_priv; + FAR struct can_dev_s *dev = (FAR struct can_dev_s *)arg; + FAR struct sam_can_s *priv; uint32_t sr; uint32_t imr; uint32_t pending; - DEBUGASSERT(priv && priv->config); + DEBUGASSERT(dev != NULL); + FAR struct sam_can_s *priv = dev->cd_priv; + DEBUGASSERT(priv != NULL && priv->config != NULL); /* Get the set of pending interrupts. * @@ -1520,52 +1514,6 @@ static void can_interrupt(FAR struct can_dev_s *dev) } } -/**************************************************************************** - * Name: can0_interrupt - * - * Description: - * CAN0 interrupt handler - * - * Input Parameters: - * irq - The IRQ number of the interrupt. - * context - The register state save array at the time of the interrupt. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_SAMA5_CAN0 -static int can0_interrupt(int irq, void *context) -{ - can_interrupt(&g_can0dev); - return OK; -} -#endif - -/**************************************************************************** - * Name: can0_interrupt - * - * Description: - * CAN0 interrupt handler - * - * Input Parameters: - * irq - The IRQ number of the interrupt. - * context - The register state save array at the time of the interrupt. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_SAMA5_CAN1 -static int can1_interrupt(int irq, void *context) -{ - can_interrupt(&g_can1dev); - return OK; -} -#endif - /**************************************************************************** * Name: can_bittiming * diff --git a/arch/arm/src/sama5/sam_dbgu.c b/arch/arm/src/sama5/sam_dbgu.c index 877e1db82dc..65242b88188 100644 --- a/arch/arm/src/sama5/sam_dbgu.c +++ b/arch/arm/src/sama5/sam_dbgu.c @@ -91,7 +91,7 @@ static int dbgu_setup(struct uart_dev_s *dev); static void dbgu_shutdown(struct uart_dev_s *dev); static int dbgu_attach(struct uart_dev_s *dev); static void dbgu_detach(struct uart_dev_s *dev); -static int dbgu_interrupt(int irq, void *context); +static int dbgu_interrupt(int irq, void *context, FAR void *arg); static int dbgu_ioctl(struct file *filep, int cmd, unsigned long arg); static int dbgu_receive(struct uart_dev_s *dev, uint32_t *status); static void dbgu_rxint(struct uart_dev_s *dev, bool enable); @@ -287,7 +287,7 @@ static int dbgu_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(SAM_IRQ_DBGU, dbgu_interrupt); + ret = irq_attach(SAM_IRQ_DBGU, dbgu_interrupt, NULL); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -328,7 +328,7 @@ static void dbgu_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int dbgu_interrupt(int irq, void *context) +static int dbgu_interrupt(int irq, void *context, FAR void *arg) { struct uart_dev_s *dev = &g_dbgu_port; struct dbgu_dev_s *priv = (struct dbgu_dev_s *)dev->priv; diff --git a/arch/arm/src/sama5/sam_dmac.c b/arch/arm/src/sama5/sam_dmac.c index e3a813c1b21..a1002395db9 100644 --- a/arch/arm/src/sama5/sam_dmac.c +++ b/arch/arm/src/sama5/sam_dmac.c @@ -1785,12 +1785,15 @@ static void sam_dmaterminate(struct sam_dmach_s *dmach, int result) * ****************************************************************************/ -static int sam_dmac_interrupt(struct sam_dmac_s *dmac) +static int sam_dmac_interrupt(int irq, void *context, FAR void *arg) { + struct sam_dmac_s *dmac = (struct sam_dmac_s *)arg; struct sam_dmach_s *dmach; unsigned int chndx; uint32_t regval; + DEBUGASSERT(dmac != NULL); + /* Get the DMAC status register value. Ignore all masked interrupt * status bits. */ @@ -1849,28 +1852,6 @@ static int sam_dmac_interrupt(struct sam_dmac_s *dmac) return OK; } -/**************************************************************************** - * Name: sam_dmac0_interrupt and sam_dmac1_interrupt - * - * Description: - * DMA interrupt handler - * - ****************************************************************************/ - -#ifdef CONFIG_SAMA5_DMAC0 -static int sam_dmac0_interrupt(int irq, void *context) -{ - return sam_dmac_interrupt(&g_dmac0); -} -#endif - -#ifdef CONFIG_SAMA5_DMAC1 -static int sam_dmac1_interrupt(int irq, void *context) -{ - return sam_dmac_interrupt(&g_dmac1); -} -#endif - /**************************************************************************** * Name: sam_dmainitialize * @@ -1928,7 +1909,7 @@ void weak_function up_dmainitialize(void) /* Attach DMA interrupt vector */ - (void)irq_attach(SAM_IRQ_DMAC0, sam_dmac0_interrupt); + (void)irq_attach(SAM_IRQ_DMAC0, sam_dmac_interrupt, &g_dmac0); /* Initialize the controller */ @@ -1948,7 +1929,7 @@ void weak_function up_dmainitialize(void) /* Attach DMA interrupt vector */ - (void)irq_attach(SAM_IRQ_DMAC1, sam_dmac1_interrupt); + (void)irq_attach(SAM_IRQ_DMAC1, sam_dmac_interrupt, &g_dmac1); /* Initialize the controller */ diff --git a/arch/arm/src/sama5/sam_ehci.c b/arch/arm/src/sama5/sam_ehci.c index 6065a04d50d..d84f1c2dbc4 100644 --- a/arch/arm/src/sama5/sam_ehci.c +++ b/arch/arm/src/sama5/sam_ehci.c @@ -388,7 +388,7 @@ static inline void sam_portsc_bottomhalf(void); static inline void sam_syserr_bottomhalf(void); static inline void sam_async_advance_bottomhalf(void); static void sam_ehci_bottomhalf(FAR void *arg); -static int sam_ehci_tophalf(int irq, FAR void *context); +static int sam_ehci_tophalf(int irq, FAR void *context, FAR void *arg); /* USB Host Controller Operations **********************************************/ @@ -3167,7 +3167,7 @@ static void sam_ehci_bottomhalf(FAR void *arg) * ****************************************************************************/ -static int sam_ehci_tophalf(int irq, FAR void *context) +static int sam_ehci_tophalf(int irq, FAR void *context, FAR void *arg) { uint32_t usbsts; uint32_t pending; @@ -3228,15 +3228,15 @@ static int sam_ehci_tophalf(int irq, FAR void *context) ****************************************************************************/ #ifdef CONFIG_SAMA5_OHCI -static int sam_uhphs_interrupt(int irq, FAR void *context) +static int sam_uhphs_interrupt(int irq, FAR void *context, FAR void *arg) { int ohci; int ehci; /* Provide the interrupting event to both the EHCI and OHCI top half */ - ohci = sam_ohci_tophalf(irq, context); - ehci = sam_ehci_tophalf(irq, context); + ohci = sam_ohci_tophalf(irq, context, arg); + ehci = sam_ehci_tophalf(irq, context, arg); /* Return OK only if both handlers returned OK */ @@ -5098,9 +5098,9 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller) */ #ifdef CONFIG_SAMA5_OHCI - ret = irq_attach(SAM_IRQ_UHPHS, sam_uhphs_interrupt); + ret = irq_attach(SAM_IRQ_UHPHS, sam_uhphs_interrupt, NULL); #else - ret = irq_attach(SAM_IRQ_UHPHS, sam_ehci_tophalf); + ret = irq_attach(SAM_IRQ_UHPHS, sam_ehci_tophalf, NULL); #endif if (ret != 0) { diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c index 29bd28c5a75..bad06160cdf 100644 --- a/arch/arm/src/sama5/sam_emaca.c +++ b/arch/arm/src/sama5/sam_emaca.c @@ -4,7 +4,7 @@ * 10/100 Base-T Ethernet driver for the SAMA5D3. Denoted as 'A' to * distinguish it from the SAMA5D4 EMAC driver. * - * Copyright (C) 2013-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -386,7 +386,7 @@ static void sam_receive(struct sam_emac_s *priv); static void sam_txdone(struct sam_emac_s *priv); static void sam_interrupt_work(FAR void *arg); -static int sam_emac_interrupt(int irq, void *context); +static int sam_emac_interrupt(int irq, void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -1653,7 +1653,7 @@ static void sam_interrupt_work(FAR void *arg) * ****************************************************************************/ -static int sam_emac_interrupt(int irq, void *context) +static int sam_emac_interrupt(int irq, void *context, FAR void *arg) { struct sam_emac_s *priv = &g_emac; uint32_t tsr; @@ -1676,6 +1676,8 @@ static int sam_emac_interrupt(int irq, void *context) tsr = sam_getreg(priv, SAM_EMAC_TSR_OFFSET); if ((tsr & EMAC_TSR_COMP) != 0) { + int delay; + /* If a TX transfer just completed, then cancel the TX timeout so * there will be do race condition between any subsequent timeout * expiration and the deferred interrupt processing. @@ -1683,13 +1685,26 @@ static int sam_emac_interrupt(int irq, void *context) wd_cancel(priv->txtimeout); - /* Make sure that the TX poll timer is running (if it is already - * running, the following would restart it). This is necessary to - * avoid certain race conditions where the polling sequence can be - * interrupted. + /* Check if the poll timer is running. If it is not, then start it + * now. There is a race condition here: We may test the time + * remaining on the poll timer and determine that it is still running, + * but then the timer expires immiately. That should not be problem, + * however, the poll timer processing should be in the work queue and + * should execute immediately after we complete the TX poll. + * Inefficient, but not fatal. */ - (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, priv); + delay = wd_gettime(priv->txpoll); + if (delay <= 0) + { + /* The poll timer is not running .. restart it. This is necessary + * to avoid certain race conditions where the polling sequence can + * be interrupted. + */ + + (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, + 1, priv); + } } /* Cancel any pending poll work */ @@ -3744,7 +3759,7 @@ int sam_emac_initialize(void) * the interface is in the 'up' state. */ - ret = irq_attach(SAM_IRQ_EMAC, sam_emac_interrupt); + ret = irq_attach(SAM_IRQ_EMAC, sam_emac_interrupt, NULL); if (ret < 0) { nerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_EMAC); diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c index 44b477cb7ba..c1fd14a5c0a 100644 --- a/arch/arm/src/sama5/sam_emacb.c +++ b/arch/arm/src/sama5/sam_emacb.c @@ -8,7 +8,7 @@ * separate (mostly because the 'B' driver needs to support two EMAC blocks. * But the 'B' driver should replace the 'A' driver someday. * - * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2014-2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * This logic derives from the SAM4E Ethernet driver which, in turn, derived @@ -349,7 +349,6 @@ struct sam_emacattr_s /* Basic hardware information */ uint32_t base; /* EMAC Register base address */ - xcpt_t handler; /* EMAC interrupt handler */ uint8_t emac; /* EMACn, n=0 or 1 */ uint8_t irq; /* EMAC interrupt number */ @@ -481,13 +480,7 @@ static void sam_receive(struct sam_emac_s *priv); static void sam_txdone(struct sam_emac_s *priv); static void sam_interrupt_work(FAR void *arg); -static int sam_emac_interrupt(struct sam_emac_s *priv); -#ifdef CONFIG_SAMA5_EMAC0 -static int sam_emac0_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_SAMA5_EMAC1 -static int sam_emac1_interrupt(int irq, void *context); -#endif +static int sam_emac_interrupt(int irq, void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -633,7 +626,6 @@ static const struct sam_emacattr_s g_emac0_attr = /* Basic hardware information */ .base = SAM_EMAC0_VBASE, - .handler = sam_emac0_interrupt, .emac = EMAC0_INTF, .irq = SAM_IRQ_EMAC0, @@ -714,7 +706,6 @@ static const struct sam_emacattr_s g_emac1_attr = /* Basic hardware information */ .base = SAM_EMAC1_VBASE, - .handler = sam_emac1_interrupt, .emac = EMAC1_INTF, .irq = SAM_IRQ_EMAC1, @@ -2012,7 +2003,7 @@ static void sam_interrupt_work(FAR void *arg) * Common hardware interrupt handler * * Parameters: - * priv - Reference to the EMAC private state structure + * Standard interrupt handler inputs * * Returned Value: * OK on success @@ -2021,10 +2012,13 @@ static void sam_interrupt_work(FAR void *arg) * ****************************************************************************/ -static int sam_emac_interrupt(struct sam_emac_s *priv) +static int sam_emac_interrupt(int irq, void *context, FAR void *arg) { + struct sam_emac_s *priv = (struct sam_emac_s *)arg; uint32_t tsr; + DEBUGASSERT(priv != NULL); + /* Disable further Ethernet interrupts. Because Ethernet interrupts are * also disabled if the TX timeout event occurs, there can be no race * condition here. @@ -2043,6 +2037,8 @@ static int sam_emac_interrupt(struct sam_emac_s *priv) tsr = sam_getreg(priv, SAM_EMAC_TSR_OFFSET); if ((tsr & EMAC_TSR_TXCOMP) != 0) { + int delay; + /* If a TX transfer just completed, then cancel the TX timeout so * there will be do race condition between any subsequent timeout * expiration and the deferred interrupt processing. @@ -2050,13 +2046,26 @@ static int sam_emac_interrupt(struct sam_emac_s *priv) wd_cancel(priv->txtimeout); - /* Make sure that the TX poll timer is running (if it is already - * running, the following would restart it). This is necessary to - * avoid certain race conditions where the polling sequence can be - * interrupted. + /* Check if the poll timer is running. If it is not, then start it + * now. There is a race condition here: We may test the time + * remaining on the poll timer and determine that it is still running, + * but then the timer expires immiately. That should not be problem, + * however, the poll timer processing should be in the work queue and + * should execute immediately after we complete the TX poll. + * Inefficient, but not fatal. */ - (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, priv); + delay = wd_gettime(priv->txpoll); + if (delay <= 0) + { + /* The poll timer is not running .. restart it. This is necessary + * to avoid certain race conditions where the polling sequence can + * be interrupted. + */ + + (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, + 1, priv); + } } /* Cancel any pending poll work */ @@ -2069,37 +2078,6 @@ static int sam_emac_interrupt(struct sam_emac_s *priv) return OK; } -/**************************************************************************** - * Function: sam_emac0/1_interrupt - * - * Description: - * EMAC hardware interrupt handler - * - * Parameters: - * irq - Number of the IRQ that generated the interrupt - * context - Interrupt register state save info (architecture-specific) - * - * Returned Value: - * OK on success - * - * Assumptions: - * - ****************************************************************************/ - -#ifdef CONFIG_SAMA5_EMAC0 -static int sam_emac0_interrupt(int irq, void *context) -{ - return sam_emac_interrupt(&g_emac0); -} -#endif - -#ifdef CONFIG_SAMA5_EMAC1 -static int sam_emac1_interrupt(int irq, void *context) -{ - return sam_emac_interrupt(&g_emac1); -} -#endif - /**************************************************************************** * Function: sam_txtimeout_work * @@ -4470,7 +4448,7 @@ int sam_emac_initialize(int intf) * the interface is in the 'up' state. */ - ret = irq_attach(priv->attr->irq, priv->attr->handler); + ret = irq_attach(priv->attr->irq, sam_emac_interrupt, priv); if (ret < 0) { nerr("ERROR: Failed to attach the handler to the IRQ%d\n", priv->attr->irq); diff --git a/arch/arm/src/sama5/sam_flexcom_serial.c b/arch/arm/src/sama5/sam_flexcom_serial.c index c0d4693ac86..b476b931143 100644 --- a/arch/arm/src/sama5/sam_flexcom_serial.c +++ b/arch/arm/src/sama5/sam_flexcom_serial.c @@ -216,7 +216,6 @@ struct flexus_dev_s { - xcpt_t handler; /* Interrupt handler */ uint32_t usartbase; /* Base address of USART registers */ uint32_t baud; /* Configured baud */ uint32_t sr; /* Saved status bits */ @@ -233,23 +232,7 @@ struct flexus_dev_s * Private Function Prototypes ****************************************************************************/ -static int flexus_interrupt(struct uart_dev_s *dev); -#ifdef CONFIG_USART0_SERIALDRIVER -static int flexus0_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_USART1_SERIALDRIVER -static int flexus1_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_USART2_SERIALDRIVER -static int flexus2_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_USART3_SERIALDRIVER -static int flexus3_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_USART4_SERIALDRIVER -static int flexus4_interrupt(int irq, void *context); -#endif - +static int flexus_interrupt(int irq, void *context, FAR void *arg); static int flexus_setup(struct uart_dev_s *dev); static void flexus_shutdown(struct uart_dev_s *dev); static int flexus_attach(struct uart_dev_s *dev); @@ -314,7 +297,6 @@ static char g_flexus4txbuffer[CONFIG_USART4_TXBUFSIZE]; #ifdef CONFIG_USART0_SERIALDRIVER static struct flexus_dev_s g_flexus0priv = { - .handler = flexus0_interrupt, .usartbase = SAM_FLEXCOM0_VBASE, .baud = CONFIG_USART0_BAUD, .irq = SAM_IRQ_FLEXCOM0, @@ -348,7 +330,6 @@ static uart_dev_t g_flexus0port = #ifdef CONFIG_USART1_SERIALDRIVER static struct flexus_dev_s g_flexus1priv = { - .handler = flexus1_interrupt, .usartbase = SAM_FLEXCOM1_VBASE, .baud = CONFIG_USART1_BAUD, .irq = SAM_IRQ_FLEXCOM1, @@ -382,7 +363,6 @@ static uart_dev_t g_flexus1port = #ifdef CONFIG_USART2_SERIALDRIVER static struct flexus_dev_s g_flexus2priv = { - .handler = flexus2_interrupt, .usartbase = SAM_FLEXCOM2_VBASE, .baud = CONFIG_USART2_BAUD, .irq = SAM_IRQ_FLEXCOM2, @@ -416,7 +396,6 @@ static uart_dev_t g_flexus2port = #ifdef CONFIG_USART3_SERIALDRIVER static struct flexus_dev_s g_flexus3priv = { - .handler = flexus3_interrupt, .usartbase = SAM_FLEXCOM3_VBASE, .baud = CONFIG_USART3_BAUD, .irq = SAM_IRQ_FLEXCOM3, @@ -450,7 +429,6 @@ static uart_dev_t g_flexus3port = #ifdef CONFIG_USART4_SERIALDRIVER static struct flexus_dev_s g_flexus4priv = { - .handler = flexus4_interrupt, .usartbase = SAM_FLEXCOM4_VBASE, .baud = CONFIG_USART4_BAUD, .irq = SAM_IRQ_FLEXCOM4, @@ -549,13 +527,14 @@ static void flexus_disableallints(struct flexus_dev_s *priv, uint32_t *imr) * ****************************************************************************/ -static int flexus_interrupt(struct uart_dev_s *dev) +static int flexus_interrupt(int irq, void *context, FAR void *arg) { - struct flexus_dev_s *priv; - uint32_t pending; - uint32_t imr; - int passes; - bool handled; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct flexus_dev_s *priv; + uint32_t pending; + uint32_t imr; + int passes; + bool handled; DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct flexus_dev_s *)dev->priv; @@ -603,47 +582,6 @@ static int flexus_interrupt(struct uart_dev_s *dev) return OK; } -/**************************************************************************** - * Name: flexus*_interrupt - * - * Description: - * This is the specific UART/USART interrupt handler. These simply map - * the interrupt to the device-specific data and passes control to the - * common interrupt handler. - * - ****************************************************************************/ - -#ifdef CONFIG_USART0_SERIALDRIVER -static int flexus0_interrupt(int irq, void *context) -{ - return flexus_interrupt(&g_flexus0port); -} -#endif -#ifdef CONFIG_USART1_SERIALDRIVER -static int flexus1_interrupt(int irq, void *context) -{ - return flexus_interrupt(&g_flexus1port); -} -#endif -#ifdef CONFIG_USART2_SERIALDRIVER -static int flexus2_interrupt(int irq, void *context) -{ - return flexus_interrupt(&g_flexus2port); -} -#endif -#ifdef CONFIG_USART3_SERIALDRIVER -static int flexus3_interrupt(int irq, void *context) -{ - return flexus_interrupt(&g_flexus3port); -} -#endif -#ifdef CONFIG_USART4_SERIALDRIVER -static int flexus4_interrupt(int irq, void *context) -{ - return flexus_interrupt(&g_flexus4port); -} -#endif - /**************************************************************************** * Name: flexus_setup * @@ -803,7 +741,7 @@ static int flexus_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, priv->handler); + ret = irq_attach(priv->irq, flexus_interrupt, dev); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c index da6b320d523..2d21e5c023b 100644 --- a/arch/arm/src/sama5/sam_gmac.c +++ b/arch/arm/src/sama5/sam_gmac.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/sama5/sam_gmac.c * - * Copyright (C) 2013-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -311,7 +311,7 @@ static void sam_receive(struct sam_gmac_s *priv); static void sam_txdone(struct sam_gmac_s *priv); static void sam_interrupt_work(FAR void *arg); -static int sam_gmac_interrupt(int irq, void *context); +static int sam_gmac_interrupt(int irq, void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -1605,7 +1605,7 @@ static void sam_interrupt_work(FAR void *arg) * ****************************************************************************/ -static int sam_gmac_interrupt(int irq, void *context) +static int sam_gmac_interrupt(int irq, void *context, FAR void *arg) { struct sam_gmac_s *priv = &g_gmac; uint32_t tsr; @@ -1628,6 +1628,8 @@ static int sam_gmac_interrupt(int irq, void *context) tsr = sam_getreg(priv, SAM_GMAC_TSR_OFFSET); if ((tsr & GMAC_TSR_TXCOMP) != 0) { + int delay; + /* If a TX transfer just completed, then cancel the TX timeout so * there will be do race condition between any subsequent timeout * expiration and the deferred interrupt processing. @@ -1635,13 +1637,25 @@ static int sam_gmac_interrupt(int irq, void *context) wd_cancel(priv->txtimeout); - /* Make sure that the TX poll timer is running (if it is already - * running, the following would restart it). This is necessary to - * avoid certain race conditions where the polling sequence can be - * interrupted. + /* Check if the poll timer is running. If it is not, then start it + * now. There is a race condition here: We may test the time + * remaining on the poll timer and determine that it is still running, + * but then the timer expires immiately. That should not be problem, + * however, the poll timer processing should be in the work queue and + * should execute immediately after we complete the TX poll. + * Inefficient, but not fatal. */ - (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, priv); + delay = wd_gettime(priv->txpoll); + if (delay <= 0) + { + /* The poll timer is not running .. restart it. This is necessary + * to avoid certain race conditions where the polling sequence can + * be interrupted. + */ + + (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, priv); + } } /* Cancel any pending poll work */ @@ -3816,7 +3830,7 @@ int sam_gmac_initialize(void) * the interface is in the 'up' state. */ - ret = irq_attach(SAM_IRQ_GMAC, sam_gmac_interrupt); + ret = irq_attach(SAM_IRQ_GMAC, sam_gmac_interrupt, NULL); if (ret < 0) { nerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_GMAC); diff --git a/arch/arm/src/sama5/sam_hsmci.c b/arch/arm/src/sama5/sam_hsmci.c index a76e471319e..3aa006d8722 100644 --- a/arch/arm/src/sama5/sam_hsmci.c +++ b/arch/arm/src/sama5/sam_hsmci.c @@ -436,17 +436,17 @@ struct sam_dev_s /* Debug stuff */ #ifdef CONFIG_SAMA5_HSMCI_REGDEBUG - bool wrlast; /* Last was a write */ - uint32_t addrlast; /* Last address */ - uint32_t vallast; /* Last value */ - int ntimes; /* Number of times */ + bool wrlast; /* Last was a write */ + uint32_t addrlast; /* Last address */ + uint32_t vallast; /* Last value */ + int ntimes; /* Number of times */ #endif /* Register logging support */ #if defined(CONFIG_SAMA5_HSMCI_CMDDEBUG) && defined(CONFIG_SAMA5_HSMCI_XFRDEBUG) - bool xfrinitialized; - bool cmdinitialized; + bool xfrinitialized; + bool cmdinitialized; #endif #ifdef CONFIG_SAMA5_HSMCI_XFRDEBUG uint8_t smplset; @@ -537,16 +537,7 @@ static void sam_notransfer(struct sam_dev_s *priv); /* Interrupt Handling *******************************************************/ -static int sam_hsmci_interrupt(struct sam_dev_s *priv); -#ifdef CONFIG_SAMA5_HSMCI0 -static int sam_hsmci0_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_SAMA5_HSMCI1 -static int sam_hsmci1_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_SAMA5_HSMCI2 -static int sam_hsmci2_interrupt(int irq, void *context); -#endif +static int sam_hsmci_interrupt(int irq, void *context, void *arg); /* SDIO interface methods ***************************************************/ @@ -1512,12 +1503,15 @@ static void sam_notransfer(struct sam_dev_s *priv) * ****************************************************************************/ -static int sam_hsmci_interrupt(struct sam_dev_s *priv) +static int sam_hsmci_interrupt(int irq, void *context, void *arg) { + struct sam_dev_s *priv = (struct sam_dev_s *)arg; uint32_t sr; uint32_t enabled; uint32_t pending; + DEBUGASSERT(priv != NULL); + /* Loop while there are pending interrupts. */ for (; ; ) @@ -1661,42 +1655,6 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv) return OK; } -/**************************************************************************** - * Name: sam_hsmci0_interrupt, sam_hsmci1_interrupt, and sam_hsmci2_interrupt - * - * Description: - * HSMCI interrupt handler - * - * Input Parameters: - * irq - IRQ number of the interrupts - * context - Saved machine context at the time of the interrupt - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SAMA5_HSMCI0 -static int sam_hsmci0_interrupt(int irq, void *context) -{ - return sam_hsmci_interrupt(&g_hsmci0); -} -#endif - -#ifdef CONFIG_SAMA5_HSMCI1 -static int sam_hsmci1_interrupt(int irq, void *context) -{ - return sam_hsmci_interrupt(&g_hsmci1); -} -#endif - -#ifdef CONFIG_SAMA5_HSMCI2 -static int sam_hsmci2_interrupt(int irq, void *context) -{ - return sam_hsmci_interrupt(&g_hsmci2); -} -#endif - /**************************************************************************** * SDIO Interface Methods ****************************************************************************/ @@ -1947,7 +1905,6 @@ static void sam_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) static int sam_attach(FAR struct sdio_dev_s *dev) { struct sam_dev_s *priv = (struct sam_dev_s *)dev; - xcpt_t handler; int irq; int ret; @@ -1956,24 +1913,21 @@ static int sam_attach(FAR struct sdio_dev_s *dev) #ifdef CONFIG_SAMA5_HSMCI0 if (priv->hsmci == 0) { - handler = sam_hsmci0_interrupt; - irq = SAM_IRQ_HSMCI0; + irq = SAM_IRQ_HSMCI0; } else #endif #ifdef CONFIG_SAMA5_HSMCI1 if (priv->hsmci == 1) { - handler = sam_hsmci1_interrupt; - irq = SAM_IRQ_HSMCI1; + irq = SAM_IRQ_HSMCI1; } else #endif #ifdef CONFIG_SAMA5_HSMCI2 if (priv->hsmci == 2) { - handler = sam_hsmci2_interrupt; - irq = SAM_IRQ_HSMCI2; + irq = SAM_IRQ_HSMCI2; } else #endif @@ -1984,7 +1938,7 @@ static int sam_attach(FAR struct sdio_dev_s *dev) /* Attach the HSMCI interrupt handler */ - ret = irq_attach(irq, handler); + ret = irq_attach(irq, sam_hsmci_interrupt, priv); if (ret == OK) { diff --git a/arch/arm/src/sama5/sam_nand.c b/arch/arm/src/sama5/sam_nand.c index 1ac8e2a9ba6..05182120d93 100644 --- a/arch/arm/src/sama5/sam_nand.c +++ b/arch/arm/src/sama5/sam_nand.c @@ -181,7 +181,7 @@ static void nand_wait_nfcbusy(struct sam_nandcs_s *priv); #endif static uint32_t nand_nfc_poll(void); #ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS -static int hsmc_interrupt(int irq, void *context); +static int hsmc_interrupt(int irq, void *context, FAR void *arg); #endif /* DMA Helpers */ @@ -1059,7 +1059,7 @@ static uint32_t nand_nfc_poll(void) ****************************************************************************/ #ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS -static int hsmc_interrupt(int irq, void *context) +static int hsmc_interrupt(int irq, void *context, FAR void *arg) { uint32_t sr = nand_nfc_poll(); uint32_t imr = nand_getreg(SAM_HSMC_IMR); @@ -2992,7 +2992,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs) #ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS /* Attach the CAN interrupt handler */ - ret = irq_attach(SAM_IRQ_HSMC, hsmc_interrupt); + ret = irq_attach(SAM_IRQ_HSMC, hsmc_interrupt, NULL); if (ret < 0) { ferr("ERROR: Failed to attach HSMC IRQ (%d)", SAM_IRQ_HSMC); diff --git a/arch/arm/src/sama5/sam_ohci.c b/arch/arm/src/sama5/sam_ohci.c index b4a6b03f92d..f6907d1b0f2 100644 --- a/arch/arm/src/sama5/sam_ohci.c +++ b/arch/arm/src/sama5/sam_ohci.c @@ -4109,7 +4109,7 @@ struct usbhost_connection_s *sam_ohci_initialize(int controller) * then it will manage the shared interrupt. */ - if (irq_attach(SAM_IRQ_UHPHS, sam_ohci_tophalf) != 0) + if (irq_attach(SAM_IRQ_UHPHS, sam_ohci_tophalf, NULL) != 0) { usbhost_trace1(OHCI_TRACE1_IRQATTACH, SAM_IRQ_UHPHS); return NULL; @@ -4176,7 +4176,7 @@ struct usbhost_connection_s *sam_ohci_initialize(int controller) * ****************************************************************************/ -int sam_ohci_tophalf(int irq, void *context) +int sam_ohci_tophalf(int irq, void *context, FAR void *arg) { uint32_t intst; uint32_t inten; diff --git a/arch/arm/src/sama5/sam_pioirq.c b/arch/arm/src/sama5/sam_pioirq.c index 2d9950168ed..97aef6a0bce 100644 --- a/arch/arm/src/sama5/sam_pioirq.c +++ b/arch/arm/src/sama5/sam_pioirq.c @@ -202,42 +202,42 @@ static int sam_piointerrupt(uint32_t base, int irq0, void *context) } #ifdef CONFIG_SAMA5_PIOA_IRQ -static int sam_pioainterrupt(int irq, void *context) +static int sam_pioainterrupt(int irq, void *context, FAR void *arg) { return sam_piointerrupt(SAM_PIOA_VBASE, SAM_IRQ_PA0, context); } #endif #ifdef CONFIG_SAMA5_PIOB_IRQ -static int sam_piobinterrupt(int irq, void *context) +static int sam_piobinterrupt(int irq, void *context, FAR void *arg) { return sam_piointerrupt(SAM_PIOB_VBASE, SAM_IRQ_PB0, context); } #endif #ifdef CONFIG_SAMA5_PIOC_IRQ -static int sam_piocinterrupt(int irq, void *context) +static int sam_piocinterrupt(int irq, void *context, FAR void *arg) { return sam_piointerrupt(SAM_PIOC_VBASE, SAM_IRQ_PC0, context); } #endif #ifdef CONFIG_SAMA5_PIOD_IRQ -static int sam_piodinterrupt(int irq, void *context) +static int sam_piodinterrupt(int irq, void *context, FAR void *arg) { return sam_piointerrupt(SAM_PIOD_VBASE, SAM_IRQ_PD0, context); } #endif #ifdef CONFIG_SAMA5_PIOE_IRQ -static int sam_pioeinterrupt(int irq, void *context) +static int sam_pioeinterrupt(int irq, void *context, FAR void *arg) { return sam_piointerrupt(SAM_PIOE_VBASE, SAM_IRQ_PE0, context); } #endif #ifdef CONFIG_SAMA5_PIOF_IRQ -static int sam_piofinterrupt(int irq, void *context) +static int sam_piofinterrupt(int irq, void *context, FAR void *arg) { return sam_piointerrupt(SAM_PIOF_VBASE, SAM_IRQ_PF0, context); } @@ -272,7 +272,7 @@ void sam_pioirqinitialize(void) /* Attach and enable the PIOA IRQ */ - (void)irq_attach(SAM_IRQ_PIOA, sam_pioainterrupt); + (void)irq_attach(SAM_IRQ_PIOA, sam_pioainterrupt, NULL); up_enable_irq(SAM_IRQ_PIOA); #endif @@ -290,7 +290,7 @@ void sam_pioirqinitialize(void) /* Attach and enable the PIOB IRQ */ - (void)irq_attach(SAM_IRQ_PIOB, sam_piobinterrupt); + (void)irq_attach(SAM_IRQ_PIOB, sam_piobinterrupt, NULL); up_enable_irq(SAM_IRQ_PIOB); #endif @@ -308,7 +308,7 @@ void sam_pioirqinitialize(void) /* Attach and enable the PIOC IRQ */ - (void)irq_attach(SAM_IRQ_PIOC, sam_piocinterrupt); + (void)irq_attach(SAM_IRQ_PIOC, sam_piocinterrupt, NULL); up_enable_irq(SAM_IRQ_PIOC); #endif @@ -326,7 +326,7 @@ void sam_pioirqinitialize(void) /* Attach and enable the PIOC IRQ */ - (void)irq_attach(SAM_IRQ_PIOD, sam_piodinterrupt); + (void)irq_attach(SAM_IRQ_PIOD, sam_piodinterrupt, NULL); up_enable_irq(SAM_IRQ_PIOD); #endif @@ -344,7 +344,7 @@ void sam_pioirqinitialize(void) /* Attach and enable the PIOE IRQ */ - (void)irq_attach(SAM_IRQ_PIOE, sam_pioeinterrupt); + (void)irq_attach(SAM_IRQ_PIOE, sam_pioeinterrupt, NULL); up_enable_irq(SAM_IRQ_PIOE); #endif @@ -362,7 +362,7 @@ void sam_pioirqinitialize(void) /* Attach and enable the PIOF IRQ */ - (void)irq_attach(SAM_IRQ_PIOF, sam_piofinterrupt); + (void)irq_attach(SAM_IRQ_PIOF, sam_piofinterrupt, NULL); up_enable_irq(SAM_IRQ_PIOF); #endif } diff --git a/arch/arm/src/sama5/sam_pwm.c b/arch/arm/src/sama5/sam_pwm.c index 622d4569b0f..90b204eac30 100644 --- a/arch/arm/src/sama5/sam_pwm.c +++ b/arch/arm/src/sama5/sam_pwm.c @@ -330,7 +330,7 @@ static void pwm_dumpregs(FAR struct sam_pwm_chan_s *chan, FAR const char *msg); /* PWM Interrupts */ #ifdef PWM_INTERRUPTS -static int pwm_interrupt(int irq, void *context); +static int pwm_interrupt(int irq, void *context, FAR void *arg); #endif /* PWM driver methods */ @@ -836,7 +836,7 @@ static void pwm_dumpregs(struct sam_pwm_chan_s *chan, FAR const char *msg) ****************************************************************************/ #ifdef PWM_INTERRUPTS -static int pwm_interrupt(int irq, void *context) +static int pwm_interrupt(int irq, void *context, FAR void *arg) { /* No PWM interrupts are used in the current design */ @@ -1393,7 +1393,7 @@ FAR struct pwm_lowerhalf_s *sam_pwminitialize(int channel) /* Attach the PWM interrupt handler */ #ifdef PWM_INTERRUPTS - ret = irq_attach(SAM_IRQ_PWM, pwm_interrupt); + ret = irq_attach(SAM_IRQ_PWM, pwm_interrupt, NULL); if (ret < 0) { pwmerr("ERROR: Failed to attach IRQ%d\n", channel); diff --git a/arch/arm/src/sama5/sam_rtc.c b/arch/arm/src/sama5/sam_rtc.c index e73e473b706..b5a893b3616 100644 --- a/arch/arm/src/sama5/sam_rtc.c +++ b/arch/arm/src/sama5/sam_rtc.c @@ -255,7 +255,7 @@ static void rtc_worker(FAR void *arg) ************************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int rtc_interrupt(int irq, void *context) +static int rtc_interrupt(int irq, void *context, FAR void *arg) { int ret; @@ -321,7 +321,7 @@ int up_rtc_initialize(void) #ifdef CONFIG_RTC_ALARM /* Then attach the ALARM interrupt handler */ - irq_attach(SAM_PID_SYS, rtc_interrupt); + irq_attach(SAM_PID_SYS, rtc_interrupt, NULL); /* Should RTC alarm interrupt be enabled at the peripheral? Let's assume so * for now. Let's say yes if the time is valid and a valid alarm has been diff --git a/arch/arm/src/sama5/sam_serial.c b/arch/arm/src/sama5/sam_serial.c index a73ac33cd24..b9da00d8555 100644 --- a/arch/arm/src/sama5/sam_serial.c +++ b/arch/arm/src/sama5/sam_serial.c @@ -418,7 +418,6 @@ struct up_dev_s { - xcpt_t handler; /* Interrupt handler */ uint32_t usartbase; /* Base address of USART registers */ uint32_t baud; /* Configured baud */ uint32_t sr; /* Saved status bits */ @@ -435,38 +434,7 @@ struct up_dev_s * Private Function Prototypes ****************************************************************************/ -static int up_interrupt(struct uart_dev_s *dev); -#ifdef CONFIG_SAMA5_UART0 -static int up_uart0_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_SAMA5_UART1 -static int up_uart1_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_SAMA5_UART2 -static int up_uart2_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_SAMA5_UART3 -static int up_uart3_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_SAMA5_UART4 -static int up_uart4_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_USART0_SERIALDRIVER -static int up_usart0_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_USART1_SERIALDRIVER -static int up_usart1_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_USART2_SERIALDRIVER -static int up_usart2_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_USART3_SERIALDRIVER -static int up_usart3_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_USART4_SERIALDRIVER -static int up_usart4_interrupt(int irq, void *context); -#endif - +static int up_interrupt(int irq, void *context, FAR void *arg); static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); @@ -561,7 +529,6 @@ static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE]; static struct up_dev_s g_uart0priv = { - .handler = up_uart0_interrupt, .usartbase = SAM_UART0_VBASE, .baud = CONFIG_UART0_BAUD, .irq = SAM_IRQ_UART0, @@ -602,7 +569,6 @@ static uart_dev_t g_uart0port = static struct up_dev_s g_uart1priv = { - .handler = up_uart1_interrupt, .usartbase = SAM_UART1_VBASE, .baud = CONFIG_UART1_BAUD, .irq = SAM_IRQ_UART1, @@ -643,7 +609,6 @@ static uart_dev_t g_uart1port = static struct up_dev_s g_uart2priv = { - .handler = up_uart2_interrupt, .usartbase = SAM_UART2_VBASE, .baud = CONFIG_UART2_BAUD, .irq = SAM_IRQ_UART2, @@ -684,7 +649,6 @@ static uart_dev_t g_uart2port = static struct up_dev_s g_uart3priv = { - .handler = up_uart3_interrupt, .usartbase = SAM_UART3_VBASE, .baud = CONFIG_UART3_BAUD, .irq = SAM_IRQ_UART3, @@ -725,7 +689,6 @@ static uart_dev_t g_uart3port = static struct up_dev_s g_uart4priv = { - .handler = up_uart4_interrupt, .usartbase = SAM_UART4_VBASE, .baud = CONFIG_UART4_BAUD, .irq = SAM_IRQ_UART4, @@ -756,7 +719,6 @@ static uart_dev_t g_uart4port = #ifdef CONFIG_USART0_SERIALDRIVER static struct up_dev_s g_usart0priv = { - .handler = up_usart0_interrupt, .usartbase = SAM_USART0_VBASE, .baud = CONFIG_USART0_BAUD, .irq = SAM_IRQ_USART0, @@ -790,7 +752,6 @@ static uart_dev_t g_usart0port = #ifdef CONFIG_USART1_SERIALDRIVER static struct up_dev_s g_usart1priv = { - .handler = up_usart1_interrupt, .usartbase = SAM_USART1_VBASE, .baud = CONFIG_USART1_BAUD, .irq = SAM_IRQ_USART1, @@ -824,7 +785,6 @@ static uart_dev_t g_usart1port = #ifdef CONFIG_USART2_SERIALDRIVER static struct up_dev_s g_usart2priv = { - .handler = up_usart2_interrupt, .usartbase = SAM_USART2_VBASE, .baud = CONFIG_USART2_BAUD, .irq = SAM_IRQ_USART2, @@ -858,7 +818,6 @@ static uart_dev_t g_usart2port = #ifdef CONFIG_USART3_SERIALDRIVER static struct up_dev_s g_usart3priv = { - .handler = up_usart3_interrupt, .usartbase = SAM_USART3_VBASE, .baud = CONFIG_USART3_BAUD, .irq = SAM_IRQ_USART3, @@ -892,7 +851,6 @@ static uart_dev_t g_usart3port = #ifdef CONFIG_USART4_SERIALDRIVER static struct up_dev_s g_usart4priv = { - .handler = up_usart4_interrupt, .usartbase = SAM_USART4_VBASE, .baud = CONFIG_USART4_BAUD, .irq = SAM_IRQ_USART4, @@ -989,8 +947,9 @@ static void up_disableallints(struct up_dev_s *priv, uint32_t *imr) * ****************************************************************************/ -static int up_interrupt(struct uart_dev_s *dev) +static int up_interrupt(int irq, void *context, FAR void *arg) { + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct up_dev_s *priv; uint32_t pending; uint32_t imr; @@ -1043,67 +1002,6 @@ static int up_interrupt(struct uart_dev_s *dev) return OK; } -#ifdef CONFIG_SAMA5_UART0 -static int up_uart0_interrupt(int irq, void *context) -{ - return up_interrupt(&g_uart0port); -} -#endif -#ifdef CONFIG_SAMA5_UART1 -static int up_uart1_interrupt(int irq, void *context) -{ - return up_interrupt(&g_uart1port); -} -#endif -#ifdef CONFIG_SAMA5_UART2 -static int up_uart2_interrupt(int irq, void *context) -{ - return up_interrupt(&g_uart2port); -} -#endif -#ifdef CONFIG_SAMA5_UART3 -static int up_uart3_interrupt(int irq, void *context) -{ - return up_interrupt(&g_uart3port); -} -#endif -#ifdef CONFIG_SAMA5_UART4 -static int up_uart4_interrupt(int irq, void *context) -{ - return up_interrupt(&g_uart4port); -} -#endif -#ifdef CONFIG_USART0_SERIALDRIVER -static int up_usart0_interrupt(int irq, void *context) -{ - return up_interrupt(&g_usart0port); -} -#endif -#ifdef CONFIG_USART1_SERIALDRIVER -static int up_usart1_interrupt(int irq, void *context) -{ - return up_interrupt(&g_usart1port); -} -#endif -#ifdef CONFIG_USART2_SERIALDRIVER -static int up_usart2_interrupt(int irq, void *context) -{ - return up_interrupt(&g_usart2port); -} -#endif -#ifdef CONFIG_USART3_SERIALDRIVER -static int up_usart3_interrupt(int irq, void *context) -{ - return up_interrupt(&g_usart3port); -} -#endif -#ifdef CONFIG_USART4_SERIALDRIVER -static int up_usart4_interrupt(int irq, void *context) -{ - return up_interrupt(&g_usart4port); -} -#endif - /**************************************************************************** * Name: up_setup * @@ -1294,7 +1192,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, priv->handler); + ret = irq_attach(priv->irq, up_interrupt, dev); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled diff --git a/arch/arm/src/sama5/sam_tc.c b/arch/arm/src/sama5/sam_tc.c index 7d8e19370cc..015d6bc96a5 100644 --- a/arch/arm/src/sama5/sam_tc.c +++ b/arch/arm/src/sama5/sam_tc.c @@ -175,13 +175,13 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, static int sam_tc_interrupt(struct sam_tc_s *tc); #ifdef CONFIG_SAMA5_TC0 -static int sam_tc012_interrupt(int irq, void *context); +static int sam_tc012_interrupt(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_SAMA5_TC1 -static int sam_tc345_interrupt(int irq, void *context); +static int sam_tc345_interrupt(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_SAMA5_TC2 -static int sam_tc678_interrupt(int irq, void *context); +static int sam_tc678_interrupt(int irq, void *context, FAR void *arg); #endif /* Initialization ***********************************************************/ @@ -763,21 +763,21 @@ static int sam_tc_interrupt(struct sam_tc_s *tc) ****************************************************************************/ #ifdef CONFIG_SAMA5_TC0 -static int sam_tc012_interrupt(int irq, void *context) +static int sam_tc012_interrupt(int irq, void *context, void *arg) { return sam_tc_interrupt(&g_tc012); } #endif #ifdef CONFIG_SAMA5_TC1 -static int sam_tc345_interrupt(int irq, void *context) +static int sam_tc345_interrupt(int irq, void *context, FAR void *arg) { return sam_tc_interrupt(&g_tc345); } #endif #ifdef CONFIG_SAMA5_TC2 -static int sam_tc678_interrupt(int irq, void *context) +static int sam_tc678_interrupt(int irq, void *context, FAR void *arg) { return sam_tc_interrupt(&g_tc678); } @@ -1038,7 +1038,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel) /* Attach the timer interrupt handler and enable the timer interrupts */ - (void)irq_attach(tc->pid, handler); + (void)irq_attach(tc->pid, handler, NULL); up_enable_irq(tc->pid); /* Now the channel is initialized */ diff --git a/arch/arm/src/sama5/sam_timerisr.c b/arch/arm/src/sama5/sam_timerisr.c index 3495bc64271..957c4efad24 100644 --- a/arch/arm/src/sama5/sam_timerisr.c +++ b/arch/arm/src/sama5/sam_timerisr.c @@ -88,7 +88,7 @@ * ****************************************************************************/ -static int sam_timerisr(int irq, uint32_t *regs) +static int sam_timerisr(int irq, uint32_t *regs, void *arg) { /* "When CPIV and PICNT values are obtained by reading the Periodic * Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is @@ -136,7 +136,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(SAM_IRQ_PIT, (xcpt_t)sam_timerisr); + (void)irq_attach(SAM_IRQ_PIT, (xcpt_t)sam_timerisr, NULL); /* Set the PIT overflow value (PIV), enable the PIT, and enable * interrupts from the PIT. diff --git a/arch/arm/src/sama5/sam_trng.c b/arch/arm/src/sama5/sam_trng.c index c724612456a..fed9a347acf 100644 --- a/arch/arm/src/sama5/sam_trng.c +++ b/arch/arm/src/sama5/sam_trng.c @@ -71,7 +71,7 @@ /* Interrupts */ -static int sam_interrupt(int irq, void *context); +static int sam_interrupt(int irq, void *context, FAR void *arg); /* Character driver methods */ @@ -127,7 +127,7 @@ static const struct file_operations g_trngops = * ****************************************************************************/ -static int sam_interrupt(int irq, void *context) +static int sam_interrupt(int irq, void *context, FAR void *arg) { uint32_t odata; @@ -371,7 +371,7 @@ static int sam_rng_initialize(void) /* Initialize the TRNG interrupt */ - ret = irq_attach(SAM_IRQ_TRNG, sam_interrupt); + ret = irq_attach(SAM_IRQ_TRNG, sam_interrupt, NULL); if (ret < 0) { ferr("ERROR: Failed to attach to IRQ%d\n", SAM_IRQ_TRNG); diff --git a/arch/arm/src/sama5/sam_twi.c b/arch/arm/src/sama5/sam_twi.c index 52f3e0950d1..117f29b4451 100644 --- a/arch/arm/src/sama5/sam_twi.c +++ b/arch/arm/src/sama5/sam_twi.c @@ -199,21 +199,9 @@ static inline void twi_putrel(struct twi_dev_s *priv, unsigned int offset, /* I2C transfer helper functions */ -static int twi_wait(struct twi_dev_s *priv, unsigned int size); +static int twi_wait(struct twi_dev_s *priv, unsigned int size); static void twi_wakeup(struct twi_dev_s *priv, int result); -static int twi_interrupt(struct twi_dev_s *priv); -#ifdef CONFIG_SAMA5_TWI0 -static int twi0_interrupt(int irq, FAR void *context); -#endif -#ifdef CONFIG_SAMA5_TWI1 -static int twi1_interrupt(int irq, FAR void *context); -#endif -#ifdef CONFIG_SAMA5_TWI2 -static int twi2_interrupt(int irq, FAR void *context); -#endif -#ifdef CONFIG_SAMA5_TWI3 -static int twi3_interrupt(int irq, FAR void *context); -#endif +static int twi_interrupt(int irq, FAR void *context, FAR void *arg); static void twi_timeout(int argc, uint32_t arg, ...); static void twi_startread(struct twi_dev_s *priv, struct i2c_msg_s *msg); @@ -246,7 +234,6 @@ static const struct twi_attr_s g_twi0attr = .sclcfg = PIO_TWI0_CK, .sdacfg = PIO_TWI0_D, .base = SAM_TWI0_VBASE, - .handler = twi0_interrupt, }; static struct twi_dev_s g_twi0; @@ -261,7 +248,6 @@ static const struct twi_attr_s g_twi1attr = .sclcfg = PIO_TWI1_CK, .sdacfg = PIO_TWI1_D, .base = SAM_TWI1_VBASE, - .handler = twi1_interrupt, }; static struct twi_dev_s g_twi1; @@ -276,7 +262,6 @@ static const struct twi_attr_s g_twi2attr = .sclcfg = PIO_TWI2_CK, .sdacfg = PIO_TWI2_D, .base = SAM_TWI2_VBASE, - .handler = twi2_interrupt, }; static struct twi_dev_s g_twi2; @@ -291,7 +276,6 @@ static const struct twi_attr_s g_twi3attr = .sclcfg = PIO_TWI3_CK, .sdacfg = PIO_TWI3_D, .base = SAM_TWI3_VBASE, - .handler = twi3_interrupt, }; static struct twi_dev_s g_twi3; @@ -550,14 +534,17 @@ static void twi_wakeup(struct twi_dev_s *priv, int result) * ****************************************************************************/ -static int twi_interrupt(struct twi_dev_s *priv) +static int twi_interrupt(int irq, FAR void *context, FAR void *arg) { + struct twi_dev_s *priv = (struct twi_dev_s *)arg; struct i2c_msg_s *msg; uint32_t sr; uint32_t imr; uint32_t pending; uint32_t regval; + DEBUGASSERT(priv != NULL); + /* Retrieve masked interrupt status */ sr = twi_getrel(priv, SAM_TWI_SR_OFFSET); @@ -667,34 +654,6 @@ static int twi_interrupt(struct twi_dev_s *priv) return OK; } -#ifdef CONFIG_SAMA5_TWI0 -static int twi0_interrupt(int irq, FAR void *context) -{ - return twi_interrupt(&g_twi0); -} -#endif - -#ifdef CONFIG_SAMA5_TWI1 -static int twi1_interrupt(int irq, FAR void *context) -{ - return twi_interrupt(&g_twi1); -} -#endif - -#ifdef CONFIG_SAMA5_TWI2 -static int twi2_interrupt(int irq, FAR void *context) -{ - return twi_interrupt(&g_twi2); -} -#endif - -#ifdef CONFIG_SAMA5_TWI3 -static int twi3_interrupt(int irq, FAR void *context) -{ - return twi_interrupt(&g_twi3); -} -#endif - /**************************************************************************** * Name: twi_timeout * @@ -1296,7 +1255,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus) /* Attach Interrupt Handler */ - ret = irq_attach(priv->attr->irq, priv->attr->handler); + ret = irq_attach(priv->attr->irq, twi_interrupt, priv); if (ret < 0) { ierr("ERROR: Failed to attach irq %d\n", priv->attr->irq); diff --git a/arch/arm/src/sama5/sam_udphs.c b/arch/arm/src/sama5/sam_udphs.c index 76f704d1f69..3f27bd31122 100644 --- a/arch/arm/src/sama5/sam_udphs.c +++ b/arch/arm/src/sama5/sam_udphs.c @@ -448,7 +448,7 @@ static void sam_setdevaddr(struct sam_usbdev_s *priv, uint8_t value); static void sam_ep0_setup(struct sam_usbdev_s *priv); static void sam_dma_interrupt(struct sam_usbdev_s *priv, int chan); static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno); -static int sam_udphs_interrupt(int irq, void *context); +static int sam_udphs_interrupt(int irq, void *context, FAR void *arg); /* Endpoint helpers *********************************************************/ @@ -2770,7 +2770,7 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno) * ****************************************************************************/ -static int sam_udphs_interrupt(int irq, void *context) +static int sam_udphs_interrupt(int irq, void *context, FAR void *arg) { /* For now there is only one USB controller, but we will always refer to * it using a pointer to make any future ports to multiple UDPHS controllers @@ -4437,7 +4437,7 @@ void up_usbinitialize(void) * them when we need them later. */ - if (irq_attach(SAM_IRQ_UDPHS, sam_udphs_interrupt) != 0) + if (irq_attach(SAM_IRQ_UDPHS, sam_udphs_interrupt, NULL) != 0) { usbtrace(TRACE_DEVERROR(SAM_TRACEERR_IRQREGISTRATION), (uint16_t)SAM_IRQ_UDPHS); diff --git a/arch/arm/src/sama5/sam_usbhost.h b/arch/arm/src/sama5/sam_usbhost.h index a67a0a42ddc..90e2b81a590 100644 --- a/arch/arm/src/sama5/sam_usbhost.h +++ b/arch/arm/src/sama5/sam_usbhost.h @@ -271,7 +271,7 @@ FAR struct usbhost_connection_s *sam_ohci_initialize(int controller); ************************************************************************************/ #ifdef CONFIG_SAMA5_OHCI -int sam_ohci_tophalf(int irq, FAR void *context); +int sam_ohci_tophalf(int irq, FAR void *context, FAR void *arg); #endif /************************************************************************************ diff --git a/arch/arm/src/sama5/sam_wdt.c b/arch/arm/src/sama5/sam_wdt.c index 342aa5c8f3d..9d3f7dd61ea 100644 --- a/arch/arm/src/sama5/sam_wdt.c +++ b/arch/arm/src/sama5/sam_wdt.c @@ -120,7 +120,7 @@ static void sam_putreg(uint32_t regval, uintptr_t regaddr); /* Interrupt hanlding *******************************************************/ #ifdef CONFIG_SAMA5_WDT_INTERRUPT -static int sam_interrupt(int irq, FAR void *context); +static int sam_interrupt(int irq, FAR void *context, FAR void *arg); #endif /* "Lower half" driver methods **********************************************/ @@ -260,7 +260,7 @@ static void sam_putreg(uint32_t regval, uintptr_t regaddr) ****************************************************************************/ #ifdef CONFIG_SAMA5_WDT_INTERRUPT -static int sam_interrupt(int irq, FAR void *context) +static int sam_interrupt(int irq, FAR void *context, FAR void *arg) { FAR struct sam_lowerhalf_s *priv = &g_wdtdev; @@ -684,7 +684,7 @@ int sam_wdt_initialize(void) #ifdef CONFIG_SAMA5_WDT_INTERRUPT /* Attach our WDT interrupt handler (But don't enable it yet) */ - (void)irq_attach(SAM_IRQ_WDT, sam_interrupt); + (void)irq_attach(SAM_IRQ_WDT, sam_interrupt, NULL); #endif /* Register the watchdog driver at the configured location (default diff --git a/arch/arm/src/sama5/sam_xdmac.c b/arch/arm/src/sama5/sam_xdmac.c index 9b819555569..54386d92e19 100644 --- a/arch/arm/src/sama5/sam_xdmac.c +++ b/arch/arm/src/sama5/sam_xdmac.c @@ -1825,14 +1825,17 @@ static void sam_dmaterminate(struct sam_xdmach_s *xdmach, int result) * ****************************************************************************/ -static int sam_xdmac_interrupt(struct sam_xdmac_s *xdmac) +static int sam_xdmac_interrupt(int irq, void *context, FAR void *arg) { + struct sam_xdmac_s *xdmac = (struct sam_xdmac_s *)arg; struct sam_xdmach_s *xdmach; unsigned int chndx; uint32_t gpending; uint32_t chpending; uint32_t bit; + DEBUGASSERT(xdmac != NULL); + /* Get the set of pending, unmasked global XDMAC interrupts */ gpending = sam_getdmac(xdmac, SAM_XDMAC_GIS_OFFSET) & @@ -1890,28 +1893,6 @@ static int sam_xdmac_interrupt(struct sam_xdmac_s *xdmac) return OK; } -/**************************************************************************** - * Name: sam_xdmac0_interrupt and sam_xdmac1_interrupt - * - * Description: - * DMA interrupt handler - * - ****************************************************************************/ - -#ifdef CONFIG_SAMA5_XDMAC0 -static int sam_xdmac0_interrupt(int irq, void *context) -{ - return sam_xdmac_interrupt(&g_xdmac0); -} -#endif - -#ifdef CONFIG_SAMA5_XDMAC1 -static int sam_xdmac1_interrupt(int irq, void *context) -{ - return sam_xdmac_interrupt(&g_xdmac1); -} -#endif - /**************************************************************************** * Name: sam_dmainitialize * @@ -1965,7 +1946,7 @@ void weak_function up_dmainitialize(void) /* Attach DMA interrupt vector */ - (void)irq_attach(SAM_IRQ_XDMAC0, sam_xdmac0_interrupt); + (void)irq_attach(SAM_IRQ_XDMAC0, sam_xdmac_interrupt, &g_xdmac0); /* Initialize the controller */ @@ -1985,7 +1966,7 @@ void weak_function up_dmainitialize(void) /* Attach DMA interrupt vector */ - (void)irq_attach(SAM_IRQ_XDMAC1, sam_xdmac1_interrupt); + (void)irq_attach(SAM_IRQ_XDMAC1, sam_xdmac_interrupt, &g_xdmac1); /* Initialize the controller */ diff --git a/arch/arm/src/samdl/sam_dmac.c b/arch/arm/src/samdl/sam_dmac.c index d465d4d5f87..20501ecc0ed 100644 --- a/arch/arm/src/samdl/sam_dmac.c +++ b/arch/arm/src/samdl/sam_dmac.c @@ -117,7 +117,7 @@ static void sam_takedsem(void); static inline void sam_givedsem(void); #endif static void sam_dmaterminate(struct sam_dmach_s *dmach, int result); -static int sam_dmainterrupt(int irq, void *context); +static int sam_dmainterrupt(int irq, void *context, FAR void *arg); static struct dma_desc_s *sam_alloc_desc(struct sam_dmach_s *dmach); static struct dma_desc_s *sam_append_desc(struct sam_dmach_s *dmach, uint16_t btctrl, uint16_t btcnt, @@ -275,7 +275,7 @@ static void sam_dmaterminate(struct sam_dmach_s *dmach, int result) * ****************************************************************************/ -static int sam_dmainterrupt(int irq, void *context) +static int sam_dmainterrupt(int irq, void *context, FAR void *arg) { struct sam_dmach_s *dmach; unsigned int chndx; @@ -807,7 +807,7 @@ void weak_function up_dmainitialize(void) /* Attach DMA interrupt vector */ - (void)irq_attach(SAM_IRQ_DMAC, sam_dmainterrupt); + (void)irq_attach(SAM_IRQ_DMAC, sam_dmainterrupt, NULL); /* Set the LPRAM DMA descriptor table addresses. These can only be * written when the DMAC is disabled. diff --git a/arch/arm/src/samdl/sam_irq.c b/arch/arm/src/samdl/sam_irq.c index 025c2008182..6d3deeb2e83 100644 --- a/arch/arm/src/samdl/sam_irq.c +++ b/arch/arm/src/samdl/sam_irq.c @@ -94,7 +94,7 @@ volatile uint32_t *g_current_regs[1]; ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int sam_nmi(int irq, FAR void *context) +static int sam_nmi(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -102,7 +102,7 @@ static int sam_nmi(int irq, FAR void *context) return 0; } -static int sam_pendsv(int irq, FAR void *context) +static int sam_pendsv(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -110,7 +110,7 @@ static int sam_pendsv(int irq, FAR void *context) return 0; } -static int sam_reserved(int irq, FAR void *context) +static int sam_reserved(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -187,15 +187,15 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(SAM_IRQ_SVCALL, up_svcall); - irq_attach(SAM_IRQ_HARDFAULT, up_hardfault); + irq_attach(SAM_IRQ_SVCALL, up_svcall, NULL); + irq_attach(SAM_IRQ_HARDFAULT, up_hardfault, NULL); /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(SAM_IRQ_NMI, sam_nmi); - irq_attach(SAM_IRQ_PENDSV, sam_pendsv); - irq_attach(SAM_IRQ_RESERVED, sam_reserved); + irq_attach(SAM_IRQ_NMI, sam_nmi, NULL); + irq_attach(SAM_IRQ_PENDSV, sam_pendsv, NULL); + irq_attach(SAM_IRQ_RESERVED, sam_reserved, NULL); #endif sam_dumpnvic("initial", NR_IRQS); diff --git a/arch/arm/src/samdl/sam_serial.c b/arch/arm/src/samdl/sam_serial.c index ac94f694acf..8c88850acc6 100644 --- a/arch/arm/src/samdl/sam_serial.c +++ b/arch/arm/src/samdl/sam_serial.c @@ -228,8 +228,6 @@ struct sam_dev_s const struct sam_usart_config_s * const config; /* Information unique to the serial driver */ - - xcpt_t handler; /* Interrupt handler */ }; /**************************************************************************** @@ -249,26 +247,7 @@ static inline void sam_serialout16(struct sam_dev_s *priv, int offset, uint16_t regval); static void sam_disableallints(struct sam_dev_s *priv); -static int sam_interrupt(struct uart_dev_s *dev); - -#ifdef SAMDL_HAVE_USART0 -static int sam_usart0_interrupt(int irq, void *context); -#endif -#ifdef SAMDL_HAVE_USART1 -static int sam_usart1_interrupt(int irq, void *context); -#endif -#ifdef SAMDL_HAVE_USART2 -static int sam_usart2_interrupt(int irq, void *context); -#endif -#ifdef SAMDL_HAVE_USART3 -static int sam_usart3_interrupt(int irq, void *context); -#endif -#ifdef SAMDL_HAVE_USART4 -static int sam_usart4_interrupt(int irq, void *context); -#endif -#ifdef SAMDL_HAVE_USART5 -static int sam_usart5_interrupt(int irq, void *context); -#endif +static int sam_interrupt(int irq, void *context, FAR void *arg); /* UART methods */ @@ -340,7 +319,6 @@ static char g_usart5txbuffer[CONFIG_USART5_TXBUFSIZE]; static struct sam_dev_s g_usart0priv = { .config = &g_usart0config, - .handler = sam_usart0_interrupt, }; static uart_dev_t g_usart0port = @@ -366,7 +344,6 @@ static uart_dev_t g_usart0port = static struct sam_dev_s g_usart1priv = { .config = &g_usart1config, - .handler = sam_usart1_interrupt, }; static uart_dev_t g_usart1port = @@ -392,7 +369,6 @@ static uart_dev_t g_usart1port = static struct sam_dev_s g_usart2priv = { .config = &g_usart2config, - .handler = sam_usart2_interrupt, }; static uart_dev_t g_usart2port = @@ -418,7 +394,6 @@ static uart_dev_t g_usart2port = static struct sam_dev_s g_usart3priv = { .config = &g_usart3config, - .handler = sam_usart3_interrupt, }; static uart_dev_t g_usart3port = @@ -444,7 +419,6 @@ static uart_dev_t g_usart3port = static struct sam_dev_s g_usart4priv = { .config = &g_usart4config, - .handler = sam_usart4_interrupt, }; static uart_dev_t g_usart4port = @@ -470,7 +444,6 @@ static uart_dev_t g_usart4port = static struct sam_dev_s g_usart5priv = { .config = &g_usart5config, - .handler = sam_usart5_interrupt, }; static uart_dev_t g_usart5port = @@ -555,13 +528,17 @@ static void sam_disableallints(struct sam_dev_s *priv) * ****************************************************************************/ -static int sam_interrupt(struct uart_dev_s *dev) +static int sam_interrupt(int irq, void *context, FAR void *arg) { - struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct sam_dev_s *priv; uint8_t pending; uint8_t intflag; uint8_t inten; + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct sam_dev_s *)dev->priv; + /* Get the set of pending USART interrupts (we are only interested in the * unmasked interrupts). */ @@ -599,57 +576,6 @@ static int sam_interrupt(struct uart_dev_s *dev) return OK; } -/**************************************************************************** - * Name: sam_usartN_interrupt - * - * Description: - * Handle each SERCOM USART interrupt by calling the common interrupt - * handling logic with the USART-specific state. - * - ****************************************************************************/ - -#ifdef SAMDL_HAVE_USART0 -static int sam_usart0_interrupt(int irq, void *context) -{ - return sam_interrupt(&g_usart0port); -} -#endif - -#ifdef SAMDL_HAVE_USART1 -static int sam_usart1_interrupt(int irq, void *context) -{ - return sam_interrupt(&g_usart1port); -} -#endif - -#ifdef SAMDL_HAVE_USART2 -static int sam_usart2_interrupt(int irq, void *context) -{ - return sam_interrupt(&g_usart2port); -} -#endif - -#ifdef SAMDL_HAVE_USART3 -static int sam_usart3_interrupt(int irq, void *context) -{ - return sam_interrupt(&g_usart3port); -} -#endif - -#ifdef SAMDL_HAVE_USART4 -static int sam_usart4_interrupt(int irq, void *context) -{ - return sam_interrupt(&g_usart4port); -} -#endif - -#ifdef SAMDL_HAVE_USART5 -static int sam_usart5_interrupt(int irq, void *context) -{ - return sam_interrupt(&g_usart5port); -} -#endif - /**************************************************************************** * Name: sam_setup * @@ -726,7 +652,7 @@ static int sam_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(config->irq, priv->handler); + ret = irq_attach(config->irq, sam_interrupt, dev); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled diff --git a/arch/arm/src/samdl/sam_spi.c b/arch/arm/src/samdl/sam_spi.c index ac7ea3d2cc2..cc17758d86a 100644 --- a/arch/arm/src/samdl/sam_spi.c +++ b/arch/arm/src/samdl/sam_spi.c @@ -163,26 +163,7 @@ static void spi_dumpregs(struct sam_spidev_s *priv, const char *msg); /* Interrupt handling */ #if 0 /* Not used */ -static int spi_interrupt(struct sam_spidev_s *dev); - -#ifdef SAMDL_HAVE_SPI0 -static int spi0_interrupt(int irq, void *context); -#endif -#ifdef SAMDL_HAVE_SPI1 -static int spi1_interrupt(int irq, void *context); -#endif -#ifdef SAMDL_HAVE_SPI2 -static int spi2_interrupt(int irq, void *context); -#endif -#ifdef SAMDL_HAVE_SPI3 -static int spi3_interrupt(int irq, void *context); -#endif -#ifdef SAMDL_HAVE_SPI4 -static int spi4_interrupt(int irq, void *context); -#endif -#ifdef SAMDL_HAVE_SPI5 -static int spi5_interrupt(int irq, void *context); -#endif +static int spi_interrupt(int irq, void *context, FAR void *arg); #endif /* SPI methods */ @@ -255,9 +236,6 @@ static struct sam_spidev_s g_spi0dev = .muxconfig = BOARD_SERCOM0_MUXCONFIG, .srcfreq = BOARD_SERCOM0_FREQUENCY, .base = SAM_SERCOM0_BASE, -#if 0 /* Not used */ - .handler = spi0_interrupt, -#endif .spilock = SEM_INITIALIZER(1), }; #endif @@ -304,9 +282,6 @@ static struct sam_spidev_s g_spi1dev = .muxconfig = BOARD_SERCOM1_MUXCONFIG, .srcfreq = BOARD_SERCOM1_FREQUENCY, .base = SAM_SERCOM1_BASE, -#if 0 /* Not used */ - .handler = spi1_interrupt, -#endif .spilock = SEM_INITIALIZER(1), }; #endif @@ -353,9 +328,6 @@ static struct sam_spidev_s g_spi2dev = .muxconfig = BOARD_SERCOM2_MUXCONFIG, .srcfreq = BOARD_SERCOM2_FREQUENCY, .base = SAM_SERCOM2_BASE, -#if 0 /* Not used */ - .handler = spi2_interrupt, -#endif .spilock = SEM_INITIALIZER(1), }; #endif @@ -402,9 +374,6 @@ static struct sam_spidev_s g_spi3dev = .muxconfig = BOARD_SERCOM3_MUXCONFIG, .srcfreq = BOARD_SERCOM3_FREQUENCY, .base = SAM_SERCOM3_BASE, -#if 0 /* Not used */ - .handler = spi3_interrupt, -#endif .spilock = SEM_INITIALIZER(1), }; #endif @@ -451,9 +420,6 @@ static struct sam_spidev_s g_spi4dev = .muxconfig = BOARD_SERCOM4_MUXCONFIG, .srcfreq = BOARD_SERCOM4_FREQUENCY, .base = SAM_SERCOM4_BASE, -#if 0 /* Not used */ - .handler = spi4_interrupt, -#endif .spilock = SEM_INITIALIZER(1), }; #endif @@ -500,9 +466,6 @@ static struct sam_spidev_s g_spi5dev = .muxconfig = BOARD_SERCOM5_MUXCONFIG, .srcfreq = BOARD_SERCOM5_FREQUENCY, .base = SAM_SERCOM5_BASE, -#if 0 /* Not used */ - .handler = spi5_interrupt, -#endif .spilock = SEM_INITIALIZER(1), }; #endif @@ -748,13 +711,15 @@ static void spi_dumpregs(struct sam_spidev_s *priv, const char *msg) ****************************************************************************/ #if 0 /* Not used */ -static int spi_interrupt(struct sam_spidev_s *dev) +static int spi_interrupt(int irq, void *context, FAR void *arg) { - struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)arg uint8_t pending; uint8_t intflag; uint8_t inten; + DEBUGASSERT(priv != NULL); + /* Get the set of pending SPI interrupts (we are only interested in the * unmasked interrupts). */ @@ -791,59 +756,6 @@ static int spi_interrupt(struct sam_spidev_s *dev) } #endif -/**************************************************************************** - * Name: spiN_interrupt - * - * Description: - * Handle each SERCOM SPI interrupt by calling the common interrupt - * handling logic with the SPI-specific state. - * - ****************************************************************************/ - -#if 0 /* Not used */ -#ifdef SAMDL_HAVE_SPI0 -static int spi0_interrupt(int irq, void *context) -{ - return spi_interrupt(&g_spi0dev); -} -#endif - -#ifdef SAMDL_HAVE_SPI1 -static int spi1_interrupt(int irq, void *context) -{ - return spi_interrupt(&g_spi1dev); -} -#endif - -#ifdef SAMDL_HAVE_SPI2 -static int spi2_interrupt(int irq, void *context) -{ - return spi_interrupt(&g_spi2dev); -} -#endif - -#ifdef SAMDL_HAVE_SPI3 -static int spi3_interrupt(int irq, void *context) -{ - return spi_interrupt(&g_spi3dev); -} -#endif - -#ifdef SAMDL_HAVE_SPI4 -static int spi4_interrupt(int irq, void *context) -{ - return spi_interrupt(&g_spi4dev); -} -#endif - -#ifdef SAMDL_HAVE_SPI5 -static int spi5_interrupt(int irq, void *context) -{ - return spi_interrupt(&g_spi5dev); -} -#endif -#endif - /**************************************************************************** * Name: spi_lock * @@ -1546,7 +1458,7 @@ struct spi_dev_s *sam_spibus_initialize(int port) #if 0 /* Not used */ /* Attach and enable the SERCOM interrupt handler */ - ret = irq_attach(priv->irq, priv->handler); + ret = irq_attach(priv->irq, spi_interrupt, priv); if (ret < 0) { spierr("ERROR: Failed to attach interrupt: %d\n", irq); diff --git a/arch/arm/src/samdl/sam_timerisr.c b/arch/arm/src/samdl/sam_timerisr.c index 5236ee45b5b..abc61f355f0 100644 --- a/arch/arm/src/samdl/sam_timerisr.c +++ b/arch/arm/src/samdl/sam_timerisr.c @@ -95,7 +95,7 @@ * ****************************************************************************/ -static int sam_timerisr(int irq, uint32_t *regs) +static int sam_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -133,7 +133,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(SAM_IRQ_SYSTICK, (xcpt_t)sam_timerisr); + (void)irq_attach(SAM_IRQ_SYSTICK, (xcpt_t)sam_timerisr, NULL); /* Enable SysTick interrupts */ diff --git a/arch/arm/src/samv7/sam_dac.c b/arch/arm/src/samv7/sam_dac.c index 598201ce390..78a19929b54 100644 --- a/arch/arm/src/samv7/sam_dac.c +++ b/arch/arm/src/samv7/sam_dac.c @@ -109,7 +109,7 @@ struct sam_chan_s /* Interrupt handler */ -static int dac_interrupt(int irq, FAR void *context); +static int dac_interrupt(int irq, FAR void *context, FAR void *arg); /* DAC methods */ @@ -199,7 +199,7 @@ static struct sam_dac_s g_dacmodule; * ****************************************************************************/ -static int dac_interrupt(int irq, FAR void *context) +static int dac_interrupt(int irq, FAR void *context, FAR void *arg) { #ifdef CONFIG_SAMV7_DAC1 uint32_t status; @@ -569,7 +569,7 @@ static int dac_module_init(void) /* Configure interrupts */ - ret = irq_attach(SAM_IRQ_DACC, dac_interrupt); + ret = irq_attach(SAM_IRQ_DACC, dac_interrupt, NULL); if (ret < 0) { aerr("irq_attach failed: %d\n", ret); diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c index a7ea10c109d..6357758b4d3 100644 --- a/arch/arm/src/samv7/sam_emac.c +++ b/arch/arm/src/samv7/sam_emac.c @@ -2,7 +2,7 @@ * arch/arm/src/samv7/sam_emac.c * 10/100 Base-T Ethernet driver for the SAMV71. * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * This logic derives from the SAMA5 Ethernet driver which, in turn, derived @@ -431,7 +431,6 @@ struct sam_emacattr_s /* Basic hardware information */ uint32_t base; /* EMAC Register base address */ - xcpt_t handler; /* EMAC interrupt handler */ uint8_t emac; /* EMACn, n=0 or 1 */ uint8_t irq; /* EMAC interrupt number */ @@ -583,13 +582,7 @@ static void sam_txdone(struct sam_emac_s *priv, int qid); static void sam_txerr_interrupt(FAR struct sam_emac_s *priv, int qid); static void sam_interrupt_work(FAR void *arg); -static int sam_emac_interrupt(struct sam_emac_s *priv); -#ifdef CONFIG_SAMV7_EMAC0 -static int sam_emac0_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_SAMV7_EMAC1 -static int sam_emac1_interrupt(int irq, void *context); -#endif +static int sam_emac_interrupt(int irq, void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -778,7 +771,6 @@ static const struct sam_emacattr_s g_emac0_attr = /* Basic hardware information */ .base = SAM_EMAC0_BASE, - .handler = sam_emac0_interrupt, .emac = EMAC0_INTF, .irq = SAM_IRQ_EMAC0, @@ -859,7 +851,6 @@ static const struct sam_emacattr_s g_emac1_attr = /* Basic hardware information */ .base = SAM_EMAC1_BASE, - .handler = sam_emac1_interrupt, .emac = EMAC1_INTF, .irq = SAM_IRQ_EMAC1, @@ -2467,10 +2458,13 @@ static void sam_interrupt_work(FAR void *arg) * ****************************************************************************/ -static int sam_emac_interrupt(struct sam_emac_s *priv) +static int sam_emac_interrupt(int irq, void *context, FAR void *arg) { + struct sam_emac_s *priv = (struct sam_emac_s *)arg; uint32_t tsr; + DEBUGASSERT(priv != NULL); + /* Disable further Ethernet interrupts. Because Ethernet interrupts are * also disabled if the TX timeout event occurs, there can be no race * condition here. @@ -2489,6 +2483,8 @@ static int sam_emac_interrupt(struct sam_emac_s *priv) tsr = sam_getreg(priv, SAM_EMAC_TSR_OFFSET); if ((tsr & EMAC_TSR_TXCOMP) != 0) { + int delay; + /* If a TX transfer just completed, then cancel the TX timeout so * there will be do race condition between any subsequent timeout * expiration and the deferred interrupt processing. @@ -2496,13 +2492,26 @@ static int sam_emac_interrupt(struct sam_emac_s *priv) wd_cancel(priv->txtimeout); - /* Make sure that the TX poll timer is running (if it is already - * running, the following would restart it). This is necessary to - * avoid certain race conditions where the polling sequence can be - * interrupted. + /* Check if the poll timer is running. If it is not, then start it + * now. There is a race condition here: We may test the time + * remaining on the poll timer and determine that it is still running, + * but then the timer expires immiately. That should not be problem, + * however, the poll timer processing should be in the work queue and + * should execute immediately after we complete the TX poll. + * Inefficient, but not fatal. */ - (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, priv); + delay = wd_gettime(priv->txpoll); + if (delay <= 0) + { + /* The poll timer is not running .. restart it. This is necessary + * to avoid certain race conditions where the polling sequence can + * be interrupted. + */ + + (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, + 1, priv); + } } /* Cancel any pending poll work */ @@ -2515,37 +2524,6 @@ static int sam_emac_interrupt(struct sam_emac_s *priv) return OK; } -/**************************************************************************** - * Function: sam_emac0/1_interrupt - * - * Description: - * EMAC hardware interrupt handler - * - * Parameters: - * irq - Number of the IRQ that generated the interrupt - * context - Interrupt register state save info (architecture-specific) - * - * Returned Value: - * OK on success - * - * Assumptions: - * - ****************************************************************************/ - -#ifdef CONFIG_SAMV7_EMAC0 -static int sam_emac0_interrupt(int irq, void *context) -{ - return sam_emac_interrupt(&g_emac0); -} -#endif - -#ifdef CONFIG_SAMV7_EMAC1 -static int sam_emac1_interrupt(int irq, void *context) -{ - return sam_emac_interrupt(&g_emac1); -} -#endif - /**************************************************************************** * Function: sam_txtimeout_work * @@ -5037,10 +5015,11 @@ int sam_emac_initialize(int intf) * the interface is in the 'up' state. */ - ret = irq_attach(priv->attr->irq, priv->attr->handler); + ret = irq_attach(priv->attr->irq, sam_emac_interrupt, priv); if (ret < 0) { - nerr("ERROR: Failed to attach the handler to the IRQ%d\n", priv->attr->irq); + nerr("ERROR: Failed to attach the handler to the IRQ%d\n", + priv->attr->irq); goto errout_with_buffers; } diff --git a/arch/arm/src/samv7/sam_gpioirq.c b/arch/arm/src/samv7/sam_gpioirq.c index 8929d175779..78cbc4c5ed7 100644 --- a/arch/arm/src/samv7/sam_gpioirq.c +++ b/arch/arm/src/samv7/sam_gpioirq.c @@ -192,35 +192,35 @@ static int sam_gpiointerrupt(uint32_t base, int irq0, void *context) } #ifdef CONFIG_SAMV7_GPIOA_IRQ -static int sam_gpioainterrupt(int irq, void *context) +static int sam_gpioainterrupt(int irq, void *context, FAR void *arg) { return sam_gpiointerrupt(SAM_PIOA_BASE, SAM_IRQ_PA0, context); } #endif #ifdef CONFIG_SAMV7_GPIOB_IRQ -static int sam_gpiobinterrupt(int irq, void *context) +static int sam_gpiobinterrupt(int irq, void *context, FAR void *arg) { return sam_gpiointerrupt(SAM_PIOB_BASE, SAM_IRQ_PB0, context); } #endif #ifdef CONFIG_SAMV7_GPIOC_IRQ -static int sam_gpiocinterrupt(int irq, void *context) +static int sam_gpiocinterrupt(int irq, void *context, FAR void *arg) { return sam_gpiointerrupt(SAM_PIOC_BASE, SAM_IRQ_PC0, context); } #endif #ifdef CONFIG_SAMV7_GPIOD_IRQ -static int sam_gpiodinterrupt(int irq, void *context) +static int sam_gpiodinterrupt(int irq, void *context, FAR void *arg) { return sam_gpiointerrupt(SAM_PIOD_BASE, SAM_IRQ_PD0, context); } #endif #ifdef CONFIG_SAMV7_GPIOE_IRQ -static int sam_gpioeinterrupt(int irq, void *context) +static int sam_gpioeinterrupt(int irq, void *context, FAR void *arg) { return sam_gpiointerrupt(SAM_PIOE_BASE, SAM_IRQ_PE0, context); } @@ -255,7 +255,7 @@ void sam_gpioirqinitialize(void) /* Attach and enable the GPIOA IRQ */ - (void)irq_attach(SAM_IRQ_PIOA, sam_gpioainterrupt); + (void)irq_attach(SAM_IRQ_PIOA, sam_gpioainterrupt, NULL); up_enable_irq(SAM_IRQ_PIOA); #endif @@ -273,7 +273,7 @@ void sam_gpioirqinitialize(void) /* Attach and enable the GPIOB IRQ */ - (void)irq_attach(SAM_IRQ_PIOB, sam_gpiobinterrupt); + (void)irq_attach(SAM_IRQ_PIOB, sam_gpiobinterrupt, NULL); up_enable_irq(SAM_IRQ_PIOB); #endif @@ -291,7 +291,7 @@ void sam_gpioirqinitialize(void) /* Attach and enable the GPIOC IRQ */ - (void)irq_attach(SAM_IRQ_PIOC, sam_gpiocinterrupt); + (void)irq_attach(SAM_IRQ_PIOC, sam_gpiocinterrupt, NULL); up_enable_irq(SAM_IRQ_PIOC); #endif @@ -309,7 +309,7 @@ void sam_gpioirqinitialize(void) /* Attach and enable the GPIOC IRQ */ - (void)irq_attach(SAM_IRQ_PIOD, sam_gpiodinterrupt); + (void)irq_attach(SAM_IRQ_PIOD, sam_gpiodinterrupt, NULL); up_enable_irq(SAM_IRQ_PIOD); #endif @@ -327,7 +327,7 @@ void sam_gpioirqinitialize(void) /* Attach and enable the GPIOE IRQ */ - (void)irq_attach(SAM_IRQ_PIOE, sam_gpioeinterrupt); + (void)irq_attach(SAM_IRQ_PIOE, sam_gpioeinterrupt, NULL); up_enable_irq(SAM_IRQ_PIOE); #endif } diff --git a/arch/arm/src/samv7/sam_hsmci.c b/arch/arm/src/samv7/sam_hsmci.c index 3fe5a7dbff3..a83a51ecc0b 100644 --- a/arch/arm/src/samv7/sam_hsmci.c +++ b/arch/arm/src/samv7/sam_hsmci.c @@ -472,13 +472,7 @@ static void sam_notransfer(struct sam_dev_s *priv); /* Interrupt Handling *******************************************************/ -static int sam_hsmci_interrupt(struct sam_dev_s *priv); -#ifdef CONFIG_SAMV7_HSMCI0 -static int sam_hsmci0_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_SAMV7_HSMCI1 -static int sam_hsmci1_interrupt(int irq, void *context); -#endif +static int sam_hsmci_interrupt(int irq, void *context, void *arg); /* SDIO interface methods ***************************************************/ @@ -1437,20 +1431,22 @@ static void sam_notransfer(struct sam_dev_s *priv) * HSMCI interrupt handler * * Input Parameters: - * irq - IRQ number of the interrupts - * context - Saved machine context at the time of the interrupt + * Standard interrupt handler arguments. * * Returned Value: * None * ****************************************************************************/ -static int sam_hsmci_interrupt(struct sam_dev_s *priv) +static int sam_hsmci_interrupt(int irq, void *context, void *arg) { + struct sam_dev_s *priv = (struct sam_dev_s *)arg; uint32_t sr; uint32_t enabled; uint32_t pending; + DEBUGASSERT(priv != NULL); + /* Loop while there are pending interrupts. */ for (; ; ) @@ -1643,35 +1639,6 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv) return OK; } -/**************************************************************************** - * Name: sam_hsmci0_interrupt, sam_hsmci1_interrupt, and sam_hsmci2_interrupt - * - * Description: - * HSMCI interrupt handler - * - * Input Parameters: - * irq - IRQ number of the interrupts - * context - Saved machine context at the time of the interrupt - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SAMV7_HSMCI0 -static int sam_hsmci0_interrupt(int irq, void *context) -{ - return sam_hsmci_interrupt(&g_hsmci0); -} -#endif - -#ifdef CONFIG_SAMV7_HSMCI1 -static int sam_hsmci1_interrupt(int irq, void *context) -{ - return sam_hsmci_interrupt(&g_hsmci1); -} -#endif - /**************************************************************************** * SDIO Interface Methods ****************************************************************************/ @@ -1922,7 +1889,6 @@ static void sam_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) static int sam_attach(FAR struct sdio_dev_s *dev) { struct sam_dev_s *priv = (struct sam_dev_s *)dev; - xcpt_t handler; int irq; int ret; @@ -1931,16 +1897,14 @@ static int sam_attach(FAR struct sdio_dev_s *dev) #ifdef CONFIG_SAMV7_HSMCI0 if (priv->hsmci == 0) { - handler = sam_hsmci0_interrupt; - irq = SAM_IRQ_HSMCI0; + irq = SAM_IRQ_HSMCI0; } else #endif #ifdef CONFIG_SAMV7_HSMCI1 if (priv->hsmci == 1) { - handler = sam_hsmci1_interrupt; - irq = SAM_IRQ_HSMCI1; + irq = SAM_IRQ_HSMCI1; } else #endif @@ -1951,7 +1915,7 @@ static int sam_attach(FAR struct sdio_dev_s *dev) /* Attach the HSMCI interrupt handler */ - ret = irq_attach(irq, handler); + ret = irq_attach(irq, sam_hsmci_interrupt, priv); if (ret == OK) { diff --git a/arch/arm/src/samv7/sam_irq.c b/arch/arm/src/samv7/sam_irq.c index 08537f65970..f2e44893298 100644 --- a/arch/arm/src/samv7/sam_irq.c +++ b/arch/arm/src/samv7/sam_irq.c @@ -174,7 +174,7 @@ static void sam_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int sam_nmi(int irq, FAR void *context) +static int sam_nmi(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -182,7 +182,7 @@ static int sam_nmi(int irq, FAR void *context) return 0; } -static int sam_busfault(int irq, FAR void *context) +static int sam_busfault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); @@ -190,7 +190,7 @@ static int sam_busfault(int irq, FAR void *context) return 0; } -static int sam_usagefault(int irq, FAR void *context) +static int sam_usagefault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); @@ -198,7 +198,7 @@ static int sam_usagefault(int irq, FAR void *context) return 0; } -static int sam_pendsv(int irq, FAR void *context) +static int sam_pendsv(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -206,7 +206,7 @@ static int sam_pendsv(int irq, FAR void *context) return 0; } -static int sam_dbgmonitor(int irq, FAR void *context) +static int sam_dbgmonitor(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -214,7 +214,7 @@ static int sam_dbgmonitor(int irq, FAR void *context) return 0; } -static int sam_reserved(int irq, FAR void *context) +static int sam_reserved(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -435,8 +435,8 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(SAM_IRQ_SVCALL, up_svcall); - irq_attach(SAM_IRQ_HARDFAULT, up_hardfault); + irq_attach(SAM_IRQ_SVCALL, up_svcall, NULL); + irq_attach(SAM_IRQ_HARDFAULT, up_hardfault, NULL); /* Set the priority of the SVCall interrupt */ @@ -452,22 +452,22 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(SAM_IRQ_MEMFAULT, up_memfault); + irq_attach(SAM_IRQ_MEMFAULT, up_memfault, NULL); up_enable_irq(SAM_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(SAM_IRQ_NMI, sam_nmi); + irq_attach(SAM_IRQ_NMI, sam_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(SAM_IRQ_MEMFAULT, up_memfault); + irq_attach(SAM_IRQ_MEMFAULT, up_memfault, NULL); #endif - irq_attach(SAM_IRQ_BUSFAULT, sam_busfault); - irq_attach(SAM_IRQ_USAGEFAULT, sam_usagefault); - irq_attach(SAM_IRQ_PENDSV, sam_pendsv); - irq_attach(SAM_IRQ_DBGMONITOR, sam_dbgmonitor); - irq_attach(SAM_IRQ_RESERVED, sam_reserved); + irq_attach(SAM_IRQ_BUSFAULT, sam_busfault, NULL); + irq_attach(SAM_IRQ_USAGEFAULT, sam_usagefault, NULL); + irq_attach(SAM_IRQ_PENDSV, sam_pendsv, NULL); + irq_attach(SAM_IRQ_DBGMONITOR, sam_dbgmonitor, NULL); + irq_attach(SAM_IRQ_RESERVED, sam_reserved, NULL); #endif sam_dumpnvic("initial", SAM_IRQ_NIRQS); diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c index 683463be9e6..7d16f0898df 100644 --- a/arch/arm/src/samv7/sam_mcan.c +++ b/arch/arm/src/samv7/sam_mcan.c @@ -841,7 +841,6 @@ struct sam_config_s { gpio_pinset_t rxpinset; /* RX pin configuration */ gpio_pinset_t txpinset; /* TX pin configuration */ - xcpt_t handler; /* MCAN common interrupt handler */ uintptr_t base; /* Base address of the MCAN registers */ uint32_t baud; /* Configured baud */ uint32_t btp; /* Bit timing/prescaler register setting */ @@ -973,13 +972,7 @@ static void mcan_error(FAR struct can_dev_s *dev, uint32_t status, #endif static void mcan_receive(FAR struct can_dev_s *dev, FAR uint32_t *rxbuffer, unsigned long nwords); -static void mcan_interrupt(FAR struct can_dev_s *dev); -#ifdef CONFIG_SAMV7_MCAN0 -static int mcan0_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_SAMV7_MCAN1 -static int mcan1_interrupt(int irq, void *context); -#endif +static int mcan_interrupt(int irq, void *context, FAR void *arg); /* Hardware initialization */ @@ -1019,7 +1012,6 @@ static const struct sam_config_s g_mcan0const = { .rxpinset = GPIO_MCAN0_RX, .txpinset = GPIO_MCAN0_TX, - .handler = mcan0_interrupt, .base = SAM_MCAN0_BASE, .baud = CONFIG_SAMV7_MCAN0_BITRATE, .btp = MCAN_BTP_BRP(MCAN0_BRP) | MCAN_BTP_TSEG1(MCAN0_TSEG1) | @@ -1096,7 +1088,6 @@ static const struct sam_config_s g_mcan1const = { .rxpinset = GPIO_MCAN1_RX, .txpinset = GPIO_MCAN1_TX, - .handler = mcan1_interrupt, .base = SAM_MCAN1_BASE, .baud = CONFIG_SAMV7_MCAN1_BITRATE, .btp = MCAN_BTP_BRP(MCAN1_BRP) | MCAN_BTP_TSEG1(MCAN1_TSEG1) | @@ -2340,7 +2331,7 @@ static int mcan_setup(FAR struct can_dev_s *dev) /* Attach the MCAN interrupt handlers */ - ret = irq_attach(config->irq0, config->handler); + ret = irq_attach(config->irq0, mcan_interrupt, dev); if (ret < 0) { canerr("ERROR: Failed to attach MCAN%d line 0 IRQ (%d)", @@ -2348,7 +2339,7 @@ static int mcan_setup(FAR struct can_dev_s *dev) return ret; } - ret = irq_attach(config->irq1, config->handler); + ret = irq_attach(config->irq1, mcan_interrupt, dev); if (ret < 0) { canerr("ERROR: Failed to attach MCAN%d line 1 IRQ (%d)", @@ -3378,9 +3369,10 @@ static void mcan_receive(FAR struct can_dev_s *dev, FAR uint32_t *rxbuffer, * ****************************************************************************/ -static void mcan_interrupt(FAR struct can_dev_s *dev) +static int mcan_interrupt(int irq, void *context, FAR void *arg) { - FAR struct sam_mcan_s *priv = dev->cd_priv; + FAR struct can_dev_s *dev = (FAR struct can_dev_s *)arg; + FAR struct sam_mcan_s *priv; FAR const struct sam_config_s *config; uint32_t ir; uint32_t ie; @@ -3390,6 +3382,8 @@ static void mcan_interrupt(FAR struct can_dev_s *dev) unsigned int ndx; bool handled; + DEBUGASSERT(dev != NULL); + priv = dev->cd_priv; DEBUGASSERT(priv && priv->config); config = priv->config; @@ -3675,52 +3669,6 @@ static void mcan_interrupt(FAR struct can_dev_s *dev) while (handled); } -/**************************************************************************** - * Name: mcan0_interrupt - * - * Description: - * MCAN0 interrupt handler - * - * Input Parameters: - * irq - The IRQ number of the interrupt. - * context - The register state save array at the time of the interrupt. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_SAMV7_MCAN0 -static int mcan0_interrupt(int irq, void *context) -{ - mcan_interrupt(&g_mcan0dev); - return OK; -} -#endif - -/**************************************************************************** - * Name: mcan1_interrupt - * - * Description: - * MCAN1 interrupt handler - * - * Input Parameters: - * irq - The IRQ number of the interrupt. - * context - The register state save array at the time of the interrupt. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_SAMV7_MCAN1 -static int mcan1_interrupt(int irq, void *context) -{ - mcan_interrupt(&g_mcan1dev); - return OK; -} -#endif - /**************************************************************************** * Name: mcan_hw_initialize * diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index a37245c7e6e..3e51bee7515 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -270,7 +270,7 @@ static void qspi_memcpy(uint8_t *dest, const uint8_t *src, #ifdef QSPI_USE_INTERRUPTS static int qspi_interrupt(struct sam_qspidev_s *priv); #ifdef CONFIG_SAMV7_QSPI -static int qspi0_interrupt(int irq, void *context); +static int qspi0_interrupt(int irq, void *context, FAR void *arg); #endif #endif @@ -1811,7 +1811,7 @@ struct qspi_dev_s *sam_qspi_initialize(int intf) #ifdef QSPI_USE_INTERRUPTS /* Attach the interrupt handler */ - ret = irq_attach(priv->irq, priv->handler); + ret = irq_attach(priv->irq, priv->handler, NULL); if (ret < 0) { spierr("ERROR: Failed to attach irq %d\n", priv->irq); diff --git a/arch/arm/src/samv7/sam_rswdt.c b/arch/arm/src/samv7/sam_rswdt.c index 980ecd5b037..6d5add03a23 100644 --- a/arch/arm/src/samv7/sam_rswdt.c +++ b/arch/arm/src/samv7/sam_rswdt.c @@ -120,7 +120,7 @@ static void sam_putreg(uint32_t regval, uintptr_t regaddr); /* Interrupt hanlding *******************************************************/ #ifdef CONFIG_SAMV7_RSWDT_INTERRUPT -static int sam_interrupt(int irq, FAR void *context); +static int sam_interrupt(int irq, FAR void *context, FAR void *arg); #endif /* "Lower half" driver methods **********************************************/ @@ -260,7 +260,7 @@ static void sam_putreg(uint32_t regval, uintptr_t regaddr) ****************************************************************************/ #ifdef CONFIG_SAMV7_RSWDT_INTERRUPT -static int sam_interrupt(int irq, FAR void *context) +static int sam_interrupt(int irq, FAR void *context, FAR void *arg) { FAR struct sam_lowerhalf_s *priv = &g_wdtdev; @@ -684,7 +684,7 @@ int sam_rswdt_initialize(void) #ifdef CONFIG_SAMV7_RSWDT_INTERRUPT /* Attach our RSWDT interrupt handler (But don't enable it yet) */ - (void)irq_attach(SAM_IRQ_RSWDT, sam_interrupt); + (void)irq_attach(SAM_IRQ_RSWDT, sam_interrupt, NULL); #endif /* Register the watchdog driver as /dev/rswdt */ diff --git a/arch/arm/src/samv7/sam_serial.c b/arch/arm/src/samv7/sam_serial.c index 6744a72ce2e..ad81eb94765 100644 --- a/arch/arm/src/samv7/sam_serial.c +++ b/arch/arm/src/samv7/sam_serial.c @@ -333,7 +333,6 @@ struct sam_dev_s { const uint32_t usartbase; /* Base address of USART registers */ - xcpt_t handler; /* Interrupt handler */ uint32_t baud; /* Configured baud */ uint32_t sr; /* Saved status bits */ uint8_t irq; /* IRQ associated with this USART */ @@ -353,31 +352,7 @@ static int sam_setup(struct uart_dev_s *dev); static void sam_shutdown(struct uart_dev_s *dev); static int sam_attach(struct uart_dev_s *dev); static void sam_detach(struct uart_dev_s *dev); -static int sam_interrupt(struct uart_dev_s *dev); -#ifdef CONFIG_SAMV7_UART0 -static int sam_uart0_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_SAMV7_UART1 -static int sam_uart1_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_SAMV7_UART2 -static int sam_uart2_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_SAMV7_UART3 -static int sam_uart3_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_SAMV7_UART4 -static int sam_uart4_interrupt(int irq, void *context); -#endif -#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_SERIALDRIVER) -static int sam_usart0_interrupt(int irq, void *context); -#endif -#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_SERIALDRIVER) -static int sam_usart1_interrupt(int irq, void *context); -#endif -#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_SERIALDRIVER) -static int sam_usart2_interrupt(int irq, void *context); -#endif +static int sam_interrupt(int irq, void *context, FAR void *arg); static int sam_ioctl(struct file *filep, int cmd, unsigned long arg); static int sam_receive(struct uart_dev_s *dev, uint32_t *status); static void sam_rxint(struct uart_dev_s *dev, bool enable); @@ -451,7 +426,6 @@ static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; static struct sam_dev_s g_uart0priv = { .usartbase = SAM_UART0_BASE, - .handler = sam_uart0_interrupt, .baud = CONFIG_UART0_BAUD, .irq = SAM_IRQ_UART0, .parity = CONFIG_UART0_PARITY, @@ -482,7 +456,6 @@ static uart_dev_t g_uart0port = static struct sam_dev_s g_uart1priv = { .usartbase = SAM_UART1_BASE, - .handler = sam_uart1_interrupt, .baud = CONFIG_UART1_BAUD, .irq = SAM_IRQ_UART1, .parity = CONFIG_UART1_PARITY, @@ -513,7 +486,6 @@ static uart_dev_t g_uart1port = static struct sam_dev_s g_uart2priv = { .usartbase = SAM_UART2_BASE, - .handler = sam_uart2_interrupt, .baud = CONFIG_UART2_BAUD, .irq = SAM_IRQ_UART2, .parity = CONFIG_UART2_PARITY, @@ -544,7 +516,6 @@ static uart_dev_t g_uart2port = static struct sam_dev_s g_uart3priv = { .usartbase = SAM_UART3_BASE, - .handler = sam_uart3_interrupt, .baud = CONFIG_UART3_BAUD, .irq = SAM_IRQ_UART3, .parity = CONFIG_UART3_PARITY, @@ -575,7 +546,6 @@ static uart_dev_t g_uart3port = static struct sam_dev_s g_uart4priv = { .usartbase = SAM_UART4_BASE, - .handler = sam_uart4_interrupt, .baud = CONFIG_UART4_BAUD, .irq = SAM_IRQ_UART4, .parity = CONFIG_UART4_PARITY, @@ -606,7 +576,6 @@ static uart_dev_t g_uart4port = static struct sam_dev_s g_usart0priv = { .usartbase = SAM_USART0_BASE, - .handler = sam_usart0_interrupt, .baud = CONFIG_USART0_BAUD, .irq = SAM_IRQ_USART0, .parity = CONFIG_USART0_PARITY, @@ -640,7 +609,6 @@ static uart_dev_t g_usart0port = static struct sam_dev_s g_usart1priv = { .usartbase = SAM_USART1_BASE, - .handler = sam_usart1_interrupt, .baud = CONFIG_USART1_BAUD, .irq = SAM_IRQ_USART1, .parity = CONFIG_USART1_PARITY, @@ -674,7 +642,6 @@ static uart_dev_t g_usart1port = static struct sam_dev_s g_usart2priv = { .usartbase = SAM_USART2_BASE, - .handler = sam_usart2_interrupt, .baud = CONFIG_USART2_BAUD, .irq = SAM_IRQ_USART2, .parity = CONFIG_USART2_PARITY, @@ -973,7 +940,7 @@ static int sam_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, priv->handler); + ret = irq_attach(priv->irq, sam_interrupt, dev); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -1014,15 +981,16 @@ static void sam_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int sam_interrupt(struct uart_dev_s *dev) +static int sam_interrupt(int irq, void *context, FAR void *arg) { + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct sam_dev_s *priv; - uint32_t pending; - uint32_t imr; - int passes; - bool handled; + uint32_t pending; + uint32_t imr; + int passes; + bool handled; - DEBUGASSERT(dev && dev->priv); + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct sam_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, until we have @@ -1068,72 +1036,6 @@ static int sam_interrupt(struct uart_dev_s *dev) return OK; } -/**************************************************************************** - * Name: sam_uart[n]_interrupt - * - * Description: - * UART interrupt handlers - * - ****************************************************************************/ - -#ifdef CONFIG_SAMV7_UART0 -static int sam_uart0_interrupt(int irq, void *context) -{ - return sam_interrupt(&g_uart0port); -} -#endif -#ifdef CONFIG_SAMV7_UART1 -static int sam_uart1_interrupt(int irq, void *context) -{ - return sam_interrupt(&g_uart1port); -} -#endif -#ifdef CONFIG_SAMV7_UART2 -static int sam_uart2_interrupt(int irq, void *context) -{ - return sam_interrupt(&g_uart2port); -} -#endif -#ifdef CONFIG_SAMV7_UART3 -static int sam_uart3_interrupt(int irq, void *context) -{ - return sam_interrupt(&g_uart3port); -} -#endif -#ifdef CONFIG_SAMV7_UART4 -static int sam_uart4_interrupt(int irq, void *context) -{ - return sam_interrupt(&g_uart4port); -} -#endif - -/**************************************************************************** - * Name: sam_usart[n]_interrupt - * - * Description: - * USART interrupt handlers - * - ****************************************************************************/ - -#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_SERIALDRIVER) -static int sam_usart0_interrupt(int irq, void *context) -{ - return sam_interrupt(&g_usart0port); -} -#endif -#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_SERIALDRIVER) -static int sam_usart1_interrupt(int irq, void *context) -{ - return sam_interrupt(&g_usart1port); -} -#endif -#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_SERIALDRIVER) -static int sam_usart2_interrupt(int irq, void *context) -{ - return sam_interrupt(&g_usart2port); -} -#endif - /**************************************************************************** * Name: sam_ioctl * diff --git a/arch/arm/src/samv7/sam_spi_slave.c b/arch/arm/src/samv7/sam_spi_slave.c index d2856cd2e99..6b68769ab87 100644 --- a/arch/arm/src/samv7/sam_spi_slave.c +++ b/arch/arm/src/samv7/sam_spi_slave.c @@ -146,13 +146,7 @@ static void spi_semtake(struct sam_spidev_s *priv); /* Interrupt Handling */ -static int spi_interrupt(struct sam_spidev_s *priv); -#ifdef CONFIG_SAMV7_SPI0_SLAVE -static int spi0_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_SAMV7_SPI1_SLAVE -static int spi1_interrupt(int irq, void *context); -#endif +static int spi_interrupt(int irq, void *context, FAR void *arg); /* SPI Helpers */ @@ -395,13 +389,16 @@ static void spi_semtake(struct sam_spidev_s *priv) * ****************************************************************************/ -static int spi_interrupt(struct sam_spidev_s *priv) +static int spi_interrupt(int irq, void *context, FAR void *arg) { + struct sam_spidev_s *priv = (struct sam_spidev_s *)arg; uint32_t sr; uint32_t imr; uint32_t pending; uint32_t regval; + DEBUGASSERT(priv != NULL); + /* We loop because the TDRE interrupt will probably immediately follow the * RDRF interrupt and we might be able to catch it in this handler * execution. @@ -553,48 +550,6 @@ static int spi_interrupt(struct sam_spidev_s *priv) return OK; } -/**************************************************************************** - * Name: spi0_interrupt - * - * Description: - * SPI0 interrupt handler - * - * Input Parameters: - * Standard interrupt input parameters - * - * Returned Value: - * Standard interrupt return value. - * - ****************************************************************************/ - -#ifdef CONFIG_SAMV7_SPI0_SLAVE -static int spi0_interrupt(int irq, void *context) -{ - return spi_interrupt(&g_spi0_sctrlr); -} -#endif - -/**************************************************************************** - * Name: spi1_interrupt - * - * Description: - * SPI1 interrupt handler - * - * Input Parameters: - * Standard interrupt input parameters - * - * Returned Value: - * Standard interrupt return value. - * - ****************************************************************************/ - -#ifdef CONFIG_SAMV7_SPI1_SLAVE -static int spi1_interrupt(int irq, void *context) -{ - return spi_interrupt(&g_spi1_sctrlr); -} -#endif - /**************************************************************************** * Name: spi_dequeue * @@ -1177,9 +1132,8 @@ struct spi_sctrlr_s *sam_spi_slave_initialize(int port) { /* Set the SPI0 register base address and interrupt information */ - priv->base = SAM_SPI0_BASE, - priv->irq = SAM_IRQ_SPI0; - priv->handler = spi0_interrupt; + priv->base = SAM_SPI0_BASE, + priv->irq = SAM_IRQ_SPI0; /* Enable peripheral clocking to SPI0 */ @@ -1200,9 +1154,8 @@ struct spi_sctrlr_s *sam_spi_slave_initialize(int port) { /* Set the SPI1 register base address and interrupt information */ - priv->base = SAM_SPI1_BASE, - priv->irq = SAM_IRQ_SPI1; - priv->handler = spi1_interrupt; + priv->base = SAM_SPI1_BASE, + priv->irq = SAM_IRQ_SPI1; /* Enable peripheral clocking to SPI1 */ @@ -1255,7 +1208,7 @@ struct spi_sctrlr_s *sam_spi_slave_initialize(int port) /* Attach and enable interrupts at the NVIC */ - DEBUGVERIFY(irq_attach(priv->irq, priv->handler)); + DEBUGVERIFY(irq_attach(priv->irq, spi_interrupt, priv)); up_enable_irq(priv->irq); spi_dumpregs(priv, "After initialization"); diff --git a/arch/arm/src/samv7/sam_tc.c b/arch/arm/src/samv7/sam_tc.c index 691366af8f8..4b9303fd534 100644 --- a/arch/arm/src/samv7/sam_tc.c +++ b/arch/arm/src/samv7/sam_tc.c @@ -186,27 +186,27 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, static int sam_tc_interrupt(struct sam_tc_s *tc, struct sam_chan_s *chan); #ifdef CONFIG_SAMV7_TC0 -static int sam_tc0_interrupt(int irq, void *context); -static int sam_tc1_interrupt(int irq, void *context); -static int sam_tc2_interrupt(int irq, void *context); +static int sam_tc0_interrupt(int irq, void *context, FAR void *arg); +static int sam_tc1_interrupt(int irq, void *context, FAR void *arg); +static int sam_tc2_interrupt(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_SAMV7_TC1 -static int sam_tc3_interrupt(int irq, void *context); -static int sam_tc4_interrupt(int irq, void *context); -static int sam_tc5_interrupt(int irq, void *context); +static int sam_tc3_interrupt(int irq, void *context, FAR void *arg); +static int sam_tc4_interrupt(int irq, void *context, FAR void *arg); +static int sam_tc5_interrupt(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_SAMV7_TC2 -static int sam_tc6_interrupt(int irq, void *context); -static int sam_tc7_interrupt(int irq, void *context); -static int sam_tc8_interrupt(int irq, void *context); +static int sam_tc6_interrupt(int irq, void *context, FAR void *arg); +static int sam_tc7_interrupt(int irq, void *context, FAR void *arg); +static int sam_tc8_interrupt(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_SAMV7_TC3 -static int sam_tc9_interrupt(int irq, void *context); -static int sam_tc10_interrupt(int irq, void *context); -static int sam_tc11_interrupt(int irq, void *context); +static int sam_tc9_interrupt(int irq, void *context, FAR void *arg); +static int sam_tc10_interrupt(int irq, void *context, FAR void *arg); +static int sam_tc11_interrupt(int irq, void *context, FAR void *arg); #endif /* Initialization ***********************************************************/ @@ -893,68 +893,68 @@ static int sam_tc_interrupt(struct sam_tc_s *tc, struct sam_chan_s *chan) ****************************************************************************/ #ifdef CONFIG_SAMV7_TC0 -static int sam_tc0_interrupt(int irq, void *context) +static int sam_tc0_interrupt(int irq, void *context, FAR void *arg) { return sam_tc_interrupt(&g_tc012, &g_tc012.channel[0]); } -static int sam_tc1_interrupt(int irq, void *context) +static int sam_tc1_interrupt(int irq, void *context, FAR void *arg) { return sam_tc_interrupt(&g_tc012, &g_tc012.channel[1]); } -static int sam_tc2_interrupt(int irq, void *context) +static int sam_tc2_interrupt(int irq, void *context, FAR void *arg) { return sam_tc_interrupt(&g_tc012, &g_tc012.channel[2]); } #endif #ifdef CONFIG_SAMV7_TC1 -static int sam_tc3_interrupt(int irq, void *context) +static int sam_tc3_interrupt(int irq, void *context, FAR void *arg) { return sam_tc_interrupt(&g_tc345, &g_tc345.channel[0]); } -static int sam_tc4_interrupt(int irq, void *context) +static int sam_tc4_interrupt(int irq, void *context, FAR void *arg) { return sam_tc_interrupt(&g_tc345, &g_tc345.channel[1]); } -static int sam_tc5_interrupt(int irq, void *context) +static int sam_tc5_interrupt(int irq, void *context, FAR void *arg) { return sam_tc_interrupt(&g_tc345, &g_tc345.channel[2]); } #endif #ifdef CONFIG_SAMV7_TC2 -static int sam_tc6_interrupt(int irq, void *context) +static int sam_tc6_interrupt(int irq, void *context, FAR void *arg) { return sam_tc_interrupt(&g_tc678, &g_tc678.channel[0]); } -static int sam_tc7_interrupt(int irq, void *context) +static int sam_tc7_interrupt(int irq, void *context, FAR void *arg) { return sam_tc_interrupt(&g_tc678, &g_tc678.channel[1]); } -static int sam_tc8_interrupt(int irq, void *context) +static int sam_tc8_interrupt(int irq, void *context, FAR void *arg) { return sam_tc_interrupt(&g_tc678, &g_tc678.channel[2]); } #endif #ifdef CONFIG_SAMV7_TC3 -static int sam_tc9_interrupt(int irq, void *context) +static int sam_tc9_interrupt(int irq, void *context, FAR void *arg) { return sam_tc_interrupt(&g_tc901, &g_tc901.channel[0]); } -static int sam_tc10_interrupt(int irq, void *context) +static int sam_tc10_interrupt(int irq, void *context, FAR void *arg) { return sam_tc_interrupt(&g_tc901, &g_tc901.channel[1]); } -static int sam_tc11_interrupt(int irq, void *context) +static int sam_tc11_interrupt(int irq, void *context, FAR void *arg) { return sam_tc_interrupt(&g_tc901, &g_tc901.channel[2]); } @@ -1279,7 +1279,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel) /* Attach the timer interrupt handler and enable the timer interrupts */ - (void)irq_attach(chconfig->irq, chconfig->handler); + (void)irq_attach(chconfig->irq, chconfig->handler, NULL); up_enable_irq(chconfig->irq); /* Mark the channel "inuse" */ diff --git a/arch/arm/src/samv7/sam_timerisr.c b/arch/arm/src/samv7/sam_timerisr.c index c2c30ea0afe..751878d9843 100644 --- a/arch/arm/src/samv7/sam_timerisr.c +++ b/arch/arm/src/samv7/sam_timerisr.c @@ -98,7 +98,7 @@ * ****************************************************************************/ -static int sam_timerisr(int irq, uint32_t *regs) +static int sam_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -130,7 +130,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(SAM_IRQ_SYSTICK, (xcpt_t)sam_timerisr); + (void)irq_attach(SAM_IRQ_SYSTICK, (xcpt_t)sam_timerisr, NULL); /* Enable SysTick interrupts (no divide-by-8) */ diff --git a/arch/arm/src/samv7/sam_trng.c b/arch/arm/src/samv7/sam_trng.c index 6fee91e850c..e8eae34f997 100644 --- a/arch/arm/src/samv7/sam_trng.c +++ b/arch/arm/src/samv7/sam_trng.c @@ -72,7 +72,7 @@ /* Interrupts */ -static int sam_interrupt(int irq, void *context); +static int sam_interrupt(int irq, void *context, FAR void *arg); /* Character driver methods */ @@ -128,7 +128,7 @@ static const struct file_operations g_trngops = * ****************************************************************************/ -static int sam_interrupt(int irq, void *context) +static int sam_interrupt(int irq, void *context, FAR void *arg) { uint32_t odata; @@ -372,7 +372,7 @@ static int sam_rng_initialize(void) /* Initialize the TRNG interrupt */ - ret = irq_attach(SAM_IRQ_TRNG, sam_interrupt); + ret = irq_attach(SAM_IRQ_TRNG, sam_interrupt, NULL); if (ret < 0) { ferr("ERROR: Failed to attach to IRQ%d\n", SAM_IRQ_TRNG); diff --git a/arch/arm/src/samv7/sam_twihs.c b/arch/arm/src/samv7/sam_twihs.c index bdb5523ace6..4cbd19d3965 100644 --- a/arch/arm/src/samv7/sam_twihs.c +++ b/arch/arm/src/samv7/sam_twihs.c @@ -140,7 +140,6 @@ struct twi_attr_s gpio_pinset_t sclcfg; /* TWIHS CK pin configuration (SCL in I2C-ese) */ gpio_pinset_t sdacfg; /* TWIHS D pin configuration (SDA in I2C-ese) */ uintptr_t base; /* Base address of TWIHS registers */ - xcpt_t handler; /* TWIHS interrupt handler */ }; /* State of a TWIHS bus */ @@ -199,18 +198,9 @@ static inline void twi_putrel(struct twi_dev_s *priv, unsigned int offset, /* I2C transfer helper functions */ -static int twi_wait(struct twi_dev_s *priv, unsigned int size); +static int twi_wait(struct twi_dev_s *priv, unsigned int size); static void twi_wakeup(struct twi_dev_s *priv, int result); -static int twi_interrupt(struct twi_dev_s *priv); -#ifdef CONFIG_SAMV7_TWIHS0 -static int twi0_interrupt(int irq, FAR void *context); -#endif -#ifdef CONFIG_SAMV7_TWIHS1 -static int twi1_interrupt(int irq, FAR void *context); -#endif -#ifdef CONFIG_SAMV7_TWIHS2 -static int twi2_interrupt(int irq, FAR void *context); -#endif +static int twi_interrupt(int irq, FAR void *context, FAR void *arg); static void twi_timeout(int argc, uint32_t arg, ...); static void twi_startread(struct twi_dev_s *priv, struct i2c_msg_s *msg); @@ -250,7 +240,6 @@ static const struct twi_attr_s g_twi0attr = .sclcfg = GPIO_TWIHS0_CK, .sdacfg = GPIO_TWIHS0_D, .base = SAM_TWIHS0_BASE, - .handler = twi0_interrupt, }; static struct twi_dev_s g_twi0; @@ -271,7 +260,6 @@ static const struct twi_attr_s g_twi1attr = .sclcfg = GPIO_TWIHS1_CK, .sdacfg = GPIO_TWIHS1_D, .base = SAM_TWIHS1_BASE, - .handler = twi1_interrupt, }; static struct twi_dev_s g_twi1; @@ -292,7 +280,6 @@ static const struct twi_attr_s g_twi2attr = .sclcfg = GPIO_TWIHS2_CK, .sdacfg = GPIO_TWIHS2_D, .base = SAM_TWIHS2_BASE, - .handler = twi2_interrupt, }; static struct twi_dev_s g_twi2; @@ -571,14 +558,17 @@ static void twi_wakeup(struct twi_dev_s *priv, int result) * ****************************************************************************/ -static int twi_interrupt(struct twi_dev_s *priv) +static int twi_interrupt(int irq, FAR void *context, FAR void *arg) { + struct twi_dev_s *priv = (struct twi_dev_s *)arg; struct i2c_msg_s *msg; uint32_t sr; uint32_t imr; uint32_t pending; uint32_t regval; + DEBUGASSERT(priv != NULL); + /* Retrieve masked interrupt status */ sr = twi_getrel(priv, SAM_TWIHS_SR_OFFSET); @@ -761,27 +751,6 @@ static int twi_interrupt(struct twi_dev_s *priv) return OK; } -#ifdef CONFIG_SAMV7_TWIHS0 -static int twi0_interrupt(int irq, FAR void *context) -{ - return twi_interrupt(&g_twi0); -} -#endif - -#ifdef CONFIG_SAMV7_TWIHS1 -static int twi1_interrupt(int irq, FAR void *context) -{ - return twi_interrupt(&g_twi1); -} -#endif - -#ifdef CONFIG_SAMV7_TWIHS2 -static int twi2_interrupt(int irq, FAR void *context) -{ - return twi_interrupt(&g_twi2); -} -#endif - /**************************************************************************** * Name: twi_timeout * @@ -1444,7 +1413,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus) /* Attach Interrupt Handler */ - ret = irq_attach(priv->attr->irq, priv->attr->handler); + ret = irq_attach(priv->attr->irq, twi_interrupt, priv); if (ret < 0) { ierr("ERROR: Failed to attach irq %d\n", priv->attr->irq); diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c index 1d48ca410a1..4adfa117c11 100644 --- a/arch/arm/src/samv7/sam_usbdevhs.c +++ b/arch/arm/src/samv7/sam_usbdevhs.c @@ -517,7 +517,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv); static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno); #endif static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno); -static int sam_usbhs_interrupt(int irq, void *context); +static int sam_usbhs_interrupt(int irq, void *context, FAR void *arg); /* Endpoint helpers *********************************************************/ @@ -2992,7 +2992,7 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno) * ****************************************************************************/ -static int sam_usbhs_interrupt(int irq, void *context) +static int sam_usbhs_interrupt(int irq, void *context, FAR void *arg) { /* For now there is only one USB controller, but we will always refer to * it using a pointer to make any future ports to multiple USBHS controllers @@ -4862,7 +4862,7 @@ void up_usbinitialize(void) * them when we need them later. */ - if (irq_attach(SAM_IRQ_USBHS, sam_usbhs_interrupt) != 0) + if (irq_attach(SAM_IRQ_USBHS, sam_usbhs_interrupt, NULL) != 0) { usbtrace(TRACE_DEVERROR(SAM_TRACEERR_IRQREGISTRATION), (uint16_t)SAM_IRQ_USBHS); diff --git a/arch/arm/src/samv7/sam_wdt.c b/arch/arm/src/samv7/sam_wdt.c index 850fd2288c3..e662146077e 100644 --- a/arch/arm/src/samv7/sam_wdt.c +++ b/arch/arm/src/samv7/sam_wdt.c @@ -120,7 +120,7 @@ static void sam_putreg(uint32_t regval, uintptr_t regaddr); /* Interrupt hanlding *******************************************************/ #ifdef CONFIG_SAMV7_WDT_INTERRUPT -static int sam_interrupt(int irq, FAR void *context); +static int sam_interrupt(int irq, FAR void *context, FAR void *arg); #endif /* "Lower half" driver methods **********************************************/ @@ -260,7 +260,7 @@ static void sam_putreg(uint32_t regval, uintptr_t regaddr) ****************************************************************************/ #ifdef CONFIG_SAMV7_WDT_INTERRUPT -static int sam_interrupt(int irq, FAR void *context) +static int sam_interrupt(int irq, FAR void *context, FAR void *arg) { FAR struct sam_lowerhalf_s *priv = &g_wdtdev; @@ -684,7 +684,7 @@ int sam_wdt_initialize(void) #ifdef CONFIG_SAMV7_WDT_INTERRUPT /* Attach our WDT interrupt handler (But don't enable it yet) */ - (void)irq_attach(SAM_IRQ_WDT, sam_interrupt); + (void)irq_attach(SAM_IRQ_WDT, sam_interrupt, NULL); #endif /* Register the watchdog driver as device-node configured via .config. diff --git a/arch/arm/src/samv7/sam_xdmac.c b/arch/arm/src/samv7/sam_xdmac.c index 206ecb5d0f1..b47617cafec 100644 --- a/arch/arm/src/samv7/sam_xdmac.c +++ b/arch/arm/src/samv7/sam_xdmac.c @@ -1506,7 +1506,7 @@ static void sam_dmaterminate(struct sam_xdmach_s *xdmach, int result) * ****************************************************************************/ -static int sam_xdmac_interrupt(int irq, void *context) +static int sam_xdmac_interrupt(int irq, void *context, FAR void *arg) { struct sam_xdmac_s *xdmac = &g_xdmac; struct sam_xdmach_s *xdmach; @@ -1624,7 +1624,7 @@ void weak_function up_dmainitialize(void) /* Attach DMA interrupt vector */ - (void)irq_attach(SAM_IRQ_XDMAC, sam_xdmac_interrupt); + (void)irq_attach(SAM_IRQ_XDMAC, sam_xdmac_interrupt, NULL); /* Initialize the controller */ diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 28665b6f0f4..53e1513e0b3 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -773,6 +773,60 @@ config ARCH_CHIP_STM32F303VC select STM32_HAVE_UART5 select STM32_HAVE_USBDEV +config ARCH_CHIP_STM32F334K4 + bool "STM32F334K4" + select ARCH_CORTEXM4 + select STM32_STM32F33XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F334K6 + bool "STM32F334K6" + select ARCH_CORTEXM4 + select STM32_STM32F33XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F334K8 + bool "STM32F334K8" + select ARCH_CORTEXM4 + select STM32_STM32F33XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F334C4 + bool "STM32F334C4" + select ARCH_CORTEXM4 + select STM32_STM32F33XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F334C6 + bool "STM32F334C6" + select ARCH_CORTEXM4 + select STM32_STM32F33XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F334C8 + bool "STM32F334C8" + select ARCH_CORTEXM4 + select STM32_STM32F33XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F334R4 + bool "STM32F334R4" + select ARCH_CORTEXM4 + select STM32_STM32F33XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F334R6 + bool "STM32F334R6" + select ARCH_CORTEXM4 + select STM32_STM32F33XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F334R8 + bool "STM32F334R8" + select ARCH_CORTEXM4 + select STM32_STM32F33XX + select ARCH_HAVE_FPU + config ARCH_CHIP_STM32F372C8 bool "STM32F372C8" select ARCH_CORTEXM4 @@ -1388,6 +1442,25 @@ config STM32_STM32F303 select STM32_HAVE_DAC2 select STM32_HAVE_TIM7 +config STM32_STM32F33XX + bool + default n + select STM32_HAVE_HRTIM1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP4 + select STM32_HAVE_COMP6 + select STM32_HAVE_OPAMP + select STM32_HAVE_CCM + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_USART3 + config STM32_STM32F37XX bool default n @@ -1673,6 +1746,10 @@ config STM32_HAVE_FSMC bool default n +config STM32_HAVE_HRTIM1 + bool + default n + config STM32_HAVE_LTDC bool default n @@ -1829,6 +1906,18 @@ config STM32_HAVE_CAN2 bool default n +config STM32_HAVE_COMP2 + bool + default n + +config STM32_HAVE_COMP4 + bool + default n + +config STM32_HAVE_COMP6 + bool + default n + config STM32_HAVE_DAC1 bool default n @@ -1881,6 +1970,10 @@ config STM32_HAVE_I2SPLL bool default n +config STM32_HAVE_OPAMP + bool + default n + # These are the peripheral selections proper config STM32_ADC1 @@ -1938,6 +2031,21 @@ config STM32_COMP default n depends on STM32_STM32L15XX +config STM32_COMP2 + bool "COMP2" + default n + depends on STM32_HAVE_COMP2 + +config STM32_COMP4 + bool "COMP4" + default n + depends on STM32_HAVE_COMP4 + +config STM32_COMP6 + bool "COMP6" + default n + depends on STM32_HAVE_COMP6 + config STM32_BKP bool "BKP" default n @@ -2033,6 +2141,11 @@ config STM32_HASH default n depends on STM32_STM32F207 || STM32_STM32F40XX +config STM32_HRTIM1 + bool "HRTIM1" + default n + depends on STM32_HAVE_HRTIM1 + config STM32_I2C1 bool "I2C1" default n @@ -2068,6 +2181,11 @@ config STM32_DMA2D The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation available on the STM32F429 and STM32F439 devices. +config STM32_OPAMP + bool "OPAMP" + default n + depends on STM32_HAVE_OPAMP + config STM32_OTGFS bool "OTG FS" default n @@ -6768,11 +6886,12 @@ config STM32_TIM1_QE if STM32_TIM1_QE -config STM32_TIM1_QECLKOUT - int "TIM1 output clock" - default 2800000 +config STM32_TIM1_QEPSC + int "TIM1 pulse prescaler" + default 1 ---help--- - The output clock of TIM1. + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. endif @@ -6785,11 +6904,12 @@ config STM32_TIM2_QE if STM32_TIM2_QE -config STM32_TIM2_QECLKOUT - int "TIM2 output clock" - default 2800000 +config STM32_TIM2_QEPSC + int "TIM2 pulse prescaler" + default 1 ---help--- - The output clock of TIM2. + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. endif @@ -6802,11 +6922,12 @@ config STM32_TIM3_QE if STM32_TIM3_QE -config STM32_TIM3_QECLKOUT - int "TIM3 output clock" - default 2800000 +config STM32_TIM3_QEPSC + int "TIM3 pulse prescaler" + default 1 ---help--- - The output clock of TIM3. + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. endif @@ -6819,11 +6940,12 @@ config STM32_TIM4_QE if STM32_TIM4_QE -config STM32_TIM4_QECLKOUT - int "TIM4 output clock" - default 2800000 +config STM32_TIM4_QEPSC + int "TIM4 pulse prescaler" + default 1 ---help--- - The output clock of TIM4. + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. endif @@ -6836,11 +6958,12 @@ config STM32_TIM5_QE if STM32_TIM5_QE -config STM32_TIM5_QECLKOUT - int "TIM5 output clock" - default 2800000 +config STM32_TIM5_QEPSC + int "TIM5 pulse prescaler" + default 1 ---help--- - The output clock of TIM5. + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. endif @@ -6853,11 +6976,12 @@ config STM32_TIM8_QE if STM32_TIM8_QE -config STM32_TIM8_QECLKOUT - int "TIM8 output clock" - default 2800000 +config STM32_TIM8_QEPSC + int "TIM8 pulse prescaler" + default 1 ---help--- - The output clock of TIM8. + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. endif diff --git a/arch/arm/src/stm32/chip.h b/arch/arm/src/stm32/chip.h index 4542a3885f0..64ec1db6049 100644 --- a/arch/arm/src/stm32/chip.h +++ b/arch/arm/src/stm32/chip.h @@ -127,6 +127,8 @@ #elif defined(CONFIG_STM32_STM32F30XX) # include "chip/stm32f30xxx_pinmap.h" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "chip/stm32f33xxx_pinmap.h" #elif defined(CONFIG_STM32_STM32F37XX) # include "chip/stm32f37xxx_pinmap.h" @@ -151,6 +153,8 @@ # include "chip/stm32f20xxx_vectors.h" # elif defined(CONFIG_STM32_STM32F30XX) # include "chip/stm32f30xxx_vectors.h" +# elif defined(CONFIG_STM32_STM32F33XX) +# include "chip/stm32f33xxx_vectors.h" # elif defined(CONFIG_STM32_STM32F37XX) # include "chip/stm32f37xxx_vectors.h" # elif defined(CONFIG_STM32_STM32F40XX) diff --git a/arch/arm/src/stm32/chip/stm32_dbgmcu.h b/arch/arm/src/stm32/chip/stm32_dbgmcu.h index dc22cd2e7be..af80113a737 100644 --- a/arch/arm/src/stm32/chip/stm32_dbgmcu.h +++ b/arch/arm/src/stm32/chip/stm32_dbgmcu.h @@ -53,7 +53,8 @@ #define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */ #define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */ #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) + defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F40XX) || \ + defined(CONFIG_STM32_STM32L15XX) # define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */ # define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */ #endif @@ -118,7 +119,8 @@ # define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: SMBUS timeout mode stopped when Core is halted */ # define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */ # define DBGMCU_APB1_CAN2STOP (1 << 26) /* Bit 26: CAN2 stopped when core is halted */ -#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32L15XX) +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32L15XX) # define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ # define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ # define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */ @@ -129,7 +131,7 @@ # define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */ # define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: SMBUS timeout mode stopped when Core is halted */ # define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: SMBUS timeout mode stopped when Core is halted */ -# if defined(CONFIG_STM32_STM32F30XX) +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) # define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */ # endif #endif @@ -142,7 +144,7 @@ # define DBGMCU_APB2_TIM9STOP (1 << 16) /* Bit 16: TIM9 stopped when core is halted */ # define DBGMCU_APB2_TIM10STOP (1 << 17) /* Bit 17: TIM10 stopped when core is halted */ # define DBGMCU_APB2_TIM11STOP (1 << 18) /* Bit 18: TIM11 stopped when core is halted */ -#elif defined(CONFIG_STM32_STM32F30XX) +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) # define DBGMCU_APB2_TIM1STOP (1 << 0) /* Bit 0: TIM1 stopped when core is halted */ # define DBGMCU_APB2_TIM8STOP (1 << 1) /* Bit 1: TIM8 stopped when core is halted */ # define DBGMCU_APB2_TIM15STOP (1 << 2) /* Bit 2: TIM15 stopped when core is halted */ diff --git a/arch/arm/src/stm32/chip/stm32_exti.h b/arch/arm/src/stm32/chip/stm32_exti.h index a3092ca0e42..791bed1f174 100644 --- a/arch/arm/src/stm32/chip/stm32_exti.h +++ b/arch/arm/src/stm32/chip/stm32_exti.h @@ -55,7 +55,7 @@ # define STM32_NEXTI 19 # define STM32_EXTI_MASK 0x0007ffff # endif -#elif defined(CONFIG_STM32_STM32F30XX) +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) # define STM32_NEXTI1 31 # define STM32_EXTI1_MASK 0xffffffff # define STM32_NEXTI2 4 @@ -69,7 +69,7 @@ /* Register Offsets *****************************************************************/ -#if defined(CONFIG_STM32_STM32F30XX) +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) # define STM32_EXTI1_OFFSET 0x0000 /* Offset to EXTI1 registers */ # define STM32_EXTI2_OFFSET 0x0018 /* Offset to EXTI2 registers */ #endif @@ -83,7 +83,7 @@ /* Register Addresses ***************************************************************/ -#if defined(CONFIG_STM32_STM32F30XX) +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) # define STM32_EXTI1_BASE (STM32_EXTI_BASE+STM32_EXTI1_OFFSET) # define STM32_EXTI2_BASE (STM32_EXTI_BASE+STM32_EXTI2_OFFSET) @@ -146,7 +146,8 @@ # define EXTI_RTC_TAMPER (1 << 21) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */ # define EXTI_RTC_TIMESTAMP (1 << 21) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */ # define EXTI_RTC_WAKEUP (1 << 22) /* EXTI line 22 is connected to the RTC Wakeup event */ -#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) # define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */ # define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */ # define EXTI_OTGFS_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB OTG FS Wakeup event */ @@ -193,7 +194,7 @@ /* Compatibility Definitions ********************************************************/ -#if defined(CONFIG_STM32_STM32F30XX) +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) # define STM32_NEXTI STM32_NEXTI1 # define STM32_EXTI_MASK STM32_EXTI1_MASK # define STM32_EXTI_IMR STM32_EXTI1_IMR diff --git a/arch/arm/src/stm32/chip/stm32_flash.h b/arch/arm/src/stm32/chip/stm32_flash.h index 70e6d62d976..218ba05fcf7 100644 --- a/arch/arm/src/stm32/chip/stm32_flash.h +++ b/arch/arm/src/stm32/chip/stm32_flash.h @@ -90,6 +90,10 @@ # define STM32_FLASH_NPAGES 128 # define STM32_FLASH_PAGESIZE 2048 +# elif defined(CONFIG_STM32_STM32F33XX) +# define STM32_FLASH_NPAGES 32 +# define STM32_FLASH_PAGESIZE 2048 + # elif defined(CONFIG_STM32_STM32F37XX) # define STM32_FLASH_NPAGES 128 # define STM32_FLASH_PAGESIZE 2048 @@ -212,7 +216,7 @@ #define STM32_FLASH_CR_OFFSET 0x0010 #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) + defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) # define STM32_FLASH_AR_OFFSET 0x0014 # define STM32_FLASH_OBR_OFFSET 0x001c # define STM32_FLASH_WRPR_OFFSET 0x0020 @@ -233,7 +237,7 @@ #define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) + defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) # define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET) # define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET) # define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET) @@ -267,10 +271,11 @@ # define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 111: Seven wait states */ # if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) + defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) # define FLASH_ACR_HLFCYA (1 << 3) /* Bit 3: FLASH half cycle access */ # define FLASH_ACR_PRTFBE (1 << 4) /* Bit 4: FLASH prefetch enable */ -# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) # define FLASH_ACR_PRFTBS (1 << 5) /* Bit 5: FLASH prefetch buffer status */ # endif # elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) @@ -285,7 +290,7 @@ /* Flash Status Register (SR) */ #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) + defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) # define FLASH_SR_BSY (1 << 0) /* Busy */ # define FLASH_SR_PGERR (1 << 2) /* Programming Error */ # define FLASH_SR_WRPRT_ERR (1 << 4) /* Write Protection Error */ @@ -303,7 +308,7 @@ /* Flash Control Register (CR) */ #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) + defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) # define FLASH_CR_PG (1 << 0) /* Bit 0: Program Page */ # define FLASH_CR_PER (1 << 1) /* Bit 1: Page Erase */ # define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase */ @@ -314,7 +319,8 @@ # define FLASH_CR_OPTWRE (1 << 9) /* Bit 8: Option Bytes Write Enable */ # define FLASH_CR_ERRIE (1 << 10) /* Bit 10: Error Interrupt Enable */ # define FLASH_CR_EOPIE (1 << 12) /* Bit 12: End of Program Interrupt Enable */ -# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) # define FLASH_CR_OBL_LAUNCH (1 << 13) /* Bit 13: Force option byte loading */ # endif #elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) diff --git a/arch/arm/src/stm32/chip/stm32_memorymap.h b/arch/arm/src/stm32/chip/stm32_memorymap.h index 28f6590033c..3e88405ca75 100644 --- a/arch/arm/src/stm32/chip/stm32_memorymap.h +++ b/arch/arm/src/stm32/chip/stm32_memorymap.h @@ -51,6 +51,8 @@ # include "chip/stm32f20xxx_memorymap.h" #elif defined(CONFIG_STM32_STM32F30XX) # include "chip/stm32f30xxx_memorymap.h" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "chip/stm32f33xxx_memorymap.h" #elif defined(CONFIG_STM32_STM32F37XX) # include "chip/stm32f37xxx_memorymap.h" #elif defined(CONFIG_STM32_STM32F40XX) diff --git a/arch/arm/src/stm32/chip/stm32_pwr.h b/arch/arm/src/stm32/chip/stm32_pwr.h index f2c2fdde0bf..20209ee12c5 100644 --- a/arch/arm/src/stm32/chip/stm32_pwr.h +++ b/arch/arm/src/stm32/chip/stm32_pwr.h @@ -150,7 +150,8 @@ #if defined(CONFIG_STM32_STM32F30XX) # define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */ # define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */ -#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F37XX) +#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) # define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */ # define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */ # define PWR_CSR_EWUP3 (1 << 10) /* Bit 8: Enable WKUP3 pin */ diff --git a/arch/arm/src/stm32/chip/stm32f10xxx_dma.h b/arch/arm/src/stm32/chip/stm32f10xxx_dma.h index a24c611a50a..673093189ac 100644 --- a/arch/arm/src/stm32/chip/stm32f10xxx_dma.h +++ b/arch/arm/src/stm32/chip/stm32f10xxx_dma.h @@ -520,6 +520,75 @@ # define DMACHAN_UART4_TX STM32_DMA2_CHAN5 # define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5 +#elif defined(CONFIG_STM32_STM32F33XX) + +# define DMACHAN_ADC1 STM32_DMA1_CHAN1 +# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1 +# define DMACHAN_TIM17_CH1_1 STM32_DMA1_CHAN1 +# define DMACHAN_TIM17_UP_1 STM32_DMA1_CHAN1 + +# define DMACHAN_ADC2_1 STM32_DMA1_CHAN2 +# define DMACHAN_SPI1_RX_1 STM32_DMA1_CHAN2 +# define DMACHAN_USART3_TX STM32_DMA1_CHAN2 +# define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4 +# define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2 +# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2 +# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2 +# define DMACHAN_HRTIM1_M STM32_DMA1_CHAN2 + +# define DMACHAN_SPI1_TX_1 STM32_DMA1_CHAN3 +# define DMACHAN_USART3_RX STM32_DMA1_CHAN3 +# define DMACHAN_I2C1_RX_2 STM32_DMA1_CHAN3 +# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3 +# define DMACHAN_TIM3_UP STM32_DMA1_CHAN3 +# define DMACHAN_TIM6_UP STM32_DMA1_CHAN3 +# define DMACHAN_DAC1_CH1 STM32_DMA1_CHAN3 +# define DMACHAN_DAC16_CH1_1 STM32_DMA1_CHAN3 +# define DMACHAN_DAC16_UP_1 STM32_DMA1_CHAN3 +# define DMACHAN_HRTIM1_A STM32_DMA1_CHAN3 + +# define DMACHAN_ADC2_2 STM32_DMA1_CHAN4 +# define DMACHAN_SPI1_RX_2 STM32_DMA1_CHAN4 +# define DMACHAN_USART1_TX STM32_DMA1_CHAN4 +# define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4 +# define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4 +# define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4 +# define DMACHAN_TIM1_COM STM32_DMA1_CHAN4 +# define DMACHAN_TIM7_UP STM32_DMA1_CHAN4 +# define DMACHAN_DAC2_CH2 STM32_DMA1_CHAN4 +# define DMACHAN_HRTIM1_B STM32_DMA1_CHAN4 + +# define DMACHAN_SPI1_TX_2 STM32_DMA1_CHAN5 +# define DMACHAN_USART1_RX STM32_DMA1_CHAN5 +# define DMACHAN_I2C1_RX_3 STM32_DMA1_CHAN5 +# define DMACHAN_TIM1_UP STM32_DMA1_CHAN5 +# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5 +# define DMACHAN_DAC2_CH1 STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_CH1 STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_UP STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_TRIG STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_COM STM32_DMA1_CHAN5 +# define DMACHAN_HRTIM1_C STM32_DMA1_CHAN5 + +# define DMACHAN_SPI1_RX_3 STM32_DMA1_CHAN6 +# define DMACHAN_USART2_RX STM32_DMA1_CHAN6 +# define DMACHAN_I2C1_TX_1 STM32_DMA1_CHAN6 +# define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6 +# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6 +# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6 +# define DMACHAN_TIM16_CH1_2 STM32_DMA1_CHAN6 +# define DMACHAN_TIM16_UP_2 STM32_DMA1_CHAN6 +# define DMACHAN_HRTIM1_D STM32_DMA1_CHAN6 + +# define DMACHAN_SPI1_TX_3 STM32_DMA1_CHAN7 +# define DMACHAN_USART2_TX STM32_DMA1_CHAN7 +# define DMACHAN_I2C1_RX_1 STM32_DMA1_CHAN7 +# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7 +# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7 +# define DMACHAN_TIM17_CH1_2 STM32_DMA1_CHAN7 +# define DMACHAN_TIM17_UP_2 STM32_DMA1_CHAN7 +# define DMACHAN_HRTIM1_E STM32_DMA1_CHAN7 + #elif defined(CONFIG_STM32_STM32F37XX) # define DMACHAN_ADC1 STM32_DMA1_CHAN1 diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_adc.h b/arch/arm/src/stm32/chip/stm32f33xxx_adc.h new file mode 100644 index 00000000000..e69de29bb2d diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_dac.h b/arch/arm/src/stm32/chip/stm32f33xxx_dac.h new file mode 100644 index 00000000000..5aa908f5391 --- /dev/null +++ b/arch/arm/src/stm32/chip/stm32f33xxx_dac.h @@ -0,0 +1 @@ +/* todo */ diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h b/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h new file mode 100644 index 00000000000..e69de29bb2d diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h new file mode 100644 index 00000000000..36a9f510efd --- /dev/null +++ b/arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h @@ -0,0 +1,149 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Modified for STM32F334 by Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_MEMORYMAP_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* STM32F33XXX Address Blocks *******************************************************/ + +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ + /* 0x60000000-0xdfffffff: Reserved */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ + +#define STM32_REGION_MASK 0xf0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) + +/* Code Base Addresses **************************************************************/ + +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x0000ffff: Aliased boot memory */ + /* 0x00010000-0x07ffffff: Reserved */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x0800ffff: FLASH memory */ + /* 0x08100000-0x1ffeffff: Reserved */ +#define STM32_CCMRAM_BASE 0x10000000 /* 0x10000000-0x10000fff: 4Kb CCM data RAM */ + /* 0x10001000-0x1ffeffff: Reserved */ +#define STM32_SYSMEM_BASE 0x1fffd800 /* 0x1fff0000-0x1fff7a0f: System memory */ + /* 0x1fff7a10-0x1fff7fff: Reserved */ +#define STM32_OPTION_BASE 0x1ffff800 /* 0x1fffc000-0x1fffc007: Option bytes */ + /* 0x1fffc008-0x1fffffff: Reserved */ + + +/* System Memory Addresses **********************************************************/ + +#define STM32_SYSMEM_UID 0x1ffff7ac /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x1ffff7cc /* This bitfield indicates the size of + * the device Flash memory expressed in + * Kbytes. Example: 0x040 corresponds + * to 64 Kbytes + */ + +/* Peripheral Base Addresses ********************************************************/ + +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40009fff: APB1 */ + /* 0x4000a000-0x4000ffff: Reserved */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40006bff: APB2 */ + /* 0x40016c00-0x4001ffff: Reserved */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */ + /* 0x40024400-0x4007ffff: Reserved */ +#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x480017ff: AHB2 */ + /* 0x48001800-0x4fffffff: Reserved */ +#define STM32_AHB3_BASE 0x50000000 /* 0x50000000-0x500003ff: AHB3 */ + +/* APB1 Base Addresses **************************************************************/ + +#define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff TIM2 */ +#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */ +#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */ +#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */ +#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */ +#define STM32_BKP_BASE 0x40002850 /* 0x40002850-0x400028cc BKP */ +#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */ +#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */ +#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff USART2 */ +#define STM32_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff USART3 */ +#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff I2C1 */ +#define STM32_CAN1_BASE 0x40006400 /* 0x40006400-0x400067ff bxCAN */ +#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */ +#define STM32_DAC1_BASE 0x40007400 /* 0x40007400-0x400077ff DAC1 */ +#define STM32_DAC2_BASE 0x40009800 /* 0x40009800-0x40009bff DAC2 */ + +/* APB2 Base Addresses **************************************************************/ + +#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103FF SYSCFG + COMP + OPAMP */ +#define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107FF EXTI */ +#define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff TIM1 */ +#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */ +#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */ +#define STM32_TIM15_BASE 0x40014000 /* 0x40014000-0x400143ff TIM15 */ +#define STM32_TIM16_BASE 0x40014400 /* 0x40014400-0x400147ff TIM16 */ +#define STM32_TIM17_BASE 0x40014800 /* 0x40014800-0x40014bff TIM17 */ +#define STM32_HRTIM1_BASE 0x40017400 /* 0x40017400-0x400177ff TIM19 */ + +/* AHB1 Base Addresses **************************************************************/ + +#define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */ +#define STM32_RCC_BASE 0x40021000 /* 0x40021000-0x400213ff: Reset and Clock control RCC */ +#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x400223ff: Flash memory interface */ +#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */ +#define STM32_TSC_BASE 0x40024000 /* 0x40024000-0x400243ff: TSC */ + +/* AHB2 Base Addresses **************************************************************/ + +#define STM32_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */ +#define STM32_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */ +#define STM32_GPIOC_BASE 0x48000800 /* 0x48000800-0x48000bff: GPIO Port C */ +#define STM32_GPIOD_BASE 0X48000C00 /* 0x48000c00-0x48000fff: GPIO Port D */ +#define STM32_GPIOE_BASE 0X48001000 /* 0x48001000-0x480013ff: GPIO Port E */ +#define STM32_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */ + +/* AHB3 Base Addresses **************************************************************/ + +#define STM32_ADC12_BASE 0x50000000 /* 0x50000000-0x500003ff: ADC12 */ + +/* Cortex-M4 Base Addresses *********************************************************/ +/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this + * address range + */ + +#define STM32_SCS_BASE 0xe000e000 +#define STM32_DEBUGMCU_BASE 0xe0042000 + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_opamp.h b/arch/arm/src/stm32/chip/stm32f33xxx_opamp.h new file mode 100644 index 00000000000..e69de29bb2d diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_pinmap.h b/arch/arm/src/stm32/chip/stm32f33xxx_pinmap.h new file mode 100644 index 00000000000..b5b97c88da0 --- /dev/null +++ b/arch/arm/src/stm32/chip/stm32f33xxx_pinmap.h @@ -0,0 +1,464 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32f33xxx_pinmap.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Modified for STM32F334 by Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_PINMAP_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_PINMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "stm32_gpio.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Alternate Pin Functions. All members of the STM32F33xxx family share the same + * pin multiplexing (although they may differ in the pins physically available). + * + * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. + * Drivers, however, will use the pin selection without the numeric suffix. + * Additional definitions are required in the board.h file. For example, if + * CAN1_RX connects vis PA11 on some board, then the following definitions should + * appear inthe board.h header file for that board: + * + * #define GPIO_CAN1_RX GPIO_CAN1_RX_1 + * + * The driver will then automatically configre PA11 as the CAN1 RX pin. + */ + +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as frequency, + * open-drain/push-pull, and pull-up/down! Just the basics are defined for most + * pins in this file. + */ + +/* ADC */ + +#define GPIO_ADC1_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0) +#define GPIO_ADC1_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1) +#define GPIO_ADC1_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2) +#define GPIO_ADC1_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3) +#undef GPIO_ADC1_IN5 +#define GPIO_ADC1_IN6 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0) +#define GPIO_ADC1_IN7 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1) +#define GPIO_ADC1_IN8 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2) +#define GPIO_ADC1_IN9 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3) +#undef GPIO_ADC1_IN10 +#define GPIO_ADC1_IN11 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0) +#define GPIO_ADC1_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1) +#define GPIO_ADC1_IN13 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN13) + +#define GPIO_ADC2_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4) +#define GPIO_ADC2_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) +#define GPIO_ADC2_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6) +#define GPIO_ADC2_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7) +#define GPIO_ADC2_IN5 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4) +#define GPIO_ADC2_IN6 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0) +#define GPIO_ADC2_IN7 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1) +#define GPIO_ADC2_IN8 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2) +#define GPIO_ADC2_IN9 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3) +#undef GPIO_ADC2_IN10 +#define GPIO_ADC2_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5) +#define GPIO_ADC2_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN2) +#define GPIO_ADC2_IN13 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN12) +#define GPIO_ADC2_IN14 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14) +#define GPIO_ADC2_IN15 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15) + +/* CAN */ + +#define GPIO_CAN_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) +#define GPIO_CAN_RX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#undef GPIO_CAN_RX_3 +#define GPIO_CAN_TX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12) +#define GPIO_CAN_TX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#undef GPIO_CAN_TX_3 + + +/* Comparator Outputs */ + +#define GPIO_COMP2_OUT_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN2) +#define GPIO_COMP2_OUT_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN12) +#define GPIO_COMP2_OUT_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN9) +#define GPIO_COMP4_OUT (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN1) +#define GPIO_COMP6_OUT_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN10) +#define GPIO_COMP6_OUT_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN6) + +/* Comparator Inputs non inverting*/ + +#define GPIO_COMP2_INP (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN7) +#define GPIO_COMP4_INP (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN0) +#define GPIO_COMP6_INP (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN11) + +/* Comparator Inputs inverting*/ + +#define GPIO_COMP2_INM (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN4) +#define GPIO_COMP4_INM_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN2) +#define GPIO_COMP4_INM_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN4) +#define GPIO_COMP6_INM_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN4) +#define GPIO_COMP6_INM_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN15) + + +/* DAC -" Once the DAC channelx is enabled, the corresponding GPIO pin + * (PA4 or PA5) is automatically connected to the analog converter output + * (DACy_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin + * should first be configured to analog (AIN)". + */ + +#define GPIO_DAC1_OUT1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4) +#define GPIO_DAC1_OUT2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) +#define GPIO_DAC2_OUT1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6) + +/* I2C */ + +#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN15) +#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6) +#define GPIO_I2C1_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN14) +#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7) +#define GPIO_I2C1_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9) +#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) + +/* IR */ + +#define GPIO_IR_OUT_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN13) +#define GPIO_IR_OUT_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN9) + +/* JTAG/SWD */ + +#define GPIO_JTDI (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN15) +#define GPIO_JTDO_TRACES_WO (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3) +#define GPIO_NJTRST (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SWCLK_JTCK (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14) +#define GPIO_SWDIO_JTMS (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13) + +/* MCO */ + +#define GPIO_MCO (GPIO_ALT|GPIO_AF0|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) + +/* SPI */ + +#define GPIO_SPI1_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6) +#define GPIO_SPI1_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SPI1_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_SPI1_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) +#define GPIO_SPI1_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4) +#define GPIO_SPI1_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15) +#define GPIO_SPI1_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5) +#define GPIO_SPI1_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3) + +/* Timers */ + +#define GPIO_TIM1_BKIN_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM1_BKIN_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN14) +#define GPIO_TIM1_BKIN_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM1_BKIN_4 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN12) +#define GPIO_TIM1_BKIN2_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN11) +#define GPIO_TIM1_BKIN2_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN3) +#define GPIO_TIM1_CH1IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN8) +#define GPIO_TIM1_CH1OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN8) +#define GPIO_TIM1_CH1IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN0) +#define GPIO_TIM1_CH1OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN0) +#define GPIO_TIM1_CH1N_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN13) +#define GPIO_TIM1_CH1N_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN11) +#define GPIO_TIM1_CH1N_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM1_CH1N_4 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN13) +#define GPIO_TIM1_CH2IN (GPIO_ALT|GPIO_FLOAT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TIM1_CH2N_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN12) +#define GPIO_TIM1_CH2N_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM1_CH2N_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM1_CH3IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TIM1_CH3OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TIM1_CH3IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN2) +#define GPIO_TIM1_CH3OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN2) +#define GPIO_TIM1_CH3N_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM1_CH3N_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM1_CH3N_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN0) +#define GPIO_TIM1_CH4IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN11) +#define GPIO_TIM1_CH4OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN11) +#define GPIO_TIM1_CH4IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN3) +#define GPIO_TIM1_CH4OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN3) +#define GPIO_TIM1_ETR_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN12) +#define GPIO_TIM1_ETR_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN4) + +#define GPIO_TIM2_CH1_ETR_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM2_CH1_ETR_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15) +#define GPIO_TIM2_CH1_ETR_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM2_CH2IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM2_CH2IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3) +#define GPIO_TIM2_CH2OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3) +#define GPIO_TIM2_CH3IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TIM2_CH3IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM2_CH3OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM2_CH3IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN10) +#define GPIO_TIM2_CH3OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN10) +#define GPIO_TIM2_CH4IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TIM2_CH4OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TIM2_CH4IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM2_CH4OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM2_CH4IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN11) +#define GPIO_TIM2_CH4OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN11) + +#define GPIO_TIM3_CH1IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM3_CH1OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM3_CH1IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM3_CH1OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM3_CH1IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM3_CH1OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM3_CH2IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4) +#define GPIO_TIM3_CH2OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4) +#define GPIO_TIM3_CH2IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM3_CH2OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM3_CH2IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM3_CH2OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM3_CH2IN_4 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM3_CH2OUT_4 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM3_CH3IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM3_CH3OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM3_CH3IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM3_CH3OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM3_CH4IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM3_CH4OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM3_CH4IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM3_CH4OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM3_CH4IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM3_CH4OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM3_ETR_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3) +#define GPIO_TIM3_ETR_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN2) + +#define GPIO_TIM15_BKIN (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TIM15_CH1IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM15_CH1OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM15_CH1IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM15_CH1OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM15_CH1N_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM15_CH1N_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM15_CH2IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM15_CH2OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM15_CH2IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM15_CH2OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3) + +#define GPIO_TIM16_BKIN (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM16_CH1IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN12) +#define GPIO_TIM16_CH1OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN12) +#define GPIO_TIM16_CH1IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM16_CH1OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM16_CH1IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM16_CH1OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM16_CH1IN_4 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM16_CH1OUT_4 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM16_CH1N_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN13) +#define GPIO_TIM16_CH1N_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN6) + +#define GPIO_TIM17_BKIN_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM17_BKIN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TIM17_CH1IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM17_CH1OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM17_CH1IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM17_CH1OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM17_CH1IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM17_CH1OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM17_CH1N (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN7) + +/* HRTIM */ + +#define GPIO_HRTIM1_SCOUT_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN3) +#define GPIO_HRTIM1_SCOUT_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN1) +#define GPIO_HRTIM1_SCIN_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN6) +#define GPIO_HRTIM1_SCIN_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN2) +#define GPIO_HRTIM1_CHA1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN8) +#define GPIO_HRTIM1_CHA2 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN9) +#define GPIO_HRTIM1_CHB1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN10) +#define GPIO_HRTIM1_CHB2 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN11) +#define GPIO_HRTIM1_CHC1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN12) +#define GPIO_HRTIM1_CHC2 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN13) +#define GPIO_HRTIM1_CHD1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN14) +#define GPIO_HRTIM1_CHD2 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN15) +#define GPIO_HRTIM1_CHE1 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN8) +#define GPIO_HRTIM1_CHE2 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN9) +#define GPIO_HRTIM1_FLT1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN12) +#define GPIO_HRTIM1_FLT2 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN15) +#define GPIO_HRTIM1_FLT3 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN10) +#define GPIO_HRTIM1_FLT4 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN11) +#define GPIO_HRTIM1_FLT5 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN7) +#define GPIO_HRTIM1_EEV1 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN12) +#define GPIO_HRTIM1_EEV2 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN11) +#define GPIO_HRTIM1_EEV3 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN7) +#define GPIO_HRTIM1_EEV4 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN6) +#define GPIO_HRTIM1_EEV5 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN9) +#define GPIO_HRTIM1_EEV6 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN5) +#define GPIO_HRTIM1_EEV7 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN4) +#define GPIO_HRTIM1_EEV8 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN8) +#define GPIO_HRTIM1_EEV9 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN3) +#define GPIO_HRTIM1_EEV10 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN6) + +/* OPAMP */ + +#define GPIO_OPAMP2_DIG (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN6) +#define GPIO_OPAMP2_VINM_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) +#define GPIO_OPAMP2_VINM_2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5) +#define GPIO_OPAMP2_VOUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6) +#define GPIO_OPAMP2_VINP_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7) +#define GPIO_OPAMP2_VINP_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0) +#define GPIO_OPAMP2_VINP_3 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14) + +/* TSC */ + +#define GPIO_TSC_G1_IO1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TSC_G1_IO2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TSC_G1_IO3 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TSC_G1_IO4 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TSC_G2_IO1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN4) +#define GPIO_TSC_G2_IO2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TSC_G2_IO3 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TSC_G2_IO4 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TSC_G3_IO1 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN5) +#define GPIO_TSC_G3_IO2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TSC_G3_IO3 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TSC_G3_IO4 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN2) +#define GPIO_TSC_G4_IO1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TSC_G4_IO2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TSC_G4_IO3 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN13) +#define GPIO_TSC_G4_IO4 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN14) +#define GPIO_TSC_G5_IO1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN3) +#define GPIO_TSC_G5_IO2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TSC_G5_IO3 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TSC_G5_IO4 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TSC_G6_IO1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN11) +#define GPIO_TSC_G6_IO2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN12) +#define GPIO_TSC_G6_IO3 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN13) +#define GPIO_TSC_G6_IO4 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TSC_SYNC_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN10) +#define GPIO_TSC_SYNC_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN15) +#define GPIO_TSC_SYNC_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN8) + +/* USARTs/UARTs */ + +#define GPIO_USART1_CK (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN8) +#define GPIO_USART1_CTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN11) +#define GPIO_USART1_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN12) +#define GPIO_USART1_RX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10) +#define GPIO_USART1_RX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN7) +#define GPIO_USART1_RX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN5) +#define GPIO_USART1_TX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9) +#define GPIO_USART1_TX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN6) +#define GPIO_USART1_TX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN4) + +#define GPIO_USART2_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN4) +#define GPIO_USART2_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN5) +#define GPIO_USART2_CTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN0) +#define GPIO_USART2_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN1) +#define GPIO_USART2_RX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3) +#define GPIO_USART2_RX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15) +#define GPIO_USART2_RX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_USART2_TX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2) +#define GPIO_USART2_TX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN14) +#define GPIO_USART2_TX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3) + +#define GPIO_USART3_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN12) +#define GPIO_USART3_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN12) +#define GPIO_USART3_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN13) +#define GPIO_USART3_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN13) +#define GPIO_USART3_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN14) +#define GPIO_USART3_RX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN11) +#define GPIO_USART3_RX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN11) +#define GPIO_USART3_RX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN8) +#define GPIO_USART3_TX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN10) +#define GPIO_USART3_TX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN10) +#define GPIO_USART3_TX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN9) + +/* Event Outputs */ + +#define GPIO_PA0_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN0) +#define GPIO_PA0_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN0) +#define GPIO_PA0_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN0) +#define GPIO_PA0_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN0) +#define GPIO_PA1_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN1) +#define GPIO_PA2_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN2) +#define GPIO_PA3_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN3) +#define GPIO_PA4_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN4) +#define GPIO_PA5_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN5) +#define GPIO_PA6_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN6) +#define GPIO_PA7_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN7) +#define GPIO_PA8_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN8) +#define GPIO_PA9_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN9) +#define GPIO_PA10_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN10) +#define GPIO_PA11_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN11) +#define GPIO_PA12_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN12) +#define GPIO_PA13_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN13) +#define GPIO_PA14_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN14) +#define GPIO_PA15_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN15) + +#define GPIO_PB0_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN0) +#define GPIO_PB1_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN1) +#define GPIO_PB2_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN2) +#define GPIO_PB3_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN3) +#define GPIO_PB4_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN4) +#define GPIO_PB5_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN5) +#define GPIO_PB6_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN6) +#define GPIO_PB7_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN7) +#define GPIO_PB8_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN8) +#define GPIO_PB9_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN9) +#define GPIO_PB10_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN10) +#define GPIO_PB11_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN11) +#define GPIO_PB12_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN12) +#define GPIO_PB13_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN13) +#define GPIO_PB14_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN14) +#define GPIO_PB15_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN15) + +#define GPIO_PC0_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN0) +#define GPIO_PC1_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN1) +#define GPIO_PC2_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN2) +#define GPIO_PC3_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN3) +#define GPIO_PC4_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN4) +#define GPIO_PC5_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN5) +#define GPIO_PC6_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN6) +#define GPIO_PC7_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN7) +#define GPIO_PC8_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN8) +#define GPIO_PC9_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN9) +#define GPIO_PC10_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN10) +#define GPIO_PC11_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN11) +#define GPIO_PC12_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN12) + +#define GPIO_PD2_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTD|GPIO_PIN2) + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_PINMAP_H */ diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_rcc.h b/arch/arm/src/stm32/chip/stm32f33xxx_rcc.h new file mode 100644 index 00000000000..806b22e0502 --- /dev/null +++ b/arch/arm/src/stm32/chip/stm32f33xxx_rcc.h @@ -0,0 +1,361 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32f33xx_rcc.h + * For STM32F33xx advanced ARM-based 32-bit MCUs + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Modified for STM32F334 by Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_RCC_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_RCC_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_CFGR_OFFSET 0x0004 /* Clock configuration register */ +#define STM32_RCC_CIR_OFFSET 0x0008 /* Clock interrupt register */ +#define STM32_RCC_APB2RSTR_OFFSET 0x000c /* APB2 Peripheral reset register */ +#define STM32_RCC_APB1RSTR_OFFSET 0x0010 /* APB1 Peripheral reset register */ +#define STM32_RCC_AHBENR_OFFSET 0x0014 /* AHB Peripheral Clock enable register */ +#define STM32_RCC_APB2ENR_OFFSET 0x0018 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR_OFFSET 0x001c /* APB1 Peripheral Clock enable register */ +#define STM32_RCC_BDCR_OFFSET 0x0020 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0024 /* Control/status register */ +#define STM32_RCC_AHBRSTR_OFFSET 0x0028 /* AHB Reset register */ +#define STM32_RCC_CFGR2_OFFSET 0x002c /* Clock configuration register 2 */ +#define STM32_RCC_CFGR3_OFFSET 0x0030 /* Clock configuration register 3 */ + +/* Register Addresses ***************************************************************/ + +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_CIR (STM32_RCC_BASE+STM32_RCC_CIR_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_APB1RSTR (STM32_RCC_BASE+STM32_RCC_APB1RSTR_OFFSET) +#define STM32_RCC_AHBENR (STM32_RCC_BASE+STM32_RCC_AHBENR_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_AHBRSTR (STM32_RCC_BASE+STM32_RCC_AHBRSTR_OFFSET) +#define STM32_RCC_CFGR2 (STM32_RCC_BASE+STM32_RCC_CFGR2_OFFSET) +#define STM32_RCC_CFGR3 (STM32_RCC_BASE+STM32_RCC_CFGR3_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +/* Clock control register */ + +#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */ +#define RCC_CR_HSIRDY (1 << 1) /* Bit 1: Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM_SHIFT (3) /* Bits 7-3: Internal High Speed clock trimming */ +#define RCC_CR_HSITRIM_MASK (0x1f << RCC_CR_HSITRIM_SHIFT) +#define RCC_CR_HSICAL_SHIFT (8) /* Bits 15-8: Internal High Speed clock Calibration */ +#define RCC_CR_HSICAL_MASK (0xff << RCC_CR_HSICAL_SHIFT) +#define RCC_CR_HSEON (1 << 16) /* Bit 16: External High Speed clock enable */ +#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External High Speed clock ready flag */ +#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External High Speed clock Bypass */ +#define RCC_CR_CSSON (1 << 19) /* Bit 19: Clock Security System enable */ +#define RCC_CR_PLLON (1 << 24) /* Bit 24: PLL enable */ +#define RCC_CR_PLLRDY (1 << 25) /* Bit 25: PLL clock ready flag */ + +/* Clock configuration register */ + +#define RCC_CFGR_SW_SHIFT (0) /* Bits 1-0: System clock Switch */ +#define RCC_CFGR_SW_MASK (3 << RCC_CFGR_SW_SHIFT) +# define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 00: HSI selected as system clock */ +# define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */ +# define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */ +#define RCC_CFGR_SWS_SHIFT (2) /* Bits 3-2: System Clock Switch Status */ +#define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT) +# define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */ +# define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */ +# define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */ +#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 7-4: AHB prescaler */ +#define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT) +# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ +# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ +# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ +# define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */ +# define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */ +# define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */ +# define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */ +# define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */ +# define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */ +#define RCC_CFGR_PPRE1_SHIFT (8) /* Bits 10-8: APB Low speed prescaler (APB1) */ +#define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT) +# define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */ +# define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */ +# define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */ +# define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */ +# define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */ +#define RCC_CFGR_PPRE2_SHIFT (11) /* Bits 13-11: APB High speed prescaler (APB2) */ +#define RCC_CFGR_PPRE2_MASK (7 << RCC_CFGR_PPRE2_SHIFT) +# define RCC_CFGR_PPRE2_HCLK (0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK not divided */ +# define RCC_CFGR_PPRE2_HCLKd2 (4 << RCC_CFGR_PPRE2_SHIFT) /* 100: HCLK divided by 2 */ +# define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */ +# define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */ +# define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */ +#define RCC_CFGR_PLLSRC (1 << 16) /* Bit 16: PLL entry clock source */ +#define RCC_CFGR_PLLXTPRE (1 << 17) /* Bit 17: HSE divider for PLL entry */ +#define RCC_CFGR_PLLMUL_SHIFT (18) /* Bits 21-18: PLL Multiplication Factor */ +#define RCC_CFGR_PLLMUL_MASK (0x0f << RCC_CFGR_PLLMUL_SHIFT) +# define RCC_CFGR_PLLMUL_CLKx2 (0 << RCC_CFGR_PLLMUL_SHIFT) /* 0000: PLL input clock x 2 */ +# define RCC_CFGR_PLLMUL_CLKx3 (1 << RCC_CFGR_PLLMUL_SHIFT) /* 0001: PLL input clock x 3 */ +# define RCC_CFGR_PLLMUL_CLKx4 (2 << RCC_CFGR_PLLMUL_SHIFT) /* 0010: PLL input clock x 4 */ +# define RCC_CFGR_PLLMUL_CLKx5 (3 << RCC_CFGR_PLLMUL_SHIFT) /* 0011: PLL input clock x 5 */ +# define RCC_CFGR_PLLMUL_CLKx6 (4 << RCC_CFGR_PLLMUL_SHIFT) /* 0100: PLL input clock x 6 */ +# define RCC_CFGR_PLLMUL_CLKx7 (5 << RCC_CFGR_PLLMUL_SHIFT) /* 0101: PLL input clock x 7 */ +# define RCC_CFGR_PLLMUL_CLKx8 (6 << RCC_CFGR_PLLMUL_SHIFT) /* 0110: PLL input clock x 8 */ +# define RCC_CFGR_PLLMUL_CLKx9 (7 << RCC_CFGR_PLLMUL_SHIFT) /* 0111: PLL input clock x 9 */ +# define RCC_CFGR_PLLMUL_CLKx10 (8 << RCC_CFGR_PLLMUL_SHIFT) /* 1000: PLL input clock x 10 */ +# define RCC_CFGR_PLLMUL_CLKx11 (9 << RCC_CFGR_PLLMUL_SHIFT) /* 1001: PLL input clock x 11 */ +# define RCC_CFGR_PLLMUL_CLKx12 (10 << RCC_CFGR_PLLMUL_SHIFT) /* 1010: PLL input clock x 12 */ +# define RCC_CFGR_PLLMUL_CLKx13 (11 << RCC_CFGR_PLLMUL_SHIFT) /* 1011: PLL input clock x 13 */ +# define RCC_CFGR_PLLMUL_CLKx14 (12 << RCC_CFGR_PLLMUL_SHIFT) /* 1100: PLL input clock x 14 */ +# define RCC_CFGR_PLLMUL_CLKx15 (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1101: PLL input clock x 15 */ +# define RCC_CFGR_PLLMUL_CLKx16 (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */ +#define RCC_CFGR_MCO_SHIFT (24) /* Bits 26-24: Microcontroller Clock Output */ +#define RCC_CFGR_MCO_MASK (3 << RCC_CFGR_MCO_SHIFT) +# define RCC_CFGR_MCO_DISABLED (0 << RCC_CFGR_MCO_SHIFT) /* 000: MCO output disabled, no clock on MCO */ +# define RCC_CFGR_MCO_LSICLK (2 << RCC_CFGR_MCO_SHIFT) /* 010: LSI clock selected */ +# define RCC_CFGR_MCO_LSECLK (3 << RCC_CFGR_MCO_SHIFT) /* 011: LSE clock selected */ +# define RCC_CFGR_MCO_SYSCLK (4 << RCC_CFGR_MCO_SHIFT) /* 100: System clock (SYSCLK) selected */ +# define RCC_CFGR_MCO_HSICLK (5 << RCC_CFGR_MCO_SHIFT) /* 101: HSI clock selected */ +# define RCC_CFGR_MCO_HSECLK (6 << RCC_CFGR_MCO_SHIFT) /* 101: HSE clock selected */ +# define RCC_CFGR_PLLCLKd2 (7 << RCC_CFGR_MCO_SHIFT) /* 111: PLL clock divided by 2 selected */ +#define RCC_CFGR_MCOPRE_SHIFT (28) /* Bits 30-28: Microcontroller Clock Output */ +#define RCC_CFGR_MCOPRE_MASK (7 << RCC_CFGR_MCOPRE_SHIFT) +# define RCC_CFGR_MCOPRE_MCOd1 (0 << RCC_CFGR_MCOPRE_SHIFT) /* 000: MCO is divided by 1 */ +# define RCC_CFGR_MCOPRE_MCOd2 (1 << RCC_CFGR_MCOPRE_SHIFT) /* 001: MCO is divided by 2 */ +# define RCC_CFGR_MCOPRE_MCOd4 (2 << RCC_CFGR_MCOPRE_SHIFT) /* 010: MCO is divided by 4 */ +# define RCC_CFGR_MCOPRE_MCOd8 (3 << RCC_CFGR_MCOPRE_SHIFT) /* 011: MCO is divided by 8 */ +# define RCC_CFGR_MCOPRE_MCOd16 (4 << RCC_CFGR_MCOPRE_SHIFT) /* 100: MCO is divided by 16 */ +# define RCC_CFGR_MCOPRE_MCOd32 (5 << RCC_CFGR_MCOPRE_SHIFT) /* 101: MCO is divided by 32 */ +# define RCC_CFGR_MCOPRE_MCOd64 (6 << RCC_CFGR_MCOPRE_SHIFT) /* 110: MCO is divided by 64 */ +# define RCC_CFGR_MCOPRE_MCOd128 (7 << RCC_CFGR_MCOPRE_SHIFT) /* 111: MCO is divided by 128 */ +#define RCC_CFGR_PLLNODIV (1 << 31) /* Bit 31: Do not divide PLL to MCO */ + +/* Clock interrupt register */ + +#define RCC_CIR_LSIRDYF (1 << 0) /* Bit 0: LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF (1 << 1) /* Bit 1: LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF (1 << 2) /* Bit 2: HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF (1 << 3) /* Bit 3: HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF (1 << 4) /* Bit 4: PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF (1 << 7) /* Bit 7: Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE (1 << 8) /* Bit 8: LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE (1 << 9) /* Bit 9: LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE (1 << 10) /* Bit 10: HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE (1 << 11) /* Bit 11: HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE (1 << 12) /* Bit 12: PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC (1 << 16) /* Bit 16: LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC (1 << 17) /* Bit 17: LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC (1 << 18) /* Bit 18: HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC (1 << 19) /* Bit 19: HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC (1 << 20) /* Bit 20: PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC (1 << 23) /* Bit 23: Clock Security System Interrupt Clear */ + +/* APB2 Peripheral reset register */ + +#define RCC_APB2RSTR_SYSCFGRST (1 << 0) /* Bit 0: SYSCFG, Comparators and operational amplifiers reset */ +#define RCC_APB2RSTR_TIM1RST (1 << 9) /* Bit 9: TIM1 reset */ +#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI 1 reset */ +#define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */ +#define RCC_APB2RSTR_TIM15RST (1 << 16) /* Bit 16: TIM15 reset */ +#define RCC_APB2RSTR_TIM16RST (1 << 17) /* Bit 17: TIM16 reset */ +#define RCC_APB2RSTR_TIM17RST (1 << 18) /* Bit 18: TIM17 reset */ +#define RCC_APB2RSTR_HRTIM1RST (1 << 26) /* Bit 29: HRTIM1 reset */ + +/* APB1 Peripheral reset register */ + +#define RCC_APB1RSTR_TIM2RST (1 << 0) /* Bit 0: Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST (1 << 1) /* Bit 1: Timer 3 reset */ +#define RCC_APB1RSTR_TIM6RST (1 << 4) /* Bit 4: Timer 6 reset */ +#define RCC_APB1RSTR_TIM7RST (1 << 5) /* Bit 5: Timer 7 reset */ +#define RCC_APB1RSTR_WWDGRST (1 << 11) /* Bit 11: Window Watchdog reset */ +#define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART 2 reset */ +#define RCC_APB1RSTR_USART3RST (1 << 18) /* Bit 18: USART 3 reset */ +#define RCC_APB1RSTR_I2C1RST (1 << 21) /* Bit 21: I2C 1 reset */ +#define RCC_APB1RSTR_CANRST (1 << 25) /* Bit 25: CAN reset */ +#define RCC_APB1RSTR_CAN1RST (1 << 25) /* Bit 25: CAN reset */ +#define RCC_APB1RSTR_DAC2RST (1 << 26) /* Bit 26: DAC2 interface reset */ +#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */ +#define RCC_APB1RSTR_DAC1RST (1 << 29) /* Bit 29: DAC1 interface reset */ + +/* AHB Peripheral Clock enable register */ + +#define RCC_AHBENR_DMA1EN (1 << 0) /* Bit 0: DMA1 clock enable */ +#define RCC_AHBENR_SRAMEN (1 << 2) /* Bit 2: SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN (1 << 4) /* Bit 4: FLITF clock enable */ +#define RCC_AHBENR_CRCEN (1 << 6) /* Bit 6: CRC clock enable */ +#define RCC_AHBENR_IOPAEN (1 << 17) /* Bit 17: I/O port A clock enable */ +#define RCC_AHBENR_IOPBEN (1 << 18) /* Bit 17: I/O port B clock enable */ +#define RCC_AHBENR_IOPCEN (1 << 19) /* Bit 17: I/O port C clock enable */ +#define RCC_AHBENR_IOPDEN (1 << 20) /* Bit 17: I/O port D clock enable */ +#define RCC_AHBENR_IOPFEN (1 << 22) /* Bit 17: I/O port F clock enable */ +#define RCC_AHBENR_TSCEN (1 << 24) /* Bit 24: TSCEN: Touch sensing controller clock enable */ +#define RCC_AHBENR_ADC12EN (1 << 28) /* Bit 28: ADC1/ADC2 clock enable */ + +/* APB2 Peripheral Clock enable register */ + +#define RCC_APB2ENR_SYSCFGEN (1 << 0) /* Bit 0: SYSCFG, Comparators and operational amplifiers clock enable */ +#define RCC_APB2ENR_TIM1EN (1 << 11) /* Bit 11: TIM1 clock enable */ +#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI 1 clock enable */ +#define RCC_APB2ENR_USART1EN (1 << 14) /* Bit 14: USART1 clock enable */ +#define RCC_APB2ENR_TIM15EN (1 << 16) /* Bit 16: TIM15 clock enable */ +#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: TIM16 clock enable */ +#define RCC_APB2ENR_TIM17EN (1 << 18) /* Bit 18: TIM17 clock enable */ +#define RCC_APB2ENR_HRTIM1EN (1 << 29) /* Bit 29: HRTIM1 clock enable */ + +/* APB1 Peripheral Clock enable register */ + +#define RCC_APB1ENR_TIM2EN (1 << 0) /* Bit 0: Timer 2 clock enable */ +#define RCC_APB1ENR_TIM3EN (1 << 1) /* Bit 1: Timer 3 clock enable */ +#define RCC_APB1ENR_TIM6EN (1 << 4) /* Bit 4: Timer 6 clock enable */ +#define RCC_APB1ENR_TIM7EN (1 << 5) /* Bit 5: Timer 7 clock enable */ +#define RCC_APB1ENR_WWDGEN (1 << 11) /* Bit 11: Window Watchdog clock enable */ +#define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 clock enable */ +#define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART 3 clock enable */ +#define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C 1 clock enable */ +#define RCC_APB1ENR_CANEN (1 << 25) /* Bit 25: CAN clock enable */ +#define RCC_APB1ENR_DAC2EN (1 << 26) /* Bit 26: DAC1 interface clock enable */ +#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */ +#define RCC_APB1ENR_DAC1EN (1 << 29) /* Bit 29: DAC1 interface clock enable */ + +/* Backup domain control register */ + +#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */ +#define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 4:3: LSE oscillator drive capability */ +#define RCC_BDCR_LSEDRV_MASK (3 << RCC_BDCR_LSEDRV_SHIFT) +# define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT) /* 'Xtal mode' lower driving capability */ +# define RCC_BDCR_LSEDRV_MEDLOW (1 << RCC_BDCR_LSEDRV_SHIFT) /* 'Xtal mode' medium low driving capability */ +# define RCC_BDCR_LSEDRV_MEDHIGH (2 << RCC_BDCR_LSEDRV_SHIFT) /* 'Xtal mode' medium high driving capability */ +# define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) /* 'Xtal mode' higher driving capability */ +#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ +#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) +# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ +# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */ +#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ +#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */ + +/* Control/status register */ + +#define RCC_CSR_LSION (1 << 0) /* Bit 0: Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY (1 << 1) /* Bit 1: Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF (1 << 24) /* Bit 24: Remove reset flag */ +#define RCC_CSR_OBLRSTF (1 << 25) /* Bit 25: Option byte loader reset flag */ +#define RCC_CSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */ +#define RCC_CSR_PORRSTF (1 << 27) /* Bit 27: POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF (1 << 28) /* Bit 28: Software Reset flag */ +#define RCC_CSR_IWDGRSTF (1 << 29) /* Bit 29: Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */ + +/* AHB peripheral clock reset register (RCC_AHBRSTR) */ + +#define RCC_AHBRSTR_IOPARST (1 << 17) /* Bit 17: I/O port A reset */ +#define RCC_AHBRSTR_IOPBRST (1 << 18) /* Bit 18: I/O port B reset */ +#define RCC_AHBRSTR_IOPCRST (1 << 29) /* Bit 19: I/O port C reset */ +#define RCC_AHBRSTR_IOPDRST (1 << 20) /* Bit 20: I/O port D reset */ +#define RCC_AHBRSTR_IOPFRST (1 << 22) /* Bit 22: I/O port F reset */ +#define RCC_AHBRSTR_TSCRST (1 << 24) /* Bit 24: Touch sensing controller reset */ +#define RCC_AHBRSTR_ADC12RST (1 << 28) /* Bit 24: ADC1/ADC2 reset */ + +/* Clock configuration register 2 */ + +#define RCC_CFGR2_PREDIV_SHIFT (0) /* Bits 0-3: PREDIV division factor */ +#define RCC_CFGR2_PREDIV_MASK (15 << RCC_CFGR2_PREDIV_SHIFT) +# define RCC_CFGR2_PREDIVd1 (0 << RCC_CFGR2_PREDIV_SHIFT) /* 0000: HSE input to PLL not divided */ +# define RCC_CFGR2_PREDIVd2 (1 << RCC_CFGR2_PREDIV_SHIFT) /* 0001: HSE input to PLL divided by 2 */ +# define RCC_CFGR2_PREDIVd3 (2 << RCC_CFGR2_PREDIV_SHIFT) /* 0010: HSE input to PLL divided by 3 */ +# define RCC_CFGR2_PREDIVd4 (3 << RCC_CFGR2_PREDIV_SHIFT) /* 0011: HSE input to PLL divided by 4 */ +# define RCC_CFGR2_PREDIVd5 (4 << RCC_CFGR2_PREDIV_SHIFT) /* 0100: HSE input to PLL divided by 5 */ +# define RCC_CFGR2_PREDIVd6 (5 << RCC_CFGR2_PREDIV_SHIFT) /* 0101: HSE input to PLL divided by 6 */ +# define RCC_CFGR2_PREDIVd7 (6 << RCC_CFGR2_PREDIV_SHIFT) /* 0110: HSE input to PLL divided by 7 */ +# define RCC_CFGR2_PREDIVd8 (7 << RCC_CFGR2_PREDIV_SHIFT) /* 0111: HSE input to PLL divided by 8 */ +# define RCC_CFGR2_PREDIVd9 (8 << RCC_CFGR2_PREDIV_SHIFT) /* 1000: HSE input to PLL divided by 9 */ +# define RCC_CFGR2_PREDIVd10 (9 << RCC_CFGR2_PREDIV_SHIFT) /* 1001: HSE input to PLL divided by 10 */ +# define RCC_CFGR2_PREDIVd11 (10 << RCC_CFGR2_PREDIV_SHIFT) /* 1010: HSE input to PLL divided by 11 */ +# define RCC_CFGR2_PREDIVd12 (11 << RCC_CFGR2_PREDIV_SHIFT) /* 1011: HSE input to PLL divided by 12 */ +# define RCC_CFGR2_PREDIVd13 (12 << RCC_CFGR2_PREDIV_SHIFT) /* 1100: HSE input to PLL divided by 13 */ +# define RCC_CFGR2_PREDIVd14 (13 << RCC_CFGR2_PREDIV_SHIFT) /* 1101: HSE input to PLL divided by 14 */ +# define RCC_CFGR2_PREDIVd15 (14 << RCC_CFGR2_PREDIV_SHIFT) /* 1110: HSE input to PLL divided by 15 */ +# define RCC_CFGR2_PREDIVd16 (15 << RCC_CFGR2_PREDIV_SHIFT) /* 1111: HSE input to PLL divided by 16 */ +#define RCC_CFGR2_ADC12PRES_SHIFT (4) /* Bits 4-8: ADC12PRES division factor */ +#define RCC_CFGR2_ADC12PRES_MASK (32 << RCC_CFGR2_ADC12PRES_SHIFT) +# define RCC_CFGR2_ADC12DISABLED (0 << RCC_CFGR2_ADC12PRES_SHIFT) /* 00000: ADC12 clock disabled */ +# define RCC_CFGR2_ADC12PRESd1 (16 << RCC_CFGR2_ADC12PRES_SHIFT) /* 10000: PLL clock divided by 1 */ +# define RCC_CFGR2_ADC12PRESd2 (17 << RCC_CFGR2_ADC12PRES_SHIFT) /* 10001: PLL clock divided by 2 */ +# define RCC_CFGR2_ADC12PRESd4 (18 << RCC_CFGR2_ADC12PRES_SHIFT) /* 10010: PLL clock divided by 4 */ +# define RCC_CFGR2_ADC12PRESd6 (19 << RCC_CFGR2_ADC12PRES_SHIFT) /* 10011: PLL clock divided by 6 */ +# define RCC_CFGR2_ADC12PRESd8 (20 << RCC_CFGR2_ADC12PRES_SHIFT) /* 10100: PLL clock divided by 8 */ +# define RCC_CFGR2_ADC12PRESd10 (21 << RCC_CFGR2_ADC12PRES_SHIFT) /* 10101: PLL clock divided by 10 */ +# define RCC_CFGR2_ADC12PRESd12 (22 << RCC_CFGR2_ADC12PRES_SHIFT) /* 10110: PLL clock divided by 12 */ +# define RCC_CFGR2_ADC12PRESd16 (23 << RCC_CFGR2_ADC12PRES_SHIFT) /* 10111: PLL clock divided by 16 */ +# define RCC_CFGR2_ADC12PRESd32 (24 << RCC_CFGR2_ADC12PRES_SHIFT) /* 11000: PLL clock divided by 32 */ +# define RCC_CFGR2_ADC12PRESd64 (25 << RCC_CFGR2_ADC12PRES_SHIFT) /* 11001: PLL clock divided by 64 */ +# define RCC_CFGR2_ADC12PRESd128 (26 << RCC_CFGR2_ADC12PRES_SHIFT) /* 11010: PLL clock divided by 128 */ +# define RCC_CFGR2_ADC12PRESd256 (27 << RCC_CFGR2_ADC12PRES_SHIFT) /* 11011: PLL clock divided by 256 */ + +/* Clock configuration register 3 */ + +#define RCC_CFGR3_USART1SW_SHIFT (0) /* Bits 0-1: USART1 clock source selection */ +#define RCC_CFGR3_USART1SW_MASK (3 << RCC_CFGR3_USART1SW_SHIFT) +# define RCC_CFGR3_USART1SW_PCLK (0 << RCC_CFGR3_USART1SW_SHIFT) /* PCLK */ +# define RCC_CFGR3_USART1SW_SYSCLK (1 << RCC_CFGR3_USART1SW_SHIFT) /* System clock (SYSCLK) */ +# define RCC_CFGR3_USART1SW_LSE (2 << RCC_CFGR3_USART1SW_SHIFT) /* LSE clock */ +# define RCC_CFGR3_USART1SW_HSI (0 << RCC_CFGR3_USART1SW_SHIFT) /* HSI clock */ +#define RCC_CFGR3_I2C1SW (1 << 4) /* Bit 4: I2C1 clock source selection */ +#define RCC_CFGR3_TIM1SW (1 << 8) /* Bit 8: TIM1 clock source selection */ +#define RCC_CFGR3_HRTIM1SW (1 << 9) /* Bit 9: HRTIM clock source selection */ +#define RCC_CFGR3_USART2SW_SHIFT (16) /* Bits 16-17: USART2 clock source selection */ +#define RCC_CFGR3_USART2SW_MASK (3 << RCC_CFGR3_USART2SW_SHIFT) +# define RCC_CFGR3_USART2SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT) /* PCLK */ +# define RCC_CFGR3_USART2SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT) /* System clock (SYSCLK) */ +# define RCC_CFGR3_USART2SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT) /* LSE clock */ +# define RCC_CFGR3_USART2SW_HSI (0 << RCC_CFGR3_USART2SW_SHIFT) /* HSI clock */ +#define RCC_CFGR3_USART3SW_SHIFT (18) /* Bits 18-19: USART3 clock source selection */ +#define RCC_CFGR3_USART3SW_MASK (3 << RCC_CFGR3_USART3SW_SHIFT) +# define RCC_CFGR3_USART3SW_PCLK (0 << RCC_CFGR3_USART3SW_SHIFT) /* PCLK */ +# define RCC_CFGR3_USART3SW_SYSCLK (1 << RCC_CFGR3_USART3SW_SHIFT) /* System clock (SYSCLK) */ +# define RCC_CFGR3_USART3SW_LSE (2 << RCC_CFGR3_USART3SW_SHIFT) /* LSE clock */ +# define RCC_CFGR3_USART3SW_HSI (0 << RCC_CFGR3_USART3SW_SHIFT) /* HSI clock */ + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_RCC_H */ diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_syscfg.h b/arch/arm/src/stm32/chip/stm32f33xxx_syscfg.h new file mode 100644 index 00000000000..6e83d0b6111 --- /dev/null +++ b/arch/arm/src/stm32/chip/stm32f33xxx_syscfg.h @@ -0,0 +1,182 @@ +/**************************************************************************************************** + * arch/arm/src/stm32/chip/stm32f33xxx_syscfg.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Modified for STM32F334 by Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_SYSCFG_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_SYSCFG_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include "chip.h" + +#ifdef CONFIG_STM32_STM32F33XX + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define STM32_SYSCFG_CFGR1_OFFSET 0x0000 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_RCR_OFFSET 0x0004 /* SYSCFG CCM SRAM protection register */ + +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ + +#define STM32_SYSCFG_CFGR2_OFFSET 0x0018 /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_CFGR3_OFFSET 0x0050 /* SYSCFG configuration register 3 */ + +/* Register Addresses *******************************************************************************/ + +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_RCR (STM32_SYSCFG_BASE+STM32_SYSCFG_RCR_OFFSET) + +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) + +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_CFGR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR3_OFFSET) + +/* Register Bitfield Definitions ********************************************************************/ + +/* SYSCFG memory remap register */ + +#define SYSCFG_CFGR1_MEMMODE_SHIFT (0) /* Bits 1:0 MEM_MODE: Memory mapping selection */ +#define SYSCFG_CFGR1_MEMMODE_MASK (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) +# define SYSCFG_CFGR1_MEMMODE_FLASH (0 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 00: Main Flash at 0x00000000 */ +# define SYSCFG_CFGR1_MEMMODE_SYSTEM (1 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 01: System Flash at 0x00000000 */ +# define SYSCFG_CFGR1_MEMMODE_SRAM (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 11: Embedded SRAM at 0x00000000 */ +#define SYSCFG_CFGR1_TIM1_ITR3RMP (1 << 6) /* Bit 6: Timer 1 ITR3 selection */ +#define SYSCFG_CFGR1_DAC_TRIGRMP (1 << 7) /* Bit 7: DAC trigger remap (when TSEL = 001) */ +#define SYSCFG_CFGR1_TIM16_DMARMP (1 << 11) /* Bit 11: TIM16 DMA request remapping bit */ +#define SYSCFG_CFGR1_TIM17_DMARMP (1 << 12) /* Bit 12: TIM17 DMA request remapping bit */ +#define SYSCFG_CFGR1_TIM6_DMARMP (1 << 13) /* Bit 13: TIM6 DMA remap, or */ +#define SYSCFG_CFGR1_DAC1_DMARMP (1 << 13) /* Bit 13: DAC channel DMA remap */ +#define SYSCFG_CFGR1_TIM7_DMARMP (1 << 14) /* Bit 14: TIM7 DMA remap */ +#define SYSCFG_CFGR1_DAC2CH2_DMARMP (1 << 14) /* Bit 14: DAC channel2 DMA remap */ +#define SYSCFG_CFGR1_DAC2CH1_DMARMP (1 << 15) /* Bit 14: DAC channel1 DMA remap */ +#define SYSCFG_CFGR1_I2C_PBXFMP_SHIFT (0) /* Bits 16-19: Fast Mode Plus (FM+) driving capability */ +#define SYSCFG_CFGR1_I2C_PBXFMP_MASK (15 << SYSCFG_CFGR1_I2C_PBXFMP_SHIFT) +#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) /* Bit 20: I2C1 fast mode Plus driving capability */ +#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) /* Bit 21: I2C2 fast mode Plus driving capability */ +#define SYSCFG_CFGR1_ENCMODE_SHIFT (22) /* Bits 22-23: Encoder mode */ +#define SYSCFG_CFGR1_ENCMODE_MASK (3 << SYSCFG_CFGR1_ENCMODE_SHIFT) +# define SYSCFG_CFGR1_ENCMODE_NONE (0 << SYSCFG_CFGR1_ENCMODE_SHIFT) /* No redirection */ +# define SYSCFG_CFGR1_ENCMODE_TIM2 (1 << SYSCFG_CFGR1_ENCMODE_SHIFT) /* TIM2 I2C1-2 -> TIM15 IC1/2 */ +# define SYSCFG_CFGR1_ENCMODE_TIM3 (2 << SYSCFG_CFGR1_ENCMODE_SHIFT) /* TIM3 I2C1-2 -> TIM15 IC1/2 */ +# define SYSCFG_CFGR1_ENCMODE_TIM4 (3 << SYSCFG_CFGR1_ENCMODE_SHIFT) /* TIM4 I2C1-2 -> TIM15 IC1/2 */ +#define SYSCFG_CFGR1_FPUIE_SHIFT (26) /* Bits 26-31: Floating Point Unit interrupts enable bits */ +#define SYSCFG_CFGR1_FPUIE_MASK (63 << SYSCFG_CFGR1_FPUIE_SHIFT) +# define SYSCFG_CFGR1_FPUIE_INVALIDOP (1 << SYSCFG_CFGR1_FPUIE_SHIFT) /* Invalid operation interrupt enable */ +# define SYSCFG_CFGR1_FPUIE_DIVZERO (2 << SYSCFG_CFGR1_FPUIE_SHIFT) /* Divide-by-zero interrupt enable */ +# define SYSCFG_CFGR1_FPUIE_UNDERFLOW (4 << SYSCFG_CFGR1_FPUIE_SHIFT) /* Underflow interrupt enable */ +# define SYSCFG_CFGR1_FPUIE_OVERFLOW (8 << SYSCFG_CFGR1_FPUIE_SHIFT) /* Overflow interrupt enable */ +# define SYSCFG_CFGR1_FPUIE_DENORMAL (16 << SYSCFG_CFGR1_FPUIE_SHIFT) /* Input denormal interrupt enable */ +# define SYSCFG_CFGR1_FPUIE_INEXACT (32 << SYSCFG_CFGR1_FPUIE_SHIFT) /* Inexact interrupt enable */ + +/* SYSCFG CCM SRAM protection register */ + +#define SYSCFG_RCR(page) (1 << (page)) /* Bit n: Write protection page n */ + +/* SYSCFG external interrupt configuration register 1-4 */ + +#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */ +#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */ +#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */ +#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */ +#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */ + +#define SYSCFG_EXTICR_PORT_MASK (15) +#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2) +#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g))) + +#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT) +#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT) +#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT) +#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT) + +#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT) +#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT) +#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT) +#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT) + +#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT) +#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT) +#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT) +#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT) + +#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT) +#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT) +#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT) +#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT) + +/* SYSCFG configuration register 2 */ + +#define SYSCFG_CFGR2_LOCKUPLOCK (1 << 0) /* Bit 0: Cortex-M4 Hardfault output bit enable */ +#define SYSCFG_CFGR2_SRAM_PARITYLOCK (1 << 1) /* Bit 1: RAM parity lock */ +#define SYSCFG_CFGR2_PVDLOCK (1 << 2) /* Bit 2: PVD lock enable */ +#define SYSCFG_CFGR2_BYPADDPAR (1 << 4) /* Bit 4: Bypass address bit 29 in parity calculation */ +#define SYSCFG_CFGR2_SRAM_PEF (1 << 8) /* Bit 8: SRAM parity error */ + +/* SYSCFG configuration register 3 */ +/* TODO */ + +#endif /* CONFIG_STM32_STM32F33XX */ +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_SYSCFG_H */ diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_vectors.h b/arch/arm/src/stm32/chip/stm32f33xxx_vectors.h new file mode 100644 index 00000000000..277cd4e6f85 --- /dev/null +++ b/arch/arm/src/stm32/chip/stm32f33xxx_vectors.h @@ -0,0 +1,151 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32f33xxx_vectors.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Modified for STM32F334 by Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor definitions + ************************************************************************************/ +/* This file is included by stm32_vectors.S. It provides the macro VECTOR that + * supplies each STM32F33xxx vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f33xxx_irq.h. + * stm32_vectors.S will defined the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + */ + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 82 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 82 + +#else + +VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* 0: Window Watchdog interrupt */ +VECTOR(stm32_pvd, STM32_IRQ_PVD) /* 1: PVD through EXTI Line detection interrupt */ +VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* 2: Tamper or Time stamp interrupt */ +VECTOR(stm32_rtc_wkup, STM32_IRQ_RTC_WKUP) /* 3: RTC global interrupt */ +VECTOR(stm32_flash, STM32_IRQ_FLASH) /* 4: Flash global interrupt */ +VECTOR(stm32_rcc, STM32_IRQ_RCC) /* 5: RCC global interrupt */ +VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* 6: EXTI Line 0 interrupt */ +VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* 7: EXTI Line 1 interrupt */ +VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* 8: EXTI Line 2 or TSC interrupt */ +VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* 9: EXTI Line 3 interrupt */ + +VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* 10: EXTI Line 4 interrupt */ +VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1) /* 11: DMA1 channel 1 global interrupt */ +VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2) /* 12: DMA1 channel 2 global interrupt */ +VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3) /* 13: DMA1 channel 3 global interrupt */ +VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4) /* 14: DMA1 channel 4 global interrupt */ +VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5) /* 15: DMA1 channel 5 global interrupt */ +VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6) /* 16: DMA1 channel 6 global interrupt */ +VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7) /* 17: DMA1 channel 7 global interrupt */ +VECTOR(stm32_adc12, STM32_IRQ_ADC12) /* 18: ADC1/ADC2 global interrupt */ +VECTOR(stm32_can1tx, STM32_IRQ_CAN1TX) /* 19: USB High Priority or CAN1 TX interrupts */ + +VECTOR(stm32_can1rx0, STM32_IRQ_CAN1RX0) /* 20: USB Low Priority or CAN1 RX0 interrupts*/ +VECTOR(stm32_can1rx1, STM32_IRQ_CAN1RX1) /* 21: CAN1 RX1 interrupt */ +VECTOR(stm32_can1sce, STM32_IRQ_CAN1SCE) /* 22: CAN1 SCE interrupt */ +VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* 23: EXTI Line[9:5] interrupts */ +VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK) /* 24: TIM1 Break or TIM15 global interrupt */ +VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP) /* 25: TIM1 Update or TIM16 global interrupt */ +VECTOR(stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM) /* 26: TIM1 Trigger or TIM17 global interrupt */ +VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC) /* 27: TIM1 Capture Compare interrupt */ +VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* 28: TIM2 global interrupt */ +VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* 29: TIM3 global interrupt */ + +UNUSED(STM32_IRQ_RESERVED30) /* 30: Reserved */ +VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* 31: I2C1 event or EXTI Line23 interrupt */ +VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* 32: I2C1 error interrupt */ +UNUSED(STM32_IRQ_RESERVED33) /* 33: Reserved */ +UNUSED(STM32_IRQ_RESERVED34) /* 34: Reserved */ +VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* 35: SPI1 global interrupt */ +UNUSED(STM32_IRQ_RESERVED36) /* 36: Reserved */ +VECTOR(stm32_usart1, STM32_IRQ_USART1) /* 37: USART1 global or EXTI Line 25 interrupt */ +VECTOR(stm32_usart2, STM32_IRQ_USART2) /* 38: USART2 global or EXTI Line 26 interrupt */ +VECTOR(stm32_usart3, STM32_IRQ_USART3) /* 39: USART3 global or EXTI Line 28 interrupt */ + +VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* 40: EXTI Line[15:10] interrupts */ +VECTOR(stm32_rtcalrm, STM32_IRQ_RTCALRM) /* 41: RTC alarm through EXTI line interrupt */ +UNUSED(STM32_IRQ_RESERVED42) /* 42: Reserved*/ +UNUSED(STM32_IRQ_RESERVED43) /* 43: Reserved */ +UNUSED(STM32_IRQ_RESERVED44) /* 44: Reserved */ +UNUSED(STM32_IRQ_RESERVED45) /* 45: Reserved */ +UNUSED(STM32_IRQ_RESERVED46) /* 46: Reserved */ +UNUSED(STM32_IRQ_RESERVED47) /* 47: Reserved*/ +UNUSED(STM32_IRQ_RESERVED48) /* 48: Reserved */ +UNUSED(STM32_IRQ_RESERVED49) /* 49: Reserved */ + +UNUSED(STM32_IRQ_RESERVED50) /* 50: Reserved */ +UNUSED(STM32_IRQ_RESERVED51) /* 51: Reserved */ +UNUSED(STM32_IRQ_RESERVED51) /* 52: Reserved*/ +UNUSED(STM32_IRQ_RESERVED52) /* 53: Reserved */ +VECTOR(stm32_dac1, STM32_IRQ_DAC1) /* 54: TIM6 global or DAC1 underrun interrupts */ +VECTOR(stm32_dac2, STM32_IRQ_DAC2) /* 55: TIM7 global or DAC2 underrun interrupt */ +UNUSED(STM32_IRQ_RESERVED56) /* 56: Reserved */ +UNUSED(STM32_IRQ_RESERVED57) /* 57: Reserved */ +UNUSED(STM32_IRQ_RESERVED58) /* 58: Reserved */ +UNUSED(STM32_IRQ_RESERVED59) /* 59: Reserved */ + +UNUSED(STM32_IRQ_RESERVED60) /* 60: Reserved */ +UNUSED(STM32_IRQ_RESERVED61) /* 61: Reserved */ +UNUSED(STM32_IRQ_RESERVED62) /* 62: Reserved */ +UNUSED(STM32_IRQ_RESERVED63) /* 63: Reserved */ +VECTOR(stm32_comp2, STM32_IRQ_COMP2) /* 64: COMP2 or EXTI Lines 21-2 and 29 interrupts */ +VECTOR(stm32_comp46, STM32_IRQ_COMP46) /* 65: COMP4/COMP6 or EXTI Lines 30-2 interrupts */ +UNUSED(STM32_IRQ_RESERVED66) /* 66: Reserved */ +VECTOR(stm32_hrtim_tm, STM32_IRQ_HRTIMTM) /* 67: HRTIM master timer interrutp */ +VECTOR(stm32_hrtim_ta, STM32_IRQ_HRTIMTA) /* 68: HRTIM timer A interrutp */ +VECTOR(stm32_hrtim_tb, STM32_IRQ_HRTIMTB) /* 69: HRTIM timer B interrutp */ + +VECTOR(stm32_hrtim_tc, STM32_IRQ_HRTIMTC) /* 70: HRTIM timer C interrutp */ +VECTOR(stm32_hrtim_td, STM32_IRQ_HRTIMTD) /* 71: HRTIM timer D interrutp */ +VECTOR(stm32_hrtim_te, STM32_IRQ_HRTIMTE) /* 72: HRTIM timer E interrutp */ +VECTOR(stm32_hrtim_flt, STM32_IRQ_HRTIMFLT) /* 73: HRTIM fault interrutp */ +UNUSED(STM32_IRQ_RESERVED73) /* 74: Reserved */ +UNUSED(STM32_IRQ_RESERVED74) /* 75: Reserved */ +UNUSED(STM32_IRQ_RESERVED75) /* 76: Reserved */ +UNUSED(STM32_IRQ_RESERVED76) /* 77: Reserved */ +UNUSED(STM32_IRQ_RESERVED77) /* 78: Reserved */ +UNUSED(STM32_IRQ_RESERVED78) /* 79: Reserved */ + +UNUSED(STM32_IRQ_RESERVED79) /* 80: Reserved */ +UNUSED(STM32_IRQ_RESERVED80) /* 81: Reserved */ +VECTOR(stm32_fpu, STM32_IRQ_FPU) /* 82: FPU global interrupt */ + +#endif /* CONFIG_ARMV7M_CMNVECTOR */ diff --git a/arch/arm/src/stm32/gnu/stm32_vectors.S b/arch/arm/src/stm32/gnu/stm32_vectors.S index a1a39dff2f9..31f62c8d112 100644 --- a/arch/arm/src/stm32/gnu/stm32_vectors.S +++ b/arch/arm/src/stm32/gnu/stm32_vectors.S @@ -177,6 +177,8 @@ _vectors: # include "chip/stm32f20xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F30XX) # include "chip/stm32f30xxx_vectors.h" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "chip/stm32f33xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F37XX) # include "chip/stm32f37xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F40XX) @@ -222,6 +224,8 @@ handlers: # include "chip/stm32f20xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F30XX) # include "chip/stm32f30xxx_vectors.h" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "chip/stm32f33xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F37XX) # include "chip/stm32f37xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F40XX) diff --git a/arch/arm/src/stm32/iar/stm32_vectors.S b/arch/arm/src/stm32/iar/stm32_vectors.S index cb9069dbc19..cf83e7b8bff 100644 --- a/arch/arm/src/stm32/iar/stm32_vectors.S +++ b/arch/arm/src/stm32/iar/stm32_vectors.S @@ -461,6 +461,8 @@ __vector_table: DCD stm32_hash /* Vector 16+80: Hash and Rng global interrupt */ #elif defined(CONFIG_STM32_STM32F30XX) # include "chip/stm32f30xxx_vectors.h" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "chip/stm32f33xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F37XX) # include "chip/stm32f37xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) @@ -778,6 +780,8 @@ handlers: #elif defined(CONFIG_STM32_STM32F30XX) # include "chip/stm32f30xxx_vectors.h" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "chip/stm32f33xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F37XX) # include "chip/stm32f37xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) diff --git a/arch/arm/src/stm32/stm32_1wire.c b/arch/arm/src/stm32/stm32_1wire.c index 952f2777ec7..b43769577a8 100644 --- a/arch/arm/src/stm32/stm32_1wire.c +++ b/arch/arm/src/stm32/stm32_1wire.c @@ -117,7 +117,6 @@ struct stm32_1wire_config_s const uint32_t apbclock; /* PCLK 1 or 2 frequency */ const uint32_t data_pin; /* GPIO configuration for DATA */ const uint8_t irq; /* IRQ associated with this USART */ - int (*const vector)(int irq, void *context); /* Interrupt handler */ }; /* 1-Wire device Private Data */ @@ -161,33 +160,7 @@ static inline void stm32_1wire_sem_wait(FAR struct stm32_1wire_priv_s *priv); static inline void stm32_1wire_sem_post(FAR struct stm32_1wire_priv_s *priv); static int stm32_1wire_process(struct stm32_1wire_priv_s *priv, FAR const struct stm32_1wire_msg_s *msgs, int count); -static int stm32_1wire_isr(struct stm32_1wire_priv_s *priv); - -#ifdef CONFIG_STM32_USART1_1WIREDRIVER -static int stm32_interrupt_1wire1(int irq, void *context); -#endif -#ifdef CONFIG_STM32_USART2_1WIREDRIVER -static int stm32_interrupt_1wire2(int irq, void *context); -#endif -#ifdef CONFIG_STM32_USART3_1WIREDRIVER -static int stm32_interrupt_1wire3(int irq, void *context); -#endif -#ifdef CONFIG_STM32_UART4_1WIREDRIVER -static int stm32_interrupt_1wire4(int irq, void *context); -#endif -#ifdef CONFIG_STM32_UART5_1WIREDRIVER -static int stm32_interrupt_1wire5(int irq, void *context); -#endif -#ifdef CONFIG_STM32_USART6_1WIREDRIVER -static int stm32_interrupt_1wire6(int irq, void *context); -#endif -#ifdef CONFIG_STM32_UART7_1WIREDRIVER -static int stm32_interrupt_1wire7(int irq, void *context); -#endif -#ifdef CONFIG_STM32_UART8_1WIREDRIVER -static int stm32_interrupt_1wire8(int irq, void *context); -#endif - +static int stm32_1wire_isr(int irq, void *context, void *arg); static int stm32_1wire_reset(FAR struct onewire_dev_s *dev); static int stm32_1wire_write(FAR struct onewire_dev_s *dev, const uint8_t *buffer, int buflen); @@ -211,7 +184,6 @@ static const struct stm32_1wire_config_s stm32_1wire1_config = .apbclock = STM32_PCLK2_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_USART1_TX), .irq = STM32_IRQ_USART1, - .vector = stm32_interrupt_1wire1, }; static struct stm32_1wire_priv_s stm32_1wire1_priv = @@ -231,7 +203,6 @@ static const struct stm32_1wire_config_s stm32_1wire2_config = .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_USART2_TX), .irq = STM32_IRQ_USART2, - .vector = stm32_interrupt_1wire2, }; static struct stm32_1wire_priv_s stm32_1wire2_priv = @@ -251,7 +222,6 @@ static const struct stm32_1wire_config_s stm32_1wire3_config = .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_USART3_TX), .irq = STM32_IRQ_USART3, - .vector = stm32_interrupt_1wire3, }; static struct stm32_1wire_priv_s stm32_1wire3_priv = @@ -271,7 +241,6 @@ static const struct stm32_1wire_config_s stm32_1wire4_config = .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_UART4_TX), .irq = STM32_IRQ_UART4, - .vector = stm32_interrupt_1wire4, }; static struct stm32_1wire_priv_s stm32_1wire4_priv = @@ -291,7 +260,6 @@ static const struct stm32_1wire_config_s stm32_1wire5_config = .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_UART5_TX), .irq = STM32_IRQ_UART5, - .vector = stm32_interrupt_1wire5, }; static struct stm32_1wire_priv_s stm32_1wire5_priv = @@ -311,7 +279,6 @@ static const struct stm32_1wire_config_s stm32_1wire6_config = .apbclock = STM32_PCLK2_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_USART6_TX), .irq = STM32_IRQ_USART6, - .vector = stm32_interrupt_1wire6, }; static struct stm32_1wire_priv_s stm32_1wire6_priv = @@ -331,7 +298,6 @@ static const struct stm32_1wire_config_s stm32_1wire7_config = .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_UART7_TX), .irq = STM32_IRQ_UART7, - .vector = stm32_interrupt_1wire7, }; static struct stm32_1wire_priv_s stm32_1wire7_priv = @@ -351,7 +317,6 @@ static const struct stm32_1wire_config_s stm32_1wire8_config = .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_UART8_TX), .irq = STM32_IRQ_UART8, - .vector = stm32_interrupt_1wire8, }; static struct stm32_1wire_priv_s stm32_1wire8_priv = @@ -679,7 +644,7 @@ static int stm32_1wire_init(FAR struct stm32_1wire_priv_s *priv) stm32_configgpio(config->data_pin); - ret = irq_attach(config->irq, config->vector); + ret = irq_attach(config->irq, stm32_1wire_isr, priv); if (ret == OK) { up_enable_irq(config->irq); @@ -917,9 +882,13 @@ static int stm32_1wire_process(struct stm32_1wire_priv_s *priv, * Common Interrupt Service Routine ****************************************************************************/ -static int stm32_1wire_isr(struct stm32_1wire_priv_s *priv) +static int stm32_1wire_isr(int irq, void *context, void *arg) { - uint32_t sr, dr; + struct stm32_1wire_priv_s *priv = (struct stm32_1wire_priv_s *)arg; + uint32_t sr; + uint32_t dr; + + DEBUGASSERT(priv != NULL); /* Get the masked USART status word. */ @@ -1041,55 +1010,6 @@ static int stm32_1wire_isr(struct stm32_1wire_priv_s *priv) return OK; } -#ifdef CONFIG_STM32_USART1_1WIREDRIVER -static int stm32_interrupt_1wire1(int irq, void *context) -{ - return stm32_1wire_isr(&stm32_1wire1_priv); -} -#endif -#ifdef CONFIG_STM32_USART2_1WIREDRIVER -static int stm32_interrupt_1wire2(int irq, void *context) -{ - return stm32_1wire_isr(&stm32_1wire2_priv); -} -#endif -#ifdef CONFIG_STM32_USART3_1WIREDRIVER -static int stm32_interrupt_1wire3(int irq, void *context) -{ - return stm32_1wire_isr(&stm32_1wire3_priv); -} -#endif -#ifdef CONFIG_STM32_UART4_1WIREDRIVER -static int stm32_interrupt_1wire4(int irq, void *context) -{ - return stm32_1wire_isr(&stm32_1wire4_priv); -} -#endif -#ifdef CONFIG_STM32_UART5_1WIREDRIVER -static int stm32_interrupt_1wire5(int irq, void *context) -{ - return stm32_1wire_isr(&stm32_1wire5_priv); -} -#endif -#ifdef CONFIG_STM32_USART6_1WIREDRIVER -static int stm32_interrupt_1wire6(int irq, void *context) -{ - return stm32_1wire_isr(&stm32_1wire6_priv); -} -#endif -#ifdef CONFIG_STM32_UART7_1WIREDRIVER -static int stm32_interrupt_1wire7(int irq, void *context) -{ - return stm32_1wire_isr(&stm32_1wire7_priv); -} -#endif -#ifdef CONFIG_STM32_UART8_1WIREDRIVER -static int stm32_interrupt_1wire8(int irq, void *context) -{ - return stm32_1wire_isr(&stm32_1wire8_priv); -} -#endif - /**************************************************************************** * Name: stm32_1wire_reset * diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c index 5ede920b24b..ef91b77b40f 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/stm32/stm32_adc.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_adc.c * - * Copyright (C) 2011, 2013, 2015-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013, 2015-2017 Gregory Nutt. All rights reserved. * Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved. * Authors: Gregory Nutt * Diego Sanchez @@ -58,6 +58,7 @@ #include #include #include +#include #include "up_internal.h" #include "up_arch.h" @@ -363,20 +364,20 @@ static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset); static int adc_interrupt(FAR struct adc_dev_s *dev); #if defined(STM32_IRQ_ADC1) && defined(CONFIG_STM32_ADC1) -static int adc1_interrupt(int irq, FAR void *context); +static int adc1_interrupt(int irq, FAR void *context, FAR void *arg); #endif #if defined(STM32_IRQ_ADC12) && (defined(CONFIG_STM32_ADC1) || \ defined(CONFIG_STM32_ADC2)) -static int adc12_interrupt(int irq, FAR void *context); +static int adc12_interrupt(int irq, FAR void *context, FAR void *arg); #endif #if (defined(STM32_IRQ_ADC3) && defined(CONFIG_STM32_ADC3)) -static int adc3_interrupt(int irq, FAR void *context); +static int adc3_interrupt(int irq, FAR void *context, FAR void *arg); #endif #if defined(STM32_IRQ_ADC4) && defined(CONFIG_STM32_ADC4) -static int adc4_interrupt(int irq, FAR void *context); +static int adc4_interrupt(int irq, FAR void *context, FAR void *arg); #endif #if defined(STM32_IRQ_ADC) -static int adc123_interrupt(int irq, FAR void *context); +static int adc123_interrupt(int irq, FAR void *context, FAR void *arg); #endif /* ADC Driver Methods */ @@ -2136,7 +2137,7 @@ static int adc_setup(FAR struct adc_dev_s *dev) /* Attach the ADC interrupt */ - ret = irq_attach(priv->irq, priv->isr); + ret = irq_attach(priv->irq, priv->isr, NULL); if (ret < 0) { ainfo("irq_attach failed: %d\n", ret); @@ -2831,7 +2832,7 @@ static int adc_interrupt(FAR struct adc_dev_s *dev) ****************************************************************************/ #if defined(STM32_IRQ_ADC1) -static int adc1_interrupt(int irq, FAR void *context) +static int adc1_interrupt(int irq, FAR void *context, FAR void *arg) { adc_interrupt(&g_adcdev1); @@ -2853,7 +2854,7 @@ static int adc1_interrupt(int irq, FAR void *context) #if defined(STM32_IRQ_ADC12) && \ (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) -static int adc12_interrupt(int irq, FAR void *context) +static int adc12_interrupt(int irq, FAR void *context, FAR void *arg) { #ifdef CONFIG_STM32_ADC1 adc_interrupt(&g_adcdev1); @@ -2880,7 +2881,7 @@ static int adc12_interrupt(int irq, FAR void *context) ****************************************************************************/ #if defined(STM32_IRQ_ADC3) && defined(CONFIG_STM32_ADC3) -static int adc3_interrupt(int irq, FAR void *context) +static int adc3_interrupt(int irq, FAR void *context, FAR void *arg) { adc_interrupt(&g_adcdev3); @@ -2901,7 +2902,7 @@ static int adc3_interrupt(int irq, FAR void *context) ****************************************************************************/ #if defined(STM32_IRQ_ADC4) && defined(CONFIG_STM32_ADC4) -static int adc4_interrupt(int irq, FAR void *context) +static int adc4_interrupt(int irq, FAR void *context, FAR void *arg) { adc_interrupt(&g_adcdev4); return OK; @@ -2921,7 +2922,7 @@ static int adc4_interrupt(int irq, FAR void *context) ****************************************************************************/ #if defined(STM32_IRQ_ADC) -static int adc123_interrupt(int irq, FAR void *context) +static int adc123_interrupt(int irq, FAR void *context, FAR void *arg) { #ifdef CONFIG_STM32_ADC1 adc_interrupt(&g_adcdev1); diff --git a/arch/arm/src/stm32/stm32_allocateheap.c b/arch/arm/src/stm32/stm32_allocateheap.c index 92a3fcdd810..3e6a73f2cd7 100644 --- a/arch/arm/src/stm32/stm32_allocateheap.c +++ b/arch/arm/src/stm32/stm32_allocateheap.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/up_allocateheap.c + * arch/arm/src/stm32/stm32_allocateheap.c * * Copyright (C) 2011-2013, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -222,6 +222,76 @@ # endif # endif +/* All members of the STM32F33xxx families have 16 Kbi ram and 4 KB CCM SRAM. + * No external RAM is supported (the F3 family has no FSMC). + * + * As a complication, CCM SRAM cannot be used for DMA. So, if STM32 DMA is + * enabled, CCM SRAM should probably be excluded from the heap. + */ +#elif defined(CONFIG_STM32_STM32F33XX) + + /* Set the end of system SRAM */ + +# define SRAM1_END CONFIG_RAM_END + +/* Set the range of CCM SRAM as well (although we may not use it) */ + +# define SRAM2_START 0x10000000 +# define SRAM2_END 0x10001000 + + /* There is no FSMC */ + +# undef CONFIG_STM32_FSMC_SRAM + + /* There are 2 possible SRAM configurations: + * + * Configuration 1. System SRAM (only) + * CONFIG_MM_REGIONS == 1 + * CONFIG_STM32_CCMEXCLUDE defined + * Configuration 2. System SRAM and CCM SRAM + * CONFIG_MM_REGIONS == 2 + * CONFIG_STM32_CCMEXCLUDE NOT defined + */ + +# if CONFIG_MM_REGIONS < 2 + + /* Only one memory region. Force Configuration 1 */ + +# ifndef CONFIG_STM32_CCMEXCLUDE +# if CONFIG_STM32_HAVE_CCM +# warning "CCM SRAM excluded from the heap" +# endif +# define CONFIG_STM32_CCMEXCLUDE 1 +# endif + + /* CONFIG_MM_REGIONS may be 2 if CCM SRAM is included in the head */ + +# elif CONFIG_MM_REGIONS >= 2 +# if CONFIG_MM_REGIONS > 2 +# error "No more than two memory regions can be supported (CONFIG_MM_REGIONS)" +# undef CONFIG_MM_REGIONS +# define CONFIG_MM_REGIONS 2 +# endif + + /* Two memory regions is okay if CCM SRAM is not disabled. */ + +# ifdef CONFIG_STM32_CCMEXCLUDE + + /* Configuration 1: CONFIG_MM_REGIONS should have been 2 */ + +# error "CONFIG_MM_REGIONS >= 2 but but CCM SRAM is excluded (CONFIG_STM32_CCMEXCLUDE)" +# undef CONFIG_MM_REGIONS +# define CONFIG_MM_REGIONS 1 +# else + + /* Configuration 2: DMA should be disabled */ + +# ifdef CONFIG_ARCH_DMA +# warning "CCM SRAM is included in the heap AND DMA is enabled" +# endif +# endif +# endif + /* All members of the STM32F37xxx families have 16-32 Kib ram in a single * bank. No external RAM is supported (the F3 family has no FSMC). */ @@ -246,7 +316,6 @@ # error "CONFIG_MM_REGIONS > 1. The STM32L15X has only one memory region." # endif - /* Most members of both the STM32F20xxx and STM32F40xxx families have 128Kib * in two banks: * diff --git a/arch/arm/src/stm32/stm32_can.c b/arch/arm/src/stm32/stm32_can.c index ed973d57bd0..d90e5cd06da 100644 --- a/arch/arm/src/stm32/stm32_can.c +++ b/arch/arm/src/stm32/stm32_can.c @@ -159,10 +159,10 @@ static bool stm32can_txempty(FAR struct can_dev_s *dev); /* CAN interrupt handling */ -static int stm32can_rxinterrupt(int irq, FAR void *context, int rxmb); -static int stm32can_rx0interrupt(int irq, FAR void *context); -static int stm32can_rx1interrupt(int irq, FAR void *context); -static int stm32can_txinterrupt(int irq, FAR void *context); +static int stm32can_rxinterrupt(FAR struct can_dev_s *dev, int rxmb); +static int stm32can_rx0interrupt(int irq, FAR void *context, FAR void *arg); +static int stm32can_rx1interrupt(int irq, FAR void *context, FAR void *arg); +static int stm32can_txinterrupt(int irq, FAR void *context, FAR void *arg); /* Initialization */ @@ -654,7 +654,7 @@ static int stm32can_setup(FAR struct can_dev_s *dev) * The others are not used. */ - ret = irq_attach(priv->canrx[0], stm32can_rx0interrupt); + ret = irq_attach(priv->canrx[0], stm32can_rx0interrupt, dev); if (ret < 0) { canerr("ERROR: Failed to attach CAN%d RX0 IRQ (%d)", @@ -662,7 +662,7 @@ static int stm32can_setup(FAR struct can_dev_s *dev) return ret; } - ret = irq_attach(priv->canrx[1], stm32can_rx1interrupt); + ret = irq_attach(priv->canrx[1], stm32can_rx1interrupt, dev); if (ret < 0) { canerr("ERROR: Failed to attach CAN%d RX1 IRQ (%d)", @@ -670,7 +670,7 @@ static int stm32can_setup(FAR struct can_dev_s *dev) return ret; } - ret = irq_attach(priv->cantx, stm32can_txinterrupt); + ret = irq_attach(priv->cantx, stm32can_txinterrupt, dev); if (ret < 0) { canerr("ERROR: Failed to attach CAN%d TX IRQ (%d)", @@ -1371,9 +1371,8 @@ static bool stm32can_txempty(FAR struct can_dev_s *dev) * ****************************************************************************/ -static int stm32can_rxinterrupt(int irq, FAR void *context, int rxmb) +static int stm32can_rxinterrupt(FAR struct can_dev_s *dev, int rxmb) { - FAR struct can_dev_s *dev = NULL; FAR struct stm32_can_s *priv; struct can_hdr_s hdr; uint8_t data[CAN_MAXDATALEN]; @@ -1381,24 +1380,7 @@ static int stm32can_rxinterrupt(int irq, FAR void *context, int rxmb) int npending; int ret; -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) - if (g_can1priv.canrx[rxmb] == irq) - { - dev = &g_can1dev; - } - else if (g_can2priv.canrx[rxmb] == irq) - { - dev = &g_can2dev; - } - else - { - PANIC(); - } -#elif defined(CONFIG_STM32_CAN1) - dev = &g_can1dev; -#else /* defined(CONFIG_STM32_CAN2) */ - dev = &g_can2dev; -#endif + DEBUGASSERT(dev != NULL && dev->cd_priv != NULL); priv = dev->cd_priv; /* Verify that a message is pending in the FIFO */ @@ -1506,9 +1488,10 @@ errout: * ****************************************************************************/ -static int stm32can_rx0interrupt(int irq, FAR void *context) +static int stm32can_rx0interrupt(int irq, FAR void *context, FAR void *arg) { - return stm32can_rxinterrupt(irq, context, 0); + FAR struct can_dev_s *dev = (FAR struct can_dev_s *)arg; + return stm32can_rxinterrupt(dev, 0); } /**************************************************************************** @@ -1526,9 +1509,10 @@ static int stm32can_rx0interrupt(int irq, FAR void *context) * ****************************************************************************/ -static int stm32can_rx1interrupt(int irq, FAR void *context) +static int stm32can_rx1interrupt(int irq, FAR void *context, FAR void *arg) { - return stm32can_rxinterrupt(irq, context, 1); + FAR struct can_dev_s *dev = (FAR struct can_dev_s *)arg; + return stm32can_rxinterrupt(dev, 1); } /**************************************************************************** @@ -1546,30 +1530,13 @@ static int stm32can_rx1interrupt(int irq, FAR void *context) * ****************************************************************************/ -static int stm32can_txinterrupt(int irq, FAR void *context) +static int stm32can_txinterrupt(int irq, FAR void *context, FAR void *arg) { - FAR struct can_dev_s *dev = NULL; + FAR struct can_dev_s *dev = (FAR struct can_dev_s *)arg; FAR struct stm32_can_s *priv; uint32_t regval; -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) - if (g_can1priv.cantx == irq) - { - dev = &g_can1dev; - } - else if (g_can2priv.cantx == irq) - { - dev = &g_can2dev; - } - else - { - PANIC(); - } -#elif defined(CONFIG_STM32_CAN1) - dev = &g_can1dev; -#else /* defined(CONFIG_STM32_CAN2) */ - dev = &g_can2dev; -#endif + DEBUGASSERT(dev != NULL && dev->cd_priv != NULL); priv = dev->cd_priv; /* Get the transmit status */ diff --git a/arch/arm/src/stm32/stm32_capture.c b/arch/arm/src/stm32/stm32_capture.c index e5fefa74cfc..ac1cb69573c 100644 --- a/arch/arm/src/stm32/stm32_capture.c +++ b/arch/arm/src/stm32/stm32_capture.c @@ -1,5 +1,5 @@ /************************************************************************************ - * arm/arm/src/stm32/stm32_capture.c + * arch/arm/src/stm32/stm32_capture.c * * Copyright (C) 2015 Bouteville Pierre-Noel. All rights reserved. * Author: Bouteville Pierre-Noel @@ -736,13 +736,13 @@ static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler) /* Otherwise set callback and enable interrupt */ - irq_attach(irq, handler); + irq_attach(irq, handler, NULL); up_enable_irq(irq); #ifdef USE_ADVENCED_TIM if (priv->irq_of) { - irq_attach(priv->irq_of, handler); + irq_attach(priv->irq_of, handler, NULL); up_enable_irq(priv->irq_of); } #endif diff --git a/arch/arm/src/stm32/stm32_capture.h b/arch/arm/src/stm32/stm32_capture.h index d015c80e562..626bbe19496 100644 --- a/arch/arm/src/stm32/stm32_capture.h +++ b/arch/arm/src/stm32/stm32_capture.h @@ -194,7 +194,7 @@ FAR struct stm32_cap_dev_s *stm32_cap_init(int timer); /* Power-down timer, mark it as unused */ -int stm32_cap_deinit(FAR struct stm32_cap_dev_s * dev); +int stm32_cap_deinit(FAR struct stm32_cap_dev_s *dev); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32/stm32_ccm.c b/arch/arm/src/stm32/stm32_ccm.c index c3f72a398ef..cdf7fb8805b 100644 --- a/arch/arm/src/stm32/stm32_ccm.c +++ b/arch/arm/src/stm32/stm32_ccm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/common/stm32_ccm.c + * arch/arm/src/stm32/stm32_ccm.c * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -62,4 +62,4 @@ struct mm_heap_s g_ccm_heap; * Public Function Prototypes ****************************************************************************/ -#endif /* HAVE_CCM_HEAP */ \ No newline at end of file +#endif /* HAVE_CCM_HEAP */ diff --git a/arch/arm/src/stm32/stm32_ccm.h b/arch/arm/src/stm32/stm32_ccm.h index ce441ff7601..20cc650eee8 100644 --- a/arch/arm/src/stm32/stm32_ccm.h +++ b/arch/arm/src/stm32/stm32_ccm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/common/stm32_ccm.h + * arch/arm/src/stm32/stm32_ccm.h * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -58,7 +58,8 @@ #if defined(CONFIG_STM32_STM32F30XX) # define CCM_START 0x10000000 # define CCM_END 0x10002000 -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \ + defined(CONFIG_STM32_STM32F33XX) # define CCM_START 0x10000000 # define CCM_END 0x10010000 #else diff --git a/arch/arm/src/stm32/stm32_dac.c b/arch/arm/src/stm32/stm32_dac.c index 796bb81d213..e12c9f65c5f 100644 --- a/arch/arm/src/stm32/stm32_dac.c +++ b/arch/arm/src/stm32/stm32_dac.c @@ -94,6 +94,12 @@ # undef CONFIG_STM32_DAC1_DMA # undef CONFIG_STM32_DAC2_DMA # endif +# elif defined(CONFIG_STM32_STM32F33XX) +# ifndef CONFIG_STM32_DMA1 +# warning "STM32 F334 DAC DMA support requires CONFIG_STM32_DMA1" +# undef CONFIG_STM32_DAC1_DMA +# undef CONFIG_STM32_DAC2_DMA +# endif # elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) # ifndef CONFIG_STM32_DMA1 # warning "STM32 F4 DAC DMA support requires CONFIG_STM32_DMA1" @@ -147,7 +153,8 @@ # define DAC_DMA 2 # define DAC1_DMA_CHAN DMACHAN_DAC_CHAN1 # define DAC2_DMA_CHAN DMACHAN_DAC_CHAN2 -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \ + defined(CONFIG_STM32_STM32F33XX) # define HAVE_DMA 1 # define DAC_DMA 1 # define DAC1_DMA_CHAN DMAMAP_DAC1 @@ -375,7 +382,7 @@ static void tim_putreg(FAR struct stm32_chan_s *chan, int offset, /* Interrupt handler */ #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) -static int dac_interrupt(int irq, FAR void *context); +static int dac_interrupt(int irq, FAR void *context, FAR void *arg); #endif /* DAC methods */ @@ -614,7 +621,7 @@ static void tim_modifyreg(FAR struct stm32_chan_s *chan, int offset, ****************************************************************************/ #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) -static int dac_interrupt(int irq, FAR void *context) +static int dac_interrupt(int irq, FAR void *context, FAR void *arg) { #warning "Missing logic" return OK; @@ -847,7 +854,6 @@ static int dac_timinit(FAR struct stm32_chan_s *chan) * default) will be enabled */ - pclk = STM32_TIM27_FREQUENCY; regaddr = STM32_RCC_APB1ENR; switch (chan->timer) @@ -855,31 +861,37 @@ static int dac_timinit(FAR struct stm32_chan_s *chan) #ifdef NEED_TIM2 case 2: setbits = RCC_APB1ENR_TIM2EN; + pclk = BOARD_TIM2_FREQUENCY; break; #endif #ifdef NEED_TIM3 case 3: setbits = RCC_APB1ENR_TIM3EN; + pclk = BOARD_TIM3_FREQUENCY; break; #endif #ifdef NEED_TIM4 case 4: setbits = RCC_APB1ENR_TIM4EN; + pclk = BOARD_TIM4_FREQUENCY; break; #endif #ifdef NEED_TIM5 case 5: setbits = RCC_APB1ENR_TIM5EN; + pclk = BOARD_TIM5_FREQUENCY; break; #endif #ifdef NEED_TIM6 case 6: setbits = RCC_APB1ENR_TIM6EN; + pclk = BOARD_TIM6_FREQUENCY; break; #endif #ifdef NEED_TIM7 case 7: setbits = RCC_APB1ENR_TIM7EN; + pclk = BOARD_TIM7_FREQUENCY; break; #endif #ifdef NEED_TIM8 @@ -891,7 +903,7 @@ static int dac_timinit(FAR struct stm32_chan_s *chan) #endif default: aerr("ERROR: Could not enable timer\n"); - break; + return -EINVAL; } /* Enable the timer. */ diff --git a/arch/arm/src/stm32/stm32_dma.c b/arch/arm/src/stm32/stm32_dma.c index 4b694e7ccb9..0de9cdcc3b8 100644 --- a/arch/arm/src/stm32/stm32_dma.c +++ b/arch/arm/src/stm32/stm32_dma.c @@ -56,7 +56,8 @@ */ #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) # include "stm32f10xxx_dma.c" #elif defined(CONFIG_STM32_STM32F20XX) # include "stm32f20xxx_dma.c" diff --git a/arch/arm/src/stm32/stm32_dma.h b/arch/arm/src/stm32/stm32_dma.h index d26428c35bb..36c21f3ca60 100644 --- a/arch/arm/src/stm32/stm32_dma.h +++ b/arch/arm/src/stm32/stm32_dma.h @@ -48,7 +48,8 @@ /* Include the correct DMA register definitions for this STM32 family */ #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) # include "chip/stm32f10xxx_dma.h" #elif defined(CONFIG_STM32_STM32F20XX) # include "chip/stm32f20xxx_dma.h" @@ -63,7 +64,8 @@ */ #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) # define DMA_STATUS_FEIF 0 /* (Not available in F1) */ # define DMA_STATUS_DMEIF 0 /* (Not available in F1) */ # define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */ @@ -106,7 +108,8 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); #ifdef CONFIG_DEBUG_DMA_INFO #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) struct stm32_dmaregs_s { uint32_t isr; diff --git a/arch/arm/src/stm32/stm32_dma2d.c b/arch/arm/src/stm32/stm32_dma2d.c index c4ef73fc2be..8611ab2c1a3 100644 --- a/arch/arm/src/stm32/stm32_dma2d.c +++ b/arch/arm/src/stm32/stm32_dma2d.c @@ -285,7 +285,7 @@ static const uintptr_t stm32_cmar_layer_t[DMA2D_NLAYERS - 1] = static int stm32_dma2d_pixelformat(uint8_t fmt, uint8_t *fmtmap); static int stm32_dma2d_bpp(uint8_t fmt, uint8_t *bpp); static void stm32_dma2d_control(uint32_t setbits, uint32_t clrbits); -static int stm32_dma2dirq(int irq, void *context); +static int stm32_dma2dirq(int irq, void *context, FAR void *arg); static int stm32_dma2d_waitforirq(void); static int stm32_dma2d_start(void); #ifdef CONFIG_STM32_DMA2D_L8 @@ -425,7 +425,7 @@ static void stm32_dma2d_control(uint32_t setbits, uint32_t clrbits) * ****************************************************************************/ -static int stm32_dma2dirq(int irq, void *context) +static int stm32_dma2dirq(int irq, void *context, FAR void *arg) { uint32_t regval = getreg32(STM32_DMA2D_ISR); FAR struct stm32_interrupt_s *priv = &g_interrupt; @@ -2190,7 +2190,7 @@ int up_dma2dinitialize(void) /* Attach DMA2D interrupt vector */ - (void)irq_attach(g_interrupt.irq, stm32_dma2dirq); + (void)irq_attach(g_interrupt.irq, stm32_dma2dirq, NULL); /* Enable the IRQ at the NVIC */ diff --git a/arch/arm/src/stm32/stm32_dma2d.h b/arch/arm/src/stm32/stm32_dma2d.h index 7755ffe39d3..ddaeada7b20 100644 --- a/arch/arm/src/stm32/stm32_dma2d.h +++ b/arch/arm/src/stm32/stm32_dma2d.h @@ -83,7 +83,7 @@ * ****************************************************************************/ -FAR struct dma2d_layer_s * stm32_dma2dinitltdc(FAR struct stm32_ltdc_s *layer); +FAR struct dma2d_layer_s *stm32_dma2dinitltdc(FAR struct stm32_ltdc_s *layer); # endif /* CONFIG_STM32_LTDC_INTERFACE */ #endif /* CONFIG_STM32_DMA2D */ diff --git a/arch/arm/src/stm32/stm32_dumpgpio.c b/arch/arm/src/stm32/stm32_dumpgpio.c index a8da3160d19..2540ffdcbcc 100644 --- a/arch/arm/src/stm32/stm32_dumpgpio.c +++ b/arch/arm/src/stm32/stm32_dumpgpio.c @@ -172,7 +172,8 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) g_portchar[port], getreg32(STM32_RCC_AHBENR)); } -#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F33XX) DEBUGASSERT(port < STM32_NGPIO_PORTS); _info("GPIO%c pinset: %08x base: %08x -- %s\n", diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c index 52dcaacd728..ac19abc52d4 100644 --- a/arch/arm/src/stm32/stm32_eth.c +++ b/arch/arm/src/stm32/stm32_eth.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_eth.c * - * Copyright (C) 2011-2012, 2014, 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2012, 2014, 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -658,7 +658,7 @@ static void stm32_freeframe(FAR struct stm32_ethmac_s *priv); static void stm32_txdone(FAR struct stm32_ethmac_s *priv); static void stm32_interrupt_work(FAR void *arg); -static int stm32_interrupt(int irq, FAR void *context); +static int stm32_interrupt(int irq, FAR void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -1927,17 +1927,32 @@ static void stm32_txdone(FAR struct stm32_ethmac_s *priv) if (priv->inflight <= 0) { + int delay; + /* Cancel the TX timeout */ wd_cancel(priv->txtimeout); - /* Then make sure that the TX poll timer is running (if it is already - * running, the following would restart it). This is necessary to - * avoid certain race conditions where the polling sequence can be - * interrupted. + /* Check if the poll timer is running. If it is not, then start it + * now. There is a race condition here: We may test the time + * remaining on the poll timer and determine that it is still running, + * but then the timer expires immiately. That should not be problem, + * however, the poll timer is queued processing should be in the work + * queue and should execute immediately after we complete the TX poll. + * Inefficient, but not fatal. */ - (void)wd_start(priv->txpoll, STM32_WDDELAY, stm32_poll_expiry, 1, priv); + delay = wd_gettime(priv->txpoll); + if (delay <= 0) + { + /* The poll timer is not running .. restart it. This is necessary + * to avoid certain race conditions where the polling sequence can + * be interrupted. + */ + + (void)wd_start(priv->txpoll, STM32_WDDELAY, stm32_poll_expiry, + 1, priv); + } /* And disable further TX interrupts. */ @@ -2073,7 +2088,7 @@ static void stm32_interrupt_work(FAR void *arg) * ****************************************************************************/ -static int stm32_interrupt(int irq, FAR void *context) +static int stm32_interrupt(int irq, FAR void *context, FAR void *arg) { FAR struct stm32_ethmac_s *priv = &g_stm32ethmac[0]; uint32_t dmasr; @@ -4008,7 +4023,7 @@ int stm32_ethinitialize(int intf) /* Attach the IRQ to the driver */ - if (irq_attach(STM32_IRQ_ETH, stm32_interrupt)) + if (irq_attach(STM32_IRQ_ETH, stm32_interrupt, NULL)) { /* We could not attach the ISR to the interrupt */ diff --git a/arch/arm/src/stm32/stm32_exti.h b/arch/arm/src/stm32/stm32_exti.h index 6a34582c676..3a395abe372 100644 --- a/arch/arm/src/stm32/stm32_exti.h +++ b/arch/arm/src/stm32/stm32_exti.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/stm32/stm32_exti.h * - * Copyright (C) 2009, 2012, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2012, 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -77,6 +77,7 @@ extern "C" * - rising/falling edge: enables * - event: generate event when set * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback * * Returns: * The previous value of the interrupt handler function pointer. This value may, @@ -86,7 +87,7 @@ extern "C" ************************************************************************************/ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func); + bool event, xcpt_t func, void *arg); /************************************************************************************ * Name: stm32_exti_alarm @@ -98,6 +99,7 @@ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, * - rising/falling edge: enables interrupt on rising/falling edges * - event: generate event when set * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback * * Returns: * The previous value of the interrupt handler function pointer. This value may, @@ -107,7 +109,8 @@ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ************************************************************************************/ #ifdef CONFIG_RTC_ALARM -xcpt_t stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func); +xcpt_t stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, + void *arg); #endif #undef EXTERN diff --git a/arch/arm/src/stm32/stm32_exti_alarm.c b/arch/arm/src/stm32/stm32_exti_alarm.c index 2e6d582a4aa..67902e11c8e 100644 --- a/arch/arm/src/stm32/stm32_exti_alarm.c +++ b/arch/arm/src/stm32/stm32_exti_alarm.c @@ -59,7 +59,8 @@ /* Interrupt handlers attached to the ALARM EXTI */ -static xcpt_t stm32_exti_callback; +static xcpt_t g_alarm_callback; +static void *g_callback_arg; /**************************************************************************** * Private Functions @@ -73,7 +74,7 @@ static xcpt_t stm32_exti_callback; * ****************************************************************************/ -static int stm32_exti_alarm_isr(int irq, void *context) +static int stm32_exti_alarm_isr(int irq, void *context, FAR void *arg) { int ret = OK; @@ -83,9 +84,9 @@ static int stm32_exti_alarm_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32_exti_callback) + if (g_alarm_callback) { - ret = stm32_exti_callback(irq, context); + ret = g_alarm_callback(irq, context, g_callback_arg); } return ret; @@ -105,6 +106,7 @@ static int stm32_exti_alarm_isr(int irq, void *context) * - rising/falling edge: enables interrupt on rising/falling edget * - event: generate event when set * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback * * Returns: * The previous value of the interrupt handler function pointer. This @@ -114,20 +116,21 @@ static int stm32_exti_alarm_isr(int irq, void *context) ****************************************************************************/ xcpt_t stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, - xcpt_t func) + xcpt_t func, void *arg) { xcpt_t oldhandler; /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ - oldhandler = stm32_exti_callback; - stm32_exti_callback = func; + oldhandler = g_alarm_callback; + g_alarm_callback = func; + g_callback_arg = arg; /* Install external interrupt handlers (if not already attached) */ if (func) { - irq_attach(STM32_IRQ_RTCALRM, stm32_exti_alarm_isr); + irq_attach(STM32_IRQ_RTCALRM, stm32_exti_alarm_isr, NULL); up_enable_irq(STM32_IRQ_RTCALRM); } else diff --git a/arch/arm/src/stm32/stm32_exti_gpio.c b/arch/arm/src/stm32/stm32_exti_gpio.c index 6aa2cf4be2b..5945c35e5c9 100644 --- a/arch/arm/src/stm32/stm32_exti_gpio.c +++ b/arch/arm/src/stm32/stm32_exti_gpio.c @@ -55,13 +55,23 @@ #include "stm32_gpio.h" #include "stm32_exti.h" +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct gpio_callback_s +{ + xcpt_t callback; + void *arg; +}; + /**************************************************************************** * Private Data ****************************************************************************/ /* Interrupt handlers attached to each EXTI */ -static xcpt_t stm32_exti_callbacks[16]; +static struct gpio_callback_s g_gpio_callbacks[16]; /**************************************************************************** * Private Functions @@ -71,7 +81,7 @@ static xcpt_t stm32_exti_callbacks[16]; * Interrupt Service Routines - Dispatchers ****************************************************************************/ -static int stm32_exti0_isr(int irq, void *context) +static int stm32_exti0_isr(int irq, void *context, void *arg) { int ret = OK; @@ -81,15 +91,18 @@ static int stm32_exti0_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32_exti_callbacks[0]) + if (g_gpio_callbacks[0].callback != NULL) { - ret = stm32_exti_callbacks[0](irq, context); + xcpt_t callback = g_gpio_callbacks[0].callback; + void *cbarg = g_gpio_callbacks[0].arg; + + ret = callback(irq, context, cbarg); } return ret; } -static int stm32_exti1_isr(int irq, void *context) +static int stm32_exti1_isr(int irq, void *context, void *arg) { int ret = OK; @@ -99,15 +112,18 @@ static int stm32_exti1_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32_exti_callbacks[1]) + if (g_gpio_callbacks[1].callback != NULL) { - ret = stm32_exti_callbacks[1](irq, context); + xcpt_t callback = g_gpio_callbacks[1].callback; + void *cbarg = g_gpio_callbacks[1].arg; + + ret = callback(irq, context, cbarg); } return ret; } -static int stm32_exti2_isr(int irq, void *context) +static int stm32_exti2_isr(int irq, void *context, void *arg) { int ret = OK; @@ -117,15 +133,18 @@ static int stm32_exti2_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32_exti_callbacks[2]) + if (g_gpio_callbacks[2].callback != NULL) { - ret = stm32_exti_callbacks[2](irq, context); + xcpt_t callback = g_gpio_callbacks[2].callback; + void *cbarg = g_gpio_callbacks[2].arg; + + ret = callback(irq, context, cbarg); } return ret; } -static int stm32_exti3_isr(int irq, void *context) +static int stm32_exti3_isr(int irq, void *context, void * arg) { int ret = OK; @@ -135,15 +154,18 @@ static int stm32_exti3_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32_exti_callbacks[3]) + if (g_gpio_callbacks[3].callback != NULL) { - ret = stm32_exti_callbacks[3](irq, context); + xcpt_t callback = g_gpio_callbacks[3].callback; + void *cbarg = g_gpio_callbacks[3].arg; + + ret = callback(irq, context, cbarg); } return ret; } -static int stm32_exti4_isr(int irq, void *context) +static int stm32_exti4_isr(int irq, void *context, void *arg) { int ret = OK; @@ -153,15 +175,19 @@ static int stm32_exti4_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32_exti_callbacks[4]) + if (g_gpio_callbacks[4].callback != NULL) { - ret = stm32_exti_callbacks[4](irq, context); + xcpt_t callback = g_gpio_callbacks[4].callback; + void *cbarg = g_gpio_callbacks[4].arg; + + ret = callback(irq, context, cbarg); } return ret; } -static int stm32_exti_multiisr(int irq, void *context, int first, int last) +static int stm32_exti_multiisr(int irq, void *context, void *arg, + int first, int last) { uint32_t pr; int pin; @@ -186,10 +212,14 @@ static int stm32_exti_multiisr(int irq, void *context, int first, int last) /* And dispatch the interrupt to the handler */ - if (stm32_exti_callbacks[pin]) + if (g_gpio_callbacks[pin].callback != NULL) { - int tmp = stm32_exti_callbacks[pin](irq, context); - if (tmp != OK) + xcpt_t callback = g_gpio_callbacks[pin].callback; + void *cbarg = g_gpio_callbacks[pin].arg; + int tmp; + + tmp = callback(irq, context, cbarg); + if (tmp < 0) { ret = tmp; } @@ -200,14 +230,14 @@ static int stm32_exti_multiisr(int irq, void *context, int first, int last) return ret; } -static int stm32_exti95_isr(int irq, void *context) +static int stm32_exti95_isr(int irq, void *context, void *arg) { - return stm32_exti_multiisr(irq, context, 5, 9); + return stm32_exti_multiisr(irq, context, arg, 5, 9); } -static int stm32_exti1510_isr(int irq, void *context) +static int stm32_exti1510_isr(int irq, void *context, void *arg) { - return stm32_exti_multiisr(irq, context, 10, 15); + return stm32_exti_multiisr(irq, context, arg, 10, 15); } /**************************************************************************** @@ -226,6 +256,7 @@ static int stm32_exti1510_isr(int irq, void *context) * - fallingedge: Enables interrupt on falling edges * - event: Generate event when set * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback * * Returns: * The previous value of the interrupt handler function pointer. This @@ -235,15 +266,15 @@ static int stm32_exti1510_isr(int irq, void *context) ****************************************************************************/ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func) + bool event, xcpt_t func, void *arg) { + FAR struct gpio_callback_s *shared_cbs; uint32_t pin = pinset & GPIO_PIN_MASK; uint32_t exti = STM32_EXTI_BIT(pin); int irq; xcpt_t handler; xcpt_t oldhandler = NULL; int nshared; - xcpt_t *shared_cbs; int i; /* Select the interrupt handler for this EXTI pin */ @@ -252,7 +283,7 @@ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, { irq = pin + STM32_IRQ_EXTI0; nshared = 1; - shared_cbs = &stm32_exti_callbacks[pin]; + shared_cbs = &g_gpio_callbacks[pin]; switch (pin) { case 0: @@ -280,27 +311,28 @@ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, { irq = STM32_IRQ_EXTI95; handler = stm32_exti95_isr; - shared_cbs = &stm32_exti_callbacks[5]; + shared_cbs = &g_gpio_callbacks[5]; nshared = 5; } else { irq = STM32_IRQ_EXTI1510; handler = stm32_exti1510_isr; - shared_cbs = &stm32_exti_callbacks[10]; + shared_cbs = &g_gpio_callbacks[10]; nshared = 6; } /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ - oldhandler = stm32_exti_callbacks[pin]; - stm32_exti_callbacks[pin] = func; + oldhandler = g_gpio_callbacks[pin].callback; + g_gpio_callbacks[pin].callback = func; + g_gpio_callbacks[pin].arg = arg; /* Install external interrupt handlers */ if (func) { - irq_attach(irq, handler); + irq_attach(irq, handler, NULL); up_enable_irq(irq); } else @@ -311,7 +343,7 @@ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, for (i = 0; i < nshared; i++) { - if (shared_cbs[i] != NULL) + if (shared_cbs[i].callback != NULL) { break; } diff --git a/arch/arm/src/stm32/stm32_exti_pwr.c b/arch/arm/src/stm32/stm32_exti_pwr.c index f57e85e6ca9..81cad7b5008 100644 --- a/arch/arm/src/stm32/stm32_exti_pwr.c +++ b/arch/arm/src/stm32/stm32_exti_pwr.c @@ -65,11 +65,8 @@ /* Interrupt handlers attached to the PVD EXTI */ -static xcpt_t stm32_exti_pvd_callback; - -/**************************************************************************** - * Public Data - ****************************************************************************/ +static xcpt_t g_pvd_callback; +static void *g_callback_arg; /**************************************************************************** * Private Functions @@ -83,7 +80,7 @@ static xcpt_t stm32_exti_pvd_callback; * ****************************************************************************/ -static int stm32_exti_pvd_isr(int irq, void *context) +static int stm32_exti_pvd_isr(int irq, void *context, FAR void *arg) { int ret = OK; @@ -93,9 +90,9 @@ static int stm32_exti_pvd_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32_exti_pvd_callback) + if (g_pvd_callback != NULL) { - ret = stm32_exti_pvd_callback(irq, context); + ret = g_pvd_callback(irq, context, g_callback_arg); } return ret; @@ -115,6 +112,7 @@ static int stm32_exti_pvd_isr(int irq, void *context) * - rising/falling edge: enables interrupt on rising/falling edge * - event: generate event when set * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback * * Returns: * The previous value of the interrupt handler function pointer. This @@ -124,20 +122,21 @@ static int stm32_exti_pvd_isr(int irq, void *context) ****************************************************************************/ xcpt_t stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, - xcpt_t func) + xcpt_t func, void *arg) { xcpt_t oldhandler; /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ - oldhandler = stm32_exti_pvd_callback; - stm32_exti_pvd_callback = func; + oldhandler = g_pvd_callback; + g_pvd_callback = func; + g_callback_arg = arg; /* Install external interrupt handlers (if not already attached) */ if (func) { - irq_attach(STM32_IRQ_PVD, stm32_exti_pvd_isr); + irq_attach(STM32_IRQ_PVD, stm32_exti_pvd_isr, NULL); up_enable_irq(STM32_IRQ_PVD); } else diff --git a/arch/arm/src/stm32/stm32_exti_pwr.h b/arch/arm/src/stm32/stm32_exti_pwr.h index 4955045a2f1..26be9bb0ef6 100644 --- a/arch/arm/src/stm32/stm32_exti_pwr.h +++ b/arch/arm/src/stm32/stm32_exti_pwr.h @@ -57,6 +57,7 @@ * - rising/falling edge: enables interrupt on rising/falling edge * - event: generate event when set * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback * * Returns: * The previous value of the interrupt handler function pointer. This @@ -66,6 +67,6 @@ ****************************************************************************/ xcpt_t stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, - xcpt_t func); + xcpt_t func, void *arg); #endif /* STM32_EXTI_PWR_H_ */ diff --git a/arch/arm/src/stm32/stm32_gpio.c b/arch/arm/src/stm32/stm32_gpio.c index 63d09e982e4..9eb5fb9597b 100644 --- a/arch/arm/src/stm32/stm32_gpio.c +++ b/arch/arm/src/stm32/stm32_gpio.c @@ -55,8 +55,8 @@ #include "stm32_gpio.h" #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32F40XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX) # include "chip/stm32_syscfg.h" #endif @@ -427,8 +427,8 @@ int stm32_configgpio(uint32_t cfgset) ****************************************************************************/ #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32F40XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX) int stm32_configgpio(uint32_t cfgset) { uintptr_t base; @@ -585,7 +585,8 @@ int stm32_configgpio(uint32_t cfgset) setting = GPIO_OSPEED_50MHz; break; -#if !defined(CONFIG_STM32_STM32F30XX) && !defined(CONFIG_STM32_STM32F37XX) +#if !defined(CONFIG_STM32_STM32F30XX) && !defined(CONFIG_STM32_STM32F33XX) && \ + !defined(CONFIG_STM32_STM32F37XX) case GPIO_SPEED_100MHz: /* 100 MHz High speed output */ setting = GPIO_OSPEED_100MHz; break; @@ -681,8 +682,8 @@ int stm32_unconfiggpio(uint32_t cfgset) #if defined(CONFIG_STM32_STM32F10XX) cfgset |= GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT; #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32F40XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX) cfgset |= GPIO_INPUT | GPIO_FLOAT; #else # error "Unsupported STM32 chip" @@ -707,8 +708,8 @@ void stm32_gpiowrite(uint32_t pinset, bool value) #if defined(CONFIG_STM32_STM32F10XX) uint32_t offset; #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32F40XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX) uint32_t bit; #endif unsigned int port; @@ -741,8 +742,8 @@ void stm32_gpiowrite(uint32_t pinset, bool value) putreg32((1 << pin), base + offset); #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32F40XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX) if (value) { @@ -787,5 +788,6 @@ bool stm32_gpioread(uint32_t pinset) pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); } + return 0; } diff --git a/arch/arm/src/stm32/stm32_gpio.h b/arch/arm/src/stm32/stm32_gpio.h index 34b49bf0d6d..06e09efc2b2 100644 --- a/arch/arm/src/stm32/stm32_gpio.h +++ b/arch/arm/src/stm32/stm32_gpio.h @@ -59,7 +59,8 @@ # include "chip/stm32f10xxx_gpio.h" #elif defined(CONFIG_STM32_STM32F20XX) # include "chip/stm32f20xxx_gpio.h" -#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) # include "chip/stm32f30xxx_gpio.h" #elif defined(CONFIG_STM32_STM32F40XX) # include "chip/stm32f40xxx_gpio.h" @@ -201,8 +202,8 @@ #define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32F40XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX) /* Each port bit of the general-purpose I/O (GPIO) ports can be individually configured * by software in several modes: @@ -491,6 +492,7 @@ bool stm32_gpioread(uint32_t pinset); * - rising/falling edge: enables * - event: generate event when set * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback * * Returns: * The previous value of the interrupt handler function pointer. This value may, @@ -500,7 +502,7 @@ bool stm32_gpioread(uint32_t pinset); ************************************************************************************/ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func); + bool event, xcpt_t func, void *arg); /************************************************************************************ * Function: stm32_dumpgpio diff --git a/arch/arm/src/stm32/stm32_i2c.c b/arch/arm/src/stm32/stm32_i2c.c index 631ba665016..f4c97eca506 100644 --- a/arch/arm/src/stm32/stm32_i2c.c +++ b/arch/arm/src/stm32/stm32_i2c.c @@ -230,7 +230,7 @@ struct stm32_i2c_config_s uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ #ifndef CONFIG_I2C_POLLED - int (*isr)(int, void *); /* Interrupt handler */ + int (*isr)(int, void *, void *); /* Interrupt handler */ uint32_t ev_irq; /* Event IRQ */ uint32_t er_irq; /* Error IRQ */ #endif @@ -317,13 +317,13 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv); #ifndef CONFIG_I2C_POLLED #ifdef CONFIG_STM32_I2C1 -static int stm32_i2c1_isr(int irq, void *context); +static int stm32_i2c1_isr(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_STM32_I2C2 -static int stm32_i2c2_isr(int irq, void *context); +static int stm32_i2c2_isr(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_STM32_I2C3 -static int stm32_i2c3_isr(int irq, void *context); +static int stm32_i2c3_isr(int irq, void *context, FAR void *arg); #endif #endif /* !CONFIG_I2C_POLLED */ @@ -1468,7 +1468,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) #ifndef CONFIG_I2C_POLLED #ifdef CONFIG_STM32_I2C1 -static int stm32_i2c1_isr(int irq, void *context) +static int stm32_i2c1_isr(int irq, void *context, FAR void *arg) { return stm32_i2c_isr(&stm32_i2c1_priv); } @@ -1483,7 +1483,7 @@ static int stm32_i2c1_isr(int irq, void *context) ************************************************************************************/ #ifdef CONFIG_STM32_I2C2 -static int stm32_i2c2_isr(int irq, void *context) +static int stm32_i2c2_isr(int irq, void *context, FAR void *arg) { return stm32_i2c_isr(&stm32_i2c2_priv); } @@ -1498,7 +1498,7 @@ static int stm32_i2c2_isr(int irq, void *context) ************************************************************************************/ #ifdef CONFIG_STM32_I2C3 -static int stm32_i2c3_isr(int irq, void *context) +static int stm32_i2c3_isr(int irq, void *context, FAR void *arg) { return stm32_i2c_isr(&stm32_i2c3_priv); } @@ -1543,8 +1543,8 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv) /* Attach ISRs */ #ifndef CONFIG_I2C_POLLED - irq_attach(priv->config->ev_irq, priv->config->isr); - irq_attach(priv->config->er_irq, priv->config->isr); + irq_attach(priv->config->ev_irq, priv->config->isr, NULL); + irq_attach(priv->config->er_irq, priv->config->isr, NULL); up_enable_irq(priv->config->ev_irq); up_enable_irq(priv->config->er_irq); #endif diff --git a/arch/arm/src/stm32/stm32_i2c.h b/arch/arm/src/stm32/stm32_i2c.h index 7274325f548..f36ee952f55 100644 --- a/arch/arm/src/stm32/stm32_i2c.h +++ b/arch/arm/src/stm32/stm32_i2c.h @@ -44,7 +44,8 @@ #include #include "chip.h" -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F33XX) # include "chip/stm32f30xxx_i2c.h" #else # include "chip/stm32_i2c.h" diff --git a/arch/arm/src/stm32/stm32_i2c_alt.c b/arch/arm/src/stm32/stm32_i2c_alt.c index 545a6473347..f9a2905f0e1 100644 --- a/arch/arm/src/stm32/stm32_i2c_alt.c +++ b/arch/arm/src/stm32/stm32_i2c_alt.c @@ -257,7 +257,7 @@ struct stm32_i2c_config_s uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ #ifndef CONFIG_I2C_POLLED - int (*isr)(int, void *); /* Interrupt handler */ + int (*isr)(int, void *, void *); /* Interrupt handler */ uint32_t ev_irq; /* Event IRQ */ uint32_t er_irq; /* Error IRQ */ #endif @@ -346,13 +346,13 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv); #ifndef CONFIG_I2C_POLLED #ifdef CONFIG_STM32_I2C1 -static int stm32_i2c1_isr(int irq, void *context); +static int stm32_i2c1_isr(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_STM32_I2C2 -static int stm32_i2c2_isr(int irq, void *context); +static int stm32_i2c2_isr(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_STM32_I2C3 -static int stm32_i2c3_isr(int irq, void *context); +static int stm32_i2c3_isr(int irq, void *context, FAR void *arg); #endif #endif /* !CONFIG_I2C_POLLED */ @@ -1899,7 +1899,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) #ifndef CONFIG_I2C_POLLED #ifdef CONFIG_STM32_I2C1 -static int stm32_i2c1_isr(int irq, void *context) +static int stm32_i2c1_isr(int irq, void *context, FAR void *arg) { return stm32_i2c_isr(&stm32_i2c1_priv); } @@ -1914,7 +1914,7 @@ static int stm32_i2c1_isr(int irq, void *context) ************************************************************************************/ #ifdef CONFIG_STM32_I2C2 -static int stm32_i2c2_isr(int irq, void *context) +static int stm32_i2c2_isr(int irq, void *context, FAR void *arg) { return stm32_i2c_isr(&stm32_i2c2_priv); } @@ -1929,7 +1929,7 @@ static int stm32_i2c2_isr(int irq, void *context) ************************************************************************************/ #ifdef CONFIG_STM32_I2C3 -static int stm32_i2c3_isr(int irq, void *context) +static int stm32_i2c3_isr(int irq, void *context, FAR void *arg) { return stm32_i2c_isr(&stm32_i2c3_priv); } @@ -1974,8 +1974,8 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv) /* Attach ISRs */ #ifndef CONFIG_I2C_POLLED - irq_attach(priv->config->ev_irq, priv->config->isr); - irq_attach(priv->config->er_irq, priv->config->isr); + irq_attach(priv->config->ev_irq, priv->config->isr, NULL); + irq_attach(priv->config->er_irq, priv->config->isr, NULL); up_enable_irq(priv->config->ev_irq); up_enable_irq(priv->config->er_irq); #endif diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/stm32/stm32_irq.c index ff40bf8d033..051c9829794 100644 --- a/arch/arm/src/stm32/stm32_irq.c +++ b/arch/arm/src/stm32/stm32_irq.c @@ -161,7 +161,7 @@ static void stm32_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int stm32_nmi(int irq, FAR void *context) +static int stm32_nmi(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -169,7 +169,7 @@ static int stm32_nmi(int irq, FAR void *context) return 0; } -static int stm32_busfault(int irq, FAR void *context) +static int stm32_busfault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); @@ -177,7 +177,7 @@ static int stm32_busfault(int irq, FAR void *context) return 0; } -static int stm32_usagefault(int irq, FAR void *context) +static int stm32_usagefault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); @@ -185,7 +185,7 @@ static int stm32_usagefault(int irq, FAR void *context) return 0; } -static int stm32_pendsv(int irq, FAR void *context) +static int stm32_pendsv(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -193,7 +193,7 @@ static int stm32_pendsv(int irq, FAR void *context) return 0; } -static int stm32_dbgmonitor(int irq, FAR void *context) +static int stm32_dbgmonitor(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -201,7 +201,7 @@ static int stm32_dbgmonitor(int irq, FAR void *context) return 0; } -static int stm32_reserved(int irq, FAR void *context) +static int stm32_reserved(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -376,8 +376,8 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32_IRQ_SVCALL, up_svcall); - irq_attach(STM32_IRQ_HARDFAULT, up_hardfault); + irq_attach(STM32_IRQ_SVCALL, up_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, up_hardfault, NULL); /* Set the priority of the SVCall interrupt */ @@ -393,22 +393,22 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(STM32_IRQ_MEMFAULT, up_memfault); + irq_attach(STM32_IRQ_MEMFAULT, up_memfault, NULL); up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32_IRQ_NMI, stm32_nmi); + irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(STM32_IRQ_MEMFAULT, up_memfault); + irq_attach(STM32_IRQ_MEMFAULT, up_memfault, NULL); #endif - irq_attach(STM32_IRQ_BUSFAULT, stm32_busfault); - irq_attach(STM32_IRQ_USAGEFAULT, stm32_usagefault); - irq_attach(STM32_IRQ_PENDSV, stm32_pendsv); - irq_attach(STM32_IRQ_DBGMONITOR, stm32_dbgmonitor); - irq_attach(STM32_IRQ_RESERVED, stm32_reserved); + irq_attach(STM32_IRQ_BUSFAULT, stm32_busfault, NULL); + irq_attach(STM32_IRQ_USAGEFAULT, stm32_usagefault, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); + irq_attach(STM32_IRQ_DBGMONITOR, stm32_dbgmonitor, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); #endif stm32_dumpnvic("initial", NR_IRQS); diff --git a/arch/arm/src/stm32/stm32_lowputc.c b/arch/arm/src/stm32/stm32_lowputc.c index 0bffb74808a..856879454a0 100644 --- a/arch/arm/src/stm32/stm32_lowputc.c +++ b/arch/arm/src/stm32/stm32_lowputc.c @@ -62,7 +62,11 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_USART1_SERIAL_CONSOLE) # define STM32_CONSOLE_BASE STM32_USART1_BASE -# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# if defined(CONFIG_STM32_STM32F33XX) +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY /* Errata 2.5.1 */ +# else +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# endif # define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR # define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN # define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD @@ -230,7 +234,8 @@ # define USART_CR1_PARITY_VALUE 0 # endif -# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) # define USART_CR1_CLRBITS\ (USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \ USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M | USART_CR1_MME | \ @@ -252,7 +257,8 @@ # define USART_CR2_STOP2_VALUE 0 # endif -# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) # define USART_CR2_CLRBITS \ (USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \ USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \ @@ -268,7 +274,8 @@ /* CR3 settings */ -# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) # define USART_CR3_CLRBITS \ (USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \ @@ -288,7 +295,8 @@ /* Calculate USART BAUD rate divider */ -# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) /* Baud rate for standard USART (SPI mode included): * @@ -563,8 +571,8 @@ void stm32_lowsetup(void) } #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32F40XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX) void stm32_lowsetup(void) { diff --git a/arch/arm/src/stm32/stm32_ltdc.c b/arch/arm/src/stm32/stm32_ltdc.c index ebaeff8d470..2573730172c 100644 --- a/arch/arm/src/stm32/stm32_ltdc.c +++ b/arch/arm/src/stm32/stm32_ltdc.c @@ -550,7 +550,7 @@ static void stm32_ltdc_periphconfig(void); static void stm32_ltdc_bgcolor(uint32_t rgb); static void stm32_ltdc_dither(bool enable, uint8_t red, uint8_t green, uint8_t blue); -static int stm32_ltdcirq(int irq, void *context); +static int stm32_ltdcirq(int irq, void *context, FAR void *arg); static int stm32_ltdc_waitforirq(void); static int stm32_ltdc_reload(uint8_t value, bool waitvblank); @@ -1128,7 +1128,7 @@ static void stm32_ltdc_irqctrl(uint32_t setirqs, uint32_t clrirqs) * ****************************************************************************/ -static int stm32_ltdcirq(int irq, void *context) +static int stm32_ltdcirq(int irq, void *context, FAR void *arg) { FAR struct stm32_interrupt_s *priv = &g_interrupt; @@ -1298,7 +1298,7 @@ static void stm32_global_configure(void) /* Attach LTDC interrupt vector */ - (void)irq_attach(g_interrupt.irq, stm32_ltdcirq); + (void)irq_attach(g_interrupt.irq, stm32_ltdcirq, NULL); /* Enable the IRQ at the NVIC */ diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/stm32/stm32_otgfsdev.c index 2fcbf599f06..47b212c3c28 100644 --- a/arch/arm/src/stm32/stm32_otgfsdev.c +++ b/arch/arm/src/stm32/stm32_otgfsdev.c @@ -619,7 +619,7 @@ static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv); /* First level interrupt processing */ -static int stm32_usbinterrupt(int irq, FAR void *context); +static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg); /* Endpoint operations *********************************************************/ /* Global OUT NAK controls */ @@ -3554,7 +3554,7 @@ static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv) * ****************************************************************************/ -static int stm32_usbinterrupt(int irq, FAR void *context) +static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) { /* At present, there is only a single OTG FS device support. Hence it is * pre-allocated as g_otgfsdev. However, in most code, the private data @@ -5502,7 +5502,7 @@ void up_usbinitialize(void) /* Attach the OTG FS interrupt handler */ - ret = irq_attach(STM32_IRQ_OTGFS, stm32_usbinterrupt); + ret = irq_attach(STM32_IRQ_OTGFS, stm32_usbinterrupt, NULL); if (ret < 0) { uerr("ERROR: irq_attach failed\n", ret); diff --git a/arch/arm/src/stm32/stm32_otgfshost.c b/arch/arm/src/stm32/stm32_otgfshost.c index 3feb0924c0d..0adea86e747 100644 --- a/arch/arm/src/stm32/stm32_otgfshost.c +++ b/arch/arm/src/stm32/stm32_otgfshost.c @@ -404,7 +404,7 @@ static inline void stm32_gint_ipxfrisr(FAR struct stm32_usbhost_s *priv); /* First level, global interrupt handler */ -static int stm32_gint_isr(int irq, FAR void *context); +static int stm32_gint_isr(int irq, FAR void *context, FAR void *arg); /* Interrupt controls */ @@ -3431,7 +3431,7 @@ static inline void stm32_gint_ipxfrisr(FAR struct stm32_usbhost_s *priv) * ****************************************************************************/ -static int stm32_gint_isr(int irq, FAR void *context) +static int stm32_gint_isr(int irq, FAR void *context, FAR void *arg) { /* At present, there is only support for a single OTG FS host. Hence it is * pre-allocated as g_usbhost. However, in most code, the private data @@ -5302,7 +5302,7 @@ FAR struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) /* Attach USB host controller interrupt handler */ - if (irq_attach(STM32_IRQ_OTGFS, stm32_gint_isr) != 0) + if (irq_attach(STM32_IRQ_OTGFS, stm32_gint_isr, NULL) != 0) { usbhost_trace1(OTGFS_TRACE1_IRQATTACH, 0); return NULL; diff --git a/arch/arm/src/stm32/stm32_otghsdev.c b/arch/arm/src/stm32/stm32_otghsdev.c index 97d71aa0aa9..97474f2f435 100644 --- a/arch/arm/src/stm32/stm32_otghsdev.c +++ b/arch/arm/src/stm32/stm32_otghsdev.c @@ -572,7 +572,7 @@ static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv); /* First level interrupt processing */ -static int stm32_usbinterrupt(int irq, FAR void *context); +static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg); /* Endpoint operations *********************************************************/ /* Global OUT NAK controls */ @@ -3498,7 +3498,7 @@ static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv) * ****************************************************************************/ -static int stm32_usbinterrupt(int irq, FAR void *context) +static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) { /* At present, there is only a single OTG HS device support. Hence it is * pre-allocated as g_otghsdev. However, in most code, the private data @@ -5438,7 +5438,7 @@ void up_usbinitialize(void) /* Attach the OTG HS interrupt handler */ - ret = irq_attach(STM32_IRQ_OTGHS, stm32_usbinterrupt); + ret = irq_attach(STM32_IRQ_OTGHS, stm32_usbinterrupt, NULL); if (ret < 0) { uerr("ERROR: irq_attach failed\n", ret); diff --git a/arch/arm/src/stm32/stm32_otghshost.c b/arch/arm/src/stm32/stm32_otghshost.c index 9dee00ae45c..c3c8be579ad 100644 --- a/arch/arm/src/stm32/stm32_otghshost.c +++ b/arch/arm/src/stm32/stm32_otghshost.c @@ -409,7 +409,7 @@ static inline void stm32_gint_ipxfrisr(FAR struct stm32_usbhost_s *priv); /* First level, global interrupt handler */ -static int stm32_gint_isr(int irq, FAR void *context); +static int stm32_gint_isr(int irq, FAR void *context, FAR void *arg); /* Interrupt controls */ @@ -3436,7 +3436,7 @@ static inline void stm32_gint_ipxfrisr(FAR struct stm32_usbhost_s *priv) * ****************************************************************************/ -static int stm32_gint_isr(int irq, FAR void *context) +static int stm32_gint_isr(int irq, FAR void *context, FAR void *arg) { /* At present, there is only support for a single OTG HS host. Hence it is * pre-allocated as g_usbhost. However, in most code, the private data @@ -5307,7 +5307,7 @@ FAR struct usbhost_connection_s *stm32_otghshost_initialize(int controller) /* Attach USB host controller interrupt handler */ - if (irq_attach(STM32_IRQ_OTGHS, stm32_gint_isr) != 0) + if (irq_attach(STM32_IRQ_OTGHS, stm32_gint_isr, NULL) != 0) { usbhost_trace1(OTGHS_TRACE1_IRQATTACH, 0); return NULL; diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c index 83a1a4cd7df..85ed3554fc9 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/stm32/stm32_pwm.c @@ -352,10 +352,10 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, #if defined(CONFIG_PWM_PULSECOUNT) && (defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM)) static int pwm_interrupt(struct stm32_pwmtimer_s *priv); #if defined(CONFIG_STM32_TIM1_PWM) -static int pwm_tim1interrupt(int irq, void *context); +static int pwm_tim1interrupt(int irq, void *context, FAR void *arg); #endif #if defined(CONFIG_STM32_TIM8_PWM) -static int pwm_tim8interrupt(int irq, void *context); +static int pwm_tim8interrupt(int irq, void *context, FAR void *arg); #endif static uint8_t pwm_pulsecount(uint32_t count); #endif @@ -1139,6 +1139,8 @@ static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg) pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); } + /* REVISIT: CNT and ARR may be 32-bits wide */ + pwminfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", pwm_getreg(priv, STM32_GTIM_CCER_OFFSET), pwm_getreg(priv, STM32_GTIM_CNT_OFFSET), @@ -1152,6 +1154,8 @@ static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg) pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET)); } + /* REVISIT: CCR1-CCR4 may be 32-bits wide */ + if (priv->timid == 16 || priv->timid == 17) { pwminfo(" CCR1: %04x\n", @@ -1981,14 +1985,14 @@ static int pwm_interrupt(struct stm32_pwmtimer_s *priv) ****************************************************************************/ #if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_STM32_TIM1_PWM) -static int pwm_tim1interrupt(int irq, void *context) +static int pwm_tim1interrupt(int irq, void *context, FAR void *arg) { return pwm_interrupt(&g_pwm1dev); } #endif #if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_STM32_TIM8_PWM) -static int pwm_tim8interrupt(int irq, void *context) +static int pwm_tim8interrupt(int irq, void *context, FAR void *arg) { return pwm_interrupt(&g_pwm8dev); } @@ -2599,7 +2603,7 @@ FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) /* Attach but disable the TIM1 update interrupt */ #ifdef CONFIG_PWM_PULSECOUNT - irq_attach(lower->irq, pwm_tim1interrupt); + irq_attach(lower->irq, pwm_tim1interrupt, NULL); up_disable_irq(lower->irq); #endif break; @@ -2636,7 +2640,7 @@ FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) /* Attach but disable the TIM8 update interrupt */ #ifdef CONFIG_PWM_PULSECOUNT - irq_attach(lower->irq, pwm_tim8interrupt); + irq_attach(lower->irq, pwm_tim8interrupt, NULL); up_disable_irq(lower->irq); #endif break; diff --git a/arch/arm/src/stm32/stm32_qencoder.c b/arch/arm/src/stm32/stm32_qencoder.c index 69b0f9b2e07..e2245075b91 100644 --- a/arch/arm/src/stm32/stm32_qencoder.c +++ b/arch/arm/src/stm32/stm32_qencoder.c @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/stm32/stm32_qencoder.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * Diego Sanchez * @@ -65,32 +65,6 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Clocking *************************************************************************/ -/* The CLKOUT value should not exceed the CLKIN value */ - -#if defined(CONFIG_STM32_TIM1_QE) && CONFIG_STM32_TIM1_QECLKOUT > STM32_APB2_TIM1_CLKIN -# warning "CONFIG_STM32_TIM1_QECLKOUT exceeds STM32_APB2_TIM1_CLKIN" -#endif - -#if defined(CONFIG_STM32_TIM2_QE) && CONFIG_STM32_TIM2_QECLKOUT > STM32_APB1_TIM2_CLKIN -# warning "CONFIG_STM32_TIM2_QECLKOUT exceeds STM32_APB2_TIM2_CLKIN" -#endif - -#if defined(CONFIG_STM32_TIM3_QE) && CONFIG_STM32_TIM3_QECLKOUT > STM32_APB1_TIM3_CLKIN -# warning "CONFIG_STM32_TIM3_QECLKOUT exceeds STM32_APB2_TIM3_CLKIN" -#endif - -#if defined(CONFIG_STM32_TIM4_QE) && CONFIG_STM32_TIM4_QECLKOUT > STM32_APB1_TIM4_CLKIN -# warning "CONFIG_STM32_TIM4_QECLKOUT exceeds STM32_APB2_TIM4_CLKIN" -#endif - -#if defined(CONFIG_STM32_TIM5_QE) && CONFIG_STM32_TIM5_QECLKOUT > STM32_APB1_TIM5_CLKIN -# warning "CONFIG_STM32_TIM5_QECLKOUT exceeds STM32_APB2_TIM5_CLKIN" -#endif - -#if defined(CONFIG_STM32_TIM8_QE) && CONFIG_STM32_TIM8_QECLKOUT > STM32_APB2_TIM8_CLKIN -# warning "CONFIG_STM32_TIM8_QECLKOUT exceeds STM32_APB2_TIM8_CLKIN" -#endif /* Timers ***************************************************************************/ @@ -269,21 +243,22 @@ struct stm32_qeconfig_s { - uint8_t timid; /* Timer ID {1,2,3,4,5,8} */ - uint8_t irq; /* Timer update IRQ */ + uint8_t timid; /* Timer ID {1,2,3,4,5,8} */ + uint8_t irq; /* Timer update IRQ */ #ifdef HAVE_MIXEDWIDTH_TIMERS - uint8_t width; /* Timer width (16- or 32-bits) */ + uint8_t width; /* Timer width (16- or 32-bits) */ #endif #ifdef CONFIG_STM32_STM32F10XX - uint16_t ti1cfg; /* TI1 input pin configuration (16-bit encoding) */ - uint16_t ti2cfg; /* TI2 input pin configuration (16-bit encoding) */ + uint16_t ti1cfg; /* TI1 input pin configuration (16-bit encoding) */ + uint16_t ti2cfg; /* TI2 input pin configuration (16-bit encoding) */ #else - uint32_t ti1cfg; /* TI1 input pin configuration (20-bit encoding) */ - uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */ + uint32_t ti1cfg; /* TI1 input pin configuration (20-bit encoding) */ + uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */ #endif - uint32_t base; /* Register base address */ - uint32_t psc; /* Timer input clock prescaler */ - xcpt_t handler; /* Interrupt handler for this IRQ */ + uintptr_t regaddr; /* RCC clock enable register address */ + uint32_t enable; /* RCC clock enable bit */ + uint32_t base; /* Register base address */ + uint32_t psc; /* Timer input clock prescaler */ }; /* Overall, RAM-based state structure */ @@ -328,25 +303,7 @@ static FAR struct stm32_lowerhalf_s *stm32_tim2lower(int tim); /* Interrupt handling */ #ifdef HAVE_16BIT_TIMERS -static int stm32_interrupt(FAR struct stm32_lowerhalf_s *priv); -#if defined(CONFIG_STM32_TIM1_QE) && TIM1_BITWIDTH == 16 -static int stm32_tim1interrupt(int irq, FAR void *context); -#endif -#if defined(CONFIG_STM32_TIM2_QE) && TIM2_BITWIDTH == 16 -static int stm32_tim2interrupt(int irq, FAR void *context); -#endif -#if defined(CONFIG_STM32_TIM3_QE) && TIM3_BITWIDTH == 16 -static int stm32_tim3interrupt(int irq, FAR void *context); -#endif -#if defined(CONFIG_STM32_TIM4_QE) && TIM4_BITWIDTH == 16 -static int stm32_tim4interrupt(int irq, FAR void *context); -#endif -#if defined(CONFIG_STM32_TIM5_QE) && TIM5_BITWIDTH == 16 -static int stm32_tim5interrupt(int irq, FAR void *context); -#endif -#if defined(CONFIG_STM32_TIM8_QE) && TIM8_BITWIDTH == 16 -static int stm32_tim8interrupt(int irq, FAR void *context); -#endif +static int stm32_interrupt(int irq, FAR void *context, FAR void *arg); #endif /* Lower-half Quadrature Encoder Driver Methods */ @@ -381,13 +338,12 @@ static const struct stm32_qeconfig_s g_tim1config = #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM1_BITWIDTH, #endif + .regaddr = STM32_RCC_APB2ENR, + .enable = RCC_APB2ENR_TIM1EN, .base = STM32_TIM1_BASE, - .psc = (STM32_APB2_TIM1_CLKIN / CONFIG_STM32_TIM1_QECLKOUT) - 1, + .psc = CONFIG_STM32_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, -#if TIM1_BITWIDTH == 16 - .handler = stm32_tim1interrupt, -#endif }; static struct stm32_lowerhalf_s g_tim1lower = @@ -407,13 +363,12 @@ static const struct stm32_qeconfig_s g_tim2config = #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM2_BITWIDTH, #endif + .regaddr = STM32_RCC_APB1ENR, + .enable = RCC_APB1ENR_TIM2EN, .base = STM32_TIM2_BASE, - .psc = (STM32_APB1_TIM2_CLKIN / CONFIG_STM32_TIM2_QECLKOUT) - 1, + .psc = CONFIG_STM32_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, -#if TIM2_BITWIDTH == 16 - .handler = stm32_tim2interrupt, -#endif }; static struct stm32_lowerhalf_s g_tim2lower = @@ -433,13 +388,12 @@ static const struct stm32_qeconfig_s g_tim3config = #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM3_BITWIDTH, #endif + .regaddr = STM32_RCC_APB1ENR, + .enable = RCC_APB1ENR_TIM3EN, .base = STM32_TIM3_BASE, - .psc = (STM32_APB1_TIM3_CLKIN / CONFIG_STM32_TIM3_QECLKOUT) - 1, + .psc = CONFIG_STM32_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, -#if TIM3_BITWIDTH == 16 - .handler = stm32_tim3interrupt, -#endif }; static struct stm32_lowerhalf_s g_tim3lower = @@ -459,13 +413,12 @@ static const struct stm32_qeconfig_s g_tim4config = #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM4_BITWIDTH, #endif + .regaddr = STM32_RCC_APB1ENR, + .enable = RCC_APB1ENR_TIM4EN, .base = STM32_TIM4_BASE, - .psc = (STM32_APB1_TIM4_CLKIN / CONFIG_STM32_TIM4_QECLKOUT) - 1, + .psc = CONFIG_STM32_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, -#if TIM4_BITWIDTH == 16 - .handler = stm32_tim4interrupt, -#endif }; static struct stm32_lowerhalf_s g_tim4lower = @@ -485,13 +438,12 @@ static const struct stm32_qeconfig_s g_tim5config = #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM5_BITWIDTH, #endif + .regaddr = STM32_RCC_APB1ENR, + .enable = RCC_APB1ENR_TIM5EN, .base = STM32_TIM5_BASE, - .psc = (STM32_APB1_TIM5_CLKIN / CONFIG_STM32_TIM5_QECLKOUT) - 1, + .psc = CONFIG_STM32_TIM5_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, -#if TIM5_BITWIDTH == 16 - .handler = stm32_tim5interrupt, -#endif }; static struct stm32_lowerhalf_s g_tim5lower = @@ -511,13 +463,12 @@ static const struct stm32_qeconfig_s g_tim8config = #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM8_BITWIDTH, #endif + .regaddr = STM32_RCC_APB2ENR, + .enable = RCC_APB2ENR_TIM8EN, .base = STM32_TIM8_BASE, - .psc = (STM32_APB2_TIM8_CLKIN / CONFIG_STM32_TIM8_QECLKOUT) - 1, + .psc = CONFIG_STM32_TIM8_QEPSC, .ti1cfg = GPIO_TIM8_CH1IN, .ti2cfg = GPIO_TIM8_CH2IN, -#if TIM8_BITWIDTH == 16 - .handler = stm32_tim8interrupt, -#endif }; static struct stm32_lowerhalf_s g_tim8lower = @@ -725,10 +676,13 @@ static FAR struct stm32_lowerhalf_s *stm32_tim2lower(int tim) ************************************************************************************/ #ifdef HAVE_16BIT_TIMERS -static int stm32_interrupt(FAR struct stm32_lowerhalf_s *priv) +static int stm32_interrupt(int irq, FAR void *context, FAR void *arg) { + FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)arg; uint16_t regval; + DEBUGASSERT(priv != NULL); + /* Verify that this is an update interrupt. Nothing else is expected. */ regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); @@ -756,56 +710,6 @@ static int stm32_interrupt(FAR struct stm32_lowerhalf_s *priv) } #endif -/************************************************************************************ - * Name: stm32_intNinterrupt - * - * Description: - * TIMN interrupt handler - * - ************************************************************************************/ - -#if defined(CONFIG_STM32_TIM1_QE) && TIM1_BITWIDTH == 16 -static int stm32_tim1interrupt(int irq, FAR void *context) -{ - return stm32_interrupt(&g_tim1lower); -} -#endif - -#if defined(CONFIG_STM32_TIM2_QE) && TIM2_BITWIDTH == 16 -static int stm32_tim2interrupt(int irq, FAR void *context) -{ - return stm32_interrupt(&g_tim2lower); -} -#endif - -#if defined(CONFIG_STM32_TIM3_QE) && TIM3_BITWIDTH == 16 -static int stm32_tim3interrupt(int irq, FAR void *context) -{ - return stm32_interrupt(&g_tim3lower); -} -#endif - -#if defined(CONFIG_STM32_TIM4_QE) && TIM4_BITWIDTH == 16 -static int stm32_tim4interrupt(int irq, FAR void *context) -{ - return stm32_interrupt(&g_tim4lower); -} -#endif - -#if defined(CONFIG_STM32_TIM5_QE) && TIM5_BITWIDTH == 16 -static int stm32_tim5interrupt(int irq, FAR void *context) -{ - return stm32_interrupt(&g_tim5lower); -} -#endif - -#if defined(CONFIG_STM32_TIM8_QE) && TIM8_BITWIDTH == 16 -static int stm32_tim8interrupt(int irq, FAR void *context) -{ - return stm32_interrupt(&g_tim8lower); -} -#endif - /************************************************************************************ * Name: stm32_setup * @@ -820,8 +724,8 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) { FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower; uint16_t dier; - uint16_t smcr; - uint16_t ccmr1; + uint32_t smcr; + uint32_t ccmr1; uint16_t ccer; uint16_t cr1; #ifdef HAVE_16BIT_TIMERS @@ -829,7 +733,9 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) int ret; #endif - /* NOTE: Clocking should have been enabled in the low-level RCC logic at boot-up */ + /* Enable clocking to the timer */ + + modifyreg32(priv->config->regaddr, 0, priv->config->enable); /* Timer base configuration */ @@ -859,10 +765,14 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); #endif - /* Set the timer prescaler value. The clock input value (CLKIN) is based on the - * peripheral clock (PCLK) and a multiplier. These CLKIN values are provided in - * the board.h file. The prescaler value is then that CLKIN value divided by the - * configured CLKOUT value (minus one) + /* Set the timer prescaler value. + * + * If we are doing precise shaft positioning, each qe pulse is important. + * So the STM32 has direct config control on the pulse count prescaler. + * This input clock just limits the incoming pulse rate, which should be + * lower than the peripheral clock due to resynchronization, but it is the + * responsibility of the system designer to decide the correct prescaler + * value, because it has a direct influence on the encoder resolution. */ stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); @@ -889,10 +799,10 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) /* Set the encoder Mode 3 */ - smcr = stm32_getreg16(priv, STM32_GTIM_SMCR_OFFSET); + smcr = stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET); smcr &= ~GTIM_SMCR_SMS_MASK; smcr |= GTIM_SMCR_ENCMD3; - stm32_putreg16(priv, STM32_GTIM_SMCR_OFFSET, smcr); + stm32_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); /* TI1 Channel Configuration */ /* Disable the Channel 1: Reset the CC1E Bit */ @@ -901,8 +811,8 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) ccer &= ~GTIM_CCER_CC1E; stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - ccmr1 = stm32_getreg16(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ @@ -917,17 +827,17 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) /* Write to TIM CCMR1 and CCER registers */ - stm32_putreg16(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Set the Input Capture Prescaler value: Capture performed each time an * edge is detected on the capture input. */ - ccmr1 = stm32_getreg16(priv, STM32_GTIM_CCMR1_OFFSET); + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); - stm32_putreg16(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); /* TI2 Channel Configuration */ /* Disable the Channel 2: Reset the CC2E Bit */ @@ -936,7 +846,7 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) ccer &= ~GTIM_CCER_CC2E; stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - ccmr1 = stm32_getreg16(priv, STM32_GTIM_CCMR1_OFFSET); + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ @@ -952,21 +862,21 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) /* Write to TIM CCMR1 and CCER registers */ - stm32_putreg16(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Set the Input Capture Prescaler value: Capture performed each time an * edge is detected on the capture input. */ - ccmr1 = stm32_getreg16(priv, STM32_GTIM_CCMR1_OFFSET); + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); - stm32_putreg16(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); /* Disable the update interrupt */ - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); + dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); dier &= ~GTIM_DIER_UIE; stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); @@ -979,7 +889,7 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) { /* Attach the interrupt handler */ - ret = irq_attach(priv->config->irq, priv->config->handler); + ret = irq_attach(priv->config->irq, stm32_interrupt, priv); if (ret < 0) { stm32_shutdown(lower); @@ -1130,6 +1040,10 @@ static int stm32_shutdown(FAR struct qe_lowerhalf_s *lower) sninfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit); stm32_dumpregs(priv, "After stop"); + /* Disable clocking to the timer */ + + modifyreg32(priv->config->regaddr, priv->config->enable, 0); + /* Put the TI1 GPIO pin back to its default state */ pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); @@ -1239,6 +1153,8 @@ static int stm32_ioctl(FAR struct qe_lowerhalf_s *lower, int cmd, unsigned long { /* No ioctl commands supported */ + /* TODO add an IOCTL to control the encoder pulse count prescaler */ + return -ENOTTY; } @@ -1284,7 +1200,7 @@ int stm32_qeinitialize(FAR const char *devpath, int tim) return -EBUSY; } - /* Register the priv-half driver */ + /* Register the upper-half driver */ ret = qe_register(devpath, (FAR struct qe_lowerhalf_s *)priv); if (ret < 0) diff --git a/arch/arm/src/stm32/stm32_rcc.c b/arch/arm/src/stm32/stm32_rcc.c index 7cae4be7449..3cb57ae6a0e 100644 --- a/arch/arm/src/stm32/stm32_rcc.c +++ b/arch/arm/src/stm32/stm32_rcc.c @@ -82,6 +82,8 @@ # include "stm32f20xxx_rcc.c" #elif defined(CONFIG_STM32_STM32F30XX) # include "stm32f30xxx_rcc.c" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "stm32f33xxx_rcc.c" #elif defined(CONFIG_STM32_STM32F37XX) # include "stm32f37xxx_rcc.c" #elif defined(CONFIG_STM32_STM32F40XX) diff --git a/arch/arm/src/stm32/stm32_rcc.h b/arch/arm/src/stm32/stm32_rcc.h index a4939221e8f..d331ab90b64 100644 --- a/arch/arm/src/stm32/stm32_rcc.h +++ b/arch/arm/src/stm32/stm32_rcc.h @@ -53,6 +53,8 @@ # include "chip/stm32f20xxx_rcc.h" #elif defined(CONFIG_STM32_STM32F30XX) # include "chip/stm32f30xxx_rcc.h" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "chip/stm32f33xxx_rcc.h" #elif defined(CONFIG_STM32_STM32F37XX) # include "chip/stm32f37xxx_rcc.h" #elif defined(CONFIG_STM32_STM32F40XX) diff --git a/arch/arm/src/stm32/stm32_rng.c b/arch/arm/src/stm32/stm32_rng.c index 8dde6a6c35c..ccbbd96dd72 100644 --- a/arch/arm/src/stm32/stm32_rng.c +++ b/arch/arm/src/stm32/stm32_rng.c @@ -61,7 +61,7 @@ ****************************************************************************/ static int stm32_rng_initialize(void); -static int stm32_interrupt(int irq, void *context); +static int stm32_interrupt(int irq, void *context, FAR void *arg); static void stm32_enable(void); static void stm32_disable(void); static ssize_t stm32_read(struct file *filep, char *buffer, size_t); @@ -113,7 +113,7 @@ static int stm32_rng_initialize() sem_init(&g_rngdev.rd_devsem, 0, 1); - if (irq_attach(STM32_IRQ_RNG, stm32_interrupt)) + if (irq_attach(STM32_IRQ_RNG, stm32_interrupt, NULL)) { /* We could not attach the ISR to the interrupt */ @@ -152,7 +152,7 @@ static void stm32_disable() putreg32(regval, STM32_RNG_CR); } -static int stm32_interrupt(int irq, void *context) +static int stm32_interrupt(int irq, void *context, FAR void *arg) { uint32_t rngsr; uint32_t data; diff --git a/arch/arm/src/stm32/stm32_rtcc.c b/arch/arm/src/stm32/stm32_rtcc.c index d27a8ddd387..b7155854965 100644 --- a/arch/arm/src/stm32/stm32_rtcc.c +++ b/arch/arm/src/stm32/stm32_rtcc.c @@ -768,7 +768,7 @@ int up_rtc_initialize(void) /* Then attach the ALARM interrupt handler */ - irq_attach(STM32_IRQ_RTC_WKUP, rtc_interrupt); + irq_attach(STM32_IRQ_RTC_WKUP, rtc_interrupt, NULL); up_enable_irq(STM32_IRQ_RTC_WKUP); #endif diff --git a/arch/arm/src/stm32/stm32_rtcounter.c b/arch/arm/src/stm32/stm32_rtcounter.c index 1c90be9c14d..9a046f8318c 100644 --- a/arch/arm/src/stm32/stm32_rtcounter.c +++ b/arch/arm/src/stm32/stm32_rtcounter.c @@ -324,7 +324,7 @@ static inline void stm32_rtc_breakout(FAR const struct timespec *tp, ************************************************************************************/ #if defined(CONFIG_RTC_HIRES) || defined(CONFIG_RTC_ALARM) -static int stm32_rtc_interrupt(int irq, void *context) +static int stm32_rtc_interrupt(int irq, void *context, FAR void *arg) { uint16_t source = getreg16(STM32_RTC_CRL); @@ -406,7 +406,7 @@ int up_rtc_initialize(void) /* Configure RTC interrupt to catch overflow and alarm interrupts. */ #if defined(CONFIG_RTC_HIRES) || defined(CONFIG_RTC_ALARM) - irq_attach(STM32_IRQ_RTC, stm32_rtc_interrupt); + irq_attach(STM32_IRQ_RTC, stm32_rtc_interrupt, NULL); up_enable_irq(STM32_IRQ_RTC); #endif diff --git a/arch/arm/src/stm32/stm32_sdadc.c b/arch/arm/src/stm32/stm32_sdadc.c index a16cade9cd2..67a769801bb 100644 --- a/arch/arm/src/stm32/stm32_sdadc.c +++ b/arch/arm/src/stm32/stm32_sdadc.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_sdadc.c * - * Copyright (C) 2011, 2013, 2015-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013, 2015-2017 Gregory Nutt. All rights reserved. * Copyright (C) 2016 Studelec. All rights reserved. * Authors: Gregory Nutt * Marc Rechté @@ -59,6 +59,7 @@ #include #include #include +#include #include "up_internal.h" #include "up_arch.h" @@ -92,6 +93,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* RCC reset ****************************************************************/ #define STM32_RCC_RSTR STM32_RCC_APB2RSTR @@ -133,7 +135,6 @@ struct stm32_dev_s #ifdef SDADC_HAVE_TIMER uint8_t trigger; /* Timer trigger selection: see SDADCx_JEXTSEL_TIMxx */ #endif - xcpt_t isr; /* Interrupt handler for this SDADC block */ uint32_t base; /* Base address of registers unique to this SDADC * block */ #ifdef SDADC_HAVE_TIMER @@ -180,16 +181,7 @@ static void sdadc_rccreset(FAR struct stm32_dev_s *priv, bool reset); /* ADC Interrupt Handler */ -static int sdadc_interrupt(FAR struct adc_dev_s *dev); -#if defined(CONFIG_STM32_SDADC1) -static int sdadc1_interrupt(int irq, FAR void *context); -#endif -#if defined(CONFIG_STM32_SDADC2) -static int sdadc2_interrupt(int irq, FAR void *context); -#endif -#if defined(CONFIG_STM32_SDADC3) -static int sdadc3_interrupt(int irq, FAR void *context); -#endif +static int sdadc_interrupt(int irq, FAR void *context, FAR void *arg); /* ADC Driver Methods */ @@ -239,7 +231,6 @@ static const struct adc_ops_s g_sdadcops = static struct stm32_dev_s g_sdadcpriv1 = { .irq = STM32_IRQ_SDADC1, - .isr = sdadc1_interrupt, .intf = 1, .base = STM32_SDADC1_BASE, .refv = SDADC1_REFV, @@ -269,8 +260,6 @@ static struct adc_dev_s g_sdadcdev1 = static struct stm32_dev_s g_sdadcpriv2 = { .irq = STM32_IRQ_SDADC2, - .isr = sdadc2_interrupt, - .intf = 2, .base = STM32_SDADC2_BASE, .refv = SDADC2_REFV, #ifdef SDADC2_HAVE_TIMER @@ -299,8 +288,6 @@ static struct adc_dev_s g_sdadcdev2 = static struct stm32_dev_s g_sdadcpriv3 = { .irq = STM32_IRQ_SDADC3, - .isr = sdadc3_interrupt, - .intf = 3, .base = STM32_SDADC3_BASE, .refv = SDADC3_REFV, #ifdef SDADC3_HAVE_TIMER @@ -996,7 +983,7 @@ static int sdadc_setup(FAR struct adc_dev_s *dev) { /* Attach the SDADC interrupt */ - ret = irq_attach(priv->irq, priv->isr); + ret = irq_attach(priv->irq, sdadc_interrupt, dev); if (ret < 0) { ainfo("irq_attach failed: %d\n", ret); @@ -1006,7 +993,7 @@ static int sdadc_setup(FAR struct adc_dev_s *dev) #else /* Attach the SDADC interrupt */ - ret = irq_attach(priv->irq, priv->isr); + ret = irq_attach(priv->irq, sdadc_interrupt, dev); if (ret < 0) { ainfo("irq_attach failed: %d\n", ret); @@ -1218,14 +1205,18 @@ static int sdadc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) * ****************************************************************************/ -static int sdadc_interrupt(FAR struct adc_dev_s *dev) +static int sdadc_interrupt(int irq, FAR void *context, FAR void *arg) { - FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; + FAR struct adc_dev_s *dev = (FAR struct adc_dev_s *)arg; + FAR struct stm32_dev_s *priv; uint32_t regval; uint32_t pending; int32_t data; uint8_t chan; + DEBUGASSERT(dev != NULL && dev->ad_priv != NULL); + priv = (FAR struct stm32_dev_s *)dev->ad_priv; + regval = sdadc_getreg(priv, STM32_SDADC_ISR_OFFSET); pending = regval & SDADC_ISR_ALLINTS; if (pending == 0) @@ -1296,75 +1287,6 @@ static int sdadc_interrupt(FAR struct adc_dev_s *dev) return OK; } -/**************************************************************************** - * Name: adc1_interrupt - * - * Description: - * ADC interrupt handler SDADC1 - * - * Input Parameters: - * irq - The IRQ number that generated the interrupt. - * context - Architecture specific register save information. - * - * Returned Value: - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_SDADC1) -static int sdadc1_interrupt(int irq, FAR void *context) -{ - sdadc_interrupt(&g_sdadcdev1); - - return OK; -} -#endif - -/**************************************************************************** - * Name: adc2_interrupt - * - * Description: - * ADC interrupt handler SDADC2 - * - * Input Parameters: - * irq - The IRQ number that generated the interrupt. - * context - Architecture specific register save information. - * - * Returned Value: - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_SDADC2) -static int sdadc2_interrupt(int irq, FAR void *context) -{ - sdadc_interrupt(&g_sdadcdev2); - - return OK; -} -#endif - -/**************************************************************************** - * Name: adc3_interrupt - * - * Description: - * ADC interrupt handler SDADC3 - * - * Input Parameters: - * irq - The IRQ number that generated the interrupt. - * context - Architecture specific register save information. - * - * Returned Value: - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_SDADC3) -static int sdadc3_interrupt(int irq, FAR void *context) -{ - sdadc_interrupt(&g_sdadcdev3); - - return OK; -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/stm32/stm32_sdio.c index 68ca6122c81..5b7f92887c8 100644 --- a/arch/arm/src/stm32/stm32_sdio.c +++ b/arch/arm/src/stm32/stm32_sdio.c @@ -416,9 +416,9 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, sdio_eventset_t wkupeven /* Interrupt Handling *******************************************************/ -static int stm32_interrupt(int irq, void *context); +static int stm32_interrupt(int irq, void *context, void *arg); #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE -static int stm32_rdyinterrupt(int irq, void *context); +static int stm32_rdyinterrupt(int irq, void *context, void *arg); #endif /* SDIO interface methods ***************************************************/ @@ -668,14 +668,16 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, /* Arm the SDIO_D Ready and install Isr */ - stm32_gpiosetevent(pinset, true, false, false, stm32_rdyinterrupt); + stm32_gpiosetevent(pinset, true, false, false, + stm32_rdyinterrupt, priv); } /* Disarm SDIO_D ready */ if ((wkupevent & SDIOWAIT_WRCOMPLETE) != 0) { - stm32_gpiosetevent(GPIO_SDIO_D0, false, false, false , NULL); + stm32_gpiosetevent(GPIO_SDIO_D0, false, false, false, + NULL, NULL); stm32_configgpio(GPIO_SDIO_D0); } #endif @@ -1315,9 +1317,9 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, sdio_eventset_t wkupeven ****************************************************************************/ #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE -static int stm32_rdyinterrupt(int irq, void *context) +static int stm32_rdyinterrupt(int irq, void *context, FAR void *arg) { - struct stm32_dev_s *priv = &g_sdiodev; + struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; stm32_endwait(priv, SDIOWAIT_WRCOMPLETE); return OK; } @@ -1337,7 +1339,7 @@ static int stm32_rdyinterrupt(int irq, void *context) * ****************************************************************************/ -static int stm32_interrupt(int irq, void *context) +static int stm32_interrupt(int irq, void *context, FAR void *arg) { struct stm32_dev_s *priv = &g_sdiodev; uint32_t enabled; @@ -1768,7 +1770,7 @@ static int stm32_attach(FAR struct sdio_dev_s *dev) /* Attach the SDIO interrupt handler */ - ret = irq_attach(STM32_IRQ_SDIO, stm32_interrupt); + ret = irq_attach(STM32_IRQ_SDIO, stm32_interrupt, NULL); if (ret == OK) { diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c index 8f774838da6..a6a2d07b51b 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/stm32/stm32_serial.c @@ -151,7 +151,8 @@ # endif # elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F30XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) # if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART2_RXDMA) || \ defined(CONFIG_USART3_RXDMA) @@ -188,7 +189,8 @@ # ifndef CONFIG_USART_DMAPRIO # if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) # define CONFIG_USART_DMAPRIO DMA_CCR_PRIMED # elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) # define CONFIG_USART_DMAPRIO DMA_SCR_PRIMED @@ -197,7 +199,8 @@ # endif # endif # if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) # if (CONFIG_USART_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 # error "Illegal value for CONFIG_USART_DMAPRIO" # endif @@ -312,8 +315,6 @@ struct up_dev_s const unsigned int rxdma_channel; /* DMA channel assigned */ #endif - int (*const vector)(int irq, void *context); /* Interrupt handler */ - /* RX DMA state */ #ifdef SERIAL_HAVE_DMA @@ -338,7 +339,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt_common(struct up_dev_s *dev); +static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); #ifndef SERIAL_HAVE_ONLY_DMA static int up_receive(struct uart_dev_s *dev, unsigned int *status); @@ -370,31 +371,6 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); #endif -#ifdef CONFIG_STM32_USART1_SERIALDRIVER -static int up_interrupt_usart1(int irq, void *context); -#endif -#ifdef CONFIG_STM32_USART2_SERIALDRIVER -static int up_interrupt_usart2(int irq, void *context); -#endif -#ifdef CONFIG_STM32_USART3_SERIALDRIVER -static int up_interrupt_usart3(int irq, void *context); -#endif -#ifdef CONFIG_STM32_UART4_SERIALDRIVER -static int up_interrupt_uart4(int irq, void *context); -#endif -#ifdef CONFIG_STM32_UART5_SERIALDRIVER -static int up_interrupt_uart5(int irq, void *context); -#endif -#ifdef CONFIG_STM32_USART6_SERIALDRIVER -static int up_interrupt_usart6(int irq, void *context); -#endif -#ifdef CONFIG_STM32_UART7_SERIALDRIVER -static int up_interrupt_uart7(int irq, void *context); -#endif -#ifdef CONFIG_STM32_UART8_SERIALDRIVER -static int up_interrupt_uart8(int irq, void *context); -#endif - /**************************************************************************** * Private Data ****************************************************************************/ @@ -540,7 +516,11 @@ static struct up_dev_s g_usart1priv = .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, +#if defined(CONFIG_STM32_STM32F33XX) + .apbclock = STM32_PCLK1_FREQUENCY, /* Errata 2.5.1 */ +#else .apbclock = STM32_PCLK2_FREQUENCY, +#endif .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, @@ -556,7 +536,6 @@ static struct up_dev_s g_usart1priv = .rxdma_channel = DMAMAP_USART1_RX, .rxfifo = g_usart1rxfifo, #endif - .vector = up_interrupt_usart1, #ifdef CONFIG_USART1_RS485 .rs485_dir_gpio = GPIO_USART1_RS485_DIR, @@ -618,7 +597,6 @@ static struct up_dev_s g_usart2priv = .rxdma_channel = DMAMAP_USART2_RX, .rxfifo = g_usart2rxfifo, #endif - .vector = up_interrupt_usart2, #ifdef CONFIG_USART2_RS485 .rs485_dir_gpio = GPIO_USART2_RS485_DIR, @@ -680,7 +658,6 @@ static struct up_dev_s g_usart3priv = .rxdma_channel = DMAMAP_USART3_RX, .rxfifo = g_usart3rxfifo, #endif - .vector = up_interrupt_usart3, #ifdef CONFIG_USART3_RS485 .rs485_dir_gpio = GPIO_USART3_RS485_DIR, @@ -746,7 +723,6 @@ static struct up_dev_s g_uart4priv = .rxdma_channel = DMAMAP_UART4_RX, .rxfifo = g_uart4rxfifo, #endif - .vector = up_interrupt_uart4, #ifdef CONFIG_UART4_RS485 .rs485_dir_gpio = GPIO_UART4_RS485_DIR, @@ -812,7 +788,6 @@ static struct up_dev_s g_uart5priv = .rxdma_channel = DMAMAP_UART5_RX, .rxfifo = g_uart5rxfifo, #endif - .vector = up_interrupt_uart5, #ifdef CONFIG_UART5_RS485 .rs485_dir_gpio = GPIO_UART5_RS485_DIR, @@ -874,7 +849,6 @@ static struct up_dev_s g_usart6priv = .rxdma_channel = DMAMAP_USART6_RX, .rxfifo = g_usart6rxfifo, #endif - .vector = up_interrupt_usart6, #ifdef CONFIG_USART6_RS485 .rs485_dir_gpio = GPIO_USART6_RS485_DIR, @@ -936,7 +910,6 @@ static struct up_dev_s g_uart7priv = .rxdma_channel = DMAMAP_UART7_RX, .rxfifo = g_uart7rxfifo, #endif - .vector = up_interrupt_uart7, #ifdef CONFIG_UART7_RS485 .rs485_dir_gpio = GPIO_UART7_RS485_DIR, @@ -998,7 +971,6 @@ static struct up_dev_s g_uart8priv = .rxdma_channel = DMAMAP_UART8_RX, .rxfifo = g_uart8rxfifo, #endif - .vector = up_interrupt_uart8, #ifdef CONFIG_UART8_RS485 .rs485_dir_gpio = GPIO_UART8_RS485_DIR, @@ -1173,7 +1145,8 @@ static int up_dma_nextrx(struct up_dev_s *priv) static void up_set_format(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) uint32_t usartdiv8; #else uint32_t usartdiv32; @@ -1187,7 +1160,8 @@ static void up_set_format(struct uart_dev_s *dev) regval = up_serialin(priv, STM32_USART_CR1_OFFSET); -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)|| \ + defined(CONFIG_STM32_STM32F37XX) /* This first implementation is for U[S]ARTs that support oversampling * by 8 in additional to the standard oversampling by 16. * With baud rate of fCK / Divider for oversampling by 16. @@ -1735,7 +1709,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, priv->vector); + ret = irq_attach(priv->irq, up_interrupt, priv); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -1744,6 +1718,7 @@ static int up_attach(struct uart_dev_s *dev) up_enable_irq(priv->irq); } + return ret; } @@ -1765,7 +1740,7 @@ static void up_detach(struct uart_dev_s *dev) } /**************************************************************************** - * Name: up_interrupt_common + * Name: up_interrupt * * Description: * This is the USART interrupt handler. It will be invoked when an @@ -1776,11 +1751,14 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt_common(struct up_dev_s *priv) +static int up_interrupt(int irq, void *context, void *arg) { + struct up_dev_s *priv = (struct up_dev_s *)arg; int passes; bool handled; + DEBUGASSERT(priv != NULL); + /* Report serial activity to the power management logic */ #if defined(CONFIG_PM) && CONFIG_PM_SERIAL_ACTIVITY > 0 @@ -1855,7 +1833,8 @@ static int up_interrupt_common(struct up_dev_s *priv) else if ((priv->sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE)) != 0) { -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) /* These errors are cleared by writing the corresponding bit to the * interrupt clear register (ICR). */ @@ -2501,70 +2480,6 @@ static bool up_txready(struct uart_dev_s *dev) return ((up_serialin(priv, STM32_USART_SR_OFFSET) & USART_SR_TXE) != 0); } -/**************************************************************************** - * Name: up_interrupt_u[s]art[n] - * - * Description: - * Interrupt handlers for U[S]ART[n] where n=1,..,6. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USART1_SERIALDRIVER -static int up_interrupt_usart1(int irq, void *context) -{ - return up_interrupt_common(&g_usart1priv); -} -#endif - -#ifdef CONFIG_STM32_USART2_SERIALDRIVER -static int up_interrupt_usart2(int irq, void *context) -{ - return up_interrupt_common(&g_usart2priv); -} -#endif - -#ifdef CONFIG_STM32_USART3_SERIALDRIVER -static int up_interrupt_usart3(int irq, void *context) -{ - return up_interrupt_common(&g_usart3priv); -} -#endif - -#ifdef CONFIG_STM32_UART4_SERIALDRIVER -static int up_interrupt_uart4(int irq, void *context) -{ - return up_interrupt_common(&g_uart4priv); -} -#endif - -#ifdef CONFIG_STM32_UART5_SERIALDRIVER -static int up_interrupt_uart5(int irq, void *context) -{ - return up_interrupt_common(&g_uart5priv); -} -#endif - -#ifdef CONFIG_STM32_USART6_SERIALDRIVER -static int up_interrupt_usart6(int irq, void *context) -{ - return up_interrupt_common(&g_usart6priv); -} -#endif - -#ifdef CONFIG_STM32_UART7_SERIALDRIVER -static int up_interrupt_uart7(int irq, void *context) -{ - return up_interrupt_common(&g_uart7priv); -} -#endif - -#ifdef CONFIG_STM32_UART8_SERIALDRIVER -static int up_interrupt_uart8(int irq, void *context) -{ - return up_interrupt_common(&g_uart8priv); -} -#endif - /**************************************************************************** * Name: up_dma_rxcallback * diff --git a/arch/arm/src/stm32/stm32_spi.c b/arch/arm/src/stm32/stm32_spi.c index ad6d2fc47cd..3a4a7c8bf98 100644 --- a/arch/arm/src/stm32/stm32_spi.c +++ b/arch/arm/src/stm32/stm32_spi.c @@ -1,5 +1,5 @@ /************************************************************************************ - * arm/arm/src/stm32/stm32_spi.c + * arch/arm/src/stm32/stm32_spi.c * * Copyright (C) 2009-2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/stm32/stm32_syscfg.h b/arch/arm/src/stm32/stm32_syscfg.h index 8098779f2a6..9d832b0f2ea 100644 --- a/arch/arm/src/stm32/stm32_syscfg.h +++ b/arch/arm/src/stm32/stm32_syscfg.h @@ -49,6 +49,8 @@ # include "chip/stm32f20xxx_syscfg.h" #elif defined(CONFIG_STM32_STM32F30XX) # include "chip/stm32f30xxx_syscfg.h" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "chip/stm32f33xxx_syscfg.h" #elif defined(CONFIG_STM32_STM32F37XX) # include "chip/stm32f37xxx_syscfg.h" #elif defined(CONFIG_STM32_STM32F40XX) diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c index ff470b3065c..fbba052d546 100644 --- a/arch/arm/src/stm32/stm32_tim.c +++ b/arch/arm/src/stm32/stm32_tim.c @@ -1,5 +1,5 @@ /************************************************************************************ - * arm/arm/src/stm32/stm32_tim.c + * arch/arm/src/stm32/stm32_tim.c * * Copyright (C) 2011 Uros Platise. All rights reserved. * Author: Uros Platise @@ -344,8 +344,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel); -static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, - int (*handler)(int irq, void *context), +static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, xcpt_t handler, int source); static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source); static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source); @@ -1484,8 +1483,7 @@ static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel * Name: stm32_tim_setisr ************************************************************************************/ -static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, - int (*handler)(int irq, void *context), +static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, xcpt_t handler, int source) { int vectorno; @@ -1596,7 +1594,7 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, /* Otherwise set callback and enable interrupt */ - irq_attach(vectorno, handler); + irq_attach(vectorno, handler, NULL); up_enable_irq(vectorno); #ifdef CONFIG_ARCH_IRQPRIO diff --git a/arch/arm/src/stm32/stm32_tim.h b/arch/arm/src/stm32/stm32_tim.h index e31250537b4..6bdf2f53963 100644 --- a/arch/arm/src/stm32/stm32_tim.h +++ b/arch/arm/src/stm32/stm32_tim.h @@ -50,6 +50,8 @@ #include "chip.h" #include "chip/stm32_tim.h" +#include + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ @@ -172,8 +174,7 @@ struct stm32_tim_ops_s /* Timer interrupts */ - int (*setisr)(FAR struct stm32_tim_dev_s *dev, - int (*handler)(int irq, void *context), int source); + int (*setisr)(FAR struct stm32_tim_dev_s *dev, xcpt_t handler, int source); void (*enableint)(FAR struct stm32_tim_dev_s *dev, int source); void (*disableint)(FAR struct stm32_tim_dev_s *dev, int source); void (*ackint)(FAR struct stm32_tim_dev_s *dev, int source); @@ -190,7 +191,7 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev); +int stm32_tim_deinit(FAR struct stm32_tim_dev_s *dev); /**************************************************************************** * Name: stm32_timer_initialize diff --git a/arch/arm/src/stm32/stm32_timerisr.c b/arch/arm/src/stm32/stm32_timerisr.c index cb0bd885a7d..ac2aaae0945 100644 --- a/arch/arm/src/stm32/stm32_timerisr.c +++ b/arch/arm/src/stm32/stm32_timerisr.c @@ -98,7 +98,7 @@ * ****************************************************************************/ -static int stm32_timerisr(int irq, uint32_t *regs) +static int stm32_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -148,7 +148,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr); + (void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); /* Enable SysTick interrupts */ diff --git a/arch/arm/src/stm32/stm32_uart.h b/arch/arm/src/stm32/stm32_uart.h index 76fc41e0ba0..fe2542cfa69 100644 --- a/arch/arm/src/stm32/stm32_uart.h +++ b/arch/arm/src/stm32/stm32_uart.h @@ -50,7 +50,8 @@ # include "chip/stm32f10xxx_uart.h" #elif defined(CONFIG_STM32_STM32F20XX) # include "chip/stm32f20xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) # include "chip/stm32f30xxx_uart.h" #elif defined(CONFIG_STM32_STM32F40XX) # include "chip/stm32f40xxx_uart.h" diff --git a/arch/arm/src/stm32/stm32_usbdev.c b/arch/arm/src/stm32/stm32_usbdev.c index 9c69a86b8fe..e042f50a76e 100644 --- a/arch/arm/src/stm32/stm32_usbdev.c +++ b/arch/arm/src/stm32/stm32_usbdev.c @@ -484,8 +484,8 @@ static void stm32_ep0in(struct stm32_usbdev_s *priv); static inline void stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr); static void stm32_lptransfer(struct stm32_usbdev_s *priv); -static int stm32_hpinterrupt(int irq, void *context); -static int stm32_lpinterrupt(int irq, void *context); +static int stm32_hpinterrupt(int irq, void *context, FAR void *arg); +static int stm32_lpinterrupt(int irq, void *context, FAR void *arg); /* Endpoint helpers *********************************************************/ @@ -2413,7 +2413,7 @@ static void stm32_lptransfer(struct stm32_usbdev_s *priv) * Name: stm32_hpinterrupt ****************************************************************************/ -static int stm32_hpinterrupt(int irq, void *context) +static int stm32_hpinterrupt(int irq, void *context, FAR void *arg) { /* For now there is only one USB controller, but we will always refer to * it using a pointer to make any future ports to multiple USB controllers @@ -2455,7 +2455,7 @@ static int stm32_hpinterrupt(int irq, void *context) * Name: stm32_lpinterrupt ****************************************************************************/ -static int stm32_lpinterrupt(int irq, void *context) +static int stm32_lpinterrupt(int irq, void *context, FAR void *arg) { /* For now there is only one USB controller, but we will always refer to * it using a pointer to make any future ports to multiple USB controllers @@ -3752,14 +3752,14 @@ void up_usbinitialize(void) * them when we need them later. */ - if (irq_attach(STM32_IRQ_USBHP, stm32_hpinterrupt) != 0) + if (irq_attach(STM32_IRQ_USBHP, stm32_hpinterrupt, NULL) != 0) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), (uint16_t)STM32_IRQ_USBHP); goto errout; } - if (irq_attach(STM32_IRQ_USBLP, stm32_lpinterrupt) != 0) + if (irq_attach(STM32_IRQ_USBLP, stm32_lpinterrupt, NULL) != 0) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), (uint16_t)STM32_IRQ_USBLP); diff --git a/arch/arm/src/stm32/stm32_wwdg.c b/arch/arm/src/stm32/stm32_wwdg.c index 6c982997437..a299de8c991 100644 --- a/arch/arm/src/stm32/stm32_wwdg.c +++ b/arch/arm/src/stm32/stm32_wwdg.c @@ -121,7 +121,7 @@ static void stm32_setwindow(FAR struct stm32_lowerhalf_s *priv, /* Interrupt hanlding *******************************************************/ -static int stm32_interrupt(int irq, FAR void *context); +static int stm32_interrupt(int irq, FAR void *context, FAR void *arg); /* "Lower half" driver methods **********************************************/ @@ -286,7 +286,7 @@ static void stm32_setwindow(FAR struct stm32_lowerhalf_s *priv, uint8_t window) * ****************************************************************************/ -static int stm32_interrupt(int irq, FAR void *context) +static int stm32_interrupt(int irq, FAR void *context, FAR void *arg) { FAR struct stm32_lowerhalf_s *priv = &g_wdgdev; uint16_t regval; @@ -305,7 +305,7 @@ static int stm32_interrupt(int irq, FAR void *context) * upon return. */ - priv->handler(irq, context); + priv->handler(irq, context, arg); } /* The EWI interrupt is cleared by writing '0' to the EWIF bit in the @@ -766,7 +766,7 @@ void stm32_wwdginitialize(FAR const char *devpath) /* Attach our EWI interrupt handler (But don't enable it yet) */ - (void)irq_attach(STM32_IRQ_WWDG, stm32_interrupt); + (void)irq_attach(STM32_IRQ_WWDG, stm32_interrupt, NULL); /* Select an arbitrary initial timeout value. But don't start the watchdog * yet. NOTE: If the "Hardware watchdog" feature is enabled through the @@ -780,7 +780,7 @@ void stm32_wwdginitialize(FAR const char *devpath) (void)watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv); - /* When the microcontroller enters debug mode (Cortex™-M4F core halted), + /* When the microcontroller enters debug mode (Cortex�-M4F core halted), * the WWDG counter either continues to work normally or stops, depending * on DBG_WWDG_STOP configuration bit in DBG module. */ diff --git a/arch/arm/src/stm32/stm32f10xxx_dma.c b/arch/arm/src/stm32/stm32f10xxx_dma.c index 8a7782773e2..1e6751ee563 100644 --- a/arch/arm/src/stm32/stm32f10xxx_dma.c +++ b/arch/arm/src/stm32/stm32f10xxx_dma.c @@ -275,7 +275,7 @@ static void stm32_dmachandisable(struct stm32_dma_s *dmach) * ************************************************************************************/ -static int stm32_dmainterrupt(int irq, void *context) +static int stm32_dmainterrupt(int irq, void *context, FAR void *arg) { struct stm32_dma_s *dmach; uint32_t isr; @@ -351,7 +351,7 @@ void weak_function up_dmainitialize(void) /* Attach DMA interrupt vectors */ - (void)irq_attach(dmach->irq, stm32_dmainterrupt); + (void)irq_attach(dmach->irq, stm32_dmainterrupt, NULL); /* Disable the DMA channel */ diff --git a/arch/arm/src/stm32/stm32f20xxx_dma.c b/arch/arm/src/stm32/stm32f20xxx_dma.c index 8edd31db2cb..6fb9d33cee1 100644 --- a/arch/arm/src/stm32/stm32f20xxx_dma.c +++ b/arch/arm/src/stm32/stm32f20xxx_dma.c @@ -370,7 +370,7 @@ static void stm32_dmastreamdisable(struct stm32_dma_s *dmast) * ************************************************************************************/ -static int stm32_dmainterrupt(int irq, void *context) +static int stm32_dmainterrupt(int irq, void *context, FAR void *arg) { struct stm32_dma_s *dmast; uint32_t status; @@ -482,7 +482,7 @@ void weak_function up_dmainitialize(void) /* Attach DMA interrupt vectors */ - (void)irq_attach(dmast->irq, stm32_dmainterrupt); + (void)irq_attach(dmast->irq, stm32_dmainterrupt, dmast); /* Disable the DMA stream */ diff --git a/arch/arm/src/stm32/stm32f30xxx_i2c.c b/arch/arm/src/stm32/stm32f30xxx_i2c.c index 312e0b4bb88..4a1ae02a512 100644 --- a/arch/arm/src/stm32/stm32f30xxx_i2c.c +++ b/arch/arm/src/stm32/stm32f30xxx_i2c.c @@ -222,7 +222,7 @@ struct stm32_i2c_config_s uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ #ifndef CONFIG_I2C_POLLED - int (*isr)(int, void *); /* Interrupt handler */ + int (*isr)(int, void *, void *); /* Interrupt handler */ uint32_t ev_irq; /* Event IRQ */ uint32_t er_irq; /* Error IRQ */ #endif @@ -304,13 +304,13 @@ static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv); static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv); #ifndef CONFIG_I2C_POLLED #ifdef CONFIG_STM32_I2C1 -static int stm32_i2c1_isr(int irq, void *context); +static int stm32_i2c1_isr(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_STM32_I2C2 -static int stm32_i2c2_isr(int irq, void *context); +static int stm32_i2c2_isr(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_STM32_I2C3 -static int stm32_i2c3_isr(int irq, void *context); +static int stm32_i2c3_isr(int irq, void *context, FAR void *arg); #endif #endif static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv); @@ -1493,7 +1493,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) #ifndef CONFIG_I2C_POLLED #ifdef CONFIG_STM32_I2C1 -static int stm32_i2c1_isr(int irq, void *context) +static int stm32_i2c1_isr(int irq, void *context, FAR void *arg) { return stm32_i2c_isr(&stm32_i2c1_priv); } @@ -1508,7 +1508,7 @@ static int stm32_i2c1_isr(int irq, void *context) ************************************************************************************/ #ifdef CONFIG_STM32_I2C2 -static int stm32_i2c2_isr(int irq, void *context) +static int stm32_i2c2_isr(int irq, void *context, FAR void *arg) { return stm32_i2c_isr(&stm32_i2c2_priv); } @@ -1523,7 +1523,7 @@ static int stm32_i2c2_isr(int irq, void *context) ************************************************************************************/ #ifdef CONFIG_STM32_I2C3 -static int stm32_i2c3_isr(int irq, void *context) +static int stm32_i2c3_isr(int irq, void *context, FAR void *arg) { return stm32_i2c_isr(&stm32_i2c3_priv); } @@ -1568,8 +1568,8 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv) /* Attach ISRs */ #ifndef CONFIG_I2C_POLLED - irq_attach(priv->config->ev_irq, priv->config->isr); - irq_attach(priv->config->er_irq, priv->config->isr); + irq_attach(priv->config->ev_irq, priv->config->isr, NULL); + irq_attach(priv->config->er_irq, priv->config->isr, NULL); up_enable_irq(priv->config->ev_irq); up_enable_irq(priv->config->er_irq); #endif diff --git a/arch/arm/src/stm32/stm32f33xxx_rcc.c b/arch/arm/src/stm32/stm32f33xxx_rcc.c new file mode 100644 index 00000000000..82923a7ef86 --- /dev/null +++ b/arch/arm/src/stm32/stm32f33xxx_rcc.c @@ -0,0 +1,628 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32f33xxx_rcc.c + * + * Copyright (C) 2012, 2015, 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Modified for STM32F334 by Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. Normally this is very fast, but I have seen at least one + * board that required this long, long timeout for the HSE to be ready. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_reset + * + * Description: + * Put all RCC registers in reset state + * + ****************************************************************************/ + +static inline void rcc_reset(void) +{ + uint32_t regval; + + putreg32(0, STM32_RCC_APB2RSTR); /* Disable APB2 Peripheral Reset */ + putreg32(0, STM32_RCC_APB1RSTR); /* Disable APB1 Peripheral Reset */ + putreg32(RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN, STM32_RCC_AHBENR); /* FLITF and SRAM Clock ON */ + putreg32(0, STM32_RCC_APB2ENR); /* Disable APB2 Peripheral Clock */ + putreg32(0, STM32_RCC_APB1ENR); /* Disable APB1 Peripheral Clock */ + + regval = getreg32(STM32_RCC_CR); /* Set the HSION bit */ + regval |= RCC_CR_HSION; + putreg32(regval, STM32_RCC_CR); + + regval = getreg32(STM32_RCC_CFGR); /* Reset SW, HPRE, PPRE1, PPRE2, and MCO bits */ + regval &= ~(RCC_CFGR_SW_MASK | RCC_CFGR_HPRE_MASK | RCC_CFGR_PPRE1_MASK | + RCC_CFGR_PPRE2_MASK | RCC_CFGR_MCO_MASK); + + putreg32(regval, STM32_RCC_CFGR); + + regval = getreg32(STM32_RCC_CFGR2); /* Reset PREDIV, and ADC12PRE bits */ + regval &= ~(RCC_CFGR2_PREDIV_MASK | RCC_CFGR2_ADC12PRES_MASK); + putreg32(regval, STM32_RCC_CFGR2); + + regval = getreg32(STM32_RCC_CFGR3); /* Reset all U[S]ARTs, I2C1, TIM1 and HRTIM1 bits */ + regval &= ~(RCC_CFGR3_USART1SW_MASK | RCC_CFGR3_USART2SW_MASK | RCC_CFGR3_USART3SW_MASK | \ + RCC_CFGR3_I2C1SW | RCC_CFGR3_TIM1SW | RCC_CFGR3_HRTIM1SW); + putreg32(regval, STM32_RCC_CFGR3); + + regval = getreg32(STM32_RCC_CR); /* Reset HSEON, CSSON and PLLON bits */ + regval &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); + putreg32(regval, STM32_RCC_CR); + + regval = getreg32(STM32_RCC_CR); /* Reset HSEBYP bit */ + regval &= ~RCC_CR_HSEBYP; + putreg32(regval, STM32_RCC_CR); + + regval = getreg32(STM32_RCC_CFGR); /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ + regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL_MASK); + putreg32(regval, STM32_RCC_CFGR); + + putreg32(0, STM32_RCC_CIR); /* Disable all interrupts */ +} + +/**************************************************************************** + * Name: rcc_enableahb + * + * Description: + * Enable selected AHB peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb(void) +{ + uint32_t regval; + + /* Always enable FLITF clock and SRAM clock */ + + regval = RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN; + + /* Enable GPIO PORTA, PORTB, ... PORTF */ + + regval |= (RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPBEN | RCC_AHBENR_IOPCEN | + RCC_AHBENR_IOPDEN | RCC_AHBENR_IOPFEN); + +#ifdef CONFIG_STM32_DMA1 + /* DMA 1 clock enable */ + + regval |= RCC_AHBENR_DMA1EN; +#endif + +#ifdef CONFIG_STM32_CRC + /* CRC clock enable */ + + regval |= RCC_AHBENR_CRCEN; +#endif + +#ifdef CONFIG_STM32_TSC + /* CRC clock enable */ + + regval |= RCC_AHBENR_TSCEN; +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) + /* ADC1/ADC2 interface clock enable */ + + regval |= RCC_AHBENR_ADC12EN; +#endif + + putreg32(regval, STM32_RCC_AHBENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb1 + * + * Description: + * Enable selected APB1 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb1(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB1ENR register to enabled the + * selected APB1 peripherals. + */ + + regval = getreg32(STM32_RCC_APB1ENR); + +#ifdef CONFIG_STM32_TIM2 + /* Timer 2 clock enable */ + +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM2EN; +#endif +#endif + +#ifdef CONFIG_STM32_TIM3 + /* Timer 3 clock enable */ + +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM3EN; +#endif +#endif + +#ifdef CONFIG_STM32_TIM6 + /* Timer 6 clock enable */ + +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM6EN; +#endif +#endif + +#ifdef CONFIG_STM32_TIM7 + /* Timer 7 clock enable */ + +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM7EN; +#endif +#endif + +#ifdef CONFIG_STM32_WWDG + /* Window Watchdog clock enable */ + + regval |= RCC_APB1ENR_WWDGEN; +#endif + +#ifdef CONFIG_STM32_USART2 + /* USART 2 clock enable */ + + regval |= RCC_APB1ENR_USART2EN; +#endif + +#ifdef CONFIG_STM32_USART3 + /* USART 3 clock enable */ + + regval |= RCC_APB1ENR_USART3EN; +#endif + +#ifdef CONFIG_STM32_I2C1 + /* I2C 1 clock enable */ + +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_I2C1EN; +#endif +#endif + +#ifdef CONFIG_STM32_CAN1 + /* CAN1 clock enable */ + + regval |= RCC_APB1ENR_CAN1EN; +#endif + +#ifdef CONFIG_STM32_DAC2 + /* DAC2 interface clock enable */ + + regval |= RCC_APB1ENR_DAC2EN; +#endif + +#ifdef CONFIG_STM32_PWR + /* Power interface clock enable */ + + regval |= RCC_APB1ENR_PWREN; +#endif + +#ifdef CONFIG_STM32_DAC1 + /* DAC1 interface clock enable */ + + regval |= RCC_APB1ENR_DAC1EN; +#endif + + putreg32(regval, STM32_RCC_APB1ENR); +} + +/**************************************************************************** + * Name: rcc_enableapb2 + * + * Description: + * Enable selected APB2 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb2(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB2ENR register to enabled the + * selected APB2 peripherals. + */ + + regval = getreg32(STM32_RCC_APB2ENR); + +#ifdef CONFIG_STM32_SYSCFG + /* SYSCFG clock */ + + regval |= RCC_APB2ENR_SYSCFGEN; +#endif + +#ifdef CONFIG_STM32_TIM1 + /* TIM1 Timer clock enable */ + +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB2ENR_TIM1EN; +#endif +#endif + +#ifdef CONFIG_STM32_SPI1 + /* SPI 1 clock enable */ + + regval |= RCC_APB2ENR_SPI1EN; +#endif + +#ifdef CONFIG_STM32_USART1 + /* USART1 clock enable */ + + regval |= RCC_APB2ENR_USART1EN; +#endif + +#ifdef CONFIG_STM32_TIM15 + /* TIM15 Timer clock enable */ + +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB2ENR_TIM15EN; +#endif +#endif + +#ifdef CONFIG_STM32_TIM16 + /* TIM16 Timer clock enable */ + +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB2ENR_TIM16EN; +#endif +#endif + +#ifdef CONFIG_STM32_TIM17 + /* TIM17 Timer clock enable */ + +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB2ENR_TIM17EN; +#endif +#endif + +#ifdef CONFIG_STM32_HRTIM1 + /* HRTIM1 Timer clock enable */ + +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB2ENR_HRTIM1EN; +#endif +#endif + + putreg32(regval, STM32_RCC_APB2ENR); +} + +/**************************************************************************** + * Name: stm32_stdclockconfig + * + * Description: + * Called to change to new clock based on settings in board.h. This + * version is for the Connectivity Line parts. + * + * NOTE: This logic would need to be extended if you need to select low- + * power clocking modes! + ****************************************************************************/ + +#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) && defined(CONFIG_STM32_CONNECTIVITYLINE) +static void stm32_stdclockconfig(void) +{ + uint32_t regval; + + /* Enable HSE */ + + regval = getreg32(STM32_RCC_CR); + regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */ + regval |= RCC_CR_HSEON; /* Enable HSE */ + putreg32(regval, STM32_RCC_CR); + + /* Set flash wait states + * Sysclk runs with 72MHz -> 2 waitstates. + * 0WS from 0-24MHz + * 1WS from 24-48MHz + * 2WS from 48-72MHz + */ + + regval = getreg32(STM32_FLASH_ACR); + regval &= ~FLASH_ACR_LATENCY_MASK; + regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE); + putreg32(regval, STM32_FLASH_ACR); + + /* Set up PLL input scaling (with source = PLL2) */ + + regval = getreg32(STM32_RCC_CFGR2); + regval &= ~(RCC_CFGR2_PREDIV2_MASK | RCC_CFGR2_PLL2MUL_MASK | + RCC_CFGR2_PREDIV1SRC_MASK | RCC_CFGR2_PREDIV1_MASK); + regval |= (STM32_PLL_PREDIV2 | STM32_PLL_PLL2MUL | + RCC_CFGR2_PREDIV1SRC_PLL2 | STM32_PLL_PREDIV1); + putreg32(regval, STM32_RCC_CFGR2); + + /* Set the PCLK2 divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_PPRE2_MASK | RCC_CFGR_HPRE_MASK); + regval |= STM32_RCC_CFGR_PPRE2; + regval |= RCC_CFGR_HPRE_SYSCLK; + putreg32(regval, STM32_RCC_CFGR); + + /* Set the PCLK1 divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_PPRE1_MASK; + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); + + /* Enable PLL2 */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLL2ON; + putreg32(regval, STM32_RCC_CR); + + /* Wait for PLL2 ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0); + + /* Setup PLL3 for MII/RMII clock on MCO */ + +#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO) + regval = getreg32(STM32_RCC_CFGR2); + regval &= ~(RCC_CFGR2_PLL3MUL_MASK); + regval |= STM32_PLL_PLL3MUL; + putreg32(regval, STM32_RCC_CFGR2); + + /* Switch PLL3 on */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLL3ON; + putreg32(regval, STM32_RCC_CR); + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL3RDY) == 0); +#endif + + /* Set main PLL source and multiplier */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL_MASK); + regval |= (RCC_CFGR_PLLSRC | STM32_PLL_PLLMUL); + putreg32(regval, STM32_RCC_CFGR); + + /* Switch main PLL on */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLON; + putreg32(regval, STM32_RCC_CR); + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0); + + /* Select PLL as system clock source */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_SW_MASK; + regval |= RCC_CFGR_SW_PLL; + putreg32(regval, STM32_RCC_CFGR); + + /* Wait until PLL is used as the system clock source */ + + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_PLL) == 0); +} +#endif + +/**************************************************************************** + * Name: stm32_stdclockconfig + * + * Description: + * Called to change to new clock based on settings in board.h. This + * version is for the non-Connectivity Line parts. + * + * NOTE: This logic would need to be extended if you need to select low- + * power clocking modes! + ****************************************************************************/ + +#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) && \ + !defined(CONFIG_STM32_CONNECTIVITYLINE) +static void stm32_stdclockconfig(void) +{ + uint32_t regval; + + /* If the PLL is using the HSE, or the HSE is the system clock */ + +#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE) + { + volatile int32_t timeout; + + /* Enable External High-Speed Clock (HSE) */ + + regval = getreg32(STM32_RCC_CR); + regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */ + regval |= RCC_CR_HSEON; /* Enable HSE */ + putreg32(regval, STM32_RCC_CR); + + /* Wait until the HSE is ready (or until a timeout elapsed) */ + + for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the HSERDY flag is the set in the CR */ + + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } + + if (timeout == 0) + { + /* In the case of a timeout starting the HSE, we really don't have a + * strategy. This is almost always a hardware failure or + * misconfiguration. + */ + + return; + } + } + +# if defined(CONFIG_STM32_VALUELINE) && (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) + /* If this is a value-line part and we are using the HSE as the PLL */ + +# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV1 & 1) +# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV1 +# endif + + /* Set the HSE prescaler */ + + regval = STM32_CFGR2_PREDIV1; + putreg32(regval, STM32_RCC_CFGR2); + +# endif +#endif + +#ifndef CONFIG_STM32_VALUELINE + /* Value-line devices don't implement flash prefetch/waitstates */ + /* Enable FLASH prefetch buffer and 2 wait states */ + + regval = getreg32(STM32_FLASH_ACR); + regval &= ~FLASH_ACR_LATENCY_MASK; + regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE); + putreg32(regval, STM32_FLASH_ACR); +#endif + + /* Set the HCLK source/divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_HPRE_MASK; + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); + + /* Set the PCLK2 divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_PPRE2_MASK; + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); + + /* Set the PCLK1 divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_PPRE1_MASK; + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); + +#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL + /* If we are using the PLL, configure and start it */ + /* Set the PLL divider and multiplier */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL_MASK); + regval |= (STM32_CFGR_PLLSRC | STM32_CFGR_PLLXTPRE | STM32_CFGR_PLLMUL); + putreg32(regval, STM32_RCC_CFGR); + + /* Enable the PLL */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLON; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the PLL is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0); + +#endif + + /* Select the system clock source (probably the PLL) */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_SW_MASK; + regval |= STM32_SYSCLK_SW; + putreg32(regval, STM32_RCC_CFGR); + + /* Wait until the selected source is used as the system clock source */ + + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); + +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK) + /* Low speed internal clock source LSI + * + * TODO: There is another case where the LSI needs to + * be enabled: if the MCO pin selects LSI as source. + */ + + stm32_rcc_enablelsi(); +#endif + +#if defined(CONFIG_RTC_LSECLOCK) + /* Low speed external clock source LSE + * + * TODO: There is another case where the LSE needs to + * be enabled: if the MCO pin selects LSE as source. + * + * TODO: There is another case where the LSE needs to + * be enabled: if USARTx selects LSE as source. + */ + + stm32_rcc_enablelse(); +#endif +} +#endif + +/**************************************************************************** + * Name: rcc_enableperiphals + ****************************************************************************/ + +static inline void rcc_enableperipherals(void) +{ + rcc_enableahb(); + rcc_enableapb2(); + rcc_enableapb1(); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32f40xxx_alarm.h b/arch/arm/src/stm32/stm32f40xxx_alarm.h index 5d8d94a1975..2c09bee31b8 100644 --- a/arch/arm/src/stm32/stm32f40xxx_alarm.h +++ b/arch/arm/src/stm32/stm32f40xxx_alarm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/include/stm32/stm32f0xxx_alarm.h + * arch/arm/src/stm32/stm32f0xxx_alarm.h * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Neil hancock - delegated to Gregory Nutt Mar 30, 2016 diff --git a/arch/arm/src/stm32/stm32f40xxx_dma.c b/arch/arm/src/stm32/stm32f40xxx_dma.c index f631c6ea4a6..1824c76bf46 100644 --- a/arch/arm/src/stm32/stm32f40xxx_dma.c +++ b/arch/arm/src/stm32/stm32f40xxx_dma.c @@ -369,7 +369,7 @@ static void stm32_dmastreamdisable(struct stm32_dma_s *dmast) * ************************************************************************************/ -static int stm32_dmainterrupt(int irq, void *context) +static int stm32_dmainterrupt(int irq, void *context, void *arg) { struct stm32_dma_s *dmast; uint32_t status; @@ -481,7 +481,7 @@ void weak_function up_dmainitialize(void) /* Attach DMA interrupt vectors */ - (void)irq_attach(dmast->irq, stm32_dmainterrupt); + (void)irq_attach(dmast->irq, stm32_dmainterrupt, dmast); /* Disable the DMA stream */ diff --git a/arch/arm/src/stm32/stm32f40xxx_i2c.c b/arch/arm/src/stm32/stm32f40xxx_i2c.c index 2bb715c4a87..be15a27be00 100644 --- a/arch/arm/src/stm32/stm32f40xxx_i2c.c +++ b/arch/arm/src/stm32/stm32f40xxx_i2c.c @@ -230,7 +230,7 @@ struct stm32_i2c_config_s uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ #ifndef CONFIG_I2C_POLLED - int (*isr)(int, void *); /* Interrupt handler */ + int (*isr)(int, void *, void *); /* Interrupt handler */ uint32_t ev_irq; /* Event IRQ */ uint32_t er_irq; /* Error IRQ */ #endif @@ -319,13 +319,13 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv); #ifndef CONFIG_I2C_POLLED #ifdef CONFIG_STM32_I2C1 -static int stm32_i2c1_isr(int irq, void *context); +static int stm32_i2c1_isr(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_STM32_I2C2 -static int stm32_i2c2_isr(int irq, void *context); +static int stm32_i2c2_isr(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_STM32_I2C3 -static int stm32_i2c3_isr(int irq, void *context); +static int stm32_i2c3_isr(int irq, void *context, FAR void *arg); #endif #endif /* !CONFIG_I2C_POLLED */ @@ -1878,7 +1878,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) #ifndef CONFIG_I2C_POLLED #ifdef CONFIG_STM32_I2C1 -static int stm32_i2c1_isr(int irq, void *context) +static int stm32_i2c1_isr(int irq, void *context, FAR void *arg) { return stm32_i2c_isr(&stm32_i2c1_priv); } @@ -1893,7 +1893,7 @@ static int stm32_i2c1_isr(int irq, void *context) ************************************************************************************/ #ifdef CONFIG_STM32_I2C2 -static int stm32_i2c2_isr(int irq, void *context) +static int stm32_i2c2_isr(int irq, void *context, FAR void *arg) { return stm32_i2c_isr(&stm32_i2c2_priv); } @@ -1908,7 +1908,7 @@ static int stm32_i2c2_isr(int irq, void *context) ************************************************************************************/ #ifdef CONFIG_STM32_I2C3 -static int stm32_i2c3_isr(int irq, void *context) +static int stm32_i2c3_isr(int irq, void *context, FAR void *arg) { return stm32_i2c_isr(&stm32_i2c3_priv); } @@ -1953,8 +1953,8 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv) /* Attach ISRs */ #ifndef CONFIG_I2C_POLLED - irq_attach(priv->config->ev_irq, priv->config->isr); - irq_attach(priv->config->er_irq, priv->config->isr); + irq_attach(priv->config->ev_irq, priv->config->isr, NULL); + irq_attach(priv->config->er_irq, priv->config->isr, NULL); up_enable_irq(priv->config->ev_irq); up_enable_irq(priv->config->er_irq); #endif diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c index cbd136d6d53..c0801a4a8f8 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c +++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c @@ -847,7 +847,7 @@ static inline void rtc_enable_alarm(void) * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B). */ - stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler); + stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler, NULL); g_alarm_enabled = true; } } diff --git a/arch/arm/src/stm32f7/stm32_adc.c b/arch/arm/src/stm32f7/stm32_adc.c index df9232048e8..df3ab7028e2 100644 --- a/arch/arm/src/stm32f7/stm32_adc.c +++ b/arch/arm/src/stm32f7/stm32_adc.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/stm32f7/stm32_adc.c * - * Copyright (C) 2011, 2013, 2015-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013, 2015-2017 Gregory Nutt. All rights reserved. * Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved. * Authors: Gregory Nutt * Diego Sanchez @@ -60,8 +60,9 @@ #include #include #include -#include #include +#include +#include #include "up_internal.h" #include "up_arch.h" @@ -257,7 +258,7 @@ static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset); /* ADC Interrupt Handler */ static int adc_interrupt(FAR struct adc_dev_s *dev); -static int adc123_interrupt(int irq, FAR void *context); +static int adc123_interrupt(int irq, FAR void *context, FAR void *arg); /* ADC Driver Methods */ @@ -1372,7 +1373,7 @@ static int adc_setup(FAR struct adc_dev_s *dev) /* Attach the ADC interrupt */ - ret = irq_attach(priv->irq, priv->isr); + ret = irq_attach(priv->irq, priv->isr, NULL); if (ret < 0) { ainfo("irq_attach failed: %d\n", ret); @@ -1677,7 +1678,7 @@ static int adc_interrupt(FAR struct adc_dev_s *dev) * ****************************************************************************/ -static int adc123_interrupt(int irq, FAR void *context) +static int adc123_interrupt(int irq, FAR void *context, FAR void *arg) { #ifdef CONFIG_STM32F7_ADC1 adc_interrupt(&g_adcdev1); diff --git a/arch/arm/src/stm32f7/stm32_allocateheap.c b/arch/arm/src/stm32f7/stm32_allocateheap.c index 8b21ad68b76..ffa6d27455b 100644 --- a/arch/arm/src/stm32f7/stm32_allocateheap.c +++ b/arch/arm/src/stm32f7/stm32_allocateheap.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/stm32f7/up_allocateheap.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -57,10 +57,12 @@ #include "up_arch.h" #include "up_internal.h" #include "stm32_mpuinit.h" +#include "stm32_dtcm.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Internal SRAM is available in all members of the STM32 family. The * following definitions must be provided to specify the size and * location of internal(system) SRAM: @@ -92,6 +94,20 @@ #define SRAM2_START STM32_SRAM2_BASE #define SRAM2_END (SRAM2_START + STM32F7_SRAM2_SIZE) +/* The STM32 F7 has DTCM memory */ + +#undef HAVE_DTCM +#define HAVE_DTCM 1 +#if !defined(DTCM_START) || !defined(DTCM_END) +# undef HAVE_DTCM +#endif + +/* DTCM to be excluded from the main heap. */ + +#ifdef CONFIG_STM32F7_DTCMEXCLUDE +# undef HAVE_DTCM +#endif + /* We can't possibly have FSMC SRAM if the FSMC is not enabled */ #ifndef CONFIG_STM32F7_FSMC @@ -110,7 +126,7 @@ # endif #endif -/* There are 3 possible heap configurations: +/* There are 4 possible heap configurations: * * Configuration 1. System SRAM1 (only) * CONFIG_MM_REGIONS == 1 @@ -118,9 +134,18 @@ * Configuration 2. System SRAM1 and SRAM2 * CONFIG_MM_REGIONS == 2 * CONFIG_STM32F7_FSMC_SRAM NOT defined - * Configuration 3. System SRAM1 and SRAM2 and FSMC SRAM + * Configuration 3. System SRAM1 and SRAM2 and DTCM + * CONFIG_MM_REGIONS == 3 + * CONFIG_STM32F7_FSMC_SRAM undefined + * HAVE_DTCM defined + * Configuration 4. System SRAM1 and SRAM2 and FSMC SRAM * CONFIG_MM_REGIONS == 3 * CONFIG_STM32F7_FSMC_SRAM defined + * HAVE_DTCM undefined + * Configuration 5. System SRAM1 and SRAM2 and DTCM and FSMC SRAM + * CONFIG_MM_REGIONS == 4 + * CONFIG_STM32F7_FSMC_SRAM defined + * HAVE_DTCM defined * * Let's make sure that all definitions are consistent before doing * anything else @@ -128,24 +153,48 @@ #if CONFIG_MM_REGIONS < 2 # ifdef CONFIG_STM32F7_FSMC_SRAM -# warning FSMC SRAM and SRAM2 excluded from the heap -# else -# warning "SRAM2 excluded from the heap" +# warning "FSMC SRAM excluded from the heap" +# undef CONFIG_STM32F7_FSMC_SRAM # endif +# ifdef HAVE_DTCM +# warning "DTCM excluded from the heap" +# undef HAVE_DTCM +# endif +# warning "SRAM2 excluded from the heap" #elif CONFIG_MM_REGIONS < 3 # ifdef CONFIG_STM32F7_FSMC_SRAM -# warning FSMC SRAM excluded from the heap +# warning "FSMC SRAM excluded from the heap" +# undef CONFIG_STM32F7_FSMC_SRAM +# endif +# ifdef HAVE_DTCM +# warning "DTCM excluded from the heap" +# undef HAVE_DTCM # endif #elif CONFIG_MM_REGIONS < 4 -# ifndef CONFIG_STM32F7_FSMC_SRAM -# error CONFIG_MM_REGIONS > 2 but I do not know what some of the region(s) are +# if defined(CONFIG_STM32F7_FSMC_SRAM) && defined(HAVE_DTCM) +# warning "CONFIG_MM_REGIONS == 3 but have both FSMC SRAM and DTCM. DTCM excluded from the heap." +# undef HAVE_DTCM +# elif !defined(CONFIG_STM32F7_FSMC_SRAM) && !defined(HAVE_DTCM) +# error "CONFIG_MM_REGIONS == 3 but I do not know what some of the region(s) are" # undef CONFIG_MM_REGIONS # define CONFIG_MM_REGIONS 2 # endif +#elif CONFIG_MM_REGIONS < 5 +# if !defined(CONFIG_STM32F7_FSMC_SRAM) && !defined(HAVE_DTCM) +# error "CONFIG_MM_REGIONS == 4 but I do not know what some of the region(s) are" +# undef CONFIG_MM_REGIONS +# define CONFIG_MM_REGIONS 2 +# elif !defined(CONFIG_STM32F7_FSMC_SRAM) || !defined(HAVE_DTCM) +# error "CONFIG_MM_REGIONS == 4 but I do not know what some of the region(s) are" +# undef CONFIG_MM_REGIONS +# define CONFIG_MM_REGIONS 3 +# endif #else -# error CONFIG_MM_REGIONS > 3 but I do not know what some of the region(s) are +# error "CONFIG_MM_REGIONS > 4 but I do not know what some of the region(s) are" # undef CONFIG_MM_REGIONS -# ifdef CONFIG_STM32F7_FSMC_SRAM +# if defined(CONFIG_STM32F7_FSMC_SRAM) && defined(HAVE_DTCM) +# define CONFIG_MM_REGIONS 4 +# elif defined(CONFIG_STM32F7_FSMC_SRAM) || defined(HAVE_DTCM) # define CONFIG_MM_REGIONS 3 # else # define CONFIG_MM_REGIONS 2 @@ -338,6 +387,24 @@ void up_addregion(void) kumm_addregion((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START); +#ifdef HAVE_DTCM +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + + /* Allow user-mode access to the DTCM heap */ + + stm32_mpu_uheap((uintptr_t)DTCM_START, DTCM_END-DTCM_START); + +#endif + + /* Colorize the heap for debug */ + + up_heap_color((FAR void *)DTCM_START, DTCM_END-DTCM_START); + + /* Add the DTCM user heap region. */ + + kumm_addregion((FAR void *)DTCM_START, DTCM_END-DTCM_START); +#endif + #ifdef CONFIG_STM32F7_FSMC_SRAM #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index a695a07adf5..e1d8256f091 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -369,7 +369,7 @@ static void stm32_dmastreamdisable(struct stm32_dma_s *dmast) * ************************************************************************************/ -static int stm32_dmainterrupt(int irq, void *context) +static int stm32_dmainterrupt(int irq, void *context, FAR void *arg) { struct stm32_dma_s *dmast; uint32_t status; @@ -482,7 +482,7 @@ void weak_function up_dmainitialize(void) /* Attach DMA interrupt vectors */ - (void)irq_attach(dmast->irq, stm32_dmainterrupt); + (void)irq_attach(dmast->irq, stm32_dmainterrupt, dmast); /* Disable the DMA stream */ diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index b84e8511ac8..0450dadab90 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/stm32f7/stm32_ethernet.c * - * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -701,7 +701,7 @@ static void stm32_freeframe(struct stm32_ethmac_s *priv); static void stm32_txdone(struct stm32_ethmac_s *priv); static void stm32_interrupt_work(void *arg); -static int stm32_interrupt(int irq, void *context); +static int stm32_interrupt(int irq, void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -2040,17 +2040,32 @@ static void stm32_txdone(struct stm32_ethmac_s *priv) if (priv->inflight <= 0) { + int delay; + /* Cancel the TX timeout */ wd_cancel(priv->txtimeout); - /* Then make sure that the TX poll timer is running (if it is already - * running, the following would restart it). This is necessary to - * avoid certain race conditions where the polling sequence can be - * interrupted. + /* Check if the poll timer is running. If it is not, then start it + * now. There is a race condition here: We may test the time + * remaining on the poll timer and determine that it is still running, + * but then the timer expires immiately. That should not be problem, + * however, the poll timer processing should be in the work queue and + * should execute immediately after we complete the TX poll. + * Inefficient, but not fatal. */ - (void)wd_start(priv->txpoll, STM32_WDDELAY, stm32_poll_expiry, 1, priv); + delay = wd_gettime(priv->txpoll); + if (delay <= 0) + { + /* The poll timer is not running .. restart it. This is necessary + * to avoid certain race conditions where the polling sequence can + * be interrupted. + */ + + (void)wd_start(priv->txpoll, STM32_WDDELAY, stm32_poll_expiry, + 1, priv); + } /* And disable further TX interrupts. */ @@ -2185,7 +2200,7 @@ static void stm32_interrupt_work(void *arg) * ****************************************************************************/ -static int stm32_interrupt(int irq, void *context) +static int stm32_interrupt(int irq, void *context, FAR void *arg) { struct stm32_ethmac_s *priv = &g_stm32ethmac[0]; uint32_t dmasr; @@ -4121,7 +4136,7 @@ int stm32_ethinitialize(int intf) /* Attach the IRQ to the driver */ - if (irq_attach(STM32_IRQ_ETH, stm32_interrupt)) + if (irq_attach(STM32_IRQ_ETH, stm32_interrupt, NULL)) { /* We could not attach the ISR to the interrupt */ diff --git a/arch/arm/src/stm32f7/stm32_exti.h b/arch/arm/src/stm32f7/stm32_exti.h index 38ed8a1d6ed..03c621f7b6b 100644 --- a/arch/arm/src/stm32f7/stm32_exti.h +++ b/arch/arm/src/stm32f7/stm32_exti.h @@ -78,6 +78,7 @@ extern "C" * - fallingedge: Enables interrupt on falling edges * - event: Generate event when set * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback * * Returns: * The previous value of the interrupt handler function pointer. This @@ -87,7 +88,7 @@ extern "C" ****************************************************************************/ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func); + bool event, xcpt_t func, void *arg); /**************************************************************************** * Name: stm32_exti_alarm @@ -100,6 +101,7 @@ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, * - fallingedge: Enables interrupt on falling edges * - event: Generate event when set * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback * * Returns: * The previous value of the interrupt handler function pointer. This @@ -109,7 +111,8 @@ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -xcpt_t stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func); +xcpt_t stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, + xcpt_t func, void *arg); #endif #undef EXTERN diff --git a/arch/arm/src/stm32f7/stm32_exti_alarm.c b/arch/arm/src/stm32f7/stm32_exti_alarm.c index ff53915178a..363166cfec0 100644 --- a/arch/arm/src/stm32f7/stm32_exti_alarm.c +++ b/arch/arm/src/stm32f7/stm32_exti_alarm.c @@ -67,7 +67,8 @@ /* Interrupt handlers attached to the ALARM EXTI */ -static xcpt_t stm32_exti_callback; +static xcpt_t g_alarm_callback; +static void *g_callback_arg; /**************************************************************************** * Public Data @@ -85,7 +86,7 @@ static xcpt_t stm32_exti_callback; * ****************************************************************************/ -static int stm32_exti_alarm_isr(int irq, void *context) +static int stm32_exti_alarm_isr(int irq, void *context, FAR void *arg) { int ret = OK; @@ -95,9 +96,9 @@ static int stm32_exti_alarm_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32_exti_callback) + if (g_alarm_callback != NULL) { - ret = stm32_exti_callback(irq, context); + ret = g_alarm_callback(irq, context, g_callback_arg); } return ret; @@ -117,6 +118,7 @@ static int stm32_exti_alarm_isr(int irq, void *context) * - rising/falling edge: enables interrupt on rising/falling edget * - event: generate event when set * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback * * Returns: * The previous value of the interrupt handler function pointer. This @@ -126,20 +128,21 @@ static int stm32_exti_alarm_isr(int irq, void *context) ****************************************************************************/ xcpt_t stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, - xcpt_t func) + xcpt_t func, void *arg) { xcpt_t oldhandler; /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ - oldhandler = stm32_exti_callback; - stm32_exti_callback = func; + oldhandler = g_alarm_callback; + g_alarm_callback = func; + g_callback_arg = arg; /* Install external interrupt handlers (if not already attached) */ if (func) { - irq_attach(STM32_IRQ_RTCALRM, stm32_exti_alarm_isr); + irq_attach(STM32_IRQ_RTCALRM, stm32_exti_alarm_isr, NULL); up_enable_irq(STM32_IRQ_RTCALRM); } else diff --git a/arch/arm/src/stm32f7/stm32_exti_gpio.c b/arch/arm/src/stm32f7/stm32_exti_gpio.c index ec4cd1a7d71..22efc0bf419 100644 --- a/arch/arm/src/stm32f7/stm32_exti_gpio.c +++ b/arch/arm/src/stm32f7/stm32_exti_gpio.c @@ -68,13 +68,23 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct gpio_callback_s +{ + xcpt_t callback; + void *arg; +}; + /**************************************************************************** * Private Data ****************************************************************************/ /* Interrupt handlers attached to each EXTI */ -static xcpt_t stm32_exti_callbacks[16]; +static struct gpio_callback_s g_gpio_callbacks[16]; /**************************************************************************** * Private Functions @@ -84,7 +94,7 @@ static xcpt_t stm32_exti_callbacks[16]; * Interrupt Service Routines - Dispatchers ****************************************************************************/ -static int stm32_exti0_isr(int irq, void *context) +static int stm32_exti0_isr(int irq, void *context, void *arg) { int ret = OK; @@ -94,15 +104,18 @@ static int stm32_exti0_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32_exti_callbacks[0]) + if (g_gpio_callbacks[0].callback != NULL) { - ret = stm32_exti_callbacks[0](irq, context); + xcpt_t callback = g_gpio_callbacks[0].callback; + void *cbarg = g_gpio_callbacks[0].arg; + + ret = callback(irq, context, cbarg); } return ret; } -static int stm32_exti1_isr(int irq, void *context) +static int stm32_exti1_isr(int irq, void *context, void *arg) { int ret = OK; @@ -112,15 +125,18 @@ static int stm32_exti1_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32_exti_callbacks[1]) + if (g_gpio_callbacks[1].callback != NULL) { - ret = stm32_exti_callbacks[1](irq, context); + xcpt_t callback = g_gpio_callbacks[1].callback; + void *cbarg = g_gpio_callbacks[1].arg; + + ret = callback(irq, context, cbarg); } return ret; } -static int stm32_exti2_isr(int irq, void *context) +static int stm32_exti2_isr(int irq, void *context, void *arg) { int ret = OK; @@ -130,15 +146,18 @@ static int stm32_exti2_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32_exti_callbacks[2]) + if (g_gpio_callbacks[2].callback != NULL) { - ret = stm32_exti_callbacks[2](irq, context); + xcpt_t callback = g_gpio_callbacks[2].callback; + void *cbarg = g_gpio_callbacks[2].arg; + + ret = callback(irq, context, cbarg); } return ret; } -static int stm32_exti3_isr(int irq, void *context) +static int stm32_exti3_isr(int irq, void *context, void *arg) { int ret = OK; @@ -148,15 +167,18 @@ static int stm32_exti3_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32_exti_callbacks[3]) + if (g_gpio_callbacks[3].callback != NULL) { - ret = stm32_exti_callbacks[3](irq, context); + xcpt_t callback = g_gpio_callbacks[3].callback; + void *cbarg = g_gpio_callbacks[3].arg; + + ret = callback(irq, context, cbarg); } return ret; } -static int stm32_exti4_isr(int irq, void *context) +static int stm32_exti4_isr(int irq, void *context, void *arg) { int ret = OK; @@ -166,9 +188,12 @@ static int stm32_exti4_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32_exti_callbacks[4]) + if (g_gpio_callbacks[4].callback != NULL) { - ret = stm32_exti_callbacks[4](irq, context); + xcpt_t callback = g_gpio_callbacks[4].callback; + void *cbarg = g_gpio_callbacks[4].arg; + + ret = callback(irq, context, cbarg); } return ret; @@ -199,10 +224,14 @@ static int stm32_exti_multiisr(int irq, void *context, int first, int last) /* And dispatch the interrupt to the handler */ - if (stm32_exti_callbacks[pin]) + if (g_gpio_callbacks[pin].callback != NULL) { - int tmp = stm32_exti_callbacks[pin](irq, context); - if (tmp != OK) + xcpt_t callback = g_gpio_callbacks[pin].callback; + void *cbarg = g_gpio_callbacks[pin].arg; + int tmp; + + tmp = callback(irq, context, cbarg); + if (tmp < 0) { ret = tmp; } @@ -213,12 +242,12 @@ static int stm32_exti_multiisr(int irq, void *context, int first, int last) return ret; } -static int stm32_exti95_isr(int irq, void *context) +static int stm32_exti95_isr(int irq, void *context, void *arg) { return stm32_exti_multiisr(irq, context, 5, 9); } -static int stm32_exti1510_isr(int irq, void *context) +static int stm32_exti1510_isr(int irq, void *context, void *arg) { return stm32_exti_multiisr(irq, context, 10, 15); } @@ -239,6 +268,7 @@ static int stm32_exti1510_isr(int irq, void *context) * - fallingedge: Enables interrupt on falling edges * - event: Generate event when set * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback * * Returns: * The previous value of the interrupt handler function pointer. This @@ -248,15 +278,15 @@ static int stm32_exti1510_isr(int irq, void *context) ****************************************************************************/ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func) + bool event, xcpt_t func, void *arg) { + struct gpio_callback_s *shared_cbs; uint32_t pin = pinset & GPIO_PIN_MASK; uint32_t exti = STM32_EXTI_BIT(pin); int irq; xcpt_t handler; xcpt_t oldhandler = NULL; int nshared; - xcpt_t *shared_cbs; int i; /* Select the interrupt handler for this EXTI pin */ @@ -265,7 +295,7 @@ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, { irq = pin + STM32_IRQ_EXTI0; nshared = 1; - shared_cbs = &stm32_exti_callbacks[pin]; + shared_cbs = &g_gpio_callbacks[pin]; switch (pin) { case 0: @@ -293,27 +323,28 @@ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, { irq = STM32_IRQ_EXTI95; handler = stm32_exti95_isr; - shared_cbs = &stm32_exti_callbacks[5]; + shared_cbs = &g_gpio_callbacks[5]; nshared = 5; } else { irq = STM32_IRQ_EXTI1510; handler = stm32_exti1510_isr; - shared_cbs = &stm32_exti_callbacks[10]; + shared_cbs = &g_gpio_callbacks[10]; nshared = 6; } /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ - oldhandler = stm32_exti_callbacks[pin]; - stm32_exti_callbacks[pin] = func; + oldhandler = g_gpio_callbacks[pin].callback; + g_gpio_callbacks[pin].callback = func; + g_gpio_callbacks[pin].arg = arg; /* Install external interrupt handlers */ if (func) { - irq_attach(irq, handler); + irq_attach(irq, handler, NULL); up_enable_irq(irq); } else @@ -324,7 +355,7 @@ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, for (i = 0; i < nshared; i++) { - if (shared_cbs[i] != NULL) + if (shared_cbs[i].callback != NULL) { break; } diff --git a/arch/arm/src/stm32f7/stm32_exti_pwr.c b/arch/arm/src/stm32f7/stm32_exti_pwr.c index 104dbff0105..54239c777ad 100644 --- a/arch/arm/src/stm32f7/stm32_exti_pwr.c +++ b/arch/arm/src/stm32f7/stm32_exti_pwr.c @@ -70,7 +70,8 @@ /* Interrupt handlers attached to the PVD EXTI */ -static xcpt_t stm32_exti_pvd_callback; +static xcpt_t g_pvd_callback; +static void *g_callback_arg; /**************************************************************************** * Public Data @@ -88,7 +89,7 @@ static xcpt_t stm32_exti_pvd_callback; * ****************************************************************************/ -static int stm32_exti_pvd_isr(int irq, void *context) +static int stm32_exti_pvd_isr(int irq, void *context, void *arg) { int ret = OK; @@ -98,9 +99,9 @@ static int stm32_exti_pvd_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32_exti_pvd_callback) + if (g_pvd_callback) { - ret = stm32_exti_pvd_callback(irq, context); + ret = g_pvd_callback(irq, context, g_callback_arg); } return ret; @@ -129,20 +130,21 @@ static int stm32_exti_pvd_isr(int irq, void *context) ****************************************************************************/ xcpt_t stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, - xcpt_t func) + xcpt_t func, void *arg) { xcpt_t oldhandler; /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ - oldhandler = stm32_exti_pvd_callback; - stm32_exti_pvd_callback = func; + oldhandler = g_pvd_callback; + g_pvd_callback = func; + g_callback_arg = arg; /* Install external interrupt handlers (if not already attached) */ if (func) { - irq_attach(STM32_IRQ_PVD, stm32_exti_pvd_isr); + irq_attach(STM32_IRQ_PVD, stm32_exti_pvd_isr, NULL); up_enable_irq(STM32_IRQ_PVD); } else diff --git a/arch/arm/src/stm32f7/stm32_exti_pwr.h b/arch/arm/src/stm32f7/stm32_exti_pwr.h index b72acd5cc9f..521e7a7b2a7 100644 --- a/arch/arm/src/stm32f7/stm32_exti_pwr.h +++ b/arch/arm/src/stm32f7/stm32_exti_pwr.h @@ -58,6 +58,7 @@ * - rising/falling edge: enables interrupt on rising/falling edge * - event: generate event when set * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback * * Returns: * The previous value of the interrupt handler function pointer. This @@ -67,6 +68,6 @@ ****************************************************************************/ xcpt_t stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, - xcpt_t func); + xcpt_t func, void *arg); #endif /* __ARCH_ARM_SRC_STM32F7_STM32_EXTI_PWR_H */ diff --git a/arch/arm/src/stm32f7/stm32_gpio.h b/arch/arm/src/stm32f7/stm32_gpio.h index f79b398b7a1..70bb15897a4 100644 --- a/arch/arm/src/stm32f7/stm32_gpio.h +++ b/arch/arm/src/stm32f7/stm32_gpio.h @@ -315,27 +315,29 @@ void stm32_gpiowrite(uint32_t pinset, bool value); bool stm32_gpioread(uint32_t pinset); -/************************************************************************************ +/**************************************************************************** * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. * * Parameters: - * - pinset: gpio pin configuration - * - rising/falling edge: enables - * - event: generate event when set - * - func: when non-NULL, generate interrupt + * - pinset: GPIO pin configuration + * - risingedge: Enables interrupt on rising edges + * - fallingedge: Enables interrupt on falling edges + * - event: Generate event when set + * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback * * Returns: - * The previous value of the interrupt handler function pointer. This value may, - * for example, be used to restore the previous handler when multiple handlers are - * used. + * The previous value of the interrupt handler function pointer. This + * value may, for example, be used to restore the previous handler when + * multiple handlers are used. * - ************************************************************************************/ + ****************************************************************************/ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func); + bool event, xcpt_t func, void *arg); /************************************************************************************ * Function: stm32_dumpgpio diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index d089db9623b..c98a1bd2251 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -402,7 +402,7 @@ struct stm32_i2c_config_s uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ #ifndef CONFIG_I2C_POLLED - int (*isr)(int, void *); /* Interrupt handler */ + int (*isr)(int, void *, void *); /* Interrupt handler */ uint32_t ev_irq; /* Event IRQ */ uint32_t er_irq; /* Error IRQ */ #endif @@ -487,16 +487,16 @@ static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv); static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv); #ifndef CONFIG_I2C_POLLED # ifdef CONFIG_STM32F7_I2C1 -static int stm32_i2c1_isr(int irq, void *context); +static int stm32_i2c1_isr(int irq, void *context, FAR void *arg); # endif # ifdef CONFIG_STM32F7_I2C2 -static int stm32_i2c2_isr(int irq, void *context); +static int stm32_i2c2_isr(int irq, void *context, FAR void *arg); # endif # ifdef CONFIG_STM32F7_I2C3 -static int stm32_i2c3_isr(int irq, void *context); +static int stm32_i2c3_isr(int irq, void *context, FAR void *arg); # endif # ifdef CONFIG_STM32F7_I2C4 -static int stm32_i2c4_isr(int irq, void *context); +static int stm32_i2c4_isr(int irq, void *context, FAR void *arg); # endif #endif static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv); @@ -2152,7 +2152,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) #ifndef CONFIG_I2C_POLLED # ifdef CONFIG_STM32F7_I2C1 -static int stm32_i2c1_isr(int irq, void *context) +static int stm32_i2c1_isr(int irq, void *context, FAR void *arg) { return stm32_i2c_isr(&stm32_i2c1_priv); } @@ -2167,7 +2167,7 @@ static int stm32_i2c1_isr(int irq, void *context) ************************************************************************************/ # ifdef CONFIG_STM32F7_I2C2 -static int stm32_i2c2_isr(int irq, void *context) +static int stm32_i2c2_isr(int irq, void *context, FAR void *arg) { return stm32_i2c_isr(&stm32_i2c2_priv); } @@ -2182,7 +2182,7 @@ static int stm32_i2c2_isr(int irq, void *context) ************************************************************************************/ # ifdef CONFIG_STM32F7_I2C3 -static int stm32_i2c3_isr(int irq, void *context) +static int stm32_i2c3_isr(int irq, void *context, FAR void *arg) { return stm32_i2c_isr(&stm32_i2c3_priv); } @@ -2197,7 +2197,7 @@ static int stm32_i2c3_isr(int irq, void *context) ************************************************************************************/ # ifdef CONFIG_STM32F7_I2C4 -static int stm32_i2c4_isr(int irq, void *context) +static int stm32_i2c4_isr(int irq, void *context, FAR void *arg) { return stm32_i2c_isr(&stm32_i2c4_priv); } @@ -2242,8 +2242,8 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv) #ifndef CONFIG_I2C_POLLED /* Attach error and event interrupts to the ISRs */ - irq_attach(priv->config->ev_irq, priv->config->isr); - irq_attach(priv->config->er_irq, priv->config->isr); + irq_attach(priv->config->ev_irq, priv->config->isr, NULL); + irq_attach(priv->config->er_irq, priv->config->isr, NULL); up_enable_irq(priv->config->ev_irq); up_enable_irq(priv->config->er_irq); #endif diff --git a/arch/arm/src/stm32f7/stm32_irq.c b/arch/arm/src/stm32f7/stm32_irq.c index 758f32b1477..b2407501036 100644 --- a/arch/arm/src/stm32f7/stm32_irq.c +++ b/arch/arm/src/stm32f7/stm32_irq.c @@ -186,7 +186,7 @@ static void stm32_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int stm32_nmi(int irq, FAR void *context) +static int stm32_nmi(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -194,7 +194,7 @@ static int stm32_nmi(int irq, FAR void *context) return 0; } -static int stm32_busfault(int irq, FAR void *context) +static int stm32_busfault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); @@ -202,7 +202,7 @@ static int stm32_busfault(int irq, FAR void *context) return 0; } -static int stm32_usagefault(int irq, FAR void *context) +static int stm32_usagefault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); @@ -210,7 +210,7 @@ static int stm32_usagefault(int irq, FAR void *context) return 0; } -static int stm32_pendsv(int irq, FAR void *context) +static int stm32_pendsv(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -218,7 +218,7 @@ static int stm32_pendsv(int irq, FAR void *context) return 0; } -static int stm32_dbgmonitor(int irq, FAR void *context) +static int stm32_dbgmonitor(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -226,7 +226,7 @@ static int stm32_dbgmonitor(int irq, FAR void *context) return 0; } -static int stm32_reserved(int irq, FAR void *context) +static int stm32_reserved(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -469,8 +469,8 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32_IRQ_SVCALL, up_svcall); - irq_attach(STM32_IRQ_HARDFAULT, up_hardfault); + irq_attach(STM32_IRQ_SVCALL, up_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, up_hardfault, NULL); /* Set the priority of the SVCall interrupt */ @@ -486,22 +486,22 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(STM32_IRQ_MEMFAULT, up_memfault); + irq_attach(STM32_IRQ_MEMFAULT, up_memfault, NULL); up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32_IRQ_NMI, stm32_nmi); + irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(STM32_IRQ_MEMFAULT, up_memfault); + irq_attach(STM32_IRQ_MEMFAULT, up_memfault, NULL); #endif - irq_attach(STM32_IRQ_BUSFAULT, stm32_busfault); - irq_attach(STM32_IRQ_USAGEFAULT, stm32_usagefault); - irq_attach(STM32_IRQ_PENDSV, stm32_pendsv); - irq_attach(STM32_IRQ_DBGMONITOR, stm32_dbgmonitor); - irq_attach(STM32_IRQ_RESERVED, stm32_reserved); + irq_attach(STM32_IRQ_BUSFAULT, stm32_busfault, NULL); + irq_attach(STM32_IRQ_USAGEFAULT, stm32_usagefault, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); + irq_attach(STM32_IRQ_DBGMONITOR, stm32_dbgmonitor, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); #endif stm32_dumpnvic("initial", STM32_IRQ_NIRQS); diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c index 9bf818182b4..ff2a6e026ee 100644 --- a/arch/arm/src/stm32f7/stm32_otgdev.c +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -650,7 +650,7 @@ static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv); /* First level interrupt processing */ -static int stm32_usbinterrupt(int irq, FAR void *context); +static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg); /* Endpoint operations *********************************************************/ /* Global OUT NAK controls */ @@ -3572,7 +3572,7 @@ static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv) * ****************************************************************************/ -static int stm32_usbinterrupt(int irq, FAR void *context) +static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) { /* At present, there is only a single OTG device support. Hence it is * pre-allocated as g_otghsdev. However, in most code, the private data @@ -5557,7 +5557,7 @@ void up_usbinitialize(void) /* Attach the OTG interrupt handler */ - ret = irq_attach(STM32_IRQ_OTG, stm32_usbinterrupt); + ret = irq_attach(STM32_IRQ_OTG, stm32_usbinterrupt, NULL); if (ret < 0) { uerr("irq_attach failed\n", ret); diff --git a/arch/arm/src/stm32f7/stm32_otghost.c b/arch/arm/src/stm32f7/stm32_otghost.c index 12488c262f0..9eb12159e7d 100644 --- a/arch/arm/src/stm32f7/stm32_otghost.c +++ b/arch/arm/src/stm32f7/stm32_otghost.c @@ -406,7 +406,7 @@ static inline void stm32_gint_ipxfrisr(FAR struct stm32_usbhost_s *priv); /* First level, global interrupt handler */ -static int stm32_gint_isr(int irq, FAR void *context); +static int stm32_gint_isr(int irq, FAR void *context, FAR void *arg); /* Interrupt controls */ @@ -3430,7 +3430,7 @@ static inline void stm32_gint_ipxfrisr(FAR struct stm32_usbhost_s *priv) * ****************************************************************************/ -static int stm32_gint_isr(int irq, FAR void *context) +static int stm32_gint_isr(int irq, FAR void *context, FAR void *arg) { /* At present, there is only support for a single OTG FS host. Hence it is * pre-allocated as g_usbhost. However, in most code, the private data @@ -5300,7 +5300,7 @@ FAR struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) /* Attach USB host controller interrupt handler */ - if (irq_attach(STM32_IRQ_OTGFS, stm32_gint_isr) != 0) + if (irq_attach(STM32_IRQ_OTGFS, stm32_gint_isr, NULL) != 0) { usbhost_trace1(OTG_TRACE1_IRQATTACH, 0); return NULL; diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index 376f67ce2d3..df02d4fb0e6 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -473,18 +473,18 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, sdio_eventset_t wkupeven static int stm32_sdmmc_interrupt(struct stm32_dev_s *sdmmc_dev); #ifdef CONFIG_STM32F7_SDMMC1 -static int stm32_sdmmc1_interrupt(int irq, void *context); +static int stm32_sdmmc1_interrupt(int irq, void *context, void *arg); #endif #ifdef CONFIG_STM32F7_SDMMC2 -static int stm32_sdmmc2_interrupt(int irq, void *context); +static int stm32_sdmmc2_interrupt(int irq, void *context, void *arg); #endif #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE #ifdef CONFIG_STM32F7_SDMMC1 -static int stm32_sdmmc1_rdyinterrupt(int irq, void *context); +static int stm32_sdmmc1_rdyinterrupt(int irq, void *context, void *arg); #endif #ifdef CONFIG_STM32F7_SDMMC2 -static int stm32_sdmmc2_rdyinterrupt(int irq, void *context); +static int stm32_sdmmc2_rdyinterrupt(int irq, void *context, void *arg); #endif #endif @@ -846,14 +846,16 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, /* Arm the SDMMC_D Ready and install Isr */ - stm32_gpiosetevent(pinset, true, false, false, priv->wrchandler); + stm32_gpiosetevent(pinset, true, false, false, + priv->wrchandler, priv); } /* Disarm SDMMC_D ready */ if ((wkupevent & SDIOWAIT_WRCOMPLETE) != 0) { - stm32_gpiosetevent(priv->d0_gpio, false, false, false , NULL); + stm32_gpiosetevent(priv->d0_gpio, false, false, false, + NULL, NULL); stm32_configgpio(priv->d0_gpio); } #endif @@ -1506,18 +1508,18 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE # if defined(CONFIG_STM32F7_SDMMC1) -static int stm32_sdmmc1_rdyinterrupt(int irq, void *context) +static int stm32_sdmmc1_rdyinterrupt(int irq, void *context, void *arg) { - struct stm32_dev_s *priv = &g_sdmmcdev1; + struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; stm32_endwait(priv, SDIOWAIT_WRCOMPLETE); return OK; } # endif # if defined(CONFIG_STM32F7_SDMMC2) -static int stm32_sdmmc2_rdyinterrupt(int irq, void *context) +static int stm32_sdmmc2_rdyinterrupt(int irq, void *context, void *arg) { - struct stm32_dev_s *priv = &g_sdmmcdev2; + struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; stm32_endwait(priv, SDIOWAIT_WRCOMPLETE); return OK; } @@ -1742,7 +1744,7 @@ static int stm32_sdmmc_interrupt(struct stm32_dev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32F7_SDMMC1 -static int stm32_sdmmc1_interrupt(int irq, void *context) +static int stm32_sdmmc1_interrupt(int irq, void *context, void *arg) { return stm32_sdmmc_interrupt(&g_sdmmcdev1); } @@ -1764,7 +1766,7 @@ static int stm32_sdmmc1_interrupt(int irq, void *context) * ****************************************************************************/ #ifdef CONFIG_STM32F7_SDMMC2 -static int stm32_sdmmc2_interrupt(int irq, void *context) +static int stm32_sdmmc2_interrupt(int irq, void *context, void *arg) { return stm32_sdmmc_interrupt(&g_sdmmcdev2); } @@ -2021,7 +2023,7 @@ static int stm32_attach(FAR struct sdio_dev_s *dev) /* Attach the SDIO interrupt handler */ - ret = irq_attach(priv->nirq, priv->handler); + ret = irq_attach(priv->nirq, priv->handler, NULL); if (ret == OK) { diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c index 1f5445ac710..77138526dd6 100644 --- a/arch/arm/src/stm32f7/stm32_serial.c +++ b/arch/arm/src/stm32f7/stm32_serial.c @@ -281,8 +281,6 @@ struct up_dev_s const unsigned int rxdma_channel; /* DMA channel assigned */ #endif - int (*const vector)(int irq, void *context); /* Interrupt handler */ - /* RX DMA state */ #ifdef SERIAL_HAVE_DMA @@ -308,7 +306,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt_common(struct up_dev_s *dev); +static int up_interrupt(int irq, void *context, FAR void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); #ifndef SERIAL_HAVE_ONLY_DMA static int up_receive(struct uart_dev_s *dev, unsigned int *status); @@ -340,31 +338,6 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); #endif -#ifdef CONFIG_STM32F7_USART1 -static int up_interrupt_usart1(int irq, void *context); -#endif -#ifdef CONFIG_STM32F7_USART2 -static int up_interrupt_usart2(int irq, void *context); -#endif -#ifdef CONFIG_STM32F7_USART3 -static int up_interrupt_usart3(int irq, void *context); -#endif -#ifdef CONFIG_STM32F7_UART4 -static int up_interrupt_uart4(int irq, void *context); -#endif -#ifdef CONFIG_STM32F7_UART5 -static int up_interrupt_uart5(int irq, void *context); -#endif -#ifdef CONFIG_STM32F7_USART6 -static int up_interrupt_usart6(int irq, void *context); -#endif -#ifdef CONFIG_STM32F7_UART7 -static int up_interrupt_uart7(int irq, void *context); -#endif -#ifdef CONFIG_STM32F7_UART8 -static int up_interrupt_uart8(int irq, void *context); -#endif - /**************************************************************************** * Private Data ****************************************************************************/ @@ -554,7 +527,6 @@ static struct up_dev_s g_usart1priv = .rxdma_channel = DMAMAP_USART1_RX, .rxfifo = g_usart1rxfifo, #endif - .vector = up_interrupt_usart1, #ifdef CONFIG_USART1_RS485 .rs485_dir_gpio = GPIO_USART1_RS485_DIR, @@ -616,7 +588,6 @@ static struct up_dev_s g_usart2priv = .rxdma_channel = DMAMAP_USART2_RX, .rxfifo = g_usart2rxfifo, #endif - .vector = up_interrupt_usart2, #ifdef CONFIG_USART2_RS485 .rs485_dir_gpio = GPIO_USART2_RS485_DIR, @@ -678,7 +649,6 @@ static struct up_dev_s g_usart3priv = .rxdma_channel = DMAMAP_USART3_RX, .rxfifo = g_usart3rxfifo, #endif - .vector = up_interrupt_usart3, #ifdef CONFIG_USART3_RS485 .rs485_dir_gpio = GPIO_USART3_RS485_DIR, @@ -744,7 +714,6 @@ static struct up_dev_s g_uart4priv = .rxdma_channel = DMAMAP_UART4_RX, .rxfifo = g_uart4rxfifo, #endif - .vector = up_interrupt_uart4, #ifdef CONFIG_UART4_RS485 .rs485_dir_gpio = GPIO_UART4_RS485_DIR, @@ -810,7 +779,6 @@ static struct up_dev_s g_uart5priv = .rxdma_channel = DMAMAP_UART5_RX, .rxfifo = g_uart5rxfifo, #endif - .vector = up_interrupt_uart5, #ifdef CONFIG_UART5_RS485 .rs485_dir_gpio = GPIO_UART5_RS485_DIR, @@ -872,7 +840,6 @@ static struct up_dev_s g_usart6priv = .rxdma_channel = DMAMAP_USART6_RX, .rxfifo = g_usart6rxfifo, #endif - .vector = up_interrupt_usart6, #ifdef CONFIG_USART6_RS485 .rs485_dir_gpio = GPIO_USART6_RS485_DIR, @@ -934,7 +901,6 @@ static struct up_dev_s g_uart7priv = .rxdma_channel = DMAMAP_UART7_RX, .rxfifo = g_uart7rxfifo, #endif - .vector = up_interrupt_uart7, #ifdef CONFIG_UART7_RS485 .rs485_dir_gpio = GPIO_UART7_RS485_DIR, @@ -996,7 +962,6 @@ static struct up_dev_s g_uart8priv = .rxdma_channel = DMAMAP_UART8_RX, .rxfifo = g_uart8rxfifo, #endif - .vector = up_interrupt_uart8, #ifdef CONFIG_UART8_RS485 .rs485_dir_gpio = GPIO_UART8_RS485_DIR, @@ -1681,7 +1646,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, priv->vector); + ret = irq_attach(priv->irq, up_interrupt, priv); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -1711,7 +1676,7 @@ static void up_detach(struct uart_dev_s *dev) } /**************************************************************************** - * Name: up_interrupt_common + * Name: up_interrupt * * Description: * This is the USART interrupt handler. It will be invoked when an @@ -1722,11 +1687,14 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt_common(struct up_dev_s *priv) +static int up_interrupt(int irq, void *context, FAR void *arg) { + struct up_dev_s *priv = (struct up_dev_s *)arg; int passes; bool handled; + DEBUGASSERT(priv != NULL); + /* Report serial activity to the power management logic */ #if defined(CONFIG_PM) && CONFIG_PM_SERIAL_ACTIVITY > 0 @@ -2501,70 +2469,6 @@ static bool up_txready(struct uart_dev_s *dev) return ((up_serialin(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } -/**************************************************************************** - * Name: up_interrupt_u[s]art[n] - * - * Description: - * Interrupt handlers for U[S]ART[n] where n=1,..,6. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F7_USART1 -static int up_interrupt_usart1(int irq, void *context) -{ - return up_interrupt_common(&g_usart1priv); -} -#endif - -#ifdef CONFIG_STM32F7_USART2 -static int up_interrupt_usart2(int irq, void *context) -{ - return up_interrupt_common(&g_usart2priv); -} -#endif - -#ifdef CONFIG_STM32F7_USART3 -static int up_interrupt_usart3(int irq, void *context) -{ - return up_interrupt_common(&g_usart3priv); -} -#endif - -#ifdef CONFIG_STM32F7_UART4 -static int up_interrupt_uart4(int irq, void *context) -{ - return up_interrupt_common(&g_uart4priv); -} -#endif - -#ifdef CONFIG_STM32F7_UART5 -static int up_interrupt_uart5(int irq, void *context) -{ - return up_interrupt_common(&g_uart5priv); -} -#endif - -#ifdef CONFIG_STM32F7_USART6 -static int up_interrupt_usart6(int irq, void *context) -{ - return up_interrupt_common(&g_usart6priv); -} -#endif - -#ifdef CONFIG_STM32F7_UART7 -static int up_interrupt_uart7(int irq, void *context) -{ - return up_interrupt_common(&g_uart7priv); -} -#endif - -#ifdef CONFIG_STM32F7_UART8 -static int up_interrupt_uart8(int irq, void *context) -{ - return up_interrupt_common(&g_uart8priv); -} -#endif - /**************************************************************************** * Name: up_dma_rxcallback * diff --git a/arch/arm/src/stm32f7/stm32_tim.c b/arch/arm/src/stm32f7/stm32_tim.c index 84934db13dc..e03076760b3 100644 --- a/arch/arm/src/stm32f7/stm32_tim.c +++ b/arch/arm/src/stm32f7/stm32_tim.c @@ -488,8 +488,7 @@ static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev, } static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, - int (*handler)(int irq, void *context), - int source) + xcpt_t handler, int source) { int vectorno; @@ -584,7 +583,7 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, /* Otherwise set callback and enable interrupt */ - irq_attach(vectorno, handler); + irq_attach(vectorno, handler, NULL); up_enable_irq(vectorno); #ifdef CONFIG_ARCH_IRQPRIO diff --git a/arch/arm/src/stm32f7/stm32_tim.h b/arch/arm/src/stm32f7/stm32_tim.h index c4561288a91..f57fcf1cf3e 100644 --- a/arch/arm/src/stm32f7/stm32_tim.h +++ b/arch/arm/src/stm32f7/stm32_tim.h @@ -167,7 +167,7 @@ struct stm32_tim_ops_s /* Timer interrupts */ - int (*setisr)(FAR struct stm32_tim_dev_s *dev, int (*handler)(int irq, void *context), int source); + int (*setisr)(FAR struct stm32_tim_dev_s *dev, xcpt_t handler, int source); void (*enableint)(FAR struct stm32_tim_dev_s *dev, int source); void (*disableint)(FAR struct stm32_tim_dev_s *dev, int source); void (*ackint)(FAR struct stm32_tim_dev_s *dev, int source); @@ -183,7 +183,7 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev); +int stm32_tim_deinit(FAR struct stm32_tim_dev_s *dev); /**************************************************************************** * Name: stm32_timer_initialize diff --git a/arch/arm/src/stm32f7/stm32_timerisr.c b/arch/arm/src/stm32f7/stm32_timerisr.c index 07cfd01d0f5..52610882356 100644 --- a/arch/arm/src/stm32f7/stm32_timerisr.c +++ b/arch/arm/src/stm32f7/stm32_timerisr.c @@ -104,7 +104,7 @@ * ****************************************************************************/ -static int stm32_timerisr(int irq, uint32_t *regs) +static int stm32_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -136,7 +136,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr); + (void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); /* Enable SysTick interrupts: * diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index eacdd4ed744..68d6ee6806b 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -37,35 +37,49 @@ endchoice # STM32 L4 Chip Selection # Chip families -config STM32L4_STM32L476XX +config STM32L4_STM32L4X3 + bool + default n + select STM32L4_HAVE_USART1 + select STM32L4_HAVE_USART2 + select STM32L4_HAVE_USART3 + select STM32L4_HAVE_LPTIM1 + select STM32L4_HAVE_LPTIM2 + select STM32L4_HAVE_COMP + select STM32L4_HAVE_SAI1 + select STM32L4_HAVE_SAI2 + +config STM32L4_STM32L4X6 bool default n - select ARCH_HAVE_FPU - select ARCH_HAVE_DPFPU # REVISIT - select ARMV7M_HAVE_ITCM - select ARMV7M_HAVE_DTCM select STM32L4_HAVE_USART1 select STM32L4_HAVE_USART2 select STM32L4_HAVE_USART3 select STM32L4_HAVE_UART4 select STM32L4_HAVE_UART5 + select STM32L4_HAVE_LPTIM1 + select STM32L4_HAVE_LPTIM2 + select STM32L4_HAVE_COMP select STM32L4_HAVE_SAI1 select STM32L4_HAVE_SAI2 +config STM32L4_STM32L476XX + bool + default n + select STM32L4_STM32L4X6 + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU # REVISIT + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + config STM32L4_STM32L486XX bool default n + select STM32L4_STM32L4X6 select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU # REVISIT select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32L4_HAVE_USART1 - select STM32L4_HAVE_USART2 - select STM32L4_HAVE_USART3 - select STM32L4_HAVE_UART4 - select STM32L4_HAVE_UART5 - select STM32L4_HAVE_SAI1 - select STM32L4_HAVE_SAI2 select STM32L4_FLASH_1024KB choice @@ -122,6 +136,18 @@ config STM32L4_HAVE_LTDC bool default n +config STM32L4_HAVE_LPTIM1 + bool + default n + +config STM32L4_HAVE_LPTIM2 + bool + default n + +config STM32L4_HAVE_COMP + bool + default n + config STM32L4_HAVE_SAI1 bool default n @@ -166,8 +192,8 @@ config STM32L4_USART default n config STM32L4_LPTIM - bool - default n + bool + default n # These are the peripheral selections proper @@ -438,8 +464,8 @@ config STM32L4_TIM7 default n config STM32L4_LCD - bool "LCD" - default n + bool "LCD" + default n config STM32L4_SPI2 bool "SPI2" @@ -525,13 +551,14 @@ config STM32L4_DAC2 select STM32L4_DAC config STM32L4_OPAMP - bool "OPAMP" - default n + bool "OPAMP" + default n config STM32L4_LPTIM1 bool "LPTIM1" default n - select STM32L4_LPTIM + select STM32L4_LPTIM + depends on STM32L4_HAVE_LPTIM1 config STM32L4_LPUART1 bool "LPUART1" @@ -540,13 +567,14 @@ config STM32L4_LPUART1 select ARCH_HAVE_LPUART1 config STM32L4_SWPMI - bool "SWPMI" - default n + bool "SWPMI" + default n config STM32L4_LPTIM2 bool "LPTIM2" default n - select STM32L4_LPTIM + select STM32L4_LPTIM + depends on STM32L4_HAVE_LPTIM2 comment "APB2 Peripherals" @@ -597,17 +625,24 @@ config STM32L4_TIM17 bool "TIM17" default n +config STM32L4_COMP + bool "COMP" + default n + depends on STM32L4_HAVE_COMP + config STM32L4_SAI1 bool "SAI1" default n + depends on STM32L4_HAVE_SAI1 config STM32L4_SAI2 bool "SAI2" default n + depends on STM32L4_HAVE_SAI2 config STM32L4_DFSDM - bool "DFSDM" - default n + bool "DFSDM" + default n comment "Other Peripherals" diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index fb2373dc610..359875b63c7 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -160,6 +160,15 @@ endif endif endif +ifeq ($(CONFIG_PM),y) +CHIP_CSRCS += stm32l4_pmlpr.c stm32l4_pmsleep.c stm32l4_pmstandby.c +CHIP_CSRCS += stm32l4_pmstop.c + +ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) +CHIP_CSRCS += stm32l4_pminitialize.c +endif +endif + ifeq ($(CONFIG_STM32L4_PWR),y) CHIP_CSRCS += stm32l4_exti_pwr.c endif @@ -178,6 +187,10 @@ ifeq ($(CONFIG_DEBUG_FEATURES),y) CHIP_CSRCS += stm32l4_dumpgpio.c endif +ifeq ($(CONFIG_STM32L4_COMP),y) +CHIP_CSRCS += stm32l4_comp.c stm32l4_exti_comp.c +endif + ifeq ($(CONFIG_STM32L4_RNG),y) CHIP_CSRCS += stm32l4_rng.c endif @@ -186,6 +199,10 @@ ifeq ($(CONFIG_STM32L4_SAI),y) CHIP_CSRCS += stm32l4_sai.c endif +ifeq ($(CONFIG_STM32L4_LPTIM),y) +CHIP_CSRCS += stm32l4_lptim.c +endif + ifeq ($(CONFIG_PWM),y) CHIP_CSRCS += stm32l4_pwm.c endif diff --git a/arch/arm/src/stm32l4/chip/stm32l4_comp.h b/arch/arm/src/stm32l4/chip/stm32l4_comp.h new file mode 100644 index 00000000000..a09c6826527 --- /dev/null +++ b/arch/arm/src/stm32l4/chip/stm32l4_comp.h @@ -0,0 +1,107 @@ +/**************************************************************************************************** + * arch/arm/src/stm32l4/stm32l4_comp.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_COMP_H +#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_COMP_H + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define STM32L4_COMP_CSR_OFFSET(n) (((n)-1) << 2) +#define STM32L4_COMP1_CSR_OFFSET 0x0000 /* Comparator 1 control and status register */ +#define STM32L4_COMP2_CSR_OFFSET 0x0004 /* Comparator 2 control and status register */ + +/* Register Addresses *******************************************************************************/ + +#define STM32L4_COMP_CSR(n) (STM32L4_COMP_BASE+STM32L4_COMP_CSR_OFFSET(n)) +#define STM32L4_COMP1_CSR (STM32L4_COMP_BASE+STM32L4_COMP1_CSR_OFFSET) +#define STM32L4_COMP2_CSR (STM32L4_COMP_BASE+STM32L4_COMP2_CSR_OFFSET) + +/* Register Bitfield Definitions ********************************************************************/ + +#define COMP_CSR_EN (1 << 0) /* Bit 0: Comparator enable bit */ + /* Bit 1: Reserved */ +#define COMP_CSR_PWRMODE_SHIFT (2) /* Bits 2-3: Power Mode */ +#define COMP_CSR_PWRMODE_MASK (3 << COMP_CSR_PWRMODE_SHIFT) +# define COMP_CSR_PWRMODE_HIGH (0 << COMP_CSR_PWRMODE_SHIFT) /* High speed */ +# define COMP_CSR_PWRMODE_MEDIUM (1 << COMP_CSR_PWRMODE_SHIFT) /* Medium speed */ +# define COMP_CSR_PWRMODE_LOW (3 << COMP_CSR_PWRMODE_SHIFT) /* Ultra low power */ +#define COMP_CSR_INMSEL_SHIFT (4) /* Bits 4-6: Input minus selection bits */ +#define COMP_CSR_INMSEL_MASK (7 << COMP_CSR_INMSEL_SHIFT) +# define COMP_CSR_INMSEL_25PCT (0 << COMP_CSR_INMSEL_SHIFT) /* 1/4 VREFINT */ +# define COMP_CSR_INMSEL_50PCT (1 << COMP_CSR_INMSEL_SHIFT) /* 1/2 VREFINT */ +# define COMP_CSR_INMSEL_75PCT (2 << COMP_CSR_INMSEL_SHIFT) /* 3/4 VREFINT */ +# define COMP_CSR_INMSEL_VREF (3 << COMP_CSR_INMSEL_SHIFT) /* VREFINT */ +# define COMP_CSR_INMSEL_DAC1 (4 << COMP_CSR_INMSEL_SHIFT) /* DAC Channel1 */ +# define COMP_CSR_INMSEL_DAC2 (5 << COMP_CSR_INMSEL_SHIFT) /* DAC Channel2 */ +# define COMP_CSR_INMSEL_PIN1 (6 << COMP_CSR_INMSEL_SHIFT) /* Input minus pin 1: COMP1=PB1; COMP2=PB3 */ +# define COMP_CSR_INMSEL_PIN2 (7 << COMP_CSR_INMSEL_SHIFT) /* Input minus pin 2: COMP1=PC4; COMP2=PB7 */ +#define COMP_CSR_INPSEL_MASK (1 << 7) /* Bit 7: Input plus selection bit */ +# define COMP_CSR_INPSEL_PIN1 (0) /* Input plus pin 1: COMP1=PC5; COMP2=PB4 */ +# define COMP_CSR_INPSEL_PIN2 COMP_CSR_INPSEL_MASK /* Input plus pin 1: COMP1=PB2; COMP2=PB6 */ +#define COMP2_CSR_WINMODE (1 << 9) /* Bit 9: Windows mode selection bit (COMP2 only) */ +# define COMP2_CSR_WINMODE_NOCONN (0) /* Comparator 2 input not connected to Comparator 1 */ +# define COMP2_CSR_WINMODE_CONN COMP2_CSR_WINMODE /* Comparator 2 input connected to Comparator 1 */ +#define COMP_CSR_POLARITY_MASK (1 << 15) /* Bit 15: Polarity selection bit */ +# define COMP_CSR_POLARITY_NORMAL (0) +# define COMP_CSR_POLARITY_INVERT COMP_CSR_POLARITY_MASK +#define COMP_CSR_HYST_SHIFT (16) /* Bits 16-17: Hysteresis selection bits */ +#define COMP_CSR_HYST_MASK (3 << COMP_CSR_HYST_SHIFT) +# define COMP_CSR_HYST_NONE (0 << COMP_CSR_HYST_SHIFT) /* No hysteresis */ +# define COMP_CSR_HYST_LOW (1 << COMP_CSR_HYST_SHIFT) /* Low hysteresis */ +# define COMP_CSR_HYST_MEDIUM (2 << COMP_CSR_HYST_SHIFT) /* Medium hysteresis */ +# define COMP_CSR_HYST_HIGH (3 << COMP_CSR_HYST_SHIFT) /* High hysteresis */ +#define COMP_CSR_BLANK_SHIFT (18) /* Bits 18-20: Blanking source selection bits */ +#define COMP_CSR_BLANK_MASK (7 << COMP_CSR_BLANK_SHIFT) +# define COMP_CSR_BLANK_NONE (0 << COMP_CSR_BLANK_SHIFT) /* No blanking */ +# define COMP1_CSR_BLANK_TIM1OC5 (1 << COMP_CSR_BLANK_SHIFT) /* TIM1 OC5 is blanking source */ +# define COMP1_CSR_BLANK_TIM2OC3 (2 << COMP_CSR_BLANK_SHIFT) /* TIM2 OC3 is blanking source */ +# define COMP1_CSR_BLANK_TIM3OC3 (4 << COMP_CSR_BLANK_SHIFT) /* TIM3 OC3 is blanking source */ +# define COMP2_CSR_BLANK_TIM3OC4 (1 << COMP_CSR_BLANK_SHIFT) /* TIM3 OC4 is blanking source */ +# define COMP2_CSR_BLANK_TIM8OC5 (2 << COMP_CSR_BLANK_SHIFT) /* TIM8 OC5 is blanking source */ +# define COMP2_CSR_BLANK_TIM15OC1 (4 << COMP_CSR_BLANK_SHIFT) /* TIM15 OC1 is blanking source */ + /* Bit 21: Reserved */ +#define COMP_CSR_BRGEN (1 << 22) /* Bit 22: Scaler bridge enable */ +#define COMP_CSR_SCALEN (1 << 23) /* Bit 23: Voltage scaler enable bit */ + /* Bits 24-29: Reserved */ +#define COMP_CSR_VALUE (1 << 30) /* Bit 30: Comparator output status bit */ +#define COMP_CSR_LOCK_MASK (1 << 31) /* Bit 31: CSR register lock bit */ +# define COMP_CSR_LOCK_RW (0) +# define COMP_CSR_LOCK_RO COMP_CSR_LOCK_MASK + +#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_COMP_H */ diff --git a/arch/arm/src/stm32l4/chip/stm32l4_lptim.h b/arch/arm/src/stm32l4/chip/stm32l4_lptim.h new file mode 100644 index 00000000000..1822effec45 --- /dev/null +++ b/arch/arm/src/stm32l4/chip/stm32l4_lptim.h @@ -0,0 +1,117 @@ +/**************************************************************************************************** + * arch/arm/src/stm32l4/stm32l4_lptim.h + * + * Copyright (C) 2016 Motorola Mobility, LLC. All rights reserved. + * Copyright (C) 2009, 2011-2012, 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_LPTIM_H +#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_LPTIM_H + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +/* Basic Timers - TIM6 and TIM7 */ + +#define STM32L4_LPTIM_ISR_OFFSET 0x0000 /* Interrupt and Status Register */ +#define STM32L4_LPTIM_ICR_OFFSET 0x0004 /* Interrupt Clear Register */ +#define STM32L4_LPTIM_IER_OFFSET 0x0008 /* Interrupt Enable Register */ +#define STM32L4_LPTIM_CFGR_OFFSET 0x000c /* Configuration Register */ +#define STM32L4_LPTIM_CR_OFFSET 0x0010 /* Control Register */ +#define STM32L4_LPTIM_CMP_OFFSET 0x0014 /* Compare Register */ +#define STM32L4_LPTIM_ARR_OFFSET 0x0018 /* Autoreload Register */ +#define STM32L4_LPTIM_CNT_OFFSET 0x001c /* Counter Register */ + +/* Register Addresses *******************************************************************************/ + +/* Low-Power Timers - LPTIM1 and LPTIM2 */ + +#define STM32L4_LPTIM1_ISR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ISR_OFFSET) +#define STM32L4_LPTIM1_ICR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ICR_OFFSET) +#define STM32L4_LPTIM1_IER (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_IER_OFFSET) +#define STM32L4_LPTIM1_CFGR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CFGR_OFFSET) +#define STM32L4_LPTIM1_CR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CR_OFFSET) +#define STM32L4_LPTIM1_CMP (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CMP_OFFSET) +#define STM32L4_LPTIM1_ARR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ARR_OFFSET) +#define STM32L4_LPTIM1_CNT (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CNT_OFFSET) + +#define STM32L4_LPTIM2_ISR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ISR_OFFSET) +#define STM32L4_LPTIM2_ICR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ICR_OFFSET) +#define STM32L4_LPTIM2_IER (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_IER_OFFSET) +#define STM32L4_LPTIM2_CFGR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CFGR_OFFSET) +#define STM32L4_LPTIM2_CR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CR_OFFSET) +#define STM32L4_LPTIM2_CMP (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CMP_OFFSET) +#define STM32L4_LPTIM2_ARR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ARR_OFFSET) +#define STM32L4_LPTIM2_CNT (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CNT_OFFSET) + +/* Register Bitfield Definitions ********************************************************************/ + +#define LPTIM_CFGR_CKSEL (1 << 0) /* Bit 0: Clock selector */ +#define LPTIM_CFGR_CKPOL_SHIFT (1) /* Bits 2-1: Clock Polarity */ +#define LPTIM_CFGR_CKPOL_MASK (3 << LPTIM_CFGR_CKPOL_SHIFT) +#define LPTIM_CFGR_CKFLT_SHIFT (3) /* Bits 4-3: Digital filter for external clock */ +#define LPTIM_CFGR_CKFLTN_MASK (3 << LPTIM_CFGR_CKFLT_SHIFT) + /* Bit 5: reserved */ +#define LPTIM_CFGR_TRGFLT_SHIFT (6) /* Bits 7-6: Digital filter for trigger */ +#define LPTIM_CFGR_TRGFLT_MASK (3 << LPTIM_CFGR_TRGFLT_SHIFT) + /* Bit 8: reserved */ +#define LPTIM_CFGR_PRESC_SHIFT (9) /* Bits 11-9: clock pre-scaler */ +#define LPTIM_CFGR_PRESC_MASK (7 << LPTIM_CFGR_PRESC_SHIFT) +# define LPTIM_CFGR_PRESCd1 (0 << LPTIM_CFGR_PRESC_SHIFT) /* 000: divide by 1 */ +# define LPTIM_CFGR_PRESCd2 (1 << LPTIM_CFGR_PRESC_SHIFT) /* 001: divide by 2 */ +# define LPTIM_CFGR_PRESCd4 (2 << LPTIM_CFGR_PRESC_SHIFT) /* 010: divide by 4 */ +# define LPTIM_CFGR_PRESCd8 (3 << LPTIM_CFGR_PRESC_SHIFT) /* 011: divide by 8 */ +# define LPTIM_CFGR_PRESCd16 (4 << LPTIM_CFGR_PRESC_SHIFT) /* 100: divide by 16 */ +# define LPTIM_CFGR_PRESCd32 (5 << LPTIM_CFGR_PRESC_SHIFT) /* 101: divide by 32 */ +# define LPTIM_CFGR_PRESCd64 (6 << LPTIM_CFGR_PRESC_SHIFT) /* 110: divide by 64 */ +# define LPTIM_CFGR_PRESCd128 (7 << LPTIM_CFGR_PRESC_SHIFT) /* 111: divide by 128 */ + /* Bit 12: reserved */ +#define LPTIM_CFGR_TRIGSEL_SHIFT (13) /* Bits 15-13: Trigger selector */ +#define LPTIM_CFGR_TRIGSEL_MASK (7 << LPTIM_CFGR_TRIGSEL_SHIFT) + /* Bit 16: reserved */ +#define LPTIM_CFGR_TRIGEN_SHIFT (17) /* Bits 18-17: Trigger enable and polarity */ +#define LPTIM_CFGR_TRIGEN_MASK (3 << LPTIM_CFGR_TRIGEN_SHIFT) +#define LPTIM_CFGR_TIMOUT (1 << 19) /* Bit 19: Timeout enable */ +#define LPTIM_CFGR_WAVE (1 << 20) /* Bit 20: Waveform shape */ +#define LPTIM_CFGR_WAVPOL (1 << 21) /* Bit 21: Waveform polarity */ +#define LPTIM_CFGR_PRELOAD (1 << 22) /* Bit 22: Update mode enable */ +#define LPTIM_CFGR_COUNTMODE (1 << 23) /* Bit 23: Count mode enable */ +#define LPTIM_CFGR_ENC (1 << 24) /* Bit 24: Encoder mode enable (LPTIM1 only) */ + +#define LPTIM_CR_ENABLE (1 << 0) /* Bit 0: Enable */ +#define LPTIM_CR_SNGSTRT (1 << 1) /* Bit 1: Single Mode */ +#define LPTIM_CR_CNTSTRT (1 << 2) /* Bit 2: Continuous Mode */ + +#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_LPTIM_H */ diff --git a/arch/arm/src/stm32l4/chip/stm32l4_pinmap.h b/arch/arm/src/stm32l4/chip/stm32l4_pinmap.h index 906e53dccb5..0b2b537f1e4 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4_pinmap.h +++ b/arch/arm/src/stm32l4/chip/stm32l4_pinmap.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32_PINMAP_H -#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_PINMAP_H +#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_PINMAP_H /************************************************************************************ * Included Files @@ -49,5 +49,5 @@ # error "Unsupported STM32 L4 pin map" #endif -#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_PINMAP_H */ diff --git a/arch/arm/src/stm32l4/chip/stm32l4_pwr.h b/arch/arm/src/stm32l4/chip/stm32l4_pwr.h index 2e771551f8e..2b81413a793 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4_pwr.h +++ b/arch/arm/src/stm32l4/chip/stm32l4_pwr.h @@ -105,8 +105,8 @@ #define PWR_CR1_LPMS_SHIFT 0 #define PWR_CR1_LPMS_MASK (7 << PWR_CR1_LPMS_SHIFT) /* Bits 0-2: Low-power mode selection */ -# define PWR_CR1_LPMS_STOP0 (0 << PWR_CR1_LPMS_SHIFT) /* 000: Stop 0 mode */ -# define PWR_CR1_LPMS_STOP1 (1 << PWR_CR1_LPMS_SHIFT) /* 001: Stpp 1 mode */ +# define PWR_CR1_LPMS_STOP1MR (0 << PWR_CR1_LPMS_SHIFT) /* Stop 1 mode with main regulator (MR) */ +# define PWR_CR1_LPMS_STOP1LPR (1 << PWR_CR1_LPMS_SHIFT) /* Stop 1 mode with low-power regulator (LPR) */ # define PWR_CR1_LPMS_STOP2 (2 << PWR_CR1_LPMS_SHIFT) /* 010: Stop 2 mode*/ # define PWR_CR1_LPMS_STANDBY (3 << PWR_CR1_LPMS_SHIFT) /* 011: Standby mode */ # define PWR_CR1_LPMS_SHUTDOWN (4 << PWR_CR1_LPMS_SHIFT) /* 1xx: Shutdown node */ @@ -120,7 +120,7 @@ /* Power control register 2 */ #define PWR_CR2_PVDE (1 << 0) /* Bit 0: Power voltage detector enable */ -#define PWR_CR2_PLS_SHIFT 1 +#define PWR_CR2_PLS_SHIFT 1 #define PWR_CR2_PLS_MASK (7 << PWR_CR2_PLS_SHIFT) /* Bits 1-3: Power voltage detector level selection */ # define PWR_CR2_PLS_2000mv (0 << PWR_CR2_PLS_SHIFT) /* 000: VPVD0 around 2.0V */ # define PWR_CR2_PLS_2200mv (1 << PWR_CR2_PLS_SHIFT) /* 001: VPVD1 around 2.2V */ diff --git a/arch/arm/src/stm32l4/chip/stm32l4_rng.h b/arch/arm/src/stm32l4/chip/stm32l4_rng.h index 434b77c1c26..7812110b620 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4_rng.h +++ b/arch/arm/src/stm32l4/chip/stm32l4_rng.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32L4_RNG_H -#define __ARCH_ARM_STC_STM32_CHIP_STM32L4_RNG_H +#ifndef __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_RNG_H +#define __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_RNG_H /************************************************************************************ * Included Files @@ -74,4 +74,4 @@ #define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */ #define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */ -#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32L4_RNG_H */ +#endif /* __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_RNG_H */ diff --git a/arch/arm/src/stm32l4/chip/stm32l4_sai.h b/arch/arm/src/stm32l4/chip/stm32l4_sai.h index a7ab977a0fc..f411fb72baf 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4_sai.h +++ b/arch/arm/src/stm32l4/chip/stm32l4_sai.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32L4_SAI_H -#define __ARCH_ARM_STC_STM32_CHIP_STM32L4_SAI_H +#ifndef __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_SAI_H +#define __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_SAI_H /************************************************************************************ * Included Files @@ -256,4 +256,4 @@ /* SAI Data Register (32-bit data) */ -#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32L4_SAI_H */ +#endif /* __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_SAI_H */ diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_firewall.h b/arch/arm/src/stm32l4/chip/stm32l4x6xx_firewall.h index e0471567fec..e1531de5d03 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_firewall.h +++ b/arch/arm/src/stm32l4/chip/stm32l4x6xx_firewall.h @@ -101,4 +101,3 @@ #define FIREWALL_CR_VDE (1 << 2) /* Bit 2: Volatile data execution */ #endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_FIREWALL_H */ - diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h b/arch/arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h index 2915c0c4397..8be6eca5a54 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h +++ b/arch/arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h @@ -845,4 +845,3 @@ #define GPIO_LPUART1_RTS_DE_2 (GPIO_ALT|GPIO_AF8 |GPIO_PORTG|GPIO_PIN6) #endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_PINMAP_H */ - diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h b/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h index c56e59c8116..c45c199e9b8 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h +++ b/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h @@ -760,5 +760,5 @@ #define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */ #define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */ -#endif /* CONFIG_STM32L4_STM32F427 || CONFIG_STM32L4_STM32F429 */ +#endif /* CONFIG_STM32L4_STM32L476XX || CONFIG_STM32L4_STM32L486XX */ #endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32F42XXX_RCC_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_can.c b/arch/arm/src/stm32l4/stm32l4_can.c index 18b49a86e74..ed14ca43609 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.c +++ b/arch/arm/src/stm32l4/stm32l4_can.c @@ -163,9 +163,9 @@ static bool stm32l4can_txempty(FAR struct can_dev_s *dev); /* CAN interrupt handling */ static int stm32l4can_rxinterrupt(int irq, FAR void *context, int rxmb); -static int stm32l4can_rx0interrupt(int irq, FAR void *context); -static int stm32l4can_rx1interrupt(int irq, FAR void *context); -static int stm32l4can_txinterrupt(int irq, FAR void *context); +static int stm32l4can_rx0interrupt(int irq, FAR void *context, FAR void *arg); +static int stm32l4can_rx1interrupt(int irq, FAR void *context, FAR void *arg); +static int stm32l4can_txinterrupt(int irq, FAR void *context, FAR void *arg); /* Initialization */ @@ -627,7 +627,7 @@ static int stm32l4can_setup(FAR struct can_dev_s *dev) * The others are not used. */ - ret = irq_attach(priv->canrx[0], stm32l4can_rx0interrupt); + ret = irq_attach(priv->canrx[0], stm32l4can_rx0interrupt, NULL); if (ret < 0) { canerr("ERROR: Failed to attach CAN%d RX0 IRQ (%d)", @@ -635,7 +635,7 @@ static int stm32l4can_setup(FAR struct can_dev_s *dev) return ret; } - ret = irq_attach(priv->canrx[1], stm32l4can_rx1interrupt); + ret = irq_attach(priv->canrx[1], stm32l4can_rx1interrupt, NULL); if (ret < 0) { canerr("ERROR: Failed to attach CAN%d RX1 IRQ (%d)", @@ -643,7 +643,7 @@ static int stm32l4can_setup(FAR struct can_dev_s *dev) return ret; } - ret = irq_attach(priv->cantx, stm32l4can_txinterrupt); + ret = irq_attach(priv->cantx, stm32l4can_txinterrupt, NULL); if (ret < 0) { canerr("ERROR: Failed to attach CAN%d TX IRQ (%d)", @@ -1462,7 +1462,7 @@ errout: * ****************************************************************************/ -static int stm32l4can_rx0interrupt(int irq, FAR void *context) +static int stm32l4can_rx0interrupt(int irq, FAR void *context, FAR void *arg) { return stm32l4can_rxinterrupt(irq, context, 0); } @@ -1482,7 +1482,7 @@ static int stm32l4can_rx0interrupt(int irq, FAR void *context) * ****************************************************************************/ -static int stm32l4can_rx1interrupt(int irq, FAR void *context) +static int stm32l4can_rx1interrupt(int irq, FAR void *context, FAR void *arg) { return stm32l4can_rxinterrupt(irq, context, 1); } @@ -1502,7 +1502,7 @@ static int stm32l4can_rx1interrupt(int irq, FAR void *context) * ****************************************************************************/ -static int stm32l4can_txinterrupt(int irq, FAR void *context) +static int stm32l4can_txinterrupt(int irq, FAR void *context, FAR void *arg) { FAR struct can_dev_s *dev = NULL; FAR struct stm32l4_can_s *priv; diff --git a/arch/arm/src/stm32l4/stm32l4_comp.c b/arch/arm/src/stm32l4/stm32l4_comp.c new file mode 100644 index 00000000000..518e648639c --- /dev/null +++ b/arch/arm/src/stm32l4/stm32l4_comp.c @@ -0,0 +1,316 @@ +/************************************************************************************ + * arch/arm/src/stm32l4/stm32l4_comp.c + * + * Copyright (c) 2017 Gregory Nutt. All rights reserved. + * + * Based on COMP driver from the Motorola MDK: + * + * Copyright (c) 2016 Motorola Mobility, LLC. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include "chip.h" +#include "stm32l4_comp.h" +#include "stm32l4_gpio.h" +#include "up_arch.h" + +#include + +#if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X6)) +# error "Unrecognized STM32 chip" +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: modify_csr + ************************************************************************************/ + +static inline void modify_csr(int cmp, uint32_t clearbits, uint32_t setbits) +{ + modifyreg32(cmp == STM32L4_COMP1 ? STM32L4_COMP1_CSR : STM32L4_COMP2_CSR, + clearbits, setbits); +} + +/************************************************************************************ + * Name: get_csr + ************************************************************************************/ + +static inline uint32_t get_csr(int cmp) +{ + return getreg32(cmp == STM32L4_COMP1 ? STM32L4_COMP1_CSR : STM32L4_COMP2_CSR); +} + +/************************************************************************************* + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32l4_compconfig + * + * Description: + * Configure comparator and I/Os used as comparators inputs + * + * Parameters: + * cmp - comparator + * cfg - configuration + * + * Returns: + * 0 on success, a negated errno value on failure + * + ************************************************************************************/ + +int stm32l4_compconfig(int cmp, const struct stm32l4_comp_config_s *cfg) +{ + uint32_t regval = 0; + uint32_t mask = 0; + uint32_t clearbits; + uint32_t setbits; + + /* Input plus */ + + mask |= COMP_CSR_INPSEL_MASK; + switch (cfg->inp) + { + case STM32L4_COMP_INP_PIN_1: + stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_1 : GPIO_COMP2_INP_1); + regval |= COMP_CSR_INPSEL_PIN1; + break; + + case STM32L4_COMP_INP_PIN_2: + stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_2 : GPIO_COMP2_INP_2); + regval |= COMP_CSR_INPSEL_PIN2; + break; + +#if defined(CONFIG_STM32L4_STM32L4X3) + case STM32L4_COMP_INP_PIN_3: + stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_3 : GPIO_COMP2_INP_3); + regval |= COMP_CSR_INPSEL_PIN3; + break; +#endif + + default: + return -EINVAL; + } + + /* Input minus */ + + mask |= COMP_CSR_INMSEL_MASK; + switch (cfg->inm) + { + case STM32L4_COMP_INM_1_4_VREF: + regval |= COMP_CSR_INMSEL_25PCT; + mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); + regval |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); + break; + + case STM32L4_COMP_INM_1_2_VREF: + regval |= COMP_CSR_INMSEL_50PCT; + mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); + regval |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); + break; + + case STM32L4_COMP_INM_3_4_VREF: + regval |= COMP_CSR_INMSEL_75PCT; + mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); + regval |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); + break; + + case STM32L4_COMP_INM_VREF: + regval |= COMP_CSR_INMSEL_VREF; + mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); + regval |= COMP_CSR_SCALEN; + break; + + case STM32L4_COMP_INM_DAC_1: + regval |= COMP_CSR_INMSEL_DAC1; + break; + + case STM32L4_COMP_INM_DAC_2: + regval |= COMP_CSR_INMSEL_DAC2; + break; + + case STM32L4_COMP_INM_PIN_1: + stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_1 : GPIO_COMP2_INM_1); + regval |= COMP_CSR_INMSEL_PIN1; + break; + + case STM32L4_COMP_INM_PIN_2: + stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_2 : GPIO_COMP2_INM_2); +#if defined(CONFIG_STM32L4_STM32L4X6) + regval |= COMP_CSR_INMSEL_PIN2; +#else + regval |= COMP_CSR_INMSEL_INMESEL; + mask |= COMP_CSR_INMESEL_MASK; + regval |= COMP_CSR_INMSEL_PIN2; +#endif + break; + +#if defined(CONFIG_STM32L4_STM32L4X3) + case STM32L4_COMP_INM_PIN_3: + stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_3 : GPIO_COMP2_INM_3); + regval |= COMP_CSR_INMSEL_INMESEL; + mask |= COMP_CSR_INMESEL_MASK; + regval |= COMP_CSR_INMSEL_PIN3; + break; + + case STM32L4_COMP_INM_PIN_4: + stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_4 : GPIO_COMP2_INM_4); + regval |= COMP_CSR_INMSEL_INMESEL; + mask |= COMP_CSR_INMESEL_MASK; + regval |= COMP_CSR_INMSEL_PIN4; + break; + + case STM32L4_COMP_INM_PIN_5: + stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_5 : GPIO_COMP2_INM_5); + regval |= COMP_CSR_INMSEL_INMESEL; + mask |= COMP_CSR_INMESEL_MASK; + regval |= COMP_CSR_INMSEL_PIN5; + break; + +#endif + default: + return -EINVAL; + } + + /* Hysteresis */ + + mask |= COMP_CSR_HYST_MASK; + switch (cfg->hyst) + { + case STM32L4_COMP_HYST_NONE: + regval |= COMP_CSR_HYST_NONE; + break; + + case STM32L4_COMP_HYST_LOW: + regval |= COMP_CSR_HYST_LOW; + break; + + case STM32L4_COMP_HYST_MEDIUM: + regval |= COMP_CSR_HYST_MEDIUM; + break; + + case STM32L4_COMP_HYST_HIGH: + regval |= COMP_CSR_HYST_HIGH; + break; + + default: + return -EINVAL; + } + + /* Power/speed Mode */ + + mask |= COMP_CSR_PWRMODE_MASK; + switch(cfg->speed) + { + case STM32L4_COMP_SPEED_HIGH: + regval |= COMP_CSR_PWRMODE_HIGH; + break; + + case STM32L4_COMP_SPEED_MEDIUM: + regval |= COMP_CSR_PWRMODE_MEDIUM; + break; + + case STM32L4_COMP_SPEED_LOW: + regval |= COMP_CSR_PWRMODE_LOW; + break; + + default: + return -EINVAL; + } + + /* Polarity */ + + mask |= COMP_CSR_POLARITY_MASK; + if (cfg->inverted) + { + regval |= COMP_CSR_POLARITY_INVERT; + } + + /* Disable blanking */ + + mask |= COMP_CSR_BLANK_MASK; + regval |= COMP_CSR_BLANK_NONE; + + clearbits = regval ^ mask; + setbits = regval; + + modify_csr(cmp, clearbits, setbits); + return 0; +} + +/************************************************************************************ + * Name: stm32l4_compenable + * + * Description: + * Enable/disable comparator + * + * Parameters: + * cmp - comparator + * cfg - enable/disable flag + * + * Returns: + * 0 on success, a negated errno value on failure + * + ************************************************************************************/ + +int stm32l4_compenable(int cmp, bool en) +{ + uint32_t clearbits = en ? 0 : COMP_CSR_EN; + uint32_t setbits = en ? COMP_CSR_EN : 0; + + modify_csr(cmp, clearbits, setbits); + return 0; +} + +/************************************************************************************ + * Name: stm32l4_compread + * + * Description: + * Read comparator output + * + * Parameters: + * - cmp: comparator + * + * Returns: + * true for high, false for low + * + ************************************************************************************/ + +bool stm32l4_compread(int cmp) +{ + return !!(get_csr(cmp) & COMP_CSR_VALUE); +} diff --git a/arch/arm/src/stm32l4/stm32l4_comp.h b/arch/arm/src/stm32l4/stm32l4_comp.h new file mode 100644 index 00000000000..eecede715b2 --- /dev/null +++ b/arch/arm/src/stm32l4/stm32l4_comp.h @@ -0,0 +1,221 @@ +/************************************************************************************ + * arch/arm/src/stm32/stm32l4_comp.h + * + * Copyright (c) 2016 Motorola Mobility, LLC. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_COMP_H +#define __ARCH_ARM_SRC_STM32L4_STM32L4_COMP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include "chip/stm32l4_comp.h" + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#if defined(CONFIG_STM32L4_STM32L4X3) +/* Comparators */ + +enum stm32l4_comp_e +{ + STM32L4_COMP1, + STM32L4_COMP2, + STM32L4_COMP_NUM /* Number of comparators */ +}; + +/* Plus input */ + +enum stm32l4_comp_inp_e +{ + STM32L4_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ + STM32L4_COMP_INP_PIN_2, /* COMP1: PB2, COMP2: PB6 */ + STM32L4_COMP_INP_PIN_3 /* COMP1: PA1, COMP2: PA3 */ +}; + +/* Minus input */ + +enum stm32l4_comp_inm_e +{ + STM32L4_COMP_INM_1_4_VREF, + STM32L4_COMP_INM_1_2_VREF, + STM32L4_COMP_INM_3_4_VREF, + STM32L4_COMP_INM_VREF, + STM32L4_COMP_INM_DAC_1, + STM32L4_COMP_INM_DAC_2, + STM32L4_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */ + STM32L4_COMP_INM_PIN_2, /* COMP1: PC4, COMP2: PB7 */ + STM32L4_COMP_INM_PIN_3, /* COMP1: PA0, COMP2: PA2 */ + STM32L4_COMP_INM_PIN_4, /* COMP1: PA4, COMP2: PA4 */ + STM32L4_COMP_INM_PIN_5 /* COMP1: PA5, COMP2: PA5 */ +}; + +#elif defined(CONFIG_STM32L4_STM32L4X6) +/* Comparators */ + +enum stm32l4_comp_e +{ + STM32L4_COMP1, + STM32L4_COMP2, + STM32L4_COMP_NUM /* Number of comparators */ +}; + +/* Plus input */ + +enum stm32l4_comp_inp_e +{ + STM32L4_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ + STM32L4_COMP_INP_PIN_2 /* COMP1: PB2, COMP2: PB6 */ +}; + +/* Minus input */ + +enum stm32l4_comp_inm_e +{ + STM32L4_COMP_INM_1_4_VREF, + STM32L4_COMP_INM_1_2_VREF, + STM32L4_COMP_INM_3_4_VREF, + STM32L4_COMP_INM_VREF, + STM32L4_COMP_INM_DAC_1, + STM32L4_COMP_INM_DAC_2, + STM32L4_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */ + STM32L4_COMP_INM_PIN_2 /* COMP1: PC4, COMP2: PB7 */ +}; +#endif + +/* Hysteresis */ + +enum stm32l4_comp_hyst_e +{ + STM32L4_COMP_HYST_NONE, + STM32L4_COMP_HYST_LOW, + STM32L4_COMP_HYST_MEDIUM, + STM32L4_COMP_HYST_HIGH +}; + +/* Power/Speed Modes */ + +enum stm32l4_comp_speed_e +{ + STM32L4_COMP_SPEED_HIGH, + STM32L4_COMP_SPEED_MEDIUM, + STM32L4_COMP_SPEED_LOW +}; + +/* Comparator configuration ***********************************************************/ + +struct stm32l4_comp_config_s +{ + uint8_t inp; /* Plus input pin (see enum stm32l4_comp_inp_e) */ + uint8_t inm; /* Minus input pin (see enum stm32l4_comp_inm_e) */ + uint8_t hyst; /* Hysteresis (see enum stm32l4_comp_hyst_e) */ + uint8_t speed; /* Speed (see stm32l4_comp_speed_e) */ + bool inverted; /* Invert output? */ +}; + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Name: stm32l4_compconfig + * + * Description: + * Configure comparator and I/Os used as comparators inputs + * + * Parameters: + * cmp - comparator + * cfg - configuration + * + * Returns: + * 0 on success, a negated errno value on failure + * + ************************************************************************************/ + +int stm32l4_compconfig(int cmp, const struct stm32l4_comp_config_s *cfg); + +/************************************************************************************ + * Name: stm32l4_compenable + * + * Description: + * Enable/disable comparator + * + * Parameters: + * cmp - comparator + * cfg - enable/disable flag + * + * Returns: + * 0 on success, a negated errno value on failure + * + ************************************************************************************/ + +int stm32l4_compenable(int cmp, bool en); + +/************************************************************************************ + * Name: stm32l4_compread + * + * Description: + * Read comparator output + * + * Parameters: + * - cmp: comparator + * + * Returns: + * true for high, false for low + * + ************************************************************************************/ + +bool stm32l4_compread(int cmp); + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_COMP_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_exti.h b/arch/arm/src/stm32l4/stm32l4_exti.h index 87dbd78c255..d090ea7d483 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti.h +++ b/arch/arm/src/stm32l4/stm32l4_exti.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/stm32l4/stm32l4_exti.h * - * Copyright (C) 2009, 2012, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2012, 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -77,6 +77,7 @@ extern "C" * - rising/falling edge: enables * - event: generate event when set * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback * * Returns: * The previous value of the interrupt handler function pointer. This value may, @@ -86,9 +87,9 @@ extern "C" ************************************************************************************/ xcpt_t stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func); + bool event, xcpt_t func, void *arg); -/************************************************************************************ +/**************************************************************************** * Name: stm32l4_exti_alarm * * Description: @@ -98,16 +99,43 @@ xcpt_t stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, * - rising/falling edge: enables interrupt on rising/falling edges * - event: generate event when set * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback * * Returns: - * The previous value of the interrupt handler function pointer. This value may, - * for example, be used to restore the previous handler when multiple handlers are - * used. + * The previous value of the interrupt handler function pointer. This + * value may, for example, be used to restore the previous handler when + * multiple handlers are used. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -xcpt_t stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func); +xcpt_t stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event, + xcpt_t func, void *arg); +#endif + +/**************************************************************************** + * Name: stm32l4_exti_comp + * + * Description: + * Sets/clears comparator based events and interrupt triggers. + * + * Parameters: + * - cmp: comparator + * - rising/falling edge: enables interrupt on rising/falling edget + * - event: generate event when set + * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + * Returns: + * The previous value of the interrupt handler function pointer. This + * value may, for example, be used to restore the previous handler when + * multiple handlers are used. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32L4_COMP +xcpt_t stm32l4_exti_comp(int cmp, bool risingedge, bool fallingedge, + bool event, xcpt_t func, void *arg); #endif #undef EXTERN diff --git a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c index c71d9752837..af0dac1bd93 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c @@ -60,7 +60,8 @@ /* Interrupt handlers attached to the ALARM EXTI */ -static xcpt_t stm32l4_exti_callback; +static xcpt_t g_alarm_callback; +static void *g_callback_arg; /**************************************************************************** * Private Functions @@ -74,15 +75,15 @@ static xcpt_t stm32l4_exti_callback; * ****************************************************************************/ -static int stm32l4_exti_alarm_isr(int irq, void *context) +static int stm32l4_exti_alarm_isr(int irq, void *context, FAR void *arg) { int ret = OK; /* Dispatch the interrupt to the handler */ - if (stm32l4_exti_callback) + if (g_alarm_callback != NULL) { - ret = stm32l4_exti_callback(irq, context); + ret = g_alarm_callback(irq, context, g_callback_arg); } /* Clear the pending EXTI interrupt */ @@ -115,20 +116,21 @@ static int stm32l4_exti_alarm_isr(int irq, void *context) ****************************************************************************/ xcpt_t stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event, - xcpt_t func) + xcpt_t func, void *arg) { xcpt_t oldhandler; /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ - oldhandler = stm32l4_exti_callback; - stm32l4_exti_callback = func; + oldhandler = g_alarm_callback; + g_alarm_callback = func; + g_callback_arg = arg; /* Install external interrupt handlers (if not already attached) */ if (func) { - irq_attach(STM32L4_IRQ_RTCALRM, stm32l4_exti_alarm_isr); + irq_attach(STM32L4_IRQ_RTCALRM, stm32l4_exti_alarm_isr, NULL); up_enable_irq(STM32L4_IRQ_RTCALRM); } else diff --git a/arch/arm/src/stm32l4/stm32l4_exti_comp.c b/arch/arm/src/stm32l4/stm32l4_exti_comp.c new file mode 100644 index 00000000000..7c508a11668 --- /dev/null +++ b/arch/arm/src/stm32l4/stm32l4_exti_comp.c @@ -0,0 +1,186 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32l4_exti_comp.c + * + * Copyright (c) 2017 Gregory Nutt. All rights reserved + * Copyright (c) 2016 Motorola Mobility, LLC. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "up_arch.h" +#include "stm32l4_comp.h" +#include "stm32l4_exti.h" +#include "chip/stm32l4_exti.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct comp_callback_s +{ + xcpt_t callback; + void *arg; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Interrupt handlers attached to the COMP EXTI lines */ + +static struct comp_callback_s g_comp_handlers[STM32L4_COMP_NUM]; + +/* Comparator EXTI lines */ + +static const uint32_t g_comp_lines[STM32L4_COMP_NUM] = +{ +#if defined(CONFIG_STM32L4_STM32L4X3) || defined (CONFIG_STM32L4_STM32L4X6) + EXTI1_COMP1, + EXTI1_COMP2 +#else +# error "Unrecognized STM32L4 chip" +#endif +}; + + /**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int stm32l4_exti_comp_isr(int irq, void *context) +{ + uint32_t pr; + uint32_t ln; + int ret = 0; + int i; + + /* Examine the state of each comparator line and dispatch interrupts */ + + pr = getreg32(STM32L4_EXTI1_PR); + for (i = 0; i < STM32L4_COMP_NUM; i++) + { + ln = g_comp_lines[i]; + if ((pr & ln) != 0) + { + /* Clear the pending interrupt */ + + putreg32(ln, STM32L4_EXTI1_PR); + if (g_comp_handlers[i].callback != NULL) + { + xcpt_t callback = g_comp_handlers[i].callback; + vid *arg = g_comp_handlers[i].arg; + ret = callback(irq, context, arg); + } + } + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32l4_exti_comp + * + * Description: + * Sets/clears comparator based events and interrupt triggers. + * + * Parameters: + * - cmp: comparator + * - rising/falling edge: enables interrupt on rising/falling edget + * - event: generate event when set + * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + * Returns: + * The previous value of the interrupt handler function pointer. This + * value may, for example, be used to restore the previous handler when + * multiple handlers are used. + * + ****************************************************************************/ + +xcpt_t stm32l4_exti_comp(int cmp, bool risingedge, bool fallingedge, + bool event, xcpt_t func, void *arg) +{ + xcpt_t oldhandler; + irqstate_t flags; + uint32_t ln = g_comp_lines[cmp]; + + /* Perform the following within a critical section so that the handler gets + * installed correctly before the next interrupt is received. + */ + + flags = enter_critical_section(); + + /* Install external interrupt handlers */ + + if (func != NULL) + { + irq_attach(STM32L4_IRQ_COMP, stm32l4_exti_comp_isr); + up_enable_irq(STM32L4_IRQ_COMP); + } + else + { + up_disable_irq(STM32L4_IRQ_COMP); + } + + /* Configure rising/falling edges */ + + modifyreg32(STM32L4_EXTI1_RTSR, risingedge ? 0 : ln, risingedge ? ln : 0); + modifyreg32(STM32L4_EXTI1_FTSR, fallingedge ? 0 : ln, fallingedge ? ln : 0); + + /* Enable Events and Interrupts */ + + modifyreg32(STM32L4_EXTI1_EMR, event ? 0 : ln, event ? ln : 0); + modifyreg32(STM32L4_EXTI1_IMR, func ? 0 : ln, func ? ln : 0); + + /* Get the previous IRQ handler and save the new IRQ handler. */ + + oldhandler = g_comp_handlers[cmp].callback; + g_comp_handlers[cmp].callback = func; + g_comp_handlers[cmp].arg = arg; + + /* Leave the critical section */ + + leave_critical_section(flags); + + /* Return the old IRQ handler */ + + return oldhandler; +} diff --git a/arch/arm/src/stm32l4/stm32l4_exti_gpio.c b/arch/arm/src/stm32l4/stm32l4_exti_gpio.c index ede05e83221..e0eeabe529f 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_gpio.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_gpio.c @@ -55,13 +55,23 @@ #include "stm32l4_gpio.h" #include "stm32l4_exti.h" +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct gpio_callback_s +{ + xcpt_t callback; + void *arg; +}; + /**************************************************************************** * Private Data ****************************************************************************/ /* Interrupt handlers attached to each EXTI */ -static xcpt_t stm32l4_exti_callbacks[16]; +static struct gpio_callback_s g_gpio_handlers[16]; /**************************************************************************** * Private Functions @@ -71,7 +81,7 @@ static xcpt_t stm32l4_exti_callbacks[16]; * Interrupt Service Routines - Dispatchers ****************************************************************************/ -static int stm32l4_exti0_isr(int irq, void *context) +static int stm32l4_exti0_isr(int irq, void *context, FAR void *arg) { int ret = OK; @@ -81,15 +91,18 @@ static int stm32l4_exti0_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32l4_exti_callbacks[0]) + if (g_gpio_handlers[0].callback != NULL) { - ret = stm32l4_exti_callbacks[0](irq, context); + xcpt_t callback = g_gpio_handlers[0].callback; + void *cbarg = g_gpio_handlers[0].arg; + + ret = callback(irq, context, cbarg); } return ret; } -static int stm32l4_exti1_isr(int irq, void *context) +static int stm32l4_exti1_isr(int irq, void *context, FAR void *arg) { int ret = OK; @@ -99,15 +112,18 @@ static int stm32l4_exti1_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32l4_exti_callbacks[1]) + if (g_gpio_handlers[1].callback != NULL) { - ret = stm32l4_exti_callbacks[1](irq, context); + xcpt_t callback = g_gpio_handlers[1].callback; + void *cbarg = g_gpio_handlers[1].arg; + + ret = callback(irq, context, cbarg); } return ret; } -static int stm32l4_exti2_isr(int irq, void *context) +static int stm32l4_exti2_isr(int irq, void *context, FAR void *arg) { int ret = OK; @@ -117,15 +133,18 @@ static int stm32l4_exti2_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32l4_exti_callbacks[2]) + if (g_gpio_handlers[2].callback != NULL) { - ret = stm32l4_exti_callbacks[2](irq, context); + xcpt_t callback = g_gpio_handlers[2].callback; + void *cbarg = g_gpio_handlers[2].arg; + + ret = callback(irq, context, cbarg); } return ret; } -static int stm32l4_exti3_isr(int irq, void *context) +static int stm32l4_exti3_isr(int irq, void *context, FAR void *arg) { int ret = OK; @@ -135,15 +154,18 @@ static int stm32l4_exti3_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32l4_exti_callbacks[3]) + if (g_gpio_handlers[3].callback != NULL) { - ret = stm32l4_exti_callbacks[3](irq, context); + xcpt_t callback = g_gpio_handlers[3].callback; + void *cbarg = g_gpio_handlers[3].arg; + + ret = callback(irq, context, cbarg); } return ret; } -static int stm32l4_exti4_isr(int irq, void *context) +static int stm32l4_exti4_isr(int irq, void *context, FAR void *arg) { int ret = OK; @@ -153,15 +175,18 @@ static int stm32l4_exti4_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32l4_exti_callbacks[4]) + if (g_gpio_handlers[4].callback != NULL) { - ret = stm32l4_exti_callbacks[4](irq, context); + xcpt_t callback = g_gpio_handlers[4].callback; + void *cbarg = g_gpio_handlers[4].arg; + + ret = callback(irq, context, cbarg); } return ret; } -static int stm32l4_exti_multiisr(int irq, void *context, int first, int last) +static int stm32l4_exti_multiisr(int irq, void *context, void *arg, int first, int last) { uint32_t pr; int pin; @@ -186,10 +211,14 @@ static int stm32l4_exti_multiisr(int irq, void *context, int first, int last) /* And dispatch the interrupt to the handler */ - if (stm32l4_exti_callbacks[pin]) + if (g_gpio_handlers[pin].callback != NULL) { - int tmp = stm32l4_exti_callbacks[pin](irq, context); - if (tmp != OK) + xcpt_t callback = g_gpio_handlers[pin].callback; + void *cbarg = g_gpio_handlers[pin].arg; + int tmp; + + tmp = callback(irq, context, cbarg); + if (tmp < 0) { ret = tmp; } @@ -200,14 +229,14 @@ static int stm32l4_exti_multiisr(int irq, void *context, int first, int last) return ret; } -static int stm32l4_exti95_isr(int irq, void *context) +static int stm32l4_exti95_isr(int irq, void *context, void *arg) { - return stm32l4_exti_multiisr(irq, context, 5, 9); + return stm32l4_exti_multiisr(irq, context, arg, 5, 9); } -static int stm32l4_exti1510_isr(int irq, void *context) +static int stm32l4_exti1510_isr(int irq, void *context, FAR void *arg) { - return stm32l4_exti_multiisr(irq, context, 10, 15); + return stm32l4_exti_multiisr(irq, context, arg, 10, 15); } /**************************************************************************** @@ -226,6 +255,7 @@ static int stm32l4_exti1510_isr(int irq, void *context) * - fallingedge: Enables interrupt on falling edges * - event: Generate event when set * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback * * Returns: * The previous value of the interrupt handler function pointer. This @@ -235,15 +265,15 @@ static int stm32l4_exti1510_isr(int irq, void *context) ****************************************************************************/ xcpt_t stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func) + bool event, xcpt_t func, void *arg) { + struct gpio_callback_s *shared_cbs; uint32_t pin = pinset & GPIO_PIN_MASK; uint32_t exti = STM32L4_EXTI1_BIT(pin); int irq; xcpt_t handler; xcpt_t oldhandler = NULL; int nshared; - xcpt_t *shared_cbs; int i; /* Select the interrupt handler for this EXTI pin */ @@ -252,7 +282,7 @@ xcpt_t stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, { irq = pin + STM32L4_IRQ_EXTI0; nshared = 1; - shared_cbs = &stm32l4_exti_callbacks[pin]; + shared_cbs = &g_gpio_handlers[pin]; switch (pin) { case 0: @@ -280,27 +310,28 @@ xcpt_t stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, { irq = STM32L4_IRQ_EXTI95; handler = stm32l4_exti95_isr; - shared_cbs = &stm32l4_exti_callbacks[5]; + shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { irq = STM32L4_IRQ_EXTI1510; handler = stm32l4_exti1510_isr; - shared_cbs = &stm32l4_exti_callbacks[10]; + shared_cbs = &g_gpio_handlers[10]; nshared = 6; } /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ - oldhandler = stm32l4_exti_callbacks[pin]; - stm32l4_exti_callbacks[pin] = func; + oldhandler = g_gpio_handlers[pin].callback; + g_gpio_handlers[pin].callback = func; + g_gpio_handlers[pin].arg = arg; /* Install external interrupt handlers */ if (func) { - irq_attach(irq, handler); + irq_attach(irq, handler, NULL); up_enable_irq(irq); } else @@ -311,7 +342,7 @@ xcpt_t stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, for (i = 0; i < nshared; i++) { - if (shared_cbs[i] != NULL) + if (shared_cbs[i].callback != NULL) { break; } diff --git a/arch/arm/src/stm32l4/stm32l4_exti_pwr.c b/arch/arm/src/stm32l4/stm32l4_exti_pwr.c index f037936c649..62c1dcfa572 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_pwr.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_pwr.c @@ -65,11 +65,8 @@ /* Interrupt handlers attached to the PVD EXTI */ -static xcpt_t stm32l4_exti_pvd_callback; - -/**************************************************************************** - * Public Data - ****************************************************************************/ +static xcpt_t g_pvd_callback; +static void *g_callback_arg; /**************************************************************************** * Private Functions @@ -83,7 +80,7 @@ static xcpt_t stm32l4_exti_pvd_callback; * ****************************************************************************/ -static int stm32l4_exti_pvd_isr(int irq, void *context) +static int stm32l4_exti_pvd_isr(int irq, void *context, FAR void *arg) { int ret = OK; @@ -93,9 +90,9 @@ static int stm32l4_exti_pvd_isr(int irq, void *context) /* And dispatch the interrupt to the handler */ - if (stm32l4_exti_pvd_callback) + if (g_pvd_callback != NULL) { - ret = stm32l4_exti_pvd_callback(irq, context); + ret = g_pvd_callback(irq, context, g_callback_arg); } return ret; @@ -124,20 +121,21 @@ static int stm32l4_exti_pvd_isr(int irq, void *context) ****************************************************************************/ xcpt_t stm32l4_exti_pvd(bool risingedge, bool fallingedge, bool event, - xcpt_t func) + xcpt_t func, void *arg) { xcpt_t oldhandler; /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ - oldhandler = stm32l4_exti_pvd_callback; - stm32l4_exti_pvd_callback = func; + oldhandler = g_pvd_callback; + g_pvd_callback = func; + g_callback_arg = arg; /* Install external interrupt handlers (if not already attached) */ if (func) { - irq_attach(STM32L4_IRQ_PVD, stm32l4_exti_pvd_isr); + irq_attach(STM32L4_IRQ_PVD, stm32l4_exti_pvd_isr, NULL); up_enable_irq(STM32L4_IRQ_PVD); } else diff --git a/arch/arm/src/stm32l4/stm32l4_exti_pwr.h b/arch/arm/src/stm32l4/stm32l4_exti_pwr.h index 5789e370764..109da434588 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_pwr.h +++ b/arch/arm/src/stm32l4/stm32l4_exti_pwr.h @@ -57,6 +57,7 @@ * - rising/falling edge: enables interrupt on rising/falling edge * - event: generate event when set * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback * * Returns: * The previous value of the interrupt handler function pointer. This @@ -66,6 +67,6 @@ ****************************************************************************/ xcpt_t stm32l4_exti_pvd(bool risingedge, bool fallingedge, bool event, - xcpt_t func); + xcpt_t func, void *arg); #endif /* STM32L4_EXTI_PWR_H_ */ diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.h b/arch/arm/src/stm32l4/stm32l4_gpio.h index 04dbc5679b1..17ce32162fb 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.h +++ b/arch/arm/src/stm32l4/stm32l4_gpio.h @@ -331,6 +331,7 @@ bool stm32l4_gpioread(uint32_t pinset); * - rising/falling edge: enables * - event: generate event when set * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback * * Returns: * The previous value of the interrupt handler function pointer. This value may, @@ -340,7 +341,7 @@ bool stm32l4_gpioread(uint32_t pinset); ************************************************************************************/ xcpt_t stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func); + bool event, xcpt_t func, void *arg); /************************************************************************************ * Function: stm32l4_dumpgpio diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c index eed199f86dd..48aa7a9b0e2 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.c +++ b/arch/arm/src/stm32l4/stm32l4_i2c.c @@ -214,7 +214,7 @@ struct stm32l4_i2c_config_s uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ #ifndef CONFIG_I2C_POLLED - int (*isr)(int, void *); /* Interrupt handler */ + int (*isr)(int, void *, void *); /* Interrupt handler */ uint32_t ev_irq; /* Event IRQ */ uint32_t er_irq; /* Error IRQ */ #endif @@ -292,13 +292,13 @@ static inline uint32_t stm32l4_i2c_getstatus(FAR struct stm32l4_i2c_priv_s *priv static int stm32l4_i2c_isr(struct stm32l4_i2c_priv_s * priv); #ifndef CONFIG_I2C_POLLED #ifdef CONFIG_STM32L4_I2C1 -static int stm32l4_i2c1_isr(int irq, void *context); +static int stm32l4_i2c1_isr(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_STM32L4_I2C2 -static int stm32l4_i2c2_isr(int irq, void *context); +static int stm32l4_i2c2_isr(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_STM32L4_I2C3 -static int stm32l4_i2c3_isr(int irq, void *context); +static int stm32l4_i2c3_isr(int irq, void *context, FAR void *arg); #endif #endif static int stm32l4_i2c_init(FAR struct stm32l4_i2c_priv_s *priv); @@ -1515,7 +1515,7 @@ static int stm32l4_i2c_isr(struct stm32l4_i2c_priv_s *priv) #ifndef CONFIG_I2C_POLLED #ifdef CONFIG_STM32L4_I2C1 -static int stm32l4_i2c1_isr(int irq, void *context) +static int stm32l4_i2c1_isr(int irq, void *context, FAR void *arg) { return stm32l4_i2c_isr(&stm32l4_i2c1_priv); } @@ -1530,7 +1530,7 @@ static int stm32l4_i2c1_isr(int irq, void *context) ************************************************************************************/ #ifdef CONFIG_STM32L4_I2C2 -static int stm32l4_i2c2_isr(int irq, void *context) +static int stm32l4_i2c2_isr(int irq, void *context, FAR void *arg) { return stm32l4_i2c_isr(&stm32l4_i2c2_priv); } @@ -1545,7 +1545,7 @@ static int stm32l4_i2c2_isr(int irq, void *context) ************************************************************************************/ #ifdef CONFIG_STM32L4_I2C3 -static int stm32l4_i2c3_isr(int irq, void *context) +static int stm32l4_i2c3_isr(int irq, void *context, FAR void *arg) { return stm32l4_i2c_isr(&stm32l4_i2c3_priv); } @@ -1590,8 +1590,8 @@ static int stm32l4_i2c_init(FAR struct stm32l4_i2c_priv_s *priv) /* Attach ISRs */ #ifndef CONFIG_I2C_POLLED - irq_attach(priv->config->ev_irq, priv->config->isr); - irq_attach(priv->config->er_irq, priv->config->isr); + irq_attach(priv->config->ev_irq, priv->config->isr, NULL); + irq_attach(priv->config->er_irq, priv->config->isr, NULL); up_enable_irq(priv->config->ev_irq); up_enable_irq(priv->config->er_irq); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_idle.c b/arch/arm/src/stm32l4/stm32l4_idle.c index 60dacd2928d..015be72d039 100644 --- a/arch/arm/src/stm32l4/stm32l4_idle.c +++ b/arch/arm/src/stm32l4/stm32l4_idle.c @@ -42,11 +42,10 @@ #include #include +#include #include #include -#include - #include "chip.h" #include "stm32l4_pm.h" #include "up_internal.h" @@ -97,7 +96,7 @@ static void up_idlepm(void) if (newstate != oldstate) { - flags = irqsave(); + flags = enter_critical_section(); /* Perform board-specific, state-dependent logic here */ @@ -141,7 +140,7 @@ static void up_idlepm(void) break; } - irqrestore(flags); + leave_critical_section(flags); } } #else diff --git a/arch/arm/src/stm32l4/stm32l4_irq.c b/arch/arm/src/stm32l4/stm32l4_irq.c index 720c05ecc69..7a0ed88bd37 100644 --- a/arch/arm/src/stm32l4/stm32l4_irq.c +++ b/arch/arm/src/stm32l4/stm32l4_irq.c @@ -155,7 +155,7 @@ static void stm32l4_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int stm32l4_nmi(int irq, FAR void *context) +static int stm32l4_nmi(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -163,7 +163,7 @@ static int stm32l4_nmi(int irq, FAR void *context) return 0; } -static int stm32l4_busfault(int irq, FAR void *context) +static int stm32l4_busfault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); @@ -171,7 +171,7 @@ static int stm32l4_busfault(int irq, FAR void *context) return 0; } -static int stm32l4_usagefault(int irq, FAR void *context) +static int stm32l4_usagefault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); @@ -179,7 +179,7 @@ static int stm32l4_usagefault(int irq, FAR void *context) return 0; } -static int stm32l4_pendsv(int irq, FAR void *context) +static int stm32l4_pendsv(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -187,7 +187,7 @@ static int stm32l4_pendsv(int irq, FAR void *context) return 0; } -static int stm32l4_dbgmonitor(int irq, FAR void *context) +static int stm32l4_dbgmonitor(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -195,7 +195,7 @@ static int stm32l4_dbgmonitor(int irq, FAR void *context) return 0; } -static int stm32l4_reserved(int irq, FAR void *context) +static int stm32l4_reserved(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -366,8 +366,8 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32L4_IRQ_SVCALL, up_svcall); - irq_attach(STM32L4_IRQ_HARDFAULT, up_hardfault); + irq_attach(STM32L4_IRQ_SVCALL, up_svcall, NULL); + irq_attach(STM32L4_IRQ_HARDFAULT, up_hardfault, NULL); /* Set the priority of the SVCall interrupt */ @@ -383,22 +383,22 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(STM32L4_IRQ_MEMFAULT, up_memfault); + irq_attach(STM32L4_IRQ_MEMFAULT, up_memfault, NULL); up_enable_irq(STM32L4_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32L4_IRQ_NMI, stm32l4_nmi); + irq_attach(STM32L4_IRQ_NMI, stm32l4_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(STM32L4_IRQ_MEMFAULT, up_memfault); + irq_attach(STM32L4_IRQ_MEMFAULT, up_memfault, NULL); #endif - irq_attach(STM32L4_IRQ_BUSFAULT, stm32l4_busfault); - irq_attach(STM32L4_IRQ_USAGEFAULT, stm32l4_usagefault); - irq_attach(STM32L4_IRQ_PENDSV, stm32l4_pendsv); - irq_attach(STM32L4_IRQ_DBGMONITOR, stm32l4_dbgmonitor); - irq_attach(STM32L4_IRQ_RESERVED, stm32l4_reserved); + irq_attach(STM32L4_IRQ_BUSFAULT, stm32l4_busfault, NULL); + irq_attach(STM32L4_IRQ_USAGEFAULT, stm32l4_usagefault, NULL); + irq_attach(STM32L4_IRQ_PENDSV, stm32l4_pendsv, NULL); + irq_attach(STM32L4_IRQ_DBGMONITOR, stm32l4_dbgmonitor, NULL); + irq_attach(STM32L4_IRQ_RESERVED, stm32l4_reserved, NULL); #endif stm32l4_dumpnvic("initial", NR_IRQS); diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.c b/arch/arm/src/stm32l4/stm32l4_lptim.c new file mode 100644 index 00000000000..4833472120c --- /dev/null +++ b/arch/arm/src/stm32l4/stm32l4_lptim.c @@ -0,0 +1,548 @@ +/************************************************************************************ + * arm/arm/src/stm3l42/stm32l4_lptim.c + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise + * + * With modifications and updates by: + * + * Copyright (C) 2016 Motorola Mobility, LLC. All rights reserved. + * Copyright (C) 2011-2012, 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ +/************************************************************************************ + * Copyright (c) 2015 Google, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +#include "stm32l4.h" +#include "stm32l4_gpio.h" +#include "stm32l4_lptim.h" + +#if defined(CONFIG_STM32L4_LPTIM1) || defined(CONFIG_STM32L4_LPTIM2) + +/************************************************************************************ + * Private Types + ************************************************************************************/ + +/* TIM Device Structure */ + +struct stm32l4_lptim_priv_s +{ + const struct stm32l4_lptim_ops_s *ops; + stm32l4_lptim_mode_t mode; + uint32_t base; /* LPTIMn base address */ + uint32_t freq; /* Clocking for the LPTIM module */ +}; + +/************************************************************************************ + * Private Function Prototypes + ************************************************************************************/ + +static struct stm32l4_lptim_dev_s *stm32l4_lptim_getstruct(int timer); +static inline void stm32l4_modifyreg32(FAR struct stm32l4_lptim_dev_s *dev, + uint8_t offset, uint32_t clearbits, + uint32_t setbits); +static int stm32l4_lptim_enable(FAR struct stm32l4_lptim_dev_s *dev); +static int stm32l4_lptim_disable(FAR struct stm32l4_lptim_dev_s *dev); +static int stm32l4_lptim_reset(FAR struct stm32l4_lptim_dev_s *dev); +static int stm32l4_lptim_get_gpioconfig(FAR struct stm32l4_lptim_dev_s *dev, + stm32l4_lptim_channel_t channel, + uint32_t *cfg); +static int stm32l4_lptim_setmode(FAR struct stm32l4_lptim_dev_s *dev, + stm32l4_lptim_mode_t mode); +static int stm32l4_lptim_setclock(FAR struct stm32l4_lptim_dev_s *dev, + uint32_t freq); +static int stm32l4_lptim_setchannel(FAR struct stm32l4_lptim_dev_s *dev, + stm32l4_lptim_channel_t channel, int enable); + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +static const struct stm32l4_lptim_ops_s stm32l4_lptim_ops = +{ + .setmode = &stm32l4_lptim_setmode, + .setclock = &stm32l4_lptim_setclock, + .setchannel = &stm32l4_lptim_setchannel, +}; + +#if CONFIG_STM32L4_LPTIM1 +static struct stm32l4_lptim_priv_s stm32l4_lptim1_priv = +{ + .ops = &stm32l4_lptim_ops, + .mode = STM32L4_LPTIM_MODE_UNUSED, + .base = STM32L4_LPTIM1_BASE, + .freq = STM32L4_LPTIM1_FREQUENCY, /* Must be efined in board.h */ +}; +#endif + +#if CONFIG_STM32L4_LPTIM2 +static struct stm32l4_lptim_priv_s stm32l4_lptim2_priv = +{ + .ops = &stm32l4_lptim_ops, + .mode = STM32L4_LPTIM_MODE_UNUSED, + .base = STM32L4_LPTIM2_BASE, + .freq = STM32L4_LPTIM2_FREQUENCY, /* Must be efined in board.h */ +}; +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32l4_lptim_getstruct + ************************************************************************************/ + +static struct stm32l4_lptim_dev_s *stm32l4_lptim_getstruct(int timer) +{ + switch (timer) + { +#if CONFIG_STM32L4_LPTIM1 + case 1: + return (struct stm32l4_lptim_dev_s *)&stm32l4_lptim1_priv; +#endif +#if CONFIG_STM32L4_LPTIM2 + case 2: + return (struct stm32l4_lptim_dev_s *)&stm32l4_lptim2_priv; +#endif + default: + return NULL; + } +} + +/************************************************************************************ + * Name: stm32l4_modifyreg32 + ************************************************************************************/ + +static inline void stm32l4_modifyreg32(FAR struct stm32l4_lptim_dev_s *dev, + uint8_t offset, uint32_t clearbits, + uint32_t setbits) +{ + modifyreg32(((struct stm32l4_lptim_priv_s *)dev)->base + offset, clearbits, setbits); +} + +/************************************************************************************ + * Name: stm32l4_lptim_enable + ************************************************************************************/ + +static int stm32l4_lptim_enable(FAR struct stm32l4_lptim_dev_s *dev) +{ + DEBUGASSERT(dev != NULL); + + switch (((struct stm32l4_lptim_priv_s *)dev)->base) + { +#if CONFIG_STM32L4_LPTIM1 + case STM32L4_LPTIM1_BASE: + modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN); + break; +#endif +#if CONFIG_STM32L4_LPTIM2 + case STM32L4_LPTIM2_BASE: + modifyreg32(STM32L4_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN); + break; +#endif + + default: + return ERROR; + } + + return OK; +} + +/************************************************************************************ + * Name: stm32l4_lptim_disable + ************************************************************************************/ + +static int stm32l4_lptim_disable(FAR struct stm32l4_lptim_dev_s *dev) +{ + DEBUGASSERT(dev != NULL); + + switch (((struct stm32l4_lptim_priv_s *)dev)->base) + { +#if CONFIG_STM32L4_LPTIM1 + case STM32L4_LPTIM1_BASE: + modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0); + break; +#endif +#if CONFIG_STM32L4_LPTIM2 + case STM32L4_LPTIM2_BASE: + modifyreg32(STM32L4_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0); + break; +#endif + + default: + return ERROR; + } + + return OK; +} + +/************************************************************************************ + * Name: stm32l4_lptim_reset + ************************************************************************************/ + +static int stm32l4_lptim_reset(FAR struct stm32l4_lptim_dev_s *dev) +{ + DEBUGASSERT(dev != NULL); + + switch (((struct stm32l4_lptim_priv_s *)dev)->base) + { +#if CONFIG_STM32L4_LPTIM1 + case STM32L4_LPTIM1_BASE: + modifyreg32(STM32L4_RCC_APB1RSTR1, 0, RCC_APB1RSTR1_LPTIM1RST); + modifyreg32(STM32L4_RCC_APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST, 0); + break; +#endif +#if CONFIG_STM32L4_LPTIM2 + case STM32L4_LPTIM2_BASE: + modifyreg32(STM32L4_RCC_APB1RSTR2, 0, RCC_APB1RSTR2_LPTIM2RST); + modifyreg32(STM32L4_RCC_APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST, 0); + break; +#endif + } + + return OK; +} + +/************************************************************************************ + * Name: stm32l4_lptim_get_gpioconfig + ************************************************************************************/ + +static int stm32l4_lptim_get_gpioconfig(FAR struct stm32l4_lptim_dev_s *dev, + stm32l4_lptim_channel_t channel, + uint32_t *cfg) +{ + DEBUGASSERT(dev != NULL && cfg != NULL); + + channel &= STM32L4_LPTIM_CH_MASK; + + switch (((struct stm32l4_lptim_priv_s *)dev)->base) + { +#if CONFIG_STM32L4_LPTIM1 + case STM32L4_LPTIM1_BASE: + switch (channel) + { +# if defined(GPIO_LPTIM1_OUT_1) + case 1: + *cfg = GPIO_LPTIM1_OUT_1; + break; +# endif +# if defined(GPIO_LPTIM1_OUT_2) + case 2: + *cfg = GPIO_LPTIM1_OUT_2; + break; +# endif +# if defined(GPIO_LPTIM1_OUT_3) + case 3: + *cfg = GPIO_LPTIM1_OUT_3; + break; +# endif + default: + return ERROR; + } + break; +#endif /* CONFIG_STM32L4_LPTIM1 */ + +#if CONFIG_STM32L4_LPTIM2 + case STM32L4_LPTIM2_BASE: + switch (channel) + { +# if defined(GPIO_LPTIM2_OUT_1) + case 1: + *cfg = GPIO_LPTIM2_OUT_1; + break; +# endif +# if defined(GPIO_LPTIM2_OUT_2) + case 2: + *cfg = GPIO_LPTIM2_OUT_2; + break; +# endif +# if defined(GPIO_LPTIM2_OUT_3) + case 3: + *cfg = GPIO_LPTIM2_OUT_3; + break; +# endif + default: + return ERROR; + } + break; +#endif /* CONFIG_STM32L4_LPTIM2 */ + + default: + return ERROR; + } + + return OK; +} + +/************************************************************************************ + * Name: stm32l4_lptim_setmode + ************************************************************************************/ + +static int stm32l4_lptim_setmode(FAR struct stm32l4_lptim_dev_s *dev, + stm32l4_lptim_mode_t mode) +{ + const uint32_t addr = ((struct stm32l4_lptim_priv_s *)dev)->base + + STM32L4_LPTIM_CR_OFFSET; + + DEBUGASSERT(dev != NULL); + + /* Mode */ + + switch (mode & STM32L4_LPTIM_MODE_MASK) + { + case STM32L4_LPTIM_MODE_DISABLED: + modifyreg32(addr, LPTIM_CR_ENABLE, 0); + break; + + case STM32L4_LPTIM_MODE_SINGLE: + modifyreg32(addr, 0, LPTIM_CR_ENABLE); + modifyreg32(addr, 0, LPTIM_CR_SNGSTRT); + break; + + case STM32L4_LPTIM_MODE_CONTINUOUS: + modifyreg32(addr, 0, LPTIM_CR_ENABLE); + modifyreg32(addr, 0, LPTIM_CR_CNTSTRT); + break; + + default: + return ERROR; + } + + /* Save mode */ + + ((struct stm32l4_lptim_priv_s *)dev)->mode = mode; + + return OK; +} + +/************************************************************************************ + * Name: stm32l4_lptim_setclock + ************************************************************************************/ + +static int stm32l4_lptim_setclock(FAR struct stm32l4_lptim_dev_s *dev, + uint32_t freq) +{ + FAR struct stm32l4_lptim_priv_s *priv = (FAR struct stm32l4_lptim_priv_s *)dev; + uint32_t setbits; + uint32_t actual; + + DEBUGASSERT(dev != NULL); + + /* Disable Timer? */ + + if (freq == 0) + { + stm32l4_lptim_disable(dev); + return 0; + } + + if (freq >= priv->freq >> 0) + { + /* More than clock source. This is as fast as we can go */ + + setbits = LPTIM_CFGR_PRESCd1; + actual = priv->freq >> 0; + } + else if (freq >= priv->freq >> 1) + { + setbits = LPTIM_CFGR_PRESCd2; + actual = priv->freq >> 1; + } + else if (freq >= priv->freq >> 2) + { + setbits = LPTIM_CFGR_PRESCd4; + actual = priv->freq >> 2; + } + else if (freq >= priv->freq >> 3) + { + setbits = LPTIM_CFGR_PRESCd8; + actual = priv->freq >> 3; + } + else if (freq >= priv->freq >> 4) + { + setbits = LPTIM_CFGR_PRESCd16; + actual = priv->freq >> 4; + } + else if (freq >= priv->freq >> 5) + { + setbits = LPTIM_CFGR_PRESCd32; + actual = priv->freq >> 5; + } + else if (freq >= priv->freq >> 6) + { + setbits = LPTIM_CFGR_PRESCd64; + actual = priv->freq >> 6; + } + else + { + /* This is as slow as we can go */ + + setbits = LPTIM_CFGR_PRESCd128; + actual = priv->freq >> 7; + } + + stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, LPTIM_CFGR_PRESC_MASK, + setbits); + stm32l4_lptim_enable(dev); + + return actual; +} + +/************************************************************************************ + * Name: stm32l4_lptim_setchannel + ************************************************************************************/ + +static int stm32l4_lptim_setchannel(FAR struct stm32l4_lptim_dev_s *dev, + stm32l4_lptim_channel_t channel, int enable) +{ + int ret = OK; + uint32_t cfg = 0; + + ASSERT(dev); + + /* Configure GPIOs */ + + ret = stm32l4_lptim_get_gpioconfig(dev, channel, &cfg); + if (!ret) + { + if (enable) + { + stm32l4_configgpio(cfg); + } + else + { + stm32l4_unconfiggpio(cfg); + } + } + + return ret; +} + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32l4_lptim_init + ************************************************************************************/ + +FAR struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer) +{ + struct stm32l4_lptim_dev_s *dev = NULL; + + /* Get structure and enable power */ + + dev = stm32l4_lptim_getstruct(timer); + if (!dev) + { + return NULL; + } + + /* Is device already allocated */ + + if (((struct stm32l4_lptim_priv_s *)dev)->mode != STM32L4_LPTIM_MODE_UNUSED) + { + return NULL; + } + + /* Enable power */ + + stm32l4_lptim_enable(dev); + + /* Reset timer */ + + stm32l4_lptim_reset(dev); + + /* Mark it as used */ + + ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32L4_LPTIM_MODE_DISABLED; + + return dev; +} + +/************************************************************************************ + * Name: stm32l4_lptim_deinit + ************************************************************************************/ + +int stm32l4_lptim_deinit(FAR struct stm32l4_lptim_dev_s * dev) +{ + ASSERT(dev); + + /* Disable power */ + + stm32l4_lptim_disable(dev); + + /* Mark it as free */ + + ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32L4_LPTIM_MODE_UNUSED; + + return OK; +} + +#endif /* CONFIG_STM32L4_LPTIM1 || CONFIG_STM32L4_LPTIM2 */ diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.h b/arch/arm/src/stm32l4/stm32l4_lptim.h new file mode 100644 index 00000000000..90e0cb0d3bb --- /dev/null +++ b/arch/arm/src/stm32l4/stm32l4_lptim.h @@ -0,0 +1,171 @@ +/************************************************************************************ + * arch/arm/src/stm32l4/stm32l4_lptim.h + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise + * + * With modifications and updates by: + * + * Copyright (C) 2016 Motorola Mobility, LLC. All rights reserved. + * Copyright (C) 2011-2012, 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ +/************************************************************************************ + * Copyright (c) 2015 Google, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_LPTIM_H +#define __ARCH_ARM_SRC_STM32L4_STM32L4_LPTIM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/stm32l4_lptim.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Helpers **************************************************************************/ + +#define STM32L4_LPTIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32L4_LPTIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32L4_LPTIM_SETCHANNEL(d,ch,en) ((d)->ops->setchannel(d,ch,en)) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* LPTIM Device Structure */ + +struct stm32l4_lptim_dev_s +{ + struct stm32l4_lptim_ops_s *ops; +}; + +/* LPTIM Modes of Operation */ + +typedef enum +{ + STM32L4_LPTIM_MODE_UNUSED = -1, + + /* MODES */ + + STM32L4_LPTIM_MODE_DISABLED = 0x0000, + STM32L4_LPTIM_MODE_SINGLE = 0x0001, + STM32L4_LPTIM_MODE_CONTINUOUS = 0x0002, + STM32L4_LPTIM_MODE_MASK = 0x003f, +} stm32l4_lptim_mode_t; + +/* LPTIM Channel Modes */ + +typedef enum +{ + STM32L4_LPTIM_CH_DISABLED = 0x0000, + + /* CHANNELS */ + + STM32L4_LPTIM_CH_CHINVALID = 0x0000, + STM32L4_LPTIM_CH_CH1 = 0x0001, + STM32L4_LPTIM_CH_CH2 = 0x0002, + STM32L4_LPTIM_CH_CH3 = 0x0003, + STM32L4_LPTIM_CH_MASK = 0x000f, +} stm32l4_lptim_channel_t; + +/* LPTIM Operations */ + +struct stm32l4_lptim_ops_s +{ + int (*setmode)(FAR struct stm32l4_lptim_dev_s *dev, stm32l4_lptim_mode_t mode); + int (*setclock)(FAR struct stm32l4_lptim_dev_s *dev, uint32_t freq); + int (*setchannel)(FAR struct stm32l4_lptim_dev_s *dev, + stm32l4_lptim_channel_t channel, int enable); +}; + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/* Get timer structure, power-up, reset, and mark it as used */ + +FAR struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer); + +/* Power-down timer, mark it as unused */ + +int stm32l4_lptim_deinit(FAR struct stm32l4_lptim_dev_s *dev); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_LPTIM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_otgfs.h b/arch/arm/src/stm32l4/stm32l4_otgfs.h index cdeb0ee590e..0d64e0a72ca 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfs.h +++ b/arch/arm/src/stm32l4/stm32l4_otgfs.h @@ -124,6 +124,5 @@ void stm32l4_usbsuspend(FAR struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32_OTGFS */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_OTGFS_H */ - +#endif /* CONFIG_STM32L4_OTGFS */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_OTGFS_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c index 407534f4fbc..d57701ad6ae 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c @@ -678,7 +678,7 @@ static inline void stm32l4_otginterrupt(FAR struct stm32l4_usbdev_s *priv); /* First level interrupt processing */ -static int stm32l4_usbinterrupt(int irq, FAR void *context); +static int stm32l4_usbinterrupt(int irq, FAR void *context, FAR void *arg); /* Endpoint operations *********************************************************/ /* Global OUT NAK controls */ @@ -3621,7 +3621,7 @@ static inline void stm32l4_otginterrupt(FAR struct stm32l4_usbdev_s *priv) * ****************************************************************************/ -static int stm32l4_usbinterrupt(int irq, FAR void *context) +static int stm32l4_usbinterrupt(int irq, FAR void *context, FAR void *arg) { /* At present, there is only a single OTG FS device support. Hence it is * pre-allocated as g_otgfsdev. However, in most code, the private data @@ -5584,7 +5584,7 @@ void up_usbinitialize(void) /* Attach the OTG FS interrupt handler */ - ret = irq_attach(STM32L4_IRQ_OTGFS, stm32l4_usbinterrupt); + ret = irq_attach(STM32L4_IRQ_OTGFS, stm32l4_usbinterrupt, NULL); if (ret < 0) { uerr("irq_attach failed\n", ret); diff --git a/arch/arm/src/stm32l4/stm32l4_otgfshost.c b/arch/arm/src/stm32l4/stm32l4_otgfshost.c index d47295f429b..f6a34f1f7a4 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfshost.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfshost.c @@ -405,7 +405,7 @@ static inline void stm32l4_gint_ipxfrisr(FAR struct stm32l4_usbhost_s *priv); /* First level, global interrupt handler */ -static int stm32l4_gint_isr(int irq, FAR void *context); +static int stm32l4_gint_isr(int irq, FAR void *context, FAR void *arg); /* Interrupt controls */ @@ -3436,7 +3436,7 @@ static inline void stm32l4_gint_ipxfrisr(FAR struct stm32l4_usbhost_s *priv) * ****************************************************************************/ -static int stm32l4_gint_isr(int irq, FAR void *context) +static int stm32l4_gint_isr(int irq, FAR void *context, FAR void *arg) { /* At present, there is only support for a single OTG FS host. Hence it is * pre-allocated as g_usbhost. However, in most code, the private data @@ -5307,7 +5307,7 @@ FAR struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) /* Attach USB host controller interrupt handler */ - if (irq_attach(STM32L4_IRQ_OTGFS, stm32l4_gint_isr) != 0) + if (irq_attach(STM32L4_IRQ_OTGFS, stm32l4_gint_isr, NULL) != 0) { usbhost_trace1(OTGFS_TRACE1_IRQATTACH, 0); return NULL; diff --git a/arch/arm/src/stm32l4/stm32l4_pm.h b/arch/arm/src/stm32l4/stm32l4_pm.h index e69de29bb2d..0bf7a827f39 100644 --- a/arch/arm/src/stm32l4/stm32l4_pm.h +++ b/arch/arm/src/stm32l4/stm32l4_pm.h @@ -0,0 +1,171 @@ +/************************************************************************************ + * arch/arm/src/stm32l4/stm32l4_pm.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_PM_H +#define __ARCH_ARM_SRC_STM32L4_STM32L4_PM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "chip.h" +#include "up_internal.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32l4_pmstop + * + * Description: + * Enter STOP mode. + * + * Input Parameters: + * lpds - true: To further reduce power consumption in Stop mode, put the + * internal voltage regulator in low-power mode using the LPDS bit + * of the Power control register (PWR_CR). + * + * Returned Value: + * Zero means that the STOP was successfully entered and the system has + * been re-awakened. The internal voltage regulator is back to its + * original state. Otherwise, STOP mode did not occur and a negated + * errno value is returned to indicate the cause of the failure. + * + ****************************************************************************/ + +int stm32l4_pmstop(bool lpds); + +/**************************************************************************** + * Name: stm32l4_pmstop2 + * + * Description: + * Enter STOP2 mode. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero means that the STOP2 was successfully entered and the system has + * been re-awakened. Otherwise, STOP2 mode did not occur and a negated + * errno value is returned to indicate the cause of the failure. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4X3) +int stm32l4_pmstop2(void); +#endif + +/**************************************************************************** + * Name: stm32l4_pmstandby + * + * Description: + * Enter STANDBY mode. + * + * Input Parameters: + * None + * + * Returned Value. + * On success, this function will not return (STANDBY mode can only be + * terminated with a reset event). Otherwise, STANDBY mode did not occur + * and a negated errno value is returned to indicate the cause of the + * failure. + * + ****************************************************************************/ + +int stm32l4_pmstandby(void); + +/**************************************************************************** + * Name: stm32l4_pmsleep + * + * Description: + * Enter SLEEP mode. + * + * Input Parameters: + * sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is + * executed, the MCU enters Sleep mode as soon as it + * exits the lowest priority ISR. + * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep mode + * as soon as WFI or WFE instruction is executed. + * Returned Value: + * Zero means that the STOP was successfully entered and the system has + * been re-awakened. The internal volatage regulator is back to its + * original state. Otherwise, STOP mode did not occur and a negated + * errno value is returned to indicate the cause of the failure. + * + ****************************************************************************/ + +void stm32l4_pmsleep(bool sleeponexit); + +/**************************************************************************** + * Name: stm32l4_pmlpr + * + * Description: + * Enter Low-Power Run (LPR) mode. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero means that LPR was successfully entered. Otherwise, LPR mode was not + * entered and a negated errno value is returned to indicate the cause of the + * failure. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4X3) +int stm32l4_pmlpr(void); +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_PM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_pminitialize.c b/arch/arm/src/stm32l4/stm32l4_pminitialize.c new file mode 100644 index 00000000000..05988f21bf5 --- /dev/null +++ b/arch/arm/src/stm32l4/stm32l4_pminitialize.c @@ -0,0 +1,78 @@ +/**************************************************************************** + * arch/arm/src/stm32l4/stm32l4_pminitialize.c + * + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "up_internal.h" +#include "stm32l4_pm.h" + +#ifdef CONFIG_PM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_pminitialize + * + * Description: + * This function is called by MCU-specific logic at power-on reset in + * order to provide one-time initialization the power management subystem. + * This function must be called *very* early in the initialization sequence + * *before* any other device drivers are initialized (since they may + * attempt to register with the power management subsystem). + * + * Input parameters: + * None. + * + * Returned value: + * None. + * + ****************************************************************************/ + +void up_pminitialize(void) +{ + /* Then initialize the NuttX power management subsystem proper */ + + pm_initialize(); +} + +#endif /* CONFIG_PM */ diff --git a/arch/arm/src/stm32l4/stm32l4_pmlpr.c b/arch/arm/src/stm32l4/stm32l4_pmlpr.c new file mode 100644 index 00000000000..83a6782cf72 --- /dev/null +++ b/arch/arm/src/stm32l4/stm32l4_pmlpr.c @@ -0,0 +1,111 @@ +/**************************************************************************** + * arch/arm/src/stm32l4/stm32l4_pmlpr.c + * + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2015 Motorola Mobility, LLC. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "up_arch.h" +#include "nvic.h" +#include "stm32l4_pwr.h" +#include "stm32l4_pm.h" +#include "stm32l4_rcc.h" + +#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4X3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32l4_pmlpr + * + * Description: + * Enter Low-Power Run (LPR) mode. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero means that LPR was successfully entered. Otherwise, LPR mode was not + * entered and a negated errno value is returned to indicate the cause of the + * failure. + * + ****************************************************************************/ + +int stm32l4_pmlpr(void) +{ + uint32_t regval; + + /* Enable MSI clock */ + + regval = getreg32(STM32L4_RCC_CR); + regval |= RCC_CR_MSION; + + /* Set MSI clock to 2 MHz */ + + regval &= ~RCC_CR_MSIRANGE_MASK; + regval |= RCC_CR_MSIRANGE_2M; /* 2 MHz */ + regval |= RCC_CR_MSIRGSEL; /* Select new MSIRANGE */ + putreg32(regval, STM32L4_RCC_CR); + + /* Select MSI clock as system clock source */ + + regval = getreg32(STM32L4_RCC_CFGR); + regval &= ~RCC_CFGR_SW_MASK; + regval |= RCC_CFGR_SW_MSI; + putreg32(regval, STM32L4_RCC_CFGR); + + /* Wait until the MSI source is used as the system clock source */ + + while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_MSI) + { + } + + /* Enable Low-Power Run */ + + regval = getreg32(STM32L4_PWR_CR1); + regval |= PWR_CR1_LPR; + putreg32(regval, STM32L4_PWR_CR1); + + return OK; +} + +#endif /* CONFIG_STM32L4_STM32L4X6 || CONFIG_STM32L4_STM32L4X3 */ diff --git a/arch/arm/src/stm32l4/stm32l4_pmsleep.c b/arch/arm/src/stm32l4/stm32l4_pmsleep.c new file mode 100644 index 00000000000..2a5ebcd58ae --- /dev/null +++ b/arch/arm/src/stm32l4/stm32l4_pmsleep.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * arch/arm/src/stm32l4/stm32l4_pmsleep.c + * + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * Diego Sanchez + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "up_arch.h" +#include "nvic.h" +#include "stm32l4_pwr.h" +#include "stm32l4_pm.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32l4_pmsleep + * + * Description: + * Enter SLEEP mode. + * + * Input Parameters: + * sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is + * executed, the MCU enters Sleep mode as soon as it + * exits the lowest priority ISR. + * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep mode + * as soon as WFI or WFE instruction is executed. + * Returned Value: + * Zero means that the STOP was successfully entered and the system has + * been re-awakened. The internal volatage regulator is back to its + * original state. Otherwise, STOP mode did not occur and a negated + * errno value is returned to indicate the cause of the failure. + * + ****************************************************************************/ + +void stm32l4_pmsleep(bool sleeponexit) +{ + uint32_t regval; + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + + regval = getreg32(NVIC_SYSCON); + regval &= ~NVIC_SYSCON_SLEEPDEEP; + if (sleeponexit) + { + regval |= NVIC_SYSCON_SLEEPONEXIT; + } + else + { + regval &= ~NVIC_SYSCON_SLEEPONEXIT; + } + + putreg32(regval, NVIC_SYSCON); + + /* Sleep until the wakeup interrupt or event occurs */ + +#ifdef CONFIG_PM_WFE + /* Mode: SLEEP + Entry with WFE */ + + asm("wfe"); +#else + /* Mode: SLEEP + Entry with WFI */ + + asm("wfi"); +#endif +} diff --git a/arch/arm/src/stm32l4/stm32l4_pmstandby.c b/arch/arm/src/stm32l4/stm32l4_pmstandby.c new file mode 100644 index 00000000000..99101ee5280 --- /dev/null +++ b/arch/arm/src/stm32l4/stm32l4_pmstandby.c @@ -0,0 +1,114 @@ +/**************************************************************************** + * arch/arm/src/stm32l4/stm32l4_pmstandby.c + * + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2015 Motorola Mobility, LLC. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "up_arch.h" +#include "nvic.h" +#include "stm32l4_pwr.h" +#include "stm32l4_pm.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32l4_pmstandby + * + * Description: + * Enter STANDBY mode. + * + * Input Parameters: + * None + * + * Returned Value. + * On success, this function will not return (STANDBY mode can only be + * terminated with a reset event). Otherwise, STANDBY mode did not occur + * and a negated errno value is returned to indicate the cause of the + * failure. + * + ****************************************************************************/ + +int stm32l4_pmstandby(void) +{ + uint32_t regval; + +#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4X3) + /* Clear the Wake-Up Flags by setting the CWUFx bits in the power status + * clear register + */ + regval = PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3 | + PWR_SCR_CWUF4 | PWR_SCR_CWUF5; + putreg32(regval, STM32L4_PWR_SCR); + + /* Select Standby mode */ + regval = getreg32(STM32L4_PWR_CR1); + regval &= ~PWR_CR1_LPMS_MASK; + regval |= PWR_CR1_LPMS_STANDBY; + + putreg32(regval, STM32L4_PWR_CR1); +#else + /* Clear the Wake-Up Flag by setting the CWUF bit in the power control + * register. + */ + + regval = getreg32(STM32L4_PWR_CR); + regval |= PWR_CR_CWUF; + putreg32(regval, STM32L4_PWR_CR); + + /* Set the Power Down Deep Sleep (PDDS) bit in the power control register. */ + + regval |= PWR_CR_PDDS; + putreg32(regval, STM32L4_PWR_CR); +#endif + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + + regval = getreg32(NVIC_SYSCON); + regval |= NVIC_SYSCON_SLEEPDEEP; + putreg32(regval, NVIC_SYSCON); + + /* Sleep until the wakeup reset occurs */ + + asm("wfi"); + return OK; /* Won't get here */ +} diff --git a/arch/arm/src/stm32l4/stm32l4_pmstop.c b/arch/arm/src/stm32l4/stm32l4_pmstop.c new file mode 100644 index 00000000000..9be563cf9ec --- /dev/null +++ b/arch/arm/src/stm32l4/stm32l4_pmstop.c @@ -0,0 +1,177 @@ +/**************************************************************************** + * arch/arm/src/stm32l4/stm32l4_pmstop.c + * + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2015 Motorola Mobility, LLC. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "up_arch.h" +#include "nvic.h" +#include "stm32l4_pwr.h" +#include "stm32l4_pm.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int do_stop(void) +{ + uint32_t regval; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + + regval = getreg32(NVIC_SYSCON); + regval |= NVIC_SYSCON_SLEEPDEEP; + putreg32(regval, NVIC_SYSCON); + + /* Sleep until the wakeup interrupt or event occurs */ + +#ifdef CONFIG_PM_WFE + /* Mode: SLEEP + Entry with WFE */ + + asm("wfe"); +#else + /* Mode: SLEEP + Entry with WFI */ + + asm("wfi"); +#endif + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + + regval = getreg32(NVIC_SYSCON); + regval &= ~NVIC_SYSCON_SLEEPDEEP; + putreg32(regval, NVIC_SYSCON); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32l4_pmstop + * + * Description: + * Enter STOP mode. + * + * Input Parameters: + * lpds - true: To further reduce power consumption in Stop mode, put the + * internal voltage regulator in low-power mode using the LPDS bit + * of the Power control register (PWR_CR). + * + * Returned Value: + * Zero means that the STOP was successfully entered and the system has + * been re-awakened. The internal volatage regulator is back to its + * original state. Otherwise, STOP mode did not occur and a negated + * errno value is returned to indicate the cause of the failure. + * + ****************************************************************************/ + +int stm32l4_pmstop(bool lpds) +{ + uint32_t regval; + +#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4X3) + /* Clear Low-Power Mode Selection (LPMS) bits in power control register 1. */ + regval = getreg32(STM32L4_PWR_CR1); + regval &= ~PWR_CR1_LPMS_MASK; + + /* Select Stop 1 mode with low-power regulator if so requested */ + if (lpds) + { + regval |= PWR_CR1_LPMS_STOP1LPR; + } + + putreg32(regval, STM32L4_PWR_CR1); +#else + /* Clear the Power Down Deep Sleep (PDDS), Low Power Deep Sleep (LPDS), and + * Low Power regulator Low Voltage in Deep Sleep (LPLVDS) bits in the power + * control register. + */ + + regval = getreg32(STM32L4_PWR_CR); + regval &= ~(PWR_CR_LPDS | PWR_CR_PDDS | PWR_CR_LPLVDS); + + /* Set the Low Power Deep Sleep (LPDS) and Low Power regulator Low Voltage + * in Deep Sleep (LPLVDS) bits if so requested */ + + if (lpds) + { + regval |= PWR_CR_LPDS | PWR_CR_LPLVDS; + } + + putreg32(regval, STM32L4_PWR_CR); +#endif + + return do_stop(); +} + +/**************************************************************************** + * Name: stm32l4_pmstop2 + * + * Description: + * Enter STOP2 mode. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero means that the STOP2 was successfully entered and the system has + * been re-awakened. Otherwise, STOP2 mode did not occur and a negated + * errno value is returned to indicate the cause of the failure. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4X3) +int stm32l4_pmstop2(void) +{ + uint32_t regval; + + /* Select Stop 2 mode in power control register 1. */ + + regval = getreg32(STM32L4_PWR_CR1); + regval &= ~PWR_CR1_LPMS_MASK; + regval |= PWR_CR1_LPMS_STOP2; + putreg32(regval, STM32L4_PWR_CR1); + + return do_stop(); +} +#endif diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c index 80214fb9e5b..fe46e8cc4ef 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.c +++ b/arch/arm/src/stm32l4/stm32l4_pwm.c @@ -178,10 +178,10 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv, #if defined(CONFIG_PWM_PULSECOUNT) && (defined(CONFIG_STM32L4_TIM1_PWM) || defined(CONFIG_STM32L4_TIM8_PWM)) static int stm32l4pwm_interrupt(struct stm32l4_pwmtimer_s *priv); #if defined(CONFIG_STM32L4_TIM1_PWM) -static int stm32l4pwm_tim1interrupt(int irq, void *context); +static int stm32l4pwm_tim1interrupt(int irq, void *context, FAR void *arg); #endif #if defined(CONFIG_STM32L4_TIM8_PWM) -static int stm32l4pwm_tim8interrupt(int irq, void *context); +static int stm32l4pwm_tim8interrupt(int irq, void *context, FAR void *arg); #endif static uint8_t stm32l4pwm_pulsecount(uint32_t count); #endif @@ -1527,14 +1527,14 @@ static int stm32l4pwm_interrupt(struct stm32l4_pwmtimer_s *priv) ****************************************************************************/ #if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_STM32L4_TIM1_PWM) -static int stm32l4pwm_tim1interrupt(int irq, void *context) +static int stm32l4pwm_tim1interrupt(int irq, void *context, FAR void *arg) { return stm32l4pwm_interrupt(&g_pwm1dev); } #endif #if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_STM32L4_TIM8_PWM) -static int stm32l4pwm_tim8interrupt(int irq, void *context) +static int stm32l4pwm_tim8interrupt(int irq, void *context, FAR void *arg) { return stm32l4pwm_interrupt(&g_pwm8dev); } @@ -2072,7 +2072,7 @@ FAR struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer) /* Attach but disable the TIM1 update interrupt */ #ifdef CONFIG_PWM_PULSECOUNT - irq_attach(lower->irq, stm32l4pwm_tim1interrupt); + irq_attach(lower->irq, stm32l4pwm_tim1interrupt, NULL); up_disable_irq(lower->irq); #endif break; @@ -2109,7 +2109,7 @@ FAR struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer) /* Attach but disable the TIM8 update interrupt */ #ifdef CONFIG_PWM_PULSECOUNT - irq_attach(lower->irq, stm32l4pwm_tim8interrupt); + irq_attach(lower->irq, stm32l4pwm_tim8interrupt, NULL); up_disable_irq(lower->irq); #endif break; diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c index 4e0ebb0283c..7c65b95d5a9 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.c +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.c @@ -199,7 +199,6 @@ struct stm32l4_qeconfig_s uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */ uint32_t base; /* Register base address */ uint32_t psc; /* Encoder pulses prescaler */ - xcpt_t handler; /* Interrupt handler for this IRQ */ }; /* Overall, RAM-based state structure */ @@ -244,25 +243,7 @@ static FAR struct stm32l4_lowerhalf_s *stm32l4_tim2lower(int tim); /* Interrupt handling */ #ifdef HAVE_16BIT_TIMERS -static int stm32l4_interrupt(FAR struct stm32l4_lowerhalf_s *priv); -#if defined(CONFIG_STM32L4_TIM1_QE) && TIM1_BITWIDTH == 16 -static int stm32l4_tim1interrupt(int irq, FAR void *context); -#endif -#if defined(CONFIG_STM32L4_TIM2_QE) && TIM2_BITWIDTH == 16 -static int stm32l4_tim2interrupt(int irq, FAR void *context); -#endif -#if defined(CONFIG_STM32L4_TIM3_QE) && TIM3_BITWIDTH == 16 -static int stm32l4_tim3interrupt(int irq, FAR void *context); -#endif -#if defined(CONFIG_STM32L4_TIM4_QE) && TIM4_BITWIDTH == 16 -static int stm32l4_tim4interrupt(int irq, FAR void *context); -#endif -#if defined(CONFIG_STM32L4_TIM5_QE) && TIM5_BITWIDTH == 16 -static int stm32l4_tim5interrupt(int irq, FAR void *context); -#endif -#if defined(CONFIG_STM32L4_TIM8_QE) && TIM8_BITWIDTH == 16 -static int stm32l4_tim8interrupt(int irq, FAR void *context); -#endif +static int stm32l4_interrupt(int irq, FAR void *context, FAR void *arg); #endif /* Lower-half Quadrature Encoder Driver Methods */ @@ -301,9 +282,6 @@ static const struct stm32l4_qeconfig_s g_tim1config = .psc = CONFIG_STM32L4_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, -#if TIM1_BITWIDTH == 16 - .handler = stm32l4_tim1interrupt, -#endif }; static struct stm32l4_lowerhalf_s g_tim1lower = @@ -327,9 +305,6 @@ static const struct stm32l4_qeconfig_s g_tim2config = .psc = CONFIG_STM32L4_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, -#if TIM2_BITWIDTH == 16 - .handler = stm32l4_tim2interrupt, -#endif }; static struct stm32l4_lowerhalf_s g_tim2lower = @@ -353,9 +328,6 @@ static const struct stm32l4_qeconfig_s g_tim3config = .psc = CONFIG_STM32L4_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, -#if TIM3_BITWIDTH == 16 - .handler = stm32l4_tim3interrupt, -#endif }; static struct stm32l4_lowerhalf_s g_tim3lower = @@ -379,9 +351,6 @@ static const struct stm32l4_qeconfig_s g_tim4config = .psc = CONFIG_STM32L4_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, -#if TIM4_BITWIDTH == 16 - .handler = stm32l4_tim4interrupt, -#endif }; static struct stm32l4_lowerhalf_s g_tim4lower = @@ -405,9 +374,6 @@ static const struct stm32l4_qeconfig_s g_tim5config = .psc = CONFIG_STM32L4_TIM5_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, -#if TIM5_BITWIDTH == 16 - .handler = stm32l4_tim5interrupt, -#endif }; static struct stm32l4_lowerhalf_s g_tim5lower = @@ -431,9 +397,6 @@ static const struct stm32l4_qeconfig_s g_tim8config = .psc = CONFIG_STM32L4_TIM8_QEPSC, .ti1cfg = GPIO_TIM8_CH1IN, .ti2cfg = GPIO_TIM8_CH2IN, -#if TIM8_BITWIDTH == 16 - .handler = stm32l4_tim8interrupt, -#endif }; static struct stm32l4_lowerhalf_s g_tim8lower = @@ -645,10 +608,13 @@ static FAR struct stm32l4_lowerhalf_s *stm32l4_tim2lower(int tim) ************************************************************************************/ #ifdef HAVE_16BIT_TIMERS -static int stm32l4_interrupt(FAR struct stm32l4_lowerhalf_s *priv) +static int stm32l4_interrupt(int irq, FAR void *context, FAR void *arg) { + FAR struct stm32l4_lowerhalf_s *priv = (FAR struct stm32l4_lowerhalf_s *)arg; uint16_t regval; + DEBUGASSERT(priv != NULL); + /* Verify that this is an update interrupt. Nothing else is expected. */ regval = stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET); @@ -676,56 +642,6 @@ static int stm32l4_interrupt(FAR struct stm32l4_lowerhalf_s *priv) } #endif -/************************************************************************************ - * Name: stm32l4_timNinterrupt - * - * Description: - * TIMN interrupt handler - * - ************************************************************************************/ - -#if defined(CONFIG_STM32L4_TIM1_QE) && TIM1_BITWIDTH == 16 -static int stm32l4_tim1interrupt(int irq, FAR void *context) -{ - return stm32l4_interrupt(&g_tim1lower); -} -#endif - -#if defined(CONFIG_STM32L4_TIM2_QE) && TIM2_BITWIDTH == 16 -static int stm32l4_tim2interrupt(int irq, FAR void *context) -{ - return stm32l4_interrupt(&g_tim2lower); -} -#endif - -#if defined(CONFIG_STM32L4_TIM3_QE) && TIM3_BITWIDTH == 16 -static int stm32l4_tim3interrupt(int irq, FAR void *context) -{ - return stm32l4_interrupt(&g_tim3lower); -} -#endif - -#if defined(CONFIG_STM32L4_TIM4_QE) && TIM4_BITWIDTH == 16 -static int stm32l4_tim4interrupt(int irq, FAR void *context) -{ - return stm32l4_interrupt(&g_tim4lower); -} -#endif - -#if defined(CONFIG_STM32L4_TIM5_QE) && TIM5_BITWIDTH == 16 -static int stm32l4_tim5interrupt(int irq, FAR void *context) -{ - return stm32l4_interrupt(&g_tim5lower); -} -#endif - -#if defined(CONFIG_STM32L4_TIM8_QE) && TIM8_BITWIDTH == 16 -static int stm32l4_tim8interrupt(int irq, FAR void *context) -{ - return stm32l4_interrupt(&g_tim8lower); -} -#endif - /************************************************************************************ * Name: stm32l4_setup * @@ -912,7 +828,7 @@ static int stm32l4_setup(FAR struct qe_lowerhalf_s *lower) { /* Attach the interrupt handler */ - ret = irq_attach(priv->config->irq, priv->config->handler); + ret = irq_attach(priv->config->irq, stm32l4_interrupt, priv); if (ret < 0) { stm32l4_shutdown(lower); diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c index 95d2da540b4..0f55e764a0d 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.c +++ b/arch/arm/src/stm32l4/stm32l4_qspi.c @@ -281,7 +281,7 @@ static void qspi_dumpgpioconfig(const char *msg); /* Interrupts */ #ifdef STM32L4_QSPI_INTERRUPTS -static int qspi0_interrupt(int irq, void *context); +static int qspi0_interrupt(int irq, void *context, FAR void *arg); #endif @@ -1067,7 +1067,7 @@ static void qspi_ccrconfig(struct stm32l4_qspidev_s *priv, * ****************************************************************************/ -static int qspi0_interrupt(int irq, void *context) +static int qspi0_interrupt(int irq, void *context, FAR void *arg) { uint32_t status; uint32_t cr; @@ -2522,7 +2522,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) #ifdef STM32L4_QSPI_INTERRUPTS /* Attach the interrupt handler */ - ret = irq_attach(priv->irq, priv->handler); + ret = irq_attach(priv->irq, priv->handler, NULL); if (ret < 0) { spierr("ERROR: Failed to attach irq %d\n", priv->irq); diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.c b/arch/arm/src/stm32l4/stm32l4_rcc.c index 599ed7c4cc8..73abae16c5b 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rcc.c @@ -105,7 +105,7 @@ * ****************************************************************************/ -#if defined(CONFIG_STM32_PWR) && defined(CONFIG_RTC) +#if defined(CONFIG_STM32L4_PWR) && defined(CONFIG_RTC) static inline void rcc_resetbkp(void) { bool init_stat; diff --git a/arch/arm/src/stm32l4/stm32l4_rng.c b/arch/arm/src/stm32l4/stm32l4_rng.c index abd28510374..dd0f782f2d0 100644 --- a/arch/arm/src/stm32l4/stm32l4_rng.c +++ b/arch/arm/src/stm32l4/stm32l4_rng.c @@ -63,7 +63,7 @@ ****************************************************************************/ static int stm32l4_rng_initialize(void); -static int stm32l4_rnginterrupt(int irq, void *context); +static int stm32l4_rnginterrupt(int irq, void *context, FAR void *arg); static void stm32l4_rngenable(void); static void stm32l4_rngdisable(void); static ssize_t stm32l4_rngread(struct file *filep, char *buffer, size_t); @@ -117,7 +117,7 @@ static int stm32l4_rng_initialize(void) sem_init(&g_rngdev.rd_devsem, 0, 1); - if (irq_attach(STM32L4_IRQ_RNG, stm32l4_rnginterrupt)) + if (irq_attach(STM32L4_IRQ_RNG, stm32l4_rnginterrupt, NULL)) { /* We could not attach the ISR to the interrupt */ @@ -157,7 +157,7 @@ static void stm32l4_rngdisable() putreg32(regval, STM32L4_RNG_CR); } -static int stm32l4_rnginterrupt(int irq, void *context) +static int stm32l4_rnginterrupt(int irq, void *context, FAR void *arg) { uint32_t rngsr; uint32_t data; diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.h b/arch/arm/src/stm32l4/stm32l4_rtc.h index 222f5bc7c0c..404f8325ad5 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.h +++ b/arch/arm/src/stm32l4/stm32l4_rtc.h @@ -54,8 +54,8 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ -#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ +#define STM32L4_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ +#define STM32L4_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ /**************************************************************************** * Public Types @@ -146,7 +146,7 @@ bool rtc_is_inits(void); * ****************************************************************************/ -#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS int stm32l4_rtc_getdatetime_with_subseconds(FAR struct tm *tp, FAR long *nsec); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_rtcc.c b/arch/arm/src/stm32l4/stm32l4_rtcc.c index 1ee4306080f..0d2627123be 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rtcc.c @@ -512,7 +512,7 @@ static void rtc_resume(void) ************************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32l4_rtc_alarm_handler(int irq, FAR void *context) +static int stm32l4_rtc_alarm_handler(int irq, FAR void *context, FAR void *rtc_handler_arg) { FAR struct alm_cbinfo_s *cbinfo; alm_callback_t cb; @@ -801,7 +801,7 @@ static inline void rtc_enable_alarm(void) * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B). */ - stm32l4_exti_alarm(true, false, true, stm32l4_rtc_alarm_handler); + stm32l4_exti_alarm(true, false, true, stm32l4_rtc_alarm_handler, NULL); g_alarm_enabled = true; } } diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c index dfef76a9b10..62b609b972c 100644 --- a/arch/arm/src/stm32l4/stm32l4_serial.c +++ b/arch/arm/src/stm32l4/stm32l4_serial.c @@ -243,8 +243,6 @@ struct stm32l4_serial_s const unsigned int rxdma_channel; /* DMA channel assigned */ #endif - int (*const vector)(int irq, void *context); /* Interrupt handler */ - /* RX DMA state */ #ifdef SERIAL_HAVE_DMA @@ -271,7 +269,7 @@ static int stm32l4serial_setup(FAR struct uart_dev_s *dev); static void stm32l4serial_shutdown(FAR struct uart_dev_s *dev); static int stm32l4serial_attach(FAR struct uart_dev_s *dev); static void stm32l4serial_detach(FAR struct uart_dev_s *dev); -static int up_interrupt_common(FAR struct stm32l4_serial_s *dev); +static int up_interrupt((int irq, FAR void *context, FAR void *arg); static int stm32l4serial_ioctl(FAR struct file *filep, int cmd, unsigned long arg); #ifndef SERIAL_HAVE_ONLY_DMA @@ -307,22 +305,6 @@ static int stm32l4serial_pmprepare(FAR struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); #endif -#ifdef CONFIG_STM32L4_USART1 -static int up_interrupt_usart1(int irq, FAR void *context); -#endif -#ifdef CONFIG_STM32L4_USART2 -static int up_interrupt_usart2(int irq, FAR void *context); -#endif -#ifdef CONFIG_STM32L4_USART3 -static int up_interrupt_usart3(int irq, FAR void *context); -#endif -#ifdef CONFIG_STM32L4_UART4 -static int up_interrupt_uart4(int irq, FAR void *context); -#endif -#ifdef CONFIG_STM32L4_UART5 -static int up_interrupt_uart5(int irq, FAR void *context); -#endif - /**************************************************************************** * Private Variables ****************************************************************************/ @@ -460,7 +442,6 @@ static struct stm32l4_serial_s g_usart1priv = .rxdma_channel = DMAMAP_USART1_RX, .rxfifo = g_usart1rxfifo, #endif - .vector = up_interrupt_usart1, #ifdef CONFIG_USART1_RS485 .rs485_dir_gpio = GPIO_USART1_RS485_DIR, @@ -522,7 +503,6 @@ static struct stm32l4_serial_s g_usart2priv = .rxdma_channel = DMAMAP_USART2_RX, .rxfifo = g_usart2rxfifo, #endif - .vector = up_interrupt_usart2, #ifdef CONFIG_USART2_RS485 .rs485_dir_gpio = GPIO_USART2_RS485_DIR, @@ -584,7 +564,6 @@ static struct stm32l4_serial_s g_usart3priv = .rxdma_channel = DMAMAP_USART3_RX, .rxfifo = g_usart3rxfifo, #endif - .vector = up_interrupt_usart3, #ifdef CONFIG_USART3_RS485 .rs485_dir_gpio = GPIO_USART3_RS485_DIR, @@ -650,7 +629,6 @@ static struct stm32l4_serial_s g_uart4priv = .rxdma_channel = DMAMAP_UART4_RX, .rxfifo = g_uart4rxfifo, #endif - .vector = up_interrupt_uart4, #ifdef CONFIG_UART4_RS485 .rs485_dir_gpio = GPIO_UART4_RS485_DIR, @@ -716,7 +694,6 @@ static struct stm32l4_serial_s g_uart5priv = .rxdma_channel = DMAMAP_UART5_RX, .rxfifo = g_uart5rxfifo, #endif - .vector = up_interrupt_uart5, #ifdef CONFIG_UART5_RS485 .rs485_dir_gpio = GPIO_UART5_RS485_DIR, @@ -1399,7 +1376,7 @@ static int stm32l4serial_attach(FAR struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, priv->vector); + ret = irq_attach(priv->irq, up_interrupt, priv); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -1429,7 +1406,7 @@ static void stm32l4serial_detach(FAR struct uart_dev_s *dev) } /**************************************************************************** - * Name: up_interrupt_common + * Name: up_interrupt * * Description: * This is the USART interrupt handler. It will be invoked when an @@ -1440,11 +1417,14 @@ static void stm32l4serial_detach(FAR struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt_common(FAR struct stm32l4_serial_s *priv) +static int up_interrupt((int irq, FAR void *context, FAR void *arg) { + FAR struct stm32l4_serial_s *priv = (FAR struct stm32l4_serial_s *)arg; int passes; bool handled; + DEBUGASSERt(priv != NULL); + /* Report serial activity to the power management logic */ #if defined(CONFIG_PM) && CONFIG_PM_SERIAL_ACTIVITY > 0 @@ -1750,8 +1730,8 @@ static int stm32l4serial_ioctl(FAR struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); - stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); + cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } break; @@ -1762,8 +1742,8 @@ static int stm32l4serial_ioctl(FAR struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); - stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); + cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } break; @@ -2200,49 +2180,6 @@ static bool stm32l4serial_txready(FAR struct uart_dev_s *dev) return ((stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } -/**************************************************************************** - * Name: up_interrupt_u[s]art[n] - * - * Description: - * Interrupt handlers for U[S]ART[n] where n=1,..,6. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32L4_USART1 -static int up_interrupt_usart1(int irq, FAR void *context) -{ - return up_interrupt_common(&g_usart1priv); -} -#endif - -#ifdef CONFIG_STM32L4_USART2 -static int up_interrupt_usart2(int irq, FAR void *context) -{ - return up_interrupt_common(&g_usart2priv); -} -#endif - -#ifdef CONFIG_STM32L4_USART3 -static int up_interrupt_usart3(int irq, FAR void *context) -{ - return up_interrupt_common(&g_usart3priv); -} -#endif - -#ifdef CONFIG_STM32L4_UART4 -static int up_interrupt_uart4(int irq, FAR void *context) -{ - return up_interrupt_common(&g_uart4priv); -} -#endif - -#ifdef CONFIG_STM32L4_UART5 -static int up_interrupt_uart5(int irq, FAR void *context) -{ - return up_interrupt_common(&g_uart5priv); -} -#endif - /**************************************************************************** * Name: stm32l4serial_dmarxcallback * diff --git a/arch/arm/src/stm32l4/stm32l4_tim.c b/arch/arm/src/stm32l4/stm32l4_tim.c index 57440d902aa..b1194446492 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.c +++ b/arch/arm/src/stm32l4/stm32l4_tim.c @@ -1239,7 +1239,7 @@ static int stm32l4_tim_setisr(FAR struct stm32l4_tim_dev_s *dev, /* Otherwise set callback and enable interrupt */ - irq_attach(vectorno, handler); + irq_attach(vectorno, handler, NULL); up_enable_irq(vectorno); #ifdef CONFIG_ARCH_IRQPRIO diff --git a/arch/arm/src/stm32l4/stm32l4_tim.h b/arch/arm/src/stm32l4/stm32l4_tim.h index 1601f1277e6..a52f64d3544 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.h +++ b/arch/arm/src/stm32l4/stm32l4_tim.h @@ -191,7 +191,7 @@ FAR struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32l4_tim_deinit(FAR struct stm32l4_tim_dev_s * dev); +int stm32l4_tim_deinit(FAR struct stm32l4_tim_dev_s *dev); /**************************************************************************** * Name: stm32l4_timer_initialize diff --git a/arch/arm/src/stm32l4/stm32l4_timerisr.c b/arch/arm/src/stm32l4/stm32l4_timerisr.c index fff106e8525..4fdec1a6209 100644 --- a/arch/arm/src/stm32l4/stm32l4_timerisr.c +++ b/arch/arm/src/stm32l4/stm32l4_timerisr.c @@ -98,7 +98,7 @@ * ****************************************************************************/ -static int stm32l4_timerisr(int irq, uint32_t *regs) +static int stm32l4_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -148,7 +148,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(STM32L4_IRQ_SYSTICK, (xcpt_t)stm32l4_timerisr); + (void)irq_attach(STM32L4_IRQ_SYSTICK, (xcpt_t)stm32l4_timerisr, NULL); /* Enable SysTick interrupts */ diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c index e05173d82c4..335e008b182 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c @@ -275,7 +275,7 @@ static void stm32l4_dmachandisable(struct stm32l4_dma_s *dmach) * ************************************************************************************/ -static int stm32l4_dmainterrupt(int irq, void *context) +static int stm32l4_dmainterrupt(int irq, void *context, FAR void *arg) { struct stm32l4_dma_s *dmach; uint32_t isr; @@ -351,7 +351,7 @@ void weak_function up_dmainitialize(void) /* Attach DMA interrupt vectors */ - (void)irq_attach(dmach->irq, stm32l4_dmainterrupt); + (void)irq_attach(dmach->irq, stm32l4_dmainterrupt, NULL); /* Disable the DMA channel */ diff --git a/arch/arm/src/str71x/str71x_serial.c b/arch/arm/src/str71x/str71x_serial.c index fe98f543aa7..f1688ae3838 100644 --- a/arch/arm/src/str71x/str71x_serial.c +++ b/arch/arm/src/str71x/str71x_serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/str71x/str71x_serial.c * - * Copyright (C) 2008-2009, 2012-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2008-2009, 2012-2013, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -254,7 +254,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); +static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -618,7 +618,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, up_interrupt); + ret = irq_attach(priv->irq, up_interrupt, dev); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -667,47 +667,15 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt(int irq, void *context) +static int up_interrupt(int irq, void *context, void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct up_dev_s *priv; int passes; bool handled; -#ifdef CONFIG_STR71X_UART0 - if (g_uart0priv.irq == irq) - { - dev = &g_uart0port; - } - else -#endif -#ifdef CONFIG_STR71X_UART1 - if (g_uart1priv.irq == irq) - { - dev = &g_uart1port; - } - else -#endif -#ifdef CONFIG_STR71X_UART2 - if (g_uart2priv.irq == irq) - { - dev = &g_uart2port; - } - else -#endif -#ifdef CONFIG_STR71X_UART3 - if (g_uart3priv.irq == irq) - { - dev = &g_uart3port; - } - else -#endif - { - PANIC(); - } - + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct up_dev_s *)dev->priv; - DEBUGASSERT(priv && dev); /* Loop until there are no characters to be transferred or, * until we have been looping for a long time. diff --git a/arch/arm/src/str71x/str71x_timerisr.c b/arch/arm/src/str71x/str71x_timerisr.c index 553705d24cc..8fe2bda5aa5 100644 --- a/arch/arm/src/str71x/str71x_timerisr.c +++ b/arch/arm/src/str71x/str71x_timerisr.c @@ -126,7 +126,7 @@ * ****************************************************************************/ -static int str71x_timerisr(int irq, uint32_t *regs) +static int str71x_timerisr(int irq, uint32_t *regs, void *arg) { uint16_t ocar; @@ -204,7 +204,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(STR71X_IRQ_SYSTIMER, (xcpt_t)str71x_timerisr); + (void)irq_attach(STR71X_IRQ_SYSTIMER, (xcpt_t)str71x_timerisr, NULL); /* And enable the timer interrupt */ diff --git a/arch/arm/src/str71x/str71x_xti.c b/arch/arm/src/str71x/str71x_xti.c index 1bb42e656b9..386b01784bb 100644 --- a/arch/arm/src/str71x/str71x_xti.c +++ b/arch/arm/src/str71x/str71x_xti.c @@ -95,7 +95,7 @@ static const struct xtiregs_s g_xtiregs[2] = * ********************************************************************************/ -static int str71x_xtiinterrupt(int irq, FAR void *context) +static int str71x_xtiinterrupt(int irq, FAR void *context, FAR void *arg) { uint16_t enabled = (uint16_t)getreg8(STR71X_XTI_MRH) << 8 | (uint16_t)getreg8(STR71X_XTI_MRL); @@ -168,7 +168,7 @@ int str71x_xtiinitialize(void) /* Attach the XTI interrupt */ - ret = irq_attach(STR71X_IRQ_XTI, str71x_xtiinterrupt); + ret = irq_attach(STR71X_IRQ_XTI, str71x_xtiinterrupt, NULL); if (ret == OK) { /* Enable the XTI interrupt at the XTI */ diff --git a/arch/arm/src/tiva/lm3s_ethernet.c b/arch/arm/src/tiva/lm3s_ethernet.c index 020569f2937..3e0895d9f1c 100644 --- a/arch/arm/src/tiva/lm3s_ethernet.c +++ b/arch/arm/src/tiva/lm3s_ethernet.c @@ -251,7 +251,7 @@ static void tiva_receive(struct tiva_driver_s *priv); static void tiva_txdone(struct tiva_driver_s *priv); static void tiva_interrupt_work(void *arg); -static int tiva_interrupt(int irq, void *context); +static int tiva_interrupt(int irq, void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -1052,7 +1052,7 @@ static void tiva_interrupt_work(void *arg) * ****************************************************************************/ -static int tiva_interrupt(int irq, void *context) +static int tiva_interrupt(int irq, void *context, FAR void *arg) { struct tiva_driver_s *priv; uint32_t ris; @@ -1272,7 +1272,8 @@ static void tiva_poll_expiry(int argc, wdparm_t arg, ...) * cycle. */ - (void)wd_start(priv->ld_txpoll, TIVA_WDDELAY, tiva_poll_expiry, 1, arg); + (void)wd_start(priv->ld_txpoll, TIVA_WDDELAY, tiva_poll_expiry, + 1, arg); } } @@ -1425,7 +1426,8 @@ static int tiva_ifup(struct net_driver_s *dev) /* Set and activate a timer process */ - (void)wd_start(priv->ld_txpoll, TIVA_WDDELAY, tiva_poll_expiry, 1, (uint32_t)priv); + (void)wd_start(priv->ld_txpoll, TIVA_WDDELAY, tiva_poll_expiry, + 1, (uint32_t)priv); priv->ld_bifup = true; leave_critical_section(flags); @@ -1739,9 +1741,9 @@ static inline int tiva_ethinitialize(int intf) /* Attach the IRQ to the driver */ #if TIVA_NETHCONTROLLERS > 1 - ret = irq_attach(priv->irq, tiva_interrupt); + ret = irq_attach(priv->irq, tiva_interrupt, NULL); #else - ret = irq_attach(TIVA_IRQ_ETHCON, tiva_interrupt); + ret = irq_attach(TIVA_IRQ_ETHCON, tiva_interrupt, NULL); #endif if (ret != 0) { diff --git a/arch/arm/src/tiva/tiva_adclib.c b/arch/arm/src/tiva/tiva_adclib.c index 8376e51cc8b..dc2768fc163 100644 --- a/arch/arm/src/tiva/tiva_adclib.c +++ b/arch/arm/src/tiva/tiva_adclib.c @@ -414,7 +414,7 @@ void tiva_adc_irq_attach(uint8_t adc, uint8_t sse, xcpt_t isr) isr, adc, sse, irq); #endif - ret = irq_attach(irq, isr); + ret = irq_attach(irq, isr, NULL); if (ret < 0) { aerr("ERROR: Failed to attach IRQ %d: %d\n", irq, ret); diff --git a/arch/arm/src/tiva/tiva_adclow.c b/arch/arm/src/tiva/tiva_adclow.c index 6a89e62b577..46943a07baf 100644 --- a/arch/arm/src/tiva/tiva_adclow.c +++ b/arch/arm/src/tiva/tiva_adclow.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/tiva/tiva_adclow.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. * Copyright (C) 2015 TRD2 Inc. All rights reserved. * Author: Calvin Maguranis * Gregory Nutt @@ -58,12 +58,9 @@ * Included Files ****************************************************************************/ -#include -#include -#include +#include #include - #include #include #include @@ -72,6 +69,11 @@ #include #include +#include +#include +#include +#include + #include #include "up_arch.h" diff --git a/arch/arm/src/tiva/tiva_gpioirq.c b/arch/arm/src/tiva/tiva_gpioirq.c index 1023dd7bc23..f8279d6f382 100644 --- a/arch/arm/src/tiva/tiva_gpioirq.c +++ b/arch/arm/src/tiva/tiva_gpioirq.c @@ -308,7 +308,7 @@ static int tiva_gpioporthandler(uint8_t port, void *context) g_gpioportirqvector[TIVA_GPIO_IRQ_IDX(port, pin)], TIVA_GPIO_IRQ_IDX(port, pin)); - g_gpioportirqvector[TIVA_GPIO_IRQ_IDX(port, pin)](irq, context); + g_gpioportirqvector[TIVA_GPIO_IRQ_IDX(port, pin)](irq, context, NULL); } } } @@ -317,7 +317,7 @@ static int tiva_gpioporthandler(uint8_t port, void *context) } #ifdef CONFIG_TIVA_GPIOA_IRQS -static int tiva_gpioahandler(int irq, FAR void *context) +static int tiva_gpioahandler(int irq, FAR void *context, FAR void *arg) { irqstate_t flags; flags = enter_critical_section(); @@ -330,7 +330,7 @@ static int tiva_gpioahandler(int irq, FAR void *context) #endif #ifdef CONFIG_TIVA_GPIOB_IRQS -static int tiva_gpiobhandler(int irq, FAR void *context) +static int tiva_gpiobhandler(int irq, FAR void *context, FAR void *arg) { irqstate_t flags; flags = enter_critical_section(); @@ -343,7 +343,7 @@ static int tiva_gpiobhandler(int irq, FAR void *context) #endif #ifdef CONFIG_TIVA_GPIOC_IRQS -static int tiva_gpiochandler(int irq, FAR void *context) +static int tiva_gpiochandler(int irq, FAR void *context, FAR void *arg) { irqstate_t flags; flags = enter_critical_section(); @@ -356,7 +356,7 @@ static int tiva_gpiochandler(int irq, FAR void *context) #endif #ifdef CONFIG_TIVA_GPIOD_IRQS -static int tiva_gpiodhandler(int irq, FAR void *context) +static int tiva_gpiodhandler(int irq, FAR void *context, FAR void *arg) { irqstate_t flags; flags = enter_critical_section(); @@ -369,7 +369,7 @@ static int tiva_gpiodhandler(int irq, FAR void *context) #endif #ifdef CONFIG_TIVA_GPIOE_IRQS -static int tiva_gpioehandler(int irq, FAR void *context) +static int tiva_gpioehandler(int irq, FAR void *context, FAR void *arg) { irqstate_t flags; flags = enter_critical_section(); @@ -382,7 +382,7 @@ static int tiva_gpioehandler(int irq, FAR void *context) #endif #ifdef CONFIG_TIVA_GPIOF_IRQS -static int tiva_gpiofhandler(int irq, FAR void *context) +static int tiva_gpiofhandler(int irq, FAR void *context, FAR void *arg) { irqstate_t flags; flags = enter_critical_section(); @@ -395,7 +395,7 @@ static int tiva_gpiofhandler(int irq, FAR void *context) #endif #ifdef CONFIG_TIVA_GPIOG_IRQS -static int tiva_gpioghandler(int irq, FAR void *context) +static int tiva_gpioghandler(int irq, FAR void *context, FAR void *arg) { irqstate_t flags; flags = enter_critical_section(); @@ -408,7 +408,7 @@ static int tiva_gpioghandler(int irq, FAR void *context) #endif #ifdef CONFIG_TIVA_GPIOH_IRQS -static int tiva_gpiohhandler(int irq, FAR void *context) +static int tiva_gpiohhandler(int irq, FAR void *context, FAR void *arg) { irqstate_t flags; flags = enter_critical_section(); @@ -421,7 +421,7 @@ static int tiva_gpiohhandler(int irq, FAR void *context) #endif #ifdef CONFIG_TIVA_GPIOJ_IRQS -static int tiva_gpiojhandler(int irq, FAR void *context) +static int tiva_gpiojhandler(int irq, FAR void *context, FAR void *arg) { irqstate_t flags; flags = enter_critical_section(); @@ -434,7 +434,7 @@ static int tiva_gpiojhandler(int irq, FAR void *context) #endif #ifdef CONFIG_TIVA_GPIOK_IRQS -static int tiva_gpiokhandler(int irq, FAR void *context) +static int tiva_gpiokhandler(int irq, FAR void *context, FAR void *arg) { irqstate_t flags; flags = enter_critical_section(); @@ -447,7 +447,7 @@ static int tiva_gpiokhandler(int irq, FAR void *context) #endif #ifdef CONFIG_TIVA_GPIOL_IRQS -static int tiva_gpiolhandler(int irq, FAR void *context) +static int tiva_gpiolhandler(int irq, FAR void *context, FAR void *arg) { irqstate_t flags; flags = enter_critical_section(); @@ -460,7 +460,7 @@ static int tiva_gpiolhandler(int irq, FAR void *context) #endif #ifdef CONFIG_TIVA_GPIOM_IRQS -static int tiva_gpiomhandler(int irq, FAR void *context) +static int tiva_gpiomhandler(int irq, FAR void *context, FAR void *arg) { irqstate_t flags; flags = enter_critical_section(); @@ -473,7 +473,7 @@ static int tiva_gpiomhandler(int irq, FAR void *context) #endif #ifdef CONFIG_TIVA_GPION_IRQS -static int tiva_gpionhandler(int irq, FAR void *context) +static int tiva_gpionhandler(int irq, FAR void *context, FAR void *arg) { irqstate_t flags; flags = enter_critical_section(); @@ -486,7 +486,7 @@ static int tiva_gpionhandler(int irq, FAR void *context) #endif #ifdef CONFIG_TIVA_GPIOP_IRQS -static int tiva_gpiophandler(int irq, FAR void *context) +static int tiva_gpiophandler(int irq, FAR void *context, FAR void *arg) { irqstate_t flags; flags = enter_critical_section(); @@ -499,7 +499,7 @@ static int tiva_gpiophandler(int irq, FAR void *context) #endif #ifdef CONFIG_TIVA_GPIOQ_IRQS -static int tiva_gpioqhandler(int irq, FAR void *context) +static int tiva_gpioqhandler(int irq, FAR void *context, FAR void *arg) { irqstate_t flags; flags = enter_critical_section(); @@ -512,7 +512,7 @@ static int tiva_gpioqhandler(int irq, FAR void *context) #endif #ifdef CONFIG_TIVA_GPIOR_IRQS -static int tiva_gpiorhandler(int irq, FAR void *context) +static int tiva_gpiorhandler(int irq, FAR void *context, FAR void *arg) { irqstate_t flags; flags = enter_critical_section(); @@ -525,7 +525,7 @@ static int tiva_gpiorhandler(int irq, FAR void *context) #endif #ifdef CONFIG_TIVA_GPIOS_IRQS -static int tiva_gpioshandler(int irq, FAR void *context) +static int tiva_gpioshandler(int irq, FAR void *context, FAR void *arg) { irqstate_t flags; flags = enter_critical_section(); @@ -568,87 +568,87 @@ int tiva_gpioirqinitialize(void) */ #ifdef CONFIG_TIVA_GPIOA_IRQS - irq_attach(TIVA_IRQ_GPIOA, tiva_gpioahandler); + irq_attach(TIVA_IRQ_GPIOA, tiva_gpioahandler, NULL); up_enable_irq(TIVA_IRQ_GPIOA); #endif #ifdef CONFIG_TIVA_GPIOB_IRQS - irq_attach(TIVA_IRQ_GPIOB, tiva_gpiobhandler); + irq_attach(TIVA_IRQ_GPIOB, tiva_gpiobhandler, NULL); up_enable_irq(TIVA_IRQ_GPIOB); #endif #ifdef CONFIG_TIVA_GPIOC_IRQS - irq_attach(TIVA_IRQ_GPIOC, tiva_gpiochandler); + irq_attach(TIVA_IRQ_GPIOC, tiva_gpiochandler, NULL); up_enable_irq(TIVA_IRQ_GPIOC); #endif #ifdef CONFIG_TIVA_GPIOD_IRQS - irq_attach(TIVA_IRQ_GPIOD, tiva_gpiodhandler); + irq_attach(TIVA_IRQ_GPIOD, tiva_gpiodhandler, NULL); up_enable_irq(TIVA_IRQ_GPIOD); #endif #ifdef CONFIG_TIVA_GPIOE_IRQS - irq_attach(TIVA_IRQ_GPIOE, tiva_gpioehandler); + irq_attach(TIVA_IRQ_GPIOE, tiva_gpioehandler, NULL); up_enable_irq(TIVA_IRQ_GPIOE); #endif #ifdef CONFIG_TIVA_GPIOF_IRQS - irq_attach(TIVA_IRQ_GPIOF, tiva_gpiofhandler); + irq_attach(TIVA_IRQ_GPIOF, tiva_gpiofhandler, NULL); up_enable_irq(TIVA_IRQ_GPIOF); #endif #ifdef CONFIG_TIVA_GPIOG_IRQS - irq_attach(TIVA_IRQ_GPIOG, tiva_gpioghandler); + irq_attach(TIVA_IRQ_GPIOG, tiva_gpioghandler, NULL); up_enable_irq(TIVA_IRQ_GPIOG); #endif #ifdef CONFIG_TIVA_GPIOH_IRQS - irq_attach(TIVA_IRQ_GPIOH, tiva_gpiohhandler); + irq_attach(TIVA_IRQ_GPIOH, tiva_gpiohhandler, NULL); up_enable_irq(TIVA_IRQ_GPIOH); #endif #ifdef CONFIG_TIVA_GPIOJ_IRQS - irq_attach(TIVA_IRQ_GPIOJ, tiva_gpiojhandler); + irq_attach(TIVA_IRQ_GPIOJ, tiva_gpiojhandler, NULL); up_enable_irq(TIVA_IRQ_GPIOJ); #endif #ifdef CONFIG_TIVA_GPIOK_IRQS - irq_attach(TIVA_IRQ_GPIOK, tiva_gpiokhandler); + irq_attach(TIVA_IRQ_GPIOK, tiva_gpiokhandler, NULL); up_enable_irq(TIVA_IRQ_GPIOK); #endif #ifdef CONFIG_TIVA_GPIOL_IRQS - irq_attach(TIVA_IRQ_GPIOL, tiva_gpiolhandler); + irq_attach(TIVA_IRQ_GPIOL, tiva_gpiolhandler, NULL); up_enable_irq(TIVA_IRQ_GPIOL); #endif #ifdef CONFIG_TIVA_GPIOM_IRQS - irq_attach(TIVA_IRQ_GPIOM, tiva_gpiomhandler); + irq_attach(TIVA_IRQ_GPIOM, tiva_gpiomhandler, NULL); up_enable_irq(TIVA_IRQ_GPIOM); #endif #ifdef CONFIG_TIVA_GPION_IRQS - irq_attach(TIVA_IRQ_GPION, tiva_gpionhandler); + irq_attach(TIVA_IRQ_GPION, tiva_gpionhandler, NULL); up_enable_irq(TIVA_IRQ_GPION); #endif #ifdef CONFIG_TIVA_GPIOP_IRQS - irq_attach(TIVA_IRQ_GPIOP, tiva_gpiophandler); + irq_attach(TIVA_IRQ_GPIOP, tiva_gpiophandler, NULL); up_enable_irq(TIVA_IRQ_GPIOP); #endif #ifdef CONFIG_TIVA_GPIOQ_IRQS - irq_attach(TIVA_IRQ_GPIOQ, tiva_gpioqhandler); + irq_attach(TIVA_IRQ_GPIOQ, tiva_gpioqhandler, NULL); up_enable_irq(TIVA_IRQ_GPIOQ); #endif #ifdef CONFIG_TIVA_GPIOR_IRQS - irq_attach(TIVA_IRQ_GPIOR, tiva_gpiorhandler); + irq_attach(TIVA_IRQ_GPIOR, tiva_gpiorhandler, NULL); up_enable_irq(TIVA_IRQ_GPIOR); #endif #ifdef CONFIG_TIVA_GPIOS_IRQS - irq_attach(TIVA_IRQ_GPIOS, tiva_gpioshandler); + irq_attach(TIVA_IRQ_GPIOS, tiva_gpioshandler, NULL); up_enable_irq(TIVA_IRQ_GPIOS); #endif @@ -742,11 +742,11 @@ void tiva_gpioportirqattach(uint8_t port, xcpt_t isr) if (isr == NULL) { tiva_gpioirqdisable(port, 0xff); - irq_attach(irq, irq_unexpected_isr); + irq_attach(irq, irq_unexpected_isr, NULL); } else { - irq_attach(irq, isr); + irq_attach(irq, isr, NULL); tiva_gpioirqenable(port, 0xff); } diff --git a/arch/arm/src/tiva/tiva_i2c.c b/arch/arm/src/tiva/tiva_i2c.c index 13b9c7b5adf..558a72554ca 100644 --- a/arch/arm/src/tiva/tiva_i2c.c +++ b/arch/arm/src/tiva/tiva_i2c.c @@ -195,7 +195,7 @@ struct tiva_i2c_config_s uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ #ifndef CONFIG_I2C_POLLED - int (*isr)(int, void *); /* Interrupt handler */ + int (*isr)(int, void *, void *); /* Interrupt handler */ uint8_t irq; /* IRQ number */ #endif uint8_t devno; /* I2Cn where n = devno */ @@ -286,34 +286,34 @@ static int tiva_i2c_interrupt(struct tiva_i2c_priv_s * priv, uint32_t status); #ifndef CONFIG_I2C_POLLED #ifdef CONFIG_TIVA_I2C0 -static int tiva_i2c0_interrupt(int irq, void *context); +static int tiva_i2c0_interrupt(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_TIVA_I2C1 -static int tiva_i2c1_interrupt(int irq, void *context); +static int tiva_i2c1_interrupt(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_TIVA_I2C2 -static int tiva_i2c2_interrupt(int irq, void *context); +static int tiva_i2c2_interrupt(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_TIVA_I2C3 -static int tiva_i2c3_interrupt(int irq, void *context); +static int tiva_i2c3_interrupt(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_TIVA_I2C4 -static int tiva_i2c4_interrupt(int irq, void *context); +static int tiva_i2c4_interrupt(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_TIVA_I2C5 -static int tiva_i2c5_interrupt(int irq, void *context); +static int tiva_i2c5_interrupt(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_TIVA_I2C6 -static int tiva_i2c6_interrupt(int irq, void *context); +static int tiva_i2c6_interrupt(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_TIVA_I2C7 -static int tiva_i2c7_interrupt(int irq, void *context); +static int tiva_i2c7_interrupt(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_TIVA_I2C8 -static int tiva_i2c8_interrupt(int irq, void *context); +static int tiva_i2c8_interrupt(int irq, void *context, FAR void *arg); #endif #ifdef CONFIG_TIVA_I2C9 -static int tiva_i2c9_interrupt(int irq, void *context); +static int tiva_i2c9_interrupt(int irq, void *context, FAR void *arg); #endif #endif /* !CONFIG_I2C_POLLED */ @@ -1419,7 +1419,7 @@ static int tiva_i2c_interrupt(struct tiva_i2c_priv_s *priv, uint32_t status) ************************************************************************************/ #if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C0) -static int tiva_i2c0_interrupt(int irq, void *context) +static int tiva_i2c0_interrupt(int irq, void *context, void *arg) { struct tiva_i2c_priv_s *priv; uint32_t status; @@ -1444,7 +1444,7 @@ static int tiva_i2c0_interrupt(int irq, void *context) ************************************************************************************/ #if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C1) -static int tiva_i2c1_interrupt(int irq, void *context) +static int tiva_i2c1_interrupt(int irq, void *context, FAR void *arg) { struct tiva_i2c_priv_s *priv; uint32_t status; @@ -1469,7 +1469,7 @@ static int tiva_i2c1_interrupt(int irq, void *context) ************************************************************************************/ #if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C2) -static int tiva_i2c2_interrupt(int irq, void *context) +static int tiva_i2c2_interrupt(int irq, void *context, FAR void *arg) { struct tiva_i2c_priv_s *priv; uint32_t status; @@ -1494,7 +1494,7 @@ static int tiva_i2c2_interrupt(int irq, void *context) ************************************************************************************/ #if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C3) -static int tiva_i2c3_interrupt(int irq, void *context) +static int tiva_i2c3_interrupt(int irq, void *context, FAR void *arg) { struct tiva_i2c_priv_s *priv; uint32_t status; @@ -1519,7 +1519,7 @@ static int tiva_i2c3_interrupt(int irq, void *context) ************************************************************************************/ #if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C4) -static int tiva_i2c4_interrupt(int irq, void *context) +static int tiva_i2c4_interrupt(int irq, void *context, FAR void *arg) { struct tiva_i2c_priv_s *priv; uint32_t status; @@ -1544,7 +1544,7 @@ static int tiva_i2c4_interrupt(int irq, void *context) ************************************************************************************/ #if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C5) -static int tiva_i2c5_interrupt(int irq, void *context) +static int tiva_i2c5_interrupt(int irq, void *context, FAR void *arg) { struct tiva_i2c_priv_s *priv; uint32_t status; @@ -1569,7 +1569,7 @@ static int tiva_i2c5_interrupt(int irq, void *context) ************************************************************************************/ #if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C6) -static int tiva_i2c6_interrupt(int irq, void *context) +static int tiva_i2c6_interrupt(int irq, void *context, FAR void *arg) { struct tiva_i2c_priv_s *priv; uint32_t status; @@ -1594,7 +1594,7 @@ static int tiva_i2c6_interrupt(int irq, void *context) ************************************************************************************/ #if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C7) -static int tiva_i2c7_interrupt(int irq, void *context) +static int tiva_i2c7_interrupt(int irq, void *context, FAR void *arg) { struct tiva_i2c_priv_s *priv; uint32_t status; @@ -1619,7 +1619,7 @@ static int tiva_i2c7_interrupt(int irq, void *context) ************************************************************************************/ #if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C8) -static int tiva_i2c8_interrupt(int irq, void *context) +static int tiva_i2c8_interrupt(int irq, void *context, FAR void *arg) { struct tiva_i2c_priv_s *priv; uint32_t status; @@ -1644,7 +1644,7 @@ static int tiva_i2c8_interrupt(int irq, void *context) ************************************************************************************/ #if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C9) -static int tiva_i2c9_interrupt(int irq, void *context) +static int tiva_i2c9_interrupt(int irq, void *context, FAR void *arg) { struct tiva_i2c_priv_s *priv; uint32_t status; @@ -1758,7 +1758,7 @@ static int tiva_i2c_initialize(struct tiva_i2c_priv_s *priv, uint32_t frequency) */ #ifndef CONFIG_I2C_POLLED - (void)irq_attach(config->irq, config->isr); + (void)irq_attach(config->irq, config->isr, NULL); up_enable_irq(config->irq); #endif diff --git a/arch/arm/src/tiva/tiva_irq.c b/arch/arm/src/tiva/tiva_irq.c index 6771007d59e..9099c54a2e9 100644 --- a/arch/arm/src/tiva/tiva_irq.c +++ b/arch/arm/src/tiva/tiva_irq.c @@ -196,7 +196,7 @@ static void tiva_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int tiva_nmi(int irq, FAR void *context) +static int tiva_nmi(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -204,7 +204,7 @@ static int tiva_nmi(int irq, FAR void *context) return 0; } -static int tiva_busfault(int irq, FAR void *context) +static int tiva_busfault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Bus fault recived\n"); @@ -212,7 +212,7 @@ static int tiva_busfault(int irq, FAR void *context) return 0; } -static int tiva_usagefault(int irq, FAR void *context) +static int tiva_usagefault(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Usage fault received\n"); @@ -220,7 +220,7 @@ static int tiva_usagefault(int irq, FAR void *context) return 0; } -static int tiva_pendsv(int irq, FAR void *context) +static int tiva_pendsv(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -228,7 +228,7 @@ static int tiva_pendsv(int irq, FAR void *context) return 0; } -static int tiva_dbgmonitor(int irq, FAR void *context) +static int tiva_dbgmonitor(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -236,7 +236,7 @@ static int tiva_dbgmonitor(int irq, FAR void *context) return 0; } -static int tiva_reserved(int irq, FAR void *context) +static int tiva_reserved(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -451,8 +451,8 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(TIVA_IRQ_SVCALL, up_svcall); - irq_attach(TIVA_IRQ_HARDFAULT, up_hardfault); + irq_attach(TIVA_IRQ_SVCALL, up_svcall, NULL); + irq_attach(TIVA_IRQ_HARDFAULT, up_hardfault, NULL); /* Set the priority of the SVCall interrupt */ @@ -468,22 +468,22 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(TIVA_IRQ_MEMFAULT, up_memfault); + irq_attach(TIVA_IRQ_MEMFAULT, up_memfault, NULL); up_enable_irq(TIVA_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(TIVA_IRQ_NMI, tiva_nmi); + irq_attach(TIVA_IRQ_NMI, tiva_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(TIVA_IRQ_MEMFAULT, up_memfault); + irq_attach(TIVA_IRQ_MEMFAULT, up_memfault, NULL); #endif - irq_attach(TIVA_IRQ_BUSFAULT, tiva_busfault); - irq_attach(TIVA_IRQ_USAGEFAULT, tiva_usagefault); - irq_attach(TIVA_IRQ_PENDSV, tiva_pendsv); - irq_attach(TIVA_IRQ_DBGMONITOR, tiva_dbgmonitor); - irq_attach(TIVA_IRQ_RESERVED, tiva_reserved); + irq_attach(TIVA_IRQ_BUSFAULT, tiva_busfault, NULL); + irq_attach(TIVA_IRQ_USAGEFAULT, tiva_usagefault, NULL); + irq_attach(TIVA_IRQ_PENDSV, tiva_pendsv, NULL); + irq_attach(TIVA_IRQ_DBGMONITOR, tiva_dbgmonitor, NULL); + irq_attach(TIVA_IRQ_RESERVED, tiva_reserved, NULL); #endif tiva_dumpnvic("initial", NR_IRQS); diff --git a/arch/arm/src/tiva/tiva_pwm.c b/arch/arm/src/tiva/tiva_pwm.c index 73b86349b33..0e882f0f7c1 100644 --- a/arch/arm/src/tiva/tiva_pwm.c +++ b/arch/arm/src/tiva/tiva_pwm.c @@ -99,19 +99,19 @@ struct tiva_pwm_chan_s ************************************************************************************/ #if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_TIVA_PWM0_CHAN0) -static int tiva_pwm_gen0_interrupt(int irq, FAR void *context); +static int tiva_pwm_gen0_interrupt(int irq, FAR void *context, FAR void *arg); #endif #if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_TIVA_PWM0_CHAN2) -static int tiva_pwm_gen1_interrupt(int irq, FAR void *context); +static int tiva_pwm_gen1_interrupt(int irq, FAR void *context, FAR void *arg); #endif #if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_TIVA_PWM0_CHAN4) -static int tiva_pwm_gen2_interrupt(int irq, FAR void *context); +static int tiva_pwm_gen2_interrupt(int irq, FAR void *context, FAR void *arg); #endif #if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_TIVA_PWM0_CHAN6) -static int tiva_pwm_gen3_interrupt(int irq, FAR void *context); +static int tiva_pwm_gen3_interrupt(int irq, FAR void *context, FAR void *arg); #endif #if defined(CONFIG_PWM_PULSECOUNT) && \ @@ -321,28 +321,28 @@ static struct tiva_pwm_chan_s g_pwm_chan7 = ************************************************************************************/ #if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_TIVA_PWM0_CHAN0) -static int tiva_pwm_gen0_interrupt(int irq, FAR void *context) +static int tiva_pwm_gen0_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_pwm_interrupt(&g_pwm_chan0); } #endif #if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_TIVA_PWM0_CHAN2) -static int tiva_pwm_gen1_interrupt(int irq, FAR void *context) +static int tiva_pwm_gen1_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_pwm_interrupt(&g_pwm_chan2); } #endif #if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_TIVA_PWM0_CHAN4) -static int tiva_pwm_gen2_interrupt(int irq, FAR void *context) +static int tiva_pwm_gen2_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_pwm_interrupt(&g_pwm_chan4); } #endif #if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_TIVA_PWM0_CHAN6) -static int tiva_pwm_gen3_interrupt(int irq, FAR void *context) +static int tiva_pwm_gen3_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_pwm_interrupt(&g_pwm_chan6); } @@ -832,28 +832,28 @@ FAR struct pwm_lowerhalf_s *tiva_pwm_initialize(int channel) { #ifdef CONFIG_TIVA_PWM0_CHAN0 case 0: - irq_attach(chan->irq, tiva_pwm_gen0_interrupt); + irq_attach(chan->irq, tiva_pwm_gen0_interrupt, NULL); up_enable_irq(chan->irq); break; #endif #ifdef CONFIG_TIVA_PWM0_CHAN2 case 2: - irq_attach(chan->irq, tiva_pwm_gen1_interrupt); + irq_attach(chan->irq, tiva_pwm_gen1_interrupt, NULL); up_enable_irq(chan->irq); break; #endif #ifdef CONFIG_TIVA_PWM0_CHAN4 case 4: - irq_attach(chan->irq, tiva_pwm_gen2_interrupt); + irq_attach(chan->irq, tiva_pwm_gen2_interrupt, NULL); up_enable_irq(chan->irq); break; #endif #ifdef CONFIG_TIVA_PWM0_CHAN6 case 6: - irq_attach(chan->irq, tiva_pwm_gen3_interrupt); + irq_attach(chan->irq, tiva_pwm_gen3_interrupt, NULL); up_enable_irq(chan->irq); break; #endif diff --git a/arch/arm/src/tiva/tiva_qencoder.h b/arch/arm/src/tiva/tiva_qencoder.h index 8714f77105e..828eaba3522 100644 --- a/arch/arm/src/tiva/tiva_qencoder.h +++ b/arch/arm/src/tiva/tiva_qencoder.h @@ -46,9 +46,9 @@ * Pre-processor Definitions ************************************************************************************/ -#define QEIOC_DIRECTION _QEIOC(QEIOC_USER) -#define QEIOC_VELOCITY _QEIOC(QEIOC_USER+1) -#define QEIOC_PPR _QEIOC(QEIOC_USER+2) +#define QEIOC_DIRECTION _QEIOC(QE_TIVA_FIRST) +#define QEIOC_VELOCITY _QEIOC(QE_TIVA_FIRST+1) +#define QEIOC_PPR _QEIOC(QE_TIVA_FIRST+2) /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/tiva/tiva_serial.c b/arch/arm/src/tiva/tiva_serial.c index fb80e9f3263..da2aedf70f4 100644 --- a/arch/arm/src/tiva/tiva_serial.c +++ b/arch/arm/src/tiva/tiva_serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/tiva/tiva_serial.c * - * Copyright (C) 2009-2010, 2012-2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010, 2012-2014, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -322,7 +322,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); +static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -903,7 +903,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, up_interrupt); + ret = irq_attach(priv->irq, up_interrupt, dev); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -946,74 +946,15 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt(int irq, void *context) +static int up_interrupt(int irq, void *context, void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct up_dev_s *priv; uint32_t mis; int passes; bool handled; -#ifdef CONFIG_TIVA_UART0 - if (g_uart0priv.irq == irq) - { - dev = &g_uart0port; - } - else -#endif -#ifdef CONFIG_TIVA_UART1 - if (g_uart1priv.irq == irq) - { - dev = &g_uart1port; - } - else -#endif -#ifdef CONFIG_TIVA_UART2 - if (g_uart2priv.irq == irq) - { - dev = &g_uart2port; - } - else -#endif -#ifdef CONFIG_TIVA_UART3 - if (g_uart3priv.irq == irq) - { - dev = &g_uart3port; - } - else -#endif -#ifdef CONFIG_TIVA_UART4 - if (g_uart4priv.irq == irq) - { - dev = &g_uart4port; - } - else -#endif -#ifdef CONFIG_TIVA_UART5 - if (g_uart5priv.irq == irq) - { - dev = &g_uart5port; - } - else -#endif -#ifdef CONFIG_TIVA_UART6 - if (g_uart6priv.irq == irq) - { - dev = &g_uart6port; - } - else -#endif -#ifdef CONFIG_TIVA_UART7 - if (g_uart7priv.irq == irq) - { - dev = &g_uart7port; - } - else -#endif - { - PANIC(); - } - + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct up_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, diff --git a/arch/arm/src/tiva/tiva_ssi.c b/arch/arm/src/tiva/tiva_ssi.c index 6c2a92fbcc0..709850e01a8 100644 --- a/arch/arm/src/tiva/tiva_ssi.c +++ b/arch/arm/src/tiva/tiva_ssi.c @@ -267,7 +267,7 @@ static int ssi_transfer(struct tiva_ssidev_s *priv, const void *txbuffer, #ifndef CONFIG_SSI_POLLWAIT static inline struct tiva_ssidev_s *ssi_mapirq(int irq); -static int ssi_interrupt(int irq, void *context); +static int ssi_interrupt(int irq, void *context, FAR void *arg); #endif /* SPI methods */ @@ -1004,7 +1004,7 @@ static inline struct tiva_ssidev_s *ssi_mapirq(int irq) ****************************************************************************/ #ifndef CONFIG_SSI_POLLWAIT -static int ssi_interrupt(int irq, void *context) +static int ssi_interrupt(int irq, void *context, FAR void *arg) { struct tiva_ssidev_s *priv = ssi_mapirq(irq); uint32_t regval; @@ -1682,9 +1682,9 @@ FAR struct spi_dev_s *tiva_ssibus_initialize(int port) #ifndef CONFIG_SSI_POLLWAIT #if NSSI_ENABLED > 1 - irq_attach(priv->irq, (xcpt_t)ssi_interrupt); + irq_attach(priv->irq, (xcpt_t)ssi_interrupt, NULL); #else - irq_attach(SSI_IRQ, (xcpt_t)ssi_interrupt); + irq_attach(SSI_IRQ, (xcpt_t)ssi_interrupt, NULL); #endif #endif /* CONFIG_SSI_POLLWAIT */ diff --git a/arch/arm/src/tiva/tiva_timerisr.c b/arch/arm/src/tiva/tiva_timerisr.c index 41b8f0e4eda..62a90f49025 100644 --- a/arch/arm/src/tiva/tiva_timerisr.c +++ b/arch/arm/src/tiva/tiva_timerisr.c @@ -88,7 +88,7 @@ * ****************************************************************************/ -static int tiva_timerisr(int irq, uint32_t *regs) +static int tiva_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -126,7 +126,7 @@ void arm_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(TIVA_IRQ_SYSTICK, (xcpt_t)tiva_timerisr); + (void)irq_attach(TIVA_IRQ_SYSTICK, (xcpt_t)tiva_timerisr, NULL); /* Enable SysTick interrupts */ diff --git a/arch/arm/src/tiva/tiva_timerlib.c b/arch/arm/src/tiva/tiva_timerlib.c index f04dd260268..e2d8bcd0b4a 100644 --- a/arch/arm/src/tiva/tiva_timerlib.c +++ b/arch/arm/src/tiva/tiva_timerlib.c @@ -126,28 +126,28 @@ static void tiva_putreg(struct tiva_gptmstate_s *priv, unsigned int offset, #ifdef CONFIG_TIVA_TIMER_32BIT static int tiva_timer32_interrupt(struct tiva_gptmstate_s *priv); # ifdef CONFIG_TIVA_TIMER0 -static int tiva_gptm0_interrupt(int irq, FAR void *context); +static int tiva_gptm0_interrupt(int irq, FAR void *context, FAR void *arg); # endif # ifdef CONFIG_TIVA_TIMER1 -static int tiva_gptm1_interrupt(int irq, FAR void *context); +static int tiva_gptm1_interrupt(int irq, FAR void *context, FAR void *arg); # endif # ifdef CONFIG_TIVA_TIMER2 -static int tiva_gptm2_interrupt(int irq, FAR void *context); +static int tiva_gptm2_interrupt(int irq, FAR void *context, FAR void *arg); # endif # ifdef CONFIG_TIVA_TIMER3 -static int tiva_gptm3_interrupt(int irq, FAR void *context); +static int tiva_gptm3_interrupt(int irq, FAR void *context, FAR void *arg); # endif # ifdef CONFIG_TIVA_TIMER4 -static int tiva_gptm4_interrupt(int irq, FAR void *context); +static int tiva_gptm4_interrupt(int irq, FAR void *context, FAR void *arg); # endif # ifdef CONFIG_TIVA_TIMER5 -static int tiva_gptm5_interrupt(int irq, FAR void *context); +static int tiva_gptm5_interrupt(int irq, FAR void *context, FAR void *arg); # endif # ifdef CONFIG_TIVA_TIMER6 -static int tiva_gptm6_interrupt(int irq, FAR void *context); +static int tiva_gptm6_interrupt(int irq, FAR void *context, FAR void *arg); # endif # ifdef CONFIG_TIVA_TIMER7 -static int tiva_gptm7_interrupt(int irq, FAR void *context); +static int tiva_gptm7_interrupt(int irq, FAR void *context, FAR void *arg); #endif #endif /* CONFIG_TIVA_TIMER_32BIT */ @@ -155,36 +155,36 @@ static int tiva_gptm7_interrupt(int irq, FAR void *context); static int tiva_timer16_interrupt(struct tiva_gptmstate_s *priv, int tmndx); #ifdef CONFIG_TIVA_TIMER0 -static int tiva_timer0a_interrupt(int irq, FAR void *context); -static int tiva_timer0b_interrupt(int irq, FAR void *context); +static int tiva_timer0a_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_timer0b_interrupt(int irq, FAR void *context, FAR void *arg); #endif #ifdef CONFIG_TIVA_TIMER1 -static int tiva_timer1a_interrupt(int irq, FAR void *context); -static int tiva_timer1b_interrupt(int irq, FAR void *context); +static int tiva_timer1a_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_timer1b_interrupt(int irq, FAR void *context, FAR void *arg); #endif #ifdef CONFIG_TIVA_TIMER2 -static int tiva_timer2a_interrupt(int irq, FAR void *context); -static int tiva_timer2b_interrupt(int irq, FAR void *context); +static int tiva_timer2a_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_timer2b_interrupt(int irq, FAR void *context, FAR void *arg); #endif #ifdef CONFIG_TIVA_TIMER3 -static int tiva_timer3a_interrupt(int irq, FAR void *context); -static int tiva_timer3b_interrupt(int irq, FAR void *context); +static int tiva_timer3a_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_timer3b_interrupt(int irq, FAR void *context, FAR void *arg); #endif #ifdef CONFIG_TIVA_TIMER4 -static int tiva_timer4a_interrupt(int irq, FAR void *context); -static int tiva_timer4b_interrupt(int irq, FAR void *context); +static int tiva_timer4a_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_timer4b_interrupt(int irq, FAR void *context, FAR void *arg); #endif #ifdef CONFIG_TIVA_TIMER5 -static int tiva_timer5a_interrupt(int irq, FAR void *context); -static int tiva_timer5b_interrupt(int irq, FAR void *context); +static int tiva_timer5a_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_timer5b_interrupt(int irq, FAR void *context, FAR void *arg); #endif #ifdef CONFIG_TIVA_TIMER6 -static int tiva_timer6a_interrupt(int irq, FAR void *context); -static int tiva_timer6b_interrupt(int irq, FAR void *context); +static int tiva_timer6a_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_timer6b_interrupt(int irq, FAR void *context, FAR void *arg); #endif #ifdef CONFIG_TIVA_TIMER7 -static int tiva_timer7a_interrupt(int irq, FAR void *context); -static int tiva_timer7b_interrupt(int irq, FAR void *context); +static int tiva_timer7a_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_timer7b_interrupt(int irq, FAR void *context, FAR void *arg); #endif #endif /* CONFIG_TIVA_TIMER_16BIT */ @@ -557,56 +557,56 @@ static int tiva_timer32_interrupt(struct tiva_gptmstate_s *priv) #ifdef CONFIG_TIVA_TIMER_32BIT #ifdef CONFIG_TIVA_TIMER0 -static int tiva_gptm0_interrupt(int irq, FAR void *context) +static int tiva_gptm0_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer32_interrupt(&g_gptm0_state); } #endif #ifdef CONFIG_TIVA_TIMER1 -static int tiva_gptm1_interrupt(int irq, FAR void *context) +static int tiva_gptm1_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer32_interrupt(&g_gptm1_state); } #endif #ifdef CONFIG_TIVA_TIMER2 -static int tiva_gptm2_interrupt(int irq, FAR void *context) +static int tiva_gptm2_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer32_interrupt(&g_gptm2_state); } #endif #ifdef CONFIG_TIVA_TIMER3 -static int tiva_gptm3_interrupt(int irq, FAR void *context) +static int tiva_gptm3_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer32_interrupt(&g_gptm3_state); } #endif #ifdef CONFIG_TIVA_TIMER4 -static int tiva_gptm4_interrupt(int irq, FAR void *context) +static int tiva_gptm4_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer32_interrupt(&g_gptm4_state); } #endif #ifdef CONFIG_TIVA_TIMER5 -static int tiva_gptm5_interrupt(int irq, FAR void *context) +static int tiva_gptm5_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer32_interrupt(&g_gptm5_state); } #endif #ifdef CONFIG_TIVA_TIMER6 -static int tiva_gptm6_interrupt(int irq, FAR void *context) +static int tiva_gptm6_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer32_interrupt(&g_gptm6_state); } #endif #ifdef CONFIG_TIVA_TIMER7 -static int tiva_gptm7_interrupt(int irq, FAR void *context) +static int tiva_gptm7_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer32_interrupt(&g_gptm7_state); } @@ -683,96 +683,96 @@ static int tiva_timer16_interrupt(struct tiva_gptmstate_s *priv, int tmndx) #ifdef CONFIG_TIVA_TIMER_16BIT #ifdef CONFIG_TIVA_TIMER0 -static int tiva_timer0a_interrupt(int irq, FAR void *context) +static int tiva_timer0a_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer16_interrupt(&g_gptm0_state, TIMER16A); } -static int tiva_timer0b_interrupt(int irq, FAR void *context) +static int tiva_timer0b_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer16_interrupt(&g_gptm0_state, TIMER16B); } #endif #ifdef CONFIG_TIVA_TIMER1 -static int tiva_timer1a_interrupt(int irq, FAR void *context) +static int tiva_timer1a_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer16_interrupt(&g_gptm1_state, TIMER16A); } -static int tiva_timer1b_interrupt(int irq, FAR void *context) +static int tiva_timer1b_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer16_interrupt(&g_gptm1_state, TIMER16B); } #endif #ifdef CONFIG_TIVA_TIMER2 -static int tiva_timer2a_interrupt(int irq, FAR void *context) +static int tiva_timer2a_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer16_interrupt(&g_gptm2_state, TIMER16A); } -static int tiva_timer2b_interrupt(int irq, FAR void *context) +static int tiva_timer2b_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer16_interrupt(&g_gptm2_state, TIMER16B); } #endif #ifdef CONFIG_TIVA_TIMER3 -static int tiva_timer3a_interrupt(int irq, FAR void *context) +static int tiva_timer3a_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer16_interrupt(&g_gptm3_state, TIMER16A); } -static int tiva_timer3b_interrupt(int irq, FAR void *context) +static int tiva_timer3b_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer16_interrupt(&g_gptm3_state, TIMER16B); } #endif #ifdef CONFIG_TIVA_TIMER4 -static int tiva_timer4a_interrupt(int irq, FAR void *context) +static int tiva_timer4a_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer16_interrupt(&g_gptm4_state, TIMER16A); } -static int tiva_timer4b_interrupt(int irq, FAR void *context) +static int tiva_timer4b_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer16_interrupt(&g_gptm4_state, TIMER16B); } #endif #ifdef CONFIG_TIVA_TIMER5 -static int tiva_timer5a_interrupt(int irq, FAR void *context) +static int tiva_timer5a_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer16_interrupt(&g_gptm5_state, TIMER16A); } -static int tiva_timer5b_interrupt(int irq, FAR void *context) +static int tiva_timer5b_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer16_interrupt(&g_gptm5_state, TIMER16B); } #endif #ifdef CONFIG_TIVA_TIMER6 -static int tiva_timer6a_interrupt(int irq, FAR void *context) +static int tiva_timer6a_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer16_interrupt(&g_gptm6_state, TIMER16A); } -static int tiva_timer6b_interrupt(int irq, FAR void *context) +static int tiva_timer6b_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer16_interrupt(&g_gptm6_state, TIMER16B); } #endif #ifdef CONFIG_TIVA_TIMER7 -static int tiva_timer7a_interrupt(int irq, FAR void *context) +static int tiva_timer7a_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer16_interrupt(&g_gptm7_state, TIMER16A); } -static int tiva_timer7b_interrupt(int irq, FAR void *context) +static int tiva_timer7b_interrupt(int irq, FAR void *context, FAR void *arg) { return tiva_timer16_interrupt(&g_gptm7_state, TIMER16B); } @@ -1803,7 +1803,7 @@ TIMER_HANDLE tiva_gptm_configure(const struct tiva_gptmconfig_s *config) * the interrupt). */ - ret = irq_attach(attr->irq[TIMER32], attr->handler32); + ret = irq_attach(attr->irq[TIMER32], attr->handler32, NULL); if (ret == OK) { /* Configure the 32-bit timer */ @@ -1824,10 +1824,10 @@ TIMER_HANDLE tiva_gptm_configure(const struct tiva_gptmconfig_s *config) * the interrupts). */ - ret = irq_attach(attr->irq[TIMER16A], attr->handler16[TIMER16A]); + ret = irq_attach(attr->irq[TIMER16A], attr->handler16[TIMER16A], NULL); if (ret == OK) { - ret = irq_attach(attr->irq[TIMER16B], attr->handler16[TIMER16B]); + ret = irq_attach(attr->irq[TIMER16B], attr->handler16[TIMER16B], NULL); } if (ret == OK) diff --git a/arch/arm/src/tiva/tm4c_ethernet.c b/arch/arm/src/tiva/tm4c_ethernet.c index a04854879d6..f689028a9a3 100644 --- a/arch/arm/src/tiva/tm4c_ethernet.c +++ b/arch/arm/src/tiva/tm4c_ethernet.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/tiva/tm4c_ethernet.c * - * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2014-2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -704,7 +704,7 @@ static void tiva_freeframe(FAR struct tiva_ethmac_s *priv); static void tiva_txdone(FAR struct tiva_ethmac_s *priv); static void tiva_interrupt_work(FAR void *arg); -static int tiva_interrupt(int irq, FAR void *context); +static int tiva_interrupt(int irq, FAR void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -1955,17 +1955,32 @@ static void tiva_txdone(FAR struct tiva_ethmac_s *priv) if (priv->inflight <= 0) { + int delay; + /* Cancel the TX timeout */ wd_cancel(priv->txtimeout); - /* Then make sure that the TX poll timer is running (if it is already - * running, the following would restart it). This is necessary to - * avoid certain race conditions where the polling sequence can be - * interrupted. + /* Check if the poll timer is running. If it is not, then start it + * now. There is a race condition here: We may test the time + * remaining on the poll timer and determine that it is still running, + * but then the timer expires immiately. That should not be problem, + * however, the poll timer processing should be in the work queue and + * should execute immediately after we complete the TX poll. + * Inefficient, but not fatal. */ - (void)wd_start(priv->txpoll, TIVA_WDDELAY, tiva_poll_expiry, 1, (uint32_t)priv); + delay = wd_gettime(priv->txpoll); + if (delay <= 0) + { + /* The poll timer is not running .. restart it. This is necessary + * to avoid certain race conditions where the polling sequence can + * be interrupted. + */ + + (void)wd_start(priv->txpoll, TIVA_WDDELAY, tiva_poll_expiry, + 1, (uint32_t)priv); + } /* And disable further TX interrupts. */ @@ -2101,7 +2116,7 @@ static void tiva_interrupt_work(FAR void *arg) * ****************************************************************************/ -static int tiva_interrupt(int irq, FAR void *context) +static int tiva_interrupt(int irq, FAR void *context, FAR void *arg) { FAR struct tiva_ethmac_s *priv = &g_tiva_ethmac[0]; uint32_t dmaris; @@ -2152,7 +2167,7 @@ static int tiva_interrupt(int irq, FAR void *context) if (priv->handler) { - (void)priv->handler(irq, context); + (void)priv->handler(irq, context, arg); } } #endif @@ -2306,7 +2321,8 @@ static void tiva_poll_work(FAR void *arg) /* Setup the watchdog poll timer again */ - (void)wd_start(priv->txpoll, TIVA_WDDELAY, tiva_poll_expiry, 1, (uint32_t)priv); + (void)wd_start(priv->txpoll, TIVA_WDDELAY, tiva_poll_expiry, + 1, (uint32_t)priv); net_unlock(); } @@ -2348,7 +2364,8 @@ static void tiva_poll_expiry(int argc, uint32_t arg, ...) * cycle. */ - (void)wd_start(priv->txpoll, TIVA_WDDELAY, tiva_poll_expiry, 1, (uint32_t)priv); + (void)wd_start(priv->txpoll, TIVA_WDDELAY, tiva_poll_expiry, + 1, (uint32_t)priv); } } @@ -2396,7 +2413,8 @@ static int tiva_ifup(struct net_driver_s *dev) /* Set and activate a timer process */ - (void)wd_start(priv->txpoll, TIVA_WDDELAY, tiva_poll_expiry, 1, (uint32_t)priv); + (void)wd_start(priv->txpoll, TIVA_WDDELAY, tiva_poll_expiry, + 1, (uint32_t)priv); /* Enable the Ethernet interrupt */ @@ -4116,7 +4134,7 @@ int tiva_ethinitialize(int intf) /* Attach the IRQ to the driver */ - if (irq_attach(TIVA_IRQ_ETHCON, tiva_interrupt)) + if (irq_attach(TIVA_IRQ_ETHCON, tiva_interrupt, NULL)) { /* We could not attach the ISR to the interrupt */ diff --git a/arch/arm/src/tms570/tms570_esm.c b/arch/arm/src/tms570/tms570_esm.c index 2019fac5065..dfecf47e8a7 100644 --- a/arch/arm/src/tms570/tms570_esm.c +++ b/arch/arm/src/tms570/tms570_esm.c @@ -145,7 +145,7 @@ int tms570_esm_initialize(void) * ****************************************************************************/ -int tms570_esm_interrupt(int irq, void *context) +int tms570_esm_interrupt(int irq, void *context, FAR void *arg) { /* Save the saved processor context in CURRENT_REGS where it can be accessed * for register dumps and possibly context switching. diff --git a/arch/arm/src/tms570/tms570_esm.h b/arch/arm/src/tms570/tms570_esm.h index 7222cc17fed..a1c93059a8e 100644 --- a/arch/arm/src/tms570/tms570_esm.h +++ b/arch/arm/src/tms570/tms570_esm.h @@ -79,7 +79,7 @@ int tms570_esm_initialize(void); * ****************************************************************************/ -int tms570_esm_interrupt(int irq, void *context); +int tms570_esm_interrupt(int irq, void *context, FAR void *arg); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/tms570/tms570_gioirq.c b/arch/arm/src/tms570/tms570_gioirq.c index 6eca48e6293..b4b5cf327b2 100644 --- a/arch/arm/src/tms570/tms570_gioirq.c +++ b/arch/arm/src/tms570/tms570_gioirq.c @@ -70,7 +70,7 @@ * ****************************************************************************/ -static int tms3570_gio_interrupt(int irq, void *context) +static int tms3570_gio_interrupt(int irq, void *context, FAR void *arg) { uint32_t off1; int irq2; @@ -113,7 +113,7 @@ void tms570_gioirq_initialize(void) /* Attach and enable the GIO level 0 interrupt */ - DEBUGVERIFY(irq_attach(TMS570_REQ_GIO_0, tms3570_gio_interrupt)); + DEBUGVERIFY(irq_attach(TMS570_REQ_GIO_0, tms3570_gio_interrupt, NULL)); up_enable_irq(TMS570_REQ_GIO_0); } diff --git a/arch/arm/src/tms570/tms570_irq.c b/arch/arm/src/tms570/tms570_irq.c index da9f8c5656f..99032611997 100644 --- a/arch/arm/src/tms570/tms570_irq.c +++ b/arch/arm/src/tms570/tms570_irq.c @@ -185,8 +185,8 @@ void up_irqinitialize(void) * an NMI. */ - (void)irq_attach(TMS570_REQ_ESMHIGH, tms570_esm_interrupt); - (void)irq_attach(TMS570_REQ_ESMLO, tms570_esm_interrupt); + (void)irq_attach(TMS570_REQ_ESMHIGH, tms570_esm_interrupt, NULL); + (void)irq_attach(TMS570_REQ_ESMLO, tms570_esm_interrupt, NULL); up_enable_irq(TMS570_REQ_ESMHIGH); up_enable_irq(TMS570_REQ_ESMLO); diff --git a/arch/arm/src/tms570/tms570_serial.c b/arch/arm/src/tms570/tms570_serial.c index b52755ac3ec..8bb84ed91fd 100644 --- a/arch/arm/src/tms570/tms570_serial.c +++ b/arch/arm/src/tms570/tms570_serial.c @@ -132,7 +132,6 @@ struct tms570_dev_s { const uint32_t scibase; /* Base address of SCI registers */ struct sci_config_s config; /* SCI configuration */ - xcpt_t handler; /* Interrupt handler */ uint8_t irq; /* IRQ associated with this SCI */ }; @@ -144,13 +143,7 @@ static int tms570_setup(struct uart_dev_s *dev); static void tms570_shutdown(struct uart_dev_s *dev); static int tms570_attach(struct uart_dev_s *dev); static void tms570_detach(struct uart_dev_s *dev); -static int tms570_interrupt(struct uart_dev_s *dev); -#ifdef CONFIG_TMS570_SCI1 -static int tms570_sci1_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_TMS570_SCI2 -static int tms570_sci2_interrupt(int irq, void *context); -#endif +static int tms570_interrupt(int irq, void *context, FAR void *arg); static int tms570_ioctl(struct file *filep, int cmd, unsigned long arg); static int tms570_receive(struct uart_dev_s *dev, uint32_t *status); static void tms570_rxint(struct uart_dev_s *dev, bool enable); @@ -207,7 +200,6 @@ static struct tms570_dev_s g_sci1priv = .bits = CONFIG_SCI1_BITS, .stopbits2 = CONFIG_SCI1_2STOP, }, - .handler = tms570_sci1_interrupt, .irq = TMS570_REQ_SCI1_0, }; @@ -241,7 +233,6 @@ static struct tms570_dev_s g_sci2priv = .bits = CONFIG_SCI2_BITS, .stopbits2 = CONFIG_SCI2_2STOP, }, - .handler = tms570_sci2_interrupt, .irq = TMS570_REQ_SCI2_0, }; @@ -387,7 +378,7 @@ static int tms570_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, priv->handler); + ret = irq_attach(priv->irq, tms570_interrupt, dev); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -428,10 +419,11 @@ static void tms570_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int tms570_interrupt(struct uart_dev_s *dev) +static int tms570_interrupt(int irq, void *context, FAR void *arg) { + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct tms570_dev_s *priv; - uint32_t intvec; + uint32_t intvec; DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct tms570_dev_s *)dev->priv; @@ -514,27 +506,6 @@ static int tms570_interrupt(struct uart_dev_s *dev) return OK; } -/**************************************************************************** - * Name: tms570_sci[n]_interrupt - * - * Description: - * SCI interrupt handlers - * - ****************************************************************************/ - -#ifdef CONFIG_TMS570_SCI1 -static int tms570_sci1_interrupt(int irq, void *context) -{ - return tms570_interrupt(&g_sci1port); -} -#endif -#ifdef CONFIG_TMS570_SCI2 -static int tms570_sci2_interrupt(int irq, void *context) -{ - return tms570_interrupt(&g_sci2port); -} -#endif - /**************************************************************************** * Name: tms570_ioctl * diff --git a/arch/arm/src/tms570/tms570_timerisr.c b/arch/arm/src/tms570/tms570_timerisr.c index 88337914524..3dba2a1eae0 100644 --- a/arch/arm/src/tms570/tms570_timerisr.c +++ b/arch/arm/src/tms570/tms570_timerisr.c @@ -130,7 +130,7 @@ * ****************************************************************************/ -static int tms570_timerisr(int irq, uint32_t *regs) +static int tms570_timerisr(int irq, uint32_t *regs, void *arg) { /* Cleear the RTI Compare 0 interrupts */ @@ -194,7 +194,7 @@ void arm_timer_initialize(void) /* Attach the interrupt handler to the RTI Compare 0 interrupt */ - DEBUGVERIFY(irq_attach(TMS570_REQ_RTICMP0, (xcpt_t)tms570_timerisr)); + DEBUGVERIFY(irq_attach(TMS570_REQ_RTICMP0, (xcpt_t)tms570_timerisr), NULL); /* Enable RTI compare 0 interrupts at the VIM */ diff --git a/arch/avr/src/at32uc3/at32uc3_gpioirq.c b/arch/avr/src/at32uc3/at32uc3_gpioirq.c index 171fa39f1f2..f525edd4451 100644 --- a/arch/avr/src/at32uc3/at32uc3_gpioirq.c +++ b/arch/avr/src/at32uc3/at32uc3_gpioirq.c @@ -262,7 +262,7 @@ static void gpio_porthandler(uint32_t regbase, int irqbase, uint32_t irqset, voi ****************************************************************************/ #if CONFIG_AVR32_GPIOIRQSETA != 0 -static int gpio0_interrupt(int irq, FAR void *context) +static int gpio0_interrupt(int irq, FAR void *context, FAR void *arg) { gpio_porthandler(AVR32_GPIO0_BASE, __IRQ_GPIO_PA0, CONFIG_AVR32_GPIOIRQSETA, context); @@ -271,7 +271,7 @@ static int gpio0_interrupt(int irq, FAR void *context) #endif #if CONFIG_AVR32_GPIOIRQSETB != 0 -static int gpio1_interrupt(int irq, FAR void *context) +static int gpio1_interrupt(int irq, FAR void *context, FAR void *arg) { gpio_porthandler(AVR32_GPIO1_BASE, __IRQ_GPIO_PB0, CONFIG_AVR32_GPIOIRQSETB, context); @@ -310,10 +310,10 @@ void gpio_irqinitialize(void) /* Then attach the GPIO interrupt handlers */ #if CONFIG_AVR32_GPIOIRQSETA != 0 - irq_attach(AVR32_IRQ_GPIO0, gpio0_interrupt); + irq_attach(AVR32_IRQ_GPIO0, gpio0_interrupt, NULL); #endif #if CONFIG_AVR32_GPIOIRQSETB != 0 - irq_attach(AVR32_IRQ_GPIO1, gpio1_interrupt); + irq_attach(AVR32_IRQ_GPIO1, gpio1_interrupt, NULL); #endif } diff --git a/arch/avr/src/at32uc3/at32uc3_irq.c b/arch/avr/src/at32uc3/at32uc3_irq.c index 4474f9e5c18..179430640cc 100644 --- a/arch/avr/src/at32uc3/at32uc3_irq.c +++ b/arch/avr/src/at32uc3/at32uc3_irq.c @@ -174,7 +174,7 @@ static int up_getgrp(unsigned int irq) * ****************************************************************************/ -static int avr32_xcptn(int irq, FAR void *context) +static int avr32_xcptn(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _alert("PANIC!!! Exception IRQ: %d\n", irq); @@ -223,7 +223,7 @@ void up_irqinitialize(void) for (irq = 0; irq < AVR32_IRQ_NEVENTS; irq++) { - irq_attach(irq, avr32_xcptn); + irq_attach(irq, avr32_xcptn, NULL); } /* Initialize GPIO interrupt facilities */ diff --git a/arch/avr/src/at32uc3/at32uc3_serial.c b/arch/avr/src/at32uc3/at32uc3_serial.c index f01dcc6ac7b..db10ae31c4d 100644 --- a/arch/avr/src/at32uc3/at32uc3_serial.c +++ b/arch/avr/src/at32uc3/at32uc3_serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/avr/src/at32uc3/at32uc3_serial.c * - * Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2010, 2012, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -160,7 +160,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); +static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -408,7 +408,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach the IRQ */ - return irq_attach(priv->irq, up_interrupt); + return irq_attach(priv->irq, up_interrupt, dev); } /**************************************************************************** @@ -440,40 +440,16 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt(int irq, void *context) +static int up_interrupt(int irq, void *context, void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct up_dev_s *priv; uint32_t csr; int passes; bool handled; -#ifdef CONFIG_AVR32_USART0_RS232 - if (g_usart0priv.irq == irq) - { - dev = &g_usart0port; - } - else -#endif -#ifdef CONFIG_AVR32_USART1_RS232 - if (g_usart1priv.irq == irq) - { - dev = &g_usart1port; - } - else -#endif -#ifdef CONFIG_AVR32_USART2_RS232 - if (g_usart2priv.irq == irq) - { - dev = &g_usart2port; - } - else -#endif - { - PANIC(); - } + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct up_dev_s *)dev->priv; - DEBUGASSERT(priv); /* Loop until there are no characters to be transferred or, * until we have been looping for a long time. diff --git a/arch/avr/src/at32uc3/at32uc3_timerisr.c b/arch/avr/src/at32uc3/at32uc3_timerisr.c index 79118a15d82..c1cb5ec48fb 100644 --- a/arch/avr/src/at32uc3/at32uc3_timerisr.c +++ b/arch/avr/src/at32uc3/at32uc3_timerisr.c @@ -157,7 +157,7 @@ static void rtc_waitnotbusy(void) * ****************************************************************************/ -static int at32uc3_timerisr(int irq, uint32_t *regs) +static int at32uc3_timerisr(int irq, uint32_t *regs, void *arg) { /* Clear the pending timer interrupt */ @@ -219,7 +219,7 @@ void avr_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(AVR32_IRQ_RTC, (xcpt_t)at32uc3_timerisr); + (void)irq_attach(AVR32_IRQ_RTC, (xcpt_t)at32uc3_timerisr, NULL); /* Enable RTC interrupts */ diff --git a/arch/avr/src/at90usb/at90usb_serial.c b/arch/avr/src/at90usb/at90usb_serial.c index 25077f57431..385211f97e8 100644 --- a/arch/avr/src/at90usb/at90usb_serial.c +++ b/arch/avr/src/at90usb/at90usb_serial.c @@ -90,8 +90,8 @@ static int usart1_setup(struct uart_dev_s *dev); static void usart1_shutdown(struct uart_dev_s *dev); static int usart1_attach(struct uart_dev_s *dev); static void usart1_detach(struct uart_dev_s *dev); -static int usart1_rxinterrupt(int irq, void *context); -static int usart1_txinterrupt(int irq, void *context); +static int usart1_rxinterrupt(int irq, void *context, FAR void *arg); +static int usart1_txinterrupt(int irq, void *context, FAR void *arg); static int usart1_ioctl(struct file *filep, int cmd, unsigned long arg); static int usart1_receive(struct uart_dev_s *dev, FAR unsigned int *status); static void usart1_rxint(struct uart_dev_s *dev, bool enable); @@ -245,9 +245,9 @@ static int usart1_attach(struct uart_dev_s *dev) * written. */ - (void)irq_attach(AT90USB_IRQ_U1RX, usart1_rxinterrupt); - (void)irq_attach(AT90USB_IRQ_U1DRE, usart1_txinterrupt); -//(void)irq_attach(AT90USB_IRQ_U1TX, usart1_txinterrupt); + (void)irq_attach(AT90USB_IRQ_U1RX, usart1_rxinterrupt, NULL); + (void)irq_attach(AT90USB_IRQ_U1DRE, usart1_txinterrupt, NULL); +//(void)irq_attach(AT90USB_IRQ_U1TX, usart1_txinterrupt, NULL); return OK; } @@ -284,7 +284,7 @@ static void usart1_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int usart1_rxinterrupt(int irq, void *context) +static int usart1_rxinterrupt(int irq, void *context, FAR void *arg) { uint8_t ucsr1a = UCSR1A; @@ -310,7 +310,7 @@ static int usart1_rxinterrupt(int irq, void *context) * ****************************************************************************/ -static int usart1_txinterrupt(int irq, void *context) +static int usart1_txinterrupt(int irq, void *context, FAR void *arg) { uint8_t ucsr1a = UCSR1A; diff --git a/arch/avr/src/at90usb/at90usb_timerisr.c b/arch/avr/src/at90usb/at90usb_timerisr.c index a2c6a089f1d..896fe111b55 100644 --- a/arch/avr/src/at90usb/at90usb_timerisr.c +++ b/arch/avr/src/at90usb/at90usb_timerisr.c @@ -114,7 +114,7 @@ * ****************************************************************************/ -static int at90usb_timerisr(int irq, uint32_t *regs) +static int at90usb_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -168,7 +168,7 @@ void avr_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(AT90USB_IRQ_T1COMPA, (xcpt_t)at90usb_timerisr); + (void)irq_attach(AT90USB_IRQ_T1COMPA, (xcpt_t)at90usb_timerisr, NULL); /* Enable the interrupt on compare match A */ diff --git a/arch/avr/src/at90usb/at90usb_usbdev.c b/arch/avr/src/at90usb/at90usb_usbdev.c index 333037d2158..2d47dd75447 100644 --- a/arch/avr/src/at90usb/at90usb_usbdev.c +++ b/arch/avr/src/at90usb/at90usb_usbdev.c @@ -295,7 +295,7 @@ static void avr_dispatchrequest(FAR const struct usb_ctrlreq_s *ctrl); static int avr_ep0configure(void); static void avr_setaddress(uint8_t address); static void avr_ep0setup(void); -static int avr_epinterrupt(int irq, FAR void *context); +static int avr_epinterrupt(int irq, FAR void *context, FAR void *arg); /* General interrupt handling **************************************************/ @@ -305,7 +305,7 @@ static void avr_genvbus(void); static inline void avr_gensuspend(void); static void avr_genwakeup(void); static inline void avr_geneor(void); -static int avr_geninterrupt(int irq, FAR void *context); +static int avr_geninterrupt(int irq, FAR void *context, FAR void *arg); /* USB device controller operations ********************************************/ @@ -1877,7 +1877,7 @@ static inline void avr_epNinterrupt(void) * ****************************************************************************/ -static int avr_epinterrupt(int irq, FAR void *context) +static int avr_epinterrupt(int irq, FAR void *context, FAR void *arg) { usbtrace(TRACE_INTENTRY(AVR_TRACEINTID_EPINT), irq); @@ -2061,7 +2061,7 @@ static inline void avr_geneor(void) * ****************************************************************************/ -static int avr_geninterrupt(int irq, FAR void *context) +static int avr_geninterrupt(int irq, FAR void *context, FAR void *arg) { usbtrace(TRACE_INTENTRY(AVR_TRACEINTID_GENINT), irq); @@ -2783,7 +2783,7 @@ void up_usbinitialize(void) /* Attach USB controller general interrupt handler */ - if (irq_attach(AT90USB_IRQ_USBGEN, avr_geninterrupt) != 0) + if (irq_attach(AT90USB_IRQ_USBGEN, avr_geninterrupt, NULL) != 0) { usbtrace(TRACE_DEVERROR(AVR_TRACEERR_IRQREGISTRATION), AT90USB_IRQ_USBGEN); goto errout; @@ -2791,7 +2791,7 @@ void up_usbinitialize(void) /* Attach USB controller endpoint/pipe interrupt handler */ - if (irq_attach(AT90USB_IRQ_USBEP, avr_epinterrupt) != 0) + if (irq_attach(AT90USB_IRQ_USBEP, avr_epinterrupt, NULL) != 0) { usbtrace(TRACE_DEVERROR(AVR_TRACEERR_IRQREGISTRATION), AT90USB_IRQ_USBEP); goto errout; diff --git a/arch/avr/src/atmega/atmega_serial.c b/arch/avr/src/atmega/atmega_serial.c index 9f770363a1d..7c49fab1c13 100644 --- a/arch/avr/src/atmega/atmega_serial.c +++ b/arch/avr/src/atmega/atmega_serial.c @@ -114,8 +114,8 @@ static int usart0_setup(struct uart_dev_s *dev); static void usart0_shutdown(struct uart_dev_s *dev); static int usart0_attach(struct uart_dev_s *dev); static void usart0_detach(struct uart_dev_s *dev); -static int usart0_rxinterrupt(int irq, void *context); -static int usart0_txinterrupt(int irq, void *context); +static int usart0_rxinterrupt(int irq, void *context, FAR void *arg); +static int usart0_txinterrupt(int irq, void *context, FAR void *arg); static int usart0_ioctl(struct file *filep, int cmd, unsigned long arg); static int usart0_receive(struct uart_dev_s *dev, FAR unsigned int *status); static void usart0_rxint(struct uart_dev_s *dev, bool enable); @@ -131,8 +131,8 @@ static int usart1_setup(struct uart_dev_s *dev); static void usart1_shutdown(struct uart_dev_s *dev); static int usart1_attach(struct uart_dev_s *dev); static void usart1_detach(struct uart_dev_s *dev); -static int usart1_rxinterrupt(int irq, void *context); -static int usart1_txinterrupt(int irq, void *context); +static int usart1_rxinterrupt(int irq, void *context, FAR void *arg); +static int usart1_txinterrupt(int irq, void *context, FAR void *arg); static int usart1_ioctl(struct file *filep, int cmd, unsigned long arg); static int usart1_receive(struct uart_dev_s *dev, FAR unsigned int *status); static void usart1_rxint(struct uart_dev_s *dev, bool enable); @@ -388,9 +388,9 @@ static int usart0_attach(struct uart_dev_s *dev) * written. */ - (void)irq_attach(ATMEGA_IRQ_U0RX, usart0_rxinterrupt); - (void)irq_attach(ATMEGA_IRQ_U0DRE, usart0_txinterrupt); -//(void)irq_attach(ATMEGA_IRQ_U0TX, usart0_txinterrupt); + (void)irq_attach(ATMEGA_IRQ_U0RX, usart0_rxinterrupt, NULL); + (void)irq_attach(ATMEGA_IRQ_U0DRE, usart0_txinterrupt, NULL); +//(void)irq_attach(ATMEGA_IRQ_U0TX, usart0_txinterrupt, NULL); return OK; } #endif @@ -410,9 +410,9 @@ static int usart1_attach(struct uart_dev_s *dev) * written. */ - (void)irq_attach(ATMEGA_IRQ_U1RX, usart1_rxinterrupt); - (void)irq_attach(ATMEGA_IRQ_U1DRE, usart1_txinterrupt); -//(void)irq_attach(ATMEGA_IRQ_U1TX, usart1_txinterrupt); + (void)irq_attach(ATMEGA_IRQ_U1RX, usart1_rxinterrupt, NULL); + (void)irq_attach(ATMEGA_IRQ_U1DRE, usart1_txinterrupt, NULL); +//(void)irq_attach(ATMEGA_IRQ_U1TX, usart1_txinterrupt, NULL); return OK; } #endif @@ -468,7 +468,7 @@ static void usart1_detach(struct uart_dev_s *dev) ****************************************************************************/ #ifdef CONFIG_AVR_USART0 -static int usart0_rxinterrupt(int irq, void *context) +static int usart0_rxinterrupt(int irq, void *context, FAR void *arg) { uint8_t ucsr0a = UCSR0A; @@ -486,7 +486,7 @@ static int usart0_rxinterrupt(int irq, void *context) #endif #ifdef CONFIG_AVR_USART1 -static int usart1_rxinterrupt(int irq, void *context) +static int usart1_rxinterrupt(int irq, void *context, FAR void *arg) { uint8_t ucsr1a = UCSR1A; @@ -514,7 +514,7 @@ static int usart1_rxinterrupt(int irq, void *context) ****************************************************************************/ #ifdef CONFIG_AVR_USART0 -static int usart0_txinterrupt(int irq, void *context) +static int usart0_txinterrupt(int irq, void *context, FAR void *arg) { uint8_t ucsr0a = UCSR0A; @@ -534,7 +534,7 @@ static int usart0_txinterrupt(int irq, void *context) #endif #ifdef CONFIG_AVR_USART1 -static int usart1_txinterrupt(int irq, void *context) +static int usart1_txinterrupt(int irq, void *context, FAR void *arg) { uint8_t ucsr1a = UCSR1A; diff --git a/arch/avr/src/atmega/atmega_timerisr.c b/arch/avr/src/atmega/atmega_timerisr.c index ead918e7c3f..41e38ae51b6 100644 --- a/arch/avr/src/atmega/atmega_timerisr.c +++ b/arch/avr/src/atmega/atmega_timerisr.c @@ -114,7 +114,7 @@ * ****************************************************************************/ -static int atmega_timerisr(int irq, uint32_t *regs) +static int atmega_timerisr(int irq, uint32_t *regs, FAR void *arg) { /* Process timer interrupt */ @@ -169,9 +169,9 @@ void avr_timer_initialize(void) /* Attach the timer interrupt vector */ #if defined(ATMEGA_IRQ_T1COMPA) - (void)irq_attach(ATMEGA_IRQ_T1COMPA, (xcpt_t)atmega_timerisr); + (void)irq_attach(ATMEGA_IRQ_T1COMPA, (xcpt_t)atmega_timerisr, NULL); #elif defined(ATMEGA_IRQ_TIM1_COMPA) - (void)irq_attach(ATMEGA_IRQ_TIM1_COMPA, (xcpt_t)atmega_timerisr); + (void)irq_attach(ATMEGA_IRQ_TIM1_COMPA, (xcpt_t)atmega_timerisr, NULL); #else # error "Unable to find IRQ for timer" #endif diff --git a/arch/hc/src/m9s12/m9s12_ethernet.c b/arch/hc/src/m9s12/m9s12_ethernet.c index 3a85446e6dc..2a2673ed5f8 100644 --- a/arch/hc/src/m9s12/m9s12_ethernet.c +++ b/arch/hc/src/m9s12/m9s12_ethernet.c @@ -127,7 +127,7 @@ static int emac_txpoll(struct net_driver_s *dev); static void emac_receive(FAR struct emac_driver_s *priv); static void emac_txdone(FAR struct emac_driver_s *priv); -static int emac_interrupt(int irq, FAR void *context); +static int emac_interrupt(int irq, FAR void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -442,7 +442,7 @@ static void emac_txdone(FAR struct emac_driver_s *priv) * ****************************************************************************/ -static int emac_interrupt(int irq, FAR void *context) +static int emac_interrupt(int irq, FAR void *context, FAR void *arg) { register FAR struct emac_driver_s *priv = &g_emac[0]; @@ -752,7 +752,7 @@ int emac_initialize(int intf) /* Attach the IRQ to the driver */ - if (irq_attach(CONFIG_HCS12_IRQ, emac_interrupt)) + if (irq_attach(CONFIG_HCS12_IRQ, emac_interrupt, NULL)) { /* We could not attach the ISR to the interrupt */ diff --git a/arch/hc/src/m9s12/m9s12_gpioirq.c b/arch/hc/src/m9s12/m9s12_gpioirq.c index b0f72d77622..e8e5f697830 100644 --- a/arch/hc/src/m9s12/m9s12_gpioirq.c +++ b/arch/hc/src/m9s12/m9s12_gpioirq.c @@ -181,7 +181,7 @@ static int hcs12_interrupt(uint16_t base, int irq0, uint8_t valid, void *context } #ifdef CONFIG_HCS12_PORTG_INTS -static int hcs12_pginterrupt(int irq, void *context) +static int hcs12_pginterrupt(int irq, void *context, FAR void *arg) { return hcs12_interrupt(HCS12_PIM_PORTG_BASE, HCS12_IRQ_PG0, HCS12_IRQ_PGSET, context); @@ -189,7 +189,7 @@ static int hcs12_pginterrupt(int irq, void *context) #endif #ifdef CONFIG_HCS12_PORTH_INTS -static int hcs12_phinterrupt(int irq, void *context) +static int hcs12_phinterrupt(int irq, void *context, FAR void *arg) { return hcs12_interrupt(HCS12_PIM_PORTH_BASE, HCS12_IRQ_PH0, HCS12_IRQ_PHSET, context); @@ -197,7 +197,7 @@ static int hcs12_phinterrupt(int irq, void *context) #endif #ifdef CONFIG_HCS12_PORTJ_INTS -static int hcs12_pjinterrupt(int irq, void *context) +static int hcs12_pjinterrupt(int irq, void *context, FAR void *arg) { return hcs12_interrupt(HCS12_PIM_PORTJ_BASE, HCS12_IRQ_PJ0, HCS12_IRQ_PJSET, context); @@ -230,13 +230,13 @@ void hcs12_gpioirqinitialize(void) #ifdef CONFIG_HCS12_GPIOIRQ # ifdef CONFIG_HCS12_PORTG_INTS - irq_attach(HCS12_IRQ_VPORTG, hcs12_pginterrupt); + irq_attach(HCS12_IRQ_VPORTG, hcs12_pginterrupt, NULL); # endif # ifdef CONFIG_HCS12_PORTH_INTS - irq_attach(HCS12_IRQ_VPORTH, hcs12_phinterrupt); + irq_attach(HCS12_IRQ_VPORTH, hcs12_phinterrupt, NULL); # endif # ifdef CONFIG_HCS12_PORTJ_INTS - irq_attach(HCS12_IRQ_VPORTJ, hcs12_pjinterrupt); + irq_attach(HCS12_IRQ_VPORTJ, hcs12_pjinterrupt, NULL); # endif #endif /* CONFIG_HCS12_GPIOIRQ */ } diff --git a/arch/hc/src/m9s12/m9s12_serial.c b/arch/hc/src/m9s12/m9s12_serial.c index 1bc0091395b..a6524534bda 100644 --- a/arch/hc/src/m9s12/m9s12_serial.c +++ b/arch/hc/src/m9s12/m9s12_serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/hc/src/m9s12/m9s12_serial.c * - * Copyright (C) 2009, 2011-2012, 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2011-2012, 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -123,7 +123,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); +static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -422,7 +422,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, up_interrupt); + ret = irq_attach(priv->irq, up_interrupt, dev); if (ret == OK) { /* Enable the Rx interrupt (the TX interrupt is still disabled @@ -465,30 +465,14 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt(int irq, void *context) +static int up_interrupt(int irq, void *context, void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct up_dev_s *priv; int passes; bool handled; -#ifndef CONFIG_SCI0_DISABLE - if (g_sci0priv.irq == irq) - { - dev = &g_sci0port; - } - else -#endif -#ifndef CONFIG_SCI1_DISABLE - if (g_sci1priv.irq == irq) - { - dev = &g_sci1port; - } - else -#endif - { - PANIC(); - } + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct up_dev_s*)dev->priv; /* Loop until there are no characters to be transferred or, diff --git a/arch/hc/src/m9s12/m9s12_timerisr.c b/arch/hc/src/m9s12/m9s12_timerisr.c index eef0613ded3..f8d570b66d7 100644 --- a/arch/hc/src/m9s12/m9s12_timerisr.c +++ b/arch/hc/src/m9s12/m9s12_timerisr.c @@ -131,7 +131,7 @@ * ****************************************************************************/ -static int m9s12_timerisr(int irq, uint32_t *regs) +static int m9s12_timerisr(int irq, uint32_t *regs, void *arg) { /* Clear real time interrupt flag */ @@ -171,7 +171,7 @@ void hc_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(HCS12_IRQ_VRTI, (xcpt_t)m9s12_timerisr); + (void)irq_attach(HCS12_IRQ_VRTI, (xcpt_t)m9s12_timerisr, NULL); /* Enable RTI interrupt by setting the RTIE bit */ diff --git a/arch/mips/src/common/up_internal.h b/arch/mips/src/common/up_internal.h index 4dc2b54907a..39ba820682e 100644 --- a/arch/mips/src/common/up_internal.h +++ b/arch/mips/src/common/up_internal.h @@ -220,7 +220,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs); /* Software interrupt 0 handler */ -int up_swint0(int irq, FAR void *context); +int up_swint0(int irq, FAR void *context, FAR void *arg); /* Signals */ diff --git a/arch/mips/src/mips32/up_swint0.c b/arch/mips/src/mips32/up_swint0.c index 95638c8c087..40cc800592c 100644 --- a/arch/mips/src/mips32/up_swint0.c +++ b/arch/mips/src/mips32/up_swint0.c @@ -129,7 +129,7 @@ static void dispatch_syscall(void) * ****************************************************************************/ -int up_swint0(int irq, FAR void *context) +int up_swint0(int irq, FAR void *context, FAR void *arg) { uint32_t *regs = (uint32_t *)context; uint32_t cause; diff --git a/arch/mips/src/pic32mx/pic32mx-ethernet.c b/arch/mips/src/pic32mx/pic32mx-ethernet.c index 3515635f220..acd5b7d44d4 100644 --- a/arch/mips/src/pic32mx/pic32mx-ethernet.c +++ b/arch/mips/src/pic32mx/pic32mx-ethernet.c @@ -395,7 +395,7 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv); static void pic32mx_txdone(struct pic32mx_driver_s *priv); static void pic32mx_interrupt_work(void *arg); -static int pic32mx_interrupt(int irq, void *context); +static int pic32mx_interrupt(int irq, void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -1853,7 +1853,7 @@ static void pic32mx_interrupt_work(void *arg) * ****************************************************************************/ -static int pic32mx_interrupt(int irq, void *context) +static int pic32mx_interrupt(int irq, void *context, FAR void *arg) { struct pic32mx_driver_s *priv; uint32_t status; @@ -3388,9 +3388,9 @@ static inline int pic32mx_ethinitialize(int intf) /* Attach the IRQ to the driver */ #if CONFIG_PIC32MX_NINTERFACES > 1 - ret = irq_attach(priv->pd_irq, pic32mx_interrupt); + ret = irq_attach(priv->pd_irq, pic32mx_interrupt, NULL); #else - ret = irq_attach(PIC32MX_IRQ_ETH, pic32mx_interrupt); + ret = irq_attach(PIC32MX_IRQ_ETH, pic32mx_interrupt, NULL); #endif if (ret != 0) { diff --git a/arch/mips/src/pic32mx/pic32mx-irq.c b/arch/mips/src/pic32mx/pic32mx-irq.c index f9e82155dc2..f19311889e8 100644 --- a/arch/mips/src/pic32mx/pic32mx-irq.c +++ b/arch/mips/src/pic32mx/pic32mx-irq.c @@ -154,7 +154,7 @@ void up_irqinitialize(void) /* Attach and enable software interrupts */ - irq_attach(PIC32MX_IRQ_CS0, up_swint0); + irq_attach(PIC32MX_IRQ_CS0, up_swint0, NULL); up_enable_irq(PIC32MX_IRQSRC_CS0); /* currents_regs is non-NULL only while processing an interrupt */ diff --git a/arch/mips/src/pic32mx/pic32mx-serial.c b/arch/mips/src/pic32mx/pic32mx-serial.c index ebd20cdfdda..8e6582a1452 100644 --- a/arch/mips/src/pic32mx/pic32mx-serial.c +++ b/arch/mips/src/pic32mx/pic32mx-serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/mips/src/pic32mx/pic32mx-serial.c * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2012, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -173,7 +173,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); +static int up_interrupt(int irq, void *context, void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -413,7 +413,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach the IRQ */ - return irq_attach(priv->irq, up_interrupt); + return irq_attach(priv->irq, up_interrupt, dev); } /**************************************************************************** @@ -451,32 +451,15 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt(int irq, void *context) +static int up_interrupt(int irq, void *context, void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct up_dev_s *priv; int passes; bool handled; -#ifdef CONFIG_PIC32MX_UART1 - if (g_uart1priv.irq == irq) - { - dev = &g_uart1port; - } - else -#endif -#ifdef CONFIG_PIC32MX_UART2 - if (g_uart2priv.irq == irq) - { - dev = &g_uart2port; - } - else -#endif - { - PANIC(); - } + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct up_dev_s *)dev->priv; - DEBUGASSERT(priv); /* Loop until there are no characters to be transferred or, * until we have been looping for a long time. diff --git a/arch/mips/src/pic32mx/pic32mx-spi.c b/arch/mips/src/pic32mx/pic32mx-spi.c index 2489f671c45..1cfd0164d52 100644 --- a/arch/mips/src/pic32mx/pic32mx-spi.c +++ b/arch/mips/src/pic32mx/pic32mx-spi.c @@ -909,7 +909,7 @@ FAR struct spi_dev_s *pic32mx_spibus_initialize(int port) * resource is available. */ - ret = irq_attach(priv->vector, spi_interrupt); + ret = irq_attach(priv->vector, spi_interrupt, NULL); if (ret < 0) { spierr("ERROR: Failed to attach vector: %d port: %d\n", diff --git a/arch/mips/src/pic32mx/pic32mx-timerisr.c b/arch/mips/src/pic32mx/pic32mx-timerisr.c index 73cdc8b3cbe..c34ceb5a9fe 100644 --- a/arch/mips/src/pic32mx/pic32mx-timerisr.c +++ b/arch/mips/src/pic32mx/pic32mx-timerisr.c @@ -137,7 +137,7 @@ * ****************************************************************************/ -static int pc32mx_timerisr(int irq, uint32_t *regs) +static int pc32mx_timerisr(int irq, uint32_t *regs, void *arg) { /* Clear the pending timer interrupt */ @@ -183,7 +183,7 @@ void mips_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(PIC32MX_IRQ_T1, (xcpt_t)pc32mx_timerisr); + (void)irq_attach(PIC32MX_IRQ_T1, (xcpt_t)pc32mx_timerisr, NULL); /* And enable the timer interrupt */ diff --git a/arch/mips/src/pic32mx/pic32mx-usbdev.c b/arch/mips/src/pic32mx/pic32mx-usbdev.c index da5544580a9..b184ff41ecd 100644 --- a/arch/mips/src/pic32mx/pic32mx-usbdev.c +++ b/arch/mips/src/pic32mx/pic32mx-usbdev.c @@ -492,7 +492,7 @@ static void pic32mx_ep0outcomplete(struct pic32mx_usbdev_s *priv); static void pic32mx_ep0incomplete(struct pic32mx_usbdev_s *priv); static void pic32mx_ep0transfer(struct pic32mx_usbdev_s *priv, uint16_t ustat); -static int pic32mx_interrupt(int irq, void *context); +static int pic32mx_interrupt(int irq, void *context, FAR void *arg); /* Endpoint helpers *********************************************************/ @@ -2643,7 +2643,7 @@ static void pic32mx_ep0transfer(struct pic32mx_usbdev_s *priv, uint16_t ustat) * Name: pic32mx_interrupt ****************************************************************************/ -static int pic32mx_interrupt(int irq, void *context) +static int pic32mx_interrupt(int irq, void *context, FAR void *arg) { /* For now there is only one USB controller, but we will always refer to * it using a pointer to make any future ports to multiple USB controllers @@ -4297,7 +4297,7 @@ void up_usbinitialize(void) * them when we need them later. */ - if (irq_attach(PIC32MX_IRQ_USB, pic32mx_interrupt) != 0) + if (irq_attach(PIC32MX_IRQ_USB, pic32mx_interrupt, NULL) != 0) { usbtrace(TRACE_DEVERROR(PIC32MX_TRACEERR_IRQREGISTRATION), (uint16_t)PIC32MX_IRQ_USB); diff --git a/arch/mips/src/pic32mz/pic32mz-ethernet.c b/arch/mips/src/pic32mz/pic32mz-ethernet.c index 7eb5c4d54cf..4e2560eecb0 100644 --- a/arch/mips/src/pic32mz/pic32mz-ethernet.c +++ b/arch/mips/src/pic32mz/pic32mz-ethernet.c @@ -422,7 +422,7 @@ static void pic32mz_rxdone(struct pic32mz_driver_s *priv); static void pic32mz_txdone(struct pic32mz_driver_s *priv); static void pic32mz_interrupt_work(void *arg); -static int pic32mz_interrupt(int irq, void *context); +static int pic32mz_interrupt(int irq, void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -1880,7 +1880,7 @@ static void pic32mz_interrupt_work(void *arg) * ****************************************************************************/ -static int pic32mz_interrupt(int irq, void *context) +static int pic32mz_interrupt(int irq, void *context, FAR void *arg) { struct pic32mz_driver_s *priv; uint32_t status; @@ -2097,7 +2097,8 @@ static void pic32mz_poll_expiry(int argc, wdparm_t arg, ...) * cycle. */ - (void)wd_start(priv->pd_txpoll, PIC32MZ_WDDELAY, pic32mz_poll_expiry, 1, arg); + (void)wd_start(priv->pd_txpoll, PIC32MZ_WDDELAY, pic32mz_poll_expiry, + 1, arg); } } @@ -3426,9 +3427,9 @@ static inline int pic32mz_ethinitialize(int intf) /* Attach the IRQ to the driver */ #if CONFIG_PIC32MZ_NINTERFACES > 1 - ret = irq_attach(priv->pd_irq, pic32mz_interrupt); + ret = irq_attach(priv->pd_irq, pic32mz_interrupt, NULL); #else - ret = irq_attach(PIC32MZ_IRQ_ETH, pic32mz_interrupt); + ret = irq_attach(PIC32MZ_IRQ_ETH, pic32mz_interrupt, NULL); #endif if (ret != 0) { diff --git a/arch/mips/src/pic32mz/pic32mz-gpioirq.c b/arch/mips/src/pic32mz/pic32mz-gpioirq.c index 9b7f8c68083..8e3106cc206 100644 --- a/arch/mips/src/pic32mz/pic32mz-gpioirq.c +++ b/arch/mips/src/pic32mz/pic32mz-gpioirq.c @@ -72,7 +72,7 @@ static inline bool pic32mz_input(pinset_t pinset); static inline bool pic32mz_interrupt(pinset_t pinset); static inline bool pic32mz_pullup(pinset_t pinset); static inline bool pic32mz_pulldown(pinset_t pinset); -static int pic32mz_cninterrupt(int irq, FAR void *context); +static int pic32mz_cninterrupt(int irq, FAR void *context, FAR void *arg); /**************************************************************************** * Public Data @@ -204,7 +204,7 @@ static inline unsigned int pic32mz_pin(pinset_t pinset) * ****************************************************************************/ -static int pic32mz_cninterrupt(int irq, FAR void *context) +static int pic32mz_cninterrupt(int irq, FAR void *context, FAR void *arg) { struct ioport_level2_s *handlers; xcpt_t handler; @@ -334,7 +334,7 @@ void pic32mz_gpioirqinitialize(void) * each IRQ number is consecutive beginning with IOPORTA. */ - ret = irq_attach(PIC32MZ_IRQ_PORTA + i, pic32mz_cninterrupt); + ret = irq_attach(PIC32MZ_IRQ_PORTA + i, pic32mz_cninterrupt, NULL); DEBUGASSERT(ret == OK); UNUSED(ret); diff --git a/arch/mips/src/pic32mz/pic32mz-irq.c b/arch/mips/src/pic32mz/pic32mz-irq.c index 4bb185939ec..bb1fda5108e 100644 --- a/arch/mips/src/pic32mz/pic32mz-irq.c +++ b/arch/mips/src/pic32mz/pic32mz-irq.c @@ -236,7 +236,7 @@ void up_irqinitialize(void) /* Attach and enable software interrupts */ - irq_attach(PIC32MZ_IRQ_CS0, up_swint0); + irq_attach(PIC32MZ_IRQ_CS0, up_swint0, NULL); up_enable_irq(PIC32MZ_IRQ_CS0); /* currents_regs is non-NULL only while processing an interrupt */ diff --git a/arch/mips/src/pic32mz/pic32mz-serial.c b/arch/mips/src/pic32mz/pic32mz-serial.c index fcdc0c1874d..cfce690614e 100644 --- a/arch/mips/src/pic32mz/pic32mz-serial.c +++ b/arch/mips/src/pic32mz/pic32mz-serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/mips/src/pic32mz/pic32mz-serial.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -248,7 +248,6 @@ struct up_dev_s { uintptr_t uartbase; /* Base address of UART registers */ - xcpt_t handler; /* UART interrupt handler */ uint32_t baud; /* Configured baud */ uint8_t irqe; /* Error IRQ associated with this UART (for enable) */ uint8_t irqrx; /* RX IRQ associated with this UART (for enable) */ @@ -276,27 +275,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); - -static int up_interrupt(struct uart_dev_s *priv); -#ifdef CONFIG_PIC32MZ_UART1 -static int up_uart1_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_PIC32MZ_UART2 -static int up_uart2_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_PIC32MZ_UART3 -static int up_uart3_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_PIC32MZ_UART4 -static int up_uart4_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_PIC32MZ_UART5 -static int up_uart5_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_PIC32MZ_UART6 -static int up_uart6_interrupt(int irq, void *context); -#endif - +static int up_interrupt(int irq, void *context, FAR void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -362,7 +341,6 @@ static char g_uart6txbuffer[CONFIG_UART6_TXBUFSIZE]; static struct up_dev_s g_uart1priv = { .uartbase = PIC32MZ_UART1_K1BASE, - .handler = up_uart1_interrupt, .baud = CONFIG_UART1_BAUD, .irqe = PIC32MZ_IRQ_U1E, .irqrx = PIC32MZ_IRQ_U1RX, @@ -395,7 +373,6 @@ static uart_dev_t g_uart1port = static struct up_dev_s g_uart2priv = { .uartbase = PIC32MZ_UART2_K1BASE, - .handler = up_uart2_interrupt, .baud = CONFIG_UART2_BAUD, .irqe = PIC32MZ_IRQ_U2E, .irqrx = PIC32MZ_IRQ_U2RX, @@ -428,7 +405,6 @@ static uart_dev_t g_uart2port = static struct up_dev_s g_uart3priv = { .uartbase = PIC32MZ_UART3_K1BASE, - .handler = up_uart3_interrupt, .baud = CONFIG_UART3_BAUD, .irqe = PIC32MZ_IRQ_U3E, .irqrx = PIC32MZ_IRQ_U3RX, @@ -461,7 +437,6 @@ static uart_dev_t g_uart3port = static struct up_dev_s g_uart4priv = { .uartbase = PIC32MZ_UART4_K1BASE, - .handler = up_uart4_interrupt, .baud = CONFIG_UART4_BAUD, .irqe = PIC32MZ_IRQ_U4E, .irqrx = PIC32MZ_IRQ_U4RX, @@ -494,7 +469,6 @@ static uart_dev_t g_uart4port = static struct up_dev_s g_uart5priv = { .uartbase = PIC32MZ_UART5_K1BASE, - .handler = up_uart5_interrupt, .baud = CONFIG_UART5_BAUD, .irqe = PIC32MZ_IRQ_U5E, .irqrx = PIC32MZ_IRQ_U5RX, @@ -527,7 +501,6 @@ static uart_dev_t g_uart5port = static struct up_dev_s g_uart6priv = { .uartbase = PIC32MZ_UART6_K1BASE, - .handler = up_uart6_interrupt, .baud = CONFIG_UART6_BAUD, .irqe = PIC32MZ_IRQ_U6E, .irqrx = PIC32MZ_IRQ_U6RX, @@ -675,17 +648,19 @@ static int up_attach(struct uart_dev_s *dev) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; int ret; - /* Attach the IRQs */ + DEBUGASSERT(dev != NULL && dev->priv != NULL); - ret = irq_attach(priv->irqrx, priv->handler); + /* Attach the IRQ */ + + ret = irq_attach(priv->irqrx, up_interrupt, dev); if (ret == 0) { - ret = irq_attach(priv->irqtx, priv->handler); + ret = irq_attach(priv->irqtx, up_interrupt, dev); } if (ret == 0) { - ret = irq_attach(priv->irqe, priv->handler); + ret = irq_attach(priv->irqe, up_interrupt, dev); } return ret; @@ -727,13 +702,14 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt(struct uart_dev_s *dev) +static int up_interrupt(int irq, void *context, FAR void *arg) { + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct up_dev_s *priv; - int passes; - bool handled; + int passes; + bool handled; - DEBUGASSERT(dev && dev->priv); + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct up_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, @@ -830,56 +806,6 @@ static int up_interrupt(struct uart_dev_s *dev) return OK; } -/**************************************************************************** - * Name: up_uartn_interrupt - * - * Description: - * These the UART-specific interrupt handlers. They simply invoke the - * common uart interrupt handler with the correct state data. - * - ****************************************************************************/ - -#ifdef CONFIG_PIC32MZ_UART1 -static int up_uart1_interrupt(int irq, void *context) -{ - return up_interrupt(&g_uart1port); -} -#endif - -#ifdef CONFIG_PIC32MZ_UART2 -static int up_uart2_interrupt(int irq, void *context) -{ - return up_interrupt(&g_uart2port); -} -#endif - -#ifdef CONFIG_PIC32MZ_UART3 -static int up_uart3_interrupt(int irq, void *context) -{ - return up_interrupt(&g_uart3port); -} -#endif - -#ifdef CONFIG_PIC32MZ_UART4 -static int up_uart4_interrupt(int irq, void *context) -{ - return up_interrupt(&g_uart4port); -} -#endif - -#ifdef CONFIG_PIC32MZ_UART5 -static int up_uart5_interrupt(int irq, void *context) -{ - return up_interrupt(&g_uart5port); -} -#endif -#ifdef CONFIG_PIC32MZ_UART6 -static int up_uart6_interrupt(int irq, void *context) -{ - return up_interrupt(&g_uart6port); -} -#endif - /**************************************************************************** * Name: up_ioctl * diff --git a/arch/mips/src/pic32mz/pic32mz-spi.c b/arch/mips/src/pic32mz/pic32mz-spi.c index 3eea799d10c..ff56c7f527d 100644 --- a/arch/mips/src/pic32mz/pic32mz-spi.c +++ b/arch/mips/src/pic32mz/pic32mz-spi.c @@ -1294,7 +1294,7 @@ FAR struct spi_dev_s *pic32mz_spibus_initialize(int port) * resources are available. */ - ret = irq_attach(priv->config->rxirq, spi_interrupt); + ret = irq_attach(priv->config->rxirq, spi_interrupt, NULL); if (ret < 0) { spierr("ERROR: Failed to attach RX interrupt: %d port: %d\n", @@ -1302,7 +1302,7 @@ FAR struct spi_dev_s *pic32mz_spibus_initialize(int port) goto errout; } - ret = irq_attach(priv->config->txirq, spi_interrupt); + ret = irq_attach(priv->config->txirq, spi_interrupt, NULL); if (ret < 0) { spierr("ERROR: Failed to attach TX interrupt: %d port: %d\n", @@ -1310,7 +1310,7 @@ FAR struct spi_dev_s *pic32mz_spibus_initialize(int port) goto errout_with_rxirq; } - ret = irq_attach(priv->config->firq, spi_interrupt); + ret = irq_attach(priv->config->firq, spi_interrupt, NULL); if (ret < 0) { spierr("ERROR: Failed to attach fault interrupt: %d port: %d\n", diff --git a/arch/mips/src/pic32mz/pic32mz-timerisr.c b/arch/mips/src/pic32mz/pic32mz-timerisr.c index 63ca681a1eb..75e35ecf057 100644 --- a/arch/mips/src/pic32mz/pic32mz-timerisr.c +++ b/arch/mips/src/pic32mz/pic32mz-timerisr.c @@ -136,7 +136,7 @@ * ****************************************************************************/ -static int pc32mz_timerisr(int irq, uint32_t *regs) +static int pc32mz_timerisr(int irq, uint32_t *regs, void *arg) { /* Clear the pending timer interrupt */ @@ -179,7 +179,7 @@ void mips_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(PIC32MZ_IRQ_T1, (xcpt_t)pc32mz_timerisr); + (void)irq_attach(PIC32MZ_IRQ_T1, (xcpt_t)pc32mz_timerisr, NULL); /* And enable the timer interrupt */ diff --git a/arch/misoc/src/common/misoc_net.c b/arch/misoc/src/common/misoc_net.c index 85d6e60bbf2..c7903f364e7 100644 --- a/arch/misoc/src/common/misoc_net.c +++ b/arch/misoc/src/common/misoc_net.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/misoc/src/commong/misoc_net_net.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * Ramtin Amin * @@ -161,7 +161,7 @@ static void misoc_net_receive(FAR struct misoc_net_driver_s *priv); static void misoc_net_txdone(FAR struct misoc_net_driver_s *priv); static void misoc_net_interrupt_work(FAR void *arg); -static int misoc_net_interrupt(int irq, FAR void *context); +static int misoc_net_interrupt(int irq, FAR void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -542,6 +542,8 @@ static void misoc_net_receive(FAR struct misoc_net_driver_s *priv) static void misoc_net_txdone(FAR struct misoc_net_driver_s *priv) { + int delay; + /* Check for errors and update statistics */ NETDEV_TXDONE(priv->misoc_net_dev); @@ -554,14 +556,25 @@ static void misoc_net_txdone(FAR struct misoc_net_driver_s *priv) wd_cancel(priv->misoc_net_txtimeout); - /* Then make sure that the TX poll timer is running (if it is already - * running, the following would restart it). This is necessary to - * avoid certain race conditions where the polling sequence can be - * interrupted. + /* Check if the poll timer is running. If it is not, then start it now. + * There is a race condition here: We may test the time remaining on the + * poll timer and determine that it is still running, but then the timer + * expires immiately. That should not be problem, however, the poll timer + * processing should be in the work queue and should execute immediately + * after we complete the TX poll. Inefficient, but not fatal. */ - (void)wd_start(priv->misoc_net_txpoll, MISOC_NET_WDDELAY, - misoc_net_poll_expiry, 1, (wdparm_t)priv); + delay = wd_gettime(priv->misoc_net_txpoll); + if (delay <= 0) + { + /* The poll timer is not running .. restart it. This is necessary to + * avoid certain race conditions where the polling sequence can be + * interrupted. + */ + + (void)wd_start(priv->misoc_net_txpoll, MISOC_NET_WDDELAY, + misoc_net_poll_expiry, 1, (wdparm_t)priv); + } /* And disable further TX interrupts. */ @@ -639,7 +652,7 @@ static void misoc_net_interrupt_work(FAR void *arg) * ****************************************************************************/ -static int misoc_net_interrupt(int irq, FAR void *context) +static int misoc_net_interrupt(int irq, FAR void *context, FAR void *arg) { FAR struct misoc_net_driver_s *priv = &g_misoc_net[0]; @@ -1174,7 +1187,7 @@ int misoc_net_initialize(int intf) /* Attach the IRQ to the driver */ - if (irq_attach(ETHMAC_INTERRUPT, misoc_net_interrupt)) + if (irq_attach(ETHMAC_INTERRUPT, misoc_net_interrupt, NULL)) { /* We could not attach the ISR to the interrupt */ diff --git a/arch/misoc/src/common/misoc_serial.c b/arch/misoc/src/common/misoc_serial.c index c9b1f838639..b64b0ea737b 100644 --- a/arch/misoc/src/common/misoc_serial.c +++ b/arch/misoc/src/common/misoc_serial.c @@ -156,7 +156,7 @@ static int misoc_setup(struct uart_dev_s *dev); static void misoc_shutdown(struct uart_dev_s *dev); static int misoc_attach(struct uart_dev_s *dev); static void misoc_detach(struct uart_dev_s *dev); -static int misoc_uart_interrupt(int irq, void *context); +static int misoc_uart_interrupt(int irq, void *context, FAR void *arg); static int misoc_ioctl(struct file *filep, int cmd, unsigned long arg); static int misoc_receive(struct uart_dev_s *dev, uint32_t *status); static void misoc_rxint(struct uart_dev_s *dev, bool enable); @@ -313,7 +313,7 @@ static int misoc_attach(struct uart_dev_s *dev) { struct misoc_dev_s *priv = (struct misoc_dev_s *)dev->priv; - (void)irq_attach(priv->irq, misoc_uart_interrupt); + (void)irq_attach(priv->irq, misoc_uart_interrupt, NULL); up_enable_irq(priv->irq); return OK; @@ -349,7 +349,7 @@ static void misoc_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int misoc_uart_interrupt(int irq, void *context) +static int misoc_uart_interrupt(int irq, void *context, FAR void *arg) { uint32_t stat; struct uart_dev_s *dev = NULL; diff --git a/arch/misoc/src/common/misoc_timerisr.c b/arch/misoc/src/common/misoc_timerisr.c index 38266b64556..3c4b4919d36 100644 --- a/arch/misoc/src/common/misoc_timerisr.c +++ b/arch/misoc/src/common/misoc_timerisr.c @@ -95,7 +95,7 @@ * ****************************************************************************/ -int misoc_timer_isr(int irq, void *context) +int misoc_timer_isr(int irq, void *context, void *arg) { /* Clear event pending */ @@ -139,7 +139,7 @@ void misoc_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(TIMER0_INTERRUPT, misoc_timer_isr); + (void)irq_attach(TIMER0_INTERRUPT, misoc_timer_isr, NULL); /* And enable the timer interrupt */ diff --git a/arch/misoc/src/lm32/lm32.h b/arch/misoc/src/lm32/lm32.h index a09bcfec47c..6d4ef15a073 100644 --- a/arch/misoc/src/lm32/lm32.h +++ b/arch/misoc/src/lm32/lm32.h @@ -139,7 +139,7 @@ uint32_t *lm32_doirq(int irq, uint32_t *regs); /* Software interrupts ******************************************************/ -int lm32_swint(int irq, FAR void *context); +int lm32_swint(int irq, FAR void *context, FAR void *arg); /* System timer *************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_irq.c b/arch/misoc/src/lm32/lm32_irq.c index eb5313810d4..08b6953b081 100644 --- a/arch/misoc/src/lm32/lm32_irq.c +++ b/arch/misoc/src/lm32/lm32_irq.c @@ -71,7 +71,7 @@ void lm32_irq_initialize(void) /* Attach the software interrupt */ - (void)irq_attach(LM32_IRQ_SWINT, lm32_swint); + (void)irq_attach(LM32_IRQ_SWINT, lm32_swint, NULL); /* Enable interrupts */ diff --git a/arch/misoc/src/lm32/lm32_swint.c b/arch/misoc/src/lm32/lm32_swint.c index cdfbeeb389e..7a49cdbb337 100644 --- a/arch/misoc/src/lm32/lm32_swint.c +++ b/arch/misoc/src/lm32/lm32_swint.c @@ -130,7 +130,7 @@ static void dispatch_syscall(void) * ****************************************************************************/ -int lm32_swint(int irq, FAR void *context) +int lm32_swint(int irq, FAR void *context, FAR void *arg) { uint32_t *regs = (uint32_t *)context; diff --git a/arch/renesas/src/m16c/m16c_serial.c b/arch/renesas/src/m16c/m16c_serial.c index cdbcc2471c8..72cf64a3a5d 100644 --- a/arch/renesas/src/m16c/m16c_serial.c +++ b/arch/renesas/src/m16c/m16c_serial.c @@ -267,12 +267,12 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_rcvinterrupt(int irq, void *context); +static int up_rcvinterrupt(int irq, void *context, void *arg); static int up_receive(struct uart_dev_s *dev, unsigned int *status); static void m16c_rxint(struct up_dev_s *dev, bool enable); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); -static int up_xmtinterrupt(int irq, void *context); +static int up_xmtinterrupt(int irq, void *context, void *arg); static void up_send(struct uart_dev_s *dev, int ch); static void m16c_txint(struct up_dev_s *dev, bool enable); static void up_txint(struct uart_dev_s *dev, bool enable); @@ -711,12 +711,12 @@ static int up_attach(struct uart_dev_s *dev) /* Attach the UART receive data available IRQ */ - ret = irq_attach(priv->rcvirq, up_rcvinterrupt); + ret = irq_attach(priv->rcvirq, up_rcvinterrupt, dev); if (ret == OK) { /* Attach the UART transmit complete IRQ */ - ret = irq_attach(priv->xmtirq, up_xmtinterrupt); + ret = irq_attach(priv->xmtirq, up_xmtinterrupt, dev); if (ret != OK) { /* Detach the ERI interrupt on failure */ @@ -764,34 +764,11 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_rcvinterrupt(int irq, void *context) +static int up_rcvinterrupt(int irq, void *context, void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; -#ifdef CONFIG_M16C_UART0 - if (irq == g_uart0priv.rcvirq) - { - dev = &g_uart0port; - } - else -#endif -#ifdef CONFIG_M16C_UART1 - if (irq == g_uart1priv.rcvirq) - { - dev = &g_uart1port; - } - else -#endif -#ifdef CONFIG_M16C_UART2 - if (irq = g_uart2priv.rcvirq) - { - dev = &g_uart2port; - } - else -#endif - { - PANIC(); - } + DEBUGASSERT(dev != NULL && dev->priv != NULL); /* Handle incoming, receive bytes (RDRF: Receive Data Register Full) */ @@ -924,40 +901,17 @@ static bool up_rxavailable(struct uart_dev_s *dev) * This is the UART receive interrupt handler. It will be invoked * when an interrupt received on the 'irq' It should call * uart_transmitchars or uart_receivechar to perform the - * appropriate data transfers. The interrupt handling logic\ + * appropriate data transfers. The interrupt handling logic * must be able to map the 'irq' number into the approprite * up_dev_s structure in order to call these functions. * ****************************************************************************/ -static int up_xmtinterrupt(int irq, void *context) +static int up_xmtinterrupt(int irq, void *context, void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; -#ifdef CONFIG_M16C_UART0 - if (irq == g_uart0priv.xmtirq) - { - dev = &g_uart0port; - } - else -#endif -#ifdef CONFIG_M16C_UART1 - if (irq == g_uart1priv.xmtirq) - { - dev = &g_uart1port; - } - else -#endif -#ifdef CONFIG_M16C_UART2 - if (irq == g_uart2priv.xmtirq) - { - dev = &g_uart1port; - } - else -#endif - { - PANIC(); - } + DEBUGASSERT(dev != NULL && dev->priv != NULL); /* Handle outgoing, transmit bytes */ diff --git a/arch/renesas/src/m16c/m16c_timerisr.c b/arch/renesas/src/m16c/m16c_timerisr.c index 8d1e8b15e8e..6d82add128f 100644 --- a/arch/renesas/src/m16c/m16c_timerisr.c +++ b/arch/renesas/src/m16c/m16c_timerisr.c @@ -119,7 +119,7 @@ * ****************************************************************************/ -static int m16c_timerisr(int irq, uint32_t *regs) +static int m16c_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -166,7 +166,7 @@ void renesas_timer_initialize(void) /* Attach the interrupt handler */ - irq_attach(M16C_SYSTIMER_IRQ, (xcpt_t)m16c_timerisr); + irq_attach(M16C_SYSTIMER_IRQ, (xcpt_t)m16c_timerisr, NULL); /* Enable timer interrupts */ diff --git a/arch/renesas/src/sh1/sh1_serial.c b/arch/renesas/src/sh1/sh1_serial.c index ff9246fad99..3dd5c1cff2b 100644 --- a/arch/renesas/src/sh1/sh1_serial.c +++ b/arch/renesas/src/sh1/sh1_serial.c @@ -158,7 +158,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); +static int up_interrupt(int irq, void *context, FAR void *arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); @@ -485,17 +485,17 @@ static int up_attach(struct uart_dev_s *dev) /* Attach the RDR full IRQ (RXI) that is enabled by the RIE SCR bit */ - ret = irq_attach(priv->irq + SH1_RXI_IRQ_OFFSET, up_interrupt); + ret = irq_attach(priv->irq + SH1_RXI_IRQ_OFFSET, up_interrupt, NULL); if (ret == OK) { /* The RIE interrupt enable also enables the receive error interrupt (ERI) */ - ret = irq_attach(priv->irq + SH1_ERI_IRQ_OFFSET, up_interrupt); + ret = irq_attach(priv->irq + SH1_ERI_IRQ_OFFSET, up_interrupt, NULL); if (ret == OK) { /* Attach the TDR empty IRQ (TXI) enabled by the TIE SCR bit */ - ret = irq_attach(priv->irq + SH1_TXI_IRQ_OFFSET, up_interrupt); + ret = irq_attach(priv->irq + SH1_TXI_IRQ_OFFSET, up_interrupt, NULL); if (ret == OK) { #ifdef CONFIG_ARCH_IRQPRIO @@ -567,7 +567,7 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt(int irq, void *context) +static int up_interrupt(int irq, void *context, FAR void *arg) { struct uart_dev_s *dev = NULL; struct up_dev_s *priv; diff --git a/arch/renesas/src/sh1/sh1_timerisr.c b/arch/renesas/src/sh1/sh1_timerisr.c index a16b17a71de..a1ec7d3a556 100644 --- a/arch/renesas/src/sh1/sh1_timerisr.c +++ b/arch/renesas/src/sh1/sh1_timerisr.c @@ -125,7 +125,7 @@ * ****************************************************************************/ -static int sh1_timerisr(int irq, uint32_t *regs) +static int sh1_timerisr(int irq, uint32_t *regs, void *arg) { uint8_t reg8; @@ -183,7 +183,7 @@ void renesas_timer_initialize(void) /* Attach the IMIA0 IRQ */ - irq_attach(SH1_SYSTIMER_IRQ, (xcpt_t)sh1_timerisr); + irq_attach(SH1_SYSTIMER_IRQ, (xcpt_t)sh1_timerisr, NULL); /* Enable interrupts on GRA compare match */ diff --git a/arch/risc-v/src/common/up_internal.h b/arch/risc-v/src/common/up_internal.h index bed5f057609..bf0fa917783 100644 --- a/arch/risc-v/src/common/up_internal.h +++ b/arch/risc-v/src/common/up_internal.h @@ -137,7 +137,7 @@ void up_irqinitialize(void); void up_copystate(uint32_t *dest, uint32_t *src); void up_dumpstate(void); void up_sigdeliver(void); -int up_swint(int irq, FAR void *context); +int up_swint(int irq, FAR void *context, FAR void *arg); uint32_t up_get_newintctx(void); /* System timer *************************************************************/ diff --git a/arch/risc-v/src/nr5m100/nr5_irq.c b/arch/risc-v/src/nr5m100/nr5_irq.c index b0d1bfa756e..fd973e74541 100644 --- a/arch/risc-v/src/nr5m100/nr5_irq.c +++ b/arch/risc-v/src/nr5m100/nr5_irq.c @@ -111,7 +111,7 @@ void epic_dump(void) #define CONFIG_DEBUG -int nr5_trap_handler(int irq, void *context) +int nr5_trap_handler(int irq, void *context, FAR void *arg) { uint32_t sp; @@ -182,11 +182,11 @@ void up_irqinitialize(void) /* Attach the Trap exception handler. */ - irq_attach(NR5_IRQ_TRAP, nr5_trap_handler); + irq_attach(NR5_IRQ_TRAP, nr5_trap_handler, NULL); /* Attach software interrupt handler */ - irq_attach(NR5_IRQ_SOFTWARE, up_swint); + irq_attach(NR5_IRQ_SOFTWARE, up_swint, NULL); up_enable_irq(NR5_IRQ_SOFTWARE); /* Set the software interrupt priority higher */ diff --git a/arch/risc-v/src/nr5m100/nr5_serial.c b/arch/risc-v/src/nr5m100/nr5_serial.c index 44a4cd5d9f0..32572a5ebc4 100644 --- a/arch/risc-v/src/nr5m100/nr5_serial.c +++ b/arch/risc-v/src/nr5m100/nr5_serial.c @@ -158,7 +158,7 @@ static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); +static int up_interrupt(int irq, void *context, FAR void *arg); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -363,8 +363,8 @@ static int up_attach(struct uart_dev_s *dev) /* Initialize interrupt generation on the peripheral */ up_serialout(priv, NR5_UART_CTRL_REG_OFFSET, IE_RX | IE_TX); - irq_attach(priv->irqrx, up_interrupt); - irq_attach(priv->irqtx, up_interrupt); + irq_attach(priv->irqrx, up_interrupt, dev); + irq_attach(priv->irqtx, up_interrupt, dev); /* Indicate no interrupts active in EPIC */ @@ -413,33 +413,16 @@ static void up_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int up_interrupt(int irq, void *context) +static int up_interrupt(int irq, void *context, FAR void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct up_dev_s *priv; int passes; uint32_t status; bool handled; -#ifdef CONFIG_NR5_UART1 - if (g_uart1priv.irqrx == irq || g_uart1priv.irqtx == irq) - { - dev = &g_uart1port; - } - else -#endif -#ifdef CONFIG_NR5_UART2 - if (g_uart2priv.irqrx == irq || g_uart2priv.irqtx == irq) - { - dev = &g_uart2port; - } - else -#endif - { - PANIC(); - } + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct up_dev_s *)dev->priv; - DEBUGASSERT(priv); /* Loop until there are no characters to be transferred or, * until we have been looping for a long time. diff --git a/arch/risc-v/src/nr5m100/nr5_timer.c b/arch/risc-v/src/nr5m100/nr5_timer.c index 132cb9e9849..4df3ef67556 100644 --- a/arch/risc-v/src/nr5m100/nr5_timer.c +++ b/arch/risc-v/src/nr5m100/nr5_timer.c @@ -275,7 +275,7 @@ static int nr5_timer_setisr(FAR struct nr5_timer_dev_s *dev, /* Otherwise set callback and enable interrupt */ - irq_attach(vectorno, handler); + irq_attach(vectorno, handler, NULL); up_enable_irq(vectorno); #ifdef CONFIG_ARCH_IRQPRIO diff --git a/arch/risc-v/src/nr5m100/nr5_timer.h b/arch/risc-v/src/nr5m100/nr5_timer.h index b1c76cc911f..1c33a7e6908 100644 --- a/arch/risc-v/src/nr5m100/nr5_timer.h +++ b/arch/risc-v/src/nr5m100/nr5_timer.h @@ -135,7 +135,7 @@ FAR struct nr5_timer_dev_s *nr5_timer_init(int timer); /* Power-down timer, mark it as unused */ -int nr5_timer_deinit(FAR struct nr5_timer_dev_s * dev); +int nr5_timer_deinit(FAR struct nr5_timer_dev_s *dev); /**************************************************************************** * Name: nr5_timer_initialize diff --git a/arch/risc-v/src/nr5m100/nr5_timerisr.c b/arch/risc-v/src/nr5m100/nr5_timerisr.c index fc168a12c8a..93375279ec7 100644 --- a/arch/risc-v/src/nr5m100/nr5_timerisr.c +++ b/arch/risc-v/src/nr5m100/nr5_timerisr.c @@ -102,7 +102,7 @@ static uint64_t g_systick = 0; * ****************************************************************************/ -static int nr5m100_timerisr(int irq, void *context) +static int nr5m100_timerisr(int irq, void *context, FAR void *arg) { /* Process timer interrupt */ @@ -146,7 +146,7 @@ void riscv_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(NR5_IRQ_SYSTICK, nr5m100_timerisr); + (void)irq_attach(NR5_IRQ_SYSTICK, nr5m100_timerisr, NULL); /* Configure and enable SysTick to interrupt at the requested rate */ diff --git a/arch/risc-v/src/nr5m100/nr5_uart.c b/arch/risc-v/src/nr5m100/nr5_uart.c index 4497e70d3e9..312c6743d17 100644 --- a/arch/risc-v/src/nr5m100/nr5_uart.c +++ b/arch/risc-v/src/nr5m100/nr5_uart.c @@ -168,7 +168,7 @@ void nr5_uart_init(int uart) { /* Attache the ISR and enable the IRQ with the EPIC */ - //irq_attach(dev->regs->rx_irq, &nr5_uart_rx_isr); + //irq_attach(dev->regs->rx_irq, &nr5_uart_rx_isr, NULL); //up_enable_irq(dev->regs->rx_irq); // Set the baud rate diff --git a/arch/risc-v/src/rv32im/up_swint.c b/arch/risc-v/src/rv32im/up_swint.c index 61f3afefacf..1ba8c73bbd8 100644 --- a/arch/risc-v/src/rv32im/up_swint.c +++ b/arch/risc-v/src/rv32im/up_swint.c @@ -128,7 +128,7 @@ static void dispatch_syscall(void) * ****************************************************************************/ -int up_swint(int irq, FAR void *context) +int up_swint(int irq, FAR void *context, FAR void *arg) { uint32_t *regs = (uint32_t *)context; diff --git a/arch/sim/src/up_qspiflash.c b/arch/sim/src/up_qspiflash.c index f2cafe608bb..c94986b3d38 100644 --- a/arch/sim/src/up_qspiflash.c +++ b/arch/sim/src/up_qspiflash.c @@ -201,7 +201,7 @@ static int qspiflash_command(FAR struct qspi_dev_s *dev, FAR struct qspi_cmdinfo_s *cmd); static int qspiflash_memory(FAR struct qspi_dev_s *dev, FAR struct qspi_meminfo_s *mem); -static FAR void * qspiflash_alloc(FAR struct qspi_dev_s *dev, size_t buflen); +static FAR void *qspiflash_alloc(FAR struct qspi_dev_s *dev, size_t buflen); static void qspiflash_free(FAR struct qspi_dev_s *dev, FAR void *buffer); static void qspiflash_writeword(FAR struct sim_qspiflashdev_s *priv, diff --git a/arch/x86/src/qemu/qemu_timerisr.c b/arch/x86/src/qemu/qemu_timerisr.c index ca1ff272f7d..56d5e42a657 100644 --- a/arch/x86/src/qemu/qemu_timerisr.c +++ b/arch/x86/src/qemu/qemu_timerisr.c @@ -93,7 +93,7 @@ * ****************************************************************************/ -static int qemu_timerisr(int irq, uint32_t *regs) +static int qemu_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -123,7 +123,7 @@ void x86_timer_initialize(void) /* Attach to the timer interrupt handler */ - (void)irq_attach(IRQ0, (xcpt_t)qemu_timerisr); + (void)irq_attach(IRQ0, (xcpt_t)qemu_timerisr, NULL); /* Send the command byte to configure counter 0 */ diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index 1efb25b567c..e79e7c3345b 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -115,7 +115,7 @@ static inline void xtensa_attach_fromcpu0_interrupt(void) /* Attach the inter-CPU interrupt. */ - (void)irq_attach(ESP32_IRQ_CPU_CPU0, (xcpt_t)esp32_fromcpu0_interrupt); + (void)irq_attach(ESP32_IRQ_CPU_CPU0, (xcpt_t)esp32_fromcpu0_interrupt, NULL); /* Enable the inter 0 CPU interrupts. */ diff --git a/arch/xtensa/src/esp32/esp32_gpio.c b/arch/xtensa/src/esp32/esp32_gpio.c index a86110c0fbb..892b87d51c5 100644 --- a/arch/xtensa/src/esp32/esp32_gpio.c +++ b/arch/xtensa/src/esp32/esp32_gpio.c @@ -119,7 +119,7 @@ static void gpio_dispatch(int irq, uint32_t status, uint32_t *regs) ****************************************************************************/ #ifdef CONFIG_ESP32_GPIO_IRQ -static int gpio_interrupt(int irq, FAR void *context) +static int gpio_interrupt(int irq, FAR void *context, FAR void *arg) { uint32_t status; @@ -336,7 +336,7 @@ void esp32_gpioirqinitialize(void) /* Attach and enable the interrupt handler */ - DEBUGVERIFY(irq_attach(ESP32_IRQ_CPU_GPIO, gpio_interrupt)); + DEBUGVERIFY(irq_attach(ESP32_IRQ_CPU_GPIO, gpio_interrupt, NULL)); up_enable_irq(g_gpio_cpuint); } #endif diff --git a/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c b/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c index 01bac85b0cb..779aa3d7465 100644 --- a/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c +++ b/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c @@ -132,12 +132,12 @@ static int esp32_fromcpu_interrupt(int fromcpu) * ****************************************************************************/ -int esp32_fromcpu0_interrupt(int irq, FAR void *context) +int esp32_fromcpu0_interrupt(int irq, FAR void *context, FAR void *arg) { return esp32_fromcpu_interrupt(0); } -int esp32_fromcpu1_interrupt(int irq, FAR void *context) +int esp32_fromcpu1_interrupt(int irq, FAR void *context, FAR void *arg) { return esp32_fromcpu_interrupt(1); } diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index 11c43a4a1ce..c5a43a3d55e 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -119,7 +119,7 @@ static inline void xtensa_attach_fromcpu1_interrupt(void) /* Attach the inter-CPU interrupt. */ - (void)irq_attach(ESP32_IRQ_CPU_CPU1, (xcpt_t)esp32_fromcpu1_interrupt); + (void)irq_attach(ESP32_IRQ_CPU_CPU1, (xcpt_t)esp32_fromcpu1_interrupt, NULL); /* Enable the inter 0 CPU interrupt. */ diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index 3226895de7d..a5b132487dd 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/xtensa/src/esp32/esp32_serial.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -147,7 +147,6 @@ struct esp32_config_s { const uint32_t uartbase; /* Base address of UART registers */ - xcpt_t handler; /* Interrupt handler */ uint8_t periph; /* UART peripheral ID */ uint8_t irq; /* IRQ number assigned to the peripheral */ uint8_t txpin; /* Tx pin number (0-39) */ @@ -186,16 +185,7 @@ static int esp32_setup(struct uart_dev_s *dev); static void esp32_shutdown(struct uart_dev_s *dev); static int esp32_attach(struct uart_dev_s *dev); static void esp32_detach(struct uart_dev_s *dev); -static int esp32_interrupt(struct uart_dev_s *dev); -#ifdef CONFIG_ESP32_UART0 -static int esp32_uart0_interrupt(int cpuint, void *context); -#endif -#ifdef CONFIG_ESP32_UART1 -static int esp32_uart1_interrupt(int cpuint, void *context); -#endif -#ifdef CONFIG_ESP32_UART2 -static int esp32_uart2_interrupt(int cpuint, void *context); -#endif +static int esp32_interrupt(int cpuint, void *context, FAR void *arg); static int esp32_ioctl(struct file *filep, int cmd, unsigned long arg); static int esp32_receive(struct uart_dev_s *dev, unsigned int *status); static void esp32_rxint(struct uart_dev_s *dev, bool enable); @@ -249,7 +239,6 @@ static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; static const struct esp32_config_s g_uart0config = { .uartbase = DR_REG_UART_BASE, - .handler = esp32_uart0_interrupt, .periph = ESP32_PERIPH_UART, .irq = ESP32_IRQ_UART, .txpin = CONFIG_ESP32_UART0_TXPIN, @@ -296,7 +285,6 @@ static uart_dev_t g_uart0port = static const struct esp32_config_s g_uart1config = { .uartbase = DR_REG_UART1_BASE, - .handler = esp32_uart1_interrupt, .periph = ESP32_PERIPH_UART1, .irq = ESP32_IRQ_UART1, .txpin = CONFIG_ESP32_UART1_TXPIN, @@ -343,7 +331,6 @@ static uart_dev_t g_uart1port = static const struct esp32_config_s g_uart2config = { .uartbase = DR_REG_UART2_BASE, - .handler = esp32_uart2_interrupt, .periph = ESP32_PERIPH_UART2, .irq = ESP32_IRQ_UART2, .txpin = CONFIG_ESP32_UART2_TXPIN, @@ -675,7 +662,7 @@ static int esp32_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->config->irq, priv->config->handler); + ret = irq_attach(priv->config->irq, esp32_interrupt, dev); if (ret == OK) { /* Enable the CPU interrupt (RX and TX interrupts are still disabled @@ -735,8 +722,9 @@ static void esp32_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int esp32_interrupt(struct uart_dev_s *dev) +static int esp32_interrupt(int cpuint, void *context, FAR void *arg) { + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct esp32_dev_s *priv; uint32_t regval; uint32_t status; @@ -806,33 +794,6 @@ static int esp32_interrupt(struct uart_dev_s *dev) return OK; } -/**************************************************************************** - * Name: esp32_uart[n]_interrupt - * - * Description: - * UART interrupt handlers - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32_UART0 -static int esp32_uart0_interrupt(int cpuint, void *context) -{ - return esp32_interrupt(&g_uart0port); -} -#endif -#ifdef CONFIG_ESP32_UART1 -static int esp32_uart1_interrupt(int cpuint, void *context) -{ - return esp32_interrupt(&g_uart1port); -} -#endif -#ifdef CONFIG_ESP32_UART2 -static int esp32_uart2_interrupt(int cpuint, void *context) -{ - return esp32_interrupt(&g_uart2port); -} -#endif - /**************************************************************************** * Name: esp32_ioctl * diff --git a/arch/xtensa/src/esp32/esp32_smp.h b/arch/xtensa/src/esp32/esp32_smp.h index 7418a2e0606..14da3164ac9 100644 --- a/arch/xtensa/src/esp32/esp32_smp.h +++ b/arch/xtensa/src/esp32/esp32_smp.h @@ -79,8 +79,8 @@ extern uint32_t g_cpu1_idlestack[CPU1_IDLETHREAD_STACKWORDS]; * ****************************************************************************/ -int esp32_fromcpu0_interrupt(int irq, FAR void *context); -int esp32_fromcpu1_interrupt(int irq, FAR void *context); +int esp32_fromcpu0_interrupt(int irq, FAR void *context, FAR void *arg); +int esp32_fromcpu1_interrupt(int irq, FAR void *context, FAR void *arg); #endif /* CONFIG_SMP */ #endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_SMP_H */ diff --git a/arch/xtensa/src/esp32/esp32_timerisr.c b/arch/xtensa/src/esp32/esp32_timerisr.c index 09653a582f3..777d0377323 100644 --- a/arch/xtensa/src/esp32/esp32_timerisr.c +++ b/arch/xtensa/src/esp32/esp32_timerisr.c @@ -126,7 +126,7 @@ static inline void xtensa_setcompare(uint32_t compare) * ****************************************************************************/ -static int esp32_timerisr(int irq, uint32_t *regs) +static int esp32_timerisr(int irq, uint32_t *regs, FAR void *arg) { uint32_t divisor; uint32_t compare; @@ -192,7 +192,7 @@ void xtensa_timer_initialize(void) /* Attach the timer interrupt */ - (void)irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)esp32_timerisr); + (void)irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)esp32_timerisr, NULL); /* Enable the timer 0 CPU interrupt. */ diff --git a/arch/z16/src/z16f/z16f_serial.c b/arch/z16/src/z16f/z16f_serial.c index dcbcff5ceff..1e24c165d17 100644 --- a/arch/z16/src/z16f/z16f_serial.c +++ b/arch/z16/src/z16f/z16f_serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/z16/src/z16f/z16f_serial.c * - * Copyright (C) 2008-2009, 2012, 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2008-2009, 2012, 2014, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -95,8 +95,8 @@ static int z16f_setup(struct uart_dev_s *dev); static void z16f_shutdown(struct uart_dev_s *dev); static int z16f_attach(struct uart_dev_s *dev); static void z16f_detach(struct uart_dev_s *dev); -static int z16f_rxinterrupt(int irq, void *context); -static int z16f_txinterrupt(int irq, void *context); +static int z16f_rxinterrupt(int irq, void *context, void *arg); +static int z16f_txinterrupt(int irq, void *context, void *arg); static int z16f_ioctl(struct file *filep, int cmd, unsigned long arg); static int z16f_receive(struct uart_dev_s *dev, uint32_t *status); static void z16f_rxint(struct uart_dev_s *dev, bool enable); @@ -426,12 +426,12 @@ static int z16f_attach(struct uart_dev_s *dev) /* Attach the RX IRQ */ - ret = irq_attach(priv->rxirq, z16f_rxinterrupt); + ret = irq_attach(priv->rxirq, z16f_rxinterrupt, dev); if (ret == OK) { /* Attach the TX IRQ */ - ret = irq_attach(priv->txirq, z16f_txinterrupt); + ret = irq_attach(priv->txirq, z16f_txinterrupt, dev); if (ret != OK) { irq_detach(priv->rxirq); @@ -471,30 +471,13 @@ static void z16f_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int z16f_rxinterrupt(int irq, void *context) +static int z16f_rxinterrupt(int irq, void *context, void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct z16f_uart_s *priv; uint8_t status; -#ifdef CONFIG_Z16F_UART1 - if (g_uart1priv.rxirq == irq) - { - dev = &g_uart1port; - } - else -#endif -#ifdef CONFIG_Z16F_UART0 - if (g_uart0priv.rxirq == irq) - { - dev = &g_uart0port; - } - else -#endif - { - PANIC(); - } - + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct z16f_uart_s*)dev->priv; /* Check the LIN-UART status 0 register to determine whether the source of @@ -526,30 +509,13 @@ static int z16f_rxinterrupt(int irq, void *context) * ****************************************************************************/ -static int z16f_txinterrupt(int irq, void *context) +static int z16f_txinterrupt(int irq, void *context, FAR void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct z16f_uart_s *priv; uint8_t status; -#ifdef CONFIG_Z16F_UART1 - if (g_uart1priv.txirq == irq) - { - dev = &g_uart1port; - } - else -#endif -#ifdef CONFIG_Z16F_UART0 - if (g_uart0priv.txirq == irq) - { - dev = &g_uart0port; - } - else -#endif - { - PANIC(); - } - + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct z16f_uart_s*)dev->priv; /* Verify that the transmit data register is empty */ diff --git a/arch/z16/src/z16f/z16f_timerisr.c b/arch/z16/src/z16f/z16f_timerisr.c index c9d75e6fa0f..19fca1f1b24 100644 --- a/arch/z16/src/z16f/z16f_timerisr.c +++ b/arch/z16/src/z16f/z16f_timerisr.c @@ -82,7 +82,7 @@ extern _Erom uint8_t SYS_CLK_FREQ; * ****************************************************************************/ -static int z16f_timerisr(int irq, uint32_t *regs) +static int z16f_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -224,6 +224,6 @@ void z16_timer_initialize(void) /* Attach and enable the timer interrupt (leaving at priority 0) */ - irq_attach(Z16F_IRQ_SYSTIMER, (xcpt_t)z16f_timerisr); + irq_attach(Z16F_IRQ_SYSTIMER, (xcpt_t)z16f_timerisr, NULL); up_enable_irq(Z16F_IRQ_SYSTIMER); } diff --git a/arch/z80/src/ez80/ez80_emac.c b/arch/z80/src/ez80/ez80_emac.c index 71f1c4ee9c6..eab60f95dce 100644 --- a/arch/z80/src/ez80/ez80_emac.c +++ b/arch/z80/src/ez80/ez80_emac.c @@ -400,13 +400,13 @@ static int ez80emac_receive(struct ez80emac_driver_s *priv); /* Interrupt handling */ static void ez80emac_txinterrupt_work(FAR void *arg); -static int ez80emac_txinterrupt(int irq, FAR void *context); +static int ez80emac_txinterrupt(int irq, FAR void *context, FAR void *arg); static void ez80emac_rxinterrupt_work(FAR void *arg); -static int ez80emac_rxinterrupt(int irq, FAR void *context); +static int ez80emac_rxinterrupt(int irq, FAR void *context, FAR void *arg); static void ez80emac_sysinterrupt_work(FAR void *arg); -static int ez80emac_sysinterrupt(int irq, FAR void *context); +static int ez80emac_sysinterrupt(int irq, FAR void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -1581,7 +1581,7 @@ static void ez80emac_txinterrupt_work(FAR void *arg) * ****************************************************************************/ -static int ez80emac_txinterrupt(int irq, FAR void *context) +static int ez80emac_txinterrupt(int irq, FAR void *context, FAR void *arg) { FAR struct ez80emac_driver_s *priv = &g_emac; uint8_t istat; @@ -1683,7 +1683,7 @@ static void ez80emac_rxinterrupt_work(FAR void *arg) * ****************************************************************************/ -static int ez80emac_rxinterrupt(int irq, FAR void *context) +static int ez80emac_rxinterrupt(int irq, FAR void *context, FAR void *arg) { FAR struct ez80emac_driver_s *priv = &g_emac; @@ -1804,7 +1804,7 @@ static void ez80emac_sysinterrupt_work(FAR void *arg) * ****************************************************************************/ -static int ez80emac_sysinterrupt(int irq, FAR void *context) +static int ez80emac_sysinterrupt(int irq, FAR void *context, FAR void *arg) { FAR struct ez80emac_driver_s *priv = &g_emac; @@ -1980,7 +1980,8 @@ static void ez80emac_poll_expiry(int argc, wdparm_t arg, ...) * cycle. */ - (void)wd_start(priv->txpoll, EMAC_WDDELAY, ez80emac_poll_expiry, 1, arg); + (void)wd_start(priv->txpoll, EMAC_WDDELAY, ez80emac_poll_expiry, + 1, arg); } } @@ -2509,7 +2510,7 @@ int up_netinitialize(void) /* Attach IRQs */ - ret = irq_attach(EZ80_EMACSYS_IRQ, ez80emac_sysinterrupt); + ret = irq_attach(EZ80_EMACSYS_IRQ, ez80emac_sysinterrupt, NULL); if (ret < 0) { nerr("ERROR: Unable to attach IRQ %d\n", EZ80_EMACSYS_IRQ); @@ -2517,7 +2518,7 @@ int up_netinitialize(void) goto errout; } - ret = irq_attach(EZ80_EMACRX_IRQ, ez80emac_rxinterrupt); + ret = irq_attach(EZ80_EMACRX_IRQ, ez80emac_rxinterrupt, NULL); if (ret < 0) { nerr("ERROR: Unable to attach IRQ %d\n", EZ80_EMACRX_IRQ); @@ -2525,7 +2526,7 @@ int up_netinitialize(void) goto errout; } - ret = irq_attach(EZ80_EMACTX_IRQ, ez80emac_txinterrupt); + ret = irq_attach(EZ80_EMACTX_IRQ, ez80emac_txinterrupt, NULL); if (ret < 0) { nerr("ERROR: Unable to attach IRQ %d\n", EZ80_EMACTX_IRQ); diff --git a/arch/z80/src/ez80/ez80_serial.c b/arch/z80/src/ez80/ez80_serial.c index 4fbfdda7d57..fa64bb32c2b 100644 --- a/arch/z80/src/ez80/ez80_serial.c +++ b/arch/z80/src/ez80/ez80_serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/z80/src/ez08/ez80_serial.c * - * Copyright (C) 2008-2009, 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2008-2009, 2012, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -85,7 +85,7 @@ static int ez80_setup(struct uart_dev_s *dev); static void ez80_shutdown(struct uart_dev_s *dev); static int ez80_attach(struct uart_dev_s *dev); static void ez80_detach(struct uart_dev_s *dev); -static int ez80_interrupt(int irq, void *context); +static int ez80_interrupt(int irq, void *context, void *arg); static int ez80_ioctl(struct file *filep, int cmd, unsigned long arg); static int ez80_receive(struct uart_dev_s *dev, unsigned int *status); static void ez80_rxint(struct uart_dev_s *dev, bool enable); @@ -438,7 +438,7 @@ static int ez80_attach(struct uart_dev_s *dev) /* Attach the IRQ */ - return irq_attach(priv->irq, ez80_interrupt); + return irq_attach(priv->irq, ez80_interrupt, dev); } /**************************************************************************** @@ -471,29 +471,13 @@ static void ez80_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int ez80_interrupt(int irq, void *context) +static int ez80_interrupt(int irq, void *context, void *arg) { - struct uart_dev_s *dev = NULL; - struct ez80_dev_s *priv; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct ez80_dev_s *priv; volatile uint32_t cause; -#ifdef CONFIG_EZ80_UART0 - if (g_uart0priv.irq == irq) - { - dev = &g_uart0port; - } - else -#endif -#ifdef CONFIG_EZ80_UART1 - if (g_uart1priv.irq == irq) - { - dev = &g_uart1port; - } - else -#endif - { - PANIC(); - } + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct ez80_dev_s*)dev->priv; cause = ez80_serialin(priv, EZ80_UART_IIR) & EZ80_UARTIIR_CAUSEMASK; diff --git a/arch/z80/src/ez80/ez80_timerisr.c b/arch/z80/src/ez80/ez80_timerisr.c index ec21d58382b..16730bf5984 100644 --- a/arch/z80/src/ez80/ez80_timerisr.c +++ b/arch/z80/src/ez80/ez80_timerisr.c @@ -62,7 +62,7 @@ * ****************************************************************************/ -static int ez80_timerisr(int irq, chipreg_t *regs) +static int ez80_timerisr(int irq, chipreg_t *regs, void *arg) { /* Read the appropriate timer0 register to clear the interrupt */ @@ -110,7 +110,7 @@ void z80_timer_initialize(void) /* Attach system timer interrupts */ - irq_attach(EZ80_IRQ_SYSTIMER, (xcpt_t)ez80_timerisr); + irq_attach(EZ80_IRQ_SYSTIMER, (xcpt_t)ez80_timerisr, NULL); /* Set up the timer reload value */ /* Write to the timer reload register to set the reload value. diff --git a/arch/z80/src/z180/z180_timerisr.c b/arch/z80/src/z180/z180_timerisr.c index 29984d77bd2..0e1ac95da01 100644 --- a/arch/z80/src/z180/z180_timerisr.c +++ b/arch/z80/src/z180/z180_timerisr.c @@ -84,7 +84,7 @@ * ****************************************************************************/ -static int z180_timerisr(int irq, chipreg_t *regs) +static int z180_timerisr(int irq, chipreg_t *regs, void *arg) { /* "When TMDR0 decrements to 0, TIF0 is set to 1. This generates an interrupt * request if enabled by TIE0 = 1. TIF0 is reset to 0 when TCR is read and @@ -142,7 +142,7 @@ void z80_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(Z180_PRT0, (xcpt_t)z180_timerisr); + (void)irq_attach(Z180_PRT0, (xcpt_t)z180_timerisr, NULL); /* And enable the timer interrupt */ diff --git a/arch/z80/src/z8/z8_serial.c b/arch/z80/src/z8/z8_serial.c index f7fe721ac03..6f6df0efae9 100644 --- a/arch/z80/src/z8/z8_serial.c +++ b/arch/z80/src/z8/z8_serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/z80/src/z8/z8_serial.c * - * Copyright (C) 2008-2009, 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2008-2009, 2012, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -96,8 +96,8 @@ static int z8_setup(FAR struct uart_dev_s *dev); static void z8_shutdown(FAR struct uart_dev_s *dev); static int z8_attach(FAR struct uart_dev_s *dev); static void z8_detach(FAR struct uart_dev_s *dev); -static int z8_rxinterrupt(int irq, FAR void *context); -static int z8_txinterrupt(int irq, FAR void *context); +static int z8_rxinterrupt(int irq, FAR void *context, FAR void *arg); +static int z8_txinterrupt(int irq, FAR void *context, FAR void *arg); static int z8_ioctl(FAR struct file *filep, int cmd, unsigned long arg); static int z8_receive(FAR struct uart_dev_s *dev, FAR uint32_t *status); static void z8_rxint(FAR struct uart_dev_s *dev, bool enable); @@ -446,12 +446,12 @@ static int z8_attach(FAR struct uart_dev_s *dev) /* Attach the RX IRQ */ - ret = irq_attach(priv->rxirq, z8_rxinterrupt); + ret = irq_attach(priv->rxirq, z8_rxinterrupt, dev); if (ret == OK) { /* Attach the TX IRQ */ - ret = irq_attach(priv->txirq, z8_txinterrupt); + ret = irq_attach(priv->txirq, z8_txinterrupt, dev); if (ret != OK) { irq_detach(priv->rxirq); @@ -488,25 +488,13 @@ static void z8_detach(FAR struct uart_dev_s *dev) * ****************************************************************************/ -static int z8_rxinterrupt(int irq, FAR void *context) +static int z8_rxinterrupt(int irq, FAR void *context, FAR void *arg) { - struct uart_dev_s *dev = NULL; - struct z8_uart_s *priv; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct z8_uart_s *priv; uint8_t status; - if (g_uart1priv.rxirq == irq) - { - dev = &g_uart1port; - } - else if (g_uart0priv.rxirq == irq) - { - dev = &g_uart0port; - } - else - { - PANIC(); - } - + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct z8_uart_s*)dev->priv; /* Check the LIN-UART status 0 register to determine whether the source of @@ -537,25 +525,13 @@ static int z8_rxinterrupt(int irq, FAR void *context) * ****************************************************************************/ -static int z8_txinterrupt(int irq, FAR void *context) +static int z8_txinterrupt(int irq, FAR void *context, FAR void *arg) { - struct uart_dev_s *dev = NULL; - struct z8_uart_s *priv; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct z8_uart_s *priv; uint8_t status; - if (g_uart1priv.txirq == irq) - { - dev = &g_uart1port; - } - else if (g_uart0priv.txirq == irq) - { - dev = &g_uart0port; - } - else - { - PANIC(); - } - + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct z8_uart_s*)dev->priv; /* Verify that the transmit data register is empty */ diff --git a/arch/z80/src/z8/z8_timerisr.c b/arch/z80/src/z8/z8_timerisr.c index b399c12d8b0..e3fd1e48580 100644 --- a/arch/z80/src/z8/z8_timerisr.c +++ b/arch/z80/src/z8/z8_timerisr.c @@ -70,7 +70,7 @@ extern uint32_t get_freq(void); * ****************************************************************************/ -static int z8_timerisr(int irq, uint32_t *regs) +static int z8_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -137,7 +137,7 @@ void z80_timer_initialize(void) /* Attach and enable the timer interrupt (leaving at priority 0 */ - irq_attach(Z8_IRQ_SYSTIMER, (xcpt_t)z8_timerisr); + irq_attach(Z8_IRQ_SYSTIMER, (xcpt_t)z8_timerisr, NULL); up_enable_irq(Z8_IRQ_SYSTIMER); } diff --git a/configs/Kconfig b/configs/Kconfig index 2eb23b0fe5c..42a35438668 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -71,12 +71,12 @@ config ARCH_BOARD_CLOUDCTRL board design. config ARCH_BOARD_DEMOS92S12NEC64 - bool "Freescale DMO9S12NE64 board" + bool "NXP/FreeScale DMO9S12NE64 board" depends on ARCH_CHIP_MCS92S12NEC64 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS ---help--- - Freescale DMO9S12NE64 board based on the MC9S12NE64 hcs12 cpu. This + NXP/FreeScale DMO9S12NE64 board based on the MC9S12NE64 hcs12 cpu. This port uses the m9s12x GCC toolchain. STATUS: (Still) under development; it is code complete but has not yet been verified. @@ -185,7 +185,7 @@ config ARCH_BOARD_FREEDOM_K64F select ARCH_HAVE_IRQBUTTONS ---help--- development board. - This port uses the FreeScale FREEDOM-K64F development board. This + This port uses the NXP/FreeScale FREEDOM-K64F development board. This board uses the Kinetis K64 MK64FN1M0VLL12 Cortex-M4 MCU. config ARCH_BOARD_FREEDOM_K66F @@ -196,23 +196,23 @@ config ARCH_BOARD_FREEDOM_K66F select ARCH_HAVE_IRQBUTTONS ---help--- development board. - This port uses the FreeScale FREEDOM-K66F development board. This + This port uses the NXP/FreeScale FREEDOM-K66F development board. This board uses the Kinetis K66 MK66FN2M0VMD18 Cortex-M4 MCU. config ARCH_BOARD_FREEDOM_KL25Z - bool "Freescale Freedom KL25Z" + bool "NXP/FreeScale Freedom KL25Z" depends on ARCH_CHIP_MKL25Z128 select ARCH_HAVE_LEDS ---help--- - This is the configuration for the Freescale Freedom KL25Z board. This + This is the configuration for the NXP/FreeScale Freedom KL25Z board. This board has the K25Z120LE3AN chip with a built-in SDA debugger. config ARCH_BOARD_FREEDOM_KL26Z - bool "Freescale Freedom KL26Z" + bool "NXP/FreeScale Freedom KL26Z" depends on ARCH_CHIP_MKL26Z128 select ARCH_HAVE_LEDS ---help--- - This is the configuration for the Freescale Freedom KL26Z board. This + This is the configuration for the NXP/FreeScale Freedom KL26Z board. This board has the K26Z128VLH4 chip with a built-in SDA debugger. config ARCH_BOARD_HYMINI_STM32V @@ -235,13 +235,13 @@ config ARCH_BOARD_LINCOLN60 Micromint Lincoln 60 board using the NXP LPC1769 MCU. config ARCH_BOARD_KWIKSTIK_K40 - bool "FreeScale KwikStik-K40 development board" + bool "NXP/FreeScale KwikStik-K40 development board" depends on ARCH_CHIP_MK40X256VLQ100 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS select ARCH_HAVE_IRQBUTTONS ---help--- - Kinetis K40 Cortex-M4 MCU. This port uses the FreeScale KwikStik-K40 + Kinetis K40 Cortex-M4 MCU. This port uses the NXP/FreeScale KwikStik-K40 development board. config ARCH_BOARD_LAUNCHXL_TMS57004 @@ -387,7 +387,7 @@ config ARCH_BOARD_MX1ADS select ARCH_HAVE_LEDS ---help--- This is a port to the Motorola MX1ADS development board. That board - is based on the Freescale i.MX1 processor. The i.MX1 is an ARM920T. + is based on the NXP/FreeScale i.MX1 processor. The i.MX1 is an ARM920T. STATUS: This port is nearly code complete but was never fully integrated due to tool-related issues. @@ -714,6 +714,15 @@ config ARCH_BOARD_NUCLEO_F303RE ---help--- STMicro Nucleo F303RE board based on the STMicro STM32F303RET6 MCU. +config ARCH_BOARD_NUCLEO_F334R8 + bool "STM32F334 Nucleo F334R8" + depends on ARCH_CHIP_STM32F334R8 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + STMicro Nucleo F334R8 board based on the STMicro STM32F334R8 MCU. + config ARCH_BOARD_NUCLEO_F401RE bool "STM32F401 Nucleo F401RE" depends on ARCH_CHIP_STM32F401RE @@ -1180,7 +1189,7 @@ config ARCH_BOARD_CC3200_LAUNCHPAD Tiva CC3200 Launchpad. config ARCH_BOARD_TWR_K60N512 - bool "FreeScale TWR-K60N512d evelopment board" + bool "FreeScale TWR-K60N512 development board" depends on ARCH_CHIP_MK60N512VMD100 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS @@ -1189,6 +1198,16 @@ config ARCH_BOARD_TWR_K60N512 Kinetis K60 Cortex-M4 MCU. This port uses the FreeScale TWR-K60N512 development board. +config ARCH_BOARD_TWR_K64F120M + bool "Freescale TWR-K64F120M development board" + depends on ARCH_CHIP_MK64FN1M0VMD12 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + Kinetis K64 Cortex-M4 MCU. This port uses the Freescale TWR-K64F120M + development board. + config ARCH_BOARD_U_BLOX_C027 bool "u-blox C027" depends on ARCH_CHIP_LPC1768 @@ -1437,6 +1456,7 @@ config ARCH_BOARD default "pic32mz-starterkit" if ARCH_BOARD_PIC32MZ_STARTERKIT default "nucleo-144" if ARCH_BOARD_NUCLEO_144 default "nucleo-f303re" if ARCH_BOARD_NUCLEO_F303RE + default "nucleo-f334r8" if ARCH_BOARD_NUCLEO_F334R8 default "nucleo-f4x1re" if ARCH_BOARD_NUCLEO_F401RE || ARCH_BOARD_NUCLEO_F411RE default "nucleo-l476rg" if ARCH_BOARD_NUCLEO_L476RG default "qemu-i486" if ARCH_BOARD_QEMU_I486 @@ -1484,6 +1504,7 @@ config ARCH_BOARD default "tm4c1294-launchpad" if ARCH_BOARD_TM4C1294_LAUNCHPAD default "cc3200-launchpad" if ARCH_BOARD_CC3200_LAUNCHPAD default "twr-k60n512" if ARCH_BOARD_TWR_K60N512 + default "twr-k64f120m" if ARCH_BOARD_TWR_K64F120M default "u-blox-c027" if ARCH_BOARD_U_BLOX_C027 default "ubw32" if ARCH_BOARD_UBW32 default "us7032evb1" if ARCH_BOARD_US7032EVB1 @@ -1737,6 +1758,9 @@ endif if ARCH_BOARD_NUCLEO_F303RE source "configs/nucleo-f303re/Kconfig" endif +if ARCH_BOARD_NUCLEO_F334R8 +source "configs/nucleo-f334r8/Kconfig" +endif if ARCH_BOARD_NUCLEO_F401RE || ARCH_BOARD_NUCLEO_F411RE source "configs/nucleo-f4x1re/Kconfig" endif @@ -1872,6 +1896,9 @@ endif if ARCH_BOARD_TWR_K60N512 source "configs/twr-k60n512/Kconfig" endif +if ARCH_BOARD_TWR_K64F120M +source "configs/twr-k64f120m/Kconfig" +endif if ARCH_BOARD_U_BLOX_C027 source "configs/u-blox-c027/Kconfig" endif diff --git a/configs/README.txt b/configs/README.txt index 80c0270ba26..a4ce0ded195 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -207,7 +207,7 @@ configs/cloudctrl the STM32F107VC MCU. configs/demo9s12ne64 - Freescale DMO9S12NE64 board based on the MC9S12NE64 hcs12 cpu. This + NXP/FreeScale DMO9S12NE64 board based on the MC9S12NE64 hcs12 cpu. This port uses the m9s12x GCC toolchain. STATUS: (Still) under development; it is code complete but has not yet been verified. @@ -266,12 +266,12 @@ configs/fire-stm32v2 the boards are supported but only version 2 has been tested. configs/freedom-k64f - This port uses the FreeScale FREEDOM-K64F development board. This board + This port uses the NXP/FreeScale FREEDOM-K64F development board. This board uses the Kinetis K64 MK64FN1M0VLL12 Cortex-M4 MCU. configs/freedom-kl25z configs/freedom-kl26z - These configurations are for the Freescale Freedom KL25Z and very similar + These configurations are for the NXP/FreeScale Freedom KL25Z and very similar KL26Z board. The Freedom-KL25Z features the K25Z120LE3AN chip; the Freedom-KL26Z has the K26Z128VLH4 chip. These are separate configurations because of minor differences in the on-board logic. Both include a @@ -282,7 +282,7 @@ configs/hymini-stm32v STM32F103VCT chip. configs/kwikstik-k40. - Kinetis K40 Cortex-M4 MCU. This port uses the FreeScale KwikStik-K40 + Kinetis K40 Cortex-M4 MCU. This port uses the NXP/FreeScale KwikStik-K40 development board. configs/launchxl-tms57004 @@ -375,7 +375,7 @@ configs/moxa configs/mx1ads This is a port to the Motorola MX1ADS development board. That board - is based on the Freescale i.MX1 processor. The i.MX1 is an ARM920T. + is based on the NXP/FreeScale i.MX1 processor. The i.MX1 is an ARM920T. STATUS: This port is nearly code complete but was never fully integrated due to tool-related issues. @@ -737,6 +737,10 @@ configs/twr-k60n512 Kinetis K60 Cortex-M4 MCU. This port uses the FreeScale TWR-K60N512 development board. +configs/twr-k64f120m + Kinetis K64 Cortex-M4 MCU. This port uses the FreeScale TWR-K64F120M + development board. + configs/ubw32 This is the port to the Sparkfun UBW32 board. This port uses the original v2.4 diff --git a/configs/arduino-due/src/sam_touchscreen.c b/configs/arduino-due/src/sam_touchscreen.c index d16184a6cd0..b93aa11f688 100644 --- a/configs/arduino-due/src/sam_touchscreen.c +++ b/configs/arduino-due/src/sam_touchscreen.c @@ -267,7 +267,7 @@ static int tsc_attach(FAR struct ads7843e_config_s *state, xcpt_t isr) /* Attach the XPT2046 interrupt */ iinfo("Attaching %p to IRQ %d\n", isr, SAM_TSC_IRQ); - return irq_attach(SAM_TSC_IRQ, isr); + return irq_attach(SAM_TSC_IRQ, isr, NULL); } static void tsc_enable(FAR struct ads7843e_config_s *state, bool enable) diff --git a/configs/avr32dev1/src/avr32_buttons.c b/configs/avr32dev1/src/avr32_buttons.c index 49a227d8a10..228a43098a9 100644 --- a/configs/avr32dev1/src/avr32_buttons.c +++ b/configs/avr32dev1/src/avr32_buttons.c @@ -55,14 +55,6 @@ #ifdef CONFIG_ARCH_BUTTONS -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -77,7 +69,7 @@ #if defined(CONFIG_AVR32_GPIOIRQ) && defined(CONFIG_ARCH_IRQBUTTONS) && \ (defined(CONFIG_AVR32DEV_BUTTON1_IRQ) || defined(CONFIG_AVR32DEV_BUTTON2_IRQ)) -static xcpt_t board_button_irqx(int irq, xcpt_t irqhandler) +static xcpt_t board_button_irqx(int irq, xcpt_t irqhandler, void *arg) { xcpt_t oldhandler; @@ -164,19 +156,19 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_AVR32_GPIOIRQ) && defined(CONFIG_ARCH_IRQBUTTONS) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { #ifdef CONFIG_AVR32DEV_BUTTON1_IRQ if (id == BUTTON1) { - return board_button_irqx(GPIO_BUTTON1_IRQ, irqhandler); + return board_button_irqx(GPIO_BUTTON1_IRQ, irqhandler, arg); } else #endif #ifdef CONFIG_AVR32DEV_BUTTON2_IRQ if (id == BUTTON2) { - return board_button_irqx(GPIO_BUTTON2_IRQ, irqhandler); + return board_button_irqx(GPIO_BUTTON2_IRQ, irqhandler, arg); } else #endif diff --git a/configs/bambino-200e/netnsh/defconfig b/configs/bambino-200e/netnsh/defconfig index f14b084712a..231bc772b6e 100644 --- a/configs/bambino-200e/netnsh/defconfig +++ b/configs/bambino-200e/netnsh/defconfig @@ -852,7 +852,6 @@ CONFIG_LIBM=y # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/bambino-200e/src/lpc43_buttons.c b/configs/bambino-200e/src/lpc43_buttons.c index 95755ccb791..dbaf33d1b53 100644 --- a/configs/bambino-200e/src/lpc43_buttons.c +++ b/configs/bambino-200e/src/lpc43_buttons.c @@ -172,7 +172,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC43_GPIO_IRQ) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; irqstate_t flags; @@ -200,7 +200,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) { /* Attach then enable the new interrupt handler */ - (void)irq_attach(irq, irqhandler); + (void)irq_attach(irq, irqhandler, NULL); up_enable_irq(irq); } else diff --git a/configs/bambino-200e/usbnsh/defconfig b/configs/bambino-200e/usbnsh/defconfig index addc5c43b59..646cdbadd64 100644 --- a/configs/bambino-200e/usbnsh/defconfig +++ b/configs/bambino-200e/usbnsh/defconfig @@ -726,7 +726,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/cloudctrl/src/stm32_buttons.c b/configs/cloudctrl/src/stm32_buttons.c index 43a090b05b2..5766e8ca331 100644 --- a/configs/cloudctrl/src/stm32_buttons.c +++ b/configs/cloudctrl/src/stm32_buttons.c @@ -159,7 +159,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -167,8 +167,10 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); } + return oldhandler; } #endif diff --git a/configs/dk-tm4c129x/src/tm4c_buttons.c b/configs/dk-tm4c129x/src/tm4c_buttons.c index 829891e7d5e..69b1766a116 100644 --- a/configs/dk-tm4c129x/src/tm4c_buttons.c +++ b/configs/dk-tm4c129x/src/tm4c_buttons.c @@ -150,7 +150,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_TIVA_GPIOP_IRQS) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { static xcpt_t handler = NULL; xcpt_t oldhandler = handler; @@ -175,7 +175,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (irqhandler) { - ret = irq_attach(IRQ_SW4, irqhandler); + ret = irq_attach(IRQ_SW4, irqhandler, NULL); if (ret == OK) { handler = irqhandler; diff --git a/configs/ez80f910200zco/src/ez80_buttons.c b/configs/ez80f910200zco/src/ez80_buttons.c index 1fbfdcf2ad8..6bc2aa9462b 100644 --- a/configs/ez80f910200zco/src/ez80_buttons.c +++ b/configs/ez80f910200zco/src/ez80_buttons.c @@ -126,9 +126,9 @@ void board_button_initialize(void) /* Attach GIO interrupts */ - irq_attach(EZ80_PB_IRQ, up_PBinterrupt); - irq_attach(EZ80_PB1_IRQ, up_pb1interrupt); - irq_attach(EZ80_PB2_IRQ, up_pb2interrupt); + irq_attach(EZ80_PB_IRQ, up_PBinterrupt, NULL); + irq_attach(EZ80_PB1_IRQ, up_pb1interrupt, NULL); + irq_attach(EZ80_PB2_IRQ, up_pb2interrupt, NULL); /* Configure PB0,1,2 as interrupt, rising edge */ diff --git a/configs/fire-stm32v2/nsh/defconfig b/configs/fire-stm32v2/nsh/defconfig index 73ae596e633..3495a7f0b8c 100644 --- a/configs/fire-stm32v2/nsh/defconfig +++ b/configs/fire-stm32v2/nsh/defconfig @@ -1176,7 +1176,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/fire-stm32v2/src/stm32_buttons.c b/configs/fire-stm32v2/src/stm32_buttons.c index fe1d35f5165..aac98c1973a 100644 --- a/configs/fire-stm32v2/src/stm32_buttons.c +++ b/configs/fire-stm32v2/src/stm32_buttons.c @@ -134,7 +134,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { uint16_t gpio; @@ -151,7 +151,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) return NULL; } - return stm32_gpiosetevent(gpio, true, true, true, irqhandler); + return stm32_gpiosetevent(gpio, true, true, true, irqhandler, arg); } #endif #endif /* CONFIG_ARCH_BUTTONS */ diff --git a/configs/fire-stm32v2/src/stm32_enc28j60.c b/configs/fire-stm32v2/src/stm32_enc28j60.c index cd5ee2c6b31..9ac4040e4ba 100644 --- a/configs/fire-stm32v2/src/stm32_enc28j60.c +++ b/configs/fire-stm32v2/src/stm32_enc28j60.c @@ -159,12 +159,14 @@ static void up_enable(FAR const struct enc_lower_s *lower) FAR struct stm32_lower_s *priv = (FAR struct stm32_lower_s *)lower; DEBUGASSERT(priv->handler); - (void)stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, priv->handler); + (void)stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, + priv->handler, NULL); } static void up_disable(FAR const struct enc_lower_s *lower) { - (void)stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, NULL); + (void)stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, + NULL, NULL); } /**************************************************************************** diff --git a/configs/freedom-k64f/nsh/defconfig b/configs/freedom-k64f/nsh/defconfig index 94a2d1e639b..f8371fbefa8 100644 --- a/configs/freedom-k64f/nsh/defconfig +++ b/configs/freedom-k64f/nsh/defconfig @@ -709,7 +709,6 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/freedom-k64f/src/k64_buttons.c b/configs/freedom-k64f/src/k64_buttons.c index f1f4ba88477..659b55497b5 100644 --- a/configs/freedom-k64f/src/k64_buttons.c +++ b/configs/freedom-k64f/src/k64_buttons.c @@ -133,7 +133,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler; uint32_t pinset; diff --git a/configs/freedom-k64f/src/k64_sdhc.c b/configs/freedom-k64f/src/k64_sdhc.c index 4083235048b..d9a25eb19b8 100644 --- a/configs/freedom-k64f/src/k64_sdhc.c +++ b/configs/freedom-k64f/src/k64_sdhc.c @@ -139,7 +139,7 @@ static void k64_mediachange(void) * Name: k64_cdinterrupt ****************************************************************************/ -static int k64_cdinterrupt(int irq, FAR void *context) +static int k64_cdinterrupt(int irq, FAR void *context, FAR void *arg) { /* All of the work is done by k64_mediachange() */ @@ -169,7 +169,7 @@ int k64_sdhc_initialize(void) /* Attached the card detect interrupt (but don't enable it yet) */ - kinetis_pinirqattach(GPIO_SD_CARDDETECT, k64_cdinterrupt); + kinetis_pinirqattach(GPIO_SD_CARDDETECT, k64_cdinterrupt, NULL); /* Configure the write protect GPIO -- None */ diff --git a/configs/freedom-k66f/include/board.h b/configs/freedom-k66f/include/board.h index 97d3bf4122e..79d2fa00056 100644 --- a/configs/freedom-k66f/include/board.h +++ b/configs/freedom-k66f/include/board.h @@ -42,11 +42,12 @@ ************************************************************************************/ #include - #ifndef __ASSEMBLY__ # include #endif +#include + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ @@ -59,10 +60,9 @@ * is 12 MHz oscillator * * X501 a High-frequency, low-power Xtal - * */ -#define BOARD_EXTAL_LP 1 +#define BOARD_EXTAL_LP 1 #define BOARD_EXTAL_FREQ 12000000 /* 12MHz Oscillator */ #define BOARD_XTAL32_FREQ 32768 /* 32KHz RTC Oscillator */ @@ -98,10 +98,50 @@ #define BOARD_OUTDIV3 3 /* FlexBus = MCG / 3, 60 MHz */ #define BOARD_OUTDIV4 7 /* Flash clock = MCG / 7, 25.7 MHz */ -#define BOARD_CORECLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV1) -#define BOARD_BUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV2) -#define BOARD_FLEXBUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV3) -#define BOARD_FLASHCLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV4) +#define BOARD_CORECLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV1) +#define BOARD_BUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV2) +#define BOARD_FLEXBUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV3) +#define BOARD_FLASHCLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV4) + +/* Use BOARD_MCG_FREQ as the output SIM_SOPT2 MUX selected by + * SIM_SOPT2[PLLFLLSEL] + */ + +#define BOARD_SOPT2_PLLFLLSEL SIM_SOPT2_PLLFLLSEL_MCGPLLCLK +#define BOARD_SOPT2_FREQ BOARD_MCG_FREQ + +/* N.B. The above BOARD_SOPT2_FREQ precludes use of USB with a 12 Mhz Xtal + * Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ] + * SIM_CLKDIV2_FREQ = BOARD_SOPT2_FREQ × [ (USBFRAC+1) / (USBDIV+1) ] + * 48Mhz = 168Mhz X [(1 + 1) / (6 + 1)] + * 48Mhz = 168Mhz / (6 + 1) * (1 + 1) + */ + +#if (BOARD_MCG_FREQ == 168000000L) +# define BOARD_SIM_CLKDIV2_USBFRAC 2 +# define BOARD_SIM_CLKDIV2_USBDIV 7 +# define BOARD_SIM_CLKDIV2_FREQ (BOARD_SOPT2_FREQ / \ + BOARD_SIM_CLKDIV2_USBDIV * \ + BOARD_SIM_CLKDIV2_USBFRAC) +#endif + +/* Divider output clock = Divider input clock * ((PLLFLLFRAC+1)/(PLLFLLDIV+1)) + * SIM_CLKDIV3_FREQ = BOARD_SOPT2_FREQ × [ (PLLFLLFRAC+1) / (PLLFLLDIV+1)] + * 90 Mhz = 180 Mhz X [(0 + 1) / (1 + 1)] + * 90 Mhz = 180 Mhz / (1 + 1) * (0 + 1) + */ + +#define BOARD_SIM_CLKDIV3_PLLFLLFRAC 1 +#define BOARD_SIM_CLKDIV3_PLLFLLDIV 2 +#define BOARD_SIM_CLKDIV3_FREQ (BOARD_SOPT2_FREQ / \ + BOARD_SIM_CLKDIV3_PLLFLLDIV * \ + BOARD_SIM_CLKDIV3_PLLFLLFRAC) + +#define BOARD_LPUART0_CLKSRC SIM_SOPT2_LPUARTSRC_MCGCLK +#define BOARD_LPUART0_FREQ BOARD_SIM_CLKDIV3_FREQ + +#define BOARD_TPM_CLKSRC SIM_SOPT2_TPMSRC_MCGCLK +#define BOARD_TPM_FREQ BOARD_SIM_CLKDIV3_FREQ /* SDHC clocking ********************************************************************/ @@ -276,6 +316,18 @@ #define PIN_UART4_RX PIN_UART4_RX_1 #define PIN_UART4_TX PIN_UART4_TX_1 +/* LPUART + * + * J1 Pin Name K66 Name + * -------- ------------ ------ --------- + * 7 I2S_RX_BCLK PTE9 LPUART0_RX + * 11 I2S_RX_FS PTE8 LPUART0_TX + * -------- ----- ------ --------- + */ + +#define PIN_LPUART0_RX PIN_LPUART0_RX_1 +#define PIN_LPUART0_TX PIN_LPUART0_TX_1 + /* I2C INERTIAL SENSOR (Gyroscope) * * Pin Name K66 Name diff --git a/configs/freedom-k66f/netnsh/defconfig b/configs/freedom-k66f/netnsh/defconfig index f7da08de50c..b31db4cfb09 100644 --- a/configs/freedom-k66f/netnsh/defconfig +++ b/configs/freedom-k66f/netnsh/defconfig @@ -916,7 +916,6 @@ CONFIG_ARCH_LOWPUTC=y # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set diff --git a/configs/freedom-k66f/nsh/defconfig b/configs/freedom-k66f/nsh/defconfig index 3da05837dad..c8032c952b8 100644 --- a/configs/freedom-k66f/nsh/defconfig +++ b/configs/freedom-k66f/nsh/defconfig @@ -802,7 +802,6 @@ CONFIG_ARCH_LOWPUTC=y # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set diff --git a/configs/freedom-k66f/src/k66_buttons.c b/configs/freedom-k66f/src/k66_buttons.c index 7cb132bd2b3..caa7da5bad7 100644 --- a/configs/freedom-k66f/src/k66_buttons.c +++ b/configs/freedom-k66f/src/k66_buttons.c @@ -137,7 +137,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler; uint32_t pinset; @@ -163,7 +163,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) * Attach the new button handler. */ - oldhandler = kinetis_pinirqattach(pinset, irqhandler); + oldhandler = kinetis_pinirqattach(pinset, irqhandler, NULL); /* Then make sure that interrupts are enabled on the pin */ diff --git a/configs/freedom-k66f/src/k66_sdhc.c b/configs/freedom-k66f/src/k66_sdhc.c index 899cc17870b..b89c9e93da9 100644 --- a/configs/freedom-k66f/src/k66_sdhc.c +++ b/configs/freedom-k66f/src/k66_sdhc.c @@ -140,7 +140,7 @@ static void k66_mediachange(void) * Name: k66_cdinterrupt ****************************************************************************/ -static int k66_cdinterrupt(int irq, FAR void *context) +static int k66_cdinterrupt(int irq, FAR void *context, FAR void *arg) { /* All of the work is done by k66_mediachange() */ @@ -170,7 +170,7 @@ int k66_sdhc_initialize(void) /* Attached the card detect interrupt (but don't enable it yet) */ - kinetis_pinirqattach(GPIO_SD_CARDDETECT, k66_cdinterrupt); + kinetis_pinirqattach(GPIO_SD_CARDDETECT, k66_cdinterrupt, NULL); /* Configure the write protect GPIO -- None */ diff --git a/configs/freedom-kl25z/src/kl_wifi.c b/configs/freedom-kl25z/src/kl_wifi.c index 56873885718..0bf17b1c8a0 100644 --- a/configs/freedom-kl25z/src/kl_wifi.c +++ b/configs/freedom-kl25z/src/kl_wifi.c @@ -121,7 +121,8 @@ struct kl_config_s * probe - Debug support */ -static int wl_attach_irq(FAR struct cc3000_config_s *state, xcpt_t handler); +static int wl_attach_irq(FAR struct cc3000_config_s *state, xcpt_t handler, + FAR void *arg); static void wl_enable_irq(FAR struct cc3000_config_s *state, bool enable); static void wl_clear_irq(FAR struct cc3000_config_s *state); static void wl_select(FAR struct cc3000_config_s *state, bool enable); @@ -160,6 +161,7 @@ static struct kl_config_s g_cc3000_info = .dev.probe = probe, /* This is used for debugging */ #endif .handler = NULL, + .arg = NULL, }; /**************************************************************************** @@ -182,13 +184,15 @@ static struct kl_config_s g_cc3000_info = * probe - Debug support */ -static int wl_attach_irq(FAR struct cc3000_config_s *state, xcpt_t handler) +static int wl_attach_irq(FAR struct cc3000_config_s *state, xcpt_t handler, + FAR void *arg) { FAR struct kl_config_s *priv = (FAR struct kl_config_s *)state; /* Just save the handler for use when the interrupt is enabled */ priv->handler = handler; + priv->arg = arg; return OK; } diff --git a/configs/hymini-stm32v/nsh/defconfig b/configs/hymini-stm32v/nsh/defconfig index 5bdfc7afe64..c569511e342 100644 --- a/configs/hymini-stm32v/nsh/defconfig +++ b/configs/hymini-stm32v/nsh/defconfig @@ -923,7 +923,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/hymini-stm32v/nsh2/defconfig b/configs/hymini-stm32v/nsh2/defconfig index d5127eca8de..b27306fb538 100644 --- a/configs/hymini-stm32v/nsh2/defconfig +++ b/configs/hymini-stm32v/nsh2/defconfig @@ -1139,7 +1139,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/hymini-stm32v/src/stm32_appinit.c b/configs/hymini-stm32v/src/stm32_appinit.c index 725a2126190..2697adcb213 100644 --- a/configs/hymini-stm32v/src/stm32_appinit.c +++ b/configs/hymini-stm32v/src/stm32_appinit.c @@ -125,7 +125,7 @@ static FAR struct sdio_dev_s *g_sdiodev; ****************************************************************************/ #ifdef NSH_HAVEMMCSD -static int nsh_cdinterrupt(int irq, FAR void *context) +static int nsh_cdinterrupt(int irq, FAR void *context, FAR void *arg) { static bool inserted = 0xff; /* Impossible value */ bool present; @@ -182,7 +182,7 @@ int board_app_initialize(uintptr_t arg) /* Register an interrupt handler for the card detect pin */ - stm32_gpiosetevent(GPIO_SD_CD, true, true, true, nsh_cdinterrupt); + stm32_gpiosetevent(GPIO_SD_CD, true, true, true, nsh_cdinterrupt, NULL); /* Mount the SDIO-based MMC/SD block driver */ diff --git a/configs/hymini-stm32v/src/stm32_buttons.c b/configs/hymini-stm32v/src/stm32_buttons.c index a31b38f923a..578b2fa5b43 100644 --- a/configs/hymini-stm32v/src/stm32_buttons.c +++ b/configs/hymini-stm32v/src/stm32_buttons.c @@ -128,7 +128,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; uint32_t pinset = GPIO_BTN_KEYA; @@ -139,8 +139,10 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) } if (id < 2) { - oldhandler = stm32_gpiosetevent(pinset, true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(pinset, true, true, true, + irqhandler, arg); } + return oldhandler; } #endif diff --git a/configs/hymini-stm32v/src/stm32_ts.c b/configs/hymini-stm32v/src/stm32_ts.c index 16f91c3fd0e..e8889571d2b 100644 --- a/configs/hymini-stm32v/src/stm32_ts.c +++ b/configs/hymini-stm32v/src/stm32_ts.c @@ -98,7 +98,7 @@ static int hymini_ts_irq_attach(FAR struct ads7843e_config_s *state, xcpt_t isr) iinfo("hymini_ts_irq_attach\n"); tc_isr = isr; - stm32_gpiosetevent(GPIO_TS_IRQ, true, true, true, isr); + stm32_gpiosetevent(GPIO_TS_IRQ, true, true, true, isr, NULL); return OK; } @@ -108,7 +108,7 @@ static void hymini_ts_irq_enable(FAR struct ads7843e_config_s *state, { iinfo("%d\n", enable); - stm32_gpiosetevent(GPIO_TS_IRQ, true, true, true, enable? tc_isr:NULL); + stm32_gpiosetevent(GPIO_TS_IRQ, true, true, true, enable ? tc_isr : NULL, NULL); } /* Acknowledge/clear any pending GPIO interrupt */ diff --git a/configs/hymini-stm32v/usbmsc/defconfig b/configs/hymini-stm32v/usbmsc/defconfig index cc248064cf2..b69eb4a9acb 100644 --- a/configs/hymini-stm32v/usbmsc/defconfig +++ b/configs/hymini-stm32v/usbmsc/defconfig @@ -976,7 +976,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/kwikstik-k40/src/k40_appinit.c b/configs/kwikstik-k40/src/k40_appinit.c index befe905af92..a336d96e473 100644 --- a/configs/kwikstik-k40/src/k40_appinit.c +++ b/configs/kwikstik-k40/src/k40_appinit.c @@ -217,7 +217,7 @@ int board_app_initialize(uintptr_t arg) /* Attached the card detect interrupt (but don't enable it yet) */ kinetis_pinconfig(GPIO_SD_CARDDETECT); - kinetis_pinirqattach(GPIO_SD_CARDDETECT, kinetis_cdinterrupt); + kinetis_pinirqattach(GPIO_SD_CARDDETECT, kinetis_cdinterrupt, NULL); /* Mount the SDHC-based MMC/SD block driver */ /* First, get an instance of the SDHC interface */ diff --git a/configs/kwikstik-k40/src/k40_buttons.c b/configs/kwikstik-k40/src/k40_buttons.c index f3bf65d3d14..3fff4a2333f 100644 --- a/configs/kwikstik-k40/src/k40_buttons.c +++ b/configs/kwikstik-k40/src/k40_buttons.c @@ -117,7 +117,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { /* The KwikStik-K40 board has no standard GPIO contact buttons */ diff --git a/configs/launchxl-tms57004/src/tms570_buttons.c b/configs/launchxl-tms57004/src/tms570_buttons.c index 2d2741280dd..68c8231926c 100644 --- a/configs/launchxl-tms57004/src/tms570_buttons.c +++ b/configs/launchxl-tms57004/src/tms570_buttons.c @@ -85,7 +85,7 @@ static xcpt_t g_irq_button; #ifdef HAVE_IRQBUTTONS static xcpt_t board_button_irqx(gio_pinset_t pinset, int irq, - xcpt_t irqhandler, xcpt_t *store) + xcpt_t irqhandler, xcpt_t *store, void *arg) { xcpt_t oldhandler; irqstate_t flags; @@ -108,7 +108,7 @@ static xcpt_t board_button_irqx(gio_pinset_t pinset, int irq, /* Configure the interrupt */ tms570_gioirq(pinset); - (void)irq_attach(irq, irqhandler); + (void)irq_attach(irq, irqhandler, arg); tms570_gioirqenable(irq); } else @@ -183,12 +183,13 @@ uint8_t board_buttons(void) * ****************************************************************************/ -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { #ifdef HAVE_IRQBUTTONS if (id == BUTTON_GIOA7) { - return board_button_irqx(GIO_BUTTON, IRQ_BUTTON, irqhandler, &g_irq_button); + return board_button_irqx(GIO_BUTTON, IRQ_BUTTON, irqhandler,i + &g_irq_button, arg); } #endif diff --git a/configs/lincoln60/src/lpc17_buttons.c b/configs/lincoln60/src/lpc17_buttons.c index ebcfc385c67..5764415e4e1 100644 --- a/configs/lincoln60/src/lpc17_buttons.c +++ b/configs/lincoln60/src/lpc17_buttons.c @@ -179,7 +179,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_GPIOIRQ) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; irqstate_t flags; @@ -207,7 +207,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) { /* Attach then enable the new interrupt handler */ - (void)irq_attach(irq, irqhandler); + (void)irq_attach(irq, irqhandler, NULL); up_enable_irq(irq); } else diff --git a/configs/lpc4330-xplorer/src/lpc43_buttons.c b/configs/lpc4330-xplorer/src/lpc43_buttons.c index a277bfc8689..33431b6f0ab 100644 --- a/configs/lpc4330-xplorer/src/lpc43_buttons.c +++ b/configs/lpc4330-xplorer/src/lpc43_buttons.c @@ -178,7 +178,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC43_GPIO_IRQ) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; irqstate_t flags; @@ -206,7 +206,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) { /* Attach then enable the new interrupt handler */ - (void)irq_attach(irq, irqhandler); + (void)irq_attach(irq, irqhandler, NULL); up_enable_irq(irq); } else diff --git a/configs/lpc4357-evb/src/lpc43_buttons.c b/configs/lpc4357-evb/src/lpc43_buttons.c index 37ac652cdfc..feeab979a06 100644 --- a/configs/lpc4357-evb/src/lpc43_buttons.c +++ b/configs/lpc4357-evb/src/lpc43_buttons.c @@ -184,7 +184,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC43_GPIO_IRQ) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { #if 0 /* Not yet implemented */ xcpt_t oldhandler = NULL; @@ -213,7 +213,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) { /* Attach then enable the new interrupt handler */ - (void)irq_attach(irq, irqhandler); + (void)irq_attach(irq, irqhandler, NULL); up_enable_irq(irq); } else diff --git a/configs/maple/src/stm32_lcd.c b/configs/maple/src/stm32_lcd.c index 64f506563ba..e6693add9ae 100644 --- a/configs/maple/src/stm32_lcd.c +++ b/configs/maple/src/stm32_lcd.c @@ -90,7 +90,7 @@ static int up_lcdextcominisr(int irq, void *context) return OK; } - return g_isr(irq, context); + return g_isr(irq, context, NULL); } static int up_lcdirqattach(xcpt_t isr) diff --git a/configs/mikroe-stm32f4/src/stm32_usb.c b/configs/mikroe-stm32f4/src/stm32_usb.c index 001d6e0930a..44321bd7d36 100644 --- a/configs/mikroe-stm32f4/src/stm32_usb.c +++ b/configs/mikroe-stm32f4/src/stm32_usb.c @@ -282,7 +282,7 @@ void stm32_usbhost_vbusdrive(int iface, bool enable) #ifdef CONFIG_USBHOST xcpt_t stm32_setup_overcurrent(xcpt_t handler) { - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler); + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); } #endif diff --git a/configs/mikroe-stm32f4/src/stm32_vs1053.c b/configs/mikroe-stm32f4/src/stm32_vs1053.c index 74e7d4310c1..182c559fa63 100644 --- a/configs/mikroe-stm32f4/src/stm32_vs1053.c +++ b/configs/mikroe-stm32f4/src/stm32_vs1053.c @@ -78,13 +78,15 @@ struct stm32_lower_s { const struct vs1053_lower_s lower; /* Low-level MCU interface */ xcpt_t handler; /* VS1053 interrupt handler */ + FAR void *arg; /* Interrupt handler argument */ }; /**************************************************************************** * Private Function Prototypes ****************************************************************************/ -static int up_attach(FAR const struct vs1053_lower_s *lower, xcpt_t handler); +static int up_attach(FAR const struct vs1053_lower_s *lower, xcpt_t handler, + FAR void *arg); static void up_enable(FAR const struct vs1053_lower_s *lower); static void up_disable(FAR const struct vs1053_lower_s *lower); static void up_reset(FAR const struct vs1053_lower_s *lower, bool state); @@ -110,6 +112,7 @@ static struct stm32_lower_s g_vs1053lower = .irq = GPIO_VS1053_DREQ_IRQ }, .handler = NULL, + .arg = NULL, }; /**************************************************************************** @@ -120,11 +123,13 @@ static struct stm32_lower_s g_vs1053lower = * Name: struct vs1053_lower_s methods ****************************************************************************/ -static int up_attach(FAR const struct vs1053_lower_s *lower, xcpt_t handler) +static int up_attach(FAR const struct vs1053_lower_s *lower, xcpt_t handler, + FAR void *arg) { FAR struct stm32_lower_s *priv = (FAR struct stm32_lower_s *)lower; priv->handler = handler; /* Save the handler for later */ + priv->arg = arg; /* Along with the handler argument */ return 0; } @@ -133,12 +138,13 @@ static void up_enable(FAR const struct vs1053_lower_s *lower) FAR struct stm32_lower_s *priv = (FAR struct stm32_lower_s *)lower; DEBUGASSERT(priv->handler); - (void)stm32_gpiosetevent(GPIO_VS1053_DREQ, true, false, false, priv->handler); + (void)stm32_gpiosetevent(GPIO_VS1053_DREQ, true, false, false, + priv->handler, priv->arg); } static void up_disable(FAR const struct vs1053_lower_s *lower) { - (void)stm32_gpiosetevent(GPIO_VS1053_DREQ, false, false, false, NULL); + (void)stm32_gpiosetevent(GPIO_VS1053_DREQ, false, false, false, NULL, NULL); } static void up_reset(FAR const struct vs1053_lower_s *lower, bool state) diff --git a/configs/nucleo-144/f767-evalos/defconfig b/configs/nucleo-144/f767-evalos/defconfig index a8983105698..058f4a1c878 100644 --- a/configs/nucleo-144/f767-evalos/defconfig +++ b/configs/nucleo-144/f767-evalos/defconfig @@ -747,7 +747,7 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue" # Memory Management # # CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=2 +CONFIG_MM_REGIONS=3 # CONFIG_ARCH_HAVE_HEAP2 is not set # CONFIG_GRAN is not set diff --git a/configs/nucleo-144/f767-nsh/defconfig b/configs/nucleo-144/f767-nsh/defconfig index 12bbaa33e14..5131470f0fa 100644 --- a/configs/nucleo-144/f767-nsh/defconfig +++ b/configs/nucleo-144/f767-nsh/defconfig @@ -734,7 +734,7 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue" # Memory Management # # CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=2 +CONFIG_MM_REGIONS=3 # CONFIG_ARCH_HAVE_HEAP2 is not set # CONFIG_GRAN is not set diff --git a/configs/nucleo-144/src/stm32_buttons.c b/configs/nucleo-144/src/stm32_buttons.c index ff0e64d7642..7745758cb9d 100644 --- a/configs/nucleo-144/src/stm32_buttons.c +++ b/configs/nucleo-144/src/stm32_buttons.c @@ -105,13 +105,14 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; if (id == BUTTON_USER) { - oldhandler = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); } return oldhandler; diff --git a/configs/nucleo-144/src/stm32_sdio.c b/configs/nucleo-144/src/stm32_sdio.c index 7904f8c2eba..0a79f9258dc 100644 --- a/configs/nucleo-144/src/stm32_sdio.c +++ b/configs/nucleo-144/src/stm32_sdio.c @@ -132,7 +132,8 @@ int stm32_sdio_initialize(void) /* Register an interrupt handler for the card detect pin */ - stm32_gpiosetevent(GPIO_SDMMC1_NCD, true, true, true, stm32_ncd_interrupt); + stm32_gpiosetevent(GPIO_SDMMC1_NCD, true, true, true, + stm32_ncd_interrupt, NULL); #endif /* Mount the SDIO-based MMC/SD block driver */ diff --git a/configs/nucleo-144/src/stm32_usb.c b/configs/nucleo-144/src/stm32_usb.c index 1cb422a78c4..a1a2059176d 100644 --- a/configs/nucleo-144/src/stm32_usb.c +++ b/configs/nucleo-144/src/stm32_usb.c @@ -304,7 +304,7 @@ void stm32_usbhost_vbusdrive(int iface, bool enable) #ifdef CONFIG_USBHOST xcpt_t stm32_setup_overcurrent(xcpt_t handler) { - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler); + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); } #endif diff --git a/configs/nucleo-f303re/src/stm32_buttons.c b/configs/nucleo-f303re/src/stm32_buttons.c index 82e9c9eff25..f5dcc7224f2 100644 --- a/configs/nucleo-f303re/src/stm32_buttons.c +++ b/configs/nucleo-f303re/src/stm32_buttons.c @@ -126,14 +126,14 @@ uint8_t board_buttons(void) ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; if (id == BUTTON_USER) { oldhandler = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, - irqhandler); + irqhandler, arg); } return oldhandler; diff --git a/configs/nucleo-f334r8/Kconfig b/configs/nucleo-f334r8/Kconfig new file mode 100644 index 00000000000..e9018b63a38 --- /dev/null +++ b/configs/nucleo-f334r8/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_NUCLEO_F334R8 + +endif diff --git a/configs/nucleo-f334r8/include/board.h b/configs/nucleo-f334r8/include/board.h new file mode 100644 index 00000000000..0ebacd0b0c3 --- /dev/null +++ b/configs/nucleo-f334r8/include/board.h @@ -0,0 +1,282 @@ +/**************************************************************************** + * configs/nucleo-f334r8/include/board.h + * include/arch/board/board.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIG_STM32F3DISCOVERY_INCLUDE_BOARD_H +#define __CONFIG_STM32F3DISCOVERY_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +#ifdef __KERNEL__ +# include "stm32.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 8 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY +#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB2 timers 1, 8, 15-17 and HRTIM1 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_THRTIM1_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_HRTIM1_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ +/* The Nucleo F334R8 board has three LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2-1. + * LD3 PWR: red LED indicates that the board is powered. + * + * And one can be controlled by software: + * + * User LD2: green LED is a user LED connected to the I/O PA5 of the + * STM32F334R8. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo F334R8. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is is sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ +/* The Nucleo F334R8 supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PC13 of the STM32F334R8. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32F334R8. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ +/* CAN */ + +#define GPIO_CAN1_RX GPIO_CAN_RX_2 +#define GPIO_CAN1_TX GPIO_CAN_TX_2 + +/* I2C */ + +#define GPIO_I2C1_SCL GPIO_I2C1_SCL_3 +#define GPIO_I2C1_SDA GPIO_I2C1_SDA_3 + +/* SPI */ + +#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 +#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 +#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 + +/* TIM */ + +#define GPIO_TIM2_CH2OUT GPIO_TIM2_CH2OUT_2 +#define GPIO_TIM2_CH3OUT GPIO_TIM2_CH3OUT_3 + +#define GPIO_TIM3_CH1OUT GPIO_TIM3_CH1OUT_2 +#define GPIO_TIM3_CH2OUT GPIO_TIM3_CH2OUT_4 + +#define GPIO_TIM4_CH1OUT GPIO_TIM4_CH1OUT_2 + +/* USART */ + +#define GPIO_USART2_RX GPIO_USART2_RX_2 +#define GPIO_USART2_TX GPIO_USART2_TX_2 + +#define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */ +#define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */ + +/* HRTIM */ + + +/* DMA channels *************************************************************/ +/* ADC */ + +#define ADC1_DMA_CHAN DMACHAN_ADC1 +#define ADC2_DMA_CHAN DMACHAN_ADC2_ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIG_NUCLEO_F334R8_INCLUDE_BOARD_H */ diff --git a/configs/nucleo-f334r8/nsh/Make.defs b/configs/nucleo-f334r8/nsh/Make.defs new file mode 100644 index 00000000000..dc83b33e38a --- /dev/null +++ b/configs/nucleo-f334r8/nsh/Make.defs @@ -0,0 +1,113 @@ +############################################################################ +# configs/nucleo-f334r8/nsh/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/nucleo-f334r8/nsh/defconfig b/configs/nucleo-f334r8/nsh/defconfig new file mode 100644 index 00000000000..6ae44c0a818 --- /dev/null +++ b/configs/nucleo-f334r8/nsh/defconfig @@ -0,0 +1,1217 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +CONFIG_DEBUG_FEATURES=y + +# +# Debug SYSLOG Output Controls +# +# CONFIG_DEBUG_ERROR is not set +# CONFIG_DEBUG_ASSERTIONS is not set + +# +# Subsystem Debug Options +# +# CONFIG_DEBUG_BINFMT is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_DEBUG_GRAPHICS is not set +# CONFIG_DEBUG_LIB is not set +# CONFIG_DEBUG_MM is not set +# CONFIG_DEBUG_SCHED is not set + +# +# OS Function Debug Options +# +# CONFIG_DEBUG_IRQ is not set + +# +# Driver Debug Options +# +# CONFIG_DEBUG_LEDS is not set +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_TIMER is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +CONFIG_ARCH_HAVE_HEAPCHECK=y +# CONFIG_HEAP_COLORATION is not set +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM23 is not set +# CONFIG_ARCH_CORTEXM3 is not set +# CONFIG_ARCH_CORTEXM33 is not set +CONFIG_ARCH_CORTEXM4=y +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARMV7M_LAZYFPU is not set +CONFIG_ARCH_HAVE_FPU=y +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set +# CONFIG_DEBUG_HARDFAULT is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set +# CONFIG_ARMV7M_OABI_TOOLCHAIN is not set +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set +# CONFIG_SERIAL_TERMIOS is not set + +# +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32L151C6 is not set +# CONFIG_ARCH_CHIP_STM32L151C8 is not set +# CONFIG_ARCH_CHIP_STM32L151CB is not set +# CONFIG_ARCH_CHIP_STM32L151R6 is not set +# CONFIG_ARCH_CHIP_STM32L151R8 is not set +# CONFIG_ARCH_CHIP_STM32L151RB is not set +# CONFIG_ARCH_CHIP_STM32L151V6 is not set +# CONFIG_ARCH_CHIP_STM32L151V8 is not set +# CONFIG_ARCH_CHIP_STM32L151VB is not set +# CONFIG_ARCH_CHIP_STM32L152C6 is not set +# CONFIG_ARCH_CHIP_STM32L152C8 is not set +# CONFIG_ARCH_CHIP_STM32L152CB is not set +# CONFIG_ARCH_CHIP_STM32L152R6 is not set +# CONFIG_ARCH_CHIP_STM32L152R8 is not set +# CONFIG_ARCH_CHIP_STM32L152RB is not set +# CONFIG_ARCH_CHIP_STM32L152V6 is not set +# CONFIG_ARCH_CHIP_STM32L152V8 is not set +# CONFIG_ARCH_CHIP_STM32L152VB is not set +# CONFIG_ARCH_CHIP_STM32L162ZD is not set +# CONFIG_ARCH_CHIP_STM32L162VE is not set +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F102CB is not set +# CONFIG_ARCH_CHIP_STM32F103T8 is not set +# CONFIG_ARCH_CHIP_STM32F103TB is not set +# CONFIG_ARCH_CHIP_STM32F103C4 is not set +# CONFIG_ARCH_CHIP_STM32F103C8 is not set +# CONFIG_ARCH_CHIP_STM32F103CB is not set +# CONFIG_ARCH_CHIP_STM32F103R8 is not set +# CONFIG_ARCH_CHIP_STM32F103RB is not set +# CONFIG_ARCH_CHIP_STM32F103RC is not set +# CONFIG_ARCH_CHIP_STM32F103RD is not set +# CONFIG_ARCH_CHIP_STM32F103RE is not set +# CONFIG_ARCH_CHIP_STM32F103RG is not set +# CONFIG_ARCH_CHIP_STM32F103V8 is not set +# CONFIG_ARCH_CHIP_STM32F103VB is not set +# CONFIG_ARCH_CHIP_STM32F103VC is not set +# CONFIG_ARCH_CHIP_STM32F103VE is not set +# CONFIG_ARCH_CHIP_STM32F103ZE is not set +# CONFIG_ARCH_CHIP_STM32F105VB is not set +# CONFIG_ARCH_CHIP_STM32F105RB is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +# CONFIG_ARCH_CHIP_STM32F205RG is not set +# CONFIG_ARCH_CHIP_STM32F207IG is not set +# CONFIG_ARCH_CHIP_STM32F207ZE is not set +# CONFIG_ARCH_CHIP_STM32F302K6 is not set +# CONFIG_ARCH_CHIP_STM32F302K8 is not set +# CONFIG_ARCH_CHIP_STM32F302CB is not set +# CONFIG_ARCH_CHIP_STM32F302CC is not set +# CONFIG_ARCH_CHIP_STM32F302RB is not set +# CONFIG_ARCH_CHIP_STM32F302RC is not set +# CONFIG_ARCH_CHIP_STM32F302VB is not set +# CONFIG_ARCH_CHIP_STM32F302VC is not set +# CONFIG_ARCH_CHIP_STM32F303K6 is not set +# CONFIG_ARCH_CHIP_STM32F303K8 is not set +# CONFIG_ARCH_CHIP_STM32F303C6 is not set +# CONFIG_ARCH_CHIP_STM32F303C8 is not set +# CONFIG_ARCH_CHIP_STM32F303CB is not set +# CONFIG_ARCH_CHIP_STM32F303CC is not set +# CONFIG_ARCH_CHIP_STM32F303RB is not set +# CONFIG_ARCH_CHIP_STM32F303RC is not set +# CONFIG_ARCH_CHIP_STM32F303RD is not set +# CONFIG_ARCH_CHIP_STM32F303RE is not set +# CONFIG_ARCH_CHIP_STM32F303VB is not set +# CONFIG_ARCH_CHIP_STM32F303VC is not set +# CONFIG_ARCH_CHIP_STM32F334K4 is not set +# CONFIG_ARCH_CHIP_STM32F334K6 is not set +# CONFIG_ARCH_CHIP_STM32F334K8 is not set +# CONFIG_ARCH_CHIP_STM32F334C4 is not set +# CONFIG_ARCH_CHIP_STM32F334C6 is not set +# CONFIG_ARCH_CHIP_STM32F334C8 is not set +# CONFIG_ARCH_CHIP_STM32F334R4 is not set +# CONFIG_ARCH_CHIP_STM32F334R6 is not set +CONFIG_ARCH_CHIP_STM32F334R8=y +# CONFIG_ARCH_CHIP_STM32F372C8 is not set +# CONFIG_ARCH_CHIP_STM32F372R8 is not set +# CONFIG_ARCH_CHIP_STM32F372V8 is not set +# CONFIG_ARCH_CHIP_STM32F372CB is not set +# CONFIG_ARCH_CHIP_STM32F372RB is not set +# CONFIG_ARCH_CHIP_STM32F372VB is not set +# CONFIG_ARCH_CHIP_STM32F372CC is not set +# CONFIG_ARCH_CHIP_STM32F372RC is not set +# CONFIG_ARCH_CHIP_STM32F372VC is not set +# CONFIG_ARCH_CHIP_STM32F373C8 is not set +# CONFIG_ARCH_CHIP_STM32F373R8 is not set +# CONFIG_ARCH_CHIP_STM32F373V8 is not set +# CONFIG_ARCH_CHIP_STM32F373CB is not set +# CONFIG_ARCH_CHIP_STM32F373RB is not set +# CONFIG_ARCH_CHIP_STM32F373VB is not set +# CONFIG_ARCH_CHIP_STM32F373CC is not set +# CONFIG_ARCH_CHIP_STM32F373RC is not set +# CONFIG_ARCH_CHIP_STM32F373VC is not set +# CONFIG_ARCH_CHIP_STM32F401RE is not set +# CONFIG_ARCH_CHIP_STM32F411RE is not set +# CONFIG_ARCH_CHIP_STM32F411VE is not set +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +# CONFIG_ARCH_CHIP_STM32F407VG is not set +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +# CONFIG_ARCH_CHIP_STM32F407ZG is not set +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +# CONFIG_ARCH_CHIP_STM32F427V is not set +# CONFIG_ARCH_CHIP_STM32F427Z is not set +# CONFIG_ARCH_CHIP_STM32F427I is not set +# CONFIG_ARCH_CHIP_STM32F429V is not set +# CONFIG_ARCH_CHIP_STM32F429Z is not set +# CONFIG_ARCH_CHIP_STM32F429I is not set +# CONFIG_ARCH_CHIP_STM32F429B is not set +# CONFIG_ARCH_CHIP_STM32F429N is not set +# CONFIG_ARCH_CHIP_STM32F446M is not set +# CONFIG_ARCH_CHIP_STM32F446R is not set +# CONFIG_ARCH_CHIP_STM32F446V is not set +# CONFIG_ARCH_CHIP_STM32F446Z is not set +# CONFIG_ARCH_CHIP_STM32F469A is not set +# CONFIG_ARCH_CHIP_STM32F469I is not set +# CONFIG_ARCH_CHIP_STM32F469B is not set +# CONFIG_ARCH_CHIP_STM32F469N is not set +CONFIG_STM32_FLASH_CONFIG_DEFAULT=y +# CONFIG_STM32_FLASH_CONFIG_4 is not set +# CONFIG_STM32_FLASH_CONFIG_6 is not set +# CONFIG_STM32_FLASH_CONFIG_8 is not set +# CONFIG_STM32_FLASH_CONFIG_B is not set +# CONFIG_STM32_FLASH_CONFIG_C is not set +# CONFIG_STM32_FLASH_CONFIG_D is not set +# CONFIG_STM32_FLASH_CONFIG_E is not set +# CONFIG_STM32_FLASH_CONFIG_F is not set +# CONFIG_STM32_FLASH_CONFIG_G is not set +# CONFIG_STM32_FLASH_CONFIG_I is not set +# CONFIG_STM32_STM32L15XX is not set +# CONFIG_STM32_ENERGYLITE is not set +# CONFIG_STM32_STM32F10XX is not set +# CONFIG_STM32_VALUELINE is not set +# CONFIG_STM32_CONNECTIVITYLINE is not set +# CONFIG_STM32_PERFORMANCELINE is not set +# CONFIG_STM32_USBACCESSLINE is not set +# CONFIG_STM32_HIGHDENSITY is not set +# CONFIG_STM32_MEDIUMDENSITY is not set +# CONFIG_STM32_LOWDENSITY is not set +# CONFIG_STM32_STM32F20XX is not set +# CONFIG_STM32_STM32F205 is not set +# CONFIG_STM32_STM32F207 is not set +# CONFIG_STM32_STM32F30XX is not set +# CONFIG_STM32_STM32F302 is not set +# CONFIG_STM32_STM32F303 is not set +CONFIG_STM32_STM32F33XX=y +# CONFIG_STM32_STM32F37XX is not set +# CONFIG_STM32_STM32F40XX is not set +# CONFIG_STM32_STM32F401 is not set +# CONFIG_STM32_STM32F411 is not set +# CONFIG_STM32_STM32F405 is not set +# CONFIG_STM32_STM32F407 is not set +# CONFIG_STM32_STM32F427 is not set +# CONFIG_STM32_STM32F429 is not set +# CONFIG_STM32_STM32F446 is not set +# CONFIG_STM32_STM32F469 is not set +# CONFIG_STM32_DFU is not set + +# +# STM32 Peripheral Support +# +CONFIG_STM32_HAVE_CCM=y +# CONFIG_STM32_HAVE_USBDEV is not set +# CONFIG_STM32_HAVE_OTGFS is not set +# CONFIG_STM32_HAVE_FSMC is not set +CONFIG_STM32_HAVE_HRTIM1=y +# CONFIG_STM32_HAVE_LTDC is not set +CONFIG_STM32_HAVE_USART3=y +# CONFIG_STM32_HAVE_UART4 is not set +# CONFIG_STM32_HAVE_UART5 is not set +# CONFIG_STM32_HAVE_USART6 is not set +# CONFIG_STM32_HAVE_UART7 is not set +# CONFIG_STM32_HAVE_UART8 is not set +CONFIG_STM32_HAVE_TIM1=y +# CONFIG_STM32_HAVE_TIM2 is not set +# CONFIG_STM32_HAVE_TIM3 is not set +# CONFIG_STM32_HAVE_TIM4 is not set +# CONFIG_STM32_HAVE_TIM5 is not set +# CONFIG_STM32_HAVE_TIM6 is not set +# CONFIG_STM32_HAVE_TIM7 is not set +# CONFIG_STM32_HAVE_TIM8 is not set +# CONFIG_STM32_HAVE_TIM9 is not set +# CONFIG_STM32_HAVE_TIM10 is not set +# CONFIG_STM32_HAVE_TIM11 is not set +# CONFIG_STM32_HAVE_TIM12 is not set +# CONFIG_STM32_HAVE_TIM13 is not set +# CONFIG_STM32_HAVE_TIM14 is not set +CONFIG_STM32_HAVE_TIM15=y +CONFIG_STM32_HAVE_TIM16=y +CONFIG_STM32_HAVE_TIM17=y +CONFIG_STM32_HAVE_ADC2=y +# CONFIG_STM32_HAVE_ADC3 is not set +# CONFIG_STM32_HAVE_ADC4 is not set +# CONFIG_STM32_HAVE_ADC1_DMA is not set +# CONFIG_STM32_HAVE_ADC2_DMA is not set +# CONFIG_STM32_HAVE_ADC3_DMA is not set +# CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set +CONFIG_STM32_HAVE_CAN1=y +# CONFIG_STM32_HAVE_CAN2 is not set +CONFIG_STM32_HAVE_DAC1=y +CONFIG_STM32_HAVE_DAC2=y +# CONFIG_STM32_HAVE_RNG is not set +# CONFIG_STM32_HAVE_ETHMAC is not set +# CONFIG_STM32_HAVE_I2C2 is not set +# CONFIG_STM32_HAVE_I2C3 is not set +# CONFIG_STM32_HAVE_SPI2 is not set +# CONFIG_STM32_HAVE_SPI3 is not set +# CONFIG_STM32_HAVE_SPI4 is not set +# CONFIG_STM32_HAVE_SPI5 is not set +# CONFIG_STM32_HAVE_SPI6 is not set +# CONFIG_STM32_HAVE_SAIPLL is not set +# CONFIG_STM32_HAVE_I2SPLL is not set +# CONFIG_STM32_ADC1 is not set +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CRC is not set +# CONFIG_STM32_DMA1 is not set +# CONFIG_STM32_DMA2 is not set +# CONFIG_STM32_DAC1 is not set +# CONFIG_STM32_DAC2 is not set +# CONFIG_STM32_HRTIM1 is not set +# CONFIG_STM32_I2C1 is not set +CONFIG_STM32_PWR=y +# CONFIG_STM32_SDIO is not set +# CONFIG_STM32_SPI1 is not set +# CONFIG_STM32_TIM1 is not set +# CONFIG_STM32_TIM2 is not set +# CONFIG_STM32_TIM15 is not set +# CONFIG_STM32_TIM16 is not set +# CONFIG_STM32_TIM17 is not set +CONFIG_STM32_USART1=y +# CONFIG_STM32_USART2 is not set +# CONFIG_STM32_USART3 is not set +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_WWDG is not set +# CONFIG_STM32_NOEXT_VECTORS is not set + +# +# Alternate Pin Mapping +# +# CONFIG_STM32_JTAG_DISABLE is not set +# CONFIG_STM32_JTAG_FULL_ENABLE is not set +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +CONFIG_STM32_JTAG_SW_ENABLE=y +# CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG is not set +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set +CONFIG_STM32_CCMEXCLUDE=y + +# +# Timer Configuration +# +# CONFIG_STM32_ONESHOT is not set +# CONFIG_STM32_FREERUN is not set +# CONFIG_STM32_TIM1_CAP is not set +CONFIG_STM32_USART=y +CONFIG_STM32_SERIALDRIVER=y + +# +# U[S]ART Configuration +# + +# +# U[S]ART Device Configuration +# +CONFIG_STM32_USART1_SERIALDRIVER=y +# CONFIG_STM32_USART1_1WIREDRIVER is not set +# CONFIG_USART1_RS485 is not set + +# +# Serial Driver Configuration +# +# CONFIG_SERIAL_DISABLE_REORDERING is not set +# CONFIG_STM32_FLOWCONTROL_BROKEN is not set +# CONFIG_STM32_USART_BREAKS is not set +# CONFIG_STM32_USART_SINGLEWIRE is not set +# CONFIG_STM32_HAVE_RTC_COUNTER is not set +# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set + +# +# USB FS Host Configuration +# + +# +# USB HS Host Configuration +# + +# +# USB Host Debug Configuration +# + +# +# USB Device Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=16717 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=12288 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_NUCLEO_F334R8=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="nucleo-f334r8" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_HAVE_IRQBUTTONS=y +# CONFIG_ARCH_IRQBUTTONS is not set + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +# CONFIG_LIB_BOARDCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_DISABLE_SIGNALS=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_ENVIRON=y + +# +# Clocks and Timers +# +CONFIG_ARCH_HAVE_TICKLESS=y +# CONFIG_SCHED_TICKLESS is not set +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +CONFIG_ARCH_HAVE_TIMEKEEPING=y +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=12 +CONFIG_START_DAY=6 +CONFIG_MAX_WDOGPARMS=1 +CONFIG_PREALLOC_WDOGS=1 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=2 + +# +# Tasks and Scheduling +# +# CONFIG_SPINLOCK is not set +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=4 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y +# CONFIG_CANCELLATION_POINTS is not set + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +CONFIG_FDCLONE_STDIO=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=16 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +# CONFIG_MODULE is not set + +# +# Work queue support +# + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +# CONFIG_DEV_NULL is not set +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +CONFIG_ARCH_HAVE_I2CRESET=y +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +CONFIG_USART1_SERIALDRIVER=y +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +# CONFIG_SERIAL_TIOCSERGSTRUCT is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_USART1_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART1 Configuration +# +CONFIG_USART1_RXBUFSIZE=256 +CONFIG_USART1_TXBUFSIZE=256 +CONFIG_USART1_BAUD=115200 +CONFIG_USART1_BITS=8 +CONFIG_USART1_PARITY=0 +CONFIG_USART1_2STOP=0 +# CONFIG_USART1_IFLOWCONTROL is not set +# CONFIG_USART1_OFLOWCONTROL is not set +# CONFIG_USART1_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +# CONFIG_SYSLOG_SERIAL_CONSOLE is not set +# CONFIG_SYSLOG_CHAR is not set +# CONFIG_SYSLOG_CONSOLE is not set +CONFIG_SYSLOG_NONE=y +# CONFIG_SYSLOG_FILE is not set +# CONFIG_CONSOLE_SYSLOG is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_PSEUDOFS_SOFTLINKS is not set +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# + +# +# Standard C I/O +# +CONFIG_STDIO_DISABLE_BUFFERING=n +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_LIBC_SCANSET is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_MEMCPY_VIK is not set +# CONFIG_LIBM is not set + +# +# Architecture-Specific Support +# +CONFIG_ARCH_LOWPUTC=y +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_LIBC_ARCH_MEMCPY is not set +# CONFIG_LIBC_ARCH_MEMCMP is not set +# CONFIG_LIBC_ARCH_MEMMOVE is not set +# CONFIG_LIBC_ARCH_MEMSET is not set +# CONFIG_LIBC_ARCH_STRCHR is not set +# CONFIG_LIBC_ARCH_STRCMP is not set +# CONFIG_LIBC_ARCH_STRCPY is not set +# CONFIG_LIBC_ARCH_STRNCPY is not set +# CONFIG_LIBC_ARCH_STRLEN is not set +# CONFIG_LIBC_ARCH_STRNLEN is not set +# CONFIG_LIBC_ARCH_BZERO is not set +# CONFIG_LIBC_ARCH_ELF is not set +# CONFIG_ARMV7M_MEMCPY is not set + +# +# stdlib Options +# +CONFIG_LIB_RAND_ORDER=1 + +# +# Program Execution Options +# +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=512 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=512 + +# +# errno Decode Support +# +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set + +# +# memcpy/memset Options +# +# CONFIG_MEMSET_OPTSPEED is not set +# CONFIG_LIBC_DLLFCN is not set +# CONFIG_LIBC_MODLIB is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set + +# +# Time/Time Zone Support +# +# CONFIG_TIME_EXTENDED is not set +CONFIG_ARCH_HAVE_TLS=y + +# +# Thread Local Storage (TLS) +# +# CONFIG_TLS is not set + +# +# Network-Related Options +# +# CONFIG_LIBC_IPv4_ADDRCONV is not set +# CONFIG_LIBC_IPv6_ADDRCONV is not set +# CONFIG_LIBC_NETDB is not set + +# +# NETDB Support +# +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=512 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLO_PRIORITY=100 +CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# External +# +# CONFIG_EXTERNAL_MY_NX is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +CONFIG_NSH_CMDPARMS=y +CONFIG_NSH_MAXARGUMENTS=6 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +CONFIG_NSH_DISABLE_ADDROUTE=y +CONFIG_NSH_DISABLE_BASENAME=y +CONFIG_NSH_DISABLE_CAT=y +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_DATE=y +CONFIG_NSH_DISABLE_DD=y +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DELROUTE=y +CONFIG_NSH_DISABLE_DIRNAME=y +# CONFIG_NSH_DISABLE_ECHO is not set +CONFIG_NSH_DISABLE_EXEC=y +CONFIG_NSH_DISABLE_EXIT=y +# CONFIG_NSH_DISABLE_FREE is not set +CONFIG_NSH_DISABLE_GET=y +# CONFIG_NSH_DISABLE_HELP is not set +CONFIG_NSH_DISABLE_HEXDUMP=y +CONFIG_NSH_DISABLE_IFCONFIG=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_KILL=y +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LOSMART=y +CONFIG_NSH_DISABLE_LS=y +CONFIG_NSH_DISABLE_MB=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_MH=y +CONFIG_NSH_DISABLE_MOUNT=y +CONFIG_NSH_DISABLE_MV=y +CONFIG_NSH_DISABLE_MW=y +# CONFIG_NSH_DISABLE_PRINTF is not set +CONFIG_NSH_DISABLE_PS=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_PWD=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_SET=y +CONFIG_NSH_DISABLE_SH=y +CONFIG_NSH_DISABLE_SLEEP=y +CONFIG_NSH_DISABLE_TIME=y +CONFIG_NSH_DISABLE_TEST=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_DISABLE_UNAME=y +CONFIG_NSH_DISABLE_UNSET=y +CONFIG_NSH_DISABLE_USLEEP=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_DISABLE_XD=y +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_FILEIOSIZE=256 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +# CONFIG_NSH_ARCHINIT is not set +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/nucleo-f334r8/nsh/setenv.sh b/configs/nucleo-f334r8/nsh/setenv.sh new file mode 100644 index 00000000000..1baaeb889e5 --- /dev/null +++ b/configs/nucleo-f334r8/nsh/setenv.sh @@ -0,0 +1,77 @@ +#!/bin/bash +# configs/nucleo-f224r8/nsh/setenv.sh +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the Atmel GCC +# toolchain under Windows. You will also have to edit this if you install +# this toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" +# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# This is the path to the location where I installed the devkitARM toolchain +# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/ +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/configs/nucleo-f334r8/scripts/ld.script b/configs/nucleo-f334r8/scripts/ld.script new file mode 100644 index 00000000000..6c11be015b8 --- /dev/null +++ b/configs/nucleo-f334r8/scripts/ld.script @@ -0,0 +1,117 @@ +/**************************************************************************** + * configs/nucleo-f334re/scripts/ld.script + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The STM32F334R8 has 64Kb of FLASH beginning at address 0x0800:0000 and + * 12Kb of SRAM. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 12K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/nucleo-f334r8/src/Makefile b/configs/nucleo-f334r8/src/Makefile new file mode 100644 index 00000000000..c2e188da400 --- /dev/null +++ b/configs/nucleo-f334r8/src/Makefile @@ -0,0 +1,91 @@ +############################################################################ +# configs/nucleo-f303re/src/Makefile +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Mateusz Szafoni +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += stm32_appinit.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_CAN),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_DAC),y) +CSRCS += stm32_dac.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_TIMER),y) +CSRCS += stm32_timer.c +endif + +ifeq ($(CONFIG_HRTIM),y) +CSRCS += stm32_hrtim.c +endif + +ifeq ($(CONFIG_COMP),y) +CSRCS += stm32_comp.c +endif + +ifeq ($(CONFIG_OPAMP),y) +CSRCS += stm32_opamp.c +endif + +include $(TOPDIR)/configs/Board.mk diff --git a/configs/nucleo-f334r8/src/nucleo-f334r8.h b/configs/nucleo-f334r8/src/nucleo-f334r8.h new file mode 100644 index 00000000000..d9cd2e1cf7c --- /dev/null +++ b/configs/nucleo-f334r8/src/nucleo-f334r8.h @@ -0,0 +1,193 @@ +/**************************************************************************** + * configs/nucleo-f334r8/src/nucleo-f334r8.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_NUCLEO_F334R8_SRC_NUCLEO_F334R8_H +#define __CONFIGS_NUCLEO_F334R8_SRC_NUCLEO_F334R8_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LED definitions **********************************************************/ +/* The Nucleo F334R8 board has three LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2-1. + * LD3 PWR: red LED indicates that the board is powered. + * + * And one can be controlled by software: + * + * User LD2: green LED is a user LED connected to the I/O PA5 of the + * STM32F334R8T6. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +#define GPIO_LED1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN5) + +#define LED_DRIVER_PATH "/dev/userleds" + +/* Button definitions *******************************************************/ +/* The Nucleo F334R8 supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PC13 of the STM32F334R8T6. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32F334R8T6. + * + * NOTE that EXTI interrupts are configured. + */ + +#define MIN_IRQBUTTON BUTTON_USER +#define MAX_IRQBUTTON BUTTON_USER +#define NUM_IRQBUTTONS 1 + +#define GPIO_BTN_USER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN13) + +/* PWM definitions **********************************************************/ +/* The Nucleo F334R8 has no real on-board PWM devices, but the board can be + * configured to output a pulse train using variously unused pins on the + * board for PWM output (see board.h for details of pins). + */ + +#ifdef CONFIG_PWM +# if defined(CONFIG_STM32_TIM2_PWM) +# define NUCLEO_F334R8_PWMTIMER 2 +# elif defined(CONFIG_STM32_TIM3_PWM) +# define NUCLEO_F334R8_PWMTIMER 3 +# elif defined(CONFIG_STM32_TIM4_PWM) +# define NUCLEO_F334R8_PWMTIMER 4 +# endif +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the board. + * + ****************************************************************************/ + +#ifdef CONFIG_SPI +void weak_function stm32_spidev_initialize(void); +#endif + +/**************************************************************************** + * Name: stm32_timer_driver_setup + * + * Description: + * Configure the timer driver. + * + * Input Parameters: + * devpath - The full path to the timer device. This should be of the form /dev/timer0 + * timer - The timer's number. + * + * Returned Values: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_TIMER +int stm32_timer_driver_setup(FAR const char *devpath, int timer); +#endif + +/**************************************************************************** + * Name: stm32_dac_setup + * + * Description: + * Configure DAC peripheral for the board. + * + ****************************************************************************/ + +#ifdef CONFIG_DAC +int stm32_dac_setup(void); +#endif + +/************************************************************************************ + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); +#endif + +/************************************************************************************ + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int stm32_adc_setup(void); +#endif + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +#ifdef CONFIG_CAN +int stm32_can_setup(void); +#endif + +#endif /* __CONFIGS_NUCLEO_F334R8_SRC_NUCLEO_F334R8_H */ diff --git a/configs/nucleo-f334r8/src/stm32_adc.c b/configs/nucleo-f334r8/src/stm32_adc.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/configs/nucleo-f334r8/src/stm32_appinit.c b/configs/nucleo-f334r8/src/stm32_appinit.c new file mode 100644 index 00000000000..8e7e7535d4b --- /dev/null +++ b/configs/nucleo-f334r8/src/stm32_appinit.c @@ -0,0 +1,112 @@ +/**************************************************************************** + * configs/nucleo-f334r8/src/stm32_appinitialize.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "nucleo-f303re.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS +#undef HAVE_DAC + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +#if defined(CONFIG_DAC) +# define HAVE_DAC1 1 +# define HAVE_DAC2 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ + int ret; + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/configs/nucleo-f334r8/src/stm32_autoleds.c b/configs/nucleo-f334r8/src/stm32_autoleds.c new file mode 100644 index 00000000000..60ccbf9fe36 --- /dev/null +++ b/configs/nucleo-f334r8/src/stm32_autoleds.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * configs/nucleo-f334r8/src/stm32_autoleds.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-f334r8.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/nucleo-f334r8/src/stm32_boot.c b/configs/nucleo-f334r8/src/stm32_boot.c new file mode 100644 index 00000000000..370a1984102 --- /dev/null +++ b/configs/nucleo-f334r8/src/stm32_boot.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * configs/nucleo-f334r8/src/stm32_boot.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-f334r8.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the intitialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} diff --git a/configs/nucleo-f334r8/src/stm32_buttons.c b/configs/nucleo-f334r8/src/stm32_buttons.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/configs/nucleo-f334r8/src/stm32_can.c b/configs/nucleo-f334r8/src/stm32_can.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/configs/nucleo-f334r8/src/stm32_comp.c b/configs/nucleo-f334r8/src/stm32_comp.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/configs/nucleo-f334r8/src/stm32_opamp.c b/configs/nucleo-f334r8/src/stm32_opamp.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/configs/nucleo-f334r8/src/stm32_pwm.c b/configs/nucleo-f334r8/src/stm32_pwm.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/configs/nucleo-f334r8/src/stm32_spi.c b/configs/nucleo-f334r8/src/stm32_spi.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/configs/nucleo-f334r8/src/stm32_timer.c b/configs/nucleo-f334r8/src/stm32_timer.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/configs/nucleo-f334r8/src/stm32_userleds.c b/configs/nucleo-f334r8/src/stm32_userleds.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/configs/nucleo-f4x1re/src/stm32_ajoystick.c b/configs/nucleo-f4x1re/src/stm32_ajoystick.c index 7bc30b1d676..fc5b5cc237e 100644 --- a/configs/nucleo-f4x1re/src/stm32_ajoystick.c +++ b/configs/nucleo-f4x1re/src/stm32_ajoystick.c @@ -122,7 +122,7 @@ static void ajoy_enable(FAR const struct ajoy_lowerhalf_s *lower, ajoy_handler_t handler, FAR void *arg); static void ajoy_disable(void); -static int ajoy_interrupt(int irq, FAR void *context); +static int ajoy_interrupt(int irq, FAR void *context, FAR void *arg); /**************************************************************************** * Private Data @@ -377,7 +377,7 @@ static void ajoy_enable(FAR const struct ajoy_lowerhalf_s *lower, i, rising, falling); (void)stm32_gpiosetevent(g_joygpio[i], rising, falling, - true, ajoy_interrupt); + true, ajoy_interrupt, NULL); } } } @@ -403,7 +403,7 @@ static void ajoy_disable(void) flags = enter_critical_section(); for (i = 0; i < AJOY_NGPIOS; i++) { - (void)stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL); + (void)stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); } leave_critical_section(flags); @@ -422,7 +422,7 @@ static void ajoy_disable(void) * ****************************************************************************/ -static int ajoy_interrupt(int irq, FAR void *context) +static int ajoy_interrupt(int irq, FAR void *context, FAR void *arg) { DEBUGASSERT(g_ajoyhandler); diff --git a/configs/nucleo-f4x1re/src/stm32_buttons.c b/configs/nucleo-f4x1re/src/stm32_buttons.c index 2960344c62e..c93b03d21a9 100644 --- a/configs/nucleo-f4x1re/src/stm32_buttons.c +++ b/configs/nucleo-f4x1re/src/stm32_buttons.c @@ -123,13 +123,14 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; if (id == BUTTON_USER) { - oldhandler = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); } return oldhandler; diff --git a/configs/nucleo-f4x1re/src/stm32_io.c b/configs/nucleo-f4x1re/src/stm32_io.c index 72563330d6c..ba190495454 100644 --- a/configs/nucleo-f4x1re/src/stm32_io.c +++ b/configs/nucleo-f4x1re/src/stm32_io.c @@ -184,11 +184,13 @@ xcpt_t up_irqio(int id, xcpt_t irqhandler) if (id == 0) { - oldhandler = stm32_gpiosetevent(GPIO_D14, true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(GPIO_D14, true, true, true, + irqhandler, arg); } else if (id == 1) { - oldhandler = stm32_gpiosetevent(GPIO_D15, true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(GPIO_D15, true, true, true, + irqhandler, arg); } return oldhandler; diff --git a/configs/nucleo-f4x1re/src/stm32_wireless.c b/configs/nucleo-f4x1re/src/stm32_wireless.c index 0cd4e2e0662..c5012f04388 100644 --- a/configs/nucleo-f4x1re/src/stm32_wireless.c +++ b/configs/nucleo-f4x1re/src/stm32_wireless.c @@ -118,7 +118,8 @@ struct stm32_config_s * wl_read_irq - Return the state of the interrupt GPIO input */ -static int wl_attach_irq(FAR struct cc3000_config_s *state, xcpt_t handler); +static int wl_attach_irq(FAR struct cc3000_config_s *state, xcpt_t handler, + FAR void *arg); static void wl_enable_irq(FAR struct cc3000_config_s *state, bool enable); static void wl_clear_irq(FAR struct cc3000_config_s *state); static void wl_select(FAR struct cc3000_config_s *state, bool enable); @@ -157,6 +158,7 @@ static struct stm32_config_s g_cc3000_info = .dev.probe = probe, /* This is used for debugging */ #endif .handler = NULL, + .arg = NULL, }; /**************************************************************************** @@ -175,13 +177,15 @@ static struct stm32_config_s g_cc3000_info = * pendown - Return the state of the pen down GPIO input */ -static int wl_attach_irq(FAR struct cc3000_config_s *state, xcpt_t handler) +static int wl_attach_irq(FAR struct cc3000_config_s *state, xcpt_t handler, + FAR void *arg) { FAR struct stm32_config_s *priv = (FAR struct stm32_config_s *)state; /* Just save the handler for use when the interrupt is enabled */ priv->handler = handler; + priv->arg = arg; return OK; } @@ -200,11 +204,13 @@ static void wl_enable_irq(FAR struct cc3000_config_s *state, bool enable) iinfo("enable:%d\n", enable); if (enable) { - (void)stm32_gpiosetevent(GPIO_WIFI_INT, false, true, false, priv->handler); + (void)stm32_gpiosetevent(GPIO_WIFI_INT, false, true, false, + priv->handler, priv->arg); } else { - (void)stm32_gpiosetevent(GPIO_WIFI_INT, false, false, false, NULL); + (void)stm32_gpiosetevent(GPIO_WIFI_INT, false, false, false, + NULL, NULL); } } diff --git a/configs/nucleo-l476rg/nsh/defconfig b/configs/nucleo-l476rg/nsh/defconfig index f4812a5a675..b9156d1774e 100644 --- a/configs/nucleo-l476rg/nsh/defconfig +++ b/configs/nucleo-l476rg/nsh/defconfig @@ -61,9 +61,12 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -103,7 +106,9 @@ CONFIG_ARCH_CHIP_STM32L4=y # CONFIG_ARCH_ARM926EJS is not set # CONFIG_ARCH_ARM920T is not set # CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM23 is not set # CONFIG_ARCH_CORTEXM3 is not set +# CONFIG_ARCH_CORTEXM33 is not set CONFIG_ARCH_CORTEXM4=y # CONFIG_ARCH_CORTEXM7 is not set # CONFIG_ARCH_CORTEXA5 is not set @@ -158,6 +163,8 @@ CONFIG_ARMV7M_HAVE_STACKCHECK=y CONFIG_ARCH_CHIP_STM32L476RG=y # CONFIG_ARCH_CHIP_STM32L476RE is not set # CONFIG_ARCH_CHIP_STM32L486 is not set +# CONFIG_STM32L4_STM32L4X3 is not set +CONFIG_STM32L4_STM32L4X6=y CONFIG_STM32L4_STM32L476XX=y # CONFIG_STM32L4_STM32L486XX is not set # CONFIG_STM32L4_FLASH_256KB is not set @@ -178,6 +185,8 @@ CONFIG_STM32L4_SRAM2_INIT=y # STM32L4 Peripheral Support # # CONFIG_STM32L4_HAVE_LTDC is not set +CONFIG_STM32L4_HAVE_SAI1=y +CONFIG_STM32L4_HAVE_SAI2=y # CONFIG_STM32L4_ADC is not set # CONFIG_STM32L4_CAN is not set # CONFIG_STM32L4_DAC is not set @@ -205,6 +214,10 @@ CONFIG_STM32L4_DMA2=y # CONFIG_STM32L4_ADC3 is not set # CONFIG_STM32L4_AES is not set CONFIG_STM32L4_RNG=y +# CONFIG_STM32L4_SAI1_A is not set +# CONFIG_STM32L4_SAI1_B is not set +# CONFIG_STM32L4_SAI2_A is not set +# CONFIG_STM32L4_SAI2_B is not set # # AHB3 Peripherals @@ -278,6 +291,11 @@ CONFIG_STM32L4_SAI1PLL=y # # CONFIG_STM32L4_ONESHOT is not set # CONFIG_STM32L4_FREERUN is not set +CONFIG_STM32L4_HAVE_USART1=y +CONFIG_STM32L4_HAVE_USART2=y +CONFIG_STM32L4_HAVE_USART3=y +CONFIG_STM32L4_HAVE_UART4=y +CONFIG_STM32L4_HAVE_UART5=y # # U[S]ART Configuration @@ -348,6 +366,7 @@ CONFIG_RAM_SIZE=98304 # CONFIG_ARCH_BOARD_NUCLEO_L476RG=y # CONFIG_ARCH_BOARD_STM32L476VG_DISCO is not set +# CONFIG_ARCH_BOARD_STM32L476_MDK is not set # CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="nucleo-l476rg" @@ -399,6 +418,7 @@ CONFIG_PREALLOC_TIMERS=4 # # Tasks and Scheduling # +# CONFIG_SPINLOCK is not set # CONFIG_INIT_NONE is not set CONFIG_INIT_ENTRYPOINT=y # CONFIG_INIT_FILEPATH is not set @@ -415,6 +435,8 @@ CONFIG_SCHED_WAITPID=y # # CONFIG_MUTEX_TYPES is not set CONFIG_NPTHREAD_KEYS=4 +# CONFIG_PTHREAD_CLEANUP is not set +# CONFIG_CANCELLATION_POINTS is not set # # Performance Monitoring @@ -497,14 +519,14 @@ CONFIG_DEV_RANDOM=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -515,6 +537,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y CONFIG_RTC_DATETIME=y CONFIG_RTC_ALARM=y @@ -610,6 +633,7 @@ CONFIG_USART2_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -647,6 +671,7 @@ CONFIG_SYSLOG_CONSOLE=y # CONFIG_DISABLE_MOUNTPOINT is not set # CONFIG_FS_AUTOMOUNTER is not set # CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_PSEUDOFS_SOFTLINKS is not set # CONFIG_FS_READABLE is not set # CONFIG_FS_WRITABLE is not set # CONFIG_FS_NAMED_SEMAPHORES is not set @@ -701,34 +726,96 @@ CONFIG_BUILTIN=y # # Standard C Library Options # + +# +# Standard C I/O +# +# CONFIG_STDIO_DISABLE_BUFFERING is not set CONFIG_STDIO_BUFFER_SIZE=64 CONFIG_STDIO_LINEBUFFER=y CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" -# CONFIG_LIBM is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y -# CONFIG_LIBC_IOCTL_VARIADIC is not set -CONFIG_LIB_RAND_ORDER=1 +# CONFIG_LIBC_SCANSET is not set # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set # CONFIG_EOL_IS_BOTH_CRLF is not set CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_MEMCPY_VIK is not set +# CONFIG_LIBM is not set + +# +# Architecture-Specific Support +# +CONFIG_ARCH_LOWPUTC=y +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_LIBC_ARCH_MEMCPY is not set +# CONFIG_LIBC_ARCH_MEMCMP is not set +# CONFIG_LIBC_ARCH_MEMMOVE is not set +# CONFIG_LIBC_ARCH_MEMSET is not set +# CONFIG_LIBC_ARCH_STRCHR is not set +# CONFIG_LIBC_ARCH_STRCMP is not set +# CONFIG_LIBC_ARCH_STRCPY is not set +# CONFIG_LIBC_ARCH_STRNCPY is not set +# CONFIG_LIBC_ARCH_STRLEN is not set +# CONFIG_LIBC_ARCH_STRNLEN is not set +# CONFIG_LIBC_ARCH_ELF is not set +# CONFIG_ARMV7M_MEMCPY is not set + +# +# stdlib Options +# +CONFIG_LIB_RAND_ORDER=1 +CONFIG_LIB_HOMEDIR="/" + +# +# Program Execution Options +# # CONFIG_LIBC_EXECFUNCS is not set CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 + +# +# errno Decode Support +# # CONFIG_LIBC_STRERROR is not set # CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y + +# +# memcpy/memset Options +# +# CONFIG_MEMSET_OPTSPEED is not set +# CONFIG_LIBC_DLLFCN is not set +# CONFIG_LIBC_MODLIB is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set + +# +# Time/Time Zone Support +# # CONFIG_LIBC_LOCALTIME is not set # CONFIG_TIME_EXTENDED is not set -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set CONFIG_ARCH_HAVE_TLS=y + +# +# Thread Local Storage (TLS) +# # CONFIG_TLS is not set + +# +# Network-Related Options +# +# CONFIG_LIBC_IPv4_ADDRCONV is not set +# CONFIG_LIBC_IPv6_ADDRCONV is not set # CONFIG_LIBC_NETDB is not set +# +# NETDB Support +# +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 + # # Non-standard Library Support # @@ -771,6 +858,8 @@ CONFIG_EXAMPLES_ALARM_PRIORITY=100 CONFIG_EXAMPLES_ALARM_STACKSIZE=2048 CONFIG_EXAMPLES_ALARM_DEVPATH="/dev/rtc0" CONFIG_EXAMPLES_ALARM_SIGNO=1 +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -822,6 +911,7 @@ CONFIG_EXAMPLES_NSAMPLES=8 # CONFIG_EXAMPLES_SMART is not set # CONFIG_EXAMPLES_SMART_TEST is not set # CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_STAT is not set # CONFIG_EXAMPLES_TCPECHO is not set # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_TIFF is not set @@ -852,6 +942,7 @@ CONFIG_EXAMPLES_NSAMPLES=8 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -922,6 +1013,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -944,6 +1036,7 @@ CONFIG_NSH_MMCSDMINOR=0 # Configure Command Options # # CONFIG_NSH_CMDOPT_DF_H is not set +# CONFIG_NSH_CMDOPT_DD_STATS is not set CONFIG_NSH_CODECS_BUFSIZE=128 # CONFIG_NSH_CMDOPT_HEXDUMP is not set CONFIG_NSH_FILEIOSIZE=512 @@ -989,6 +1082,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/nucleo-l476rg/src/stm32_ajoystick.c b/configs/nucleo-l476rg/src/stm32_ajoystick.c index 1fc72b5629c..3c20ebca2ec 100644 --- a/configs/nucleo-l476rg/src/stm32_ajoystick.c +++ b/configs/nucleo-l476rg/src/stm32_ajoystick.c @@ -121,7 +121,7 @@ static void ajoy_enable(FAR const struct ajoy_lowerhalf_s *lower, ajoy_handler_t handler, FAR void *arg); static void ajoy_disable(void); -static int ajoy_interrupt(int irq, FAR void *context); +static int ajoy_interrupt(int irq, FAR void *context, FAR void *arg); /**************************************************************************** * Private Data @@ -376,7 +376,7 @@ static void ajoy_enable(FAR const struct ajoy_lowerhalf_s *lower, i, rising, falling); (void)stm32_gpiosetevent(g_joygpio[i], rising, falling, - true, ajoy_interrupt); + true, ajoy_interrupt, NULL); } } } @@ -402,7 +402,7 @@ static void ajoy_disable(void) flags = up_irq_save(); for (i = 0; i < AJOY_NGPIOS; i++) { - (void)stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL); + (void)stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); } up_irq_restore(flags); @@ -421,7 +421,7 @@ static void ajoy_disable(void) * ****************************************************************************/ -static int ajoy_interrupt(int irq, FAR void *context) +static int ajoy_interrupt(int irq, FAR void *context, FAR void *arg) { DEBUGASSERT(g_ajoyhandler); diff --git a/configs/nucleo-l476rg/src/stm32_buttons.c b/configs/nucleo-l476rg/src/stm32_buttons.c index f9211a13c7d..63a96d7a92c 100644 --- a/configs/nucleo-l476rg/src/stm32_buttons.c +++ b/configs/nucleo-l476rg/src/stm32_buttons.c @@ -123,13 +123,14 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; if (id == BUTTON_USER) { - oldhandler = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); } return oldhandler; diff --git a/configs/nucleo-l476rg/src/stm32_io.c b/configs/nucleo-l476rg/src/stm32_io.c index d98f2985bf2..d6468c5d053 100644 --- a/configs/nucleo-l476rg/src/stm32_io.c +++ b/configs/nucleo-l476rg/src/stm32_io.c @@ -184,11 +184,13 @@ xcpt_t up_irqio(int id, xcpt_t irqhandler) if (id == 0) { - oldhandler = stm32_gpiosetevent(GPIO_D14, true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(GPIO_D14, true, true, true, + irqhandler, NULL); } else if (id == 1) { - oldhandler = stm32_gpiosetevent(GPIO_D15, true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(GPIO_D15, true, true, true, + irqhandler, NULL); } return oldhandler; diff --git a/configs/nucleo-l476rg/src/stm32_wireless.c b/configs/nucleo-l476rg/src/stm32_wireless.c index c17da677feb..b65a5eaae5f 100644 --- a/configs/nucleo-l476rg/src/stm32_wireless.c +++ b/configs/nucleo-l476rg/src/stm32_wireless.c @@ -118,7 +118,8 @@ struct stm32_config_s * wl_read_irq - Return the state of the interrupt GPIO input */ -static int wl_attach_irq(FAR struct cc3000_config_s *state, xcpt_t handler); +static int wl_attach_irq(FAR struct cc3000_config_s *state, xcpt_t handler, + FAR void *arg); static void wl_enable_irq(FAR struct cc3000_config_s *state, bool enable); static void wl_clear_irq(FAR struct cc3000_config_s *state); static void wl_select(FAR struct cc3000_config_s *state, bool enable); @@ -157,6 +158,7 @@ static struct stm32_config_s g_cc3000_info = .dev.probe = probe, /* This is used for debugging */ #endif .handler = NULL, + .arg = NULL, }; /**************************************************************************** @@ -175,13 +177,15 @@ static struct stm32_config_s g_cc3000_info = * pendown - Return the state of the pen down GPIO input */ -static int wl_attach_irq(FAR struct cc3000_config_s *state, xcpt_t handler) +static int wl_attach_irq(FAR struct cc3000_config_s *state, xcpt_t handler, + FAR void *arg) { FAR struct stm32_config_s *priv = (FAR struct stm32_config_s *)state; /* Just save the handler for use when the interrupt is enabled */ priv->handler = handler; + priv->arg = arg; return OK; } @@ -200,11 +204,13 @@ static void wl_enable_irq(FAR struct cc3000_config_s *state, bool enable) iinfo("enable:%d\n", enable); if (enable) { - (void)stm32_gpiosetevent(GPIO_WIFI_INT, false, true, false, priv->handler); + (void)stm32_gpiosetevent(GPIO_WIFI_INT, false, true, false, + priv->handler, priv->arg); } else { - (void)stm32_gpiosetevent(GPIO_WIFI_INT, false, false, false, NULL); + (void)stm32_gpiosetevent(GPIO_WIFI_INT, false, false, false, + NULL, NULL); } } diff --git a/configs/olimex-efm32g880f128-stk/src/efm32_buttons.c b/configs/olimex-efm32g880f128-stk/src/efm32_buttons.c index 5545d5dac77..10c0df1ae00 100644 --- a/configs/olimex-efm32g880f128-stk/src/efm32_buttons.c +++ b/configs/olimex-efm32g880f128-stk/src/efm32_buttons.c @@ -168,7 +168,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_EFM32_GPIO_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -205,7 +205,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) /* Attach and enable the interrupt */ - (void)irq_attach(g_button_irqs[id], irqhandler); + (void)irq_attach(g_button_irqs[id], irqhandler, NULL); efm32_gpioirqenable(g_button_irqs[id]); } else diff --git a/configs/olimex-lpc1766stk/src/lpc17_buttons.c b/configs/olimex-lpc1766stk/src/lpc17_buttons.c index 888335f46bc..3b541d94024 100644 --- a/configs/olimex-lpc1766stk/src/lpc17_buttons.c +++ b/configs/olimex-lpc1766stk/src/lpc17_buttons.c @@ -182,7 +182,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_GPIOIRQ) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; irqstate_t flags; @@ -210,7 +210,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) { /* Attach then enable the new interrupt handler */ - (void)irq_attach(irq, irqhandler); + (void)irq_attach(irq, irqhandler, NULL); up_enable_irq(irq); } else diff --git a/configs/olimex-lpc1766stk/src/lpc17_ssp.c b/configs/olimex-lpc1766stk/src/lpc17_ssp.c index 17df5733e0e..7317a014b0f 100644 --- a/configs/olimex-lpc1766stk/src/lpc17_ssp.c +++ b/configs/olimex-lpc1766stk/src/lpc17_ssp.c @@ -142,7 +142,7 @@ static void ssp_cdirqsetup(int irq, xcpt_t irqhandler) { /* Attach then enable the new interrupt handler */ - (void)irq_attach(irq, irqhandler); + (void)irq_attach(irq, irqhandler, NULL); up_enable_irq(irq); } else diff --git a/configs/olimex-stm32-e407/include/board.h b/configs/olimex-stm32-e407/include/board.h index b1dff5e69a1..df7751c5795 100644 --- a/configs/olimex-stm32-e407/include/board.h +++ b/configs/olimex-stm32-e407/include/board.h @@ -1,7 +1,7 @@ /************************************************************************************ * configs/olimex-stm32-e407/include/board.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * Modified for H407 Neil Hancock * Modified for E407 Mateusz Szafoni @@ -160,13 +160,19 @@ #define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx +/* Timer Frequencies, if APBx is set to 1, frequency is same as APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY /* LED definitions ******************************************************************/ /* If CONFIG_ARCH_LEDS is not defined, then the user can control the status LED in any diff --git a/configs/olimex-stm32-e407/src/stm32_buttons.c b/configs/olimex-stm32-e407/src/stm32_buttons.c index 951df8ef1c4..32681e5e2d9 100644 --- a/configs/olimex-stm32-e407/src/stm32_buttons.c +++ b/configs/olimex-stm32-e407/src/stm32_buttons.c @@ -133,7 +133,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -142,7 +142,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { oldhandler = - stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler); + stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, arg); } return oldhandler; diff --git a/configs/olimex-stm32-e407/src/stm32_usb.c b/configs/olimex-stm32-e407/src/stm32_usb.c index db93fcbf178..55df883ba8d 100644 --- a/configs/olimex-stm32-e407/src/stm32_usb.c +++ b/configs/olimex-stm32-e407/src/stm32_usb.c @@ -311,7 +311,7 @@ void stm32_usbhost_vbusdrive(int iface, bool enable) #ifdef CONFIG_USBHOST xcpt_t stm32_setup_overcurrent(xcpt_t handler) { - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler); + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); } #endif diff --git a/configs/olimex-stm32-h405/src/stm32_buttons.c b/configs/olimex-stm32-h405/src/stm32_buttons.c index aefe40fc8c3..03092eaece8 100644 --- a/configs/olimex-stm32-h405/src/stm32_buttons.c +++ b/configs/olimex-stm32-h405/src/stm32_buttons.c @@ -141,7 +141,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -149,7 +149,8 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); } return oldhandler; diff --git a/configs/olimex-stm32-h407/src/stm32_buttons.c b/configs/olimex-stm32-h407/src/stm32_buttons.c index 47873bf39b5..da8c5657654 100644 --- a/configs/olimex-stm32-h407/src/stm32_buttons.c +++ b/configs/olimex-stm32-h407/src/stm32_buttons.c @@ -133,7 +133,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -141,7 +141,8 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); } return oldhandler; diff --git a/configs/olimex-stm32-h407/src/stm32_sdio.c b/configs/olimex-stm32-h407/src/stm32_sdio.c index 05df07dee81..f87e76c741e 100644 --- a/configs/olimex-stm32-h407/src/stm32_sdio.c +++ b/configs/olimex-stm32-h407/src/stm32_sdio.c @@ -128,7 +128,8 @@ int stm32_sdio_initialize(void) /* Register an interrupt handler for the card detect pin */ - stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, stm32_ncd_interrupt); + stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, + stm32_ncd_interrupt, NULL); #endif /* Mount the SDIO-based MMC/SD block driver */ diff --git a/configs/olimex-stm32-h407/src/stm32_usb.c b/configs/olimex-stm32-h407/src/stm32_usb.c index d948604a3b2..10cb1c16d46 100644 --- a/configs/olimex-stm32-h407/src/stm32_usb.c +++ b/configs/olimex-stm32-h407/src/stm32_usb.c @@ -289,7 +289,7 @@ void stm32_usbhost_vbusdrive(int iface, bool enable) #ifdef CONFIG_USBHOST xcpt_t stm32_setup_overcurrent(xcpt_t handler) { - return stm32_gpiosetevent(GPIO_OTGHS_OVER, true, true, true, handler); + return stm32_gpiosetevent(GPIO_OTGHS_OVER, true, true, true, handler, NULL); } #endif diff --git a/configs/olimex-stm32-p107/src/stm32_encx24j600.c b/configs/olimex-stm32-p107/src/stm32_encx24j600.c index c5ec3b96636..6654c7bd329 100644 --- a/configs/olimex-stm32-p107/src/stm32_encx24j600.c +++ b/configs/olimex-stm32-p107/src/stm32_encx24j600.c @@ -151,12 +151,14 @@ static void up_enable(FAR const struct enc_lower_s *lower) FAR struct stm32_lower_s *priv = (FAR struct stm32_lower_s *)lower; DEBUGASSERT(priv->handler); - (void)stm32_gpiosetevent(GPIO_ENCX24J600_INTR, false, true, true, priv->handler); + (void)stm32_gpiosetevent(GPIO_ENCX24J600_INTR, false, true, true, + priv->handler, NULL); } static void up_disable(FAR const struct enc_lower_s *lower) { - (void)stm32_gpiosetevent(GPIO_ENCX24J600_INTR, false, true, true, NULL); + (void)stm32_gpiosetevent(GPIO_ENCX24J600_INTR, false, true, true, + NULL, NULL); } /**************************************************************************** diff --git a/configs/olimex-stm32-p207/src/stm32_buttons.c b/configs/olimex-stm32-p207/src/stm32_buttons.c index 5caaeab8351..17c0cc50ff4 100644 --- a/configs/olimex-stm32-p207/src/stm32_buttons.c +++ b/configs/olimex-stm32-p207/src/stm32_buttons.c @@ -177,7 +177,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -185,7 +185,8 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); } return oldhandler; diff --git a/configs/olimex-stm32-p207/src/stm32_usb.c b/configs/olimex-stm32-p207/src/stm32_usb.c index 65198bf0041..9996da8b7fe 100644 --- a/configs/olimex-stm32-p207/src/stm32_usb.c +++ b/configs/olimex-stm32-p207/src/stm32_usb.c @@ -247,7 +247,7 @@ int stm32_usbhost_initialize(void) #ifdef CONFIG_USBHOST xcpt_t stm32_setup_overcurrent(xcpt_t handler) { - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler); + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); } #endif diff --git a/configs/olimex-stm32-p407/include/board.h b/configs/olimex-stm32-p407/include/board.h index 75038ad39d9..888ddad8735 100644 --- a/configs/olimex-stm32-p407/include/board.h +++ b/configs/olimex-stm32-p407/include/board.h @@ -45,8 +45,6 @@ #ifndef __ASSEMBLY__ # include #endif -#include "stm32_rcc.h" -#include "stm32.h" /************************************************************************************ * Pre-processor Definitions @@ -235,6 +233,11 @@ #define GPIO_USART3_CTS GPIO_USART3_CTS_2 /* PD11 */ #define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */ +/* USART6: */ + +#define GPIO_USART6_RX GPIO_USART6_RX_2 /* PG9 */ +#define GPIO_USART6_TX GPIO_USART6_TX_1 /* PC6 */ + /* CAN: */ #define GPIO_CAN1_RX GPIO_CAN1_RX_2 /* PB8 */ diff --git a/configs/olimex-stm32-p407/knsh/defconfig b/configs/olimex-stm32-p407/knsh/defconfig index d49b31fbd7d..4e30aad6199 100644 --- a/configs/olimex-stm32-p407/knsh/defconfig +++ b/configs/olimex-stm32-p407/knsh/defconfig @@ -944,7 +944,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/olimex-stm32-p407/nsh/defconfig b/configs/olimex-stm32-p407/nsh/defconfig index 1d81763bc97..264454ff37a 100644 --- a/configs/olimex-stm32-p407/nsh/defconfig +++ b/configs/olimex-stm32-p407/nsh/defconfig @@ -937,7 +937,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/olimex-stm32-p407/src/Makefile b/configs/olimex-stm32-p407/src/Makefile index fa543389eb4..6c580d3f096 100644 --- a/configs/olimex-stm32-p407/src/Makefile +++ b/configs/olimex-stm32-p407/src/Makefile @@ -48,6 +48,11 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif + +ifeq ($(CONFIG_STM32_FSMC),y) +CSRCS += stm32_sram.c +endif + ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif diff --git a/configs/olimex-stm32-p407/src/olimex-stm32-p407.h b/configs/olimex-stm32-p407/src/olimex-stm32-p407.h index ecf95b60c0a..76cc41e8604 100644 --- a/configs/olimex-stm32-p407/src/olimex-stm32-p407.h +++ b/configs/olimex-stm32-p407/src/olimex-stm32-p407.h @@ -190,6 +190,36 @@ int stm32_bringup(void); +/************************************************************************************ + * Name: stm32_stram_configure + * + * Description: + * Initialize to access external SRAM. SRAM will be visible at the FSMC Bank + * NOR/SRAM2 base address (0x64000000) + * + * General transaction rules. The requested AHB transaction data size can be 8-, + * 16- or 32-bit wide whereas the SRAM has a fixed 16-bit data width. Some simple + * transaction rules must be followed: + * + * Case 1: AHB transaction width and SRAM data width are equal + * There is no issue in this case. + * Case 2: AHB transaction size is greater than the memory size + * In this case, the FSMC splits the AHB transaction into smaller consecutive + * memory accesses in order to meet the external data width. + * Case 3: AHB transaction size is smaller than the memory size. + * SRAM supports the byte select feature. + * a) FSMC allows write transactions accessing the right data through its + * byte lanes (NBL[1:0]) + * b) Read transactions are allowed (the controller reads the entire memory + * word and uses the needed byte only). The NBL[1:0] are always kept low + * during read transactions. + * + ************************************************************************************/ + +#ifdef CONFIG_STM32_FSMC +void stm32_stram_configure(void); +#endif + /************************************************************************************ * Name: stm32_usb_configure * diff --git a/configs/olimex-stm32-p407/src/stm32_boot.c b/configs/olimex-stm32-p407/src/stm32_boot.c index 220455fef01..f52fe6d2e03 100644 --- a/configs/olimex-stm32-p407/src/stm32_boot.c +++ b/configs/olimex-stm32-p407/src/stm32_boot.c @@ -63,6 +63,12 @@ void stm32_boardinitialize(void) { +#ifdef CONFIG_STM32_FSMC + /* If the FSMC is enabled, then enable SRAM access */ + + stm32_stram_configure(); +#endif + /* Initialize USB if the 1) OTG FS controller is in the configuration and 2) * disabled, and 3) the weak function stm32_usb_configure() has been brought * into the build. Presumeably either CONFIG_USBDEV or CONFIG_USBHOST is also diff --git a/configs/olimex-stm32-p407/src/stm32_bringup.c b/configs/olimex-stm32-p407/src/stm32_bringup.c index 0894f48b92b..2529cbd87a4 100644 --- a/configs/olimex-stm32-p407/src/stm32_bringup.c +++ b/configs/olimex-stm32-p407/src/stm32_bringup.c @@ -47,6 +47,7 @@ #include #include +#include #ifdef CONFIG_USBMONITOR # include @@ -169,6 +170,16 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/configs/olimex-stm32-p407/src/stm32_buttons.c b/configs/olimex-stm32-p407/src/stm32_buttons.c index 94580ec5a1c..ab07a2ed1e9 100644 --- a/configs/olimex-stm32-p407/src/stm32_buttons.c +++ b/configs/olimex-stm32-p407/src/stm32_buttons.c @@ -45,18 +45,12 @@ #include #include +#include "stm32_gpio.h" + #include "olimex-stm32-p407.h" #ifdef CONFIG_ARCH_BUTTONS -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -177,7 +171,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -185,7 +179,8 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); } return oldhandler; diff --git a/configs/olimex-stm32-p407/src/stm32_sram.c b/configs/olimex-stm32-p407/src/stm32_sram.c new file mode 100644 index 00000000000..3350c467af4 --- /dev/null +++ b/configs/olimex-stm32-p407/src/stm32_sram.c @@ -0,0 +1,262 @@ +/************************************************************************************ + * configs/olimex-stm32-p407/src/stm32_sram.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" + +#include "stm32.h" +#include "stm3240g-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +#if defined(CONFIG_STM32_USART3) || defined(CONFIG_STM32_USART6) +# error "USART3 and USART6 conflict with use of SRAM" +#endif + +/* SRAM Timing + * REVIST: These were ported from the STM3240G-EVAL and have not been verified on + * this platform. + */ + +#define SRAM_ADDRESS_SETUP_TIME 3 +#define SRAM_ADDRESS_HOLD_TIME 0 +#define SRAM_DATA_SETUP_TIME 6 +#define SRAM_BUS_TURNAROUND_DURATION 1 +#define SRAM_CLK_DIVISION 0 +#define SRAM_DATA_LATENCY 0 + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +/* GPIOs Configuration ************************************************************** + *---------------------+------------------+------------------+-----------------+ + * GPIO FSMC NOTE |GPIO FSMC NOTE|GPIO FSMC NOTE|GPIO FSMC NOTE| + *---------------------+------------------+------------------+-----------------+ + * PD0 FSMC_D2 |PE0 FSMC_NBL0 |PF0 FSMC_A0 |PG0 FSMC_A10 | + * PD1 FSMC_D3 |PE1 FSMC_NBL1 |PF1 FSMC_A1 |PG1 FSMC_A11 | + * | |PF2 FSMC_A2 |PG2 FSMC_A12 | + * | |PF3 FSMC_A3 |PG3 FSMC_A13 | + * PD4 FSMC_NOE 2 | |PF4 FSMC_A4 |PG4 FSMC_A14 | + * PD5 FSMC_NWE | |PF5 FSMC_A5 |PG5 FSMC_A15 | + * | | | | + * PD7 FSMC_NE1/NCE2 |PE7 FSMC_D4 | | | + * PD8 FSMC_D13 1 |PE8 FSMC_D5 | | | + * PD9 FSMC_D14 1 |PE9 FSMC_D6 | | | + * PD10 FSMC_D15 1 |PE10 FSMC_D7 | | | + * PD11 FSMC_A16 1 |PE11 FSMC_D8 | | | + * PD12 FSMC_A17 |PE12 FSMC_D9 |PF12 FSMC_A6 | | + * |PE13 FSMC_D10 |PF13 FSMC_A7 | | + * PD14 FSMC_D0 |PE14 FSMC_D11 |PF14 FSMC_A8 | | + * PD15 FSMC_D1 |PE15 FSMC_D12 |PF15 FSMC_A9 | | + *---------------------+------------------+------------------+-----------------+ + * + * NOTES: + * (1) Shared with USART3: PD8=USART3_TX PD9=USART3_RX PD11=USART3_CTS + * PD12=USART3_RTS + * (2) Shared with USB: PD4=USB_HS_FAULT + */ + +/* SRAM GPIO configuration */ + +static const uint32_t g_sramconfig[] = +{ + /* Address configuration: FSMC_A0-FSMC_A17 */ + + GPIO_FSMC_A0, GPIO_FSMC_A1 , GPIO_FSMC_A2, GPIO_FSMC_A3, GPIO_FSMC_A4 , GPIO_FSMC_A5, + GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, + GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, + + /* Data Configuration: FSMC_D0-FSMC_D15 */ + + GPIO_FSMC_D0, GPIO_FSMC_D1 , GPIO_FSMC_D2, GPIO_FSMC_D3, GPIO_FSMC_D4 , GPIO_FSMC_D5, + GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, + GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, GPIO_FSMC_D15 + + /* Control Signals: + * + * /CS = PD7, FSMC_NE1 + * /OE = PD4, FSMC_NOE + * /WE = PD5, FSMC_NWE + * /BHE = PE0, FSMC_NBL0 + * /BHL = PE1, PSMC_NBL1 + */ + + GPIO_FSMC_NE1, GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NBL0, GPIO_FSMC_NBL1 +}; +#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint32_t)) + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_enablefsmc + * + * Description: + * Enable clocking to the FSMC module + * + ************************************************************************************/ + +static void stm32_enablefsmc(void) +{ + uint32_t regval; + + /* Enable AHB clocking to the FSMC */ + + regval = getreg32( STM32_RCC_AHB3ENR); + regval |= RCC_AHB3ENR_FSMCEN; + putreg32(regval, STM32_RCC_AHB3ENR); +} + +/************************************************************************************ + * Name: stm32_sramgpios + * + * Description: + * Configure SRAM GPIO pins + * + ************************************************************************************/ + +static void stm32_sramgpios(void) +{ + int i; + + /* Configure SRAM GPIOs */ + + for (i = 0; i < NSRAM_CONFIG; i++) + { + stm32_configgpio(g_sramconfig[i]); + } +} + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_stram_configure + * + * Description: + * Initialize to access external SRAM. SRAM will be visible at the FSMC Bank + * NOR/SRAM2 base address (0x64000000) + * + * General transaction rules. The requested AHB transaction data size can be 8-, + * 16- or 32-bit wide whereas the SRAM has a fixed 16-bit data width. Some simple + * transaction rules must be followed: + * + * Case 1: AHB transaction width and SRAM data width are equal + * There is no issue in this case. + * Case 2: AHB transaction size is greater than the memory size + * In this case, the FSMC splits the AHB transaction into smaller consecutive + * memory accesses in order to meet the external data width. + * Case 3: AHB transaction size is smaller than the memory size. + * SRAM supports the byte select feature. + * a) FSMC allows write transactions accessing the right data through its + * byte lanes (NBL[1:0]) + * b) Read transactions are allowed (the controller reads the entire memory + * word and uses the needed byte only). The NBL[1:0] are always kept low + * during read transactions. + * + ************************************************************************************/ + +void stm32_stram_configure(void) +{ + /* Configure GPIO pins */ + + stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG); /* SRAM-specific control lines */ + + /* Enable AHB clocking to the FSMC */ + + stm32_enablefsmc(); + + /* Bank1 NOR/SRAM control register configuration + * + * Bank enable : Not yet + * Data address mux : Disabled + * Memory Type : PSRAM + * Data bus width : 16-bits + * Flash access : Disabled + * Burst access mode : Disabled + * Polarity : Low + * Wrapped burst mode : Disabled + * Write timing : Before state + * Write enable : Yes + * Wait signal : Disabled + * Extended mode : Disabled + * Asynchronous wait : Disabled + * Write burst : Disabled + */ + + putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) | + FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) | + FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) | FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) | + FSMC_BTR_ACCMODA), + STM32_FSMC_BTR2); + + /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + + putreg32(0xffffffff, STM32_FSMC_BWTR2); /* Extended mode not used */ + + /* Enable the bank */ + + putreg32((FSMC_BCR_MBKEN | FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/configs/olimex-stm32-p407/src/stm32_usb.c b/configs/olimex-stm32-p407/src/stm32_usb.c index e6340dcc50f..4c3799e3af0 100644 --- a/configs/olimex-stm32-p407/src/stm32_usb.c +++ b/configs/olimex-stm32-p407/src/stm32_usb.c @@ -247,7 +247,7 @@ int stm32_usbhost_setup(void) #ifdef CONFIG_USBHOST xcpt_t stm32_setup_overcurrent(xcpt_t handler) { - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler); + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); } #endif diff --git a/configs/olimex-strp711/src/str71_enc28j60.c b/configs/olimex-strp711/src/str71_enc28j60.c index 73d16f1eadc..5b40eb13570 100644 --- a/configs/olimex-strp711/src/str71_enc28j60.c +++ b/configs/olimex-strp711/src/str71_enc28j60.c @@ -184,7 +184,7 @@ static const struct enc_lower_s g_enclower = static int up_attach(FAR const struct enc_lower_s *lower, xcpt_t handler) { - return irq_attach(ENC28J60_IRQ, handler); + return irq_attach(ENC28J60_IRQ, handler, NULL); } static void up_enable(FAR const struct enc_lower_s *lower) diff --git a/configs/olimexino-stm32/src/stm32_buttons.c b/configs/olimexino-stm32/src/stm32_buttons.c index 85066d568f6..55021c3a948 100644 --- a/configs/olimexino-stm32/src/stm32_buttons.c +++ b/configs/olimexino-stm32/src/stm32_buttons.c @@ -133,7 +133,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -141,7 +141,8 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (id == IRQBUTTON) { - oldhandler = stm32_gpiosetevent(BUTTON_BOOT0n, true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(BUTTON_BOOT0n, true, true, true, + irqhandler, arg); } return oldhandler; diff --git a/configs/olimexino-stm32/src/stm32_usbdev.c b/configs/olimexino-stm32/src/stm32_usbdev.c index dd0846ae48c..148ae443129 100644 --- a/configs/olimexino-stm32/src/stm32_usbdev.c +++ b/configs/olimexino-stm32/src/stm32_usbdev.c @@ -77,7 +77,7 @@ void stm32_usb_set_pwr_callback(xcpt_t pwr_changed_handler) { - (void) stm32_gpiosetevent(GPIO_USB_VBUS, true, true, true, pwr_changed_handler); + (void)stm32_gpiosetevent(GPIO_USB_VBUS, true, true, true, pwr_changed_handler, NULL); } /************************************************************************************ diff --git a/configs/open1788/knsh/defconfig b/configs/open1788/knsh/defconfig index 07bc4bb806e..77f55906843 100644 --- a/configs/open1788/knsh/defconfig +++ b/configs/open1788/knsh/defconfig @@ -687,7 +687,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/open1788/nsh/defconfig b/configs/open1788/nsh/defconfig index 98453cfa474..cadcbd8d9d4 100644 --- a/configs/open1788/nsh/defconfig +++ b/configs/open1788/nsh/defconfig @@ -684,7 +684,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/open1788/src/lpc17_appinit.c b/configs/open1788/src/lpc17_appinit.c index d25f9bc2d18..7a43837649f 100644 --- a/configs/open1788/src/lpc17_appinit.c +++ b/configs/open1788/src/lpc17_appinit.c @@ -209,7 +209,7 @@ static int nsh_waiter(int argc, char *argv[]) ****************************************************************************/ #ifdef NSH_HAVE_MMCSD_CDINT -static int nsh_cdinterrupt(int irq, FAR void *context) +static int nsh_cdinterrupt(int irq, FAR void *context, FAR void *arg) { static bool inserted = 0xff; /* Impossible value */ bool present; @@ -249,7 +249,7 @@ static int nsh_sdinitialize(void) #ifdef NSH_HAVE_MMCSD_CDINT - (void)irq_attach(LPC17_IRQ_P0p13, nsh_cdinterrupt); + (void)irq_attach(LPC17_IRQ_P0p13, nsh_cdinterrupt, NULL); up_enable_irq(LPC17_IRQ_P0p13); #endif diff --git a/configs/open1788/src/lpc17_buttons.c b/configs/open1788/src/lpc17_buttons.c index 5ad2814f1ac..c9313525524 100644 --- a/configs/open1788/src/lpc17_buttons.c +++ b/configs/open1788/src/lpc17_buttons.c @@ -200,7 +200,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_GPIOIRQ) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; irqstate_t flags; @@ -234,7 +234,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) { /* Attach then enable the new interrupt handler */ - (void)irq_attach(irq, irqhandler); + (void)irq_attach(irq, irqhandler, NULL); up_enable_irq(irq); } else diff --git a/configs/open1788/src/lpc17_touchscreen.c b/configs/open1788/src/lpc17_touchscreen.c index 008abc0660d..f6143069796 100644 --- a/configs/open1788/src/lpc17_touchscreen.c +++ b/configs/open1788/src/lpc17_touchscreen.c @@ -169,7 +169,7 @@ static int tsc_attach(FAR struct ads7843e_config_s *state, xcpt_t handler) { /* Attach then enable the touchscreen interrupt handler */ - (void)irq_attach(LPC17_IRQ_PENIRQ, handler); + (void)irq_attach(LPC17_IRQ_PENIRQ, handler, NULL); return OK; } diff --git a/configs/pcduino-a10/src/a1x_buttons.c b/configs/pcduino-a10/src/a1x_buttons.c index 1802b3656d8..2cc53b81d6b 100644 --- a/configs/pcduino-a10/src/a1x_buttons.c +++ b/configs/pcduino-a10/src/a1x_buttons.c @@ -120,7 +120,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -142,7 +142,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) /* Configure the interrupt */ a1x_pioirq(xxx); - (void)irq_attach(xxx, irqhandler); + (void)irq_attach(xxx, irqhandler, NULL); a1x_pioirqenable(xxx); leave_critical_section(flags); } diff --git a/configs/pic32mz-starterkit/src/pic32mz_buttons.c b/configs/pic32mz-starterkit/src/pic32mz_buttons.c index 4e26b559507..d5e06bd3104 100644 --- a/configs/pic32mz-starterkit/src/pic32mz_buttons.c +++ b/configs/pic32mz-starterkit/src/pic32mz_buttons.c @@ -152,7 +152,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { #ifdef CONFIG_PIC32MZ_GPIOIRQ_PORTB xcpt_t oldhandler = NULL; diff --git a/configs/sam3u-ek/src/sam_buttons.c b/configs/sam3u-ek/src/sam_buttons.c index 57d087792ff..6bfdf269d54 100644 --- a/configs/sam3u-ek/src/sam_buttons.c +++ b/configs/sam3u-ek/src/sam_buttons.c @@ -80,7 +80,7 @@ static xcpt_t g_irqbutton2; #if defined(CONFIG_SAM34_GPIOA_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) static xcpt_t board_button_irqx(gpio_pinset_t pinset, int irq, - xcpt_t irqhandler, xcpt_t *store) + xcpt_t irqhandler, xcpt_t *store, void *arg) { xcpt_t oldhandler; irqstate_t flags; @@ -103,7 +103,7 @@ static xcpt_t board_button_irqx(gpio_pinset_t pinset, int irq, /* Configure the interrupt */ sam_gpioirq(pinset); - (void)irq_attach(irq, irqhandler); + (void)irq_attach(irq, irqhandler, arg); sam_gpioirqenable(irq); } else @@ -183,17 +183,17 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_SAM34_GPIOA_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { if (id == BUTTON1) { return board_button_irqx(GPIO_BUTTON1, IRQ_BUTTON1, - irqhandler, &g_irqbutton1); + irqhandler, &g_irqbutton1, arg); } else if (id == BUTTON2) { return board_button_irqx(GPIO_BUTTON2, IRQ_BUTTON2, - irqhandler, &g_irqbutton2); + irqhandler, &g_irqbutton2, arg); } else { diff --git a/configs/sam3u-ek/src/sam_touchscreen.c b/configs/sam3u-ek/src/sam_touchscreen.c index 7dec7f8e7a3..c5cc9df288d 100644 --- a/configs/sam3u-ek/src/sam_touchscreen.c +++ b/configs/sam3u-ek/src/sam_touchscreen.c @@ -157,7 +157,7 @@ static int tsc_attach(FAR struct ads7843e_config_s *state, xcpt_t isr) /* Attach the ADS7843E interrupt */ iinfo("Attaching %p to IRQ %d\n", isr, SAM_TCS_IRQ); - return irq_attach(SAM_TCS_IRQ, isr); + return irq_attach(SAM_TCS_IRQ, isr, NULL); } static void tsc_enable(FAR struct ads7843e_config_s *state, bool enable) diff --git a/configs/sam4e-ek/src/sam_ads7843e.c b/configs/sam4e-ek/src/sam_ads7843e.c index d4b555aa449..82dd848cd90 100644 --- a/configs/sam4e-ek/src/sam_ads7843e.c +++ b/configs/sam4e-ek/src/sam_ads7843e.c @@ -154,7 +154,7 @@ static int tsc_attach(FAR struct ads7843e_config_s *state, xcpt_t isr) /* Attach the ADS7843E interrupt */ iinfo("Attaching %p to IRQ %d\n", isr, SAM_TCS_IRQ); - return irq_attach(SAM_TCS_IRQ, isr); + return irq_attach(SAM_TCS_IRQ, isr, NULL); } static void tsc_enable(FAR struct ads7843e_config_s *state, bool enable) diff --git a/configs/sam4e-ek/src/sam_buttons.c b/configs/sam4e-ek/src/sam_buttons.c index d6650047284..23851d10832 100644 --- a/configs/sam4e-ek/src/sam_buttons.c +++ b/configs/sam4e-ek/src/sam_buttons.c @@ -82,7 +82,7 @@ static xcpt_t g_irq_tamp; #if defined(CONFIG_SAM34_GPIOA_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) static xcpt_t board_button_irqx(gpio_pinset_t pinset, int irq, - xcpt_t irqhandler, xcpt_t *store) + xcpt_t irqhandler, xcpt_t *store, void *arg) { xcpt_t oldhandler; irqstate_t flags; @@ -105,7 +105,7 @@ static xcpt_t board_button_irqx(gpio_pinset_t pinset, int irq, /* Configure the interrupt */ sam_gpioirq(pinset); - (void)irq_attach(irq, irqhandler); + (void)irq_attach(irq, irqhandler, arg); sam_gpioirqenable(irq); } else @@ -189,25 +189,25 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_SAM34_GPIOA_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { switch (id) { case BUTTON_SCROLLUP: return board_button_irqx(GPIO_SCROLLUP, IRQ_SCROLLUP, - irqhandler, &g_irq_scrollup); + irqhandler, &g_irq_scrollup, arg); case BUTTON_SCROLLDOWN: return board_button_irqx(GPIO_SCROLLDWN, IRQ_SCROLLDWN, - irqhandler, &g_irq_scrolldown); + irqhandler, &g_irq_scrolldown, arg); case BUTTON_WAKU: return board_button_irqx(GPIO_WAKU, IRQ_WAKU, - irqhandler, &g_irq_waku); + irqhandler, &g_irq_waku, arg); case BUTTON_TAMP: return board_button_irqx(GPIO_TAMP, IRQ_TAMP, - irqhandler, &g_irq_tamp); + irqhandler, &g_irq_tamp, arg); default: return NULL; diff --git a/configs/sam4e-ek/src/sam_ethernet.c b/configs/sam4e-ek/src/sam_ethernet.c index b15cf06107a..c59e395e94f 100644 --- a/configs/sam4e-ek/src/sam_ethernet.c +++ b/configs/sam4e-ek/src/sam_ethernet.c @@ -243,7 +243,7 @@ xcpt_t arch_phy_irq(FAR const char *intf, xcpt_t handler, phy_enable_t *enable) sam_gpioirq(pinset); phyinfo("Attach IRQ%d\n", irq); - (void)irq_attach(irq, handler); + (void)irq_attach(irq, handler, NULL); } else { diff --git a/configs/sam4e-ek/src/sam_hsmci.c b/configs/sam4e-ek/src/sam_hsmci.c index e799cf0d1b9..92eb8f7ba19 100644 --- a/configs/sam4e-ek/src/sam_hsmci.c +++ b/configs/sam4e-ek/src/sam_hsmci.c @@ -90,7 +90,7 @@ static struct sam_hsmci_state_s g_hsmci; * ****************************************************************************/ -static int sam_hsmci_cardetect(int irq, void *regs) +static int sam_hsmci_cardetect(int irq, void *regs, FAR void *arg) { bool inserted; @@ -160,7 +160,7 @@ int sam_hsmci_initialize(int minor) /* Configure card detect interrupts */ sam_gpioirq(GPIO_MCI_CD); - (void)irq_attach(MCI_CD_IRQ, sam_hsmci_cardetect); + (void)irq_attach(MCI_CD_IRQ, sam_hsmci_cardetect, NULL); /* Then inform the HSMCI driver if there is or is not a card in the slot. */ diff --git a/configs/sam4l-xplained/src/sam_buttons.c b/configs/sam4l-xplained/src/sam_buttons.c index f57cf79eb5b..9095bd820b5 100644 --- a/configs/sam4l-xplained/src/sam_buttons.c +++ b/configs/sam4l-xplained/src/sam_buttons.c @@ -124,7 +124,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_SAM34_GPIOA_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -150,7 +150,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) /* Configure the interrupt */ sam_gpioirq(GPIO_SW0); - (void)irq_attach(IRQ_SW0, irqhandler); + (void)irq_attach(IRQ_SW0, irqhandler, NULL); sam_gpioirqenable(IRQ_SW0); } else diff --git a/configs/sam4s-xplained-pro/nsh/defconfig b/configs/sam4s-xplained-pro/nsh/defconfig index 1dbfc022368..788b53c4faf 100644 --- a/configs/sam4s-xplained-pro/nsh/defconfig +++ b/configs/sam4s-xplained-pro/nsh/defconfig @@ -831,7 +831,6 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/sam4s-xplained-pro/src/sam_buttons.c b/configs/sam4s-xplained-pro/src/sam_buttons.c index 85d461217a5..0a4f057dd8a 100644 --- a/configs/sam4s-xplained-pro/src/sam_buttons.c +++ b/configs/sam4s-xplained-pro/src/sam_buttons.c @@ -123,7 +123,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_SAM34_GPIOA_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -149,7 +149,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) /* Configure the interrupt */ sam_gpioirq(GPIO_SW0); - (void)irq_attach(IRQ_SW0, irqhandler); + (void)irq_attach(IRQ_SW0, irqhandler, NULL); sam_gpioirqenable(IRQ_SW0); } else diff --git a/configs/sam4s-xplained-pro/src/sam_hsmci.c b/configs/sam4s-xplained-pro/src/sam_hsmci.c index e71e948de82..1446269a5d5 100644 --- a/configs/sam4s-xplained-pro/src/sam_hsmci.c +++ b/configs/sam4s-xplained-pro/src/sam_hsmci.c @@ -95,7 +95,7 @@ static struct sam_hsmci_state_s g_hsmci; ****************************************************************************/ #ifdef CONFIG_MMCSD_HAVECARDDETECT -static int sam_hsmci_cardetect_int(int irq, void *regs) +static int sam_hsmci_cardetect_int(int irq, void *regs, FAR void *arg) { bool inserted; @@ -168,7 +168,7 @@ int sam_hsmci_initialize(void) /* Configure card detect interrupts */ sam_gpioirq(GPIO_MCI_CD); - (void)irq_attach(MCI_CD_IRQ, sam_hsmci_cardetect_int); + (void)irq_attach(MCI_CD_IRQ, sam_hsmci_cardetect_int, NULL); g_hsmci.inserted = sam_cardinserted(0); #else g_hsmci.inserted = true; /* An assumption? */ diff --git a/configs/sam4s-xplained-pro/src/sam_wdt.c b/configs/sam4s-xplained-pro/src/sam_wdt.c index 4223671f395..fd3e01fe440 100644 --- a/configs/sam4s-xplained-pro/src/sam_wdt.c +++ b/configs/sam4s-xplained-pro/src/sam_wdt.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/sam4s-xplained-pro/src/up_watchdog.c + * configs/sam4s-xplained-pro/src/up_wdt.c * * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt diff --git a/configs/sam4s-xplained/src/sam_buttons.c b/configs/sam4s-xplained/src/sam_buttons.c index b48e88461bb..4ce25925927 100644 --- a/configs/sam4s-xplained/src/sam_buttons.c +++ b/configs/sam4s-xplained/src/sam_buttons.c @@ -124,7 +124,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_SAM34_GPIOA_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -150,7 +150,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) /* Configure the interrupt */ sam_gpioirq(GPIO_BP2); - (void)irq_attach(IRQ_BP2, irqhandler); + (void)irq_attach(IRQ_BP2, irqhandler, NULL); sam_gpioirqenable(IRQ_BP2); } else diff --git a/configs/sama5d2-xult/src/sam_buttons.c b/configs/sama5d2-xult/src/sam_buttons.c index 2bdef205c02..3dd77011814 100644 --- a/configs/sama5d2-xult/src/sam_buttons.c +++ b/configs/sama5d2-xult/src/sam_buttons.c @@ -133,7 +133,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_SAMA5_PIOB_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -159,7 +159,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) /* Configure the interrupt */ sam_pioirq(PIO_BTN_USER); - (void)irq_attach(IRQ_BTN_USER, irqhandler); + (void)irq_attach(IRQ_BTN_USER, irqhandler, NULL); sam_pioirqenable(IRQ_BTN_USER); } else diff --git a/configs/sama5d3-xplained/src/sam_ajoystick.c b/configs/sama5d3-xplained/src/sam_ajoystick.c index a4712eabf85..322240fd9da 100644 --- a/configs/sama5d3-xplained/src/sam_ajoystick.c +++ b/configs/sama5d3-xplained/src/sam_ajoystick.c @@ -107,7 +107,7 @@ static void ajoy_enable(FAR const struct ajoy_lowerhalf_s *lower, ajoy_handler_t handler, FAR void *arg); static void ajoy_disable(void); -static int ajoy_interrupt(int irq, FAR void *context); +static int ajoy_interrupt(int irq, FAR void *context, FAR void *arg); /**************************************************************************** * Private Data @@ -377,7 +377,7 @@ static void ajoy_disable(void) * ****************************************************************************/ -static int ajoy_interrupt(int irq, FAR void *context) +static int ajoy_interrupt(int irq, FAR void *context, FAR void *arg) { DEBUGASSERT(g_ajoyhandler); if (g_ajoyhandler) @@ -442,7 +442,7 @@ int sam_ajoy_initialization(void) */ sam_pioirq(g_joypio[i]); - (void)irq_attach(g_joyirq[i], ajoy_interrupt); + (void)irq_attach(g_joyirq[i], ajoy_interrupt, NULL); sam_pioirqdisable(g_joyirq[i]); } diff --git a/configs/sama5d3-xplained/src/sam_buttons.c b/configs/sama5d3-xplained/src/sam_buttons.c index 50636737c4e..b2d0af924ea 100644 --- a/configs/sama5d3-xplained/src/sam_buttons.c +++ b/configs/sama5d3-xplained/src/sam_buttons.c @@ -137,7 +137,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_SAMA5_PIOE_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -163,7 +163,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) /* Configure the interrupt */ sam_pioirq(PIO_USER); - (void)irq_attach(IRQ_USER1, irqhandler); + (void)irq_attach(IRQ_USER1, irqhandler, NULL); sam_pioirqenable(IRQ_USER1); } else diff --git a/configs/sama5d3-xplained/src/sam_ethernet.c b/configs/sama5d3-xplained/src/sam_ethernet.c index 8505711302a..bad7d48b92a 100644 --- a/configs/sama5d3-xplained/src/sam_ethernet.c +++ b/configs/sama5d3-xplained/src/sam_ethernet.c @@ -332,7 +332,7 @@ xcpt_t arch_phy_irq(FAR const char *intf, xcpt_t handler, phy_enable_t *enable) sam_pioirq(pinset); phyinfo("Attach IRQ%d\n", irq); - (void)irq_attach(irq, handler); + (void)irq_attach(irq, handler, NULL); } else { diff --git a/configs/sama5d3-xplained/src/sam_hsmci.c b/configs/sama5d3-xplained/src/sam_hsmci.c index 27db3addacf..d32f6ab26b5 100644 --- a/configs/sama5d3-xplained/src/sam_hsmci.c +++ b/configs/sama5d3-xplained/src/sam_hsmci.c @@ -86,10 +86,6 @@ #ifdef HAVE_HSMCI -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - /**************************************************************************** * Private Types ****************************************************************************/ @@ -112,7 +108,7 @@ struct sam_hsmci_state_s /* HSCMI device state */ #ifdef CONFIG_SAMA5_HSMCI0 -static int sam_hsmci0_cardetect(int irq, void *regs); +static int sam_hsmci0_cardetect(int irq, void *regs, FAR void *arg); static struct sam_hsmci_state_s g_hsmci0 = { @@ -124,7 +120,7 @@ static struct sam_hsmci_state_s g_hsmci0 = #endif #ifdef CONFIG_SAMA5_HSMCI1 -static int sam_hsmci1_cardetect(int irq, void *regs); +static int sam_hsmci1_cardetect(int irq, void *regs, FAR void *arg); static struct sam_hsmci_state_s g_hsmci1 = { @@ -189,14 +185,14 @@ static int sam_hsmci_cardetect(struct sam_hsmci_state_s *state) } #ifdef CONFIG_SAMA5_HSMCI0 -static int sam_hsmci0_cardetect(int irq, void *regs) +static int sam_hsmci0_cardetect(int irq, void *regs, FAR void *arg) { return sam_hsmci_cardetect(&g_hsmci0); } #endif #ifdef CONFIG_SAMA5_HSMCI1 -static int sam_hsmci1_cardetect(int irq, void *regs) +static int sam_hsmci1_cardetect(int irq, void *regs, FAR void *arg) { return sam_hsmci_cardetect(&g_hsmci1); } @@ -287,7 +283,7 @@ int sam_hsmci_initialize(int slotno, int minor) /* Configure card detect interrupts */ sam_pioirq(state->pincfg); - (void)irq_attach(state->irq, state->handler); + (void)irq_attach(state->irq, state->handler, NULL); /* Then inform the HSMCI driver if there is or is not a card in the slot. */ diff --git a/configs/sama5d3-xplained/src/sam_usb.c b/configs/sama5d3-xplained/src/sam_usb.c index b04c4eeb2ee..cad7cf01500 100644 --- a/configs/sama5d3-xplained/src/sam_usb.c +++ b/configs/sama5d3-xplained/src/sam_usb.c @@ -517,7 +517,7 @@ xcpt_t sam_setup_overcurrent(xcpt_t handler) /* Configure the interrupt */ sam_pioirq(PIO_USBBC_VBUS_OVERCURRENT); - (void)irq_attach(IRQ_USBBC_VBUS_OVERCURRENT, handler); + (void)irq_attach(IRQ_USBBC_VBUS_OVERCURRENT, handler, NULL); sam_pioirqenable(IRQ_USBBC_VBUS_OVERCURRENT); /* Return the old handler (so that it can be restored) */ diff --git a/configs/sama5d3x-ek/demo/defconfig b/configs/sama5d3x-ek/demo/defconfig index 59e5a4aadfd..36d6061a81f 100644 --- a/configs/sama5d3x-ek/demo/defconfig +++ b/configs/sama5d3x-ek/demo/defconfig @@ -910,7 +910,6 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7A_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/sama5d3x-ek/nxplayer/defconfig b/configs/sama5d3x-ek/nxplayer/defconfig index 2cfc66ab289..72f90e709d6 100644 --- a/configs/sama5d3x-ek/nxplayer/defconfig +++ b/configs/sama5d3x-ek/nxplayer/defconfig @@ -859,7 +859,6 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7A_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/sama5d3x-ek/src/sam_buttons.c b/configs/sama5d3x-ek/src/sam_buttons.c index 0449c3a4627..d9ea68baa42 100644 --- a/configs/sama5d3x-ek/src/sam_buttons.c +++ b/configs/sama5d3x-ek/src/sam_buttons.c @@ -137,7 +137,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_SAMA5_PIOE_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -163,7 +163,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) /* Configure the interrupt */ sam_pioirq(PIO_USER1); - (void)irq_attach(IRQ_USER1, irqhandler); + (void)irq_attach(IRQ_USER1, irqhandler, NULL); sam_pioirqenable(IRQ_USER1); } else diff --git a/configs/sama5d3x-ek/src/sam_ethernet.c b/configs/sama5d3x-ek/src/sam_ethernet.c index 87ee620ba7b..9dd45b9c62e 100644 --- a/configs/sama5d3x-ek/src/sam_ethernet.c +++ b/configs/sama5d3x-ek/src/sam_ethernet.c @@ -332,7 +332,7 @@ xcpt_t arch_phy_irq(FAR const char *intf, xcpt_t handler, phy_enable_t *enable) sam_pioirq(pinset); phyinfo("Attach IRQ%d\n", irq); - (void)irq_attach(irq, handler); + (void)irq_attach(irq, handler, NULL); } else { diff --git a/configs/sama5d3x-ek/src/sam_hsmci.c b/configs/sama5d3x-ek/src/sam_hsmci.c index 89a0307d890..aedd81d0853 100644 --- a/configs/sama5d3x-ek/src/sam_hsmci.c +++ b/configs/sama5d3x-ek/src/sam_hsmci.c @@ -86,10 +86,6 @@ #ifdef HAVE_HSMCI -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - /**************************************************************************** * Private Types ****************************************************************************/ @@ -112,7 +108,7 @@ struct sam_hsmci_state_s /* HSCMI device state */ #ifdef CONFIG_SAMA5_HSMCI0 -static int sam_hsmci0_cardetect(int irq, void *regs); +static int sam_hsmci0_cardetect(int irq, void *regs, FAR void *arg); static struct sam_hsmci_state_s g_hsmci0 = { @@ -124,7 +120,7 @@ static struct sam_hsmci_state_s g_hsmci0 = #endif #ifdef CONFIG_SAMA5_HSMCI1 -static int sam_hsmci1_cardetect(int irq, void *regs); +static int sam_hsmci1_cardetect(int irq, void *regs, FAR void *arg); static struct sam_hsmci_state_s g_hsmci1 = { @@ -189,14 +185,14 @@ static int sam_hsmci_cardetect(struct sam_hsmci_state_s *state) } #ifdef CONFIG_SAMA5_HSMCI0 -static int sam_hsmci0_cardetect(int irq, void *regs) +static int sam_hsmci0_cardetect(int irq, void *regs, FAR void *arg) { return sam_hsmci_cardetect(&g_hsmci0); } #endif #ifdef CONFIG_SAMA5_HSMCI1 -static int sam_hsmci1_cardetect(int irq, void *regs) +static int sam_hsmci1_cardetect(int irq, void *regs, FAR void *arg) { return sam_hsmci_cardetect(&g_hsmci1); } @@ -287,7 +283,7 @@ int sam_hsmci_initialize(int slotno, int minor) /* Configure card detect interrupts */ sam_pioirq(state->pincfg); - (void)irq_attach(state->irq, state->handler); + (void)irq_attach(state->irq, state->handler, NULL); /* Then inform the HSMCI driver if there is or is not a card in the slot. */ diff --git a/configs/sama5d3x-ek/src/sam_usb.c b/configs/sama5d3x-ek/src/sam_usb.c index 93fec362310..5b365f422d9 100644 --- a/configs/sama5d3x-ek/src/sam_usb.c +++ b/configs/sama5d3x-ek/src/sam_usb.c @@ -509,7 +509,7 @@ xcpt_t sam_setup_overcurrent(xcpt_t handler) /* Configure the interrupt */ sam_pioirq(PIO_USBBC_VBUS_OVERCURRENT); - (void)irq_attach(IRQ_USBBC_VBUS_OVERCURRENT, handler); + (void)irq_attach(IRQ_USBBC_VBUS_OVERCURRENT, handler, NULL); sam_pioirqenable(IRQ_USBBC_VBUS_OVERCURRENT); /* Return the old handler (so that it can be restored) */ diff --git a/configs/sama5d3x-ek/src/sam_wm8904.c b/configs/sama5d3x-ek/src/sam_wm8904.c index 7727afcd353..2bba0f3f045 100644 --- a/configs/sama5d3x-ek/src/sam_wm8904.c +++ b/configs/sama5d3x-ek/src/sam_wm8904.c @@ -204,7 +204,7 @@ static bool wm8904_enable(FAR const struct wm8904_lower_s *lower, bool enable) return ret; } -static int wm8904_interrupt(int irq, FAR void *context) +static int wm8904_interrupt(int irq, FAR void *context, FAR void *arg) { /* Just forward the interrupt to the WM8904 driver */ @@ -311,7 +311,7 @@ int sam_wm8904_initialize(int minor) /* Configure WM8904 interrupts */ sam_pioirq(PIO_INT_WM8904); - ret = irq_attach(IRQ_INT_WM8904, wm8904_interrupt); + ret = irq_attach(IRQ_INT_WM8904, wm8904_interrupt, NULL); if (ret < 0) { auderr("ERROR: Failed to attach WM8904 interrupt: %d\n", ret); diff --git a/configs/sama5d4-ek/elf/defconfig b/configs/sama5d4-ek/elf/defconfig index f655be3561e..12c4f503eb7 100644 --- a/configs/sama5d4-ek/elf/defconfig +++ b/configs/sama5d4-ek/elf/defconfig @@ -782,7 +782,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set CONFIG_LIBC_ARCH_ELF=y # CONFIG_ARMV7A_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/sama5d4-ek/ipv6/defconfig b/configs/sama5d4-ek/ipv6/defconfig index c93f8ba6724..94b5c44322e 100644 --- a/configs/sama5d4-ek/ipv6/defconfig +++ b/configs/sama5d4-ek/ipv6/defconfig @@ -1243,7 +1243,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7A_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/sama5d4-ek/knsh/defconfig b/configs/sama5d4-ek/knsh/defconfig index 8e8f52d2d6c..ef2d700d1a3 100644 --- a/configs/sama5d4-ek/knsh/defconfig +++ b/configs/sama5d4-ek/knsh/defconfig @@ -831,7 +831,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set CONFIG_LIBC_ARCH_ELF=y # CONFIG_ARMV7A_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/sama5d4-ek/nsh/defconfig b/configs/sama5d4-ek/nsh/defconfig index 6b4bd49fa88..6e9b13f709e 100644 --- a/configs/sama5d4-ek/nsh/defconfig +++ b/configs/sama5d4-ek/nsh/defconfig @@ -1247,7 +1247,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7A_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/sama5d4-ek/nxwm/defconfig b/configs/sama5d4-ek/nxwm/defconfig index da05e2c1fc2..a77ab4e6cbe 100644 --- a/configs/sama5d4-ek/nxwm/defconfig +++ b/configs/sama5d4-ek/nxwm/defconfig @@ -1239,7 +1239,6 @@ CONFIG_LIBM=y # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7A_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/sama5d4-ek/src/sam_buttons.c b/configs/sama5d4-ek/src/sam_buttons.c index 52fc7af11b1..b0fa42ecde3 100644 --- a/configs/sama5d4-ek/src/sam_buttons.c +++ b/configs/sama5d4-ek/src/sam_buttons.c @@ -133,7 +133,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_SAMA5_PIOE_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -159,7 +159,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) /* Configure the interrupt */ sam_pioirq(PIO_BTN_USER); - (void)irq_attach(IRQ_BTN_USER, irqhandler); + (void)irq_attach(IRQ_BTN_USER, irqhandler, NULL); sam_pioirqenable(IRQ_BTN_USER); } else diff --git a/configs/sama5d4-ek/src/sam_ethernet.c b/configs/sama5d4-ek/src/sam_ethernet.c index edda5f686a2..9231e227585 100644 --- a/configs/sama5d4-ek/src/sam_ethernet.c +++ b/configs/sama5d4-ek/src/sam_ethernet.c @@ -301,7 +301,7 @@ xcpt_t arch_phy_irq(FAR const char *intf, xcpt_t handler, phy_enable_t *enable) sam_pioirq(pinset); phyinfo("Attach IRQ%d\n", irq); - (void)irq_attach(irq, handler); + (void)irq_attach(irq, handler, NULL); } else { diff --git a/configs/sama5d4-ek/src/sam_hsmci.c b/configs/sama5d4-ek/src/sam_hsmci.c index 5af7468a5ec..2f23d9b7983 100644 --- a/configs/sama5d4-ek/src/sam_hsmci.c +++ b/configs/sama5d4-ek/src/sam_hsmci.c @@ -124,7 +124,7 @@ struct sam_hsmci_state_s /* HSCMI device state */ #ifdef CONFIG_SAMA5_HSMCI0 -static int sam_hsmci0_cardetect(int irq, void *regs); +static int sam_hsmci0_cardetect(int irq, void *regs, FAR void *arg); static struct sam_hsmci_state_s g_hsmci0 = { @@ -136,7 +136,7 @@ static struct sam_hsmci_state_s g_hsmci0 = #endif #ifdef CONFIG_SAMA5_HSMCI1 -static int sam_hsmci1_cardetect(int irq, void *regs); +static int sam_hsmci1_cardetect(int irq, void *regs, FAR void *arg); static struct sam_hsmci_state_s g_hsmci1 = { @@ -202,7 +202,7 @@ static int sam_hsmci_cardetect(struct sam_hsmci_state_s *state) } #ifdef CONFIG_SAMA5_HSMCI0 -static int sam_hsmci0_cardetect(int irq, void *regs) +static int sam_hsmci0_cardetect(int irq, FAR void *regs, FAR void *arg) { int ret; @@ -224,7 +224,7 @@ static int sam_hsmci0_cardetect(int irq, void *regs) #endif #ifdef CONFIG_SAMA5_HSMCI1 -static int sam_hsmci1_cardetect(int irq, void *regs) +static int sam_hsmci1_cardetect(int irq, FAR void *regs, FAR void *arg) { int ret; @@ -337,7 +337,7 @@ int sam_hsmci_initialize(int slotno, int minor) /* Configure card detect interrupts */ sam_pioirq(state->cdcfg); - (void)irq_attach(state->irq, state->handler); + (void)irq_attach(state->irq, state->handler, NULL); /* Then inform the HSMCI driver if there is or is not a card in the slot. */ diff --git a/configs/sama5d4-ek/src/sam_maxtouch.c b/configs/sama5d4-ek/src/sam_maxtouch.c index adc98320ade..1511c7a662c 100644 --- a/configs/sama5d4-ek/src/sam_maxtouch.c +++ b/configs/sama5d4-ek/src/sam_maxtouch.c @@ -197,7 +197,7 @@ static void mxt_clear(FAR const struct mxt_lower_s *lower) /* Does nothing */ } -static int mxt_interrupt(int irq, FAR void *context) +static int mxt_interrupt(int irq, FAR void *context, FAR void *arg) { /* Just forward the interrupt to the maXTouch driver */ @@ -269,7 +269,7 @@ int board_tsc_setup(int minor) /* Configure maXTouch CHG interrupts */ sam_pioirq(PIO_CHG_MXT); - (void)irq_attach(IRQ_CHG_MXT, mxt_interrupt); + (void)irq_attach(IRQ_CHG_MXT, mxt_interrupt, NULL); /* Initialize and register the I2C touchscreen device */ diff --git a/configs/sama5d4-ek/src/sam_usb.c b/configs/sama5d4-ek/src/sam_usb.c index 1f4d3aff62a..a73c4b384f7 100644 --- a/configs/sama5d4-ek/src/sam_usb.c +++ b/configs/sama5d4-ek/src/sam_usb.c @@ -510,7 +510,7 @@ xcpt_t sam_setup_overcurrent(xcpt_t handler) /* Configure the interrupt */ sam_pioirq(PIO_USBBC_VBUS_OVERCURRENT); - (void)irq_attach(IRQ_USBBC_VBUS_OVERCURRENT, handler); + (void)irq_attach(IRQ_USBBC_VBUS_OVERCURRENT, handler, NULL); sam_pioirqenable(IRQ_USBBC_VBUS_OVERCURRENT); /* Return the old handler (so that it can be restored) */ diff --git a/configs/sama5d4-ek/src/sam_wm8904.c b/configs/sama5d4-ek/src/sam_wm8904.c index 7afb4b85af4..34ded3756d7 100644 --- a/configs/sama5d4-ek/src/sam_wm8904.c +++ b/configs/sama5d4-ek/src/sam_wm8904.c @@ -204,7 +204,7 @@ static bool wm8904_enable(FAR const struct wm8904_lower_s *lower, bool enable) return ret; } -static int wm8904_interrupt(int irq, FAR void *context) +static int wm8904_interrupt(int irq, FAR void *context, FAR void *arg) { /* Just forward the interrupt to the WM8904 driver */ @@ -311,7 +311,7 @@ int sam_wm8904_initialize(int minor) /* Configure WM8904 interrupts */ sam_pioirq(PIO_INT_WM8904); - ret = irq_attach(IRQ_INT_WM8904, wm8904_interrupt); + ret = irq_attach(IRQ_INT_WM8904, wm8904_interrupt, NULL); if (ret < 0) { auderr("ERROR: Failed to attach WM8904 interrupt: %d\n", ret); diff --git a/configs/samd20-xplained/src/sam_buttons.c b/configs/samd20-xplained/src/sam_buttons.c index 368014f2bce..5edeb965d8a 100644 --- a/configs/samd20-xplained/src/sam_buttons.c +++ b/configs/samd20-xplained/src/sam_buttons.c @@ -124,7 +124,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_PORTA_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -146,7 +146,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) /* Configure the interrupt */ sam_portirq(IRQ_SW0); - (void)irq_attach(IRQ_SW0, irqhandler); + (void)irq_attach(IRQ_SW0, irqhandler, NULL); sam_portirqenable(IRQ_SW0); leave_critical_section(flags); } diff --git a/configs/samd21-xplained/src/sam_buttons.c b/configs/samd21-xplained/src/sam_buttons.c index 280475de6de..cb5806f748a 100644 --- a/configs/samd21-xplained/src/sam_buttons.c +++ b/configs/samd21-xplained/src/sam_buttons.c @@ -124,7 +124,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_PORTA_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -146,7 +146,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) /* Configure the interrupt */ sam_portirq(IRQ_SW0); - (void)irq_attach(IRQ_SW0, irqhandler); + (void)irq_attach(IRQ_SW0, irqhandler, NULL); sam_portirqenable(IRQ_SW0); leave_critical_section(flags); } diff --git a/configs/same70-xplained/netnsh/defconfig b/configs/same70-xplained/netnsh/defconfig index 50457729763..ceff93f76cc 100644 --- a/configs/same70-xplained/netnsh/defconfig +++ b/configs/same70-xplained/netnsh/defconfig @@ -986,7 +986,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/same70-xplained/nsh/defconfig b/configs/same70-xplained/nsh/defconfig index f3486acd06b..1c771712930 100644 --- a/configs/same70-xplained/nsh/defconfig +++ b/configs/same70-xplained/nsh/defconfig @@ -819,7 +819,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/same70-xplained/src/sam_buttons.c b/configs/same70-xplained/src/sam_buttons.c index d1154f70c89..251cf113c0e 100644 --- a/configs/same70-xplained/src/sam_buttons.c +++ b/configs/same70-xplained/src/sam_buttons.c @@ -89,7 +89,7 @@ static xcpt_t g_irq_sw0; #ifdef HAVE_IRQBUTTONS static xcpt_t board_button_irqx(gpio_pinset_t pinset, int irq, - xcpt_t irqhandler, xcpt_t *store) + xcpt_t irqhandler, xcpt_t *store, void *arg) { xcpt_t oldhandler; irqstate_t flags; @@ -112,7 +112,7 @@ static xcpt_t board_button_irqx(gpio_pinset_t pinset, int irq, /* Configure the interrupt */ sam_gpioirq(pinset); - (void)irq_attach(irq, irqhandler); + (void)irq_attach(irq, irqhandler, arg); sam_gpioirqenable(irq); } else @@ -188,12 +188,12 @@ uint8_t board_buttons(void) ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { #ifdef HAVE_IRQBUTTONS if (id == BUTTON_SW0) { - return board_button_irqx(GPIO_SW0, IRQ_SW0, irqhandler, &g_irq_sw0); + return board_button_irqx(GPIO_SW0, IRQ_SW0, irqhandler, &g_irq_sw0, arg); } #endif diff --git a/configs/same70-xplained/src/sam_ethernet.c b/configs/same70-xplained/src/sam_ethernet.c index 8f427e8c97a..ecf61bdf731 100644 --- a/configs/same70-xplained/src/sam_ethernet.c +++ b/configs/same70-xplained/src/sam_ethernet.c @@ -347,7 +347,7 @@ xcpt_t arch_phy_irq(FAR const char *intf, xcpt_t handler, phy_enable_t *enable) sam_gpioirq(pinset); phyinfo("Attach IRQ%d\n", irq); - (void)irq_attach(irq, handler); + (void)irq_attach(irq, handler, NULL); } else { diff --git a/configs/same70-xplained/src/sam_hsmci.c b/configs/same70-xplained/src/sam_hsmci.c index 56df5830bd9..24d27d1c821 100644 --- a/configs/same70-xplained/src/sam_hsmci.c +++ b/configs/same70-xplained/src/sam_hsmci.c @@ -99,7 +99,7 @@ struct sam_hsmci_state_s /* HSCMI device state */ #ifdef CONFIG_SAMV7_HSMCI0 -static int sam_hsmci0_cardetect(int irq, void *regs); +static int sam_hsmci0_cardetect(int irq, void *regs, FAR void *arg); static struct sam_hsmci_state_s g_hsmci0 = { @@ -164,7 +164,7 @@ static int sam_hsmci_cardetect(struct sam_hsmci_state_s *state) } #ifdef CONFIG_SAMV7_HSMCI0 -static int sam_hsmci0_cardetect(int irq, void *regs) +static int sam_hsmci0_cardetect(int irq, void *regs, FAR void *arg) { int ret; @@ -263,7 +263,7 @@ int sam_hsmci_initialize(int slotno, int minor) /* Configure card detect interrupts */ sam_gpioirq(state->cdcfg); - (void)irq_attach(state->irq, state->handler); + (void)irq_attach(state->irq, state->handler, NULL); /* Then inform the HSMCI driver if there is or is not a card in the slot. */ diff --git a/configs/saml21-xplained/src/sam_buttons.c b/configs/saml21-xplained/src/sam_buttons.c index ea8994df6aa..303a95a084f 100644 --- a/configs/saml21-xplained/src/sam_buttons.c +++ b/configs/saml21-xplained/src/sam_buttons.c @@ -124,7 +124,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #if defined(CONFIG_PORTA_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -146,7 +146,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) /* Configure the interrupt */ sam_portirq(IRQ_SW0); - (void)irq_attach(IRQ_SW0, irqhandler); + (void)irq_attach(IRQ_SW0, irqhandler, NULL); sam_portirqenable(IRQ_SW0); leave_critical_section(flags); } diff --git a/configs/samv71-xult/knsh/defconfig b/configs/samv71-xult/knsh/defconfig index cf6aeef2e38..369dcc43d4c 100644 --- a/configs/samv71-xult/knsh/defconfig +++ b/configs/samv71-xult/knsh/defconfig @@ -829,7 +829,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/samv71-xult/module/defconfig b/configs/samv71-xult/module/defconfig index a5f3e3043b7..2c060c0c5e2 100644 --- a/configs/samv71-xult/module/defconfig +++ b/configs/samv71-xult/module/defconfig @@ -741,7 +741,6 @@ CONFIG_MODLIB_BUFFERINCR=32 # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set CONFIG_LIBC_ARCH_ELF=y # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/samv71-xult/mxtxplnd/defconfig b/configs/samv71-xult/mxtxplnd/defconfig index 63eef944d0e..858d40340fa 100644 --- a/configs/samv71-xult/mxtxplnd/defconfig +++ b/configs/samv71-xult/mxtxplnd/defconfig @@ -950,7 +950,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/samv71-xult/netnsh/defconfig b/configs/samv71-xult/netnsh/defconfig index 535e8d25b45..adcd503dde6 100644 --- a/configs/samv71-xult/netnsh/defconfig +++ b/configs/samv71-xult/netnsh/defconfig @@ -989,7 +989,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/samv71-xult/nsh/defconfig b/configs/samv71-xult/nsh/defconfig index 5d1d84fc0a6..90d4a321fcf 100644 --- a/configs/samv71-xult/nsh/defconfig +++ b/configs/samv71-xult/nsh/defconfig @@ -822,7 +822,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/samv71-xult/nxwm/defconfig b/configs/samv71-xult/nxwm/defconfig index ee1a5d4f509..be4635e3323 100644 --- a/configs/samv71-xult/nxwm/defconfig +++ b/configs/samv71-xult/nxwm/defconfig @@ -968,7 +968,6 @@ CONFIG_LIBM=y # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/samv71-xult/src/sam_buttons.c b/configs/samv71-xult/src/sam_buttons.c index 2a803623880..7e2ecd1b404 100644 --- a/configs/samv71-xult/src/sam_buttons.c +++ b/configs/samv71-xult/src/sam_buttons.c @@ -92,7 +92,7 @@ static xcpt_t g_irq_sw1; #ifdef HAVE_IRQBUTTONS static xcpt_t board_button_irqx(gpio_pinset_t pinset, int irq, - xcpt_t irqhandler, xcpt_t *store) + xcpt_t irqhandler, xcpt_t *store, void *arg) { xcpt_t oldhandler; irqstate_t flags; @@ -115,7 +115,7 @@ static xcpt_t board_button_irqx(gpio_pinset_t pinset, int irq, /* Configure the interrupt */ sam_gpioirq(pinset); - (void)irq_attach(irq, irqhandler); + (void)irq_attach(irq, irqhandler, arg); sam_gpioirqenable(irq); } else @@ -208,7 +208,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { #ifdef HAVE_IRQBUTTONS @@ -216,12 +216,12 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) { #ifdef CONFIG_SAMV7_GPIOA_IRQ case BUTTON_SW0: - return board_button_irqx(GPIO_SW0, IRQ_SW0, irqhandler, &g_irq_sw0); + return board_button_irqx(GPIO_SW0, IRQ_SW0, irqhandler, &g_irq_sw0, arg); #endif #ifdef CONFIG_SAMV7_GPIOB_IRQ case BUTTON_SW1: - return board_button_irqx(GPIO_SW1, IRQ_SW1, irqhandler, &g_irq_sw1); + return board_button_irqx(GPIO_SW1, IRQ_SW1, irqhandler, &g_irq_sw1, arg); #endif default: diff --git a/configs/samv71-xult/src/sam_ethernet.c b/configs/samv71-xult/src/sam_ethernet.c index 2714eab3beb..247c7258244 100644 --- a/configs/samv71-xult/src/sam_ethernet.c +++ b/configs/samv71-xult/src/sam_ethernet.c @@ -352,7 +352,7 @@ xcpt_t arch_phy_irq(FAR const char *intf, xcpt_t handler, phy_enable_t *enable) sam_gpioirq(pinset); phyinfo("Attach IRQ%d\n", irq); - (void)irq_attach(irq, handler); + (void)irq_attach(irq, handler, NULL); } else { diff --git a/configs/samv71-xult/src/sam_hsmci.c b/configs/samv71-xult/src/sam_hsmci.c index 2b4cb3295f8..2835e64357c 100644 --- a/configs/samv71-xult/src/sam_hsmci.c +++ b/configs/samv71-xult/src/sam_hsmci.c @@ -99,7 +99,7 @@ struct sam_hsmci_state_s /* HSCMI device state */ #ifdef CONFIG_SAMV7_HSMCI0 -static int sam_hsmci0_cardetect(int irq, void *regs); +static int sam_hsmci0_cardetect(int irq, void *regs, FAR void *arg); static struct sam_hsmci_state_s g_hsmci0 = { @@ -164,7 +164,7 @@ static int sam_hsmci_cardetect(struct sam_hsmci_state_s *state) } #ifdef CONFIG_SAMV7_HSMCI0 -static int sam_hsmci0_cardetect(int irq, void *regs) +static int sam_hsmci0_cardetect(int irq, void *regs, FAR void *arg) { int ret; @@ -263,7 +263,7 @@ int sam_hsmci_initialize(int slotno, int minor) /* Configure card detect interrupts */ sam_gpioirq(state->cdcfg); - (void)irq_attach(state->irq, state->handler); + (void)irq_attach(state->irq, state->handler, NULL); /* Then inform the HSMCI driver if there is or is not a card in the slot. */ diff --git a/configs/samv71-xult/src/sam_maxtouch.c b/configs/samv71-xult/src/sam_maxtouch.c index 7bce968fcd0..32e1cda60d3 100644 --- a/configs/samv71-xult/src/sam_maxtouch.c +++ b/configs/samv71-xult/src/sam_maxtouch.c @@ -196,7 +196,7 @@ static void mxt_clear(FAR const struct mxt_lower_s *lower) /* Does nothing */ } -static int mxt_interrupt(int irq, FAR void *context) +static int mxt_interrupt(int irq, FAR void *context, FAR void *arg) { /* Just forward the interrupt to the maXTouch driver */ @@ -268,7 +268,7 @@ int board_tsc_setup(int minor) /* Configure maXTouch CHG interrupts */ sam_gpioirq(GPIO_MXT_CHG); - (void)irq_attach(IRQ_MXT_CHG, mxt_interrupt); + (void)irq_attach(IRQ_MXT_CHG, mxt_interrupt, NULL); /* Initialize and register the I2C touchscreen device */ diff --git a/configs/samv71-xult/src/sam_wm8904.c b/configs/samv71-xult/src/sam_wm8904.c index abb920bd0b7..8ffe0dfe214 100644 --- a/configs/samv71-xult/src/sam_wm8904.c +++ b/configs/samv71-xult/src/sam_wm8904.c @@ -204,7 +204,7 @@ static bool wm8904_enable(FAR const struct wm8904_lower_s *lower, bool enable) return ret; } -static int wm8904_interrupt(int irq, FAR void *context) +static int wm8904_interrupt(int irq, FAR void *context, FAR void *arg) { /* Just forward the interrupt to the WM8904 driver */ @@ -311,7 +311,7 @@ int sam_wm8904_initialize(int minor) /* Configure WM8904 interrupts */ sam_gpioirq(GPIO_INT_WM8904); - ret = irq_attach(IRQ_INT_WM8904, wm8904_interrupt); + ret = irq_attach(IRQ_INT_WM8904, wm8904_interrupt, NULL); if (ret < 0) { auderr("ERROR: Failed to attach WM8904 interrupt: %d\n", ret); diff --git a/configs/samv71-xult/vnc/defconfig b/configs/samv71-xult/vnc/defconfig index 47bdacb1db8..c8eca8144a6 100644 --- a/configs/samv71-xult/vnc/defconfig +++ b/configs/samv71-xult/vnc/defconfig @@ -1090,7 +1090,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/samv71-xult/vnxwm/defconfig b/configs/samv71-xult/vnxwm/defconfig index 7e0ae170591..b17bf8ba95f 100644 --- a/configs/samv71-xult/vnxwm/defconfig +++ b/configs/samv71-xult/vnxwm/defconfig @@ -1118,7 +1118,6 @@ CONFIG_LIBM=y # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/shenzhou/src/stm32_buttons.c b/configs/shenzhou/src/stm32_buttons.c index cf31d666e82..2d90fafcc16 100644 --- a/configs/shenzhou/src/stm32_buttons.c +++ b/configs/shenzhou/src/stm32_buttons.c @@ -156,7 +156,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -164,7 +164,8 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); } return oldhandler; } diff --git a/configs/shenzhou/src/stm32_touchscreen.c b/configs/shenzhou/src/stm32_touchscreen.c index dec42e95ffa..99b3971df80 100644 --- a/configs/shenzhou/src/stm32_touchscreen.c +++ b/configs/shenzhou/src/stm32_touchscreen.c @@ -185,11 +185,12 @@ static void tsc_enable(FAR struct ads7843e_config_s *state, bool enable) if (enable) { (void)stm32_gpiosetevent(GPIO_TP_INT, true, true, false, - priv->handler); + priv->handler, NULL); } else { - (void)stm32_gpiosetevent(GPIO_TP_INT, false, false, false, NULL); + (void)stm32_gpiosetevent(GPIO_TP_INT, false, false, false, + NULL, NULL); } } diff --git a/configs/spark/src/stm32_buttons.c b/configs/spark/src/stm32_buttons.c index 4f4224146ed..d38a868cc59 100644 --- a/configs/spark/src/stm32_buttons.c +++ b/configs/spark/src/stm32_buttons.c @@ -120,7 +120,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -128,8 +128,9 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (id == BUTTON_USER) { - oldhandler = stm32_gpiosetevent(GPIO_BTN, true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(GPIO_BTN, true, true, true, irqhandler, arg); } + return oldhandler; } #endif diff --git a/configs/spark/src/stm32_io.c b/configs/spark/src/stm32_io.c index 404cd4143ae..5730abe689d 100644 --- a/configs/spark/src/stm32_io.c +++ b/configs/spark/src/stm32_io.c @@ -183,11 +183,13 @@ xcpt_t up_irqio(int id, xcpt_t irqhandler) if (id == 0) { - oldhandler = stm32_gpiosetevent(GPIO_D0, true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(GPIO_D0, true, true, true, + irqhandler, NULL); } else if (id == 1) { - oldhandler = stm32_gpiosetevent(GPIO_D1, true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(GPIO_D1, true, true, true, + irqhandler, NULL); } return oldhandler; diff --git a/configs/spark/src/stm32_wireless.c b/configs/spark/src/stm32_wireless.c index 2d1f6855d82..afd0f9a819d 100644 --- a/configs/spark/src/stm32_wireless.c +++ b/configs/spark/src/stm32_wireless.c @@ -96,6 +96,7 @@ struct stm32_config_s { struct cc3000_config_s dev; xcpt_t handler; + void *arg; }; /**************************************************************************** @@ -118,7 +119,8 @@ struct stm32_config_s * wl_read_irq - Return the state of the interrupt GPIO input */ -static int wl_attach_irq(FAR struct cc3000_config_s *state, xcpt_t handler); +static int wl_attach_irq(FAR struct cc3000_config_s *state, xcpt_t handler, + FAR void *arg); static void wl_enable_irq(FAR struct cc3000_config_s *state, bool enable); static void wl_clear_irq(FAR struct cc3000_config_s *state); static void wl_select(FAR struct cc3000_config_s *state, bool enable); @@ -157,6 +159,7 @@ static struct stm32_config_s g_cc3000_info = .dev.probe = probe, /* This is used for debugging */ #endif .handler = NULL, + .arg = NULL, }; /**************************************************************************** @@ -175,13 +178,15 @@ static struct stm32_config_s g_cc3000_info = * pendown - Return the state of the pen down GPIO input */ -static int wl_attach_irq(FAR struct cc3000_config_s *state, xcpt_t handler) +static int wl_attach_irq(FAR struct cc3000_config_s *state, xcpt_t handler, + FAR void *arg) { FAR struct stm32_config_s *priv = (FAR struct stm32_config_s *)state; /* Just save the handler for use when the interrupt is enabled */ priv->handler = handler; + priv->arg = arg; return OK; } @@ -200,11 +205,13 @@ static void wl_enable_irq(FAR struct cc3000_config_s *state, bool enable) iinfo("enable:%d\n", enable); if (enable) { - (void)stm32_gpiosetevent(GPIO_WIFI_INT, false, true, false, priv->handler); + (void)stm32_gpiosetevent(GPIO_WIFI_INT, false, true, false, + priv->handler, priv->arg); } else { - (void)stm32_gpiosetevent(GPIO_WIFI_INT, false, false, false, NULL); + (void)stm32_gpiosetevent(GPIO_WIFI_INT, false, false, false, + NULL, NULL); } } diff --git a/configs/stm3210e-eval/composite/defconfig b/configs/stm3210e-eval/composite/defconfig index f454776e90b..8e3a48b02b9 100644 --- a/configs/stm3210e-eval/composite/defconfig +++ b/configs/stm3210e-eval/composite/defconfig @@ -1056,7 +1056,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm3210e-eval/nsh/defconfig b/configs/stm3210e-eval/nsh/defconfig index 889b14ce339..d233f7dc33f 100644 --- a/configs/stm3210e-eval/nsh/defconfig +++ b/configs/stm3210e-eval/nsh/defconfig @@ -1013,7 +1013,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm3210e-eval/nsh2/defconfig b/configs/stm3210e-eval/nsh2/defconfig index 48c896283e2..74add5e1970 100644 --- a/configs/stm3210e-eval/nsh2/defconfig +++ b/configs/stm3210e-eval/nsh2/defconfig @@ -1173,7 +1173,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm3210e-eval/src/stm32_buttons.c b/configs/stm3210e-eval/src/stm32_buttons.c index 526309f0178..a2dc1c6cf7e 100644 --- a/configs/stm3210e-eval/src/stm32_buttons.c +++ b/configs/stm3210e-eval/src/stm32_buttons.c @@ -161,7 +161,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -169,7 +169,8 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); } return oldhandler; diff --git a/configs/stm3210e-eval/src/stm32_djoystick.c b/configs/stm3210e-eval/src/stm32_djoystick.c index 72d5009e705..40e8e3bf265 100644 --- a/configs/stm3210e-eval/src/stm32_djoystick.c +++ b/configs/stm3210e-eval/src/stm32_djoystick.c @@ -213,7 +213,7 @@ static void djoy_enable(FAR const struct djoy_lowerhalf_s *lower, i, rising, falling); (void)stm32_gpiosetevent(g_joygpio[i], rising, falling, - true, djoy_interrupt); + true, djoy_interrupt, NULL); } } } @@ -239,7 +239,7 @@ static void djoy_disable(void) flags = enter_critical_section(); for (i = 0; i < DJOY_NGPIOS; i++) { - (void)stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL); + (void)stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); } leave_critical_section(flags); diff --git a/configs/stm3210e-eval/src/stm32_idle.c b/configs/stm3210e-eval/src/stm32_idle.c index e50aac3c854..5073218ad0a 100644 --- a/configs/stm3210e-eval/src/stm32_idle.c +++ b/configs/stm3210e-eval/src/stm32_idle.c @@ -177,7 +177,7 @@ static int stm32_alarm_exti(int irq, FAR void *context) #if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) static void stm32_exti_cancel(void) { - (void)stm32_exti_alarm(false, false, false, NULL); + (void)stm32_exti_alarm(false, false, false, NULL, NULL); } #endif @@ -201,7 +201,7 @@ static int stm32_rtc_alarm(time_t tv_sec, time_t tv_nsec, bool exti) { /* TODO: Make sure that that is no pending EXTI interrupt */ - (void)stm32_exti_alarm(true, true, true, stm32_alarm_exti); + (void)stm32_exti_alarm(true, true, true, stm32_alarm_exti, NULL); } /* Configure the RTC alarm to Auto Wake the system */ diff --git a/configs/stm3210e-eval/src/stm32_lm75.c b/configs/stm3210e-eval/src/stm32_lm75.c index ba0591fb87c..a238bf7d637 100644 --- a/configs/stm3210e-eval/src/stm32_lm75.c +++ b/configs/stm3210e-eval/src/stm32_lm75.c @@ -114,7 +114,7 @@ int stm32_lm75initialize(FAR const char *devpath) xcpt_t stm32_lm75attach(xcpt_t irqhandler) { - return stm32_gpiosetevent(GPIO_LM75_OSINT, true, true, true, irqhandler); + return stm32_gpiosetevent(GPIO_LM75_OSINT, true, true, true, irqhandler, NULL); } #endif /* CONFIG_I2C && CONFIG_I2C_LM75 && CONFIG_STM32_I2C1 */ diff --git a/configs/stm3210e-eval/src/stm32_pmbuttons.c b/configs/stm3210e-eval/src/stm32_pmbuttons.c index 50a06cc95d5..9e72b528311 100644 --- a/configs/stm3210e-eval/src/stm32_pmbuttons.c +++ b/configs/stm3210e-eval/src/stm32_pmbuttons.c @@ -314,7 +314,8 @@ void stm32_pmbuttons(void) int i; for (i = CONFIG_PM_IRQBUTTONS_MIN; i <= CONFIG_PM_IRQBUTTONS_MAX; i++) { - xcpt_t oldhandler = board_button_irq(i, g_buttonhandlers[BUTTON_INDEX(i)]); + xcpt_t oldhandler = + board_button_irq(i, g_buttonhandlers[BUTTON_INDEX(i)], NULL); if (oldhandler != NULL) { diff --git a/configs/stm3210e-eval/usbmsc/defconfig b/configs/stm3210e-eval/usbmsc/defconfig index e403f0a600c..6195a105332 100644 --- a/configs/stm3210e-eval/usbmsc/defconfig +++ b/configs/stm3210e-eval/usbmsc/defconfig @@ -981,7 +981,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm3220g-eval/nsh2/defconfig b/configs/stm3220g-eval/nsh2/defconfig index f537fb7c3c7..34f4a330203 100644 --- a/configs/stm3220g-eval/nsh2/defconfig +++ b/configs/stm3220g-eval/nsh2/defconfig @@ -1145,7 +1145,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm3220g-eval/src/stm32_buttons.c b/configs/stm3220g-eval/src/stm32_buttons.c index 85db973fa55..ec5428eb069 100644 --- a/configs/stm3220g-eval/src/stm32_buttons.c +++ b/configs/stm3220g-eval/src/stm32_buttons.c @@ -157,7 +157,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -165,8 +165,10 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); } + return oldhandler; } #endif diff --git a/configs/stm3220g-eval/src/stm32_stmpe811.c b/configs/stm3220g-eval/src/stm32_stmpe811.c index 5748600e957..ec79a318644 100644 --- a/configs/stm3220g-eval/src/stm32_stmpe811.c +++ b/configs/stm3220g-eval/src/stm32_stmpe811.c @@ -137,6 +137,7 @@ struct stm32_stmpe811config_s STMPE811_HANDLE handle; /* The STMPE811 driver handle */ xcpt_t handler; /* The STMPE811 interrupt handler */ + void *arg; /* Interrupt handler argument */ }; /**************************************************************************** @@ -152,7 +153,8 @@ struct stm32_stmpe811config_s * clear - Acknowledge/clear any pending GPIO interrupt */ -static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr); +static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr, + FAR void *arg); static void stmpe811_enable(FAR struct stmpe811_config_s *state, bool enable); static void stmpe811_clear(FAR struct stmpe811_config_s *state); @@ -191,6 +193,7 @@ static struct stm32_stmpe811config_s g_stmpe811config = .clear = stmpe811_clear, }, .handler = NULL, + .arg = NULL, }; #endif @@ -207,7 +210,8 @@ static struct stm32_stmpe811config_s g_stmpe811config = * clear - Acknowledge/clear any pending GPIO interrupt */ -static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr) +static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr, + FAR void *arg) { FAR struct stm32_stmpe811config_s *priv = (FAR struct stm32_stmpe811config_s *)state; @@ -217,6 +221,7 @@ static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr) /* Just save the handler. We will use it when EXTI interruptsare enabled */ priv->handler = isr; + priv->arg = arg; return OK; } @@ -235,14 +240,17 @@ static void stmpe811_enable(FAR struct stmpe811_config_s *state, bool enable) { /* Configure the EXTI interrupt using the SAVED handler */ - (void)stm32_gpiosetevent(GPIO_IO_EXPANDER, true, true, true, priv->handler); + (void)stm32_gpiosetevent(GPIO_IO_EXPANDER, true, true, true, + priv->handler, priv->arg); } else { /* Configure the EXTI interrupt with a NULL handler to disable it */ - (void)stm32_gpiosetevent(GPIO_IO_EXPANDER, false, false, false, NULL); + (void)stm32_gpiosetevent(GPIO_IO_EXPANDER, false, false, false, + NULL, NULL); } + leave_critical_section(flags); } diff --git a/configs/stm3220g-eval/src/stm32_usb.c b/configs/stm3220g-eval/src/stm32_usb.c index adecafb76df..371daed38ad 100644 --- a/configs/stm3220g-eval/src/stm32_usb.c +++ b/configs/stm3220g-eval/src/stm32_usb.c @@ -282,7 +282,7 @@ void stm32_usbhost_vbusdrive(int iface, bool enable) #ifdef CONFIG_USBHOST xcpt_t stm32_setup_overcurrent(xcpt_t handler) { - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler); + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); } #endif diff --git a/configs/stm3240g-eval/nsh2/defconfig b/configs/stm3240g-eval/nsh2/defconfig index 07738c41d00..5065e288c67 100644 --- a/configs/stm3240g-eval/nsh2/defconfig +++ b/configs/stm3240g-eval/nsh2/defconfig @@ -1149,7 +1149,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm3240g-eval/src/stm32_buttons.c b/configs/stm3240g-eval/src/stm32_buttons.c index e3e761b217b..db034d5a4e3 100644 --- a/configs/stm3240g-eval/src/stm32_buttons.c +++ b/configs/stm3240g-eval/src/stm32_buttons.c @@ -157,7 +157,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -165,8 +165,10 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); } + return oldhandler; } #endif diff --git a/configs/stm3240g-eval/src/stm32_stmpe811.c b/configs/stm3240g-eval/src/stm32_stmpe811.c index 0bb25376fa3..b1b8126c579 100644 --- a/configs/stm3240g-eval/src/stm32_stmpe811.c +++ b/configs/stm3240g-eval/src/stm32_stmpe811.c @@ -137,6 +137,7 @@ struct stm32_stmpe811config_s STMPE811_HANDLE handle; /* The STMPE811 driver handle */ xcpt_t handler; /* The STMPE811 interrupt handler */ + FAR void *arg; /* Interrupt handler argument */ }; /**************************************************************************** @@ -152,7 +153,8 @@ struct stm32_stmpe811config_s * clear - Acknowledge/clear any pending GPIO interrupt */ -static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr); +static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr, + FAR void *arg); static void stmpe811_enable(FAR struct stmpe811_config_s *state, bool enable); static void stmpe811_clear(FAR struct stmpe811_config_s *state); @@ -191,6 +193,7 @@ static struct stm32_stmpe811config_s g_stmpe811config = .clear = stmpe811_clear, }, .handler = NULL, + .arg = NULL, }; #endif @@ -207,7 +210,8 @@ static struct stm32_stmpe811config_s g_stmpe811config = * clear - Acknowledge/clear any pending GPIO interrupt */ -static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr) +static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr, + FAR void *arg) { FAR struct stm32_stmpe811config_s *priv = (FAR struct stm32_stmpe811config_s *)state; @@ -217,6 +221,7 @@ static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr) /* Just save the handler. We will use it when EXTI interruptsare enabled */ priv->handler = isr; + priv->arg = arg; return OK; } @@ -235,14 +240,17 @@ static void stmpe811_enable(FAR struct stmpe811_config_s *state, bool enable) { /* Configure the EXTI interrupt using the SAVED handler */ - (void)stm32_gpiosetevent(GPIO_IO_EXPANDER, true, true, true, priv->handler); + (void)stm32_gpiosetevent(GPIO_IO_EXPANDER, true, true, true, + priv->handler, priv->arg); } else { /* Configure the EXTI interrupt with a NULL handler to disable it */ - (void)stm32_gpiosetevent(GPIO_IO_EXPANDER, false, false, false, NULL); + (void)stm32_gpiosetevent(GPIO_IO_EXPANDER, false, false, false, + NULL, NULL); } + leave_critical_section(flags); } diff --git a/configs/stm3240g-eval/src/stm32_usb.c b/configs/stm3240g-eval/src/stm32_usb.c index 71d51ce9ed4..7c5494a501b 100644 --- a/configs/stm3240g-eval/src/stm32_usb.c +++ b/configs/stm3240g-eval/src/stm32_usb.c @@ -282,7 +282,7 @@ void stm32_usbhost_vbusdrive(int iface, bool enable) #ifdef CONFIG_USBHOST xcpt_t stm32_setup_overcurrent(xcpt_t handler) { - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler); + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); } #endif diff --git a/configs/stm32_tiny/src/stm32_wireless.c b/configs/stm32_tiny/src/stm32_wireless.c index bbfdedc13b1..ef3fc3f54cb 100644 --- a/configs/stm32_tiny/src/stm32_wireless.c +++ b/configs/stm32_tiny/src/stm32_wireless.c @@ -57,7 +57,7 @@ * Private Function Prototypes ************************************************************************************/ -static int stm32tiny_wl_irq_attach(xcpt_t isr); +static int stm32tiny_wl_irq_attach(xcpt_t isr, FAR void *arg); static void stm32tiny_wl_chip_enable(bool enable); @@ -72,16 +72,18 @@ static FAR struct nrf24l01_config_s nrf_cfg = }; static xcpt_t g_isr; +static FAR void *g_arg; /************************************************************************************ * Private Functions ************************************************************************************/ -static int stm32tiny_wl_irq_attach(xcpt_t isr) +static int stm32tiny_wl_irq_attach(xcpt_t isr, FAR void *arg) { _info("Attach IRQ\n"); g_isr = isr; - stm32_gpiosetevent(GPIO_NRF24L01_IRQ, false, true, false, g_isr); + g_arg = arg; + stm32_gpiosetevent(GPIO_NRF24L01_IRQ, false, true, false, g_isr, g_arg); return OK; } diff --git a/configs/stm32butterfly2/src/stm32_mmcsd.c b/configs/stm32butterfly2/src/stm32_mmcsd.c index 696ad7d0c56..d045d05c710 100644 --- a/configs/stm32butterfly2/src/stm32_mmcsd.c +++ b/configs/stm32butterfly2/src/stm32_mmcsd.c @@ -124,7 +124,7 @@ static void *stm32_cd_thread(void *arg) * Card detect interrupt handler. ****************************************************************************/ -static int stm32_cd(int irq, void *context) +static int stm32_cd(int irq, void *context, void *arg) { static const int debounce_time = 100; /* [ms] */ static uint32_t now = 0; @@ -196,7 +196,7 @@ int stm32_mmcsd_initialize(int minor) return rv; } - stm32_gpiosetevent(GPIO_SD_CD, true, true, true, stm32_cd); + stm32_gpiosetevent(GPIO_SD_CD, true, true, true, stm32_cd, NULL); sem_init(&g_cdsem, 0, 0); pthread_attr_init(&pattr); diff --git a/configs/stm32f103-minimum/Kconfig b/configs/stm32f103-minimum/Kconfig index 15ead9d2c21..3479da27251 100644 --- a/configs/stm32f103-minimum/Kconfig +++ b/configs/stm32f103-minimum/Kconfig @@ -4,4 +4,10 @@ # if ARCH_BOARD_STM32F103_MINIMUM + +config STM32F103MINIMUM_QETIMER + int "Timer to use with QE encoder" + default 4 + depends on QENCODER + endif diff --git a/configs/stm32f103-minimum/README.txt b/configs/stm32f103-minimum/README.txt index 08d359f66a3..6b2db769398 100644 --- a/configs/stm32f103-minimum/README.txt +++ b/configs/stm32f103-minimum/README.txt @@ -4,70 +4,86 @@ README This README discusses issues unique to NuttX configurations for the STM32F103C8T6 Minimum System Development Board for ARM Microcontroller. -This board is available from several vendors on the net, and may -be sold under different names or no name at all. It is based on a -STM32F103C8T6 and has a DIP-40 form-factor. +Contents +======== -There are two versions of very similar boards: One is red and one is -blue. See http://www.stm32duino.com/viewtopic.php?f=28&t=117 + - STM32F103C8T6 Minimum System Development Boards: + - LEDs + - UARTs + - Timer Inputs/Outputs + - Using 128KiB of Flash instead of 64KiB + - Quadrature Encoder + - STM32F103 Minimum - specific Configuration Options + - Configurations -The Red Board: +STM32F103C8T6 Minimum System Development Boards: +================================================ - Good things about the red board: + This STM32F103C8T6 minimum system development board is available from + several vendors on the net, and may be sold under different names or + no name at all. It is based on a STM32F103C8T6 and has a DIP-40 form- + factor. - - 1.5k pull up resistor on the PA12 pin (USB D+) which you can - programatically drag down for automated USB reset. - - large power capacitors and LDO power. + There are two versions of very similar boards: One is red and one is + blue. See http://www.stm32duino.com/viewtopic.php?f=28&t=117 - Problems with the red board: + The Red Board: - - Silk screen is barely readable, the text is chopped off on some of - the pins - - USB connector only has two anchor points and it is directly soldered - on the surface - - Small reset button with hardly any resistance + Good things about the red board: -The Blue Board: + - 1.5k pull up resistor on the PA12 pin (USB D+) which you can + programatically drag down for automated USB reset. + - large power capacitors and LDO power. - Good things about the blue board: + Problems with the red board: - - Four soldered anchor point on the USB connector. What you can't tell - from this picture is that there is a notch in the pcb board and the USB - connector sits down inside it some. This provides some lateral stability - that takes some of the stress off the solder points. - - It has nice clear readable silkscreen printing. - - It also a larger reset button. + - Silk screen is barely readable, the text is chopped off on some of + the pins + - USB connector only has two anchor points and it is directly soldered + on the surface + - Small reset button with hardly any resistance - Problems with the blue board: + The Blue Board: - - Probably won't work as a USB device if it has a 10k pull-up on PA12. You - have to check the pull up on PA12 (USB D+). If it has a 10k pull-up - resistor, you will need to replace it with a 1.5k one to use the native - USB. - - Puny voltage regulator probably 100mA. + Good things about the blue board: - A schematic for the blue board is available here: - http://www.stm32duino.com/download/file.php?id=276 + - Four soldered anchor point on the USB connector. What you can't tell + from this picture is that there is a notch in the pcb board and the USB + connector sits down inside it some. This provides some lateral stability + that takes some of the stress off the solder points. + - It has nice clear readable silkscreen printing. + - It also a larger reset button. -Both Boards: + Problems with the blue board: - Nice features common to both: + - Probably won't work as a USB device if it has a 10k pull-up on PA12. You + have to check the pull up on PA12 (USB D+). If it has a 10k pull-up + resistor, you will need to replace it with a 1.5k one to use the native + USB. + - Puny voltage regulator probably 100mA. - - SWD pins broken out and easily connected (VCC, GND, SWDIO, SWCLK) - - USB 5V is broken out with easy access. - - User LED on PC13 - - Power LED - - You can probably use more flash (128k) than officially documented for - the chip (stm32f103c8t6 64k), I was able to load 115k of flash on mine - and it seemed to work. + A schematic for the blue board is available here: + http://www.stm32duino.com/download/file.php?id=276 - Problems with both boards: + Both Boards: - - No preloaded bootloader * to me this isn't really a problem as the - entire 64k of flash is available for use - - No user button + Nice features common to both: -This is the board pinout based on its form-factor for the Blue board: + - SWD pins broken out and easily connected (VCC, GND, SWDIO, SWCLK) + - USB 5V is broken out with easy access. + - User LED on PC13 + - Power LED + - You can probably use more flash (128k) than officially documented for + the chip (stm32f103c8t6 64k), I was able to load 115k of flash on mine + and it seemed to work. + + Problems with both boards: + + - No preloaded bootloader * to me this isn't really a problem as the + entire 64k of flash is available for use + - No user button + + This is the board pinout based on its form-factor for the Blue board: USB ___ @@ -94,25 +110,15 @@ This is the board pinout based on its form-factor for the Blue board: |3.3V VB| |_____________| -Contents -======== - - - LEDs - - UARTs - - Timer Inputs/Outputs - - Using 128KiB of Flash instead of 64KiB - - STM32F103 Minimum - specific Configuration Options - - Configurations - LEDs ==== -The STM32F103 Minimum board has only one software controllable LED. -This LED can be used by the board port when CONFIG_ARCH_LEDS option is -enabled. + The STM32F103 Minimum board has only one software controllable LED. + This LED can be used by the board port when CONFIG_ARCH_LEDS option is + enabled. -If enabled the LED is simply turned on when the board boots -succesfully, and is blinking on panic / assertion failed. + If enabled the LED is simply turned on when the board boots + succesfully, and is blinking on panic / assertion failed. UARTs ===== @@ -139,7 +145,7 @@ UARTs Default USART/UART Configuration -------------------------------- -USART1 (RX & TX only) is available through pins PA9 (TX) and PA10 (RX). + USART1 (RX & TX only) is available through pins PA9 (TX) and PA10 (RX). Timer Inputs/Outputs ==================== @@ -171,69 +177,133 @@ Timer Inputs/Outputs Using 128KiB of Flash instead of 64KiB ====================================== -Some people figured out that the STM32F103C8T6 has 128KiB of internal memory -instead of 64KiB as documented in the datasheet and reported by its internal -register. + Some people figured out that the STM32F103C8T6 has 128KiB of internal memory + instead of 64KiB as documented in the datasheet and reported by its internal + register. -In order to enable 128KiB you need modify the linker script to reflect this -new size. Open the configs/stm32f103-minimum/scripts/ld.script and replace: + In order to enable 128KiB you need modify the linker script to reflect this + new size. Open the configs/stm32f103-minimum/scripts/ld.script and replace: - flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K + flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K -with + with - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K -Enable many NuttX features (ie. many filesystems and applications) to get a -large binary image with more than 64K. + Enable many NuttX features (ie. many filesystems and applications) to get a + large binary image with more than 64K. -We will use OpenOCD to write the firmware in the STM32F103C8T6 Flash. Use a -up to dated OpenOCD version (ie. openocd-0.9). + We will use OpenOCD to write the firmware in the STM32F103C8T6 Flash. Use a + up to dated OpenOCD version (ie. openocd-0.9). -You will need to create a copy of original openocd/scripts/target/stm32f1x.cfg -to openocd/scripts/target/stm32f103c8t6.cfg and edit the later file replacing: + You will need to create a copy of original openocd/scripts/target/stm32f1x.cfg + to openocd/scripts/target/stm32f103c8t6.cfg and edit the later file replacing: - flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME + flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME -with + with - flash bank $_FLASHNAME stm32f1x 0x08000000 0x20000 0 0 $_TARGETNAME + flash bank $_FLASHNAME stm32f1x 0x08000000 0x20000 0 0 $_TARGETNAME -We will use OpenOCD with STLink-V2 programmer, but it will work with other -programmers (JLink, Versaloon, or some based on FTDI FT232, etc). + We will use OpenOCD with STLink-V2 programmer, but it will work with other + programmers (JLink, Versaloon, or some based on FTDI FT232, etc). -Open a terminal and execute: + Open a terminal and execute: - $ sudo openocd -f interface/stlink-v2.cfg -f target/stm32f103c8t6.cfg + $ sudo openocd -f interface/stlink-v2.cfg -f target/stm32f103c8t6.cfg -Now in other terminal execute: + Now in other terminal execute: - $ telnet localhost 4444 + $ telnet localhost 4444 - Trying 127.0.0.1... - Connected to localhost. - Escape character is '^]'. - Open On-Chip Debugger + Trying 127.0.0.1... + Connected to localhost. + Escape character is '^]'. + Open On-Chip Debugger - > reset halt - stm32f1x.cpu: target state: halted - target halted due to debug-request, current mode: Thread - xPSR: 0x01000000 pc: 0x080003ac msp: 0x20000d78 + > reset halt + stm32f1x.cpu: target state: halted + target halted due to debug-request, current mode: Thread + xPSR: 0x01000000 pc: 0x080003ac msp: 0x20000d78 - > flash write_image erase nuttx.bin 0x08000000 - auto erase enabled - device id = 0x20036410 - ignoring flash probed value, using configured bank size - flash size = 128kbytes - stm32f1x.cpu: target state: halted - target halted due to breakpoint, current mode: Thread - xPSR: 0x61000000 pc: 0x2000003a msp: 0x20000d78 - wrote 92160 bytes from file nuttx.bin in 4.942194s (18.211 KiB/s) + > flash write_image erase nuttx.bin 0x08000000 + auto erase enabled + device id = 0x20036410 + ignoring flash probed value, using configured bank size + flash size = 128kbytes + stm32f1x.cpu: target state: halted + target halted due to breakpoint, current mode: Thread + xPSR: 0x61000000 pc: 0x2000003a msp: 0x20000d78 + wrote 92160 bytes from file nuttx.bin in 4.942194s (18.211 KiB/s) - > reset run - > exit + > reset run + > exit -Now NuttX should start normally. + Now NuttX should start normally. + +Quadrature Encoder: +=================== + + The nsh configuration has been used to test the Quadrture Encoder + (QEncoder, QE) with the following modifications to the configuration + file: + + - These setting enable support for the common QEncode upper half driver: + + CONFIG_SENSORS=y + CONFIG_QENCODER=y + + - This is a board setting that selected timer 4 for use with the + quadrature encode: + + CONFIG_STM32F103MINIMUM_QETIMER=4 + + - These settings enable the STM32 Quadrature encoder on timer 4: + + CONFIG_STM32_TIM4_CAP=y + CONFIG_STM32_TIM4_QE=y + CONFIG_STM32_TIM4_QECLKOUT=2800000 + CONFIG_STM32_QENCODER_FILTER=y + CONFIG_STM32_QENCODER_SAMPLE_EVENT_6=y + CONFIG_STM32_QENCODER_SAMPLE_FDTS_4=y + + - These settings enable the test case at apps/examples/qencoder: + + CONFIG_EXAMPLES_QENCODER=y + CONFIG_EXAMPLES_QENCODER_DELAY=100 + CONFIG_EXAMPLES_QENCODER_DEVPATH="/dev/qe0" + + In this configuration, the QEncoder inputs will be on the TIM4 inputs of + PB6 and PB7. + +SDCard support: +=============== + + Only STM32F103xx High-density devices has SDIO controller. STM32F103C8T6 is a + Medium-density device, but we can use SDCard over SPI. + + You can do that enabling these options: + + CONFIG_FS_FAT=y + + CONFIG_FS_WRITABLE=y + + CONFIG_MMCSD=y + CONFIG_MMCSD_NSLOTS=1 + CONFIG_MMCSD_SPI=y + CONFIG_MMCSD_SPICLOCK=20000000 + CONFIG_MMCSD_SPIMODE=0 + + CONFIG_STM32_SPI=y + CONFIG_STM32_SPI1=y + + CONFIG_SPI=y + CONFIG_SPI_CALLBACK=y + CONFIG_SPI_EXCHANGE=y + + And connect a SDCard/SPI board on SPI1. Connect the CS pin to PA4, SCK to + PA5, MOSI to PA7 and MISO to PA6. Note: some chinese boards use MOSO instead + of MISO. STM32F103 Minimum - specific Configuration Options ================================================== @@ -406,21 +476,25 @@ STM32F103 Minimum - specific Configuration Options Configurations ============== -Each STM32F103 Minimum configuration is maintained in a sub-directory and -can be selected as follow: + Instantiating Configurations + ---------------------------- + Each STM32F103 Minimum configuration is maintained in a sub-directory and + can be selected as follow: cd tools ./configure.sh STM32F103 Minimum/ cd - . ./setenv.sh -If this is a Windows native build, then configure.bat should be used -instead of configure.sh: + If this is a Windows native build, then configure.bat should be used + instead of configure.sh: configure.bat STM32F103-Minimum\ -Where is one of the following: + Where is one of the following: + Configuration Directories + ------------------------- nsh: --- Configures the NuttShell (nsh) located at apps/examples/nsh. This diff --git a/configs/stm32f103-minimum/audio_tone/defconfig b/configs/stm32f103-minimum/audio_tone/defconfig index 492e93b565f..47bc80d08ff 100644 --- a/configs/stm32f103-minimum/audio_tone/defconfig +++ b/configs/stm32f103-minimum/audio_tone/defconfig @@ -945,7 +945,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f103-minimum/src/Makefile b/configs/stm32f103-minimum/src/Makefile index 367a1677e43..387e2bfe6a3 100644 --- a/configs/stm32f103-minimum/src/Makefile +++ b/configs/stm32f103-minimum/src/Makefile @@ -61,6 +61,10 @@ ifeq ($(CONFIG_RGBLED),y) CSRCS += stm32_rgbled.c endif +ifeq ($(CONFIG_MMCSD),y) +CSRCS += stm32_mmcsd.c +endif + ifeq ($(CONFIG_AUDIO_TONE),y) CSRCS += stm32_tone.c endif @@ -73,6 +77,10 @@ ifeq ($(CONFIG_LCD_ST7567),y) CSRCS += stm32_lcd.c endif +ifeq ($(CONFIG_QENCODER),y) +CSRCS += stm32_qencoder.c +endif + ifeq ($(CONFIG_VEML6070),y) CSRCS += stm32_veml6070.c endif diff --git a/configs/stm32f103-minimum/src/stm32_bringup.c b/configs/stm32f103-minimum/src/stm32_bringup.c index b193c04ab0b..2e76db5b8cd 100644 --- a/configs/stm32f103-minimum/src/stm32_bringup.c +++ b/configs/stm32f103-minimum/src/stm32_bringup.c @@ -81,6 +81,12 @@ # include "stm32_rtc.h" #endif +#ifdef CONFIG_NSH_MMCSDMINOR +# define MMCSD_MINOR CONFIG_NSH_MMCSDMINOR +#else +# define MMCSD_MINOR 0 +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -106,6 +112,15 @@ int stm32_bringup(void) #endif int ret = OK; +#ifdef CONFIG_MMCSD + ret = stm32_mmcsd_initialize(MMCSD_MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", ret); + return ret; + } +#endif + #ifdef CONFIG_PWM /* Initialize PWM and register the PWM device. */ @@ -163,6 +178,18 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_QENCODER + /* Initialize and register the qencoder driver */ + + ret = stm32_qencoder_initialize("/dev/qe0", CONFIG_STM32F103MINIMUM_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + } +#endif + #ifdef CONFIG_USERLED /* Register the LED driver */ diff --git a/configs/stm32f103-minimum/src/stm32_buttons.c b/configs/stm32f103-minimum/src/stm32_buttons.c index d611bf44fb2..96fd053eef3 100644 --- a/configs/stm32f103-minimum/src/stm32_buttons.c +++ b/configs/stm32f103-minimum/src/stm32_buttons.c @@ -152,7 +152,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -161,7 +161,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler); + irqhandler, arg); } return oldhandler; diff --git a/configs/stm32f103-minimum/src/stm32_mmcsd.c b/configs/stm32f103-minimum/src/stm32_mmcsd.c new file mode 100644 index 00000000000..2b657a66473 --- /dev/null +++ b/configs/stm32f103-minimum/src/stm32_mmcsd.c @@ -0,0 +1,129 @@ +/***************************************************************************** + * configs/stm32f103-minimum/src/stm32_mmcsd.c + * + * Copyright (C) 2017 Greg Nutt. All rights reserved. + * Author: Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + +/***************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stm32.h" +#include "stm32f103_minimum.h" +#include "stm32_spi.h" + +/***************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_SPI1 +# error "SD driver requires CONFIG_STM32_SPI1 to be enabled" +#endif + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" +#endif + +/***************************************************************************** + * Private Definitions + ****************************************************************************/ + +static const int SD_SPI_PORT = 1; /* SD is connected to SPI1 port */ +static const int SD_SLOT_NO = 0; /* There is only one SD slot */ + +/***************************************************************************** + * Private Functions + ****************************************************************************/ + +/* NOTE: We are using a SDCard adapter/module without Card Detect pin! + * Then we don't need to Card Detect callback here. + */ + +/***************************************************************************** + * Public Functions + ****************************************************************************/ + +/***************************************************************************** + * Name: stm32_spi1register + * + * Description: + * Registers media change callback + ****************************************************************************/ + +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg) +{ + spiinfo("INFO: Registering spi1 device\n"); + return OK; +} + +/***************************************************************************** + * Name: stm32_mmcsd_initialize + * + * Description: + * Initialize SPI-based SD card and card detect thread. + ****************************************************************************/ + +int stm32_mmcsd_initialize(int minor) +{ + struct spi_dev_s *spi; + int rv; + + mcinfo("INFO: Initializing mmcsd card\n"); + + spi = stm32_spibus_initialize(SD_SPI_PORT); + if (spi == NULL) + { + mcerr("ERROR: Failed to initialize SPI port %d\n", SD_SPI_PORT); + return -ENODEV; + } + + rv = mmcsd_spislotinitialize(minor, SD_SLOT_NO, spi); + if (rv < 0) + { + mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n", + SD_SPI_PORT, SD_SLOT_NO); + return rv; + } + + spiinfo("INFO: mmcsd card has been initialized successfully\n"); + return OK; +} diff --git a/configs/stm32f103-minimum/src/stm32_qencoder.c b/configs/stm32f103-minimum/src/stm32_qencoder.c new file mode 100644 index 00000000000..ae4508b02b3 --- /dev/null +++ b/configs/stm32f103-minimum/src/stm32_qencoder.c @@ -0,0 +1,80 @@ +/************************************************************************************ + * configs/stm32f103-minimum/src/stm32_qencoder.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "stm32_qencoder.h" +#include "stm32f103_minimum.h" + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_qencoder_initialize + * + * Description: + * All STM32 architectures must provide the following interface to work with + * examples/qencoder. + * + ************************************************************************************/ + +int stm32_qencoder_initialize(FAR const char *devpath, int timer) +{ + int ret; + + /* Initialize a quadrature encoder interface. */ + + sninfo("Initializing the quadrature encoder using TIM%d\n", timer); + ret = stm32_qeinitialize(devpath, timer); + if (ret < 0) + { + snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); + } + + return ret; +} diff --git a/configs/stm32f103-minimum/src/stm32_spi.c b/configs/stm32f103-minimum/src/stm32_spi.c index 2ddc0184814..2d24b7aa3d9 100644 --- a/configs/stm32f103-minimum/src/stm32_spi.c +++ b/configs/stm32f103-minimum/src/stm32_spi.c @@ -85,6 +85,10 @@ void stm32_spidev_initialize(void) #ifdef CONFIG_WL_NRF24L01 stm32_configgpio(GPIO_NRF24L01_CS); /* nRF24L01 chip select */ #endif + +#ifdef CONFIG_MMCSD_SPI + stm32_configgpio(GPIO_SDCARD_CS); /* SD/MMC Card chip select */ +#endif } /**************************************************************************** @@ -136,6 +140,13 @@ void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, stm32_gpiowrite(GPIO_NRF24L01_CS, !selected); } #endif + +#ifdef CONFIG_MMCSD_SPI + if (devid == SPIDEV_MMCSD) + { + stm32_gpiowrite(GPIO_SDCARD_CS, !selected); + } +#endif } uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) @@ -149,6 +160,13 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) } #endif +#ifdef CONFIG_MMCSD_SPI + if (devid == SPIDEV_MMCSD) + { + status |= SPI_STATUS_PRESENT; + } +#endif + return status; } #endif diff --git a/configs/stm32f103-minimum/src/stm32_wireless.c b/configs/stm32f103-minimum/src/stm32_wireless.c index 51802585f63..e5d7c21073d 100644 --- a/configs/stm32f103-minimum/src/stm32_wireless.c +++ b/configs/stm32f103-minimum/src/stm32_wireless.c @@ -60,8 +60,7 @@ * Private Function Prototypes ************************************************************************************/ -static int stm32tiny_wl_irq_attach(xcpt_t isr); - +static int stm32tiny_wl_irq_attach(xcpt_t isr, FAR void *arg); static void stm32tiny_wl_chip_enable(bool enable); /************************************************************************************ @@ -75,16 +74,18 @@ static FAR struct nrf24l01_config_s nrf_cfg = }; static xcpt_t g_isr; +static FAR void *g_arg; /************************************************************************************ * Private Functions ************************************************************************************/ -static int stm32tiny_wl_irq_attach(xcpt_t isr) +static int stm32tiny_wl_irq_attach(xcpt_t isr, FAR void *arg) { winfo("Attach IRQ\n"); g_isr = isr; - stm32_gpiosetevent(GPIO_NRF24L01_IRQ, false, true, false, g_isr); + g_arg = arg; + stm32_gpiosetevent(GPIO_NRF24L01_IRQ, false, true, false, g_isr, g_arg); return OK; } diff --git a/configs/stm32f103-minimum/src/stm32f103_minimum.h b/configs/stm32f103-minimum/src/stm32f103_minimum.h index de00b39f628..5495596a0be 100644 --- a/configs/stm32f103-minimum/src/stm32f103_minimum.h +++ b/configs/stm32f103-minimum/src/stm32f103_minimum.h @@ -89,6 +89,9 @@ #define GPIO_NRF24L01_CS (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN4) +#define GPIO_SDCARD_CS (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN4) + #define STM32_LCD_RST (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN3) @@ -152,6 +155,18 @@ int stm32_bringup(void); void stm32_spidev_initialize(void); +/**************************************************************************** + * Name: stm32_qencoder_initialize + * + * Description: + * Initialize and register a qencoder + * + ****************************************************************************/ + +#ifdef CONFIG_QENCODER +int stm32_qencoder_initialize(FAR const char *devpath, int timer); +#endif + /**************************************************************************** * Name stm32_rgbled_setup * diff --git a/configs/stm32f3discovery/src/stm32_buttons.c b/configs/stm32f3discovery/src/stm32_buttons.c index db0d6418313..f15c22f8a9c 100644 --- a/configs/stm32f3discovery/src/stm32_buttons.c +++ b/configs/stm32f3discovery/src/stm32_buttons.c @@ -152,7 +152,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -160,7 +160,8 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); } return oldhandler; diff --git a/configs/stm32f429i-disco/README.txt b/configs/stm32f429i-disco/README.txt index 13ba9b52ca1..2b406e035cb 100644 --- a/configs/stm32f429i-disco/README.txt +++ b/configs/stm32f429i-disco/README.txt @@ -8,7 +8,7 @@ memory and 256kbytes. The board features: - On-board ST-LINK/V2 for programming and debugging, - On-board 64 Mbits (8 Mbytes) External SDRAM (1 Mbit x 16-bit x 4-bank) - - LIS302DL, ST MEMS motion sensor, 3-axis digital output accelerometer, + - L3GD20, ST MEMS motion sensor, 3-axis digital output gyroscope, - TFT 2.4" LCD, 262K color RGB, 240 x 320 pixels - Touchscreen controller - Two user LEDs and two push-buttons, diff --git a/configs/stm32f429i-disco/extflash/defconfig b/configs/stm32f429i-disco/extflash/defconfig index 45d62cfe047..adb39d76a14 100644 --- a/configs/stm32f429i-disco/extflash/defconfig +++ b/configs/stm32f429i-disco/extflash/defconfig @@ -1022,7 +1022,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f429i-disco/lcd/defconfig b/configs/stm32f429i-disco/lcd/defconfig index 017587b2936..55c086a56c3 100644 --- a/configs/stm32f429i-disco/lcd/defconfig +++ b/configs/stm32f429i-disco/lcd/defconfig @@ -1070,7 +1070,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f429i-disco/ltdc/defconfig b/configs/stm32f429i-disco/ltdc/defconfig index eada5df1f99..f534914cda9 100644 --- a/configs/stm32f429i-disco/ltdc/defconfig +++ b/configs/stm32f429i-disco/ltdc/defconfig @@ -1088,7 +1088,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f429i-disco/nsh/defconfig b/configs/stm32f429i-disco/nsh/defconfig index 9941b7aa49e..aa843ace342 100644 --- a/configs/stm32f429i-disco/nsh/defconfig +++ b/configs/stm32f429i-disco/nsh/defconfig @@ -935,7 +935,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f429i-disco/nxwm/defconfig b/configs/stm32f429i-disco/nxwm/defconfig index 0a9414b9763..6c90c64117a 100644 --- a/configs/stm32f429i-disco/nxwm/defconfig +++ b/configs/stm32f429i-disco/nxwm/defconfig @@ -1141,7 +1141,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f429i-disco/src/Makefile b/configs/stm32f429i-disco/src/Makefile index 9dcff952a20..2ff0cb8d235 100644 --- a/configs/stm32f429i-disco/src/Makefile +++ b/configs/stm32f429i-disco/src/Makefile @@ -72,6 +72,10 @@ ifeq ($(CONFIG_STM32F429I_DISCO_ILI9341),y) CSRCS += stm32_ili93414ws.c endif +ifeq ($(CONFIG_SENSORS_L3GD20),y) +CSRCS += stm32_l3gd20.c +endif + ifeq ($(and \ $(CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE), \ $(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE), \ diff --git a/configs/stm32f429i-disco/src/stm32_appinit.c b/configs/stm32f429i-disco/src/stm32_appinit.c index 26b92f3e4cc..bbd1b18078c 100644 --- a/configs/stm32f429i-disco/src/stm32_appinit.c +++ b/configs/stm32f429i-disco/src/stm32_appinit.c @@ -165,6 +165,8 @@ int board_app_initialize(uintptr_t arg) int ret; #elif defined(HAVE_USBHOST) || defined(HAVE_USBMONITOR) int ret; +#elif defined(CONFIG_SENSORS_L3GD20) + int ret; #endif /* Configure SPI-based devices */ @@ -378,5 +380,13 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_SENSORS_L3GD20 + ret = stm32_l3gd20initialize("/dev/gyr0"); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize l3gd20 sensor: %d\n", ret); + } +#endif + return OK; } diff --git a/configs/stm32f429i-disco/src/stm32_buttons.c b/configs/stm32f429i-disco/src/stm32_buttons.c index 6dbe3cba7a9..396b8750546 100644 --- a/configs/stm32f429i-disco/src/stm32_buttons.c +++ b/configs/stm32f429i-disco/src/stm32_buttons.c @@ -152,7 +152,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -160,8 +160,10 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); } + return oldhandler; } #endif diff --git a/configs/stm32f429i-disco/src/stm32_l3gd20.c b/configs/stm32f429i-disco/src/stm32_l3gd20.c new file mode 100644 index 00000000000..1d6dd2cc2d5 --- /dev/null +++ b/configs/stm32f429i-disco/src/stm32_l3gd20.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * configs/stm32f429i-disco/src/stm32_l3gd20.c + * + * Copyright (C) Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_spi.h" +#include "stm32f429i-disco.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_SPI) & defined(CONFIG_SENSORS_L3GD20) + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int l3gd20_attach(FAR struct l3gd20_config_s * cfg, xcpt_t irq); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Only one L3GD20 device on board */ + +static struct l3gd20_config_s g_l3gd20_config = +{ + .attach = l3gd20_attach, + .irq = L3GD20_IRQ, + .spi_devid = SPIDEV_ACCELEROMETER +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: l3gd20_attach() + * + * Description: Attach the l3gd20 interrupt handler to the GPIO interrupt + * + ****************************************************************************/ + +static int l3gd20_attach(FAR struct l3gd20_config_s * cfg, xcpt_t irq) +{ + stm32_gpiosetevent(GPIO_L3GD20_DREADY, true, false, true, irq, NULL); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_l3gd20initialize() + * + * Description: + * Initialize and register the L3GD20 3 axis gyroscope sensor driver. + * + * Input parameters: + * devpath - The full path to the driver to register. E.g., "/dev/gyro0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_l3gd20initialize(FAR const char *devpath) +{ + int ret = 0; + struct spi_dev_s *spi; + + /* Configure DREADY IRQ input */ + + stm32_configgpio(GPIO_L3GD20_DREADY); + + /* Initialize SPI */ + + spi = stm32_spi5initialize(); + + if (!spi) + { + ret = -ENODEV; + goto errout; + } + + /* Then register the gyro */ + + ret = l3gd20_register(devpath, spi, &g_l3gd20_config); + if (ret != OK) + { + goto errout; + } + +errout: + return ret; +} + +#endif /* CONFIG_SPI && CONFIG_SENSORS_L3GD20 */ diff --git a/configs/stm32f429i-disco/src/stm32_stmpe811.c b/configs/stm32f429i-disco/src/stm32_stmpe811.c index 4e678cef0e8..13c0a91dc79 100644 --- a/configs/stm32f429i-disco/src/stm32_stmpe811.c +++ b/configs/stm32f429i-disco/src/stm32_stmpe811.c @@ -137,6 +137,7 @@ struct stm32_stmpe811config_s STMPE811_HANDLE handle; /* The STMPE811 driver handle */ xcpt_t handler; /* The STMPE811 interrupt handler */ + FAR void *arg; /* Interrupt handler argument */ }; /**************************************************************************** @@ -153,7 +154,8 @@ struct stm32_stmpe811config_s * clear - Acknowledge/clear any pending GPIO interrupt */ -static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr); +static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr, + FAR void *arg); static void stmpe811_enable(FAR struct stmpe811_config_s *state, bool enable); static void stmpe811_clear(FAR struct stmpe811_config_s *state); @@ -192,6 +194,7 @@ static struct stm32_stmpe811config_s g_stmpe811config = .clear = stmpe811_clear, }, .handler = NULL, + .arg = NULL, }; #endif @@ -208,7 +211,8 @@ static struct stm32_stmpe811config_s g_stmpe811config = * clear - Acknowledge/clear any pending GPIO interrupt */ -static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr) +static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr, + FAR void *arg) { FAR struct stm32_stmpe811config_s *priv = (FAR struct stm32_stmpe811config_s *)state; @@ -219,6 +223,7 @@ static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr) /* Just save the handler. We will use it when EXTI interruptsare enabled */ priv->handler = isr; + priv->arg = arg; return OK; } @@ -239,14 +244,16 @@ static void stmpe811_enable(FAR struct stmpe811_config_s *state, bool enable) /* Configure the EXTI interrupt using the SAVED handler */ (void)stm32_gpiosetevent(GPIO_IO_EXPANDER, true, true, true, - priv->handler); + priv->handler, priv->arg); } else { /* Configure the EXTI interrupt with a NULL handler to disable it */ - (void)stm32_gpiosetevent(GPIO_IO_EXPANDER, false, false, false, NULL); + (void)stm32_gpiosetevent(GPIO_IO_EXPANDER, false, false, false, + NULL, NULL); } +` leave_critical_section(flags); } diff --git a/configs/stm32f429i-disco/src/stm32_usb.c b/configs/stm32f429i-disco/src/stm32_usb.c index 011726a69b1..3daa643edca 100644 --- a/configs/stm32f429i-disco/src/stm32_usb.c +++ b/configs/stm32f429i-disco/src/stm32_usb.c @@ -288,7 +288,7 @@ void stm32_usbhost_vbusdrive(int iface, bool enable) #ifdef CONFIG_USBHOST xcpt_t stm32_setup_overcurrent(xcpt_t handler) { - return stm32_gpiosetevent(GPIO_OTGHS_OVER, true, true, true, handler); + return stm32_gpiosetevent(GPIO_OTGHS_OVER, true, true, true, handler, NULL); } #endif diff --git a/configs/stm32f429i-disco/src/stm32f429i-disco.h b/configs/stm32f429i-disco/src/stm32f429i-disco.h index 1b309a72006..e9408e3355b 100644 --- a/configs/stm32f429i-disco/src/stm32f429i-disco.h +++ b/configs/stm32f429i-disco/src/stm32f429i-disco.h @@ -114,6 +114,11 @@ #define GPIO_CS_SST25 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN4) +/* L3GD20 MEMS */ + +#define GPIO_L3GD20_DREADY (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN2) +#define L3GD20_IRQ (2 + STM32_IRQ_EXTI0) + /* USB OTG HS * * PA9 OTG_HS_VBUS VBUS sensing (also connected to the green LED) @@ -230,7 +235,6 @@ void stm32_ledpminitialize(void); void stm32_pmbuttons(void); #endif -#ifdef CONFIG_STM32F429I_DISCO_ILI9341 /**************************************************************************** * Name: stm32_ili93414ws_initialize * @@ -246,10 +250,10 @@ void stm32_pmbuttons(void); * ****************************************************************************/ +#ifdef CONFIG_STM32F429I_DISCO_ILI9341 FAR struct ili9341_lcd_s *stm32_ili93414ws_initialize(void); #endif -#ifdef CONFIG_STM32_SPI5 /**************************************************************************** * Name: stm32_spi5initialize * @@ -272,9 +276,29 @@ FAR struct ili9341_lcd_s *stm32_ili93414ws_initialize(void); * ****************************************************************************/ +#ifdef CONFIG_STM32_SPI5 FAR struct spi_dev_s *stm32_spi5initialize(void); #endif + +/**************************************************************************** + * Name: stm32_l3gd20initialize() + * + * Description: + * Initialize and register the L3GD20 3 axis gyroscope sensor driver. + * + * Input parameters: + * devpath - The full path to the driver to register. E.g., "/dev/gyro0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#if defined(CONFIG_SPI) & defined(CONFIG_SENSORS_L3GD20) +int stm32_l3gd20initialize(FAR const char *devpath); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_STM32F429I_DISCO_SRC_STM32F429I_DISCO_H */ diff --git a/configs/stm32f429i-disco/usbmsc/defconfig b/configs/stm32f429i-disco/usbmsc/defconfig index 75fd641a7e2..fa1af2fa910 100644 --- a/configs/stm32f429i-disco/usbmsc/defconfig +++ b/configs/stm32f429i-disco/usbmsc/defconfig @@ -971,7 +971,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f429i-disco/usbnsh/defconfig b/configs/stm32f429i-disco/usbnsh/defconfig index f646ce371e9..aa1481a5e8d 100644 --- a/configs/stm32f429i-disco/usbnsh/defconfig +++ b/configs/stm32f429i-disco/usbnsh/defconfig @@ -985,7 +985,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f4discovery/Kconfig b/configs/stm32f4discovery/Kconfig index 9703364210e..badfd635f94 100644 --- a/configs/stm32f4discovery/Kconfig +++ b/configs/stm32f4discovery/Kconfig @@ -24,7 +24,7 @@ config STM32F4DISCO_USBHOST_PRIO config STM32F4DISCO_QETIMER int "Timer to use with QE encoder" - default 3 + default 2 depends on QENCODER config PM_BUTTONS diff --git a/configs/stm32f4discovery/README.txt b/configs/stm32f4discovery/README.txt index 3885d33063e..472621c1fec 100644 --- a/configs/stm32f4discovery/README.txt +++ b/configs/stm32f4discovery/README.txt @@ -31,6 +31,7 @@ Contents - PWM - UARTs - Timer Inputs/Outputs + - Quadrature Encoder - FPU - STM32F4DIS-BB - FSMC SRAM @@ -447,16 +448,52 @@ TIM14 free I/O pins. ** Port H pins are not supported by the MCU -Quadrature Encode Timer Inputs ------------------------------- +Quadrature Encoder: +=================== -If enabled (by setting CONFIG_QENCODER=y), then quadrature encoder will -use either TIM2 or TIM8 (see nsh/defconfig). If TIM2 is selected, the input -pins PA15 and PA1 for CH1 and CH2, respectively). If TIM8 is selected, then -PC6 and PI5 will be used for CH1 and CH2 (see include board.h for pin -definitions). + The nsh configuration has been used to test the Quadrture Encoder + (QEncoder, QE) with the following modifications to the configuration + file: -Selected via CONFIG_STM32F4DISCO_QETIMER + - These setting enable support for the common QEncode upper half driver: + + CONFIG_BOARD_INITIALIZE=y + + CONFIG_SENSORS=y + CONFIG_QENCODER=y + + - The timer 2 needs to be enabled: + + CONFIG_STM32_TIM2=y + + - This is a board setting that selected timer 2 for use with the + quadrature encode: + + CONFIG_STM32F4DISCO_QETIMER=2 + + - These settings enable the STM32 Quadrature encoder on timer 2: + + CONFIG_STM32_TIM2_QE=y + CONFIG_STM32_TIM4_QECLKOUT=2800000 + CONFIG_STM32_QENCODER_FILTER=y + CONFIG_STM32_QENCODER_SAMPLE_EVENT_6=y + CONFIG_STM32_QENCODER_SAMPLE_FDTS_4=y + + - These settings enable the test case at apps/examples/qencoder: + + CONFIG_EXAMPLES_QENCODER=y + CONFIG_EXAMPLES_QENCODER_DELAY=100 + CONFIG_EXAMPLES_QENCODER_DEVPATH="/dev/qe0" + + In this configuration, the QEncoder inputs will be on the TIM2 inputs of + PA15 and PA1 (CH1 and CH2 respectively). + + You can also use QEncoder with other timers, but keep in mind that only TIM2 + and TIM5 are 32bits timers, all other timers are 16-bit then the QE counter + will overflow after 65535. + + If TIM4 is selected, then PB6 and PB7 will be used for CH1 and CH2. + If TIM8 is selected, then PC6 and PI5 will be used for CH1 and CH2. FPU === diff --git a/configs/stm32f4discovery/elf/defconfig b/configs/stm32f4discovery/elf/defconfig index c2b11282d53..254c8c9fadf 100644 --- a/configs/stm32f4discovery/elf/defconfig +++ b/configs/stm32f4discovery/elf/defconfig @@ -930,7 +930,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set CONFIG_LIBC_ARCH_ELF=y # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f4discovery/ipv6/defconfig b/configs/stm32f4discovery/ipv6/defconfig index 4ffc7411b70..297762a9b9a 100644 --- a/configs/stm32f4discovery/ipv6/defconfig +++ b/configs/stm32f4discovery/ipv6/defconfig @@ -1161,7 +1161,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f4discovery/netnsh/defconfig b/configs/stm32f4discovery/netnsh/defconfig index f797f4176f6..a7f1bfd9e9d 100644 --- a/configs/stm32f4discovery/netnsh/defconfig +++ b/configs/stm32f4discovery/netnsh/defconfig @@ -1165,7 +1165,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f4discovery/nsh/defconfig b/configs/stm32f4discovery/nsh/defconfig index 48d50e75921..f20f8922393 100644 --- a/configs/stm32f4discovery/nsh/defconfig +++ b/configs/stm32f4discovery/nsh/defconfig @@ -951,7 +951,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f4discovery/posix_spawn/defconfig b/configs/stm32f4discovery/posix_spawn/defconfig index e278e58698a..e25f358c9a3 100644 --- a/configs/stm32f4discovery/posix_spawn/defconfig +++ b/configs/stm32f4discovery/posix_spawn/defconfig @@ -930,7 +930,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set CONFIG_LIBC_ARCH_ELF=y # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f4discovery/src/stm32_buttons.c b/configs/stm32f4discovery/src/stm32_buttons.c index b068e03dad2..5143fd8eca0 100644 --- a/configs/stm32f4discovery/src/stm32_buttons.c +++ b/configs/stm32f4discovery/src/stm32_buttons.c @@ -152,7 +152,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -160,8 +160,10 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); } + return oldhandler; } #endif diff --git a/configs/stm32f4discovery/src/stm32_ethernet.c b/configs/stm32f4discovery/src/stm32_ethernet.c index 67b7b9e95e3..0cc23c60167 100644 --- a/configs/stm32f4discovery/src/stm32_ethernet.c +++ b/configs/stm32f4discovery/src/stm32_ethernet.c @@ -112,13 +112,15 @@ static void stm32_emac0_phy_enable(bool enable) { /* Attach and enable GPIO interrupt (and event) on the falling edge */ - (void)stm32_gpiosetevent(GPIO_EMAC_NINT, false, true, true, g_ethmac_handler); + (void)stm32_gpiosetevent(GPIO_EMAC_NINT, false, true, true, + g_ethmac_handler, NULL); } else { /* Detach and disable GPIO interrupt */ - (void)stm32_gpiosetevent(GPIO_EMAC_NINT, false, false, false, NULL); + (void)stm32_gpiosetevent(GPIO_EMAC_NINT, false, false, false, + NULL, NULL); } } #endif diff --git a/configs/stm32f4discovery/src/stm32_pmbuttons.c b/configs/stm32f4discovery/src/stm32_pmbuttons.c index 750eaadbbe1..6b974ea38b6 100644 --- a/configs/stm32f4discovery/src/stm32_pmbuttons.c +++ b/configs/stm32f4discovery/src/stm32_pmbuttons.c @@ -80,7 +80,7 @@ ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -static int button_handler(int irq, FAR void *context); +static int button_handler(int irq, FAR void *context, FAR void *arg); #endif /* CONFIG_ARCH_IRQBUTTONS */ /**************************************************************************** @@ -96,7 +96,7 @@ static int button_handler(int irq, FAR void *context); ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -static int button_handler(int irq, FAR void *context) +static int button_handler(int irq, FAR void *context, FAR void *arg) { /* At this point the MCU should have already awakened. The state * change will be handled in the IDLE loop when the system is re-awakened @@ -130,7 +130,7 @@ void stm32_pm_buttons(void) board_button_initialize(); #ifdef CONFIG_ARCH_IRQBUTTONS - xcpt_t oldhandler = board_button_irq(0, button_handler); + xcpt_t oldhandler = board_button_irq(0, button_handler, NULL); if (oldhandler != NULL) { diff --git a/configs/stm32f4discovery/src/stm32_qencoder.c b/configs/stm32f4discovery/src/stm32_qencoder.c index 80264a7a2a0..24bf2519d30 100644 --- a/configs/stm32f4discovery/src/stm32_qencoder.c +++ b/configs/stm32f4discovery/src/stm32_qencoder.c @@ -78,5 +78,3 @@ int stm32_qencoder_initialize(FAR const char *devpath, int timer) return ret; } - -#endif /* HAVE_QENCODER */ diff --git a/configs/stm32f4discovery/src/stm32_sdio.c b/configs/stm32f4discovery/src/stm32_sdio.c index a82a38d3488..d7271c7cab9 100644 --- a/configs/stm32f4discovery/src/stm32_sdio.c +++ b/configs/stm32f4discovery/src/stm32_sdio.c @@ -128,7 +128,8 @@ int stm32_sdio_initialize(void) /* Register an interrupt handler for the card detect pin */ - stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, stm32_ncd_interrupt); + stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, + stm32_ncd_interrupt, NULL); #endif /* Mount the SDIO-based MMC/SD block driver */ diff --git a/configs/stm32f4discovery/src/stm32_usb.c b/configs/stm32f4discovery/src/stm32_usb.c index 397aaff76df..f6571406540 100644 --- a/configs/stm32f4discovery/src/stm32_usb.c +++ b/configs/stm32f4discovery/src/stm32_usb.c @@ -311,7 +311,7 @@ void stm32_usbhost_vbusdrive(int iface, bool enable) #ifdef CONFIG_USBHOST xcpt_t stm32_setup_overcurrent(xcpt_t handler) { - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler); + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); } #endif diff --git a/configs/stm32f4discovery/src/stm32_xen1210.c b/configs/stm32f4discovery/src/stm32_xen1210.c index a8dc104ebe2..b6363a1e2ec 100644 --- a/configs/stm32f4discovery/src/stm32_xen1210.c +++ b/configs/stm32f4discovery/src/stm32_xen1210.c @@ -154,7 +154,7 @@ static struct stm32_xen1210config_s g_xen1210config = /* This is the XEN1210 Interrupt handler */ -int xen1210_interrupt(int irq, FAR void *context) +int xen1210_interrupt(int irq, FAR void *context, FAR void *arg) { /* Verify that we have a handler attached */ @@ -211,13 +211,14 @@ static void xen1210_enable(FAR struct xen1210_config_s *state, bool enable) stm32_configgpio(GPIO_XEN1210_INT); (void)stm32_gpiosetevent(GPIO_XEN1210_INT, false, true, - true, xen1210_interrupt); + true, xen1210_interrupt, NULL); } else { /* Configure the interrupt with a NULL handler to disable it */ - (void)stm32_gpiosetevent(GPIO_XEN1210_INT, false, false, false, NULL); + (void)stm32_gpiosetevent(GPIO_XEN1210_INT, false, false, false, + NULL, NULL); } leave_critical_section(flags); diff --git a/configs/stm32f4discovery/src/stm32_zerocross.c b/configs/stm32f4discovery/src/stm32_zerocross.c index af0b99b860a..92703f56615 100644 --- a/configs/stm32f4discovery/src/stm32_zerocross.c +++ b/configs/stm32f4discovery/src/stm32_zerocross.c @@ -120,7 +120,7 @@ static void zcross_enable(FAR const struct zc_lowerhalf_s *lower, } (void)stm32_gpiosetevent(GPIO_ZEROCROSS, rising, falling, - true, zcross_interrupt); + true, zcross_interrupt, NULL); leave_critical_section(flags); } diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig index 4c8131f4877..1aecbaa4f1b 100644 --- a/configs/stm32f746-ws/nsh/defconfig +++ b/configs/stm32f746-ws/nsh/defconfig @@ -862,7 +862,7 @@ CONFIG_FAT_DIRECT_RETRY=y # Memory Management # # CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=2 +CONFIG_MM_REGIONS=3 # CONFIG_ARCH_HAVE_HEAP2 is not set CONFIG_GRAN=y # CONFIG_GRAN_SINGLE is not set @@ -912,7 +912,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f746-ws/src/stm32_sdmmc.c b/configs/stm32f746-ws/src/stm32_sdmmc.c index 9dfaaa34a71..dce13b291da 100644 --- a/configs/stm32f746-ws/src/stm32_sdmmc.c +++ b/configs/stm32f746-ws/src/stm32_sdmmc.c @@ -126,7 +126,8 @@ int stm32_sdio_initialize(void) /* Register an interrupt handler for the card detect pin */ - stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, stm32_ncd_interrupt); + stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, + stm32_ncd_interrupt, NULL); #endif /* Mount the SDIO-based MMC/SD block driver */ diff --git a/configs/stm32f746-ws/src/stm32_usb.c b/configs/stm32f746-ws/src/stm32_usb.c index 770f950fa06..84f782c5ef9 100644 --- a/configs/stm32f746-ws/src/stm32_usb.c +++ b/configs/stm32f746-ws/src/stm32_usb.c @@ -314,7 +314,7 @@ void stm32_usbhost_vbusdrive(int iface, bool enable) #ifdef CONFIG_USBHOST xcpt_t stm32_setup_overcurrent(xcpt_t handler) { - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler); + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); } #endif diff --git a/configs/stm32f746g-disco/nsh/defconfig b/configs/stm32f746g-disco/nsh/defconfig index e26a16f8abb..8d24e4b5ee9 100644 --- a/configs/stm32f746g-disco/nsh/defconfig +++ b/configs/stm32f746g-disco/nsh/defconfig @@ -732,7 +732,7 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue" # Memory Management # # CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=2 +CONFIG_MM_REGIONS=3 # CONFIG_ARCH_HAVE_HEAP2 is not set # CONFIG_GRAN is not set diff --git a/configs/stm32f746g-disco/src/stm32_buttons.c b/configs/stm32f746g-disco/src/stm32_buttons.c index 8578c0794ed..43051e49604 100644 --- a/configs/stm32f746g-disco/src/stm32_buttons.c +++ b/configs/stm32f746g-disco/src/stm32_buttons.c @@ -104,7 +104,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { #warning Missing logic } diff --git a/configs/stm32l476-mdk/nsh/defconfig b/configs/stm32l476-mdk/nsh/defconfig index 7882b95b172..9ff2d597c4f 100644 --- a/configs/stm32l476-mdk/nsh/defconfig +++ b/configs/stm32l476-mdk/nsh/defconfig @@ -61,9 +61,12 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -103,7 +106,9 @@ CONFIG_ARCH_CHIP_STM32L4=y # CONFIG_ARCH_ARM926EJS is not set # CONFIG_ARCH_ARM920T is not set # CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM23 is not set # CONFIG_ARCH_CORTEXM3 is not set +# CONFIG_ARCH_CORTEXM33 is not set CONFIG_ARCH_CORTEXM4=y # CONFIG_ARCH_CORTEXM7 is not set # CONFIG_ARCH_CORTEXA5 is not set @@ -158,6 +163,8 @@ CONFIG_ARMV7M_HAVE_STACKCHECK=y CONFIG_ARCH_CHIP_STM32L476RG=y # CONFIG_ARCH_CHIP_STM32L476RE is not set # CONFIG_ARCH_CHIP_STM32L486 is not set +# CONFIG_STM32L4_STM32L4X3 is not set +CONFIG_STM32L4_STM32L4X6=y CONFIG_STM32L4_STM32L476XX=y # CONFIG_STM32L4_STM32L486XX is not set # CONFIG_STM32L4_FLASH_256KB is not set @@ -178,6 +185,8 @@ CONFIG_STM32L4_FLASH_1024KB=y # STM32L4 Peripheral Support # # CONFIG_STM32L4_HAVE_LTDC is not set +CONFIG_STM32L4_HAVE_SAI1=y +CONFIG_STM32L4_HAVE_SAI2=y # CONFIG_STM32L4_ADC is not set # CONFIG_STM32L4_CAN is not set # CONFIG_STM32L4_DAC is not set @@ -205,6 +214,10 @@ CONFIG_STM32L4_DMA2=y # CONFIG_STM32L4_ADC3 is not set # CONFIG_STM32L4_AES is not set CONFIG_STM32L4_RNG=y +# CONFIG_STM32L4_SAI1_A is not set +# CONFIG_STM32L4_SAI1_B is not set +# CONFIG_STM32L4_SAI2_A is not set +# CONFIG_STM32L4_SAI2_B is not set # # AHB3 Peripherals @@ -228,6 +241,8 @@ CONFIG_STM32L4_PWR=y # CONFIG_STM32L4_USART1 is not set # CONFIG_STM32L4_USART2 is not set CONFIG_STM32L4_USART3=y +# CONFIG_STM32L4_UART4 is not set +# CONFIG_STM32L4_UART5 is not set # CONFIG_STM32L4_I2C1 is not set # CONFIG_STM32L4_I2C2 is not set # CONFIG_STM32L4_I2C3 is not set @@ -276,9 +291,11 @@ CONFIG_STM32L4_SAI1PLL=y # # CONFIG_STM32L4_ONESHOT is not set # CONFIG_STM32L4_FREERUN is not set +CONFIG_STM32L4_HAVE_USART1=y +CONFIG_STM32L4_HAVE_USART2=y CONFIG_STM32L4_HAVE_USART3=y -# CONFIG_STM32L4_HAVE_USART4 is not set -# CONFIG_STM32L4_HAVE_USART5 is not set +CONFIG_STM32L4_HAVE_UART4=y +CONFIG_STM32L4_HAVE_UART5=y # # U[S]ART Configuration @@ -403,6 +420,7 @@ CONFIG_PREALLOC_TIMERS=4 # # Tasks and Scheduling # +# CONFIG_SPINLOCK is not set # CONFIG_INIT_NONE is not set CONFIG_INIT_ENTRYPOINT=y # CONFIG_INIT_FILEPATH is not set @@ -419,6 +437,8 @@ CONFIG_SCHED_WAITPID=y # # CONFIG_MUTEX_TYPES is not set CONFIG_NPTHREAD_KEYS=4 +# CONFIG_PTHREAD_CLEANUP is not set +# CONFIG_CANCELLATION_POINTS is not set # # Performance Monitoring @@ -501,14 +521,14 @@ CONFIG_DEV_LOOP=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -653,6 +673,7 @@ CONFIG_SYSLOG_CONSOLE=y # CONFIG_DISABLE_MOUNTPOINT is not set # CONFIG_FS_AUTOMOUNTER is not set # CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_PSEUDOFS_SOFTLINKS is not set CONFIG_FS_READABLE=y CONFIG_FS_WRITABLE=y # CONFIG_FS_NAMED_SEMAPHORES is not set @@ -720,36 +741,98 @@ CONFIG_BUILTIN=y # # Standard C Library Options # + +# +# Standard C I/O +# +# CONFIG_STDIO_DISABLE_BUFFERING is not set CONFIG_STDIO_BUFFER_SIZE=64 CONFIG_STDIO_LINEBUFFER=y CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" -CONFIG_LIBM=y # CONFIG_NOPRINTF_FIELDWIDTH is not set # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y -# CONFIG_LIBC_IOCTL_VARIADIC is not set -CONFIG_LIB_RAND_ORDER=1 +# CONFIG_LIBC_SCANSET is not set # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set # CONFIG_EOL_IS_BOTH_CRLF is not set CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_MEMCPY_VIK is not set +CONFIG_LIBM=y + +# +# Architecture-Specific Support +# +CONFIG_ARCH_LOWPUTC=y +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_LIBC_ARCH_MEMCPY is not set +# CONFIG_LIBC_ARCH_MEMCMP is not set +# CONFIG_LIBC_ARCH_MEMMOVE is not set +# CONFIG_LIBC_ARCH_MEMSET is not set +# CONFIG_LIBC_ARCH_STRCHR is not set +# CONFIG_LIBC_ARCH_STRCMP is not set +# CONFIG_LIBC_ARCH_STRCPY is not set +# CONFIG_LIBC_ARCH_STRNCPY is not set +# CONFIG_LIBC_ARCH_STRLEN is not set +# CONFIG_LIBC_ARCH_STRNLEN is not set +# CONFIG_LIBC_ARCH_ELF is not set +# CONFIG_ARMV7M_MEMCPY is not set + +# +# stdlib Options +# +CONFIG_LIB_RAND_ORDER=1 +CONFIG_LIB_HOMEDIR="/" +CONFIG_LIBC_TMPDIR="/tmp" +CONFIG_LIBC_MAX_TMPFILE=32 + +# +# Program Execution Options +# # CONFIG_LIBC_EXECFUNCS is not set CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 + +# +# errno Decode Support +# # CONFIG_LIBC_STRERROR is not set # CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_LIBC_TMPDIR="/tmp" -CONFIG_LIBC_MAX_TMPFILE=32 -CONFIG_ARCH_LOWPUTC=y + +# +# memcpy/memset Options +# +# CONFIG_MEMSET_OPTSPEED is not set +# CONFIG_LIBC_DLLFCN is not set +# CONFIG_LIBC_MODLIB is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set + +# +# Time/Time Zone Support +# # CONFIG_LIBC_LOCALTIME is not set # CONFIG_TIME_EXTENDED is not set -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set CONFIG_ARCH_HAVE_TLS=y + +# +# Thread Local Storage (TLS) +# # CONFIG_TLS is not set + +# +# Network-Related Options +# +# CONFIG_LIBC_IPv4_ADDRCONV is not set +# CONFIG_LIBC_IPv6_ADDRCONV is not set # CONFIG_LIBC_NETDB is not set + +# +# NETDB Support +# # CONFIG_NETDB_HOSTFILE is not set +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Non-standard Library Support @@ -790,6 +873,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # CONFIG_EXAMPLES_ALARM is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -812,10 +896,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_NRF24L01TERM is not set CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set @@ -835,6 +919,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_SMART is not set # CONFIG_EXAMPLES_SMART_TEST is not set # CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_STAT is not set # CONFIG_EXAMPLES_TCPECHO is not set # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_THTTPD is not set @@ -963,6 +1048,7 @@ CONFIG_NSH_MMCSDMINOR=0 # Configure Command Options # # CONFIG_NSH_CMDOPT_DF_H is not set +# CONFIG_NSH_CMDOPT_DD_STATS is not set CONFIG_NSH_CODECS_BUFSIZE=128 # CONFIG_NSH_CMDOPT_HEXDUMP is not set CONFIG_NSH_PROC_MOUNTPOINT="/proc" diff --git a/configs/stm32l476-mdk/src/stm32_buttons.c b/configs/stm32l476-mdk/src/stm32_buttons.c index a59430ec82b..7dfc0469418 100644 --- a/configs/stm32l476-mdk/src/stm32_buttons.c +++ b/configs/stm32l476-mdk/src/stm32_buttons.c @@ -1,7 +1,7 @@ /**************************************************************************** * configs/stm32l476-mdk/src/stm32_buttons.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. * Author: dev@ziggurat29.com * * Redistribution and use in source and binary forms, with or without @@ -150,14 +150,14 @@ uint8_t board_buttons(void) ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { oldhandler = stm32l4_gpiosetevent(g_buttons[id], true, true, true, - irqhandler); + irqhandler, arg); } return oldhandler; diff --git a/configs/stm32l476vg-disco/nsh/defconfig b/configs/stm32l476vg-disco/nsh/defconfig index a55374381b5..c98f47a46cf 100644 --- a/configs/stm32l476vg-disco/nsh/defconfig +++ b/configs/stm32l476vg-disco/nsh/defconfig @@ -106,7 +106,9 @@ CONFIG_ARCH_CHIP_STM32L4=y # CONFIG_ARCH_ARM926EJS is not set # CONFIG_ARCH_ARM920T is not set # CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM23 is not set # CONFIG_ARCH_CORTEXM3 is not set +# CONFIG_ARCH_CORTEXM33 is not set CONFIG_ARCH_CORTEXM4=y # CONFIG_ARCH_CORTEXM7 is not set # CONFIG_ARCH_CORTEXA5 is not set @@ -161,6 +163,8 @@ CONFIG_ARMV7M_HAVE_STACKCHECK=y CONFIG_ARCH_CHIP_STM32L476RG=y # CONFIG_ARCH_CHIP_STM32L476RE is not set # CONFIG_ARCH_CHIP_STM32L486 is not set +# CONFIG_STM32L4_STM32L4X3 is not set +CONFIG_STM32L4_STM32L4X6=y CONFIG_STM32L4_STM32L476XX=y # CONFIG_STM32L4_STM32L486XX is not set # CONFIG_STM32L4_FLASH_256KB is not set @@ -181,6 +185,8 @@ CONFIG_STM32L4_FLASH_1024KB=y # STM32L4 Peripheral Support # # CONFIG_STM32L4_HAVE_LTDC is not set +CONFIG_STM32L4_HAVE_SAI1=y +CONFIG_STM32L4_HAVE_SAI2=y # CONFIG_STM32L4_ADC is not set # CONFIG_STM32L4_CAN is not set # CONFIG_STM32L4_DAC is not set @@ -208,6 +214,10 @@ CONFIG_STM32L4_DMA2=y # CONFIG_STM32L4_ADC3 is not set # CONFIG_STM32L4_AES is not set CONFIG_STM32L4_RNG=y +# CONFIG_STM32L4_SAI1_A is not set +# CONFIG_STM32L4_SAI1_B is not set +# CONFIG_STM32L4_SAI2_A is not set +# CONFIG_STM32L4_SAI2_B is not set # # AHB3 Peripherals @@ -294,6 +304,8 @@ CONFIG_STM32L4_SAI1PLL=y # # CONFIG_STM32L4_ONESHOT is not set # CONFIG_STM32L4_FREERUN is not set +CONFIG_STM32L4_HAVE_USART1=y +CONFIG_STM32L4_HAVE_USART2=y CONFIG_STM32L4_HAVE_USART3=y CONFIG_STM32L4_HAVE_UART4=y CONFIG_STM32L4_HAVE_UART5=y @@ -421,6 +433,7 @@ CONFIG_PREALLOC_TIMERS=4 # # Tasks and Scheduling # +# CONFIG_SPINLOCK is not set # CONFIG_INIT_NONE is not set CONFIG_INIT_ENTRYPOINT=y # CONFIG_INIT_FILEPATH is not set @@ -437,6 +450,8 @@ CONFIG_SCHED_WAITPID=y # # CONFIG_MUTEX_TYPES is not set CONFIG_NPTHREAD_KEYS=4 +# CONFIG_PTHREAD_CLEANUP is not set +# CONFIG_CANCELLATION_POINTS is not set # # Performance Monitoring @@ -706,6 +721,7 @@ CONFIG_SYSLOG_CONSOLE=y # CONFIG_DISABLE_MOUNTPOINT is not set # CONFIG_FS_AUTOMOUNTER is not set # CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_PSEUDOFS_SOFTLINKS is not set CONFIG_FS_READABLE=y CONFIG_FS_WRITABLE=y # CONFIG_FS_NAMED_SEMAPHORES is not set @@ -775,38 +791,98 @@ CONFIG_BUILTIN=y # # Standard C Library Options # + +# +# Standard C I/O +# +# CONFIG_STDIO_DISABLE_BUFFERING is not set CONFIG_STDIO_BUFFER_SIZE=64 CONFIG_STDIO_LINEBUFFER=y CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" -# CONFIG_LIBM is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y -# CONFIG_LIBC_IOCTL_VARIADIC is not set -# CONFIG_LIBC_WCHAR is not set -# CONFIG_LIBC_LOCALE is not set -CONFIG_LIB_RAND_ORDER=1 +# CONFIG_LIBC_SCANSET is not set # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set # CONFIG_EOL_IS_BOTH_CRLF is not set CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_MEMCPY_VIK is not set +# CONFIG_LIBM is not set + +# +# Architecture-Specific Support +# +CONFIG_ARCH_LOWPUTC=y +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_LIBC_ARCH_MEMCPY is not set +# CONFIG_LIBC_ARCH_MEMCMP is not set +# CONFIG_LIBC_ARCH_MEMMOVE is not set +# CONFIG_LIBC_ARCH_MEMSET is not set +# CONFIG_LIBC_ARCH_STRCHR is not set +# CONFIG_LIBC_ARCH_STRCMP is not set +# CONFIG_LIBC_ARCH_STRCPY is not set +# CONFIG_LIBC_ARCH_STRNCPY is not set +# CONFIG_LIBC_ARCH_STRLEN is not set +# CONFIG_LIBC_ARCH_STRNLEN is not set +# CONFIG_LIBC_ARCH_ELF is not set +# CONFIG_ARMV7M_MEMCPY is not set + +# +# stdlib Options +# +CONFIG_LIB_RAND_ORDER=1 +CONFIG_LIB_HOMEDIR="/" +CONFIG_LIBC_TMPDIR="/tmp" +CONFIG_LIBC_MAX_TMPFILE=32 + +# +# Program Execution Options +# # CONFIG_LIBC_EXECFUNCS is not set CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 + +# +# errno Decode Support +# # CONFIG_LIBC_STRERROR is not set # CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_LIBC_TMPDIR="/tmp" -CONFIG_LIBC_MAX_TMPFILE=32 -CONFIG_ARCH_LOWPUTC=y + +# +# memcpy/memset Options +# +# CONFIG_MEMSET_OPTSPEED is not set +# CONFIG_LIBC_DLLFCN is not set +# CONFIG_LIBC_MODLIB is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set + +# +# Time/Time Zone Support +# # CONFIG_LIBC_LOCALTIME is not set # CONFIG_TIME_EXTENDED is not set -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set CONFIG_ARCH_HAVE_TLS=y + +# +# Thread Local Storage (TLS) +# # CONFIG_TLS is not set + +# +# Network-Related Options +# +# CONFIG_LIBC_IPv4_ADDRCONV is not set +# CONFIG_LIBC_IPv6_ADDRCONV is not set # CONFIG_LIBC_NETDB is not set + +# +# NETDB Support +# # CONFIG_NETDB_HOSTFILE is not set +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Non-standard Library Support @@ -900,6 +976,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_SMART is not set # CONFIG_EXAMPLES_SMART_TEST is not set # CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_STAT is not set # CONFIG_EXAMPLES_TCPECHO is not set # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_THTTPD is not set @@ -1029,6 +1106,7 @@ CONFIG_NSH_MMCSDMINOR=0 # Configure Command Options # # CONFIG_NSH_CMDOPT_DF_H is not set +# CONFIG_NSH_CMDOPT_DD_STATS is not set CONFIG_NSH_CODECS_BUFSIZE=128 # CONFIG_NSH_CMDOPT_HEXDUMP is not set CONFIG_NSH_PROC_MOUNTPOINT="/proc" diff --git a/configs/stm32l476vg-disco/src/stm32_buttons.c b/configs/stm32l476vg-disco/src/stm32_buttons.c index b113718c9a1..7fc0c09d8a9 100644 --- a/configs/stm32l476vg-disco/src/stm32_buttons.c +++ b/configs/stm32l476vg-disco/src/stm32_buttons.c @@ -1,7 +1,7 @@ /**************************************************************************** * configs/stm32l476vg-disco/src/stm32_buttons.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. * Author: dev@ziggurat29.com * * Redistribution and use in source and binary forms, with or without @@ -176,7 +176,7 @@ static void button_pm_notify(struct pm_callback_s *cb, int domain, #if 0 #ifdef CONFIG_ARCH_IRQBUTTONS -static int button_handler(int irq, FAR void *context) +static int button_handler(int irq, FAR void *context, FAR void *arg) { #ifdef CONFIG_PM /* At this point the MCU should have already awakened. The state @@ -325,7 +325,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -333,7 +333,8 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - oldhandler = stm32l4_gpiosetevent(g_buttons[id], true, true, true, irqhandler); + oldhandler = stm32l4_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); } return oldhandler; diff --git a/configs/stm32l476vg-disco/src/stm32_usb.c b/configs/stm32l476vg-disco/src/stm32_usb.c index de9f08c4eeb..0b08a9264d2 100644 --- a/configs/stm32l476vg-disco/src/stm32_usb.c +++ b/configs/stm32l476vg-disco/src/stm32_usb.c @@ -311,7 +311,7 @@ void stm32l4_usbhost_vbusdrive(int iface, bool enable) #ifdef CONFIG_USBHOST xcpt_t stm32l4_setup_overcurrent(xcpt_t handler) { - return stm32l4_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler); + return stm32l4_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); } #endif diff --git a/configs/stm32ldiscovery/src/stm32_buttons.c b/configs/stm32ldiscovery/src/stm32_buttons.c index 5427ac751b1..b703bf8d2de 100644 --- a/configs/stm32ldiscovery/src/stm32_buttons.c +++ b/configs/stm32ldiscovery/src/stm32_buttons.c @@ -152,7 +152,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -160,7 +160,8 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); } return oldhandler; diff --git a/configs/stm32vldiscovery/src/stm32_buttons.c b/configs/stm32vldiscovery/src/stm32_buttons.c index 87442c115e1..63be9ee2a17 100644 --- a/configs/stm32vldiscovery/src/stm32_buttons.c +++ b/configs/stm32vldiscovery/src/stm32_buttons.c @@ -107,12 +107,14 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; if (id == 0) - oldhandler = stm32_gpiosetevent(GPIO_BTN_0, true, true, true, irqhandler); + { + oldhandler = stm32_gpiosetevent(GPIO_BTN_0, true, true, true, irqhandler, arg); + } return oldhandler; } diff --git a/configs/sure-pic32mx/src/pic32mx_buttons.c b/configs/sure-pic32mx/src/pic32mx_buttons.c index 62e0330c410..8de2633e2f6 100644 --- a/configs/sure-pic32mx/src/pic32mx_buttons.c +++ b/configs/sure-pic32mx/src/pic32mx_buttons.c @@ -206,7 +206,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; diff --git a/configs/teensy-3.x/include/board.h b/configs/teensy-3.x/include/board.h index b67fe21b6c6..508d5a811dc 100644 --- a/configs/teensy-3.x/include/board.h +++ b/configs/teensy-3.x/include/board.h @@ -74,10 +74,10 @@ * is 72MHz and 50MHz for the MK20DX128VLH5, but according to the PJRC website, * both can be overclocked at 96MHz * - * MK20DX128VLH5 Rated Frequency 50MHz + * MK20DX128VLH5 Rated Frequency 50MHz (selecting 48Mhz to use USB) * * PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/8 = 2MHz - * PLL Output frequency: PLLOUT = PLLIN*VDIV = 2Mhz*25 = 50MHz + * PLL Output frequency: PLLOUT = PLLIN*VDIV = 2Mhz*24 = 48MHz * MCG Frequency: PLLOUT = 48MHz * * MK20DX256VLH7 Rated Frequency 72MHz @@ -102,7 +102,7 @@ # define BOARD_OUTDIV1 1 /* Core = MCG, 96MHz */ # define BOARD_OUTDIV2 2 /* Bus = MCG/2, 48MHz */ -# define BOARD_OUTDIV3 2 /* FlexBus = MCG/2, 48MHz */ +# define BOARD_OUTDIV3 0 /* N/A = No OUTDIV3 */ # define BOARD_OUTDIV4 4 /* Flash clock = MCG/4, 24MHz */ #elif defined(CONFIG_ARCH_CHIP_MK20DX256VLH7) @@ -116,21 +116,21 @@ # define BOARD_OUTDIV1 1 /* Core = MCG, 72MHz */ # define BOARD_OUTDIV2 2 /* Bus = MCG/2, 36MHz */ -# define BOARD_OUTDIV3 2 /* FlexBus = MCG/2, 36MHz */ +# define BOARD_OUTDIV3 0 /* N/A = No OUTDIV3 */ # define BOARD_OUTDIV4 3 /* Flash clock = MCG/3, 72MHz */ #elif defined(CONFIG_ARCH_CHIP_MK20DX128VLH5) /* PLL Configuration */ # define BOARD_PRDIV 8 /* PLL External Reference Divider */ -# define BOARD_VDIV 25 /* PLL VCO Divider (frequency multiplier) */ +# define BOARD_VDIV 24 /* PLL VCO Divider (frequency multiplier) */ /* SIM CLKDIV1 dividers */ -# define BOARD_OUTDIV1 1 /* Core = MCG, 50MHz */ -# define BOARD_OUTDIV2 1 /* Bus = MCG/1, 50MHz */ -# define BOARD_OUTDIV3 1 /* FlexBus = MCG/1, 20MHz */ -# define BOARD_OUTDIV4 2 /* Flash clock = MCG/2, 25MHz */ +# define BOARD_OUTDIV1 1 /* Core = MCG, 48MHz */ +# define BOARD_OUTDIV2 1 /* Bus = MCG/1, 48MHz */ +# define BOARD_OUTDIV3 0 /* N/A = No OUTDIV3 */ +# define BOARD_OUTDIV4 2 /* Flash clock = MCG/2, 24MHz */ #endif #define BOARD_PLLIN_FREQ (BOARD_EXTAL_FREQ / BOARD_PRDIV) @@ -142,6 +142,44 @@ #define BOARD_FLEXBUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV3) #define BOARD_FLASHCLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV4) +/* Use MCGPLLCLK as the output SIM_SOPT2 MUX selected by + * SIM_SOPT2[PLLFLLSEL] + */ + +#define BOARD_SOPT2_PLLFLLSEL SIM_SOPT2_PLLFLLSEL_MCGPLLCLK +#define BOARD_SOPT2_FREQ BOARD_MCG_FREQ + + /* Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ] + * SIM_CLKDIV2_FREQ = BOARD_SOPT2_FREQ × [ (USBFRAC+1) / (USBDIV+1) ] + */ + +#if BOARD_SOPT2_FREQ == 96000000 + /* USBFRAC/USBDIV = 1/2 of 96Mhz clock = 48MHz */ + +# define BOARD_SIM_CLKDIV2_USBFRAC 1 +# define BOARD_SIM_CLKDIV2_USBDIV 2 +#elif BOARD_SOPT2_FREQ == 72000000 + /* USBFRAC/USBDIV = 2/3 of 72Mhz clock = 48MHz */ + +# define BOARD_SIM_CLKDIV2_USBFRAC 2 +# define BOARD_SIM_CLKDIV2_USBDIV 3 +#elif BOARD_SOPT2_FREQ == 48000000 + /* USBFRAC/USBDIV = 1/1 of 48Mhz clock = 48MHz */ + +# define BOARD_SIM_CLKDIV2_USBFRAC 1 +# define BOARD_SIM_CLKDIV2_USBDIV 1 +#endif + +#define BOARD_SIM_CLKDIV2_FREQ (BOARD_SOPT2_FREQ / \ + BOARD_SIM_CLKDIV2_USBDIV * \ + BOARD_SIM_CLKDIV2_USBFRAC) + +/* Use the output of SIM_SOPT2[PLLFLLSEL] as the USB clock source */ + +#define BOARD_USB_CLKSRC SIM_SOPT2_USBSRC +#define BOARD_USB_FREQ BOARD_SIM_CLKDIV2_FREQ + + /* PWM Configuration */ /* FTM0 Channels */ diff --git a/configs/teensy-3.x/src/k20_usbdev.c b/configs/teensy-3.x/src/k20_usbdev.c index 2cf0d9d2e00..f5f20fbf246 100644 --- a/configs/teensy-3.x/src/k20_usbdev.c +++ b/configs/teensy-3.x/src/k20_usbdev.c @@ -59,7 +59,6 @@ #define khci_getreg(addr) getreg8(addr) #define khci_putreg(val,addr) putreg8(val,addr) -#define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1) /************************************************************************************ * Public Functions diff --git a/configs/tm4c123g-launchpad/src/tm4c_buttons.c b/configs/tm4c123g-launchpad/src/tm4c_buttons.c index 57c285ea60b..a151bce0caf 100644 --- a/configs/tm4c123g-launchpad/src/tm4c_buttons.c +++ b/configs/tm4c123g-launchpad/src/tm4c_buttons.c @@ -149,7 +149,7 @@ uint8_t board_buttons(void) ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; uint32_t pinset= 0; diff --git a/configs/twr-k60n512/src/k60_appinit.c b/configs/twr-k60n512/src/k60_appinit.c index fde0ef30139..dcf7183d0bc 100644 --- a/configs/twr-k60n512/src/k60_appinit.c +++ b/configs/twr-k60n512/src/k60_appinit.c @@ -224,7 +224,7 @@ int board_app_initialize(uintptr_t arg) /* Attached the card detect interrupt (but don't enable it yet) */ kinetis_pinconfig(GPIO_SD_CARDDETECT); - kinetis_pinirqattach(GPIO_SD_CARDDETECT, kinetis_cdinterrupt); + kinetis_pinirqattach(GPIO_SD_CARDDETECT, kinetis_cdinterrupt, NULL); /* Configure the write protect GPIO */ diff --git a/configs/twr-k60n512/src/k60_buttons.c b/configs/twr-k60n512/src/k60_buttons.c index 0cda4324838..6a936935da1 100644 --- a/configs/twr-k60n512/src/k60_buttons.c +++ b/configs/twr-k60n512/src/k60_buttons.c @@ -134,7 +134,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler; uint32_t pinset; diff --git a/configs/twr-k64f120m/Kconfig b/configs/twr-k64f120m/Kconfig new file mode 100644 index 00000000000..4131b4feac4 --- /dev/null +++ b/configs/twr-k64f120m/Kconfig @@ -0,0 +1,36 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_TWR_K64F120M + +config TWR_K64F120M_SDHC_AUTOMOUNT + bool "SDHC automounter" + default n + depends on FS_AUTOMOUNTER && KINETIS_SDHC + +if TWR_K64F120M_SDHC_AUTOMOUNT + +config TWR_K64F120M_SDHC_AUTOMOUNT_FSTYPE + string "SDHC file system type" + default "vfat" + +config TWR_K64F120M_SDHC_AUTOMOUNT_BLKDEV + string "SDHC block device" + default "/dev/mmcsd0" + +config TWR_K64F120M_SDHC_AUTOMOUNT_MOUNTPOINT + string "SDHC mount point" + default "/mnt/sdcard" + +config TWR_K64F120M_SDHC_AUTOMOUNT_DDELAY + int "SDHC debounce delay (milliseconds)" + default 1000 + +config TWR_K64F120M_SDHC_AUTOMOUNT_UDELAY + int "SDHC unmount retry delay (milliseconds)" + default 2000 + +endif # TWR_K64F120M_SDHC_AUTOMOUNT +endif # ARCH_BOARD_TWR_K64F120M diff --git a/configs/twr-k64f120m/README.txt b/configs/twr-k64f120m/README.txt new file mode 100644 index 00000000000..cbb5a88b8d3 --- /dev/null +++ b/configs/twr-k64f120m/README.txt @@ -0,0 +1,821 @@ +README.txt +========== + +This is the README file for the port of NuttX to the Freescale Kinetis +TWR-K64F120M. Refer to the Freescale web site for further information +about this part: + +www.nxp.com/products/sensors/accelerometers/3-axis-accelerometers/kinetis-k64-mcu-tower-system-module:TWR-K64F120M + +The board may be complemented by TWR-SER which includes (among other things), an RS232 and Ethernet connections: + +http://www.nxp.com/pages/serial-usb-ethernet-can-rs232-485-tower-system-module:TWR-SER + +Contents +======== + + o Kinetis TWR-K64F120M Features + o Kinetis TWR-K64F120M Pin Configuration + - On-Board Connections + - Connections via the General Purpose Tower Plug-in (TWRPI) Socket + - Connections via the Tower Primary Connector Side A + - Connections via the Tower Primary Connector Side B + - TWR-SER Serial Board Connection + o LEDs + o Development Environment + o GNU Toolchain Options + o IDEs + o NuttX EABI "buildroot" Toolchain + o NuttX OABI "buildroot" Toolchain + o NXFLAT Toolchain + +Kinetis TWR-K64F120M Features: +============================= + + o K64N1M in 144 MAPBGA, MK64FN1M0VMD12 + o Integrated, Open-SDA serial, flash and debug through USB + o SD Card Slot + o MMA7660 3-axis accelerometer + o Tower Plug-In (TWRPI) Socket for expansion (sensors, etc.) + o Touch TWRPI Socket adds support for various capacitive touch boards + (e.g. keypads, rotary dials, sliders, etc.) + o Tower connectivity for access to USB, Ethernet, RS232/RS485, CAN, SPI, + I²C, Flexbus, etc. + o Plus: Potentiometer, 4 LEDs, 2 pushbuttons, accelerometer, RTC battery + +Kinetis TWR-K64F120M Pin Configuration +====================================== + +On-Board Connections +-------------------- ------------------------- -------- ------------------- +FEATURE CONNECTION PORT/PIN PIN FUNCTION +-------------------- ------------------------- -------- ------------------- +OSJTAG USB-to-serial OSJTAG Bridge RX Data PTC3 UART1_RX +Bridge OSJTAG Bridge TX Data PTC4 UART1_TX +SD Card Slot SD Clock PTE2 SDHC0_DCLK + SD Command PTE3 SDHC0_CMD + SD Data0 PTE1 SDHC0_D0 + SD Data1 PTE0 SDHC0_D1 + SD Data2 PTE5 SDHC0_D2 + SD Data3 PTE4 SDHC0_D3 + SD Card Detect PTB20 PTB20 + SD Write Protect PTB21 PTB21 +Micro-USB K64_MICRO_USB_DN USB0_DN + K64_MICRO_USB_DP USB0_DP + K64_USB_ID_J PTE12 + K64_USB_FLGA PTC8 + K64_USB_ENABLE PTC9 +Pushbuttons SW1 (LLWU_P10) PTC6 PTC6 + SW2 (RSTIN_B_R) RSTIN RESET + SW3 (NMI B) PTA4 PTA4 +LEDs D5 / Green LED PTE6 PTE6 + D6 / Yellow LED PTE7 PTE7 + D7 / Orange LED PTE8 PTE8 + D9 / Blue LED PTE9 PTE9 +Potentiometer Potentiometer (R526) ? ADC1_SE18 +Accelerometer I2C SDA PTC11 I2C1_SDA + I2C SCL PTC10 I2C1_SCL + INT1 PTA6 PTA6 + INT2 PTA8 PTA8 + +SDHC important notice: on TWR-K64F120M, R521 (close to the SD card holder) is not placed, +hence WRPROTEC is always ON. Either place a 4.7KOhm resistor or change PIN config +to PULLDOWN, loosing Write Protect function. See twrk64.h. + +Connections via the General Purpose Tower Plug-in (TWRPI) Socket +-------------------- ------------------------- -------- ------------------- +FEATURE CONNECTION PORT/PIN PIN FUNCTION +-------------------- ------------------------- -------- ------------------- +General Purpose TWRPI ADC0 (J4 Pin 8) ? ADC1_SE16/ADC0_SE22 +TWRPI Socket TWRPI_ADC1 (J4 Pin 9) ? ADC0_SE16/ADC0_SE21 + TWRPI_ADC2 (J4 Pin 12) ? ADC1_DP0/ADC0_DP3 + TWRPI_ID0 (J4 Pin 17) ? ADC0_DP0/AD1_DP3 + TWRPI_ID1 (J4 Pin 18) ? ADC0_DM0/ADC1_DM3 + TWRPI I2C SCL (J3 Pin 3) PTC10 I2C1_SCL + TWRPI I2C SDA (J3 Pin 4) PTC11 I2C1_SDA + SPI1_SOUT (J3 Pin 10) PTB16 ? + SPI1_PCS0 (J3 Pin 11) PTB10 PTB10 + SPI1_SCK (J3 Pin 12) PTB11 ? + TWRPI_GPIO0 (J3 Pin 15) PTB3 PTB3 + TWRPI GPIO1 (J3 Pin 16) PTC0 PTC0 + TWRPI GPIO2 (J3 Pin 17) PTC16 PTC16 + TWRPI GPIO3 (J3 Pin 18) PTC17 PTC17 + TWRPI GPIO4 (J3 Pin 19) PTC18 PTC18 + TWRPI GPIO5 (J3 Pin 20) PTC19 PTC19 + +The TWR-K64F120M features two expansion card-edge connectors that interface +to the Primary and Secondary Elevator boards in a Tower system. The Primary +Connector (comprised of sides A and B) is identified by a white strip. +The Secondary Connector is comprised of sides C and D. + + +TWR-SER Serial Board Connection +=============================== + +The serial board connects into the tower and then maps to the tower pins to +yet other functions (see TWR-SER-SCH.pdf). + +In particular it features an Ethernet port. + +Networking Support +================== + + U2 is a 25 MHz oscillator (which may be disabled by setting J4), which clock is sent to U1. + U1 has two clock output banks: 25MHz (CLKBx) and 50MHz (CLKAx). + J2 (ser board) is used to select the PHY clock source: 50MHz, 25MHz or CLCKOUT0 from K64. Set it to 25MHz. + In order to keep synchornized the PHY clock with the K64 clock, one can set J3 (default is open) + to route CLOCKIN0 either from 25MHz or 50Mhz lines. In that case, J33 (main board) will have to be removed + and J32 (main board set) set to disable its 50MHz_OSC and use CLKIN0 provided by ser board. + J12 is by default set to RMII mode. In this case J2 should be placed to 50MHz clock + Note that in MII mode, MII0_TXER is required by kinetis driver, but not connected on ser board + + Ethernet MAC/KSZ8041NL PHY + -------------------------- + ------------ ---------------------------------------------------------- ------------------------------ ------------------------------- + KSZ8041 TWR Board Signal(s) K64F Pin Pin name + Pin Signal Function MII RMII + --- -------- ---------------------------------------------------------- ------------------------------ ------------------------------- + 9 REFCLK CLK_SEL J2: CLOCKOUT0/25MHz/50MHz, PHY clock input PTC3/CLKOUT --- direct to PHY + 11 MDIO FEC_MDIO PTB0/RMII0_MDIO/MII0_MDIO PIN_MII0_MDIO PIN_RMII0_MDIO + 12 MDC FEC_MDC PTB1/RMII0_MDC/MII0_MDC PIN_MII0_MDC PIN_RMII0_MDC + 13 PHYAD0 FEC_RXD3 J12: PHY Adress select (pull-down if set) PTA9/MII0_RXD3 PIN_RMII0_RXD3 --- + 14 PHYAD1 FEC_RXD2 J12: PHY Adress select (pull-up if set) PTA10/MII0_RXD2 PIN_RMII0_RXD2 --- + 15 PHYAD2 FEC_RXD1 J12: PHY Adress select (pull-up if set) PTA12/RMII0_RXD1/MII0_RXD1 PIN_MII0_RXD1 PIN_RMII0_RXD1 + 16 DUPLEX FEC_RXD0 J12: Half-duplex (pull-down if set) PTA13/RMII0_RXD0/MII0_RXD0 PIN_MII0_RXD0 PIN_RMII0_RXD0 + 18 CONFIG2 FEC_RXDV J12: Loopback select (pull-up if set) PTA14/RMII0_CRS_DV/MII0_RXDV PIN_MII0_RXDV PIN_RMII0_CRS_DV + 19 RXC FEC_RXCLK PTA11/MII0_RXCLK PIN_MII0_RXCLK --- + 20 ISO FEC_RXER J12: Isolation mode select (pull-up if set) PTA5/RMII0_RXER/MII0_RXER PIN_MII_RXER PIN_RMII_RXER + 22 TXC FEC_TXCLK PTA25/MII0_TXCLK PIN_MII0_TXCLK --- + 23 TXEN FEC_TXEN PTA15/RMII0_TXEN/MII0_TXEN PIN_MII0_TXEN PIN_RMII0_TXEN + 24 TXD0 FEC_TXD0 PTA16/RMII0_TXD0/MII0_TXD0 PIN_MII0_TXD0 PIN_RMII0_TXD0 + 25 TXD1 FEC_TXD1 PTA17/RMII0_TXD1/MII0_TXD1 PIN_MII0_TXD1 PIN_RMII0_TXD1 + 26 TXD2 FEC_TXD2 PTA24/MII0_TXD2 PIN_MII0_TXD2 --- + 27 TXD3 FEC_TXD3 PTA26/MII0_TXD3 PIN_MII0_TXD3 --- + 28 CONFIG0 FEC_COL J12: RMII select (pull-up if set) PTA29/MII0_COL PIN_MII0_COL --- + 29 CONFIG1 FEC_CRS PTA27/MII0_CRS PIN_MII0_CRS --- + 30 LED0 LED0/NWAYEN J12: Disable auto_negotiation (pull-down if s --- --- + 31 LED1 LED1/SPEED J12: 10Mbps select (pull-down if set) --- --- + --- -------- ----------------- ---------------------------------------- ------------------------------ ------------------------------- + + Networking support can be added to NSH by selecting the following + configuration options. + + Selecting the MAC peripheral + ---------------------------- + + System Type -> Kinetis Peripheral Support + CONFIG_KINETIS_ENET=y : Enable the Ethernet MAC peripheral + + System Type -> Ethernet Configuration + CONFIG_KINETIS_ENETNETHIFS=1 + CONFIG_KINETIS_ENETNRXBUFFERS=6 + CONFIG_KINETIS_ENETNTXBUFFERS=2 + CONFIG_KINETIS_ENET_MDIOPULLUP=y + + Networking Support + CONFIG_NET=y : Enable Neworking + CONFIG_NET_ETHERNET=y : Support Ethernet data link + CONFIG_NET_SOCKOPTS=y : Enable socket operations + CONFIG_NET_ETH_MTU=590 : Maximum packet size (MTU) 1518 is more standard + CONFIG_NET_ETH_TCP_RECVWNDO=536 : Should be the same as CONFIG_NET_ETH_MTU + CONFIG_NET_ARP=y : Enable ARP + CONFIG_NET_ARPTAB_SIZE=16 : ARP table size + CONFIG_NET_ARP_IPIN=y : Enable ARP address harvesting + CONFIG_NET_ARP_SEND=y : Send ARP request before sending data + CONFIG_NET_TCP=y : Enable TCP/IP networking + CONFIG_NET_TCP_READAHEAD=y : Support TCP read-ahead + CONFIG_NET_TCP_WRITE_BUFFERS=y : Support TCP write-buffering + CONFIG_NET_TCPBACKLOG=y : Support TCP/IP backlog + CONFIG_NET_MAX_LISTENPORTS=20 : + CONFIG_NET_TCP_READAHEAD_BUFSIZE=536 Read-ahead buffer size + CONFIG_NET_UDP=y : Enable UDP networking + CONFIG_NET_BROADCAST=y : Needed for DNS name resolution + CONFIG_NET_ICMP=y : Enable ICMP networking + CONFIG_NET_ICMP_PING=y : Needed for NSH ping command + : Defaults should be okay for other options + Application Configuration -> Network Utilities + CONFIG_NETDB_DNSCLIENT=y : Enable host address resolution + CONFIG_NETUTILS_TELNETD=y : Enable the Telnet daemon + CONFIG_NETUTILS_TFTPC=y : Enable TFTP data file transfers for get and put commands + CONFIG_NETUTILS_NETLIB=y : Network library support is needed + CONFIG_NETUTILS_WEBCLIENT=y : Needed for wget support + : Defaults should be okay for other options + Application Configuration -> NSH Library + CONFIG_NSH_TELNET=y : Enable NSH session via Telnet + CONFIG_NSH_IPADDR=0xc0a800e9 : Select a fixed IP address + CONFIG_NSH_DRIPADDR=0xc0a800fe : IP address of gateway/host PC + CONFIG_NSH_NETMASK=0xffffff00 : Netmask + CONFIG_NSH_NOMAC=y : Need to make up a bogus MAC address + : Defaults should be okay for other options + + You can also enable enable the DHCPC client for networks that use + dynamically assigned address: + + Application Configuration -> Network Utilities + CONFIG_NETUTILS_DHCPC=y : Enables the DHCP client + + Networking Support + CONFIG_NET_UDP=y : Depends on broadcast UDP + + Application Configuration -> NSH Library + CONFIG_NET_BROADCAST=y + CONFIG_NSH_DHCPC=y : Tells NSH to use DHCPC, not + : the fixed addresses + + Using the network with NSH + -------------------------- + + So what can you do with this networking support? First you see that + NSH has several new network related commands: + + ifconfig, ifdown, ifup: Commands to help manage your network + get and put: TFTP file transfers + wget: HTML file transfers + ping: Check for access to peers on the network + Telnet console: You can access the NSH remotely via telnet. + + You can also enable other add on features like full FTP or a Web + Server or XML RPC and others. There are also other features that + you can enable like DHCP client (or server) or network name + resolution. + + By default, the IP address of the DK-TM4C129X will be 192.168.0.233 and + it will assume that your host is the gateway and has the IP address + 192.168.0.254. + + nsh> ifconfig + eth0 Link encap:Ethernet HWaddr 16:03:60:0f:00:33 at UP + inet addr:192.168.0.233 DRaddr:192.168.0.254 Mask:255.255.255. + + You can use ping to test for connectivity to the host (Careful, + Window firewalls usually block ping-related ICMP traffic). + + On the host PC side, you may be able to ping the TWR-K64F120M: + + $ ping 192.168.0.233 + PING 192.168.0.233 (192.168.0.233) 56(84) bytes of data. + 64 bytes from 192.168.0.233: icmp_seq=1 ttl=64 time=7.82 ms + 64 bytes from 192.168.0.233: icmp_seq=2 ttl=64 time=4.50 ms + 64 bytes from 192.168.0.233: icmp_seq=3 ttl=64 time=2.04 ms + ^C + --- 192.168.0.233 ping statistics --- + 3 packets transmitted, 3 received, 0% packet loss, time 2003ms + rtt min/avg/max/mdev = 2.040/4.789/7.822/2.369 ms + + + From the target side, you may should also be able to ping the host + (assuming it's IP is 192.168.0.1): + + nsh> ping 192.168.0.1 + PING 192.168.0.1 56 bytes of data + 56 bytes from 192.168.0.1: icmp_seq=1 time=0 ms + 56 bytes from 192.168.0.1: icmp_seq=2 time=0 ms + 56 bytes from 192.168.0.1: icmp_seq=3 time=0 ms + 56 bytes from 192.168.0.1: icmp_seq=4 time=0 ms + 56 bytes from 192.168.0.1: icmp_seq=5 time=0 ms + 56 bytes from 192.168.0.1: icmp_seq=6 time=0 ms + 56 bytes from 192.168.0.1: icmp_seq=7 time=0 ms + 56 bytes from 192.168.0.1: icmp_seq=8 time=0 ms + 56 bytes from 192.168.0.1: icmp_seq=9 time=0 ms + 56 bytes from 192.168.0.1: icmp_seq=10 time=0 ms + 10 packets transmitted, 10 received, 0% packet loss, time 10100 ms + nsh> + + You can also log into the NSH from the host PC like this: + + $ telnet 192.168.0.233 + Trying 192.168.0.233... + Connected to 192.168.0.233. + Escape character is '^]'. + + NuttShell (NSH) + nsh> + + NOTE: If you enable this networking as described above, you will + experience a delay on booting NSH. That is because the start-up logic + waits for the network connection to be established before starting + NuttX. In a real application, you would probably want to do the + network bringup on a separate thread so that access to the NSH prompt + is not delayed. + + The kinetis_enet.c driver, does not wait too long for PHY to negotiate + the link speed. In this case it folds back to 10Mbs half-duplex + mode. This behaviour should be improved in order to cope with the + plug and play nature of this port. + + Reconfiguring after the network becomes available requires the + network monitor feature, also discussed below. + + Network Initialization Thread + ----------------------------- + [not tested on K64F120M] + There is a configuration option enabled by CONFIG_NSH_NETINIT_THREAD + that will do the NSH network bring-up asynchronously in parallel on + a separate thread. This eliminates the (visible) networking delay + altogether. This current implementation, however, has some limitations: + + - If no network is connected, the network bring-up will fail and + the network initialization thread will simply exit. There are no + retries and no mechanism to know if the network initialization was + successful (it could perform a network Ioctl to see if the link is + up and it now, keep trying, but it does not do that now). + + - Furthermore, there is currently no support for detecting loss of + network connection and recovery of the connection (similarly, this + thread could poll periodically for network status, but does not). + + Both of these shortcomings could be eliminated by enabling the network + monitor: + + Network Monitor + --------------- + By default the network initialization thread will bring-up the network + then exit, freeing all of the resources that it required. This is a + good behavior for systems with limited memory. + + If the CONFIG_NSH_NETINIT_MONITOR option is selected, however, then the + network initialization thread will persist forever; it will monitor the + network status. In the event that the network goes down (for example, if + a cable is removed), then the thread will monitor the link status and + attempt to bring the network back up. In this case the resources + required for network initialization are never released. + + Pre-requisites: + + - CONFIG_NSH_NETINIT_THREAD as described above. + + - The K64F EMAC block does not support PHY interrupts. The KSZ8081 + PHY interrupt line is brought to a jumper block and it should be + possible to connect that some some interrupt port pin. You would + need to provide some custom logic in the Freedcom K64F + configuration to set up that PHY interrupt. + + - In addtion to the PHY interrupt, the Network Monitor also requires the + following setting: + + CONFIG_NETDEV_PHY_IOCTL. Enable PHY IOCTL commands in the Ethernet + device driver. Special IOCTL commands must be provided by the Ethernet + driver to support certain PHY operations that will be needed for link + management. There operations are not complex and are implemented for + the Atmel SAMA5 family. + + CONFIG_ARCH_PHY_INTERRUPT. This is not a user selectable option. + Rather, it is set when you select a board that supports PHY + interrupts. For the K64F, like most other architectures, the PHY + interrupt must be provided via some board-specific GPIO. In any + event, the board-specific logic must provide support for the PHY + interrupt. To do this, the board logic must do two things: (1) It + must provide the function arch_phy_irq() as described and prototyped + in the nuttx/include/nuttx/arch.h, and (2) it must select + CONFIG_ARCH_PHY_INTERRUPT in the board configuration file to + advertise that it supports arch_phy_irq(). + + And a few other things: UDP support is required (CONFIG_NET_UDP) and + signals must not be disabled (CONFIG_DISABLE_SIGNALS). + + Given those prerequisites, the network monitor can be selected with these + additional settings. + + System Type -> Kinetis Ethernet Configuration + CONFIG_ARCH_PHY_INTERRUPT=y : (auto-selected) + CONFIG_NETDEV_PHY_IOCTL=y : (auto-selected) + + Application Configuration -> NSH Library -> Networking Configuration + CONFIG_NSH_NETINIT_THREAD : Enable the network initialization thread + CONFIG_NSH_NETINIT_MONITOR=y : Enable the network monitor + CONFIG_NSH_NETINIT_RETRYMSEC=2000 : Configure the network monitor as you like + CONFIG_NSH_NETINIT_SIGNO=18 + + +LEDs +==== + +The TWR-K64F120M board has four LEDs labeled D5, D6, D7, D9 on the board. Usage of +these LEDs is defined in include/board.h and src/up_leds.c. They are encoded +as follows: + + SYMBOL Meaning LED1* LED2 LED3 LED4 + ------------------- ----------------------- ------- ------- ------- ------ + LED_STARTED NuttX has been started OFF OFF OFF N/A + LED_HEAPALLOCATE Heap has been allocated OFF OFF OFF N/A + LED_IRQSENABLED Interrupts enabled OFF OFF OFF N/A + LED_STACKCREATED Idle stack created ON OFF OFF N/A + LED_INIRQ In an interrupt** N/C ON N/C N/A + LED_SIGNAL In a signal handler*** N/C N/C ON N/A + LED_ASSERTION An assertion failed ON ON ON N/A + LED_PANIC The system has crashed Blink N/C N/C N/A + LED_IDLE K64 is is sleep mode (Optional, not used) + + * If LED1, LED2, LED3 are statically on, then NuttX probably failed to boot + and these LEDs will give you some indication of where the failure was + ** The normal state is LED1 ON and LED2 faintly glowing. This faint glow + is because of timer interrupts and signal that result in the LED being + illuminated on a small proportion of the time. +*** LED3 may even glow faintlier then LED2 while signals are processed. + +Development Environment +======================= + + Either Linux or Cygwin on Windows can be used for the development environment. + The source has been built only using the GNU toolchain (see below). Other + toolchains will likely cause problems. Testing was performed using the Linux + environment. + +GNU Toolchain Options +===================== + + The NuttX make system has been modified to support the following different + toolchain options. + + 1. The CodeSourcery GNU toolchain, + 2. The devkitARM GNU toolchain, + 3. The NuttX buildroot Toolchain (see below). + + All testing has been conducted using the CodeSourcery Windows toolchain. To + use the devkitARM or the NuttX GNU toolchain, you simply need to change the + the following configuration options to your .config (or defconfig) file: + + CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows + CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux + CONFIG_ARMV7M_TOOLCHAIN_IARL=y : IAR + CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows + CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin + CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y : GCC (default) + + If you are not using CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT, then you may also have to modify + the PATH in the setenv.h file if your make cannot find the tools. + + NOTE: the CodeSourcery (for Windows) and devkitARM toolchains are + Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot + toolchains are Cygwin and/or Linux native toolchains. There are several limitations + to using a Windows based toolchain in a Cygwin environment. The three biggest are: + + 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are + performed automatically in the Cygwin makefiles using the 'cygpath' utility + but you might easily find some new path problems. If so, check out 'cygpath -w' + + 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links + are used in Nuttx (e.g., include/arch). The make system works around these + problems for the Windows tools by copying directories instead of linking them. + But this can also cause some confusion for you: For example, you may edit + a file in a "linked" directory and find that your changes had no effect. + That is because you are building the copy of the file in the "fake" symbolic + directory. If you use a Windows toolchain, you should get in the habit of + making like this: + + make clean_context all + + An alias in your .bashrc file might make that less painful. + + NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization + level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with + -Os. + + NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that + the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM + path or will get the wrong version of make. + +IDEs +==== + + NuttX is built using command-line make. It can be used with an IDE, but some + effort will be required to create the project. + + Makefile Build + -------------- + Under Eclipse, it is pretty easy to set up an "empty makefile project" and + simply use the NuttX makefile to build the system. That is almost for free + under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty + makefile project in order to work with Windows (Google for "Eclipse Cygwin" - + there is a lot of help on the internet). + + Native Build + ------------ + Here are a few tips before you start that effort: + + 1) Select the toolchain that you will be using in your .config file + 2) Start the NuttX build at least one time from the Cygwin command line + before trying to create your project. This is necessary to create + certain auto-generated files and directories that will be needed. + 3) Set up include pathes: You will need include/, arch/arm/src/k40, + arch/arm/src/common, arch/arm/src/armv7-m, and sched/. + 4) All assembly files need to have the definition option -D __ASSEMBLY__ + on the command line. + + Startup files will probably cause you some headaches. The NuttX startup file + is arch/arm/src/kinetis/k40_vectors.S. + +NuttX EABI "buildroot" Toolchain +================================ + + A GNU GCC-based toolchain is assumed. The files */setenv.sh should + be modified to point to the correct path to the Cortex-M4 GCC toolchain (if + different from the default in your PATH variable). + + If you have no Cortex-M4 toolchain, one can be downloaded from the NuttX + Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). + This GNU toolchain builds and executes in the Linux or Cygwin environment. + + NOTE: The NuttX toolchain may not include optimizations for Cortex-M4 (ARMv7E-M). + + 1. You must have already configured Nuttx in /nuttx. + + cd tools + ./configure.sh twr-k64f120m/ + + 2. Download the latest buildroot package into + + 3. unpack the buildroot tarball. The resulting directory may + have versioning information on it like buildroot-x.y.z. If so, + rename /buildroot-x.y.z to /buildroot. + + 4. cd /buildroot + + 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config + + 6. make oldconfig + + 7. make + + 8. Edit setenv.h, if necessary, so that the PATH variable includes + the path to the newly built binaries. + + See the file configs/README.txt in the buildroot source tree. That has more + details PLUS some special instructions that you will need to follow if you are + building a Cortex-M4 toolchain for Cygwin under Windows. + + NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the + the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for + more information about this problem. If you plan to use NXFLAT, please do not + use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. + See instructions below. + +NuttX OABI "buildroot" Toolchain +================================ + + The older, OABI buildroot toolchain is also available. To use the OABI + toolchain: + + 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 + configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI + configuration such as cortexm3-defconfig-4.3.3 + + 2. Modify the Make.defs file to use the OABI conventions: + + +CROSSDEV = arm-nuttx-elf- + +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft + +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections + -CROSSDEV = arm-nuttx-eabi- + -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft + -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections + +NXFLAT Toolchain +================ + + If you are *not* using the NuttX buildroot toolchain and you want to use + the NXFLAT tools, then you will still have to build a portion of the buildroot + tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can + be downloaded from the NuttX Bitbucket download site + (https://bitbucket.org/nuttx/nuttx/downloads/). + + This GNU toolchain builds and executes in the Linux or Cygwin environment. + + 1. You must have already configured Nuttx in /nuttx. + + cd tools + ./configure.sh lpcxpresso-lpc1768/ + + 2. Download the latest buildroot package into + + 3. unpack the buildroot tarball. The resulting directory may + have versioning information on it like buildroot-x.y.z. If so, + rename /buildroot-x.y.z to /buildroot. + + 4. cd /buildroot + + 5. cp configs/cortexm3-defconfig-nxflat .config + + 6. make oldconfig + + 7. make + + 8. Edit setenv.h, if necessary, so that the PATH variable includes + the path to the newly builtNXFLAT binaries. + +TWR-K64F120M-specific Configuration Options +========================================== + + CONFIG_ARCH - Identifies the arch/ subdirectory. This sould + be set to: + + CONFIG_ARCH=arm + + CONFIG_ARCH_family - For use in C code: + + CONFIG_ARCH_ARM=y + + CONFIG_ARCH_architecture - For use in C code: + + CONFIG_ARCH_CORTEXM4=y + + CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory + + CONFIG_ARCH_CHIP=kinetis + + CONFIG_ARCH_CHIP_name - For use in C code to identify the exact + chip: + + CONFIG_ARCH_CHIP_MK64FN1M0VMD12=y + + CONFIG_ARCH_BOARD - Identifies the configs subdirectory and + hence, the board that supports the particular chip or SoC. + + CONFIG_ARCH_BOARD=twr-k64f120m (for the TWR-K64F120M development board) + + CONFIG_ARCH_BOARD_name - For use in C code + + CONFIG_ARCH_BOARD_TWR_K64F120M=y + + CONFIG_ENDIAN_BIG - define if big endian (default is little + endian) + + CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case): + + CONFIG_RAM_SIZE=262144 (256Kb) + + CONFIG_RAM_START - The start address of installed DRAM + + CONFIG_RAM_START=0x1fff0000 + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that + have LEDs + + CONFIG_ARCH_LEDS=y + + CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt + stack. If defined, this symbol is the size of the interrupt + stack in bytes. If not defined, the user task stacks will be + used during interrupt handling. + + CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions + + CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that + cause a 100 second delay during boot-up. This 100 second delay + serves no purpose other than it allows you to calibratre + CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure + the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until + the delay actually is 100 seconds. + + Individual subsystems can be enabled: + + CONFIG_KINETIS_TRACE -- Enable trace clocking on power up. + CONFIG_KINETIS_FLEXBUS -- Enable flexbus clocking on power up. + CONFIG_KINETIS_UART0 -- Support UART0 + CONFIG_KINETIS_UART1 -- Support UART1 + CONFIG_KINETIS_UART2 -- Support UART2 + CONFIG_KINETIS_UART3 -- Support UART3 + CONFIG_KINETIS_UART4 -- Support UART4 + CONFIG_KINETIS_UART5 -- Support UART5 + CONFIG_KINETIS_ENET -- Support Ethernet (K60 only) + CONFIG_KINETIS_RNGB -- Support the random number generator(K60 only) + CONFIG_KINETIS_FLEXCAN0 -- Support FlexCAN0 + CONFIG_KINETIS_FLEXCAN1 -- Support FlexCAN1 + CONFIG_KINETIS_SPI0 -- Support SPI0 + CONFIG_KINETIS_SPI1 -- Support SPI1 + CONFIG_KINETIS_SPI2 -- Support SPI2 + CONFIG_KINETIS_I2C0 -- Support I2C0 + CONFIG_KINETIS_I2C1 -- Support I2C1 + CONFIG_KINETIS_I2S -- Support I2S + CONFIG_KINETIS_DAC0 -- Support DAC0 + CONFIG_KINETIS_DAC1 -- Support DAC1 + CONFIG_KINETIS_ADC0 -- Support ADC0 + CONFIG_KINETIS_ADC1 -- Support ADC1 + CONFIG_KINETIS_CMP -- Support CMP + CONFIG_KINETIS_VREF -- Support VREF + CONFIG_KINETIS_SDHC -- Support SD host controller + CONFIG_KINETIS_FTM0 -- Support FlexTimer 0 + CONFIG_KINETIS_FTM1 -- Support FlexTimer 1 + CONFIG_KINETIS_FTM2 -- Support FlexTimer 2 + CONFIG_KINETIS_LPTIMER -- Support the low power timer + CONFIG_KINETIS_RTC -- Support RTC + CONFIG_KINETIS_SLCD -- Support the segment LCD (K60 only) + CONFIG_KINETIS_EWM -- Support the external watchdog + CONFIG_KINETIS_CMT -- Support Carrier Modulator Transmitter + CONFIG_KINETIS_USBOTG -- Support USB OTG (see also CONFIG_USBHOST and CONFIG_USBDEV) + CONFIG_KINETIS_USBDCD -- Support the USB Device Charger Detection module + CONFIG_KINETIS_LLWU -- Support the Low Leakage Wake-Up Unit + CONFIG_KINETIS_TSI -- Support the touch screeen interface + CONFIG_KINETIS_FTFL -- Support FLASH + CONFIG_KINETIS_DMA -- Support DMA + CONFIG_KINETIS_CRC -- Support CRC + CONFIG_KINETIS_PDB -- Support the Programmable Delay Block + CONFIG_KINETIS_PIT -- Support Programmable Interval Timers + CONFIG_ARM_MPU -- Support the MPU + + Kinetis interrupt priorities (Default is the mid priority). These should + not be set because they can cause unhandled, nested interrupts. All + interrupts need to be at the default priority in the current design. + + CONFIG_KINETIS_UART0PRIO + CONFIG_KINETIS_UART1PRIO + CONFIG_KINETIS_UART2PRIO + CONFIG_KINETIS_UART3PRIO + CONFIG_KINETIS_UART4PRIO + CONFIG_KINETIS_UART5PRIO + + CONFIG_KINETIS_EMACTMR_PRIO + CONFIG_KINETIS_EMACTX_PRIO + CONFIG_KINETIS_EMACRX_PRIO + CONFIG_KINETIS_EMACMISC_PRIO + + CONFIG_KINETIS_SDHC_PRIO + + PIN Interrupt Support + + CONFIG_KINETIS_GPIOIRQ -- Enable pin interrupt support. Also needs + one or more of the following: + CONFIG_KINETIS_PORTAINTS -- Support 32 Port A interrupts + CONFIG_KINETIS_PORTBINTS -- Support 32 Port B interrupts + CONFIG_KINETIS_PORTCINTS -- Support 32 Port C interrupts + CONFIG_KINETIS_PORTDINTS -- Support 32 Port D interrupts + CONFIG_KINETIS_PORTEINTS -- Support 32 Port E interrupts + + Kinetis specific device driver settings + + CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn (n=0..5) for the + console and ttys0 (default is the UART0). + CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received. + This specific the size of the receive buffer + CONFIG_UARTn_TXBUFSIZE - Characters are buffered before + being sent. This specific the size of the transmit buffer + CONFIG_UARTn_BAUD - The configure BAUD of the UART. + CONFIG_UARTn_BITS - The number of bits. Must be either 8 or 8. + CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity + + Kenetis ethernet controller settings + + CONFIG_ENET_NRXBUFFERS - Number of RX buffers. The size of one + buffer is determined by CONFIG_NET_ETH_MTU. Default: 6 + CONFIG_ENET_NTXBUFFERS - Number of TX buffers. The size of one + buffer is determined by CONFIG_NET_ETH_MTU. Default: 2 + CONFIG_ENET_USEMII - Use MII mode. Default: RMII mode. + CONFIG_ENET_PHYADDR - PHY address + +Configurations +============== + +Each TWR-K64F120M configuration is maintained in a sub-directory and +can be selected as follow: + + cd tools + ./configure.sh twr-k64f120m/ + cd .. + . ./setenv.sh + +Where is one of the following: + + nsh: + --- + Configures the NuttShell (nsh) located at apps/examples/nsh. The + Configuration enables only the serial interface. + The serial console is on OpenSDA serial bridge. For access, + use $ miniterm.py -f direct /dev/ttyACM0 115200 from Linux PC + Support for the board's SDHC MicroSD card is included. + + NOTES: + + 1. The SDHC driver is under work and currently support IRQ mode (no DMA): + + CONFIG_KINETIS_SDHC=y : Enable the SDHC driver + + CONFIG_MMCSD=y : Enable MMC/SD support + CONFIG_MMCSD_SDIO=y : Use the SDIO-based MMC/SD driver + CONFIG_MMCSD_NSLOTS=1 : One MMC/SD slot + + CONFIG_FAT=y : Eable FAT file system + CONFIG_FAT_LCNAMES=n : FAT lower case name support + CONFIG_FAT_LFN=y : FAT long file name support + CONFIG_FAT_MAXFNAME=32 : Maximum length of a long file name + + CONFIG_KINETIS_GPIOIRQ=y : Enable GPIO interrupts + CONFIG_KINETIS_PORTEINTS=y : Enable PortE GPIO interrupts + + CONFIG_SCHED_WORKQUEUE=y : Enable the NuttX workqueue + + CONFIG_NSH_ARCHINIT=y : Provide NSH initializeation logic + + netnsh: + ------ + This is the same config then nsh, but it adds Ethernet support with the + TWR-SER card. It includes telnetd in order to access nsh from Ethernet. + IP address defaults to 192.168.0.233/24. + + NOTES: + + 1. See networking support for application and especially for jumper setting. + In this config, this is TWR-SER that clocks the MCU. + + 2. The PHY link negotiation is done at boot time only. If no link is then + available, a fallback mode is used at 10Mbs/half-duplex. Please make sure + your ethernet cable and switches are on before booting. + diff --git a/configs/twr-k64f120m/include/board.h b/configs/twr-k64f120m/include/board.h new file mode 100644 index 00000000000..638bdd57121 --- /dev/null +++ b/configs/twr-k64f120m/include/board.h @@ -0,0 +1,197 @@ +/************************************************************************************ + * configs/twr-k64f120m/include/board.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_TWR_K64F120M_INCLUDE_BOARCH_H +#define __CONFIGS_TWR_K64F120M_INCLUDE_BOARCH_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* The K64 tower board uses a 50MHz external clock */ + +#define BOARD_EXTCLOCK 1 /* External clock */ +#define BOARD_EXTAL_FREQ 50000000 /* 50MHz Oscillator */ +#define BOARD_XTAL32_FREQ 32768 /* 32KHz RTC Oscillator */ + +/* PLL Configuration. Either the external clock or crystal frequency is used to + * select the PRDIV value. Only reference clock frequencies are supported that will + * produce a range 2MHz-4MHz reference clock to the PLL. + * + * PLL Input frequency: PLLIN = REFCLK/PRDIV = 50MHz/20 = 2.5 MHz + * PLL Output frequency: PLLOUT = PLLIN*VDIV = 2.5Mhz*48 = 120MHz + * MCG Frequency: PLLOUT = 120 Mhz + */ + +#define BOARD_PRDIV 20 /* PLL External Reference Divider */ +#define BOARD_VDIV 48 /* PLL VCO Divider (frequency multiplier) */ + +#define BOARD_PLLIN_FREQ (BOARD_EXTAL_FREQ / BOARD_PRDIV) +#define BOARD_PLLOUT_FREQ (BOARD_PLLIN_FREQ * BOARD_VDIV) +#define BOARD_MCG_FREQ BOARD_PLLOUT_FREQ + +/* Define additional MCG_C2 Setting */ + +#define BOARD_MCG_C2_FCFTRIM 0 /* Do not enable FCFTRIM */ +#define BOARD_MCG_C2_LOCRE0 MCG_C2_LOCRE0 /* Enable reset on loss of clock */ + +/* SIM CLKDIV1 dividers */ + +#define BOARD_OUTDIV1 1 /* Core = MCG, 120MHz */ +#define BOARD_OUTDIV2 2 /* Bus = MCG/2, 60MHz */ +#define BOARD_OUTDIV3 2 /* FlexBus = MCG/2, 60MHz */ +#define BOARD_OUTDIV4 5 /* Flash clock = MCG/5, 24MHz */ + +#define BOARD_CORECLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV1) +#define BOARD_BUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV2) +#define BOARD_FLEXBUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV3) +#define BOARD_FLASHCLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV4) + +/* SDHC clocking ********************************************************************/ + +/* SDCLK configurations corresponding to various modes of operation. Formula is: + * + * SDCLK frequency = (base clock) / (prescaler * divisor) + * + * The SDHC module is always configure configured so that the core clock is the base + * clock. + */ + +/* Identification mode: 375KHz = 120MHz / ( 64 * 5) <= 400 KHz */ + +#define BOARD_SDHC_IDMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV64 +#define BOARD_SDHC_IDMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(5) + +/* MMC normal mode: 15MHz = 120MHz / (8 * 1) <= 16 MHz*/ + +#define BOARD_SDHC_MMCMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV8 +#define BOARD_SDHC_MMCMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(1) + +/* SD normal mode (1-bit): 15MHz = 120MHz / (8 * 1) <= 16 MHz*/ + +#define BOARD_SDHC_SD1MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV8 +#define BOARD_SDHC_SD1MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(1) + +/* SD normal mode (4-bit): 20MHz = 120MHz / (2 * 3) (with DMA) <= 24MHz + * SD normal mode (4-bit): 15MHz = 120MHz / (8 * 1) (no DMA) <= 16MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2 +# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3) +#else +# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV8 +# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(1) +#endif + + +/* LED definitions ******************************************************************/ +/* The TWR-K64F120M has four LEDs: + * + * 1. D5 / Green LED PTE6 + * 2. D6 / Yellow LED PTE7 + * 3. D7 / Orange LED PTE8 + * 4 D9 / Blue LED PTE9 + * + * LED4 is reservered for user. + * The 3 first LEDs are encoded as follows: + */ + +#define LED_STARTED 0 /* N/A */ +#define LED_HEAPALLOCATE 1 /* N/A */ +#define LED_IRQSENABLED 2 /* N/A */ +#define LED_STACKCREATED 3 /* LED1 - OS is started */ +#define LED_INIRQ 4 /* LED2 */ +#define LED_SIGNAL 5 /* LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* LED1 (blink) */ + + +/* Open SDA serial link */ +#define PIN_UART1_RX PIN_UART1_RX_1 +#define PIN_UART1_TX PIN_UART1_TX_1 + + +/* Ethernet */ +#ifdef CONFIG_KINETIS_ENET +# define CONFIG_KINETIS_NENET 1 +#endif + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ +/************************************************************************************ + * Name: kinetis_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void kinetis_boardinitialize(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_TWR_K64F120M_INCLUDE_BOARCH_H */ diff --git a/configs/twr-k64f120m/netnsh/Make.defs b/configs/twr-k64f120m/netnsh/Make.defs new file mode 100644 index 00000000000..4ed1515b60a --- /dev/null +++ b/configs/twr-k64f120m/netnsh/Make.defs @@ -0,0 +1,111 @@ +############################################################################ +# configs/twr-k64f120m/netnsh/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/twr-k64f120m/netnsh/defconfig b/configs/twr-k64f120m/netnsh/defconfig new file mode 100644 index 00000000000..d0b964f8ef2 --- /dev/null +++ b/configs/twr-k64f120m/netnsh/defconfig @@ -0,0 +1,1263 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +# CONFIG_RAW_BINARY is not set +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +# CONFIG_DEBUG_SYMBOLS is not set +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +CONFIG_ARCH_CHIP_KINETIS=y +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM23 is not set +# CONFIG_ARCH_CORTEXM3 is not set +# CONFIG_ARCH_CORTEXM33 is not set +CONFIG_ARCH_CORTEXM4=y +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="kinetis" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARMV7M_LAZYFPU is not set +CONFIG_ARCH_HAVE_FPU=y +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y +# CONFIG_ARMV7M_HAVE_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set + +# +# Kinetis Configuration Options +# +# CONFIG_ARCH_CHIP_MK20DN32VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX32VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DN64VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX64VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DN128VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX128VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX64VLH7 is not set +# CONFIG_ARCH_CHIP_MK20DX128VLH7 is not set +# CONFIG_ARCH_CHIP_MK20DX256VLH7 is not set +# CONFIG_ARCH_CHIP_MK40N512VLQ100 is not set +# CONFIG_ARCH_CHIP_MK40N512VMD100 is not set +# CONFIG_ARCH_CHIP_MK40X128VLQ100 is not set +# CONFIG_ARCH_CHIP_MK40X128VMD100 is not set +# CONFIG_ARCH_CHIP_MK40X256VLQ100 is not set +# CONFIG_ARCH_CHIP_MK40X256VMD100 is not set +# CONFIG_ARCH_CHIP_MK60N256VLQ100 is not set +# CONFIG_ARCH_CHIP_MK60N256VMD100 is not set +# CONFIG_ARCH_CHIP_MK60N512VLL100 is not set +# CONFIG_ARCH_CHIP_MK60N512VLQ100 is not set +# CONFIG_ARCH_CHIP_MK60N512VMD100 is not set +# CONFIG_ARCH_CHIP_MK60X256VLQ100 is not set +# CONFIG_ARCH_CHIP_MK60X256VMD100 is not set +# CONFIG_ARCH_CHIP_MK60FN1M0VLQ12 is not set +# CONFIG_ARCH_CHIP_MK64FN1M0VLL12 is not set +# CONFIG_ARCH_CHIP_MK64FX512VLL12 is not set +# CONFIG_ARCH_CHIP_MK64FX512VDC12 is not set +# CONFIG_ARCH_CHIP_MK64FN1M0VDC12 is not set +# CONFIG_ARCH_CHIP_MK64FX512VLQ12 is not set +# CONFIG_ARCH_CHIP_MK64FX512VMD12 is not set +CONFIG_ARCH_CHIP_MK64FN1M0VMD12=y +# CONFIG_ARCH_CHIP_MK66FX1M0VMD18 is not set +# CONFIG_ARCH_CHIP_MK66FN2M0VMD18 is not set +# CONFIG_ARCH_CHIP_MK66FX1M0VLQ18 is not set +# CONFIG_ARCH_CHIP_MK66FN2M0VLQ18 is not set +# CONFIG_ARCH_FAMILY_K20 is not set +# CONFIG_ARCH_FAMILY_K40 is not set +# CONFIG_ARCH_FAMILY_K60 is not set +CONFIG_ARCH_FAMILY_K64=y +# CONFIG_ARCH_FAMILY_K66 is not set + +# +# Kinetis Peripheral Support +# +CONFIG_KINETIS_HAVE_I2C1=y +CONFIG_KINETIS_HAVE_I2C2=y +# CONFIG_KINETIS_HAVE_I2C3 is not set +CONFIG_KINETIS_HAVE_SPI1=y +CONFIG_KINETIS_HAVE_SPI2=y +# CONFIG_KINETIS_TRACE is not set +# CONFIG_KINETIS_FLEXBUS is not set +# CONFIG_KINETIS_UART0 is not set +CONFIG_KINETIS_UART1=y +# CONFIG_KINETIS_UART2 is not set +# CONFIG_KINETIS_UART3 is not set +# CONFIG_KINETIS_UART4 is not set +# CONFIG_KINETIS_UART5 is not set +CONFIG_KINETIS_ENET=y +# CONFIG_KINETIS_RNGB is not set +# CONFIG_KINETIS_FLEXCAN0 is not set +# CONFIG_KINETIS_FLEXCAN1 is not set +# CONFIG_KINETIS_SPI0 is not set +# CONFIG_KINETIS_SPI1 is not set +# CONFIG_KINETIS_SPI2 is not set +# CONFIG_KINETIS_I2C0 is not set +# CONFIG_KINETIS_I2C1 is not set +# CONFIG_KINETIS_I2C2 is not set +# CONFIG_KINETIS_I2S is not set +# CONFIG_KINETIS_DAC0 is not set +# CONFIG_KINETIS_DAC1 is not set +# CONFIG_KINETIS_ADC0 is not set +# CONFIG_KINETIS_ADC1 is not set +# CONFIG_KINETIS_CMP is not set +# CONFIG_KINETIS_VREF is not set +CONFIG_KINETIS_SDHC=y +# CONFIG_KINETIS_FTM0 is not set +# CONFIG_KINETIS_FTM1 is not set +# CONFIG_KINETIS_FTM2 is not set +# CONFIG_KINETIS_FTM3 is not set +# CONFIG_KINETIS_LPTIMER is not set +# CONFIG_KINETIS_RTC is not set +# CONFIG_KINETIS_EWM is not set +# CONFIG_KINETIS_CMT is not set +# CONFIG_KINETIS_USBOTG is not set +# CONFIG_KINETIS_USBDCD is not set +# CONFIG_KINETIS_LLWU is not set +# CONFIG_KINETIS_TSI is not set +# CONFIG_KINETIS_FTFL is not set +# CONFIG_KINETIS_DMA is not set +# CONFIG_KINETIS_CRC is not set +# CONFIG_KINETIS_PDB is not set +# CONFIG_KINETIS_PIT is not set + +# +# Kinetis GPIO Interrupt Configuration +# +CONFIG_KINETIS_GPIOIRQ=y +# CONFIG_KINETIS_PORTAINTS is not set +CONFIG_KINETIS_PORTBINTS=y +# CONFIG_KINETIS_PORTCINTS is not set +# CONFIG_KINETIS_PORTDINTS is not set +# CONFIG_KINETIS_PORTEINTS is not set + +# +# Kinetis Ethernet Configuration +# +# CONFIG_KINETIS_ENETENHANCEDBD is not set +CONFIG_KINETIS_ENETNETHIFS=1 +CONFIG_KINETIS_ENETNRXBUFFERS=6 +CONFIG_KINETIS_ENETNTXBUFFERS=2 +# CONFIG_KINETIS_ENETUSEMII is not set +# CONFIG_KINETIS_ENET_MDIOPULLUP is not set +# CONFIG_KINETIS_ENET_NORXER is not set +CONFIG_KINETIS_EMAC_RMIICLKEXTAL=y +# CONFIG_KINETIS_EMAC_RMIICLK1588CLKIN is not set +CONFIG_KINETIS_EMAC_HPWORK=y + +# +# Kinetis SDHC Configuration +# +# CONFIG_KINETIS_SDHC_DMA is not set +# CONFIG_KINETIS_SDHC_WIDTH_D1_ONLY is not set +# CONFIG_KINETIS_SDHC_ABSFREQ is not set + +# +# Kinetis UART Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +CONFIG_ARCH_HAVE_RAMFUNCS=y +CONFIG_ARCH_RAMFUNCS=y +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=9535 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x1fff0000 +CONFIG_RAM_SIZE=262144 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_TWR_K64F120M=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="twr-k64f120m" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +# CONFIG_ARCH_BUTTONS is not set +CONFIG_ARCH_HAVE_IRQBUTTONS=y + +# +# Board-Specific Options +# +CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT=y +CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_FSTYPE="vfat" +CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_BLKDEV="/dev/mmcsd0" +CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_MOUNTPOINT="/mnt/sdcard" +CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_DDELAY=1000 +CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_UDELAY=2000 +# CONFIG_BOARD_CRASHDUMP is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2017 +CONFIG_START_MONTH=1 +CONFIG_START_DAY=23 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_SPINLOCK is not set +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=10 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 +# CONFIG_PTHREAD_CLEANUP is not set +# CONFIG_CANCELLATION_POINTS is not set + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set +# CONFIG_SPI is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +CONFIG_MMCSD=y +CONFIG_MMCSD_NSLOTS=1 +# CONFIG_MMCSD_READONLY is not set +# CONFIG_MMCSD_MULTIBLOCK_DISABLE is not set +CONFIG_MMCSD_MMCSUPPORT=y +CONFIG_MMCSD_HAVECARDDETECT=y +CONFIG_ARCH_HAVE_SDIO=y +# CONFIG_SDIO_DMA is not set +# CONFIG_ARCH_HAVE_SDIOWAIT_WRCOMPLETE is not set +CONFIG_MMCSD_SDIO=y +# CONFIG_SDIO_PREFLIGHT is not set +# CONFIG_SDIO_MUXBUS is not set +# CONFIG_SDIO_WIDTH_D1_ONLY is not set +# CONFIG_SDIO_BLOCKSETUP is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +CONFIG_NETDEVICES=y + +# +# General Ethernet MAC Driver Options +# +# CONFIG_NETDEV_LOOPBACK is not set +CONFIG_NETDEV_TELNET=y +CONFIG_TELNET_RXBUFFER_SIZE=256 +CONFIG_TELNET_TXBUFFER_SIZE=256 +# CONFIG_NETDEV_MULTINIC is not set +CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y +# CONFIG_NETDEV_LATEINIT is not set + +# +# External Ethernet MAC Device Support +# +# CONFIG_NET_DM90x0 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ENCX24J600 is not set +# CONFIG_NET_SLIP is not set +# CONFIG_NET_FTMAC100 is not set + +# +# External Ethernet PHY Device Support +# +# CONFIG_ARCH_PHY_INTERRUPT is not set +# CONFIG_ETH0_PHY_NONE is not set +# CONFIG_ETH0_PHY_AM79C874 is not set +# CONFIG_ETH0_PHY_KS8721 is not set +CONFIG_ETH0_PHY_KSZ8041=y +# CONFIG_ETH0_PHY_KSZ8051 is not set +# CONFIG_ETH0_PHY_KSZ8061 is not set +# CONFIG_ETH0_PHY_KSZ8081 is not set +# CONFIG_ETH0_PHY_KSZ90x1 is not set +# CONFIG_ETH0_PHY_DP83848C is not set +# CONFIG_ETH0_PHY_LAN8720 is not set +# CONFIG_ETH0_PHY_LAN8740 is not set +# CONFIG_ETH0_PHY_LAN8740A is not set +# CONFIG_ETH0_PHY_LAN8742A is not set +# CONFIG_ETH0_PHY_DM9161 is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +CONFIG_UART1_SERIALDRIVER=y +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +CONFIG_UART1_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART1 Configuration +# +CONFIG_UART1_RXBUFSIZE=256 +CONFIG_UART1_TXBUFSIZE=256 +CONFIG_UART1_BAUD=115200 +CONFIG_UART1_BITS=8 +CONFIG_UART1_PARITY=0 +CONFIG_UART1_2STOP=0 +# CONFIG_UART1_IFLOWCONTROL is not set +# CONFIG_UART1_OFLOWCONTROL is not set +# CONFIG_UART1_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +CONFIG_ARCH_HAVE_NET=y +CONFIG_ARCH_HAVE_PHY=y +CONFIG_NET=y +# CONFIG_NET_PROMISCUOUS is not set + +# +# Driver buffer configuration +# +CONFIG_NET_ETH_MTU=590 +CONFIG_NET_ETH_TCP_RECVWNDO=536 +CONFIG_NET_GUARDSIZE=2 + +# +# Data link support +# +# CONFIG_NET_MULTILINK is not set +CONFIG_NET_ETHERNET=y +# CONFIG_NET_LOOPBACK is not set +# CONFIG_NET_TUN is not set + +# +# Network Device Operations +# +# CONFIG_NETDEV_PHY_IOCTL is not set + +# +# Internet Protocol Selection +# +CONFIG_NET_IPv4=y +# CONFIG_NET_IPv6 is not set + +# +# Socket Support +# +CONFIG_NSOCKET_DESCRIPTORS=8 +CONFIG_NET_NACTIVESOCKETS=16 +# CONFIG_NET_SOCKOPTS is not set + +# +# Raw Socket Support +# +# CONFIG_NET_PKT is not set + +# +# Unix Domain Socket Support +# +# CONFIG_NET_LOCAL is not set + +# +# TCP/IP Networking +# +CONFIG_NET_TCP=y +# CONFIG_NET_TCPURGDATA is not set +CONFIG_NET_TCP_CONNS=8 +CONFIG_NET_MAX_LISTENPORTS=20 +CONFIG_NET_TCP_READAHEAD=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_TCP_NWRBCHAINS=8 +CONFIG_NET_TCP_RECVDELAY=0 +# CONFIG_NET_TCPBACKLOG is not set +# CONFIG_NET_SENDFILE is not set + +# +# UDP Networking +# +CONFIG_NET_UDP=y +# CONFIG_NET_UDP_CHECKSUMS is not set +CONFIG_NET_UDP_CONNS=8 +CONFIG_NET_BROADCAST=y +# CONFIG_NET_RXAVAIL is not set +CONFIG_NET_UDP_READAHEAD=y + +# +# ICMP Networking Support +# +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_PING=y + +# +# IGMPv2 Client Support +# +# CONFIG_NET_IGMP is not set + +# +# ARP Configuration +# +CONFIG_NET_ARP=y +CONFIG_NET_ARPTAB_SIZE=16 +CONFIG_NET_ARP_MAXAGE=120 +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_ARP_SEND=y +CONFIG_ARP_SEND_MAXTRIES=5 +CONFIG_ARP_SEND_DELAYMSEC=20 + +# +# Network I/O Buffer Support +# +CONFIG_NET_IOB=y +CONFIG_IOB_NBUFFERS=36 +CONFIG_IOB_BUFSIZE=196 +CONFIG_IOB_NCHAINS=8 +CONFIG_IOB_THROTTLE=8 +# CONFIG_NET_ARCH_INCR32 is not set +# CONFIG_NET_ARCH_CHKSUM is not set +# CONFIG_NET_STATISTICS is not set + +# +# Routing Table Configuration +# +# CONFIG_NET_ROUTE is not set +CONFIG_NET_HOSTNAME="TWRK64" + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +CONFIG_FS_AUTOMOUNTER=y +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_PSEUDOFS_SOFTLINKS is not set +CONFIG_FS_READABLE=y +CONFIG_FS_WRITABLE=y +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +CONFIG_FS_FAT=y +# CONFIG_FAT_LCNAMES is not set +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=32 +# CONFIG_FS_FATTIME is not set +# CONFIG_FAT_FORCE_INDIRECT is not set +# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FAT_DIRECT_RETRY is not set +# CONFIG_NFS is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +CONFIG_FS_PROCFS=y +# CONFIG_FS_PROCFS_REGISTER is not set + +# +# Exclude individual procfs entries +# +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set +# CONFIG_FS_PROCFS_EXCLUDE_NET is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_BUILTIN is not set +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# + +# +# Standard C I/O +# +# CONFIG_STDIO_DISABLE_BUFFERING is not set +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_SCANSET is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_MEMCPY_VIK is not set +# CONFIG_LIBM is not set + +# +# Architecture-Specific Support +# +CONFIG_ARCH_LOWPUTC=y +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_LIBC_ARCH_MEMCPY is not set +# CONFIG_LIBC_ARCH_MEMCMP is not set +# CONFIG_LIBC_ARCH_MEMMOVE is not set +# CONFIG_LIBC_ARCH_MEMSET is not set +# CONFIG_LIBC_ARCH_STRCHR is not set +# CONFIG_LIBC_ARCH_STRCMP is not set +# CONFIG_LIBC_ARCH_STRCPY is not set +# CONFIG_LIBC_ARCH_STRNCPY is not set +# CONFIG_LIBC_ARCH_STRLEN is not set +# CONFIG_LIBC_ARCH_STRNLEN is not set +# CONFIG_LIBC_ARCH_ELF is not set +# CONFIG_ARMV7M_MEMCPY is not set + +# +# stdlib Options +# +CONFIG_LIB_RAND_ORDER=1 +CONFIG_LIB_HOMEDIR="/" +CONFIG_LIBC_TMPDIR="/tmp" +CONFIG_LIBC_MAX_TMPFILE=32 + +# +# Program Execution Options +# +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 + +# +# errno Decode Support +# +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set + +# +# memcpy/memset Options +# +# CONFIG_MEMSET_OPTSPEED is not set +# CONFIG_LIBC_DLLFCN is not set +# CONFIG_LIBC_MODLIB is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set + +# +# Time/Time Zone Support +# +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_ARCH_HAVE_TLS=y + +# +# Thread Local Storage (TLS) +# +# CONFIG_TLS is not set + +# +# Network-Related Options +# +# CONFIG_LIBC_IPv6_ADDRCONV is not set +CONFIG_LIBC_NETDB=y + +# +# NETDB Support +# +# CONFIG_NETDB_HOSTFILE is not set +# CONFIG_NETDB_DNSCLIENT is not set +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_DISCOVER is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FSTEST is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NETTEST is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_STAT is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UDPBLASTER is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set +# CONFIG_EXAMPLES_WGET is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set +# CONFIG_FSUTILS_PASSWD is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_BAS is not set +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_DISCOVER is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +CONFIG_NETUTILS_NETLIB=y +# CONFIG_NETUTILS_NTPCLIENT is not set +# CONFIG_NETUTILS_PPPD is not set +# CONFIG_NETUTILS_SMTP is not set +CONFIG_NETUTILS_TELNETD=y +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_WEBCLIENT is not set +# CONFIG_NETUTILS_WEBSERVER is not set +# CONFIG_NETUTILS_XMLRPC is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +CONFIG_NSH_CMDPARMS=y +CONFIG_NSH_MAXARGUMENTS=6 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_ARP is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PING is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 + +# +# Configure Command Options +# +CONFIG_NSH_CMDOPT_DF_H=y +# CONFIG_NSH_CMDOPT_DD_STATS is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_CMDOPT_HEXDUMP=y +CONFIG_NSH_PROC_MOUNTPOINT="/proc" +CONFIG_NSH_FILEIOSIZE=512 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +CONFIG_NSH_ARCHINIT=y + +# +# Networking Configuration +# +CONFIG_NSH_NETINIT=y +# CONFIG_NSH_NETINIT_THREAD is not set + +# +# IP Address Configuration +# + +# +# IPv4 Addresses +# +CONFIG_NSH_IPADDR=0xc0a800e9 +CONFIG_NSH_DRIPADDR=0xc0a800fe +CONFIG_NSH_NETMASK=0xffffff00 +# CONFIG_NSH_NOMAC is not set +CONFIG_NSH_MAX_ROUNDTRIP=20 + +# +# Telnet Configuration +# +CONFIG_NSH_TELNET=y +CONFIG_NSH_TELNETD_PORT=23 +CONFIG_NSH_TELNETD_DAEMONPRIO=100 +CONFIG_NSH_TELNETD_DAEMONSTACKSIZE=2048 +CONFIG_NSH_TELNETD_CLIENTPRIO=100 +CONFIG_NSH_TELNETD_CLIENTSTACKSIZE=2048 +CONFIG_NSH_IOBUFFER_SIZE=512 +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set +# CONFIG_NSH_TELNET_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_NETDB is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/twr-k64f120m/netnsh/setenv.sh b/configs/twr-k64f120m/netnsh/setenv.sh new file mode 100755 index 00000000000..009064720ba --- /dev/null +++ b/configs/twr-k64f120m/netnsh/setenv.sh @@ -0,0 +1,61 @@ +#!/bin/bash +# configs/twr-k64f120m/netnsh/setenv.sh +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" +echo "PATH : ${PATH}" diff --git a/configs/twr-k64f120m/nsh/Make.defs b/configs/twr-k64f120m/nsh/Make.defs new file mode 100644 index 00000000000..5b468a19c20 --- /dev/null +++ b/configs/twr-k64f120m/nsh/Make.defs @@ -0,0 +1,111 @@ +############################################################################ +# configs/twr-k64f120m/nsh/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/twr-k64f120m/nsh/defconfig b/configs/twr-k64f120m/nsh/defconfig new file mode 100644 index 00000000000..d819dfe55f9 --- /dev/null +++ b/configs/twr-k64f120m/nsh/defconfig @@ -0,0 +1,1050 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +# CONFIG_RAW_BINARY is not set +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +# CONFIG_DEBUG_SYMBOLS is not set +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +CONFIG_ARCH_CHIP_KINETIS=y +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM23 is not set +# CONFIG_ARCH_CORTEXM3 is not set +# CONFIG_ARCH_CORTEXM33 is not set +CONFIG_ARCH_CORTEXM4=y +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="kinetis" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARMV7M_LAZYFPU is not set +CONFIG_ARCH_HAVE_FPU=y +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y +# CONFIG_ARMV7M_HAVE_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set + +# +# Kinetis Configuration Options +# +# CONFIG_ARCH_CHIP_MK20DN32VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX32VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DN64VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX64VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DN128VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX128VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX64VLH7 is not set +# CONFIG_ARCH_CHIP_MK20DX128VLH7 is not set +# CONFIG_ARCH_CHIP_MK20DX256VLH7 is not set +# CONFIG_ARCH_CHIP_MK40N512VLQ100 is not set +# CONFIG_ARCH_CHIP_MK40N512VMD100 is not set +# CONFIG_ARCH_CHIP_MK40X128VLQ100 is not set +# CONFIG_ARCH_CHIP_MK40X128VMD100 is not set +# CONFIG_ARCH_CHIP_MK40X256VLQ100 is not set +# CONFIG_ARCH_CHIP_MK40X256VMD100 is not set +# CONFIG_ARCH_CHIP_MK60N256VLQ100 is not set +# CONFIG_ARCH_CHIP_MK60N256VMD100 is not set +# CONFIG_ARCH_CHIP_MK60N512VLL100 is not set +# CONFIG_ARCH_CHIP_MK60N512VLQ100 is not set +# CONFIG_ARCH_CHIP_MK60N512VMD100 is not set +# CONFIG_ARCH_CHIP_MK60X256VLQ100 is not set +# CONFIG_ARCH_CHIP_MK60X256VMD100 is not set +# CONFIG_ARCH_CHIP_MK60FN1M0VLQ12 is not set +# CONFIG_ARCH_CHIP_MK64FN1M0VLL12 is not set +# CONFIG_ARCH_CHIP_MK64FX512VLL12 is not set +# CONFIG_ARCH_CHIP_MK64FX512VDC12 is not set +# CONFIG_ARCH_CHIP_MK64FN1M0VDC12 is not set +# CONFIG_ARCH_CHIP_MK64FX512VLQ12 is not set +# CONFIG_ARCH_CHIP_MK64FX512VMD12 is not set +CONFIG_ARCH_CHIP_MK64FN1M0VMD12=y +# CONFIG_ARCH_CHIP_MK66FX1M0VMD18 is not set +# CONFIG_ARCH_CHIP_MK66FN2M0VMD18 is not set +# CONFIG_ARCH_CHIP_MK66FX1M0VLQ18 is not set +# CONFIG_ARCH_CHIP_MK66FN2M0VLQ18 is not set +# CONFIG_ARCH_FAMILY_K20 is not set +# CONFIG_ARCH_FAMILY_K40 is not set +# CONFIG_ARCH_FAMILY_K60 is not set +CONFIG_ARCH_FAMILY_K64=y +# CONFIG_ARCH_FAMILY_K66 is not set + +# +# Kinetis Peripheral Support +# +CONFIG_KINETIS_HAVE_I2C1=y +CONFIG_KINETIS_HAVE_I2C2=y +# CONFIG_KINETIS_HAVE_I2C3 is not set +CONFIG_KINETIS_HAVE_SPI1=y +CONFIG_KINETIS_HAVE_SPI2=y +# CONFIG_KINETIS_TRACE is not set +# CONFIG_KINETIS_FLEXBUS is not set +# CONFIG_KINETIS_UART0 is not set +CONFIG_KINETIS_UART1=y +# CONFIG_KINETIS_UART2 is not set +# CONFIG_KINETIS_UART3 is not set +# CONFIG_KINETIS_UART4 is not set +# CONFIG_KINETIS_UART5 is not set +# CONFIG_KINETIS_ENET is not set +# CONFIG_KINETIS_RNGB is not set +# CONFIG_KINETIS_FLEXCAN0 is not set +# CONFIG_KINETIS_FLEXCAN1 is not set +# CONFIG_KINETIS_SPI0 is not set +# CONFIG_KINETIS_SPI1 is not set +# CONFIG_KINETIS_SPI2 is not set +# CONFIG_KINETIS_I2C0 is not set +# CONFIG_KINETIS_I2C1 is not set +# CONFIG_KINETIS_I2C2 is not set +# CONFIG_KINETIS_I2S is not set +# CONFIG_KINETIS_DAC0 is not set +# CONFIG_KINETIS_DAC1 is not set +# CONFIG_KINETIS_ADC0 is not set +# CONFIG_KINETIS_ADC1 is not set +# CONFIG_KINETIS_CMP is not set +# CONFIG_KINETIS_VREF is not set +CONFIG_KINETIS_SDHC=y +# CONFIG_KINETIS_FTM0 is not set +# CONFIG_KINETIS_FTM1 is not set +# CONFIG_KINETIS_FTM2 is not set +# CONFIG_KINETIS_FTM3 is not set +# CONFIG_KINETIS_LPTIMER is not set +# CONFIG_KINETIS_RTC is not set +# CONFIG_KINETIS_EWM is not set +# CONFIG_KINETIS_CMT is not set +# CONFIG_KINETIS_USBOTG is not set +# CONFIG_KINETIS_USBDCD is not set +# CONFIG_KINETIS_LLWU is not set +# CONFIG_KINETIS_TSI is not set +# CONFIG_KINETIS_FTFL is not set +# CONFIG_KINETIS_DMA is not set +# CONFIG_KINETIS_CRC is not set +# CONFIG_KINETIS_PDB is not set +# CONFIG_KINETIS_PIT is not set + +# +# Kinetis GPIO Interrupt Configuration +# +CONFIG_KINETIS_GPIOIRQ=y +# CONFIG_KINETIS_PORTAINTS is not set +CONFIG_KINETIS_PORTBINTS=y +# CONFIG_KINETIS_PORTCINTS is not set +# CONFIG_KINETIS_PORTDINTS is not set +# CONFIG_KINETIS_PORTEINTS is not set + +# +# Kinetis SDHC Configuration +# +# CONFIG_KINETIS_SDHC_DMA is not set +# CONFIG_KINETIS_SDHC_WIDTH_D1_ONLY is not set +# CONFIG_KINETIS_SDHC_ABSFREQ is not set + +# +# Kinetis UART Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +CONFIG_ARCH_HAVE_RAMFUNCS=y +CONFIG_ARCH_RAMFUNCS=y +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=9535 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x1fff0000 +CONFIG_RAM_SIZE=262144 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_TWR_K64F120M=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="twr-k64f120m" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +# CONFIG_ARCH_BUTTONS is not set +CONFIG_ARCH_HAVE_IRQBUTTONS=y + +# +# Board-Specific Options +# +CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT=y +CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_FSTYPE="vfat" +CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_BLKDEV="/dev/mmcsd0" +CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_MOUNTPOINT="/mnt/sdcard" +CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_DDELAY=1000 +CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_UDELAY=2000 +# CONFIG_BOARD_CRASHDUMP is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2017 +CONFIG_START_MONTH=1 +CONFIG_START_DAY=23 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_SPINLOCK is not set +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=10 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 +# CONFIG_PTHREAD_CLEANUP is not set +# CONFIG_CANCELLATION_POINTS is not set + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set +# CONFIG_SPI is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +CONFIG_MMCSD=y +CONFIG_MMCSD_NSLOTS=1 +# CONFIG_MMCSD_READONLY is not set +# CONFIG_MMCSD_MULTIBLOCK_DISABLE is not set +CONFIG_MMCSD_MMCSUPPORT=y +CONFIG_MMCSD_HAVECARDDETECT=y +CONFIG_ARCH_HAVE_SDIO=y +# CONFIG_SDIO_DMA is not set +# CONFIG_ARCH_HAVE_SDIOWAIT_WRCOMPLETE is not set +CONFIG_MMCSD_SDIO=y +# CONFIG_SDIO_PREFLIGHT is not set +# CONFIG_SDIO_MUXBUS is not set +# CONFIG_SDIO_WIDTH_D1_ONLY is not set +# CONFIG_SDIO_BLOCKSETUP is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +CONFIG_UART1_SERIALDRIVER=y +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +CONFIG_UART1_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART1 Configuration +# +CONFIG_UART1_RXBUFSIZE=256 +CONFIG_UART1_TXBUFSIZE=256 +CONFIG_UART1_BAUD=115200 +CONFIG_UART1_BITS=8 +CONFIG_UART1_PARITY=0 +CONFIG_UART1_2STOP=0 +# CONFIG_UART1_IFLOWCONTROL is not set +# CONFIG_UART1_OFLOWCONTROL is not set +# CONFIG_UART1_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +CONFIG_FS_AUTOMOUNTER=y +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_PSEUDOFS_SOFTLINKS is not set +CONFIG_FS_READABLE=y +CONFIG_FS_WRITABLE=y +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +CONFIG_FS_FAT=y +# CONFIG_FAT_LCNAMES is not set +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=32 +# CONFIG_FS_FATTIME is not set +# CONFIG_FAT_FORCE_INDIRECT is not set +# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FAT_DIRECT_RETRY is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +CONFIG_FS_PROCFS=y +# CONFIG_FS_PROCFS_REGISTER is not set + +# +# Exclude individual procfs entries +# +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_BUILTIN is not set +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# + +# +# Standard C I/O +# +# CONFIG_STDIO_DISABLE_BUFFERING is not set +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_SCANSET is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_MEMCPY_VIK is not set +# CONFIG_LIBM is not set + +# +# Architecture-Specific Support +# +CONFIG_ARCH_LOWPUTC=y +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_LIBC_ARCH_MEMCPY is not set +# CONFIG_LIBC_ARCH_MEMCMP is not set +# CONFIG_LIBC_ARCH_MEMMOVE is not set +# CONFIG_LIBC_ARCH_MEMSET is not set +# CONFIG_LIBC_ARCH_STRCHR is not set +# CONFIG_LIBC_ARCH_STRCMP is not set +# CONFIG_LIBC_ARCH_STRCPY is not set +# CONFIG_LIBC_ARCH_STRNCPY is not set +# CONFIG_LIBC_ARCH_STRLEN is not set +# CONFIG_LIBC_ARCH_STRNLEN is not set +# CONFIG_LIBC_ARCH_ELF is not set +# CONFIG_ARMV7M_MEMCPY is not set + +# +# stdlib Options +# +CONFIG_LIB_RAND_ORDER=1 +CONFIG_LIB_HOMEDIR="/" +CONFIG_LIBC_TMPDIR="/tmp" +CONFIG_LIBC_MAX_TMPFILE=32 + +# +# Program Execution Options +# +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 + +# +# errno Decode Support +# +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set + +# +# memcpy/memset Options +# +# CONFIG_MEMSET_OPTSPEED is not set +# CONFIG_LIBC_DLLFCN is not set +# CONFIG_LIBC_MODLIB is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set + +# +# Time/Time Zone Support +# +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_ARCH_HAVE_TLS=y + +# +# Thread Local Storage (TLS) +# +# CONFIG_TLS is not set + +# +# Network-Related Options +# +# CONFIG_LIBC_IPv4_ADDRCONV is not set +# CONFIG_LIBC_IPv6_ADDRCONV is not set +# CONFIG_LIBC_NETDB is not set + +# +# NETDB Support +# +# CONFIG_NETDB_HOSTFILE is not set +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FSTEST is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_STAT is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set +# CONFIG_FSUTILS_PASSWD is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_BAS is not set +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +CONFIG_NSH_CMDPARMS=y +CONFIG_NSH_MAXARGUMENTS=6 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 + +# +# Configure Command Options +# +CONFIG_NSH_CMDOPT_DF_H=y +# CONFIG_NSH_CMDOPT_DD_STATS is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_CMDOPT_HEXDUMP=y +CONFIG_NSH_PROC_MOUNTPOINT="/proc" +CONFIG_NSH_FILEIOSIZE=512 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/twr-k64f120m/nsh/setenv.sh b/configs/twr-k64f120m/nsh/setenv.sh new file mode 100755 index 00000000000..7761313c011 --- /dev/null +++ b/configs/twr-k64f120m/nsh/setenv.sh @@ -0,0 +1,61 @@ +#!/bin/bash +# configs/twr-k64f120m/nsh/setenv.sh +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" +echo "PATH : ${PATH}" diff --git a/configs/twr-k64f120m/scripts/ld.script b/configs/twr-k64f120m/scripts/ld.script new file mode 100644 index 00000000000..9ddd83ff6c5 --- /dev/null +++ b/configs/twr-k64f120m/scripts/ld.script @@ -0,0 +1,142 @@ +/**************************************************************************** + * configs/twr-k64f120m/scripts/ld.script + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The MK64FN1M0VMD12 has 1MB of FLASH beginning at address 0x0000:0000 and + * 256KB of SRAM beginning at address 0x1fff:0000 (SRAM_L 64KB) and 0x2000:0000 + * (SRAM_U 192KB). + * + * NOTE: that the first part of the K64 FLASH region is reserved for + * interrupt vectflash and, following that, is a region from 0x0000:0400 + * to 0x0000:040f that is reserved for the FLASH control fields (FCF). + * + * NOTE: The on-chip RAM is split evenly among SRAM_L and SRAM_U. The RAM is + * also implemented such that the SRAM_L and SRAM_U ranges form a + * contiguous block in the memory map. + */ + +MEMORY +{ + vectflash (rx) : ORIGIN = 0x00000000, LENGTH = 1K + cfmprotect (rx) : ORIGIN = 0x00000400, LENGTH = 16 + progflash (rx) : ORIGIN = 0x00000800, LENGTH = 1M - 2K + datasram (rwx) : ORIGIN = 0x1fff0000, LENGTH = 256K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +EXTERN(__flashconfigbytes) +SECTIONS +{ + .vectors : { + _svectors = ABSOLUTE(.); + *(.vectors) + _evectors = ABSOLUTE(.); + } > vectflash + + .cfmprotect : { + KEEP(*(.cfmconfig)) + } > cfmprotect + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > progflash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > progflash + + .ARM.extab : { + *(.ARM.extab*) + } > progflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > progflash + __exidx_end = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > datasram AT > progflash + + _eronly = LOADADDR(.data); + + .ramfunc ALIGN(4): { + _sramfuncs = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfuncs = ABSOLUTE(.); + } > datasram AT > progflash + + _framfuncs = LOADADDR(.ramfunc); + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > datasram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/twr-k64f120m/src/Makefile b/configs/twr-k64f120m/src/Makefile new file mode 100644 index 00000000000..7f9b0102208 --- /dev/null +++ b/configs/twr-k64f120m/src/Makefile @@ -0,0 +1,69 @@ +############################################################################ +# configs/twr-k64f120m/src/Makefile +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +#CSRCS = k64_boot.c k64_spi.c +CSRCS = k64_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += k64_leds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +#CSRCS += k64_buttons.c +endif + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += k64_appinit.c +endif + +ifeq ($(CONFIG_KINETIS_SDHC),y) +CSRCS += k64_sdhc.c +ifeq ($(CONFIG_FS_AUTOMOUNTER),y) +CSRCS += k64_automount.c +endif +endif + +ifeq ($(CONFIG_USBDEV),y) +#CSRCS += k64_usbdev.c +endif + +ifeq ($(CONFIG_USBMSC),y) +#CSRCS += k64_usbmsc.c +endif + +include $(TOPDIR)/configs/Board.mk diff --git a/configs/twr-k64f120m/src/k64_appinit.c b/configs/twr-k64f120m/src/k64_appinit.c new file mode 100644 index 00000000000..1c59c4aa2af --- /dev/null +++ b/configs/twr-k64f120m/src/k64_appinit.c @@ -0,0 +1,112 @@ +/**************************************************************************** + * config/twr-k64f120m/src/k64_appinit.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#ifdef CONFIG_KINETIS_SDHC +# include +# include +#endif + +#include "kinetis.h" +#include "twrk64.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ + int ret; + +#ifdef HAVE_PROC + /* Mount the proc filesystem */ + + syslog(LOG_INFO, "Mounting procfs to /proc\n"); + + ret = mount(NULL, PROCFS_MOUNTPOUNT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount the PROC filesystem: %d (%d)\n", + ret, errno); + return ret; + } +#endif + +#ifdef HAVE_MMCSD + /* Initialize the MMC/SD driver and possible automount */ + + return k64_sdhc_initialize(); +#endif + return OK; +} diff --git a/configs/twr-k64f120m/src/k64_automount.c b/configs/twr-k64f120m/src/k64_automount.c new file mode 100644 index 00000000000..5e0ddfb4659 --- /dev/null +++ b/configs/twr-k64f120m/src/k64_automount.c @@ -0,0 +1,311 @@ +/************************************************************************************ + * configs/twr-k64f120m/src/k64_automount.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#if defined(CONFIG_FS_AUTOMOUNTER_DEBUG) && !defined(CONFIG_DEBUG_FS) +# define CONFIG_DEBUG_FS 1 +#endif + +#include + +#include +#include +#include + +#include "twrk64.h" + +#ifdef HAVE_AUTOMOUNTER + +/************************************************************************************ + * Private Types + ************************************************************************************/ + +/* This structure represents the changeable state of the automounter */ + +struct k64_automount_state_s +{ + volatile automount_handler_t handler; /* Upper half handler */ + FAR void *arg; /* Handler argument */ + bool enable; /* Fake interrupt enable */ + bool pending; /* Set if there an event while disabled */ +}; + +/* This structure represents the static configuration of an automounter */ + +struct k64_automount_config_s +{ + /* This must be first thing in structure so that we can simply cast from struct + * automount_lower_s to struct k64_automount_config_s + */ + + struct automount_lower_s lower; /* Publicly visible part */ + FAR struct k64_automount_state_s *state; /* Changeable state */ +}; + +/************************************************************************************ + * Private Function Prototypes + ************************************************************************************/ + +static int k64_attach(FAR const struct automount_lower_s *lower, + automount_handler_t isr, FAR void *arg); +static void k64_enable(FAR const struct automount_lower_s *lower, bool enable); +static bool k64_inserted(FAR const struct automount_lower_s *lower); + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +static struct k64_automount_state_s g_sdhc_state; +static const struct k64_automount_config_s g_sdhc_config = +{ + .lower = + { + .fstype = CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_FSTYPE, + .blockdev = CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_BLKDEV, + .mountpoint = CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_MOUNTPOINT, + .ddelay = MSEC2TICK(CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_DDELAY), + .udelay = MSEC2TICK(CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_UDELAY), + .attach = k64_attach, + .enable = k64_enable, + .inserted = k64_inserted + }, + .state = &g_sdhc_state +}; + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: k64_attach + * + * Description: + * Attach a new SDHC event handler + * + * Input Parameters: + * lower - An instance of the auto-mounter lower half state structure + * isr - The new event handler to be attach + * arg - Client data to be provided when the event handler is invoked. + * + * Returned Value: + * Always returns OK + * + ************************************************************************************/ + +static int k64_attach(FAR const struct automount_lower_s *lower, + automount_handler_t isr, FAR void *arg) +{ + FAR const struct k64_automount_config_s *config; + FAR struct k64_automount_state_s *state; + + /* Recover references to our structure */ + + config = (FAR struct k64_automount_config_s *)lower; + DEBUGASSERT(config != NULL && config->state != NULL); + + state = config->state; + + /* Save the new handler info (clearing the handler first to eliminate race + * conditions). + */ + + state->handler = NULL; + state->pending = false; + state->arg = arg; + state->handler = isr; + return OK; +} + +/************************************************************************************ + * Name: k64_enable + * + * Description: + * Enable card insertion/removal event detection + * + * Input Parameters: + * lower - An instance of the auto-mounter lower half state structure + * enable - True: enable event detection; False: disable + * + * Returned Value: + * None + * + ************************************************************************************/ + +static void k64_enable(FAR const struct automount_lower_s *lower, bool enable) +{ + FAR const struct k64_automount_config_s *config; + FAR struct k64_automount_state_s *state; + irqstate_t flags; + + /* Recover references to our structure */ + + config = (FAR struct k64_automount_config_s *)lower; + DEBUGASSERT(config != NULL && config->state != NULL); + + state = config->state; + + /* Save the fake enable setting */ + + flags = enter_critical_section(); + state->enable = enable; + + /* Did an interrupt occur while interrupts were disabled? */ + + if (enable && state->pending) + { + /* Yes.. perform the fake interrupt if the interrutp is attached */ + + if (state->handler) + { + bool inserted = k64_cardinserted(); + (void)state->handler(&config->lower, state->arg, inserted); + } + + state->pending = false; + } + + leave_critical_section(flags); +} + +/************************************************************************************ + * Name: k64_inserted + * + * Description: + * Check if a card is inserted into the slot. + * + * Input Parameters: + * lower - An instance of the auto-mounter lower half state structure + * + * Returned Value: + * True if the card is inserted; False otherwise + * + ************************************************************************************/ + +static bool k64_inserted(FAR const struct automount_lower_s *lower) +{ + return k64_cardinserted(); +} + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: k64_automount_initialize + * + * Description: + * Configure auto-mounters for each enable and so configured SDHC + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ************************************************************************************/ + +void k64_automount_initialize(void) +{ + FAR void *handle; + + finfo("Initializing automounter(s)\n"); + + /* Initialize the SDHC0 auto-mounter */ + + handle = automount_initialize(&g_sdhc_config.lower); + if (!handle) + { + ferr("ERROR: Failed to initialize auto-mounter for SDHC0\n"); + } +} + +/************************************************************************************ + * Name: k64_automount_event + * + * Description: + * The SDHC card detection logic has detected an insertion or removal event. It + * has already scheduled the MMC/SD block driver operations. Now we need to + * schedule the auto-mount event which will occur with a substantial delay to make + * sure that everything has settle down. + * + * Input Parameters: + * slotno - Identifies the SDHC0 slot: SDHC0_SLOTNO or SDHC1_SLOTNO. There is a + * terminology problem here: Each SDHC supports two slots, slot A and slot B. + * Only slot A is used. So this is not a really a slot, but an HSCMI peripheral + * number. + * inserted - True if the card is inserted in the slot. False otherwise. + * + * Returned Value: + * None + * + * Assumptions: + * Interrupts are disabled. + * + ************************************************************************************/ + +void k64_automount_event(bool inserted) +{ + FAR const struct k64_automount_config_s *config = &g_sdhc_config; + FAR struct k64_automount_state_s *state = &g_sdhc_state; + + /* Is the auto-mounter interrupt attached? */ + + if (state->handler) + { + /* Yes.. Have we been asked to hold off interrupts? */ + + if (!state->enable) + { + /* Yes.. just remember the there is a pending interrupt. We will + * deliver the interrupt when interrupts are "re-enabled." + */ + + state->pending = true; + } + else + { + /* No.. forward the event to the handler */ + + (void)state->handler(&config->lower, state->arg, inserted); + } + } +} + +#endif /* HAVE_AUTOMOUNTER */ diff --git a/configs/twr-k64f120m/src/k64_boot.c b/configs/twr-k64f120m/src/k64_boot.c new file mode 100644 index 00000000000..b185423ed23 --- /dev/null +++ b/configs/twr-k64f120m/src/k64_boot.c @@ -0,0 +1,102 @@ +/************************************************************************************ + * configs/twr-k64f120m/src/k64_boot.c + * + * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_arch.h" +#include "twrk64.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: kinetis_boardinitialize + * + * Description: + * All Kinetis architectures must provide the following entry point. This entry + * point is called early in the initialization -- after all memory has been + * configured and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void kinetis_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function + * kinetis_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_KINETIS_SPI1) || defined(CONFIG_KINETIS_SPI2) + if (kinetis_spidev_initialize) + { + kinetis_spidev_initialize(); + } +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function kinetis_usbinitialize() has been brought + * into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_KINETIS_USB) + if (kinetis_usbinitialize) + { + kinetis_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} diff --git a/configs/twr-k64f120m/src/k64_leds.c b/configs/twr-k64f120m/src/k64_leds.c new file mode 100644 index 00000000000..ec120b4faf5 --- /dev/null +++ b/configs/twr-k64f120m/src/k64_leds.c @@ -0,0 +1,250 @@ +/**************************************************************************** + * configs/twr-k64f120m/src/k64_leds.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "kinetis.h" +#include "twrk64.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The TWR-K64F120M has four LEDs: + * + * 1. D5 / Green LED PTE6 + * 2. D6 / Yellow LED PTE7 + * 3. D7 / Orange LED PTE8 + * 4 D9 / Blue LED PTE9 + * + * LED4 is reservered for user. + */ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define K64_LED1 (1 << 0) +#define K64_LED2 (1 << 1) +#define K64_LED3 (1 << 2) +// #define K64_LED4 (1 << 3) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +#define LED_STARTED_ON_SETBITS (0 << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS (0 << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS (0 << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS (0 << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS (0 << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS (0 << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS (0 << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS (0 << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS (0 << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS (K64_LED1 << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS (0 << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS (0 << OFF_CLRBITS_SHIFT) + +#define LED_INIRQ_ON_SETBITS (K64_LED2 << ON_SETBITS_SHIFT) +#define LED_INIRQ_ON_CLRBITS (0 << ON_CLRBITS_SHIFT) +#define LED_INIRQ_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_INIRQ_OFF_CLRBITS (K64_LED2 << OFF_CLRBITS_SHIFT) + +#define LED_SIGNAL_ON_SETBITS (K64_LED3 << ON_SETBITS_SHIFT) +#define LED_SIGNAL_ON_CLRBITS (0 << ON_CLRBITS_SHIFT) +#define LED_SIGNAL_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_SIGNAL_OFF_CLRBITS (K64_LED3 << OFF_CLRBITS_SHIFT) + +#define LED_ASSERTION_ON_SETBITS ((K64_LED1|K64_LED2|K64_LED3) << ON_SETBITS_SHIFT) +#define LED_ASSERTION_ON_CLRBITS (0 << ON_CLRBITS_SHIFT) +#define LED_ASSERTION_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_ASSERTION_OFF_CLRBITS (0 << OFF_CLRBITS_SHIFT) + +#define LED_PANIC_ON_SETBITS (K64_LED1 << ON_SETBITS_SHIFT) +#define LED_PANIC_ON_CLRBITS (0 << ON_CLRBITS_SHIFT) +#define LED_PANIC_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_PANIC_OFF_CLRBITS (K64_LED1 << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + + (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + + (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + + (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & K64_LED1) != 0) + { + kinetis_gpiowrite(GPIO_LED1, true); + } + + if ((clrbits & K64_LED2) != 0) + { + kinetis_gpiowrite(GPIO_LED2, true); + } + + if ((clrbits & K64_LED3) != 0) + { + kinetis_gpiowrite(GPIO_LED3, true); + } + +} + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & K64_LED1) != 0) + { + kinetis_gpiowrite(GPIO_LED1, false); + } + + if ((setbits & K64_LED2) != 0) + { + kinetis_gpiowrite(GPIO_LED2, false); + } + + if ((setbits & K64_LED3) != 0) + { + kinetis_gpiowrite(GPIO_LED3, false); + } + +} + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + * + * Description: + * Initialize LED GPIOs so that LEDs can be controlled. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_initialize(void) +{ + /* Configure LED1-3 GPIOs for output */ + + kinetis_pinconfig(GPIO_LED1); + kinetis_pinconfig(GPIO_LED2); + kinetis_pinconfig(GPIO_LED3); +} + +/**************************************************************************** + * Name: board_autoled_on + * + * Description: + * Puts on the relevants LEDs for one of the LED_condition (see board.h) + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + * + * Description: + * Puts off the relevants LEDs for one of the LED_condition (see board.h) + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/twr-k64f120m/src/k64_sdhc.c b/configs/twr-k64f120m/src/k64_sdhc.c new file mode 100644 index 00000000000..36896e410d5 --- /dev/null +++ b/configs/twr-k64f120m/src/k64_sdhc.c @@ -0,0 +1,254 @@ +/**************************************************************************** + * config/twr-k64f120m/src/k64_sdhc.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* A micro Secure Digital (SD) card slot is available on the FRDM-K64F connected to + * the SD Host Controller (SDHC) signals of the MCU. This slot will accept micro + * format SD memory cards. The SD card detect pin (PTE6) is an open switch that + * shorts with VDD when card is inserted. + * + * ------------ ------------- -------- + * SD Card Slot Board Signal K64F Pin + * ------------ ------------- -------- + * DAT0 SDHC0_D0 PTE0 + * DAT1 SDHC0_D1 PTE1 + * DAT2 SDHC0_D2 PTE5 + * CD/DAT3 SDHC0_D3 PTE4 + * CMD SDHC0_CMD PTE3 + * CLK SDHC0_DCLK PTE2 + * SWITCH D_CARD_DETECT PTE6 + * ------------ ------------- -------- + * + * There is no Write Protect pin available to the K64F. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "kinetis.h" + +#include "twrk64.h" + +#ifdef HAVE_MMCSD + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure holds static information unique to one SDHC peripheral */ + +struct k64_sdhc_state_s +{ + struct sdio_dev_s *sdhc; /* R/W device handle */ + bool inserted; /* TRUE: card is inserted */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* HSCMI device state */ + +static struct k64_sdhc_state_s g_sdhc; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: k64_mediachange + ****************************************************************************/ + +static void k64_mediachange(void) +{ + bool inserted; + + /* Get the current value of the card detect pin. This pin is pulled up on + * board. So low means that a card is present. + */ + + inserted = !kinetis_gpioread(GPIO_SD_CARDDETECT); + mcinfo("inserted: %s\n", inserted ? "Yes" : "No"); + + /* Has the pin changed state? */ + + if (inserted != g_sdhc.inserted) + { + mcinfo("Media change: %d->%d\n", g_sdhc.inserted, inserted); + + /* Yes.. perform the appropriate action (this might need some debounce). */ + + g_sdhc.inserted = inserted; + sdhc_mediachange(g_sdhc.sdhc, inserted); + +#ifdef CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT + /* Let the automounter know about the insertion event */ + + k64_automount_event(k64_cardinserted()); +#endif + } +} + +/**************************************************************************** + * Name: k64_cdinterrupt + ****************************************************************************/ + +static int k64_cdinterrupt(int irq, FAR void *context, FAR void *arg) +{ + /* All of the work is done by k64_mediachange() */ + + k64_mediachange(); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: k64_sdhc_initialize + * + * Description: + * Inititialize the SDHC SD card slot + * + ****************************************************************************/ + +int k64_sdhc_initialize(void) +{ + int ret; + + /* Configure GPIO pins */ + + kinetis_pinconfig(GPIO_SD_CARDDETECT); + + /* Attached the card detect interrupt (but don't enable it yet) */ + + kinetis_pinirqattach(GPIO_SD_CARDDETECT, k64_cdinterrupt, NULL); + + /* Configure the write protect GPIO -- None */ + + /* Mount the SDHC-based MMC/SD block driver */ + /* First, get an instance of the SDHC interface */ + + mcinfo("Initializing SDHC slot %d\n", MMCSD_SLOTNO); + + g_sdhc.sdhc = sdhc_initialize(MMCSD_SLOTNO); + if (!g_sdhc.sdhc) + { + mcerr("ERROR: Failed to initialize SDHC slot %d\n", MMCSD_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDHC interface to the MMC/SD driver */ + + mcinfo("Bind SDHC to the MMC/SD driver, minor=%d\n", MMSCD_MINOR); + + ret = mmcsd_slotinitialize(MMSCD_MINOR, g_sdhc.sdhc); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to bind SDHC to the MMC/SD driver: %d\n", ret); + return ret; + } + + syslog(LOG_INFO, "Successfully bound SDHC to the MMC/SD driver\n"); + + /* Handle the initial card state */ + + k64_mediachange(); + + /* Enable CD interrupts to handle subsequent media changes */ + + kinetis_pinirqenable(GPIO_SD_CARDDETECT); + + /* Initialize automount system if configured */ +#ifdef CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT + k64_automount_initialize(); +#endif + + return OK; +} + +/**************************************************************************** + * Name: k64_cardinserted + * + * Description: + * Check if a card is inserted into the SDHC slot + * + ****************************************************************************/ + +#ifdef HAVE_AUTOMOUNTER +bool k64_cardinserted(void) +{ + bool inserted; + + /* Get the current value of the card detect pin. This pin is pulled up on + * board. So low means that a card is present. + */ + + inserted = !kinetis_gpioread(GPIO_SD_CARDDETECT); + mcinfo("inserted: %s\n", inserted ? "Yes" : "No"); + return inserted; +} +#endif + +/**************************************************************************** + * Name: k64_writeprotected + * + * Description: + * Check if a card is inserted into the SDHC slot + * + ****************************************************************************/ + +#ifdef HAVE_AUTOMOUNTER +bool k64_writeprotected(void) +{ + /* There are no write protect pins */ + + return false; +} +#endif + +#endif /* HAVE_MMCSD */ diff --git a/configs/twr-k64f120m/src/twrk64.h b/configs/twr-k64f120m/src/twrk64.h new file mode 100644 index 00000000000..5de682600e8 --- /dev/null +++ b/configs/twr-k64f120m/src/twrk64.h @@ -0,0 +1,388 @@ +/************************************************************************************ + * configs/twr-k64f120m/src/twrk64.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Marc Rechte + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * This header file is only accessible from the src directory. + * For /arch/arm/src accessibilty use ../include/board.h instead. + ************************************************************************************/ + +#ifndef __CONFIGS_TWR_K64F120M_SRC_TWRK64_H +#define __CONFIGS_TWR_K64F120M_SRC_TWRK64_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Assume we have everything */ + +#define HAVE_PROC 1 +#define HAVE_MMCSD 1 +#define HAVE_AUTOMOUNTER 1 +#define HAVE_USBDEV 1 + +#if defined(CONFIG_KINETIS_RTC) +#define HAVE_RTC_DRIVER 1 +#endif + +/* Automount procfs */ + +#if !defined(CONFIG_FS_PROCFS) +# undef HAVE_PROC +#endif + +#if defined(HAVE_PROC) && defined(CONFIG_DISABLE_MOUNTPOINT) +# warning Mountpoints disabled. No procfs support +# undef HAVE_PROC +#endif + +#if defined(CONFIG_NSH_PROC_MOUNTPOINT) +# define PROCFS_MOUNTPOUNT CONFIG_NSH_PROC_MOUNTPOINT +#else +# define PROCFS_MOUNTPOUNT "/proc" +#endif + +/* SD card support */ + +#define MMCSD_SLOTNO 0 + +/* Can't support MMC/SD features if mountpoints are disabled or if SDHC support + * is not enabled. + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_KINETIS_SDHC) +# undef HAVE_MMCSD +#endif + +#ifdef HAVE_MMCSD +# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 +# error Only one MMC/SD slot, slot 0 +# endif + +# ifdef CONFIG_NSH_MMCSDMINOR +# define MMSCD_MINOR CONFIG_NSH_MMCSDMINOR +# else +# define MMSCD_MINOR 0 +# endif + +/* We expect to receive GPIO interrupts for card insertion events */ + +# ifndef CONFIG_KINETIS_GPIOIRQ +# error "CONFIG_KINETIS_GPIOIRQ required for card detect interrupt" +# endif + +# ifndef CONFIG_KINETIS_PORTBINTS +# error "CONFIG_KINETIS_PORTBINTS required for card detect interrupt" +# endif + +#endif + +/* Automounter */ + +#if !defined(CONFIG_FS_AUTOMOUNTER) || !defined(HAVE_MMCSD) +# undef HAVE_AUTOMOUNTER +# undef CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT +#endif + +#ifndef CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT +# undef HAVE_AUTOMOUNTER +#endif + +/* Automounter defaults */ + +#ifdef HAVE_AUTOMOUNTER + +# ifndef CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_FSTYPE +# define CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_FSTYPE "vfat" +# endif + +# ifndef CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_BLKDEV +# define CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_BLKDEV "/dev/mmcds0" +# endif + +# ifndef CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_MOUNTPOINT +# define CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_MOUNTPOINT "/mnt/sdcard" +# endif + +# ifndef CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_DDELAY +# define CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_DDELAY 1000 +# endif + +# ifndef CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_UDELAY +# define CONFIG_TWR_K64F120M_SDHC_AUTOMOUNT_UDELAY 2000 +# endif +#endif /* HAVE_AUTOMOUNTER */ + +/* Can't support USB features if USB is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +#endif + +/* How many SPI modules does this chip support? The LM3S6918 supports 2 SPI + * modules (others may support more -- in such case, the following must be + * expanded). + */ + +#if KINETIS_NSPI < 1 +# undef CONFIG_KINETIS_SPI1 +# undef CONFIG_KINETIS_SPI2 +#elif KINETIS_NSPI < 2 +# undef CONFIG_KINETIS_SPI2 +#endif + +/* Button definitions ***************************************************************/ +/* The TWR-K64F120M has 2 user buttons (plus a reset button): + * + * 1. SW1 (IRQ?) PTC6 + * 2. SW3 (IRQ?) PTA4 + */ + +#define BUTTON_SW1 0 +#define BUTTON_SW3 1 + +#define BUTTON_SW1_BIT (1 << BUTTON_SW1) +#define BUTTON_SW3_BIT (1 << BUTTON_SW3) + +/* Alternative pin resolution *******************************************************/ +/* If there are alternative configurations for various pins in the + * kinetis_k64pinmux.h header file, those alternative pins will be labeled with a + * suffix like _1, _2, etc. The logic in this file must select the correct pin + * configuration for the board by defining a pin configuration (with no suffix) that + * maps to the correct alternative. + * Please refer to board README for pin explanation. + */ + +#if 0 +#define PIN_I2C0_SDA PIN_I2C0_SDA_3 +#define PIN_I2C0_SCL PIN_I2C0_SCL_3 + +/* Connections via the General Purpose Tower Plug-in (TWRPI) Socket +TODO See README + */ + +#define PIN_SPI2_SIN PIN_SPI2_SIN_2 +#define PIN_SPI2_SOUT PIN_SPI2_SOUT_2 +#define PIN_SPI2_SCK PIN_SPI2_SCK_2 + +/* Connections via the Tower Primary Connector Side A +TODO See README + */ + +/* PTE 26/27 */ + +#define PIN_UART3_RX PIN_UART3_RX_2 +#define PIN_UART3_TX PIN_UART3_TX_2 + +/* PTE 24/25 */ + +#define PIN_UART4_RX PIN_UART4_RX_2 +#define PIN_UART4_TX PIN_UART4_TX_2 + +/* Connections via the Tower Primary Connector Side B +TODO See README + */ +#endif + +/* SDHC + important notice: on TWR-K64F120M, R521 (close to the SD card holder) is not placed, + hence WRPROTEC is always ON. Either place a 4.7KOhm resistor or change PIN config + to PULLDOWN, loosing Write Protect function */ + +#define GPIO_SD_CARDDETECT (GPIO_PULLUP | PIN_INT_BOTH | PIN_PORTB | PIN20) +#define GPIO_SD_WRPROTECT (GPIO_PULLUP | PIN_PORTB | PIN21) + +/* SW */ + +#define GPIO_SW1 (GPIO_PULLUP | PIN_INT_BOTH | PIN_PORTC | PIN6) +#define GPIO_SW3 (GPIO_PULLUP | PIN_INT_BOTH | PIN_PORTA | PIN4) + +/* LEDs. Note that LED1-3 are used by system, LED4 is for user defined apps. */ + +#define GPIO_LED1 (GPIO_LOWDRIVE | GPIO_OUTPUT_ZER0 | PIN_PORTE | PIN6) +#define GPIO_LED2 (GPIO_LOWDRIVE | GPIO_OUTPUT_ZER0 | PIN_PORTE | PIN7) +#define GPIO_LED3 (GPIO_LOWDRIVE | GPIO_OUTPUT_ZER0 | PIN_PORTE | PIN8) +#define GPIO_LED4 (GPIO_LOWDRIVE | GPIO_OUTPUT_ZER0 | PIN_PORTE | PIN9) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: k64_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the TWR-K64F120M board. + * + ************************************************************************************/ + +void weak_function k64_spidev_initialize(void); + +/************************************************************************************ + * Name: k64_usbinitialize + * + * Description: + * Called to setup USB-related GPIO pins for the TWR-K64F120M board. + * + ************************************************************************************/ + +void weak_function k64_usbinitialize(void); + +/************************************************************************************ + * Name: k64_bringup + * + * Description: + * Bring up board features + * + ************************************************************************************/ + +#if defined(CONFIG_LIB_BOARDCTL) || defined(CONFIG_BOARD_INITIALIZE) +int k64_bringup(void); +#endif + +/**************************************************************************** + * Name: k64_sdhc_initialize + * + * Description: + * Inititialize the SDHC SD card slot + * + ****************************************************************************/ + +#ifdef HAVE_MMCSD +int k64_sdhc_initialize(void); +#else +# define k64_sdhc_initialize() (OK) +#endif + +/************************************************************************************ + * Name: k64_cardinserted + * + * Description: + * Check if a card is inserted into the SDHC slot + * + ************************************************************************************/ + +#ifdef HAVE_AUTOMOUNTER +bool k64_cardinserted(void); +#else +# define k64_cardinserted() (false) +#endif + +/************************************************************************************ + * Name: k64_writeprotected + * + * Description: + * Check if the card in the MMC/SD slot is write protected + * + ************************************************************************************/ + +#ifdef HAVE_AUTOMOUNTER +bool k64_writeprotected(void); +#else +# define k64_writeprotected() (false) +#endif + +/************************************************************************************ + * Name: k64_automount_initialize + * + * Description: + * Configure auto-mounter for the configured SDHC slot + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ************************************************************************************/ + +#ifdef HAVE_AUTOMOUNTER +void k64_automount_initialize(void); +#endif + +/************************************************************************************ + * Name: k64_automount_event + * + * Description: + * The SDHC card detection logic has detected an insertion or removal event. It + * has already scheduled the MMC/SD block driver operations. Now we need to + * schedule the auto-mount event which will occur with a substantial delay to make + * sure that everything has settle down. + * + * Input Parameters: + * inserted - True if the card is inserted in the slot. False otherwise. + * + * Returned Value: + * None + * + * Assumptions: + * Interrupts are disabled. + * + ************************************************************************************/ + +#ifdef HAVE_AUTOMOUNTER +void k64_automount_event(bool inserted); +#endif + +/************************************************************************************ + * Name: k64_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int k64_pwm_setup(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_TWR_K64F120M_SRC_TWRK64_H */ diff --git a/configs/ubw32/src/pic32_buttons.c b/configs/ubw32/src/pic32_buttons.c index 290832c3690..dec8fe416eb 100644 --- a/configs/ubw32/src/pic32_buttons.c +++ b/configs/ubw32/src/pic32_buttons.c @@ -181,7 +181,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; diff --git a/configs/viewtool-stm32f107/src/stm32_buttons.c b/configs/viewtool-stm32f107/src/stm32_buttons.c index cff85be4c6e..97b02d1c5c3 100644 --- a/configs/viewtool-stm32f107/src/stm32_buttons.c +++ b/configs/viewtool-stm32f107/src/stm32_buttons.c @@ -152,7 +152,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t oldhandler = NULL; @@ -160,7 +160,8 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler); + oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); } return oldhandler; diff --git a/configs/viewtool-stm32f107/src/stm32_touchscreen.c b/configs/viewtool-stm32f107/src/stm32_touchscreen.c index 6abba71e5cd..8d6bc3c2593 100644 --- a/configs/viewtool-stm32f107/src/stm32_touchscreen.c +++ b/configs/viewtool-stm32f107/src/stm32_touchscreen.c @@ -201,13 +201,15 @@ static void tsc_enable(FAR struct ads7843e_config_s *state, bool enable) { /* Configure the EXTI interrupt using the SAVED handler */ - (void)stm32_gpiosetevent(GPIO_LCDTP_IRQ, true, true, true, priv->handler); + (void)stm32_gpiosetevent(GPIO_LCDTP_IRQ, true, true, true, + priv->handler, NULL); } else { /* Configure the EXTI interrupt with a NULL handler to disable it */ - (void)stm32_gpiosetevent(GPIO_LCDTP_IRQ, false, false, false, NULL); + (void)stm32_gpiosetevent(GPIO_LCDTP_IRQ, false, false, false, + NULL, NULL); } leave_critical_section(flags); diff --git a/configs/xtrs/src/xtr_irq.c b/configs/xtrs/src/xtr_irq.c index fb9890390ab..5cc00da9503 100644 --- a/configs/xtrs/src/xtr_irq.c +++ b/configs/xtrs/src/xtr_irq.c @@ -70,7 +70,7 @@ void up_irqinitialize(void) * xtrs_timer_initialize() */ - irq_attach(Z80_IRQ_SYSTIMER, (xcpt_t)xtrs_timerisr); + irq_attach(Z80_IRQ_SYSTIMER, (xcpt_t)xtrs_timerisr, NULL); /* And finally, enable interrupts (including the timer) */ diff --git a/configs/xtrs/src/xtr_timerisr.c b/configs/xtrs/src/xtr_timerisr.c index 5c12e6630c9..c05c661b35e 100644 --- a/configs/xtrs/src/xtr_timerisr.c +++ b/configs/xtrs/src/xtr_timerisr.c @@ -59,7 +59,7 @@ * ****************************************************************************/ -int xtrs_timerisr(int irq, FAR chipreg_t *regs) +int xtrs_timerisr(int irq, FAR chipreg_t *regs, FAR void *arg) { /* Process timer interrupt */ diff --git a/configs/z80sim/src/z80_irq.c b/configs/z80sim/src/z80_irq.c index b1fa22dc4cb..27f3c393e97 100644 --- a/configs/z80sim/src/z80_irq.c +++ b/configs/z80sim/src/z80_irq.c @@ -70,7 +70,7 @@ void up_irqinitialize(void) * z80sim_timer_initialize() */ - irq_attach(Z80_IRQ_SYSTIMER, (xcpt_t)z80sim_timerisr); + irq_attach(Z80_IRQ_SYSTIMER, (xcpt_t)z80sim_timerisr, NULL); /* And finally, enable interrupts (including the timer) */ diff --git a/configs/z80sim/src/z80_timerisr.c b/configs/z80sim/src/z80_timerisr.c index cd0bb57292b..a230652d5cc 100644 --- a/configs/z80sim/src/z80_timerisr.c +++ b/configs/z80sim/src/z80_timerisr.c @@ -59,7 +59,7 @@ * ****************************************************************************/ -int z80sim_timerisr(int irq, FAR chipreg_t *regs) +int z80sim_timerisr(int irq, FAR chipreg_t *regs, void *arg) { /* Process timer interrupt */ diff --git a/configs/zkit-arm-1769/src/lpc17_buttons.c b/configs/zkit-arm-1769/src/lpc17_buttons.c index 205473b2132..24d60216938 100644 --- a/configs/zkit-arm-1769/src/lpc17_buttons.c +++ b/configs/zkit-arm-1769/src/lpc17_buttons.c @@ -160,7 +160,7 @@ uint8_t board_buttons(void) ************************************************************************************/ #if defined CONFIG_ARCH_IRQBUTTONS && CONFIG_LPC17_GPIOIRQ -xcpt_t board_button_irq(int id, xcpt_t irqhandler) +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) { xcpt_t rethandler = NULL; irqstate_t flags; @@ -186,7 +186,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler) /* Attach the new interrupt handler and enable the interrupt */ - ret = irq_attach(ZKITARM_KEY5_IRQ, irqhandler); + ret = irq_attach(ZKITARM_KEY5_IRQ, irqhandler, NULL); if (ret == OK) { up_enable_irq(ZKITARM_KEY5_IRQ); diff --git a/drivers/Kconfig b/drivers/Kconfig index 740602b9f25..6dc2c875a86 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -337,14 +337,6 @@ if I2C source drivers/i2c/Kconfig endif -menuconfig SPI - bool "SPI Driver Support" - default n - ---help--- - This selection enables selection of common SPI options. This option - should be enabled by all platforms that support SPI interfaces. - See include/nuttx/spi/spi.h for further SPI driver information. - source drivers/spi/Kconfig menuconfig I2S diff --git a/drivers/analog/ad5410.c b/drivers/analog/ad5410.c index 1608fc0689f..679edf2c5f2 100644 --- a/drivers/analog/ad5410.c +++ b/drivers/analog/ad5410.c @@ -97,7 +97,7 @@ static void dac_shutdown(FAR struct dac_dev_s *dev); static void dac_txint(FAR struct dac_dev_s *dev, bool enable); static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg); static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg); -static int dac_interrupt(int irq, void *context); +static int dac_interrupt(int irq, void *context, FAR void *arg); /**************************************************************************** * ad_private Data diff --git a/drivers/analog/ads1255.c b/drivers/analog/ads1255.c index 30810c2f69f..94b278de096 100644 --- a/drivers/analog/ads1255.c +++ b/drivers/analog/ads1255.c @@ -148,7 +148,7 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg); /* Interrupt handling */ static void adc_worker(FAR void *arg); -static int adc_interrupt(int irq, void *context); +static int adc_interrupt(int irq, void *context, FAR void *arg); /**************************************************************************** * Private Data @@ -312,7 +312,7 @@ static int adc_setup(FAR struct adc_dev_s *dev) DEBUGASSERT(priv != NULL && priv->spi != NULL); spi = priv->spi; - ret = irq_attach(priv->irq, adc_interrupt); + ret = irq_attach(priv->irq, adc_interrupt, NULL); if (ret == OK) { adc_lock(spi); @@ -473,7 +473,7 @@ static void adc_worker(FAR void *arg) * ****************************************************************************/ -static int adc_interrupt(int irq, void *context) +static int adc_interrupt(int irq, void *context, FAR void *arg) { FAR struct ads1255_dev_s *priv = (FAR struct ads1255_dev_s *)g_adcdev.ad_priv; diff --git a/drivers/audio/Kconfig b/drivers/audio/Kconfig index 20664dbe2b3..ade8bc93756 100644 --- a/drivers/audio/Kconfig +++ b/drivers/audio/Kconfig @@ -36,11 +36,11 @@ config AUDIO_I2SCHAR_TXTIMEOUT endif # AUDIO_I2SCHAR config AUDIO_TONE - bool "Audio Tone Generator using PWM" - default n - depends on PWM && AUDIO_DEVICES - ---help--- - This driver enables the Audio Tone Generator for NuttX. + bool "Audio Tone Generator using PWM" + default n + depends on PWM && AUDIO_DEVICES + ---help--- + This driver enables the Audio Tone Generator for NuttX. if AUDIO_TONE diff --git a/drivers/audio/tone.c b/drivers/audio/tone.c index 93d5324e902..f9b5393f73b 100644 --- a/drivers/audio/tone.c +++ b/drivers/audio/tone.c @@ -94,6 +94,9 @@ struct tone_upperhalf_s { uint8_t crefs; /* The number of times the device has been * opened */ +#ifdef CONFIG_PWM_MULTICHAN + uint8_t channel; /* Output channel that drives the tone. */ +#endif volatile bool started; /* True: pulsed output is being generated */ sem_t exclsem; /* Supports mutual exclusion */ struct pwm_info_s tone; /* Pulsed output for Audio Tone */ @@ -146,6 +149,19 @@ static bool g_repeat; * Private Function Prototypes ****************************************************************************/ +static void oneshot_callback(FAR struct oneshot_lowerhalf_s *lower, + FAR void *arg); +static uint32_t note_duration(FAR uint32_t *silence, uint32_t note_length, + uint32_t dots); +static uint32_t rest_duration(uint32_t rest_length, uint32_t dots); +static void start_note(FAR struct tone_upperhalf_s *upper, uint8_t note); +static void stop_note(FAR struct tone_upperhalf_s *upper); +static void start_tune(FAR struct tone_upperhalf_s *upper, const char *tune); +static void next_note(FAR struct tone_upperhalf_s *upper); +static int next_char(void); +static uint8_t next_number(void); +static uint8_t next_dots(void); + static int tone_open(FAR struct file *filep); static int tone_close(FAR struct file *filep); static ssize_t tone_read(FAR struct file *filep, FAR char *buffer, @@ -153,10 +169,6 @@ static ssize_t tone_read(FAR struct file *filep, FAR char *buffer, static ssize_t tone_write(FAR struct file *filep, FAR const char *buffer, size_t buflen); -static int next_char(void); -static uint8_t next_number(void); -static uint8_t next_dots(void); -static void next_note(FAR struct tone_upperhalf_s *upper); /**************************************************************************** * Private Data @@ -294,12 +306,17 @@ static void start_note(FAR struct tone_upperhalf_s *upper, uint8_t note) { FAR struct pwm_lowerhalf_s *tone = upper->devtone; - upper->tone.frequency = g_notes_freq[note - 1]; - upper->tone.duty = 50; + upper->tone.frequency = g_notes_freq[note - 1]; +#ifdef CONFIG_PWM_MULTICHAN + upper->tone.channels[0].channel = upper->channel; + upper->tone.channels[0].duty = b16HALF; +#else + upper->tone.duty = b16HALF; +#endif + + /* REVISIT: Should check the return value */ tone->ops->start(tone, &upper->tone); - - return; } /**************************************************************************** @@ -311,8 +328,6 @@ static void stop_note(FAR struct tone_upperhalf_s *upper) FAR struct pwm_lowerhalf_s *tone = upper->devtone; tone->ops->stop(tone); - - return; } /**************************************************************************** @@ -520,7 +535,6 @@ static void next_note(FAR struct tone_upperhalf_s *upper) ts.tv_nsec = (unsigned long)nsec; ONESHOT_START(upper->oneshot, oneshot_callback, upper, &ts); - return; /* Change tempo */ @@ -648,7 +662,6 @@ static void next_note(FAR struct tone_upperhalf_s *upper) /* And arrange a callback when the note should stop */ ONESHOT_START(upper->oneshot, oneshot_callback, upper, &ts); - return; /* Tune looks bad (unexpected EOF, bad character, etc.) */ @@ -925,10 +938,15 @@ static ssize_t tone_write(FAR struct file *filep, FAR const char *buffer, ****************************************************************************/ int tone_register(FAR const char *path, FAR struct pwm_lowerhalf_s *tone, +#ifdef CONFIG_PWM_MULTICHAN + int channel, +#endif FAR struct oneshot_lowerhalf_s *oneshot) { FAR struct tone_upperhalf_s *upper; + DEBUGASSERT(path != NULL && tone != NULL); + /* Allocate the upper-half data structure */ upper = @@ -947,6 +965,9 @@ int tone_register(FAR const char *path, FAR struct pwm_lowerhalf_s *tone, sem_init(&upper->exclsem, 0, 1); upper->devtone = tone; upper->oneshot = oneshot; +#ifdef CONFIG_PWM_MULTICHAN + upper->channel = (uint8_t)channel; +#endif /* Register the PWM device */ diff --git a/drivers/audio/vs1053.c b/drivers/audio/vs1053.c index aa4eb861a79..3582bf98e1c 100644 --- a/drivers/audio/vs1053.c +++ b/drivers/audio/vs1053.c @@ -217,13 +217,6 @@ static const struct audio_ops_s g_audioops = vs1053_release /* release */ }; -/* ISR context pointers */ - -static struct vs1053_struct_s *g_isrdata[CONFIG_VS1053_DEVICE_COUNT] = -{ - NULL, -}; - /* Volume control log table. This table is in increments of 2% of * requested volume level and is the register value that should be * programmed to the VS1053 to achieve that volume pecentage. @@ -1215,32 +1208,12 @@ err_out: * ****************************************************************************/ -static int vs1053_dreq_isr(int irq, FAR void *context) +static int vs1053_dreq_isr(int irq, FAR void *context, FAR void *arg) { - struct vs1053_struct_s *dev = NULL; + struct vs1053_struct_s *dev = (struct vs1053_struct_s *)arg; struct audio_msg_s msg; - /* Get the driver context */ - -#if CONFIG_VS1053_DEVICE_COUNT == 1 - dev = g_isrdata[0]; /* Simple case */ -#else - /* More complex case */ - { - int x; - - for (x = 0; x < CONFIG_VS1053_DEVICE_COUNT; x++) - { - if (g_isrdata[x]->hw_lower->irq == irq) - { - dev = g_isrdata[x]; - break; - } - } - - DEBUGASSERT(dev); - } -#endif + DEBUGASSERT(dev != NULL); /* Now create a message and send it to the workerthread */ @@ -1909,33 +1882,10 @@ struct audio_lowerhalf_s *vs1053_initialize(FAR struct spi_dev_s *spi, } /* Attach our ISR to this device */ - dev->hw_lower->attach(dev->hw_lower, vs1053_dreq_isr); - /* Find a slot to save the device context for ISR lookup */ + dev->hw_lower->attach(dev->hw_lower, vs1053_dreq_isr, dev); -#if CONFIG_VS1053_DEVICE_COUNT == 1 - g_isrdata[0] = dev; /* The simple case */ -#else - /* The more complex case */ - { - int x; - - /* Initialize the ISR data if not alrady */ - - for (x = 0; x < CONFIG_VS1053_DEVICE_COUNT; x++) - { - /* Find an empty slot */ - - if (g_isrdata[x] == NULL) - { - g_isrdata[x] = dev; - break; - } - } - } -#endif - - /* Do some initialization of the codec */ + /* Do some initialization of the codec */ vs1053_shutdown(&dev->lower); /* Go to shutdown state */ } diff --git a/drivers/input/ads7843e.c b/drivers/input/ads7843e.c index f7019639de3..d9c2c3b9882 100644 --- a/drivers/input/ads7843e.c +++ b/drivers/input/ads7843e.c @@ -109,7 +109,7 @@ static int ads7843e_sample(FAR struct ads7843e_dev_s *priv, static int ads7843e_waitsample(FAR struct ads7843e_dev_s *priv, FAR struct ads7843e_sample_s *sample); static void ads7843e_worker(FAR void *arg); -static int ads7843e_interrupt(int irq, FAR void *context); +static int ads7843e_interrupt(int irq, FAR void *context, FAR void *arg); /* Character driver methods */ @@ -703,7 +703,7 @@ ignored: * Name: ads7843e_interrupt ****************************************************************************/ -static int ads7843e_interrupt(int irq, FAR void *context) +static int ads7843e_interrupt(int irq, FAR void *context, FAR void *arg) { FAR struct ads7843e_dev_s *priv; FAR struct ads7843e_config_s *config; diff --git a/drivers/input/button_lower.c b/drivers/input/button_lower.c index 9be0b4a35f7..b2b830f8f56 100644 --- a/drivers/input/button_lower.c +++ b/drivers/input/button_lower.c @@ -1,7 +1,7 @@ /**************************************************************************** * drivers/input/button_lower.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -64,7 +64,7 @@ static void btn_enable(FAR const struct btn_lowerhalf_s *lower, btn_handler_t handler, FAR void *arg); static void btn_disable(void); -static int btn_interrupt(int irq, FAR void *context); +static int btn_interrupt(int irq, FAR void *context, FAR void *arg); /**************************************************************************** * Private Data @@ -159,7 +159,7 @@ static void btn_enable(FAR const struct btn_lowerhalf_s *lower, mask = (1 << id); if ((either & mask) != 0) { - (void)board_button_irq(id, btn_interrupt); + (void)board_button_irq(id, btn_interrupt, NULL); } } } @@ -185,7 +185,7 @@ static void btn_disable(void) flags = enter_critical_section(); for (id = 0; id < NUM_BUTTONS; id++) { - (void)board_button_irq(id, NULL); + (void)board_button_irq(id, NULL, NULL); } /* Nullify the handler and argument */ @@ -203,7 +203,7 @@ static void btn_disable(void) * ****************************************************************************/ -static int btn_interrupt(int irq, FAR void *context) +static int btn_interrupt(int irq, FAR void *context, FAR void *arg) { DEBUGASSERT(g_btnhandler); diff --git a/drivers/input/mxt.c b/drivers/input/mxt.c index 5d617ba764b..f19c2bb0be5 100644 --- a/drivers/input/mxt.c +++ b/drivers/input/mxt.c @@ -256,7 +256,7 @@ static void mxt_touch_event(FAR struct mxt_dev_s *priv, FAR struct mxt_msg_s *msg, int ndx); static void mxt_worker(FAR void *arg); static int mxt_interrupt(FAR const struct mxt_lower_s *lower, - FAR void *arg); + FAR void *context); /* Character driver methods */ diff --git a/drivers/input/stmpe811_base.c b/drivers/input/stmpe811_base.c index dca84ae76a8..62b86a420fd 100644 --- a/drivers/input/stmpe811_base.c +++ b/drivers/input/stmpe811_base.c @@ -1,7 +1,7 @@ /**************************************************************************** * drivers/input/stmpe811_base.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -54,10 +54,6 @@ #if defined(CONFIG_INPUT) && defined(CONFIG_INPUT_STMPE811) -/**************************************************************************** - * Private Types - ****************************************************************************/ - /**************************************************************************** * Private Data ****************************************************************************/ @@ -155,30 +151,14 @@ static void stmpe811_worker(FAR void *arg) * ****************************************************************************/ -static int stmpe811_interrupt(int irq, FAR void *context) +static int stmpe811_interrupt(int irq, FAR void *context, FAR void *arg) { - FAR struct stmpe811_dev_s *priv; + FAR struct stmpe811_dev_s *priv = (FAR struct stmpe811_dev_s *)arg; FAR struct stmpe811_config_s *config; - int ret; - - /* Which STMPE811 device caused the interrupt? */ - -#ifndef CONFIG_STMPE811_MULTIPLE - priv = &g_stmpe811; -#else - for (priv = g_stmpe811list; - priv && priv->config->irq != irq; - priv = priv->flink); - - ASSERT(priv != NULL); -#endif - - /* Get a pointer the callbacks for convenience (and so the code is not so - * ugly). - */ + int ret; + DEBUGASSERT(priv != NULL && priv->config != NULL); config = priv->config; - DEBUGASSERT(config != NULL); /* Disable further interrupts */ @@ -359,7 +339,7 @@ STMPE811_HANDLE stmpe811_instantiate(FAR struct i2c_master_s *dev, /* Attach the STMPE811 interrupt handler. */ - config->attach(config, stmpe811_interrupt); + config->attach(config, stmpe811_interrupt, priv); /* Clear any pending interrupts */ diff --git a/drivers/ioexpander/skeleton.c b/drivers/ioexpander/skeleton.c index 03f15f8cffb..77e390a2f90 100644 --- a/drivers/ioexpander/skeleton.c +++ b/drivers/ioexpander/skeleton.c @@ -664,7 +664,7 @@ static void skel_irqworker(void *arg) * * NOTE: A more typical prototype for an interrupt handler would be: * - * int skel_interrupt(int irq, FAR void *context) + * int skel_interrupt(int irq, FAR void *context, FAR void *arg) * * However, it is assume that the lower half, board specific interface * can provide intercept the actual interrupt, and call this function with diff --git a/drivers/net/cs89x0.c b/drivers/net/cs89x0.c index f662f40f38a..ef2f7f46aed 100644 --- a/drivers/net/cs89x0.c +++ b/drivers/net/cs89x0.c @@ -85,14 +85,6 @@ #define BUF ((struct eth_hdr_s *)cs89x0->cs_dev.d_buf) -/* If there is only one CS89x0 instance, then mapping the CS89x0 IRQ to - * a driver state instance is trivial. - */ - -#if CONFIG_CS89x0_NINTERFACES == 1 -# define cs89x0_mapirq(irq) g_cs89x0[0] -#endif - #define PKTBUF_SIZE (MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE) /**************************************************************************** @@ -123,10 +115,7 @@ static int cs89x0_txpoll(struct net_driver_s *dev); static void cs89x0_receive(struct cs89x0_driver_s *cs89x0); static void cs89x0_txdone(struct cs89x0_driver_s *cs89x0, uint16_t isq); -#if CONFIG_CS89x0_NINTERFACES > 1 -static inline FAR struct cs89x0_driver_s *cs89x0_mapirq(int irq); -#endif -static int cs89x0_interrupt(int irq, FAR void *context); +static int cs89x0_interrupt(int irq, FAR void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -621,40 +610,6 @@ static void cs89x0_txdone(struct cs89x0_driver_s *cs89x0, uint16_t isq) (void)devif_poll(&cs89x0->cs_dev, cs89x0_txpoll); } -/**************************************************************************** - * Function: cs89x0_mapirq - * - * Description: - * Map an IRQ number to a CS89x0 device state instance. This is only - * necessary to handler the case where the architecture includes more than - * on CS89x0 chip. - * - * Parameters: - * irq - Number of the IRQ that generated the interrupt - * - * Returned Value: - * A reference to device state structure (NULL if irq does not correspond - * to any CS89x0 device). - * - * Assumptions: - * - ****************************************************************************/ - -#if CONFIG_CS89x0_NINTERFACES > 1 -static inline FAR struct cs89x0_driver_s *cs89x0_mapirq(int irq) -{ - int i; - for (i = 0; i < CONFIG_CS89x0_NINTERFACES; i++) - { - if (g_cs89x0[i] && g_cs89x0[i].irq == irq) - { - return g_cs89x0[i]; - } - } - return NULL; -} -#endif - /**************************************************************************** * Function: cs89x0_interrupt * @@ -672,17 +627,12 @@ static inline FAR struct cs89x0_driver_s *cs89x0_mapirq(int irq) * ****************************************************************************/ -static int cs89x0_interrupt(int irq, FAR void *context) +static int cs89x0_interrupt(int irq, FAR void *context, FAR void *arg) { - register struct cs89x0_driver_s *cs89x0 = s89x0_mapirq(irq); + FAR struct cs89x0_driver_s *cs89x0 = (FAR struct cs89x0_driver_s *)arg; uint16_t isq; -#ifdef CONFIG_DEBUG_FEATURES - if (!cs89x0) - { - return -ENODEV; - } -#endif + DEBUGASSERT(cs89x0 != NULL); /* Read and process all of the events from the ISQ */ @@ -1023,7 +973,7 @@ int cs89x0_initialize(FAR const cs89x0_driver_s *cs89x0, int devno) /* Attach the IRQ to the driver */ - if (irq_attach(cs89x0->irq, cs89x0_interrupt)) + if (irq_attach(cs89x0->irq, cs89x0_interrupt, cs89x0)) { /* We could not attach the ISR to the ISR */ diff --git a/drivers/net/dm90x0.c b/drivers/net/dm90x0.c index 61c22a929bd..6416ffb9731 100644 --- a/drivers/net/dm90x0.c +++ b/drivers/net/dm90x0.c @@ -385,7 +385,7 @@ static void dm9x_receive(struct dm9x_driver_s *priv); static void dm9x_txdone(struct dm9x_driver_s *priv); static void dm9x_interrupt_work(FAR void *arg); -static int dm9x_interrupt(int irq, FAR void *context); +static int dm9x_interrupt(int irq, FAR void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -1238,7 +1238,7 @@ static void dm9x_interrupt_work(FAR void *arg) * ****************************************************************************/ -static int dm9x_interrupt(int irq, FAR void *context) +static int dm9x_interrupt(int irq, FAR void *context, FAR void *arg) { #if CONFIG_DM9X_NINTERFACES == 1 FAR struct dm9x_driver_s *priv = &g_dm9x[0]; @@ -1453,7 +1453,8 @@ static void dm9x_poll_expiry(int argc, wdparm_t arg, ...) * cycle. */ - (void)wd_start(priv->dm_txpoll, DM9X_WDDELAY, dm9x_poll_expiry, 1, arg); + (void)wd_start(priv->dm_txpoll, DM9X_WDDELAY, dm9x_poll_expiry, + 1, arg); } } @@ -1951,7 +1952,7 @@ int dm9x_initialize(void) /* Attach the IRQ to the driver */ - if (irq_attach(CONFIG_DM9X_IRQ, dm9x_interrupt)) + if (irq_attach(CONFIG_DM9X_IRQ, dm9x_interrupt, NULL)) { /* We could not attach the ISR to the ISR */ diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c index e91a5652ce4..8f2ab3ff02f 100644 --- a/drivers/net/enc28j60.c +++ b/drivers/net/enc28j60.c @@ -1,7 +1,7 @@ /**************************************************************************** * drivers/net/enc28j60.c * - * Copyright (C) 2010-2012, 2014-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2010-2012, 2014-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -327,7 +327,7 @@ static void enc_rxerif(FAR struct enc_driver_s *priv); static void enc_rxdispatch(FAR struct enc_driver_s *priv); static void enc_pktif(FAR struct enc_driver_s *priv); static void enc_irqworker(FAR void *arg); -static int enc_interrupt(int irq, FAR void *context); +static int enc_interrupt(int irq, FAR void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -1275,6 +1275,8 @@ static void enc_linkstatus(FAR struct enc_driver_s *priv) static void enc_txif(FAR struct enc_driver_s *priv) { + int delay; + /* Update statistics */ NETDEV_TXDONE(&priv->dev); @@ -1287,14 +1289,25 @@ static void enc_txif(FAR struct enc_driver_s *priv) wd_cancel(priv->txtimeout); - /* Then make sure that the TX poll timer is running (if it is already - * running, the following would restart it). This is necessary to - * avoid certain race conditions where the polling sequence can be - * interrupted. + /* Check if the poll timer is running. If it is not, then start it now. + * There is a race condition here: We may test the time remaining on the + * poll timer and determine that it is still running, but then the timer + * expires immiately. That should not be problem, however, the poll timer + * processing should be in the work queue and should execute immediately + * after we complete the TX poll. Inefficient, but not fatal. */ - (void)wd_start(priv->txpoll, ENC_WDDELAY, enc_polltimer, 1, - (wdparm_t)priv); + delay = wd_gettime(priv->txpoll); + if (delay <= 0) + { + /* The poll timer is not running .. restart it. This is necessary to + * avoid certain race conditions where the polling sequence can be + * interrupted. + */ + + (void)wd_start(priv->txpoll, ENC_WDDELAY, enc_polltimer, 1, + (wdparm_t)priv); + } /* Then poll the network for new XMIT data */ @@ -1840,7 +1853,7 @@ static void enc_irqworker(FAR void *arg) * ****************************************************************************/ -static int enc_interrupt(int irq, FAR void *context) +static int enc_interrupt(int irq, FAR void *context, FAR void *arg) { register FAR struct enc_driver_s *priv = &g_enc28j60[0]; diff --git a/drivers/net/encx24j600.c b/drivers/net/encx24j600.c index e1690680471..2249d4e58fe 100644 --- a/drivers/net/encx24j600.c +++ b/drivers/net/encx24j600.c @@ -1291,18 +1291,32 @@ static void enc_txif(FAR struct enc_driver_s *priv) if (sq_empty(&priv->txqueue)) { + int delay; + /* If no further xmits are pending, then cancel the TX timeout */ wd_cancel(priv->txtimeout); - /* Then make sure that the TX poll timer is running (if it is already - * running, the following would restart it). This is necessary to - * avoid certain race conditions where the polling sequence can be - * interrupted. + /* Check if the poll timer is running. If it is not, then start it + * now. There is a race condition here: We may test the time + * remaining on the poll timer and determine that it is still running, + * but then the timer expires immiately. That should not be problem, + * however, the poll timer processing should be in the work queue and + * should execute immediately after we complete the TX poll. + * Inefficient, but not fatal. */ - (void)wd_start(priv->txpoll, ENC_WDDELAY, enc_polltimer, 1, - (wdparm_t)priv); + delay = wd_gettime(priv->txpoll); + if (delay <= 0) + { + /* The poll timer is not running .. restart it. This is necessary + * to avoid certain race conditions where the polling sequence can + * be interrupted. + */ + + (void)wd_start(priv->txpoll, ENC_WDDELAY, enc_polltimer, 1, + (wdparm_t)priv); + } /* Poll for TX packets from the networking layer */ diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c index 1550d9ad7c5..d579b0e4db9 100644 --- a/drivers/net/ftmac100.c +++ b/drivers/net/ftmac100.c @@ -210,7 +210,7 @@ static void ftmac100_receive(FAR struct ftmac100_driver_s *priv); static void ftmac100_txdone(FAR struct ftmac100_driver_s *priv); static void ftmac100_interrupt_work(FAR void *arg); -static int ftmac100_interrupt(int irq, FAR void *context); +static int ftmac100_interrupt(int irq, FAR void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -805,6 +805,7 @@ static void ftmac100_receive(FAR struct ftmac100_driver_s *priv) static void ftmac100_txdone(FAR struct ftmac100_driver_s *priv) { FAR struct ftmac100_txdes_s *txdes; + int delay; /* Check if a Tx was pending */ @@ -843,13 +844,25 @@ static void ftmac100_txdone(FAR struct ftmac100_driver_s *priv) wd_cancel(priv->ft_txtimeout); - /* Then make sure that the TX poll timer is running (if it is already - * running, the following would restart it). This is necessary to avoid - * certain race conditions where the polling sequence can be interrupted. + /* Check if the poll timer is running. If it is not, then start it now. + * There is a race condition here: We may test the time remaining on the + * poll timer and determine that it is still running, but then the timer + * expires immiately. That should not be problem, however, the poll timer + * processing should be in the work queue and should execute immediately + * after we complete the TX poll. Inefficient, but not fatal. */ - (void)wd_start(priv->ft_txpoll, FTMAC100_WDDELAY, ftmac100_poll_expiry, 1, - (wdparm_t)priv); + delay = wd_gettime(priv->ft_txpoll); + if (delay <= 0) + { + /* The poll timer is not running .. restart it. This is necessary to + * avoid certain race conditions where the polling sequence can be + * interrupted. + */ + + (void)wd_start(priv->ft_txpoll, FTMAC100_WDDELAY, ftmac100_poll_expiry, + 1, (wdparm_t)priv); + } /* Then poll the network for new XMIT data */ @@ -977,7 +990,7 @@ out: * ****************************************************************************/ -static int ftmac100_interrupt(int irq, FAR void *context) +static int ftmac100_interrupt(int irq, FAR void *context, FAR void *arg) { FAR struct ftmac100_driver_s *priv = &g_ftmac100[0]; FAR struct ftmac100_register_s *iobase = (FAR struct ftmac100_register_s *)priv->iobase; @@ -1566,7 +1579,7 @@ int ftmac100_initialize(int intf) /* Attach the IRQ to the driver */ - if (irq_attach(CONFIG_FTMAC100_IRQ, ftmac100_interrupt)) + if (irq_attach(CONFIG_FTMAC100_IRQ, ftmac100_interrupt, NULL)) { /* We could not attach the ISR to the interrupt */ diff --git a/drivers/net/loopback.c b/drivers/net/loopback.c index 06459d54490..ced03b59105 100644 --- a/drivers/net/loopback.c +++ b/drivers/net/loopback.c @@ -338,7 +338,8 @@ static int lo_ifup(FAR struct net_driver_s *dev) /* Set and activate a timer process */ - (void)wd_start(priv->lo_polldog, LO_WDDELAY, lo_poll_expiry, 1, (wdparm_t)priv); + (void)wd_start(priv->lo_polldog, LO_WDDELAY, lo_poll_expiry, + 1, (wdparm_t)priv); priv->lo_bifup = true; return OK; diff --git a/drivers/net/phy_notify.c b/drivers/net/phy_notify.c index 5f202f9ae93..2b552d620de 100644 --- a/drivers/net/phy_notify.c +++ b/drivers/net/phy_notify.c @@ -116,13 +116,13 @@ struct phy_notify_s ****************************************************************************/ static int phy_handler(FAR struct phy_notify_s *client); -static int phy_handler_0(int irq, FAR void *context); +static int phy_handler_0(int irq, FAR void *context, FAR void *arg); #if CONFIG_PHY_NOTIFICATION_NCLIENTS > 1 -static int phy_handler_1(int irq, FAR void *context); +static int phy_handler_1(int irq, FAR void *context, FAR void *arg); #if CONFIG_PHY_NOTIFICATION_NCLIENTS > 2 -static int phy_handler_2(int irq, FAR void *context); +static int phy_handler_2(int irq, FAR void *context, FAR void *arg); #if CONFIG_PHY_NOTIFICATION_NCLIENTS > 3 -static int phy_handler_3(int irq, FAR void *context); +static int phy_handler_3(int irq, FAR void *context, FAR void *arg); #endif #endif #endif @@ -298,27 +298,27 @@ static int phy_handler(FAR struct phy_notify_s *client) * Name: phy_handler_0, phy_handler_1, ... ****************************************************************************/ -static int phy_handler_0(int irq, FAR void *context) +static int phy_handler_0(int irq, FAR void *context, FAR void *arg) { return phy_handler(&g_notify_clients[0]); } #if CONFIG_PHY_NOTIFICATION_NCLIENTS > 1 -static int phy_handler_1(int irq, FAR void *context) +static int phy_handler_1(int irq, FAR void *context, FAR void *arg) { return phy_handler(&g_notify_clients[1]); } #endif #if CONFIG_PHY_NOTIFICATION_NCLIENTS > 2 -static int phy_handler_2(int irq, FAR void *context) +static int phy_handler_2(int irq, FAR void *context, FAR void *arg) { return phy_handler(&g_notify_clients[2]); } #endif #if CONFIG_PHY_NOTIFICATION_NCLIENTS > 3 -static int phy_handler_3(int irq, FAR void *context) +static int phy_handler_3(int irq, FAR void *context, FAR void *arg) { return phy_handler(&g_notify_clients[3]); } diff --git a/drivers/net/skeleton.c b/drivers/net/skeleton.c index 59c5a8fac50..c11c5e729bb 100644 --- a/drivers/net/skeleton.c +++ b/drivers/net/skeleton.c @@ -1,7 +1,7 @@ /**************************************************************************** * drivers/net/skeleton.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -157,7 +157,7 @@ static void skel_receive(FAR struct skel_driver_s *priv); static void skel_txdone(FAR struct skel_driver_s *priv); static void skel_interrupt_work(FAR void *arg); -static int skel_interrupt(int irq, FAR void *context); +static int skel_interrupt(int irq, FAR void *context, FAR void *arg); /* Watchdog timer expirations */ @@ -463,6 +463,8 @@ static void skel_receive(FAR struct skel_driver_s *priv) static void skel_txdone(FAR struct skel_driver_s *priv) { + int delay; + /* Check for errors and update statistics */ NETDEV_TXDONE(priv->sk_dev); @@ -475,14 +477,25 @@ static void skel_txdone(FAR struct skel_driver_s *priv) wd_cancel(priv->sk_txtimeout); - /* Then make sure that the TX poll timer is running (if it is already - * running, the following would restart it). This is necessary to - * avoid certain race conditions where the polling sequence can be - * interrupted. + /* Check if the poll timer is running. If it is not, then start it now. + * There is a race condition here: We may test the time remaining on the + * poll timer and determine that it is still running, but then the timer + * expires immiately. That should not be problem, however, the poll timer + * processing should be in the work queue and should execute immediately + * after we complete the TX poll. Inefficient, but not fatal. */ - (void)wd_start(priv->sk_txpoll, skeleton_WDDELAY, skel_poll_expiry, 1, - (wdparm_t)priv); + delay = wd_gettime(priv->sk_txpoll); + if (delay <= 0) + { + /* The poll timer is not running .. restart it. This is necessary to + * avoid certain race conditions where the polling sequence can be + * interrupted. + */ + + (void)wd_start(priv->sk_txpoll, skeleton_WDDELAY, skel_poll_expiry, + 1, (wdparm_t)priv); + } /* And disable further TX interrupts. */ @@ -553,7 +566,7 @@ static void skel_interrupt_work(FAR void *arg) * ****************************************************************************/ -static int skel_interrupt(int irq, FAR void *context) +static int skel_interrupt(int irq, FAR void *context, FAR void *arg) { FAR struct skel_driver_s *priv = &g_skel[0]; @@ -1102,7 +1115,7 @@ int skel_initialize(int intf) /* Attach the IRQ to the driver */ - if (irq_attach(CONFIG_skeleton_IRQ, skel_interrupt)) + if (irq_attach(CONFIG_skeleton_IRQ, skel_interrupt, NULL)) { /* We could not attach the ISR to the interrupt */ diff --git a/drivers/net/tun.c b/drivers/net/tun.c index ebb59587b62..cf44ca651b5 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -656,7 +656,8 @@ static int tun_ifup(struct net_driver_s *dev) /* Set and activate a timer process */ - (void)wd_start(priv->txpoll, TUN_WDDELAY, tun_poll_expiry, 1, (wdparm_t)priv); + (void)wd_start(priv->txpoll, TUN_WDDELAY, tun_poll_expiry, + 1, (wdparm_t)priv); priv->bifup = true; return OK; diff --git a/drivers/sensors/Kconfig b/drivers/sensors/Kconfig index d43362eb6cb..9b3e2660b20 100644 --- a/drivers/sensors/Kconfig +++ b/drivers/sensors/Kconfig @@ -32,6 +32,13 @@ config BMP180 ---help--- Enable driver support for the Bosch BMP180 barometer sensor. +config SENSORS_L3GD20 + bool "ST L3GD20 Gyroscope Sensor support" + default n + select SPI + ---help--- + Enable driver support for the ST L3GD20 gyroscope sensor. + config SENSOR_KXTJ9 bool "Kionix KXTJ9 Accelerometer support" default n diff --git a/drivers/sensors/Make.defs b/drivers/sensors/Make.defs index 4a215042811..c4b14ace8f6 100644 --- a/drivers/sensors/Make.defs +++ b/drivers/sensors/Make.defs @@ -50,7 +50,7 @@ ifeq ($(CONFIG_AS5048B),y) endif ifeq ($(CONFIG_SENSOR_KXTJ9),y) - CSRCS += kxjt9.c + CSRCS += kxtj9.c endif ifeq ($(CONFIG_LIS3DSH),y) @@ -130,6 +130,10 @@ ifeq ($(CONFIG_LIS3MDL),y) CSRCS += lis3mdl.c endif +ifeq ($(CONFIG_SENSORS_L3GD20),y) + CSRCS += l3gd20.c +endif + endif # CONFIG_SPI # Quadrature encoder upper half diff --git a/drivers/sensors/kxjt9.c b/drivers/sensors/kxtj9.c similarity index 88% rename from drivers/sensors/kxjt9.c rename to drivers/sensors/kxtj9.c index 36b23e2fa35..70ec5ec808b 100644 --- a/drivers/sensors/kxjt9.c +++ b/drivers/sensors/kxtj9.c @@ -1,5 +1,5 @@ /**************************************************************************** - * drivers/sensors/kxjt9.c + * drivers/sensors/kxtj9.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -50,7 +50,7 @@ #include #include #include -#include +#include #if defined(CONFIG_I2C) && defined(CONFIG_SENSOR_KXTJ9) @@ -123,7 +123,7 @@ /* This structure describes the state of one KXTJ9 device */ -struct kxjt9_dev_s +struct kxtj9_dev_s { FAR struct i2c_master_s *i2c; sem_t exclsem; @@ -142,29 +142,29 @@ struct kxjt9_dev_s /* I2C helpers */ -static int kxtj9_reg_read(FAR struct kxjt9_dev_s *priv, uint8_t regaddr, +static int kxtj9_reg_read(FAR struct kxtj9_dev_s *priv, uint8_t regaddr, FAR uint8_t *regval, unsigned int len); -static int kxtj9_reg_write(FAR struct kxjt9_dev_s *priv, +static int kxtj9_reg_write(FAR struct kxtj9_dev_s *priv, uint8_t regaddr, uint8_t regval); /* KXTJ9 helpers */ -static int kxtj9_configure(FAR struct kxjt9_dev_s *priv, uint8_t odr); -static int kxtj9_enable(FAR struct kxjt9_dev_s *priv, bool on); -static int kxtj9_read_sensor_data(FAR struct kxjt9_dev_s *priv, +static int kxtj9_configure(FAR struct kxtj9_dev_s *priv, uint8_t odr); +static int kxtj9_enable(FAR struct kxtj9_dev_s *priv, bool on); +static int kxtj9_read_sensor_data(FAR struct kxtj9_dev_s *priv, FAR struct kxtj9_sensor_data *sensor_data); -static void kxtj9_soft_reset(FAR struct kxjt9_dev_s *priv); -static void kxtj9_set_mode_standby(FAR struct kxjt9_dev_s *priv); +static void kxtj9_soft_reset(FAR struct kxtj9_dev_s *priv); +static void kxtj9_set_mode_standby(FAR struct kxtj9_dev_s *priv); /* Character driver methods */ -static int kxjt9_open(FAR struct file *filep); -static int kxjt9_close(FAR struct file *filep); -static ssize_t kxjt9_read(FAR struct file *filep, FAR char *buffer, +static int kxtj9_open(FAR struct file *filep); +static int kxtj9_close(FAR struct file *filep); +static ssize_t kxtj9_read(FAR struct file *filep, FAR char *buffer, size_t buflen); -static ssize_t kxjt9_write(FAR struct file *filep, FAR const char *buffer, +static ssize_t kxtj9_write(FAR struct file *filep, FAR const char *buffer, size_t buflen); -static int kxjt9_ioctl(FAR struct file *filep, int cmd, +static int kxtj9_ioctl(FAR struct file *filep, int cmd, unsigned long arg); /**************************************************************************** @@ -173,12 +173,12 @@ static int kxjt9_ioctl(FAR struct file *filep, int cmd, static const struct file_operations g_fops = { - kxjt9_open, - kxjt9_close, - kxjt9_read, - kxjt9_write, + kxtj9_open, + kxtj9_close, + kxtj9_read, + kxtj9_write, NULL, - kxjt9_ioctl, + kxtj9_ioctl, #ifndef CONFIG_DISABLE_POLL NULL, #endif @@ -199,7 +199,7 @@ static const struct file_operations g_fops = * ****************************************************************************/ -static int kxtj9_reg_read(FAR struct kxjt9_dev_s *priv, uint8_t regaddr, +static int kxtj9_reg_read(FAR struct kxtj9_dev_s *priv, uint8_t regaddr, FAR uint8_t *regval, unsigned int len) { struct i2c_msg_s msg[2]; @@ -246,7 +246,7 @@ static int kxtj9_reg_read(FAR struct kxjt9_dev_s *priv, uint8_t regaddr, * ****************************************************************************/ -static int kxtj9_reg_write(FAR struct kxjt9_dev_s *priv, uint8_t regaddr, +static int kxtj9_reg_write(FAR struct kxtj9_dev_s *priv, uint8_t regaddr, uint8_t regval) { struct i2c_msg_s msg; @@ -284,7 +284,7 @@ static int kxtj9_reg_write(FAR struct kxjt9_dev_s *priv, uint8_t regaddr, * ****************************************************************************/ -static void kxtj9_soft_reset(FAR struct kxjt9_dev_s *priv) +static void kxtj9_soft_reset(FAR struct kxtj9_dev_s *priv) { uint8_t wbuf[1]; @@ -313,7 +313,7 @@ static void kxtj9_soft_reset(FAR struct kxjt9_dev_s *priv) * ****************************************************************************/ -static void kxtj9_set_mode_standby(FAR struct kxjt9_dev_s *priv) +static void kxtj9_set_mode_standby(FAR struct kxtj9_dev_s *priv) { uint8_t wbuf[1]; @@ -336,7 +336,7 @@ static void kxtj9_set_mode_standby(FAR struct kxjt9_dev_s *priv) * ****************************************************************************/ -static int kxtj9_configure(FAR struct kxjt9_dev_s *priv, uint8_t odr) +static int kxtj9_configure(FAR struct kxtj9_dev_s *priv, uint8_t odr) { uint8_t wbuf[0]; int ret; @@ -389,7 +389,7 @@ static int kxtj9_configure(FAR struct kxjt9_dev_s *priv, uint8_t odr) * ****************************************************************************/ -static int kxtj9_enable(FAR struct kxjt9_dev_s *priv, bool on) +static int kxtj9_enable(FAR struct kxtj9_dev_s *priv, bool on) { uint8_t wbuf[1]; int ret; @@ -434,7 +434,7 @@ static int kxtj9_enable(FAR struct kxjt9_dev_s *priv, bool on) * ****************************************************************************/ -static int kxtj9_read_sensor_data(FAR struct kxjt9_dev_s *priv, +static int kxtj9_read_sensor_data(FAR struct kxtj9_dev_s *priv, FAR struct kxtj9_sensor_data *sensor_data) { int16_t acc_data[3]; @@ -463,44 +463,44 @@ static int kxtj9_read_sensor_data(FAR struct kxjt9_dev_s *priv, } /**************************************************************************** - * Name: kxjt9_open + * Name: kxtj9_open * * Description: * This method is called when the device is opened. * ****************************************************************************/ -static int kxjt9_open(FAR struct file *filep) +static int kxtj9_open(FAR struct file *filep) { return OK; } /**************************************************************************** - * Name: kxjt9_close + * Name: kxtj9_close * * Description: * This method is called when the device is closed. * ****************************************************************************/ -static int kxjt9_close(FAR struct file *filep) +static int kxtj9_close(FAR struct file *filep) { return OK; } /**************************************************************************** - * Name: kxjt9_read + * Name: kxtj9_read * * Description: * The standard read method. * ****************************************************************************/ -static ssize_t kxjt9_read(FAR struct file *filep, FAR char *buffer, +static ssize_t kxtj9_read(FAR struct file *filep, FAR char *buffer, size_t buflen) { FAR struct inode *inode; - FAR struct kxjt9_dev_s *priv; + FAR struct kxtj9_dev_s *priv; size_t nsamples; size_t i; int ret; @@ -523,7 +523,7 @@ static ssize_t kxjt9_read(FAR struct file *filep, FAR char *buffer, DEBUGASSERT(filep != NULL && filep->f_inode != NULL && buffer != NULL); inode = filep->f_inode; - priv = (FAR struct kxjt9_dev_s *)inode->i_private; + priv = (FAR struct kxtj9_dev_s *)inode->i_private; DEBUGASSERT(priv != NULL && priv->i2c != NULL); /* Return all of the samples that will fit in the user-provided buffer */ @@ -548,31 +548,31 @@ static ssize_t kxjt9_read(FAR struct file *filep, FAR char *buffer, } /**************************************************************************** - * Name: kxjt9_write + * Name: kxtj9_write * * Description: * A dummy write method. * ****************************************************************************/ -static ssize_t kxjt9_write(FAR struct file *filep, FAR const char *buffer, +static ssize_t kxtj9_write(FAR struct file *filep, FAR const char *buffer, size_t buflen) { return -ENOSYS; } /**************************************************************************** - * Name: kxjt9_ioctl + * Name: kxtj9_ioctl * * Description: * The standard ioctl method. * ****************************************************************************/ -static int kxjt9_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +static int kxtj9_ioctl(FAR struct file *filep, int cmd, unsigned long arg) { FAR struct inode *inode; - FAR struct kxjt9_dev_s *priv; + FAR struct kxtj9_dev_s *priv; int ret; /* Sanity check */ @@ -580,7 +580,7 @@ static int kxjt9_ioctl(FAR struct file *filep, int cmd, unsigned long arg) DEBUGASSERT(filep != NULL && filep->f_inode != NULL); inode = filep->f_inode; - priv = (FAR struct kxjt9_dev_s *)inode->i_private; + priv = (FAR struct kxtj9_dev_s *)inode->i_private; DEBUGASSERT(priv != NULL && priv->i2c != NULL); /* Handle ioctl commands */ @@ -626,15 +626,15 @@ static int kxjt9_ioctl(FAR struct file *filep, int cmd, unsigned long arg) ****************************************************************************/ /**************************************************************************** - * Name: kxjt9_register + * Name: kxtj9_register * * Description: - * Register the KXJT9 accelerometer device as 'devpath'. + * Register the KXTJ9 accelerometer device as 'devpath'. * * Input Parameters: * devpath - The full path to the driver to register, e.g., "/dev/accel0". * i2c - An I2C driver instance. - * addr - The I2C address of the KXJT9 accelerometer, gyroscope or + * addr - The I2C address of the KXTJ9 accelerometer, gyroscope or * magnetometer. * * Returned Value: @@ -642,10 +642,10 @@ static int kxjt9_ioctl(FAR struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -int kxjt9_register(FAR const char *devpath, FAR struct i2c_master_s *i2c, +int kxtj9_register(FAR const char *devpath, FAR struct i2c_master_s *i2c, uint8_t address) { - FAR struct kxjt9_dev_s *priv; + FAR struct kxtj9_dev_s *priv; int ret; /* Sanity check */ @@ -654,7 +654,7 @@ int kxjt9_register(FAR const char *devpath, FAR struct i2c_master_s *i2c, /* Initialize the device's structure */ - priv = (FAR struct kxjt9_dev_s *)kmm_zalloc(sizeof(struct kxjt9_dev_s)); + priv = (FAR struct kxtj9_dev_s *)kmm_zalloc(sizeof(struct kxtj9_dev_s)); if (priv == NULL) { snerr("ERROR: Failed to allocate driver instance\n"); diff --git a/drivers/sensors/l3gd20.c b/drivers/sensors/l3gd20.c new file mode 100644 index 00000000000..d400f213088 --- /dev/null +++ b/drivers/sensors/l3gd20.c @@ -0,0 +1,653 @@ +/**************************************************************************** + * drivers/sensors/l3gd20.c + * Character driver for the ST L3GD20 3-Axis gyroscope. + * + * Copyright (C) Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Based on drivers/sensors/lis3dsh.c + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#include + +#if defined(CONFIG_SPI) && defined(CONFIG_SENSORS_L3GD20) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(CONFIG_SCHED_HPWORK) +# error Hi-priority work queue support is required (CONFIG_SCHED_HPWORK) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct l3gd20_dev_s +{ + FAR struct l3gd20_dev_s *flink; /* Supports a singly linked list of + * drivers */ + FAR struct spi_dev_s *spi; /* Pointer to the SPI instance */ + FAR struct l3gd20_config_s *config; /* Pointer to the configuration of the + * L3GD20 sensor */ + sem_t datasem; /* Manages exclusive access to this + * structure */ + struct l3gd20_sensor_data_s data; /* The data as measured by the sensor */ + struct work_s work; /* The work queue is responsible for + * retrieving the data from the sensor + * after the arrival of new data was + * signalled in an interrupt */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void l3gd20_read_register(FAR struct l3gd20_dev_s *dev, + uint8_t const reg_addr, uint8_t *reg_data); +static void l3gd20_write_register(FAR struct l3gd20_dev_s *dev, + uint8_t const reg_addr, + uint8_t const reg_data); +static void l3gd20_reset(FAR struct l3gd20_dev_s *dev); +static void l3gd20_read_measurement_data(FAR struct l3gd20_dev_s *dev); +static void l3gd20_read_gyroscope_data(FAR struct l3gd20_dev_s *dev, + uint16_t *x_gyr, uint16_t *y_gyr, + uint16_t *z_gyr); +static void l3gd20_read_temperature(FAR struct l3gd20_dev_s *dev, + uint8_t * temperature); +static int l3gd20_interrupt_handler(int irq, FAR void *context); +static void l3gd20_worker(FAR void *arg); + +static int l3gd20_open(FAR struct file *filep); +static int l3gd20_close(FAR struct file *filep); +static ssize_t l3gd20_read(FAR struct file *filep, FAR char *buffer, + size_t buflen); +static ssize_t l3gd20_write(FAR struct file *filep, FAR const char *buffer, + size_t buflen); +static int l3gd20_ioctl(FAR struct file *filep, int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct file_operations g_l3gd20_fops = +{ + l3gd20_open, + l3gd20_close, + l3gd20_read, + l3gd20_write, + NULL, + l3gd20_ioctl +#ifndef CONFIG_DISABLE_POLL + , NULL +#endif +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + , NULL +#endif +}; + +/* Single linked list to store instances of drivers */ + +static struct l3gd20_dev_s *g_l3gd20_list = NULL; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: l3gd20_read_register + ****************************************************************************/ + +static void l3gd20_read_register(FAR struct l3gd20_dev_s *dev, + uint8_t const reg_addr, uint8_t *reg_data) +{ + /* Lock the SPI bus so that only one device can access it at the same time */ + + SPI_LOCK(dev->spi, true); + + /* Set CS to low which selects the L3GD20 */ + + SPI_SELECT(dev->spi, dev->config->spi_devid, true); + + /* Transmit the register address from where we want to read - the MSB needs + * to be set to indicate the read indication. + */ + + SPI_SEND(dev->spi, reg_addr | 0x80); + + /* Write an idle byte while receiving the required data */ + + *reg_data = (uint8_t) (SPI_SEND(dev->spi, 0)); + + /* Set CS to high which deselects the L3GD20 */ + + SPI_SELECT(dev->spi, dev->config->spi_devid, false); + + /* Unlock the SPI bus */ + + SPI_LOCK(dev->spi, false); +} + +/**************************************************************************** + * Name: l3gd20_write_register + ****************************************************************************/ + +static void l3gd20_write_register(FAR struct l3gd20_dev_s *dev, + uint8_t const reg_addr, + uint8_t const reg_data) +{ + /* Lock the SPI bus so that only one device can access it at the same time */ + + SPI_LOCK(dev->spi, true); + + /* Set CS to low which selects the L3GD20 */ + + SPI_SELECT(dev->spi, dev->config->spi_devid, true); + + /* Transmit the register address from where we want to read */ + + SPI_SEND(dev->spi, reg_addr); + + /* Transmit the content which should be written in the register */ + + SPI_SEND(dev->spi, reg_data); + + /* Set CS to high which deselects the L3GD20 */ + + SPI_SELECT(dev->spi, dev->config->spi_devid, false); + + /* Unlock the SPI bus */ + + SPI_LOCK(dev->spi, false); +} + +/**************************************************************************** + * Name: l3gd20_reset + ****************************************************************************/ + +static void l3gd20_reset(FAR struct l3gd20_dev_s *dev) +{ + /* Reboot memory content */ + + l3gd20_write_register(dev, L3GD20_CTRL_REG_5, L3GD20_CTRL_REG_5_BOOT_bm); + + up_mdelay(100); +} + +/**************************************************************************** + * Name: l3gd20_read_measurement_data + ****************************************************************************/ + +static void l3gd20_read_measurement_data(FAR struct l3gd20_dev_s *dev) +{ + uint16_t x_gyr = 0; + uint16_t y_gyr = 0; + uint16_t z_gyr = 0; + uint8_t temperature = 0; + int ret; + + /* Read Gyroscope */ + + l3gd20_read_gyroscope_data(dev, &x_gyr, &y_gyr, &z_gyr); + + /* Read Temperature */ + + l3gd20_read_temperature(dev, &temperature); + + /* Aquire the semaphore before the data is copied */ + + ret = sem_wait(&dev->datasem); + if (ret < 0) + { + snerr("ERROR: Could not aquire dev->datasem: %d\n", ret); + return; + } + + /* Copy retrieve data to internal data structure */ + + dev->data.x_gyr = (int16_t) (x_gyr); + dev->data.y_gyr = (int16_t) (y_gyr); + dev->data.z_gyr = (int16_t) (z_gyr); + + /* Give back the semaphore */ + + sem_post(&dev->datasem); +} + +/**************************************************************************** + * Name: l3gd20_read_gyroscope_data + ****************************************************************************/ + +static void l3gd20_read_gyroscope_data(FAR struct l3gd20_dev_s *dev, + uint16_t * x_gyr, uint16_t * y_gyr, + uint16_t * z_gyr) +{ + /* Lock the SPI bus so that only one device can access it at the same time */ + + SPI_LOCK(dev->spi, true); + + /* Set CS to low which selects the L3GD20 */ + + SPI_SELECT(dev->spi, dev->config->spi_devid, true); + + /* Transmit the register address from where we want to start reading + * 0x80 -> MSB is set -> Read Indication + * 0x40 -> MSB-1 (MS-Bit) is set -> auto increment of address when reading + * multiple bytes. + */ + + SPI_SEND(dev->spi, (L3GD20_OUT_X_L_REG | 0x80 | 0x40)); /* RX */ + + *x_gyr = ((uint16_t) (SPI_SEND(dev->spi, 0)) << 0); /* LSB */ + *x_gyr |= ((uint16_t) (SPI_SEND(dev->spi, 0)) << 8); /* MSB */ + + *y_gyr = ((uint16_t) (SPI_SEND(dev->spi, 0)) << 0); /* LSB */ + *y_gyr |= ((uint16_t) (SPI_SEND(dev->spi, 0)) << 8); /* MSB */ + + *z_gyr = ((uint16_t) (SPI_SEND(dev->spi, 0)) << 0); /* LSB */ + *z_gyr |= ((uint16_t) (SPI_SEND(dev->spi, 0)) << 8); /* MSB */ + + /* Set CS to high which deselects the L3GD20 */ + + SPI_SELECT(dev->spi, dev->config->spi_devid, false); + + /* Unlock the SPI bus */ + + SPI_LOCK(dev->spi, false); +} + +/**************************************************************************** + * Name: l3gd20_read_temperature + ****************************************************************************/ + +static void l3gd20_read_temperature(FAR struct l3gd20_dev_s* dev, + uint8_t* temperature) +{ + /* Lock the SPI bus so that only one device can access it at the same time */ + + SPI_LOCK(dev->spi, true); + + /* Set CS to low which selects the L3GD20 */ + + SPI_SELECT(dev->spi, dev->config->spi_devid, true); + + /* Transmit the register address from where we want to start reading + * 0x80 MSB is set -> Read Indication + */ + + SPI_SEND(dev->spi, (L3GD20_OUT_TEMP_REG | 0x80)); + + /* RX */ + + *temperature = (SPI_SEND(dev->spi, 0)); + + /* Set CS to high which deselects the L3GD20 */ + + SPI_SELECT(dev->spi, dev->config->spi_devid, false); + + /* Unlock the SPI bus */ + + SPI_LOCK(dev->spi, false); +} + +/**************************************************************************** + * Name: l3gd20_interrupt_handler + ****************************************************************************/ + +static int l3gd20_interrupt_handler(int irq, FAR void* context) +{ + /* This function should be called upon a rising edge on the L3GD20 new data + * interrupt pin since it signals that new data has been measured. + */ + + FAR struct l3gd20_dev_s *priv = 0; + int ret; + + /* Find out which L3GD20 device caused the interrupt */ + + for (priv = g_l3gd20_list; + priv && priv->config->irq != irq; + priv = priv->flink) + { + DEBUGASSERT(priv != NULL); + } + + /* Task the worker with retrieving the latest sensor data. We should not do + * this in a interrupt since it might take too long. Also we cannot lock the + * SPI bus from within an interrupt. + */ + + DEBUGASSERT(priv->work.worker == NULL); + ret = work_queue(HPWORK, &priv->work, l3gd20_worker, priv, 0); + if (ret < 0) + { + snerr("ERROR: Failed to queue work: %d\n", ret); + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: l3gd20_worker + ****************************************************************************/ + +static void l3gd20_worker(FAR void *arg) +{ + FAR struct l3gd20_dev_s *priv = (FAR struct l3gd20_dev_s *)(arg); + DEBUGASSERT(priv != NULL); + + /* Read out the latest sensor data */ + + l3gd20_read_measurement_data(priv); +} + +/**************************************************************************** + * Name: l3gd20_open + ****************************************************************************/ + +static int l3gd20_open(FAR struct file *filep) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct l3gd20_dev_s *priv = inode->i_private; +#ifdef CONFIG_DEBUG_SENSORS_INFO + uint8_t reg_content; + uint8_t reg_addr; +#endif + + DEBUGASSERT(priv != NULL); + + /* Perform a reset */ + + l3gd20_reset(priv); + + /* Enable DRDY signal on INT 2 */ + + l3gd20_write_register(priv, + L3GD20_CTRL_REG_3, + L3GD20_CTRL_REG_3_I2_DRDY_bm); + + /* Enable the maximum full scale mode. + * Enable block data update for gyro sensor data. + * This should prevent race conditions when reading sensor data. + */ + + l3gd20_write_register(priv, + L3GD20_CTRL_REG_4, + L3GD20_CTRL_REG_4_BDU_bm | + L3GD20_CTRL_REG_4_FS_1_bm | + L3GD20_CTRL_REG_4_FS_0_bm); + + /* Enable X,Y,Z axis + * DR=00 -> Output data rate = 95 Hz, Cut-off = 12.5 + */ + + l3gd20_write_register(priv, + L3GD20_CTRL_REG_1, + L3GD20_CTRL_REG_1_POWERDOWN_bm | + L3GD20_CTRL_REG_1_X_EN_bm | + L3GD20_CTRL_REG_1_Y_EN_bm | + L3GD20_CTRL_REG_1_Z_EN_bm); + + /* Read measurement data to ensure DRDY is low */ + + l3gd20_read_measurement_data(priv); + + /* Read back the content of all control registers for debug purposes */ + +#ifdef CONFIG_DEBUG_SENSORS_INFO + reg_content = 0; + + l3gd20_read_register(priv, L3GD20_WHO_AM_I, ®_content); + sninfo("WHO_AM_I_REG = %04x\n", reg_content); + + for (reg_addr = L3GD20_CTRL_REG_1; + reg_addr <= L3GD20_CTRL_REG_5; + reg_addr++) + { + l3gd20_read_register(priv, reg_addr, ®_content); + sninfo("R#%04x = %04x\n", reg_addr, reg_content); + } + + l3gd20_read_register(priv, L3GD20_STATUS_REG, ®_content); + sninfo("STATUS_REG = %04x\n", reg_content); +#endif + + return OK; +} + +/**************************************************************************** + * Name: l3gd20_close + ****************************************************************************/ + +static int l3gd20_close(FAR struct file *filep) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct l3gd20_dev_s *priv = inode->i_private; + + DEBUGASSERT(priv != NULL); + + /* Perform a reset */ + + l3gd20_reset(priv); + return OK; +} + +/**************************************************************************** + * Name: l3gd20_read + ****************************************************************************/ + +static ssize_t l3gd20_read(FAR struct file *filep, FAR char *buffer, + size_t buflen) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct l3gd20_dev_s *priv = inode->i_private; + FAR struct l3gd20_sensor_data_s *data; + int ret; + + DEBUGASSERT(priv != NULL); + + /* Check if enough memory was provided for the read call */ + + if (buflen < sizeof(FAR struct l3gd20_sensor_data_s)) + { + snerr("ERROR: Not enough memory for reading out a sensor data sample\n"); + return -ENOSYS; + } + + /* Acquire the semaphore before the data is copied */ + + ret = sem_wait(&priv->datasem); + if (ret < 0) + { + int errcode = errno; + snerr("ERROR: Could not aquire priv->datasem: %d\n", errcode); + return -errcode; + } + + /* Copy the sensor data into the buffer */ + + data = (FAR struct l3gd20_sensor_data_s *)buffer; + memset(data, 0, sizeof(FAR struct l3gd20_sensor_data_s)); + + data->x_gyr = priv->data.x_gyr; + data->y_gyr = priv->data.y_gyr; + data->z_gyr = priv->data.z_gyr; + data->temperature = priv->data.temperature; + + /* Give back the semaphore */ + + sem_post(&priv->datasem); + + return sizeof(FAR struct l3gd20_sensor_data_s); +} + +/**************************************************************************** + * Name: l3gd20_write + ****************************************************************************/ + +static ssize_t l3gd20_write(FAR struct file *filep, FAR const char *buffer, + size_t buflen) +{ + return -ENOSYS; +} + +/**************************************************************************** + * Name: l3gd20_ioctl + ****************************************************************************/ + +static int l3gd20_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +{ + int ret = OK; + + switch (cmd) + { + /* @TODO */ + + /* Command was not recognized */ + + default: + snerr("ERROR: Unrecognized cmd: %d\n", cmd); + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: l3gd20_register + * + * Description: + * Register the L3DF20 character device as 'devpath'. + * + * Input Parameters: + * devpath - The full path to the driver to register, e.g., "/dev/gyr0". + * spi - An SPI driver instance. + * config - configuration for the L3GD20 driver. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int l3gd20_register(FAR const char *devpath, FAR struct spi_dev_s *spi, + FAR struct l3gd20_config_s *config) +{ + FAR struct l3gd20_dev_s *priv; + int ret = OK; + + /* Sanity check */ + + DEBUGASSERT(spi != NULL); + DEBUGASSERT(config != NULL); + + /* Initialize the L3GD20 device structure */ + + priv = (FAR struct l3gd20_dev_s *)kmm_malloc(sizeof(struct l3gd20_dev_s)); + if (priv == NULL) + { + snerr("ERROR: Failed to allocate instance\n"); + ret = -ENOMEM; + goto errout; + } + + priv->spi = spi; + priv->config = config; + priv->work.worker = NULL; + + priv->data.x_gyr = 0; + priv->data.y_gyr = 0; + priv->data.z_gyr = 0; + priv->data.temperature = 0; + + /* Initialize sensor data access semaphore */ + + sem_init(&priv->datasem, 0, 1); + + /* Setup SPI frequency and mode */ + + SPI_SETFREQUENCY(spi, L3GD20_SPI_FREQUENCY); + SPI_SETMODE(spi, L3GD20_SPI_MODE); + + /* Attach the interrupt handler */ + + ret = priv->config->attach(priv->config, &l3gd20_interrupt_handler); + if (ret < 0) + { + snerr("ERROR: Failed to attach interrupt\n"); + goto errout; + } + + /* Register the character driver */ + + ret = register_driver(devpath, &g_l3gd20_fops, 0666, priv); + if (ret < 0) + { + snerr("ERROR: Failed to register driver: %d\n", ret); + kmm_free(priv); + sem_destroy(&priv->datasem); + goto errout; + } + + /* Since we support multiple L3GD20 devices, we will need to add this new + * instance to a list of device instances so that it can be found by the + * interrupt handler based on the received IRQ number. */ + + priv->flink = g_l3gd20_list; + g_l3gd20_list = priv; + +errout: + return ret; +} + +#endif /* CONFIG_SPI && CONFIG_SENSORS_L3GD20 */ diff --git a/drivers/serial/uart_16550.c b/drivers/serial/uart_16550.c index 2d77ea812e8..ab532a49db3 100644 --- a/drivers/serial/uart_16550.c +++ b/drivers/serial/uart_16550.c @@ -2,7 +2,7 @@ * drivers/serial/uart_16550.c * Serial driver for 16550 UART * - * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -74,10 +74,8 @@ struct u16550_s uint32_t baud; /* Configured baud */ uint32_t uartclk; /* UART clock frequency */ #endif -#ifndef CONFIG_SUPPRESS_SERIAL_INTS uart_datawidth_t ier; /* Saved IER value */ uint8_t irq; /* IRQ associated with this UART */ -#endif #ifndef CONFIG_16550_SUPRESS_CONFIG uint8_t parity; /* 0=none, 1=odd, 2=even */ uint8_t bits; /* Number of bits (7 or 8) */ @@ -89,21 +87,19 @@ struct u16550_s * Private Function Prototypes ****************************************************************************/ -static int u16550_setup(struct uart_dev_s *dev); -static void u16550_shutdown(struct uart_dev_s *dev); -static int u16550_attach(struct uart_dev_s *dev); -static void u16550_detach(struct uart_dev_s *dev); -#ifndef CONFIG_SUPPRESS_SERIAL_INTS -static int u16550_interrupt(int irq, void *context); -#endif -static int u16550_ioctl(struct file *filep, int cmd, unsigned long arg); -static int u16550_receive(struct uart_dev_s *dev, uint32_t *status); -static void u16550_rxint(struct uart_dev_s *dev, bool enable); -static bool u16550_rxavailable(struct uart_dev_s *dev); -static void u16550_send(struct uart_dev_s *dev, int ch); -static void u16550_txint(struct uart_dev_s *dev, bool enable); -static bool u16550_txready(struct uart_dev_s *dev); -static bool u16550_txempty(struct uart_dev_s *dev); +static int u16550_setup(FAR struct uart_dev_s *dev); +static void u16550_shutdown(FAR struct uart_dev_s *dev); +static int u16550_attach(FAR struct uart_dev_s *dev); +static void u16550_detachFAR struct uart_dev_s *dev); +static int u16550_interrupt(int irq, FAR void *context, FAR void *arg); +static int u16550_ioctl(FAR struct file *filep, int cmd, unsigned long arg); +static int u16550_receive(FAR struct uart_dev_s *dev, uint32_t *status); +static void u16550_rxint(FAR struct uart_dev_s *dev, bool enable); +static bool u16550_rxavailable(FAR struct uart_dev_s *dev); +static void u16550_send(FAR struct uart_dev_s *dev, int ch); +static void u16550_txint(FAR struct uart_dev_s *dev, bool enable); +static bool u16550_txready(FAR struct uart_dev_s *dev); +static bool u16550_txempty(FAR struct uart_dev_s *dev); /**************************************************************************** * Private Data @@ -157,9 +153,7 @@ static struct u16550_s g_uart0priv = .baud = CONFIG_16550_UART0_BAUD, .uartclk = CONFIG_16550_UART0_CLOCK, #endif -#ifndef CONFIG_SUPPRESS_SERIAL_INTS .irq = CONFIG_16550_UART0_IRQ, -#endif #ifndef CONFIG_16550_SUPRESS_CONFIG .parity = CONFIG_16550_UART0_PARITY, .bits = CONFIG_16550_UART0_BITS, @@ -194,9 +188,7 @@ static struct u16550_s g_uart1priv = .baud = CONFIG_16550_UART1_BAUD, .uartclk = CONFIG_16550_UART1_CLOCK, #endif -#ifndef CONFIG_SUPPRESS_SERIAL_INTS .irq = CONFIG_16550_UART1_IRQ, -#endif #ifndef CONFIG_16550_SUPRESS_CONFIG .parity = CONFIG_16550_UART1_PARITY, .bits = CONFIG_16550_UART1_BITS, @@ -231,9 +223,7 @@ static struct u16550_s g_uart2priv = .baud = CONFIG_16550_UART2_BAUD, .uartclk = CONFIG_16550_UART2_CLOCK, #endif -#ifndef CONFIG_SUPPRESS_SERIAL_INTS .irq = CONFIG_16550_UART2_IRQ, -#endif #ifndef CONFIG_16550_SUPRESS_CONFIG .parity = CONFIG_16550_UART2_PARITY, .bits = CONFIG_16550_UART2_BITS, @@ -268,9 +258,7 @@ static struct u16550_s g_uart3priv = .baud = CONFIG_16550_UART3_BAUD, .uartclk = CONFIG_16550_UART3_CLOCK, #endif -#ifndef CONFIG_SUPPRESS_SERIAL_INTS .irq = CONFIG_16550_UART3_IRQ, -#endif #ifndef CONFIG_16550_SUPRESS_CONFIG .parity = CONFIG_16550_UART3_PARITY, .bits = CONFIG_16550_UART3_BITS, @@ -483,7 +471,6 @@ static inline void u16550_serialout(FAR struct u16550_s *priv, int offset, * Name: u16550_disableuartint ****************************************************************************/ -#ifndef CONFIG_SUPPRESS_SERIAL_INTS static inline void u16550_disableuartint(FAR struct u16550_s *priv, FAR uart_datawidth_t *ier) { @@ -495,23 +482,16 @@ static inline void u16550_disableuartint(FAR struct u16550_s *priv, priv->ier &= ~UART_IER_ALLIE; u16550_serialout(priv, UART_IER_OFFSET, priv->ier); } -#else -# define u16550_disableuartint(priv,ier) -#endif /**************************************************************************** * Name: u16550_restoreuartint ****************************************************************************/ -#ifndef CONFIG_SUPPRESS_SERIAL_INTS static inline void u16550_restoreuartint(FAR struct u16550_s *priv, uint32_t ier) { priv->ier |= ier & UART_IER_ALLIE; u16550_serialout(priv, UART_IER_OFFSET, priv->ier); } -#else -# define u16550_restoreuartint(priv,ier) -#endif /**************************************************************************** * Name: u16550_enablebreaks @@ -586,9 +566,7 @@ static int u16550_setup(struct uart_dev_s *dev) /* Set up the IER */ -#ifndef CONFIG_SUPPRESS_SERIAL_INTS priv->ier = u16550_serialin(priv, UART_IER_OFFSET); -#endif /* Set up the LCR */ @@ -682,13 +660,12 @@ static void u16550_shutdown(struct uart_dev_s *dev) static int u16550_attach(struct uart_dev_s *dev) { -#ifndef CONFIG_SUPPRESS_SERIAL_INTS FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv; int ret; /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, u16550_interrupt); + ret = irq_attach(priv->irq, u16550_interrupt, dev); #ifndef CONFIG_ARCH_NOINTC if (ret == OK) { @@ -700,9 +677,6 @@ static int u16550_attach(struct uart_dev_s *dev) } #endif return ret; -#else - return OK; -#endif } /**************************************************************************** @@ -717,13 +691,10 @@ static int u16550_attach(struct uart_dev_s *dev) static void u16550_detach(FAR struct uart_dev_s *dev) { -#ifndef CONFIG_SUPPRESS_SERIAL_INTS FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv; -#ifndef CONFIG_ARCH_NOINTC + up_disable_irq(priv->irq); -#endif irq_detach(priv->irq); -#endif } /**************************************************************************** @@ -738,42 +709,14 @@ static void u16550_detach(FAR struct uart_dev_s *dev) * ****************************************************************************/ -#ifndef CONFIG_SUPPRESS_SERIAL_INTS -static int u16550_interrupt(int irq, void *context) +static int u16550_interrupt(int irq, FAR void *context, FAR void *arg) { - struct uart_dev_s *dev = NULL; + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct u16550_s *priv; uint32_t status; int passes; -#ifdef CONFIG_16550_UART0 - if (g_uart0priv.irq == irq) - { - dev = &g_uart0port; - } - else -#endif -#ifdef CONFIG_16550_UART1 - if (g_uart1priv.irq == irq) - { - dev = &g_uart1port; - } - else -#endif -#ifdef CONFIG_16550_UART2 - if (g_uart2priv.irq == irq) - { - dev = &g_uart2port; - } - else -#endif -#ifdef CONFIG_16550_UART3 - if (g_uart3priv.irq == irq) - { - dev = &g_uart3port; - } -#endif - ASSERT(dev != NULL); + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (FAR struct u16550_s *)dev->priv; /* Loop until there are no characters to be transferred or, @@ -856,7 +799,6 @@ static int u16550_interrupt(int irq, void *context) return OK; } -#endif /**************************************************************************** * Name: u16550_ioctl @@ -959,7 +901,6 @@ static int u16550_receive(struct uart_dev_s *dev, uint32_t *status) static void u16550_rxint(struct uart_dev_s *dev, bool enable) { -#ifndef CONFIG_SUPPRESS_SERIAL_INTS FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv; if (enable) { @@ -969,8 +910,8 @@ static void u16550_rxint(struct uart_dev_s *dev, bool enable) { priv->ier &= ~UART_IER_ERBFI; } + u16550_serialout(priv, UART_IER_OFFSET, priv->ier); -#endif } /**************************************************************************** @@ -1011,7 +952,6 @@ static void u16550_send(struct uart_dev_s *dev, int ch) static void u16550_txint(struct uart_dev_s *dev, bool enable) { -#ifndef CONFIG_SUPPRESS_SERIAL_INTS FAR struct u16550_s *priv = (FAR struct u16550_s *)dev->priv; irqstate_t flags; @@ -1034,7 +974,6 @@ static void u16550_txint(struct uart_dev_s *dev, bool enable) } leave_critical_section(flags); -#endif } /**************************************************************************** @@ -1161,11 +1100,9 @@ void up_serialinit(void) int up_putc(int ch) { FAR struct u16550_s *priv = (FAR struct u16550_s *)CONSOLE_DEV.priv; -#ifndef CONFIG_SUPPRESS_SERIAL_INTS uart_datawidth_t ier; u16550_disableuartint(priv, &ier); -#endif /* Check for LF */ @@ -1177,9 +1114,7 @@ int up_putc(int ch) } u16550_putc(priv, ch); -#ifndef CONFIG_SUPPRESS_SERIAL_INTS u16550_restoreuartint(priv, ier); -#endif return ch; } #endif diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 177d863ee2c..c8bd5c72328 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -15,6 +15,14 @@ config ARCH_HAVE_SPI_BITORDER bool default n +menuconfig SPI + bool "SPI Driver Support" + default n + ---help--- + This selection enables selection of common SPI options. This option + should be enabled by all platforms that support SPI interfaces. + See include/nuttx/spi/spi.h for further SPI driver information. + if SPI config SPI_SLAVE diff --git a/drivers/wireless/cc1101.c b/drivers/wireless/cc1101.c index aa27eda883b..e42fe085728 100644 --- a/drivers/wireless/cc1101.c +++ b/drivers/wireless/cc1101.c @@ -291,12 +291,12 @@ struct cc1101_dev_s { const struct c1101_rfsettings_s *rfsettings; - struct spi_dev_s * spi; - uint8_t isrpin; /* CC1101 pin used to trigger interrupts */ - uint32_t pinset; /* GPIO of the MCU */ - uint8_t flags; - uint8_t channel; - uint8_t power; + struct spi_dev_s *spi; + uint8_t isrpin; /* CC1101 pin used to trigger interrupts */ + uint32_t pinset; /* GPIO of the MCU */ + uint8_t flags; + uint8_t channel; + uint8_t power; }; /**************************************************************************** @@ -309,7 +309,7 @@ static volatile int cc1101_interrupt = 0; * Private Functions ****************************************************************************/ -void cc1101_access_begin(FAR struct cc1101_dev_s * dev) +void cc1101_access_begin(FAR struct cc1101_dev_s *dev) { (void)SPI_LOCK(dev->spi, true); SPI_SELECT(dev->spi, SPIDEV_WIRELESS, true); @@ -318,7 +318,7 @@ void cc1101_access_begin(FAR struct cc1101_dev_s * dev) (void)SPI_HWFEATURES(dev->spi, 0); } -void cc1101_access_end(FAR struct cc1101_dev_s * dev) +void cc1101_access_end(FAR struct cc1101_dev_s *dev) { SPI_SELECT(dev->spi, SPIDEV_WIRELESS, false); (void)SPI_LOCK(dev->spi, false); @@ -338,7 +338,7 @@ void cc1101_access_end(FAR struct cc1101_dev_s * dev) * OK on success or errno is set. */ -int cc1101_access(FAR struct cc1101_dev_s * dev, uint8_t addr, +int cc1101_access(FAR struct cc1101_dev_s *dev, uint8_t addr, FAR uint8_t *buf, int length) { int stabyte; @@ -407,7 +407,7 @@ int cc1101_access(FAR struct cc1101_dev_s * dev, uint8_t addr, * pending in RX FIFO. */ -inline uint8_t cc1101_strobe(struct cc1101_dev_s * dev, uint8_t command) +inline uint8_t cc1101_strobe(struct cc1101_dev_s *dev, uint8_t command) { uint8_t status; @@ -421,13 +421,13 @@ inline uint8_t cc1101_strobe(struct cc1101_dev_s * dev, uint8_t command) return status; } -int cc1101_reset(struct cc1101_dev_s * dev) +int cc1101_reset(struct cc1101_dev_s *dev) { cc1101_strobe(dev, CC1101_SRES); return OK; } -int cc1101_checkpart(struct cc1101_dev_s * dev) +int cc1101_checkpart(struct cc1101_dev_s *dev) { uint8_t partnum; uint8_t version; @@ -446,7 +446,7 @@ int cc1101_checkpart(struct cc1101_dev_s * dev) return ERROR; } -void cc1101_dumpregs(struct cc1101_dev_s * dev, uint8_t addr, uint8_t length) +void cc1101_dumpregs(struct cc1101_dev_s *dev, uint8_t addr, uint8_t length) { uint8_t buf[0x30], i; @@ -463,7 +463,7 @@ void cc1101_dumpregs(struct cc1101_dev_s * dev, uint8_t addr, uint8_t length) printf("\n"); } -void cc1101_setpacketctrl(struct cc1101_dev_s * dev) +void cc1101_setpacketctrl(struct cc1101_dev_s *dev) { uint8_t values[3]; @@ -524,10 +524,10 @@ int cc1101_eventcb(int irq, FAR void *context) * Public Functions ****************************************************************************/ -struct cc1101_dev_s * cc1101_init(struct spi_dev_s * spi, uint8_t isrpin, - uint32_t pinset, const struct c1101_rfsettings_s * rfsettings) +struct cc1101_dev_s *cc1101_init(struct spi_dev_s *spi, uint8_t isrpin, + uint32_t pinset, const struct c1101_rfsettings_s *rfsettings) { - struct cc1101_dev_s * dev; + struct cc1101_dev_s *dev; ASSERT(spi); @@ -595,7 +595,7 @@ struct cc1101_dev_s * cc1101_init(struct spi_dev_s * spi, uint8_t isrpin, return dev; } -int cc1101_deinit(struct cc1101_dev_s * dev) +int cc1101_deinit(struct cc1101_dev_s *dev) { ASSERT(dev); @@ -612,19 +612,19 @@ int cc1101_deinit(struct cc1101_dev_s * dev) return 0; } -int cc1101_powerup(struct cc1101_dev_s * dev) +int cc1101_powerup(struct cc1101_dev_s *dev) { ASSERT(dev); return 0; } -int cc1101_powerdown(struct cc1101_dev_s * dev) +int cc1101_powerdown(struct cc1101_dev_s *dev) { ASSERT(dev); return 0; } -int cc1101_setgdo(struct cc1101_dev_s * dev, uint8_t pin, uint8_t function) +int cc1101_setgdo(struct cc1101_dev_s *dev, uint8_t pin, uint8_t function) { ASSERT(dev); ASSERT(pin <= CC1101_IOCFG0); @@ -658,7 +658,7 @@ int cc1101_setgdo(struct cc1101_dev_s * dev, uint8_t pin, uint8_t function) return cc1101_access(dev, pin, &function, -1); } -int cc1101_setrf(struct cc1101_dev_s * dev, const struct c1101_rfsettings_s *settings) +int cc1101_setrf(struct cc1101_dev_s *dev, const struct c1101_rfsettings_s *settings) { ASSERT(dev); ASSERT(settings); @@ -696,7 +696,7 @@ int cc1101_setrf(struct cc1101_dev_s * dev, const struct c1101_rfsettings_s *set return OK; } -int cc1101_setchannel(struct cc1101_dev_s * dev, uint8_t channel) +int cc1101_setchannel(struct cc1101_dev_s *dev, uint8_t channel) { ASSERT(dev); @@ -719,7 +719,7 @@ int cc1101_setchannel(struct cc1101_dev_s * dev, uint8_t channel) return dev->flags & FLAGS_RXONLY; } -uint8_t cc1101_setpower(struct cc1101_dev_s * dev, uint8_t power) +uint8_t cc1101_setpower(struct cc1101_dev_s *dev, uint8_t power) { ASSERT(dev); @@ -765,7 +765,7 @@ int cc1101_calcRSSIdBm(int rssi) return (rssi >> 1) - 74; } -int cc1101_receive(struct cc1101_dev_s * dev) +int cc1101_receive(struct cc1101_dev_s *dev) { ASSERT(dev); @@ -778,7 +778,7 @@ int cc1101_receive(struct cc1101_dev_s * dev) return 0; } -int cc1101_read(struct cc1101_dev_s * dev, uint8_t * buf, size_t size) +int cc1101_read(struct cc1101_dev_s *dev, uint8_t * buf, size_t size) { ASSERT(dev); @@ -828,7 +828,7 @@ int cc1101_read(struct cc1101_dev_s * dev, uint8_t * buf, size_t size) return 0; } -int cc1101_write(struct cc1101_dev_s * dev, const uint8_t * buf, size_t size) +int cc1101_write(struct cc1101_dev_s *dev, const uint8_t *buf, size_t size) { uint8_t packetlen; @@ -857,7 +857,7 @@ int cc1101_write(struct cc1101_dev_s * dev, const uint8_t * buf, size_t size) return 0; } -int cc1101_send(struct cc1101_dev_s * dev) +int cc1101_send(struct cc1101_dev_s *dev) { ASSERT(dev); @@ -877,7 +877,7 @@ int cc1101_send(struct cc1101_dev_s * dev) return 0; } -int cc1101_idle(struct cc1101_dev_s * dev) +int cc1101_idle(struct cc1101_dev_s *dev) { ASSERT(dev); cc1101_strobe(dev, CC1101_SIDLE); diff --git a/drivers/wireless/cc3000/cc3000.c b/drivers/wireless/cc3000/cc3000.c index 2a651cd19c5..1b13276ede6 100644 --- a/drivers/wireless/cc3000/cc3000.c +++ b/drivers/wireless/cc3000/cc3000.c @@ -142,7 +142,7 @@ static void cc3000_deselect_and_unlock(FAR struct spi_dev_s *spi); static void cc3000_notify(FAR struct cc3000_dev_s *priv); static void *cc3000_worker(FAR void *arg); -static int cc3000_interrupt(int irq, FAR void *context); +static int cc3000_interrupt(int irq, FAR void *context, FAR void *arg); /* Character driver methods */ @@ -462,7 +462,7 @@ static void cc3000_notify(FAR struct cc3000_dev_s *priv) * Name: cc3000_worker ****************************************************************************/ -static void * select_thread_func(FAR void *arg) +static void *select_thread_func(FAR void *arg) { FAR struct cc3000_dev_s *priv = (FAR struct cc3000_dev_s *)arg; struct timeval timeout; @@ -601,7 +601,7 @@ static void * select_thread_func(FAR void *arg) * Name: cc3000_worker ****************************************************************************/ -static void * cc3000_worker(FAR void *arg) +static void *cc3000_worker(FAR void *arg) { FAR struct cc3000_dev_s *priv = (FAR struct cc3000_dev_s *)arg; int ret; @@ -746,21 +746,11 @@ static void * cc3000_worker(FAR void *arg) * Name: cc3000_interrupt ****************************************************************************/ -static int cc3000_interrupt(int irq, FAR void *context) +static int cc3000_interrupt(int irq, FAR void *context, FAR void *arg) { - FAR struct cc3000_dev_s *priv; + FAR struct cc3000_dev_s *priv = (FAR struct cc3000_dev_s *)arg; - /* Which CC3000 device caused the interrupt? */ - -#ifndef CONFIG_CC3000_MULTIPLE - priv = &g_cc3000; -#else - for (priv = g_cc3000list; - priv && priv->configs->irq != irq; - priv = priv->flink); - - ASSERT(priv != NULL); -#endif + DEBUGASSERT(priv != NULL); /* Run the worker thread */ @@ -1522,7 +1512,7 @@ errout: ****************************************************************************/ int cc3000_register(FAR struct spi_dev_s *spi, - FAR struct cc3000_config_s *config, int minor) + FAR struct cc3000_config_s *config, int minor) { FAR struct cc3000_dev_s *priv; char drvname[DEV_NAMELEN]; @@ -1577,7 +1567,7 @@ int cc3000_register(FAR struct spi_dev_s *spi, /* Attach the interrupt handler */ - ret = config->irq_attach(config, cc3000_interrupt); + ret = config->irq_attach(config, cc3000_interrupt, priv); if (ret < 0) { nerr("ERROR: Failed to attach interrupt\n"); diff --git a/drivers/wireless/nrf24l01.c b/drivers/wireless/nrf24l01.c index 166ab5c4ed1..61378b19287 100644 --- a/drivers/wireless/nrf24l01.c +++ b/drivers/wireless/nrf24l01.c @@ -163,42 +163,40 @@ static void nrf24l01_lock(FAR struct spi_dev_s *spi); static void nrf24l01_unlock(FAR struct spi_dev_s *spi); static uint8_t nrf24l01_access(FAR struct nrf24l01_dev_s *dev, - nrf24l01_access_mode_t mode, uint8_t cmd, uint8_t *buf, int length); + nrf24l01_access_mode_t mode, uint8_t cmd, uint8_t *buf, + int length); static uint8_t nrf24l01_flush_rx(FAR struct nrf24l01_dev_s *dev); static uint8_t nrf24l01_flush_tx(FAR struct nrf24l01_dev_s *dev); /* Read register from nrf24 */ static uint8_t nrf24l01_readreg(FAR struct nrf24l01_dev_s *dev, uint8_t reg, - uint8_t *value, int len); + FAR uint8_t *value, int len); /* Read single byte value from a register of nrf24 */ static uint8_t nrf24l01_readregbyte(FAR struct nrf24l01_dev_s *dev, - uint8_t reg); - -static void nrf24l01_writeregbyte(FAR struct nrf24l01_dev_s *dev, uint8_t reg, - uint8_t value); - -static uint8_t nrf24l01_setregbit(FAR struct nrf24l01_dev_s *dev, uint8_t reg, - uint8_t value, bool set); - -static void nrf24l01_tostate(FAR struct nrf24l01_dev_s *dev, nrf24l01_state_t state); - -static int nrf24l01_irqhandler(FAR int irq, FAR void *context); - -static inline int nrf24l01_attachirq(FAR struct nrf24l01_dev_s *dev, xcpt_t isr); - -static int dosend(FAR struct nrf24l01_dev_s *dev, FAR const uint8_t *data, size_t datalen); - + uint8_t reg); +static void nrf24l01_writeregbyte(FAR struct nrf24l01_dev_s *dev, + uint8_t reg, uint8_t value); +static uint8_t nrf24l01_setregbit(FAR struct nrf24l01_dev_s *dev, + uint8_t reg, uint8_t value, bool set); +static void nrf24l01_tostate(FAR struct nrf24l01_dev_s *dev, + nrf24l01_state_t state); +static int nrf24l01_irqhandler(FAR int irq, FAR void *context, + FAR void *arg); +static inline int nrf24l01_attachirq(FAR struct nrf24l01_dev_s *dev, + xcpt_t isr, FAR void *arg); +static int dosend(FAR struct nrf24l01_dev_s *dev, FAR const uint8_t *data, + size_t datalen); static int nrf24l01_unregister(FAR struct nrf24l01_dev_s *dev); #ifdef CONFIG_WL_NRF24L01_RXSUPPORT -void fifoput(struct nrf24l01_dev_s *dev, uint8_t pipeno, uint8_t *buffer, uint8_t buflen); - -uint8_t fifoget(struct nrf24l01_dev_s *dev, uint8_t *buffer, uint8_t buflen, uint8_t *pipeno); - +void fifoput(struct nrf24l01_dev_s *dev, uint8_t pipeno, + FAR uint8_t *buffer, uint8_t buflen); +uint8_t fifoget(struct nrf24l01_dev_s *dev, FAR uint8_t *buffer, + uint8_t buflen, FAR uint8_t *pipeno); static void nrf24l01_worker(FAR void *arg); #endif @@ -206,24 +204,20 @@ static void nrf24l01_worker(FAR void *arg); /* POSIX API */ static int nrf24l01_open(FAR struct file *filep); - static int nrf24l01_close(FAR struct file *filep); - -static ssize_t nrf24l01_read(FAR struct file *filep, FAR char *buffer, size_t buflen); - -static ssize_t nrf24l01_write(FAR struct file *filep, FAR const char *buffer, size_t buflen); - -static int nrf24l01_ioctl(FAR struct file *filep, int cmd, unsigned long arg); - +static ssize_t nrf24l01_read(FAR struct file *filep, FAR char *buffer, + size_t buflen); +static ssize_t nrf24l01_write(FAR struct file *filep, + FAR const char *buffer, size_t buflen); +static int nrf24l01_ioctl(FAR struct file *filep, int cmd, + unsigned long arg); static int nrf24l01_poll(FAR struct file *filep, FAR struct pollfd *fds, - bool setup); + bool setup); /**************************************************************************** * Private Data ****************************************************************************/ -static FAR struct nrf24l01_dev_s *g_nrf24l01dev; - static const struct file_operations nrf24l01_fops = { nrf24l01_open, /* open */ @@ -491,9 +485,9 @@ uint8_t fifoget(struct nrf24l01_dev_s *dev, uint8_t *buffer, uint8_t buflen, uin #endif -static int nrf24l01_irqhandler(int irq, FAR void *context) +static int nrf24l01_irqhandler(int irq, FAR void *context, FAR void *arg) { - FAR struct nrf24l01_dev_s *dev = g_nrf24l01dev; + FAR struct nrf24l01_dev_s *dev = (FAR struct nrf24l01_dev_s *)arg; winfo("*IRQ*"); @@ -501,7 +495,7 @@ static int nrf24l01_irqhandler(int irq, FAR void *context) /* If RX is enabled we delegate the actual work to bottom-half handler */ - work_queue(HPWORK, &g_nrf24l01dev->irq_work, nrf24l01_worker, dev, 0); + work_queue(HPWORK, &dev->irq_work, nrf24l01_worker, dev, 0); #else /* Otherwise we simply wake up the send function */ @@ -512,11 +506,12 @@ static int nrf24l01_irqhandler(int irq, FAR void *context) return OK; } -/* Configure IRQ pin (falling edge) */ +/* Configure IRQ pin (falling edge) */ -static inline int nrf24l01_attachirq(FAR struct nrf24l01_dev_s *dev, xcpt_t isr) +static inline int nrf24l01_attachirq(FAR struct nrf24l01_dev_s *dev, xcpt_t isr, + FAR void *arg) { - return dev->config->irqattach(isr); + return dev->config->irqattach(isr, arg); } static inline bool nrf24l01_chipenable(FAR struct nrf24l01_dev_s *dev, bool enable) @@ -1177,11 +1172,10 @@ static int nrf24l01_unregister(FAR struct nrf24l01_dev_s *dev) /* Release IRQ */ - nrf24l01_attachirq(dev, NULL); - - g_nrf24l01dev = NULL; + nrf24l01_attachirq(dev, NULL, NULL); /* Free memory */ + #ifdef CONFIG_WL_NRF24L01_RXSUPPORT kmm_free(dev->rx_fifo); #endif @@ -1244,13 +1238,9 @@ int nrf24l01_register(FAR struct spi_dev_s *spi, FAR struct nrf24l01_config_s *c sem_setprotocol(&dev->sem_rx, SEM_PRIO_NONE); #endif - /* Set the global reference */ - - g_nrf24l01dev = dev; - /* Configure IRQ pin (falling edge) */ - nrf24l01_attachirq(dev, nrf24l01_irqhandler); + nrf24l01_attachirq(dev, nrf24l01_irqhandler, dev); /* Register the device as an input device */ @@ -1266,11 +1256,6 @@ int nrf24l01_register(FAR struct spi_dev_s *spi, FAR struct nrf24l01_config_s *c return result; } -FAR struct nrf24l01_dev_s * nrf24l01_getinstance(void) -{ - return g_nrf24l01dev; -} - /* (re)set the device in a default initial state */ int nrf24l01_init(FAR struct nrf24l01_dev_s *dev) diff --git a/fs/vfs/fs_fdopen.c b/fs/vfs/fs_fdopen.c index c795d81630c..43e00f184af 100644 --- a/fs/vfs/fs_fdopen.c +++ b/fs/vfs/fs_fdopen.c @@ -277,7 +277,7 @@ FAR struct file_struct *fs_fdopen(int fd, int oflags, FAR struct tcb_s *tcb) errcode = ENFILE; -#if CONFIG_STDIO_BUFFER_SIZE > 0 +#if !defined(CONFIG_STDIO_DISABLE_BUFFERING) && CONFIG_STDIO_BUFFER_SIZE > 0 errout_with_sem: #endif sem_post(&slist->sl_sem); diff --git a/fs/vfs/fs_fstatfs.c b/fs/vfs/fs_fstatfs.c index cdeba3c4570..207311ea470 100644 --- a/fs/vfs/fs_fstatfs.c +++ b/fs/vfs/fs_fstatfs.c @@ -79,7 +79,7 @@ int fstatfs(int fd, FAR struct statfs *buf) if ((unsigned int)fd >= CONFIG_NFILE_DESCRIPTORS) { - /* No networking... it is a bad descriptor in any event */ + /* It is a bad, out-of-range descriptor */ set_errno(EBADF); return ERROR; @@ -103,11 +103,20 @@ int fstatfs(int fd, FAR struct statfs *buf) inode = filep->f_inode; DEBUGASSERT(inode != NULL); + /* Check if the file is open */ + + if (inode == NULL) + { + /* The descriptor does not refer to an open file. */ + + ret = -EBADF; + } + else +#ifndef CONFIG_DISABLE_MOUNTPOINT /* The way we handle the stat depends on the type of inode that we * are dealing with. */ -#ifndef CONFIG_DISABLE_MOUNTPOINT if (INODE_IS_MOUNTPT(inode)) { /* The node is a file system mointpoint. Verify that the mountpoint diff --git a/fs/vfs/fs_read.c b/fs/vfs/fs_read.c index 6da412c3793..b00616682a0 100644 --- a/fs/vfs/fs_read.c +++ b/fs/vfs/fs_read.c @@ -92,7 +92,7 @@ ssize_t file_read(FAR struct file *filep, FAR void *buf, size_t nbytes) * method? */ - else if (inode && inode->u.i_ops && inode->u.i_ops->read) + else if (inode != NULL && inode->u.i_ops && inode->u.i_ops->read) { /* Yes.. then let it perform the read. NOTE that for the case of the * mountpoint, we depend on the read methods being identical in diff --git a/include/cxx/cstring b/include/cxx/cstring index 7fca19c45a7..038080e75d0 100644 --- a/include/cxx/cstring +++ b/include/cxx/cstring @@ -87,6 +87,11 @@ namespace std // Declared in legacy strings.h + using ::bcmp; + using ::bcopy; + using ::bzero; + using ::index; + using ::rindex; using ::ffs; using ::strcasecmp; using ::strncasecmp; diff --git a/include/nuttx/analog/ads1242.h b/include/nuttx/analog/ads1242.h index d8a630bd207..aeeb48da6cf 100644 --- a/include/nuttx/analog/ads1242.h +++ b/include/nuttx/analog/ads1242.h @@ -1,5 +1,5 @@ /**************************************************************************** - * include/nuttx/sensors/ads1242.h + * include/nuttx/analog/ads1242.h * * Copyright (C) 2016, DS-Automotion GmbH. All rights reserved. * Author: Alexander Entinger @@ -41,7 +41,7 @@ ****************************************************************************/ #include -#include +#include #include #if defined(CONFIG_SPI) && defined(CONFIG_ADC_ADS1242) @@ -59,12 +59,12 @@ * Cmd: ANIOC_ADS2142_DO_SYSTEM_OFFSET_CALIB Arg: None */ -#define ANIOC_ADS2142_READ _ANIOC(ANIOC_USER + 0) -#define ANIOC_ADS2142_SET_GAIN _ANIOC(ANIOC_USER + 1) -#define ANIOC_ADS2142_SET_POSITIVE_INPUT _ANIOC(ANIOC_USER + 2) -#define ANIOC_ADS2142_SET_NEGATIVE_INPUT _ANIOC(ANIOC_USER + 3) -#define ANIOC_ADS2142_IS_DATA_READY _ANIOC(ANIOC_USER + 4) -#define ANIOC_ADS2142_DO_SYSTEM_OFFSET_CALIB _ANIOC(ANIOC_USER + 5) +#define ANIOC_ADS2142_READ _ANIOC(AN_ADS2142_FIRST + 0) +#define ANIOC_ADS2142_SET_GAIN _ANIOC(AN_ADS2142_FIRST + 1) +#define ANIOC_ADS2142_SET_POSITIVE_INPUT _ANIOC(AN_ADS2142_FIRST + 2) +#define ANIOC_ADS2142_SET_NEGATIVE_INPUT _ANIOC(AN_ADS2142_FIRST + 3) +#define ANIOC_ADS2142_IS_DATA_READY _ANIOC(AN_ADS2142_FIRST + 4) +#define ANIOC_ADS2142_DO_SYSTEM_OFFSET_CALIB _ANIOC(AN_ADS2142_FIRST + 5) /* ADS1242 REGISTER *********************************************************/ diff --git a/include/nuttx/analog/ioctl.h b/include/nuttx/analog/ioctl.h new file mode 100644 index 00000000000..97e48360187 --- /dev/null +++ b/include/nuttx/analog/ioctl.h @@ -0,0 +1,94 @@ +/**************************************************************************** + * include/nuttx/analog/ioctl.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_ANALOG_IOCTL_H +#define __INCLUDE_NUTTX_ANALOG_IOCTL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The analog driver sub-system uses the standard character driver framework. + * However, since the driver is a devices control interface rather than a + * data transfer interface, the majority of the functionality is implemented + * in driver ioctl calls. Standard ioctl commands are listed below: + */ + +/* DAC/ADC */ + +#define ANIOC_TRIGGER _ANIOC(0x0001) /* Trigger one conversion + * IN: None + * OUT: None */ + +#define AN_FIRST 0x0001 /* First common command */ +#define AN_NCMDS 1 /* Two common commands */ + +/* User defined ioctl commands are also supported. These will be forwarded + * by the upper-half QE driver to the lower-half QE driver via the ioctl() + * method fo the QE lower-half interface. However, the lower-half driver + * must reserve a block of commands as follows in order prevent IOCTL + * command numbers from overlapping. + */ + +/* See include/nuttx/sensors/ads1242.h */ + +#define AN_ADS2142_FIRST (AN_FIRST + AN_NCMDS) +#define AN_ADS2142_NCMDS 6 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_NUTTX_ANALOG_IOCTL_H */ diff --git a/include/nuttx/audio/audio.h b/include/nuttx/audio/audio.h index d312a6f6d10..1bdb9fe7ef4 100644 --- a/include/nuttx/audio/audio.h +++ b/include/nuttx/audio/audio.h @@ -389,12 +389,12 @@ begin_packed_struct struct ap_buffer_s struct audio_msg_s { #ifdef CONFIG_AUDIO_MULTI_SESSION - FAR void *session; /* Associated channel */ + FAR void *session; /* Associated channel */ #endif uint16_t msgId; /* Message ID */ union { - FAR void * pPtr; /* Buffer being dequeued */ + FAR void *pPtr; /* Buffer being dequeued */ uint32_t data; /* Message data */ } u; }; diff --git a/include/nuttx/audio/tone.h b/include/nuttx/audio/tone.h index 7f15dc69548..e9a9c0059ac 100644 --- a/include/nuttx/audio/tone.h +++ b/include/nuttx/audio/tone.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/nuttx/audio/tone.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. * Author: Alan Carvalho de Assis * * Redistribution and use in source and binary forms, with or without @@ -76,6 +76,9 @@ extern "C" * filesystem. The recommended convention is to name all PWM drivers * as "/dev/tone0", "/dev/tone1", etc. where the driver path * differs only in the "minor" number at the end of the device name. + * channel - The the PWM peripheral supports multiple output channels, then + * this value must be provided to indicate the output channel that drives + * the tone. * tone - A pointer to an instance of lower half PWM driver tone. This * instance will be bound to the Audio Tone driver and must persists as * long as that driver persists. @@ -86,6 +89,9 @@ extern "C" ****************************************************************************/ int tone_register(FAR const char *path, FAR struct pwm_lowerhalf_s *tone, +#ifdef CONFIG_PWM_MULTICHAN + int channel, +#endif FAR struct oneshot_lowerhalf_s *oneshot); #undef EXTERN diff --git a/include/nuttx/audio/vs1053.h b/include/nuttx/audio/vs1053.h index aa08b7c04c1..75cc291674a 100644 --- a/include/nuttx/audio/vs1053.h +++ b/include/nuttx/audio/vs1053.h @@ -66,7 +66,8 @@ struct vs1053_lower_s { - int (*attach)(FAR const struct vs1053_lower_s *lower, xcpt_t handler); + int (*attach)(FAR const struct vs1053_lower_s *lower, xcpt_t handler, + FAR void *arg); void (*enable)(FAR const struct vs1053_lower_s *lower); void (*disable)(FAR const struct vs1053_lower_s *lower); void (*reset)(FAR const struct vs1053_lower_s *lower, bool state); diff --git a/include/nuttx/board.h b/include/nuttx/board.h index f31398548d4..633ea9c6839 100644 --- a/include/nuttx/board.h +++ b/include/nuttx/board.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/nuttx/board.h * - * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -614,7 +614,7 @@ uint8_t board_buttons(void); ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS -xcpt_t board_button_irq(int id, xcpt_t irqhandler); +xcpt_t board_button_irq(int id, xcpt_t irqhandler, FAR void *arg); #endif /**************************************************************************** diff --git a/include/nuttx/drivers/can.h b/include/nuttx/drivers/can.h index 310822b0e06..68df58dd791 100644 --- a/include/nuttx/drivers/can.h +++ b/include/nuttx/drivers/can.h @@ -197,11 +197,34 @@ #define CANIOC_GET_CONNMODES _CANIOC(8) #define CANIOC_SET_CONNMODES _CANIOC(9) -/* CANIOC_USER: Device specific ioctl calls can be supported with cmds greater - * than this value - */ +#define CAN_FIRST 0x0001 /* First common command */ +#define CAN_NCMDS 9 /* Nine common commands */ -#define CANIOC_USER _CANIOC(10) +/* User defined ioctl commands are also supported. These will be forwarded + * by the upper-half CAN driver to the lower-half CAN driver via the co_ioctl() + * method fo the CAN lower-half interface. However, the lower-half driver + * must reserve a block of commands as follows in order prevent IOCTL + * command numbers from overlapping. + * + * This is generally done as follows. The first reservation for CAN driver A would + * look like: + * + * CAN_A_FIRST (CAN_FIRST + CAN_NCMDS) <- First command + * CAN_A_NCMDS 42 <- Number of commands + * + * IOCTL commands for CAN driver A would then be defined in a CAN A header file like: + * + * CANIOC_A_CMD1 _CANIOC(CAN_A_FIRST+0) + * CANIOC_A_CMD2 _CANIOC(CAN_A_FIRST+1) + * CANIOC_A_CMD3 _CANIOC(CAN_A_FIRST+2) + * ... + * CANIOC_A_CMD42 _CANIOC(CAN_A_FIRST+41) + * + * The next reservation would look like: + * + * CAN_B_FIRST (CAN_A_FIRST + CAN_A_NCMDS) <- Next command + * CAN_B_NCMDS 77 <- Number of commands + */ /* Convenience macros ***************************************************************/ diff --git a/include/nuttx/drivers/pwm.h b/include/nuttx/drivers/pwm.h index 7cf80b0d7b3..eddea5804e2 100644 --- a/include/nuttx/drivers/pwm.h +++ b/include/nuttx/drivers/pwm.h @@ -66,12 +66,16 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ /* CONFIG_PWM - Enables because PWM driver support * CONFIG_PWM_PULSECOUNT - Some hardware will support generation of a fixed * number of pulses. This might be used, for example to support a stepper * motor. If the hardware will support a fixed pulse count, then this * configuration should be set to enable the capability. + * CONFIG_PWM_MULTICHAN - Enables support for multiple output channels per + * timer. If selected, then CONFIG_PWM_NCHANNELS must be provided to + * indicated the maximum number of supported PWM output channels. * CONFIG_DEBUG_PWM_INFO - This will generate output that can be use to * debug the PWM driver. */ @@ -122,6 +126,10 @@ * Public Types ****************************************************************************/ +/* If the PWM peripheral supports multiple output channels, then this + * structure describes the output state on one channel. + */ + #ifdef CONFIG_PWM_MULTICHAN struct pwm_chan_s { @@ -135,8 +143,11 @@ struct pwm_chan_s struct pwm_info_s { uint32_t frequency; /* Frequency of the pulse train */ + #ifdef CONFIG_PWM_MULTICHAN + /* Per-channel output state */ struct pwm_chan_s channels[CONFIG_PWM_NCHANNELS]; + #else ub16_t duty; /* Duty of the pulse train, "1"-to-"0" duration. * Maximum: 65535/65536 (0x0000ffff) @@ -145,7 +156,7 @@ struct pwm_info_s uint32_t count; /* The number of pulse to generate. 0 means to * generate an indefinite number of pulses */ # endif -#endif +#endif /* CONFIG_PWM_MULTICHAN */ }; /* This structure is a set a callback functions used to call from the upper- @@ -184,7 +195,7 @@ struct pwm_ops_s FAR const struct pwm_info_s *info); #endif - /* Stop the pulsed output and reset the timer resources*/ + /* Stop the pulsed output and reset the timer resources */ CODE int (*stop)(FAR struct pwm_lowerhalf_s *dev); diff --git a/include/nuttx/fs/ioctl.h b/include/nuttx/fs/ioctl.h index c8e76b3ca35..c5d25cd2120 100644 --- a/include/nuttx/fs/ioctl.h +++ b/include/nuttx/fs/ioctl.h @@ -242,21 +242,16 @@ #define _TSIOCVALID(c) (_IOC_TYPE(c)==_TSIOCBASE) #define _TSIOC(nr) _IOC(_TSIOCBASE,nr) -/* NuttX sensor ioctl definitions (see nuttx/sensor/xxx.h) ******************/ +/* NuttX sensor ioctl definitions (see nuttx/sensor/ioctl.h) ****************/ #define _SNIOCVALID(c) (_IOC_TYPE(c)==_SNIOCBASE) #define _SNIOC(nr) _IOC(_SNIOCBASE,nr) -/* Nuttx Analog (DAC/ADC_ ioctl commands ************************************/ +/* Nuttx Analog (DAC/ADC) ioctl commands (see nuttx/analog/ioctl.h **********/ #define _ANIOCVALID(c) (_IOC_TYPE(c)==_ANIOCBASE) #define _ANIOC(nr) _IOC(_ANIOCBASE,nr) -#define ANIOC_TRIGGER _ANIOC(0x0001) /* Trigger one conversion - * IN: None - * OUT: None */ -#define ANIOC_USER 0x0002 /* Device specific IOCTL commands - * may follow */ /* NuttX PWM ioctl definitions (see nuttx/drivers/pwm.h) ********************/ #define _PWMIOCVALID(c) (_IOC_TYPE(c)==_PWMIOCBASE) diff --git a/include/nuttx/input/stmpe811.h b/include/nuttx/input/stmpe811.h index 08b7e6f3cf9..861377e81e4 100644 --- a/include/nuttx/input/stmpe811.h +++ b/include/nuttx/input/stmpe811.h @@ -1,7 +1,7 @@ /******************************************************************************************** * include/nuttx/input/stmpe811.h * - * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -500,7 +500,7 @@ struct stmpe811_config_s * clear - Acknowledge/clear any pending GPIO interrupt */ - int (*attach)(FAR struct stmpe811_config_s *state, xcpt_t isr); + int (*attach)(FAR struct stmpe811_config_s *state, xcpt_t isr, FAR void *arg); void (*enable)(FAR struct stmpe811_config_s *state, bool enable); void (*clear)(FAR struct stmpe811_config_s *state); }; diff --git a/include/nuttx/input/touchscreen.h b/include/nuttx/input/touchscreen.h index c81c9c36b7d..96041946cba 100644 --- a/include/nuttx/input/touchscreen.h +++ b/include/nuttx/input/touchscreen.h @@ -1,7 +1,7 @@ /************************************************************************************ * include/nuttx/input/touchscreen.h * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2012, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -57,18 +57,41 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ + /* IOCTL Commands *******************************************************************/ +/* Common TSC IOCTL commands */ #define TSIOC_SETCALIB _TSIOC(0x0001) /* arg: Pointer to int calibration value */ #define TSIOC_GETCALIB _TSIOC(0x0002) /* arg: Pointer to int calibration value */ #define TSIOC_SETFREQUENCY _TSIOC(0x0003) /* arg: Pointer to uint32_t frequency value */ #define TSIOC_GETFREQUENCY _TSIOC(0x0004) /* arg: Pointer to uint32_t frequency value */ -/* Specific touchscreen drivers may support additional, device specific ioctl - * commands, beginning with this value: - */ +#define TSC_FIRST 0x0001 /* First common command */ +#define TSC_NCMDS 4 /* Four common commands */ -#define TSIOC_USER 0x0005 /* Lowest, unused TSC ioctl command */ +/* User defined ioctl commands are also supported. However, the TSC driver must + * reserve a block of commands as follows in order prevent IOCTL command numbers + * from overlapping. + * + * This is generally done as follows. The first reservation for TSC driver A would + * look like: + * + * TSC_A_FIRST (TSC_FIRST + TSC_NCMDS) <- First command + * TSC_A_NCMDS 42 <- Number of commands + * + * IOCTL commands for TSC driver A would then be defined in a TSC A header file like: + * + * TSCIOC_A_CMD1 _TSIOC(TSC_A_FIRST+0) + * TSCIOC_A_CMD2 _TSIOC(TSC_A_FIRST+1) + * TSCIOC_A_CMD3 _TSIOC(TSC_A_FIRST+2) + * ... + * TSCIOC_A_CMD42 _TSIOC(TSC_A_FIRST+41) + * + * The next reservation would look like: + * + * TSC_B_FIRST (TSC_A_FIRST + TSC_A_NCMDS) <- Next command + * TSC_B_NCMDS 77 <- Number of commands + */ /* These definitions provide the meaning of all of the bits that may be * reported in the struct touch_point_s flags. diff --git a/include/nuttx/irq.h b/include/nuttx/irq.h index e5ae0807d9e..59d8a3a3302 100644 --- a/include/nuttx/irq.h +++ b/include/nuttx/irq.h @@ -55,7 +55,7 @@ */ #ifndef __ASSEMBLY__ -# define irq_detach(isr) irq_attach(isr, NULL) +# define irq_detach(isr) irq_attach(isr, NULL, NULL) #endif /**************************************************************************** @@ -65,7 +65,7 @@ /* This struct defines the way the registers are stored */ #ifndef __ASSEMBLY__ -typedef int (*xcpt_t)(int irq, FAR void *context); +typedef int (*xcpt_t)(int irq, FAR void *context, FAR void *arg); #endif /* Now include architecture-specific types */ @@ -94,11 +94,11 @@ extern "C" * * Description: * Configure the IRQ subsystem so that IRQ number 'irq' is dispatched to - * 'isr' + * 'isr' with argument 'arg' * ****************************************************************************/ -int irq_attach(int irq, xcpt_t isr); +int irq_attach(int irq, xcpt_t isr, FAR void *arg); /**************************************************************************** * Name: enter_critical_section diff --git a/include/nuttx/sensors/as5048b.h b/include/nuttx/sensors/as5048b.h index 9a274d90ae5..76ea307c23b 100644 --- a/include/nuttx/sensors/as5048b.h +++ b/include/nuttx/sensors/as5048b.h @@ -59,10 +59,10 @@ /* IOCTL Commands ***********************************************************/ -#define QEIOC_ZEROPOSITION _QEIOC(QEIOC_USER+0) /* Arg: int32_t* pointer */ -#define QEIOC_AUTOGAINCTL _QEIOC(QEIOC_USER+1) /* Arg: uint8_t* pointer */ -#define QEIOC_DIAGNOSTICS _QEIOC(QEIOC_USER+2) /* Arg: uint8_t* pointer */ -#define QEIOC_MAGNITUDE _QEIOC(QEIOC_USER+3) /* Arg: int32_t* pointer */ +#define QEIOC_ZEROPOSITION _QEIOC(QE_AS5048B_FIRST+0) /* Arg: int32_t* pointer */ +#define QEIOC_AUTOGAINCTL _QEIOC(QE_AS5048B_FIRST+1) /* Arg: uint8_t* pointer */ +#define QEIOC_DIAGNOSTICS _QEIOC(QE_AS5048B_FIRST+2) /* Arg: uint8_t* pointer */ +#define QEIOC_MAGNITUDE _QEIOC(QE_AS5048B_FIRST+3) /* Arg: int32_t* pointer */ /* Resolution ***************************************************************/ diff --git a/include/nuttx/sensors/ioctl.h b/include/nuttx/sensors/ioctl.h index 036042a926b..acbf31d8100 100644 --- a/include/nuttx/sensors/ioctl.h +++ b/include/nuttx/sensors/ioctl.h @@ -57,7 +57,7 @@ #define SNIOC_OTLRM _SNIOC(0x0006) /* One Time L-Res Mode Arg: None */ #define SNIOC_CHMEATIME _SNIOC(0x0007) /* Change Meas. Time Arg: uint8_t */ -/* IOCTL commands unique to the KXJT9 */ +/* IOCTL commands unique to the KXTJ9 */ #define SNIOC_ENABLE _SNIOC(0x0008) /* Arg: None */ #define SNIOC_DISABLE _SNIOC(0x0009) /* Arg: None */ diff --git a/include/nuttx/sensors/kxjt9.h b/include/nuttx/sensors/kxtj9.h similarity index 91% rename from include/nuttx/sensors/kxjt9.h rename to include/nuttx/sensors/kxtj9.h index 9c4f234b117..4c3facaf733 100644 --- a/include/nuttx/sensors/kxjt9.h +++ b/include/nuttx/sensors/kxtj9.h @@ -1,5 +1,5 @@ /**************************************************************************** - * include/nuttx/sensors/kxjt9.h + * include/nuttx/sensors/kxtj9.h * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -35,8 +35,8 @@ * ****************************************************************************/ -#ifndef __INCLUDE_NUTTX_SENSORS_KXJT9_H -#define __INCLUDE_NUTTX_SENSORS_KXJT9_H +#ifndef __INCLUDE_NUTTX_SENSORS_KXTJ9_H +#define __INCLUDE_NUTTX_SENSORS_KXTJ9_H /**************************************************************************** * Included Files @@ -91,15 +91,15 @@ extern "C" #endif /**************************************************************************** - * Name: kxjt9_register + * Name: kxtj9_register * * Description: - * Register the KXJT9 accelerometer device as 'devpath'. + * Register the KXTJ9 accelerometer device as 'devpath'. * * Input Parameters: * devpath - The full path to the driver to register, e.g., "/dev/accel0". * i2c - An I2C driver instance. - * addr - The I2C address of the KXJT9 accelerometer, gyroscope or + * addr - The I2C address of the KXTJ9 accelerometer, gyroscope or * magnetometer. * * Returned Value: @@ -108,7 +108,7 @@ extern "C" ****************************************************************************/ struct i2c_master_s; -int kxjt9_register(FAR const char *devpath, FAR struct i2c_master_s *i2c, +int kxtj9_register(FAR const char *devpath, FAR struct i2c_master_s *i2c, uint8_t address); #ifdef __cplusplus @@ -116,4 +116,4 @@ int kxjt9_register(FAR const char *devpath, FAR struct i2c_master_s *i2c, #endif #endif /* CONFIG_I2C && CONFIG_SENSOR_KXTJ9 */ -#endif /* __INCLUDE_NUTTX_SENSORS_KXJT9_H */ +#endif /* __INCLUDE_NUTTX_SENSORS_KXTJ9_H */ diff --git a/include/nuttx/sensors/l3gd20.h b/include/nuttx/sensors/l3gd20.h new file mode 100644 index 00000000000..95a3cedbdd8 --- /dev/null +++ b/include/nuttx/sensors/l3gd20.h @@ -0,0 +1,294 @@ +/**************************************************************************** + * include/nuttx/sensors/l3gd20.h + * + * Copyright (C) Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_SENSORS_L3GD20_H +#define __INCLUDE_NUTTX_SENSORS_L3GD20_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#if defined(CONFIG_SPI) && defined(CONFIG_SENSORS_L3GD20) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SPI BUS PARAMETERS ********************************************************/ + +#define L3GD20_SPI_FREQUENCY (4000000) /* 4 MHz */ +#define L3GD20_SPI_MODE (SPIDEV_MODE3) /* Device uses SPI Mode 3: CPOL=1, CPHA=1 * + +/* Register Addresses *******************************************************/ +/* Gyroscope registers */ + +#define L3GD20_WHO_AM_I 0x0F /* Accelerometer and gyroscope device identification */ +#define L3GD20_CTRL_REG_1 0x20 /* Gyroscope control register 1 */ +#define L3GD20_CTRL_REG_2 0x21 /* Gyroscope control register 2 */ +#define L3GD20_CTRL_REG_3 0x22 /* Gyroscope control register 3 */ +#define L3GD20_CTRL_REG_4 0x23 /* Gyroscope control register 4 */ +#define L3GD20_CTRL_REG_5 0x24 /* Gyroscope control register 5 */ +#define L3GD20_REF_REG 0x25 /* Gyroscope reference value for interrupt generation */ +#define L3GD20_OUT_TEMP_REG 0x26 /* Temperature data */ +#define L3GD20_STATUS_REG 0x27 /* Status register */ +#define L3GD20_OUT_X_L_REG 0x28 /* Gyroscope pitch (X) low byte */ +#define L3GD20_OUT_X_H_REG 0x29 /* Gyroscope pitch (X) high byte */ +#define L3GD20_OUT_Y_L_REG 0x2A /* Gyroscope roll (Y) low byte */ +#define L3GD20_OUT_Y_H_REG 0x2B /* Gyroscope roll (Y) high byte */ +#define L3GD20_OUT_Z_L_REG 0x2C /* Gyroscope yaw (Z) low byte */ +#define L3GD20_OUT_Z_H_REG 0x2D /* Gyroscope yaw (Z) high byte */ +#define L3GD20_FIFO_CTRL_REG 0x2E /* FIFO control register */ +#define L3GD20_FIFO_SRC_REG 0x2f /* FIFO status control register */ +#define L3GD20_INT_GEN_CFG_REG 0x30 /* Gyroscope interrupt configuration */ +#define L3GD20_INT_GEN_SRC_REG 0x31 /* Gyroscope interrupt source */ +#define L3GD20_INT_GEN_THS_X_H_REG 0x32 /* Gyroscope pitch (X) interrupt threshold high byte */ +#define L3GD20_INT_GEN_THS_X_L_REG 0x33 /* Gyroscope pitch (X) interrupt threshold low byte */ +#define L3GD20_INT_GEN_THS_Y_H_REG 0x34 /* Gyroscope roll (Y) interrupt threshold high byte */ +#define L3GD20_INT_GEN_THS_Y_L_REG 0x35 /* Gyroscope roll (Y) interrupt threshold low byte */ +#define L3GD20_INT_GEN_THS_Z_H_REG 0x36 /* Gyroscope yaw (Z) interrupt threshold high byte */ +#define L3GD20_INT_GEN_THS_Z_L_REG 0x37 /* Gyroscope yaw (Z) interrupt threshold low byte */ +#define L3GD20_INT_GEN_DUR_REG 0x38 /* Gyroscope interrupt duration */ + +/* Register Bit Definitions *************************************************/ + +/* Device identification register */ + +#define L3GD20_WHO_AM_I_VALUE 0xD4 + +/* Gyroscope control register 1 */ + +#define L3GD20_CTRL_REG_1_X_EN_bm (1 << 0) +#define L3GD20_CTRL_REG_1_Y_EN_bm (1 << 1) +#define L3GD20_CTRL_REG_1_Z_EN_bm (1 << 2) +#define L3GD20_CTRL_REG_1_POWERDOWN_bm (1 << 3) +#define L3GD20_CTRL_REG_1_BW_0_bm (1 << 4) +#define L3GD20_CTRL_REG_1_BW_1_bm (1 << 5) +#define L3GD20_CTRL_REG_1_DR_0_bm (1 << 6) +#define L3GD20_CTRL_REG_1_DR_1_bm (1 << 7) + +/* Gyroscope control register 2 */ + +#define L3GD20_CTRL_REG_2_HPCF_0_bm (1 << 0) +#define L3GD20_CTRL_REG_2_HPCF_1_bm (1 << 1) +#define L3GD20_CTRL_REG_2_HPCF_2_bm (1 << 2) +#define L3GD20_CTRL_REG_2_HPCF_3_bm (1 << 3) +#define L3GD20_CTRL_REG_2_HPM_0_bm (1 << 4) +#define L3GD20_CTRL_REG_2_HPM_1_bm (1 << 5) +#define L3GD20_CTRL_REG_2_RES6_ (1 << 6) +#define L3GD20_CTRL_REG_2_RES7_ (1 << 7) + +/* Gyroscope control register 3 */ + +#define L3GD20_CTRL_REG_3_I2_EMPTY_bm (1 << 0) +#define L3GD20_CTRL_REG_3_I2_ORUN_bm (1 << 1) +#define L3GD20_CTRL_REG_3_I2_WTM_bm (1 << 2) +#define L3GD20_CTRL_REG_3_I2_DRDY_bm (1 << 3) +#define L3GD20_CTRL_REG_3_PP_OD_bm (1 << 4) +#define L3GD20_CTRL_REG_3_H_LACTIVE_bm (1 << 5) +#define L3GD20_CTRL_REG_3_I1_BOOT_bm (1 << 6) +#define L3GD20_CTRL_REG_3_I1_INT1_bm (1 << 7) + + +/* Gyroscope control register 4 */ + +#define L3GD20_CTRL_REG_4_SIM_bm (1 << 0) +#define L3GD20_CTRL_REG_4_RES1_ (1 << 1) +#define L3GD20_CTRL_REG_4_RES2_ (1 << 2) +#define L3GD20_CTRL_REG_4_RES3_ (1 << 3) +#define L3GD20_CTRL_REG_4_FS_0_bm (1 << 4) +#define L3GD20_CTRL_REG_4_FS_1_bm (1 << 5) +#define L3GD20_CTRL_REG_4_BLE_bm (1 << 6) +#define L3GD20_CTRL_REG_4_BDU_bm (1 << 7) + +/* Gyroscope control register 5 */ + +#define L3GD20_CTRL_REG_5_OUT_SEL_0_bm (1 << 0) +#define L3GD20_CTRL_REG_5_OUT_SEL_1_bm (1 << 1) +#define L3GD20_CTRL_REG_5_INT1_SEL_0_bm (1 << 2) +#define L3GD20_CTRL_REG_5_INT1_SEL_1_bm (1 << 3) +#define L3GD20_CTRL_REG_5_HP_EN_bm (1 << 4) +#define L3GD20_CTRL_REG_5_RES5_ (1 << 5) +#define L3GD20_CTRL_REG_5_FIFO_EN_bm (1 << 6) +#define L3GD20_CTRL_REG_5_BOOT_bm (1 << 7) + +/* Status register */ + +#define L3GD20_STATUS_REG_X_DA_bm (1 << 0) +#define L3GD20_STATUS_REG_Y_DA_bm (1 << 1) +#define L3GD20_STATUS_REG_Z_DA_bm (1 << 2) +#define L3GD20_STATUS_REG_ZYX_DA_bm (1 << 3) +#define L3GD20_STATUS_REG_X_OR_bm (1 << 4) +#define L3GD20_STATUS_REG_Y_OR_bm (1 << 5) +#define L3GD20_STATUS_REG_Z_OR_bm (1 << 6) +#define L3GD20_STATUS_REG_ZYX_OR_bm (1 << 7) + +/* FIFO control register */ + +#define L3GD20_FIFO_CTRL_WTM_0_bm (1 << 0) +#define L3GD20_FIFO_CTRL_WTM_1_bm (1 << 1) +#define L3GD20_FIFO_CTRL_WTM_2_bm (1 << 2) +#define L3GD20_FIFO_CTRL_WTM_3_bm (1 << 3) +#define L3GD20_FIFO_CTRL_WTM_4_bm (1 << 4) +#define L3GD20_FIFO_CTRL_FM_0_bm (1 << 5) +#define L3GD20_FIFO_CTRL_FM_1_bm (1 << 6) +#define L3GD20_FIFO_CTRL_FM_2_bm (1 << 7) +#define L3GD20_FIFO_CTRL_FMODE_BYPASS (0) +#define L3GD20_FIFO_CTRL_FMODE_FIFO (L3GD20_FIFO_CTRL_FM0) +#define L3GD20_FIFO_CTRL_FMODE_CONT (L3GD20_FIFO_CTRL_FM1) +#define L3GD20_FIFO_CTRL_FMODE_CONT_FIFO (L3GD20_FIFO_CTRL_FM1 | L3GD20_FIFO_CTRL_FM0) +#define L3GD20_FIFO_CTRL_FMODE_BYPASS_CONT (L3GD20_FIFO_CTRL_FM2 | L3GD20_FIFO_CTRL_FM1) + +/* FIFO status control register */ + +#define L3GD20_FIFO_SRC_FSS_0_bm (1 << 0) +#define L3GD20_FIFO_SRC_FSS_1_bm (1 << 1) +#define L3GD20_FIFO_SRC_FSS_2_bm (1 << 2) +#define L3GD20_FIFO_SRC_FSS_3_bm (1 << 3) +#define L3GD20_FIFO_SRC_FSS_4_bm (1 << 4) +#define L3GD20_FIFO_SRC_EMPTY_bm (1 << 5) +#define L3GD20_FIFO_SRC_OVRUN_bm (1 << 6) +#define L3GD20_FIFO_SRC_WTM_bm (1 << 7) + +/* Gyroscope interrupt configuration */ + +#define L3GD20_INT_GEN_CFG_X_L_IE_bm (1 << 0) +#define L3GD20_INT_GEN_CFG_X_H_IE_bm (1 << 1) +#define L3GD20_INT_GEN_CFG_Y_L_IE_bm (1 << 2) +#define L3GD20_INT_GEN_CFG_Y_H_IE_bm (1 << 3) +#define L3GD20_INT_GEN_CFG_Z_L_IE_bm (1 << 4) +#define L3GD20_INT_GEN_CFG_Z_H_IE_bm (1 << 5) +#define L3GD20_INT_GEN_CFG_LIR_bm (1 << 6) +#define L3GD20_INT_GEN_CFG_AOI_bm (1 << 7) + + +/* Gyroscope interrupt source */ + +#define L3GD20_INT_GEN_SRC_X_L_bm (1 << 0) +#define L3GD20_INT_GEN_SRC_X_H_bm (1 << 1) +#define L3GD20_INT_GEN_SRC_Y_L_bm (1 << 2) +#define L3GD20_INT_GEN_SRC_Y_H_bm (1 << 3) +#define L3GD20_INT_GEN_SRC_Z_L_bm (1 << 4) +#define L3GD20_INT_GEN_SRC_Z_H_bm (1 << 5) +#define L3GD20_INT_GEN_SRC_I_A_bm (1 << 6) +#define L3GD20_INT_GEN_SRC_RES7_ (1 << 7) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the L3GD20 + * driver. This structure provides information about the configuration + * of the sensor and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. + */ + +struct l3gd20_config_s +{ + /* Since multiple L3GD20 can be connected to the same SPI bus we need + * to use multiple spi device ids which are employed by NuttX to select/ + * deselect the desired L3GD20 chip via their chip select inputs. + */ + + int spi_devid; + + /* The IRQ number must be provided for each L3GD20 device so that + * their interrupts can be distinguished. + */ + + int irq; + + /* Attach the L3GD20 interrupt handler to the GPIO interrupt of the + * concrete L3GD20 instance. + */ + + int (*attach)(FAR struct l3gd20_config_s *, xcpt_t); +}; + +/* Data returned by reading from the L3GD20 is returned in this format. */ + +struct l3gd20_sensor_data_s +{ + int16_t x_gyr; /* Measurement result for x axis */ + int16_t y_gyr; /* Measurement result for y axis */ + int16_t z_gyr; /* Measurement result for z axis */ + int8_t temperature; /* Measurement result for temperature sensor */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: l3gd20_register + * + * Description: + * Register the L3DF20 character device as 'devpath'. + * + * Input Parameters: + * devpath - The full path to the driver to register, e.g., "/dev/gyr0". + * i2c - An SPI driver instance. + * config - configuration for the L3GD20 driver. For details see + * description above. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int l3gd20_register(FAR const char *devpath, FAR struct spi_dev_s *spi, + FAR struct l3gd20_config_s *config); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_SPI && CONFIG_SENSORS_L3GD20 */ +#endif /* __INCLUDE_NUTTX_SENSORS_L3GD20_H */ diff --git a/include/nuttx/sensors/lis331dl.h b/include/nuttx/sensors/lis331dl.h index 8d69b5d7c35..ab86728aa2b 100644 --- a/include/nuttx/sensors/lis331dl.h +++ b/include/nuttx/sensors/lis331dl.h @@ -100,7 +100,7 @@ struct i2c_master_s; * ************************************************************************************/ -FAR struct lis331dl_dev_s *lis331dl_init(FAR struct i2c_master_s * i2c, +FAR struct lis331dl_dev_s *lis331dl_init(FAR struct i2c_master_s *i2c, uint16_t address); /************************************************************************************ @@ -117,7 +117,7 @@ FAR struct lis331dl_dev_s *lis331dl_init(FAR struct i2c_master_s * i2c, * ************************************************************************************/ -int lis331dl_deinit(FAR struct lis331dl_dev_s * dev); +int lis331dl_deinit(FAR struct lis331dl_dev_s *dev); /************************************************************************************ * Name: lis331dl_powerup @@ -127,7 +127,7 @@ int lis331dl_deinit(FAR struct lis331dl_dev_s * dev); * ************************************************************************************/ -int lis331dl_powerup(FAR struct lis331dl_dev_s * dev); +int lis331dl_powerup(FAR struct lis331dl_dev_s *dev); /************************************************************************************ * Name: lis331dl_powerdown @@ -137,7 +137,7 @@ int lis331dl_powerup(FAR struct lis331dl_dev_s * dev); * ************************************************************************************/ -int lis331dl_powerdown(FAR struct lis331dl_dev_s * dev); +int lis331dl_powerdown(FAR struct lis331dl_dev_s *dev); /************************************************************************************ * Name: lis331dl_setconversion @@ -155,7 +155,7 @@ int lis331dl_powerdown(FAR struct lis331dl_dev_s * dev); * ************************************************************************************/ -int lis331dl_setconversion(FAR struct lis331dl_dev_s * dev, bool full, bool fast); +int lis331dl_setconversion(FAR struct lis331dl_dev_s *dev, bool full, bool fast); /************************************************************************************ * Name: lis331dl_getprecision @@ -168,7 +168,7 @@ int lis331dl_setconversion(FAR struct lis331dl_dev_s * dev, bool full, bool fast * ************************************************************************************/ -int lis331dl_getprecision(FAR struct lis331dl_dev_s * dev); +int lis331dl_getprecision(FAR struct lis331dl_dev_s *dev); /************************************************************************************ * Name: lis331dl_getsamplerate @@ -181,7 +181,7 @@ int lis331dl_getprecision(FAR struct lis331dl_dev_s * dev); * ************************************************************************************/ -int lis331dl_getsamplerate(FAR struct lis331dl_dev_s * dev); +int lis331dl_getsamplerate(FAR struct lis331dl_dev_s *dev); /************************************************************************************ * Name: lis331dl_getreadings @@ -200,7 +200,7 @@ int lis331dl_getsamplerate(FAR struct lis331dl_dev_s * dev); ************************************************************************************/ FAR const struct lis331dl_vector_s * - lis331dl_getreadings(FAR struct lis331dl_dev_s * dev); + lis331dl_getreadings(FAR struct lis331dl_dev_s *dev); #undef EXTERN #if defined(__cplusplus) diff --git a/include/nuttx/sensors/qencoder.h b/include/nuttx/sensors/qencoder.h index 8a240ad1314..33041f254e9 100644 --- a/include/nuttx/sensors/qencoder.h +++ b/include/nuttx/sensors/qencoder.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/nuttx/qencoder.h * - * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -54,9 +54,9 @@ /* IOCTL Commands ***********************************************************/ /* The Quadrature Encode module uses a standard character driver framework. - * However, since the driver is a devices control interface and not a data - * transfer interface, the majority of the functionality is implemented in - * driver ioctl calls. The PWM ioctl commands are listed below: + * However, since the driver is a device control interface rather than a + * data transfer interface, the majority of the functionality is implemented + * in driver ioctl calls. The PWM ioctl commands are listed below: * * QEIOC_POSITION - Get the current position from the encoder. * Argument: int32_t pointer to the location to return the position. @@ -67,14 +67,25 @@ #define QEIOC_POSITION _QEIOC(0x0001) /* Arg: int32_t* pointer */ #define QEIOC_RESET _QEIOC(0x0002) /* Arg: None */ -/* User defined ioctl cms should use QEIOC_USER like this: - * - * #define QEIOC_MYCMD1 _QEIOC(QEIOC_USER) - * #define QEIOC_MYCMD2 _QEIOC(QEIOC_USER+1) - * ... +#define QE_FIRST 0x0001 /* First required command */ +#define QE_NCMDS 2 /* Two required commands */ + +/* User defined ioctl commands are also supported. These will be forwarded + * by the upper-half QE driver to the lower-half QE driver via the ioctl() + * method fo the QE lower-half interface. However, the lower-half driver + * must reserve a block of commands as follows in order prevent IOCTL + * command numbers from overlapping. */ -#define QEIOC_USER 0x0003 +/* See arch/arm/src/tiva/tiva_qencoder.h (Not usable at that location) */ + +#define QE_TIVA_FIRST (QE_FIRST + QE_NCMDS) +#define QE_TIVA_NCMDS 3 + +/* See include/nuttx/sensors/as5048b.h */ + +#define QE_AS5048B_FIRST (QE_TIVA_FIRST + QEIOC_TIVA_NCMDS) +#define QE_AS5048B_NCMDS 4 /**************************************************************************** * Public Types diff --git a/include/nuttx/wdog.h b/include/nuttx/wdog.h index beb13880933..7aacca711c7 100644 --- a/include/nuttx/wdog.h +++ b/include/nuttx/wdog.h @@ -165,11 +165,117 @@ extern "C" #define EXTERN extern #endif +/**************************************************************************** + * Name: wd_create + * + * Description: + * The wd_create function will create a watchdog timer by allocating one + * from the list of free watchdog timers. + * + * Parameters: + * None + * + * Return Value: + * Pointer to watchdog (i.e., the watchdog ID), or NULL if insufficient + * watchdogs are available. + * + ****************************************************************************/ + WDOG_ID wd_create(void); -int wd_delete(WDOG_ID wdog); -int wd_start(WDOG_ID wdog, int32_t delay, wdentry_t wdentry, int argc, ...); -int wd_cancel(WDOG_ID wdog); -int wd_gettime(WDOG_ID wdog); + +/**************************************************************************** + * Name: wd_delete + * + * Description: + * The wd_delete() function will deallocate a watchdog timer by returning + * it to the free pool of watchdog timers. The watchdog timer will be + * removed from the active timer queue if had been started. + * + * Parameters: + * wdog - The watchdog ID to delete. This is actually a pointer to a + * watchdog structure. + * + * Return Value: + * Returns OK or ERROR + * + * Assumptions: + * The caller has assured that the watchdog is no longer in use. + * + ****************************************************************************/ + +int wd_delete(WDOG_ID wdog); + +/**************************************************************************** + * Name: wd_start + * + * Description: + * This function adds a watchdog timer to the actuve timer queue. The + * specified watchdog function at 'wdentry' will be called from the + * interrupt level after the specified number of ticks has elapsed. + * Watchdog timers may be started from the interrupt level. + * + * Watchdog timers execute in the address environment that was in effect + * when wd_start() is called. + * + * Watchdog timers execute only once. + * + * To replace either the timeout delay or the function to be executed, + * call wd_start again with the same wdog; only the most recent wdStart() + * on a given watchdog ID has any effect. + * + * Parameters: + * wdog - watchdog ID + * delay - Delay count in clock ticks + * wdentry - function to call on timeout + * parm1..4 - parameters to pass to wdentry + * + * Return Value: + * OK or ERROR + * + * Assumptions: + * The watchdog routine runs in the context of the timer interrupt handler + * and is subject to all ISR restrictions. + * + ****************************************************************************/ + +int wd_start(WDOG_ID wdog, int32_t delay, wdentry_t wdentry, int argc, ...); + +/**************************************************************************** + * Name: wd_cancel + * + * Description: + * This function cancels a currently running watchdog timer. Watchdog + * timers may be cancelled from the interrupt level. + * + * Parameters: + * wdog - ID of the watchdog to cancel. + * + * Return Value: + * Zero (OK) is returned on success; A negated errno value is returned to + * indicate the nature of any failure. + * + ****************************************************************************/ + +int wd_cancel(WDOG_ID wdog); + +/**************************************************************************** + * Name: wd_gettime + * + * Description: + * This function returns the time remaining before the specified watchdog + * timer expires. + * + * Parameters: + * wdog - watchdog ID + * + * Return Value: + * The time in system ticks remaining until the watchdog time expires. + * Zero means either that wdog is not valid or that the wdog has already + * expired. + * + ****************************************************************************/ + +int wd_gettime(WDOG_ID wdog); #undef EXTERN #ifdef __cplusplus diff --git a/include/nuttx/wireless/cc1101.h b/include/nuttx/wireless/cc1101.h index 8d8c4992967..0f695744fb6 100644 --- a/include/nuttx/wireless/cc1101.h +++ b/include/nuttx/wireless/cc1101.h @@ -395,8 +395,8 @@ EXTERN const struct c1101_rfsettings_s cc1101_rfsettings_ISM2_905MHzGFSK250kbps; * ****************************************************************************/ -struct cc1101_dev_s * cc1101_init(struct spi_dev_s * spi, uint8_t isrpin, - uint32_t pinset, const struct c1101_rfsettings_s * rfsettings); +struct cc1101_dev_s *cc1101_init(struct spi_dev_s *spi, uint8_t isrpin, + uint32_t pinset, const struct c1101_rfsettings_s *rfsettings); /**************************************************************************** ** Deinitialize Chipcon CC1101 Chip @@ -409,31 +409,31 @@ struct cc1101_dev_s * cc1101_init(struct spi_dev_s * spi, uint8_t isrpin, * ****************************************************************************/ -int cc1101_deinit(struct cc1101_dev_s * dev); +int cc1101_deinit(struct cc1101_dev_s *dev); /**************************************************************************** * Power up device, start conversion. Returns zero on success. ****************************************************************************/ -int cc1101_powerup(struct cc1101_dev_s * dev); +int cc1101_powerup(struct cc1101_dev_s *dev); /**************************************************************************** * Power down device, stop conversion. Returns zero on success. ****************************************************************************/ -int cc1101_powerdown(struct cc1101_dev_s * dev); +int cc1101_powerdown(struct cc1101_dev_s *dev); /**************************************************************************** * Set Multi Purpose Output Function. Returns zero on success. ****************************************************************************/ -int cc1101_setgdo(struct cc1101_dev_s * dev, uint8_t pin, uint8_t function); +int cc1101_setgdo(struct cc1101_dev_s *dev, uint8_t pin, uint8_t function); /**************************************************************************** * Set RF settings. Use one from the database above. ****************************************************************************/ -int cc1101_setrf(struct cc1101_dev_s * dev, +int cc1101_setrf(struct cc1101_dev_s *dev, const struct c1101_rfsettings_s *settings); /**************************************************************************** @@ -447,7 +447,7 @@ int cc1101_setrf(struct cc1101_dev_s * dev, * ****************************************************************************/ -int cc1101_setchannel(struct cc1101_dev_s * dev, uint8_t channel); +int cc1101_setchannel(struct cc1101_dev_s *dev, uint8_t channel); /**************************************************************************** * Set Output Power @@ -465,7 +465,7 @@ int cc1101_setchannel(struct cc1101_dev_s * dev, uint8_t channel); * ****************************************************************************/ -uint8_t cc1101_setpower(struct cc1101_dev_s * dev, uint8_t power); +uint8_t cc1101_setpower(struct cc1101_dev_s *dev, uint8_t power); /**************************************************************************** * Convert RSSI as obtained from CC1101 to [dBm] */ @@ -486,7 +486,7 @@ int cc1101_calcRSSIdBm(int rssi); * ****************************************************************************/ -int cc1101_receive(struct cc1101_dev_s * dev); +int cc1101_receive(struct cc1101_dev_s *dev); /**************************************************************************** * Read received packet @@ -508,7 +508,7 @@ int cc1101_receive(struct cc1101_dev_s * dev); * ****************************************************************************/ -int cc1101_read(struct cc1101_dev_s * dev, uint8_t * buf, size_t size); +int cc1101_read(struct cc1101_dev_s *dev, uint8_t *buf, size_t size); /**************************************************************************** * Write data to be send, using the cc1101_send() @@ -522,7 +522,7 @@ int cc1101_read(struct cc1101_dev_s * dev, uint8_t * buf, size_t size); * ****************************************************************************/ -int cc1101_write(struct cc1101_dev_s * dev, const uint8_t * buf, size_t size); +int cc1101_write(struct cc1101_dev_s *dev, const uint8_t *buf, size_t size); /**************************************************************************** * Send data previously written using cc1101_write() @@ -535,7 +535,7 @@ int cc1101_write(struct cc1101_dev_s * dev, const uint8_t * buf, size_t size); * ****************************************************************************/ -int cc1101_send(struct cc1101_dev_s * dev); +int cc1101_send(struct cc1101_dev_s *dev); /**************************************************************************** * Enter idle state (after reception and transmission completes). @@ -545,7 +545,7 @@ int cc1101_send(struct cc1101_dev_s * dev); * ****************************************************************************/ -int cc1101_idle(struct cc1101_dev_s * dev); +int cc1101_idle(struct cc1101_dev_s *dev); #undef EXTERN #if defined(__cplusplus) diff --git a/include/nuttx/wireless/cc3000.h b/include/nuttx/wireless/cc3000.h index f369dc07943..6aa234ed560 100644 --- a/include/nuttx/wireless/cc3000.h +++ b/include/nuttx/wireless/cc3000.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/nuttx/wireless/cc3000.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane * @@ -56,24 +56,24 @@ * Pre-processor Definitions ****************************************************************************/ -#define DEV_FORMAT "/dev/wireless%d" /* The device Name*/ -#define DEV_NAMELEN 17 /* The buffer size to hold formatted string*/ +#define DEV_FORMAT "/dev/wireless%d" /* The device Name*/ +#define DEV_NAMELEN 17 /* The buffer size to hold formatted string*/ -#define QUEUE_FORMAT "wlq%d" /* The Queue name */ -#define QUEUE_NAMELEN 8 /* The buffer size to hold formatted string*/ +#define QUEUE_FORMAT "wlq%d" /* The Queue name */ +#define QUEUE_NAMELEN 8 /* The buffer size to hold formatted string*/ -#define SEM_FORMAT "wls%d" /* The Spi Resume Senaphore name*/ -#define SEM_NAMELEN 8 /* The buffer size to hold formatted string*/ +#define SEM_FORMAT "wls%d" /* The Spi Resume Senaphore name*/ +#define SEM_NAMELEN 8 /* The buffer size to hold formatted string*/ /* IOCTL commands */ -#define CC3000IOC_GETQUESEMID _WLIOC_USER(0x0001) /* arg: Address of int for number*/ -#define CC3000IOC_ADDSOCKET _WLIOC_USER(0x0002) /* arg: Address of int for result*/ -#define CC3000IOC_REMOVESOCKET _WLIOC_USER(0x0003) /* arg: Address of int for result*/ -#define CC3000IOC_SELECTDATA _WLIOC_USER(0x0004) /* arg: Address of int for result*/ -#define CC3000IOC_SELECTACCEPT _WLIOC_USER(0x0005) /* arg: Address of struct cc3000_acceptcfg_s */ -#define CC3000IOC_SETRX_SIZE _WLIOC_USER(0x0006) /* arg: Address of int for new size */ -#define CC3000IOC_REMOTECLOSEDSOCKET _WLIOC_USER(0x0007) /* arg: Address of int for result*/ +#define CC3000IOC_GETQUESEMID _WLIOC(CC3000_FIRST+0) /* arg: Address of int for number*/ +#define CC3000IOC_ADDSOCKET _WLIOC(CC3000_FIRST+1) /* arg: Address of int for result*/ +#define CC3000IOC_REMOVESOCKET _WLIOC(CC3000_FIRST+2) /* arg: Address of int for result*/ +#define CC3000IOC_SELECTDATA _WLIOC(CC3000_FIRST+3) /* arg: Address of int for result*/ +#define CC3000IOC_SELECTACCEPT _WLIOC(CC3000_FIRST+4) /* arg: Address of struct cc3000_acceptcfg_s */ +#define CC3000IOC_SETRX_SIZE _WLIOC(CC3000_FIRST+5) /* arg: Address of int for new size */ +#define CC3000IOC_REMOTECLOSEDSOCKET _WLIOC(CC3000_FIRST+6) /* arg: Address of int for result*/ /**************************************************************************** * Public Types diff --git a/include/nuttx/wireless/cc3000/include/cc3000_upif.h b/include/nuttx/wireless/cc3000/include/cc3000_upif.h index 26c2e109721..e24d572b009 100644 --- a/include/nuttx/wireless/cc3000/include/cc3000_upif.h +++ b/include/nuttx/wireless/cc3000/include/cc3000_upif.h @@ -138,7 +138,7 @@ struct cc3000_config_s * probe - Debug support */ - int (*irq_attach)(FAR struct cc3000_config_s *state, xcpt_t isr); + int (*irq_attach)(FAR struct cc3000_config_s *state, xcpt_t isr, FAR void *arg); void (*irq_enable)(FAR struct cc3000_config_s *state, bool enable); void (*irq_clear)(FAR struct cc3000_config_s *state); void (*power_enable)(FAR struct cc3000_config_s *state,bool enable); diff --git a/include/nuttx/wireless/nrf24l01.h b/include/nuttx/wireless/nrf24l01.h index 4ed00c1a47b..af17428d237 100644 --- a/include/nuttx/wireless/nrf24l01.h +++ b/include/nuttx/wireless/nrf24l01.h @@ -52,36 +52,36 @@ * Pre-Processor Declarations ****************************************************************************/ -#define NRF24L01_MIN_ADDR_LEN 3 /* Minimal length (in bytes) of a pipe address */ -#define NRF24L01_MAX_ADDR_LEN 5 /* Maximum length (in bytes) of a pipe address */ -#define NRF24L01_MAX_PAYLOAD_LEN 32 /* Maximum length (in bytes) of a payload */ -#define NRF24L01_MAX_XMIT_RETR 15 /* Maximum auto retransmit count (for AA transmissions) */ -#define NRF24L01_PIPE_COUNT 6 /* Number of available pipes */ +#define NRF24L01_MIN_ADDR_LEN 3 /* Minimal length (in bytes) of a pipe address */ +#define NRF24L01_MAX_ADDR_LEN 5 /* Maximum length (in bytes) of a pipe address */ +#define NRF24L01_MAX_PAYLOAD_LEN 32 /* Maximum length (in bytes) of a payload */ +#define NRF24L01_MAX_XMIT_RETR 15 /* Maximum auto retransmit count (for AA transmissions) */ +#define NRF24L01_PIPE_COUNT 6 /* Number of available pipes */ -#define NRF24L01_MIN_FREQ 2400 /* Lower bound for RF frequency */ -#define NRF24L01_MAX_FREQ 2525 /* Upper bound for RF frequency */ +#define NRF24L01_MIN_FREQ 2400 /* Lower bound for RF frequency */ +#define NRF24L01_MAX_FREQ 2525 /* Upper bound for RF frequency */ -#define NRF24L01_DYN_LENGTH 33 /* Specific length value to use to enable dynamic packet length */ -#define NRF24L01_XMIT_MAXRT 255 /* Specific value returned by Number of available pipes */ +#define NRF24L01_DYN_LENGTH 33 /* Specific length value to use to enable dynamic packet length */ +#define NRF24L01_XMIT_MAXRT 255 /* Specific value returned by Number of available pipes */ -/* #define NRF24L01_DEBUG 1 */ +/* #define NRF24L01_DEBUG 1 */ /* IOCTL commands */ -#define NRF24L01IOC_SETRETRCFG _WLIOC_USER(0x0001) /* arg: Pointer to nrf24l01_retrcfg_t structure */ -#define NRF24L01IOC_GETRETRCFG _WLIOC_USER(0x0002) /* arg: Pointer to nrf24l01_retrcfg_t structure */ -#define NRF24L01IOC_SETPIPESCFG _WLIOC_USER(0x0003) /* arg: Pointer to an array of nrf24l01_pipecfg_t pointers */ -#define NRF24L01IOC_GETPIPESCFG _WLIOC_USER(0x0004) /* arg: Pointer to an array of nrf24l01_pipecfg_t pointers */ -#define NRF24L01IOC_SETPIPESENABLED _WLIOC_USER(0x0005) /* arg: Pointer to a uint8_t value, bit field of enabled / disabled pipes */ -#define NRF24L01IOC_GETPIPESENABLED _WLIOC_USER(0x0006) /* arg: Pointer to a uint8_t value, bit field of enabled / disabled pipes */ -#define NRF24L01IOC_SETDATARATE _WLIOC_USER(0x0007) /* arg: Pointer to a nrf24l01_datarate_t value */ -#define NRF24L01IOC_GETDATARATE _WLIOC_USER(0x0008) /* arg: Pointer to a nrf24l01_datarate_t value */ -#define NRF24L01IOC_SETADDRWIDTH _WLIOC_USER(0x0009) /* arg: Pointer to an uint32_t value, width of the address */ -#define NRF24L01IOC_GETADDRWIDTH _WLIOC_USER(0x000A) /* arg: Pointer to an uint32_t value, width of the address */ -#define NRF24L01IOC_SETSTATE _WLIOC_USER(0x000B) /* arg: Pointer to a nrf24l01_state_t value */ -#define NRF24L01IOC_GETSTATE _WLIOC_USER(0x000C) /* arg: Pointer to a nrf24l01_state_t value */ -#define NRF24L01IOC_GETLASTXMITCOUNT _WLIOC_USER(0x000D) /* arg: Pointer to an uint32_t value, retransmission count of the last send operation (NRF24L01_XMIT_MAXRT if no ACK received)*/ -#define NRF24L01IOC_GETLASTPIPENO _WLIOC_USER(0x000E) /* arg: Pointer to an uint32_t value, pipe # of the last received packet */ +#define NRF24L01IOC_SETRETRCFG _WLIOC(NRF24L01_FIRST+0) /* arg: Pointer to nrf24l01_retrcfg_t structure */ +#define NRF24L01IOC_GETRETRCFG _WLIOC(NRF24L01_FIRST+1) /* arg: Pointer to nrf24l01_retrcfg_t structure */ +#define NRF24L01IOC_SETPIPESCFG _WLIOC(NRF24L01_FIRST+2) /* arg: Pointer to an array of nrf24l01_pipecfg_t pointers */ +#define NRF24L01IOC_GETPIPESCFG _WLIOC(NRF24L01_FIRST+3) /* arg: Pointer to an array of nrf24l01_pipecfg_t pointers */ +#define NRF24L01IOC_SETPIPESENABLED _WLIOC(NRF24L01_FIRST+4) /* arg: Pointer to a uint8_t value, bit field of enabled / disabled pipes */ +#define NRF24L01IOC_GETPIPESENABLED _WLIOC(NRF24L01_FIRST+5) /* arg: Pointer to a uint8_t value, bit field of enabled / disabled pipes */ +#define NRF24L01IOC_SETDATARATE _WLIOC(NRF24L01_FIRST+6) /* arg: Pointer to a nrf24l01_datarate_t value */ +#define NRF24L01IOC_GETDATARATE _WLIOC(NRF24L01_FIRST+7) /* arg: Pointer to a nrf24l01_datarate_t value */ +#define NRF24L01IOC_SETADDRWIDTH _WLIOC(NRF24L01_FIRST+8) /* arg: Pointer to an uint32_t value, width of the address */ +#define NRF24L01IOC_GETADDRWIDTH _WLIOC(NRF24L01_FIRST+9) /* arg: Pointer to an uint32_t value, width of the address */ +#define NRF24L01IOC_SETSTATE _WLIOC(NRF24L01_FIRST+10) /* arg: Pointer to a nrf24l01_state_t value */ +#define NRF24L01IOC_GETSTATE _WLIOC(NRF24L01_FIRST+11) /* arg: Pointer to a nrf24l01_state_t value */ +#define NRF24L01IOC_GETLASTXMITCOUNT _WLIOC(NRF24L01_FIRST+12) /* arg: Pointer to an uint32_t value, retransmission count of the last send operation (NRF24L01_XMIT_MAXRT if no ACK received)*/ +#define NRF24L01IOC_GETLASTPIPENO _WLIOC(NRF24L01_FIRST+13) /* arg: Pointer to an uint32_t value, pipe # of the last received packet */ /* Aliased name for these commands */ @@ -92,7 +92,7 @@ #ifdef NRF24L01_DEBUG # define werr(format, ...) _err(format, ##__VA_ARGS__) -# define werr(format, ...) _err(format, ##__VA_ARGS__) +# define werr(format, ...) _err(format, ##__VA_ARGS__) # define winfo(format, ...) _info(format, ##__VA_ARGS__) #else # define werr(x...) @@ -199,7 +199,7 @@ struct nrf24l01_config_s * chipenable - Enable or disable the chip (CE line) */ - int (*irqattach)(xcpt_t isr); + int (*irqattach)(xcpt_t isr, FAR void *arg); void (*chipenable)(bool enable); }; @@ -235,12 +235,6 @@ int nrf24l01_register(FAR struct spi_dev_s *spi, FAR struct nrf24l01_config_s *c int nrf24l01_init(FAR struct nrf24l01_dev_s *dev); -/************************************************************************************ - * Get a pointer to the registered device - ************************************************************************************/ - -FAR struct nrf24l01_dev_s * nrf24l01_getinstance(void); - /************************************************************************************ * Set the default TX address. * diff --git a/include/nuttx/wireless/wireless.h b/include/nuttx/wireless/wireless.h index fd87265228d..f1726691140 100644 --- a/include/nuttx/wireless/wireless.h +++ b/include/nuttx/wireless/wireless.h @@ -1,7 +1,7 @@ /************************************************************************************ * include/nuttx/wireless/wireless.h * - * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2013, 2017 Gregory Nutt. All rights reserved. * Author: Laurent Latil * * Redistribution and use in source and binary forms, with or without @@ -52,7 +52,9 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ + /* IOCTL Commands *******************************************************************/ +/* Common wireless IOCTL commands */ #define WLIOC_SETRADIOFREQ _WLIOC(0x0001) /* arg: Pointer to uint32_t, frequency value (in Mhz) */ #define WLIOC_GETRADIOFREQ _WLIOC(0x0002) /* arg: Pointer to uint32_t, frequency value (in Mhz) */ @@ -61,14 +63,25 @@ #define WLIOC_SETTXPOWER _WLIOC(0x0005) /* arg: Pointer to int32_t, output power (in dBm) */ #define WLIOC_GETTXPOWER _WLIOC(0x0006) /* arg: Pointer to int32_t, output power (in dBm) */ -/* Wireless drivers can provide additional, device specific ioctl - * commands, beginning with this value: +#define WL_FIRST 0x0001 /* First common command */ +#define WL_NCMDS 6 /* Six common commands */ + +/* User defined ioctl commands are also supported. These will be forwarded + * by the upper-half QE driver to the lower-half QE driver via the ioctl() + * method fo the QE lower-half interface. However, the lower-half driver + * must reserve a block of commands as follows in order prevent IOCTL + * command numbers from overlapping. */ -#define WLIOC_USER 0x0007 /* Lowest, unused WL ioctl command */ +/* See include/nuttx/wireless/cc3000.h */ -#define _WLIOC_USER(nr) _WLIOC(nr + WLIOC_USER) +#define CC3000_FIRST (WL_FIRST + WL_NCMDS) +#define CC3000_NCMDS 7 -#endif +/* See include/nuttx/wireless/nrf24l01.h */ -#endif /* __INCLUDE_NUTTX_WIRELESS_H */ +#define NRF24L01_FIRST (CC3000_FIRST + CC3000_NCMDS) +#define NRF24L01_NCMDS 14 + +#endif /* CONFIG_DRIVERS_WIRELESS */ +#endif /* __INCLUDE_NUTTX_WIRELESS_H */ diff --git a/include/strings.h b/include/strings.h index bff724d9ba3..4b7fc439da4 100644 --- a/include/strings.h +++ b/include/strings.h @@ -47,20 +47,24 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Compatibility definitions */ -#define bcmp(b1,b2,len) memcmp(b1,b2,(size_t)len) -#define bcopy(b1,b2,len) (void)memmove(b2,b1,len) +#if !defined(CONFIG_HAVE_INLINE) && !defined(__cplusplus) +/* Compatibility definitions + * + * Marked LEGACY in Open Group Base Specifications Issue 6/IEEE Std 1003.1-2004 + * Removed from Open Group Base Specifications Issue 7/IEEE Std 1003.1-2008 + */ -#ifndef CONFIG_LIBC_ARCH_BZERO -# define bzero(s,n) (void)memset(s,0,n) -#endif +# define bcmp(b1,b2,len) memcmp(b1,b2,(size_t)len) +# define bcopy(b1,b2,len) (void)memmove(b2,b1,len) +# define bzero(s,n) (void)memset(s,0,n) +# define index(s,c) strchr(s,c) +# define rindex(s,c) strrchr(s,c) -#define index(s,c) strchr(s,c) -#define rindex(s,c) strrchr(s,c) +#endif /* !CONFIG_HAVE_INLINE && !__cplusplus */ /**************************************************************************** - * Public Function Prototypes + * Inline Functions ****************************************************************************/ #undef EXTERN @@ -72,6 +76,43 @@ extern "C" #define EXTERN extern #endif +#if defined(CONFIG_HAVE_INLINE) || defined(__cplusplus) +/* Compatibility inline functions. + * + * Marked LEGACY in Open Group Base Specifications Issue 6/IEEE Std 1003.1-2004 + * Removed from Open Group Base Specifications Issue 7/IEEE Std 1003.1-2008 + */ + +static inline int bcmp(FAR const void *b1, FAR const void *b2, size_t len) +{ + return memcmp(b1, b2, len); +} + +static inline void bcopy(FAR const void *b1, FAR void *b2, size_t len) +{ + (void)memmove(b2, b1, len); +} + +static inline void bzero(FAR void *s, size_t len) +{ + (void)memset(s, 0, len); +} + +static inline FAR char *index(FAR const char *s, int c) +{ + return strchr(s, c); +} + +static inline FAR char *rindex(FAR const char *s, int c) +{ + return strrchr(s, c); +} +#endif /* CONFIG_HAVE_INLINE || __cplusplus */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + int ffs(int j); int strcasecmp(FAR const char *, FAR const char *); int strncasecmp(FAR const char *, FAR const char *, size_t); diff --git a/include/sys/syscall.h b/include/sys/syscall.h index a3dadd9eecf..101816d7ff0 100644 --- a/include/sys/syscall.h +++ b/include/sys/syscall.h @@ -326,11 +326,11 @@ # define SYS_telldir (__SYS_filedesc+15) # if defined(CONFIG_PSEUDOFS_SOFTLINKS) -# define SYS_link (__SYS_filedesc+15) -# define SYS_readlink (__SYS_filedesc+16) -# define __SYS_pipes (__SYS_filedesc+17) +# define SYS_link (__SYS_filedesc+16) +# define SYS_readlink (__SYS_filedesc+17) +# define __SYS_pipes (__SYS_filedesc+18) # else -# define __SYS_pipes (__SYS_filedesc+15) +# define __SYS_pipes (__SYS_filedesc+16) # endif # if defined(CONFIG_PIPES) && CONFIG_DEV_PIPE_SIZE > 0 diff --git a/libc/machine/Kconfig b/libc/machine/Kconfig index 693ede6a7f3..cd5c2905d2f 100644 --- a/libc/machine/Kconfig +++ b/libc/machine/Kconfig @@ -84,10 +84,6 @@ config LIBC_ARCH_STRNLEN bool default n -config LIBC_ARCH_BZERO - bool - default n - config LIBC_ARCH_ELF bool default n diff --git a/libc/stdio/lib_dtoa.c b/libc/stdio/lib_dtoa.c index 1e85bc3e0f6..ab03d9b4a4a 100644 --- a/libc/stdio/lib_dtoa.c +++ b/libc/stdio/lib_dtoa.c @@ -819,11 +819,6 @@ static const double bigtens[] = 1e16, 1e32, 1e64, 1e128, 1e256 }; -static const double tinytens[] = -{ - 1e-16, 1e-32, 1e-64, 1e-128, 1e-256 -}; - # define n_bigtens 5 #else static const double bigtens[] = @@ -831,11 +826,6 @@ static const double bigtens[] = 1e16, 1e32 }; -static const double tinytens[] = -{ - 1e-16, 1e-32 -}; - # define n_bigtens 2 #endif diff --git a/libc/string/lib_strcasestr.c b/libc/string/lib_strcasestr.c index ab8df1eede2..e7ab021ffad 100644 --- a/libc/string/lib_strcasestr.c +++ b/libc/string/lib_strcasestr.c @@ -1,7 +1,7 @@ /**************************************************************************** - * libc/string/lib_strstr.c + * libc/string/lib_strcasestr.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use str source and binary forms, with or without @@ -40,6 +40,7 @@ #include #include +#include #include /**************************************************************************** diff --git a/sched/irq/irq.h b/sched/irq/irq.h index a7b4b431ab3..59bd5ea2436 100644 --- a/sched/irq/irq.h +++ b/sched/irq/irq.h @@ -50,6 +50,22 @@ #include #include +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* This is the type of the list of interrupt handlers, one for each IRQ. + * This type provided all of the information necessary to irq_dispatch to + * transfer control to interrupt handlers after the occurrence of an + * interrupt. + */ + +struct irq +{ + xcpt_t handler; /* Address of the interrupt handler */ + FAR void *arg; /* The argument provided to the interrupt handler. */ +}; + /**************************************************************************** * Public Data ****************************************************************************/ @@ -59,7 +75,7 @@ * occurrence of an interrupt. */ -extern FAR xcpt_t g_irqvector[NR_IRQS]; +extern struct irq g_irqvector[NR_IRQS]; #ifdef CONFIG_SMP /* This is the spinlock that enforces critical sections when interrupts are @@ -109,7 +125,7 @@ void weak_function irq_initialize(void); * ****************************************************************************/ -int irq_unexpected_isr(int irq, FAR void *context); +int irq_unexpected_isr(int irq, FAR void *context, FAR void *arg); /**************************************************************************** * Name: irq_cpu_locked diff --git a/sched/irq/irq_attach.c b/sched/irq/irq_attach.c index d111eeb5c78..218ceb7ca1f 100644 --- a/sched/irq/irq_attach.c +++ b/sched/irq/irq_attach.c @@ -43,26 +43,6 @@ #include "irq/irq.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Type Declarations - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -76,7 +56,7 @@ * ****************************************************************************/ -int irq_attach(int irq, xcpt_t isr) +int irq_attach(int irq, xcpt_t isr, FAR void *arg) { #if NR_IRQS > 0 int ret = ERROR; @@ -111,11 +91,13 @@ int irq_attach(int irq, xcpt_t isr) */ isr = irq_unexpected_isr; + arg = NULL; } /* Save the new ISR in the table. */ - g_irqvector[irq] = isr; + g_irqvector[irq].handler = isr; + g_irqvector[irq].arg = arg; leave_critical_section(flags); ret = OK; } diff --git a/sched/irq/irq_dispatch.c b/sched/irq/irq_dispatch.c index becc5b09795..576e7576289 100644 --- a/sched/irq/irq_dispatch.c +++ b/sched/irq/irq_dispatch.c @@ -62,17 +62,20 @@ void irq_dispatch(int irq, FAR void *context) { xcpt_t vector; + FAR void *arg; /* Perform some sanity checks */ #if NR_IRQS > 0 - if ((unsigned)irq >= NR_IRQS || g_irqvector[irq] == NULL) + if ((unsigned)irq >= NR_IRQS || g_irqvector[irq].handler == NULL) { vector = irq_unexpected_isr; + arg = NULL; } else { - vector = g_irqvector[irq]; + vector = g_irqvector[irq].handler; + arg = g_irqvector[irq].arg; } #else vector = irq_unexpected_isr; @@ -80,5 +83,5 @@ void irq_dispatch(int irq, FAR void *context) /* Then dispatch to the interrupt handler */ - vector(irq, context); + vector(irq, context, arg); } diff --git a/sched/irq/irq_initialize.c b/sched/irq/irq_initialize.c index 50bbc581bf1..e03d27abdc8 100644 --- a/sched/irq/irq_initialize.c +++ b/sched/irq/irq_initialize.c @@ -47,7 +47,7 @@ * Public Data ****************************************************************************/ -FAR xcpt_t g_irqvector[NR_IRQS]; +struct irq g_irqvector[NR_IRQS]; /**************************************************************************** * Public Functions @@ -69,6 +69,7 @@ void irq_initialize(void) for (i = 0; i < NR_IRQS; i++) { - g_irqvector[i] = irq_unexpected_isr; + g_irqvector[i].handler = irq_unexpected_isr; + g_irqvector[i].arg = NULL; } } diff --git a/sched/irq/irq_unexpectedisr.c b/sched/irq/irq_unexpectedisr.c index 9eb250fa491..ae3097786f1 100644 --- a/sched/irq/irq_unexpectedisr.c +++ b/sched/irq/irq_unexpectedisr.c @@ -58,7 +58,7 @@ * ****************************************************************************/ -int irq_unexpected_isr(int irq, FAR void *context) +int irq_unexpected_isr(int irq, FAR void *context, FAR void *arg) { (void)up_irq_save(); _err("ERROR irq: %d\n", irq); diff --git a/sched/mqueue/mq_sndinternal.c b/sched/mqueue/mq_sndinternal.c index 946c69275ce..12fb9948415 100644 --- a/sched/mqueue/mq_sndinternal.c +++ b/sched/mqueue/mq_sndinternal.c @@ -224,7 +224,7 @@ FAR struct mqueue_msg_s *mq_msgalloc(void) * * Assumptions/restrictions: * - The caller has verified the input parameters using mq_verifysend(). - * - Interrupts are disabled. + * - Executes within a critical section established by the caller. * ****************************************************************************/ diff --git a/sched/pthread/pthread_create.c b/sched/pthread/pthread_create.c index 7a4e628e00d..957936cd826 100644 --- a/sched/pthread/pthread_create.c +++ b/sched/pthread/pthread_create.c @@ -1,7 +1,7 @@ /**************************************************************************** * sched/pthread/pthread_create.c * - * Copyright (C) 2007-2009, 2011, 2013-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2011, 2013-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -75,9 +75,11 @@ const pthread_attr_t g_default_pthread_attr = PTHREAD_ATTR_INITIALIZER; * Private Data ****************************************************************************/ +#if CONFIG_TASK_NAME_SIZE > 0 /* This is the name for name-less pthreads */ static const char g_pthreadname[] = ""; +#endif /**************************************************************************** * Private Functions diff --git a/sched/pthread/pthread_mutexlock.c b/sched/pthread/pthread_mutexlock.c index ebd650df6fb..f94890505df 100644 --- a/sched/pthread/pthread_mutexlock.c +++ b/sched/pthread/pthread_mutexlock.c @@ -150,7 +150,7 @@ int pthread_mutex_lock(FAR pthread_mutex_t *mutex) ret = pthread_takesemaphore((FAR sem_t *)&mutex->sem); - /* If we succussfully obtained the semaphore, then indicate + /* If we successfully obtained the semaphore, then indicate * that we own it. */ diff --git a/sched/sched/sched_processtimer.c b/sched/sched/sched_processtimer.c index d8bcc3e1110..d928d40649c 100644 --- a/sched/sched/sched_processtimer.c +++ b/sched/sched/sched_processtimer.c @@ -124,9 +124,18 @@ static inline void sched_process_scheduler(void) irqstate_t flags; int i; - /* Perform scheduler operations on all CPUs */ + /* If we are running on a single CPU architecture, then we know interrupts + * a disabled an there is no need to explicitly call + * enter_critical_section(). However, in the SMP case, + * enter_critical_section() does much more than just disable interrupts on + * the local CPU; it also manages spinlocks to assure the stability of the + * TCB that we are manipulating. + */ flags = enter_critical_section(); + + /* Perform scheduler operations on all CPUs */ + for (i = 0; i < CONFIG_SMP_NCPUS; i++) { sched_cpu_scheduler(i); diff --git a/sched/sched/sched_timerexpiration.c b/sched/sched/sched_timerexpiration.c index 47095306cf0..174ff1f7a70 100644 --- a/sched/sched/sched_timerexpiration.c +++ b/sched/sched/sched_timerexpiration.c @@ -290,9 +290,18 @@ static uint32_t sched_process_scheduler(uint32_t ticks, bool noswitches) irqstate_t flags; int i; - /* Perform scheduler operations on all CPUs */ + /* If we are running on a single CPU architecture, then we know interrupts + * a disabled an there is no need to explicitly call + * enter_critical_section(). However, in the SMP case, + * enter_critical_section() does much more than just disable interrupts on + * the local CPU; it also manages spinlocks to assure the stability of the + * TCB that we are manipulating. + */ flags = enter_critical_section(); + + /* Perform scheduler operations on all CPUs */ + for (i = 0; i < CONFIG_SMP_NCPUS; i++) { timeslice = sched_cpu_scheduler(i, ticks, noswitches); diff --git a/sched/sched/sched_unlock.c b/sched/sched/sched_unlock.c index d22a4b48bd6..091ad7b1cb0 100644 --- a/sched/sched/sched_unlock.c +++ b/sched/sched/sched_unlock.c @@ -145,7 +145,6 @@ int sched_unlock(void) * we should go ahead and release the pending tasks. See the logic * leave_critical_section(): It will call up_release_pending() * BEFORE it clears IRQ lock. - * BEFORE it clears IRQ lock. */ if (!spin_islocked(&g_cpu_schedlock) && !irq_cpu_locked(cpu) && diff --git a/sched/signal/sig_timedwait.c b/sched/signal/sig_timedwait.c index bdb5376d8bd..dcbc892fd97 100644 --- a/sched/signal/sig_timedwait.c +++ b/sched/signal/sig_timedwait.c @@ -1,7 +1,7 @@ /**************************************************************************** * sched/signal/sig_timedwait.c * - * Copyright (C) 2007-2009, 2012-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2012-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -76,12 +76,20 @@ * Name: sig_timeout * * Description: - * A timeout elapsed while waiting for signals to be queued. + * A timeout elapsed while waiting for signals to be queued. + * + * Assumptions: + * This function executes in the context of the timer interrupt handler. + * Local interrupts are assumed to be disabled on entry. * ****************************************************************************/ static void sig_timeout(int argc, wdparm_t itcb) { +#ifdef CONFIG_SMP + irqstate_t flags; +#endif + /* On many small machines, pointers are encoded and cannot be simply cast * from uint32_t to struct tcb_s *. The following union works around this * (see wdogparm_t). This odd logic could be conditioned on @@ -97,6 +105,19 @@ static void sig_timeout(int argc, wdparm_t itcb) u.itcb = itcb; ASSERT(u.wtcb); +#ifdef CONFIG_SMP + /* We must be in a critical section in order to call up_unblock_task() + * below. If we are running on a single CPU architecture, then we know + * interrupts a disabled an there is no need to explicitly call + * enter_critical_section(). However, in the SMP case, + * enter_critical_section() does much more than just disable interrupts on + * the local CPU; it also manages spinlocks to assure the stability of the + * TCB that we are manipulating. + */ + + flags = enter_critical_section(); +#endif + /* There may be a race condition -- make sure the task is * still waiting for a signal */ @@ -113,6 +134,10 @@ static void sig_timeout(int argc, wdparm_t itcb) #endif up_unblock_task(u.wtcb); } + +#ifdef CONFIG_SMP + leave_critical_section(flags); +#endif } /**************************************************************************** diff --git a/sched/task/task_exit.c b/sched/task/task_exit.c index 26d30ba3dbc..e8f3b9cd595 100644 --- a/sched/task/task_exit.c +++ b/sched/task/task_exit.c @@ -76,7 +76,7 @@ * OK on success; or ERROR on failure * * Assumeptions: - * Interrupts are disabled. + * Executing within a critical section established by the caller. * ****************************************************************************/ diff --git a/sched/wdog/wd_cancel.c b/sched/wdog/wd_cancel.c index ac8db7ed337..040385d31d5 100644 --- a/sched/wdog/wd_cancel.c +++ b/sched/wdog/wd_cancel.c @@ -1,7 +1,7 @@ /**************************************************************************** * sched/wdog/wd_cancel.c * - * Copyright (C) 2007-2009, 2014, 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2014, 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -41,6 +41,7 @@ #include #include +#include #include #include @@ -64,9 +65,8 @@ * wdog - ID of the watchdog to cancel. * * Return Value: - * OK or ERROR - * - * Assumptions: + * Zero (OK) is returned on success; A negated errno value is returned to + * indicate the nature of any failure. * ****************************************************************************/ @@ -75,7 +75,7 @@ int wd_cancel(WDOG_ID wdog) FAR struct wdog_s *curr; FAR struct wdog_s *prev; irqstate_t flags; - int ret = ERROR; + int ret = -EINVAL; /* Prohibit timer interactions with the timer queue until the * cancellation is complete @@ -87,7 +87,7 @@ int wd_cancel(WDOG_ID wdog) * active. */ - if (wdog && WDOG_ISACTIVE(wdog)) + if (wdog != NULL && WDOG_ISACTIVE(wdog)) { /* Search the g_wdactivelist for the target FCB. We can't use sq_rem * to do this because there are additional operations that need to be diff --git a/sched/wdog/wd_create.c b/sched/wdog/wd_create.c index 416da9c351f..6b9f944cd93 100644 --- a/sched/wdog/wd_create.c +++ b/sched/wdog/wd_create.c @@ -57,8 +57,8 @@ * Name: wd_create * * Description: - * The wd_create function will create a watchdog by allocating it from the - * list of free watchdogs. + * The wd_create function will create a watchdog timer by allocating one + * from the list of free watchdog timers. * * Parameters: * None @@ -67,8 +67,6 @@ * Pointer to watchdog (i.e., the watchdog ID), or NULL if insufficient * watchdogs are available. * - * Assumptions: - * ****************************************************************************/ WDOG_ID wd_create (void) diff --git a/sched/wdog/wd_delete.c b/sched/wdog/wd_delete.c index d28252fce47..a497c1146e0 100644 --- a/sched/wdog/wd_delete.c +++ b/sched/wdog/wd_delete.c @@ -58,9 +58,9 @@ * Name: wd_delete * * Description: - * The wd_delete function will deallocate a watchdog by returning it to - * the free pool of watchdogs. The watchdog will be removed from the timer - * queue if has been started. + * The wd_delete() function will deallocate a watchdog timer by returning + * it to the free pool of watchdog timers. The watchdog timer will be + * removed from the active timer queue if had been started. * * Parameters: * wdog - The watchdog ID to delete. This is actually a pointer to a diff --git a/sched/wdog/wd_gettime.c b/sched/wdog/wd_gettime.c index 3027b29636e..0e48dec2f38 100644 --- a/sched/wdog/wd_gettime.c +++ b/sched/wdog/wd_gettime.c @@ -53,10 +53,10 @@ * * Description: * This function returns the time remaining before the specified watchdog - * expires. + * timer expires. * * Parameters: - * wdog = watchdog ID + * wdog - watchdog ID * * Return Value: * The time in system ticks remaining until the watchdog time expires. @@ -72,7 +72,7 @@ int wd_gettime(WDOG_ID wdog) /* Verify the wdog */ flags = enter_critical_section(); - if (wdog && WDOG_ISACTIVE(wdog)) + if (wdog != NULL && WDOG_ISACTIVE(wdog)) { /* Traverse the watchdog list accumulating lag times until we find the * wdog that we are looking for diff --git a/sched/wdog/wd_start.c b/sched/wdog/wd_start.c index 149b95427e1..227a7933bd9 100644 --- a/sched/wdog/wd_start.c +++ b/sched/wdog/wd_start.c @@ -190,10 +190,10 @@ static inline void wd_expiration(void) * Name: wd_start * * Description: - * This function adds a watchdog to the timer queue. The specified - * watchdog function will be called from the interrupt level after the - * specified number of ticks has elapsed. Watchdog timers may be started - * from the interrupt level. + * This function adds a watchdog timer to the actuve timer queue. The + * specified watchdog function at 'wdentry' will be called from the + * interrupt level after the specified number of ticks has elapsed. + * Watchdog timers may be started from the interrupt level. * * Watchdog timers execute in the address environment that was in effect * when wd_start() is called. @@ -205,10 +205,10 @@ static inline void wd_expiration(void) * on a given watchdog ID has any effect. * * Parameters: - * wdog = watchdog ID - * delay = Delay count in clock ticks - * wdentry = function to call on timeout - * parm1..4 = parameters to pass to wdentry + * wdog - watchdog ID + * delay - Delay count in clock ticks + * wdentry - function to call on timeout + * parm1..4 - parameters to pass to wdentry * * Return Value: * OK or ERROR