Merged nuttx/nuttx into master

COPYING

@@ -93,7 +93,7 @@ has a similar BSD style license:
 IGMP
 ^^^^
 
-IGMP support, if enabled in uIP, adds additional logic by Steve Reynolds:
+IGMP support, if enabled, adds additional logic by Steve Reynolds:
 
   Copyright (c) 2002 CITEL Technologies Ltd.
   All rights reserved.

ChangeLog

@@ -10401,7 +10401,7 @@
 	* arch/arm/src/efm32/efm32_rtc_burtc.c: Updated EFM32 RTC driver from
 	  Pierre-noel Bouteville (2015-05-19).
 	* arch/arm/src/tiva/chip/tm4c_memorymap.h, tm4c_pinmap.h, and vectors.h.
-	  configs/tm4c1294-launchpad/include/board.h and src/tm4c_autoleds.c: 
+	  configs/tm4c1294-launchpad/include/board.h and src/tm4c_autoleds.c:
 	  Fixes for Tiva TM4C1294NCPDT.  From Frank Sautter.  (2015-05-20).
 	* configs/tm4c1294-launchpad/include/board.h:  Added TM4C1294NCPDT
 	  EN0_LED2 (10/100-Base-Tx); removed all booster pack pin definitions.
@@ -11376,7 +11376,7 @@
 	  I2C_READ and I2C_WRITE which are not thread safe (2016-01-26).
 	* SPI: Rename the STM32 up_spiinitialize() to stm32_spibus_initialize()
 	  (2016-01-26).
-	* SPI: Rename the SAM up_spiinitialize() to stm32_spibus_initialize()
+	* SPI: Rename the SAM up_spiinitialize() to sam_spibus_initialize()
 	  (2016-01-26).
 	* SPI: Rename the Tiva up_spiinitialize() to tiva_spibus_intialize()
 	  (2016-01-26).
@@ -11625,13 +11625,13 @@
 	* configs/nucleus2g:  Removed the Nucleus2G configuration.  There has
 	  not been any activity with the commercial board in a few years and it
 	  no longer appears to be available from the 2g-eng.com website.
-	  Since the board is commercial and no longer publically available, it
+	  Since the board is commercial and no longer publicly available, it
 	  no longer qualifies for inclusion in the open source repositories.
 	  The code as of this data is still available in the Obsoleted
 	  repository at configs/nucleus2g (2016-04-12).
 	* arch/arm/src/stm32l4: Fix the STM32L4 SPI driver.  That SPI driver is
 	  quite different. They now handle frames of arbitrary size between 4
-	  and 16 bits. It was broken before a new bit has to be set (rx fifo
+	  and 16 bits. It was broken before a new bit has to be set (RX fifo
 	  threshold) to handle <= 8-bit transactions. If not set, the default is
 	  16-bit packed >=8-bit frames and the RXNE bit is never set (it is set
 	  when 16-bits are received). weird things as always.
@@ -11652,6 +11652,220 @@
 	* drivers/wireless/nrf24l01.c: Fix backward calculation of relative
 	  frequency.  Noted by Henry Zhang (2015-04-15).
 	* drivers/sensors/h1750fvi.c:  Add a character driver for Rohm Ambient
-	  Light Sensor BH1750FVI.  From Alan Carvalho de Assi (2016-04-15).
+	  Light Sensor BH1750FVI.  From Alan Carvalho de Assis (2016-04-15).
 	* configs/stm32f4discovery: Integrate BH1750FVI driver in the
-	  STM32F4Discovery board.  From Alan Carvalho de Assi (2016-04-15).
+	  STM32F4Discovery board.  From Alan Carvalho de Assis (2016-04-15).
+	* drivers/mtd: Add MTD support for Micron N25Qxxx family of QSPI flash.
+	  From Dave dev@ziggurat29.com (2016-04-17).
+	* arch/arm/src/stm32l: Add a QSPI driver. From Dave dev@ziggurat29.com
+	  (2016-04-18).
+	* configs/stm32l476vb-disco:  Add support for QSPI based N25Qxxx flash.
+	  From Dave dev@ziggurat29.com (2016-04-18).
+	* graphics/vnc:  Add support for a VNC server.  This logic is code
+	  complete, but untested and so not ready for prime time (2016-04-18).
+	* configs/samv71-xult/vnc:  Add a configuration that will be used to
+	  verify VNC (also untested) (2016-04-18).
+	* drivers/ioexpander: Fix an error in the PCA9555 driver: Under certain
+	  error conditions, interrupts were not being re-enabled.  Sebastien
+	  Lorquet (2016-04-20).
+	* arch/arm/src/stm32 and configs/stm32f429i-disco:  Correct some bad
+	  commits that broke the LTDC display example.  From Marco Krahl
+	  (2016-04-22).
+	* configs/samv71-xult/vncwwm:  Add a more complex NxWM configuration
+	  to support further VNC testing (particularly of VNC keyboard and
+	  mouse inputs).  Initial configuration is not functional (2016-04-23).
+	* arch/arm/src/stm32l4: Add support for QSPI DMA. From Dave
+	  dev@ziggurat29.com (2016-04-24).
+	* configs/stm32l476vg-disco: Update stm32l4 disco board to reflect QSPI
+	  DMA support. From Dave dev@ziggurat29.com (2016-04-24).
+	* arch/arm/src/stm32l4: Add configuration options to allow SRAM2 to be
+	  used for heap, or not at all, and to zero-initialize it on OS start,
+	  or not at all. From Dave dev@ziggurat29.com (2016-04-24).
+	* drivers/mtd/smart.c:  Return code of smart_scan not checked, can
+	  cause success result in failure case, leading to 'dev' pointer being
+	  invalid. From Dave dev@ziggurat29.com (2016-04-27).
+	* arch/arm/src/stm32l4: Add support for QSPI memory mapped mode. From
+	  Dave dev@ziggurat29.com (2016-04-27).
+	* configs/stm32l476vg-disco: Add board ioctls for allowing user
+	  application to cause QSPI memory mapped mode to be engaged and
+	  disengaged.  Also partitioned QSPI flash for file system and other
+	 (eventually xip).  From Dave dev@ziggurat29.com (2016-04-27).
+	* fs/mount: Fix a backward debug assertion.  Noted by David Sidrane
+	  (2016-04-29).
+	* arch/arm/src/stm32l4: Add support for HSE and MSI clocks, and auto
+	  trim of MSI to LSE (needed for USB).  From Dave dev@ziggurat29.com
+	  (2016-04-29).
+	* arch/arm/src/stm32l4: Add support for unique id function to arch;
+	  modified board to support unique id boardctl.  From Dave
+	  dev@ziggurat29.com (2016-05-03).
+	* Makefile.unix and tools/mkexport.sh: Pass top-level make to the
+	  script to allow -j greater than 1.  From David Sidrane (2016-05-04).
+	* arch/arm/src/stm32, stm32f7, stm32l4: Fix typo in variable name in
+	  serial BREAK logic.  Review other serial implementations for similar
+	  naming problems. (2016-05-05).
+	* arch/arm/src/samv7:  Fix typo in MATRIX register definitions.  From
+	  Stefan Kolb (2016-05-06).
+	* arch/arm/src/stm32l4: Problem with resetting backup domain clears
+	  clocking options set up before in *rcc.c use INITS flag to avoid magic
+	  reg value to detect power up reset state of RTC correct a problem
+	  clearing interrupt flags (they weren't) which prevented an alarm from
+	  ever being used more than once per reset cycle.  From Dave
+	  dev@ziggurat29.com (2016-05-07).
+	* arch/arm/src/tiva: Fix a bug of GPIO falling-edge interrupt for tiva.
+	  From Young (2016-05-07).
+	* drivrs/mtd:  Add a driver for SST26F spi/qspi flash devices (SPI mode
+	  only).  From Sebastien Lorquet (2016-05-10).
+	* Several Makefiles: Add .PHONY definitions to prevent 'clean up to date'
+	  message weirdness when 'make clean' is done with no .config or Make.defs
+	  file (2016-05-10).
+	* include/nuttx/can.h and drivers/can.c:  Improve CAN error reporting.
+	  From Frank Benkert (2016-05-11).
+	* fs/Kconfig:  Allow CONFIG_FS_WRITABLE to be manually selectable
+	  (2016-05-11).
+	* Various file:  Search for places where a stray semicolon following an
+	  if condition cause the if body to be executed unconditionally.  Fixes
+	  in all SAM DMA logic, unionfs, OS signalling logic,
+	* configs/nucleo-144: Basic port for the Nucleo-144 board with the
+	  STM32F746ZG MCU.  From Kconstantin Berezenko (2015-05-12).
+	* arch/arm-src/armv7-a:  Complete re-design of logic to initialize each
+	  CPUn, n > 0, when CONFIG_SMP=y (2016-05-13).
+	* arch/arm/src/imx6 and configs/sabre-6quad:  The basic i.MX6 port is
+	  complete.  This is a very minimal port at present and probably still
+	  has some as-of-yet-undiscovered issues (2016-05-17).
+	* arch/*/Makefile: Add definitions that can be overrided to use GCC
+	  instead of LD in the final link.  From Paul Alexander Patience
+	  (2016-05-18) .
+	* arch/arm/src/stm32, stm32l4, and stm32f7 serial:  Add support for
+	  compliant BSD-style breaks. From David Sidrane (2016-05-18).
+	* enter/leave_critical_section() may attempt to access task lists before
+	  they have been initialized in the SMP configuration (2016-05-18).
+	* configs/stm32f103-minimum: Add support for this minimual STM32F103CBT6
+	  "blue" board.  From Alan Carvalho de Assis (2016-05-18).
+	* arch/arm/src/sam* Watchdogs:  Rename up_wdginitialize() to something
+	  more appropriate for an internal, MCU-specific function (2016-05-18).
+	* configs/*/src/*_watchdog.c:  Remove all implementations of
+	  up_wdginitialize() which was only used by apps/examples/watchdog.
+	  That internal OS function is no longer called from application code.
+	  If you want to use the watchdog example, you will need to configure
+	  the watchdog driver by calling the appropriate, MCU-specific driver
+	  configuration function from your board initialization logic
+	  (2016-05-18).
+	* arch/srm/src/stm32l4: Add CAN support for STM32L4.  From Sebastien
+	  Lorquet (2016-05-19).
+	* arch/arm/src/samv7: Adds a JTAG config and ERASE config to  Kconfig to
+	  set the CCFG_SYSIO SYSIO Pins.  From Davide Sidrane (2016-05-19).
+	* arch/sim/src:  Enhance networking support for the simulation under Linux.
+	  Includes updated support for Linux TUN/TAP, and the addition of support
+	  for Linux bridge devices.  From Steve (2016-05-20).
+	* configs/stm32f411e-disco:  Add basic configuration for stm32f411e-disco
+	  board with STM32F411VE chip.  From Konstantin Berezenko (2016-05-20).
+	* i.MX6 Sabre-6Quad: Basic SMP NSH configuration is now working.  But
+	  this is probably only because the SMP NSH case does not stress the
+	  logic.  There are know outstanding SMP issues as noted in the
+	  Sabre-6Quad README.txt file (2016-05-22).
+	* configs/sabre-6quad: Add an SMP configuration; Enable procfs in all
+	  configurations (2016-05-22).
+	* include/nuttx/crypto/aes.h:  Modifications to the crypto API needed
+	  for LPC43xx.  From Alexander Vasiljev (2016-05-23).
+	* arch/arm/src/lpc32xx:  Add AES support.  From Alexander Vasiljev
+	  (2016-05-24).
+	* configs/*/src/tiva_timer.c:  Tiva boards:  Fix a naming collision,
+	  rename board-specific function from tiva_timer_initialize() to
+	  tiva_timer_configure() to remove conflict (2016-05-23).
+	* arch/arm/src/sam*:  Ensure that the TWIHS (i2c) hw get's its clock
+	  set when the sequence of sam_i2cbus_initialize(),
+	  sam_i2cbus_uninitialize(), then sam_i2cbus_initialize() or twi_reset()
+	  is called.  I found this a while back in the stm32 family, so there
+	  may be more arch-es with this sort of bug. I suppose any driver that
+	  has the notion of "do not set the freq if it is already set" could be
+	  suspect.  From David Sidrane (2016-05-23).
+	* arch/arm/src/samv7: Add the up_systemreset interface to the samv7
+	  arch.  The approach is slightly different in that: 1) It enables
+	  ARCH_HAVE_RESET and allows the user to set if, and for how long, to
+	  drive External nRST signal. It also does not contain a default
+	  board_reset, as that really should be done in the config's src if
+	  CONFIG_BOARDCTL_RESET is defined.  From David Sidrane (2016-05-23).
+	* arch/arm/include/lpc43xx and src/lpc43xx: Adds definitions for the
+	  LPC4337jet100 chip.  From Alexander Vasiljev (2016-05-24).
+	* Many files:  board_app_initialize() now accepts an argument that may
+	  be used to support initialization in different configurations
+	  (2016-05-24).
+	* arch/arm/src/samv7: Remove disabling of whole USB on suspend of USBHS.
+	  This fix removes the disabling of the whole USB peripheral on suspend
+	  interrupt. Its enough to freeze the clock instead. When disabling the
+	  whole peripheral, the next wakeup-interrupt comes up with an disabled
+	  clocking. The unfreeze clock has no effect, because the master clock
+	  is disabled. This makes all registers, including the IDR unwriteable
+	  and the IRQ falls in an endless loop blocking the whole system.
+	  Furthermore the disabling of the peripheral clock prevents hotplugging
+	  or reconnecting the USB.  From  Frank Benkert  (2015-05-25).
+	* drivers/lcd: Add support for PCF8574 LCD Backpack driver. This driver
+	  supports an interface board that is based on the PCF8574 io expander
+	  and supports the HD44780-based (or compatible) LCD modules.  There
+	  are a myriad of different vendors of such, but they are principally
+	  the same, save wiring and minor features like jumpers for I2C
+	  addresses. This driver supports known and unknown variants.  From
+	  Dave (ziggurat29, 2013-6-26).
+	* arch/arm/stm32:  Add support for a custom 1-wire driver.  The serial
+	  driver already supports a 1-wire interface, but this driver uses the
+	  same serial logic to implement a lower half driver much like the I2C
+	  lower half driver.  From Aleksandr Vyhovanec (2015-05-25).
+	* fs/: Add logic to detach a file structure from a file descriptor.
+	  This is for use only within the OS.  It permits an open file or driver
+	  to be used across multiple threads (2016-05-26).
+	* arch/arm/src/stm32l4: Get I2C working for STM32L4.  From Dave
+	  (ziggurat29) (2016-05-25).
+	* fs/ and include/nuttx/fs: Add logic to detach a file structure from a
+	  file descriptor.  This is for use only within the OS.  It permits an
+	  open file or driver to be used across multiple threads.  (2016-05-26).
+	* drivers/analog/adc.c, include/nuttx/analog/adc.h, and all ADC lower
+	  half drivers:  No longer uses global adc_receive() call.  Added a new
+	  bind() method to the ADC interface.  Now the ADC upper half driver
+	  will register its receipt-of-data callback.  This change allows the
+	  ADC lower half driver to be used with a differ ADC upper half
+	  (2016-05-26).
+	* drivers/analog/ads1255.c: Must not do SPI access from interrupt
+	  handler.  Use the worker thread instead.  Must also lock the SPI bus
+	  before using it. (2015-05-26).
+	* drivers/:  Several SPI-based drivers modified.  All drivers that use
+	  SPI must call SPI_LOCK and SPI_UNLOCK.  This is not optional
+	  (2016-05-26).
+	* drivers/sensosrs:  Fix a bug in crc computation for ms583730.
+	  Implement POSIX read (2016-05-27).
+	* arch/arm/src/samv7: This is a fix to a problem in the handling of the
+	  oneshot timer. Due to a wrong assumption concerning the behavior
+	  directly after the start of the timer/counter the function
+	  sam_oneshot_cancel(…) calculates the wrong remaining time. The code
+	  assumes that the counter register is zero directly after the start of
+	  the timer, but this is not true. To start the time/counter a software
+	  trigger is invoked, this trigger starts the timer/count and sets the
+	  counter register to zero, but the reset of the counter register is not
+	  performed instantly. According to the datasheet: "The counter can be
+	  reset by a trigger. In this case, the counter value passes to zero on
+	  the next valid edge of the selected clock.” Thus the counter is set to
+	  zero between 0 and USEC_PER_TICK microseconds after the clock was
+	  started.
+	  In my fix I use the freerun count value to determine if at least one
+	  tick passed since the start of the timer and thus if the value of the
+	  oneshot counter is correct. I also tried to use the function
+	  up_timer_gettime(…) to achieve this but, at least if compiled with no
+	  optimization the problem vanishes without using the value of the
+	  function, the function call takes too long.
+	  Another problem treated in the fix is that if the oneshot timer/counter
+	  is canceled, we only know the remaining time with a precision of
+	  USEC_PER_TICK microseconds. This means the calculated remaining time
+	  is between 0 and USEC_PER_TICK microseconds  too long. To fix this I
+	  subtract one tick if the calculated remaining time is greater than one
+	  tick and otherwise set the remaining time to zero. By doing so the
+	  measured times are much more precise as without it.  From Stefan Kolb
+	  (2016-05-27).
+	* arch/arm/src/sama5:  Stefan Kolb's change to the SAMV7 Oneshot Timer
+	  should also be applied to the SAMA5 oneshot time since the drivers are
+	  identical (2016-05-27).
+	* arch/arm/src/stm32l4: Add support for SPI 4 and 5 on stm32f411 chips.
+	  From Konstantin Berezenko (2016-05-27).
+	* arch/arm/src/sam34:  Stefan Kolb's change to the SAMV7 Oneshot Timer
+	  should also be applied to the SAM3/4 oneshot time since the drivers
+	  are identical (2016-05-29).
+	* arch/arm/src/stm32: Allow to not use all channel in a lower part of
+	  PWM.  From Pierre-noel Bouteville (2016-05-30).

Documentation/NuttX.html

@@ -680,7 +680,10 @@
   <td><br></td>
   <td>
     <p>
-      <li>Graphics: framebuffer drivers, graphic- and segment-LCD drivers.</li>
+      <li>
+        Graphics: framebuffer drivers, graphic- and segment-LCD drivers.
+        VNC server.
+      </li>
     </p>
   </td>
 </tr>
@@ -831,7 +834,8 @@
   <td>
     <p>
       <li>Networking utilities (DHCP server and client, SMTP client, TELNET client, FTP server and client, TFTP client, HTTP server and client, PPPD, NTP client).
-      Inheritable TELNET sessions (as &quot;controlling terminal&quot;)</li>
+      Inheritable TELNET sessions (as &quot;controlling terminal&quot;).
+      VNC server.</li>
     </p>
   </td>
 </tr>

Documentation/NuttxPortingGuide.html

@@ -12,7 +12,7 @@
       <h1><big><font color="#3c34ec">
         <i>NuttX RTOS Porting Guide</i>
       </font></big></h1>
-      <p>Last Updated: March 28, 2016</p>
+      <p>Last Updated: May 12, 2016</p>
     </td>
   </tr>
 </table>
@@ -154,9 +154,8 @@
       <a href="#uptestset">4.7.1 <code>up_testset()</code></a><br>
       <a href="#upcpuindex">4.7.2 <code>up_cpu_index()</code></a><br>
       <a href="#upcpustart">4.7.3 <code>up_cpu_start()</code></a><br>
-      <a href="#upcpuinitialize">4.7.4 <code>up_cpu_initialize()</code></a><br>
-      <a href="#upcpupause">4.7.5 <code>up_cpu_pause()</code></a><br>
-      <a href="#upcpuresume">4.7.6 <code>up_cpu_resume()</code></a>
+      <a href="#upcpupause">4.7.4 <code>up_cpu_pause()</code></a><br>
+      <a href="#upcpuresume">4.7.5 <code>up_cpu_resume()</code></a>
     </ul>
     <a href="#exports">4.8 APIs Exported by NuttX to Architecture-Specific Logic</a>
     <ul>
@@ -3722,34 +3721,7 @@ int up_cpu_start(int cpu);
   </p>
 </ul>
 
-<h3><a name="upcpuinitialize">4.7.4 <code>up_cpu_initialize()</code></a></h3>
-<p><b>Function Prototype</b>:<p>
-<ul><pre>
-#include &lt;nuttx/arch.h&gt;
-#ifdef CONFIG_SMP
-int up_cpu_initialize(void);
-#endif
-</pre></ul>
-
-<p><b>Description</b>:</p>
-<ul>
-  <p>
-    After the CPU has been started (via <code>up_cpu_start()</code>) the system will call back into the architecture-specific code with this function on the thread of execution of the newly started CPU.
-    This gives the architecture-specific a chance to perform ny initial, CPU-specific initialize on that thread.
-  </p>
-</ul>
-<p><b>Input Parameters</b>:</p>
-<ul>
-  None
-</ul>
-<p><b>Returned Value</b>:</p>
-<ul>
-  <p>
-    Zero (<code>OK</code>) is returned on success; a negated <code>errno</code> value on failure.
-  </p>
-</ul>
-
-<h3><a name="upcpupause">4.7.5 <code>up_cpu_pause()</code></a></h3>
+<h3><a name="upcpupause">4.7.4 <code>up_cpu_pause()</code></a></h3>
 <p><b>Function Prototype</b>:<p>
 <ul><pre>
 #include &lt;nuttx/arch.h&gt;
@@ -3781,7 +3753,7 @@ int up_cpu_pause(int cpu);
   </p>
 </ul>
 
-<h3><a name="upcpuresume">4.7.6 <code>up_cpu_resume()</code></a></h3>
+<h3><a name="upcpuresume">4.7.5 <code>up_cpu_resume()</code></a></h3>
 <p><b>Function Prototype</b>:<p>
 <ul><pre>
 #include &lt;nuttx/arch.h&gt;
@@ -4929,8 +4901,7 @@ int kbd_decode(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *sta
     <p>
     <b><code>include/nuttx/net/netdev.h</code></b>.
     All structures and APIs needed to work with Ethernet drivers are provided in this header file.
-    The structure <code>struct net_driver_s</code> defines the interface and is passed to uIP via
-    <code>netdev_register()</code>.
+    The structure <code>struct net_driver_s</code> defines the interface and is passed to the network via <code>netdev_register()</code>.
     </p>
   </li>
   <li>

Documentation/NuttxUserGuide.html

@@ -8755,9 +8755,8 @@ FAR void *mmap(FAR void *start, size_t length, int prot, int flags, int fd, off_
 </table>
 
 <p>
-  NuttX includes a simple interface layer based on uIP (see <a href="http://www.sics.se/~adam/uip/index.php/Main_Page">http://www.sics.se</a>).
-  NuttX supports subset of a standard socket interface to uIP.
-  These network feature can be enabled by settings in the architecture <a href="NuttXConfigVariables.html">configuration file</a>.
+  NuttX supports a BSD-compatible socket interface layer.
+  These socket interface can be enabled by settings in the architecture <a href="NuttXConfigVariables.html">configuration file</a>.
   Those socket APIs are discussed in the following paragraphs.
 </p>
 <ul>

Documentation/README.html

@@ -8,7 +8,7 @@
   <tr align="center" bgcolor="#e4e4e4">
     <td>
       <h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
-      <p>Last Updated:  April 12, 2016</p>
+      <p>Last Updated:  May 26, 2016</p>
     </td>
   </tr>
 </table>
@@ -157,6 +157,8 @@ nuttx/
  |   |- ntosd-dm320/
  |   |   |- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/ntosd-dm320/doc/README.txt" target="_blank">doc/README.txt</a>
  |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/ntosd-dm320/README.txt" target="_blank"><b><i>README.txt</i></b></a>
+ |   |- nucleo-144/
+ |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/nucleo-144/README.txt" target="_blank"><b><i>README.txt</i></b></a>
  |   |- nucleo-f4x1re/
  |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/nucleo-f4x1re/README.txt" target="_blank"><b><i>README.txt</i></b></a>
  |   |- nutiny-nuc120/
@@ -249,10 +251,14 @@ nuttx/
  |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm3240g-eval/README.txt" target="_blank"><b><i>README.txt</i></b></a>
  |   |- stm32_tiny/
  |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32_tiny/README.txt" target="_blank"><b><i>README.txt</i></b></a>
+ |   |- stm32f103-minumum/
+ |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32f103-minumum/README.txt" target="_blank"><b><i>README.txt</i></b></a>
  |   |- stm32f3discovery/
  |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32f3discovery/README.txt" target="_blank"><b><i>README.txt</i></b></a>
  |   |- stm32f4discovery/
  |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32f4discovery/README.txt" target="_blank"><b><i>README.txt</i></b></a>
+ |   |- stm32f411e-disco/
+ |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32f411e-disco/README.txt" target="_blank"><b><i>README.txt</i></b></a>
  |   |- stm32f429i-disco/
  |   |   |- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32f429i-disco/ide/ltcd/uvision/README.txt" target="_blank"><b><i>ide/ltcd/uvision/README.txt</i></b></a>
  |   |   |- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32f429i-disco/ltdc/README.txt" target="_blank"><b><i>ltdc/README.txt</i></b></a>
@@ -310,7 +316,8 @@ nuttx/
  |   |- eeprom/
  |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/eeprom/README.txt" target="_blank"><b><i>README.txt</i></b></a>
  |   |- lcd/
- |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/lcd/README.txt" target="_blank"><b><i>README.txt</i></b></a>
+ |   |   |- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/lcd/README.txt" target="_blank"><b><i>README.txt</i></b></a>
+ |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/lcd/pcf8574_lcd_backpack_readme.txt" target="_blank"><b><i>pcf8574_lcd_backpack_readme.txt</i></b></a>
  |   |- mtd/
  |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/mtd/README.txt" target="_blank"><b><i>README.txt</i></b></a>
  |   |- sensors/

Kconfig

@@ -574,16 +574,6 @@ config DEBUG_INPUT
 		this debug option is board-specific and may not be available for
 		some boards.
 
-config DEBUG_DISCRETE
-	bool "Discrete I/O Debug Output"
-	default n
-	depends on DISCRETE_IO
-	---help---
-		Enable low level debug SYSLOG output from the discrete I/O device
-		drivers such as LEDs and I/O expanders (disabled by default).
-		Support for this debug option is board-specific and may not be
-		available for some boards.
-
 config DEBUG_ANALOG
 	bool "Analog Device Debug Output"
 	default n

Makefile.unix

@@ -507,7 +507,7 @@ gconfig: apps_preconfig
 # that the archiver is 'ar'
 
 export: pass2deps
-	$(Q) $(MKEXPORT) $(MKEXPORT_ARGS) -l "$(EXPORTLIBS)"
+	$(Q) MAKE=${MAKE} $(MKEXPORT) $(MKEXPORT_ARGS) -l "$(EXPORTLIBS)"
 
 # General housekeeping targets:  dependencies, cleaning, etc.
 #

README.txt

@@ -833,14 +833,29 @@ Re-building
   a file in one of the linked (i.e., copied) directories, re-build NuttX,
   and then not see your changes when you run the program.  That is because
   build is still using the version of the file in the copied directory, not
-  your modified file! To work around this annoying behavior, do the
-  following when you re-build:
+  your modified file!
+
+  Older versions of NuttX did not support dependiencies in this
+  configuration.  So a simple work around this annoying behavior in this
+  case was the following when you re-build:
 
      make clean_context all
 
   This 'make' command will remove of the copied directories, re-copy them,
   then make NuttX.
 
+  However, more recent versions of NuttX do support dependencies for the
+  Cygwin build.  As a result, the above command will cause everything to be
+  rebuilt (beause it removes and will cause recreating the
+  include/nuttx/config.h header file).  A much less gracefully but still
+  effective command in this case is the following for the ARM configuration:
+
+    rm -rf arch/arm/src/chip arch/arm/src/board
+
+  This "kludge" simple removes the copied directories.  These directories
+  will be re-created when you do a normal 'make' and your edits will then be
+  effective.
+
 Build Targets and Options
 -------------------------
 
@@ -1317,6 +1332,8 @@ nuttx/
  |   |- ntosd-dm320/
  |   |   |- doc/README.txt
  |   |   `- README.txt
+ |   |- nucleo-144/
+ |   |   `- README.txt
  |   |- nucleo-f4x1re/
  |   |   `- README.txt
  |   |- nutiny-nuc120/
@@ -1409,10 +1426,14 @@ nuttx/
  |   |   `- README.txt
  |   |- stm32_tiny/
  |   |   `- README.txt
+ |   |- stm32f103-minumum/
+ |   |   `- README.txt
  |   |- stm32f3discovery/
  |   |   `- README.txt
  |   |- stm32f4discovery/
  |   |   `- README.txt
+ |   |- stm32f411e-disco/
+ |   |   `- README.txt
  |   |- stm32f429i-disco/
  |   |   |- ide/ltcd/uvision/README.txt
  |   |   |- ltdc/README.txt
@@ -1470,7 +1491,8 @@ nuttx/
  |   |- eeprom/
  |   |   `- README.txt
  |   |- lcd/
- |   |   `- README.txt
+ |   |   | README.txt
+ |   |   `- pcf8574_lcd_backpack_readme.txt
  |   |- mtd/
  |   |   `- README.txt
  |   |- sensors/

TODO

@@ -1,20 +1,20 @@
-NuttX TODO List (Last updated March 31, 2016)
+NuttX TODO List (Last updated May 28, 2016)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 This file summarizes known NuttX bugs, limitations, inconsistencies with
 standards, things that could be improved, and ideas for enhancements.  This
 TODO list does not include issues associated with individual boar ports. See
-altheso individual README.txt files in the configs/ sub-directories for
-issues reated to each board port.
+also the individual README.txt files in the configs/ sub-directories for
+issues related to each board port.
 
-nuttx/
+nuttx/:
 
  (13)  Task/Scheduler (sched/)
   (1)  Memory Management (mm/)
   (3)  Signals (sched/signal, arch/)
   (2)  pthreads (sched/pthread)
   (0)  Message Queues (sched/mqueue)
-  (8)  Kernel/Protected Build
+  (9)  Kernel/Protected Build
   (3)  C++ Support
   (6)  Binary loaders (binfmt/)
  (12)  Network (net/, drivers/net)
@@ -23,16 +23,16 @@ nuttx/
  (11)  Libraries (libc/, libm/)
  (11)  File system/Generic drivers (fs/, drivers/)
   (8)  Graphics subsystem (graphics/)
-  (1)  Pascal add-on (pcode/)
   (1)  Build system / Toolchains
-  (4)  Linux/Cywgin simulation (arch/sim)
+  (3)  Linux/Cywgin simulation (arch/sim)
   (4)  ARM (arch/arm/)
 
-apps/
+apps/ and other Add-Ons:
 
   (3)  Network Utilities (apps/netutils/)
   (2)  NuttShell (NSH) (apps/nshlib)
   (1)  System libraries apps/system (apps/system)
+  (1)  Pascal add-on (pcode/)
   (4)  Other Applications & Tests (apps/examples/)
 
 o Task/Scheduler (sched/)
@@ -70,7 +70,7 @@ o Task/Scheduler (sched/)
   Title:       GET_ENVIRON_PTR()
   Description: get_environ_ptr() (sched/sched_getenvironptr.c) is not implemented.
                The representation of the environment strings selected for
-               NutX is not compatible with the operation.  Some significant
+               NuttX is not compatible with the operation.  Some significant
                re-design would be required to implement this function and that
                effort is thought to be not worth the result.
   Status:      Open.  No change is planned.
@@ -81,7 +81,7 @@ o Task/Scheduler (sched/)
   Status:      Open
   Priority:    Low -- There is no plan to implement this.
 
-  Title:       INCOMPATIBILITES WITH execv() AND execl()
+  Title:       INCOMPATIBILITIES WITH execv() AND execl()
   Description: Simplified 'execl()' and 'execv()' functions are provided by
                NuttX.  NuttX does not support processes and hence the concept
                of overlaying a tasks process image with a new process image
@@ -175,7 +175,7 @@ o Task/Scheduler (sched/)
                Yahoo! Groups message 7726: "I think that the system
                 should be required to handle pthread_cancel safely in
                 all cases.  In the NuttX model, a task is like a Unix
-                process and a pthread is like a Unix thread.  Cancelling
+                process and a pthread is like a Unix thread.  Canceling
                 threads should always be safe (or at least as unsafe) as
                 under Unix because the model is complete for pthreads...
 
@@ -188,7 +188,7 @@ o Task/Scheduler (sched/)
 
                "The patch I just incorporated is also insufficient.  It
                 works only if the serial driver is shut down when the
-                thread is cancelled.  But what if there are other open
+                thread is canceled.  But what if there are other open
                 references to the driver?  Then the driver will not be
                 shut down, the semaphores will not be re-initialized, and
                 the semaphore counts will still be off by one.
@@ -202,7 +202,7 @@ o Task/Scheduler (sched/)
                hooks so that given a semaphore it can traverse all
                holders.  What is needed would be logic so that given
                a task, you can traverse all semaphores held by the task,
-               releasing each semaphore cound held by the exiting task.
+               releasing each semaphore count held by the exiting task.
                Nothing like this exists now so that solution is not
                imminent.
 
@@ -228,16 +228,15 @@ o Task/Scheduler (sched/)
                hidden behind simple accessor functions and so the internal
                data structures can be changed if need with very little impact.
 
-
-               Explicity refereence to the list strucutre are hidden behnid
+               Explicitly reference to the list structure are hidden behind
                the macro this_task().
 
   Status:      Open
   Priority:    Low.  Things are just the way that we want them for the way
                that NuttX is used today.
 
-o Memory Managment (mm/)
-  ^^^^^^^^^^^^^^^^^^^^^^
+o Memory Management (mm/)
+  ^^^^^^^^^^^^^^^^^^^^^^^
 
   Title:       FREE MEMORY ON TASK EXIT
   Description: Add an option to free all memory allocated by a task when the
@@ -390,7 +389,7 @@ o pthreads (sched/pthreads)
   Priority:    Low -- about zero, probably not that useful. Priority inheritance is
                already supported and is a much better solution.  And it turns out
                that priority protection is just about as complex as priority inheritance.
-               Exerpted from my post in a Linked-In discussion:
+               Excerpted from my post in a Linked-In discussion:
 
                "I started to implement this HLS/"PCP" semaphore in an RTOS that I
                work with (http://www.nuttx.org) and I discovered after doing the
@@ -589,8 +588,27 @@ o Kernel/Protected Build
                interrupt level callbacks into applications.  This, of course,
                will never work in anything but a non-secure, flat build.
   Status:      Open
-  Priority:    Medium.  The driver is only usable with all of its features in a FLAT build.
-  
+  Priority:    Medium.  The driver is only usable with all of its features
+               in a FLAT build.
+
+  Title:       USER MODE TASKS CAN MODIFY PRIVILEGED TASKS
+  Description: Certain interfaces, such as sched_setparam(),
+               sched_setscheduler(), etc. can be used by user mode tasks to
+               modify the behavior of priviledged kernel threads.
+               task_delete() could even be used to kill a kernel thread.
+               For a truly secure system.  Privileges need to be checked in
+               every interface that permits one thread to modify the
+               properties of another thread.
+
+               NOTE:  It would be a simple matter to simply disable user
+               threads from modifying privileged threads.  However, you
+               might also want to be able to modify privileged threads from
+               user tasks with certain permissions.  Permissions is a much
+               more complex issue.
+  Status:      Open
+  Priority:    Low for most embedded systems but would be a critical need if
+               NuttX were used in a secure system.
+
 o C++ Support
   ^^^^^^^^^^^
 
@@ -784,7 +802,7 @@ o Binary loaders (binfmt/)
                to get fixed as needed for Windows native tool builds.
 
   Title:       TOOLCHAIN COMPATIBILITY PROBLEM
-  Descripton:  The older 4.3.3 compiler generates GOTOFF relocations to the constant
+  Description: The older 4.3.3 compiler generates GOTOFF relocations to the constant
                strings, like:
 
                .L3:
@@ -794,7 +812,7 @@ o Binary loaders (binfmt/)
                   .word   .LC3(GOTOFF)
                   .word   .LC4(GOTOFF)
 
-               Where .LC0, LC1, LC2, LC3, and .LC4 are the labels correponding to strings in
+               Where .LC0, LC1, LC2, LC3, and .LC4 are the labels corresponding to strings in
                the .rodata.str1.1 section.  One consequence of this is that .rodata must reside
                in D-Space since it will addressed relative to the GOT (see the section entitled
                "Read-Only Data in RAM" at
@@ -880,7 +898,7 @@ o Network (net/, drivers/net)
                RFC3678 (IGMPv3) suggests ioctl() commands to do this (SIOCSIPMSFILTER) but
                also status that those APIs are historic.  NuttX implements these ioctl
                commands, but is non-standard because:  (1) It does not support IGMPv3, and
-               (2) it looks up drivers by their device name (eg., "eth0") vs IP address.
+               (2) it looks up drivers by their device name (e.g., "eth0") vs IP address.
 
                Linux uses setsockopt() to control multicast group membership using the
                IP_ADD_MEMBERSHIP and IP_DROP_MEMBERSHIP options.  It also looks up drivers
@@ -896,7 +914,7 @@ o Network (net/, drivers/net)
                that connection may time out.  How should this be handled?  Should the
                connection be removed from the backlog if it is times out or is closed?
                Or should it remain in the backlog with a status indication so that accept()
-               can fail when it encounteres the invalid connection?
+               can fail when it encounters the invalid connection?
   Status:      Open
   Priority:    Medium.  Important on slow applications that will not accept
                connections promptly.
@@ -975,7 +993,7 @@ o Network (net/, drivers/net)
                it is no longer needed.  Perhaps there should be a delayed
                call to unlink() (using a watchdog or the work queue).  If
                the driver is re-opened, the delayed unlink could be
-               cancelled?  Needs more thought.
+               canceled?  Needs more thought.
                NOTE: This is not an issue for Unix domain streams sockets:
                The end-of-life of the FIFO is well determined when sockets
                are disconnected and support for that case is fully implemented.
@@ -1020,7 +1038,7 @@ o USB (drivers/usbdev, drivers/usbhost)
                that involves delays.  This needs to be redesigned to eliminate these
                delays.  See logic conditioned on CONFIG_USBMSC_RACEWAR.
 
-               If queuing of stall requests is supported by DCD then this workaround
+               If queuing of stall requests is supported by the DCD then this workaround
                is not required.  In this case, (1) the stall is not sent until all
                write requests preceding the stall request are sent, (2) the stall is
                sent, and then after the stall is cleared, (3) all write requests
@@ -1135,7 +1153,7 @@ o USB (drivers/usbdev, drivers/usbhost)
   Priority:    Medium-Low
 
   Title:       USB CDC/ACM HOST CLASS DRIVER
-  Desciption:  A CDC/ACM host class driver has been added.  This has been
+  Description: A CDC/ACM host class driver has been added.  This has been
                testing by running the USB CDC/ACM host on an Olimex
                LPC1766STK and using the configs/stm3210e-eval/usbserial
                configuration (using the CDC/ACM device side driver).  There
@@ -1374,7 +1392,7 @@ o File system / Generic drivers (fs/, drivers/)
   Priority:    Medium
 
   Title:       UNIFIED DESCRIPTOR REPRESENTATION
-  Descripton:  There are two separate ranges of descriptors for file and
+  Description: There are two separate ranges of descriptors for file and
                socket descriptors: if a descriptor is in one range then it is
                recognized as a file descriptor; if it is in another range
                then it is recognized as a socket descriptor.  These separate
@@ -1410,7 +1428,7 @@ o File system / Generic drivers (fs/, drivers/)
   Status:      Open
   Priority:    Low
 
-  Title:       FAT LONG FILENAME COMPATIBILTY
+  Title:       FAT LONG FILENAME COMPATIBILITY
   Description: Recently there have been reports that file with long file
                names created by NuttX don't have long file names when viewed
                on Windows.  The long file name support has been around for a
@@ -1423,7 +1441,7 @@ o File system / Generic drivers (fs/, drivers/)
   Description: I have seen cases where (1) long file names are enabled,
                but (2) a short file name is created like:
 
-                 nsh> echo "This is another thest" >/mnt/sdcard/another.txt
+                 nsh> echo "This is another test" >/mnt/sdcard/another.txt
 
                But then on subsequent 'ls' operations, the file does not appear:
 
@@ -1472,7 +1490,7 @@ o File system / Generic drivers (fs/, drivers/)
 
                4) When comparing the checksum in the long file name
                   entry with the checksum of the short file name, the
-                  checksum fails and the entire directlry sequence is
+                  checksum fails and the entire directory sequence is
                   ignored by readder() logic.  This the file does not
                   appear in the 'ls'.
 
@@ -1539,7 +1557,7 @@ o Graphics subsystem (graphics/)
   Priority:    Low, the need has not yet arisen.
 
   Title:       PER-WINDOW FRAMEBUFFERS
-  Description: One of the most awkard things to handle in the NX windowing
+  Description: One of the most awkward things to handle in the NX windowing
                system is the re-draw callback.  This is difficult because it
                requires ad hoc, custom logic to be able to do the redrawing
                in most cases.
@@ -1567,26 +1585,6 @@ o Graphics subsystem (graphics/)
   Priority:    Low, not a serious issue but worth noting.  There is no plan
                to change this behavior.
 
-o Pascal Add-On (pcode/)
-  ^^^^^^^^^^^^^^^^^^^^^^
-
-  Title:       P-CODES IN MEMORY UNTESTED
-  Description: Need APIs to verify execution of P-Code from memory buffer.
-  Status:      Open
-  Priority:    Low
-
-  Title:       SMALLER LOADER AND OBJECT FORMAT
-  Description: Loader and object format may be too large for some small
-               memory systems.  Consider ways to reduce memory footprint.
-  Status:      Open
-  Priority:    Medium
-
-  Title:       PDBG
-  Description: Move the the pascal p-code debugger into the NuttX apps/ tree
-               where it can be used from the NSH command line.
-  Status:      Open
-  Priority:    Low
-
 o Build system
   ^^^^^^^^^^^^
 
@@ -1609,15 +1607,6 @@ o Other drivers (drivers/)
 o Linux/Cywgin simulation (arch/sim)
   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-  Title:       SIMULATOR NETWORKING SUPPORT
-  Description: I never did get networking to work on the sim Linux target.  On Linux,
-               it tries to use the tap device (/dev/net/tun) to emulate an Ethernet
-               NIC, but I never got it correctly integrated with the NuttX networking.
-               NOTE: On Cygwin, the build uses the Cygwin WPCAP library and is, at
-               least, partially functional (it has never been rigorously tested).
-  Status:      Open
-  Priority:    Low (unless you want to test networking features on the simulation).
-
   Title:       SIMULATOR HAS NO INTERRUPTS (NON-PREMPTIBLE)
   Description: The current simulator implementation is has no interrupts and, hence,
                is non-preemptible.  Also, without simulated interrupt, there can
@@ -1765,7 +1754,7 @@ o ARM (arch/arm/)
 
                But this has not been proven to be a solution.
 
-               UPDATE:  Other ARM architectures have a similer issue.
+               UPDATE:  Other ARM architectures have a similar issue.
 
   Status:      Open
   Priority:    Low.  The conditions of continuous interrupts is really the problem.
@@ -1823,7 +1812,7 @@ o NuttShell (NSH) (apps/nshlib)
   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
   Title:       IFCONFIG AND MULTIPLE NETWORK INTERFACES
-  Descripton:  The ifconfig command will not behave correctly if an interface
+  Description: The ifconfig command will not behave correctly if an interface
                is provided and there are multiple interfaces.  It should only
                show status for the single interface on the command line; it will
                still show status for all interfaces.
@@ -1848,6 +1837,26 @@ o System libraries apps/system (apps/system)
   Priority:    Low (unless you are using mixed C-buffered I/O with readline and
                fgetc, for example).
 
+o Pascal Add-On (pcode/)
+  ^^^^^^^^^^^^^^^^^^^^^^
+
+  Title:       P-CODES IN MEMORY UNTESTED
+  Description: Need APIs to verify execution of P-Code from memory buffer.
+  Status:      Open
+  Priority:    Low
+
+  Title:       SMALLER LOADER AND OBJECT FORMAT
+  Description: Loader and object format may be too large for some small
+               memory systems.  Consider ways to reduce memory footprint.
+  Status:      Open
+  Priority:    Medium
+
+  Title:       PDBG
+  Description: Move the the pascal p-code debugger into the NuttX apps/ tree
+               where it can be used from the NSH command line.
+  Status:      Open
+  Priority:    Low
+
 o Other Applications & Tests (apps/examples/)
   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 

arch/README.txt

@@ -134,6 +134,8 @@ src/Makefile
 
 Supported Architectures
 ^^^^^^^^^^^^^^^^^^^^^^^
+NOTE: nuttx/Documentation/NuttX.html for current information about the
+state of these MCU ports.
 
 arch/sim - Linux/Cygwin simulation
     A user-mode port of NuttX to the x86 Linux platform is available.
@@ -145,135 +147,68 @@ arch/arm - ARM-based micro-controllers
     This directory holds common ARM architectures.  At present, this includes
     the following subdirectories:
 
-    arch/arm/include and arch/arm/src/common
-        Common ARM/Cortex-M3 logic.
+    Architecture Support
+      arch/arm/include and arch/arm/src/common
+      arch/arm/src/arm and arch/arm/include/arm
+      arch/arm/src/armv7-a and arch/arm/include/armv7-a
+      arch/arm/src/armv7-m and arch/arm/include/armv7-m
+      arch/arm/src/armv7-r and arch/arm/include/armv7-4
 
-    arch/arm/src/arm and arch/arm/include/arm
-        Common ARM-specific logic
-
-    arch/arm/src/armv7-m and arch/arm/include/armv7-m
-        Common ARMv7-M logic (Cortex-M3 and Cortex-M4)
-
-    arch/arm/include/c5471 and arch/arm/src/c5471
-        TI TMS320C5471 (also called TMS320DM180 or just C5471).
-        NuttX operates on the ARM7 of this dual core processor. This port
-        complete, verified, and included in the NuttX release 0.1.1.
-
-    arch/arm/include/calypso and arch/arm/src/calypso
-        TI "Calypso" MCU used in various cell phones (and, in particular,
-        by the Osmocom-bb project).  Like the c5471, NuttX operates on the
-        ARM7 of this dual core processor. This port was contributed by
-        Denis Carilki and includes the work of Denis, Alan Carvalho de Assis,
-        and Stefan Richter.  Calypso support first appeared in NuttX-6.17.
-
-    arch/arm/include/dm320 and arch/arm/src/dm320
-        TI TMS320DM320 (also called just DM320).
-        NuttX operates on the ARM9EJS of this dual core processor.  This port
-        complete, verified, and included in the NuttX release 0.2.1.
-
-    arch/arm/include/imx and arch/arm/src/imx
-        Freescale MC9328MX1 or i.MX1. This port uses the Freescale MX1ADS
-        development board with a GNU arm-elf toolchain* under either Linux or Cygwin.
-        STATUS: This port has stalled because of development tool issues. Coding
-        is complete on the basic port (timer, serial console, SPI).
-
-    arch/arm/include/lm and arch/arm/src/lm
-        These directories contain support for the Luminary LM3S/4F family. The
-        initial, release of this port was included in NuttX version 0.4.6.  The
-        current port includes timer, serial console, Ethernet, SSI, and microSD
-        support. There are working configurations the NuttX OS test, to run the
-        NuttShell (NSH), the NuttX networking test, and the uIP web server.
-
-    arch/arm/include/lpc214x and arch/arm/src/lpc214x
-        These directories provide support for NXP LPC214x family of
-        ARM7TDMI processors.  This port boots and passes the OS test (examples/ostest).
-        The port is complete and verifed.  As of NuttX 0.3.17, the port includes:
-        timer interrupts, serial console, USB driver, and SPI-based MMC/SD card
-        support.  A verifed NuttShell (NSH) configuration is also available.
-
-    arch/arm/include/lpc2378 and arch/arm/src/lpc2378.
-        NXP LPC2378. Support is provided for the NXP LPC2378 MCU. This port was
-        contributed by Rommel Marcelo is was first released in NuttX-5.3.
-        STATUS: This port boots and passes the OS test (examples/ostest) and
-        includes a working implementation of the NuttShell (NSH). The port is
-        complete and verified. As of NuttX 5.3, the port includes only basic
-        timer interrupts and serial console support.
-
-    arch/arm/include/lpc31xx and arch/arm/src/lpc31xx
-        These directories provide support for NXP LPC31xx family of
-        ARM926EJ-S processors.  The port for the NXP LPC3131 was first
-        released in NuttX-5.1 (but was not functional until NuttX-5.2).
-        STATUS: The basic EA3131 port is complete and verified in NuttX-5.2
-        This basic port includes basic boot-up, serial console, and timer
-        interrupts. This port was extended in NuttX 5.3 with a USB high
-        speed driver contributed by David Hewson. This port has been
-        verified using the NuttX OS test, USB serial and mass storage tests
-        and includes a working implementation of the NuttShell ((NSH)).
-
-        This port was later extended to support additional members of the
-        LPC31xx family including, specifically, the LPC3152.
-
-    arch/arm/include/sam3u and arch/arm/src/sam3u
-        Atmel AT91SAM3U. This port is for Atmel AT91SAM3U4E MCU.
-        STATUS: The basic AT91SAM3U port was released in NuttX version 5.1.
-        The basic port includes boot-up logic, interrupt driven serial
-        console, and system timer interrupts. That release passes the
-        NuttX OS test and is proven to have a valid OS implementation. A
-        onfiguration to support the NuttShell is also included.
-
-    arch/arm/include/stm32 and arch/arm/src/stm32
-        These directories contain support for the STMicro STM32 F1, F2, and
-        F4 families.
-
-        STATUS: The basic STM32 F1 port was released in NuttX version 0.4.12.
-        and has continued to develop consistently over time.  It now includes
-        support for the F2 and F4 families and a rich offering of peripheral
-        drivers.
-
-    arch/arm/include/str71x and arch/arm/src/str71x
-        These directories provide support for the STMicro STR71x processors.
-        Coding is complete on the basic port (boot logic, system time, serial console),
-        but no testing has been performed due to some problems I am having with my
-        JTAG wiggler and OpenOCD on Linux.
+    MCU support
+      arch/arm/include/c5471 and arch/arm/src/c5471
+      arch/arm/include/calypso and arch/arm/src/calypso
+      arch/arm/include/dm320 and arch/arm/src/dm320
+      arch/arm/include/efm32 and arch/arm/src/efm32
+      arch/arm/include/imx1 and arch/arm/src/imx1
+      arch/arm/include/imx6 and arch/arm/src/imx6
+      arch/arm/include/kinetis and arch/arm/src/kinetis
+      arch/arm/include/kl and arch/arm/src/kl
+      arch/arm/include/lpc11xx and arch/arm/src/lpc11xx
+      arch/arm/include/lpc17xx and arch/arm/src/lpc17xx
+      arch/arm/include/lpc214x and arch/arm/src/lpc214x
+      arch/arm/include/lpc2378 and arch/arm/src/lpc2378.
+      arch/arm/include/lpc31xx and arch/arm/src/lpc31xx
+      arch/arm/include/lpc43xx and arch/arm/src/lpc43xx
+      arch/arm/include/moxart and arch/arm/src/moxart
+      arch/arm/include/nuc1xx and arch/arm/src/nuc1xx
+      arch/arm/include/sam34 and arch/arm/src/sam34
+      arch/arm/include/sama45 and arch/arm/src/sama5
+      arch/arm/include/samdl and arch/arm/src/samdl
+      arch/arm/include/samv7 and arch/arm/src/samv7
+      arch/arm/include/stm32 and arch/arm/src/stm32
+      arch/arm/include/stm32f7 and arch/arm/src/stm32f7
+      arch/arm/include/stm32l4 and arch/arm/src/stm32l4
+      arch/arm/include/str71x and arch/arm/src/str71x
+      arch/arm/include/tiva and arch/arm/src/tiva
+      arch/arm/include/tms570 and arch/arm/src/tms570
 
 arch/avr
     This directory is dedicated to ports to the Atmel AVR (8-bit) and AVR32 (32-bit)
     MCU families.  STATUS:  Under development.
 
-    arch/avr/include/avr and arch/avr/src/avr
-      Common support for all 8-bit AVR MCUs
+    Architecture Support
+      arch/avr/include/avr and arch/avr/src/avr
+      arch/avr/include/avr32 and arch/avr/src/avr32
 
-    arch/avr/include/atmega and arch/avr/src/atmega
-      Support specifically for the AVR ATMega family (specifically only for
-      the ATMega128 at the moment).
-
-    arch/avr/include/at90usb and arch/avr/src/at90usb
-      Support specifically for the AVR AT90USB646, 647, 1286, and 1287 family.
-
-    arch/avr/include/avr32 and arch/avr/src/avr32
-      Common support for all AVR32 MCUs
-
-    arch/avr/include/at32uc3 and arch/avr/src/at32uc3
-      Support specifically for the AT32UC3Bxxx family (specifically only for
-      the AT32UC3B0256 at the moment).
+    MCU support
+      arch/avr/include/atmega and arch/avr/src/atmega
+      arch/avr/include/at90usb and arch/avr/src/at90usb
+      arch/avr/include/at32uc3 and arch/avr/src/at32uc3
 
 arch/hc
     This directory is dedicated to ports to the Freescale HC family.
 
     arch/arm/include/m9s12 and arch/arm/src/m9s12
-      These directories provide support for the Freescale mc9s12x family.
-      STATUS:  Fragments of this port were first released in nuttx-5.0 and
-      the port was "code-complete" as nuttx-5.18.  However, the final
-      verification effort has been stalled because of higher priority tasks.
 
 arch/mips
     This directory is dedicated to ports to the MIPS family.
 
-    arch/mips/include/mips32 and arch/mips/src/mips32
-      Common support for all MIPS32 architectures
+    Architecture Support
+      arch/mips/include/mips32 and arch/mips/src/mips32
 
-    arch/mips/include/pic32mx and arch/mips/src/pic32mx
-      Support for all MicroChip PIC32MX architectures
+    MCU support
+      arch/mips/include/pic32mx and arch/mips/src/pic32mx
+      arch/mips/include/pic32mz and arch/mips/src/pic32mz
 
 arch/rgmp
 
@@ -288,52 +223,42 @@ arch/rgmp
 
 arch/sh - SuperH and related Hitachi/Renesas microcontrollers
 
-    arch/sh/include and arch/sh/src/common
-        Common SuperH logic.
+    Architecture Support
+      arch/sh/include and arch/sh/src/common
 
-    arch/sh/include/shs and arch/sh/src/sh1
-        Support for the SH-1 processor.
+    MCU support
+      arch/sh/include/m16c and arch/sh/src/m16c
+      arch/sh/include/sh1 and arch/sh/src/sh1
 
 arch/x86 - Intel x86 architectures
     This directory holds related, 32- and 64-bit architectures from Intel.
     At present, this includes the following subdirectories:
 
-    arch/x86/include and arch/x86/src/common
-        Common x86 logic.
+    Architecture Support
+      arch/x86/include and arch/x86/src/common
 
-    arch/x86/include/i486 and arch/x86/src/i486
-        These directories hold definitions and logic appropriate for any
-        instantiation of the 32-bit i486 architecture.
-
-    arch/x86/include/qemu and arch/x86/src/qemu
-        This is the implementation of NuttX on the QEMU x86 simulation.
+    MCU support
+      arch/x86/include/i486 and arch/x86/src/i486
+      arch/x86/include/qemu and arch/x86/src/qemu
 
 arch/z16 - ZiLOG 16-bit processors
     This directory holds related, 16-bit architectures from ZiLOG.  At
     present, this includes the following subdirectories:
 
-    arch/z16/include and arch/z16/src/common
-        Common microcontroller logic.
+    Architecture Support
+      arch/z16/include and arch/z16/src/common
 
-    arch/z16/include/z16f and arch/z16/src/z16f
-        ZiLOG z16f Microcontroller.
-        STATUS: Released in nuttx-0.3.7.  Fully functional other than issues
-        addressed in ${TOPDIR}/TODO.
+    MCU support
+      arch/z16/include/z16f and arch/z16/src/z16f
 
 arch/z80 - ZiLOG 8-bit microcontrollers
     This directory holds related, 8-bit architectures from ZiLOG.  At
     present, this includes the following subdirectories:
 
-    arch/z80/include and arch/z80/src/common
-        Common microcontroller logic.
+    Architecture Support
+      arch/z80/include and arch/z80/src/common
 
-    arch/z80/include/z80 and arch/z80/src/z80
-        Classic ZiLOG z80 Microcontroller.
-        STATUS: Functional with no known defects.  There are still several
-         OS features that have not yet been tested (e.g., networking).
-
-    arch/z80/include/z8 and arch/z80/src/z8
-        ZiLOG Z8Encore! Microcontroller
-
-    arch/z80/include/ez80 and arch/z80/src/ez80
-        ZiLOG ez80 Acclaim! Microcontroller
+    MCU support
+      arch/z80/include/z80 and arch/z80/src/z80
+      arch/z80/include/z8 and arch/z80/src/z8
+      arch/z80/include/ez80 and arch/z80/src/ez80

arch/arm/Kconfig

@@ -27,7 +27,7 @@ config ARCH_CHIP_C5471
 	bool "TMS320 C5471"
 	select ARCH_ARM7TDMI
 	select ARCH_HAVE_LOWVECTORS
-	select ARCH_HAVE_OTHER_UART
+	select OTHER_UART_SERIALDRIVER
 	---help---
 		TI TMS320 C5471, A180, or DA180 (ARM7TDMI)
 
@@ -36,7 +36,7 @@ config ARCH_CHIP_CALYPSO
 	select ARCH_ARM7TDMI
 	select ARCH_HAVE_HEAP2
 	select ARCH_HAVE_LOWVECTORS
-	select ARCH_HAVE_OTHER_UART
+	select OTHER_UART_SERIALDRIVER
 	select ARCH_HAVE_POWEROFF
 	---help---
 		TI Calypso-based cell phones (ARM7TDMI)

arch/arm/include/lpc43xx/chip.h

@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/include/lpc43xx/chip.h
  *
- *   Copyright (C) 2012-2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2012-2013, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -167,7 +167,7 @@
 #  warning "Data sheet and user manual are consistement for the LPC4320"
 #  define LPC43_FLASH_BANKA_SIZE   (0)         /* Flashless */
 #  define LPC43_FLASH_BANKB_SIZE   (0)
-#  define LPC43_LOCSRAM_BANK0_SIZE (128*1024)  /* 168Kb Local SRAM*/
+#  define LPC43_LOCSRAM_BANK0_SIZE (128*1024)  /* 168Kb Local SRAM */
 #  define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
 #  define LPC43_AHBSRAM_BANK0_SIZE (16*1024)   /* 32Kb AHB SRAM */
 #  define LPC43_AHBSRAM_BANK1_SIZE (0)
@@ -194,7 +194,7 @@
 #  warning "Data sheet and user manual are consistement for the LPC4320"
 #  define LPC43_FLASH_BANKA_SIZE   (0)         /* Flashless */
 #  define LPC43_FLASH_BANKB_SIZE   (0)
-#  define LPC43_LOCSRAM_BANK0_SIZE (128*1024)  /* 168Kb Local SRAM*/
+#  define LPC43_LOCSRAM_BANK0_SIZE (128*1024)  /* 168Kb Local SRAM */
 #  define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
 #  define LPC43_AHBSRAM_BANK0_SIZE (16*1024)   /* 32Kb AHB SRAM */
 #  define LPC43_AHBSRAM_BANK1_SIZE (0)
@@ -220,7 +220,7 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC4330FBD144)
 #  define LPC43_FLASH_BANKA_SIZE   (0)         /* Flashless */
 #  define LPC43_FLASH_BANKB_SIZE   (0)
-#  define LPC43_LOCSRAM_BANK0_SIZE (128*1024)  /* 200Kb Local SRAM*/
+#  define LPC43_LOCSRAM_BANK0_SIZE (128*1024)  /* 200Kb Local SRAM */
 #  define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
 #  define LPC43_AHBSRAM_BANK0_SIZE (48*1024)   /* 64Kb AHB SRAM */
 #  define LPC43_AHBSRAM_BANK1_SIZE (0)
@@ -246,7 +246,7 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC4330FET100)
 #  define LPC43_FLASH_BANKA_SIZE   (0)         /* Flashless */
 #  define LPC43_FLASH_BANKB_SIZE   (0)
-#  define LPC43_LOCSRAM_BANK0_SIZE (128*1024)  /* 200Kb Local SRAM*/
+#  define LPC43_LOCSRAM_BANK0_SIZE (128*1024)  /* 200Kb Local SRAM */
 #  define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
 #  define LPC43_AHBSRAM_BANK0_SIZE (48*1024)   /* 64Kb AHB SRAM */
 #  define LPC43_AHBSRAM_BANK1_SIZE (0)
@@ -272,7 +272,7 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC4330FET180)
 #  define LPC43_FLASH_BANKA_SIZE   (0)         /* Flashless */
 #  define LPC43_FLASH_BANKB_SIZE   (0)
-#  define LPC43_LOCSRAM_BANK0_SIZE (128*1024)  /* 200Kb Local SRAM*/
+#  define LPC43_LOCSRAM_BANK0_SIZE (128*1024)  /* 200Kb Local SRAM */
 #  define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
 #  define LPC43_AHBSRAM_BANK0_SIZE (48*1024)   /* 64Kb AHB SRAM */
 #  define LPC43_AHBSRAM_BANK1_SIZE (0)
@@ -298,7 +298,7 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC4330FET256)
 #  define LPC43_FLASH_BANKA_SIZE   (0)         /* Flashless */
 #  define LPC43_FLASH_BANKB_SIZE   (0)
-#  define LPC43_LOCSRAM_BANK0_SIZE (128*1024)  /* 200Kb Local SRAM*/
+#  define LPC43_LOCSRAM_BANK0_SIZE (128*1024)  /* 200Kb Local SRAM */
 #  define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
 #  define LPC43_AHBSRAM_BANK0_SIZE (48*1024)   /* 64Kb AHB SRAM */
 #  define LPC43_AHBSRAM_BANK1_SIZE (0)
@@ -322,9 +322,9 @@
 #  define LPC43_NADC10_CHANNELS    (8)         /* Eight ADC channels */
 #  undef  LPC43_NADC12                         /* No 12-bit ADC controllers */
 #elif defined(CONFIG_ARCH_CHIP_LPC4337JBD144)
-#  define LPC43_FLASH_BANKA_SIZE   (512*1025)  /* 1024Kb FLASH */
-#  define LPC43_FLASH_BANKB_SIZE   (512*1025)
-#  define LPC43_LOCSRAM_BANK0_SIZE (32*1024)  /*  72Kb Local SRAM*/
+#  define LPC43_FLASH_BANKA_SIZE   (512*1024)  /* 1024Kb FLASH */
+#  define LPC43_FLASH_BANKB_SIZE   (512*1024)
+#  define LPC43_LOCSRAM_BANK0_SIZE (32*1024)   /* 72Kb Local SRAM */
 #  define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
 #  define LPC43_AHBSRAM_BANK0_SIZE (48*1024)   /* 64Kb AHB SRAM */
 #  define LPC43_AHBSRAM_BANK1_SIZE (0)
@@ -350,7 +350,7 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208)
 #  define LPC43_FLASH_BANKA_SIZE   (0)         /* Flashless */
 #  define LPC43_FLASH_BANKB_SIZE   (0)
-#  define LPC43_LOCSRAM_BANK0_SIZE (128*1024)  /* 200Kb Local SRAM*/
+#  define LPC43_LOCSRAM_BANK0_SIZE (128*1024)  /* 200Kb Local SRAM */
 #  define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
 #  define LPC43_AHBSRAM_BANK0_SIZE (48*1024)   /* 64Kb AHB SRAM */
 #  define LPC43_AHBSRAM_BANK1_SIZE (0)
@@ -376,7 +376,7 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC4350FET180)
 #  define LPC43_FLASH_BANKA_SIZE   (0)         /* Flashless */
 #  define LPC43_FLASH_BANKB_SIZE   (0)
-#  define LPC43_LOCSRAM_BANK0_SIZE (128*1024)  /* 200Kb Local SRAM*/
+#  define LPC43_LOCSRAM_BANK0_SIZE (128*1024)  /* 200Kb Local SRAM */
 #  define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
 #  define LPC43_AHBSRAM_BANK0_SIZE (48*1024)   /* 64Kb AHB SRAM */
 #  define LPC43_AHBSRAM_BANK1_SIZE (0)
@@ -402,7 +402,7 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC4350FET256)
 #  define LPC43_FLASH_BANKA_SIZE   (0)         /* Flashless */
 #  define LPC43_FLASH_BANKB_SIZE   (0)
-#  define LPC43_LOCSRAM_BANK0_SIZE (128*1024)  /* 200Kb Local SRAM*/
+#  define LPC43_LOCSRAM_BANK0_SIZE (128*1024)  /* 200Kb Local SRAM */
 #  define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
 #  define LPC43_AHBSRAM_BANK0_SIZE (48*1024)   /* 64Kb AHB SRAM */
 #  define LPC43_AHBSRAM_BANK1_SIZE (0)
@@ -426,9 +426,9 @@
 #  define LPC43_NADC10_CHANNELS    (8)         /* Eight ADC channels */
 #  undef  LPC43_NADC12                         /* No 12-bit ADC controllers */
 #elif defined(CONFIG_ARCH_CHIP_LPC4353FBD208)
-#  define LPC43_FLASH_BANKA_SIZE   (256*1025)  /* 512Kb FLASH */
-#  define LPC43_FLASH_BANKB_SIZE   (256*1025)
-#  define LPC43_LOCSRAM_BANK0_SIZE (32*1024)  /*  72Kb Local SRAM*/
+#  define LPC43_FLASH_BANKA_SIZE   (256*1024)  /* 512Kb FLASH */
+#  define LPC43_FLASH_BANKB_SIZE   (256*1024)
+#  define LPC43_LOCSRAM_BANK0_SIZE (32*1024)   /* 72Kb Local SRAM */
 #  define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
 #  define LPC43_AHBSRAM_BANK0_SIZE (48*1024)   /* 64Kb AHB SRAM */
 #  define LPC43_AHBSRAM_BANK1_SIZE (0)
@@ -452,9 +452,9 @@
 #  define LPC43_NADC10_CHANNELS    (8)         /* Eight ADC channels */
 #  undef  LPC43_NADC12                         /* No 12-bit ADC controllers */
 #elif defined(CONFIG_ARCH_CHIP_LPC4353FET180)
-#  define LPC43_FLASH_BANKA_SIZE   (256*1025)  /* 512Kb FLASH */
-#  define LPC43_FLASH_BANKB_SIZE   (256*1025)
-#  define LPC43_LOCSRAM_BANK0_SIZE (32*1024)  /*  72Kb Local SRAM*/
+#  define LPC43_FLASH_BANKA_SIZE   (256*1024)  /* 512Kb FLASH */
+#  define LPC43_FLASH_BANKB_SIZE   (256*1024)
+#  define LPC43_LOCSRAM_BANK0_SIZE (32*1024)   /* 72Kb Local SRAM */
 #  define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
 #  define LPC43_AHBSRAM_BANK0_SIZE (48*1024)   /* 64Kb AHB SRAM */
 #  define LPC43_AHBSRAM_BANK1_SIZE (0)
@@ -478,9 +478,9 @@
 #  define LPC43_NADC10_CHANNELS    (8)         /* Eight ADC channels */
 #  undef  LPC43_NADC12                         /* No 12-bit ADC controllers */
 #elif defined(CONFIG_ARCH_CHIP_LPC4353FET256)
-#  define LPC43_FLASH_BANKA_SIZE   (256*1025)  /* 512Kb FLASH */
-#  define LPC43_FLASH_BANKB_SIZE   (256*1025)
-#  define LPC43_LOCSRAM_BANK0_SIZE (32*1024)  /*  72Kb Local SRAM*/
+#  define LPC43_FLASH_BANKA_SIZE   (256*1024)  /* 512Kb FLASH */
+#  define LPC43_FLASH_BANKB_SIZE   (256*1024)
+#  define LPC43_LOCSRAM_BANK0_SIZE (32*1024)   /* 72Kb Local SRAM */
 #  define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
 #  define LPC43_AHBSRAM_BANK0_SIZE (48*1024)   /* 64Kb AHB SRAM */
 #  define LPC43_AHBSRAM_BANK1_SIZE (0)
@@ -504,9 +504,9 @@
 #  define LPC43_NADC10_CHANNELS    (8)         /* Eight ADC channels */
 #  undef  LPC43_NADC12                         /* No 12-bit ADC controllers */
 #elif defined(CONFIG_ARCH_CHIP_LPC4357FET180)
-#  define LPC43_FLASH_BANKA_SIZE   (512*1025)  /* 1024Kb FLASH */
-#  define LPC43_FLASH_BANKB_SIZE   (512*1025)
-#  define LPC43_LOCSRAM_BANK0_SIZE (32*1024)  /*  72Kb Local SRAM*/
+#  define LPC43_FLASH_BANKA_SIZE   (512*1024)  /* 1024Kb FLASH */
+#  define LPC43_FLASH_BANKB_SIZE   (512*1024)
+#  define LPC43_LOCSRAM_BANK0_SIZE (32*1024)   /* 72Kb Local SRAM */
 #  define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
 #  define LPC43_AHBSRAM_BANK0_SIZE (48*1024)   /* 64Kb AHB SRAM */
 #  define LPC43_AHBSRAM_BANK1_SIZE (0)
@@ -530,9 +530,9 @@
 #  define LPC43_NADC10_CHANNELS    (8)         /* Eight ADC channels */
 #  undef  LPC43_NADC12                         /* No 12-bit ADC controllers */
 #elif defined(CONFIG_ARCH_CHIP_LPC4357FBD208)
-#  define LPC43_FLASH_BANKA_SIZE   (512*1025)  /* 1024Kb FLASH */
-#  define LPC43_FLASH_BANKB_SIZE   (512*1025)
-#  define LPC43_LOCSRAM_BANK0_SIZE (32*1024)  /*  72Kb Local SRAM*/
+#  define LPC43_FLASH_BANKA_SIZE   (512*1024)  /* 1024Kb FLASH */
+#  define LPC43_FLASH_BANKB_SIZE   (512*1024)
+#  define LPC43_LOCSRAM_BANK0_SIZE (32*1024)   /* 72Kb Local SRAM */
 #  define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
 #  define LPC43_AHBSRAM_BANK0_SIZE (48*1024)   /* 64Kb AHB SRAM */
 #  define LPC43_AHBSRAM_BANK1_SIZE (0)
@@ -556,9 +556,9 @@
 #  define LPC43_NADC10_CHANNELS    (8)         /* Eight ADC channels */
 #  undef  LPC43_NADC12                         /* No 12-bit ADC controllers */
 #elif defined(CONFIG_ARCH_CHIP_LPC4357FET256)
-#  define LPC43_FLASH_BANKA_SIZE   (512*1025)  /* 1024Kb FLASH */
-#  define LPC43_FLASH_BANKB_SIZE   (512*1025)
-#  define LPC43_LOCSRAM_BANK0_SIZE (32*1024)  /*  72Kb Local SRAM*/
+#  define LPC43_FLASH_BANKA_SIZE   (512*1024)  /* 1024Kb FLASH */
+#  define LPC43_FLASH_BANKB_SIZE   (512*1024)
+#  define LPC43_LOCSRAM_BANK0_SIZE (32*1024)   /* 72Kb Local SRAM */
 #  define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
 #  define LPC43_AHBSRAM_BANK0_SIZE (48*1024)   /* 64Kb AHB SRAM */
 #  define LPC43_AHBSRAM_BANK1_SIZE (0)
@@ -632,6 +632,31 @@
 #  define LPC43_NDAC               (1)         /* One 10-bit DAC */
 #  define LPC43_NADC10_CHANNELS    (8)         /* Eight ADC channels (per ADC)*/
 #  define LPC43_NADC12             (1)         /* ONne 12-bit ADC controllers (ADCHS)*/
+#elif defined(CONFIG_ARCH_CHIP_LPC4337JET100)
+#  define LPC43_FLASH_BANKA_SIZE   (512*1024)  /* 1024Kb FLASH */
+#  define LPC43_FLASH_BANKB_SIZE   (512*1024)
+#  define LPC43_LOCSRAM_BANK0_SIZE (32*1024)   /* 72Kb Local SRAM */
+#  define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
+#  define LPC43_AHBSRAM_BANK0_SIZE (48*1024)   /* 64Kb AHB SRAM */
+#  define LPC43_AHBSRAM_BANK1_SIZE (0)
+#  define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
+#  define LPC43_EEPROM_SIZE        (16*1024)   /* 16Kb EEPROM */
+#  define LPC43_NLCD               (0)         /* Has LCD controller */
+#  define LPC43_ETHERNET           (1)         /* One Ethernet controller */
+#  define LPC43_USB0               (1)         /* Have USB0 (Host, Device, OTG) */
+#  define LPC43_USB1               (1)         /* Have USB1 (Host, Device) */
+#  define LPC43_USB1_ULPI          (0)         /* Have USB1 (Host, Device) with ULPI I/F */
+#  define LPC43_MCPWM              (0)         /* One PWM interface */
+#  define LPC43_QEI                (0)         /* One Quadrature Encoder interface */
+#  define LPC43_NUSARTS            (4)         /* Three USARTs + 1 UART */
+#  define LPC43_NSSP               (2)         /* Two SSP controllers */
+#  define LPC43_NTIMERS            (4)         /* Four Timers */
+#  define LPC43_NI2C               (2)         /* Two I2C controllers */
+#  define LPC43_NI2S               (2)         /* Two I2S controllers */
+#  define LPC43_NCAN               (2)         /* Two CAN controllers */
+#  define LPC43_NDAC               (1)         /* One 10-bit DAC */
+#  define LPC43_NADC               (2)         /* Two 10-bit ADC controllers */
+#  define LPC43_NADC_CHANNELS      (4)         /* Four ADC channels */
 #else
 #  error "Unsupported LPC43xx chip"
 #endif

arch/arm/include/stm32/chip.h

@@ -1568,7 +1568,7 @@
 #  define STM32_NGTIMNDMA                3   /* 16-bit general timers TIM9-11 without DMA */
 #  define STM32_NBTIM                    0   /* No basic timers */
 #  define STM32_NDMA                     2   /* DMA1-2 with 8 streams each*/
-#  define STM32_NSPI                     4   /* SPI1-4 */
+#  define STM32_NSPI                     5   /* SPI1-5 */
 #  define STM32_NI2S                     2   /* I2S1-2 (multiplexed with SPI2-3) */
 #  define STM32_NUSART                   6   /* Actually only 3: USART1, 2 and 6 */
 #  define STM32_NI2C                     3   /* I2C1-3 */
@@ -1585,6 +1585,44 @@
 #  define STM32_NRNG                     0   /* No Random number generator (RNG) */
 #  define STM32_NDCMI                    0   /* No digital camera interface (DCMI) */
 
+#elif defined(CONFIG_ARCH_CHIP_STM32F411VE)  /* 100 pin LQFP/BGA package, 512Kb FLASH, 128KiB SRAM */
+#  undef  CONFIG_STM32_STM32L15XX            /* STM32L151xx and STM32L152xx family */
+#  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite family */
+#  undef  CONFIG_STM32_STM32F10XX            /* STM32F10xxx family */
+#  undef  CONFIG_STM32_LOWDENSITY            /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+#  undef  CONFIG_STM32_MEDIUMDENSITY         /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+#  undef  CONFIG_STM32_MEDIUMPLUSDENSITY     /* STM32L15xxC w/ 32/256 Kbytes */
+#  undef  CONFIG_STM32_HIGHDENSITY           /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
+#  undef  CONFIG_STM32_VALUELINE             /* STM32F100x */
+#  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
+#  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
+#  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
+#  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx and STM32407xx */
+#  define STM32_NFSMC                    0   /* No FSMC */
+#  define STM32_NATIM                    1   /* One advanced timers TIM1 */
+#  define STM32_NGTIM                    4   /* 16-bit general timers TIM3 and 4 with DMA
+                                              * 32-bit general timers TIM2 and 5 with DMA */
+#  define STM32_NGTIMNDMA                3   /* 16-bit general timers TIM9-11 without DMA */
+#  define STM32_NBTIM                    0   /* No basic timers */
+#  define STM32_NDMA                     2   /* DMA1-2 with 8 streams each*/
+#  define STM32_NSPI                     5   /* SPI1-5 */
+#  define STM32_NI2S                     2   /* I2S1-2 (multiplexed with SPI2-3) */
+#  define STM32_NUSART                   6   /* Actually only 3: USART1, 2 and 6 */
+#  define STM32_NI2C                     3   /* I2C1-3 */
+#  define STM32_NCAN                     0   /* No CAN */
+#  define STM32_NSDIO                    1   /* One SDIO interface */
+#  define STM32_NLCD                     0   /* No LCD */
+#  define STM32_NUSBOTG                  1   /* USB OTG FS (only) */
+#  define STM32_NGPIO                    81  /* GPIOA-H */
+#  define STM32_NADC                     1   /* One 12-bit ADC1, 16 channels */
+#  define STM32_NDAC                     0   /* No DAC */
+#  define STM32_NCAPSENSE                0   /* No capacitive sensing channels */
+#  define STM32_NCRC                     1   /* No CRC */
+#  define STM32_NETHERNET                0   /* No Ethernet MAC */
+#  define STM32_NRNG                     0   /* No Random number generator (RNG) */
+#  define STM32_NDCMI                    0   /* No digital camera interface (DCMI) */
+
 #elif defined(CONFIG_ARCH_CHIP_STM32F405RG)  /* LQFP 64 10x10x1.4 1024Kb FLASH 192Kb SRAM */
 #  undef  CONFIG_STM32_STM32L15XX            /* STM32L151xx and STM32L152xx family */
 #  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite family */

arch/arm/include/stm32/stm32f10xxx_irq.h

@@ -120,7 +120,7 @@
 #  define STM32_IRQ_TIM5        (66) /* 50: TIM5 global interrupt */
 #  define STM32_IRQ_SPI3        (67) /* 51: SPI3 global interrupt */
 #  define STM32_IRQ_UART4       (68) /* 52: USART2 global interrupt */
-#  define STM32_IRQ_UART5       (69) /* 53: USART5 global interrupt */
+#  define STM32_IRQ_UART5       (69) /* 53: UART5 global interrupt */
 #  define STM32_IRQ_TIM6        (70) /* 54: TIM6 global interrupt */
 #  define STM32_IRQ_TIM7        (71) /* 55: TIM7 global interrupt */
 #  define STM32_IRQ_DMA2CH1     (72) /* 56: DMA2 Channel 1 global interrupt */

arch/arm/src/Makefile

@@ -1,7 +1,7 @@
 ############################################################################
 # arch/arm/src/Makefile
 #
-#   Copyright (C) 2007-2009, 2011-2012, 2014-2015 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2007-2009, 2011-2012, 2014-2016 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -127,6 +127,11 @@ BIN  = libarch$(LIBEXT)
 
 LDFLAGS += $(ARCHSCRIPT)
 
+# Override in Make.defs if linker is not 'ld'
+
+LDSTARTGROUP ?= --start-group
+LDENDGROUP ?= --end-group
+
 EXTRA_LIBS ?=
 EXTRA_LIBPATHS ?=
 LINKLIBS ?=
@@ -198,7 +203,7 @@ nuttx$(EXEEXT): $(HEAD_OBJ) board$(DELIM)libboard$(LIBEXT)
 	$(Q) echo "LD: nuttx"
 	$(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \
 		-o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \
-		--start-group $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) --end-group
+		$(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) $(LDENDGROUP)
 ifneq ($(CONFIG_WINDOWS_NATIVE),y)
 	$(Q) $(NM) $(NUTTX) | \
 	grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \

arch/arm/src/a1x/Kconfig

@@ -21,49 +21,49 @@ menu "Allwinner A1X Peripheral Support"
 config A1X_UART0
 	bool "UART 0"
 	default n
-	select ARCH_HAVE_UART0
+	select UART0_SERIALDRIVER
 	select ARCH_HAVE_SERIAL_TERMIOS
 
 config A1X_UART1
 	bool "UART 1"
 	default n
-	select ARCH_HAVE_UART1
+	select UART1_SERIALDRIVER
 	select ARCH_HAVE_SERIAL_TERMIOS
 
 config A1X_UART2
 	bool "UART 2"
 	default n
-	select ARCH_HAVE_UART2
+	select UART2_SERIALDRIVER
 	select ARCH_HAVE_SERIAL_TERMIOS
 
 config A1X_UART3
 	bool "UART 3"
 	default n
-	select ARCH_HAVE_UART3
+	select UART3_SERIALDRIVER
 	select ARCH_HAVE_SERIAL_TERMIOS
 
 config A1X_UART4
 	bool "UART 4"
 	default n
-	select ARCH_HAVE_UART4
+	select UART4_SERIALDRIVER
 	select ARCH_HAVE_SERIAL_TERMIOS
 
 config A1X_UART5
 	bool "UART 5"
 	default n
-	select ARCH_HAVE_UART5
+	select UART5_SERIALDRIVER
 	select ARCH_HAVE_SERIAL_TERMIOS
 
 config A1X_UART6
 	bool "UART 6"
 	default n
-	select ARCH_HAVE_UART6
+	select UART6_SERIALDRIVER
 	select ARCH_HAVE_SERIAL_TERMIOS
 
 config A1X_UART7
 	bool "UART 7"
 	default n
-	select ARCH_HAVE_UART7
+	select UART7_SERIALDRIVER
 	select ARCH_HAVE_SERIAL_TERMIOS
 
 config A1X_IR0

arch/arm/src/a1x/a1x_boot.c

@@ -289,7 +289,7 @@ static void a1x_copyvectorblock(void)
  ****************************************************************************/
 
 /****************************************************************************
- * Name: up_boot
+ * Name: arm_boot
  *
  * Description:
  *   Complete boot operations started in arm_head.S
@@ -305,7 +305,7 @@ static void a1x_copyvectorblock(void)
  *
  ****************************************************************************/
 
-void up_boot(void)
+void arm_boot(void)
 {
 #ifndef CONFIG_ARCH_ROMPGTABLE
   /* __start provided the basic MMU mappings for SRAM.  Now provide mappings

arch/arm/src/arm/up_head.S

@@ -609,7 +609,7 @@ __start:
 
 	/* Perform early C-level, platform-specific initialization */
 
-	bl		up_boot
+	bl		arm_boot
 
 #ifdef CONFIG_STACK_COLORATION
 	/* Write a known value to the IDLE thread stack to support stack

arch/arm/src/arm/up_pginitialize.c

@@ -88,7 +88,7 @@ void up_pginitialize(void)
 {
   /* None needed at present.  This file is just retained in case the need
    * arises in the future.  Nothing calls up_pginitialize() now.  If needed,
-   * if should be called early in up_boot.c to assure that all paging is
+   * if should be called early in arm_boot.c to assure that all paging is
    * ready.
    */
 }

arch/arm/src/armv7-a/arm_addrenv.c

@@ -141,10 +141,6 @@
 #  error CONFIG_ARCH_HEAP_VBASE not aligned to section boundary
 #endif
 
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
 /****************************************************************************
  * Private Functions
  ****************************************************************************/

arch/arm/src/armv7-a/arm_addrenv_kstack.c

@@ -121,18 +121,6 @@
 
 #if defined(CONFIG_ARCH_ADDRENV) && defined(CONFIG_ARCH_KERNEL_STACK)
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/armv7-a/arm_addrenv_shm.c

@@ -55,18 +55,6 @@
 
 #if defined(CONFIG_BUILD_KERNEL) && defined(CONFIG_MM_SHM)
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/armv7-a/arm_addrenv_ustack.c

@@ -116,14 +116,6 @@
 #  error CONFIG_ARCH_STACK_VBASE not aligned to section boundary
 #endif
 
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/armv7-a/arm_addrenv_utils.c

@@ -53,18 +53,6 @@
 
 #ifdef CONFIG_ARCH_ADDRENV
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/armv7-a/arm_allocpage.c

@@ -54,10 +54,6 @@
 #include "pg_macros.h"
 #include "up_internal.h"
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
 /****************************************************************************
  * Private Types
  ****************************************************************************/
@@ -108,10 +104,6 @@ static L1ndx_t g_ptemap[CONFIG_PAGING_NPPAGED];
 
 static bool g_pgwrap;
 
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/armv7-a/arm_assert.c

@@ -334,7 +334,13 @@ static void up_dumpstate(void)
     }
 #endif
 
-  /* Then dump the registers (if available) */
+#ifdef CONFIG_SMP
+  /* Show the CPU number */
+
+  lldbg("CPU%d:\n", up_cpu_index());
+#endif
+
+  /* Then dump the CPU registers (if available) */
 
   up_registerdump();
 

arch/arm/src/armv7-a/arm_checkmapping.c

@@ -51,18 +51,6 @@
 
 #ifdef CONFIG_PAGING
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/armv7-a/arm_coherent_dcache.c

@@ -46,18 +46,6 @@
 
 #include <nuttx/arch.h>
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/armv7-a/arm_copyfullstate.c

@@ -44,18 +44,6 @@
 
 #include "up_internal.h"
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/armv7-a/arm_cpuhead.S

@@ -0,0 +1,492 @@
+/****************************************************************************
+ * arch/arm/src/armv7-a/arm_cpuhead.S
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/board/board.h>
+
+#include "arm.h"
+#include "cp15.h"
+#include "sctlr.h"
+#include "mmu.h"
+#include "smp.h"
+
+#include "chip.h"
+#include "up_internal.h"
+
+	.file	"arm_cpuhead.S"
+
+/**********************************************************************************
+ * Configuration
+ **********************************************************************************/
+
+/* Hard-coded options */
+
+#undef CPU_ALIGNMENT_TRAP
+#undef CPU_CACHE_ROUND_ROBIN
+#undef CPU_DCACHE_DISABLE
+#undef CPU_ICACHE_DISABLE
+#undef CPU_AFE_ENABLE
+
+/* Check for the identity mapping:  For this configuration, this would be
+ * the case where the virtual beginning of RAM is the same as the physical
+ * beginning of RAM.
+ */
+
+#if !defined(CONFIG_RAM_START) || !defined(CONFIG_RAM_VSTART)
+#  error "CONFIG_RAM_START or CONFIG_RAM_VSTART is not defined"
+#endif
+
+#if CONFIG_RAM_START == CONFIG_RAM_VSTART
+#  define CONFIG_IDENTITY_TEXTMAP 1
+#endif
+
+/****************************************************************************
+ * .text
+ ****************************************************************************/
+
+	.text
+
+/****************************************************************************
+ * Name: __cpu[n]_start
+ *
+ * Description:
+ *   Boot functions for each CPU (other than CPU0).  These functions set up
+ *   the ARM operating mode, the initial stack, and configure co-processor
+ *   registers.  At the end of the boot, arm_cpu_boot() is called.
+ *
+ *   These functions are provided by the common ARMv7-A logic.
+ *
+ * Input parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Do not return.
+ *
+ ****************************************************************************/
+
+#if CONFIG_SMP_NCPUS > 1
+	.global	__cpu1_start
+	.type	__cpu1_start, #function
+
+__cpu1_start:
+	/* Set up the stack pointer and the CPU index */
+
+	ldr		sp, .Lcpu1_stackpointer
+	mov		r5, #1
+
+	/* Then branch to the common startup logic (PC-relative) */
+
+	b		.Lcpu_start
+
+.Lcpu1_stackpointer:
+	.long	.Lcpu1_stacktop
+	.size	__cpu1_start, .-__cpu1_start
+
+#if CONFIG_SMP_NCPUS > 2
+	.global	__cpu2_start
+	.type	__cpu2_start, #function
+
+__cpu2_start:
+	/* Set up the stack pointer and the CPU index */
+
+	ldr		sp, .Lcpu2_stackpointer
+	mov		r5, #2
+
+	/* Then branch to the common startup logic (PC-relative) */
+
+	b		.Lcpu_start
+
+.Lcpu2_stackpointer:
+	.long	.Lcpu2_stacktop
+	.size	__cpu2_start, .-__cpu2_start
+
+#if CONFIG_SMP_NCPUS > 3
+	.global	__cpu3_start
+	.type	__cpu3_start, #function
+
+__cpu3_start:
+	/* Set up the stack pointer and the CPU index */
+
+	ldr		sp, .Lcpu3_stackpointer
+	mov		r5, #3
+
+	/* Then branch to the common startup logic (PC-relative) */
+
+	b		.Lcpu_start
+
+.Lcpu3_stackpointer:
+	.long	.Lcpu3_stacktop
+	.size	__cpu3_start, .-__cpu3_start
+
+#if CONFIG_SMP_NCPUS > 4
+#  error This logic needs to extended for CONFIG_SMP_NCPUS > 4
+
+#endif /* CONFIG_SMP_NCPUS > 4 */
+#endif /* CONFIG_SMP_NCPUS > 3 */
+#endif /* CONFIG_SMP_NCPUS > 2 */
+#endif /* CONFIG_SMP_NCPUS > 1 */
+
+/****************************************************************************
+ * Name: .Lcpu_start
+ *
+ * Description:
+ *   Common CPUn startup logic (n > 0)
+ *
+ * On input:
+ *   SP = Set to top of CPU IDLE stack (virtual)
+ *   R5 = CPU number
+ *
+ ****************************************************************************/
+
+	.type	.Lcpu_start, #function
+
+.Lcpu_start:
+	/* Make sure that we are in SVC mode with IRQs and FIQs disabled */
+
+	mov		r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+	msr		cpsr_c, r0
+
+	/* The MMU and caches should be disabled */
+
+	mrc		CP15_SCTLR(r0)
+	bic		r0, r0, #(SCTLR_M | SCTLR_C)
+	bic		r0, r0, #(SCTLR_I)
+	mcr		CP15_SCTLR(r0)
+
+	/* Invalidate caches and TLBs.
+	 *
+	 *   NOTE: "The ARMv7 Virtual Memory System Architecture (VMSA) does not
+	 *   support a CP15 operation to invalidate the entire data cache. ...
+	 *   In normal usage the only time the entire data cache has to be
+	 *   invalidated is on reset."
+	 *
+	 * The instruction cache is virtually indexed and physically tagged but
+	 * the data cache is physically indexed and physically tagged.  So it
+	 * should not be an issue if the system comes up with a dirty Dcache;
+	 * the ICache, however, must be invalidated.
+	 */
+
+	mov		r0, #0
+	mcr		CP15_TLBIALL(r0,c7)	/* Invalidate the entire unified TLB */
+	mcr		CP15_TLBIALL(r0,c6)
+	mcr		CP15_TLBIALL(r0,c5)
+	mcr		CP15_BPIALL(r0)		/* Invalidate entire branch prediction array */
+	mcr		CP15_ICIALLU(r0)	/* Invalidate I-cache */
+
+	/* Load the page table address.
+	 *
+	 * NOTES:
+	 * - Here we assume that the page table address is aligned to at least
+	 *   least a 16KB boundary (bits 0-13 are zero).  No masking is provided
+	 *   to protect against an unaligned page table address.
+	 * - The ARMv7-A has two page table address registers, TTBR0 and 1.
+	 *   Only TTBR0 is used in this implementation but both are initialized.
+	 */
+
+	ldr		r1, .LCppgtable		/* r1=phys. page table */
+	orr		r1, r1, #(TTBR0_RGN_WBWA | TTBR0_IRGN0)	/* Select cache properties */
+	mcr		CP15_TTBR0(r1)
+	mcr		CP15_TTBR1(r1)
+
+	/* Set the TTB control register (TTBCR) to indicate that we are using
+	 * TTBR0.  r0 still holds the value of zero.
+	 *
+	 *   N   : 0=Selects TTBR0 and 16KB page table size indexed by VA[31:20]
+	 *   PD0 : 0=Perform translation table walks using TTBR0
+	 *   PD1 : 0=Perform translation table walks using TTBR1 (but it is disabled)
+	 *   EAE : 0=Use 32-bit translation system
+	 */
+
+	mcr		CP15_TTBCR(r0)
+
+	/* Enable the MMU and caches
+	 * lr = Resume at .Lcpu_vstart with the MMU enabled
+	 */
+
+	ldr		lr, .LCcpu_vstart		/* Abs. virtual address */
+
+	/* Configure the domain access register (see mmu.h).  Only domain 0 is
+	 * supported and it uses the permissions in the TLB.
+	 */
+
+	mov		r0, #DACR_CLIENT(0)
+	mcr		CP15_DACR(r0)			/* Set domain access register */
+
+	/* Configure the system control register (see sctrl.h) */
+
+	mrc		CP15_SCTLR(r0)			/* Get control register */
+
+	/* Clear bits to reset values.  This is only necessary in situations like, for
+	 * example, we get here via a bootloader and the control register is in some
+	 * unknown state.
+	 *
+	 *   SCTLR_M    Bit 0:  Enable the MMU
+	 *   SCTLR_A    Bit 1:  Strict alignment disabled (reset value)
+	 *   SCTLR_C    Bit 2:  DCache disabled (reset value)
+	 *
+	 *   SCTLR_SW   Bit 10: SWP/SWPB not enabled (reset value)
+	 *   SCTLR_I    Bit 12: ICache disabled (reset value)
+	 *   SCTLR_V    Bit 13: Assume low vectors (reset value)
+	 *   SCTLR_RR   Bit 14: The Cortex-A5 processor only supports a fixed random
+	 *                      replacement strategy.
+	 *   SCTLR_HA   Bit 17: Not supported by A5
+	 *
+	 *   SCTLR_EE   Bit 25: 0=Little endian (reset value).
+	 *   SCTLR_TRE  Bit 28: No memory region remapping (reset value)
+	 *   SCTLR_AFE  Bit 29: Full, legacy access permissions behavior (reset value).
+	 *   SCTLR_TE   Bit 30: All exceptions handled in ARM state (reset value).
+	 */
+
+	bic		r0, r0, #(SCTLR_A  | SCTLR_C)
+	bic		r0, r0, #(SCTLR_SW | SCTLR_I   | SCTLR_V   | SCTLR_RR | SCTLR_HA)
+	bic		r0, r0, #(SCTLR_EE | SCTLR_TRE | SCTLR_AFE | SCTLR_TE)
+
+	/* Set bits to enable the MMU
+	 *
+	 *   SCTLR_M     Bit 0:  Enable the MMU
+	 *   SCTLR_Z     Bit 11: Program flow prediction control always enabled on A5
+	 */
+
+	orr		r0, r0, #(SCTLR_M)
+#ifndef CONFIG_ARCH_CORTEXA5
+	orr		r0, r0, #(SCTLR_Z)
+#endif
+
+#ifndef CONFIG_ARCH_LOWVECTORS
+	/* Position vectors to 0xffff0000 if so configured.
+	 *
+	 *   SCTLR_V    Bit 13: High vectors
+	 */
+
+	orr		r0, r0, #(SCTLR_V)
+#endif
+
+#if defined(CPU_CACHE_ROUND_ROBIN) && !defined(CONFIG_ARCH_CORTEXA5)
+	/* Round Robin cache replacement
+	 *
+	 *   SCTLR_RR   Bit 14: The Cortex-A5 processor only supports a fixed random
+	 *                      replacement strategy.
+	 */
+
+	orr		r0, r0, #(SCTLR_RR)
+#endif
+
+#ifndef CPU_DCACHE_DISABLE
+	/* Dcache enable
+	 *
+	 *   SCTLR_C    Bit 2:  DCache enable
+	 */
+
+	orr		r0, r0, #(SCTLR_C)
+#endif
+
+#ifndef CPU_ICACHE_DISABLE
+	/* Icache enable
+	 *
+	 *   SCTLR_I    Bit 12: ICache enable
+	 */
+
+	orr		r0, r0, #(SCTLR_I)
+#endif
+
+#ifdef CPU_ALIGNMENT_TRAP
+	/* Alignment abort enable
+	 *
+	 *   SCTLR_A    Bit 1:  Strict alignment enabled
+	 */
+
+	orr		r0, r0, #(SCTLR_A)
+#endif
+
+#ifdef CONFIG_ENDIAN_BIG
+	/* Big endian mode
+	 *
+	 *   SCTLR_EE       Bit 25: 1=Big endian.
+	 */
+
+	orr		r0, r0, #(SCTLR_EE)
+#endif
+
+#ifdef CPU_AFE_ENABLE
+	/* AP[0:2] Permissions model
+	 *
+	 *   SCTLR_AFE  Bit 29: Full, legacy access permissions behavior (reset value).
+	 *
+	 * When AFE=1, the page table AP[0] is used as an access flag and AP[2:1]
+	 * control.  When AFE=0, AP[2:0] control access permissions.
+	 */
+
+	orr		r0, r0, #(SCTLR_AFE)
+#endif
+
+	/* Then write the configured control register */
+
+	mcr		CP15_SCTLR(r0)			/* Write control reg */
+	.rept	12						/* Cortex A8 wants lots of NOPs here */
+	nop
+	.endr
+
+	/* And "jump" to .Lcpu_vstart in the newly mapped virtual address space */
+
+	mov		pc, lr
+
+/****************************************************************************
+ * PC_Relative Data
+ ****************************************************************************/
+
+	/* The physical base address of the page table */
+
+	.type	.LCppgtable, %object
+.LCppgtable:
+	.long	PGTABLE_BASE_PADDR		/* Physical start of page table */
+	.size	.LCppgtable, . -.LCppgtable
+
+	/* The virtual start address of the second phase boot logic */
+
+	.type	.LCcpu_vstart, %object
+.LCcpu_vstart:
+	.long	.Lcpu_vstart
+	.size	.LCcpu_vstart, . -.LCcpu_vstart
+
+	.size	.Lcpu_start, .-.Lcpu_start
+
+/****************************************************************************
+ * Name: .Lcpu_vstart
+ *
+ * Description:
+ *   Continue initialization after the MMU has been enabled.
+ *
+ *   The following is executed after the MMU has been enabled. This uses
+ *   absolute addresses; this is not position independent.
+ *
+ * On input:
+ *   SP = Set to top of CPU IDLE stack (virtual)
+ *   R5 = CPU number
+ *
+ ****************************************************************************/
+
+	.align	8
+	.globl	arm_cpu_boot
+	.type	.Lcpu_vstart, %function
+
+.Lcpu_vstart:
+
+#ifdef CONFIG_STACK_COLORATION
+	/* Write a known value to the IDLE thread stack to support stack
+	 * monitoring logic
+	 */
+
+	adr		r3, .Lstkinit
+	ldmia	r3, {r0, r1, r2}	/* R0 = start of IDLE stack; R1 = Size of stack; R2 = coloration */
+
+1:								/* Top of the loop */
+	sub		r1, r1, #1			/* R1 = Number of words remaining */
+	cmp		r1, #0				/* Check (nwords == 0) */
+	str		r2, [r0], #4		/* Save stack color word, increment stack address */
+	bne		1b					/* Bottom of the loop */
+#endif
+
+	/* Branch to continue C level CPU initialization */
+
+	mov		fp, #0				/* Clear framepointer */
+	mov		lr, #0				/* LR = return address (none) */
+	mov		r0, r5				/* Input parameter = CPU index */
+	b		arm_cpu_boot		/* Branch to C level CPU initialization */
+	.size	.Lcpu_vstart, .-.Lcpu_vstart
+
+/***************************************************************************
+ * Text-section constants
+ ***************************************************************************/
+
+	/* Text-section constants: */
+
+#ifdef CONFIG_STACK_COLORATION
+	.type	.Lstkinit, %object
+.Lstkinit:
+	.long	SMP_STACK_WORDS
+	.long	STACK_COLOR				/* Stack coloration word */
+	.size	.Lstkinit, . -.Lstkinit
+#endif
+
+/***************************************************************************
+ * .noinit section data
+ ***************************************************************************/
+
+	.section	.noinit, "aw"
+
+#if CONFIG_SMP_NCPUS > 1
+	.align	8
+	.globl	g_cpu1_idlestack
+	.type	g_cpu1_idlestack, object
+
+g_cpu1_idlestack:
+	.space	SMP_STACK_SIZE
+.Lcpu1_stacktop:
+	.size	g_cpu1_idlestack, .Lcpu1_stacktop-g_cpu1_idlestack
+
+#if CONFIG_SMP_NCPUS > 2
+	.align	8
+	.globl	g_cpu2_idlestack
+	.type	g_cpu2_idlestack, object
+
+g_cpu2_idlestack:
+	.space	SMP_STACK_SIZE
+.Lcpu2_stacktop:
+	.size	g_cpu2_idlestack, .Lcpu2_stacktop-g_cpu2_idlestack
+
+#if CONFIG_SMP_NCPUS > 3
+	.align	8
+	.globl	g_cpu3_idlestack
+	.type	g_cpu3_idlestack, object
+
+g_cpu3_idlestack:
+	.space	SMP_STACK_SIZE
+.Lcpu3_stacktop:
+	.size	g_cpu3_idlestack, .Lcpu3_stacktop-g_cpu3_idlestack
+
+#if CONFIG_SMP_NCPUS > 4
+#  error This logic needs to extended for CONFIG_SMP_NCPUS > 4
+
+#endif /* CONFIG_SMP_NCPUS > 4 */
+#endif /* CONFIG_SMP_NCPUS > 3 */
+#endif /* CONFIG_SMP_NCPUS > 2 */
+#endif /* CONFIG_SMP_NCPUS > 1 */
+
+	.end

arch/arm/src/armv7-a/arm_cpuidlestack.c

@@ -0,0 +1,149 @@
+/****************************************************************************
+ * arch/arm/src/armv7-a/arm_cpuidlestack.c
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/sched.h>
+
+#include "smp.h"
+#include "up_internal.h"
+
+#ifdef CONFIG_SMP
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Stack alignment macros */
+
+#define STACK_ISALIGNED(a) ((uintptr_t)(a) & ~SMP_STACK_MASK)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#if CONFIG_SMP_NCPUS > 1
+static FAR const uint32_t *g_cpu_stackalloc[CONFIG_SMP_NCPUS] =
+{
+    0
+  , g_cpu1_idlestack
+#if CONFIG_SMP_NCPUS > 2
+  , g_cpu2_idlestack
+#if CONFIG_SMP_NCPUS > 3
+  , g_cpu3_idlestack
+#endif /* CONFIG_SMP_NCPUS > 3 */
+#endif /* CONFIG_SMP_NCPUS > 2 */
+};
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_cpu_idlestack
+ *
+ * Description:
+ *   Allocate a stack for the CPU[n] IDLE task (n > 0) if appropriate and
+ *   setup up stack-related information in the IDLE task's TCB.  This
+ *   function is always called before up_cpu_start().  This function is
+ *   only called for the CPU's initial IDLE task; up_create_task is used for
+ *   all normal tasks, pthreads, and kernel threads for all CPUs.
+ *
+ *   The initial IDLE task is a special case because the CPUs can be started
+ *   in different wans in different environments:
+ *
+ *   1. The CPU may already have been started and waiting in a low power
+ *      state for up_cpu_start().  In this case, the IDLE thread's stack
+ *      has already been allocated and is already in use.  Here
+ *      up_cpu_idlestack() only has to provide information about the
+ *      already allocated stack.
+ *
+ *   2. The CPU may be disabled but started when up_cpu_start() is called.
+ *      In this case, a new stack will need to be created for the IDLE
+ *      thread and this function is then equivalent to:
+ *
+ *      return up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL);
+ *
+ *   The following TCB fields must be initialized by this function:
+ *
+ *   - adj_stack_size: Stack size after adjustment for hardware, processor,
+ *     etc.  This value is retained only for debug purposes.
+ *   - stack_alloc_ptr: Pointer to allocated stack
+ *   - adj_stack_ptr: Adjusted stack_alloc_ptr for HW.  The initial value of
+ *     the stack pointer.
+ *
+ * Inputs:
+ *   - cpu:         CPU index that indicates which CPU the IDLE task is
+ *                  being created for.
+ *   - tcb:         The TCB of new CPU IDLE task
+ *   - stack_size:  The requested stack size for the IDLE task.  At least
+ *                  this much must be allocated.  This should be
+ *                  CONFIG_SMP_STACK_SIZE.
+ *
+ ****************************************************************************/
+
+int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size)
+{
+#if CONFIG_SMP_NCPUS > 1
+  uintptr_t stack_alloc;
+  uintptr_t top_of_stack;
+
+  DEBUGASSERT(cpu > 0 && cpu < CONFIG_SMP_NCPUS && tcb != NULL &&
+              stack_size <= SMP_STACK_SIZE);
+
+  /* Get the top of the stack */
+
+
+  stack_alloc          = (uintptr_t)g_cpu_stackalloc[cpu];
+  DEBUGASSERT(stack_alloc != 0 && STACK_ISALIGNED(stack_alloc));
+  top_of_stack         = stack_alloc + SMP_STACK_TOP;
+
+  tcb->adj_stack_size  = SMP_STACK_SIZE;
+  tcb->stack_alloc_ptr = (FAR uint32_t *)stack_alloc;
+  tcb->adj_stack_ptr   = (FAR uint32_t *)top_of_stack;
+#endif
+
+  return OK;
+}
+
+#endif /* CONFIG_SMP */

arch/arm/src/armv7-a/arm_cpustart.c

@@ -46,10 +46,42 @@
 
 #include "up_internal.h"
 #include "gic.h"
+#include "cp15_cacheops.h"
 #include "sched/sched.h"
 
 #ifdef CONFIG_SMP
 
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm_registerdump
+ ****************************************************************************/
+
+#if 0 /* Was useful in solving some startup problems */
+static inline void arm_registerdump(FAR struct tcb_s *tcb)
+{
+  int regndx;
+
+  lldbg("CPU%d:\n", up_cpu_index());
+
+  /* Dump the startup registers */
+
+  for (regndx = REG_R0; regndx <= REG_R15; regndx += 8)
+    {
+      uint32_t *ptr = (uint32_t *)&tcb->xcp.regs[regndx];
+      lldbg("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+             regndx, ptr[0], ptr[1], ptr[2], ptr[3],
+             ptr[4], ptr[5], ptr[6], ptr[7]);
+    }
+
+  lldbg("CPSR: %08x\n", tcb->xcp.regs[REG_CPSR]);
+}
+#else
+# define arm_registerdump(tcb)
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -72,12 +104,19 @@
 
 int arm_start_handler(int irq, FAR void *context)
 {
-  FAR struct tcb_s *tcb = this_task();
+  FAR struct tcb_s *tcb;
+
+  sllvdbg("CPU%d Started\n", up_cpu_index());
 
   /* Reset scheduler parameters */
 
+  tcb = this_task();
   sched_resume_scheduler(tcb);
 
+  /* Dump registers so that we can see what is going to happen on return */
+
+  arm_registerdump(tcb);
+
   /* Then switch contexts. This instantiates the exception context of the
    * tcb at the head of the assigned task list.  In this case, this should
    * be the CPUs NULL task.
@@ -116,8 +155,14 @@ int arm_start_handler(int irq, FAR void *context)
 
 int up_cpu_start(int cpu)
 {
+  sllvdbg("Starting CPU%d\n", cpu);
+
   DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
 
+  /* Make the content of CPU0 L1 cache has been written to coherent L2 */
+
+  cp15_clean_dcache(CONFIG_RAM_START, CONFIG_RAM_END - 1);
+
   /* Execute SGI1 */
 
   return arm_cpu_sgi(GIC_IRQ_SGI1, (1 << cpu));

arch/arm/src/armv7-a/arm_doirq.c

@@ -52,22 +52,6 @@
 
 #include "group/group.h"
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/armv7-a/arm_elf.c

@@ -48,18 +48,6 @@
 #include <nuttx/arch.h>
 #include <nuttx/binfmt/elf.h>
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/armv7-a/arm_fullcontextrestore.S

@@ -44,28 +44,12 @@
 
 	.file	"arm_fullcontextrestore.S"
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Symbols
  ****************************************************************************/
 
 	.globl	up_fullcontextrestore
 
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/armv7-a/arm_gicv2.c

@@ -166,12 +166,12 @@ void arm_gic_initialize(void)
 
   /* Registers with 8-bits per interrupt */
 
-  putreg32(0x80808080, GIC_ICDIPR(0));         /* SGI[3:0] priority */
-  putreg32(0x80808080, GIC_ICDIPR(4));         /* SGI[4:7] priority */
-  putreg32(0x80808080, GIC_ICDIPR(8));         /* SGI[8:11] priority */
-  putreg32(0x80808080, GIC_ICDIPR(12));        /* SGI[12:15] priority */
-  putreg32(0x80000000, GIC_ICDIPR(24));        /* PPI[0] priority */
-  putreg32(0x80808080, GIC_ICDIPR(28));        /* PPI[1:4] priority */
+  putreg32(0x80808080, GIC_ICDIPR(0));      /* SGI[3:0] priority */
+  putreg32(0x80808080, GIC_ICDIPR(4));      /* SGI[4:7] priority */
+  putreg32(0x80808080, GIC_ICDIPR(8));      /* SGI[8:11] priority */
+  putreg32(0x80808080, GIC_ICDIPR(12));     /* SGI[12:15] priority */
+  putreg32(0x80000000, GIC_ICDIPR(24));     /* PPI[0] priority */
+  putreg32(0x80808080, GIC_ICDIPR(28));     /* PPI[1:4] priority */
 
   /* Set the binary point register.
    *
@@ -211,7 +211,16 @@ void arm_gic_initialize(void)
 
 #endif
 
-#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_TRUSTZONE_BOTH)
+#if defined(CONFIG_ARCH_TRUSTZONE_SECURE)
+  /* Set FIQn=1 if secure interrupts are to signal using nfiq_c.
+   *
+   * NOTE:  Only for processors that operate in secure state.
+   * REVISIT: Do I need to do this?
+   */
+
+  //iccicr |= GIC_ICCICRS_FIQEN;
+
+#elif defined(CONFIG_ARCH_TRUSTZONE_BOTH)
   /* Set FIQn=1 if secure interrupts are to signal using nfiq_c.
    *
    * NOTE:  Only for processors that operate in secure state.
@@ -221,25 +230,35 @@ void arm_gic_initialize(void)
   iccicr |= GIC_ICCICRS_FIQEN;
 #endif
 
-#if defined(ONFIG_ARCH_TRUSTZONE_BOTH)
+#if defined(CONFIG_ARCH_TRUSTZONE_SECURE)
   /* Program the AckCtl bit to select the required interrupt acknowledge
    * behavior.
    *
    * NOTE: Only for processors that operate in both secure and non-secure
    * state.
-   * REVISIT: I don't yet fully understand this setting.
+   * REVISIT: This is here only for superstituous reasons.  I don't think
+   * I need this setting in this configuration.
    */
 
-  // iccicr |= GIC_ICCICRS_ACKTCTL;
+   iccicr |= GIC_ICCICRS_ACKTCTL;
+
+#elif defined(CONFIG_ARCH_TRUSTZONE_BOTH)
+  /* Program the AckCtl bit to select the required interrupt acknowledge
+   * behavior.
+   *
+   * NOTE: Only for processors that operate in both secure and non-secure
+   * state.
+   */
+
+   iccicr |= GIC_ICCICRS_ACKTCTL;
 
   /* Program the SBPR bit to select the required binary pointer behavior.
    *
    * NOTE: Only for processors that operate in both secure and non-secure
    * state.
-   * REVISIT: I don't yet fully understand this setting.
    */
 
-  // iccicr |= GIC_ICCICRS_CBPR;
+   iccicr |= GIC_ICCICRS_CBPR;
 #endif
 
 #if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_TRUSTZONE_BOTH)
@@ -291,9 +310,15 @@ void arm_gic_initialize(void)
    * bypass.
    */
 
+#if 0 /* REVISIT -- I don't know why this needs to be like this */
   iccicr |= (GIC_ICCICRS_ENABLEGRP0 | GIC_ICCICRS_FIQBYPDISGRP0 |
              GIC_ICCICRS_IRQBYPDISGRP0 | GIC_ICCICRS_FIQBYPDISGRP1 |
              GIC_ICCICRS_IRQBYPDISGRP1);
+#else
+  iccicr |= (GIC_ICCICRS_ENABLEGRP0 | GIC_ICCICRS_ENABLEGRP1 |
+             GIC_ICCICRS_FIQBYPDISGRP0 | GIC_ICCICRS_IRQBYPDISGRP0 |
+             GIC_ICCICRS_FIQBYPDISGRP1 | GIC_ICCICRS_IRQBYPDISGRP1);
+#endif
   icddcr  = GIC_ICDDCR_ENABLEGRP0;
 
 #elif defined(CONFIG_ARCH_TRUSTZONE_BOTH)
@@ -498,4 +523,56 @@ int up_prioritize_irq(int irq, int priority)
   return -EINVAL;
 }
 
+/****************************************************************************
+ * Name: arm_gic_irq_trigger
+ *
+ * Description:
+ *   Set the trigger type for the specified IRQ source and the current CPU.
+ *
+ *   Since this API is not supported on all architectures, it should be
+ *   avoided in common implementations where possible.
+ *
+ * Input Paramters:
+ *   irq - The interrupt request to modify.
+ *   edge - False: Active HIGH level sensitive, True: Rising edge sensitive
+ *
+ * Returned Value:
+ *   Zero (OK) on success; a negated errno value is returned on any failure.
+ *
+ ****************************************************************************/
+
+int arm_gic_irq_trigger(int irq, bool edge)
+{
+  uintptr_t regaddr;
+  uint32_t regval;
+  uint32_t intcfg;
+
+  if (irq > GIC_IRQ_SGI15 && irq < NR_IRQS)
+    {
+      /* Get the address of the Interrupt Configuration Register for this
+       * irq.
+       */
+
+      regaddr = GIC_ICDICFR(irq);
+
+      /* Get the new Interrupt configuration bit setting */
+
+      intcfg = (edge ? (INT_ICDICFR_EDGE | INT_ICDICFR_1N) : INT_ICDICFR_1N);
+
+      /* Write the correct interrupt trigger to the Interrupt Configuration
+       * Register.
+       */
+
+      regval  = getreg32(regaddr);
+      regval &= ~GIC_ICDICFR_ID_MASK(irq);
+      regval |= GIC_ICDICFR_ID(irq, intcfg);
+      putreg32(regval, regaddr);
+
+      return OK;
+    }
+
+  return -EINVAL;
+}
+
+
 #endif /* CONFIG_ARMV7A_HAVE_GICv2 */

arch/arm/src/armv7-a/arm_head.S

@@ -630,18 +630,18 @@ __start:
 #ifndef CONFIG_BOOT_SDRAM_DATA
 	/* Initialize .bss and .data ONLY if .bss and .data lie in SRAM that is
 	 * ready to use.  Other memory, such as SDRAM, must be initialized before
-	 * it can be used.  up_boot() will perform that memory initialization and
-	 * .bss and .data can be initialized after up_boot() returns.
+	 * it can be used.  arm_boot() will perform that memory initialization and
+	 * .bss and .data can be initialized after arm_boot() returns.
 	 */
 
 	bl		arm_data_initialize
 #endif
 
 	/* Perform early C-level, platform-specific initialization.  Logic
-	 * within up_boot() must configure SDRAM and call arm_ram_initailize.
+	 * within arm_boot() must configure SDRAM and call arm_ram_initailize.
 	 */
 
-	bl		up_boot
+	bl		arm_boot
 
 #ifdef CONFIG_STACK_COLORATION
 	/* Write a known value to the IDLE thread stack to support stack

arch/arm/src/armv7-a/arm_initialstate.c

@@ -48,18 +48,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/armv7-a/arm_mmu.c

@@ -44,18 +44,6 @@
 #include "cache.h"
 #include "mmu.h"
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/armv7-a/arm_pgalloc.c

@@ -54,13 +54,6 @@
 
 #ifdef CONFIG_BUILD_KERNEL
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
 
 /****************************************************************************
  * Private Functions

arch/arm/src/armv7-a/arm_pghead.S

@@ -650,8 +650,8 @@ __start:
 
 	/* Initialize .bss and .data ONLY if .bss and .data lie in SRAM that is
 	 * ready to use.  Other memory, such as SDRAM, must be initialized before
-	 * it can be used.  up_boot() will perform that memory initialization and
-	 * .bss and .data can be initialized after up_boot() returns.
+	 * it can be used.  arm_boot() will perform that memory initialization and
+	 * .bss and .data can be initialized after arm_boot() returns.
 	 */
 
 	/* Set up the stack pointer and clear the frame pointer */
@@ -662,18 +662,18 @@ __start:
 #ifndef CONFIG_BOOT_SDRAM_DATA
 	/* Initialize .bss and .data ONLY if .bss and .data lie in SRAM that is
 	 * ready to use.  Other memory, such as SDRAM, must be initialized before
-	 * it can be used.  up_boot() will perform that memory initialization and
-	 * .bss and .data can be initialized after up_boot() returns.
+	 * it can be used.  arm_boot() will perform that memory initialization and
+	 * .bss and .data can be initialized after arm_boot() returns.
 	 */
 
 	bl		arm_data_initialize
 #endif
 
 	/* Perform early C-level, platform-specific initialization.  Logic
-	 * within up_boot() must configure SDRAM and call arm_ram_initailize.
+	 * within arm_boot() must configure SDRAM and call arm_ram_initailize.
 	 */
 
-	bl		up_boot
+	bl		arm_boot
 
 #ifdef CONFIG_STACK_COLORATION
 	/* Write a known value to the IDLE thread stack to support stack

arch/arm/src/armv7-a/arm_pginitialize.c

@@ -49,18 +49,6 @@
 
 #ifdef CONFIG_PAGING
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -88,7 +76,7 @@ void up_pginitialize(void)
 {
   /* None needed at present.  This file is just retained in case the need
    * arises in the future.  Nothing calls up_pginitialize() now.  If needed,
-   * if should be called early in up_boot.c to assure that all paging is
+   * if should be called early in arm_boot.c to assure that all paging is
    * ready.
    */
 }

arch/arm/src/armv7-a/arm_physpgaddr.c

@@ -55,17 +55,6 @@
 
 #ifdef CONFIG_MM_PGALLOC
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/armv7-a/arm_prefetchabort.c

@@ -61,18 +61,6 @@
 #include "sched/sched.h"
 #include "up_internal.h"
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/armv7-a/arm_restorefpu.S

@@ -45,10 +45,6 @@
 
 	.file		"arm_restorefpu.S"
 
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
 /************************************************************************************
  * Public Symbols
  ************************************************************************************/

arch/arm/src/armv7-a/arm_saveusercontext.S

@@ -42,28 +42,12 @@
 
 	.file	"arm_saveusercontext.S"
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Symbols
  ****************************************************************************/
 
 	.globl	up_saveusercontext
 
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/armv7-a/arm_schedulesigaction.c

@@ -53,18 +53,6 @@
 
 #ifndef CONFIG_DISABLE_SIGNALS
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/armv7-a/arm_signal_dispatch.c

@@ -47,18 +47,6 @@
 #if ((defined(CONFIG_BUILD_PROTECTED) && defined(__KERNEL__)) || \
       defined(CONFIG_BUILD_KERNEL)) && !defined(CONFIG_DISABLE_SIGNALS)
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/armv7-a/arm_syscall.c

@@ -77,7 +77,7 @@
 #endif
 
 /****************************************************************************
- * Private Data
+ * Private Functions
  ****************************************************************************/
 
 /****************************************************************************