mirror of
https://github.com/apache/nuttx.git
synced 2026-05-19 03:03:37 +08:00
style fixes
This commit is contained in:
Matias N
committed by
Mateusz Szafoni
Mateusz Szafoni
parent
4ad36ffbbf
commit
ae6ae113eb
@@ -1,4 +1,4 @@
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/************************************************************************************************
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/****************************************************************************
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* arch/arm/src/nrf52/hardware/nrf52_clock.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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@@ -31,23 +31,23 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_CLOCK_H
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#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_CLOCK_H
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/************************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/nrf52_memorymap.h"
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/************************************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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************************************************************************************************/
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****************************************************************************/
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/* Register offsets *****************************************************************************/
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/* Register offsets *********************************************************/
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#define NRF52_CLOCK_TASKS_HFCLKSTART_OFFSET 0x0000 /* Start HFCLK crystal oscillator */
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#define NRF52_CLOCK_TASKS_HFCLKSTOP_OFFSET 0x0004 /* Stop HFCLK crystal oscillator */
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@@ -78,7 +78,7 @@
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#define NRF52_CLOCK_CTIV_OFFSET 0x0538 /* Calibration timer interval */
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#define NRF52_CLOCK_TRACECONFIG_OFFSET 0x055c /* Clocking options for the Trace Port debug interface */
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/* Register Addresses ***************************************************************************/
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/* Register Addresses *******************************************************/
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#define NRF52_CLOCK_TASKS_HFCLKSTART (NRF52_CLOCK_BASE + NRF52_CLOCK_TASKS_HFCLKSTART_OFFSET)
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#define NRF52_CLOCK_TASKS_HFCLKSTOP (NRF52_CLOCK_BASE + NRF52_CLOCK_TASKS_HFCLKSTOP_OFFSET)
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@@ -109,7 +109,7 @@
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#define NRF52_CLOCK_CTIV (NRF52_CLOCK_BASE + NRF52_CLOCK_CTIV_OFFSET)
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#define NRF52_CLOCK_TRACECONFIG (NRF52_CLOCK_BASE + NRF52_CLOCK_TRACECONFIG_OFFSET)
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/* Register Bitfield Definitions ****************************************************************/
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/* Register Bitfield Definitions ********************************************/
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/* HFCLKRUN Register */
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@@ -117,11 +117,11 @@
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/* HFCLKSTAT Register */
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#define CLOCK_HFCLKSTAT_SRC_SHIFT (0) /* Bit 0: Source of HFCLK */
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#define CLOCK_HFCLKSTAT_SRC_SHIFT (0) /* Bit 0: Source of HFCLK */
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#define CLOCK_HFCLKSTAT_SRC_MASK (1 << CLOCK_HFCLKSTAT_SRC_SHIFT)
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# define CLOCK_HFCLKSTAT_SRC_RC (0 << CLOCK_HFCLKSTAT_SRC_SHIFT) /* 0b0: 64 MHz internal oscillator (HFINT) */
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# define CLOCK_HFCLKSTAT_SRC_XTAL (1 << CLOCK_HFCLKSTAT_SRC_SHIFT) /* 0b1: 64 MHz crystal oscilator (HFXO) */
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#define CLOCK_HFCLKSTAT_STATE (1 << 16) /* Bit 16: HFCLK state */
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#define CLOCK_HFCLKSTAT_STATE (1 << 16) /* Bit 16: HFCLK state */
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/* LFCLKRUN Register */
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@@ -129,12 +129,12 @@
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/* LFCLKSTAT Register */
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#define CLOCK_LFCLKSTAT_SRC_SHIFT (0) /* Bits 0-1: Source of LFCLK */
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#define CLOCK_LFCLKSTAT_SRC_SHIFT (0) /* Bits 0-1: Source of LFCLK */
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#define CLOCK_LFCLKSTAT_SRC_MASK (3 << CLOCK_LFCLKSTAT_SRC_SHIFT)
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# define CLOCK_LFCLKSTAT_SRC_RC (0 << CLOCK_LFCLKSTAT_SRC_SHIFT) /* 0b0: RC oscillator (LFRC) */
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# define CLOCK_LFCLKSTAT_SRC_XTAL (1 << CLOCK_LFCLKSTAT_SRC_SHIFT) /* 0b1: crystal oscillator (LFXO) */
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# define CLOCK_LFCLKSTAT_SRC_SYNTH (2 << CLOCK_LFCLKSTAT_SRC_SHIFT) /* 0b2: synthesized from HFCLK (LFSYNT) */
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#define CLOCK_LFCLKSTAT_STATE (1 << 16) /* Bit 16: LFCLKSTAT state */
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#define CLOCK_LFCLKSTAT_STATE (1 << 16) /* Bit 16: LFCLKSTAT state */
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/* LFCLKSRC Register */
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@@ -23,16 +23,16 @@
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/****************************************************************************
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* Included Files
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***************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/nrf52_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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***************************************************************************/
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****************************************************************************/
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/* Register offsets for GPIOTE *********************************************/
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/* Register offsets for GPIOTE **********************************************/
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#define NRF52_GPIOTE_TASKS_OUT_OFFSET(x) (0x0000 + (0x04 * x)) /* TASKS_OUT[x] */
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#define NRF52_GPIOTE_TASKS_SET_OFFSET(x) (0x0030 + (0x04 * x)) /* TASKS_SET[x] */
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@@ -43,7 +43,7 @@
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#define NRF52_GPIOTE_INTENCLR_OFFSET 0x0308 /* INTENCLR */
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#define NRF52_GPIOTE_CONFIG_OFFSET(x) (0x0510 + (0x04 * x)) /* CONFIG[x] */
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/* Register addresses for GPIOTE *******************************************/
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/* Register addresses for GPIOTE ********************************************/
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#define NRF52_GPIOTE_TASKS_OUT(x) (NRF52_GPIOTE_BASE + NRF52_GPIOTE_TASKS_OUT_OFFSET(x))
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#define NRF52_GPIOTE_TASKS_SET(x) (NRF52_GPIOTE_BASE + NRF52_GPIOTE_TASKS_SET_OFFSET(x))
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@@ -54,18 +54,20 @@
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#define NRF52_GPIOTE_INTENCLR (NRF52_GPIOTE_BASE + NRF52_GPIOTE_INTENCLR_OFFSET)
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#define NRF52_GPIOTE_CONFIG(x) (NRF52_GPIOTE_BASE + NRF52_GPIOTE_CONFIG_OFFSET(x))
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/* Register offsets for GPIOTE *********************************************/
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/* Register offsets for GPIOTE **********************************************/
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/* EVENT_IN Register */
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#define GPIOTE_EVENT_IN_EVENT (1 << 0) /* Bit 0: Event generated from pin */
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#define GPIOTE_EVENT_IN_EVENT (1 << 0) /* Bit 0: Event generated from pin */
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/* INTENSET/INTENCLR Register */
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#define GPIOTE_INT_IN_SHIFT 0 /* Bits 0-7: Enable interrupt for event IN[i] */
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#define GPIOTE_INT_IN_MASK (0xff << GPIOTE_INT_IN_SHIFT)
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# define GPIOTE_INT_IN(i) ((1 << (i + GPIOTE_INT_IN_SHIFT)) & GPIOTE_INT_IN_MASK)
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#define GPIOTE_INT_PORT 31 /* Bit 31: Enable interrupt for event PORT */
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#define GPIOTE_INT_IN_SHIFT 0 /* Bits 0-7: Enable interrupt for event IN[i] */
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#define GPIOTE_INT_IN_MASK (0xff << GPIOTE_INT_IN_SHIFT)
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# define GPIOTE_INT_IN(i) ((1 << (i + GPIOTE_INT_IN_SHIFT)) & GPIOTE_INT_IN_MASK)
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#define GPIOTE_INT_PORT 31 /* Bit 31: Enable interrupt for event PORT */
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/* CONFIG Register */
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@@ -74,6 +76,7 @@
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# define GPIOTE_CONFIG_MODE_DIS (0x0 << GPIOTE_CONFIG_MODE_SHIFT) /* 0: Disabled */
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# define GPIOTE_CONFIG_MODE_EV (0x1 << GPIOTE_CONFIG_MODE_SHIFT) /* 1: Event */
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# define GPIOTE_CONFIG_MODE_TS (0x3 << GPIOTE_CONFIG_MODE_SHIFT) /* 2: Task */
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#define GPIOTE_CONFIG_PSEL_SHIFT (8) /* Bits 8-12: GPIO number */
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#define GPIOTE_CONFIG_PSEL_MASK (0x1f << GPIOTE_CONFIG_PSEL_SHIFT)
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#define GPIOTE_CONFIG_PORT_SHIFT (13) /* Bit 13: GPIO port */
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@@ -83,6 +86,7 @@
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# define GPIOTE_CONFIG_POL_LTH (0x1 << GPIOTE_CONFIG_POL_SHIFT) /* 1: LoToHi */
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# define GPIOTE_CONFIG_POL_HTL (0x2 << GPIOTE_CONFIG_POL_SHIFT) /* 2: HiToLo */
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# define GPIOTE_CONFIG_POL_TG (0x3 << GPIOTE_CONFIG_POL_SHIFT) /* 3: Toggle */
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#define GPIOTE_CONFIG_OUTINIT_SHIFT (20) /* Bit 20: Initial value */
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#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_GPIOTE_H */
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@@ -21,18 +21,18 @@
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#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_RADIO_H
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#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_RADIO_H
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/************************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/nrf52_memorymap.h"
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/************************************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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************************************************************************************************/
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****************************************************************************/
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/* Register offsets *****************************************************************************/
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/* Register offsets *********************************************************/
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#define NRF52_RADIO_TASKS_TXEN_OFFSET 0x0000 /* Enable RADIO in TX mode */
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#define NRF52_RADIO_TASKS_RXEN_OFFSET 0x0004 /* Enable RADIO in RX mode */
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@@ -97,8 +97,10 @@
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#define NRF52_RADIO_STATE_OFFSET 0x0550 /* Current radio state */
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#define NRF52_RADIO_DATAWHITEIV_OFFSET 0x0554 /* Data whitening initial value */
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#define NRF52_RADIO_BCC_OFFSET 0x0560 /* Bit counter compare */
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#define NRF52_RADIO_DAB_OFFSET(p) (0x0600 + ((p) * 0x4)) /* Device address base segment */
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#define NRF52_RADIO_DAP_OFFSET(p) (0x0620 + ((p) * 0x4)) /* Device address prefix */
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#define NRF52_RADIO_DACNF_OFFSET 0x0640 /* Device address match configuration */
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#define NRF52_RADIO_MHRMATCHCONF_OFFSET 0x0644 /* Search pattern configuration */
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#define NRF52_RADIO_MHRMATCHMAS_OFFSET 0x0648 /* Pattern mask */
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@@ -109,7 +111,7 @@
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#define NRF52_RADIO_CCACTRL_OFFSET 0x066c /* IEEE 802.15.4 clear channel assessment control */
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#define NRF52_RADIO_POWER_OFFSET 0x0ffc /* Peripheral power control */
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/* Register Addresses ***************************************************************************/
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/* Register Addresses *******************************************************/
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#define NRF52_RADIO_TASKS_TXEN (NRF52_RADIO_BASE + NRF52_RADIO_TASKS_TXEN_OFFSET)
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#define NRF52_RADIO_TASKS_RXEN (NRF52_RADIO_BASE + NRF52_RADIO_TASKS_RXEN_OFFSET)
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@@ -186,7 +188,7 @@
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#define NRF52_RADIO_CCACTRL (NRF52_RADIO_BASE + NRF52_RADIO_CCACTRL_OFFSET)
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#define NRF52_RADIO_POWER (NRF52_RADIO_BASE + NRF52_RADIO_POWER_OFFSET)
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/* Register Bitfield Definitions ****************************************************************/
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/* Register Bitfield Definitions ********************************************/
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/* TASKS_TXEN Register */
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@@ -423,15 +425,15 @@
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#define RADIO_MODE_NRF2MBIT (0x01 << RADIO_MODE_SHIFT) /* 1: 2 Mbit/s Nordic proprietary radio mode */
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#if defined(CONFIG_ARCH_CHIP_NRF52832)
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#define RADIO_MODE_NRF250KBIT (0x02 << RADIO_MODE_SHIFT) /* 2: 250 kbit/s Nordic proprietary radio mode (deprecated) */
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#define RADIO_MODE_BLE1MBIT (0x03 << RADIO_MODE_SHIFT) /* 3: 1 Mbit/s BLE */
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#define RADIO_MODE_BLE2MBIT (0x04 << RADIO_MODE_SHIFT) /* 4: 2 Mbit/s BLE */
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# define RADIO_MODE_NRF250KBIT (0x02 << RADIO_MODE_SHIFT) /* 2: 250 kbit/s Nordic proprietary radio mode (deprecated) */
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# define RADIO_MODE_BLE1MBIT (0x03 << RADIO_MODE_SHIFT) /* 3: 1 Mbit/s BLE */
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# define RADIO_MODE_BLE2MBIT (0x04 << RADIO_MODE_SHIFT) /* 4: 2 Mbit/s BLE */
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#elif defined(CONFIG_ARCH_CHIP_NRF52840)
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#define RADIO_MODE_BLE1MBIT (0x03 << RADIO_MODE_SHIFT) /* 3: 1 Mbit/s BLE */
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#define RADIO_MODE_BLE2MBIT (0x04 << RADIO_MODE_SHIFT) /* 4: 2 Mbit/s BLE */
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#define RADIO_MODE_BLELR125KBIT (0x05 << RADIO_MODE_SHIFT) /* 5: Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX */
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#define RADIO_MODE_BLELR500KBIT (0x06 << RADIO_MODE_SHIFT) /* 6: Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX */
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#define RADIO_MODE_IEEE802154 (0x0f << RADIO_MODE_SHIFT) /* 15: IEEE 802.15.4-2006 250 kbit/s */
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# define RADIO_MODE_BLE1MBIT (0x03 << RADIO_MODE_SHIFT) /* 3: 1 Mbit/s BLE */
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# define RADIO_MODE_BLE2MBIT (0x04 << RADIO_MODE_SHIFT) /* 4: 2 Mbit/s BLE */
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# define RADIO_MODE_BLELR125KBIT (0x05 << RADIO_MODE_SHIFT) /* 5: Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX */
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# define RADIO_MODE_BLELR500KBIT (0x06 << RADIO_MODE_SHIFT) /* 6: Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX */
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# define RADIO_MODE_IEEE802154 (0x0f << RADIO_MODE_SHIFT) /* 15: IEEE 802.15.4-2006 250 kbit/s */
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#endif
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/* PCNF0 Register */
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@@ -448,9 +450,9 @@
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#define RADIO_PCNF0_S1INCL (1 << 20) /* Bit 20: Include or exclude S1 field in RAM */
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#ifdef CONFIG_ARCH_CHIP_NRF52840
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#define RADIO_PCNF0_CILEN_SHIFT (22) /* Bits 22-23: Length of code indicator - long range */
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#define RADIO_PCNF0_CILEN_MASK (0x3 << RADIO_PCNF0_CILEN_SHIFT)
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#define RADIO_PCNF0_CILEN_MAX (0x3)
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# define RADIO_PCNF0_CILEN_SHIFT (22) /* Bits 22-23: Length of code indicator - long range */
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# define RADIO_PCNF0_CILEN_MASK (0x3 << RADIO_PCNF0_CILEN_SHIFT)
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# define RADIO_PCNF0_CILEN_MAX (0x3)
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#endif
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#define RADIO_PCNF0_PLEN_SHIFT (24) /* Bits 24-25: Length of preamble on air */
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@@ -461,11 +463,11 @@
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# define RADIO_PCNF0_PLEN_LONGRANGE (3 << RADIO_PCNF0_PLEN_SHIFT)
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#ifdef CONFIG_ARCH_CHIP_NRF52840
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#define RADIO_PCNF0_CRCINC_SHIFT (26) /* Bit 26: Indicates if LENGTH field contains CRC */
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#define RADIO_PCNF0_CRCINC (1 << RADIO_PCNF0_CRCINC_SHIFT)
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#define RADIO_PCNF0_TERMLEN_SHIFT (29) /* Bits 29-30: Length of TERM field in Long Range operation */
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#define RADIO_PCNF0_TERMLEN_MASK (0x3 << RADIO_PCNF0_TERMLEN_SHIFT)
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#define RADIO_PCNF0_TERMLEN_MAX (0x3)
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# define RADIO_PCNF0_CRCINC_SHIFT (26) /* Bit 26: Indicates if LENGTH field contains CRC */
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# define RADIO_PCNF0_CRCINC (1 << RADIO_PCNF0_CRCINC_SHIFT)
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# define RADIO_PCNF0_TERMLEN_SHIFT (29) /* Bits 29-30: Length of TERM field in Long Range operation */
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# define RADIO_PCNF0_TERMLEN_MASK (0x3 << RADIO_PCNF0_TERMLEN_SHIFT)
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# define RADIO_PCNF0_TERMLEN_MAX (0x3)
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#endif
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/* PCNF1 Register */
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