diff --git a/arch/arm/src/nrf52/hardware/nrf52_clock.h b/arch/arm/src/nrf52/hardware/nrf52_clock.h index 472bd4be670..80b8eae26ed 100644 --- a/arch/arm/src/nrf52/hardware/nrf52_clock.h +++ b/arch/arm/src/nrf52/hardware/nrf52_clock.h @@ -1,4 +1,4 @@ -/************************************************************************************************ +/**************************************************************************** * arch/arm/src/nrf52/hardware/nrf52_clock.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -31,23 +31,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_CLOCK_H #define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_CLOCK_H -/************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/nrf52_memorymap.h" -/************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ + ****************************************************************************/ -/* Register offsets *****************************************************************************/ +/* Register offsets *********************************************************/ #define NRF52_CLOCK_TASKS_HFCLKSTART_OFFSET 0x0000 /* Start HFCLK crystal oscillator */ #define NRF52_CLOCK_TASKS_HFCLKSTOP_OFFSET 0x0004 /* Stop HFCLK crystal oscillator */ @@ -78,7 +78,7 @@ #define NRF52_CLOCK_CTIV_OFFSET 0x0538 /* Calibration timer interval */ #define NRF52_CLOCK_TRACECONFIG_OFFSET 0x055c /* Clocking options for the Trace Port debug interface */ -/* Register Addresses ***************************************************************************/ +/* Register Addresses *******************************************************/ #define NRF52_CLOCK_TASKS_HFCLKSTART (NRF52_CLOCK_BASE + NRF52_CLOCK_TASKS_HFCLKSTART_OFFSET) #define NRF52_CLOCK_TASKS_HFCLKSTOP (NRF52_CLOCK_BASE + NRF52_CLOCK_TASKS_HFCLKSTOP_OFFSET) @@ -109,7 +109,7 @@ #define NRF52_CLOCK_CTIV (NRF52_CLOCK_BASE + NRF52_CLOCK_CTIV_OFFSET) #define NRF52_CLOCK_TRACECONFIG (NRF52_CLOCK_BASE + NRF52_CLOCK_TRACECONFIG_OFFSET) -/* Register Bitfield Definitions ****************************************************************/ +/* Register Bitfield Definitions ********************************************/ /* HFCLKRUN Register */ @@ -117,11 +117,11 @@ /* HFCLKSTAT Register */ -#define CLOCK_HFCLKSTAT_SRC_SHIFT (0) /* Bit 0: Source of HFCLK */ +#define CLOCK_HFCLKSTAT_SRC_SHIFT (0) /* Bit 0: Source of HFCLK */ #define CLOCK_HFCLKSTAT_SRC_MASK (1 << CLOCK_HFCLKSTAT_SRC_SHIFT) # define CLOCK_HFCLKSTAT_SRC_RC (0 << CLOCK_HFCLKSTAT_SRC_SHIFT) /* 0b0: 64 MHz internal oscillator (HFINT) */ # define CLOCK_HFCLKSTAT_SRC_XTAL (1 << CLOCK_HFCLKSTAT_SRC_SHIFT) /* 0b1: 64 MHz crystal oscilator (HFXO) */ -#define CLOCK_HFCLKSTAT_STATE (1 << 16) /* Bit 16: HFCLK state */ +#define CLOCK_HFCLKSTAT_STATE (1 << 16) /* Bit 16: HFCLK state */ /* LFCLKRUN Register */ @@ -129,12 +129,12 @@ /* LFCLKSTAT Register */ -#define CLOCK_LFCLKSTAT_SRC_SHIFT (0) /* Bits 0-1: Source of LFCLK */ +#define CLOCK_LFCLKSTAT_SRC_SHIFT (0) /* Bits 0-1: Source of LFCLK */ #define CLOCK_LFCLKSTAT_SRC_MASK (3 << CLOCK_LFCLKSTAT_SRC_SHIFT) # define CLOCK_LFCLKSTAT_SRC_RC (0 << CLOCK_LFCLKSTAT_SRC_SHIFT) /* 0b0: RC oscillator (LFRC) */ # define CLOCK_LFCLKSTAT_SRC_XTAL (1 << CLOCK_LFCLKSTAT_SRC_SHIFT) /* 0b1: crystal oscillator (LFXO) */ # define CLOCK_LFCLKSTAT_SRC_SYNTH (2 << CLOCK_LFCLKSTAT_SRC_SHIFT) /* 0b2: synthesized from HFCLK (LFSYNT) */ -#define CLOCK_LFCLKSTAT_STATE (1 << 16) /* Bit 16: LFCLKSTAT state */ +#define CLOCK_LFCLKSTAT_STATE (1 << 16) /* Bit 16: LFCLKSTAT state */ /* LFCLKSRC Register */ diff --git a/arch/arm/src/nrf52/hardware/nrf52_gpiote.h b/arch/arm/src/nrf52/hardware/nrf52_gpiote.h index cb593d6ca32..e4fb92bd48f 100644 --- a/arch/arm/src/nrf52/hardware/nrf52_gpiote.h +++ b/arch/arm/src/nrf52/hardware/nrf52_gpiote.h @@ -23,16 +23,16 @@ /**************************************************************************** * Included Files - ***************************************************************************/ + ****************************************************************************/ #include #include "hardware/nrf52_memorymap.h" /**************************************************************************** * Pre-processor Definitions - ***************************************************************************/ + ****************************************************************************/ -/* Register offsets for GPIOTE *********************************************/ +/* Register offsets for GPIOTE **********************************************/ #define NRF52_GPIOTE_TASKS_OUT_OFFSET(x) (0x0000 + (0x04 * x)) /* TASKS_OUT[x] */ #define NRF52_GPIOTE_TASKS_SET_OFFSET(x) (0x0030 + (0x04 * x)) /* TASKS_SET[x] */ @@ -43,7 +43,7 @@ #define NRF52_GPIOTE_INTENCLR_OFFSET 0x0308 /* INTENCLR */ #define NRF52_GPIOTE_CONFIG_OFFSET(x) (0x0510 + (0x04 * x)) /* CONFIG[x] */ -/* Register addresses for GPIOTE *******************************************/ +/* Register addresses for GPIOTE ********************************************/ #define NRF52_GPIOTE_TASKS_OUT(x) (NRF52_GPIOTE_BASE + NRF52_GPIOTE_TASKS_OUT_OFFSET(x)) #define NRF52_GPIOTE_TASKS_SET(x) (NRF52_GPIOTE_BASE + NRF52_GPIOTE_TASKS_SET_OFFSET(x)) @@ -54,18 +54,20 @@ #define NRF52_GPIOTE_INTENCLR (NRF52_GPIOTE_BASE + NRF52_GPIOTE_INTENCLR_OFFSET) #define NRF52_GPIOTE_CONFIG(x) (NRF52_GPIOTE_BASE + NRF52_GPIOTE_CONFIG_OFFSET(x)) -/* Register offsets for GPIOTE *********************************************/ +/* Register offsets for GPIOTE **********************************************/ /* EVENT_IN Register */ -#define GPIOTE_EVENT_IN_EVENT (1 << 0) /* Bit 0: Event generated from pin */ +#define GPIOTE_EVENT_IN_EVENT (1 << 0) /* Bit 0: Event generated from pin */ /* INTENSET/INTENCLR Register */ -#define GPIOTE_INT_IN_SHIFT 0 /* Bits 0-7: Enable interrupt for event IN[i] */ -#define GPIOTE_INT_IN_MASK (0xff << GPIOTE_INT_IN_SHIFT) -# define GPIOTE_INT_IN(i) ((1 << (i + GPIOTE_INT_IN_SHIFT)) & GPIOTE_INT_IN_MASK) -#define GPIOTE_INT_PORT 31 /* Bit 31: Enable interrupt for event PORT */ +#define GPIOTE_INT_IN_SHIFT 0 /* Bits 0-7: Enable interrupt for event IN[i] */ + +#define GPIOTE_INT_IN_MASK (0xff << GPIOTE_INT_IN_SHIFT) +# define GPIOTE_INT_IN(i) ((1 << (i + GPIOTE_INT_IN_SHIFT)) & GPIOTE_INT_IN_MASK) + +#define GPIOTE_INT_PORT 31 /* Bit 31: Enable interrupt for event PORT */ /* CONFIG Register */ @@ -74,6 +76,7 @@ # define GPIOTE_CONFIG_MODE_DIS (0x0 << GPIOTE_CONFIG_MODE_SHIFT) /* 0: Disabled */ # define GPIOTE_CONFIG_MODE_EV (0x1 << GPIOTE_CONFIG_MODE_SHIFT) /* 1: Event */ # define GPIOTE_CONFIG_MODE_TS (0x3 << GPIOTE_CONFIG_MODE_SHIFT) /* 2: Task */ + #define GPIOTE_CONFIG_PSEL_SHIFT (8) /* Bits 8-12: GPIO number */ #define GPIOTE_CONFIG_PSEL_MASK (0x1f << GPIOTE_CONFIG_PSEL_SHIFT) #define GPIOTE_CONFIG_PORT_SHIFT (13) /* Bit 13: GPIO port */ @@ -83,6 +86,7 @@ # define GPIOTE_CONFIG_POL_LTH (0x1 << GPIOTE_CONFIG_POL_SHIFT) /* 1: LoToHi */ # define GPIOTE_CONFIG_POL_HTL (0x2 << GPIOTE_CONFIG_POL_SHIFT) /* 2: HiToLo */ # define GPIOTE_CONFIG_POL_TG (0x3 << GPIOTE_CONFIG_POL_SHIFT) /* 3: Toggle */ + #define GPIOTE_CONFIG_OUTINIT_SHIFT (20) /* Bit 20: Initial value */ #endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_GPIOTE_H */ diff --git a/arch/arm/src/nrf52/hardware/nrf52_radio.h b/arch/arm/src/nrf52/hardware/nrf52_radio.h index 22ceebf4b5a..bed74ec61f5 100644 --- a/arch/arm/src/nrf52/hardware/nrf52_radio.h +++ b/arch/arm/src/nrf52/hardware/nrf52_radio.h @@ -21,18 +21,18 @@ #ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_RADIO_H #define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_RADIO_H -/************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/nrf52_memorymap.h" -/************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ + ****************************************************************************/ -/* Register offsets *****************************************************************************/ +/* Register offsets *********************************************************/ #define NRF52_RADIO_TASKS_TXEN_OFFSET 0x0000 /* Enable RADIO in TX mode */ #define NRF52_RADIO_TASKS_RXEN_OFFSET 0x0004 /* Enable RADIO in RX mode */ @@ -97,8 +97,10 @@ #define NRF52_RADIO_STATE_OFFSET 0x0550 /* Current radio state */ #define NRF52_RADIO_DATAWHITEIV_OFFSET 0x0554 /* Data whitening initial value */ #define NRF52_RADIO_BCC_OFFSET 0x0560 /* Bit counter compare */ + #define NRF52_RADIO_DAB_OFFSET(p) (0x0600 + ((p) * 0x4)) /* Device address base segment */ #define NRF52_RADIO_DAP_OFFSET(p) (0x0620 + ((p) * 0x4)) /* Device address prefix */ + #define NRF52_RADIO_DACNF_OFFSET 0x0640 /* Device address match configuration */ #define NRF52_RADIO_MHRMATCHCONF_OFFSET 0x0644 /* Search pattern configuration */ #define NRF52_RADIO_MHRMATCHMAS_OFFSET 0x0648 /* Pattern mask */ @@ -109,7 +111,7 @@ #define NRF52_RADIO_CCACTRL_OFFSET 0x066c /* IEEE 802.15.4 clear channel assessment control */ #define NRF52_RADIO_POWER_OFFSET 0x0ffc /* Peripheral power control */ -/* Register Addresses ***************************************************************************/ +/* Register Addresses *******************************************************/ #define NRF52_RADIO_TASKS_TXEN (NRF52_RADIO_BASE + NRF52_RADIO_TASKS_TXEN_OFFSET) #define NRF52_RADIO_TASKS_RXEN (NRF52_RADIO_BASE + NRF52_RADIO_TASKS_RXEN_OFFSET) @@ -186,7 +188,7 @@ #define NRF52_RADIO_CCACTRL (NRF52_RADIO_BASE + NRF52_RADIO_CCACTRL_OFFSET) #define NRF52_RADIO_POWER (NRF52_RADIO_BASE + NRF52_RADIO_POWER_OFFSET) -/* Register Bitfield Definitions ****************************************************************/ +/* Register Bitfield Definitions ********************************************/ /* TASKS_TXEN Register */ @@ -423,15 +425,15 @@ #define RADIO_MODE_NRF2MBIT (0x01 << RADIO_MODE_SHIFT) /* 1: 2 Mbit/s Nordic proprietary radio mode */ #if defined(CONFIG_ARCH_CHIP_NRF52832) -#define RADIO_MODE_NRF250KBIT (0x02 << RADIO_MODE_SHIFT) /* 2: 250 kbit/s Nordic proprietary radio mode (deprecated) */ -#define RADIO_MODE_BLE1MBIT (0x03 << RADIO_MODE_SHIFT) /* 3: 1 Mbit/s BLE */ -#define RADIO_MODE_BLE2MBIT (0x04 << RADIO_MODE_SHIFT) /* 4: 2 Mbit/s BLE */ +# define RADIO_MODE_NRF250KBIT (0x02 << RADIO_MODE_SHIFT) /* 2: 250 kbit/s Nordic proprietary radio mode (deprecated) */ +# define RADIO_MODE_BLE1MBIT (0x03 << RADIO_MODE_SHIFT) /* 3: 1 Mbit/s BLE */ +# define RADIO_MODE_BLE2MBIT (0x04 << RADIO_MODE_SHIFT) /* 4: 2 Mbit/s BLE */ #elif defined(CONFIG_ARCH_CHIP_NRF52840) -#define RADIO_MODE_BLE1MBIT (0x03 << RADIO_MODE_SHIFT) /* 3: 1 Mbit/s BLE */ -#define RADIO_MODE_BLE2MBIT (0x04 << RADIO_MODE_SHIFT) /* 4: 2 Mbit/s BLE */ -#define RADIO_MODE_BLELR125KBIT (0x05 << RADIO_MODE_SHIFT) /* 5: Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX */ -#define RADIO_MODE_BLELR500KBIT (0x06 << RADIO_MODE_SHIFT) /* 6: Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX */ -#define RADIO_MODE_IEEE802154 (0x0f << RADIO_MODE_SHIFT) /* 15: IEEE 802.15.4-2006 250 kbit/s */ +# define RADIO_MODE_BLE1MBIT (0x03 << RADIO_MODE_SHIFT) /* 3: 1 Mbit/s BLE */ +# define RADIO_MODE_BLE2MBIT (0x04 << RADIO_MODE_SHIFT) /* 4: 2 Mbit/s BLE */ +# define RADIO_MODE_BLELR125KBIT (0x05 << RADIO_MODE_SHIFT) /* 5: Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX */ +# define RADIO_MODE_BLELR500KBIT (0x06 << RADIO_MODE_SHIFT) /* 6: Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX */ +# define RADIO_MODE_IEEE802154 (0x0f << RADIO_MODE_SHIFT) /* 15: IEEE 802.15.4-2006 250 kbit/s */ #endif /* PCNF0 Register */ @@ -448,9 +450,9 @@ #define RADIO_PCNF0_S1INCL (1 << 20) /* Bit 20: Include or exclude S1 field in RAM */ #ifdef CONFIG_ARCH_CHIP_NRF52840 -#define RADIO_PCNF0_CILEN_SHIFT (22) /* Bits 22-23: Length of code indicator - long range */ -#define RADIO_PCNF0_CILEN_MASK (0x3 << RADIO_PCNF0_CILEN_SHIFT) -#define RADIO_PCNF0_CILEN_MAX (0x3) +# define RADIO_PCNF0_CILEN_SHIFT (22) /* Bits 22-23: Length of code indicator - long range */ +# define RADIO_PCNF0_CILEN_MASK (0x3 << RADIO_PCNF0_CILEN_SHIFT) +# define RADIO_PCNF0_CILEN_MAX (0x3) #endif #define RADIO_PCNF0_PLEN_SHIFT (24) /* Bits 24-25: Length of preamble on air */ @@ -461,11 +463,11 @@ # define RADIO_PCNF0_PLEN_LONGRANGE (3 << RADIO_PCNF0_PLEN_SHIFT) #ifdef CONFIG_ARCH_CHIP_NRF52840 -#define RADIO_PCNF0_CRCINC_SHIFT (26) /* Bit 26: Indicates if LENGTH field contains CRC */ -#define RADIO_PCNF0_CRCINC (1 << RADIO_PCNF0_CRCINC_SHIFT) -#define RADIO_PCNF0_TERMLEN_SHIFT (29) /* Bits 29-30: Length of TERM field in Long Range operation */ -#define RADIO_PCNF0_TERMLEN_MASK (0x3 << RADIO_PCNF0_TERMLEN_SHIFT) -#define RADIO_PCNF0_TERMLEN_MAX (0x3) +# define RADIO_PCNF0_CRCINC_SHIFT (26) /* Bit 26: Indicates if LENGTH field contains CRC */ +# define RADIO_PCNF0_CRCINC (1 << RADIO_PCNF0_CRCINC_SHIFT) +# define RADIO_PCNF0_TERMLEN_SHIFT (29) /* Bits 29-30: Length of TERM field in Long Range operation */ +# define RADIO_PCNF0_TERMLEN_MASK (0x3 << RADIO_PCNF0_TERMLEN_SHIFT) +# define RADIO_PCNF0_TERMLEN_MAX (0x3) #endif /* PCNF1 Register */