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This is the initial commit the port to the SAMD5x/E5x MCU family and also support for the Adafruit Metro M4 board. It port is untested and unfinished. It currently will not even link due to some missing clock related logic.

Browse Source 
Squashed commit of the following:

    arch/arm/src/samd5e5: Clean-up EIC logic.
    arch/arm/src/samd5e5:  Fix some compilation issues; Still issues with the EIC logic from samd2x.
    arch/arm/src/samd5e5:  Fix some compilation issues; bring in some EIC logic from samd2x.
    arch/arm/src/samd5e5:  Add NVMCTRL header file, fix some compiler problems, misc. clean-up.
    configs/metro-m4:  Add LED support.
    arch/arm/src/samd5e5:  Bring in SAML21 clock configuration.  This is a WIP; it cannot possible even compile yet.
    arch/arm/src/samd5e5:  Leverage Cortex-M4 interrupt and SysTick logic from the SAM3/4.
    arch/arm/src/samd5e5: Add SERCOM utility function.
    arch/arm/src/samd5e5:  Bring all SERCOM USART logic from SAMD2L2 to SAMD5E5.  This is a brute coy with nothing more than more that name changes and extension from 5 to 7 SERCOMs.
    arch/arm/src/samd5e5: Add sam_config.h header file
    arch/arm/src/samd5e5/:  Add Generic Clock (GCLK) utility functions.
    arch/arm/src/samd5e5:  Add EVSYS register definition file
    arch/arm/src/samd5e5 and configs/metro-m4:  Use SERCOM3 for the Arduino serial shield as console.
    arch/arm/src/samd5e5/chip:  Add SERCOM USART, SPI, I2C master, and slave register defintions header files
    arch/arm/src/samd5e5/chip:  Add AES, PM, TRNG, and WDT header files.
    arch/arm/src/samd5e5/chip:  Add pin multiplexing header files.
    Various fixes to configuration system; fix metro-m4/nsh defconfig file.
    configs/metro-m4:  Add initial support for the Adafruit Metro M4 board.
    arch/arm/src/samd5e5:  Add peripheral clock helpers.
    arch/arm/src/samd5e5/chip:  Add PAC register definition header file.  Fix some errors in the memory map header file.
    arch/arm/src/samd5e5:  Add chip.h headerf file.
    arch/arm/src/samd5e5:  Add PORT register definitions and support from SAML21.
    arch/arm/include/samd5e5:  Add interrupt vector definitions.
    arch/arm/src/samd5e5:  Add some boilerplate files.  Correct some typos.
    arch/arm/src/samd5e5/chip/sam_eic.h:  Add EIC register definitions.
    arch/arm/src/samd5e5/chip:  Add OSC32KCTRL and OSCCTRL register definitions.
    arch/arm/src/samd5e5/chip:  Add GCLK, MCLK, and RSTC header files.
    arch/arm/src/samd5e5/chip/sam_cmcc.h:  Add CMCC register definitions
    arch/arm/src/samd5e5/chip/sam_supc.h:  Add SUPC header file.
    arch/arm/src/samd5e5:  Add start-up logic.
    arch/arm/src/samd5e5:  Add Make.defs file
    arch/arm/src/samd5e5/chip:  Add memory map header file.
    arch/arm/include/samd5e5:  Add chip.h header file.
    arch/arm/Kconfig and arch/arm/src/samd5e5/Kconfig:  Add configuration logic for the SAMD5x/Ex family.
This commit is contained in:
Gregory Nutt
2018-07-26 12:08:58 -06:00
parent bf2a61b8cf
commit a9d713bbcc
77 changed files with 18888 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/README.html
+3 -1
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@@ -8,7 +8,7 @@
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
<p>Last Updated: July 18, 2018</p>
<p>Last Updated: July 24, 2018</p>
</td>
</tr>
</table>
@@ -154,6 +154,8 @@ nuttx/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/mcb1700/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- mcu123-lpc214x/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/mcu123-lpc214x/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- metro-m4/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/metro-m4/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- micropendous3/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/micropendous3/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- mikroe-stm32f4/
README.txt
+2
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@@ -1827,6 +1827,8 @@ nuttx/
| | `- README.txt
| |- mcu123-lpc214x/
| | `- README.txt
| |- metro-m4/
| | `- README.txt
| |- micropendous3/
| | `- README.txt
| |- mikroe-stm32f/
arch/arm/Kconfig
+20 -4
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@@ -222,16 +222,28 @@ config ARCH_CHIP_SAMA5
Atmel SAMA5 (ARM Cortex-A5)
config ARCH_CHIP_SAMD2X
bool "Atmel SAMD2x"
bool "Microchip/Atmel SAMD2x"
select ARCH_CORTEXM0
---help---
Atmel SAMD (ARM Cortex-M0+)
Microchip (formerly Atmel) SAMD2X (ARM Cortex-M0+)
config ARCH_CHIP_SAML2X
bool "Atmel SAML2x"
bool "Microchip/Atmel SAML2x"
select ARCH_CORTEXM0
---help---
Atmel SAML (ARM Cortex-M0+)
Microchip (formerly Atmel) SAML2X (ARM Cortex-M0+)
config ARCH_CHIP_SAMD5X
bool "Microchip SAMD5x"
select ARCH_CORTEXM4
---help---
Microchip SAMD5X (ARM Cortex-M4)
config ARCH_CHIP_SAME5X
bool "Microchip SAME5x"
select ARCH_CORTEXM4
---help---
Microchip SAME5x (ARM Cortex-M4)
config ARCH_CHIP_SAM34
bool "Atmel SAM3/SAM4"
@@ -580,6 +592,7 @@ config ARCH_CHIP
default "nuc1xx" if ARCH_CHIP_NUC1XX
default "sama5" if ARCH_CHIP_SAMA5
default "samd2l2" if ARCH_CHIP_SAMD2X || ARCH_CHIP_SAML2X
default "samd5e5" if ARCH_CHIP_SAMD5X || ARCH_CHIP_SAME5X
default "sam34" if ARCH_CHIP_SAM34
default "samv7" if ARCH_CHIP_SAMV7
default "stm32" if ARCH_CHIP_STM32
@@ -846,6 +859,9 @@ endif
if ARCH_CHIP_SAMD2X || ARCH_CHIP_SAML2X
source arch/arm/src/samd2l2/Kconfig
endif
if ARCH_CHIP_SAMD5X || ARCH_CHIP_SAME5X
source arch/arm/src/samd5e5/Kconfig
endif
if ARCH_CHIP_SAM34
source arch/arm/src/sam34/Kconfig
endif
arch/arm/include/samd5e5/chip.h
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arch/arm/include/samd5e5/irq.h
+113
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@@ -0,0 +1,113 @@
/****************************************************************************************
* arch/arm/include/samd5e5/irq.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAMD5E5_IRQ_H
#define __ARCH_ARM_INCLUDE_SAMD5E5_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include <arch/samd5e5/chip.h>
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*/
/* Common Processor Exceptions (vectors 0-15) */
#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define SAM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define SAM_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define SAM_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define SAM_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define SAM_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define SAM_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define SAM_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define SAM_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define SAM_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* Chip-Specific External interrupts */
#define SAM_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(ARCH_CHIP_SAME5X)
# include <arch/samd5e5/samd5e5_irq.h>
#else
# error "Unsupported SAMD5/E5 family"
#endif
/****************************************************************************************
* Public Types
****************************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************************
* Public Data
****************************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAMD5E5_IRQ_H */
arch/arm/include/samd5e5/samd5e5_irq.h
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@@ -0,0 +1,246 @@
/************************************************************************************************
* arch/arm/include/samd5e5/sam4l_irq.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAMD5E5_SAM4L_IRQ_H
#define __ARCH_ARM_INCLUDE_SAMD5E5_SAM4L_IRQ_H
/************************************************************************************************
* Included Files
************************************************************************************************/
/************************************************************************************************
* Pre-processor Definitions
************************************************************************************************/
/* External interrupts (vectors >= 16) */
#define SAM_IRQ_PM (SAM_IRQ_EXTINT+0) /* 0 Power Manager: SLEEPRDY */
#define SAM_IRQ_MCLK (SAM_IRQ_EXTINT+1) /* 1 Main clock: CKRDY */
#define SAM_IRQ_XOSC0 (SAM_IRQ_EXTINT+2) /* 2 XOSC0: Fail/Ready */
#define SAM_IRQ_XOSC1 (SAM_IRQ_EXTINT+3) /* 3 XOSC1: Fail/Ready */
#define SAM_IRQ_DFLL (SAM_IRQ_EXTINT+4) /* 4 OSCCTRLD: FLLLOCKC, DFLLLOCKF,
* DFLLOOB, DFLLRCS, DFLLRDY */
#define SAM_IRQ_DPLL0 (SAM_IRQ_EXTINT+5) /* 5 DPLL0: DPLLLCKF, DPLLLCKR,
* DPLLLDRTO, DPLLLTO */
#define SAM_IRQ_DPLL1 (SAM_IRQ_EXTINT+6) /* 6 DPLL1: DPLLLCKF, DPLLLCKR,
* DPLLLDRTO, DPLLLTO */
#define SAM_IRQ_OSC32K (SAM_IRQ_EXTINT+7) /* 7 OSC32KCTRL: OSC32KRDY,
* XOSC32KFAIL, XOSC32KRDY */
#define SAM_IRQ_SUPCRDY (SAM_IRQ_EXTINT+8) /* 8 Supply Controller: BOD12RDY,
* BOD33RDY, B12SRDY, B33SRDY,
* VCORERDY, VREGRDY */
#define SAM_IRQ_SUPCDET (SAM_IRQ_EXTINT+9) /* 9 Supply Controller: BOD12DET,
* BOD33DET */
#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+10) /* 10 WDT: EW */
#define SAM_IRQ_RTC (SAM_IRQ_EXTINT+11) /* 11 RTC, CMPA0-3, PERA0-7, TAMPERA */
#define SAM_IRQ_EXTINT0 (SAM_IRQ_EXTINT+12) /* 12 EIC: EXTINT0 */
#define SAM_IRQ_EXTINT1 (SAM_IRQ_EXTINT+13) /* 13 EIC: EXTINT1 */
#define SAM_IRQ_EXTINT2 (SAM_IRQ_EXTINT+14) /* 14 EIC: EXTINT2 */
#define SAM_IRQ_EXTINT3 (SAM_IRQ_EXTINT+15) /* 15 EIC: EXTINT3 */
#define SAM_IRQ_EXTINT4 (SAM_IRQ_EXTINT+16) /* 16 EIC: EXTINT4 */
#define SAM_IRQ_EXTINT5 (SAM_IRQ_EXTINT+17) /* 17 EIC: EXTINT5 */
#define SAM_IRQ_EXTINT6 (SAM_IRQ_EXTINT+18) /* 18 EIC: EXTINT6 */
#define SAM_IRQ_EXTINT7 (SAM_IRQ_EXTINT+19) /* 19 EIC: EXTINT7 */
#define SAM_IRQ_EXTINT8 (SAM_IRQ_EXTINT+20) /* 20 EIC: EXTINT8 */
#define SAM_IRQ_EXTINT9 (SAM_IRQ_EXTINT+21) /* 21 EIC: EXTINT9 */
#define SAM_IRQ_EXTINT10 (SAM_IRQ_EXTINT+22) /* 22 EIC: EXTINT10 */
#define SAM_IRQ_EXTINT11 (SAM_IRQ_EXTINT+23) /* 23 EIC: EXTINT11 */
#define SAM_IRQ_EXTINT12 (SAM_IRQ_EXTINT+24) /* 24 EIC: EXTINT12 */
#define SAM_IRQ_EXTINT13 (SAM_IRQ_EXTINT+25) /* 25 EIC: EXTINT13 */
#define SAM_IRQ_EXTINT14 (SAM_IRQ_EXTINT+26) /* 26 EIC: EXTINT14 */
#define SAM_IRQ_EXTINT15 (SAM_IRQ_EXTINT+27) /* 27 EIC: EXTINT15 */
#define SAM_IRQ_FREQM (SAM_IRQ_EXTINT+28) /* 28 FREQM: Done */
#define SAM_IRQ_NVMCTRL0 (SAM_IRQ_EXTINT+29) /* 29 NVMCTRL: 0-7 */
#define SAM_IRQ_NVMCTRL1 (SAM_IRQ_EXTINT+30) /* 30 NVMCTRL: 8-10 */
#define SAM_IRQ_DMACH0 (SAM_IRQ_EXTINT+31) /* 31 DMA Channel 0: SUSP, TCMPL, TERR */
#define SAM_IRQ_DMACH1 (SAM_IRQ_EXTINT+32) /* 32 DMA Channel 1: SUSP, TCMPL, TERR */
#define SAM_IRQ_DMACH2 (SAM_IRQ_EXTINT+33) /* 33 DMA Channel 2: SUSP, TCMPL, TERR */
#define SAM_IRQ_DMACH3 (SAM_IRQ_EXTINT+34) /* 34 DMA Channel 3: SUSP, TCMPL, TERR */
#define SAM_IRQ_DMACH4_31 (SAM_IRQ_EXTINT+35) /* 35 DMA Channels 4-31: SUSP, TCMPL, TERR */
#define SAM_IRQ_EVSYS0 (SAM_IRQ_EXTINT+36) /* 36 EVSYS Channel 0: EVD, OVR */
#define SAM_IRQ_EVSYS1 (SAM_IRQ_EXTINT+37) /* 37 EVSYS Channel 1: EVD, OVR */
#define SAM_IRQ_EVSYS2 (SAM_IRQ_EXTINT+38) /* 38 EVSYS Channel 2: EVD, OVR */
#define SAM_IRQ_EVSYS3 (SAM_IRQ_EXTINT+39) /* 39 EVSYS Channel 3: EVD, OVR */
#define SAM_IRQ_EVSYS4_11 (SAM_IRQ_EXTINT+40) /* 40 EVSYS Channels 4-11: EVD, OVR */
#define SAM_IRQ_PAC (SAM_IRQ_EXTINT+41) /* 41 PAC: ERR */
#define SAM_IRQ_RAMECC (SAM_IRQ_EXTINT+45) /* 45 RAM ECC: 0-1 */
#define SAM_IRQ_SERCOM0_0 (SAM_IRQ_EXTINT+46) /* 46 SERCOM0: 0 */
#define SAM_IRQ_SERCOM0_1 (SAM_IRQ_EXTINT+47) /* 47 SERCOM0: 1 */
#define SAM_IRQ_SERCOM0_2 (SAM_IRQ_EXTINT+48) /* 48 SERCOM0: 2 */
#define SAM_IRQ_SERCOM0_46 (SAM_IRQ_EXTINT+49) /* 49 SERCOM0: 4-6 */
#define SAM_IRQ_SERCOM1_0 (SAM_IRQ_EXTINT+50) /* 50 SERCOM1: 0 */
#define SAM_IRQ_SERCOM1_1 (SAM_IRQ_EXTINT+51) /* 51 SERCOM1: 1 */
#define SAM_IRQ_SERCOM1_2 (SAM_IRQ_EXTINT+52) /* 52 SERCOM1: 2 */
#define SAM_IRQ_SERCOM1_46 (SAM_IRQ_EXTINT+53) /* 53 SERCOM1: 4-6 */
#define SAM_IRQ_SERCOM2_0 (SAM_IRQ_EXTINT+54) /* 54 SERCOM2: 0 */
#define SAM_IRQ_SERCOM2_1 (SAM_IRQ_EXTINT+55) /* 55 SERCOM2: 1 */
#define SAM_IRQ_SERCOM2_2 (SAM_IRQ_EXTINT+56) /* 56 SERCOM2: 2 */
#define SAM_IRQ_SERCOM2_46 (SAM_IRQ_EXTINT+57) /* 57 SERCOM2: 4-6 */
#define SAM_IRQ_SERCOM3_0 (SAM_IRQ_EXTINT+58) /* 58 SERCOM3: 0 */
#define SAM_IRQ_SERCOM3_1 (SAM_IRQ_EXTINT+59) /* 59 SERCOM3: 1 */
#define SAM_IRQ_SERCOM3_2 (SAM_IRQ_EXTINT+60) /* 60 SERCOM3: 2 */
#define SAM_IRQ_SERCOM3_46 (SAM_IRQ_EXTINT+61) /* 61 SERCOM3: 4-6 */
#define SAM_IRQ_SERCOM4_0 (SAM_IRQ_EXTINT+62) /* 62 SERCOM4: 0 */
#define SAM_IRQ_SERCOM4_1 (SAM_IRQ_EXTINT+63) /* 63 SERCOM4: 1 */
#define SAM_IRQ_SERCOM4_2 (SAM_IRQ_EXTINT+64) /* 64 SERCOM4: 2 */
#define SAM_IRQ_SERCOM4_46 (SAM_IRQ_EXTINT+65) /* 65 SERCOM4: 4-6 */
#define SAM_IRQ_SERCOM5_0 (SAM_IRQ_EXTINT+66) /* 66 SERCOM5: 0 */
#define SAM_IRQ_SERCOM5_1 (SAM_IRQ_EXTINT+67) /* 67 SERCOM5: 1 */
#define SAM_IRQ_SERCOM5_2 (SAM_IRQ_EXTINT+68) /* 68 SERCOM5: 2 */
#define SAM_IRQ_SERCOM5_46 (SAM_IRQ_EXTINT+69) /* 69 SERCOM5: 4-6 */
#define SAM_IRQ_SERCOM6_0 (SAM_IRQ_EXTINT+70) /* 70 SERCOM6: 0 */
#define SAM_IRQ_SERCOM6_1 (SAM_IRQ_EXTINT+71) /* 71 SERCOM6: 1 */
#define SAM_IRQ_SERCOM6_2 (SAM_IRQ_EXTINT+72) /* 72 SERCOM6: 2 */
#define SAM_IRQ_SERCOM6_46 (SAM_IRQ_EXTINT+73) /* 73 SERCOM6: 4-6 */
#define SAM_IRQ_SERCOM7_0 (SAM_IRQ_EXTINT+74) /* 74 SERCOM7: 0 */
#define SAM_IRQ_SERCOM7_1 (SAM_IRQ_EXTINT+75) /* 75 SERCOM7: 1 */
#define SAM_IRQ_SERCOM7_2 (SAM_IRQ_EXTINT+76) /* 76 SERCOM7: 2 */
#define SAM_IRQ_SERCOM7_46 (SAM_IRQ_EXTINT+77) /* 77 SERCOM7: 4-6 */
#define SAM_IRQ_CAN0 (SAM_IRQ_EXTINT+78) /* 78 CAN0: Line0, Line1 */
#define SAM_IRQ_CAN1 (SAM_IRQ_EXTINT+79) /* 79 CAN1: Line0, Line1 */
#define SAM_IRQ_USB (SAM_IRQ_EXTINT+80) /* 80 USB: EORSM, DNRSM, EORST RST,
* LPM DCONN, LPMSUSP DDISC, MSOF,
* RAMACER, RXSTP TXSTP 0-7, STALL0
* STALL 0-7, STALL1 0-7, SUSPEND,
* TRFAIL0 TRFAIL 097, TRFAIL1 PERR
* 0..7, UPRSM, WAKEUP */
#define SAM_IRQ_USBSOF (SAM_IRQ_EXTINT+81) /* 81 USB: SOF HSOF */
#define SAM_IRQ_USBTRCPT0 (SAM_IRQ_EXTINT+82) /* 82 USB: TRCPT0 0..7 */
#define SAM_IRQ_USBTRCPT1 (SAM_IRQ_EXTINT+83) /* 83 USB: TRCPT0 0..7 */
#define SAM_IRQ_GMAL (SAM_IRQ_EXTINT+84) /* 84 GMAC: GMAC, WOL */
#define SAM_IRQ_TCC0 (SAM_IRQ_EXTINT+85) /* 85 TCC0: CNT A, DFS A, ERR A, FAULTA
* A, FAULTB A, FAULT0 A, FAULT1 A,
* OVF, TRG, UFS A */
#define SAM_IRQ_TCC0MC0 (SAM_IRQ_EXTINT+86) /* 86 TCC0: MC 0 */
#define SAM_IRQ_TCC0MC1 (SAM_IRQ_EXTINT+87) /* 87 TCC0: MC 1 */
#define SAM_IRQ_TCC0MC2 (SAM_IRQ_EXTINT+88) /* 88 TCC0: MC 2 */
#define SAM_IRQ_TCC0MC3 (SAM_IRQ_EXTINT+89) /* 89 TCC0: MC 3 */
#define SAM_IRQ_TCC0MC4 (SAM_IRQ_EXTINT+90) /* 90 TCC0: MC 4 */
#define SAM_IRQ_TCC0MC5 (SAM_IRQ_EXTINT+91) /* 91 TCC0: MC 5 */
#define SAM_IRQ_TCC1 (SAM_IRQ_EXTINT+92) /* 92 TCC1: CNT A, DFS A, ERR A, FAULTA
* A, FAULTB A, FAULT0 A, FAULT1 A,
* OVF, TRG, UFS A */
#define SAM_IRQ_TCC1MC0 (SAM_IRQ_EXTINT+93) /* 93 TCC1: MC 0 */
#define SAM_IRQ_TCC1MC1 (SAM_IRQ_EXTINT+94) /* 94 TCC1: MC 1 */
#define SAM_IRQ_TCC1MC2 (SAM_IRQ_EXTINT+95) /* 95 TCC1: MC 2 */
#define SAM_IRQ_TCC1MC3 (SAM_IRQ_EXTINT+96) /* 96 TCC1: MC 3 */
#define SAM_IRQ_TCC2 (SAM_IRQ_EXTINT+97) /* 97 TCC2: CNT A, DFS A, ERR A, FAULTA
* A, FAULTB A, FAULT0 A, FAULT1 A,
* OVF, TRG, UFS A */
#define SAM_IRQ_TCC2MC0 (SAM_IRQ_EXTINT+98) /* 98 TCC2: MC 0 */
#define SAM_IRQ_TCC2MC1 (SAM_IRQ_EXTINT+99) /* 99 TCC2: MC 1 */
#define SAM_IRQ_TCC2MC2 (SAM_IRQ_EXTINT+100) /* 100 TCC2: MC 2 */
#define SAM_IRQ_TCC3 (SAM_IRQ_EXTINT+101) /* 101 TCC3: CNT A, DFS A, ERR A, FAULTA
* A, FAULTB A, FAULT0 A, FAULT1 A,
* OVF, TRG, UFS A */
#define SAM_IRQ_TCC3MC0 (SAM_IRQ_EXTINT+102) /* 102 TCC3: MC 0 */
#define SAM_IRQ_TCC3MC1 (SAM_IRQ_EXTINT+103) /* 103 TCC3: MC 1 */
#define SAM_IRQ_TCC4 (SAM_IRQ_EXTINT+104) /* 104 TCC4: CNT A, DFS A, ERR A, FAULTA
* A, FAULTB A, FAULT0 A, FAULT1 A,
* OVF, TRG, UFS A */
#define SAM_IRQ_TCC4MC0 (SAM_IRQ_EXTINT+105) /* 105 TCC4: MC 0 */
#define SAM_IRQ_TCC4MC1 (SAM_IRQ_EXTINT+106) /* 106 TCC4: MC 1 */
#define SAM_IRQ_TC0 (SAM_IRQ_EXTINT+107) /* 107 TC0: ERR A, MC 0, MC 1, OVF */
#define SAM_IRQ_TC1 (SAM_IRQ_EXTINT+108) /* 108 TC1: ERR A, MC 0, MC 1, OVF */
#define SAM_IRQ_TC2 (SAM_IRQ_EXTINT+109) /* 109 TC2: ERR A, MC 0, MC 1, OVF */
#define SAM_IRQ_TC3 (SAM_IRQ_EXTINT+110) /* 110 TC3: ERR A, MC 0, MC 1, OVF */
#define SAM_IRQ_TC4 (SAM_IRQ_EXTINT+111) /* 111 TC4: ERR A, MC 0, MC 1, OVF */
#define SAM_IRQ_TC5 (SAM_IRQ_EXTINT+112) /* 112 TC5: ERR A, MC 0, MC 1, OVF */
#define SAM_IRQ_TC6 (SAM_IRQ_EXTINT+113) /* 113 TC6: ERR A, MC 0, MC 1, OVF */
#define SAM_IRQ_TC7 (SAM_IRQ_EXTINT+114) /* 114 TC7: ERR A, MC 0, MC 1, OVF */
#define SAM_IRQ_PDEC (SAM_IRQ_EXTINT+115) /* 115 PDEC: DIR A, ERR A, OVF, VLC A */
#define SAM_IRQ_PDECMC0 (SAM_IRQ_EXTINT+116) /* 116 PDEC: MC 0 */
#define SAM_IRQ_PDECMC1 (SAM_IRQ_EXTINT+117) /* 117 PDEC: MC 1 */
#define SAM_IRQ_ADC0 (SAM_IRQ_EXTINT+118) /* 118 ADC0: OVERRUN, WINMON */
#define SAM_IRQ_ADC0RDY (SAM_IRQ_EXTINT+119) /* 119 ADC0: RESRDY */
#define SAM_IRQ_ADC1 (SAM_IRQ_EXTINT+120) /* 120 ADC0: OVERRUN, WINMON */
#define SAM_IRQ_ADC1RDY (SAM_IRQ_EXTINT+121) /* 121 ADC0: RESRDY */
#define SAM_IRQ_AC (SAM_IRQ_EXTINT+122) /* 122 AC: COMP 0, COMP 1, WIN 0 */
#define SAM_IRQ_DACERR (SAM_IRQ_EXTINT+123) /* 123 DAC: OVERRUN A 0, OVERRUN A 1,
* UNDERRUN A 0, UNDERRUN A 1 */
#define SAM_IRQ_DACEMPTY0 (SAM_IRQ_EXTINT+124) /* 124 DAC: EMPTY 0 */
#define SAM_IRQ_DACEMPTY1 (SAM_IRQ_EXTINT+125) /* 125 DAC: EMPTY 1 */
#define SAM_IRQ_DACRDY0 (SAM_IRQ_EXTINT+126) /* 126 DAC: RESRDY 0 */
#define SAM_IRQ_DACRDY1 (SAM_IRQ_EXTINT+127) /* 127 DAC: RESRDY 1 */
#define SAM_IRQ_I2S (SAM_IRQ_EXTINT+128) /* 128 I2S: RXOR 0, RXOR 1, RXRDY 0, RXRDY
* 1, TXRDY 0, TXRDY 1, TXUR 0, TXUR 1 */
#define SAM_IRQ_PCC (SAM_IRQ_EXTINT+129) /* 129 PCC: */
#define SAM_IRQ_AES (SAM_IRQ_EXTINT+130) /* 130 AES: ENCCMP, GFMCMP */
#define SAM_IRQ_TRNG (SAM_IRQ_EXTINT+131) /* 131 TRNG: IS0 */
#define SAM_IRQ_ICM (SAM_IRQ_EXTINT+132) /* 132 ICM: */
#define SAM_IRQ_PUKCC (SAM_IRQ_EXTINT+133) /* 133 PUKCC: */
#define SAM_IRQ_QSPI (SAM_IRQ_EXTINT+134) /* 134 QSPI: */
#define SAM_IRQ_SDHC0 (SAM_IRQ_EXTINT+135) /* 135 SDHC0: SDHC0, TIMER */
#define SAM_IRQ_SDHC1 (SAM_IRQ_EXTINT+136) /* 136 SDHC1: SDHC1, TIMER */
#define SAM_IRQ_NEXTINT 137 /* Total number of external interrupt numbers */
#define NR_IRQS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT) /* The number of vectors */
/************************************************************************************************
* Public Types
************************************************************************************************/
/************************************************************************************************
* Inline functions
************************************************************************************************/
/************************************************************************************************
* Public Data
************************************************************************************************/
/************************************************************************************************
* Public Function Prototypes
************************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAMD5E5_SAM4L_IRQ_H */
arch/arm/src/samd5e5/Kconfig
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arch/arm/src/samd5e5/Make.defs
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############################################################################
# arch/arm/src/samd5e5/Make.defs
#
# Copyright (C) 2018 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
# The start-up, "head", file
HEAD_ASRC =
# Common ARM and Cortex-M4 files
CMN_UASRCS =
CMN_UCSRCS =
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copyfullstate.c
CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c
CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c
CMN_CSRCS += up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c
CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_stackframe.c
CMN_CSRCS += up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c
CMN_CSRCS += up_svcall.c up_vfork.c
# Configuration-dependent common files
ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_ASRCS += up_lazyexception.S
else
CMN_ASRCS += up_exception.S
endif
CMN_CSRCS += up_vectors.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
ifneq ($(CONFIG_DISABLE_SIGNALS),y)
CMN_CSRCS += up_signal_dispatch.c
CMN_UASRCS += up_signal_handler.S
endif
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S
CMN_CSRCS += up_copyarmstate.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c
endif
# Required SAMD5x/E5x files
CHIP_ASRCS =
# REVISIT: sam_clockconfig.c and sam_eic.c
#CHIP_CSRCS = sam_clockconfig.c sam_cmcc.c sam_gclk.c sam_irq.c
CHIP_CSRCS = sam_cmcc.c sam_gclk.c sam_irq.c
CHIP_CSRCS += sam_lowputc.c sam_port.c sam_serial.c sam_start.c
CHIP_CSRCS += sam_supc.c sam_usart.c
# Configuration-dependent SAMD5x/E5x files
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += sam_timerisr.c
endif
ifeq ($(CONFIG_SAMD5E5_TC),y)
CHIP_CSRCS += sam_tc.c
ifeq ($(CONFIG_SAMD5E5_ONESHOT),y)
CHIP_CSRCS += sam_oneshot.c sam_oneshot_lowerhalf.c
endif # CONFIG_SAMD5E5_ONESHOT
ifeq ($(CONFIG_SAMD5E5_FREERUN),y)
CHIP_CSRCS += sam_freerun.c
endif # CONFIG_SAMD5E5_FREERUN
ifeq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += sam_tickless.c
endif # CONFIG_SCHED_TICKLESS
endif # CONFIG_SAMD5E5_TC
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += sam_userspace.c sam_mpuinit.c
endif
ifeq ($(CONFIG_SAMD5E5_EIC),y)
CHIP_CSRCS += sam_eic.c
endif
ifeq ($(CONFIG_SAMD5E5_CMCC),y)
CHIP_CSRCS += sam_cmcc.c
endif
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += sam_idle.c
endif
ifeq ($(CONFIG_SAMD5E5_WDT),y)
CHIP_CSRCS += sam_wdt.c
endif
ifeq ($(CONFIG_SAMD5E5_GMAC),y)
CHIP_CSRCS += sam_gmac.c
endif
ifeq ($(CONFIG_SAMD5E5_USB),y)
CHIP_CSRCS += sam_usb.c
endif
ifeq ($(CONFIG_SAMD5E5_SDHC0),y)
CHIP_CSRCS += sam_sdhc.c
else ifeq ($(CONFIG_SAMD5E5_SDHC1),y)
CHIP_CSRCS += sam_sdhc.c
endif
ifeq ($(CONFIG_SAMD5E5_AES),y)
CHIP_CSRCS += sam_aes.c
endif
ifeq ($(CONFIG_SAMD5E5_RTC),y)
CHIP_CSRCS += sam_rtc.c
endif
arch/arm/src/samd5e5/chip.h
+72
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/************************************************************************************
* arch/arm/src/samd5e5/chip.h
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/* Include the chip interrupt definitions file */
#include <arch/samd5e5/irq.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Provide the required number of peripheral interrupt vector definitions as well.
* The definition SAM_IRQ_NEXTINT simply comes from the chip-specific IRQ header
* file included by arch/sam34/irq.h.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS SAM_IRQ_NEXTINT
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_H */
arch/arm/src/samd5e5/chip/sam_aes.h
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/********************************************************************************************
* arch/arm/src/samd5e5/chip/sam_aes.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_AES_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_AES_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* AES register offsets ********************************************************************/
#define SAM_AES_CTRLA_OFFSET 0x0000 /* Control A Register */
#define SAM_AES_CTRLB_OFFSET 0x0004 /* Control B Register */
#define SAM_AES_INTENCLR_OFFSET 0x0005 /* Interrupt Enable Clear Register */
#define SAM_AES_INTENSET_OFFSET 0x0006 /* Interrupt Enable Set Register */
#define SAM_AES_INTENFLAG_OFFSET 0x0007 /* Interrupt Flag Status and Clear Register */
#define SAM_AES_DATABUFPTR_OFFSET 0x0008 /* Data Buffer Pointer Register */
#define SAM_AES_DBGCTRL_OFFSET 0x0009 /* Debug Register */
#define SAM_AES_KEYWORD_OFFSET(n) (0x000c + ((n) << 2))
# define SAM_AES_KEYWORD0_OFFSET 0x000c /* Keyword 0 Register */
# define SAM_AES_KEYWORD1_OFFSET 0x0010 /* Keyword 1 Register */
# define SAM_AES_KEYWORD2_OFFSET 0x0014 /* Keyword 2 Register */
# define SAM_AES_KEYWORD3_OFFSET 0x0018 /* Keyword 3 Register */
# define SAM_AES_KEYWORD4_OFFSET 0x001c /* Keyword 4 Register */
# define SAM_AES_KEYWORD5_OFFSET 0x0020 /* Keyword 5 Register */
# define SAM_AES_KEYWORD6_OFFSET 0x0024 /* Keyword 6 Register */
# define SAM_AES_KEYWORD7_OFFSET 0x0028 /* Keyword 7 Register */
#define SAM_AES_DATA_OFFSET 0x0038 /* Data Register */
#define SAM_AES_INTVECT_OFFSET(n) (0x003c + ((n) << 2))
# define SAM_AES_INTVECT0_OFFSET 0x003c /* Initialization Vector 0 Register */
# define SAM_AES_INTVECT1_OFFSET 0x0040 /* Initialization Vector 1 Register */
# define SAM_AES_INTVECT2_OFFSET 0x0044 /* Initialization Vector 2 Register */
# define SAM_AES_INTVECT3_OFFSET 0x0048 /* Initialization Vector 3 Register */
#define SAM_AES_HASHKEY_OFFSET(n) (0x005c + ((n) << 2))
# define SAM_AES_HASHKEY0_OFFSET 0x005c /* Hash Key 0 Register */
# define SAM_AES_HASHKEY1_OFFSET 0x0060 /* Hash Key 1 Register */
# define SAM_AES_HASHKEY2_OFFSET 0x0064 /* Hash Key 2 Register */
# define SAM_AES_HASHKEY3_OFFSET 0x0068 /* Hash Key 3 Register */
#define SAM_AES_GHASH_OFFSET(n) (0x006c + ((n) << 2))
# define SAM_AES_GHASH0_OFFSET 0x006c /* Galois Hash 0 Register */
# define SAM_AES_GHASH1_OFFSET 0x0070 /* Galois Hash 1 Register */
# define SAM_AES_GHASH2_OFFSET 0x0074 /* Galois Hash 2 Register */
# define SAM_AES_GHASH3_OFFSET 0x0078 /* Galois Hash 3 Register */
#define SAM_AES_CIPLEN_OFFSET 0x0080 /* Cipher Length Register */
#define SAM_AES_RANDSEED_OFFSET 0x0084 /* Random Seed Register */
/* AES register addresses ******************************************************************/
#define SAM_AES_CTRLA (SAM_AES_BASE+SAM_AES_CTRLA_OFFSET)
#define SAM_AES_CTRLB (SAM_AES_BASE+SAM_AES_CTRLB_OFFSET)
#define SAM_AES_INTENCLR (SAM_AES_BASE+SAM_AES_INTENCLR_OFFSET)
#define SAM_AES_INTENSET (SAM_AES_BASE+SAM_AES_INTENSET_OFFSET)
#define SAM_AES_INTENFLAG (SAM_AES_BASE+SAM_AES_INTENFLAG_OFFSET)
#define SAM_AES_DATABUFPTR (SAM_AES_BASE+SAM_AES_DATABUFPTR_OFFSET)
#define SAM_AES_DBGCTRL (SAM_AES_BASE+SAM_AES_DBGCTRL_OFFSET)
#define SAM_AES_KEYWORD(n) (SAM_AES_BASE+SAM_AES_KEYWORD_OFFSET(n))
# define SAM_AES_KEYWORD0 (SAM_AES_BASE+SAM_AES_KEYWORD0_OFFSET)
# define SAM_AES_KEYWORD1 (SAM_AES_BASE+SAM_AES_KEYWORD1_OFFSET)
# define SAM_AES_KEYWORD2 (SAM_AES_BASE+SAM_AES_KEYWORD2_OFFSET)
# define SAM_AES_KEYWORD3 (SAM_AES_BASE+SAM_AES_KEYWORD3_OFFSET)
# define SAM_AES_KEYWORD4 (SAM_AES_BASE+SAM_AES_KEYWORD4_OFFSET)
# define SAM_AES_KEYWORD5 (SAM_AES_BASE+SAM_AES_KEYWORD5_OFFSET)
# define SAM_AES_KEYWORD6 (SAM_AES_BASE+SAM_AES_KEYWORD6_OFFSET)
# define SAM_AES_KEYWORD7 (SAM_AES_BASE+SAM_AES_KEYWORD7_OFFSET)
#define SAM_AES_DATA (SAM_AES_BASE+SAM_AES_DATA_OFFSET)
#define SAM_AES_INTVECT(n) (SAM_AES_BASE+SAM_AES_INTVECT_OFFSET(n))
# define SAM_AES_INTVECT0 (SAM_AES_BASE+SAM_AES_INTVECT0_OFFSET)
# define SAM_AES_INTVECT1 (SAM_AES_BASE+SAM_AES_INTVECT1_OFFSET)
# define SAM_AES_INTVECT2 (SAM_AES_BASE+SAM_AES_INTVECT2_OFFSET)
# define SAM_AES_INTVECT3 (SAM_AES_BASE+SAM_AES_INTVECT3_OFFSET)
#define SAM_AES_HASHKEY(n) (SAM_AES_BASE+SAM_AES_HASHKEY_OFFSET(n))
# define SAM_AES_HASHKEY0 (SAM_AES_BASE+SAM_AES_HASHKEY0_OFFSET)
# define SAM_AES_HASHKEY1 (SAM_AES_BASE+SAM_AES_HASHKEY1_OFFSET)
# define SAM_AES_HASHKEY2 (SAM_AES_BASE+SAM_AES_HASHKEY2_OFFSET)
# define SAM_AES_HASHKEY3 (SAM_AES_BASE+SAM_AES_HASHKEY3_OFFSET)
#define SAM_AES_GHASH(n) (SAM_AES_BASE+SAM_AES_GHASH_OFFSET(n))
# define SAM_AES_GHASH0 (SAM_AES_BASE+SAM_AES_GHASH0_OFFSET)
# define SAM_AES_GHASH1 (SAM_AES_BASE+SAM_AES_GHASH1_OFFSET)
# define SAM_AES_GHASH2 (SAM_AES_BASE+SAM_AES_GHASH2_OFFSET)
# define SAM_AES_GHASH3 (SAM_AES_BASE+SAM_AES_GHASH3_OFFSET)
#define SAM_AES_CIPLEN (SAM_AES_BASE+SAM_AES_CIPLEN_OFFSET)
#define SAM_AES_RANDSEED (SAM_AES_BASE+SAM_AES_RANDSEED_OFFSET)
/* AES register bit definitions ************************************************************/
/* Control A Register */
#define AES_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
#define AES_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
#define AES_CTRLA_AESMODE_SHIFT (2) /* Bits 2-4: AES mode of operation */
#define AES_CTRLA_AESMODE_MASK (7 << AES_CTRLA_AESMODE_SHIFT)
# define AES_CTRLA_AESMODE_ECB (0 << AES_CTRLA_AESMODE_SHIFT) /* Electronic code book mode */
# define AES_CTRLA_AESMODE_CBC (1 << AES_CTRLA_AESMODE_SHIFT) /* Cipher block chaining mode */
# define AES_CTRLA_AESMODE_OFB (2 << AES_CTRLA_AESMODE_SHIFT) /* Output feedback mode */
# define AES_CTRLA_AESMODE_CFB (3 << AES_CTRLA_AESMODE_SHIFT) /* Cipher feedback mode */
# define AES_CTRLA_AESMODE_CNTR (4 << AES_CTRLA_AESMODE_SHIFT) /* Counter mode */
# define AES_CTRLA_AESMODE_CCM (5 << AES_CTRLA_AESMODE_SHIFT) /* CCM mode */
# define AES_CTRLA_AESMODE_GCM (6 << AES_CTRLA_AESMODE_SHIFT) /* Galois counter mode */
#define AES_CTRLA_CFBS_SHIFT (5) /* Bits 5-7: Cipher feedback block size */
#define AES_CTRLA_CFBS_MASK (7 << AES_CTRLA_CFBS_SHIFT)
# define AES_CTRLA_CFBS_128 (0 << AES_CTRLA_CFBS_SHIFT) /* 128-bit data block */
# define AES_CTRLA_CFBS_64 (1 << AES_CTRLA_CFBS_SHIFT) /* 64-bit data block */
# define AES_CTRLA_CFBS_32 (2 << AES_CTRLA_CFBS_SHIFT) /* 32-bit data block */
# define AES_CTRLA_CFBS_16 (3 << AES_CTRLA_CFBS_SHIFT) /* 16-bit data block */
# define AES_CTRLA_CFBS_8 (4 << AES_CTRLA_CFBS_SHIFT) /* 8-bit data block */
#define AES_CTRLA_KEYSIZE_SHIFT (8) /* Bits 8-9: Encryption key size */
#define AES_CTRLA_KEYSIZE_MASK (3 << AES_CTRLA_KEYSIZE_SHIFT)
# define AES_CTRLA_KEYSIZE_128 (0 << AES_CTRLA_KEYSIZE_SHIFT) /* 128-bit key */
# define AES_CTRLA_KEYSIZE_192 (1 << AES_CTRLA_KEYSIZE_SHIFT) /* 192-bit key */
# define AES_CTRLA_KEYSIZE_256 (2 << AES_CTRLA_KEYSIZE_SHIFT) /* 256-bit key */
#define AES_CTRLA_CIPHER (1 << 10) /* Bit 10: Cipher */
#define AES_CTRLA_STARTMODE (1 << 11) /* Bit 11: Start mode select */
#define AES_CTRLA_LOD (1 << 12) /* Bit 12: Last output data mode */
#define AES_CTRLA_KEYGEN (1 << 13) /* Bit 13: Key generation */
#define AES_CTRLA_XORKEY (1 << 14) /* Bit 14: XOR key */
#define AES_CTRLA_CTYPE_SHIFT (16) /* Bits 16-19: Countermeasure type */
#define AES_CTRLA_CTYPE_MASK (15 << AES_CTRLA_CTYPE_SHIFT)
# define AES_CTRLA_CTYPE1_DISAB (0 << AES_CTRLA_CTYPE_SHIFT) /* Countermeasure 1 disabled */
# define AES_CTRLA_CTYPE1_ENAB (1 << AES_CTRLA_CTYPE_SHIFT) /* Countermeasure 1 enabled */
# define AES_CTRLA_CTYPE2_DISAB (0 << AES_CTRLA_CTYPE_SHIFT) /* Countermeasure 2 disabled */
# define AES_CTRLA_CTYPE2_ENAB (2 << AES_CTRLA_CTYPE_SHIFT) /* Countermeasure 2 enabled */
# define AES_CTRLA_CTYPE3_DISAB (0 << AES_CTRLA_CTYPE_SHIFT) /* Countermeasure 3 disabled */
# define AES_CTRLA_CTYPE3_ENAB (4 << AES_CTRLA_CTYPE_SHIFT) /* Countermeasure 3 enabled */
# define AES_CTRLA_CTYPE4_DISAB (0 << AES_CTRLA_CTYPE_SHIFT) /* Countermeasure 4 disabled */
# define AES_CTRLA_CTYPE4_ENAB (8 << AES_CTRLA_CTYPE_SHIFT) /* Countermeasure 4 enabled */
/* Control B Register */
#define AES_CTRLB_START (1 << 0) /* Bit 0: Start encryption/decryption */
#define AES_CTRLB_NEWMSG (1 << 1) /* Bit 1: New message */
#define AES_CTRLB_EOM (1 << 2) /* Bit 2: End of message */
#define AES_CTRLB_GFMUL (1 << 3) /* Bit 3: GF multiplication */
/* Common Bit Definitions for the Interrupt Enable Clear Register, Interrupt Enable Set
* Register, and Interrupt Flag Status and Clear Register
*/
#define AES_INT_ENCCMP (1 << 0) /* Bit 0: Encryption complete interrupt */
#define AES_INT_GFMCMP (1 << 1) /* Bit 1: GF multiplication complete interrupt */
#define AES_INT_ALL 0x03
/* Data Buffer Pointer Register */
#define AES_DATABUFPTR_MASK 0x03 /* Bits 0-1: Data pointer */
/* Debug Register */
#define AES_DBGCTRL_DBGRUN (1 << 0) /* Bit 0: Debug run */
/* Keyword n Register, n = 0-7 (32-value) */
/* Data Register (32-bit value) */
/* Initialization Vector n Register, n=0-3 (32-bit value) */
/* Hash Key n Register, n=0-3 (32-bit value) */
/* Galois Hash n Register, n=0-3 (32-bit value) */
/* Cipher Length Register (32-bit value) */
/* Random Seed Register (32-bit value) */
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_AES_H */
arch/arm/src/samd5e5/chip/sam_cmcc.h
+196
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/****************************************************************************************
* arch/arm/src/samd5e5/chip/sam_cmcc.h
* Cortex M Cache Controller (CMCC) for the SAMD5/E5
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_CMCC_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_CMCC_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* This information is available in the Cache Type Register. How every, it is more
* efficient if we do not to do the decoding on each cache access.
*
* CacheSize = CacheLineSize * NCacheLines * NWays
* CacheAddressRange = CacheLineSize * NCacheLines = CacheSize / NWays
*/
#define CMCC_CACHE_SIZE 4096 /* 4Kb L1 data/instruction cache */
#define CMCC_CACHE_LINE_SIZE 16 /* 16 byte cache line size */
#define CMCC_NWAYS 4 /* 4 ways */
/* CMCC register offsets ****************************************************************/
#define SAM_CMCC_TYPE_OFFSET 0x0000 /* Cache Type Register */
#define SAM_CMCC_CFG_OFFSET 0x0004 /* Cache Configuration Register */
#define SAM_CMCC_CTRL_OFFSET 0x0008 /* Cache Control Register */
#define SAM_CMCC_SR_OFFSET 0x000c /* Cache Status Register */
#define SAM_CMCC_LCKWAY_OFFSET 0x0010 /* Cache Lock per Way */
/* 0x0014-0x001c Reserved */
#define SAM_CMCC_MAINT0_OFFSET 0x0020 /* Cache Maintenance Register 0 */
#define SAM_CMCC_MAINT1_OFFSET 0x0024 /* Cache Maintenance Register 1 */
#define SAM_CMCC_MCFG_OFFSET 0x0028 /* Cache Monitor Configuration Register */
#define SAM_CMCC_MEN_OFFSET 0x002c /* Cache Monitor Enable Register */
#define SAM_CMCC_MCTRL_OFFSET 0x0030 /* Cache Monitor Control Register */
#define SAM_CMCC_MSR_OFFSET 0x0034 /* Cache Monitor Status Register */
/* 0x0038-0x00fc Reserved */
/* CMCC register addresses **************************************************************/
#define SAM_CMCC_TYPE (SAM_CMCC_BASE + SAM_CMCC_TYPE_OFFSET)
#define SAM_CMCC_CFG (SAM_CMCC_BASE + SAM_CMCC_CFG_OFFSET)
#define SAM_CMCC_CTRL (SAM_CMCC_BASE + SAM_CMCC_CTRL_OFFSET)
#define SAM_CMCC_SR (SAM_CMCC_BASE + SAM_CMCC_SR_OFFSET)
#define SAM_CMCC_MAINT0 (SAM_CMCC_BASE + SAM_CMCC_MAINT0_OFFSET)
#define SAM_CMCC_MAINT1 (SAM_CMCC_BASE + SAM_CMCC_MAINT1_OFFSET)
#define SAM_CMCC_MCFG (SAM_CMCC_BASE + SAM_CMCC_MCFG_OFFSET)
#define SAM_CMCC_MEN (SAM_CMCC_BASE + SAM_CMCC_MEN_OFFSET)
#define SAM_CMCC_MCTRL (SAM_CMCC_BASE + SAM_CMCC_MCTRL_OFFSET)
#define SAM_CMCC_MSR (SAM_CMCC_BASE + SAM_CMCC_MSR_OFFSET)
/* CMCC register bit definitions ********************************************************/
/* Cache Type Register */
#define CMCC_TYPE_AP (1 << 0) /* Bit 0: Access Port Access Allowed */
#define CMCC_TYPE_GCLK (1 << 1) /* Bit 1: Dynamic Clock Gating Supported */
#define CMCC_TYPE_RANDP (1 << 2) /* Bit 2: Random Selection Policy Supported */
#define CMCC_TYPE_LRUP (1 << 3) /* Bit 3: Least Recently Used Policy Supported */
#define CMCC_TYPE_RRP (1 << 4) /* Bit 4: Random Selection Policy Supported */
#define CMCC_TYPE_WAYNUM_SHIFT (5) /* Bits 5-6: Number of Way */
#define CMCC_TYPE_WAYNUM_MASK (3 << CMCC_TYPE_WAYNUM_SHIFT)
# define CMCC_TYPE_WAYNUM_DMAPPED (0 << CMCC_TYPE_WAYNUM_SHIFT) /* Direct Mapped Cache */
# define CMCC_TYPE_WAYNUM_ARCH2WAY (1 << CMCC_TYPE_WAYNUM_SHIFT) /* 2-WAY set associative */
# define CMCC_TYPE_WAYNUM_ARCH4WAY (2 << CMCC_TYPE_WAYNUM_SHIFT) /* 4-WAY set associative */
# define CMCC_TYPE_WAYNUM_ARCH8WAY (3 << CMCC_TYPE_WAYNUM_SHIFT) /* 8-WAY set associative */
#define CMCC_TYPE_LCKDOWN (1 << 7) /* Bit 7: Lock Down Supported */
#define CMCC_TYPE_CSIZE_SHIFT (8) /* Bits 8-10: Cache Size */
#define CMCC_TYPE_CSIZE_MASK (7 << CMCC_TYPE_CSIZE_SHIFT)
# define CMCC_TYPE_CSIZE_1KB (0 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 1 Kbytes */
# define CMCC_TYPE_CSIZE_2KB (1 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 2 Kbytes */
# define CMCC_TYPE_CSIZE_4KB (2 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 4 Kbytes */
# define CMCC_TYPE_CSIZE_8KB (3 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 8 Kbytes */
#define CMCC_TYPE_CLSIZE_SHIFT (11) /* Bits 11-13: Cache Line Size */
#define CMCC_TYPE_CLSIZE_MASK (7 << CMCC_TYPE_CLSIZE_SHIFT)
# define CMCC_TYPE_CLSIZE_4B (0 << CMCC_TYPE_CLSIZE_SHIFT) /* 4 Bytes */
# define CMCC_TYPE_CLSIZE_8B (1 << CMCC_TYPE_CLSIZE_SHIFT) /* 8 Bytes */
# define CMCC_TYPE_CLSIZE_16B (2 << CMCC_TYPE_CLSIZE_SHIFT) /* 16 Bytes */
# define CMCC_TYPE_CLSIZE_32B (3 << CMCC_TYPE_CLSIZE_SHIFT) /* 32 Bytes */
/* Cache Configuration Register */
#define CMCC_CFG_GCLKDIS (1 << 0) /* Bit 0: Disable Clock Gating */
#define CMCC_CFG_ICDIS (1 << 1) /* Bit 1: Instruction Cache Disable */
#define CMCC_CFG_DCDIS (1 << 2) /* Bit 2: Data Cache Disable */
#define CMCC_CFG_CSIZEW_SHIFT (8) /* Bits 4-6: Cache Size Configured by Software */
#define CMCC_CFG_CSIZEW_MASK (7 << CMCC_CFG_CSIZEW_SHIFT)
# define CMCC_CFG_CSIZEW_1KB (0 << CMCC_CFG_CSIZEW_SHIFT) /* Cache Size configured to 1KB */
# define CMCC_CFG_CSIZEW_2KB (1 << CMCC_CFG_CSIZEW_SHIFT) /* Cache Size configured to 2KB */
# define CMCC_CFG_CSIZEW_4KB (2 << CMCC_CFG_CSIZEW_SHIFT) /* Cache Size configured to 4KB */
# define CMCC_CFG_CSIZEW_8KB (3 << CMCC_CFG_CSIZEW_SHIFT) /* Cache Size configured to 8KB */
# define CMCC_CFG_CSIZEW_16KB (4 << CMCC_CFG_CSIZEW_SHIFT) /* Cache Size configured to 16KB */
# define CMCC_CFG_CSIZEW_32KB (5 << CMCC_CFG_CSIZEW_SHIFT) /* Cache Size configured to 32KB */
# define CMCC_CFG_CSIZEW_64KB (6 << CMCC_CFG_CSIZEW_SHIFT) /* Cache Size configured to 64KB */
/* Cache Control Register */
#define CMCC_CTRL_CEN (1 << 0) /* Bit 0: Cache Controller Enable */
/* Cache Status Register */
#define CMCC_SR_CSTS (1 << 0) /* Bit 0: Cache Controller Status */
/* Cache Lock per Way */
#define CMCC_LCKWAY_SHIFT (0) /* Bits 0-3: Lockdown Way Register */
#define CMCC_LCKWAY_MASK (7 << CMCC_LCKWAY_SHIFT)
#define CMCC_LCKWAY(n) ((uint32_t)(n) << CMCC_LCKWAY_SHIFT)
/* Cache Maintenance Register 0 */
#define CMCC_MAINT0_INVALL (1 << 0) /* Bit 0: Cache Controller Invalidate All */
/* Cache Maintenance Register 1 */
#define CMCC_MAINT1_INDEX_SHIFT (4) /* Bits 4-11: Invalidate Index */
#define CMCC_MAINT1_INDEX_MASK (0xff << CMCC_MAINT1_INDEX_SHIFT)
# define CMCC_MAINT1_INDEX(n) ((uint32_t)(n) << CMCC_MAINT1_INDEX_SHIFT)
#define CMCC_MAINT1_WAY_SHIFT (28) /* Bits 28-31: Invalidate Way */
#define CMCC_MAINT1_WAY_MASK (15 << CMCC_MAINT1_WAY_SHIFT)
# define CMCC_MAINT1_WAY(n) ((uint32_t)(n) << CMCC_MAINT1_WAY_SHIFT)
# define CMCC_MAINT1_WAY0 (0 << CMCC_MAINT1_WAY_SHIFT) /* Way 0 selected */
# define CMCC_MAINT1_WAY1 (1 << CMCC_MAINT1_WAY_SHIFT) /* Way 1 selected */
# define CMCC_MAINT1_WAY2 (2 << CMCC_MAINT1_WAY_SHIFT) /* Way 2 selected */
# define CMCC_MAINT1_WAY3 (3 << CMCC_MAINT1_WAY_SHIFT) /* Way 3 selected */
/* Cache Monitor Configuration Register */
#define CMCC_MCFG_MODE_SHIFT (0) /* Bits 0-1: Cache Controller Monitor Counter Mode */
#define CMCC_MCFG_MODE_MASK (3 << CMCC_MCFG_MODE_SHIFT)
# define CMCC_MCFG_MODE_CYCLECOUNT (0 << CMCC_MCFG_MODE_SHIFT) /* Cycle counter */
# define CMCC_MCFG_MODE_IHITCOUNT (1 << CMCC_MCFG_MODE_SHIFT) /* Instruction hit counter */
# define CMCC_MCFG_MODE_DHITCOUNT (2 << CMCC_MCFG_MODE_SHIFT) /* Data hit counter */
/* Cache Monitor Enable Register */
#define CMCC_MEN_MENABLE (1 << 0) /* Bit 0: Cache Controller Monitor Enable */
/* Cache Monitor Control Register */
#define CMCC_MCTRL_SWRST (1 << 0) /* Bit 0: Monitor */
/* Cache Monitor Status Register -- 32-bit event count */
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_CMCC_H */
arch/arm/src/samd5e5/chip/sam_eic.h
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/********************************************************************************************
* arch/arm/src/samd5e5/chip/sam_eic.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_EIC_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_EIC_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* EIC register offsets *********************************************************************/
#define SAM_EIC_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_EIC_NMITRCL_OFFSET 0x0001 /* Non-maskable interrupt control register */
#define SAM_EIC_NMIFLAG_OFFSET 0x0002 /* Non-maskable interrupt flasg status and clear register */
#define SAM_EIC_SYNCBUSY_OFFSET 0x0004 /* Synchronization busy register */
#define SAM_EIC_EVCTRL_OFFSET 0x0008 /* Event control register */
#define SAM_EIC_INTENCLR_OFFSET 0x000c /* Interrupt enable clear register */
#define SAM_EIC_INTENSET_OFFSET 0x0010 /* Interrupt enable set register */
#define SAM_EIC_INTFLAG_OFFSET 0x0014 /* Interrupt flag and status clear register */
#define SAM_EIC_ASYNCH_OFFSET 0x0018 /* External interrupt asynchronous mode register */
#define SAM_EIC_CONFIG0_OFFSET 0x001c /* Configuration 0 register */
#define SAM_EIC_CONFIG1_OFFSET 0x0020 /* Configuration 1 register */
#define SAM_EIC_DEBOUNCEN_OFFSET 0x0030 /* Debouncer enable */
#define SAM_EIC_DPRESCALER_OFFSET 0x0034 /* Debouncer prescaler */
#define SAM_EIC_PINSTATE_OFFSET 0x0038 /* Pin state */
/* EIC register addresses *******************************************************************/
#define SAM_EIC_CTRLA (SAM_EIC_BASE + SAM_EIC_CTRLA_OFFSET)
#define SAM_EIC_NMITRCL (SAM_EIC_BASE + SAM_EIC_NMITRCL_OFFSET)
#define SAM_EIC_NMIFLAG (SAM_EIC_BASE + SAM_EIC_NMIFLAG_OFFSET)
#define SAM_EIC_SYNCBUSY (SAM_EIC_BASE + SAM_EIC_SYNCBUSY_OFFSET)
#define SAM_EIC_EVCTRL (SAM_EIC_BASE + SAM_EIC_EVCTRL_OFFSET)
#define SAM_EIC_INTENCLR (SAM_EIC_BASE + SAM_EIC_INTENCLR_OFFSET)
#define SAM_EIC_INTENSET (SAM_EIC_BASE + SAM_EIC_INTENSET_OFFSET)
#define SAM_EIC_INTFLAG (SAM_EIC_BASE + SAM_EIC_INTFLAG_OFFSET)
#define SAM_EIC_ASYNCH (SAM_EIC_BASE + SAM_EIC_ASYNCH_OFFSET)
#define SAM_EIC_CONFIG0 (SAM_EIC_BASE + SAM_EIC_CONFIG0_OFFSET)
#define SAM_EIC_CONFIG1 (SAM_EIC_BASE + SAM_EIC_CONFIG1_OFFSET)
#define SAM_EIC_DEBOUNCEN (SAM_EIC_BASE + SAM_EIC_DEBOUNCEN_OFFSET)
#define SAM_EIC_DPRESCALER (SAM_EIC_BASE + SAM_EIC_DPRESCALER_OFFSET)
#define SAM_EIC_PINSTATE (SAM_EIC_BASE + SAM_EIC_PINSTATE_OFFSET)
/* EIC register bit definitions *************************************************************/
/* Control A register */
#define EIC_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
#define EIC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
#define EIC_CTRLA_CKSEL (1 << 4) /* Bit 4: Clock selection */
# define EIC_CTRLA_CKSEL_GCLK_EIC (0) /* 0=EIC clocked by GCLK_EIC */
# define EIC_CTRLA_CKSEL_CLK_ULP32K EIC_CTRLA_CKSEL /* 1=EIC clocked by CLK_ULP32K */
/* Non-maskable interrupt control register */
#define EIC_NMITRCL_NMISENSE_SHIFT (0) /* Bits 0-2: Non-maskable interrupt sense */
#define EIC_NMITRCL_NMISENSE_MASK (7 << EIC_NMITRCL_NMISENSE_SHIFT)
# define EIC_NMITRCL_NMISENSE_NONE (0 << EIC_NMITRCL_NMISENSE_SHIFT) /* No detection */
# define EIC_NMITRCL_NMISENSE_RISE (1 << EIC_NMITRCL_NMISENSE_SHIFT) /* Rising edge detection */
# define EIC_NMITRCL_NMISENSE_FALL (2 << EIC_NMITRCL_NMISENSE_SHIFT) /* Falling edge detection */
# define EIC_NMITRCL_NMISENSE_BOTH (3 << EIC_NMITRCL_NMISENSE_SHIFT) /* Both edge detection */
# define EIC_NMITRCL_NMISENSE_HIGH (4 << EIC_NMITRCL_NMISENSE_SHIFT) /* High level detection */
# define EIC_NMITRCL_NMISENSE_LOW (5 << EIC_NMITRCL_NMISENSE_SHIFT) /* Low level detection */
#define EIC_NMITRCL_NMIFLTEN (1 << 3) /* Bit 3: Non-maskable interrupt filter enable */
#define EIC_NMITRCL_ASYNC (1 << 4) /* Bit 4: Asynchronous edge detection mode */
/* Non-maskable interrupt flas status and clear register */
#define EIC_NMIFLAG_NMI (1 << 0) /* Non-maskable interrupt */
/* Synchronization busy register */
#define EIC_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset syncrhonization busy */
#define EIC_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: Enable synchronization busy */
/* Event control, Interrupt enable clear, interrupt enable set register, interrupt flag
* status and clear, and External interrupt asynchronous mode registers.
*/
#define EIC_EXTINT_SHIFT (0) /* Bits 0-15: External interrupt n */
#define EIC_EXTINT_MASK (0xffff << EIC_EXTINT_SHIFT)
# define EIC_EXTINT(n) (1 << (n))
# define EIC_EXTINT_0 (1 << 0) /* Bit 0: External interrupt 0 */
# define EIC_EXTINT_1 (1 << 1) /* Bit 1: External interrupt 1 */
# define EIC_EXTINT_2 (1 << 2) /* Bit 2: External interrupt 2 */
# define EIC_EXTINT_3 (1 << 3) /* Bit 3: External interrupt 3 */
# define EIC_EXTINT_4 (1 << 4) /* Bit 4: External interrupt 4 */
# define EIC_EXTINT_5 (1 << 5) /* Bit 5: External interrupt 5 */
# define EIC_EXTINT_6 (1 << 6) /* Bit 6: External interrupt 6 */
# define EIC_EXTINT_7 (1 << 7) /* Bit 7: External interrupt 7 */
# define EIC_EXTINT_8 (1 << 8) /* Bit 8: External interrupt 8 */
# define EIC_EXTINT_9 (1 << 9) /* Bit 9: External interrupt 9 */
# define EIC_EXTINT_10 (1 << 10) /* Bit 10: External interrupt 10 */
# define EIC_EXTINT_11 (1 << 11) /* Bit 11: External interrupt 11 */
# define EIC_EXTINT_12 (1 << 12) /* Bit 12: External interrupt 12 */
# define EIC_EXTINT_13 (1 << 13) /* Bit 13: External interrupt 13 */
# define EIC_EXTINT_14 (1 << 14) /* Bit 14: External interrupt 14 */
# define EIC_EXTINT_15 (1 << 15) /* Bit 15: External interrupt 15 */
#define EIC_EXTINT_ALL EIC_EXTINT_MASK
/* Configuration 0 register */
#define EIC_CONFIG0_FILTEN(n) (3 + ((n) << 2)) /* Filter n enable, n=0-7 */
#define EIC_CONFIG0_SENSE_SHIFT(n) ((n) << 2) /* Filter n input sense, n=0-7 */
#define EIC_CONFIG0_SENSE_MASK(n) (7 << EIC_CONFIG0_SENSE_SHIFT(n))
# define EIC_CONFIG0_SENSE_NONE (0 << EIC_CONFIG0_SENSE_SHIFT(n)) /* No detection */
# define EIC_CONFIG0_SENSE_RISE (1 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Rising edge detection */
# define EIC_CONFIG0_SENSE_FALL (2 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Falling edge detection */
# define EIC_CONFIG0_SENSE_BOTH (3 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Both edge detection */
# define EIC_CONFIG0_SENSE_HIGH (4 << EIC_CONFIG0_SENSE_SHIFT(n)) /* High level detection */
# define EIC_CONFIG0_SENSE_LOW (5 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Low level detection */
/* Configuration 1 register */
#define EIC_CONFIG1_FILTEN(n) (3 + (((n) - 8) << 2)) /* Filter n enable, n=8-15 */
#define EIC_CONFIG1_SENSE_SHIFT(n) (((n) - 8) << 2) /* Filter n input sense, n=8-17 */
#define EIC_CONFIG1_SENSE_MASK(n) (7 << EIC_CONFIG1_SENSE_SHIFT(n))
# define EIC_CONFIG1_SENSE_NONE(n) (0 << EIC_CONFIG1_SENSE_SHIFT(n)) /* No detection */
# define EIC_CONFIG1_SENSE_RISE(n) (1 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Rising edge detection */
# define EIC_CONFIG1_SENSE_FALL(n) (2 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Falling edge detection */
# define EIC_CONFIG1_SENSE_BOTH(n) (3 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Both edge detection */
# define EIC_CONFIG1_SENSE_HIGH(n) (4 << EIC_CONFIG1_SENSE_SHIFT(n)) /* High level detection */
# define EIC_CONFIG1_SENSE_LOW(n) (5 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Low level detection */
/* Debouncer enable */
#define EIC_DEBOUNCEN_SHIFT (0) /* Bits 0-15: EXTINT n Debouncer enable */
#define EIC_DEBOUNCEN_MASK (0xffff << EIC_DEBOUNCEN_SHIFT)
# define EIC_DEBOUNCEN(n) (1 << (n))
# define EIC_DEBOUNCEN_0 (1 << 0) /* Bit 0: EXTINT 0 edge input is debounced */
# define EIC_DEBOUNCEN_1 (1 << 1) /* Bit 1: EXTINT 1 edge input is debounced */
# define EIC_DEBOUNCEN_2 (1 << 2) /* Bit 2: EXTINT 2 edge input is debounced */
# define EIC_DEBOUNCEN_3 (1 << 3) /* Bit 3: EXTINT 3 edge input is debounced */
# define EIC_DEBOUNCEN_4 (1 << 4) /* Bit 4: EXTINT 4 edge input is debounced */
# define EIC_DEBOUNCEN_5 (1 << 5) /* Bit 5: EXTINT 5 edge input is debounced */
# define EIC_DEBOUNCEN_6 (1 << 6) /* Bit 6: EXTINT 6 edge input is debounced */
# define EIC_DEBOUNCEN_7 (1 << 7) /* Bit 7: EXTINT 7 edge input is debounced */
# define EIC_DEBOUNCEN_8 (1 << 8) /* Bit 8: EXTINT 8 edge input is debounced */
# define EIC_DEBOUNCEN_9 (1 << 9) /* Bit 9: EXTINT 9 edge input is debounced */
# define EIC_DEBOUNCEN_10 (1 << 10) /* Bit 10: EXTINT 10 edge input is debounced */
# define EIC_DEBOUNCEN_11 (1 << 11) /* Bit 11: EXTINT 11 edge input is debounced */
# define EIC_DEBOUNCEN_12 (1 << 12) /* Bit 12: EXTINT 12 edge input is debounced */
# define EIC_DEBOUNCEN_13 (1 << 13) /* Bit 13: EXTINT 13 edge input is debounced */
# define EIC_DEBOUNCEN_14 (1 << 14) /* Bit 14: EXTINT 14 edge input is debounced */
# define EIC_DEBOUNCEN_15 (1 << 15) /* Bit 15: EXTINT 15 edge input is debounced */
/* Debouncer prescaler */
#define EIC_DPRESCALER_PRESCALER0_SHIFT (0) /* Bitx 0-2: Debouncer Prescaler. EXTINT 0-7 */
#define EIC_DPRESCALER_PRESCALER0_MASK (7 << EIC_DPRESCALER_PRESCALER0_SHIFT)
# define EIC_DPRESCALER_PRESCALER0_DIV2 (0 << EIC_DPRESCALER_PRESCALER0_SHIFT) /* EIC clock divided by 2 */
# define EIC_DPRESCALER_PRESCALER0_DIV4 (1 << EIC_DPRESCALER_PRESCALER0_SHIFT) /* EIC clock divided by 4 */
# define EIC_DPRESCALER_PRESCALER0_DIV8 (2 << EIC_DPRESCALER_PRESCALER0_SHIFT) /* EIC clock divided by 8 */
# define EIC_DPRESCALER_PRESCALER0_DIV16 (3 << EIC_DPRESCALER_PRESCALER0_SHIFT) /* EIC clock divided by 16 */
# define EIC_DPRESCALER_PRESCALER0_DIV32 (4 << EIC_DPRESCALER_PRESCALER0_SHIFT) /* EIC clock divided by 32 */
# define EIC_DPRESCALER_PRESCALER0_DIV64 (5 << EIC_DPRESCALER_PRESCALER0_SHIFT) /* EIC clock divided by 64 */
# define EIC_DPRESCALER_PRESCALER0_DIV128 (6 << EIC_DPRESCALER_PRESCALER0_SHIFT) /* EIC clock divided by 128 */
# define EIC_DPRESCALER_PRESCALER0_DIV256 (7 << EIC_DPRESCALER_PRESCALER0_SHIFT) /* EIC clock divided by 256 */
#define EIC_DPRESCALER_STATES0 (1 << 3) /* Bit 3: Debouncer number of states. EXTINT 0-7 */
# define EIC_DPRESCALER_STATES0_3 (0) /* 3 low frequency samples */
# define EIC_DPRESCALER_STATES0_7 EIC_DPRESCALER_STATES0 /* 7 low frequency samples */
#define EIC_DPRESCALER_PRESCALER1_SHIFT (4) /* Bitx 4-6: Debouncer Prescaler. EXTINT 8-15 */
#define EIC_DPRESCALER_PRESCALER1_MASK (7 << EIC_DPRESCALER_PRESCALER1_SHIFT)
# define EIC_DPRESCALER_PRESCALER1_DIV2 (0 << EIC_DPRESCALER_PRESCALER1_SHIFT) /* EIC clock divided by 2 */
# define EIC_DPRESCALER_PRESCALER1_DIV4 (1 << EIC_DPRESCALER_PRESCALER1_SHIFT) /* EIC clock divided by 4 */
# define EIC_DPRESCALER_PRESCALER1_DIV8 (2 << EIC_DPRESCALER_PRESCALER1_SHIFT) /* EIC clock divided by 8 */
# define EIC_DPRESCALER_PRESCALER1_DIV16 (3 << EIC_DPRESCALER_PRESCALER1_SHIFT) /* EIC clock divided by 16 */
# define EIC_DPRESCALER_PRESCALER1_DIV32 (4 << EIC_DPRESCALER_PRESCALER1_SHIFT) /* EIC clock divided by 32 */
# define EIC_DPRESCALER_PRESCALER1_DIV64 (5 << EIC_DPRESCALER_PRESCALER1_SHIFT) /* EIC clock divided by 64 */
# define EIC_DPRESCALER_PRESCALER1_DIV128 (6 << EIC_DPRESCALER_PRESCALER1_SHIFT) /* EIC clock divided by 128 */
# define EIC_DPRESCALER_PRESCALER1_DIV256 (7 << EIC_DPRESCALER_PRESCALER1_SHIFT) /* EIC clock divided by 256 */
#define EIC_DPRESCALER_STATES1 (1 << 7) /* Bit 7: Debouncer number of states. EXTINT 8-15 */
# define EIC_DPRESCALER_STATES1_3 (0) /* 3 low frequency samples */
# define EIC_DPRESCALER_STATES1_7 EIC_DPRESCALER_STATES1 /* 7 low frequency samples */
#define EIC_DPRESCALER_TICKON (1 << 16) /* Bit 16: Pin Sampler frequency selection */
# define EIC_DPRESCALER_TICKON_GCLKEIC (0) /* Bounce sampler uses GCLK_EIC */
# define EIC_DPRESCALER_TICKON_LFCLK EIC_DPRESCALER_TICKON /* Bounce sampler uses low frequency clock */
/* Pin state */
#define EIC_PINSTATE_SHIFT (0) /* Bits 0-15: EXTINT n Debouncer enable */
#define EIC_PINSTATE_MASK (0xffff << EIC_PINSTATE_SHIFT)
# define EIC_PINSTATE(n) (1 << (n))
# define EIC_PINSTATE_0 (1 << 0) /* Bit 0: EXTINT 0 pin state */
# define EIC_PINSTATE_1 (1 << 1) /* Bit 1: EXTINT 1 pin state */
# define EIC_PINSTATE_2 (1 << 2) /* Bit 2: EXTINT 2 pin state */
# define EIC_PINSTATE_3 (1 << 3) /* Bit 3: EXTINT 3 pin state */
# define EIC_PINSTATE_4 (1 << 4) /* Bit 4: EXTINT 4 pin state */
# define EIC_PINSTATE_5 (1 << 5) /* Bit 5: EXTINT 5 pin state */
# define EIC_PINSTATE_6 (1 << 6) /* Bit 6: EXTINT 6 pin state */
# define EIC_PINSTATE_7 (1 << 7) /* Bit 7: EXTINT 7 pin state */
# define EIC_PINSTATE_8 (1 << 8) /* Bit 8: EXTINT 8 pin state */
# define EIC_PINSTATE_9 (1 << 9) /* Bit 9: EXTINT 9 pin state */
# define EIC_PINSTATE_10 (1 << 10) /* Bit 10: EXTINT 10 pin state */
# define EIC_PINSTATE_11 (1 << 11) /* Bit 11: EXTINT 11 pin state */
# define EIC_PINSTATE_12 (1 << 12) /* Bit 12: EXTINT 12 pin state */
# define EIC_PINSTATE_13 (1 << 13) /* Bit 13: EXTINT 13 pin state */
# define EIC_PINSTATE_14 (1 << 14) /* Bit 14: EXTINT 14 pin state */
# define EIC_PINSTATE_15 (1 << 15) /* Bit 15: EXTINT 15 pin state */
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_EIC_H */
arch/arm/src/samd5e5/chip/sam_evsys.h
+369
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@@ -0,0 +1,369 @@
/********************************************************************************************
* arch/arm/src/samd5e5/chip/sam_evsys.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_EVSYS_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_EVSYS_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
#define SAM_EVSYS_NCHANNELS 32 /* 0-31 */
#define SAM_EVSYS_NUSER 67 /* 0-66 */
/* EVSYS register offsets *******************************************************************/
#define SAM_EVSYS_CTRLA_OFFSET 0x0000 /* Control register */
#define SAM_EVSYS_SWEVT_OFFSET 0x0004 /* Software event register */
#define SAM_EVSYS_PRICTRL_OFFSET 0x0008 /* Software event register */
#define SAM_EVSYS_INTPEND_OFFSET 0x0010 /* Channel pending interrupt register */
#define SAM_EVSYS_INTSTATUS_OFFSET 0x0014 /* Channel pending interrupt register */
#define SAM_EVSYS_BUSYCH_OFFSET 0x0018 /* Busy channels register */
#define SAM_EVSYS_READYUSR_OFFSET 0x001c /* Busy channels register */
#define SAM_EVSYS_CHOFFSET(n) (0x0020 + ((n) << 3)) /* Channel registers */
# define SAM_EVSYS_CHANNEL_OFFSET 0x0000 /* Channel control register */
# define SAM_EVSYS_CHINTENCLR_OFFSET 0x0004 /* Channl interrupt clear register */
# define SAM_EVSYS_CHINTENSET_OFFSET 0x0005 /* Channel interrupt enable register */
# define SAM_EVSYS_CHINTFLAG_OFFSET 0x0006 /* Channel interrupt status register */
# define SAM_EVSYS_CHSTATUS_OFFSET 0x0007 /* Channel status register */
#define SAM_EVSYS_USER_OFFSET(n) (0x0120 + ((m)) /* User registers */
/* EVSYS register addresses *****************************************************************/
#define SAM_EVSYS_CTRLA (SAM_EVSYS_BASE + SAM_EVSYS_CTRLA_OFFSET)
#define SAM_EVSYS_SWEVT (SAM_EVSYS_BASE + SAM_EVSYS_SWEVT_OFFSET)
#define SAM_EVSYS_PRICTRL (SAM_EVSYS_BASE + SAM_EVSYS_PRICTRL_OFFSET)
#define SAM_EVSYS_INTPEND (SAM_EVSYS_BASE + SAM_EVSYS_INTPEND_OFFSET)
#define SAM_EVSYS_INTSTATUS (SAM_EVSYS_BASE + SAM_EVSYS_INTSTATUS_OFFSET)
#define SAM_EVSYS_BUSYCH (SAM_EVSYS_BASE + SAM_EVSYS_BUSYCH_OFFSET)
#define SAM_EVSYS_READYUSR (SAM_EVSYS_BASE + SAM_EVSYS_READYUSR_OFFSET)
#define SAM_EVSYS_CHBASEBASE(n) (SAM_EVSYS_BASE + SAM_EVSYS_CHOFFSET(n))
# define SAM_EVSYS_CHANNEL(n) (SAM_EVSYS_CHBASEBASE(n) + SAM_EVSYS_CHANNEL_OFFSET)
# define SAM_EVSYS_CHINTENCLR(n) (SAM_EVSYS_CHBASEBASE(n) + SAM_EVSYS_CHINTENCLR_OFFSET)
# define SAM_EVSYS_CHINTENSET(n) (SAM_EVSYS_CHBASEBASE(n) + SAM_EVSYS_CHINTENSET_OFFSET)
# define SAM_EVSYS_CHINTFLAG(n) (SAM_EVSYS_CHBASEBASE(n) + SAM_EVSYS_CHINTFLAG_OFFSET)
# define SAM_EVSYS_CHSTATUS(n) (SAM_EVSYS_CHBASEBASE(n) + SAM_EVSYS_CHSTATUS_OFFSET
#define SAM_EVSYS_USER(n) (SAM_EVSYS_BASE + SAM_EVSYS_USER_OFFSET(n))
/* EVSYS register bit definitions ***********************************************************/
/* Control register */
#define EVSYS_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
/* Software event register */
#define EVSYS_SWEVT_CHAN(n) (1 << (n)) /* Bit n: Channel n software selection */
/* Software event register */
#define EVSYS_PRICTRL_PRI_SHIFT (0) /* Bist 0-4: Channel priority number */
#define EVSYS_PRICTRL_PRI_MASK (31 << EVSYS_PRICTRL_PRI_SHIFT)
# define EVSYS_PRICTRL_PRI(n) ((uint8_t)(n) << EVSYS_PRICTRL_PRI_SHIFT)
#define EVSYS_PRICTRL_RREN (1 << 7) /* Bit 7: Round-robin scheduling enable */
/* Channel pending interrupt register */
#define EVSYS_INTPEND_ID_SHIFT (0) /* Bits 0-4: Channel ID */
#define EVSYS_INTPEND_ID_MASK (31 << EVSYS_INTPEND_ID_SHIFT)
# define EVSYS_INTPEND_ID(n) ((uint16_t)(n) << EVSYS_INTPEND_ID_SHIFT)
#define EVSYS_INTPEND_OVR (1 << 8) /* Bit 8: Channel Overrun */
#define EVSYS_INTPEND_EVD (1 << 9) /* Bit 9: Channel Event Detected */
#define EVSYS_INTPEND_READY (1 << 14) /* Bit 14: Ready */
#define EVSYS_INTPEND_BUSY (1 << 15) /* Bit 15: Busy */
/* Channel pending interrupt register */
#define EVSYS_INTSTATUS_CHAN(n) (1 << (n)) /* Bit n: Channel n pending interrupt */
/* Busy channels register */
#define EVSYS_BUSYCH_CHAN(n) (1 << (n)) /* Bit n: Busy channel n */
/* Busy channels register */
#define EVSYS_READYUSR_CHAN(n) (1 << (n)) /* Bit n: Ready user for channel n */
/* Channel control register (see event generator selections below) */
#define EVSYS_CHANNEL_EVGEN_SHIFT (0) /* Bits 0-7: Event generator selection */
#define EVSYS_CHANNEL_EVGEN_MASK (0xff << EVSYS_CHANNEL_EVGEN_SHIFT)
# define EVSYS_CHANNEL_EVGEN(n) ((uint32_t)(n) << EVSYS_CHANNEL_EVGEN_SHIFT)
#define EVSYS_CHANNEL_PATH_SHIFT (8) /* Bits 8-9: Path Selection */
#define EVSYS_CHANNEL_PATH_MASK (3 << EVSYS_CHANNEL_PATH_SHIFT)
# define EVSYS_CHANNEL_PATH_SYNCH (0 << EVSYS_CHANNEL_PATH_SHIFT) /* Synchronous path */
# define EVSYS_CHANNEL_PATH_RESYNCH (1 << EVSYS_CHANNEL_PATH_SHIFT) /* Resynchronized path */
# define EVSYS_CHANNEL_PATH_ASYNCH (2 << EVSYS_CHANNEL_PATH_SHIFT) /* Asynchronous path */
#define EVSYS_CHANNEL_EDGSEL_SHIFT (10) /* Bits 10-11: Edge detection selection */
#define EVSYS_CHANNEL_EDGSEL_MASK (3 << EVSYS_CHANNEL_EDGSEL_SHIFT)
# define EVSYS_CHANNEL_EDGSEL_NONE (0 << EVSYS_CHANNEL_EDGSEL_SHIFT) /* No event output */
# define EVSYS_CHANNEL_EDGSEL_ RISING (1 << EVSYS_CHANNEL_EDGSEL_SHIFT) /* Event on rising edge */
# define EVSYS_CHANNEL_EDGSEL_FALLING (2 << EVSYS_CHANNEL_EDGSEL_SHIFT) /* Event on falling edge */
# define EVSYS_CHANNEL_EDGSEL_BOTH (3 << EVSYS_CHANNEL_EDGSEL_SHIFT) /* Event on both edges */
#define EVSYS_CHANNEL_RUNSTDBY (1 << 14) /* Bit 14: Run in standby */
#define EVSYS_CHANNEL_ONDEMAND (1 << 15) /* Bit 15: Generic clock on demand */
/* Channel interrupt clear register, Channel interrupt enable register, and Channel interrupt
* status register
*/
#define EVSYS_CHINT_OVR (1 << 0) /* Bit 0: Channel overrun */
#define EVSYS_CHINT_EVD (1 << 1) /* Bit 1: Channel event detected */
/* Channel status register */
#define EVSYS_CHSTATUS_RDYUSR (1 << 0) /* Bit 0: Ready user */
#define EVSYS_CHSTATUS_BUSYCH (1 << 1) /* Bit 1: Busy channel */
/* User registers (8-bit channel number. See user multiplexor numbers below */
/* Event generator channel event selection **************************************************/
#define EVSYS_EVENT_NONE 0x00 /* No event generator selected */
#define EVSYS_EVENT_OSCCTRL_XOSC_FAIL0 0x01 /* XOSC fail detection 0 */
#define EVSYS_EVENT_OSCCTRL_XOSC_FAIL1 0x02 /* XOSC fail detection 1 */
#define EVSYS_EVENT_OSC32KCTRL_XOSC32K_FAIL 0x03 /* XOSC32K fail detection */
#define EVSYS_EVENT_RTC_PER0 0x04 /* RTC period 0 */
#define EVSYS_EVENT_RTC_PER1 0x05 /* RTC period 1 */
#define EVSYS_EVENT_RTC_PER2 0x06 /* RTC period 2 */
#define EVSYS_EVENT_RTC_PER3 0x07 /* RTC period 3 */
#define EVSYS_EVENT_RTC_PER4 0x08 /* RTC period 4 */
#define EVSYS_EVENT_RTC_PER5 0x09 /* RTC period 5 */
#define EVSYS_EVENT_RTC_PER6 0x0a /* RTC period 6 */
#define EVSYS_EVENT_RTC_PER7 0x0b /* RTC period 7 */
#define EVSYS_EVENT_RTC_CMP0 0x0c /* RTC comparison 0 */
#define EVSYS_EVENT_RTC_CMP1 0x0d /* RTC comparison 0 */
#define EVSYS_EVENT_RTC_CMP2 0x0e /* RTC comparison 0 */
#define EVSYS_EVENT_RTC_CMP3 0x0f /* RTC comparison 0 */
#define EVSYS_EVENT_RTC_TAMPER 0x10 /* RTC tamper detection */
#define EVSYS_EVENT_RTC_OVF 0x11 /* RTC overflow */
#define EVSYS_EVENT_EIC_EXTINT0 0x12 /* EIC external interrupt 0 */
#define EVSYS_EVENT_EIC_EXTINT1 0x13 /* EIC external interrupt 1 */
#define EVSYS_EVENT_EIC_EXTINT2 0x14 /* EIC external interrupt 2 */
#define EVSYS_EVENT_EIC_EXTINT3 0x15 /* EIC external interrupt 3 */
#define EVSYS_EVENT_EIC_EXTINT4 0x16 /* EIC external interrupt 4 */
#define EVSYS_EVENT_EIC_EXTINT5 0x17 /* EIC external interrupt 5 */
#define EVSYS_EVENT_EIC_EXTINT6 0x18 /* EIC external interrupt 6 */
#define EVSYS_EVENT_EIC_EXTINT7 0x19 /* EIC external interrupt 7 */
#define EVSYS_EVENT_EIC_EXTINT8 0x1a /* EIC external interrupt 8 */
#define EVSYS_EVENT_EIC_EXTINT9 0x1b /* EIC external interrupt 9 */
#define EVSYS_EVENT_EIC_EXTINT10 0x1c /* EIC external interrupt 10 */
#define EVSYS_EVENT_EIC_EXTINT11 0x1d /* EIC external interrupt 11 */
#define EVSYS_EVENT_EIC_EXTINT12 0x1e /* EIC external interrupt 12 */
#define EVSYS_EVENT_EIC_EXTINT13 0x1f /* EIC external interrupt 13 */
#define EVSYS_EVENT_EIC_EXTINT14 0x20 /* EIC external interrupt 14 */
#define EVSYS_EVENT_EIC_EXTINT15 0x21 /* EIC external interrupt 15 */
#define EVSYS_EVENT_DMAC_CH0 0x22 /* DMA channel 0 */
#define EVSYS_EVENT_DMAC_CH1 0x23 /* DMA channel 0 */
#define EVSYS_EVENT_DMAC_CH2 0x24 /* DMA channel 0 */
#define EVSYS_EVENT_DMAC_CH3 0x25 /* DMA channel 0 */
#define EVSYS_EVENT_PAC_ACCERR 0x26 /* PAC Acc. error */
#define EVSYS_EVENT_TCC0_OVF 0x29 /* TCC0 Overflow */
#define EVSYS_EVENT_TCC0_TRG 0x2a /* TCC0 Trigger Event */
#define EVSYS_EVENT_TCC0_CNT 0x2b /* TCC0 Counter */
#define EVSYS_EVENT_TCC0_MC0 0x2c /* TCC0 Match/Compare 0 */
#define EVSYS_EVENT_TCC0_MC1 0x2d /* TCC0 Match/Compare 1 */
#define EVSYS_EVENT_TCC0_MC2 0x2e /* TCC0 Match/Compare 2 */
#define EVSYS_EVENT_TCC0_MC3 0x2f /* TCC0 Match/Compare 3 */
#define EVSYS_EVENT_TCC0_MC4 0x30 /* TCC0 Match/Compare 4 */
#define EVSYS_EVENT_TCC0_MC5 0x31 /* TCC0 Match/Compare 5 */
#define EVSYS_EVENT_TCC1_OVF 0x32 /* TCC1 Overflow */
#define EVSYS_EVENT_TCC1_TRG 0x33 /* TCC1 Trigger Event */
#define EVSYS_EVENT_TCC1_CNT 0x34 /* TCC1 Counter */
#define EVSYS_EVENT_TCC1_MC0 0x35 /* TCC1 Match/Compare 0 */
#define EVSYS_EVENT_TCC1_MC1 0x36 /* TCC1 Match/Compare 1 */
#define EVSYS_EVENT_TCC1_MC2 0x37 /* TCC1 Match/Compare 2 */
#define EVSYS_EVENT_TCC1_MC3 0x38 /* TCC1 Match/Compare 3 */
#define EVSYS_EVENT_TCC2_OVF 0x39 /* TCC2 Overflow */
#define EVSYS_EVENT_TCC2 0x3a /* TCC2_TRG Trigger Event */
#define EVSYS_EVENT_TCC2_CNT 0x3b /* TCC2 Counter */
#define EVSYS_EVENT_TCC2_MC0 0x3c /* TCC2 Match/Compare 0 */
#define EVSYS_EVENT_TCC2_MC1 0x3d /* TCC2 Match/Compare 1 */
#define EVSYS_EVENT_TCC2_MC2 0x3e /* TCC2 Match/Compare 2 */
#define EVSYS_EVENT_TCC3_OVF 0x3f /* TCC3 Overflow */
#define EVSYS_EVENT_TCC3_TRG 0x40 /* TCC3 Trigger Event */
#define EVSYS_EVENT_TCC3_CNT 0x41 /* TCC3 Counter */
#define EVSYS_EVENT_TCC3_MC0 0x42 /* TCC3 Match/Compare 0 */
#define EVSYS_EVENT_TCC3_MC1 0x43 /* TCC3 Match/Compare 1 */
#define EVSYS_EVENT_TCC4_OVF 0x44 /* TCC4 Overflow */
#define EVSYS_EVENT_TCC4_TRG 0x45 /* TCC4 Trigger Event */
#define EVSYS_EVENT_TCC4_CNT 0x46 /* TCC4 Counter */
#define EVSYS_EVENT_TCC4_MC0 0x47 /* TCC4 Match/Compare 0 */
#define EVSYS_EVENT_TCC4_MC1 0x48 /* TCC4 Match/Compare 1 */
#define EVSYS_EVENT_TC0_OVF 0x49 /* TC0 Overflow */
#define EVSYS_EVENT_TC0_MC0 0x4a /* TC0 Match/Compare 0 */
#define EVSYS_EVENT_TC0_MC1 0x4b /* TC0 Match/Compare 1 */
#define EVSYS_EVENT_TC1_OVF 0x4c /* TC1 Overflow */
#define EVSYS_EVENT_TC1_MC0 0x4d /* TC1 Match/Compare 0 */
#define EVSYS_EVENT_TC1_MC1 0x4e /* TC1 Match/Compare 1 */
#define EVSYS_EVENT_TC2_OVF 0x4f /* TC2 Overflow */
#define EVSYS_EVENT_TC2_MC0 0x50 /* TC2 Match/Compare 0 */
#define EVSYS_EVENT_TC2_MC1 0x51 /* TC2 Match/Compare 1 */
#define EVSYS_EVENT_TC3_OVF 0x52 /* TC3 Overflow */
#define EVSYS_EVENT_TC3_MC0 0x53 /* TC3 Match/Compare 0 */
#define EVSYS_EVENT_TC3_MC1 0x54 /* TC3 Match/Compare 1 */
#define EVSYS_EVENT_TC4_OVF 0x55 /* TC4 Overflow */
#define EVSYS_EVENT_TC4_MC0 0x56 /* TC4 Match/Compare 0 */
#define EVSYS_EVENT_TC4_MC1 0x57 /* TC4 Match/Compare 1 */
#define EVSYS_EVENT_TC5_OVF 0x58 /* TC5 Overflow */
#define EVSYS_EVENT_TC5_MC0 0x59 /* TC5 Match/Compare 0 */
#define EVSYS_EVENT_TC5_MC1 0x5a /* TC5 Match/Compare 1 */
#define EVSYS_EVENT_TC6_OVF 0x5b /* TC6 Overflow */
#define EVSYS_EVENT_TC6_MC0 0x5c /* TC6 Match/Compare 0 */
#define EVSYS_EVENT_TC6_MC1 0x5d /* TC6 Match/Compare 1 */
#define EVSYS_EVENT_TC7_OVF 0x5e /* TC7 Overflow */
#define EVSYS_EVENT_TC7_MC0 0x5f /* TC7 Match/Compare 0 */
#define EVSYS_EVENT_TC7_MC1 0x60 /* TC7 Match/Compare 1 */
#define EVSYS_EVENT_PDEC_OVF 0x61 /* PDEC Overflow */
#define EVSYS_EVENT_PDEC_ERR 0x62 /* PDEC Error */
#define EVSYS_EVENT_PDEC_DIR 0x63 /* PDEC Direction */
#define EVSYS_EVENT_PDEC_VLC 0x64 /* PDEC VLC */
#define EVSYS_EVENT_PDEC_MC0 0x65 /* PDEC MC0 */
#define EVSYS_EVENT_PDEC_MC1 0x66 /* PDEC MC1 */
#define EVSYS_EVENT_ADC0_RESRDY 0x67 /* ADC0 RESRDY */
#define EVSYS_EVENT_ADC0_WINMON 0x68 /* ADC0 Window Monitor */
#define EVSYS_EVENT_ADC1_RESRDY 0x69 /* ADC1 RESRDY */
#define EVSYS_EVENT_ADC1_WINMON 0x6a /* ADC1 Window Monitor */
#define EVSYS_EVENT_AC_COMP0 0x6b /* AC Comparator 0 */
#define EVSYS_EVENT_AC_COMP1 0x6c /* AC Comparator 1 */
#define EVSYS_EVENT_AC_WIN 0x6d /* AC0 Window */
#define EVSYS_EVENT_DAC_EMPTY0 0x6e /* DAC empty 0 */
#define EVSYS_EVENT_DAC_EMPTY1 0x6f /* DAC empty 1 */
#define EVSYS_EVENT_DAC_RESRDY0 0x70 /* DAC RSRDY 0 */
#define EVSYS_EVENT_DAC_RESRDY1 0x71 /* DAC RSRDY 1 */
#define EVSYS_EVENT_GMAC_TSU_CMP 0x72 /* GMAC Timestamp CMP */
#define EVSYS_EVENT_TRNG_READY 0x73 /* TRNG ready */
#define EVSYS_EVENT_CCL_LUTOUT0 0x74 /* CCL LUTOUT 0 */
#define EVSYS_EVENT_CCL_LUTOUT1 0x75 /* CCL LUTOUT 1 */
#define EVSYS_EVENT_CCL_LUTOUT2 0x76 /* CCL LUTOUT 2 */
#define EVSYS_EVENT_CCL_LUTOUT3 0x77 /* CCL LUTOUT 3 */
/* User multiplexer numbers ****************************************************************/
/* These are indices that may be used with the SAM_EVSYS_USER(n) macro to get the address of
* the correct user register.
*/
#define EVSYS_USER_RTC_TAMPER 0 /* RTC Tamper A */
#define EVSYS_USER_PORT_EV0 1 /* Port 0 event */
#define EVSYS_USER_PORT_EV1 2 /* Port 1 event */
#define EVSYS_USER_PORT_EV2 3 /* Port 2 event */
#define EVSYS_USER_PORT_EV3 4 /* Port 3 event */
#define EVSYS_USER_DMAC_CH0 5 /* DMA channel 0 event */
#define EVSYS_USER_DMAC_CH1 6 /* DMA channel 1 event */
#define EVSYS_USER_DMAC_CH2 7 /* DMA channel 2 event */
#define EVSYS_USER_DMAC_CH3 8 /* DMA channel 3 event */
#define EVSYS_USER_DMAC_CH4 9 /* DMA channel 4 event */
#define EVSYS_USER_DMAC_CH5 10 /* DMA channel 5 event */
#define EVSYS_USER_DMAC_CH6 11 /* DMA channel 6 event */
#define EVSYS_USER_DMAC_CH7 12 /* DMA channel 7 event */
#define EVSYS_USER_CM4_TRACE_START 14 /* CM4 trace start */
#define EVSYS_USER_CM4_TRACE_STOP 15 /* CM4 trace stop */
#define EVSYS_USER_CM4_TRACE_TRIG 16 /* CM4 trace trigger */
#define EVSYS_USER_TCC0_EV0 17 /* TCC0 EV0 */
#define EVSYS_USER_TCC0_EV1 18 /* TCC0 EV1 */
#define EVSYS_USER_TCC0_MC0 19 /* TCC0 MC0 */
#define EVSYS_USER_TCC0_MC1 20 /* TCC0 MC1 */
#define EVSYS_USER_TCC0_MC2 21 /* TCC0 MC2 */
#define EVSYS_USER_TCC0_MC3 22 /* TCC0 MC3 */
#define EVSYS_USER_TCC0_MC4 23 /* TCC0 MC4 */
#define EVSYS_USER_TCC0_MC5 24 /* TCC0 MC5 */
#define EVSYS_USER_TCC1_EV0 25 /* TCC1 EV0 */
#define EVSYS_USER_TCC1_EV1 26 /* TCC1 EV1 */
#define EVSYS_USER_TCC1_MC0 27 /* TCC1 MC0 */
#define EVSYS_USER_TCC1_MC1 28 /* TCC1 MC1 */
#define EVSYS_USER_TCC1_MC2 29 /* TCC1 MC2 */
#define EVSYS_USER_TCC1_MC3 30 /* TCC1 MC3 */
#define EVSYS_USER_TCC2_EV0 31 /* TCC2 EV0 */
#define EVSYS_USER_TCC2_EV1 32 /* TCC2 EV1 */
#define EVSYS_USER_TCC2_MC0 33 /* TCC2 MC0 */
#define EVSYS_USER_TCC2_MC1 34 /* TCC2 MC1 */
#define EVSYS_USER_TCC2_MC2 35 /* TCC2 MC2 */
#define EVSYS_USER_TCC3_EV0 36 /* TCC3 EV0 */
#define EVSYS_USER_TCC3_EV1 37 /* TCC3 EV1 */
#define EVSYS_USER_TCC3_MC0 38 /* TCC3 MC0 */
#define EVSYS_USER_TCC3_MC1 39 /* TCC3 MC1 */
#define EVSYS_USER_TCC4_EV0 40 /* TCC4 EV0 */
#define EVSYS_USER_TCC4_EV1 41 /* TCC4 EV1 */
#define EVSYS_USER_TCC4_MC0 42 /* TCC4 MC0 */
#define EVSYS_USER_TCC4_MC1 43 /* TCC4 MC1 */
#define EVSYS_USER_TC0_EVU 44 /* TC0 EVU */
#define EVSYS_USER_TC1_EVU 45 /* TC1 EVU */
#define EVSYS_USER_TC2_EVU 46 /* TC2 EVU */
#define EVSYS_USER_TC3_EVU 47 /* TC3 EVU */
#define EVSYS_USER_TC4_EVU 48 /* TC4 EVU */
#define EVSYS_USER_TC5_EVU 49 /* TC5 EVU */
#define EVSYS_USER_TC6_EVU 50 /* TC6 EVU */
#define EVSYS_USER_TC7_EVU 51 /* TC7 EVU */
#define EVSYS_USER_PDEC_EVU0 52 /* PDEC EVU 0 */
#define EVSYS_USER_PDEC_EVU1 53 /* PDEC EVU 1 */
#define EVSYS_USER_PDEC_EVU2 54 /* PDEC EVU 2 */
#define EVSYS_USER_ADC0_START 55 /* ADC0 start conversion */
#define EVSYS_USER_ADC0_SYNC 56 /* SYNC Flush ADC0 */
#define EVSYS_USER_ADC1_START 57 /* ADC1 start conversion */
#define EVSYS_USER_ADC1_SYNC 58 /* SYNC Flush ADC1 */
#define EVSYS_USER_AC_SOC0 59 /* AC SOC 0 */
#define EVSYS_USER_AC_SOC1 60 /* AC SOC 1 */
#define EVSYS_USER_DAC_START0 61 /* DAC0 start conversion */
#define EVSYS_USER_DAC_START1 62 /* DAC1 start conversion */
#define EVSYS_USER_CCL_LUTIN0 63 /* CCL input 0 */
#define EVSYS_USER_CCL_LUTIN1 64 /* CCL input 1 */
#define EVSYS_USER_CCL_LUTIN2 65 /* CCL input 2 */
#define EVSYS_USER_CCL_LUTIN3 66 /* CCL input 3 */
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_EVSYS_H */
arch/arm/src/samd5e5/chip/sam_gclk.h
+217
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@@ -0,0 +1,217 @@
/********************************************************************************************
* arch/arm/src/samd5e5/chip/sam_gclk.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_GCLK_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_GCLK_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* GCLK register offsets ********************************************************************/
#define SAM_GCLK_CTRLA_OFFSET 0x0000 /* Control register */
#define SAM_GCLK_SYNCHBUSY_OFFSET 0x0004 /* Status register */
#define SAM_GCLK_GENCTRL_OFFSET(n) (0x0020 + ((n) << 2)) /* General clock generator n */
#define SAM_GCLK_PCHCTRL_OFFSET(m) (0x0080 + ((m) << 2)) /* Peripheral channel control m */
/* GCLK register addresses ******************************************************************/
#define SAM_GCLK_CTRLA (SAM_GCLK_BASE + SAM_GCLK_CTRLA_OFFSET)
#define SAM_GCLK_SYNCHBUSY (SAM_GCLK_BASE + SAM_GCLK_SYNCHBUSY_OFFSET)
#define SAM_GCLK_GENCTRL(n) (SAM_GCLK_BASE + SAM_GCLK_GENCTRL_OFFSET(n))
#define SAM_GCLK_PCHCTRL(m) (SAM_GCLK_BASE + SAM_GCLK_PCHCTRL_OFFSET(m))
/* GCLK register bit definitions ************************************************************/
/* Control register */
#define GCLK_CTRLA_SWRST (1 << 0) /* Bit 0: Software Reset */
/* Status register */
#define GCLK_SYNCHBUSY_SWRST (1 << 0) /* Bit 0: SWRST synchronization busy */
#define GCLK_SYNCHBUSY_GENCTRL(n) (1 << ((n) + 2)) /* Bit n+2: Generator control n busy */
# define GCLK_SYNCHBUSY_GENCTRL0 (1 << 2) /* Bit 2: Generator control 0 busy */
# define GCLK_SYNCHBUSY_GENCTRL1 (1 << 3) /* Bit 3: Generator control 1 busy */
# define GCLK_SYNCHBUSY_GENCTRL2 (1 << 4) /* Bit 4: Generator control 2 busy */
# define GCLK_SYNCHBUSY_GENCTRL3 (1 << 5) /* Bit 5: Generator control 3 busy */
# define GCLK_SYNCHBUSY_GENCTRL4 (1 << 6) /* Bit 6: Generator control 4 busy */
# define GCLK_SYNCHBUSY_GENCTRL5 (1 << 7) /* Bit 7: Generator control 5 busy */
# define GCLK_SYNCHBUSY_GENCTRL6 (1 << 8) /* Bit 8: Generator control 6 busy */
# define GCLK_SYNCHBUSY_GENCTRL7 (1 << 9) /* Bit 9: Generator control 7 busy */
# define GCLK_SYNCHBUSY_GENCTRL8 (1 << 10) /* Bit 10: Generator control 8 busy */
# define GCLK_SYNCHBUSY_GENCTRL9 (1 << 11) /* Bit 11: Generator control 9 busy */
# define GCLK_SYNCHBUSY_GENCTRL10 (1 << 12) /* Bit 12: Generator control 10 busy */
/* General clock generator n */
#define GCLK_GENCTRL_SRC_SHIFT (0) /* Bits 0-4: Generator source selection */
#define GCLK_GENCTRL_SRC_MASK (31 << GCLK_GENCTRL_SRC_SHIFT)
# define GCLK_GENCTRL_SRC_XOSC0 (0 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC 0 oscillator input */
# define GCLK_GENCTRL_SRC_XOSC1 (1 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC 1 oscillator input */
# define GCLK_GENCTRL_SRC_GCLK_IN (2 << GCLK_GENCTRL_SRC_SHIFT) /* Generator input pad */
# define GCLK_GENCTRL_SRC_GLCK_GEN1 (3 << GCLK_GENCTRL_SRC_SHIFT) /* Generic clock generater 1 output */
# define GCLK_GENCTRL_SRC_OSCULP32K (4 << GCLK_GENCTRL_SRC_SHIFT) /* OSCULP32K oscillator output */
# define GCLK_GENCTRL_SRC_XOSC32K (5 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC32K oscillator output */
# define GCLK_GENCTRL_SRC_DFLL (6 << GCLK_GENCTRL_SRC_SHIFT) /* DFLL oscillator output */
# define GCLK_GENCTRL_SRC_DPLL0 (7 << GCLK_GENCTRL_SRC_SHIFT) /* DPLL0 output */
# define GCLK_GENCTRL_SRC_DPLL1 (8 << GCLK_GENCTRL_SRC_SHIFT) /* DPLL1 output */
#define GCLK_GENCTRL_GENEN (1 << 8) /* Bit 8: Generator enable */
#define GCLK_GENCTRL_IDC (1 << 9) /* Bit 9: Improve duty cycle */
#define GCLK_GENCTRL_OOV (1 << 10) /* Bit 10: Clock output selection */
#define GCLK_GENCTRL_OE (1 << 11) /* Bit 11: Clock output enable */
#define GCLK_GENCTRL_DIVSEL (1 << 12) /* Bit 12: Clock source divider */
#define GCLK_GENCTRL_RUNSTDBY (1 << 13) /* Bit 13: Run in standby */
#define GCLK_GENCTRL_DIV_SHIFT (16) /* Bits 16-31: Generator 0,2-11 Division factor */
#define GCLK_GENCTRL_DIV_MASK (0xff << GCLK_GENCTRL_DIV_SHIFT)
# define GCLK_GENCTRL_DIV(n) ((uint32_t)(n) << GCLK_GENCTRL_DIV_SHIFT)
#define GCLK_GENCTRL1_DIV_SHIFT (16) /* Bits 16-23: Generator 1 Division factor **/
#define GCLK_GENCTRL1_DIV_MASK (0xffff << GCLK_GENCTRL1_DIV_SHIFT)
# define GCLK_GENCTRL1_DIV(n) ((uint32_t)(n) << GCLK_GENCTRL1_DIV_SHIFT)
/* Peripheral channel control m */
#define GCLK_PCHCTRL_GEN_SHIFT (0) /* Bits 0-3: Generator selection */
#define GCLK_PCHCTRL_GEN_MASK (15 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN(n) ((uint32_t)(n) << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN0 (0 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN1 (1 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN2 (2 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN3 (3 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN4 (4 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN5 (5 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN6 (6 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN7 (7 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN8 (8 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN9 (9 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN10 (10 << GCLK_PCHCTRL_GEN_SHIFT)
# define GCLK_PCHCTRL_GEN11 (11 << GCLK_PCHCTRL_GEN_SHIFT)
#define GCLK_PCHCTRL_CHEN (1 << 6) /* Bit 6: Channel enable */
#define GCLK_PCHCTRL_WRTLOCK (1 << 7) /* Bit 7: Write lock */
/* PCHCTRL channel mapping ******************************************************************/
#define GCLK_CHAN_OSCCTRL_DFLL48 0 /* DFLL48 input clock source */
#define GCLK_CHAN_OSCCTRL_FDPLL0 1 /* Reference clock for FDPLL0 */
#define GCLK_CHAN_OSCCTRL_FDPLL1 2 /* Reference clock for FDPLL1 */
#define GCLK_CHAN_OSCCTRL_FDPLL0_32K 3 /* FDPLL0 32KHz clock for internal lock timer */
#define GCLK_CHAN_OSCCTRL_FDPLL1_32K 3 /* FDPLL1 32KHz clock for internal lock timer */
#define GCLK_CHAN_SDHCn_SLOW 3 /* SDHC0-1 Slow */
#define GCLK_CHAN_SDHC0_SLOW 3 /* SDHC0 Slow */
#define GCLK_CHAN_SDHC1_SLOW 3 /* SDHC1 Slow */
#define GCLK_CHAN_SERCOMn_SLOW 3 /* SERCOM0=7 Slow */
#define GCLK_CHAN_SERCOM0_SLOW 3 /* SERCOM0 Slow */
#define GCLK_CHAN_SERCOM1_SLOW 3 /* SERCOM1 Slow */
#define GCLK_CHAN_SERCOM2_SLOW 3 /* SERCOM2 Slow */
#define GCLK_CHAN_SERCOM3_SLOW 3 /* SERCOM3 Slow */
#define GCLK_CHAN_SERCOM4_SLOW 3 /* SERCOM4 Slow */
#define GCLK_CHAN_SERCOM5_SLOW 3 /* SERCOM5 Slow */
#define GCLK_CHAN_SERCOM6_SLOW 3 /* SERCOM6 Slow */
#define GCLK_CHAN_SERCOM7_SLOW 3 /* SERCOM7 Slow */
#define GCLK_CHAN_EIC 4 /* EIC */
#define GCLK_CHAN_FREQM_MSR 5 /* FREQM Measure */
#define GCLK_CHAN_FREQM_REF 6 /* FREQM Reference */
#define GCLK_CHAN_SERCOM0_CORE 7 /* SERCOM0 Core */
#define GCLK_CHAN_SERCOM1_CORE 8 /* SERCOM1 Core */
#define GCLK_CHAN_TCn 9 /* TC0-1 */
#define GCLK_CHAN_TC0 9 /* TC0 */
#define GCLK_CHAN_TC1 9 /* TC1 */
#define GCLK_CHAN_USB 10 /* USB */
#define GCLK_CHAN_EVSYS0 11 /* EVSYS0 */
#define GCLK_CHAN_EVSYS1 12 /* EVSYS1 */
#define GCLK_CHAN_EVSYS2 13 /* EVSYS2 */
#define GCLK_CHAN_EVSYS3 14 /* EVSYS3 */
#define GCLK_CHAN_EVSYS4 15 /* EVSYS4 */
#define GCLK_CHAN_EVSYS5 16 /* EVSYS5 */
#define GCLK_CHAN_EVSYS6 17 /* EVSYS6 */
#define GCLK_CHAN_EVSYS7 18 /* EVSYS7 */
#define GCLK_CHAN_EVSYS8 19 /* EVSYS8 */
#define GCLK_CHAN_EVSYS9 20 /* EVSYS9 */
#define GCLK_CHAN_EVSYS10 21 /* EVSYS10 */
#define GCLK_CHAN_EVSYS11 22 /* EVSYS11 */
#define GCLK_CHAN_SERCOM2_CORE 23 /* SERCOM2 Core */
#define GCLK_CHAN_SERCOM3_CORE 24 /* SERCOM3 Core */
#define GCLK_CHAN_TCC0 25 /* TCC0 */
#define GCLK_CHAN_TCC1 25 /* TCC1 */
#define GCLK_CHAN_TC2 26 /* TC2 */
#define GCLK_CHAN_TC3 26 /* TC3 */
#define GCLK_CHAN_CAN0 27 /* CAN0 */
#define GCLK_CHAN_CAN1 28 /* CAN1 */
#define GCLK_CHAN_TCC2 29 /* TCC2 */
#define GCLK_CHAN_TCC3 29 /* TCC3 */
#define GCLK_CHAN_TC4 30 /* TC4 */
#define GCLK_CHAN_TC5 30 /* TC5 */
#define GCLK_CHAN_PDEC 31 /* PDEC */
#define GCLK_CHAN_AC 32 /* AC */
#define GCLK_CHAN_CCL 33 /* CCL */
#define GCLK_CHAN_SERCOM4_CORE 34 /* SERCOM4 Core */
#define GCLK_CHAN_SERCOM5_CORE 35 /* SERCOM5 Core */
#define GCLK_CHAN_SERCOM6_CORE 36 /* SERCOM6 Core */
#define GCLK_CHAN_SERCOM7_CORE 37 /* SERCOM7 Core */
#define GCLK_CHAN_TCC4 38 /* TCC4 */
#define GCLK_CHAN_TC6 39 /* TC6 */
#define GCLK_CHAN_TC7 39 /* TC7 */
#define GCLK_CHAN_ADC0 40 /* ADC0 */
#define GCLK_CHAN_ADC1 41 /* ADC1 */
#define GCLK_CHAN_DAC 42 /* DAC */
#define GCLK_CHAN_I2S_1 43 /* I2S */
#define GCLK_CHAN_I2S_2 44 /* I2S */
#define GCLK_CHAN_SDHC0 45 /* SDHC0 */
#define GCLK_CHAN_SDHC1 46 /* SDHC1 */
#define GCLK_CHAN_CM4_TRACE 47 /* CM4 Trace */
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_GCLK_H */
arch/arm/src/samd5e5/chip/sam_i2c_master.h
+307
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@@ -0,0 +1,307 @@
/********************************************************************************************
* arch/arm/src/samd5e5/chip/sam_i2c_master.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_I2C_MASTER_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_I2C_MASTER_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* I2C register offsets *********************************************************************/
#define SAM_I2C_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_I2C_CTRLB_OFFSET 0x0004 /* Control B register */
#define SAM_I2C_CTRLC_OFFSET 0x0004 /* Control C register */
#define SAM_I2C_BAUD_OFFSET 0x000c /* Baud register */
#define SAM_I2C_INTENCLR_OFFSET 0x0014 /* Interrupt enable clear register */
#define SAM_I2C_INTENSET_OFFSET 0x0016 /* Interrupt enable set register */
#define SAM_I2C_INTFLAG_OFFSET 0x0018 /* Interrupt flag and status clear register */
#define SAM_I2C_STATUS_OFFSET 0x001a /* Status register */
#define SAM_I2C_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */
#define SAM_I2C_ADDR_OFFSET 0x0024 /* Address register */
#define SAM_I2C_DATA_OFFSET 0x0028 /* Data register */
#define SAM_I2C_DBGCTRL_OFFSET 0x0030 /* Debug control register */
/* I2C register addresses *******************************************************************/
#define SAM_I2C0_CTRLA (SAM_SERCOM0_BASE + SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C0_CTRLB (SAM_SERCOM0_BASE + SAM_I2C_CTRLB_OFFSET)
#define SAM_I20C_CTRLC (SAM_SERCOM0_BASE + SAM_I2C_CTRLC_OFFSET)
#define SAM_I2C0_BAUD (SAM_SERCOM0_BASE + SAM_I2C_BAUD_OFFSET)
#define SAM_I2C0_INTENCLR (SAM_SERCOM0_BASE + SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C0_INTENSET (SAM_SERCOM0_BASE + SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C0_INTFLAG (SAM_SERCOM0_BASE + SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C0_STATUS (SAM_SERCOM0_BASE + SAM_I2C_STATUS_OFFSET)
#define SAM_I2C0_SYNCBUSY (SAM_SERCOM0_BASE + SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C0_ADDR (SAM_SERCOM0_BASE + SAM_I2C_ADDR_OFFSET)
#define SAM_I2C0_DATA (SAM_SERCOM0_BASE + SAM_I2C_DATA_OFFSET)
#define SAM_I2C0_DBGCTRL (SAM_SERCOM0_BASE + SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C1_CTRLA (SAM_SERCOM1_BASE + SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C1_CTRLB (SAM_SERCOM1_BASE + SAM_I2C_CTRLB_OFFSET)
#define SAM_I21C_CTRLC (SAM_SERCOM1_BASE + SAM_I2C_CTRLC_OFFSET)
#define SAM_I2C1_BAUD (SAM_SERCOM1_BASE + SAM_I2C_BAUD_OFFSET)
#define SAM_I2C1_INTENCLR (SAM_SERCOM1_BASE + SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C1_INTENSET (SAM_SERCOM1_BASE + SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C1_INTFLAG (SAM_SERCOM1_BASE + SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C1_STATUS (SAM_SERCOM1_BASE + SAM_I2C_STATUS_OFFSET)
#define SAM_I2C1_SYNCBUSY (SAM_SERCOM1_BASE + SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C1_ADDR (SAM_SERCOM1_BASE + SAM_I2C_ADDR_OFFSET)
#define SAM_I2C1_DATA (SAM_SERCOM1_BASE + SAM_I2C_DATA_OFFSET)
#define SAM_I2C1_DBGCTRL (SAM_SERCOM1_BASE + SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C2_CTRLA (SAM_SERCOM2_BASE + SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C2_CTRLB (SAM_SERCOM2_BASE + SAM_I2C_CTRLB_OFFSET)
#define SAM_I22C_CTRLC (SAM_SERCOM2_BASE + SAM_I2C_CTRLC_OFFSET)
#define SAM_I2C2_BAUD (SAM_SERCOM2_BASE + SAM_I2C_BAUD_OFFSET)
#define SAM_I2C2_INTENCLR (SAM_SERCOM2_BASE + SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C2_INTENSET (SAM_SERCOM2_BASE + SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C2_INTFLAG (SAM_SERCOM2_BASE + SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C2_STATUS (SAM_SERCOM2_BASE + SAM_I2C_STATUS_OFFSET)
#define SAM_I2C2_SYNCBUSY (SAM_SERCOM2_BASE + SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C2_ADDR (SAM_SERCOM2_BASE + SAM_I2C_ADDR_OFFSET)
#define SAM_I2C2_DATA (SAM_SERCOM2_BASE + SAM_I2C_DATA_OFFSET)
#define SAM_I2C2_DBGCTRL (SAM_SERCOM2_BASE + SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C3_CTRLA (SAM_SERCOM3_BASE + SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C3_CTRLB (SAM_SERCOM3_BASE + SAM_I2C_CTRLB_OFFSET)
#define SAM_I23C_CTRLC (SAM_SERCOM3_BASE + SAM_I2C_CTRLC_OFFSET)
#define SAM_I2C3_BAUD (SAM_SERCOM3_BASE + SAM_I2C_BAUD_OFFSET)
#define SAM_I2C3_INTENCLR (SAM_SERCOM3_BASE + SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C3_INTENSET (SAM_SERCOM3_BASE + SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C3_INTFLAG (SAM_SERCOM3_BASE + SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C3_STATUS (SAM_SERCOM3_BASE + SAM_I2C_STATUS_OFFSET)
#define SAM_I2C3_SYNCBUSY (SAM_SERCOM3_BASE + SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C3_ADDR (SAM_SERCOM3_BASE + SAM_I2C_ADDR_OFFSET)
#define SAM_I2C3_DATA (SAM_SERCOM3_BASE + SAM_I2C_DATA_OFFSET)
#define SAM_I2C3_DBGCTRL (SAM_SERCOM3_BASE + SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C4_CTRLA (SAM_SERCOM4_BASE + SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C4_CTRLB (SAM_SERCOM4_BASE + SAM_I2C_CTRLB_OFFSET)
#define SAM_I24C_CTRLC (SAM_SERCOM4_BASE + SAM_I2C_CTRLC_OFFSET)
#define SAM_I2C4_BAUD (SAM_SERCOM4_BASE + SAM_I2C_BAUD_OFFSET)
#define SAM_I2C4_INTENCLR (SAM_SERCOM4_BASE + SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C4_INTENSET (SAM_SERCOM4_BASE + SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C4_INTFLAG (SAM_SERCOM4_BASE + SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C4_STATUS (SAM_SERCOM4_BASE + SAM_I2C_STATUS_OFFSET)
#define SAM_I2C4_SYNCBUSY (SAM_SERCOM4_BASE + SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C4_ADDR (SAM_SERCOM4_BASE + SAM_I2C_ADDR_OFFSET)
#define SAM_I2C4_DATA (SAM_SERCOM4_BASE + SAM_I2C_DATA_OFFSET)
#define SAM_I2C4_DBGCTRL (SAM_SERCOM4_BASE + SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C5_CTRLA (SAM_SERCOM5_BASE + SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C5_CTRLB (SAM_SERCOM5_BASE + SAM_I2C_CTRLB_OFFSET)
#define SAM_I25C_CTRLC (SAM_SERCOM5_BASE + SAM_I2C_CTRLC_OFFSET)
#define SAM_I2C5_BAUD (SAM_SERCOM5_BASE + SAM_I2C_BAUD_OFFSET)
#define SAM_I2C5_INTENCLR (SAM_SERCOM5_BASE + SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C5_INTENSET (SAM_SERCOM5_BASE + SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C5_INTFLAG (SAM_SERCOM5_BASE + SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C5_STATUS (SAM_SERCOM5_BASE + SAM_I2C_STATUS_OFFSET)
#define SAM_I2C5_SYNCBUSY (SAM_SERCOM5_BASE + SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C5_ADDR (SAM_SERCOM5_BASE + SAM_I2C_ADDR_OFFSET)
#define SAM_I2C5_DATA (SAM_SERCOM5_BASE + SAM_I2C_DATA_OFFSET)
#define SAM_I2C5_DBGCTRL (SAM_SERCOM5_BASE + SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C6_CTRLA (SAM_SERCOM6_BASE + SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C6_CTRLB (SAM_SERCOM6_BASE + SAM_I2C_CTRLB_OFFSET)
#define SAM_I26C_CTRLC (SAM_SERCOM6_BASE + SAM_I2C_CTRLC_OFFSET)
#define SAM_I2C6_BAUD (SAM_SERCOM6_BASE + SAM_I2C_BAUD_OFFSET)
#define SAM_I2C6_INTENCLR (SAM_SERCOM6_BASE + SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C6_INTENSET (SAM_SERCOM6_BASE + SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C6_INTFLAG (SAM_SERCOM6_BASE + SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C6_STATUS (SAM_SERCOM6_BASE + SAM_I2C_STATUS_OFFSET)
#define SAM_I2C6_SYNCBUSY (SAM_SERCOM6_BASE + SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C6_ADDR (SAM_SERCOM6_BASE + SAM_I2C_ADDR_OFFSET)
#define SAM_I2C6_DATA (SAM_SERCOM6_BASE + SAM_I2C_DATA_OFFSET)
#define SAM_I2C6_DBGCTRL (SAM_SERCOM6_BASE + SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C5_CTRLA (SAM_SERCOM7_BASE + SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C7_CTRLB (SAM_SERCOM7_BASE + SAM_I2C_CTRLB_OFFSET)
#define SAM_I27C_CTRLC (SAM_SERCOM7_BASE + SAM_I2C_CTRLC_OFFSET)
#define SAM_I2C7_BAUD (SAM_SERCOM7_BASE + SAM_I2C_BAUD_OFFSET)
#define SAM_I2C7_INTENCLR (SAM_SERCOM7_BASE + SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C7_INTENSET (SAM_SERCOM7_BASE + SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C7_INTFLAG (SAM_SERCOM7_BASE + SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C7_STATUS (SAM_SERCOM7_BASE + SAM_I2C_STATUS_OFFSET)
#define SAM_I2C7_SYNCBUSY (SAM_SERCOM7_BASE + SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C7_ADDR (SAM_SERCOM7_BASE + SAM_I2C_ADDR_OFFSET)
#define SAM_I2C7_DATA (SAM_SERCOM7_BASE + SAM_I2C_DATA_OFFSET)
#define SAM_I2C7_DBGCTRL (SAM_SERCOM7_BASE + SAM_I2C_DBGCTRL_OFFSET)
/* I2C register bit definitions *************************************************************/
/* Control A register */
#define I2C_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
#define I2C_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
#define I2C_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */
#define I2C_CTRLA_MODE_MASK (7 << I2C_CTRLA_MODE_SHIFT)
# define I2C_CTRLA_MODE_MASTER (5 << I2C_CTRLA_MODE_SHIFT) /* I2C master mode */
#define I2C_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */
#define I2C_CTRLA_PINOUT (1 << 16) /* Bit 16: Transmit data pinout */
# define I2C_CTRLA_1WIRE (0) /* 4-wire operation disable */
# define I2C_CTRLA_4WIRE I2C_CTRLA_PINOUT /* 4-wire operation enable */
#define I2C_CTRLA_SDAHOLD_SHIFT (20) /* Bits 20-21: SDA Hold Time */
#define I2C_CTRLA_SDAHOLD_MASK (3 << I2C_CTRLA_SDAHOLD_SHIFT)
# define I2C_CTRLA_SDAHOLD_DIS (0 << I2C_CTRLA_SDAHOLD_SHIFT) /* Disabled */
# define I2C_CTRLA_SDAHOLD_75NS (1 << I2C_CTRLA_SDAHOLD_SHIFT) /* 50-100ns hold time */
# define I2C_CTRLA_SDAHOLD_450NS (2 << I2C_CTRLA_SDAHOLD_SHIFT) /* 300-600ns hold time */
# define I2C_CTRLA_SDAHOLD_600NS (3 << I2C_CTRLA_SDAHOLD_SHIFT) /* 400-800ns hold time */
#define I2C_CTRLA_MEXTTOEN (1 << 22) /* Bit 22: Master SCL low extend time-out */
#define I2C_CTRLA_SEXTTOEN (1 << 23) /* Bit 23: Slave SCL low extend time-out */
#define I2C_CTRLA_SPEED_SHIFT (24) /* Bits 24-25: Transfer speed */
#define I2C_CTRLA_SPEED_MASK (3 << I2C_CTRLA_SPEED_SHIFT)
# define I2C_CTRLA_SPEED_STD (0 << I2C_CTRLA_SPEED_SHIFT) /* Standard (<=100KHz) and fast (<=400KHz) */
# define I2C_CTRLA_SPEED_FAST (1 << I2C_CTRLA_SPEED_SHIFT) /* Fast-mode plus (<=1MHz) */
# define I2C_CTRLA_SPEED_HIGH (2 << I2C_CTRLA_SPEED_SHIFT) /* High speed mode (<=3.4Mhz */
#define I2C_CTRLA_SCLAM (1 << 27) /* Bit 27: CSL clock stretch mode */
#define I2C_CTRLA_INACTOUT_SHIFT (28) /* Bits 28-29: Inactive Time-Out */
#define I2C_CTRLA_INACTOUT_MASK (7 << I2C_CTRLA_INACTOUT_SHIFT)
# define I2C_CTRLA_INACTOUT_DIS (0 << I2C_CTRLA_INACTOUT_SHIFT) /* Disabled */
# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60µs) */
# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110µs) */
# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210µs) */
#define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */
/* Control B register */
#define I2C_CTRLB_SMEN (1 << 8) /* Bit 8: Smart Mode Enable */
#define I2C_CTRLB_QCEN (1 << 9) /* Bit 9: Quick Command Enable */
#define I2C_CTRLB_CMD_SHIFT (16) /* Bits 16-17: Command */
#define I2C_CTRLB_CMD_MASK (3 << I2C_CTRLB_CMD_SHIFT)
# define I2C_CTRLB_CMD_NOACTION (0 << I2C_CTRLB_CMD_SHIFT) /* No action */
# define I2C_CTRLB_CMD_ACKREP (1 << I2C_CTRLB_CMD_SHIFT) /* ACK followed by repeated START */
# define I2C_CTRLB_CMD_ACKREAD (2 << I2C_CTRLB_CMD_SHIFT) /* ACK followed by read operation */
# define I2C_CTRLB_CMD_ACKSTOP (3 << I2C_CTRLB_CMD_SHIFT) /* ACK followed by STOP */
#define I2C_CTRLB_ACKACT (1 << 18) /* Bit 18: Acknowledge Action */
# define I2C_CTRLB_ACK (0) /* Send ACK */
# define I2C_CTRLB_NACK I2C_CTRLB_ACKACT /* Send NACK */
/* Control C register */
#define I2C_CTRLC_DATA32B (1 << 24) /* Bit 24: Data 32 Bit */
# define I2C_CTRLC_DATA32B_8BIT (0) /* DATA register is 8-bit */
# define I2C_CTRLC_DATA32B_32BIT I2C_CTRLC_DATA32B /* DATA register is 32-bit */
/* Baud register (16-bit baud value) */
#define I2C_BAUD_SHIFT (0) /* Bits 0-7: Master Baud Rate */
#define I2C_BAUD_MASK (0xff << I2C_BAUD_SHIFT)
# define I2C_BAUD(n) ((uint16)(n) << I2C_BAUD_SHIFT)
#define I2C_BAUDLOW_SHIFT (8) /* Bits 8-15: Master Baud Rate Low */
#define I2C_BAUDLOW_MASK (0xff << I2C_BAUDLOW_SHIFT)
# define I2C_BAUDLOW(n) (uint16)(n) << I2C_BAUDLOW_SHIFT)
#define I2C_HSBAUD_SHIFT (16) /* Bits 16-23: High speed master Baud Rate */
#define I2C_HSBAUD_MASK (0xff << I2C_HSBAUD_SHIFT)
# define I2C_HSBAUD(n) ((uint16)(n) << I2C_HSBAUD_SHIFT)
#define I2C_HSBAUDLOW_SHIFT (24) /* Bits 24-31: High speed master Baud Rate Low */
#define I2C_HSBAUDLOW_MASK (0xff << I2C_HSBAUDLOW_SHIFT)
# define I2C_HSBAUDLOW(n) (uint16)(n) << I2C_HSBAUDLOW_SHIFT)
/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and
* status clear registers.
*/
#define I2C_INT_MB (1 << 0) /* Bit 0: Master on bus interrupt */
#define I2C_INT_SB (1 << 1) /* Bit 1: Slave on bus interrupt */
#define I2C_INT_ERR (1 << 7) /* Bit 7: Bus Error */
#define I2C_INT_ALL (0x03)
/* Status register */
#define I2C_STATUS_BUSERR (1 << 0) /* Bit 0: Bus Error */
#define I2C_STATUS_ARBLOST (1 << 1) /* Bit 1: Arbitration Lost */
#define I2C_STATUS_RXNACK (1 << 2) /* Bit 2: Received Not Acknowledge */
#define I2C_STATUS_BUSSTATE_SHIFT (4) /* Bits 4-5: Bus State */
#define I2C_STATUS_BUSSTATE_MASK (3 << I2C_STATUS_BUSSTATE_SHIFT)
# define I2C_STATUS_BUSSTATE_UNKNOWN (0 << I2C_STATUS_BUSSTATE_SHIFT) /* Unknown to master */
# define I2C_STATUS_BUSSTATE_IDLE (1 << I2C_STATUS_BUSSTATE_SHIFT) /* Waiting for transaction */
# define I2C_STATUS_BUSSTATE_OWNER (2 << I2C_STATUS_BUSSTATE_SHIFT) /* Master of bus owner */
# define I2C_STATUS_BUSSTATE_BUSY (3 << I2C_STATUS_BUSSTATE_SHIFT) /* Other master owns */
#define I2C_STATUS_LOWTOUT (1 << 6) /* Bit 6: SCL Low Time-Out */
#define I2C_STATUS_CLKHOLD (1 << 7) /* Bit 7: Clock Hold */
#define I2C_STATUS_MEXTTOUT (1 << 8) /* Bit 8: Master SCL low extend time-out */
#define I2C_STATUS_SEXTTOUT (1 << 9) /* Bit 9: Slave SCL low extend time-out */
#define I2C_STATUS_LENERR (1 << 10) /* Bit 10: Transaction length error */
/* Synchronization busy register */
#define I2C_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset synchronization busy */
#define I2C_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: SERCOM enable synchronization busy */
#define I2C_SYNCBUSY_SYSOP (1 << 2) /* Bit 2: System operation synchronization busy */
/* Address register */
#define I2C_ADDR_SHIFT (0) /* Bits 0-10: Address */
#define I2C_ADDR_MASK (0x7ff << I2C_ADDR_SHIFT)
# define I2C_ADDR(n) ((uint32-_t(n) << I2C_ADDR_SHIFT)
#define I2C_ADDR_LENEN (1 << 13) /* Bit 13: Transfer length enable */
#define I2C_ADDR_HS (1 << 14) /* Bit 14: High speed */
#define I2C_ADDR_TENBITEN (1 << 15) /* Bit 15: Ten bit addressing enable */
#define I2C_ADDR_LEN_SHIFT (16) /* Bits 16-23: Transaction length */
#define I2C_ADDR_LEN_MASK (0xff << I2C_ADDR_LEN_SHIFT)
# define I2C_ADDR_LEN(n) ((uint32_t)(n) << I2C_ADDR_LEN_SHIFT)
/* Data register (8- or 32-bit data) */
#define I2C_DATA_MASK (0xff) /* Bits 0-7: Data */
/* Debug control register */
#define I2C_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_I2C_MASTER_H */
arch/arm/src/samd5e5/chip/sam_i2c_slave.h
+283
View File
@@ -0,0 +1,283 @@
/********************************************************************************************
* arch/arm/src/samd5e5/chip/sam_i2c_slave.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_I2C_SLAVE_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_I2C_SLAVE_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* I2C register offsets *********************************************************************/
#define SAM_I2C_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_I2C_CTRLB_OFFSET 0x0004 /* Control B register */
#define SAM_I2C_CTRLC_OFFSET 0x0008 /* Control C register */
#define SAM_I2C_INTENCLR_OFFSET 0x0014 /* Interrupt enable clear register */
#define SAM_I2C_INTENSET_OFFSET 0x0016 /* Interrupt enable set register */
#define SAM_I2C_INTFLAG_OFFSET 0x0018 /* Interrupt flag and status clear register */
#define SAM_I2C_STATUS_OFFSET 0x001a /* Status register */
#define SAM_I2C_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */
#define SAM_I2C_LENGTH_OFFSET 0x0022 /* Length register */
#define SAM_I2C_ADDR_OFFSET 0x0024 /* Address register */
#define SAM_I2C_DATA_OFFSET 0x0028 /* Data register */
/* I2C register addresses *******************************************************************/
#define SAM_I2C0_CTRLA (SAM_SERCOM0_BASE + SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C0_CTRLB (SAM_SERCOM0_BASE + SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C0_CTRLC (SAM_SERCOM0_BASE + SAM_I2C_CTRLC_OFFSET)
#define SAM_I2C0_INTENCLR (SAM_SERCOM0_BASE + SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C0_INTENSET (SAM_SERCOM0_BASE + SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C0_INTFLAG (SAM_SERCOM0_BASE + SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C0_STATUS (SAM_SERCOM0_BASE + SAM_I2C_STATUS_OFFSET)
#define SAM_I2C0_SYNCBUSY (SAM_SERCOM0_BASE + SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C0_LENGTH (SAM_SERCOM0_BASE + SAM_I2C_LENGTH_OFFSET)
#define SAM_I2C0_ADDR (SAM_SERCOM0_BASE + SAM_I2C_ADDR_OFFSET)
#define SAM_I2C0_DATA (SAM_SERCOM0_BASE + SAM_I2C_DATA_OFFSET)
#define SAM_I2C1_CTRLA (SAM_SERCOM1_BASE + SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C1_CTRLB (SAM_SERCOM1_BASE + SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C1_CTRLC (SAM_SERCOM1_BASE + SAM_I2C_CTRLC_OFFSET)
#define SAM_I2C1_INTENCLR (SAM_SERCOM1_BASE + SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C1_INTENSET (SAM_SERCOM1_BASE + SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C1_INTFLAG (SAM_SERCOM1_BASE + SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C1_STATUS (SAM_SERCOM1_BASE + SAM_I2C_STATUS_OFFSET)
#define SAM_I2C1_SYNCBUSY (SAM_SERCOM1_BASE + SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C1_LENGTH (SAM_SERCOM1_BASE + SAM_I2C_LENGTH_OFFSET)
#define SAM_I2C1_ADDR (SAM_SERCOM1_BASE + SAM_I2C_ADDR_OFFSET)
#define SAM_I2C1_DATA (SAM_SERCOM1_BASE + SAM_I2C_DATA_OFFSET)
#define SAM_I2C2_CTRLA (SAM_SERCOM2_BASE + SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C2_CTRLB (SAM_SERCOM2_BASE + SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C2_CTRLC (SAM_SERCOM2_BASE + SAM_I2C_CTRLC_OFFSET)
#define SAM_I2C2_INTENCLR (SAM_SERCOM2_BASE + SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C2_INTENSET (SAM_SERCOM2_BASE + SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C2_INTFLAG (SAM_SERCOM2_BASE + SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C2_STATUS (SAM_SERCOM2_BASE + SAM_I2C_STATUS_OFFSET)
#define SAM_I2C2_SYNCBUSY (SAM_SERCOM2_BASE + SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C2_LENGTH (SAM_SERCOM2_BASE + SAM_I2C_LENGTH_OFFSET)
#define SAM_I2C2_ADDR (SAM_SERCOM2_BASE + SAM_I2C_ADDR_OFFSET)
#define SAM_I2C2_DATA (SAM_SERCOM2_BASE + SAM_I2C_DATA_OFFSET)
#define SAM_I2C3_CTRLA (SAM_SERCOM3_BASE + SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C3_CTRLB (SAM_SERCOM3_BASE + SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C3_CTRLC (SAM_SERCOM3_BASE + SAM_I2C_CTRLC_OFFSET)
#define SAM_I2C3_INTENCLR (SAM_SERCOM3_BASE + SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C3_INTENSET (SAM_SERCOM3_BASE + SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C3_INTFLAG (SAM_SERCOM3_BASE + SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C3_STATUS (SAM_SERCOM3_BASE + SAM_I2C_STATUS_OFFSET)
#define SAM_I2C3_SYNCBUSY (SAM_SERCOM3_BASE + SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C3_LENGTH (SAM_SERCOM3_BASE + SAM_I2C_LENGTH_OFFSET)
#define SAM_I2C3_ADDR (SAM_SERCOM3_BASE + SAM_I2C_ADDR_OFFSET)
#define SAM_I2C3_DATA (SAM_SERCOM3_BASE + SAM_I2C_DATA_OFFSET)
#define SAM_I2C4_CTRLA (SAM_SERCOM4_BASE + SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C4_CTRLB (SAM_SERCOM4_BASE + SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C4_CTRLC (SAM_SERCOM4_BASE + SAM_I2C_CTRLC_OFFSET)
#define SAM_I2C4_INTENCLR (SAM_SERCOM4_BASE + SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C4_INTENSET (SAM_SERCOM4_BASE + SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C4_INTFLAG (SAM_SERCOM4_BASE + SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C4_STATUS (SAM_SERCOM4_BASE + SAM_I2C_STATUS_OFFSET)
#define SAM_I2C4_SYNCBUSY (SAM_SERCOM4_BASE + SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C4_LENGTH (SAM_SERCOM4_BASE + SAM_I2C_LENGTH_OFFSET)
#define SAM_I2C4_ADDR (SAM_SERCOM4_BASE + SAM_I2C_ADDR_OFFSET)
#define SAM_I2C4_DATA (SAM_SERCOM4_BASE + SAM_I2C_DATA_OFFSET)
#define SAM_I2C5_CTRLA (SAM_SERCOM5_BASE + SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C5_CTRLB (SAM_SERCOM5_BASE + SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C5_CTRLC (SAM_SERCOM5_BASE + SAM_I2C_CTRLC_OFFSET)
#define SAM_I2C5_INTENCLR (SAM_SERCOM5_BASE + SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C5_INTENSET (SAM_SERCOM5_BASE + SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C5_INTFLAG (SAM_SERCOM5_BASE + SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C5_STATUS (SAM_SERCOM5_BASE + SAM_I2C_STATUS_OFFSET)
#define SAM_I2C5_SYNCBUSY (SAM_SERCOM5_BASE + SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C5_LENGTH (SAM_SERCOM5_BASE + SAM_I2C_LENGTH_OFFSET)
#define SAM_I2C5_ADDR (SAM_SERCOM5_BASE + SAM_I2C_ADDR_OFFSET)
#define SAM_I2C5_DATA (SAM_SERCOM5_BASE + SAM_I2C_DATA_OFFSET)
#define SAM_I2C6_CTRLA (SAM_SERCOM6_BASE + SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C6_CTRLB (SAM_SERCOM6_BASE + SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C6_CTRLC (SAM_SERCOM6_BASE + SAM_I2C_CTRLC_OFFSET)
#define SAM_I2C6_INTENCLR (SAM_SERCOM6_BASE + SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C6_INTENSET (SAM_SERCOM6_BASE + SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C6_INTFLAG (SAM_SERCOM6_BASE + SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C6_STATUS (SAM_SERCOM6_BASE + SAM_I2C_STATUS_OFFSET)
#define SAM_I2C6_SYNCBUSY (SAM_SERCOM6_BASE + SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C6_LENGTH (SAM_SERCOM6_BASE + SAM_I2C_LENGTH_OFFSET)
#define SAM_I2C6_ADDR (SAM_SERCOM6_BASE + SAM_I2C_ADDR_OFFSET)
#define SAM_I2C6_DATA (SAM_SERCOM6_BASE + SAM_I2C_DATA_OFFSET)
#define SAM_I2C7_CTRLA (SAM_SERCOM7_BASE + SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C7_CTRLB (SAM_SERCOM7_BASE + SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C7_CTRLC (SAM_SERCOM7_BASE + SAM_I2C_CTRLC_OFFSET)
#define SAM_I2C7_INTENCLR (SAM_SERCOM7_BASE + SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C7_INTENSET (SAM_SERCOM7_BASE + SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C7_INTFLAG (SAM_SERCOM7_BASE + SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C7_STATUS (SAM_SERCOM7_BASE + SAM_I2C_STATUS_OFFSET)
#define SAM_I2C7_SYNCBUSY (SAM_SERCOM7_BASE + SAM_I2C_SYNCBUSY_OFFSET)
#define SAM_I2C7_LENGTH (SAM_SERCOM7_BASE + SAM_I2C_LENGTH_OFFSET)
#define SAM_I2C7_ADDR (SAM_SERCOM7_BASE + SAM_I2C_ADDR_OFFSET)
#define SAM_I2C7_DATA (SAM_SERCOM7_BASE + SAM_I2C_DATA_OFFSET)
/* I2C register bit definitions *************************************************************/
/* Control A register */
#define I2C_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
#define I2C_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
#define I2C_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */
#define I2C_CTRLA_MODE_MASK (7 << I2C_CTRLA_MODE_SHIFT)
# define I2C_CTRLA_MODE_SLAVE (4 << I2C_CTRLA_MODE_SHIFT) /* I2C slave mode */
#define I2C_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */
#define I2C_CTRLA_PINOUT (1 << 16) /* Bit 16: Pin usage */
# define I2C_CTRLA_1WIRE (0) /* 4-wire operation disabled */
# define I2C_CTRLA_4WIRE I2C_CTRLA_PINOUT /* 4-wire operation enabled */
#define I2C_CTRLA_SDAHOLD_SHIFT (20) /* Bits 20-21: SDA Hold Time */
#define I2C_CTRLA_SDAHOLD_MASK (3 << I2C_CTRLA_SDAHOLD_SHIFT)
# define I2C_CTRLA_SDAHOLD_DIS (0 << I2C_CTRLA_SDAHOLD_SHIFT) /* Disabled */
# define I2C_CTRLA_SDAHOLD_75NS (1 << I2C_CTRLA_SDAHOLD_SHIFT) /* 50-100ns hold time */
# define I2C_CTRLA_SDAHOLD_450NS (2 << I2C_CTRLA_SDAHOLD_SHIFT) /* 300-600ns hold time */
# define I2C_CTRLA_SDAHOLD_600NS (3 << I2C_CTRLA_SDAHOLD_SHIFT) /* 400-800ns hold time */
#define I2C_CTRLA_SEXTTOEN (1 << 23) /* Bit 23: Slave SCL low extend time-out */
#define I2C_CTRLA_SPEED_SHIFT (24) /* Bits 24-25: Trnasfer speed */
#define I2C_CTRLA_SPEED_MASK (3 << I2C_CTRLA_SPEED_SHIFT)
# define I2C_CTRLA_SPEED_STD (0 << I2C_CTRLA_SPEED_SHIFT) /* Standard (<=100KHz) fast <=400KHz */
# define I2C_CTRLA_SPEED_FAST (1 << I2C_CTRLA_SPEED_SHIFT) /* Fast-mode plase (<=1MHz) */
# define I2C_CTRLA_SPEED_HIGH (2 << I2C_CTRLA_SPEED_SHIFT) /* High-speed mode (<=3.4Mhz */
#define I2C_CTRLA_SCLSM (1 << 27) /* Bit 27: SCL clock stretch mode */
#define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */
/* Control B register */
#define I2C_CTRLB_SMEN (1 << 8) /* Bit 8: Smart Mode Enable */
#define I2C_CTRLB_GCMD (1 << 9) /* Bit 9: PMBus group commend */
#define I2C_CTRLB_AACKEN (1 << 10) /* Bit 10: Automatic acknowledge enable */
#define I2C_CRLB_AMODE_SHIFT (14) /* Bits 14-15: Address Mode */
#define I2C_CRLB_AMODE_MASK (3 << I2C_CRLB_AMODE_SHIFT)
# define I2C_CRLB_AMODE_MASK (0 << I2C_CRLB_AMODE_SHIFT) /* ADDRMASK used to mask ADDR */
# define I2C_CRLB_AMODE_2ADDRS (1 << I2C_CRLB_AMODE_SHIFT) /* Slave 2 addresses: ADDR & ADDRMASK */
# define I2C_CRLB_AMODE_RANGE (2 << I2C_CRLB_AMODE_SHIFT) /* Slave range of addresses: ADDRMASK-ADDR */
#define I2C_CTRLB_CMD_SHIFT (16) /* Bits 16-17: Command */
#define I2C_CTRLB_CMD_MASK (3 << I2C_CTRLB_CMD_SHIFT)
# define I2C_CTRLB_CMD_NOACTION (0 << I2C_CTRLB_CMD_SHIFT) /* No action */
# define I2C_CTRLB_CMD_WAITSTART (2 << I2C_CTRLB_CMD_SHIFT) /* ACK (write) wait for START */
# define I2C_CTRLB_CMD_ACKREAD (3 << I2C_CTRLB_CMD_SHIFT) /* ACK with read (context dependent) */
#define I2C_CTRLB_ACKACT (1 << 18) /* Bit 18: Acknowledge Action */
# define I2C_CTRLB_ACK (0) /* Send ACK */
# define I2C_CTRLB_NCK I2C_CTRLB_ACKACT /* Send NACK */
/* Control C register */
#define I2C_CTRLC_SDASETUP_SHIFT (0) /* Bits 0-3: Inter-Character Spacing */
#define I2C_CTRLC_SDASETUP_MASK (15 << I2C_CTRLC_SDASETUP_SHIFT)
# define I2C_CTRLC_SDASETUP(n) ((uint32_t)(n) << I2C_CTRLC_SDASETUP_SHIFT)
#define I2C_CTRLC_DATA32B (1 << 24) /* Bit 24: Data 32 Bit */
# define I2C_CTRLC_DATA32B_8BIT (0) /* DATA register is 8-bit */
# define I2C_CTRLC_DATA32B_32BIT I2C_CTRLC_DATA32B /* DATA register is 32-bit */
/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and
* status clear registers.
*/
#define I2C_INT_PREC (1 << 0) /* Bit 0: Stop received interrupt */
#define I2C_INT_AMATCH (1 << 1) /* Bit 1: Address match interrupt */
#define I2C_INT_DRDY (1 << 2) /* Bit 2: Data ready interrupt */
#define I2C_INT_ERROR (1 << 7) /* Bit 7: Error interrupt */
#define I2C_INT_ALL (0x87)
/* Status register */
#define I2C_STATUS_BUSERR (1 << 0) /* Bit 0: Bus Error */
#define I2C_STATUS_COLL (1 << 1) /* Bit 1: Transmit Collision */
#define I2C_STATUS_RXNACK (1 << 2) /* Bit 2: Received Not Acknowledge */
#define I2C_STATUS_DIR (1 << 3) /* Bit 3: Read / Write Direction */
#define I2C_STATUS_SR (1 << 4) /* Bit 4: Repeated Start */
#define I2C_STATUS_LOWTOUT (1 << 6) /* Bit 6: SCL Low Time-out */
#define I2C_STATUS_CLKHOLD (1 << 7) /* Bit 7: Clock Hold */
#define I2C_STATUS_SEXTTOUT (1 << 9) /* Bit 9: Slave SCL Low Extend Time-Out */
#define I2C_STATUS_HS (1 << 10) /* Bit 10: High-speed */
#define I2C_STATUS_LENERR (1 << 11) /* Bit 11: Transaction Length Error */
/* Synchronization busy register */
#define I2C_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset synchronization busy */
#define I2C_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: SERCOM enable synchronization busy */
#define I2C_SYNCBUSY_LENGTH (1 << 4) /* Bit 3: LENGTH synchronization busy */
/* Length register */
#define I2C_LENGTH_LEN_SHIFT (0) /* Bit 0-7: Data length enable */
#define I2C_LENGTH_LEN_MASK (0xff << I2C_LENGTH_LEN_SHIFT)
# define I2C_LENGTHLEN(n) ((uint32_t)(n) << I2C_LENGTH_LEN_SHIFT)
#define I2C_LENGTH_LENEN (1 << 8) /* Bit 8: Data Length Enable */
/* Address register */
#define I2C_ADDR_GENCEN (1 << 0) /* Bit 0: General Call Address Enable */
#define I2C_ADDR_SHIFT (1) /* Bits 1-10: Address */
#define I2C_ADDR_MASK (0x3ff << I2C_ADDR_SHIFT)
# define I2C_ADDR(n) ((uint32_t)(n) << I2C_ADDR_SHIFT)
#define I2C_ADDR_TENBITEN (1 << 15) /* Bit 15: */
#define I2C_ADDRMASK_SHIFT (17) /* Bits 17-26: Address Mask */
#define I2C_ADDRMASK_MASK (0x3ff << I2C_ADDRMASK_SHIFT)
# define I2C_ADDRMASK(n) ((uint32_t)(n) << I2C_ADDRMASK_SHIFT)
/* Data register (8- or 32-bit data) */
#define I2C_DATA_MASK (0xff) /* Bits 0-7: Data */
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_I2C_SLAVE_H */
arch/arm/src/samd5e5/chip/sam_mclk.h
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/************************************************************************************
* arch/arm/src/samd5e5/chip/sam_mclk.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MCLK_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MCLK_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* MCLK register offsets ************************************************************/
#define SAM_MCLK_CTRLA_OFFSET 0x0000 /* CTRLA register */
#define SAM_MCLK_INTENCLR_OFFSET 0x0001 /* Interrupt enable clear */
#define SAM_MCLK_INTENSET_OFFSET 0x0002 /* Interrupt enable set */
#define SAM_MCLK_INTFLAG_OFFSET 0x0003 /* Interrupt flag status and clear */
#define SAM_MCLK_HSDIV_OFFSET 0x0004 /* High-Speed Clock Division */
#define SAM_MCLK_CPUDIV_OFFSET 0x0005 /* CPU clock division */
/* 0x0006-0x000f: Reserved */
#define SAM_MCLK_AHBMASK_OFFSET 0x0010 /* AHB mask */
#define SAM_MCLK_APBAMASK_OFFSET 0x0014 /* APBA mask */
#define SAM_MCLK_APBBMASK_OFFSET 0x0018 /* APBB mask */
#define SAM_MCLK_APBCMASK_OFFSET 0x001c /* APBC mask */
#define SAM_MCLK_APBDMASK_OFFSET 0x0020 /* APBD mask */
/* MCLK register addresses **********************************************************/
#define SAM_MCLK_CTRLA (SAM_MCLK_BASE + SAM_MCLK_CTRLA_OFFSET)
#define SAM_MCLK_INTENCLR (SAM_MCLK_BASE + SAM_MCLK_INTENCLR_OFFSET)
#define SAM_MCLK_INTENSET (SAM_MCLK_BASE + SAM_MCLK_INTENSET_OFFSET)
#define SAM_MCLK_INTFLAG (SAM_MCLK_BASE + SAM_MCLK_INTFLAG_OFFSET)
#define SAM_MCLK_HSDIV (SAM_MCLK_BASE + SAM_MCLK_HSDIV_OFFSET)
#define SAM_MCLK_CPUDIV (SAM_MCLK_BASE + SAM_MCLK_CPUDIV_OFFSET)
#define SAM_MCLK_AHBMASK (SAM_MCLK_BASE + SAM_MCLK_AHBMASK_OFFSET)
#define SAM_MCLK_APBAMASK (SAM_MCLK_BASE + SAM_MCLK_APBAMASK_OFFSET)
#define SAM_MCLK_APBBMASK (SAM_MCLK_BASE + SAM_MCLK_APBBMASK_OFFSET)
#define SAM_MCLK_APBCMASK (SAM_MCLK_BASE + SAM_MCLK_APBCMASK_OFFSET)
#define SAM_MCLK_APBDMASK (SAM_MCLK_BASE + SAM_MCLK_APBDMASK_OFFSET)
/* MCLK register bit definitions ****************************************************/
/* CTRLA register -- All bits are reserved (?) */
/* Interrupt enable clear, Interrupt enable set, and Interrupt flag status and
* clear.
*/
#define MCLK_INT_CKRDY (1 << 0) /* Bit 0: Clock ready */
/* High-Speed Clock Division (8-bit value) */
/* CPU clock division (8-bit divider) */
#define MCLK_CPUDIV_DIV1 0x01
#define MCLK_CPUDIV_DIV2 0x02
#define MCLK_CPUDIV_DIV4 0x04
#define MCLK_CPUDIV_DIV8 0x08
#define MCLK_CPUDIV_DIV16 0x10
#define MCLK_CPUDIV_DIV32 0x20
#define MCLK_CPUDIV_DIV64 0x40
#define MCLK_CPUDIV_DIV128 0x80
/* AHB mask */
#define MCLK_AHBMASK_HPB0 (1 << 0) /* Bit 0: AHB HPB0 clock for enable */
#define MCLK_AHBMASK_HPB1 (1 << 1) /* Bit 1: AHB HPB1 clock enable */
#define MCLK_AHBMASK_HPB2 (1 << 2) /* Bit 2: AHB HPB2 clock enable */
#define MCLK_AHBMASK_HPB3 (1 << 3) /* Bit 3: AHB HPB3 clock enable */
#define MCLK_AHBMASK_DSU (1 << 4) /* Bit 4: DSU AHB clock enable */
/* Bit 5: Reserved */
#define MCLK_AHBMASK_NVMCTRL (1 << 6) /* Bit 6: NVMCTRL AHB clock enable */
/* Bit 7: Reserved */
#define MCLK_AHBMASK_CMCC (1 << 8) /* Bit 8: CMCC AHB Clock Enable */
#define MCLK_AHBMASK_DMAC (1 << 9) /* Bit 9: DMAC AHB clock enable */
#define MCLK_AHBMASK_USB (1 << 10) /* Bit 10: USB AHB clock enable */
/* Bit 11: Reserved */
#define MCLK_AHBMASK_PAC (1 << 12) /* Bit 12: PAC AHB clock enable */
#define MCLK_AHBMASK_QSPI (1 << 13) /* Bit 13: QSPI AHB Clock Enable */
#define MCLK_AHBMASK_GMAC (1 << 14) /* Bit 14: GMAC AHB Clock Enable */
#define MCLK_AHBMASK_SDHC0 (1 << 15) /* Bit 15: SDHC0 HB Clock Enable */
#define MCLK_AHBMASK_SDHC1 (1 << 16) /* Bit 16: SDHC1 HB Clock Enable */
#define MCLK_AHBMASK_CAN0 (1 << 17) /* Bit 17: CAN0 AHB Clock Enable */
#define MCLK_AHBMASK_CAN1 (1 << 18) /* Bit 18: CAN1 AHB Clock Enable */
#define MCLK_AHBMASK_ICM (1 << 19) /* Bit 19: ICM AHB Clock Enable */
#define MCLK_AHBMASK_PUKCC (1 << 20) /* Bit 20: PUKCC AHB Clock Enable */
#define MCLK_AHBMASK_QSPI2X (1 << 21) /* Bit 21: QSPI_2X AHB Clock Enable */
#define MCLK_AHBMASK_NVMCTRL_SMEEPROM (1 << 22) /* Bit 22: NVMCTRL_SMEEPROM AHB Clock Enable */
#define MCLK_AHBMASK_NVMCTRL_CACHE (1 << 23) /* Bit 23: NVMCTRL_CACHE AHB Clock Enable */
/* APBA mask */
#define MCLK_APBAMASK_PAC (1 << 1) /* Bit 0: PAC APBA Clock Enable */
#define MCLK_APBAMASK_PM (1 << 1) /* Bit 1: PM APBA clock enable */
#define MCLK_APBAMASK_MCLK (1 << 2) /* Bit 2: MCLK APBA clock enable */
#define MCLK_APBAMASK_RSTC (1 << 3) /* Bit 3: RSTC APBA clock enable */
#define MCLK_APBAMASK_OSCCTRL (1 << 4) /* Bit 4: OSCCTRL APBA clock enable */
#define MCLK_APBAMASK_OSC32KCTRL (1 << 5) /* Bit 5: OSC32KCTRL APBA clock enable */
#define MCLK_APBAMASK_SUPC (1 << 6) /* Bit 6: SUPC APBA clock enable */
#define MCLK_APBAMASK_GCLK (1 << 7) /* Bit 7: GCLK APBA clock enable */
#define MCLK_APBAMASK_WDT (1 << 8) /* Bit 8: WDT APBA clock enable */
#define MCLK_APBAMASK_RTC (1 << 9) /* Bit 9: RTC APBA clock enable */
#define MCLK_APBAMASK_EIC (1 << 10) /* Bit 10: EIC APBA clock enable */
#define MCLK_APBAMASK_FREQM (1 << 11) /* Bit 11: FREQM APBA clock enable */
#define MCLK_APBAMASK_SERCOM0 (1 << 12) /* Bit 12: SERCOM0 APBA Clock Enable */
#define MCLK_APBAMASK_SERCOM1 (1 << 13) /* Bit 13: SERCOM1 APBA Clock Enable */
#define MCLK_APBAMASK_TC0 (1 << 14) /* Bit 14: TC0 APBA clock enable */
#define MCLK_APBAMASK_TC1 (1 << 15) /* Bit 15: TC1 APBA clock enable */
/* APBB mask */
#define MCLK_APBBMASK_USB (1 << 0) /* Bit 0: USB APBB clock enable */
#define MCLK_APBBMASK_DSU (1 << 1) /* Bit 1: DSU APBB clock enable */
#define MCLK_APBBMASK_NVMCTRL (1 << 2) /* Bit 2: NVMCTRL APBB clock enable */
#define MCLK_APBBMASK_PORT (1 << 4) /* Bit 4: PORT APBB Clock Enable */
#define MCLK_APBBMASK_EVSYS (1 << 7) /* Bit 7: EVSYS APBB Clock Enable */
#define MCLK_APBBMASK_SERCOM2 (1 << 9) /* Bit 9: SERCOM2 APBB Clock Enable */
#define MCLK_APBBMASK_SERCOM3 (1 << 10) /* Bit 10: SERCOM3 APBB Clock Enable */
#define MCLK_APBBMASK_TCC0 (1 << 11) /* Bit 11: TCC2 APBB Clock Enable */
#define MCLK_APBBMASK_TCC1 (1 << 12) /* Bit 12: TCC3 APBB Clock Enable */
#define MCLK_APBBMASK_TC2 (1 << 13) /* Bit 13: TC2 APBB Clock Enable */
#define MCLK_APBBMASK_TC3 (1 << 14) /* Bit 14: TC3 APBB Clock Enable */
#define MCLK_APBBMASK_RAMECC (1 << 16) /* Bit 16: RAMECC APBB Clock Enable */
/* APBC mask */
#define MCLK_APBCMASK_GMAC (1 << 2) /* Bit 2: GMAC APBC Mask Clock Enable */
#define MCLK_APBCMASK_TCC2 (1 << 3) /* Bit 3: TCC2 APBC Clock Enable */
#define MCLK_APBCMASK_TCC3 (1 << 4) /* Bit 4: TCC3 APBC Clock Enable */
#define MCLK_APBCMASK_TC4 (1 << 5) /* Bit 5: TC4 APBC Clock Enable */
#define MCLK_APBCMASK_TC5 (1 << 6) /* Bit 6: TC5 APBC Clock Enable */
#define MCLK_APBCMASK_PDEC (1 << 7) /* Bit 7: PDEC APBC Mask Clock Enable */
#define MCLK_APBCMASK_AC (1 << 8) /* Bit 8: AC APBC Mask Clock Enable */
#define MCLK_APBCMASK_AES (1 << 9) /* Bit 9: AES APBC Mask Clock Enable */
#define MCLK_APBCMASK_TRNG (1 << 10) /* Bit 10: TRNG APBC Mask Clock Enable */
#define MCLK_APBCMASK_ICM (1 << 11) /* Bit 11: ICM APBC Mask Clock Enable */
#define MCLK_APBCMASK_QSPI (1 << 13) /* Bit 13: QSPI APBC Mask Clock Enable */
#define MCLK_APBCMASK_CCL (1 << 14) /* Bit 14: CCL APBC Mask Clock Enable */
/* APBD mask */
#define MCLK_APBDMASK_SERCOM4 (1 << 0) /* Bit 0: SERCOM4 APBD clock enable */
#define MCLK_APBDMASK_SERCOM5 (1 << 1) /* Bit 1: SERCOM5 APBD clock enable */
#define MCLK_APBDMASK_SERCOM6 (1 << 2) /* Bit 2: SERCOM6 APBD clock enable */
#define MCLK_APBDMASK_SERCOM7 (1 << 3) /* Bit 3: SERCOM7 APBD clock enable */
#define MCLK_APBDMASK_TCC4 (1 << 4) /* Bit 4: TCC5 APBD Clock Enable */
#define MCLK_APBDMASK_TC6 (1 << 5) /* Bit 5: TC6 APBD Clock Enable */
#define MCLK_APBDMASK_TC7 (1 << 6) /* Bit 6: TC7 APBD Clock Enable */
#define MCLK_APBDMASK_ADC0 (1 << 7) /* Bit 7: ADC0 APBD clock enable */
#define MCLK_APBDMASK_ADC1 (1 << 8) /* Bit 8: ADC1 APBD clock enable */
#define MCLK_APBDMASK_DAC (1 << 9) /* Bit 9: DAC APBD clock enable */
#define MCLK_APBDMASK_I2C (1 << 10) /* Bit 10: I2S APBD clock enable */
#define MCLK_APBDMASK_PCC (1 << 11) /* Bit 11: PCC APBD clock enable */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MCLK_H */
arch/arm/src/samd5e5/chip/sam_memorymap.h
+52
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/************************************************************************************
* arch/arm/src/samd5e5/chip/sam_memorymap.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MEMORYMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(ARCH_CHIP_SAME5X)
# include "chip/samd5e5_memorymap.h"
#else
# error "Unsupported SAMD5/E5 family"
#endif
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MEMORYMAP_H */
arch/arm/src/samd5e5/chip/sam_nvmctrl.h
+253
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/********************************************************************************************
* arch/arm/src/samd5e5/chip/sam_nvmctrl.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_NVMCTRL_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_NVMCTRL_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* NVMCTRL register offsets *****************************************************************/
#define SAM_NVMCTRL_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_NVMCTRL_CTRLB_OFFSET 0x0004 /* Control B register */
#define SAM_NVMCTRL_PARAM_OFFSET 0x0008 /* NVM parameter register */
#define SAM_NVMCTRL_INTENCLR_OFFSET 0x000c /* Interrupt clear register */
#define SAM_NVMCTRL_INTENSET_OFFSET 0x000e /* Interrupt set register */
#define SAM_NVMCTRL_INTFLAG_OFFSET 0x0010 /* Interface flags status and clear register */
#define SAM_NVMCTRL_STATUS_OFFSET 0x0012 /* Status register */
#define SAM_NVMCTRL_ADDR_OFFSET 0x0014 /* Address register */
#define SAM_NVMCTRL_RUNLOCK_OFFSET 0x0018 /* Lock section register */
#define SAM_NVMCTRL_PBLDATAn0_OFFSET 0x001c /* Page buffer load data n 0 */
#define SAM_NVMCTRL_PBLDATAn1_OFFSET 0x0020 /* Page buffer load data n 1 */
#define SAM_NVMCTRL_ECCERR_OFFSET 0x0024 /* ECC error status register */
#define SAM_NVMCTRL_DBGCTRL_OFFSET 0x0028 /* Debug control register */
#define SAM_NVMCTRL_SEECFG_OFFSET 0x002a /* SmartEEPROM configuration register */
#define SAM_NVMCTRL_SEESTAT_OFFSET 0x002c /* SmartEEPROM status register */
/* NVMCTRL register addresses ***************************************************************/
#define SAM_NVMCTRL_CTRLA (SAM_NVMCTRL_BASE + SAM_NVMCTRL_CTRLA_OFFSET)
#define SAM_NVMCTRL_CTRLB (SAM_NVMCTRL_BASE + SAM_NVMCTRL_CTRLB_OFFSET)
#define SAM_NVMCTRL_INTENCLR (SAM_NVMCTRL_BASE + SAM_NVMCTRL_INTENCLR_OFFSET)
#define SAM_NVMCTRL_INTENSET (SAM_NVMCTRL_BASE + SAM_NVMCTRL_INTENSET_OFFSET)
#define SAM_NVMCTRL_INTFLAG (SAM_NVMCTRL_BASE + SAM_NVMCTRL_INTFLAG_OFFSET)
#define SAM_NVMCTRL_STATUS (SAM_NVMCTRL_BASE + SAM_NVMCTRL_STATUS_OFFSET)
#define SAM_NVMCTRL_ADDR (SAM_NVMCTRL_BASE + SAM_NVMCTRL_ADDR_OFFSET)
#define SAM_NVMCTRL_RUNLOCK (SAM_NVMCTRL_BASE + SAM_NVMCTRL_RUNLOCK_OFFSET)
#define SAM_NVMCTRL_PBLDATAn0 (SAM_NVMCTRL_BASE + SAM_NVMCTRL_PBLDATAn0_OFFSET)
#define SAM_NVMCTRL_PBLDATAn1 (SAM_NVMCTRL_BASE + SAM_NVMCTRL_PBLDATAn1_OFFSET)
#define SAM_NVMCTRL_ECCERR (SAM_NVMCTRL_BASE + SAM_NVMCTRL_ECCERR_OFFSET)
#define SAM_NVMCTRL_DBGCTRL (SAM_NVMCTRL_BASE + SAM_NVMCTRL_DBGCTRL_OFFSET)
#define SAM_NVMCTRL_SEECFG (SAM_NVMCTRL_BASE + SAM_NVMCTRL_SEECFG_OFFSET)
#define SAM_NVMCTRL_SEESTAT (SAM_NVMCTRL_BASE + SAM_NVMCTRL_SEESTAT_OFFSET)
/* NVMCTRL register bit definitions *********************************************************/
/* Control A register */
#define NVMCTRL_CTRLA_AUTOWS (1 << 2) /* Bit 2: Auto Wait State Enable */
#define NVMCTRL_CTRLA_SUSPEN (1 << 3) /* Bit 3: Suspend Enable */
#define NVMCTRL_CTRLA_WMODE_SHIFT (4) /* Bits 4-5: NVMCTRL Write Mode */
#define NVMCTRL_CTRLA_WMODE_MASK (3 << NVMCTRL_CTRLA_WMODE_SHIFT)
# define NVMCTRL_CTRLA_WMODE_MAN (0 << NVMCTRL_CTRLA_WMODE_SHIFT) /* Manual Write */
# define NVMCTRL_CTRLA_WMODE_ADW (1 << NVMCTRL_CTRLA_WMODE_SHIFT) /* Automatic Double Word Write */
# define NVMCTRL_CTRLA_WMODE_AQW (2 << NVMCTRL_CTRLA_WMODE_SHIFT) /* Automatic Quad Word */
# define NVMCTRL_CTRLA_WMODE_AP (2 << NVMCTRL_CTRLA_WMODE_SHIFT) /* Automatic Page Write */
#define NVMCTRL_CTRLA_PRM_SHIFT (8) /* Bits 8-9: Power Reduction Mode during Sleep */
#define NVMCTRL_CTRLA_PRM_MASK (3 << NVMCTRL_CTRLA_PRM_SHIFT)
# define NVMCTRL_CTRLA_PRM_SEMIAUTO (0 << NVMCTRL_CTRLA_PRM_SHIFT) /* Enter low power on STANDBY/SPRM cmd;
* Exit on first access */
# define NVMCTRL_CTRLA_PRM_FULLAUTO (1 << NVMCTRL_CTRLA_PRM_SHIFT) /* Enter/Exit low power on STANDBY */
# define NVMCTRL_CTRLA_PRM_MANUAL (3 << NVMCTRL_CTRLA_PRM_SHIFT) /* Enter low power only on SPRM cmd;
* Exit on first access */
#define NVMCTRL_CTRLA_RWS_SHIFT (8) /* Bits 8-11: NVM Read Wait States */
#define NVMCTRL_CTRLA_RWS_MASK (15 << NVMCTRL_CTRLA_RWS_SHIFT)
# define NVMCTRL_CTRLA_RWS(n) ((uint32_t)(n) << NVMCTRL_CTRLA_RWS_SHIFT)
#define NVMCTRL_CTRLA_AHBNS0 (1 << 12) /* Bit 12: Force AHB0 access to Non-Sequential */
#define NVMCTRL_CTRLA_AHBNS1 (1 << 13) /* Bit 13: Force AHB1 access to Non-Sequential */
#define NVMCTRL_CTRLA_CACHEDIS0 (1 << 14) /* Bit 14: AHB0 Cache Disable */
#define NVMCTRL_CTRLA_CACHEDIS1 (1 << 15) /* Bit 15: AHB1 Cache Disable */
/* Control B register */
#define NVMCTRL_CTRLB_CMD_SHIFT (0) /* Bits 0-6: Command */
#define NVMCTRL_CTRLB_CMD_MASK (0x7f << NVMCTRL_CTRLB_CMD_SHIFT)
# define NVMCTRL_CTRLB_CMD_EP (0x00 << NVMCTRL_CTRLB_CMD_SHIFT) /* Erase Page */
# define NVMCTRL_CTRLB_CMD_EB (0x01 << NVMCTRL_CTRLB_CMD_SHIFT) /* Erase Block */
# define NVMCTRL_CTRLB_CMD_WP (0x03 << NVMCTRL_CTRLB_CMD_SHIFT) /* Write Page */
# define NVMCTRL_CTRLB_CMD_WQW (0x04 << NVMCTRL_CTRLB_CMD_SHIFT) /* Write Quad Word */
# define NVMCTRL_CTRLB_CMD_SRST (0x10 << NVMCTRL_CTRLB_CMD_SHIFT) /* Software reset */
# define NVMCTRL_CTRLB_CMD_LR (0x11 << NVMCTRL_CTRLB_CMD_SHIFT) /* Lock Region */
# define NVMCTRL_CTRLB_CMD_UR (0x12 << NVMCTRL_CTRLB_CMD_SHIFT) /* Unlock Region */
# define NVMCTRL_CTRLB_CMD_SPRM (0x13 << NVMCTRL_CTRLB_CMD_SHIFT) /* Set power reduction mode */
# define NVMCTRL_CTRLB_CMD_CPRM (0x14 << NVMCTRL_CTRLB_CMD_SHIFT) /* Clear power reduction mode */
# define NVMCTRL_CTRLB_CMD_PBC (0x15 << NVMCTRL_CTRLB_CMD_SHIFT) /* Page Buffer Clear */
# define NVMCTRL_CTRLB_CMD_SSB (0x16 << NVMCTRL_CTRLB_CMD_SHIFT) /* Set Security Bit */
# define NVMCTRL_CTRLB_CMD_BKSWRST (0x17 << NVMCTRL_CTRLB_CMD_SHIFT) /* Bank swap and system reset */
# define NVMCTRL_CTRLB_CMD_CELCK (0x18 << NVMCTRL_CTRLB_CMD_SHIFT) /* Chip Erase Lock */
# define NVMCTRL_CTRLB_CMD_CEULCK (0x19 << NVMCTRL_CTRLB_CMD_SHIFT) /* Chip Erase Lock */
# define NVMCTRL_CTRLB_CMD_SBPDIS (0x1a << NVMCTRL_CTRLB_CMD_SHIFT) /* Sets STATUS */
# define NVMCTRL_CTRLB_CMD_CBPDIS (0x1b << NVMCTRL_CTRLB_CMD_SHIFT) /* Clears STATUS */
# define NVMCTRL_CTRLB_CMD_ASEES0 (0x30 << NVMCTRL_CTRLB_CMD_SHIFT) /* Configure SmartEEPROM Sector 0 */
# define NVMCTRL_CTRLB_CMD_ASEES1 (0x31 << NVMCTRL_CTRLB_CMD_SHIFT) /* Configure SmartEEPROM Sector 1 */
# define NVMCTRL_CTRLB_CMD_SEERALOC (0x32 << NVMCTRL_CTRLB_CMD_SHIFT) /* SmartEEPROM sector reallocation */
# define NVMCTRL_CTRLB_CMD_SEEFLSUH (0x33 << NVMCTRL_CTRLB_CMD_SHIFT) /* Flush SmartEEPROM data1 */
# define NVMCTRL_CTRLB_CMD_LSEE (0x34 << NVMCTRL_CTRLB_CMD_SHIFT) /* Lock SmartEEPROM data */
# define NVMCTRL_CTRLB_CMD_USEE (0x35 << NVMCTRL_CTRLB_CMD_SHIFT) /* Unlock SmartEEPROM data*/
# define NVMCTRL_CTRLB_CMD_LSEER (0x36 << NVMCTRL_CTRLB_CMD_SHIFT) /* Lock SmartEEPROM registers */
# define NVMCTRL_CTRLB_CMD_USEER (0x37 << NVMCTRL_CTRLB_CMD_SHIFT) /* Unlock SmartEEPROM registers */
#define NVMCTRL_CTRLB_CMDEX_SHIFT (8) /* Bits 8-15: Command Execution */
#define NVMCTRL_CTRLB_CMDEX_MASK (0xff << NVMCTRL_CTRLB_CMDEX_SHIFT)
# define NVMCTRL_CTRLB_CMDEX_KEY (0xa5 << NVMCTRL_CTRLB_CMDEX_SHIFT)
/* NVM parameter register */
#define NVMCTRL_PARAM_NVMP_SHIFT (0) /* Bits 0-15: NVM Pages */
#define NVMCTRL_PARAM_NVMP_MASK (0xffff << NVMCTRL_PARAM_NVMP_SHIFT)
# define NVMCTRL_PARAM_NVMP(n) ((uint32_t)(n) << NVMCTRL_PARAM_NVMP_SHIFT)
#define NVMCTRL_PARAM_PSZ_SHIFT (16) /* Bits 16-18: Page Size */
#define NVMCTRL_PARAM_PSZ_MASK (7 << NVMCTRL_PARAM_PSZ_SHIFT)
# define NVMCTRL_PARAM_PSZ_8B (0 << NVMCTRL_PARAM_PSZ_SHIFT) /* 8 bytes */
# define NVMCTRL_PARAM_PSZ_16B (1 << NVMCTRL_PARAM_PSZ_SHIFT) /* 16 bytes */
# define NVMCTRL_PARAM_PSZ_32B (2 << NVMCTRL_PARAM_PSZ_SHIFT) /* 32 bytes */
# define NVMCTRL_PARAM_PSZ_64B (3 << NVMCTRL_PARAM_PSZ_SHIFT) /* 64 bytes */
# define NVMCTRL_PARAM_PSZ_128B (4 << NVMCTRL_PARAM_PSZ_SHIFT) /* 128 bytes */
# define NVMCTRL_PARAM_PSZ_256B (5 << NVMCTRL_PARAM_PSZ_SHIFT) /* 256 bytes */
# define NVMCTRL_PARAM_PSZ_512B (6 << NVMCTRL_PARAM_PSZ_SHIFT) /* 512 bytes */
# define NVMCTRL_PARAM_PSZ_1KB (7 << NVMCTRL_PARAM_PSZ_SHIFT) /* 1024 bytes */
#define NVMCTRL_PARAM_SEE_ (1 << 31) /* Bit 31: SmartEEPROM Supported */
/* Interrupt clear register */
/* Interrupt set register */
/* Interface flags status and clear register */
#define NVMCTRL_INT_DONE (1 << 0) /* Bit 0: Command done interrupt */
#define NVMCTRL_INT_ADDRE (1 << 1) /* Bit 1: Address error interrupt */
#define NVMCTRL_INT_PROGE (1 << 2) /* Bit 2: Programming Error Status */
#define NVMCTRL_INT_LOCKE (1 << 3) /* Bit 3: Lock Error Status */
#define NVMCTRL_INT_ECCSE (1 << 4) /* Bit 4: ECC single error interrupt */
#define NVMCTRL_INT_ECCDE (1 << 5) /* Bit 5: ECC dual error interrupt */
#define NVMCTRL_INT_NVME (1 << 6) /* Bit 6: NVM error interrupt */
#define NVMCTRL_INT_SUSP (1 << 7) /* Bit 7: Suspended write or erase interrupt */
#define NVMCTRL_INT_SEESFULL (1 << 8) /* Bit 8: Active SEES full interrupt */
#define NVMCTRL_INT_SEESOVF (1 << 9) /* Bit 9: Active SEES overflow interrupt */
#define NVMCTRL_INT_SEEWRC (1 << 10) /* Bit 10: SEE Write completed interrupt */
/* Status register */
#define NVMCTRL_STATUS_READY (1 << 0) /* Bit 0: Ready to accept a command */
#define NVMCTRL_STATUS_PRM (1 << 1) /* Bit 1: Power reduction mode */
#define NVMCTRL_STATUS_LOAD (1 << 2) /* Bit 2: NVM Page Buffer active loading */
#define NVMCTRL_STATUS_SUSP (1 << 3) /* Bit 3: NVM Write or erase operation suspended */
#define NVMCTRL_STATUS_AFIRST (1 << 4) /* Bit 2: BANKA first */
#define NVMCTRL_STATUS_BPDIS (1 << 5) /* Bit 5: Boot loader protection disable */
#define NVMCTRL_STATUS_BOOTPROT_SHIFT (8) /* Bits 8-11: Boot loader protection size */
#define NVMCTRL_STATUS_BOOTPROT_MASK (15 << NVMCTRL_STATUS_BOOTPROT_SHIFT)
# define NVMCTRL_STATUS_BOOTPROT(n) ((uint16_t)(n) << NVMCTRL_STATUS_BOOTPROT_SHIFT)
/* Address register */
#define NVMCTRL_ADDR_MASK (0x00ffffff) /* Bits 0-23: NVM Address */
/* Lock section register */
#define NVMCTRL_RUNLOCK_REGION(n) (1 << (n)) /* Region n is locked */
/* Page buffer load data n 0/1 (32-bit data) */
/* ECC error status register */
#define NVMCTRL_ECCERR_ADDR_SHIFT (0) /* Bits 0-23: Error address */
#define NVMCTRL_ECCERR_ADDR_MASK (0xffffff << NVMCTRL_ECCERR_ADDR_SHIFT)
# define NVMCTRL_ECCERR_ADDR(n) ((uint32_t)(n) << NVMCTRL_ECCERR_ADDR_SHIFT)
#define NVMCTRL_ECCERR_TYPEL_SHIFT (28) /* Bits 28-29: Low double-word error type */
#define NVMCTRL_ECCERR_TYPEL_MASK (3 << NVMCTRL_ECCERR_TYPEL_SHIFT)
# define NVMCTRL_ECCERR_TYPEL_NONE (0 << NVMCTRL_ECCERR_TYPEL_SHIFT) /* No error detected */
# define NVMCTRL_ECCERR_TYPEL_SINGLE (1 << NVMCTRL_ECCERR_TYPEL_SHIFT) /* Single error(s) detected */
# define NVMCTRL_ECCERR_TYPEL_DUAL (2 << NVMCTRL_ECCERR_TYPEL_SHIFT) /* Dual error(s) detected */
#define NVMCTRL_ECCERR_TYPEH_SHIFT (30) /* Bits 30-31: High double-word error type */
#define NVMCTRL_ECCERR_TYPEH_MASK (3 << NVMCTRL_ECCERR_TYPEH_SHIFT)
# define NVMCTRL_ECCERR_TYPEH_NONE (0 << NVMCTRL_ECCERR_TYPEH_SHIFT) /* No error detected */
# define NVMCTRL_ECCERR_TYPEH_SINGLE (1 << NVMCTRL_ECCERR_TYPEH_SHIFT) /* Single error(s) detected */
# define NVMCTRL_ECCERR_TYPEH_DUAL (2 << NVMCTRL_ECCERR_TYPEH_SHIFT) /* Dual error(s) detected */
/* Debug control register */
#define NVMCTRL_DBGCTRL_ECCDIS (1 << 0) /* Bit 0: Debugger ECC read disable */
#define NVMCTRL_DBGCTRL_ECCELOG (1 << 1) /* Bit 1: Debugger ECC error tracking mode */
/* SmartEEPROM configuration register */
#define NVMCTRL_SEECFG_WMODE (1 << 0) /* Bit 0: Write mode */
#define NVMCTRL_SEECFG_APRDIS (1 << 1) /* Bit 1: Automatic page reallocation disable */
/* SmartEEPROM status register */
#define NVMCTRL_SEESTAT_ASEES (1 << 0) /* Bit 0: Active SmartEEPROM Sector */
#define NVMCTRL_SEESTAT_LOAD (1 << 1) /* Bit 1: Page buffer loaded */
#define NVMCTRL_SEESTAT_BUSY (1 << 2) /* Bit 2: Busy */
#define NVMCTRL_SEESTAT_LOCK (1 << 3) /* Bit 3: SmartEEPROM section locked */
#define NVMCTRL_SEESTAT_RLOCK (1 << 4) /* Bit 4: RLOCK */
#define NVMCTRL_SEESTAT_SBLK_SHIFT (8) /* Bits 8-11: Blocks number in a sector */
#define NVMCTRL_SEESTAT_SBLK_MASK (15 << NVMCTRL_SEESTAT_SBLK_SHIFT)
# define NVMCTRL_SEESTAT_SBLK(n) ((uint32_t)(n) << NVMCTRL_SEESTAT_SBLK_SHIFT)
#define NVMCTRL_SEESTAT_PSZ_SHIFT (16) /* Bits 16-18: SmartEEPROM page size */
#define NVMCTRL_SEESTAT_PSZ_MASK (7 << NVMCTRL_SEESTAT_PSZ_SHIFT)
# define NVMCTRL_SEESTAT_PSZ(n) ((uint32_t)(n) << NVMCTRL_SEESTAT_PSZ_SHIFT)
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_NVMCTRL_H */
arch/arm/src/samd5e5/chip/sam_osc32kctrl.h
+151
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/********************************************************************************************
* arch/arm/src/samd5e5/chip/sam_osc32kctrl.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_OSC32KCTRL_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_OSC32KCTRL_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* OSC32KCTRL register offsets **************************************************************/
#define SAM_OSC32KCTRL_INTENCLR_OFFSET 0x0000 /* Interrupt enable clear */
#define SAM_OSC32KCTRL_INTENSET_OFFSET 0x0004 /* Interrupt enable set */
#define SAM_OSC32KCTRL_INTFLAG_OFFSET 0x0008 /* Interrupt flag status and clear */
#define SAM_OSC32KCTRL_STATUS_OFFSET 0x000c /* Status */
#define SAM_OSC32KCTRL_RTCCTRL_OFFSET 0x0010 /* RTC clock selection */
#define SAM_OSC32KCTRL_XOSC32K_OFFSET 0x0014 /* 32kHz external crystal oscillator control */
#define SAM_OSC32KCTRL_CFDCTRL_OFFSET 0x0016 /* Clock Failure Detector Control */
#define SAM_OSC32KCTRL_EVCTRL_OFFSET 0x0017 /* Event Control */
#define SAM_OSC32KCTRL_OSCULP32K_OFFSET 0x001c /* 32kHz ultra low power internal oscillator control */
/* OSC32KCTRL register addresses ************************************************************/
#define SAM_OSC32KCTRL_INTENCLR (SAM_OSC32KCTRL_BASE + SAM_OSC32KCTRL_INTENCLR_OFFSET)
#define SAM_OSC32KCTRL_INTENSET (SAM_OSC32KCTRL_BASE + SAM_OSC32KCTRL_INTENSET_OFFSET)
#define SAM_OSC32KCTRL_INTFLAG (SAM_OSC32KCTRL_BASE + SAM_OSC32KCTRL_INTFLAG_OFFSET)
#define SAM_OSC32KCTRL_STATUS (SAM_OSC32KCTRL_BASE + SAM_OSC32KCTRL_STATUS_OFFSET)
#define SAM_OSC32KCTRL_RTCCTRL (SAM_OSC32KCTRL_BASE + SAM_OSC32KCTRL_RTCCTRL_OFFSET)
#define SAM_OSC32KCTRL_XOSC32K (SAM_OSC32KCTRL_BASE + SAM_OSC32KCTRL_XOSC32K_OFFSET)
#define SAM_OSC32KCTRL_CFDCTRL (SAM_OSC32KCTRL_BASE + SAM_OSC32KCTRL_CFDCTRL_OFFSET )
#define SAM_OSC32KCTRL_EVCTRL (SAM_OSC32KCTRL_BASE + SAM_OSC32KCTRL_EVCTRL_OFFSET )
#define SAM_OSC32KCTRL_OSCULP32K (SAM_OSC32KCTRL_BASE + SAM_OSC32KCTRL_OSCULP32K_OFFSET)
/* OSC32KCTRL register bit definitions ******************************************************/
/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and clear, and
* status registers.
*/
#define OSC32KCTRL_INT_XOSC32KRDY (1 << 0) /* Bit 0: XOSC32K ready interrupt */
#define OSC32KCTRL_INT_XOSC32KFAIL (1 << 2) /* Bit 2: Clock failure detector interrupt */
#define OSC32KCTRL_STATUS_XOSC32KSW (1 << 3) /* Bit 3: XOSC32K Clock Switch */
#define OSC32KCTRL_INT_ALL (0x00000005)
/* RTC clock selection */
#define OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT (0) /* Bits 0-2: RTC clock source selection */
#define OSC32KCTRL_RTCCTRL_RTCSEL_MASK (7 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT)
# define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (0 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT) /* 1.024KHz from 32HKz internal ULP oscillator */
# define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (1 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT) /* 32.768KHz from 32KHz internal ULP oscillator */
# define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (4 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT) /* 1.024kHz from 32KHz external oscillator */
# define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC312K (5 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT) /* 32.768KHz from 32KHz external crystal oscillator */
/* 32kHz external crystal oscillator control register */
#define OSC32KCTRL_XOSC32K_ENABLE (1 << 1) /* Bit 1: Oscillator enable */
#define OSC32KCTRL_XOSC32K_XTALEN (1 << 2) /* Bit 2: Crystal oscillator enable */
#define OSC32KCTRL_XOSC32K_EN32K (1 << 3) /* Bit 3: 32kHz Output enable */
#define OSC32KCTRL_XOSC32K_EN1K (1 << 4) /* Bit 4: 1kHz Output enable */
#define OSC32KCTRL_XOSC32K_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
#define OSC32KCTRL_XOSC32K_ONDEMAND (1 << 7) /* Bit 7: On demand control */
#define OSC32KCTRL_XOSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */
#define OSC32KCTRL_XOSC32K_STARTUP_MASK (7 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT)
# define OSC32KCTRL_XOSC32K_STARTUP(n) ((n) << OSC32KCTRL_XOSC32K_STARTUP_SHIFT)
# define OSC32KCTRL_XOSC32K_STARTUP_63MS (0 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 62.592 msec */
# define OSC32KCTRL_XOSC32K_STARTUP_125MS (1 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 125.092 msec */
# define OSC32KCTRL_XOSC32K_STARTUP_500MS (2 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 500.092 msec */
# define OSC32KCTRL_XOSC32K_STARTUP_1S (3 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 1000.0092 msec */
# define OSC32KCTRL_XOSC32K_STARTUP_2S (4 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 2000.0092 msec */
# define OSC32KCTRL_XOSC32K_STARTUP_4S (5 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 4000.092 msec */
# define OSC32KCTRL_XOSC32K_STARTUP_8S (6 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 8000.0092 msec */
#define OSC32KCTRL_XOSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */
#define OSC32KCTRL_XOSC32K_GCM_SHIFT (13) /* Bits 13-14: Control Gain Mode */
#define OSC32KCTRL_XOSC32K_GCM_MASK (3 << OSC32KCTRL_XOSC32K_GCM_SHIFT)
# define OSC32KCTRL_XOSC32K_GCM_XT (1 << OSC32KCTRL_XOSC32K_GCM_SHIFT) /* Standard mode */
# define OSC32KCTRL_XOSC32K_GCM_HS (2 << OSC32KCTRL_XOSC32K_GCM_SHIFT) /* High Speed mode */
/* Clock Failure Detector Control */
#define OSC32KCTRL_CFDCTRL_CFDEN (1 << 0) /* Bit 0: Clock Failure Detector Enable */
#define OSC32KCTRL_CFDCTRL_SWBACK (1 << 1) /* Bit 1: Clock Switch Back */
#define OSC32KCTRL_CFDCTRL_CFDPRESC (1 << 2) /* Bit 2: Clock Failure Detector Prescaler */
/* Event Control */
#define OSC32KCTRL_EVCTRL_CFDEO (1 << 0) /* Bit 0: Clock Failure Detector Event Out Enable */
/* 32kHz ultra low power internal oscillator control register */
#define OSC32KCTRL_OSCULP32K_EN32K (1 << 0) /* Bit 0: 32kHz Output Enable */
#define OSC32KCTRL_OSCULP32K_EN1K (1 << 1) /* Bit 1: 1kHz Output Enable */
#define OSC32KCTRL_OSCULP32K_CALIB_SHIFT (8) /* Bits 8-13: Oscillator Calibration */
#define OSC32KCTRL_OSCULP32K_CALIB_MASK (0x3f << OSC32KCTRL_OSCULP32K_CALIB_SHIFT)
# define OSC32KCTRL_OSCULP32K_CALIB(n) ((uint16_t)(n) << OSC32KCTRL_OSCULP32K_CALIB_SHIFT)
#define OSC32KCTRL_OSCULP32K_WRTLOCK (1 << 15) /* Bit 15: Write Lock */
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_OSC32KCTRL_H */
arch/arm/src/samd5e5/chip/sam_oscctrl.h
+311
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/********************************************************************************************
* arch/arm/src/samd5e5/chip/sam_oscctrl.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_OSCCTRL_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_OSCCTRL_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* OSCCTRL register offsets *****************************************************************/
#define SAM_OSCCTRL_EVCTRL_OFFSET 0x0000 /* Event Control */
#define SAM_OSCCTRL_INTENCLR_OFFSET 0x0004 /* Interrupt enable clear */
#define SAM_OSCCTRL_INTENSET_OFFSET 0x0008 /* Interrupt enable set */
#define SAM_OSCCTRL_INTFLAG_OFFSET 0x000c /* Interrupt flag status and clear */
#define SAM_OSCCTRL_STATUS_OFFSET 0x0010 /* Status */
#define SAM_OSCCTRL_XOSCCTRL0_OFFSET 0x0014 /* External multi-purpose crystal oscillator control 0 */
#define SAM_OSCCTRL_XOSCCTRL1_OFFSET 0x0018 /* External multi-purpose crystal oscillator control 1 */
#define SAM_OSCCTRL_DFLLCTRLA_OFFSET 0x001c /* DFLL48M Control A */
#define SAM_OSCCTRL_DFLLCTRLB_OFFSET 0x0020 /* DFLL48M Control B */
#define SAM_OSCCTRL_DFLLVAL_OFFSET 0x0024 /* DFLL48M value */
#define SAM_OSCCTRL_DFLLMUL_OFFSET 0x0028 /* DFLL48M multiplier */
#define SAM_OSCCTRL_DFLLSYNC_OFFSET 0x002c /* DFLL48M synchronization */
#define SAM_OSCCTRL_DPLL0CTRLA_OFFSET 0x0030 /* DPLL0 control A */
#define SAM_OSCCTRL_DPLL0RATIO_OFFSET 0x0034 /* DPLL0 ratio control */
#define SAM_OSCCTRL_DPLL0CTRLB_OFFSET 0x0038 /* DPLL0 control B */
#define SAM_OSCCTRL_DPLL0SYNCBUSY_OFFSET 0x003c /* DPLL0 synchronization busy */
#define SAM_OSCCTRL_DPLL0STATUS_OFFSET 0x0040 /* DPLL0 status */
#define SAM_OSCCTRL_DPLL1CTRLA_OFFSET 0x0044 /* DPLL1 control A */
#define SAM_OSCCTRL_DPLL1RATIO_OFFSET 0x0048 /* DPLL1 ratio control */
#define SAM_OSCCTRL_DPLL1CTRLB_OFFSET 0x004c /* DPLL1 control B */
#define SAM_OSCCTRL_DPLL1SYNCBUSY_OFFSET 0x0050 /* DPLL1 synchronization busy */
#define SAM_OSCCTRL_DPLL1STATUS_OFFSET 0x0054 /* DPLL1 status */
/* OSCCTRL register addresses ***************************************************************/
#define SAM_OSCCTRL_EVCTRL (SAM_OSCCTRL_BASE + SAM_OSCCTRL_EVCTRL_OFFSET)
#define SAM_OSCCTRL_INTENCLR (SAM_OSCCTRL_BASE + SAM_OSCCTRL_INTENCLR_OFFSET)
#define SAM_OSCCTRL_INTENSET (SAM_OSCCTRL_BASE + SAM_OSCCTRL_INTENSET_OFFSET)
#define SAM_OSCCTRL_INTFLAG (SAM_OSCCTRL_BASE + SAM_OSCCTRL_INTFLAG_OFFSET)
#define SAM_OSCCTRL_STATUS (SAM_OSCCTRL_BASE + SAM_OSCCTRL_STATUS_OFFSET)
#define SAM_OSCCTRL_XOSCCTRL0 (SAM_OSCCTRL_BASE + SAM_OSCCTRL_XOSCCTRL0_OFFSET)
#define SAM_OSCCTRL_XOSCCTRL1 (SAM_OSCCTRL_BASE + SAM_OSCCTRL_XOSCCTRL1_OFFSET)
#define SAM_OSCCTRL_DFLLCTRLA (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DFLLCTRLA_OFFSET)
#define SAM_OSCCTRL_DFLLCTRLB (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DFLLCTRLB_OFFSET)
#define SAM_OSCCTRL_DFLLVAL (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DFLLVAL_OFFSET)
#define SAM_OSCCTRL_DFLLMUL (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DFLLMUL_OFFSET)
#define SAM_OSCCTRL_DFLLSYNC (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DFLLSYNC_OFFSET)
#define SAM_OSCCTRL_DPLL0CTRLA (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL0CTRLA_OFFSET)
#define SAM_OSCCTRL_DPLL0RATIO (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL0RATIO_OFFSET)
#define SAM_OSCCTRL_DPLL0CTRLB (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL0CTRLB_OFFSET)
#define SAM_OSCCTRL_DPLLPRESC (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLLPRESC_OFFSET)
#define SAM_OSCCTRL_DPLL0SYNCBUSY (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL0SYNCBUSY_OFFSET)
#define SAM_OSCCTRL_DPLL0STATUS (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL0STATUS_OFFSET)
#define SAM_OSCCTRL_DPLL1CTRLA (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL1CTRLA_OFFSET)
#define SAM_OSCCTRL_DPLL1RATIO (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL1RATIO_OFFSET)
#define SAM_OSCCTRL_DPLL1CTRLB (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL1CTRLB_OFFSET)
#define SAM_OSCCTRL_DPLLPRESC (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLLPRESC_OFFSET)
#define SAM_OSCCTRL_DPLL1SYNCBUSY (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL1SYNCBUSY_OFFSET)
#define SAM_OSCCTRL_DPLL1STATUS (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL1STATUS_OFFSET)
/* OSCCTRL register bit definitions *********************************************************/
/* Event Control */
#define OSCCTRL_EVCTRL_CFDEO0 (1 << 0) /* Bit 0: Clock 0 failure detector event output enable */
#define OSCCTRL_EVCTRL_CFDEO1 (1 << 1) /* Bit 1: Clock 1 failure detector event output enable */
/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and clear, and
* Status registers.
*/
#define OSCCTRL_INT_XOSCRDY0 (1 << 0) /* Bit 0: XOSC 0 ready interrupt */
#define OSCCTRL_INT_XOSCRDY1 (1 << 1) /* Bit 1: XOSC 1 ready interrupt */
#define OSCCTRL_INT_XOSCFAIL0 (1 << 2) /* Bit 2: XOSC 0 clock failure interrupt */
#define OSCCTRL_INT_XOSCFAIL1 (1 << 3) /* Bit 3: XOSC 1 clock failure interrupt */
#define OSCCTRL_STATUS_XOSCCKSW0 (1 << 4) /* Bit 4: XOSC 1 clock failure interrupt (status) */
#define OSCCTRL_STATUS_XOSCCKSW1 (1 << 5) /* Bit 5: XOSC 1 clock failure interrupt (status) */
#define OSCCTRL_INT_DFLLRDY (1 << 8) /* Bit 8: DFLL ready interrupt */
#define OSCCTRL_INT_DFLLOOB (1 << 9) /* Bit 9: DFLL out of bounds interrupt */
#define OSCCTRL_INT_DFLLLCKF (1 << 10) /* Bit 10: DFLL lock fine interrupt */
#define OSCCTRL_INT_DFLLLCKC (1 << 11) /* Bit 11: DFLL lock coarse interrupt */
#define OSCCTRL_INT_DFLLRCS (1 << 12) /* Bit 12: DFLL reference clock stopped interrupt */
#define OSCCTRL_INT_DPLL0LCKR (1 << 16) /* Bit 16: DPLL0 lock rise interrupt */
#define OSCCTRL_INT_DPLL0LCKF (1 << 17) /* Bit 17: DPLL0 lock fall interrupt */
#define OSCCTRL_INT_DPLL0LTO (1 << 18) /* Bit 18: DPLL0 lock timeout */
#define OSCCTRL_INT_DPLL0DRTO (1 << 19) /* Bit 19: DPLL0 loop divider ratio update complete */
#define OSCCTRL_INT_DPLL1LCKR (1 << 24) /* Bit 24: DPLL1 lock rise interrupt */
#define OSCCTRL_INT_DPLL1LCKF (1 << 25) /* Bit 25: DPLL1 lock fall interrupt */
#define OSCCTRL_INT_DPLL1LTO (1 << 26) /* Bit 26: DPLL1 lock timeout */
#define OSCCTRL_INT_DPLL1DRTO (1 << 27) /* Bit 27: DPLL1 loop divider ratio update complete */
#define OSCCTRL_INT_ALL (0x0f0f1f0f)
/* External multi-purpose crystal oscillator control register 0/1 */
#define OSCCTRL_XOSCCTRL_ENABLE (1 << 1) /* Bit 1: Oscillator enable */
#define OSCCTRL_XOSCCTRL_XTALEN (1 << 2) /* Bit 2: Crystal oscillator enable */
#define OSCCTRL_XOSCCTRL_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
#define OSCCTRL_XOSCCTRL_ONDEMAND (1 << 7) /* Bit 7: On demand control */
#define OSCCTRL_XOSCCTRL_LOWBUFGAIN (1 << 8) /* Bit 8: Low buffer gain enable */
#define OSCCTRL_XOSCCTRL_IPTAT_SHIFT (9) /* Bits 9-10: Oscillator current reference */
#define OSCCTRL_XOSCCTRL_IPTAT_MASK (3 << OSCCTRL_XOSCCTRL_IPTAT_SHIFT)
# define OSCCTRL_XOSCCTRL_IPTAT(n) ((uint32_t)(n) << OSCCTRL_XOSCCTRL_IPTAT_SHIFT)
#define OSCCTRL_XOSCCTRL_IMULT_SHIFT (11) /* Bits 11-14: Oscillator current reference */
#define OSCCTRL_XOSCCTRL_IMULT_MASK (15 << OSCCTRL_XOSCCTRL_IMULT_SHIFT)
# define OSCCTRL_XOSCCTRL_IMULT(n) ((uint32_t)(n) << OSCCTRL_XOSCCTRL_IMULT_SHIFT)
#define OSCCTRL_XOSCCTRL_ENALC (1 << 15) /* Bit 15: Automatic loop control enable */
#define OSCCTRL_XOSCCTRL_CFDEN (1 << 16) /* Bit 16: Clock failure detector enable */
#define OSCCTRL_XOSCCTRL_SWBEN (1 << 17) /* Bit 17: XOSC clock switch enable */
#define OSCCTRL_XOSCCTRL_STARTUP_SHIFT (20) /* Bits 20-23: Start-up time */
#define OSCCTRL_XOSCCTRL_STARTUP_MASK (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT)
# define OSCCTRL_XOSCCTRL_STARTUP(n) ((n) << OSCCTRL_XOSCCTRL_STARTUP_SHIFT)
# define OSCCTRL_XOSCCTRL_STARTUP_31US (0 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31µs */
# define OSCCTRL_XOSCCTRL_STARTUP_61US (1 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 61µs */
# define OSCCTRL_XOSCCTRL_STARTUP_122US (2 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 122µs */
# define OSCCTRL_XOSCCTRL_STARTUP_244US (3 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 244µs */
# define OSCCTRL_XOSCCTRL_STARTUP_488US (4 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 488µs */
# define OSCCTRL_XOSCCTRL_STARTUP_977US (5 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 977µs */
# define OSCCTRL_XOSCCTRL_STARTUP_2MS (6 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1953µs */
# define OSCCTRL_XOSCCTRL_STARTUP_4MS (7 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 3906µs */
# define OSCCTRL_XOSCCTRL_STARTUP_8MS (8 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 7813µs */
# define OSCCTRL_XOSCCTRL_STARTUP_16MS (9 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 15625µs */
# define OSCCTRL_XOSCCTRL_STARTUP_31MS (10 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31250µs */
# define OSCCTRL_XOSCCTRL_STARTUP_63MS (11 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 62500µs */
# define OSCCTRL_XOSCCTRL_STARTUP_125MS (12 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 125000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_250MS (13 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 250000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_500MS (14 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 500000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_1S (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1000000µs */
/* DFLL48M control register A */
#define OSCCTRL_DFLLCTRLA_ENABLE (1 << 1) /* Bit 1: DFLL enable */
#define OSCCTRL_DFLLCTRLA_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
#define OSCCTRL_DFLLCTRLA_ONDEMAND (1 << 7) /* Bit 7: On demand control */
/* DFLL48M control register B */
#define OSCCTRL_DFLLCTRLB_MODE (1 << 0) /* Bit 0: Operating mode selection */
#define OSCCTRL_DFLLCTRLB_STABLE (1 << 1) /* Bit 1: Stable DFLL frequency */
#define OSCCTRL_DFLLCTRLB_LLAW (1 << 2) /* Bit 2: Lose lock after wake */
#define OSCCTRL_DFLLCTRLB_USBCRM (1 << 3) /* Bit 3: USB clock recovery mode */
#define OSCCTRL_DFLLCTRLB_CCDIS (1 << 4) /* Bit 4: Chill cycle disable */
#define OSCCTRL_DFLLCTRLB_QLDIS (1 << 5) /* Bit 5: Quick Lock Disable */
#define OSCCTRL_DFLLCTRLB_BPLCKC (1 << 6) /* Bit 6: Bypass coarse clock */
#define OSCCTRL_DFLLCTRLB_WAITLOCK (1 << 7) /* Bit 7: Wait lock */
/* DFLL48M value register */
#define OSCCTRL_DFLLVAL_FINE_SHIFT (0) /* Bits 0-7: Fine value */
#define OSCCTRL_DFLLVAL_FINE_MASK (0xff << OSCCTRL_DFLLVAL_FINE_SHIFT)
# define OSCCTRL_DFLLVAL_FINE(n) ((uint32_t)(n) << OSCCTRL_DFLLVAL_FINE_SHIFT)
#define OSCCTRL_DFLLVAL_COARSE_SHIFT (10) /* Bits 10-15: Coarse value */
#define OSCCTRL_DFLLVAL_COARSE_MASK (0x3f << OSCCTRL_DFLLVAL_COARSE_SHIFT)
# define OSCCTRL_DFLLVAL_COARSE(n) ((uint32_t)(n) << OSCCTRL_DFLLVAL_COARSE_SHIFT)
#define OSCCTRL_DFLLVAL_DIFF_SHIFT (16) /* Bits 16-31: Multiplication ratio difference */
#define OSCCTRL_DFLLVAL_DIFF_MASK (0xffff << OSCCTRL_DFLLVAL_DIFF_SHIFT)
# define OSCCTRL_DFLLVAL_DIFF(n) ((n) << OSCCTRL_DFLLVAL_DIFF_SHIFT)
/* DFLL48M multiplier register */
#define OSCCTRL_DFLLMUL_MUL_SHIFT (0) /* Bits 0-15: DFLL multiply factor */
#define OSCCTRL_DFLLMUL_MUL_MASK (0xffff << OSCCTRL_DFLLMUL_MUL_SHIFT)
# define OSCCTRL_DFLLMUL_MUL(n) ((uint32_t)(n) << OSCCTRL_DFLLMUL_MUL_SHIFT)
#define OSCCTRL_DFLLMUL_FSTEP_SHIFT (16) /* Bits 16-23: Fine maximum step */
#define OSCCTRL_DFLLMUL_FSTEP_MASK (0xff << OSCCTRL_DFLLMUL_FSTEP_SHIFT)
# define OSCCTRL_DFLLMUL_FSTEP(n) ((uint32_t)(n) << OSCCTRL_DFLLMUL_FSTEP_SHIFT)
#define OSCCTRL_DFLLMUL_CSTEP_SHIFT (26) /* Bits 26-31: Coarse maximum step */
#define OSCCTRL_DFLLMUL_CSTEP_MASK (0x3f << OSCCTRL_DFLLMUL_CSTEP_SHIFT)
# define OSCCTRL_DFLLMUL_CSTEP(n) ((uint32_t)(n) << OSCCTRL_DFLLMUL_CSTEP_SHIFT)
/* DFLL48M synchronization register */
#define OSCCTRL_DFLLSYNC_ENABLE (1 << 1) /* Bit 1: ENABLE Synchronization Busy */
#define OSCCTRL_DFLLSYNC_DFLLCTRLB (1 << 2) /* Bit 2: DFLLCTRLB Synchronization Busy */
#define OSCCTRL_DFLLSYNC_DFLLVAL (1 << 3) /* Bit 3: DFLLVAL Synchronization Busy */
#define OSCCTRL_DFLLSYNC_REDFLLMULADREQ (1 << 4) /* Bit 4: DFLLMUL Synchronization Busy */
/* DPLL0/1 control A */
#define OSCCTRL_DPLLCTRLA_ENABLE (1 << 1) /* Bit 1: DPLL enable */
#define OSCCTRL_DPLLCTRLA_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
#define OSCCTRL_DPLLCTRLA_ONDEMAND (1 << 7) /* Bit 7: On demand clock activation */
/* DPLL0/1 ratio control */
#define OSCCTRL_DPLLRATIO_LDR_SHIFT (0) /* Bits 0-11: Loop divider ratio */
#define OSCCTRL_DPLLRATIO_LDR_MASK (0x1fff << OSCCTRL_DPLLRATIO_LDR_SHIFT)
# define OSCCTRL_DPLLRATIO_LDR(n) ((uint32_t)(n) << OSCCTRL_DPLLRATIO_LDR_SHIFT)
#define OSCCTRL_DPLLRATIO_LDRFRAC_SHIFT (16) /* Bits 16-20: Loop divider fractional part */
#define OSCCTRL_DPLLRATIO_LDRFRAC_MASK (31 << OSCCTRL_DPLLRATIO_LDRFRAC_SHIFT)
# define OSCCTRL_DPLLRATIO_LDRFRAC(n) ((uint32_t)(n) << OSCCTRL_DPLLRATIO_LDRFRAC_SHIFT)
/* DPLL0/1 control B */
#define OSCCTRL_DPLLCTRLB_FILTER_SHIFT (0) /* Bits 0-3: Proportional integer filter selection */
#define OSCCTRL_DPLLCTRLB_FILTER_MASK (15 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT)
# define OSCCTRL_DPLLCTRLB_FILTER(n) ((uint32_t)(n) << OSCCTRL_DPLLCTRLB_FILTER_SHIFT)
/* PLL BW Damping */
# define OSCCTRL_DPLLCTRLB_FILTER0 (0 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 92.7 kHz 0.76 */
# define OSCCTRL_DPLLCTRLB_FILTER1 (1 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 131 kHz 1.08 */
# define OSCCTRL_DPLLCTRLB_FILTER2 (2 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 46.4 kHz 0.38 */
# define OSCCTRL_DPLLCTRLB_FILTER3 (3 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 65.6 kHz 0.54 */
# define OSCCTRL_DPLLCTRLB_FILTER4 (4 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 131 kHz 0.56 */
# define OSCCTRL_DPLLCTRLB_FILTER5 (5 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 185 kHz 0.79 */
# define OSCCTRL_DPLLCTRLB_FILTER6 (6 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 65.6 kHz 0.28 */
# define OSCCTRL_DPLLCTRLB_FILTER7 (7 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 92.7 kHz 0.39 */
# define OSCCTRL_DPLLCTRLB_FILTER8 (8 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 46.4 kHz 1.49 */
# define OSCCTRL_DPLLCTRLB_FILTER9 (9 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 65.6 kHz 2.11 */
# define OSCCTRL_DPLLCTRLB_FILTER10 (10 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 23.2 kHz 0.75 */
# define OSCCTRL_DPLLCTRLB_FILTER11 (11 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 32.8 kHz 1.06 */
# define OSCCTRL_DPLLCTRLB_FILTER12 (12 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 65.6 kHz 1.07 */
# define OSCCTRL_DPLLCTRLB_FILTER13 (13 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 92.7 kHz 1.51 */
# define OSCCTRL_DPLLCTRLB_FILTER14 (14 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 32.8 kHz 0.53 */
# define OSCCTRL_DPLLCTRLB_FILTER15 (15 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 46.4 kHz 0.75 */
#define OSCCTRL_DPLLCTRLB_WUF (1 << 4) /* Bit 4: Wake up fast */
#define OSCCTRL_DPLLCTRLB_REFLCK_SHIFT (5) /* Bits 5-7: Reference clock selection */
#define OSCCTRL_DPLLCTRLB_REFLCK_MASK (3 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT)
# define OSCCTRL_DPLLCTRLB_REFLCK_GLCK (0 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* Dedicated GCLK clock reference */
# define OSCCTRL_DPLLCTRLB_REFLCK_XOSC32 (1 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC32K clock reference (default) */
# define OSCCTRL_DPLLCTRLB_REFLCK_XOSC0 (2 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC0 clock reference */
# define OSCCTRL_DPLLCTRLB_REFLCK_XOSC1 (3 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC2 clock reference */
#define OSCCTRL_DPLLCTRLB_LTIME_SHIFT (8) /* Bits 8-10: Lock time */
#define OSCCTRL_DPLLCTRLB_LTIME_MASK (7 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT)
# define OSCCTRL_DPLLCTRLB_LTIME_NONE (0 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* No time-out. Automatic lock */
# define OSCCTRL_DPLLCTRLB_LTIME_800US (4 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no locka within 800 us */
# define OSCCTRL_DPLLCTRLB_LTIME_900US (5 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no locka within 900 us */
# define OSCCTRL_DPLLCTRLB_LTIME_1MS (6 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no locka within 1MS */
# define OSCCTRL_DPLLCTRLB_LTIME_1p1MS (7 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no locka within 1.1MS */
#define OSCCTRL_DPLLCTRLB_LBYPASS (1 << 11) /* Bit 11: Lock bypass */
#define OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT (12) /* Bits 12-14: Sigma-Delta DCO Filter Selection */
#define OSCCTRL_DPLLCTRLB_DCOFILTER_MASK (7 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT)
# define OSCCTRL_DPLLCTRLB_DCOFILTER(n) ((uint32_t)(n) << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT)
/* Capa pF BW MHz */
# define OSCCTRL_DPLLCTRLB_DCOFILTER0 (0 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 0.5 3.21 */
# define OSCCTRL_DPLLCTRLB_DCOFILTER1 (1 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 1 1.6 */
# define OSCCTRL_DPLLCTRLB_DCOFILTER2 (2 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 1.5 1.1 */
# define OSCCTRL_DPLLCTRLB_DCOFILTER3 (3 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 2 0.8 */
# define OSCCTRL_DPLLCTRLB_DCOFILTER4 (4 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 2.5 0.64 */
# define OSCCTRL_DPLLCTRLB_DCOFILTER5 (5 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 3 0.55 */
# define OSCCTRL_DPLLCTRLB_DCOFILTER6 (6 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 3.5 0.45 */
# define OSCCTRL_DPLLCTRLB_DCOFILTER7 (7 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 4 0.4 */
#define OSCCTRL_DPLLCTRLB_DCOEN (1 << 15) /* Bit 15: DCO Filter Enable */
#define OSCCTRL_DPLLCTRLB_DIV_SHIFT (16) /* Bits 16-26: Clock divider */
#define OSCCTRL_DPLLCTRLB_DIV_MASK (0x7ff << OSCCTRL_DPLLCTRLB_DIV_SHIFT)
# define OSCCTRL_DPLLCTRLB_DIV(n) ((uint32_t)(n) << OSCCTRL_DPLLCTRLB_DIV_SHIFT)
/* DPLL0 synchronization busy */
#define OSCCTRL_DPLL0STATUS_ENABLE (1 << 1) /* Bit 1: DPLL enable synchronization status */
#define OSCCTRL_DPLL0STATUS_DPLLRATIO (1 << 2) /* Bit 2: DPLL loop divider ratio synchronization status */
/* DPLL0 status */
#define OSCCTRL_DPLL0STATUS_LOCK (1 << 0) /* Bit 0: DPLL lock status */
#define OSCCTRL_DPLL0STATUS_CLKRDY (1 << 1) /* Bit 1: Output clock ready */
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_OSCCTRL_H */
arch/arm/src/samd5e5/chip/sam_pac.h
+268
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@@ -0,0 +1,268 @@
/********************************************************************************************
* arch/arm/src/samd5e5/chip/sam_pac.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PAC_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PAC_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* PAC register offsets *********************************************************************/
#define SAM_PAC_WRCTRL_OFFSET 0x0000 /* Write control */
#define SAM_PAC_EVCTRL_OFFSET 0x0004 /* Event control */
#define SAM_PAC_INTENCLR_OFFSET 0x0008 /* Interrupt enable clear */
#define SAM_PAC_INTENSET_OFFSET 0x0009 /* Interrupt enable set */
#define SAM_PAC_INTFLAGAHB_OFFSET 0x0010 /* Bridge interrupt flag status */
#define SAM_PAC_INTFLAGA_OFFSET 0x0014 /* Interrupt flag status bridge A */
#define SAM_PAC_INTFLAGB_OFFSET 0x0018 /* Interrupt flag status bridge B */
#define SAM_PAC_INTFLAGC_OFFSET 0x001c /* Interrupt flag status bridge C */
#define SAM_PAC_INTFLAGD_OFFSET 0x0020 /* Interrupt flag status bridge D */
#define SAM_PAC_STATUSA_OFFSET 0x0034 /* Write protection status bridge A */
#define SAM_PAC_STATUSB_OFFSET 0x0038 /* Write protection status bridge B */
#define SAM_PAC_STATUSC_OFFSET 0x003c /* Write protection status bridge C */
#define SAM_PAC_STATUSD_OFFSET 0x0040 /* Write protection status bridge D */
/* PAC register addresses *******************************************************************/
#define SAM_PAC_WRCTRL (SAM_PAC_BASE + SAM_PAC_WRCTRL_OFFSET)
#define SAM_PAC_EVCTRL (SAM_PAC_BASE + SAM_PAC_EVCTRL_OFFSET)
#define SAM_PAC_INTENCLR (SAM_PAC_BASE + SAM_PAC_INTENCLR_OFFSET)
#define SAM_PAC_INTENSET (SAM_PAC_BASE + SAM_PAC_INTENSET_OFFSET)
#define SAM_PAC_INTFLAGAHB (SAM_PAC_BASE + SAM_PAC_INTFLAGAHB_OFFSET)
#define SAM_PAC_INTFLAGA (SAM_PAC_BASE + SAM_PAC_INTFLAGA_OFFSET)
#define SAM_PAC_INTFLAGB (SAM_PAC_BASE + SAM_PAC_INTFLAGB_OFFSET)
#define SAM_PAC_INTFLAGC (SAM_PAC_BASE + SAM_PAC_INTFLAGC_OFFSET)
#define SAM_PAC_INTFLAGD (SAM_PAC_BASE + SAM_PAC_INTFLAGD_OFFSET)
#define SAM_PAC_STATUSA (SAM_PAC_BASE + SAM_PAC_STATUSA_OFFSET)
#define SAM_PAC_STATUSB (SAM_PAC_BASE + SAM_PAC_STATUSB_OFFSET)
#define SAM_PAC_STATUSC (SAM_PAC_BASE + SAM_PAC_STATUSC_OFFSET)
#define SAM_PAC_STATUSD (SAM_PAC_BASE + SAM_PAC_STATUSD_OFFSET)
/* PAC register bit definitions *************************************************************/
/* Write control */
#define PAC_WRCTRL_PERID_SHIFT (0) /* Bits 0-15: Peripheral Identifier */
#define PAC_WRCTRL_PERID_MASK (0xffff << PAC_WRCTRL_PERID_SHIFT)
# define PAC_WRCTRL_PERID(n) ((uint32_t)(n) << PAC_WRCTRL_PERID_SHIFT)
#define PAC_WRCTRL_KEY_SHIFT (16) /* Bits 16-23: Peripheral Access Control Key */
#define PAC_WRCTRL_KEY_MASK (0xff << PAC_WRCTRL_KEY_SHIFT)
# define PAC_WRCTRL_KEY_OFF (0 << PAC_WRCTRL_KEY_SHIFT) /* No action */
# define PAC_WRCTRL_KEY_CLEAR (1 << PAC_WRCTRL_KEY_SHIFT) /* Clear the peripheral write
* control */
# define PAC_WRCTRL_KEY_SET (2 << PAC_WRCTRL_KEY_SHIFT) /* Set the peripheral write
* control */
# define PAC_WRCTRL_KEY_LOCK (3 << PAC_WRCTRL_KEY_SHIFT) /* Set and lock the peripheral
* write control until the
* next hardware reset */
/* Event control */
#define PAC_EVCTRL_ERREO (1 << 0) /* Bit 0: Peripheral access error event output */
/* Interrupt enable clear, Interrupt enable set */
#define PAC_INTEN_ERR (1 << 0) /* Bit 0: Peripheral access error interrupt */
/* Bridge interrupt flag status */
#define PAC_INTFLAGAHB_NVMCTRL0 (1 << 0) /* Bit 0: Interrupt flag for NVMCTRL0 */
#define PAC_INTFLAGAHB_NVMCTRL1 (1 << 1) /* Bit 1: Interrupt flag for NVMCTRL1 */
#define PAC_INTFLAGAHB_NVMCTRL2 (1 << 2) /* Bit 2: Interrupt flag for NVMCTRL2 */
#define PAC_INTFLAGAHB_RAMCM4S (1 << 3) /* Bit 3: Interrupt flag for RAMCM4S */
#define PAC_INTFLAGAHB_RAMPPPDSU (1 << 4) /* Bit 4: Interrupt flag for RAMPPPDSU */
#define PAC_INTFLAGAHB_RAMDMAWR (1 << 5) /* Bit 5: Interrupt flag for RAMDMAWR */
#define PAC_INTFLAGAHB_RAMDMACICM (1 << 6) /* Bit 6: Interrupt flag for RAMDMACICM */
#define PAC_INTFLAGAHB_HPB0 (1 << 7) /* Bit 7: Interrupt flag for HPB0 */
#define PAC_INTFLAGAHB_HPB1 (1 << 8) /* Bit 8: Interrupt flag for HPB1 */
#define PAC_INTFLAGAHB_HPB2 (1 << 9) /* Bit 9: Interrupt flag for HPB2 */
#define PAC_INTFLAGAHB_HPB3 (1 << 0) /* Bit 10: Interrupt flag for HPB3 */
#define PAC_INTFLAGAHB_PUKCC (1 << 1) /* Bit 11: Interrupt flag for PUKCC */
#define PAC_INTFLAGAHB_SDHC0 (1 << 2) /* Bit 12: Interrupt flag for SDHC0 */
#define PAC_INTFLAGAHB_SDHC1 (1 << 3) /* Bit 13: Interrupt flag for SDHC1 */
#define PAC_INTFLAGAHB_QSPI (1 << 4) /* Bit 14: Interrupt flag for QSPI */
/* Interrupt flag status bridge A and Write protection status bridge A */
#define PAC_INTA_PAC (1 << 0) /* Bit 0: Interrupt for PAC */
#define PAC_INTA_PM (1 << 1) /* Bit 1: Interrupt for PM */
#define PAC_INTA_MCLK (1 << 2) /* Bit 2: Interrupt for MCLK */
#define PAC_INTA_RSTC (1 << 3) /* Bit 3: Interrupt for RSTC */
#define PAC_INTA_OSCCTRL (1 << 4) /* Bit 4: Interrupt for OSCCTRL */
#define PAC_INTA_OSC32KCTRL (1 << 5) /* Bit 5: Interrupt for OSC32KCTRL */
#define PAC_INTA_SUPC (1 << 6) /* Bit 6: Interrupt for SUPC */
#define PAC_INTA_GCLK (1 << 7) /* Bit 7: Interrupt for GCLK */
#define PAC_INTA_WDT (1 << 8) /* Bit 8: Interrupt for WDT */
#define PAC_INTA_RTC (1 << 9) /* Bit 9: Interrupt for RTC */
#define PAC_INTA_EIC (1 << 10) /* Bit 10: Interrupt for EIC */
#define PAC_INTA_FREQM (1 << 11) /* Bit 11: Interrupt for FREQM */
#define PAC_INTA_SERCOM0 (1 << 12) /* Bit 12: Interrupt for SERCOM0 */
#define PAC_INTA_SERCOM1 (1 << 13) /* Bit 13: Interrupt for SERCOM1 */
#define PAC_INTA_TC0 (1 << 14) /* Bit 14: Interrupt for TC0 */
#define PAC_INTA_TC1 (1 << 15) /* Bit 15: Interrupt for TC1 */
#define SAM_PAC_PERID ((0 << 5) + 0) /* PAC Peripheral IDs */
#define SAM_PM_PERID ((0 << 5) + 1)
#define SAM_MCLK_PERID ((0 << 5) + 2)
#define SAM_RSTC_PERID ((0 << 5) + 3)
#define SAM_OSCCTRL_PERID ((0 << 5) + 4)
#define SAM_OSC32KCTRL_PERID ((0 << 5) + 5)
#define SAM_SUPC_PERID ((0 << 5) + 6)
#define SAM_GCLK_PERID ((0 << 5) + 7)
#define SAM_WDT_PERID ((0 << 5) + 8)
#define SAM_RTC_PERID ((0 << 5) + 9)
#define SAM_EIC_PERID ((0 << 5) + 10)
#define SAM_FREQM_PERID ((0 << 5) + 11)
#define SAM_SERCOM0_PERID ((0 << 5) + 12)
#define SAM_SERCOM1_PERID ((0 << 5) + 13)
#define SAM_TC0_PERID ((0 << 5) + 14)
#define SAM_TC1_PERID ((0 << 5) + 15)
/* Interrupt flag status bridge B and Write protection status bridge B */
#define PAC_INTB_USB (1 << 0) /* Bit 0: Interrupt for USB */
#define PAC_INTB_DSU (1 << 1) /* Bit 1: Interrupt for DSU */
#define PAC_INTB_CMCC (1 << 2) /* Bit 3: Interrupt for CMCC */
#define PAC_INTB_NVMCTRL (1 << 3) /* Bit 2: Interrupt for NVMCTRL */
#define PAC_INTB_PORT (1 << 4) /* Bit 4: Interrupt for PORT */
#define PAC_INTB_DMAC (1 << 5) /* Bit 5: Interrupt for DMAC */
#define PAC_INTB_EVSYS (1 << 7) /* Bit 7: Interrupt for EVSYS */
#define PAC_INTB_SERCOM2 (1 << 9) /* Bit 9: Interrupt for SERCOM2 */
#define PAC_INTB_SERCOM3 (1 << 10) /* Bit 10: Interrupt for SERCOM3 */
#define PAC_INTB_TCC0 (1 << 11) /* Bit 11: Interrupt for TCC0 */
#define PAC_INTB_TCC1 (1 << 12) /* Bit 12: Interrupt for TCC1 */
#define PAC_INTB_TC2 (1 << 13) /* Bit 13: Interrupt for TC2 */
#define PAC_INTB_TC3 (1 << 14) /* Bit 14: Interrupt for TC3 */
#define PAC_INTB_RAMECC (1 << 16) /* Bit 16: Interrupt for RAMECC */
#define SAM_USB_PERID ((1 << 5) + 0) /* PAC Peripheral IDs */
#define SAM_DSU_PERID ((1 << 5) + 1)
#define SAM_NVMCTRL_PERID ((1 << 5) + 2)
#define SAM_CMCCC_PERID ((1 << 5) + 3)
#define SAM_PORT_PERID ((1 << 5) + 4)
#define SAM_DMAC_PERID ((1 << 5) + 5)
#define SAM_EVSYS_PERID ((1 << 5) + 7)
#define SAM_SERCOM2_PERID ((1 << 5) + 9)
#define SAM_SERCOM3_PERID ((1 << 5) + 10)
#define SAM_TCC0_PERID ((1 << 5) + 11)
#define SAM_TCC1_PERID ((1 << 5) + 12)
#define SAM_TC2_PERID ((1 << 5) + 13)
#define SAM_TC3_PERID ((1 << 5) + 14)
#define SAM_RAMECC_PERID ((1 << 5) + 16)
/* Interrupt flag status bridge C and Write protection status bridge C */
#define PAC_INTC_CAN0 (1 << 0) /* Bit 0: Interrupt for CAN0 */
#define PAC_INTC_CAN1 (1 << 1) /* Bit 1: Interrupt for CAN1 */
#define PAC_INTC_GMAC (1 << 2) /* Bit 2: Interrupt for GMAC */
#define PAC_INTC_TCC2 (1 << 3) /* Bit 3: Interrupt for TCC2 */
#define PAC_INTC_TCC3 (1 << 4) /* Bit 4: Interrupt for TCC3 */
#define PAC_INTC_TC4 (1 << 5) /* Bit 5: Interrupt for TC4 */
#define PAC_INTC_TC5 (1 << 6) /* Bit 6: Interrupt for TC5 */
#define PAC_INTC_PDEC (1 << 7) /* Bit 7: Interrupt for PDEC */
#define PAC_INTC_AES (1 << 9) /* Bit 9: Interrupt for AES */
#define PAC_INTC_TRNG (1 << 10) /* Bit 10: Interrupt for TRNG */
#define PAC_INTC_ICM (1 << 11) /* Bit 11: Interrupt for ICM */
#define PAC_INTC_PUKCC (1 << 12) /* Bit 12: Interrupt for PUKCC */
#define PAC_INTC_QSPI (1 << 13) /* Bit 13: Interrupt for QSPI */
#define PAC_INTC_CCL (1 << 14) /* Bit 14: Interrupt for CCL */
#define SAM_CAN0_PERID ((2 << 5) + 0) /* PAC Peripheral IDs */
#define SAM_CAN1_PERID ((2 << 5) + 1)
#define SAM_GMAC_PERID ((2 << 5) + 2)
#define SAM_TCC2_PERID ((2 << 5) + 3)
#define SAM_TCC3_PERID ((2 << 5) + 4)
#define SAM_TC4_PERID ((2 << 5) + 5)
#define SAM_TC5_PERID ((2 << 5) + 6)
#define SAM_PDEC_PERID ((2 << 5) + 7)
#define SAM_AC_PERID ((2 << 5) + 8)
#define SAM_AES_PERID ((2 << 5) + 9)
#define SAM_TRNG_PERID ((2 << 5) + 10)
#define SAM_ICM_PERID ((2 << 5) + 11)
#define SAM_PUKCC_PERID ((2 << 5) + 12)
#define SAM_QSPIC_PERID ((2 << 5) + 13)
#define SAM_CCL_PERID ((2 << 5) + 14)
/* Interrupt flag status bridge D and Write protection status bridge D */
#define PAC_INTD_SERCOM4 (1 << 0) /* Bit 0: Interrupt for SERCOM4 */
#define PAC_INTD_SERCOM5 (1 << 1) /* Bit 1: Interrupt for SERCOM5 */
#define PAC_INTD_SERCOM6 (1 << 2) /* Bit 2: Interrupt for SERCOM6 */
#define PAC_INTD_SERCOM7 (1 << 3) /* Bit 3: Interrupt for SERCOM7 */
#define PAC_INTD_TCC4 (1 << 4) /* Bit 4: Interrupt for TCC4 */
#define PAC_INTD_TC6 (1 << 5) /* Bit 5: Interrupt for TC6 */
#define PAC_INTD_TC7 (1 << 6) /* Bit 6: Interrupt for TC7 */
#define PAC_INTD_ADC0 (1 << 7) /* Bit 7: Interrupt for ADC0 */
#define PAC_INTD_ADC1 (1 << 8) /* Bit 8: Interrupt for ADC1 */
#define PAC_INTD_DAC (1 << 9) /* Bit 9: Interrupt for DAC */
#define PAC_INTD_I2S (1 << 10) /* Bit 10: Interrupt for I2S */
#define PAC_INTD_PCC (1 << 11) /* Bit 11: Interrupt for PCC */
#define SAM_SERCOM4_PERID ((3 << 5) + 0) /* PAC Peripheral IDs */
#define SAM_SERCOM5_PERID ((3 << 5) + 1)
#define SAM_SERCOM6_PERID ((3 << 5) + 2)
#define SAM_SERCOM7_PERID ((3 << 5) + 3)
#define SAM_TCC4_PERID ((3 << 5) + 4)
#define SAM_TC6_PERID ((3 << 5) + 5)
#define SAM_TC7_PERID ((3 << 5) + 6)
#define SAM_ADC0_PERID ((3 << 5) + 7)
#define SAM_ADC1_PERID ((3 << 5) + 8)
#define SAM_DAC_PERID ((3 << 5) + 9)
#define SAM_I2S_PERID ((3 << 5) + 10)
#define SAM_PCC_PERID ((3 << 5) + 11)
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PAC_H */
arch/arm/src/samd5e5/chip/sam_pinmap.h
+52
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/************************************************************************************
* arch/arm/src/samd5e5/chip/sam_memorymap.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MEMORYMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(ARCH_CHIP_SAME5X)
# include "chip/samd5e5_memorymap.h"
#else
# error "Unsupported SAMD5/E5 family"
#endif
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MEMORYMAP_H */
arch/arm/src/samd5e5/chip/sam_pm.h
+147
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/****************************************************************************************************
* arch/arm/src/samd5e5/chip/sam_pm.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PM_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PM_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* PM register offsets ******************************************************************************/
#define SAM_PM_CTRLA_OFFSET 0x0000 /* Control A */
#define SAM_PM_SLEEPCFG_OFFSET 0x0001 /* Sleep configuration */
#define SAM_PM_INTENCLR_OFFSET 0x0004 /* Interrupt enable clear register */
#define SAM_PM_INTENSET_OFFSET 0x0005 /* Interrupt enable set register */
#define SAM_PM_INTFLAG_OFFSET 0x0006 /* Interrupt flag status and clear register */
#define SAM_PM_STDBYCFG_OFFSET 0x0008 /* Standy configuration */
#define SAM_PM_HIBCFG_OFFSET 0x0009 /* Hibernate configuration */
#define SAM_PM_BKUPCFG_OFFSET 0x000a /* Backup configuration */
/* PM register addresses ****************************************************************************/
#define SAM_PM_CTRLA (SAM_PM_BASE + SAM_PM_CTRLA_OFFSET)
#define SAM_PM_SLEEPCFG (SAM_PM_BASE + SAM_PM_SLEEPCFG_OFFSET)
#define SAM_PM_INTENCLR (SAM_PM_BASE + SAM_PM_INTENCLR_OFFSET)
#define SAM_PM_INTENSET (SAM_PM_BASE + SAM_PM_INTENSET_OFFSET)
#define SAM_PM_INTFLAG (SAM_PM_BASE + SAM_PM_INTFLAG_OFFSET)
#define SAM_PM_STDBYCFG (SAM_PM_BASE + SAM_PM_STDBYCFG_OFFSET)
#define SAM_PM_HIBCFG (SAM_PM_BASE + SAM_PM_HIBCFG_OFFSET)
#define SAM_PM_BKUPCFG (SAM_PM_BASE + SAM_PM_BKUPCFG_OFFSET)
/* PM register bit definitions **********************************************************************/
/* Control A register */
#define PM_CTRLA_IORET (1 << 2) /* Bit 2: I/O retention */
/* Sleep configuration register */
#define PM_SLEEPCFG_MODE_SHIFT (0) /* Bits 0-2: Idle Mode Configuration */
#define PM_SLEEPCFG_MODE_MASK (7 << PM_SLEEPCFG_MODE_SHIFT)
# define PM_SLEEPCFG_MODE_IDLE (2 << PM_SLEEPCFG_MODE_SHIFT) /* CPU, AHBx, APBx clocks OFF */
# define PM_SLEEPCFG_MODE_STANDBY (4 << PM_SLEEPCFG_MODE_SHIFT) /* All clocks OFF */
# define PM_SLEEPCFG_MODE_HIBERNATE (5 << PM_SLEEPCFG_MODE_SHIFT) /* Backup domain is ON as well as
* some PDRAMs */
# define PM_SLEEPCFG_MODE_BACKUP (6 << PM_SLEEPCFG_MODE_SHIFT) /* Only backup domain is
* powered ON */
# define PM_SLEEPCFG_MODE_OFF (7 << PM_SLEEPCFG_MODE_SHIFT) /* All power domains are
* powered OFF */
/* Interrupt enable clear, Interrupt enable set, and Interrupt flag status and clear registers */
#define PM_INT_SLEEPRDY (1 << 0) /* Bit 0: Sleep mode entry ready interrupt */
/* Standy configuration */
#define PM_STDBYCFG_RAMCFG_SHIFT (0) /* Bits 0-1: RAM Configuration */
#define PM_STDBYCFG_RAMCFG_MASK (3 << PM_STDBYCFG_RAMCFG_SHIFT)
# define PM_STDBYCFG_RAMCFG_RET (0 << PM_STDBYCFG_RAMCFG_SHIFT) /* System RAM is retained */
# define PM_STDBYCFG_RAMCFG_PARTIAL (1 << PM_STDBYCFG_RAMCFG_SHIFT) /* PD0 ACTIVE; PD1/2 handled by HW */
# define PM_STDBYCFG_RAMCFG_OFF (2 << PM_STDBYCFG_RAMCFG_SHIFT) /* Only the first 32Kb of system
* RAM is retained */
#define PM_STDBYCFG_FASTWKUP_SHIFT (4) /* Bits 4-5: Fast Wakeup */
#define PM_STDBYCFG_FASTWKUP_MASK (3 << PM_STDBYCFG_FASTWKUP_SHIFT)
# define PM_STDBYCFG_FASTWKUP_NO (0 << PM_STDBYCFG_FASTWKUP_SHIFT) /* Disabled */
# define PM_STDBYCFG_FASTWKUP_NVM (1 << PM_STDBYCFG_FASTWKUP_SHIFT) /* Enabled on NVM */
# define PM_STDBYCFG_FASTWKUP_MAINVREG (2 << PM_STDBYCFG_FASTWKUP_SHIFT) /* Enabled on MAINVREG */
# define PM_STDBYCFG_FASTWKUP_BOTH (3 << PM_STDBYCFG_FASTWKUP_SHIFT) /* Enabled on both */
/* Hibernate configuration */
#define PM_HIBCFG_RAMCFG_SHIFT (0) /* Bits 0-1: RAM Configuration */
#define PM_HIBCFG_RAMCFG_MASK (3 << PM_HIBCFG_RAMCFG_SHIFT)
# define PM_HIBCFG_RAMCFG_RET (0 << PM_HIBCFG_RAMCFG_SHIFT) /* System RAM is retained */
# define PM_HIBCFG_RAMCFG_PARTIAL (1 << PM_HIBCFG_RAMCFG_SHIFT) /* PD0 ACTIVE; PD1/2 handled by HW */
# define PM_HIBCFG_RAMCFG_OFF (2 << PM_HIBCFG_RAMCFG_SHIFT) /* Only the first 32Kb of system
* RAM is retained */
#define PM_HIBCFG_BRAMCFG_SHIFT (0) /* Bits 0-1: Backup RAM Configuration */
#define PM_HIBCFG_BRAMCFG_MASK (3 << PM_HIBCFG_BRAMCFG_SHIFT)
# define PM_HIBCFG_BRAMCFG_RET (0 << PM_HIBCFG_BRAMCFG_SHIFT) /* System RAM is retained */
# define PM_HIBCFG_BRAMCFG_PARTIAL (1 << PM_HIBCFG_BRAMCFG_SHIFT) /* PD0 ACTIVE; PD1/2 handled by HW */
# define PM_HIBCFG_BRAMCFG_OFF (2 << PM_HIBCFG_BRAMCFG_SHIFT) /* Only the first 32Kb of system
* RAM is retained */
/* Backup configuration */
#define PM_BKUPCFG_BRAMCFG_SHIFT (0) /* Bits 0-1: RAM Configuration */
#define PM_BKUPCFG_BRAMCFG_MASK (3 << PM_BKUPCFG_BRAMCFG_SHIFT)
# define PM_BKUPCFG_BRAMCFG_RET (0 << PM_BKUPCFG_BRAMCFG_SHIFT) /* System RAM is retained */
# define PM_BKUPCFG_BRAMCFG_PARTIAL (1 << PM_BKUPCFG_BRAMCFG_SHIFT) /* PD0 ACTIVE; PD1/2 handled by HW */
# define PM_BKUPCFG_BRAMCFG_OFF (2 << PM_BKUPCFG_BRAMCFG_SHIFT) /* Only the first 32Kb of system
* RAM is retained */
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PM_H */
arch/arm/src/samd5e5/chip/sam_port.h
+526
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arch/arm/src/samd5e5/chip/sam_rstc.h
+91
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/********************************************************************************************
* arch/arm/src/samd5e5/chip/sam_rstc.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_RSTC_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_RSTC_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* RSTC register offsets ********************************************************************/
#define SAM_RSTC_RCAUSE_OFFSET 0x0000 /* Reset cause */
#define SAM_RSTC_BKUPEXIT_OFFSET 0x0002 /* Backup exit source */
/* RSTC register addresses ******************************************************************/
#define SAM_RSTC_RCAUSE (SAM_RSTC_BASE + SAM_RSTC_RCAUSE_OFFSET)
#define SAM_RSTC_BKUPEXIT (SAM_RSTC_BASE + SAM_RSTC_BKUPEXIT_OFFSET)
/* RSTC register bit definitions ************************************************************/
/* Reset cause */
#define RSTC_RCAUSE_POR (1 << 0) /* Bit 0: Power on reset */
#define RSTC_RCAUSE_BOD12 (1 << 1) /* Bit 1: Brown out 12 detector reset */
#define RSTC_RCAUSE_BOD33 (1 << 2) /* Bit 2: Brown out 33 detector reset */
#define RSTC_RCAUSE_NVM (1 << 3) /* Bit 3: External reset */
#define RSTC_RCAUSE_EXT (1 << 4) /* Bit 4: External reset */
#define RSTC_RCAUSE_WDT (1 << 5) /* Bit 5: Watchdog reset */
#define RSTC_RCAUSE_SYST (1 << 6) /* Bit 6: System reset request */
#define RSTC_RCAUSE_BACKUP (1 << 7) /* Bit 7: Backup reset*/
/* Backup exit source */
#define RSTC_BKUPEXIT_RTC (1 << 1) /* Bit 1: Real time counter interrupt */
#define RSTC_BKUPEXIT_BBPS (1 << 2) /* Bit 2: Battery backup power switch */
#define RSTC_BKUPEXIT_HIB (1 << 7) /* Bit 7: Hibernate */
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_RSTC_H */
arch/arm/src/samd5e5/chip/sam_spi.h
+303
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/********************************************************************************************
* arch/arm/src/samd5e5/chip/sam_spi.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_SPI_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_SPI_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* SPI register offsets *********************************************************************/
#define SAM_SPI_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_SPI_CTRLB_OFFSET 0x0004 /* Control B register */
#define SAM_SPI_CTRLC_OFFSET 0x0008 /* Control C register */
#define SAM_SPI_BAUD_OFFSET 0x000c /* Baud register */
#define SAM_SPI_INTENCLR_OFFSET 0x0014 /* Interrupt enable clear register */
#define SAM_SPI_INTENSET_OFFSET 0x0016 /* Interrupt enable set register */
#define SAM_SPI_INTFLAG_OFFSET 0x0018 /* Interrupt flag and status clear register */
#define SAM_SPI_STATUS_OFFSET 0x001a /* Status register */
#define SAM_SPI_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */
#define SAM_SPI_LENGTH_OFFSET 0x0022 /* Length register */
#define SAM_SPI_ADDR_OFFSET 0x0024 /* Address register */
#define SAM_SPI_DATA_OFFSET 0x0028 /* Data register */
#define SAM_SPI_DBGCTRL_OFFSET 0x0030 /* Debug control register */
/* SPI register addresses *******************************************************************/
#define SAM_SPI0_CTRLA (SAM_SERCOM0_BASE + SAM_SPI_CTRLA_OFFSET)
#define SAM_SPI0_CTRLB (SAM_SERCOM0_BASE + SAM_SPI_CTRLB_OFFSET)
#define SAM_SPI0_CTRLC (SAM_SERCOM0_BASE + SAM_SPI_CTRLC_OFFSET)
#define SAM_SPI0_BAUD (SAM_SERCOM0_BASE + SAM_SPI_BAUD_OFFSET)
#define SAM_SPI0_INTENCLR (SAM_SERCOM0_BASE + SAM_SPI_INTENCLR_OFFSET)
#define SAM_SPI0_INTENSET (SAM_SERCOM0_BASE + SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI0_INTFLAG (SAM_SERCOM0_BASE + SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI0_STATUS (SAM_SERCOM0_BASE + SAM_SPI_STATUS_OFFSET)
#define SAM_SPI0_SYNCBUSY (SAM_SERCOM0_BASE + SAM_SPI_SYNCBUSY_OFFSET)
#define SAM_SPI0_LENGTH (SAM_SERCOM0_BASE + SAM_SPI_LENGTH_OFFSET)
#define SAM_SPI0_ADDR (SAM_SERCOM0_BASE + SAM_SPI_ADDR_OFFSET)
#define SAM_SPI0_DATA (SAM_SERCOM0_BASE + SAM_SPI_DATA_OFFSET)
#define SAM_SPI0_DBGCTRL (SAM_SERCOM0_BASE + SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI1_CTRLA (SAM_SERCOM1_BASE + SAM_SPI_CTRLA_OFFSET)
#define SAM_SPI1_CTRLB (SAM_SERCOM1_BASE + SAM_SPI_CTRLB_OFFSET)
#define SAM_SPI1_CTRLC (SAM_SERCOM1_BASE + SAM_SPI_CTRLC_OFFSET)
#define SAM_SPI1_BAUD (SAM_SERCOM1_BASE + SAM_SPI_BAUD_OFFSET)
#define SAM_SPI1_INTENCLR (SAM_SERCOM1_BASE + SAM_SPI_INTENCLR_OFFSET)
#define SAM_SPI1_INTENSET (SAM_SERCOM1_BASE + SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI1_INTFLAG (SAM_SERCOM1_BASE + SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI1_STATUS (SAM_SERCOM1_BASE + SAM_SPI_STATUS_OFFSET)
#define SAM_SPI1_SYNCBUSY (SAM_SERCOM1_BASE + SAM_SPI_SYNCBUSY_OFFSET)
#define SAM_SPI1_LENGTH (SAM_SERCOM1_BASE + SAM_SPI_LENGTH_OFFSET)
#define SAM_SPI1_ADDR (SAM_SERCOM1_BASE + SAM_SPI_ADDR_OFFSET)
#define SAM_SPI1_DATA (SAM_SERCOM1_BASE + SAM_SPI_DATA_OFFSET)
#define SAM_SPI1_DBGCTRL (SAM_SERCOM1_BASE + SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI2_CTRLA (SAM_SERCOM2_BASE + SAM_SPI_CTRLA_OFFSET)
#define SAM_SPI2_CTRLB (SAM_SERCOM2_BASE + SAM_SPI_CTRLB_OFFSET)
#define SAM_SPI2_CTRLC (SAM_SERCOM2_BASE + SAM_SPI_CTRLC_OFFSET)
#define SAM_SPI2_BAUD (SAM_SERCOM2_BASE + SAM_SPI_BAUD_OFFSET)
#define SAM_SPI2_INTENCLR (SAM_SERCOM2_BASE + SAM_SPI_INTENCLR_OFFSET)
#define SAM_SPI2_INTENSET (SAM_SERCOM2_BASE + SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI2_INTFLAG (SAM_SERCOM2_BASE + SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI2_STATUS (SAM_SERCOM2_BASE + SAM_SPI_STATUS_OFFSET)
#define SAM_SPI2_SYNCBUSY (SAM_SERCOM2_BASE + SAM_SPI_SYNCBUSY_OFFSET)
#define SAM_SPI2_LENGTH (SAM_SERCOM2_BASE + SAM_SPI_LENGTH_OFFSET)
#define SAM_SPI2_ADDR (SAM_SERCOM2_BASE + SAM_SPI_ADDR_OFFSET)
#define SAM_SPI2_DATA (SAM_SERCOM2_BASE + SAM_SPI_DATA_OFFSET)
#define SAM_SPI2_DBGCTRL (SAM_SERCOM2_BASE + SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI3_CTRLA (SAM_SERCOM3_BASE + SAM_SPI_CTRLA_OFFSET)
#define SAM_SPI3_CTRLB (SAM_SERCOM3_BASE + SAM_SPI_CTRLB_OFFSET)
#define SAM_SPI3_CTRLC (SAM_SERCOM3_BASE + SAM_SPI_CTRLC_OFFSET)
#define SAM_SPI3_BAUD (SAM_SERCOM3_BASE + SAM_SPI_BAUD_OFFSET)
#define SAM_SPI3_INTENCLR (SAM_SERCOM3_BASE + SAM_SPI_INTENCLR_OFFSET)
#define SAM_SPI3_INTENSET (SAM_SERCOM3_BASE + SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI3_INTFLAG (SAM_SERCOM3_BASE + SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI3_STATUS (SAM_SERCOM3_BASE + SAM_SPI_STATUS_OFFSET)
#define SAM_SPI3_SYNCBUSY (SAM_SERCOM3_BASE + SAM_SPI_SYNCBUSY_OFFSET)
#define SAM_SPI3_LENGTH (SAM_SERCOM3_BASE + SAM_SPI_LENGTH_OFFSET)
#define SAM_SPI3_ADDR (SAM_SERCOM3_BASE + SAM_SPI_ADDR_OFFSET)
#define SAM_SPI3_DATA (SAM_SERCOM3_BASE + SAM_SPI_DATA_OFFSET)
#define SAM_SPI3_DBGCTRL (SAM_SERCOM3_BASE + SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI4_CTRLA (SAM_SERCOM4_BASE + SAM_SPI_CTRLA_OFFSET)
#define SAM_SPI4_CTRLB (SAM_SERCOM4_BASE + SAM_SPI_CTRLB_OFFSET)
#define SAM_SPI4_CTRLC (SAM_SERCOM4_BASE + SAM_SPI_CTRLC_OFFSET)
#define SAM_SPI4_BAUD (SAM_SERCOM4_BASE + SAM_SPI_BAUD_OFFSET)
#define SAM_SPI4_INTENCLR (SAM_SERCOM4_BASE + SAM_SPI_INTENCLR_OFFSET)
#define SAM_SPI4_INTENSET (SAM_SERCOM4_BASE + SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI4_INTFLAG (SAM_SERCOM4_BASE + SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI4_STATUS (SAM_SERCOM4_BASE + SAM_SPI_STATUS_OFFSET)
#define SAM_SPI4_SYNCBUSY (SAM_SERCOM4_BASE + SAM_SPI_SYNCBUSY_OFFSET)
#define SAM_SPI4_LENGTH (SAM_SERCOM4_BASE + SAM_SPI_LENGTH_OFFSET)
#define SAM_SPI4_ADDR (SAM_SERCOM4_BASE + SAM_SPI_ADDR_OFFSET)
#define SAM_SPI4_DATA (SAM_SERCOM4_BASE + SAM_SPI_DATA_OFFSET)
#define SAM_SPI4_DBGCTRL (SAM_SERCOM4_BASE + SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI5_CTRLA (SAM_SERCOM5_BASE + SAM_SPI_CTRLA_OFFSET)
#define SAM_SPI5_CTRLB (SAM_SERCOM5_BASE + SAM_SPI_CTRLB_OFFSET)
#define SAM_SPI5_BAUD (SAM_SERCOM5_BASE + SAM_SPI_BAUD_OFFSET)
#define SAM_SPI5_CTRLC (SAM_SERCOM5_BASE + SAM_SPI_CTRLC_OFFSET)
#define SAM_SPI5_INTENCLR (SAM_SERCOM5_BASE + SAM_SPI_INTENCLR_OFFSET)
#define SAM_SPI5_INTENSET (SAM_SERCOM5_BASE + SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI5_INTFLAG (SAM_SERCOM5_BASE + SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI5_STATUS (SAM_SERCOM5_BASE + SAM_SPI_STATUS_OFFSET)
#define SAM_SPI5_SYNCBUSY (SAM_SERCOM5_BASE + SAM_SPI_SYNCBUSY_OFFSET)
#define SAM_SPI5_LENGTH (SAM_SERCOM5_BASE + SAM_SPI_LENGTH_OFFSET)
#define SAM_SPI5_ADDR (SAM_SERCOM5_BASE + SAM_SPI_ADDR_OFFSET)
#define SAM_SPI5_DATA (SAM_SERCOM5_BASE + SAM_SPI_DATA_OFFSET)
#define SAM_SPI5_DBGCTRL (SAM_SERCOM5_BASE + SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI6_CTRLA (SAM_SERCOM6_BASE + SAM_SPI_CTRLA_OFFSET)
#define SAM_SPI6_CTRLB (SAM_SERCOM6_BASE + SAM_SPI_CTRLB_OFFSET)
#define SAM_SPI6_BAUD (SAM_SERCOM6_BASE + SAM_SPI_BAUD_OFFSET)
#define SAM_SPI6_CTRLC (SAM_SERCOM6_BASE + SAM_SPI_CTRLC_OFFSET)
#define SAM_SPI6_INTENCLR (SAM_SERCOM6_BASE + SAM_SPI_INTENCLR_OFFSET)
#define SAM_SPI6_INTENSET (SAM_SERCOM6_BASE + SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI6_INTFLAG (SAM_SERCOM6_BASE + SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI6_STATUS (SAM_SERCOM6_BASE + SAM_SPI_STATUS_OFFSET)
#define SAM_SPI6_SYNCBUSY (SAM_SERCOM6_BASE + SAM_SPI_SYNCBUSY_OFFSET)
#define SAM_SPI6_LENGTH (SAM_SERCOM6_BASE + SAM_SPI_LENGTH_OFFSET)
#define SAM_SPI6_ADDR (SAM_SERCOM6_BASE + SAM_SPI_ADDR_OFFSET)
#define SAM_SPI6_DATA (SAM_SERCOM6_BASE + SAM_SPI_DATA_OFFSET)
#define SAM_SPI6_DBGCTRL (SAM_SERCOM6_BASE + SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI7_CTRLA (SAM_SERCOM7_BASE + SAM_SPI_CTRLA_OFFSET)
#define SAM_SPI7_CTRLB (SAM_SERCOM7_BASE + SAM_SPI_CTRLB_OFFSET)
#define SAM_SPI7_BAUD (SAM_SERCOM7_BASE + SAM_SPI_BAUD_OFFSET)
#define SAM_SPI7_CTRLC (SAM_SERCOM7_BASE + SAM_SPI_CTRLC_OFFSET)
#define SAM_SPI7_INTENCLR (SAM_SERCOM7_BASE + SAM_SPI_INTENCLR_OFFSET)
#define SAM_SPI7_INTENSET (SAM_SERCOM7_BASE + SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI7_INTFLAG (SAM_SERCOM7_BASE + SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI7_STATUS (SAM_SERCOM7_BASE + SAM_SPI_STATUS_OFFSET)
#define SAM_SPI7_SYNCBUSY (SAM_SERCOM7_BASE + SAM_SPI_SYNCBUSY_OFFSET)
#define SAM_SPI7_LENGTH (SAM_SERCOM7_BASE + SAM_SPI_LENGTH_OFFSET)
#define SAM_SPI7_ADDR (SAM_SERCOM7_BASE + SAM_SPI_ADDR_OFFSET)
#define SAM_SPI7_DATA (SAM_SERCOM7_BASE + SAM_SPI_DATA_OFFSET)
#define SAM_SPI7_DBGCTRL (SAM_SERCOM7_BASE + SAM_SPI_DBGCTRL_OFFSET)
/* SPI register bit definitions *************************************************************/
/* Control A register */
#define SPI_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
#define SPI_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
#define SPI_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */
#define SPI_CTRLA_MODE_MASK (7 << SPI_CTRLA_MODE_SHIFT)
# define SPI_CTRLA_MODE_SLAVE (2 << SPI_CTRLA_MODE_SHIFT) /* SPI slave operation */
# define SPI_CTRLA_MODE_MASTER (3 << SPI_CTRLA_MODE_SHIFT) /* SPI master operation */
#define SPI_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */
#define SPI_CTRLA_IBON (1 << 8) /* Bit 8: Immediate BUFOVF notification */
#define SPI_CTRLA_DOPO_SHIFT (16) /* Bit 16-17: Data out pinout */
#define SPI_CTRLA_DOPO_MASK (3 << SPI_CTRLA_DOPO_SHIFT) /* Bit 16-17: Data out pinout */
# define SPI_CTRLA_DOPO_DOPAD012 (0 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD0 SCK=PAD1 SS=PAD2 */
# define SPI_CTRLA_DOPO_DOPAD312 (2 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD3 SCK=PAD1 SS=PAD2 */
#define SPI_CTRLA_DIPO_SHIFT (20) /* Bits 20-21: Data in pinout */
#define SPI_CTRLA_DIPO_MASK (3 << SPI_CTRLA_DIPO_SHIFT)
# define SPI_CTRLA_DIPAD0 (0 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD0 for DI */
# define SPI_CTRLA_DIPAD1 (1 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD1 for DI */
# define SPI_CTRLA_DIPAD2 (2 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD2 for DI */
# define SPI_CTRLA_DIPAD3 (3 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD3 for DI */
#define SPI_CTRLA_FORM_SHIFT (24) /* Bits 24-27: Frame format */
#define SPI_CTRLA_FORM_MASK (7 << SPI_CTRLA_FORM_SHIFT)
# define SPI_CTRLA_FORM_SPI (0 << SPI_CTRLA_FORM_SHIFT) /* SPI frame (no address) */
# define SPI_CTRLA_FORM_ADDR (2 << SPI_CTRLA_FORM_SHIFT) /* SPI frame (w/address) */
#define SPI_CTRLA_CPHA (1 << 28) /* Bit 28: Clock phase */
#define SPI_CTRLA_CPOL (1 << 29) /* Bit 29: Clock polarity */
#define SPI_CTRLA_DORD (1 << 30) /* Bit 30: Data order */
# define SPI_CTRLA_MSBFIRST (0)
# define SPI_CTRLA_LSBFIRST SPI_CTRLA_DORD
/* Control B register */
#define SPI_CTRLB_CHSIZE_SHIFT (0) /* Bits 0-2: Character Size */
#define SPI_CTRLB_CHSIZE_MASK (7 << SPI_CTRLB_CHSIZE_SHIFT)
# define SPI_CTRLB_CHSIZE_8BITS (0 << SPI_CTRLB_CHSIZE_SHIFT) /* 8 bits */
# define SPI_CTRLB_CHSIZE_9BITS (1 << SPI_CTRLB_CHSIZE_SHIFT) /* 9 bits */
#define SPI_CTRLB_PLOADEN (1 << 6) /* Bit 6: Slave Data Preload Enable */
#define SPI_CTRLB_SSDE (1 << 9) /* Bit 9: Slave select low detect enable */
#define SPI_CTRLB_MSSEN (1 << 13) /* Bit 13: Master slave select enable */
#define SPI_CTRLB_AMODE_SHIFT (14) /* Bits 14-15: Address Mode */
#define SPI_CTRLB_AMODE_MASK (3 << SPI_CTRLB_AMODE_SHIFT)
# define SPI_CTRLB_AMODE_ADDRMASK (0 << SPI_CTRLB_AMODE_SHIFT) /* ADDRMASK used to mask ADDR */
# define SPI_CTRLB_AMODE_2ADDRS (1 << SPI_CTRLB_AMODE_SHIFT) /* Slave 2 addresses: ADDR & ADDRMASK */
# define SPI_CTRLB_AMODE_RANGE (2 << SPI_CTRLB_AMODE_SHIFT) /* Slave range of addresses: ADDRMASK-ADDR */
#define SPI_CTRLB_RXEN (1 << 17) /* Bit 17: Receiver enable */
/* Control C register */
#
#define SPI_CTRLC_ICSPACE_SHIFT (0) /* Bits 0-2: Inter-Character Spacing */
#define SPI_CTRLC_ICSPACE_MASK (7 << SPI_CTRLC_ICSPACE_SHIFT)
# define SPI_CTRLC_ICSPACE_DISABLE (0 << SPI_CTRLC_ICSPACE_SHIFT)
# define SPI_CTRLC_ICSPACE(n) ((uint32_t)(n) << SPI_CTRLC_ICSPACE_SHIFT)
#define SPI_CTRLC_DATA32B (1 << 24 /* Bit 24: Data 32 Bit */
# define SPI_CTRLC_DATA32B_8BIT (0) /* DATA register is 8-bit */
# define SPI_CTRLC_DATA32B_32BIT SPI_CTRLC_DATA32B /* DATA register is 32-bit */
/* Baud register (8-bit baud value) */
/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and
* status clear registers.
*/
#define SPI_INT_DRE (1 << 0) /* Bit 0: Data register empty interrupt */
#define SPI_INT_TXC (1 << 1) /* Bit 1: Transmit complete interrupt */
#define SPI_INT_RXC (1 << 2) /* Bit 2: Receive complete interrupt */
#define SPI_INT_SSL (1 << 3) /* Bit 3: Slave select low interrupt */
#define SPI_INT_ERROR (1 << 7) /* Bit 7: Error interrupt */
#define SPI_INT_ALL (0x8f)
/* Status register */
#define SPI_STATUS_BUFOVF (1 << 2) /* Bit 2: Buffer overflow */
#define SPI_STATUS_LENERR (1 << 11) /* Bit 11: Transaction Length Error */
#define SPI_STATUS_CLRALL (SPI_STATUS_BUFOVF | SPI_STATUS_LENERR)
/* Synchronization busy register */
#define SPI_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset synchronization busy */
#define SPI_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: SERCOM enable synchronization busy */
#define SPI_SYNCBUSY_CTRLB (1 << 2) /* Bit 2: CTRLB synchronization busy */
#define SPI_SYNCBUSY_LENGTH (1 << 4) /* Bit 4: LENGTH synchronization busy */
/* Length register */
#define SPI_LENGTH_LEN_SHIFT (0) /* Bit 0-7: Data length enable */
#define SPI_LENGTH_LEN_MASK (0xff << SPI_LENGTH_LEN_SHIFT)
# define SPI_LENGTHLEN(n) ((uint32_t)(n) << SPI_LENGTH_LEN_SHIFT)
#define SPI_LENGTH_LENEN (1 << 8) /* Bit 8: Data Length Enable */
/* Address register */
#define SPI_ADDR_SHIFT (0) /* Bits 0-7: Address */
#define SPI_ADDR_MASK (0xff << SPI_ADDR_SHIFT)
# define SPI_ADDR(n) ((uint32_t)(n) << SPI_ADDR_SHIFT)
#define SPI_ADDRMASK_SHIFT (16) /* Bits 16-23: Address Mask */
#define SPI_ADDRMASK_MASK (0xff << SPI_ADDRMASK_SHIFT)
# define SPI_ADDRMASK(n) ((uint32_t)(n) << SPI_ADDRMASK_SHIFT)
/* Data register (8-, 9- or 32-bit data) */
#define SPI_DATA_MASK9 (0x1ff) /* Bits 0-8: 8- or 9-bit Data */
/* Debug control register */
#define SPI_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_SPI_H */
arch/arm/src/samd5e5/chip/sam_supc.h
+231
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@@ -0,0 +1,231 @@
/********************************************************************************************
* arch/arm/src/samd5e5/chip/sam_supc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_SUPC_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_SUPC_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* SUPC register offsets *********************************************************************/
#define SAM_SUPC_INTENCLR_OFFSET 0x0000 /* Interrupt enable clear */
#define SAM_SUPC_INTENSET_OFFSET 0x0004 /* Interrupt enable set */
#define SAM_SUPC_INTFLAG_OFFSET 0x0008 /* Interrupt flag status and clear */
#define SAM_SUPC_STATUS_OFFSET 0x000c /* Status */
#define SAM_SUPC_BOD33_OFFSET 0x0010 /* 3.3V brown-out detector control */
#define SAM_SUPC_BOD12_OFFSET 0x0014 /* 1.2V brown-out detctor control */
#define SAM_SUPC_VREG_OFFSET 0x0018 /* Voltage regulator system control */
#define SAM_SUPC_VREF_OFFSET 0x001c /* Voltage references system control */
#define SAM_SUPC_BBPS_OFFSET 0x0020 /* Battery backup power switch control */
#define SAM_SUPC_BKOUT_OFFSET 0x0024 /* Backup output control */
#define SAM_SUPC_BKIN_OFFSET 0x0028 /* Backup input value */
/* SUPC register addresses *******************************************************************/
#define SAM_SUPC_INTENCLR (SAM_SUPC_BASE + SAM_SUPC_INTENCLR_OFFSET)
#define SAM_SUPC_INTENSET (SAM_SUPC_BASE + SAM_SUPC_INTENSET_OFFSET)
#define SAM_SUPC_INTFLAG (SAM_SUPC_BASE + SAM_SUPC_INTFLAG_OFFSET)
#define SAM_SUPC_STATUS (SAM_SUPC_BASE + SAM_SUPC_STATUS_OFFSET)
#define SAM_SUPC_BOD33 (SAM_SUPC_BASE + SAM_SUPC_BOD33_OFFSET)
#define SAM_SUPC_BOD12 (SAM_SUPC_BASE + SAM_SUPC_BOD12_OFFSET)
#define SAM_SUPC_VREG (SAM_SUPC_BASE + SAM_SUPC_VREG_OFFSET)
#define SAM_SUPC_VREF (SAM_SUPC_BASE + SAM_SUPC_VREF_OFFSET)
#define SAM_SUPC_BBPS (SAM_SUPC_BASE + SAM_SUPC_BBPS_OFFSET)
#define SAM_SUPC_BKOUT (SAM_SUPC_BASE + SAM_SUPC_BKOUT_OFFSET)
#define SAM_SUPC_BKIN (SAM_SUPC_BASE + SAM_SUPC_BKIN_OFFSET)
/* SUPC register bit definitions *************************************************************/
/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and clear, and
* Status registers.
*/
#define SUPC_INT_BOD33RDY (1 << 0) /* Bit 0: BOD33 ready interrupt */
#define SUPC_INT_BOD33DET (1 << 1) /* Bit 1: BOD33 detection interrupt */
#define SUPC_INT_B33SRDY (1 << 2) /* Bit 2: BOD33 synchronization ready interrupt */
#define SUPC_INT_BOD12RDY (1 << 3) /* Bit 3: BOD12 ready interrupt */
#define SUPC_INT_BOD12DET (1 << 4) /* Bit 4: BOD12 detection interrupt */
#define SUPC_INT_B12SRDY (1 << 5) /* Bit 5: BOD12 synchronization ready interrupt */
#define SUPC_INT_VREGRDY (1 << 8) /* Bit 8: Voltage regulator ready interrupt */
#define SUPC_INT_VCORERDY (1 << 10) /* Bit 10: VDDCORE voltage ready interrupt */
#define SUPC_INT_ALL (0x0000053f)
/* 3.3V brown-out detector control register */
#define SUPC_BOD33_ENABLE (1 << 1) /* Bit 1: Enable */
#define SUPC_BOD33_ACTION_SHIFT (2) /* Bits 2-3: BOD33 action */
#define SUPC_BOD33_ACTION_MASK (3 << SUPC_BOD33_ACTION_SHIFT)
# define SUPC_BOD33_ACTION(n) ((n) << SUPC_BOD33_ACTION_SHIFT)
# define SUPC_BOD33_ACTION_NONE (0 << SUPC_BOD33_ACTION_SHIFT) /* No action */
# define SUPC_BOD33_ACTION_RESET (1 << SUPC_BOD33_ACTION_SHIFT) /* BOD33 generates reset */
# define SUPC_BOD33_ACTION_INTR (2 << SUPC_BOD33_ACTION_SHIFT) /* BOD33 generates interrupt */
# define SUPC_BOD33_ACTION_BKUP (3 << SUPC_BOD33_ACTION_SHIFT) /* BOD33 backup sleep mode */
#define SUPC_BOD33_STDBYCFG (1 << 4) /* Bit 4: BOD33 configuration in standby sleep mode */
#define SUPC_BOD33_RUNSTDBY (1 << 5) /* Bit 5: Run in standby */
#define SUPC_BOD33_RUNHIB (1 << 6) /* Bit 6: BOD33 configuration in hibernate sleep mode */
#define SUPC_BOD33_RUNBKUP (1 << 7) /* Bit 7: BOD33 configuration in backup sleep */
#define SUPC_BOD33_HYST_SHIFT (8) /* Bits 8-11: BOD33 Hysteresis Voltage Value on VDD */
#define SUPC_BOD33_HYST_MASK (15 << SUPC_BOD33_HYST_SHIFT)
# define SUPC_BOD33_HYST_NONE (0 << SUPC_BOD33_HYST_SHIFT)
# define SUPC_BOD33_HYST(n) ((uint32_t)(n) << SUPC_BOD33_HYST_SHIFT)
#define SUPC_BOD33_PSEL_SHIFT (12) /* Bits 12-14: Prescaler select */
#define SUPC_BOD33_PSEL_MASK (7 << SUPC_BOD33_PSEL_SHIFT)
# define SUPC_BOD33_PSEL(n) ((uint32_t)(n) << SUPC_BOD33_PSEL_SHIFT)
# define SUPC_BOD33_PSEL_NODIV (0 << SUPC_BOD33_PSEL_SHIFT) /* Not divided: Sampling mode is OFF */
# define SUPC_BOD33_PSEL_DIV4 (1 << SUPC_BOD33_PSEL_SHIFT) /* Divide clock by 4 */
# define SUPC_BOD33_PSEL_DIV8 (2 << SUPC_BOD33_PSEL_SHIFT) /* Divide clock by 8 */
# define SUPC_BOD33_PSEL_DIV16 (3 << SUPC_BOD33_PSEL_SHIFT) /* Divide clock by 16 */
# define SUPC_BOD33_PSEL_DIV32 (4 << SUPC_BOD33_PSEL_SHIFT) /* Divide clock by 32 */
# define SUPC_BOD33_PSEL_DIV64 (5 << SUPC_BOD33_PSEL_SHIFT) /* Divide clock by 64 */
# define SUPC_BOD33_PSEL_DIV128 (6 << SUPC_BOD33_PSEL_SHIFT) /* Divide clock by 128 */
# define SUPC_BOD33_PSEL_DIV256 (7 << SUPC_BOD33_PSEL_SHIFT) /* Divide clock by 256 */
#define SUPC_BOD33_LEVEL_SHIFT (16) /* Bits 16-23: BOD33 threshold level VDD */
#define SUPC_BOD33_LEVEL_MASK (0xff << SUPC_BOD33_LEVEL_SHIFT)
# define SUPC_BOD33_LEVEL(n) ((uint32_t)(n) << SUPC_BOD33_LEVEL_SHIFT)
#define SUPC_BOD33_VBATLEVEL_SHIFT (24) /* Bits 24-31: BOD33 Threshold Level on VBAT */
#define SUPC_BOD33_VBATLEVEL_MASK (0xff << SUPC_BOD33_VBATLEVEL_SHIFT)
# define SUPC_BOD33_VBATLEVEL(n) ((uint32_t)(n) << SUPC_BOD33_VBATLEVEL_SHIFT)
/* 1.2V brown-out detector control */
#define SUPC_BOD12_ENABLE (1 << 1) /* Bit 1: Enable */
#define SUPC_BOD12_HYST (1 << 2) /* Bit 2: Hysteresis */
#define SUPC_BOD12_ACTION_SHIFT (3) /* Bits 3-4: BOD12 action */
#define SUPC_BOD12_ACTION_MASK (3 << SUPC_BOD12_ACTION_SHIFT)
# define SUPC_BOD12_ACTION(n) ((n) << SUPC_BOD12_ACTION_SHIFT)
# define SUPC_BOD12_ACTION_NONE (0 << SUPC_BOD12_ACTION_SHIFT) /* No action */
# define SUPC_BOD12_ACTION_RESET (1 << SUPC_BOD12_ACTION_SHIFT) /* BOD12 generates reset */
# define SUPC_BOD12_ACTION_INTR (2 << SUPC_BOD12_ACTION_SHIFT) /* BOD12 generates interrupt */
#define SUPC_BOD12_STDBYCFG (1 << 5) /* Bit 5: BOD12 configuration in standby sleep mode */
#define SUPC_BOD12_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
#define SUPC_BOD12_ACTCFG (1 << 8) /* Bit 8: BOD12 configuration in active sleep */
#define SUPC_BOD12_PSEL_SHIFT (12) /* Bits 12-15: Prescaler select */
#define SUPC_BOD12_PSEL_MASK (15 << SUPC_BOD12_PSEL_SHIFT)
# define SUPC_BOD12_PSEL(n) ((uint32_t)(n) << SUPC_BOD12_PSEL_SHIFT)
# define SUPC_BOD12_PSEL_DIV2 (0 << SUPC_BOD12_PSEL_SHIFT) /* Divide clock by 2 */
# define SUPC_BOD12_PSEL_DIV4 (1 << SUPC_BOD12_PSEL_SHIFT) /* Divide clock by 4 */
# define SUPC_BOD12_PSEL_DIV8 (2 << SUPC_BOD12_PSEL_SHIFT) /* Divide clock by 8 */
# define SUPC_BOD12_PSEL_DIV16 (3 << SUPC_BOD12_PSEL_SHIFT) /* Divide clock by 16 */
# define SUPC_BOD12_PSEL_DIV32 (4 << SUPC_BOD12_PSEL_SHIFT) /* Divide clock by 32 */
# define SUPC_BOD12_PSEL_DIV64 (5 << SUPC_BOD12_PSEL_SHIFT) /* Divide clock by 64 */
# define SUPC_BOD12_PSEL_DIV128 (6 << SUPC_BOD12_PSEL_SHIFT) /* Divide clock by 128 */
# define SUPC_BOD12_PSEL_DIV256 (7 << SUPC_BOD12_PSEL_SHIFT) /* Divide clock by 256 */
# define SUPC_BOD12_PSEL_DIV512 (8 << SUPC_BOD12_PSEL_SHIFT) /* Divide clock by 512 */
# define SUPC_BOD12_PSEL_DIV1K (9 << SUPC_BOD12_PSEL_SHIFT) /* Divide clock by 1024 */
# define SUPC_BOD12_PSEL_DIV2K (10 << SUPC_BOD12_PSEL_SHIFT) /* Divide clock by 2048 */
# define SUPC_BOD12_PSEL_DIV4K (11 << SUPC_BOD12_PSEL_SHIFT) /* Divide clock by 4096 */
# define SUPC_BOD12_PSEL_DIV8K (12 << SUPC_BOD12_PSEL_SHIFT) /* Divide clock by 8192 */
# define SUPC_BOD12_PSEL_DIV16K (13 << SUPC_BOD12_PSEL_SHIFT) /* Divide clock by 16384 */
# define SUPC_BOD12_PSEL_DIV32K (14 << SUPC_BOD12_PSEL_SHIFT) /* Divide clock by 32768 */
# define SUPC_BOD12_PSEL_DIV64K (15 << SUPC_BOD12_PSEL_SHIFT) /* Divide clock by 65536 */
/* Voltage regulator system control */
#define SUPC_VREG_SEL (1 << 2) /* Bit 2: Voltage regulator selection */
#define SUPC_VREG_RUNBKUP (1 << 7) /* Bit 7: Run in Backup */
#define SUPC_VREG_VSEN (1 << 16) /* Bit 16: Voltage Scaling Enable */
#define SUPC_VREG_VSPER_SHIFT (24) /* Bits 24-26: Voltage scaling period */
#define SUPC_VREG_VSPER_MASK (7 << SUPC_VREG_VSPER_SHIFT)
# define SUPC_VREG_VSPER(n) ((uint32_t)(n) << SUPC_VREG_VSPER_SHIFT)
/* Voltage references system control register */
#define SUPC_VREF_TSEN (1 << 1) /* Bit 1: Temperature sensor enable */
#define SUPC_VREF_VREFOE (1 << 2) /* Bit 2: Voltage reference output enable */
#define SUPC_VREF_TSSEL (1 << 3) /* Bit 3: Temperature Sensor Channel Selection */
#define SUPC_VREF_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
#define SUPC_VREF_ONDEMAND (1 << 7) /* Bit 7: On demand control */
#define SUPC_VREF_SEL_SHIFT (16) /* Bits 16-19: Voltage reference selection */
#define SUPC_VREF_SEL_MASK (15 << SUPC_VREF_SEL_SHIFT)
# define SUPC_VREF_SEL_1V0 (0 << SUPC_VREF_SEL_SHIFT) /* 1.0V voltage reference typical value */
# define SUPC_VREF_SEL_1V1 (1 << SUPC_VREF_SEL_SHIFT) /* 1.1V voltage reference typical value */
# define SUPC_VREF_SEL_1V2 (2 << SUPC_VREF_SEL_SHIFT) /* 1.2V voltage reference typical value */
# define SUPC_VREF_SEL_1V25 (3 << SUPC_VREF_SEL_SHIFT) /* 1.25V voltage reference typical value */
# define SUPC_VREF_SEL_2V0 (4 << SUPC_VREF_SEL_SHIFT) /* 2.0V voltage reference typical value */
# define SUPC_VREF_SEL_2V2 (5 << SUPC_VREF_SEL_SHIFT) /* 2.2V voltage reference typical value */
# define SUPC_VREF_SEL_2V4 (6 << SUPC_VREF_SEL_SHIFT) /* 2.4V voltage reference typical value */
# define SUPC_VREF_SEL_2V5 (7 << SUPC_VREF_SEL_SHIFT) /* 5.5V voltage reference typical value */
/* Battery backup power switch control */
#define SUPC_BBPS_WAKEEN (1 << 2) /* Bit 2: Wake enable */
/* Backup output control */
#define SUPC_BKOUT_EN_SHIFT (0) /* Bits 0-1: Output enable */
#define SUPC_BKOUT_EN_MASK (3 << SUPC_BKOUT_EN_SHIFT)
# define SUPC_BKOUT_DISABLE (0 << SUPC_BKOUT_EN_SHIFT)
# define SUPC_BKOUT_ENABLE (1 << SUPC_BKOUT_EN_SHIFT)
#define SUPC_BKOUT_CLR_SHIFT (8) /* Bits 8-9: Clear output */
#define SUPC_BKOUT_CLR_MASK (3 << SUPC_BKOUT_CLR_SHIFT)
# define SUPC_BKOUT_CLR (1 << SUPC_BKOUT_CLR_SHIFT)
#define SUPC_BKOUT_SET_SHIFT (16) /* Bits 16-17: Set output */
#define SUPC_BKOUT_SET_MASK (3 << SUPC_BKOUT_SET_SHIFT)
# define SUPC_BKOUT_SET (1 << SUPC_BKOUT_SET_SHIFT)
#define SUPC_BKOUT_RTCTGL_SHIFT (24) /* Bits 24-25: RTC toggle output */
#define SUPC_BKOUT_RTCTGL_MASK (3 << SUPC_BKOUT_RTCTGL_SHIFT)
# define SUPC_BKOUT_RTCTGL_NONE (0 << SUPC_BKOUT_EN_SHIFT) /* No toggle */
# define SUPC_BKOUT_RTCTGL_TOGGLE (1 << SUPC_BKOUT_EN_SHIFT) /* Toggle */
/* Backup input value */
#define SUPC_BKIN_SHIFT (0) /* Bits 0-1: Backup I/O data input value */
#define SUPC_BKIN_MASK (3 << SUPC_BKIN_SHIFT)
# define SUPC_BKIN_OUT0 (1 << SUPC_BKIN_SHIFT) /* Input value of OUT[0] pin */
# define SUPC_BKIN_OUT1 (2 << SUPC_BKIN_SHIFT) /* Input value of OUT[1] pin */
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_SUPC_H */
arch/arm/src/samd5e5/chip/sam_trng.h
+96
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/********************************************************************************************
* arch/arm/src/samd5e5/chip/sam_trng.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_TRNG_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_TRNG_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* TRNG register offsets ********************************************************************/
#define SAM_TRNG_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_TRNG_EVCTRL_OFFSET 0x0004 /* Event control register */
#define SAM_TRNG_INTENCLR_OFFSET 0x0008 /* Interrupt enable clear register */
#define SAM_TRNG_INTENSET_OFFSET 0x0009 /* Interrupt enable set register */
#define SAM_TRNG_INTFLAG_OFFSET 0x000a /* Interrupt flag and status clear register */
#define SAM_TRNG_DATA_OFFSET 0x0020 /* Output data register */
/* TRNG register addresses ******************************************************************/
#define SAM_TRNG_CTRLA (SAM_TRNG_BASE+SAM_TRNG_CTRLA_OFFSET)
#define SAM_TRNG_EVCTRL (SAM_TRNG_BASE+SAM_TRNG_EVCTRL_OFFSET)
#define SAM_TRNG_INTENCLR (SAM_TRNG_BASE+SAM_TRNG_INTENCLR_OFFSET)
#define SAM_TRNG_INTENSET (SAM_TRNG_BASE+SAM_TRNG_INTENSET_OFFSET)
#define SAM_TRNG_INTFLAG (SAM_TRNG_BASE+SAM_TRNG_INTFLAG_OFFSET)
#define SAM_TRNG_DATA (SAM_TRNG_BASE+SAM_TRNG_DATA_OFFSET)
/* TRNG register bit definitions ************************************************************/
/* Control register */
#define TRNG_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
#define TRNG_CTRLA_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
/* Event control register, Interrupt enable clear, interrupt enable set register, interrupt
* flag status registers.
*/
#define TRNG_EVCTRL_DATARDYEO (1 << 0) /* Bit 0: Data ready event output */
/* Data register (32-bit data) */
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_TRNG_H */
arch/arm/src/samd5e5/chip/sam_usart.h
+391
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/********************************************************************************************
* arch/arm/src/samd5e5/chip/sam_usart.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_USART_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_USART_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* USART register offsets *******************************************************************/
#define SAM_USART_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_USART_CTRLB_OFFSET 0x0004 /* Control B register */
#define SAM_USART_CTRLC_OFFSET 0x0008 /* Control C register */
#define SAM_USART_BAUD_OFFSET 0x000c /* Baud register */
#define SAM_USART_RXPL_OFFSET 0x000e /* Receive pulse length register */
#define SAM_USART_INTENCLR_OFFSET 0x0014 /* Interrupt enable clear register */
#define SAM_USART_INTENSET_OFFSET 0x0016 /* Interrupt enable set register */
#define SAM_USART_INTFLAG_OFFSET 0x0018 /* Interrupt flag and status clear register */
#define SAM_USART_STATUS_OFFSET 0x001a /* Status register */
#define SAM_USART_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */
#define SAM_USART_RXERRCNT_OFFSET 0x0020 /* Receive error count register */
#define SAM_USART_LENGTH_OFFSET 0x0022 /* Length register */
#define SAM_USART_DATA_OFFSET 0x0028 /* Data register */
#define SAM_USART_DBGCTRL_OFFSET 0x0030 /* Debug control register */
/* USART register addresses *****************************************************************/
#define SAM_USART0_CTRLA (SAM_SERCOM0_BASE + SAM_USART_CTRLA_OFFSET)
#define SAM_USART0_CTRLB (SAM_SERCOM0_BASE + SAM_USART_CTRLB_OFFSET)
#define SAM_USART0_CTRLC (SAM_SERCOM0_BASE + SAM_USART_CTRLC_OFFSET)
#define SAM_USART0_BAUD (SAM_SERCOM0_BASE + SAM_USART_BAUD_OFFSET)
#define SAM_USART0_RXPL (SAM_SERCOM0_BASE + SAM_USART_RXPL_OFFSET)
#define SAM_USART0_INTENCLR (SAM_SERCOM0_BASE + SAM_USART_INTENCLR_OFFSET)
#define SAM_USART0_INTENSET (SAM_SERCOM0_BASE + SAM_USART_INTENSET_OFFSET)
#define SAM_USART0_INTFLAG (SAM_SERCOM0_BASE + SAM_USART_INTFLAG_OFFSET)
#define SAM_USART0_STATUS (SAM_SERCOM0_BASE + SAM_USART_STATUS_OFFSET)
#define SAM_USART0_SYNCBUSY (SAM_SERCOM0_BASE + SAM_USART_SYNCBUSY_OFFSET)
#define SAM_USART0_RXERRCNT (SAM_SERCOM0_BASE + SAM_USART_RXERRCNT_OFFSET)
#define SAM_USART0_LENGTH (SAM_SERCOM0_BASE + SAM_USART_LENGTH_OFFSET)
#define SAM_USART0_DATA (SAM_SERCOM0_BASE + SAM_USART_DATA_OFFSET)
#define SAM_USART0_DBGCTRL (SAM_SERCOM0_BASE + SAM_USART_DBGCTRL_OFFSET)
#define SAM_USART1_CTRLA (SAM_SERCOM1_BASE + SAM_USART_CTRLA_OFFSET)
#define SAM_USART1_CTRLB (SAM_SERCOM1_BASE + SAM_USART_CTRLB_OFFSET)
#define SAM_USART1_CTRLC (SAM_SERCOM1_BASE + SAM_USART_CTRLC_OFFSET)
#define SAM_USART1_BAUD (SAM_SERCOM1_BASE + SAM_USART_BAUD_OFFSET)
#define SAM_USART1_RXPL (SAM_SERCOM1_BASE + SAM_USART_RXPL_OFFSET)
#define SAM_USART1_INTENCLR (SAM_SERCOM1_BASE + SAM_USART_INTENCLR_OFFSET)
#define SAM_USART1_INTENSET (SAM_SERCOM1_BASE + SAM_USART_INTENSET_OFFSET)
#define SAM_USART1_INTFLAG (SAM_SERCOM1_BASE + SAM_USART_INTFLAG_OFFSET)
#define SAM_USART1_STATUS (SAM_SERCOM1_BASE + SAM_USART_STATUS_OFFSET)
#define SAM_USART1_SYNCBUSY (SAM_SERCOM1_BASE + SAM_USART_SYNCBUSY_OFFSET)
#define SAM_USART1_RXERRCNT (SAM_SERCOM1_BASE + SAM_USART_RXERRCNT_OFFSET)
#define SAM_USART1_LENGTH (SAM_SERCOM1_BASE + SAM_USART_LENGTH_OFFSET)
#define SAM_USART1_DATA (SAM_SERCOM1_BASE + SAM_USART_DATA_OFFSET)
#define SAM_USART1_DBGCTRL (SAM_SERCOM1_BASE + SAM_USART_DBGCTRL_OFFSET)
#define SAM_USART2_CTRLA (SAM_SERCOM2_BASE + SAM_USART_CTRLA_OFFSET)
#define SAM_USART2_CTRLB (SAM_SERCOM2_BASE + SAM_USART_CTRLB_OFFSET)
#define SAM_USART2_CTRLC (SAM_SERCOM2_BASE + SAM_USART_CTRLC_OFFSET)
#define SAM_USART2_BAUD (SAM_SERCOM2_BASE + SAM_USART_BAUD_OFFSET)
#define SAM_USART2_RXPL (SAM_SERCOM2_BASE + SAM_USART_RXPL_OFFSET)
#define SAM_USART2_INTENCLR (SAM_SERCOM2_BASE + SAM_USART_INTENCLR_OFFSET)
#define SAM_USART2_INTENSET (SAM_SERCOM2_BASE + SAM_USART_INTENSET_OFFSET)
#define SAM_USART2_INTFLAG (SAM_SERCOM2_BASE + SAM_USART_INTFLAG_OFFSET)
#define SAM_USART2_STATUS (SAM_SERCOM2_BASE + SAM_USART_STATUS_OFFSET)
#define SAM_USART2_SYNCBUSY (SAM_SERCOM2_BASE + SAM_USART_SYNCBUSY_OFFSET)
#define SAM_USART2_RXERRCNT (SAM_SERCOM2_BASE + SAM_USART_RXERRCNT_OFFSET)
#define SAM_USART2_LENGTH (SAM_SERCOM2_BASE + SAM_USART_LENGTH_OFFSET)
#define SAM_USART2_DATA (SAM_SERCOM2_BASE + SAM_USART_DATA_OFFSET)
#define SAM_USART2_DBGCTRL (SAM_SERCOM2_BASE + SAM_USART_DBGCTRL_OFFSET)
#define SAM_USART3_CTRLA (SAM_SERCOM3_BASE + SAM_USART_CTRLA_OFFSET)
#define SAM_USART3_CTRLB (SAM_SERCOM3_BASE + SAM_USART_CTRLB_OFFSET)
#define SAM_USART3_CTRLC (SAM_SERCOM3_BASE + SAM_USART_CTRLC_OFFSET)
#define SAM_USART3_BAUD (SAM_SERCOM3_BASE + SAM_USART_BAUD_OFFSET)
#define SAM_USART3_RXPL (SAM_SERCOM3_BASE + SAM_USART_RXPL_OFFSET)
#define SAM_USART3_INTENCLR (SAM_SERCOM3_BASE + SAM_USART_INTENCLR_OFFSET)
#define SAM_USART3_INTENSET (SAM_SERCOM3_BASE + SAM_USART_INTENSET_OFFSET)
#define SAM_USART3_INTFLAG (SAM_SERCOM3_BASE + SAM_USART_INTFLAG_OFFSET)
#define SAM_USART3_STATUS (SAM_SERCOM3_BASE + SAM_USART_STATUS_OFFSET)
#define SAM_USART3_SYNCBUSY (SAM_SERCOM3_BASE + SAM_USART_SYNCBUSY_OFFSET)
#define SAM_USART3_RXERRCNT (SAM_SERCOM3_BASE + SAM_USART_RXERRCNT_OFFSET)
#define SAM_USART3_LENGTH (SAM_SERCOM3_BASE + SAM_USART_LENGTH_OFFSET)
#define SAM_USART3_DATA (SAM_SERCOM3_BASE + SAM_USART_DATA_OFFSET)
#define SAM_USART3_DBGCTRL (SAM_SERCOM3_BASE + SAM_USART_DBGCTRL_OFFSET)
#define SAM_USART4_CTRLA (SAM_SERCOM4_BASE + SAM_USART_CTRLA_OFFSET)
#define SAM_USART4_CTRLB (SAM_SERCOM4_BASE + SAM_USART_CTRLB_OFFSET)
#define SAM_USART4_CTRLC (SAM_SERCOM4_BASE + SAM_USART_CTRLC_OFFSET)
#define SAM_USART4_BAUD (SAM_SERCOM4_BASE + SAM_USART_BAUD_OFFSET)
#define SAM_USART4_RXPL (SAM_SERCOM4_BASE + SAM_USART_RXPL_OFFSET)
#define SAM_USART4_INTENCLR (SAM_SERCOM4_BASE + SAM_USART_INTENCLR_OFFSET)
#define SAM_USART4_INTENSET (SAM_SERCOM4_BASE + SAM_USART_INTENSET_OFFSET)
#define SAM_USART4_INTFLAG (SAM_SERCOM4_BASE + SAM_USART_INTFLAG_OFFSET)
#define SAM_USART4_STATUS (SAM_SERCOM4_BASE + SAM_USART_STATUS_OFFSET)
#define SAM_USART4_SYNCBUSY (SAM_SERCOM4_BASE + SAM_USART_SYNCBUSY_OFFSET)
#define SAM_USART4_RXERRCNT (SAM_SERCOM4_BASE + SAM_USART_RXERRCNT_OFFSET)
#define SAM_USART4_LENGTH (SAM_SERCOM4_BASE + SAM_USART_LENGTH_OFFSET)
#define SAM_USART4_DATA (SAM_SERCOM4_BASE + SAM_USART_DATA_OFFSET)
#define SAM_USART4_DBGCTRL (SAM_SERCOM4_BASE + SAM_USART_DBGCTRL_OFFSET)
#define SAM_USART5_CTRLA (SAM_SERCOM5_BASE + SAM_USART_CTRLA_OFFSET)
#define SAM_USART5_CTRLB (SAM_SERCOM5_BASE + SAM_USART_CTRLB_OFFSET)
#define SAM_USART5_CTRLC (SAM_SERCOM5_BASE + SAM_USART_CTRLC_OFFSET)
#define SAM_USART5_BAUD (SAM_SERCOM5_BASE + SAM_USART_BAUD_OFFSET)
#define SAM_USART5_RXPL (SAM_SERCOM5_BASE + SAM_USART_RXPL_OFFSET)
#define SAM_USART5_INTENCLR (SAM_SERCOM5_BASE + SAM_USART_INTENCLR_OFFSET)
#define SAM_USART5_INTENSET (SAM_SERCOM5_BASE + SAM_USART_INTENSET_OFFSET)
#define SAM_USART5_INTFLAG (SAM_SERCOM5_BASE + SAM_USART_INTFLAG_OFFSET)
#define SAM_USART5_STATUS (SAM_SERCOM5_BASE + SAM_USART_STATUS_OFFSET)
#define SAM_USART5_SYNCBUSY (SAM_SERCOM5_BASE + SAM_USART_SYNCBUSY_OFFSET)
#define SAM_USART5_RXERRCNT (SAM_SERCOM5_BASE + SAM_USART_RXERRCNT_OFFSET)
#define SAM_USART5_LENGTH (SAM_SERCOM5_BASE + SAM_USART_LENGTH_OFFSET)
#define SAM_USART5_DATA (SAM_SERCOM5_BASE + SAM_USART_DATA_OFFSET)
#define SAM_USART5_DBGCTRL (SAM_SERCOM5_BASE + SAM_USART_DBGCTRL_OFFSET)
#define SAM_USART6_CTRLA (SAM_SERCOM6_BASE + SAM_USART_CTRLA_OFFSET)
#define SAM_USART6_CTRLB (SAM_SERCOM6_BASE + SAM_USART_CTRLB_OFFSET)
#define SAM_USART6_CTRLC (SAM_SERCOM6_BASE + SAM_USART_CTRLC_OFFSET)
#define SAM_USART6_BAUD (SAM_SERCOM6_BASE + SAM_USART_BAUD_OFFSET)
#define SAM_USART6_RXPL (SAM_SERCOM6_BASE + SAM_USART_RXPL_OFFSET)
#define SAM_USART6_INTENCLR (SAM_SERCOM6_BASE + SAM_USART_INTENCLR_OFFSET)
#define SAM_USART6_INTENSET (SAM_SERCOM6_BASE + SAM_USART_INTENSET_OFFSET)
#define SAM_USART6_INTFLAG (SAM_SERCOM6_BASE + SAM_USART_INTFLAG_OFFSET)
#define SAM_USART6_STATUS (SAM_SERCOM6_BASE + SAM_USART_STATUS_OFFSET)
#define SAM_USART6_SYNCBUSY (SAM_SERCOM6_BASE + SAM_USART_SYNCBUSY_OFFSET)
#define SAM_USART6_RXERRCNT (SAM_SERCOM6_BASE + SAM_USART_RXERRCNT_OFFSET)
#define SAM_USART6_LENGTH (SAM_SERCOM6_BASE + SAM_USART_LENGTH_OFFSET)
#define SAM_USART6_DATA (SAM_SERCOM6_BASE + SAM_USART_DATA_OFFSET)
#define SAM_USART6_DBGCTRL (SAM_SERCOM6_BASE + SAM_USART_DBGCTRL_OFFSET)
#define SAM_USART7_CTRLA (SAM_SERCOM7_BASE + SAM_USART_CTRLA_OFFSET)
#define SAM_USART7_CTRLB (SAM_SERCOM7_BASE + SAM_USART_CTRLB_OFFSET)
#define SAM_USART7_CTRLC (SAM_SERCOM7_BASE + SAM_USART_CTRLC_OFFSET)
#define SAM_USART7_BAUD (SAM_SERCOM7_BASE + SAM_USART_BAUD_OFFSET)
#define SAM_USART7_RXPL (SAM_SERCOM7_BASE + SAM_USART_RXPL_OFFSET)
#define SAM_USART7_INTENCLR (SAM_SERCOM7_BASE + SAM_USART_INTENCLR_OFFSET)
#define SAM_USART7_INTENSET (SAM_SERCOM7_BASE + SAM_USART_INTENSET_OFFSET)
#define SAM_USART7_INTFLAG (SAM_SERCOM7_BASE + SAM_USART_INTFLAG_OFFSET)
#define SAM_USART7_STATUS (SAM_SERCOM7_BASE + SAM_USART_STATUS_OFFSET)
#define SAM_USART7_SYNCBUSY (SAM_SERCOM7_BASE + SAM_USART_SYNCBUSY_OFFSET)
#define SAM_USART7_RXERRCNT (SAM_SERCOM7_BASE + SAM_USART_RXERRCNT_OFFSET)
#define SAM_USART7_LENGTH (SAM_SERCOM7_BASE + SAM_USART_LENGTH_OFFSET)
#define SAM_USART7_DATA (SAM_SERCOM7_BASE + SAM_USART_DATA_OFFSET)
#define SAM_USART7_DBGCTRL (SAM_SERCOM7_BASE + SAM_USART_DBGCTRL_OFFSET)
/* USART register bit definitions ***********************************************************/
/* Control A register */
#define USART_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
#define USART_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
#define USART_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */
#define USART_CTRLA_MODE_MASK (7 << USART_CTRLA_MODE_SHIFT)
# define USART_CTRLA_MODE_EXTUSART (0 << USART_CTRLA_MODE_SHIFT) /* USART with external
* clock */
# define USART_CTRLA_MODE_INTUSART (1 << USART_CTRLA_MODE_SHIFT) /* USART with internal
* clock */
#define USART_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */
#define USART_CTRLA_IBON (1 << 8) /* Bit 8: Immediate BUFOVF notification */
#define USART_CTRLA_TXINV (1 << 9) /* Bit 9: Transmit Data Invert */
#define USART_CTRLA_RXINV (1 << 10) /* Bit 10: Receive Data Invert */
#define USART_CTRLA_SAMPR_SHIFT (11) /* Bits 13-15: Sample rate */
#define USART_CTRLA_SAMPR_MASK (7 << USART_CTRLA_SAMPR_SHIFT)
# define USART_CTRLA_SAMPR_16XA (0 << USART_CTRLA_SAMPR_SHIFT) /* 16x oversampling;
* arithmetic baud */
# define USART_CTRLA_SAMPR_16XF (1 << USART_CTRLA_SAMPR_SHIFT) /* 16x oversampling;
* fractional baud */
# define USART_CTRLA_SAMPR_8XA (2 << USART_CTRLA_SAMPR_SHIFT) /* 8x oversampling;
* arithmetic baud */
# define USART_CTRLA_SAMPR_8XF (3 << USART_CTRLA_SAMPR_SHIFT) /* 8x oversampling;
* fractional baud */
# define USART_CTRLA_SAMPR_3XA (4 << USART_CTRLA_SAMPR_SHIFT) /* 3x oversampling;
* arithmetic baud */
#define USART_CTRLA_TXPO_SHIFT (16) /* Bits 16-17: Transmit data pinout */
#define USART_CTRLA_TXPO_MASK (3 << USART_CTRLA_TXPO_SHIFT)
# define USART_CTRLA_TXPAD0_1 (0 << USART_CTRLA_TXPO_SHIFT) /* TxD=PAD0 XCK=PAD1
* RTS/TE=N/A CTS=N/A */
# define USART_CTRLA_TXPAD0_2 (2 << USART_CTRLA_TXPO_SHIFT) /* TxD=PAD0 XCK=N/A
* RTS/TE=PAD2 CTS=PAD3 */
# define USART_CTRLA_TXPAD0_3 (3 << USART_CTRLA_TXPO_SHIFT) /* TxD=PAD0 RTS=PAD1
* RTS/PAD2 CTS=N/A */
#define USART_CTRLA_RXPO_SHIFT (20) /* Bits 20-21: Receive data pinout */
#define USART_CTRLA_RXPO_MASK (3 << USART_CTRLA_RXPO_SHIFT)
# define USART_CTRLA_RXPAD0 (0 << USART_CTRLA_RXPO_SHIFT) /* RxD=SERCOM PAD0 */
# define USART_CTRLA_RXPAD1 (1 << USART_CTRLA_RXPO_SHIFT) /* RxD=SERCOM PAD1 */
# define USART_CTRLA_RXPAD2 (2 << USART_CTRLA_RXPO_SHIFT) /* RxD=SERCOM PAD2 */
# define USART_CTRLA_RXPAD3 (3 << USART_CTRLA_RXPO_SHIFT) /* RxD=SERCOM PAD3 */
#define USART_CTRLA_SAMPA_SHIFT (22) /* Bits 22-23: Sample adjustment */
#define USART_CTRLA_SAMPA_MASK (3 << USART_CTRLA_SAMPA_SHIFT)
# define USART_CTRLA_SAMPA_789 (0 << USART_CTRLA_SAMPA_SHIFT) /* 16x oversampling 7-8-9 */
# define USART_CTRLA_SAMPA_91011 (1 << USART_CTRLA_SAMPA_SHIFT) /* 16x oversampling 9-10-11 */
# define USART_CTRLA_SAMPA_111213 (2 << USART_CTRLA_SAMPA_SHIFT) /* 16x oversampling 11-12-13 */
# define USART_CTRLA_SAMPA_131415 (3 << USART_CTRLA_SAMPA_SHIFT) /* 16x oversampling 13-14-15 */
# define USART_CTRLA_SAMPA_345 (0 << USART_CTRLA_SAMPA_SHIFT) /* 8x oversampling 3-4-5 */
# define USART_CTRLA_SAMPA_456 (1 << USART_CTRLA_SAMPA_SHIFT) /* 8x oversampling 4-5-6 */
# define USART_CTRLA_SAMPA_567 (2 << USART_CTRLA_SAMPA_SHIFT) /* 8x oversampling 5-6-7 */
# define USART_CTRLA_SAMPA_678 (3 << USART_CTRLA_SAMPA_SHIFT) /* 8x oversampling 6-7-8 */
#define USART_CTRLA_FORM_SHIFT (24) /* Bits 24-27: Frame format */
#define USART_CTRLA_FORM_MASK (7 << USART_CTRLA_FORM_SHIFT)
# define USART_CTRLA_FORM_NOPARITY (0 << USART_CTRLA_FORM_SHIFT) /* USART frame (no parity) */
# define USART_CTRLA_FORM_PARITY (1 << USART_CTRLA_FORM_SHIFT) /* USART frame (w/parity) */
# define USART_CTRLA_FORM_LINMSTR (2 << USART_CTRLA_FORM_SHIFT) /* LIN master */
# define USART_CTRLA_FORM_AUTOBAUD (4 << USART_CTRLA_FORM_SHIFT) /* Lin slave; Auto-baud (no parity) */
# define USART_CTRLA_FORM_AUTOBAUDP (5 << USART_CTRLA_FORM_SHIFT) /* Auto-baud (w/ parity) */
# define USART_CTRLA_FORM_ISO7816 (7 << USART_CTRLA_FORM_SHIFT) /* ISO 7816 */
#define USART_CTRLA_CMODE (1 << 28) /* Bit 28: Communication mode */
# define USART_CTRLA_ASYNCH (0)
# define USART_CTRLA_SYNCH USART_CTRLA_CMODE
#define USART_CTRLA_CPOL (1 << 29) /* Bit 29: Clock polarity */
# define USART_CTRLA_CPOL_NORMAL (0) /* Rising XCK edge Falling XCK edge */
# define USART_CTRLA_CPOL_INVERTED USART_CTRLA_CPOL /* Falling XCK edge Rising XCK edge */
#define USART_CTRLA_DORD (1 << 30) /* Bit 30: Data order */
# define USART_CTRLA_MSBFIRST (0)
# define USART_CTRLA_LSBFIRST USART_CTRLA_DORD
/* Control B register */
#define USART_CTRLB_CHSIZE_SHIFT (0) /* Bits 0-2: Character Size */
#define USART_CTRLB_CHSIZE_MASK (7 << USART_CTRLB_CHSIZE_SHIFT)
# define USART_CTRLB_CHSIZE_8BITS (0 << USART_CTRLB_CHSIZE_SHIFT) /* 8 bits */
# define USART_CTRLB_CHSIZE_9BITS (1 << USART_CTRLB_CHSIZE_SHIFT) /* 9 bits */
# define USART_CTRLB_CHSIZE_5BITS (5 << USART_CTRLB_CHSIZE_SHIFT) /* 5 bits */
# define USART_CTRLB_CHSIZE_6BITS (6 << USART_CTRLB_CHSIZE_SHIFT) /* 6 bits */
# define USART_CTRLB_CHSIZE_7BITS (7 << USART_CTRLB_CHSIZE_SHIFT) /* 7 bits */
#define USART_CTRLB_SBMODE (1 << 6) /* Bit 6: Stop bit mode */
# define USART_CTRLB_SBMODE_1 (0)
# define USART_CTRLB_SBMODE_2 USART_CTRLB_SBMODE
#define USART_CTRLB_COLDEN (1 << 8) /* Bit 8: Collision detection enable */
#define USART_CTRLB_SFDE (1 << 9) /* Bit 9: Start of frame detection enable */
#define USART_CTRLB_ENC (1 << 10) /* Bit 10: Encoding format */
# define USART_CTRLB_UNENCODED (0)
# define USART_CTRLB_IRDA USART_CTRLB_ENC
#define USART_CTRLB_PMODE (1 << 13) /* Bit 13: Parity mode */
# define USART_CTRLB_PEVEN (0)
# define USART_CTRLB_PODD USART_CTRLB_PMODE
#define USART_CTRLB_TXEN (1 << 16) /* Bit 16: Transmitter enable */
#define USART_CTRLB_RXEN (1 << 17) /* Bit 17: Receiver enable */
#define USART_CTRLB_LINCMD_SHIFT (24) /* Bits 24-25: Receiver enable */
#define USART_CTRLB_LINCMD_MASK (3 << USART_CTRLB_LINCMD_SHIFT)
# define USART_CTRLB_LINCMD_NORMAL (0 << USART_CTRLB_LINCMD_SHIFT) /* Normal USART transmission */
# define USART_CTRLB_LINCMD_BREAK (1 << USART_CTRLB_LINCMD_SHIFT) /* Break field is transmitted */
# define USART_CTRLB_LINCMD_BSI (2 << USART_CTRLB_LINCMD_SHIFT) /* Break, sync and identifier
* transmitted */
/* Control C register */
#define USART_CTRLC_GTIME_SHIFT (0) /* Bits 0-2: Guard Time */
#define USART_CTRLC_GTIME_MASK (7 << USART_CTRLC_GTIME_SHIFT)
# define USART_CTRLC_GTIME(n) ((uint32_t)(n) << USART_CTRLC_GTIME_SHIFT)
#define USART_CTRLC_BRKLEN_SHIFT (8) /* Bits 8-9: LIN Master Break Length */
#define USART_CTRLC_BRKLEN_MASK (3 << USART_CTRLC_BRKLEN_SHIFT)
# define USART_CTRLC_BRKLEN_13BITS (0 << USART_CTRLC_BRKLEN_SHIFT) /* 13 bit times */
# define USART_CTRLC_BRKLEN_17BITS (1 << USART_CTRLC_BRKLEN_SHIFT) /* 17 bit times */
# define USART_CTRLC_BRKLEN_21BITS (2 << USART_CTRLC_BRKLEN_SHIFT) /* 21 bit times */
# define USART_CTRLC_BRKLEN_26BITS (3 << USART_CTRLC_BRKLEN_SHIFT) /* 26 bit times */
#define USART_CTRLC_HDRDLY_SHIFT (10) /* Bits 10-11: LIN Master Header Delay */
#define USART_CTRLC_HDRDLY_MASK (3 << USART_CTRLC_HDRDLY_SHIFT)
# define USART_CTRLC_HDRDLY_1_1 (0 << USART_CTRLC_HDRDLY_SHIFT) /* 1, 1 bit times */
# define USART_CTRLC_HDRDLY_4_4 (1 << USART_CTRLC_HDRDLY_SHIFT) /* 4, 4 bit times */
# define USART_CTRLC_HDRDLY_8_4 (2 << USART_CTRLC_HDRDLY_SHIFT) /* 8, 4 bit times */
# define USART_CTRLC_HDRDLY_14_4 (3 << USART_CTRLC_HDRDLY_SHIFT) /* 14, 4 bit times */
#define USART_CTRLC_INACK (1 << 16) /* Bit 16: Inhibit Not Acknowledge */
# define USART_CTRLC_NACK (0) /* 0=NACK transmitted */
# define USART_CTRLC_NONACK USART_CTRLC_INACK /* 1=NACK not ransmitted */
#define USART_CTRLC_DSNACK (1 << 17) /* Bit 17: Disable Successive Not Acknowledge */
#define USART_CTRLC_MAXITER_SHIFT (20) /* Bits 20-22: Data 32 Bit */
#define USART_CTRLC_MAXITER_MASK (7 << USART_CTRLC_MAXITER_SHIFT)
# define USART_CTRLC_MAXITER(n) ((uint32_t)(n) << USART_CTRLC_MAXITER_SHIFT)
#define USART_CTRLC_DATA32B_SHIFT (24) /* Bits 24-25: Data 32 Bit */
#define USART_CTRLC_DATA32B_MASK (3 << USART_CTRLC_DATA32B_SHIFT)
# define USART_CTRLC_DATA32B_CHSIZE (0 << USART_CTRLC_DATA32B_SHIFT) /* Read/write per CHSIZE */
# define USART_CTRLC_DATA32B_WRITE (1 << USART_CTRLC_DATA32B_SHIFT) /* Read CHSIZE; Write 32b */
# define USART_CTRLC_DATA32B_READ (2 << USART_CTRLC_DATA32B_SHIFT) /* Write CHSIZE; Read 32b */
# define USART_CTRLC_DATA32B_BOTH (3 << USART_CTRLC_DATA32B_SHIFT) /* Both per 32-bit extension */
/* Baud register (16-bit baud value) */
/* Receive pulse length register (8-bit value) */
/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and
* status clear registers.
*/
#define USART_INT_DRE (1 << 0) /* Bit 0: Data register empty interrupt */
#define USART_INT_TXC (1 << 1) /* Bit 1: Transmit complete interrupt */
#define USART_INT_RXC (1 << 2) /* Bit 2: Receive complete interrupt */
#define USART_INT_RXS (1 << 3) /* Bit 3: Receive start interrupt */
#define USART_INT_CTSIC (1 << 4) /* Bit 4: Clear to send input change interrupt */
#define USART_INT_RXBRK (1 << 5) /* Bit 5: Receive break interrupt */
#define USART_INT_ERROR (1 << 6) /* Bit 7: Error interrupt */
#define USART_INT_ALL (0xbf)
/* Status register */
#define USART_STATUS_PERR (1 << 0) /* Bit 0: Parity error */
#define USART_STATUS_FERR (1 << 1) /* Bit 1: Frame error */
#define USART_STATUS_BUFOVF (1 << 2) /* Bit 2: Buffer overflow */
#define USART_STATUS_CTS (1 << 3) /* Bit 3: Clear to send */
#define USART_STATUS_ISF (1 << 4) /* Bit 4: Inconsistent sync field */
#define USART_STATUS_COLL (1 << 5) /* Bit 5: Collision detected */
#define USART_STATUS_TXE (1 << 6) /* Bit 6: Transmitter Empty */
#define USART_STATUS_ITER (1 << 7) /* Bit 7: Maximum Number of Repetitions Reached */
/* Synchronization busy register */
#define USART_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset synchronization busy */
#define USART_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: SERCOM enable synchronization busy */
#define USART_SYNCBUSY_CTRLB (1 << 2) /* Bit 2: CTRLB synchronization busy */
#define USART_SYNCBUSY_RXERRCNT (1 << 3) /* Bit 3: Receive error count synchronization busy */
#define USART_SYNCBUSY_LENGTH (1 << 4) /* Bit 4: LENGTH synchronization busy */
#define USART_SYNCBUSY_ALL 0x001f
/* Receive error count register (8-bit value) */
/* Length register */
#define USART_LENGTH_LEN_SHIFT (0) /* Bit 0-7: Data length */
#define USART_LENGTH_LEN_MASK (0xff << USART_LENGTH_LEN_SHIFT)
# define USART_LENGTHLEN(n) ((uint32_t)(n) << USART_LENGTH_LEN_SHIFT)
#define USART_LENGTH_LENEN_SHIFT (8) /* Bits 8-9: Data Length Enable */
#define USART_LENGTH_LENEN_MASK (3 << USART_LENGTH_LENEN_SHIFT)
# define USART_LENGTH_LENEN_DISABLE (0 << USART_LENGTH_LENEN_SHIFT) /* Length counter disabled */
# define USART_LENGTH_LENEN_XMIT (1 << USART_LENGTH_LENEN_SHIFT) /* Enabled for transmit */
# define USART_LENGTH_LENEN_RECV (2 << USART_LENGTH_LENEN_SHIFT) /* Enabled for receive */
/* Data register (8-, 9- or 32-bit data) */
#define USART_DATA_MASK9 (0x1ff) /* Bits 0-8: 8- or 9-bit Data */
/* Debug control register */
#define USART_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_USART_H */
arch/arm/src/samd5e5/chip/sam_wdt.h
+160
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/********************************************************************************************
* arch/arm/src/samd5e5/chip/sam_wdt.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_WDT_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_WDT_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* WDT register offsets *********************************************************************/
#define SAM_WDT_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_WDT_CONFIG_OFFSET 0x0001 /* Configuration register */
#define SAM_WDT_EWCTRL_OFFSET 0x0002 /* Early warning interrupt control register */
#define SAM_WDT_INTENCLR_OFFSET 0x0004 /* Interrupt enable clear register */
#define SAM_WDT_INTENSET_OFFSET 0x0005 /* Interrupt enable set register */
#define SAM_WDT_INTFLAG_OFFSET 0x0006 /* Interrupt flag and status clear register */
#define SAM_WDT_SYNCBUSY_OFFSET 0x0008 /* Synchronization busy register */
#define SAM_WDT_CLEAR_OFFSET 0x000c /* Clear register */
/* WDT register addresses *******************************************************************/
#define SAM_WDT_CTRLA (SAM_WDT_BASE + SAM_WDT_CTRLA_OFFSET)
#define SAM_WDT_CONFIG (SAM_WDT_BASE + SAM_WDT_CONFIG_OFFSET)
#define SAM_WDT_EWCTRL (SAM_WDT_BASE + SAM_WDT_EWCTRL_OFFSET)
#define SAM_WDT_INTENCLR (SAM_WDT_BASE + SAM_WDT_INTENCLR_OFFSET)
#define SAM_WDT_INTENSET (SAM_WDT_BASE + SAM_WDT_INTENSET_OFFSET)
#define SAM_WDT_INTFLAG (SAM_WDT_BASE + SAM_WDT_INTFLAG_OFFSET)
#define SAM_WDT_SYNCBUSY (SAM_WDT_BASE + SAM_WDT_SYNCBUSY_OFFSET)
#define SAM_WDT_CLEAR (SAM_WDT_BASE + SAM_WDT_CLEAR_OFFSET)
/* WDT register bit definitions *************************************************************/
/* Control register */
#define WDT_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
#define WDT_CTRLA_WEN (1 << 2) /* Bit 2: Watchdog Timer Window Mode Enable */
#define WDT_CTRLA_ALWAYSON (1 << 7) /* Bit 7: Always-On */
/* Configuration register */
#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0–3: Time-Out Period */
#define WDT_CONFIG_PER_MASK (15 << WDT_CONFIG_PER_SHIFT)
# define WDT_CONFIG_PER_8 (0 << WDT_CONFIG_PER_SHIFT) /* 8 clock cycles */
# define WDT_CONFIG_PER_16 (1 << WDT_CONFIG_PER_SHIFT) /* 16 clock cycles */
# define WDT_CONFIG_PER_32 (2 << WDT_CONFIG_PER_SHIFT) /* 32 clock cycles */
# define WDT_CONFIG_PER_64 (3 << WDT_CONFIG_PER_SHIFT) /* 64 clock cycles */
# define WDT_CONFIG_PER_128 (4 << WDT_CONFIG_PER_SHIFT) /* 128 clock cycles */
# define WDT_CONFIG_PER_256 (5 << WDT_CONFIG_PER_SHIFT) /* 256 clocks cycles */
# define WDT_CONFIG_PER_512 (6 << WDT_CONFIG_PER_SHIFT) /* 512 clocks cycles */
# define WDT_CONFIG_PER_1K (7 << WDT_CONFIG_PER_SHIFT) /* 1024 clock cycles */
# define WDT_CONFIG_PER_2K (8 << WDT_CONFIG_PER_SHIFT) /* 2048 clock cycles */
# define WDT_CONFIG_PER_4K (9 << WDT_CONFIG_PER_SHIFT) /* 4096 clock cycles */
# define WDT_CONFIG_PER_8k (10 << WDT_CONFIG_PER_SHIFT) /* 8192 clock cycles */
# define WDT_CONFIG_PER_16K (11 << WDT_CONFIG_PER_SHIFT) /* 16384 clock cycles */
#define WDT_CONFIG_WINDOW_SHIFT (4) /* Bits 4-7: Window Mode Time-Out Period */
#define WDT_CONFIG_WINDOW_MASK (15 << WDT_CONFIG_WINDOW_SHIFT)
# define WDT_CONFIG_WINDOW_8 (0 << WDT_CONFIG_WINDOW_SHIFT) /* 8 clock cycles */
# define WDT_CONFIG_WINDOW_16 (1 << WDT_CONFIG_WINDOW_SHIFT) /* 16 clock cycles */
# define WDT_CONFIG_WINDOW_32 (2 << WDT_CONFIG_WINDOW_SHIFT) /* 32 clock cycles */
# define WDT_CONFIG_WINDOW_64 (3 << WDT_CONFIG_WINDOW_SHIFT) /* 64 clock cycles */
# define WDT_CONFIG_WINDOW_128 (4 << WDT_CONFIG_WINDOW_SHIFT) /* 128 clock cycles */
# define WDT_CONFIG_WINDOW_256 (5 << WDT_CONFIG_WINDOW_SHIFT) /* 256 clocks cycles */
# define WDT_CONFIG_WINDOW_512 (6 << WDT_CONFIG_WINDOW_SHIFT) /* 512 clocks cycles */
# define WDT_CONFIG_WINDOW_1K (7 << WDT_CONFIG_WINDOW_SHIFT) /* 1024 clock cycles */
# define WDT_CONFIG_WINDOW_2K (8 << WDT_CONFIG_WINDOW_SHIFT) /* 2048 clock cycles */
# define WDT_CONFIG_WINDOW_4K (9 << WDT_CONFIG_WINDOW_SHIFT) /* 4096 clock cycles */
# define WDT_CONFIG_WINDOW_8k (10 << WDT_CONFIG_WINDOW_SHIFT) /* 8192 clock cycles */
/* Early warning interrupt control register */
#define WDT_EWCTRL_EWOFFSET_SHIFT (0) /* Bits 0-3: Early warning interrupt time offset */
#define WDT_EWCTRL_EWOFFSET_MASK (15 << WDT_EWCTRL_EWOFFSET_SHIFT)
# define WDT_EWCTRL_EWOFFSET_8 (0 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 8 clock cycles */
# define WDT_EWCTRL_EWOFFSET_16 (1 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 16 clock cycles */
# define WDT_EWCTRL_EWOFFSET_32 (2 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 32 clock cycles */
# define WDT_EWCTRL_EWOFFSET_64 (3 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 64 clock cycles */
# define WDT_EWCTRL_EWOFFSET_128 (4 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 128 clock cycles */
# define WDT_EWCTRL_EWOFFSET_256 (5 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 256 clocks cycles */
# define WDT_EWCTRL_EWOFFSET_512 (6 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 512 clocks cycles */
# define WDT_EWCTRL_EWOFFSET_1K (7 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 1024 clock cycles */
# define WDT_EWCTRL_EWOFFSET_2K (8 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 2048 clock cycles */
# define WDT_EWCTRL_EWOFFSET_4K (9 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 4096 clock cycles */
# define WDT_EWCTRL_EWOFFSET_8k (10 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 8192 clock cycles */
# define WDT_EWCTRL_EWOFFSET_16K (11 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 16384 clock cycles */
/* Interrupt enable clear, interrupt enable set register, interrupt flag status and clear
* registers
*/
#define WDT_INT_EW (1 << 0) /* Bit 0: Early warning interrupt */
#define WDT_INT_All (0x01)
/* Synchronization busy register */
#define WDT_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: Enable syncrhonization busy */
#define WDT_SYNCBUSY_WEN (1 << 2) /* Bit 2: Window enable synchronization busy */
#define WDT_SYNCBUSY_ALWAYSON (1 << 3) /* Bit 3: Always-on synchronization busy */
#define WDT_SYNCBUSY_CLEAR (1 << 4) /* Bit 4: Clear syncrhonization busy */
/* Clear register */
#define WDT_CLEAR_CLEAR_SHIFT (0) /* Bits 0-7: Watchdog clear */
#define WDT_CLEAR_CLEAR_MASK (0xff << WDT_CLEAR_CLEAR_SHIFT)
# define WDT_CLEAR_CLEAR (0xa5 << WDT_CLEAR_CLEAR_SHIFT)
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_WDT_H */
arch/arm/src/samd5e5/chip/samd5e5_memorymap.h
+157
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/********************************************************************************************
* arch/arm/src/samd5e5/chip/samd5e5_memorymap.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAMD5E5_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAMD5E5_MEMORYMAP_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* System Memory Map */
#define SAM_CODE_BASE 0x00000000 /* Code address space */
# define SAM_FLASH_BASE 0x00000000 /* FLASH address space */
# define SAM_CMCC_BASE 0x03000000 /* CMCC address space */
# define SAM_QSPI_BASE 0x04000000 /* QSPI address space */
#define SAM_SRAM_BASE 0x20000000 /* SRAM address space */
#define SAM_PERIPH_BASE 0x40000000 /* Peripherals memory space */
# define SAM_AHBA_BASE 0x40000000 /* AHB-APB Bridge A */
# define SAM_AHBB_BASE 0x41000000 /* AHB-APB Bridge B */
# define SAM_AHBC_BASE 0x42000000 /* AHB-APB Bridge C */
# define SAM_AHBD_BASE 0x43000000 /* AHB-APB Bridge D */
# define SAM_SEEPROM_BASE 0x44000000 /* SEEPROM */
# define SAM_SDHC0_BASE 0x45000000 /* Memory card interface (SDHC0) */
# define SAM_SDHC1_BASE 0x46000000 /* Memory card interface (SDHC1) */
# define SAM_BKPRAM_BASE 0x47000000 /* Backup RAM */
#define SAM_SYSTEM_BASE 0xe0000000 /* System address space */
# define SAM_SCS_BASE 0xe000e000 /* SCSS */
# define SAM_ROMTAB_BASE 0xe000ff00 /* ROM table */
/* AHB-APB Bridge A */
#define SAM_PAC_BASE 0x40000000 /* Peripheral Access Controller 0 */
#define SAM_PM_BASE 0x40000400 /* Power Manager (PM) */
#define SAM_MCLK_BASE 0x40000800 /* Main clock (MCLK) */
#define SAM_RSTC_BASE 0x40000c00 /* Reset Controller (RSTC) */
#define SAM_OSCCTRL_BASE 0x40001000 /* OSCCTRL */
#define SAM_OSC32KCTRL_BASE 0x40001400 /* OSC32KCTRL */
#define SAM_SUPC_BASE 0x40001800 /* Supply Controller (SUPC) */
#define SAM_GCLK_BASE 0x40001c00 /* Generic Clock Controller */
#define SAM_WDT_BASE 0x40002000 /* Watchdog Timer */
#define SAM_RTC_BASE 0x40002400 /* Real-Time Counter */
#define SAM_EIC_BASE 0x40002800 /* External Interrupt Controller */
#define SAM_FREQM_BASE 0x40002c00 /* Frequency Meter (FREQM) */
#define SAM_SERCOM0_BASE 0x40003000 /* Serial Communication Interface 0 */
#define SAM_SERCOM1_BASE 0x40003400 /* Serial Communication Interface 1 */
#define SAM_TC0_BASE 0x40003800 /* Timer/Counter 2 */
#define SAM_TC1_BASE 0x40003c00 /* Timer/Counter 3 */
/* Reserved */
/* AHB-APB Bridge B */
#define SAM_USB_BASE 0x41000000 /* USB */
#define SAM_DSU_BASE 0x41002000 /* Device Service Unit (DSU) */
#define SAM_NVMCTRL_BASE 0x41004000 /* Non-Volatile Memory Controller (NVMCTRL) */
#define SAM_CMCCC_BASE 0x41006000 /* Cortex-M Cache Controller (CMCC) */
#define SAM_PORT_BASE 0x41008000 /* Ports */
#define SAM_DMAC_BASE 0x4100a000 /* DMA Controller */
/* Reserved */
#define SAM_EVSYS_BASE 0x4100e000 /* Event System */
/* Reserved */
#define SAM_SERCOM2_BASE 0x41001200 /* Serial Communication Interface 2 */
#define SAM_SERCOM3_BASE 0x41001400 /* Serial Communication Interface 3 */
#define SAM_TCC0_BASE 0x41001600 /* Timer/Counter Control 0 */
#define SAM_TCC1_BASE 0x41001800 /* Timer/Counter Control 1 */
#define SAM_TC2_BASE 0x41001a00 /* Timer/Counter 2 */
#define SAM_TC3_BASE 0x41001c00 /* Timer/Counter 3 */
/* Reserved */
#define SAM_RAMECC_BASE 0x41002000 /* RAM Error Correction Code (RAMECC) */
/* Reserved */
/* AHB-APB Bridge C */
#define SAM_CAN0_BASE 0x42000000 /* CAN0 */
#define SAM_CAN1_BASE 0x42000400 /* CAN1 */
#define SAM_GMAC_BASE 0x42000800 /* GMAC */
#define SAM_TCC2_BASE 0x42000c00 /* Timer/Counter Control 2 */
#define SAM_TCC3_BASE 0x42001000 /* Timer/Counter Control 3 */
#define SAM_TC4_BASE 0x42001400 /* Timer/Counter 4 */
#define SAM_TC5_BASE 0x42001800 /* Timer/Counter 5 */
#define SAM_PDEC_BASE 0x42001c00 /* Position Decoder (PDEC) */
#define SAM_AC_BASE 0x42002000 /* Analog Comparator (AC) */
#define SAM_AES_BASE 0x42002400 /* Advanced Encryption Standard (AES) */
#define SAM_TRNG_BASE 0x42002800 /* True Random Number Generator (TRNG) */
#define SAM_ICM_BASE 0x42002c00 /* Integrity Check Monitor (ICM) */
#define SAM_PUKCC_BASE 0x42003000 /* Public-Key Cryptography Controller (PUKCC) */
#define SAM_QSPIC_BASE 0x42003400 /* QSPI controller */
#define SAM_CCL_BASE 0x42003800 /* Configurable Custom Logic (CCL) */
/* Reserved */
/* AHB-APB Bridge D */
#define SAM_SERCOM4_BASE 0x43000000 /* Serial Communication Interface 4 */
#define SAM_SERCOM5_BASE 0x43000400 /* Serial Communication Interface 5 */
#define SAM_SERCOM6_BASE 0x43000800 /* Serial Communication Interface 6 */
#define SAM_SERCOM7_BASE 0x43000c00 /* Serial Communication Interface 7 */
#define SAM_TCC4_BASE 0x43001000 /* Timer/Counter Control 4 */
#define SAM_TC6_BASE 0x43001400 /* Timer/Counter 6 */
#define SAM_TC7_BASE 0x43001800 /* Timer/Counter 7 */
#define SAM_ADC0_BASE 0x43001c00 /* Analog-to-Digital Converter 0 (ADC0) */
#define SAM_ADC1_BASE 0x43002000 /* Analog-to-Digital Converter 1 (ADC1) */
#define SAM_DAC_BASE 0x43002400 /* Digital-to-Analog Converter (DAC) */
#define SAM_I2S_BASE 0x43002800 /* Inter IC Sound (I2S) */
#define SAM_PCC_BASE 0x44002c00 /* Parallel Capture Controller (PCC) */
/* Reserved */
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAMD5E5_MEMORYMAP_H */
arch/arm/src/samd5e5/chip/samd5e5_pinmap.h
+790
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arch/arm/src/samd5e5/sam_clockconfig.c
+1361
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arch/arm/src/samd5e5/sam_clockconfig.h
+94
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@@ -0,0 +1,94 @@
/************************************************************************************
* arch/arm/src/samd5e5/sam_clockconfig.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_SAM_CLOCKCONFIG_H
#define __ARCH_ARM_SRC_SAMD5E5_SAM_CLOCKCONFIG_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Data
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
* Name: sam_clockconfig
*
* Description:
* Called to initialize the SAM3/4. This does whatever setup is needed to put the
* SoC in a usable state. This includes the initialization of clocking using the
* settings in board.h.
*
************************************************************************************/
void sam_clockconfig(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMD5E5_SAM_CLOCKCONFIG_H */
arch/arm/src/samd5e5/sam_cmcc.c
+234
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/****************************************************************************
* arch/arm/src/samd5e5/sam_cmcc.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <assert.h>
#include "up_arch.h"
#include "chip/sam_cmcc.h"
#include "sam_cmcc.h"
#ifdef CONFIG_SAMD5E5_CMCC
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define CMCC_MASK (CMCC_CACHE_LINE_SIZE-1)
#if CMCC_CACHE_LINE_SIZE == 4
# define CMCC_SHIFT 2
#elif CMCC_CACHE_LINE_SIZE == 8
# define CMCC_SHIFT 3
#elif CMCC_CACHE_LINE_SIZE == 16
# define CMCC_SHIFT 4
#elif CMCC_CACHE_LINE_SIZE == 32
# define CMCC_SHIFT 5
#else
# error Unknown cache line size
#endif
#define ALIGN_UP(a) (((a)+CMCC_MASK) & ~CMCC_MASK)
#define ALIGN_DOWN(a) ((a) & ~CMCC_MASK)
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: sam_cmcc_enable
*
* Description:
* Enable the Cortex-M Cache Controller
*
****************************************************************************/
void sam_cmcc_enable(void)
{
/* "On reset, the cache controller data entries are all invalidated and the
* cache is disabled. The cache is transparent to processor operations. The
* cache controller is activated with its configuration registers. The
* configuration interface is memory mapped in the private peripheral bus.
*
* "Use the following sequence to enable the cache controller.
*
* "1. Verify that the cache controller is disabled, reading the value of the
* CSTS (cache status) field of the CMCC_SR register.
* "2. Enable the cache controller, writing 1 to the CEN (cache enable) field
* of the CMCC_CTRL register."
*/
if ((getreg32(SAM_CMCC_SR) & CMCC_SR_CSTS) == 0)
{
putreg32(CMCC_CTRL_CEN, SAM_CMCC_CTRL);
}
}
/****************************************************************************
* Name: sam_cmcc_disable
*
* Description:
* Disable the Cortex-M Cache Controller
*
****************************************************************************/
void sam_cmcc_disable(void)
{
/* "1. Disable the cache controller, writing 0 to the CEN field of the
* CMCC_CTRL register.
* "2. Check CSTS field of the CMCC_SR to verify that the cache is
* successfully disabled.
*/
putreg32(0, SAM_CMCC_CTRL);
while ((getreg32(SAM_CMCC_SR) & CMCC_SR_CSTS) != 0);
}
/****************************************************************************
* Name: sam_cmcc_invalidate
*
* Description:
* Invalidate a range of addresses. Note: These addresses should be
* aligned with the beginning and end of cache lines. Otherwise, values
* at the edges of the region will also be invalidated!
*
****************************************************************************/
void sam_cmcc_invalidate(uintptr_t start, uintptr_t end)
{
uintptr_t addr;
uint32_t regval;
ssize_t size;
int index;
int way;
/* Get the aligned addresses and size (in bytes) for the memory region
* to be invalidated.
*/
start = ALIGN_DOWN(start);
end = ALIGN_UP(end);
size = end - start + 1;
/* If this is a large region (as big as the cache), then just invalidate
* the entire cache the easy way.
*
* CacheSize = CacheLineSize * NCacheLines * NWays
* CacheAddressRange = CacheLineSize * NCacheLines = CacheSize / NWays
*
* Example: CacheSize = 2048, CacheLineSize=16, NWays=4:
*
* CacheAddressRange = 2048 / 4 = 512
* NCacheLines = 32
*/
if (size >= (CMCC_CACHE_SIZE / CMCC_NWAYS))
{
sam_cmcc_invalidateall();
return;
}
/* "When an invalidate by line command is issued the cache controller resets
* the valid bit information of the decoded cache line. As the line is no
* longer valid the replacement counter points to that line.
*
* "Use the following sequence to invalidate one line of cache.
*
* "1. Disable the cache controller, writing 0 to the CEN field of the
* CMCC_CTRL register.
* "2. Check CSTS field of the CMCC_SR to verify that the cache is
* successfully disabled.
* "3. Perform an invalidate by line writing the bit set {index, way} in
* the CMCC_MAINT1 register.
* "4. Enable the cache controller, writing 1 to the CEN field of the
* CMCC_CTRL register."
*/
/* Disable the cache controller */
sam_cmcc_disable();
/* Invalidate the address region */
for (addr = start, index = (int)(start >> CMCC_SHIFT);
addr <= end;
addr += CMCC_CACHE_LINE_SIZE, index++)
{
regval = CMCC_MAINT1_INDEX(index);
for (way = 0; way < CMCC_NWAYS; way++)
{
putreg32(regval | CMCC_MAINT1_WAY(way), SAM_CMCC_MAINT1);
}
}
/* Re-enable the cache controller */
sam_cmcc_enable();
}
/****************************************************************************
* Name: sam_cmcc_invalidateall
*
* Description:
* Invalidate the entire cache
*
****************************************************************************/
void sam_cmcc_invalidateall(void)
{
/* "To invalidate all cache entries:
*
* " Write 1 to the INVALL field of the CMCC_MAINT0 register."
*/
putreg32(CMCC_MAINT0_INVALL, SAM_CMCC_MAINT0);
}
#endif /* CONFIG_SAMD5E5_CMCC */
arch/arm/src/samd5e5/sam_cmcc.h
+136
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/************************************************************************************
* arch/arm/src/samd5e5/sam_cmcc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_SAM_CMCC_H
#define __ARCH_ARM_SRC_SAMD5E5_SAM_CMCC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#ifdef CONFIG_SAMD5E5_CMCC
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Data
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/****************************************************************************
* Name: sam_cmcc_enable
*
* Description:
* Enable the Cortex-M Cache Controller
*
****************************************************************************/
void sam_cmcc_enable(void);
/****************************************************************************
* Name: sam_cmcc_disable
*
* Description:
* Disable the Cortex-M Cache Controller
*
****************************************************************************/
void sam_cmcc_disable(void);
/****************************************************************************
* Name: sam_cmcc_invalidate
*
* Description:
* Invalidate a range of addresses. Note: These addresses should be
* aligned with the beginning and end of cache lines. Otherwise, values
* at the edges of the region will also be invalidated!
*
****************************************************************************/
void sam_cmcc_invalidate(uintptr_t start, uintptr_t end);
/****************************************************************************
* Name: sam_cmcc_invalidateall
*
* Description:
* Invalidate the entire cache
*
****************************************************************************/
void sam_cmcc_invalidateall(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#else /* CONFIG_SAMD5E5_CMCC */
/* Stubs so that we don't have to put condition compilation in driver source */
# define sam_cmcc_invalidate(start, end)
# define sam_cmcc_invalidateall()
#endif /* CONFIG_SAMD5E5_CMCC */
#endif /* __ARCH_ARM_SRC_SAMD5E5_SAM_CMCC_H */
arch/arm/src/samd5e5/sam_config.h
+372
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@@ -0,0 +1,372 @@
/************************************************************************************
* arch/arm/src/samd5e5/sam_config.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_SAM_CONFIG_H
#define __ARCH_ARM_SRC_SAMD5E5_SAM_CONFIG_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* How many SERCOM peripherals are configured as USART peripherals? */
#define SAMD5E5_HAVE_USART0 1
#define SAMD5E5_HAVE_USART1 1
#define SAMD5E5_HAVE_USART2 1
#define SAMD5E5_HAVE_USART3 1
#define SAMD5E5_HAVE_USART4 1
#define SAMD5E5_HAVE_USART5 1
#define SAMD5E5_HAVE_USART6 1
#define SAMD5E5_HAVE_USART7 1
#if !defined(CONFIG_SAMD5E5_SERCOM0) || !defined(CONFIG_SAMD5E5_SERCOM0_ISUSART) || \
!defined(CONFIG_USART0_SERIALDRIVER)
# undef SAMD5E5_HAVE_USART0
# undef CONFIG_SAMD5E5_SERCOM0_ISUSART
# undef CONFIG_USART0_SERIAL_CONSOLE
# undef CONFIG_USART0_FLOWCONTROL
# undef CONFIG_USART0_IRDAMODE
# undef CONFIG_USART0_RS485MODE
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM1) || !defined(CONFIG_SAMD5E5_SERCOM1_ISUSART) || \
!defined(CONFIG_USART1_SERIALDRIVER)
# undef SAMD5E5_HAVE_USART1
# undef CONFIG_SAMD5E5_SERCOM1_ISUSART
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART1_FLOWCONTROL
# undef CONFIG_USART1_IRDAMODE
# undef CONFIG_USART1_RS485MODE
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM2) || !defined(CONFIG_SAMD5E5_SERCOM2_ISUSART) || \
!defined(CONFIG_USART2_SERIALDRIVER)
# undef SAMD5E5_HAVE_USART2
# undef CONFIG_SAMD5E5_SERCOM2_ISUSART
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART2_FLOWCONTROL
# undef CONFIG_USART2_IRDAMODE
# undef CONFIG_USART2_RS485MODE
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM3) || !defined(CONFIG_SAMD5E5_SERCOM3_ISUSART) || \
!defined(CONFIG_USART3_SERIALDRIVER)
# undef SAMD5E5_HAVE_USART3
# undef CONFIG_SAMD5E5_SERCOM3_ISUSART
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_USART3_FLOWCONTROL
# undef CONFIG_USART3_IRDAMODE
# undef CONFIG_USART3_RS485MODE
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM4) || !defined(CONFIG_SAMD5E5_SERCOM4_ISUSART) || \
!defined(CONFIG_USART4_SERIALDRIVER)
# undef SAMD5E5_HAVE_USART4
# undef CONFIG_SAMD5E5_SERCOM4_ISUSART
# undef CONFIG_USART4_SERIAL_CONSOLE
# undef CONFIG_USART4_FLOWCONTROL
# undef CONFIG_USART4_IRDAMODE
# undef CONFIG_USART4_RS485MODE
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM5) || !defined(CONFIG_SAMD5E5_SERCOM5_ISUSART) || \
!defined(CONFIG_USART5_SERIALDRIVER)
# undef SAMD5E5_HAVE_USART5
# undef CONFIG_SAMD5E5_SERCOM5_ISUSART
# undef CONFIG_USART5_SERIAL_CONSOLE
# undef CONFIG_USART5_FLOWCONTROL
# undef CONFIG_USART5_IRDAMODE
# undef CONFIG_USART5_RS485MODE
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM6) || !defined(CONFIG_SAMD5E5_SERCOM6_ISUSART) || \
!defined(CONFIG_USART6_SERIALDRIVER)
# undef SAMD5E5_HAVE_USART6
# undef CONFIG_SAMD5E5_SERCOM6_ISUSART
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_USART6_FLOWCONTROL
# undef CONFIG_USART6_IRDAMODE
# undef CONFIG_USART6_RS485MODE
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM7) || !defined(CONFIG_SAMD5E5_SERCOM7_ISUSART) || \
!defined(CONFIG_USART7_SERIALDRIVER)
# undef SAMD5E5_HAVE_USART7
# undef CONFIG_SAMD5E5_SERCOM7_ISUSART
# undef CONFIG_USART7_SERIAL_CONSOLE
# undef CONFIG_USART7_FLOWCONTROL
# undef CONFIG_USART7_IRDAMODE
# undef CONFIG_USART7_RS485MODE
#endif
/* Are any USARTs enabled? */
#undef SAMD5E5_HAVE_USART
#if defined(SAMD5E5_HAVE_USART0) || defined(SAMD5E5_HAVE_USART1) || \
defined(SAMD5E5_HAVE_USART2) || defined(SAMD5E5_HAVE_USART3) || \
defined(SAMD5E5_HAVE_USART4) || defined(SAMD5E5_HAVE_USART5) || \
defined(SAMD5E5_HAVE_USART6) || defined(SAMD5E5_HAVE_USART7)
# define SAMD5E5_HAVE_USART 1
#endif
/* Is there a serial console? There should be at most one defined. It could be on
* any USARTn, n=0-5 - OR - there might not be any serial console at all.
*/
#if defined(CONFIG_USART0_SERIAL_CONSOLE)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_USART4_SERIAL_CONSOLE
# undef CONFIG_USART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_USART7_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_USART1_SERIAL_CONSOLE)
# undef CONFIG_USART0_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_USART4_SERIAL_CONSOLE
# undef CONFIG_USART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_USART7_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_USART2_SERIAL_CONSOLE)
# undef CONFIG_USART0_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_USART4_SERIAL_CONSOLE
# undef CONFIG_USART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_USART7_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_USART3_SERIAL_CONSOLE)
# undef CONFIG_USART0_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART4_SERIAL_CONSOLE
# undef CONFIG_USART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_USART7_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_USART4_SERIAL_CONSOLE)
# undef CONFIG_USART0_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_USART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_USART7_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_USART5_SERIAL_CONSOLE)
# undef CONFIG_USART0_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_USART4_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_USART7_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_USART6_SERIAL_CONSOLE)
# undef CONFIG_USART0_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_USART4_SERIAL_CONSOLE
# undef CONFIG_USART5_SERIAL_CONSOLE
# undef CONFIG_USART7_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_USART7_SERIAL_CONSOLE)
# undef CONFIG_USART0_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_USART4_SERIAL_CONSOLE
# undef CONFIG_USART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#else
# undef CONFIG_USART0_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_USART4_SERIAL_CONSOLE
# undef CONFIG_USART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_USART7_SERIAL_CONSOLE
# undef HAVE_SERIAL_CONSOLE
#endif
/* Are any SERCOM peripherals are configured as SPI peripherals? */
#define SAMD5E5_HAVE_SPI0 1
#define SAMD5E5_HAVE_SPI1 1
#define SAMD5E5_HAVE_SPI2 1
#define SAMD5E5_HAVE_SPI3 1
#define SAMD5E5_HAVE_SPI4 1
#define SAMD5E5_HAVE_SPI5 1
#define SAMD5E5_HAVE_SPI6 1
#define SAMD5E5_HAVE_SPI7 1
#if !defined(CONFIG_SAMD5E5_SERCOM0) || !defined(CONFIG_SAMD5E5_SERCOM0_ISSPI)
# undef SAMD5E5_HAVE_SPI0
# undef CONFIG_SAMD5E5_SERCOM0_ISSPI
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM1) || !defined(CONFIG_SAMD5E5_SERCOM1_ISSPI)
# undef SAMD5E5_HAVE_SPI1
# undef CONFIG_SAMD5E5_SERCOM1_ISSPI
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM2) || !defined(CONFIG_SAMD5E5_SERCOM2_ISSPI)
# undef SAMD5E5_HAVE_SPI2
# undef CONFIG_SAMD5E5_SERCOM2_ISSPI
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM3) || !defined(CONFIG_SAMD5E5_SERCOM3_ISSPI)
# undef SAMD5E5_HAVE_SPI3
# undef CONFIG_SAMD5E5_SERCOM3_ISSPI
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM4) || !defined(CONFIG_SAMD5E5_SERCOM4_ISSPI)
# undef SAMD5E5_HAVE_SPI4
# undef CONFIG_SAMD5E5_SERCOM4_ISSPI
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM5) || !defined(CONFIG_SAMD5E5_SERCOM5_ISSPI)
# undef SAMD5E5_HAVE_SPI5
# undef CONFIG_SAMD5E5_SERCOM5_ISSPI
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM6) || !defined(CONFIG_SAMD5E5_SERCOM6_ISSPI)
# undef SAMD5E5_HAVE_SPI6
# undef CONFIG_SAMD5E5_SERCOM6_ISSPI
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM7) || !defined(CONFIG_SAMD5E5_SERCOM7_ISSPI)
# undef SAMD5E5_HAVE_SPI7
# undef CONFIG_SAMD5E5_SERCOM7_ISSPI
#endif
/* Are any SERCOMs configured for SPI? */
#undef SAMD5E5_HAVE_SPI
#if defined(SAMD5E5_HAVE_SPI0) || defined(SAMD5E5_HAVE_SPI1) || \
defined(SAMD5E5_HAVE_SPI2) || defined(SAMD5E5_HAVE_SPI3) || \
defined(SAMD5E5_HAVE_SPI4) || defined(SAMD5E5_HAVE_SPI5) || \
defined(SAMD5E5_HAVE_SPI6) || defined(SAMD5E5_HAVE_SPI7)
# define SAMD5E5_HAVE_SPI 1
#endif
/* Are any SERCOM peripherals are configured as I2C peripherals? */
#define SAMD5E5_HAVE_I2C0 1
#define SAMD5E5_HAVE_I2C1 1
#define SAMD5E5_HAVE_I2C2 1
#define SAMD5E5_HAVE_I2C3 1
#define SAMD5E5_HAVE_I2C4 1
#define SAMD5E5_HAVE_I2C5 1
#define SAMD5E5_HAVE_I2C6 1
#define SAMD5E5_HAVE_I2C7 1
#if !defined(CONFIG_SAMD5E5_SERCOM0) || !defined(CONFIG_SAMD5E5_SERCOM0_ISI2C)
# undef SAMD5E5_HAVE_I2C0
# undef CONFIG_SAMD5E5_SERCOM0_ISI2C
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM1) || !defined(CONFIG_SAMD5E5_SERCOM1_ISI2C)
# undef SAMD5E5_HAVE_I2C1
# undef CONFIG_SAMD5E5_SERCOM1_ISI2C
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM2) || !defined(CONFIG_SAMD5E5_SERCOM2_ISI2C)
# undef SAMD5E5_HAVE_I2C2
# undef CONFIG_SAMD5E5_SERCOM2_ISI2C
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM3) || !defined(CONFIG_SAMD5E5_SERCOM3_ISI2C)
# undef SAMD5E5_HAVE_I2C3
# undef CONFIG_SAMD5E5_SERCOM3_ISI2C
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM4) || !defined(CONFIG_SAMD5E5_SERCOM4_ISI2C)
# undef SAMD5E5_HAVE_I2C4
# undef CONFIG_SAMD5E5_SERCOM4_ISI2C
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM5) || !defined(CONFIG_SAMD5E5_SERCOM5_ISI2C)
# undef SAMD5E5_HAVE_I2C5
# undef CONFIG_SAMD5E5_SERCOM5_ISI2C
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM6) || !defined(CONFIG_SAMD5E5_SERCOM6_ISI2C)
# undef SAMD5E5_HAVE_I2C6
# undef CONFIG_SAMD5E5_SERCOM6_ISI2C
#endif
#if !defined(CONFIG_SAMD5E5_SERCOM7) || !defined(CONFIG_SAMD5E5_SERCOM7_ISI2C)
# undef SAMD5E5_HAVE_I2C7
# undef CONFIG_SAMD5E5_SERCOM7_ISI2C
#endif
/* Are any SERCOMs configured for I2C? */
#undef SAMD5E5_HAVE_I2C
#if defined(SAMD5E5_HAVE_I2C0) || defined(SAMD5E5_HAVE_I2C1) || \
defined(SAMD5E5_HAVE_I2C2) || defined(SAMD5E5_HAVE_I2C3) || \
defined(SAMD5E5_HAVE_I2C4) || defined(SAMD5E5_HAVE_I2C5) || \
defined(SAMD5E5_HAVE_I2C6) || defined(SAMD5E5_HAVE_I2C7)
# define SAMD5E5_HAVE_I2C 1
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_SAM_CONFIG_H */
arch/arm/src/samd5e5/sam_eic.c
+273
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/****************************************************************************
* arch/arm/src/samd5e5/sam_eic.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Matt Thompson <matt@extent3d.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include "up_arch.h"
#include "sam_gclk.h"
#include "sam_periphclks.h"
#include "sam_port.h"
#include "sam_eic.h"
#include <arch/board/board.h>
#ifdef CONFIG_SAMD5E5_EIC
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: sam_eic_syncwait
*
* Description:
* Wait until the ENABLE synchronization is complete
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static void sam_eic_syncwait(void)
{
while ((getreg8(SAM_EIC_SYNCBUSY) & EIC_SYNCBUSY_ENABLE) != 0);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: sam_eic_dumpregs
*
* Description:
* Dump all external interrupt controller (EIC) registers
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void sam_eic_dumpregs(void)
{
irqinfo("EIC:\n");
irqinfo(" CTRLA: %02x\n", getreg8(SAM_EIC_CTRLA));
irqinfo(" NMICTRL: %02x\n", getreg8(SAM_EIC_NVMICTRL));
irqinfo(" NMIFLAG: %04x\n", getreg16(SAM_EIC_NMIFLAG));
irqinfo(" SYNCBUSY: %08x\n", getreg32(SAM_EIC_SYNCBUSY));
irqinfo(" EVCTRL: %08x\n", getreg32(SAM_EIC_EVCTRL));
irqinfo(" INTENCLR: %08x\n", getreg32(SAM_EIC_INTENCLR));
irqinfo(" INTENSET: %08x\n", getreg32(SAM_EIC_INTENSET));
irqinfo(" INTFLAG: %08x\n", getreg32(SAM_EIC_INTFLAG));
irqinfo(" ASYNCH: %08x\n", getreg32(SAM_EIC_ASYNCH));
irqinfo(" CONFIG0: %08x\n", getreg32(SAM_EIC_CONFIG0));
irqinfo(" CONFIG1: %08x\n", getreg32(SAM_EIC_CONFIG1));
irqinfo(" DEBOUNCEN: %08x\n", getreg32(SAM_EIC_DEBOUNCEN));
irqinfo(" DPRESCALER: %08x\n", getreg32(SAM_EIC_DPRESCALER));
irqinfo(" PINSTATE: %08x\n", getreg32(SAM_EIC_PINSTATE));
}
/****************************************************************************
* Name: sam_eic_initialize
*
* Description:
* Initialize the external interrupt controller (EIC).
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
int sam_eic_initialize(void)
{
uint16_t regval;
/* Configure the EIC APB clock */
sam_apb_eic_enableperiph();
regval = GCLK_CLKCTRL_ID_EIC |
GCLK_CLKCTRL_GEN(CONFIG_SAMD5E5_EIC_GCLKGEN) |
GCLK_CLKCTRL_CLKEN;
putreg16(regval, SAM_GCLK_CLKCTRL);
/* Enable the EIC APB clock */
putreg8(EIC_CTRLA_ENABLE, SAM_EIC_CTRLA);
sam_eic_syncwait();
sam_eic_dumpregs();
return OK;
}
/****************************************************************************
* Name: sam_eic_configure
*
* Description:
* Configure the interrupt edge sensitivity in CONFIGn register of the EIC
*
* Input Parameters:
* eirq - Pin to be configured
* pinset - Configuration of the pin
*
* Returned Value:
* None
*
****************************************************************************/
int sam_eic_configure(uint8_t eirq, port_pinset_t pinset)
{
uint32_t reg;
uint32_t val;
uint32_t config;
/* Determine which of the CONFIG[0:1] registers to write to */
if (eirq < 8)
{
reg = SAM_EIC_CONFIG0;
val = EIC_CONFIG0_SENSE_BOTH(eirq);
if (pinset & PORT_INT_RISING)
{
val = EIC_CONFIG0_SENSE_RISE(eirq);
}
if (pinset & PORT_INT_FALLING)
{
val = EIC_CONFIG0_SENSE_FALL(eirq);
}
val |= EIC_CONFIG0_FILTEN(eirq);
}
else /* if (eirq < 16) */
{
reg = SAM_EIC_CONFIG1;
val = EIC_CONFIG1_SENSE_BOTH(eirq);
if (pinset & PORT_INT_RISING)
{
val = EIC_CONFIG1_SENSE_RISE(eirq);
}
if (pinset & PORT_INT_FALLING)
{
val = EIC_CONFIG1_SENSE_FALL(eirq);
}
val |= EIC_CONFIG1_FILTEN(eirq);
}
/* Write the new config to the CONFIGn register */
config = getreg32(reg);
config |= val;
putreg32(config, reg);
/* Enable interrupt generation for this pin */
putreg32(EIC_EXTINT(eirq), SAM_EIC_INTENSET);
sam_eic_dumpregs();
return OK;
}
/****************************************************************************
* Name: sam_eic_irq_enable
*
* Description:
* Enable an external interrupt.
*
* Input Parameters:
* irq - SAM_IRQ_EXTINTn IRQ to be enabled
*
* Returned Value:
* None
*
****************************************************************************/
int sam_eic_irq_enable(int irq)
{
uint32_t config;
int eirq = irq - SAM_IRQ_EXTINT0;
config = getreg32(SAM_EIC_CONFIG0);
config |= EIC_CONFIG0_FILTEN(eirq) | EIC_CONFIG0_SENSE_FALL(eirq);
putreg32(config, SAM_EIC_CONFIG0);
putreg32(EIC_EXTINT(eirq), SAM_EIC_INTENSET);
sam_eic_dumpregs();
return OK;
}
/****************************************************************************
* Name: sam_eic_irq_ack
*
* Description:
* Acknowledge receipt of an external interrupt.
*
* Input Parameters:
* irq - SAM_IRQ_EXTINTn IRQ to be acknowledged
*
* Returned Value:
* None
*
****************************************************************************/
int sam_eic_irq_ack(int irq)
{
int eirq = irq - SAM_IRQ_EXTINT0;
putreg32(EIC_EXTINT(eirq), SAM_EIC_INTENCLR);
}
#endif /* CONFIG_SAMD5E5_EIC */
arch/arm/src/samd5e5/sam_eic.h
+137
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/****************************************************************************
* arch/arm/src/samd5e5/sam_eic.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Matt Thompson <matt@extent3d.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_SAM_EIC_H
#define __ARCH_ARM_SRC_SAMD5E5_SAM_EIC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include "sam_config.h"
#include "sam_port.h"
#include "chip/sam_eic.h"
#ifdef CONFIG_SAMD5E5_EIC
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: sam_eic_initialize
*
* Description:
* Initialize the EIC
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
int sam_eic_initialize(void);
/****************************************************************************
* Name: sam_eic_configure
*
* Description:
* Configure the interrupt edge sensitivity in CONFIGn register of the EIC
*
* Input Parameters:
* eirq - Pin to be configured
* pinset - Configuration of the pin
*
* Returned Value:
* None
*
****************************************************************************/
int sam_eic_configure(uint8_t eirq, port_pinset_t pinset);
/****************************************************************************
* Name: sam_eic_irq_enable
*
* Description:
* Enable a external interrupt.
*
* Input Parameters:
* irq - SAM_IRQ_EXTINTn IRQ to be enabled
*
* Returned Value:
* None
*
****************************************************************************/
int sam_eic_irq_enable(int irq);
/****************************************************************************
* Name: sam_eic_irq_ack
*
* Description:
* Acknowledge receipt of an external interrupt.
*
* Input Parameters:
* irq - SAM_IRQ_EXTINTn IRQ to be acknowledged
*
* Returned Value:
* None
*
****************************************************************************/
int sam_eic_irq_ack(int irq);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* CONFIG_SAMD5E5_EIC */
#endif /* __ARCH_ARM_SRC_SAMD5E5_SAM_EIC_H */
arch/arm/src/samd5e5/sam_gclk.c
+284
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/****************************************************************************
* arch/arm/src/samd5e5/sam_glck.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <nuttx/irq.h>
#include "up_arch.h"
#include "sam_gclk.h"
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: sam_gclck_waitsyncbusy
*
* Description:
* What until the SYNCBUSY bit is cleared. The SYNCBUSY bit was set when
* the synchronization of registers between clock domains is started. The
* SYNCBUSY bit is cleared when the synchronization of registers between
* the clock domains is complete.
*
* Input Parameters:
* glck - GCLK clock index
*
* Returned Value:
* None
*
****************************************************************************/
static void sam_gclck_waitsyncbusy(uint8_t gclk)
{
uintptr_t gclkbit = GCLK_SYNCHBUSY_GENCTRL(gclk);
while ((getreg8(SAM_GCLK_SYNCHBUSY) & gclkbit) != 0);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: sam_gclk_config
*
* Description:
* Configure a single GCLK(s) based on settings in the config structure.
*
* Input Parameters:
* config - An instance of struct sam_gclkconfig describing the GCLK
* configuration.
*
* Returned Value:
* None
*
****************************************************************************/
void sam_gclk_config(FAR const struct sam_gclkconfig_s *config)
{
irqstate_t flags;
uintptr_t regaddr;
uint32_t regval;
uint32_t genctrl;
/* Select the requested source clock for the generator */
genctrl = ((uint32_t)config->clksrc << GCLK_GENCTRL_SRC_SHIFT);
#if 0 /* Not yet supported */
/* Configure the clock to be either high or low when disabled */
if (config->level)
{
genctrl |= GCLK_GENCTRL_OOV;
}
#endif
/* Configure if the clock output to I/O pin should be enabled */
if (config->output)
{
genctrl |= GCLK_GENCTRL_OE;
}
/* Set the prescaler division factor */
if (config->prescaler > 1)
{
/* Check if division is a power of two */
if (((config->prescaler & (config->prescaler - 1)) == 0))
{
/* Determine the index of the highest bit set to get the
* division factor that must be loaded into the division
* register.
*/
uint32_t count = 0;
uint32_t mask;
for (mask = 2; mask < (uint32_t)config->prescaler; mask <<= 1)
{
count++;
}
/* Set binary divider power of 2 division factor */
genctrl |= count << GCLK_GENCTRL_DIV_SHIFT;
genctrl |= GCLK_GENCTRL_DIVSEL;
}
else
{
/* Set integer division factor */
genctrl |= GCLK_GENCTRL_DIV((uint32_t)config->prescaler);
/* Enable non-binary division with increased duty cycle accuracy */
genctrl |= GCLK_GENCTRL_IDC;
}
}
/* Enable or disable the clock in standby mode */
if (config->runstandby)
{
genctrl |= GCLK_GENCTRL_RUNSTDBY;
}
/* Wait for synchronization */
sam_gclck_waitsyncbusy(config->gclk);
/* Preserve the GENEN bit */
regaddr = SAM_GCLK_GENCTRL(config->gclk);
flags = enter_critical_section();
regval = getreg32(regaddr);
regval &= GCLK_GENCTRL_GENEN;
genctrl |= regval;
/* Configure the generator */
putreg32(genctrl, regaddr);
/* Wait for synchronization */
sam_gclck_waitsyncbusy(config->gclk);
leave_critical_section(flags);
sam_gclck_waitsyncbusy(config->gclk);
/* Enable the clock generator */
flags = enter_critical_section();
genctrl |= GCLK_GENCTRL_GENEN;
putreg32(genctrl, regaddr);
/* Wait for synchronization */
sam_gclck_waitsyncbusy(config->gclk);
leave_critical_section(flags);
}
/****************************************************************************
* Name: sam_gclk_chan_enable
*
* Description:
* Configure and enable a GCLK peripheral channel.
*
* Input Parameters:
* channel - Index of the GCLK channel to be enabled
* srcgen - The GCLK source generator index
*
* Returned Value:
* None
*
****************************************************************************/
void sam_gclk_chan_enable(uint8_t channel, uint8_t srcgen)
{
irqstate_t flags;
uint32_t regaddr;
uint32_t regval;
/* Get the address of the peripheral channel control register */
regaddr = SAM_GCLK_PCHCTRL(channel);
/* Disable generic clock channel */
flags = enter_critical_section();
sam_gclk_chan_disable(channel);
/* Configure the peripheral channel */
regval = GCLK_PCHCTRL_GEN(srcgen);
putreg32(regval, regaddr);
/* Enable the peripheral channel */
regval |= GCLK_PCHCTRL_CHEN;
putreg32(regval, regaddr);
/* Wait for clock synchronization */
while ((getreg32(regaddr) &GCLK_PCHCTRL_CHEN) == 0);
leave_critical_section(flags);
}
/****************************************************************************
* Name: sam_gclk_chan_disable
*
* Description:
* Disable a GCLK peripheral channel.
*
* Input Parameters:
* channel - Index of the GCLK channel to be disabled
*
* Returned Value:
* None
*
****************************************************************************/
void sam_gclk_chan_disable(uint8_t channel)
{
irqstate_t flags;
uint32_t regaddr;
uint32_t regval;
/* Get the address of the peripheral channel control register */
regaddr = SAM_GCLK_PCHCTRL(channel);
/* Disable generic clock channel */
flags = enter_critical_section();
regval = getreg32(regaddr);
regval &= ~GCLK_PCHCTRL_CHEN;
putreg32(regval, regaddr);
/* Wait for clock synchronization */
while ((getreg32(regaddr) &GCLK_PCHCTRL_CHEN) != 0);
leave_critical_section(flags);
}
arch/arm/src/samd5e5/sam_gclk.h
+148
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/****************************************************************************
* arch/arm/src/samd5e5/sam_gclk.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_SAM_GCLK_H
#define __ARCH_ARM_SRC_SAMD5E5_SAM_GCLK_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include "sam_config.h"
#include "chip/sam_gclk.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/* This structure describes the configuration of one GCLK */
struct sam_gclkconfig_s
{
uint8_t gclk; /* Clock generator */
bool runstandby; /* Run clock in standby */
bool output; /* Output enable */
uint8_t clksrc; /* Encoded clock source */
uint16_t prescaler; /* Prescaler value */
};
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_gclk_config
*
* Description:
* Configure a single GCLK(s) based on settings in the config structure.
*
* Input Parameters:
* config - An instance of struct sam_gclkconfig describing the GCLK
* configuration.
*
* Returned Value:
* None
*
****************************************************************************/
void sam_gclk_config(FAR const struct sam_gclkconfig_s *config);
/****************************************************************************
* Name: sam_gclk_chan_enable
*
* Description:
* Configure and enable a GCLK peripheral channel.
*
* Input Parameters:
* channel - Index of the GCLK channel to be enabled
* srcgen - The GCLK source generator index
*
* Returned Value:
* None
*
****************************************************************************/
void sam_gclk_chan_enable(uint8_t channel, uint8_t srcgen);
/****************************************************************************
* Name: sam_gclk_chan_disable
*
* Description:
* Disable a GCLK peripheral channel.
*
* Input Parameters:
* channel - Index of the GCLK channel to be disabled
*
* Returned Value:
* None
*
****************************************************************************/
void sam_gclk_chan_disable(uint8_t channel);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMD5E5_SAM_GCLK_H */
arch/arm/src/samd5e5/sam_idle.c
+186
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/****************************************************************************
* arch/arm/src/samd5e5/sam_idle.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <arch/board/board.h>
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/power/pm.h>
#include <nuttx/irq.h>
#include "chip.h"
#include "up_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Does the board support an IDLE LED to indicate that the board is in the
* IDLE state?
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()
#endif
#define PM_IDLE_DOMAIN 0 /* Revisit */
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_idlepm
*
* Description:
* Perform IDLE state power management.
*
****************************************************************************/
#ifdef CONFIG_PM
static void up_idlepm(void)
{
static enum pm_state_e oldstate = PM_NORMAL;
enum pm_state_e newstate;
irqstate_t flags;
int ret;
/* Decide, which power saving level can be obtained */
newstate = pm_checkstate(PM_IDLE_DOMAIN);
/* Check for state changes */
if (newstate != oldstate)
{
flags = enter_critical_section();
/* Perform board-specific, state-dependent logic here */
_info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
ret = pm_changestate(PM_IDLE_DOMAIN, newstate);
if (ret < 0)
{
/* The new state change failed, revert to the preceding state */
(void)pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
/* Save the new state */
oldstate = newstate;
}
/* MCU-specific power management logic */
switch (newstate)
{
case PM_NORMAL:
break;
case PM_IDLE:
break;
case PM_STANDBY:
sam_pmstop(true);
break;
case PM_SLEEP:
(void)sam_pmstandby();
break;
default:
break;
}
leave_critical_section(flags);
}
}
#else
# define up_idlepm()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_idle
*
* Description:
* up_idle() is the logic that will be executed when their is no other
* ready-to-run task. This is processor idle time and will continue until
* some interrupt occurs to cause a context switch from the idle task.
*
* Processing in this state may be processor-specific. e.g., this is where
* power management operations might be performed.
*
****************************************************************************/
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
sched_process_timer();
#else
/* Perform IDLE mode power management */
up_idlepm();
/* Sleep until an interrupt occurs to save power. */
BEGIN_IDLE();
asm("WFI");
END_IDLE();
#endif
}
arch/arm/src/samd5e5/sam_irq.c
+708
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arch/arm/src/samd5e5/sam_lowputc.c
+467
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@@ -0,0 +1,467 @@
/****************************************************************************
* arch/arm/src/samd5e5/sam_lowputc.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <errno.h>
#include <nuttx/irq.h>
#include "up_arch.h"
#include "chip/sam_pm.h"
#include "sam_config.h"
#include "sam_gclk.h"
#include "sam_sercom.h"
#include "sam_usart.h"
#include "sam_lowputc.h"
#include <arch/board/board.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef OK
# define OK 0
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: sam_wait_synchronization
*
* Description:
* Wait until the SERCOM USART reports that it is synchronized.
*
****************************************************************************/
#ifdef SAMD5E5_HAVE_USART
static void
sam_wait_synchronization(const struct sam_usart_config_s * const config)
{
while (usart_syncbusy(config));
}
#endif
/****************************************************************************
* Name: sam_usart_configure
*
* Description:
* Configure the SERCOM USART operating mode (as a normal UART).
*
****************************************************************************/
#ifdef SAMD5E5_HAVE_USART
static inline int
sam_usart_configure(const struct sam_usart_config_s * const config)
{
uint32_t ctrla;
uint32_t ctrlb;
uint16_t baud;
uint64_t tmp;
/* Calculate BAUD divider from the source clock frequency and desired.
* baud. For asynchronous mode, the formula for the baud generation is
*
* Fbaud = (Frefclk / 16) * (1 - (BAUD / 65,536))
*
* Or,
*
* BAUD = 65,536 * (1 - 16 * (Fbaud / Fref))
* = 65,536 - 16 * 65,536 * Fbaud / Fref
*
* Example: Fref = 48MHz and Fbaud = 9600
*
* BAUD = 65,326
* Fbaud = 9600
*
* Example: Fref = 48MHz and Fbaud = 115,200
*
* BAUD = 63,019
* Fbaud = 115,219
*/
tmp = (uint64_t)config->baud << 20;
tmp = (tmp + (config->frequency >> 1)) / config->frequency;
/* Verify that the calculated result is within range */
if (tmp < 1 || tmp > UINT16_MAX)
{
return -ERANGE;
}
baud = 65536 - (uint16_t)tmp;
/* Disable all USART interrupts */
putreg8(USART_INT_ALL, config->base + SAM_USART_INTENCLR_OFFSET);
/* Wait until synchronization is complete */
sam_wait_synchronization(config);
/* Set baud divisor */
putreg16((uint16_t)baud, config->base + SAM_USART_BAUD_OFFSET);
/* Configure the USART CTRLA and CTRLB registers */
ctrla = (USART_CTRLA_MODE_INTUSART | (uint32_t)config->muxconfig |
USART_CTRLA_ASYNCH | USART_CTRLA_CPOL_NORMAL |
USART_CTRLA_LSBFIRST);
ctrlb = (USART_CTRLB_TXEN | USART_CTRLB_RXEN);
/* Set the number of stop bits */
if (config->stopbits2)
{
ctrlb |= USART_CTRLB_SBMODE;
}
/* Set the USART word size */
switch (config->bits)
{
case 5:
ctrlb |= USART_CTRLB_CHSIZE_5BITS;
break;
case 6:
ctrlb |= USART_CTRLB_CHSIZE_6BITS;
break;
case 7:
ctrlb |= USART_CTRLB_CHSIZE_7BITS;
break;
default:
case 8:
break;
case 9:
ctrlb |= USART_CTRLB_CHSIZE_9BITS;
break;
}
/* Set parity mode */
switch (config->parity)
{
default:
case 0: /* None */
break;
case 1: /* Odd */
ctrlb |= USART_CTRLB_PODD;
/* Fall through */
case 2: /* Even */
ctrla |= USART_CTRLA_FORM_PARITY;
break;
}
#if 0 /* Not supported */
/* Set run mode during device sleep */
if (config->runinstandby)
{
/* Enable in sleep mode */
ctrla |= USART_CTRLA_RUNSTDBY;
}
#endif
/* Wait until synchronization is complete */
sam_wait_synchronization(config);
/* Write configuration to CTRLB */
putreg32(ctrlb, config->base + SAM_USART_CTRLB_OFFSET);
/* Wait until synchronization is complete */
sam_wait_synchronization(config);
/* Write configuration to CTRLA */
putreg32(ctrla, config->base + SAM_USART_CTRLA_OFFSET);
return OK;
}
#endif
/****************************************************************************
* Name: sam_pad_configure
*
* Description:
* Configure the SERCOM USART pads.
*
****************************************************************************/
#ifdef SAMD5E5_HAVE_USART
static inline void
sam_pad_configure(const struct sam_usart_config_s * const config)
{
/* Configure SERCOM pads */
if (config->pad0 != 0)
{
sam_configport(config->pad0);
}
if (config->pad1 != 0)
{
sam_configport(config->pad1);
}
if (config->pad2 != 0)
{
sam_configport(config->pad2);
}
if (config->pad3 != 0)
{
sam_configport(config->pad3);
}
}
#endif
/****************************************************************************
* Name: sam_usart_internal
*
* Description:
* Set the configuration of a SERCOM for provided USART configuration.
* This configures the SERCOM as a USART, but does not configure USART
* interrupts or enable the USART.
*
****************************************************************************/
#ifdef SAMD5E5_HAVE_USART
int sam_usart_internal(const struct sam_usart_config_s * const config)
{
int channel;
int ret;
/* Enable clocking to the SERCOM module */
sercom_enable(config->sercom);
/* Configure the GCLKs for the SERCOM module */
sercom_coreclk_configure(config->sercom, config->gclkgen, false);
if (config->sercom == 5)
{
channel = GCLK_CHAN_SERCOM5_CORE;
}
else
{
channel = config->sercom + GCLK_CHAN_SERCOM0_CORE;
}
sam_gclk_chan_enable(channel, config->gclkgen);
sercom_slowclk_configure(config->sercom, config->slowgen);
/* Set USART configuration according to the board configuration */
ret = sam_usart_configure(config);
if (ret == OK)
{
/* Configure USART pins */
sam_pad_configure(config);
}
return ret;
}
#endif
/****************************************************************************
* Name: sam_usart_enable
*
* Description:
* Enable the SERCOM USART (without enabling interrupts).
*
****************************************************************************/
#ifdef SAMD5E5_HAVE_USART
static inline void
sam_usart_enable(const struct sam_usart_config_s * const config)
{
uintptr_t regaddr;
uint32_t regval;
/* Wait until synchronization is complete */
sam_wait_synchronization(config);
/* Enable USART module */
regaddr = config->base + SAM_USART_CTRLA_OFFSET;
regval = getreg32(regaddr);
regval |= USART_CTRLA_ENABLE;
putreg32(regval, regaddr);
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: sam_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level
* initialization.
*
****************************************************************************/
void sam_lowsetup(void)
{
#ifdef HAVE_SERIAL_CONSOLE
/* Configure and enable the console USART */
VERIFY(sam_usart_internal(&g_consoleconfig));
sam_usart_enable(&g_consoleconfig);
#endif
}
/****************************************************************************
* Name: sam_usart_initialize
*
* Description:
* Set the configuration of a SERCOM for provided USART configuration.
* This configures the SERCOM as a USART, but does not configure USART
* interrupts or enable the USART.
*
****************************************************************************/
#ifdef SAMD5E5_HAVE_USART
int sam_usart_initialize(const struct sam_usart_config_s * const config)
{
irqstate_t flags;
int ret;
/* Reset the SERCOM so that we know that it is in its initial state */
flags = enter_critical_section();
sam_usart_reset(config);
/* Just invoke the internal implementation, but with interrupts disabled
* so that the operation is atomic.
*/
ret = sam_usart_internal(config);
leave_critical_section(flags);
return ret;
}
#endif
/****************************************************************************
* Name: sam_usart_reset
*
* Description:
* Reset the USART SERCOM. This restores all SERCOM register to the
* initial state and disables the SERCOM.
*
****************************************************************************/
#ifdef SAMD5E5_HAVE_USART
void sam_usart_reset(const struct sam_usart_config_s * const config)
{
uintptr_t regaddr = config->base + SAM_USART_CTRLA_OFFSET;
uint32_t regval;
/* Reset the SERCOM by setting the SWRST bit in the CTRLA register. When
* the reset completes, the SERCOM will registers will be restored to there
* initial state and the SERCOM will be disabled.
*/
regval = getreg32(regaddr);
regval |= USART_CTRLA_SWRST;
putreg32(regval, regaddr);
/* Wait for the reset to complete */
while ((getreg32(regaddr) & USART_CTRLA_SWRST) != 0);
}
#endif
/****************************************************************************
* Name: sam_lowputc
*
* Description:
* Output one character to the USART using a simple polling method.
*
****************************************************************************/
#ifdef HAVE_SERIAL_CONSOLE
void sam_lowputc(uint32_t ch)
{
uintptr_t base = g_consoleconfig.base;
uintptr_t intflag = base + SAM_USART_INTFLAG_OFFSET;
/* Wait for the USART to be ready for new TX data */
while ((getreg8(intflag) & USART_INT_DRE) == 0);
/* Wait until synchronization is complete */
sam_wait_synchronization(&g_consoleconfig);
/* Write data to USART module */
putreg16((uint16_t)ch, base + SAM_USART_DATA_OFFSET);
/* Wait until data is sent */
while ((getreg8(intflag) & USART_INT_TXC) == 0);
}
#endif
arch/arm/src/samd5e5/sam_lowputc.h
+130
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/****************************************************************************
* arch/arm/src/samd5e5/sam_lowputc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_SAM_LOWPUTC_H
#define __ARCH_ARM_SRC_SAMD5E5_SAM_LOWPUTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "sam_config.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level
* initialization.
*
****************************************************************************/
void sam_lowsetup(void);
/****************************************************************************
* Name: sam_usart_initialize
*
* Description:
* Set the configuration of a SERCOM for provided USART configuration.
* This configures the SERCOM as a USART, but does not configure USART
* interrupts or enable the USART.
*
****************************************************************************/
#ifdef SAMD5E5_HAVE_USART
struct sam_usart_config_s;
int sam_usart_initialize(const struct sam_usart_config_s * const config);
#endif
/****************************************************************************
* Name: sam_usart_reset
*
* Description:
* Reset the USART SERCOM. This restores all SERCOM register to the
* initial state and disables the SERCOM.
*
****************************************************************************/
#ifdef SAMD5E5_HAVE_USART
struct sam_usart_config_s;
void sam_usart_reset(const struct sam_usart_config_s * const config);
#endif
/****************************************************************************
* Name: sam_lowputc
*
* Description:
* Output one character to the USART using a simple polling method.
*
****************************************************************************/
#ifdef HAVE_SERIAL_CONSOLE
void sam_lowputc(uint32_t ch);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMD5E5_SAM_LOWPUTC_H */
arch/arm/src/samd5e5/sam_mpuinit.c
+124
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@@ -0,0 +1,124 @@
/****************************************************************************
* arch/arm/src/samd5e5/sam_mpuinit.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <assert.h>
#include <nuttx/userspace.h>
#include "mpu.h"
#include "sam_mpuinit.h"
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ARM_MPU)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef MAX
# define MAX(a,b) a > b ? a : b
#endif
#ifndef MIN
# define MIN(a,b) a < b ? a : b
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: sam_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only restricted SAM3/4
* resources.
*
****************************************************************************/
void sam_mpuinitialize(void)
{
uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart);
uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend);
DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart &&
dataend >= datastart);
/* Show MPU information */
mpu_showtype();
/* Configure user flash and SRAM space */
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_user_intsram(datastart, dataend - datastart);
/* Then enable the MPU */
mpu_control(true, false, true);
}
/****************************************************************************
* Name: sam_mpu_uheap
*
* Description:
* Map the user-heap region.
*
* This logic may need an extension to handle external SDRAM).
*
****************************************************************************/
void sam_mpu_uheap(uintptr_t start, size_t size)
{
mpu_user_intsram(start, size);
}
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARM_MPU */
arch/arm/src/samd5e5/sam_mpuinit.h
+114
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@@ -0,0 +1,114 @@
/************************************************************************************
* arch/arm/src/samd5e5/sam_mpuinit.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_SAM_MPUINIT_H
#define __ARCH_ARM_SRC_SAMD5E5_SAM_MPUINIT_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Data
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/****************************************************************************
* Name: sam_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only unrestricted SAM3/4
* resources.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void sam_mpuinitialize(void);
#else
# define sam_mpuinitialize()
#endif
/****************************************************************************
* Name: sam_mpu_uheap
*
* Description:
* Map the user heap region.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void sam_mpu_uheap(uintptr_t start, size_t size);
#else
# define sam_mpu_uheap(start,size)
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMD5E5_SAM_MPUINIT_H */
arch/arm/src/samd5e5/sam_periphclks.h
+347
View File
@@ -0,0 +1,347 @@
/****************************************************************************
* arch/arm/src/samd5e5/sam_periphclks.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_SAM_PERIPHCLKS_H
#define __ARCH_ARM_SRC_SAMD5E5_SAM_PERIPHCLKS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_mclk.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define sam_ahb_enableperiph(s) modifyreg32(SAM_MCLK_AHBMASK,0,s)
#define sam_ahb_hpb0_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_HPB0)
#define sam_ahb_hpb1_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_HPB1)
#define sam_ahb_hpb2_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_HPB2)
#define sam_ahb_hpb3_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_HPB3)
#define sam_ahb_dsu_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_DSU)
#define sam_ahb_nvmctrl_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_NVMCTRL)
#define sam_ahb_cmcc_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_CMCC)
#define sam_ahb_dmac_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_DMAC)
#define sam_ahb_usb_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_USB)
#define sam_ahb_pac_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_PAC)
#define sam_ahb_qspi_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_QSPI)
#define sam_ahb_gmac_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_GMAC)
#define sam_ahb_sdhc0_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_SDHC0)
#define sam_ahb_sdhc1_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_SDHC1)
#define sam_ahb_can0_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_CAN0)
#define sam_ahb_can1_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_CAN1)
#define sam_ahb_icm_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_ICM)
#define sam_ahb_pukcc_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_PUKCC)
#define sam_ahb_qspi2x_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_QSPI2X)
#define sam_ahb_nvmctrl_smeeprom_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_NVMCTRL_SMEEPROM)
#define sam_ahb_nvmctrl_cache_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_NVMCTRL_CACHE)
#define sam_apba_enableperiph(s) modifyreg32(SAM_MCLK_APBAMASK,0,s)
#define sam_apb_pac_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_PAC)
#define sam_apb_pm_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_PM)
#define sam_apb_mclk_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_MCLK)
#define sam_apb_rstc_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_RSTC)
#define sam_apb_oscctrl_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_OSCCTRL)
#define sam_apb_osc32kctrl_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_OSC32KCTRL)
#define sam_apb_supc_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_SUPC)
#define sam_apb_gclk_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_GCLK)
#define sam_apb_wdt_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_WDT)
#define sam_apb_rtc_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_RTC)
#define sam_apb_eic_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_EIC)
#define sam_apb_freqm_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_FREQM)
#define sam_apb_sercom0_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_SERCOM0)
#define sam_apb_sercom1_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_SERCOM1)
#define sam_apb_tc0_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_TC0)
#define sam_apb_tc1_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_TC1)
#define sam_apbb_enableperiph(s) modifyreg32(SAM_MCLK_APBBMASK,0,s)
#define sam_apb_usb_enableperiph() sam_apbb_enableperiph(MCLK_APBBMASK_USB)
#define sam_apb_dsu_enableperiph() sam_apbb_enableperiph(MCLK_APBBMASK_DSU)
#define sam_apb_nvmctrl_enableperiph() sam_apbb_enableperiph(MCLK_APBBMASK_NVMCTRL)
#define sam_apb_port_enableperiph() sam_apbb_enableperiph(MCLK_APBBMASK_PORT)
#define sam_apb_evsys_enableperiph() sam_apbb_enableperiph(MCLK_APBBMASK_EVSYS)
#define sam_apb_sercom2_enableperiph() sam_apbb_enableperiph(MCLK_APBBMASK_SERCOM2)
#define sam_apb_sercom3_enableperiph() sam_apbb_enableperiph(MCLK_APBBMASK_SERCOM3)
#define sam_apb_tcc0_enableperiph() sam_apbb_enableperiph(MCLK_APBBMASK_TCC0)
#define sam_apb_tcc1_enableperiph() sam_apbb_enableperiph(MCLK_APBBMASK_TCC1)
#define sam_apb_tc2_enableperiph() sam_apbb_enableperiph(MCLK_APBBMASK_TC2)
#define sam_apb_tc3_enableperiph() sam_apbb_enableperiph(MCLK_APBBMASK_TC3)
#define sam_apb_ramecc_enableperiph() sam_apbb_enableperiph(MCLK_APBBMASK_RAMECC)
#define sam_apbc_enableperiph(s) modifyreg32(SAM_MCLK_APBCMASK,0,s)
#define sam_apb_gmac_enableperiph(n) sam_apbc_enableperiph(MCLK_APBCMASK_GMAC)
#define sam_apb_tcc2_enableperiph(n) sam_apbc_enableperiph(MCLK_APBCMASK_TCC2)
#define sam_apb_tcc3_enableperiph(n) sam_apbc_enableperiph(MCLK_APBCMASK_TCC3)
#define sam_apb_tc4_enableperiph(n) sam_apbc_enableperiph(MCLK_APBCMASK_TC4)
#define sam_apb_tc5_enableperiph(n) sam_apbc_enableperiph(MCLK_APBCMASK_TC5)
#define sam_apb_pdec_enableperiph(n) sam_apbc_enableperiph(MCLK_APBCMASK_PDEC)
#define sam_apb_ac_enableperiph(n) sam_apbc_enableperiph(MCLK_APBCMASK_AC)
#define sam_apb_aes_enableperiph(n) sam_apbc_enableperiph(MCLK_APBCMASK_AES)
#define sam_apb_trng_enableperiph(n) sam_apbc_enableperiph(MCLK_APBCMASK_TRNG)
#define sam_apb_icm_enableperiph(n) sam_apbc_enableperiph(MCLK_APBCMASK_ICM)
#define sam_apb_qspi_enableperiph(n) sam_apbc_enableperiph(MCLK_APBCMASK_QSPI)
#define sam_apb_ccl_enableperiph(n) sam_apbc_enableperiph(MCLK_APBCMASK_CCL)
#define sam_apbd_enableperiph(s) modifyreg32(SAM_MCLK_APBDMASK,0,s)
#define sam_apb_sercom4_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_SERCOM4)
#define sam_apb_sercom5_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_SERCOM5)
#define sam_apb_sercom6_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_SERCOM6)
#define sam_apb_sercom7_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_SERCOM7)
#define sam_apb_tcc4_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_TCC4)
#define sam_apb_tc6_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_TC6)
#define sam_apb_tc7_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_TC7)
#define sam_apb_adc0_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_ADC0)
#define sam_apb_adc1_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_ADC1)
#define sam_apb_dac_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_DAC)
#define sam_apb_i2c_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_I2C)
#define sam_apb_pcc_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_PCC)
#define sam_ahb_disableperiph(s) modifyreg32(SAM_MCLK_AHBMASK,s,0)
#define sam_ahb_hpb0_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_HPB0)
#define sam_ahb_hpb1_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_HPB1)
#define sam_ahb_hpb2_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_HPB2)
#define sam_ahb_hpb3_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_HPB3)
#define sam_ahb_dsu_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_DSU)
#define sam_ahb_nvmctrl_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_NVMCTRL)
#define sam_ahb_cmcc_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_CMCC)
#define sam_ahb_dmac_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_DMAC)
#define sam_ahb_usb_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_USB)
#define sam_ahb_pac_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_PAC)
#define sam_ahb_qspi_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_QSPI)
#define sam_ahb_gmac_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_GMAC)
#define sam_ahb_sdhc0_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_SDHC0)
#define sam_ahb_sdhc1_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_SDHC1)
#define sam_ahb_can0_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_CAN0)
#define sam_ahb_can1_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_CAN1)
#define sam_ahb_icm_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_ICM)
#define sam_ahb_pukcc_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_PUKCC)
#define sam_ahb_qspi2x_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_QSPI2X)
#define sam_ahb_nvmctrl_smeeprom_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_NVMCTRL_SMEEPROM)
#define sam_ahb_nvmctrl_cache_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_NVMCTRL_CACHE)
#define sam_apba_disableperiph(s) modifyreg32(SAM_MCLK_APBAMASK,s,0)
#define sam_apb_pac_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_PAC)
#define sam_apb_pm_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_PM)
#define sam_apb_mclk_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_MCLK)
#define sam_apb_rstc_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_RSTC)
#define sam_apb_oscctrl_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_OSCCTRL)
#define sam_apb_osc32kctrl_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_OSC32KCTRL)
#define sam_apb_supc_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_SUPC)
#define sam_apb_gclk_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_GCLK)
#define sam_apb_wdt_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_WDT)
#define sam_apb_rtc_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_RTC)
#define sam_apb_eic_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_EIC)
#define sam_apb_freqm_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_FREQM)
#define sam_apb_sercom0_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_SERCOM0)
#define sam_apb_sercom1_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_SERCOM1)
#define sam_apb_tc0_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_TC0)
#define sam_apb_tc1_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_TC1)
#define sam_apbb_disableperiph(s) modifyreg32(SAM_MCLK_APBBMASK,s,0)
#define sam_apb_usb_disableperiph() sam_apbb_disableperiph(MCLK_APBBMASK_USB)
#define sam_apb_dsu_disableperiph() sam_apbb_disableperiph(MCLK_APBBMASK_DSU)
#define sam_apb_nvmctrl_disableperiph() sam_apbb_disableperiph(MCLK_APBBMASK_NVMCTRL)
#define sam_apb_port_disableperiph() sam_apbb_disableperiph(MCLK_APBBMASK_PORT)
#define sam_apb_evsys_disableperiph() sam_apbb_disableperiph(MCLK_APBBMASK_EVSYS)
#define sam_apb_sercom2_disableperiph() sam_apbb_disableperiph(MCLK_APBBMASK_SERCOM2)
#define sam_apb_sercom3_disableperiph() sam_apbb_disableperiph(MCLK_APBBMASK_SERCOM3)
#define sam_apb_tcc0_disableperiph() sam_apbb_disableperiph(MCLK_APBBMASK_TCC0)
#define sam_apb_tcc1_disableperiph() sam_apbb_disableperiph(MCLK_APBBMASK_TCC1)
#define sam_apb_tc2_disableperiph() sam_apbb_disableperiph(MCLK_APBBMASK_TC2)
#define sam_apb_tc3_disableperiph() sam_apbb_disableperiph(MCLK_APBBMASK_TC3)
#define sam_apb_ramecc_disableperiph() sam_apbb_disableperiph(MCLK_APBBMASK_RAMECC)
#define sam_apbc_disableperiph(s) modifyreg32(SAM_MCLK_APBCMASK,s,0)
#define sam_apb_gmac_disableperiph(n) sam_apbc_disableperiph(MCLK_APBCMASK_GMAC)
#define sam_apb_tcc2_disableperiph(n) sam_apbc_disableperiph(MCLK_APBCMASK_TCC2)
#define sam_apb_tcc3_disableperiph(n) sam_apbc_disableperiph(MCLK_APBCMASK_TCC3)
#define sam_apb_tc4_disableperiph(n) sam_apbc_disableperiph(MCLK_APBCMASK_TC4)
#define sam_apb_tc5_disableperiph(n) sam_apbc_disableperiph(MCLK_APBCMASK_TC5)
#define sam_apb_pdec_disableperiph(n) sam_apbc_disableperiph(MCLK_APBCMASK_PDEC)
#define sam_apb_ac_disableperiph(n) sam_apbc_disableperiph(MCLK_APBCMASK_AC)
#define sam_apb_aes_disableperiph(n) sam_apbc_disableperiph(MCLK_APBCMASK_AES)
#define sam_apb_trng_disableperiph(n) sam_apbc_disableperiph(MCLK_APBCMASK_TRNG)
#define sam_apb_icm_disableperiph(n) sam_apbc_disableperiph(MCLK_APBCMASK_ICM)
#define sam_apb_qspi_disableperiph(n) sam_apbc_disableperiph(MCLK_APBCMASK_QSPI)
#define sam_apb_ccl_disableperiph(n) sam_apbc_disableperiph(MCLK_APBCMASK_CCL)
#define sam_apbd_disableperiph(s) modifyreg32(SAM_MCLK_APBDMASK,s,0)
#define sam_apb_sercom4_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_SERCOM4)
#define sam_apb_sercom5_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_SERCOM5)
#define sam_apb_sercom6_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_SERCOM6)
#define sam_apb_sercom7_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_SERCOM7)
#define sam_apb_tcc4_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_TCC4)
#define sam_apb_tc6_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_TC6)
#define sam_apb_tc7_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_TC7)
#define sam_apb_adc0_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_ADC0)
#define sam_apb_adc1_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_ADC1)
#define sam_apb_dac_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_DAC)
#define sam_apb_i2c_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_I2C)
#define sam_apb_pcc_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_PCC)
#define sam_ahb_isenabled(s) (getreg32(SAM_MCLK_AHBMASK) & (s)) != 0)
#define sam_ahb_hpb0_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_HPB0)
#define sam_ahb_hpb1_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_HPB1)
#define sam_ahb_hpb2_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_HPB2)
#define sam_ahb_hpb3_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_HPB3)
#define sam_ahb_dsu_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_DSU)
#define sam_ahb_nvmctrl_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_NVMCTRL)
#define sam_ahb_cmcc_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_CMCC)
#define sam_ahb_dmac_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_DMAC)
#define sam_ahb_usb_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_USB)
#define sam_ahb_pac_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_PAC)
#define sam_ahb_qspi_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_QSPI)
#define sam_ahb_gmac_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_GMAC)
#define sam_ahb_sdhc0_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_SDHC0)
#define sam_ahb_sdhc1_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_SDHC1)
#define sam_ahb_can0_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_CAN0)
#define sam_ahb_can1_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_CAN1)
#define sam_ahb_icm_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_ICM)
#define sam_ahb_pukcc_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_PUKCC)
#define sam_ahb_qspi2x_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_QSPI2X)
#define sam_ahb_nvmctrl_smeeprom_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_NVMCTRL_SMEEPROM)
#define sam_ahb_nvmctrl_cache_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_NVMCTRL_CACHE)
#define sam_apba_isenabled(s) (getreg32(SAM_MCLK_APBAMASK) & (s)) != 0)
#define sam_apb_pac_isenabled() sam_apba_isenabled(MCLK_APBAMASK_PAC)
#define sam_apb_pm_isenabled() sam_apba_isenabled(MCLK_APBAMASK_PM)
#define sam_apb_mclk_isenabled() sam_apba_isenabled(MCLK_APBAMASK_MCLK)
#define sam_apb_rstc_isenabled() sam_apba_isenabled(MCLK_APBAMASK_RSTC)
#define sam_apb_oscctrl_isenabled() sam_apba_isenabled(MCLK_APBAMASK_OSCCTRL)
#define sam_apb_osc32kctrl_isenabled() sam_apba_isenabled(MCLK_APBAMASK_OSC32KCTRL)
#define sam_apb_supc_isenabled() sam_apba_isenabled(MCLK_APBAMASK_SUPC)
#define sam_apb_gclk_isenabled() sam_apba_isenabled(MCLK_APBAMASK_GCLK)
#define sam_apb_wdt_isenabled() sam_apba_isenabled(MCLK_APBAMASK_WDT)
#define sam_apb_rtc_isenabled() sam_apba_isenabled(MCLK_APBAMASK_RTC)
#define sam_apb_eic_isenabled() sam_apba_isenabled(MCLK_APBAMASK_EIC)
#define sam_apb_freqm_isenabled() sam_apba_isenabled(MCLK_APBAMASK_FREQM)
#define sam_apb_sercom0_isenabled() sam_apba_isenabled(MCLK_APBAMASK_SERCOM0)
#define sam_apb_sercom1_isenabled() sam_apba_isenabled(MCLK_APBAMASK_SERCOM1)
#define sam_apb_tc0_isenabled() sam_apba_isenabled(MCLK_APBAMASK_TC0)
#define sam_apb_tc1_isenabled() sam_apba_isenabled(MCLK_APBAMASK_TC1)
#define sam_apbb_isenabled(s) (getreg32(SAM_MCLK_APBBMASK) & (s)) != 0)
#define sam_apb_usb_isenabled() sam_apbb_isenabled(MCLK_APBBMASK_USB)
#define sam_apb_dsu_isenabled() sam_apbb_isenabled(MCLK_APBBMASK_DSU)
#define sam_apb_nvmctrl_isenabled() sam_apbb_isenabled(MCLK_APBBMASK_NVMCTRL)
#define sam_apb_port_isenabled() sam_apbb_isenabled(MCLK_APBBMASK_PORT)
#define sam_apb_evsys_isenabled() sam_apbb_isenabled(MCLK_APBBMASK_EVSYS)
#define sam_apb_sercom2_isenabled() sam_apbb_isenabled(MCLK_APBBMASK_SERCOM2)
#define sam_apb_sercom3_isenabled() sam_apbb_isenabled(MCLK_APBBMASK_SERCOM3)
#define sam_apb_tcc0_isenabled() sam_apbb_isenabled(MCLK_APBBMASK_TCC0)
#define sam_apb_tcc1_isenabled() sam_apbb_isenabled(MCLK_APBBMASK_TCC1)
#define sam_apb_tc2_isenabled() sam_apbb_isenabled(MCLK_APBBMASK_TC2)
#define sam_apb_tc3_isenabled() sam_apbb_isenabled(MCLK_APBBMASK_TC3)
#define sam_apb_ramecc_isenabled() sam_apbb_isenabled(MCLK_APBBMASK_RAMECC)
#define sam_apbc_isenabled(s) (getreg32(SAM_MCLK_APBCMASK) & (s)) != 0)
#define sam_apb_gmac_isenabled(n) sam_apbc_isenabled(MCLK_APBCMASK_GMAC)
#define sam_apb_tcc2_isenabled(n) sam_apbc_isenabled(MCLK_APBCMASK_TCC2)
#define sam_apb_tcc3_isenabled(n) sam_apbc_isenabled(MCLK_APBCMASK_TCC3)
#define sam_apb_tc4_isenabled(n) sam_apbc_isenabled(MCLK_APBCMASK_TC4)
#define sam_apb_tc5_isenabled(n) sam_apbc_isenabled(MCLK_APBCMASK_TC5)
#define sam_apb_pdec_isenabled(n) sam_apbc_isenabled(MCLK_APBCMASK_PDEC)
#define sam_apb_ac_isenabled(n) sam_apbc_isenabled(MCLK_APBCMASK_AC)
#define sam_apb_aes_isenabled(n) sam_apbc_isenabled(MCLK_APBCMASK_AES)
#define sam_apb_trng_isenabled(n) sam_apbc_isenabled(MCLK_APBCMASK_TRNG)
#define sam_apb_icm_isenabled(n) sam_apbc_isenabled(MCLK_APBCMASK_ICM)
#define sam_apb_qspi_isenabled(n) sam_apbc_isenabled(MCLK_APBCMASK_QSPI)
#define sam_apb_ccl_isenabled(n) sam_apbc_isenabled(MCLK_APBCMASK_CCL)
#define sam_apbd_isenabled(s) (getreg32(SAM_MCLK_APBDMASK) & (s)) != 0)
#define sam_apb_sercom4_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_SERCOM4)
#define sam_apb_sercom5_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_SERCOM5)
#define sam_apb_sercom6_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_SERCOM6)
#define sam_apb_sercom7_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_SERCOM7)
#define sam_apb_tcc4_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_TCC4)
#define sam_apb_tc6_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_TC6)
#define sam_apb_tc7_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_TC7)
#define sam_apb_adc0_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_ADC0)
#define sam_apb_adc1_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_ADC1)
#define sam_apb_dac_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_DAC)
#define sam_apb_i2c_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_I2C)
#define sam_apb_pcc_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_PCC)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMD5E5_SAM_PERIPHCLKS_H */
arch/arm/src/samd5e5/sam_port.c
+578
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