mirror of
https://github.com/apache/nuttx.git
synced 2026-06-04 06:42:32 +08:00
Gregory Nutt
a9d713bbcc
Squashed commit of the following:
arch/arm/src/samd5e5: Clean-up EIC logic.
arch/arm/src/samd5e5: Fix some compilation issues; Still issues with the EIC logic from samd2x.
arch/arm/src/samd5e5: Fix some compilation issues; bring in some EIC logic from samd2x.
arch/arm/src/samd5e5: Add NVMCTRL header file, fix some compiler problems, misc. clean-up.
configs/metro-m4: Add LED support.
arch/arm/src/samd5e5: Bring in SAML21 clock configuration. This is a WIP; it cannot possible even compile yet.
arch/arm/src/samd5e5: Leverage Cortex-M4 interrupt and SysTick logic from the SAM3/4.
arch/arm/src/samd5e5: Add SERCOM utility function.
arch/arm/src/samd5e5: Bring all SERCOM USART logic from SAMD2L2 to SAMD5E5. This is a brute coy with nothing more than more that name changes and extension from 5 to 7 SERCOMs.
arch/arm/src/samd5e5: Add sam_config.h header file
arch/arm/src/samd5e5/: Add Generic Clock (GCLK) utility functions.
arch/arm/src/samd5e5: Add EVSYS register definition file
arch/arm/src/samd5e5 and configs/metro-m4: Use SERCOM3 for the Arduino serial shield as console.
arch/arm/src/samd5e5/chip: Add SERCOM USART, SPI, I2C master, and slave register defintions header files
arch/arm/src/samd5e5/chip: Add AES, PM, TRNG, and WDT header files.
arch/arm/src/samd5e5/chip: Add pin multiplexing header files.
Various fixes to configuration system; fix metro-m4/nsh defconfig file.
configs/metro-m4: Add initial support for the Adafruit Metro M4 board.
arch/arm/src/samd5e5: Add peripheral clock helpers.
arch/arm/src/samd5e5/chip: Add PAC register definition header file. Fix some errors in the memory map header file.
arch/arm/src/samd5e5: Add chip.h headerf file.
arch/arm/src/samd5e5: Add PORT register definitions and support from SAML21.
arch/arm/include/samd5e5: Add interrupt vector definitions.
arch/arm/src/samd5e5: Add some boilerplate files. Correct some typos.
arch/arm/src/samd5e5/chip/sam_eic.h: Add EIC register definitions.
arch/arm/src/samd5e5/chip: Add OSC32KCTRL and OSCCTRL register definitions.
arch/arm/src/samd5e5/chip: Add GCLK, MCLK, and RSTC header files.
arch/arm/src/samd5e5/chip/sam_cmcc.h: Add CMCC register definitions
arch/arm/src/samd5e5/chip/sam_supc.h: Add SUPC header file.
arch/arm/src/samd5e5: Add start-up logic.
arch/arm/src/samd5e5: Add Make.defs file
arch/arm/src/samd5e5/chip: Add memory map header file.
arch/arm/include/samd5e5: Add chip.h header file.
arch/arm/Kconfig and arch/arm/src/samd5e5/Kconfig: Add configuration logic for the SAMD5x/Ex family.
159 lines
4.6 KiB
Plaintext
159 lines
4.6 KiB
Plaintext
############################################################################
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# arch/arm/src/samd5e5/Make.defs
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#
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# Copyright (C) 2018 Gregory Nutt. All rights reserved.
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# Author: Gregory Nutt <gnutt@nuttx.org>
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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#
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# 1. Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in
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# the documentation and/or other materials provided with the
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# distribution.
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# 3. Neither the name NuttX nor the names of its contributors may be
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# used to endorse or promote products derived from this software
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# without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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#
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############################################################################
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# The start-up, "head", file
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HEAD_ASRC =
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# Common ARM and Cortex-M4 files
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CMN_UASRCS =
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CMN_UCSRCS =
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CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
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CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S
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CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copyfullstate.c
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CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c
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CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c
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CMN_CSRCS += up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
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CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c
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CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_stackframe.c
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CMN_CSRCS += up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c
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CMN_CSRCS += up_svcall.c up_vfork.c
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# Configuration-dependent common files
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ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
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CMN_ASRCS += up_lazyexception.S
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else
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CMN_ASRCS += up_exception.S
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endif
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CMN_CSRCS += up_vectors.c
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ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
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CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
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endif
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ifeq ($(CONFIG_BUILD_PROTECTED),y)
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CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
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ifneq ($(CONFIG_DISABLE_SIGNALS),y)
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CMN_CSRCS += up_signal_dispatch.c
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CMN_UASRCS += up_signal_handler.S
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endif
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endif
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ifeq ($(CONFIG_ARCH_FPU),y)
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CMN_ASRCS += up_fpu.S
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CMN_CSRCS += up_copyarmstate.c
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endif
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ifeq ($(CONFIG_STACK_COLORATION),y)
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CMN_CSRCS += up_checkstack.c
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endif
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# Required SAMD5x/E5x files
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CHIP_ASRCS =
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# REVISIT: sam_clockconfig.c and sam_eic.c
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#CHIP_CSRCS = sam_clockconfig.c sam_cmcc.c sam_gclk.c sam_irq.c
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CHIP_CSRCS = sam_cmcc.c sam_gclk.c sam_irq.c
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CHIP_CSRCS += sam_lowputc.c sam_port.c sam_serial.c sam_start.c
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CHIP_CSRCS += sam_supc.c sam_usart.c
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# Configuration-dependent SAMD5x/E5x files
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ifneq ($(CONFIG_SCHED_TICKLESS),y)
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CHIP_CSRCS += sam_timerisr.c
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endif
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ifeq ($(CONFIG_SAMD5E5_TC),y)
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CHIP_CSRCS += sam_tc.c
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ifeq ($(CONFIG_SAMD5E5_ONESHOT),y)
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CHIP_CSRCS += sam_oneshot.c sam_oneshot_lowerhalf.c
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endif # CONFIG_SAMD5E5_ONESHOT
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ifeq ($(CONFIG_SAMD5E5_FREERUN),y)
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CHIP_CSRCS += sam_freerun.c
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endif # CONFIG_SAMD5E5_FREERUN
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ifeq ($(CONFIG_SCHED_TICKLESS),y)
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CHIP_CSRCS += sam_tickless.c
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endif # CONFIG_SCHED_TICKLESS
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endif # CONFIG_SAMD5E5_TC
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ifeq ($(CONFIG_BUILD_PROTECTED),y)
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CHIP_CSRCS += sam_userspace.c sam_mpuinit.c
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endif
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ifeq ($(CONFIG_SAMD5E5_EIC),y)
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CHIP_CSRCS += sam_eic.c
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endif
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ifeq ($(CONFIG_SAMD5E5_CMCC),y)
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CHIP_CSRCS += sam_cmcc.c
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endif
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ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
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CHIP_CSRCS += sam_idle.c
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endif
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ifeq ($(CONFIG_SAMD5E5_WDT),y)
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CHIP_CSRCS += sam_wdt.c
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endif
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ifeq ($(CONFIG_SAMD5E5_GMAC),y)
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CHIP_CSRCS += sam_gmac.c
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endif
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ifeq ($(CONFIG_SAMD5E5_USB),y)
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CHIP_CSRCS += sam_usb.c
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endif
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ifeq ($(CONFIG_SAMD5E5_SDHC0),y)
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CHIP_CSRCS += sam_sdhc.c
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else ifeq ($(CONFIG_SAMD5E5_SDHC1),y)
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CHIP_CSRCS += sam_sdhc.c
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endif
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ifeq ($(CONFIG_SAMD5E5_AES),y)
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CHIP_CSRCS += sam_aes.c
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endif
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ifeq ($(CONFIG_SAMD5E5_RTC),y)
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CHIP_CSRCS += sam_rtc.c
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endif
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