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xtensa/esp32s3: Stall Systimer when core 1 is temporarily stalled

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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
This commit is contained in:
Gustavo Henrique Nihei
2022-03-11 09:30:52 -03:00
committed by Xiang Xiao
parent 023b1a5260
commit a4db4031c9
2 changed files with 6 additions and 0 deletions
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arch/xtensa/src/esp32s3/esp32s3_tickless.c
+3
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@@ -479,6 +479,9 @@ void up_timer_initialize(void)
/* Stall systimer 0 when CPU stalls, e.g., when using JTAG to debug */
modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN);
#ifdef CONFIG_SMP
modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN);
#endif
}
#endif /* CONFIG_SCHED_TICKLESS */
arch/xtensa/src/esp32s3/esp32s3_timerisr.c
+3
View File
@@ -130,6 +130,9 @@ void up_timer_initialize(void)
/* Stall systimer 0 when CPU stalls, e.g., when using JTAG to debug */
modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN);
#ifdef CONFIG_SMP
modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN);
#endif
/* Enable interrupt */