diff --git a/arch/xtensa/src/esp32s3/esp32s3_tickless.c b/arch/xtensa/src/esp32s3/esp32s3_tickless.c
index 7e188b350ca..e379c48e4e5 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_tickless.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_tickless.c
@@ -479,6 +479,9 @@ void up_timer_initialize(void)
   /* Stall systimer 0 when CPU stalls, e.g., when using JTAG to debug */
 
   modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN);
+#ifdef CONFIG_SMP
+  modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN);
+#endif
 }
 
 #endif /* CONFIG_SCHED_TICKLESS */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_timerisr.c b/arch/xtensa/src/esp32s3/esp32s3_timerisr.c
index 30896f07a24..e2d4b232d8a 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_timerisr.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_timerisr.c
@@ -130,6 +130,9 @@ void up_timer_initialize(void)
   /* Stall systimer 0 when CPU stalls, e.g., when using JTAG to debug */
 
   modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN);
+#ifdef CONFIG_SMP
+  modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN);
+#endif
 
   /* Enable interrupt */