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STM32, STM32L4, STM32F7 ADC: fix channel 18 sample time

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This commit is contained in:
Juha Niskanen
2017-08-28 06:54:39 -06:00
committed by Gregory Nutt
parent fa5a2035ff
commit a2dc88e075
6 changed files with 9 additions and 9 deletions
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arch/arm/src/stm32/chip/stm32_adc.h
+1 -1
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@@ -479,7 +479,7 @@
# define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */
# define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
# define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP18_SHIFT)
# endif
#else
# define ADC_SMPR1_SMP20_SHIFT (0) /* Bits 0-2: Channel 20 Sample time selection */
arch/arm/src/stm32/chip/stm32f30xxx_adc.h
+2 -2
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@@ -352,8 +352,8 @@
#define ADC_SMPR2_SMP16_MASK (7 << ADC_SMPR2_SMP16_SHIFT)
#define ADC_SMPR2_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
#define ADC_SMPR2_SMP17_MASK (7 << ADC_SMPR2_SMP17_SHIFT)
#define ADC_SMPR2_SMP18_SHIFT (21) /* Bits 24-26: Channel 18 Sample time selection */
#define ADC_SMPR2_SMP18_MASK (7 << ADC_SMPR2_SMP17_SHIFT)
#define ADC_SMPR2_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */
#define ADC_SMPR2_SMP18_MASK (7 << ADC_SMPR2_SMP18_SHIFT)
/* ADC watchdog threshold register 1 */
arch/arm/src/stm32/chip/stm32f33xxx_adc.h
+2 -2
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@@ -286,8 +286,8 @@
#define ADC_SMPR2_SMP16_MASK (7 << ADC_SMPR2_SMP16_SHIFT)
#define ADC_SMPR2_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
#define ADC_SMPR2_SMP17_MASK (7 << ADC_SMPR2_SMP17_SHIFT)
#define ADC_SMPR2_SMP18_SHIFT (21) /* Bits 24-26: Channel 18 Sample time selection */
#define ADC_SMPR2_SMP18_MASK (7 << ADC_SMPR2_SMP17_SHIFT)
#define ADC_SMPR2_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */
#define ADC_SMPR2_SMP18_MASK (7 << ADC_SMPR2_SMP18_SHIFT)
/* ADC watchdog threshold register 1 */
arch/arm/src/stm32/chip/stm32f37xxx_adc.h
+2 -2
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@@ -183,8 +183,8 @@
#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT)
#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
#define ADC_SMPR1_SMP18_SHIFT (21) /* Bits 24-26: Channel 18 Sample time selection */
#define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
#define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */
#define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP18_SHIFT)
/* ADC sample time register 2 */
arch/arm/src/stm32f7/chip/stm32f74xx77xx_adc.h
+1 -1
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@@ -276,7 +276,7 @@
#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
#define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */
#define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
#define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP18_SHIFT)
/* ADC sample time register 2 */
arch/arm/src/stm32l4/chip/stm32l4_adc.h
+1 -1
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@@ -350,7 +350,7 @@
#define ADC_SMPR2_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
#define ADC_SMPR2_SMP17_MASK (7 << ADC_SMPR2_SMP17_SHIFT)
#define ADC_SMPR2_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */
#define ADC_SMPR2_SMP18_MASK (7 << ADC_SMPR2_SMP17_SHIFT)
#define ADC_SMPR2_SMP18_MASK (7 << ADC_SMPR2_SMP18_SHIFT)
/* ADC watchdog threshold register 1 */