diff --git a/arch/arm/src/stm32/chip/stm32_adc.h b/arch/arm/src/stm32/chip/stm32_adc.h
index 6c84c513be2..73d3acb3532 100644
--- a/arch/arm/src/stm32/chip/stm32_adc.h
+++ b/arch/arm/src/stm32/chip/stm32_adc.h
@@ -479,7 +479,7 @@
 #  define ADC_SMPR1_SMP17_MASK       (7 << ADC_SMPR1_SMP17_SHIFT)
 #  if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
 #    define ADC_SMPR1_SMP18_SHIFT    (24)      /* Bits 24-26: Channel 18 Sample time selection */
-#    define ADC_SMPR1_SMP18_MASK     (7 << ADC_SMPR1_SMP17_SHIFT)
+#    define ADC_SMPR1_SMP18_MASK     (7 << ADC_SMPR1_SMP18_SHIFT)
 #  endif
 #else
 #  define ADC_SMPR1_SMP20_SHIFT      (0)       /* Bits 0-2: Channel 20 Sample time selection */
diff --git a/arch/arm/src/stm32/chip/stm32f30xxx_adc.h b/arch/arm/src/stm32/chip/stm32f30xxx_adc.h
index 7c9da24b0c1..c9d26873012 100644
--- a/arch/arm/src/stm32/chip/stm32f30xxx_adc.h
+++ b/arch/arm/src/stm32/chip/stm32f30xxx_adc.h
@@ -352,8 +352,8 @@
 #define ADC_SMPR2_SMP16_MASK         (7 << ADC_SMPR2_SMP16_SHIFT)
 #define ADC_SMPR2_SMP17_SHIFT        (21)      /* Bits 21-23: Channel 17 Sample time selection */
 #define ADC_SMPR2_SMP17_MASK         (7 << ADC_SMPR2_SMP17_SHIFT)
-#define ADC_SMPR2_SMP18_SHIFT        (21)      /* Bits 24-26: Channel 18 Sample time selection */
-#define ADC_SMPR2_SMP18_MASK         (7 << ADC_SMPR2_SMP17_SHIFT)
+#define ADC_SMPR2_SMP18_SHIFT        (24)      /* Bits 24-26: Channel 18 Sample time selection */
+#define ADC_SMPR2_SMP18_MASK         (7 << ADC_SMPR2_SMP18_SHIFT)
 
 /* ADC watchdog threshold register 1 */
 
diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_adc.h b/arch/arm/src/stm32/chip/stm32f33xxx_adc.h
index b6609d08280..c645c7f869d 100644
--- a/arch/arm/src/stm32/chip/stm32f33xxx_adc.h
+++ b/arch/arm/src/stm32/chip/stm32f33xxx_adc.h
@@ -286,8 +286,8 @@
 #define ADC_SMPR2_SMP16_MASK         (7 << ADC_SMPR2_SMP16_SHIFT)
 #define ADC_SMPR2_SMP17_SHIFT        (21)      /* Bits 21-23: Channel 17 Sample time selection */
 #define ADC_SMPR2_SMP17_MASK         (7 << ADC_SMPR2_SMP17_SHIFT)
-#define ADC_SMPR2_SMP18_SHIFT        (21)      /* Bits 24-26: Channel 18 Sample time selection */
-#define ADC_SMPR2_SMP18_MASK         (7 << ADC_SMPR2_SMP17_SHIFT)
+#define ADC_SMPR2_SMP18_SHIFT        (24)      /* Bits 24-26: Channel 18 Sample time selection */
+#define ADC_SMPR2_SMP18_MASK         (7 << ADC_SMPR2_SMP18_SHIFT)
 
 /* ADC watchdog threshold register 1 */
 
diff --git a/arch/arm/src/stm32/chip/stm32f37xxx_adc.h b/arch/arm/src/stm32/chip/stm32f37xxx_adc.h
index 95a40ade448..c8dcbbccb47 100644
--- a/arch/arm/src/stm32/chip/stm32f37xxx_adc.h
+++ b/arch/arm/src/stm32/chip/stm32f37xxx_adc.h
@@ -183,8 +183,8 @@
 #define ADC_SMPR1_SMP16_MASK         (7 << ADC_SMPR1_SMP16_SHIFT)
 #define ADC_SMPR1_SMP17_SHIFT        (21)      /* Bits 21-23: Channel 17 Sample time selection */
 #define ADC_SMPR1_SMP17_MASK         (7 << ADC_SMPR1_SMP17_SHIFT)
-#define ADC_SMPR1_SMP18_SHIFT        (21)      /* Bits 24-26: Channel 18 Sample time selection */
-#define ADC_SMPR1_SMP18_MASK         (7 << ADC_SMPR1_SMP17_SHIFT)
+#define ADC_SMPR1_SMP18_SHIFT        (24)      /* Bits 24-26: Channel 18 Sample time selection */
+#define ADC_SMPR1_SMP18_MASK         (7 << ADC_SMPR1_SMP18_SHIFT)
 
 /* ADC sample time register 2 */
 
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_adc.h b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_adc.h
index bc79490798b..14685022a4e 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_adc.h
+++ b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_adc.h
@@ -276,7 +276,7 @@
 #define ADC_SMPR1_SMP17_SHIFT        (21)      /* Bits 21-23: Channel 17 Sample time selection */
 #define ADC_SMPR1_SMP17_MASK         (7 << ADC_SMPR1_SMP17_SHIFT)
 #define ADC_SMPR1_SMP18_SHIFT        (24)      /* Bits 24-26: Channel 18 Sample time selection */
-#define ADC_SMPR1_SMP18_MASK         (7 << ADC_SMPR1_SMP17_SHIFT)
+#define ADC_SMPR1_SMP18_MASK         (7 << ADC_SMPR1_SMP18_SHIFT)
 
 
 /* ADC sample time register 2 */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_adc.h b/arch/arm/src/stm32l4/chip/stm32l4_adc.h
index 8a01e41771c..f133306146e 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_adc.h
+++ b/arch/arm/src/stm32l4/chip/stm32l4_adc.h
@@ -350,7 +350,7 @@
 #define ADC_SMPR2_SMP17_SHIFT        (21)      /* Bits 21-23: Channel 17 Sample time selection */
 #define ADC_SMPR2_SMP17_MASK         (7 << ADC_SMPR2_SMP17_SHIFT)
 #define ADC_SMPR2_SMP18_SHIFT        (24)      /* Bits 24-26: Channel 18 Sample time selection */
-#define ADC_SMPR2_SMP18_MASK         (7 << ADC_SMPR2_SMP17_SHIFT)
+#define ADC_SMPR2_SMP18_MASK         (7 << ADC_SMPR2_SMP18_SHIFT)
 
 /* ADC watchdog threshold register 1 */