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arch: arm: efm32: fix nxstyle errors

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Fix nxstyle errors to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea
2021-03-24 09:19:50 +01:00
committed by Xiang Xiao
parent de435a8a1e
commit a1b653d8b6
58 changed files with 1424 additions and 1144 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/efm32/chip.h
+9 -9
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/chip.h
*
* Copyright (C) 2009, 2011-2014, 2018 Gregory Nutt. All rights reserved.
@@ -33,14 +33,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_H
#define __ARCH_ARM_SRC_EFM32_CHIP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -52,13 +52,13 @@
#include <arch/efm32/irq.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Provide the required number of peripheral interrupt vector definitions as well.
* The definition EFM32_PERIPH_INTS simply comes from the chip-specific IRQ header
* file included by arch/efm32/irq.h.
/* Provide the required number of peripheral interrupt vector definitions as
* well. The definition EFM32_PERIPH_INTS simply comes from the chip-specific
* IRQ header file included by arch/efm32/irq.h.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS EFM32_PERIPH_INTS
arch/arm/src/efm32/efm32_adc.c
+72 -40
View File
@@ -79,6 +79,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* ADC interrupts ***********************************************************/
/* The maximum number of channels that can be sampled. If dma support is
@@ -117,12 +118,14 @@ struct efm32_dev_s
/* ADC Register access */
static uint32_t adc_getreg(struct efm32_dev_s *priv, int offset);
static void adc_putreg(struct efm32_dev_s *priv, int offset, uint32_t value);
static void adc_putreg(struct efm32_dev_s *priv, int offset,
uint32_t value);
static void adc_hw_reset(struct efm32_dev_s *priv, bool reset);
/* ADC Interrupt Handler */
static int adc_interrupt(int irq, FAR void *context, FAR struct adc_dev_s *dev);
static int adc_interrupt(int irq,
FAR void *context, FAR struct adc_dev_s *dev);
/* ADC Driver Methods */
@@ -227,9 +230,9 @@ static void adc_putreg(struct efm32_dev_s *priv, int offset, uint32_t value)
* reference.
*
* During production, calibration values are made and stored in the device
* information page for known references. Notice that for external references,
* calibration values must be determined explicitly, and this function
* will not modify the calibration register.
* information page for known references. Notice that for external
* references, calibration values must be determined explicitly, and this
* function will not modify the calibration register.
*
* Input Parameters:
* adc - Pointer to ADC peripheral register block.
@@ -254,7 +257,8 @@ static void ADC_CalibrateLoadScan(ADC_TypeDef *adc, ADC_Ref_TypeDef ref)
cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_1V25_GAIN_MASK) >>
_DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT) << _ADC_CAL_SCANGAIN_SHIFT;
cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK) >>
_DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT) << _ADC_CAL_SCANOFFSET_SHIFT;
_DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT) <<
_ADC_CAL_SCANOFFSET_SHIFT;
adc->CAL = cal;
break;
@@ -263,7 +267,8 @@ static void ADC_CalibrateLoadScan(ADC_TypeDef *adc, ADC_Ref_TypeDef ref)
cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_2V5_GAIN_MASK) >>
_DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT) << _ADC_CAL_SCANGAIN_SHIFT;
cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK) >>
_DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT) << _ADC_CAL_SCANOFFSET_SHIFT;
_DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT) <<
_ADC_CAL_SCANOFFSET_SHIFT;
adc->CAL = cal;
break;
@@ -272,7 +277,8 @@ static void ADC_CalibrateLoadScan(ADC_TypeDef *adc, ADC_Ref_TypeDef ref)
cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_VDD_GAIN_MASK) >>
_DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT) << _ADC_CAL_SCANGAIN_SHIFT;
cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK) >>
_DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT) << _ADC_CAL_SCANOFFSET_SHIFT;
_DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT) <<
_ADC_CAL_SCANOFFSET_SHIFT;
adc->CAL = cal;
break;
@@ -281,16 +287,19 @@ static void ADC_CalibrateLoadScan(ADC_TypeDef *adc, ADC_Ref_TypeDef ref)
cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK) >>
_DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT) << _ADC_CAL_SCANGAIN_SHIFT;
cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK) >>
_DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT) << _ADC_CAL_SCANOFFSET_SHIFT;
_DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT) <<
_ADC_CAL_SCANOFFSET_SHIFT;
adc->CAL = cal;
break;
case adcRef2xVDD:
/* Gain value not of relevance for this reference, leave as is */
cal = adc->CAL & ~_ADC_CAL_SCANOFFSET_MASK;
cal |= ((DEVINFO->ADC0CAL2 & _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK) >>
_DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT) << _ADC_CAL_SCANOFFSET_SHIFT;
_DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT) <<
_ADC_CAL_SCANOFFSET_SHIFT;
adc->CAL = cal;
break;
@@ -311,9 +320,9 @@ static void ADC_CalibrateLoadScan(ADC_TypeDef *adc, ADC_Ref_TypeDef ref)
* reference.
*
* During production, calibration values are made and stored in the device
* information page for known references. Notice that for external references,
* calibration values must be determined explicitly, and this function
* will not modify the calibration register.
* information page for known references. Notice that for external
* references, calibration values must be determined explicitly, and this
* function will not modify the calibration register.
*
* Input Parameters:
* adc - Pointer to ADC peripheral register block.
@@ -334,47 +343,58 @@ static void ADC_CalibrateLoadSingle(ADC_TypeDef *adc, ADC_Ref_TypeDef ref)
switch (ref)
{
case adcRef1V25:
cal = adc->CAL & ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK);
cal = adc->CAL &
~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK);
cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_1V25_GAIN_MASK) >>
_DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT) << _ADC_CAL_SINGLEGAIN_SHIFT;
cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK) >>
_DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT;
_DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT) <<
_ADC_CAL_SINGLEOFFSET_SHIFT;
adc->CAL = cal;
break;
case adcRef2V5:
cal = adc->CAL & ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK);
cal = adc->CAL &
~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK);
cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_2V5_GAIN_MASK) >>
_DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT) << _ADC_CAL_SINGLEGAIN_SHIFT;
cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK) >>
_DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT;
_DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT) <<
_ADC_CAL_SINGLEOFFSET_SHIFT;
adc->CAL = cal;
break;
case adcRefVDD:
cal = adc->CAL & ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK);
cal = adc->CAL &
~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK);
cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_VDD_GAIN_MASK) >>
_DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT) << _ADC_CAL_SINGLEGAIN_SHIFT;
cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK) >>
_DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT;
_DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT) <<
_ADC_CAL_SINGLEOFFSET_SHIFT;
adc->CAL = cal;
break;
case adcRef5VDIFF:
cal = adc->CAL & ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK);
cal = adc->CAL &
~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK);
cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK) >>
_DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT) << _ADC_CAL_SINGLEGAIN_SHIFT;
_DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT) <<
_ADC_CAL_SINGLEGAIN_SHIFT;
cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK) >>
_DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT;
_DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT) <<
_ADC_CAL_SINGLEOFFSET_SHIFT;
adc->CAL = cal;
break;
case adcRef2xVDD:
/* Gain value not of relevance for this reference, leave as is */
cal = adc->CAL & ~_ADC_CAL_SINGLEOFFSET_MASK;
cal |= ((DEVINFO->ADC0CAL2 & _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK) >>
_DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT;
_DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT) <<
_ADC_CAL_SINGLEOFFSET_SHIFT;
adc->CAL = cal;
break;
@@ -397,8 +417,8 @@ static void ADC_CalibrateLoadSingle(ADC_TypeDef *adc, ADC_Ref_TypeDef ref)
*
* Description:
* Initializes common parts for both single conversion and scan sequence.
* In addition, single and/or scan control configuration must be done, please
* refer to ADC_InitSingle() and ADC_InitScan() respectively.
* In addition, single and/or scan control configuration must be done,
* please refer to ADC_InitSingle() and ADC_InitScan() respectively.
*
* NOTE: This function will stop any ongoing conversion.
*
@@ -419,8 +439,10 @@ void ADC_Init(ADC_TypeDef *adc, const ADC_Init_TypeDef *init)
adc->CMD = ADC_CMD_SINGLESTOP | ADC_CMD_SCANSTOP;
tmp = ((uint32_t)(init->ovsRateSel) << _ADC_CTRL_OVSRSEL_SHIFT) |
(((uint32_t)(init->timebase) << _ADC_CTRL_TIMEBASE_SHIFT) & _ADC_CTRL_TIMEBASE_MASK) |
(((uint32_t)(init->prescale) << _ADC_CTRL_PRESC_SHIFT) & _ADC_CTRL_PRESC_MASK) |
(((uint32_t)(init->timebase) << _ADC_CTRL_TIMEBASE_SHIFT) &
_ADC_CTRL_TIMEBASE_MASK) |
(((uint32_t)(init->prescale) << _ADC_CTRL_PRESC_SHIFT) &
_ADC_CTRL_PRESC_MASK) |
((uint32_t)(init->lpfMode) << _ADC_CTRL_LPFMODE_SHIFT) |
((uint32_t)(init->warmUpMode) << _ADC_CTRL_WARMUPMODE_SHIFT);
@@ -568,7 +590,8 @@ void ADC_InitSingle(ADC_TypeDef *adc, const ADC_InitSingle_TypeDef *init)
*
* Input Parameters:
* adcFreq ADC frequency wanted. The frequency will automatically
* be adjusted to be within valid range according to reference manual.
* be adjusted to be within valid range according to reference
* manual.
* hfperFreq Frequency in Hz of reference HFPER clock. Set to 0 to
* use currently defined HFPER clock setting.
*
@@ -648,7 +671,8 @@ void ADC_Reset(ADC_TypeDef *adc)
* Name: ADC_TimebaseCalc
*
* Description:
* Calculate timebase value in order to get a timebase providing at least 1us.
* Calculate timebase value in order to get a timebase providing at least
* 1us.
*
* Input Parameters:
* hfperFreq Frequency in Hz of reference HFPER clock. Set to 0 to
@@ -696,6 +720,7 @@ uint8_t ADC_TimebaseCalc(uint32_t hfperFreq)
return (uint8_t)(hfperFreq - 1);
}
endif /* defined(ADC_COUNT) && (ADC_COUNT > 0) */
/****************************************************************************
@@ -882,8 +907,8 @@ static void adc_enable(FAR struct efm32_dev_s *priv, bool enable)
* Name: adc_bind
*
* Description:
* Bind the upper-half driver callbacks to the lower-half implementation. This
* must be called early in order to receive ADC event notifications.
* Bind the upper-half driver callbacks to the lower-half implementation.
* This must be called early in order to receive ADC event notifications.
*
****************************************************************************/
@@ -1015,16 +1040,18 @@ static void adc_reset(FAR struct adc_dev_s *dev)
/* ADC CCR configuration */
regval = getreg32(EFM32_ADC_CCR);
regval &= ~(ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | ADC_CCR_DMA_MASK |
regval &= ~(ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK |
ADC_CCR_DDS | ADC_CCR_DMA_MASK |
ADC_CCR_ADCPRE_MASK | ADC_CCR_VBATE | ADC_CCR_TSVREFE);
regval |= (ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED | ADC_CCR_ADCPRE_DIV2);
regval |= (ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED |
ADC_CCR_ADCPRE_DIV2);
putreg32(regval, EFM32_ADC_CCR);
/* Set the number of conversions */
DEBUGASSERT(priv->nchannels <= ADC_MAX_SAMPLES);
regval |= (((uint32_t)priv->nchannels-1) << ADC_SQR1_L_SHIFT);
regval |= (((uint32_t)priv->nchannels - 1) << ADC_SQR1_L_SHIFT);
adc_putreg(priv, EFM32_ADC_SQR1_OFFSET, regval);
/* Set the channel index of the first conversion */
@@ -1055,8 +1082,8 @@ static void adc_reset(FAR struct adc_dev_s *dev)
* Description:
* Configure the ADC. This method is called the first time that the ADC
* device is opened. This will occur when the port is first opened.
* This setup includes configuring and attaching ADC interrupts. Interrupts
* are all disabled upon return.
* This setup includes configuring and attaching ADC interrupts.
* Interrupts are all disabled upon return.
*
* Input Parameters:
*
@@ -1179,7 +1206,8 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
*
****************************************************************************/
static int adc_interrupt(int irq, FAR void *context, FAR struct adc_dev_s *dev)
static int adc_interrupt(int irq,
FAR void *context, FAR struct adc_dev_s *dev)
{
FAR struct efm32_dev_s *priv = (FAR struct efm32_dev_s *)dev->ad_priv;
uint32_t adcsr;
@@ -1220,7 +1248,9 @@ static int adc_interrupt(int irq, FAR void *context, FAR struct adc_dev_s *dev)
priv->cb->au_receive(dev, priv->chanlist[priv->current], value);
}
/* Set the channel number of the next channel that will complete conversion */
/* Set the channel number of the next channel that will complete
* conversion
*/
priv->current++;
@@ -1245,7 +1275,8 @@ static int adc_interrupt(int irq, FAR void *context, FAR struct adc_dev_s *dev)
* Description:
* Initialize the ADC.
*
* The logic is, save nchannels : # of channels (conversions) in ADC_SQR1_L
* The logic is, save nchannels :
* # of channels (conversions) in ADC_SQR1_L
* Then, take the chanlist array and store it in the SQR Regs,
* chanlist[0] -> ADC_SQR3_SQ1
* chanlist[1] -> ADC_SQR3_SQ2
@@ -1265,7 +1296,8 @@ static int adc_interrupt(int irq, FAR void *context, FAR struct adc_dev_s *dev)
*
****************************************************************************/
struct adc_dev_s *efm32_adcinitialize(int intf, const uint8_t *chanlist, int nchannels)
struct adc_dev_s *efm32_adcinitialize(int intf,
const uint8_t *chanlist, int nchannels)
{
FAR struct adc_dev_s *dev;
FAR struct efm32_dev_s *priv;
arch/arm/src/efm32/efm32_adc.h
+31 -24
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/efm32_adc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_EFM32_ADC_H
#define __ARCH_ARM_SRC_EFM32_EFM32_ADC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -33,18 +33,20 @@
#include <nuttx/analog/adc.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
/* Timer devices may be used for different purposes. One special purpose is to
* control periodic ADC sampling. If CONFIG_EFM32_TIMn is defined then
* CONFIG_EFM32_TIMn_ADC must also be defined to indicate that timer "n" is intended
* to be used for that purpose.
****************************************************************************/
/* Configuration ************************************************************/
/* Timer devices may be used for different purposes. One special purpose is
* to control periodic ADC sampling. If CONFIG_EFM32_TIMn is defined then
* CONFIG_EFM32_TIMn_ADC must also be defined to indicate that timer "n" is
* intended to be used for that purpose.
*/
/* For the EFM32 F1 line, timers 1-4 may be used. For EFM32 F4 line, timers 1-5 and
* 8 may be used.
/* For the EFM32 F1 line, timers 1-4 may be used.
* For EFM32 F4 line, timers 1-5 and 8 may be used.
*/
#ifndef CONFIG_EFM32_TIM1
@@ -84,7 +86,9 @@
# undef CONFIG_EFM32_TIM8_ADC3
#endif
/* Timers 6, 7, and 10-14 are not used with the ADC by any supported family */
/* Timers 6, 7,
* and 10-14 are not used with the ADC by any supported family
*/
#undef CONFIG_EFM32_TIM6_ADC
#undef CONFIG_EFM32_TIM6_ADC1
@@ -141,8 +145,8 @@
# warning "DMA is not supported by the current driver"
#endif
/* Timer configuration: If a timer trigger is specified, then get information
* about the timer.
/* Timer configuration:
* If a timer trigger is specified, then get information about the timer.
*/
#if defined(CONFIG_EFM32_TIM1_ADC1)
@@ -268,11 +272,13 @@
# undef ADC_HAVE_TIMER
#endif
/* NOTE: The following assumes that all possible combinations of timers and
* values are support EXTSEL. That is not so and it varies from one EFM32 to another.
* But this (wrong) assumptions keeps the logic as simple as possible. If un
* unsupported combination is used, an error will show up later during compilation
* although it may be difficult to track it back to this simplification.
/* NOTE:
* The following assumes that all possible combinations of timers and values
* are support EXTSEL. That is not so and it varies from one EFM32 to
* another. But this (wrong) assumptions keeps the logic as simple as
* possible. If un unsupported combination is used, an error will show
* up later during compilation although it may be difficult to track it back
* to this simplification.
*/
#if defined(CONFIG_EFM32_TIM1_ADC1)
@@ -533,14 +539,15 @@
# endif
#endif
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
extern "C"
{
#else
#define EXTERN extern
#endif
arch/arm/src/efm32/efm32_bitband.c
+16 -6
View File
@@ -93,10 +93,13 @@
*
****************************************************************************/
inline void bitband_set_peripheral(uint32_t addr, uint32_t bit, uint32_t val)
inline void bitband_set_peripheral(uint32_t addr,
uint32_t bit, uint32_t val)
{
uint32_t regval;
regval = EFM32_BITBAND_PER_BASE + ((addr-EFM32_PER_MEM_BASE)*32) + (bit*4);
regval = EFM32_BITBAND_PER_BASE +
((addr - EFM32_PER_MEM_BASE) * 32) +
(bit * 4);
*((volatile uint32_t *)regval) = (uint32_t)val;
}
@@ -107,7 +110,8 @@ inline void bitband_set_peripheral(uint32_t addr, uint32_t bit, uint32_t val)
* Description:
* Perform bit-band operation on peripheral memory location.
*
* This function reads a single bit from the peripheral bit-band alias region.
* This function reads a single bit from the peripheral bit-band alias
* region.
* Bit-banding provides atomic read-modify-write cycle for single bit
* modification. Please refer to the reference manual for further details
* about bit-banding.
@@ -127,7 +131,9 @@ inline void bitband_set_peripheral(uint32_t addr, uint32_t bit, uint32_t val)
inline uint32_t bitband_get_peripheral(uint32_t addr, uint32_t bit)
{
uint32_t regval;
regval = EFM32_BITBAND_PER_BASE + ((addr-EFM32_PER_MEM_BASE)*32) + (bit*4);
regval = EFM32_BITBAND_PER_BASE +
((addr - EFM32_PER_MEM_BASE) * 32) +
(bit * 4);
return *((volatile uint32_t *)regval);
}
@@ -155,7 +161,9 @@ inline uint32_t bitband_get_peripheral(uint32_t addr, uint32_t bit)
inline void bitband_set_sram(uint32_t addr, uint32_t bit, uint32_t val)
{
uint32_t regval;
regval = EFM32_BITBAND_RAM_BASE + ((addr-EFM32_RAM_MEM_BASE)*32) + (bit*4);
regval = EFM32_BITBAND_RAM_BASE +
((addr - EFM32_RAM_MEM_BASE) * 32) +
(bit * 4);
*((volatile uint32_t *)regval) = (uint32_t)val;
}
@@ -186,7 +194,9 @@ inline void bitband_set_sram(uint32_t addr, uint32_t bit, uint32_t val)
inline uint32_t bitband_get_sram(uint32_t addr, uint32_t bit)
{
uint32_t regval;
regval = EFM32_BITBAND_RAM_BASE + ((addr-EFM32_RAM_MEM_BASE)*32) + (bit*4);
regval = EFM32_BITBAND_RAM_BASE +
((addr - EFM32_RAM_MEM_BASE) * 32) +
(bit * 4);
return *((volatile uint32_t *)regval);
}
arch/arm/src/efm32/efm32_bitband.h
+3 -2
View File
@@ -47,8 +47,8 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* Configuration ************************************************************/
/****************************************************************************
* Public Data
@@ -59,7 +59,8 @@
****************************************************************************/
#if defined(CONFIG_EFM32_BITBAND)
inline void bitband_set_peripheral(uint32_t addr, uint32_t bit, uint32_t val);
inline void bitband_set_peripheral(uint32_t addr,
uint32_t bit, uint32_t val);
inline uint32_t bitband_get_peripheral(uint32_t addr, uint32_t bit);
inline void bitband_set_sram(uint32_t addr, uint32_t bit, uint32_t val);
inline uint32_t bitband_get_sram(uint32_t addr, uint32_t bit);
arch/arm/src/efm32/efm32_clockconfig.c
+18 -11
View File
@@ -42,6 +42,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* BOARD Configuration ******************************************************/
/* Pre-scalers not currently implemented */
@@ -207,7 +208,6 @@ static void efm32_enable_leclocking(void)
putreg32(regval, EFM32_CMU_HFCORECLKEN0);
}
/****************************************************************************
* Name: efm32_maxwaitstates
*
@@ -241,7 +241,7 @@ static void efm32_maxwaitstates(void)
regval |= MSC_READCTRL_MODE_WSMAXSCBTP;
}
else
else
{
/* No.. select the mximum number of wait states without SCBTP */
@@ -353,7 +353,8 @@ static void efm32_setwaitstates(uint32_t hfcoreclk)
*
****************************************************************************/
static inline uint32_t efm32_hfclk_config(uint32_t hfclksel, uint32_t hfclkdiv)
static inline uint32_t efm32_hfclk_config(uint32_t hfclksel,
uint32_t hfclkdiv)
{
uint32_t frequency;
#ifdef CMU_CTRL_HFLE
@@ -399,10 +400,11 @@ static inline uint32_t efm32_hfclk_config(uint32_t hfclksel, uint32_t hfclkdiv)
#ifdef CMU_CTRL_HFLE
#if BOARD_HFXO_FREQUENCY > CMU_MAX_FREQ_HFLE
/* Adjust HFXO buffer current for high crystal frequencies, enable HFLE
* for frequencies above CMU_MAX_FREQ_HFLE.
/* Adjust HFXO buffer current for high crystal frequencies,
* enable HFLE for frequencies above CMU_MAX_FREQ_HFLE.
*
* We must also have HFLE enabled to access some LE peripherals >= 32MHz.
* We must also have HFLE enabled to access some LE peripherals
* >= 32MHz.
*/
regval = getreg32(EFM32_CMU_CTRL);
@@ -556,6 +558,7 @@ static inline uint32_t efm32_hfcoreclk_config(uint32_t hfcoreclkdiv,
uint32_t hfclk)
{
/* REVISIT: Divider not currently used */
return hfclk;
}
@@ -883,7 +886,8 @@ static inline void efm32_itm_syslog(void)
regval = getreg32(EFM32_GPIO_ROUTE);
regval &= ~_GPIO_ROUTE_SWLOCATION_MASK;
regval |= GPIO_ROUTE_SWOPEN;
regval |= ((uint32_t)BOARD_SWOPORT_LOCATION << _GPIO_ROUTE_SWLOCATION_SHIFT);
regval |= ((uint32_t)BOARD_SWOPORT_LOCATION <<
_GPIO_ROUTE_SWLOCATION_SHIFT);
putreg32(regval, EFM32_GPIO_ROUTE);
/* Enable output on pin */
@@ -893,7 +897,6 @@ static inline void efm32_itm_syslog(void)
/* Enable debug clock AUXHFRCO */
efm32_enable_auxhfrco();
}
#else
# define efm32_itm_syslog()
@@ -922,14 +925,18 @@ void efm32_clockconfig(void)
uint32_t lfaclk;
uint32_t lfbclk;
/* Enable clocks and set dividers as determined by the board.h header file */
/* Enable clocks and set dividers as determined by the board.h header
* file
*/
hfclk = efm32_hfclk_config(BOARD_HFCLKSEL, BOARD_HFCLKDIV);
hfcoreclk = efm32_hfcoreclk_config(BOARD_HFCORECLKDIV, hfclk);
hfperclk = efm32_hfperclk_config(BOARD_HFPERCLKDIV, hfclk);
coreleclk = efm32_coreleclk_config(hfclk);
lfaclk = efm32_lfaclk_config(BOARD_LFACLKSEL, BOARD_LFA_ULFCO_ENABLE, hfcoreclk);
lfbclk = efm32_lfbclk_config(BOARD_LFBCLKSEL, BOARD_LFB_ULFCO_ENABLE, hfcoreclk);
lfaclk = efm32_lfaclk_config(BOARD_LFACLKSEL,
BOARD_LFA_ULFCO_ENABLE, hfcoreclk);
lfbclk = efm32_lfbclk_config(BOARD_LFBCLKSEL,
BOARD_LFB_ULFCO_ENABLE, hfcoreclk);
efm32_pcntclk_config();
efm32_wdogclk_config();
arch/arm/src/efm32/efm32_clockconfig.h
+1 -1
View File
@@ -28,7 +28,7 @@
#include <nuttx/config.h>
/****************************************************************************
* Public Functions
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
arch/arm/src/efm32/efm32_config.h
+2
View File
@@ -30,7 +30,9 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* Make sure that the configuration does not enable UARTs that the MCU does
* not have.
*/
arch/arm/src/efm32/efm32_dma.h
+54 -47
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/efm32_dma.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_EFM32_DMA_H
#define __ARCH_ARM_SRC_EFM32_EFM32_DMA_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -34,12 +34,12 @@
#include "chip.h"
#include "hardware/efm32_dma.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Bit encoded input parameter to efm32_channel(). These encodings must fit in the
* an unsigned integer of type dma_config_t.
/* Bit encoded input parameter to efm32_channel().
* These encodings must fit in the an unsigned integer of type dma_config_t.
*
* Current limitations/assumptions in the encoding:
*
@@ -70,12 +70,12 @@
# define EFM32_DMA_MEMINCR (1 << 13) /* 1=Increment memory address */
# define EFM32_DMA_NOINCR (0) /* 0=No memory address increment */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/* DMA_HANDLE provides an opaque reference that can be used to represent a DMA
* channel.
/* DMA_HANDLE provides an opaque reference that can be used to represent a
* DMA channel.
*/
typedef FAR void *DMA_HANDLE;
@@ -122,16 +122,17 @@ struct efm32_dmaregs_s
};
#endif
/* Type of 'config' argument passed to efm32_rxdmasetup() and efm32_txdmasetup.
* See EFM32_DMA_* encodings above. If these encodings exceed 16-bits, then this
* should be changed to a uint32_t.
/* Type of 'config' argument passed to efm32_rxdmasetup() and
* efm32_txdmasetup. See EFM32_DMA_* encodings above.
* If these encodings exceed 16-bits, then this should be changed to a
* uint32_t.
*/
typedef uint16_t dma_config_t;
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
@@ -144,19 +145,21 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: efm32_dmachannel
*
* Description:
* Allocate a DMA channel. This function gives the caller mutually exclusive
* access to a DMA channel.
* Allocate a DMA channel.
* This function gives the caller mutually exclusive access to a DMA
* channel.
*
* If no DMA channel is available, then efm32_dmachannel() will wait until the
* holder of a channel relinquishes the channel by calling efm32_dmafree().
* If no DMA channel is available, then efm32_dmachannel() will wait until
* the holder of a channel relinquishes the channel by calling
* efm32_dmafree().
*
* Input Parameters:
* None
@@ -165,21 +168,23 @@ extern "C"
* This function ALWAYS returns a non-NULL, void* DMA channel handle.
*
* Assumptions:
* - The caller can wait for a DMA channel to be freed if it is not available.
* - The caller can wait for a DMA channel to be freed if it is not
* available.
*
************************************************************************************/
****************************************************************************/
DMA_HANDLE efm32_dmachannel(void);
/************************************************************************************
/****************************************************************************
* Name: efm32_dmafree
*
* Description:
* Release a DMA channel. If another thread is waiting for this DMA channel in a
* call to efm32_dmachannel, then this function will re-assign the DMA channel to
* that thread and wake it up. NOTE: The 'handle' used in this argument must
* NEVER be used again until efm32_dmachannel() is called again to re-gain access
* to the channel.
* Release a DMA channel.
* If another thread is waiting for this DMA channel in a call to
* efm32_dmachannel, then this function will re-assign the DMA channel to
* that thread and wake it up. NOTE: The 'handle' used in this argument
* must NEVER be used again until efm32_dmachannel() is called again to
* re-gain access to the channel.
*
* Returned Value:
* None
@@ -188,11 +193,11 @@ DMA_HANDLE efm32_dmachannel(void);
* - The caller holds the DMA channel.
* - There is no DMA in progress
*
************************************************************************************/
****************************************************************************/
void efm32_dmafree(DMA_HANDLE handle);
/************************************************************************************
/****************************************************************************
* Name: efm32_rxdmasetup
*
* Description:
@@ -205,12 +210,12 @@ void efm32_dmafree(DMA_HANDLE handle);
* configured transfer size.
* config - Channel configuration selections
*
************************************************************************************/
****************************************************************************/
void efm32_rxdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr,
size_t nbytes, dma_config_t config);
/************************************************************************************
/****************************************************************************
* Name: efm32_txdmasetup
*
* Description:
@@ -223,12 +228,12 @@ void efm32_rxdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr,
* configured transfer size.
* config - Channel configuration selections
*
************************************************************************************/
****************************************************************************/
void efm32_txdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr,
size_t nbytes, dma_config_t config);
/************************************************************************************
/****************************************************************************
* Name: efm32_dmastart
*
* Description:
@@ -238,25 +243,27 @@ void efm32_txdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr,
* - DMA handle allocated by efm32_dmachannel()
* - No DMA in progress
*
************************************************************************************/
****************************************************************************/
void efm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
/************************************************************************************
/****************************************************************************
* Name: efm32_dmastop
*
* Description:
* Cancel the DMA. After efm32_dmastop() is called, the DMA channel is reset and
* efm32_dmasetup() must be called before efm32_dmastart() can be called again
* Cancel the DMA.
* After efm32_dmastop() is called, the DMA channel is reset and
* efm32_dmasetup() must be called before efm32_dmastart() can be called
* again
*
* Assumptions:
* - DMA handle allocated by efm32_dmachannel()
*
************************************************************************************/
****************************************************************************/
void efm32_dmastop(DMA_HANDLE handle);
/************************************************************************************
/****************************************************************************
* Name: efm32_dmasample
*
* Description:
@@ -265,7 +272,7 @@ void efm32_dmastop(DMA_HANDLE handle);
* Assumptions:
* - DMA handle allocated by efm32_dmachannel()
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_DEBUG_DMA_INFO
void efm32_dmasample(DMA_HANDLE handle, struct efm32_dmaregs_s *regs);
@@ -273,7 +280,7 @@ void efm32_dmasample(DMA_HANDLE handle, struct efm32_dmaregs_s *regs);
# define efm32_dmasample(handle,regs)
#endif
/************************************************************************************
/****************************************************************************
* Name: efm32_dmadump
*
* Description:
@@ -282,7 +289,7 @@ void efm32_dmasample(DMA_HANDLE handle, struct efm32_dmaregs_s *regs);
* Assumptions:
* - DMA handle allocated by efm32_dmachannel()
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_DEBUG_DMA_INFO
void efm32_dmadump(DMA_HANDLE handle, const struct efm32_dmaregs_s *regs,
arch/arm/src/efm32/efm32_flash.c
+80 -65
View File
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,17 +56,17 @@
*
****************************************************************************/
/* Provides standard flash access functions, to be used by the flash mtd driver.
* The interface is defined in the include/nuttx/progmem.h
/* Provides standard flash access functions, to be used by the flash mtd
* driver. The interface is defined in the include/nuttx/progmem.h
*
* Requirements during write/erase operations on FLASH:
* - HSI must be ON.
* - Low Power Modes are not permitted during write/erase
*/
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -91,9 +91,9 @@
#if (defined(CONFIG_ARCH_CHIP_EFM32) && defined(CONFIG_EFM32_FLASHPROG))
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
#ifndef CONFIG_ARCH_RAMFUNCS
# error "Flashing function should executed in ram"
@@ -117,8 +117,8 @@
/* brief:
* The timeout used while waiting for the flash to become ready after
* a write. This number indicates the number of iterations to perform before
* issuing a timeout.
* a write. This number indicates the number of iterations to perform
* before issuing a timeout.
* note:
* This timeout is set very large (in the order of 100x longer than
* necessary). This is to avoid any corner cases.
@@ -126,9 +126,9 @@
#define MSC_PROGRAM_TIMEOUT 10000000ul
/************************************************************************************
/****************************************************************************
* Private Functions
************************************************************************************/
****************************************************************************/
void efm32_flash_unlock(void)
{
@@ -238,7 +238,6 @@ int __ramfunc__ msc_load_verify_address(uint32_t *address)
status = getreg32(EFM32_MSC_STATUS);
if (status & (MSC_STATUS_INVADDR | MSC_STATUS_LOCKED))
{
/* Check for invalid address */
if (status & MSC_STATUS_INVADDR)
@@ -263,8 +262,8 @@ int __ramfunc__ msc_load_verify_address(uint32_t *address)
* Description:
* Perform data phase of FLASH write cycle.
*
* This function performs the data phase of a Flash write operation by loading
* the given number of 32-bit words to the WDATA register.
* This function performs the data phase of a Flash write operation by
* loading the given number of 32-bit words to the WDATA register.
*
* note:
* This function MUST be executed from RAM. Failure to execute this portion
@@ -294,12 +293,14 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words,
#if defined(_MSC_WRITECTRL_LPWRITE_MASK) && defined(_MSC_WRITECTRL_WDOUBLE_MASK)
/* If LPWRITE (Low Power Write) is NOT enabled, set WDOUBLE (Write Double word) */
/* If LPWRITE (Low Power Write) is NOT enabled,
* set WDOUBLE (Write Double word)
*/
if (!(getreg32(EFM32_MSC_WRITECTRL) & MSC_WRITECTRL_LPWRITE))
{
/* If the number of words to be written are odd, we need to align by writing
* a single word first, before setting the WDOUBLE bit.
/* If the number of words to be written are odd, we need to align by
* writing a single word first, before setting the WDOUBLE bit.
*/
if (num_words & 0x1)
@@ -322,20 +323,22 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words,
/* Clear double word option, in order to write one single word. */
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WDOUBLE_SHIFT, 0);
bitband_set_peripheral(EFM32_MSC_WRITECTRL,
_MSC_WRITECTRL_WDOUBLE_SHIFT, 0);
/* Write first data word. */
putreg32(*data++, EFM32_MSC_WDATA);
putreg32(MSC_WRITECMD_WRITEONCE, EFM32_MSC_WRITECMD);
/* Wait for the operation to finish. It may be required to change the
* WDOUBLE config after the initial write. It should not be changed
* while BUSY.
/* Wait for the operation to finish. It may be required to change
* the WDOUBLE config after the initial write. It should not be
* changed while BUSY.
*/
timeout = MSC_PROGRAM_TIMEOUT;
while ((getreg32(EFM32_MSC_STATUS) & MSC_STATUS_BUSY) && (timeout != 0))
while ((getreg32(EFM32_MSC_STATUS) & MSC_STATUS_BUSY) &&
(timeout != 0))
{
timeout--;
}
@@ -353,11 +356,12 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words,
ret = 0;
}
/* Now we can set the double word option in order to write two words per
* data phase.
/* Now we can set the double word option in order to write two words
* per data phase.
*/
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WDOUBLE_SHIFT, 1);
bitband_set_peripheral(EFM32_MSC_WRITECTRL,
_MSC_WRITECTRL_WDOUBLE_SHIFT, 1);
words_per_data_phase = 2;
}
else
@@ -374,7 +378,6 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words,
if (write_strategy_safe)
{
/* Requires a system core clock at 1MHz or higher */
DEBUGASSERT(BOARD_SYSTEM_FREQUENCY >= 1000000);
@@ -386,7 +389,8 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words,
word_index++;
if (words_per_data_phase == 2)
{
while (!(getreg32(EFM32_MSC_STATUS) & MSC_STATUS_WDATAREADY))
while (!(getreg32(EFM32_MSC_STATUS) &
MSC_STATUS_WDATAREADY))
{
}
@@ -439,7 +443,6 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words,
while (word_index < num_words)
{
/* Wait for the MSC to be ready for the next word. */
while (!(getreg32(EFM32_MSC_STATUS) & MSC_STATUS_WDATAREADY))
@@ -448,13 +451,13 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words,
/* If the write to MSC->WDATA below missed the 30us timeout
* and the following MSC_WRITECMD_WRITETRIG command arrived
* while MSC_STATUS_BUSY is 1, then the MSC_WRITECMD_WRITETRIG
* could be ignored by the MSC. In this case,
* MSC_STATUS_WORDTIMEOUT is set to 1 and MSC_STATUS_BUSY is
* 0. A new trigger is therefore needed here to complete write
* of data in MSC->WDATA. If WDATAREADY became high since
* entry into this loop, exit and continue to the next WDATA
* write.
* while MSC_STATUS_BUSY is 1, then the
* MSC_WRITECMD_WRITETRIG could be ignored by the MSC.
* In this case, MSC_STATUS_WORDTIMEOUT is set to 1 and
* MSC_STATUS_BUSY is 0. A new trigger is therefore needed
* here to complete write of data in MSC->WDATA.
* If WDATAREADY became high since entry into this loop,
* exit and continue to the next WDATA write.
*/
regval = getreg32(EFM32_MSC_STATUS);
@@ -500,7 +503,8 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words,
/* Clear double word option, which should not be left on when returning. */
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WDOUBLE_SHIFT, 0);
bitband_set_peripheral(EFM32_MSC_WRITECTRL,
_MSC_WRITECTRL_WDOUBLE_SHIFT, 0);
#endif
@@ -511,7 +515,8 @@ void efm32_flash_lock(void)
{
/* Disable writing to the flash */
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 0);
bitband_set_peripheral(EFM32_MSC_WRITECTRL,
_MSC_WRITECTRL_WREN_SHIFT, 0);
/* Unlock the EFM32_MSC */
@@ -527,7 +532,7 @@ uint32_t efm32_get_flash_size(void)
regval = (regval & _DEVINFO_MEMINFO_SIZE_FLASH_MASK) \
>> _DEVINFO_MEMINFO_SIZE_FLASH_SHIFT;
return regval*1024;
return regval * 1024;
}
#endif
@@ -544,7 +549,7 @@ uint32_t efm32_get_flash_page_size(void)
return 512;
}
return 1 << (regval+10);
return 1 << (regval + 10);
}
#endif
@@ -552,13 +557,13 @@ uint32_t efm32_get_flash_page_size(void)
#define EFM32_FLASH_NPAGES efm32_get_flash_page_nbr()
uint32_t efm32_get_flash_page_nbr(void)
{
return (EFM32_FLASH_SIZE/EFM32_FLASH_PAGESIZE);
return (EFM32_FLASH_SIZE / EFM32_FLASH_PAGESIZE);
}
#endif
/************************************************************************************
/****************************************************************************
* Public Functions
************************************************************************************/
****************************************************************************/
size_t up_progmem_pagesize(size_t page)
{
@@ -586,7 +591,7 @@ ssize_t up_progmem_getpage(size_t addr)
{
#if (EFM32_FLASH_BASE != 0)
if ((addr >= (EFM32_FLASH_BASE)) && \
(addr < (EFM32_FLASH_BASE+EFM32_FLASH_SIZE)))
(addr < (EFM32_FLASH_BASE + EFM32_FLASH_SIZE)))
{
addr -= EFM32_FLASH_BASE;
@@ -601,7 +606,7 @@ ssize_t up_progmem_getpage(size_t addr)
#endif
if ((addr >= (EFM32_USERDATA_BASE)) && \
(addr < (EFM32_USERDATA_BASE+EFM32_USERDATA_SIZE)))
(addr < (EFM32_USERDATA_BASE + EFM32_USERDATA_SIZE)))
{
addr -= EFM32_USERDATA_BASE;
@@ -630,7 +635,7 @@ size_t up_progmem_getaddress(size_t page)
size_t up_progmem_neraseblocks(void)
{
return EFM32_FLASH_NPAGES+EFM32_USERDATA_NPAGES;
return EFM32_FLASH_NPAGES + EFM32_USERDATA_NPAGES;
}
bool up_progmem_isuniform(void)
@@ -645,7 +650,7 @@ ssize_t __ramfunc__ up_progmem_eraseblock(size_t block)
uint32_t regval;
irqstate_t flags;
if (block >= (EFM32_FLASH_NPAGES+EFM32_USERDATA_NPAGES))
if (block >= (EFM32_FLASH_NPAGES + EFM32_USERDATA_NPAGES))
{
return -EFAULT;
}
@@ -656,7 +661,8 @@ ssize_t __ramfunc__ up_progmem_eraseblock(size_t block)
/* enable writing to the flash */
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 1);
bitband_set_peripheral(EFM32_MSC_WRITECTRL,
_MSC_WRITECTRL_WREN_SHIFT, 1);
/* Load address */
@@ -688,7 +694,8 @@ ssize_t __ramfunc__ up_progmem_eraseblock(size_t block)
/* Wait for the erase to complete */
timeout = MSC_PROGRAM_TIMEOUT;
while ((getreg32(EFM32_MSC_STATUS) & MSC_STATUS_BUSY) && (timeout != 0))
while ((getreg32(EFM32_MSC_STATUS) & MSC_STATUS_BUSY) &&
(timeout != 0))
{
timeout--;
}
@@ -701,7 +708,8 @@ ssize_t __ramfunc__ up_progmem_eraseblock(size_t block)
/* Disable writing to the MSC */
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 0);
bitband_set_peripheral(EFM32_MSC_WRITECTRL,
_MSC_WRITECTRL_WREN_SHIFT, 0);
if (ret == 0)
{
@@ -731,14 +739,15 @@ ssize_t up_progmem_ispageerased(size_t page)
size_t count;
size_t bwritten = 0;
if (page >= (EFM32_FLASH_NPAGES+EFM32_USERDATA_NPAGES))
if (page >= (EFM32_FLASH_NPAGES + EFM32_USERDATA_NPAGES))
{
return -EFAULT;
}
/* Verify */
for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page);
for (addr = up_progmem_getaddress(page),
count = up_progmem_pagesize(page);
count; count--, addr++)
{
if (getreg8(addr) != 0xff)
@@ -748,10 +757,10 @@ ssize_t up_progmem_ispageerased(size_t page)
}
return bwritten;
}
ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size)
ssize_t __ramfunc__ up_progmem_write(size_t addr,
const void *buf, size_t size)
{
int ret = 0;
int word_count;
@@ -779,18 +788,22 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size)
/* enable writing to the flash */
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 1);
bitband_set_peripheral(EFM32_MSC_WRITECTRL,
_MSC_WRITECTRL_WREN_SHIFT, 1);
/* Convert bytes to words */
num_words = num_bytes >> 2;
/* The following loop splits the data into chunks corresponding to flash pages.
* The address is loaded only once per page, because the hardware automatically
* increments the address internally for each data load inside a page.
/* The following loop splits the data into chunks corresponding to flash
* pages. The address is loaded only once per page, because the hardware
* automatically increments the address internally for each data load
* inside a page.
*/
for (word_count = 0, p_data = (uint32_t *)buf; word_count < num_words; )
for (word_count = 0, p_data = (uint32_t *)buf;
word_count < num_words;
)
{
int page_bytes;
ssize_t page_idx;
@@ -798,7 +811,7 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size)
/* Compute the number of words to write to the current page. */
page_idx = up_progmem_getpage((size_t)address+(word_count << 2));
page_idx = up_progmem_getpage((size_t)address + (word_count << 2));
if (page_idx < 0)
{
ret = -EINVAL;
@@ -813,7 +826,7 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size)
}
page_words = (page_bytes - (((uint32_t) (address + word_count)) & \
(page_bytes-1))) / sizeof(uint32_t);
(page_bytes - 1))) / sizeof(uint32_t);
if (page_words > num_words - word_count)
{
@@ -822,7 +835,8 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size)
flags = enter_critical_section();
/* First we load address. The address is auto-incremented within a page.
/* First we load address.
* The address is auto-incremented within a page.
* Therefore the address phase is only needed once for each page.
*/
@@ -854,7 +868,8 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size)
/* Turn off double word write cycle support. */
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WDOUBLE_SHIFT, 0);
bitband_set_peripheral(EFM32_MSC_WRITECTRL,
_MSC_WRITECTRL_WDOUBLE_SHIFT, 0);
#endif
arch/arm/src/efm32/efm32_gpio.c
+47 -43
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/efm32_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,11 +16,11 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -33,18 +33,18 @@
#include "hardware/efm32_gpio.h"
#include "efm32_gpio.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
#define __GPIO_INPUT (1 << 0) /* Bit 0: GPIO is an input */
#define __GPIO_OUTPUT (1 << 1) /* Bit 1: GPIO is an output */
#define __GPIO_DOUT (1 << 2) /* Bit 2: An input modified with DOUT setting */
#define __GPIO_DRIVE (1 << 3) /* Bit 3: An output with drive selection */
/************************************************************************************
/****************************************************************************
* Private Data
************************************************************************************/
****************************************************************************/
static const uint8_t g_gpiomode[16] =
{
@@ -77,56 +77,56 @@ static const uint8_t g_gpiomode[16] =
* by DRIVEMODE */
};
/************************************************************************************
/****************************************************************************
* Private Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: efm32_getport
*
* Description:
* Extract the encoded port number
*
************************************************************************************/
****************************************************************************/
static inline uint8_t efm32_getport(gpio_pinset_t cfgset)
{
return (uint8_t)((cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
}
/************************************************************************************
/****************************************************************************
* Name: efm32_getpin
*
* Description:
* Extract the encoded pin number
*
************************************************************************************/
****************************************************************************/
static inline uint8_t efm32_getpin(gpio_pinset_t cfgset)
{
return (uint8_t)((cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
}
/************************************************************************************
/****************************************************************************
* Name: efm32_getmode
*
* Description:
* Extract the encoded pin mode
*
************************************************************************************/
****************************************************************************/
static inline uint8_t efm32_getmode(gpio_pinset_t cfgset)
{
return (uint8_t)((cfgset & GPIO_MODE_MASK) >> GPIO_MODE_SHIFT);
}
/************************************************************************************
/****************************************************************************
* Name: efm32_getdrive
*
* Description:
* Extract the output drive strength from the encoded configuration
*
************************************************************************************/
****************************************************************************/
static uint8_t efm32_getdrive(uint8_t mode, gpio_pinset_t cfgset)
{
@@ -140,22 +140,24 @@ static uint8_t efm32_getdrive(uint8_t mode, gpio_pinset_t cfgset)
}
}
/************************************************************************************
/****************************************************************************
* Name: efm32_setdrive
*
* Description:
* Set the GPIO output drive strength
*
************************************************************************************/
****************************************************************************/
static inline void efm32_setdrive(uintptr_t base, uint8_t pin, uint8_t drive)
{
/* Select drive mode for all pins on port configured with alternate drive
* strength.
*
* REVISIT: Is there any sane way to manage this for multiple pins in the port
* REVISIT:
* Is there any sane way to manage this for multiple pins in the port
* with different drive values?
*/
if (drive != _GPIO_DRIVE_STANDARD)
{
putreg32((uint32_t)drive << _GPIO_P_CTRL_DRIVEMODE_SHIFT,
@@ -163,13 +165,13 @@ static inline void efm32_setdrive(uintptr_t base, uint8_t pin, uint8_t drive)
}
}
/************************************************************************************
/****************************************************************************
* Name: efm32_getdout
*
* Description:
* Extract the encoded port number
*
************************************************************************************/
****************************************************************************/
static inline bool efm32_getdout(uint8_t mode, gpio_pinset_t cfgset)
{
@@ -187,13 +189,13 @@ static inline bool efm32_getdout(uint8_t mode, gpio_pinset_t cfgset)
}
}
/************************************************************************************
/****************************************************************************
* Name: efm32_setdout
*
* Description:
* Set the GPIO output data value
*
************************************************************************************/
****************************************************************************/
static inline void efm32_setdout(uintptr_t base, uint8_t pin, bool dout)
{
@@ -209,26 +211,27 @@ static inline void efm32_setdout(uintptr_t base, uint8_t pin, bool dout)
}
}
/************************************************************************************
/****************************************************************************
* Name: efm32_getdin
*
* Description:
* Get the GPIO input value
*
************************************************************************************/
****************************************************************************/
static inline bool efm32_getdin(uintptr_t base, uint8_t pin)
{
return ((getreg32(base + EFM32_GPIO_Pn_DIN_OFFSET) & ((uint32_t)1 << pin)) != 0);
return ((getreg32(base + EFM32_GPIO_Pn_DIN_OFFSET) &
((uint32_t)1 << pin)) != 0);
}
/************************************************************************************
/****************************************************************************
* Name: efm32_setmode
*
* Description:
* Set the GPIO mode
*
************************************************************************************/
****************************************************************************/
static inline void efm32_setmode(uintptr_t base, uint8_t pin, uint8_t mode)
{
@@ -257,17 +260,17 @@ static inline void efm32_setmode(uintptr_t base, uint8_t pin, uint8_t mode)
putreg32(regval, regaddr);
}
/************************************************************************************
/****************************************************************************
* Public Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: efm32_configgpio
*
* Description:
* Configure a PIO pin based on bit-encoded description of the pin.
*
************************************************************************************/
****************************************************************************/
int efm32_configgpio(gpio_pinset_t cfgset)
{
@@ -301,13 +304,13 @@ int efm32_configgpio(gpio_pinset_t cfgset)
return OK;
}
/************************************************************************************
/****************************************************************************
* Name: efm32_unconfiggpio
*
* Description:
* unConfigure a PIO pin based on bit-encoded description of the pin.
*
************************************************************************************/
****************************************************************************/
int efm32_unconfiggpio(gpio_pinset_t cfgset)
{
@@ -317,13 +320,13 @@ int efm32_unconfiggpio(gpio_pinset_t cfgset)
return efm32_configgpio(cfgset);
}
/************************************************************************************
/****************************************************************************
* Name: efm32_gpiowrite
*
* Description:
* Write one or zero to the selected PIO pin
*
************************************************************************************/
****************************************************************************/
void efm32_gpiowrite(gpio_pinset_t pinset, bool value)
{
@@ -342,13 +345,13 @@ void efm32_gpiowrite(gpio_pinset_t pinset, bool value)
efm32_setdout(base, pin, value);
}
/************************************************************************************
/****************************************************************************
* Name: efm32_gpioread
*
* Description:
* Read one or zero from the selected PIO pin
*
************************************************************************************/
****************************************************************************/
bool efm32_gpioread(gpio_pinset_t pinset)
{
@@ -367,13 +370,14 @@ bool efm32_gpioread(gpio_pinset_t pinset)
return efm32_getdin(base, pin);
}
/************************************************************************************
/****************************************************************************
* Function: efm32_dumpgpio
*
* Description:
* Dump all PIO registers associated with the base address of the provided pinset.
* Dump all PIO registers associated with the base address of the provided
* pinset.
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_DEBUG_GPIO_INFO
int efm32_dumpgpio(uint32_t pinset, const char *msg)
arch/arm/src/efm32/efm32_gpio.h
+43 -39
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/efm32_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,28 +16,29 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_EFM32_GPIO_H
#define __ARCH_ARM_SRC_EFM32_EFM32_GPIO_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
****************************************************************************/
/* Configuration ************************************************************/
#define EFM32_NGPIO 5 /* (5) GPIOA-F */
/* Bit-encoded input to efm32_configgpio() *******************************************/
/* Bit-encoded input to efm32_configgpio() **********************************/
/* 16-bit Encoding:
*
@@ -106,7 +107,8 @@
# define GPIO_OUTPUT_WIREDAND_DRIVE_PULLUP_FILTER \
(15 << GPIO_MODE_SHIFT)
/* If the pin is an PIO output, then this identifies the initial output value:
/* If the pin is an PIO output, then this identifies the initial output
* value:
*
* .... V... .... ....
*/
@@ -182,23 +184,23 @@
# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/* Must be big enough to hold the 16-bit encoding */
typedef uint16_t gpio_pinset_t;
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -209,17 +211,18 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: efm32_gpioirqinitialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for PIO pins.
* Initialize logic to support a second level of interrupt decoding for PIO
* pins.
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_EFM32_GPIO_IRQ
void efm32_gpioirqinitialize(void);
@@ -227,53 +230,53 @@ void efm32_gpioirqinitialize(void);
# define efm32_gpioirqinitialize()
#endif
/************************************************************************************
/****************************************************************************
* Name: efm32_configgpio
*
* Description:
* Configure a PIO pin based on bit-encoded description of the pin.
*
************************************************************************************/
****************************************************************************/
int efm32_configgpio(gpio_pinset_t cfgset);
/************************************************************************************
/****************************************************************************
* Name: efm32_unconfiggpio
*
* Description:
* UnConfigure a PIO pin based on bit-encoded description of the pin.
*
************************************************************************************/
****************************************************************************/
int efm32_unconfiggpio(gpio_pinset_t cfgset);
/************************************************************************************
/****************************************************************************
* Name: efm32_gpiowrite
*
* Description:
* Write one or zero to the selected PIO pin
*
************************************************************************************/
****************************************************************************/
void efm32_gpiowrite(gpio_pinset_t pinset, bool value);
/************************************************************************************
/****************************************************************************
* Name: efm32_gpioread
*
* Description:
* Read one or zero from the selected PIO pin
*
************************************************************************************/
****************************************************************************/
bool efm32_gpioread(gpio_pinset_t pinset);
/************************************************************************************
/****************************************************************************
* Name: efm32_gpioirq
*
* Description:
* Configure an interrupt for the specified PIO pin.
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_EFM32_GPIO_IRQ
void efm32_gpioirq(gpio_pinset_t pinset);
@@ -281,13 +284,13 @@ void efm32_gpioirq(gpio_pinset_t pinset);
# define efm32_gpioirq(pinset)
#endif
/************************************************************************************
/****************************************************************************
* Name: efm32_gpioirqenable
*
* Description:
* Enable the interrupt for specified PIO IRQ
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_EFM32_GPIO_IRQ
void efm32_gpioirqenable(int irq);
@@ -295,13 +298,13 @@ void efm32_gpioirqenable(int irq);
# define efm32_gpioirqenable(irq)
#endif
/************************************************************************************
/****************************************************************************
* Name: efm32_gpioirqdisable
*
* Description:
* Disable the interrupt for specified PIO IRQ
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_EFM32_GPIO_IRQ
void efm32_gpioirqdisable(int irq);
@@ -309,13 +312,13 @@ void efm32_gpioirqdisable(int irq);
# define efm32_gpioirqdisable(irq)
#endif
/************************************************************************************
/****************************************************************************
* Name: efm32_gpioirqclear
*
* Description:
* clear the interrupt for specified PIO IRQ
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_EFM32_GPIO_IRQ
void efm32_gpioirqclear(int irq);
@@ -323,13 +326,14 @@ void efm32_gpioirqclear(int irq);
# define efm32_gpioirqclear(irq)
#endif
/************************************************************************************
/****************************************************************************
* Function: efm32_dumpgpio
*
* Description:
* Dump all PIO registers associated with the base address of the provided pinset.
* Dump all PIO registers associated with the base address of the provided
* pinset.
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_DEBUG_GPIO_INFO
int efm32_dumpgpio(uint32_t pinset, const char *msg);
arch/arm/src/efm32/efm32_gpioirq.c
+35 -33
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/efm32_gpioirq.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,11 +16,11 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -38,47 +38,47 @@
#ifdef CONFIG_EFM32_GPIO_IRQ
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Private Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: efm32_getport
*
* Description:
* Extract the encoded port number
*
************************************************************************************/
****************************************************************************/
static inline uint8_t efm32_getport(gpio_pinset_t cfgset)
{
return (uint8_t)((cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
}
/************************************************************************************
/****************************************************************************
* Name: efm32_getpin
*
* Description:
* Extract the encoded pin number
*
************************************************************************************/
****************************************************************************/
static inline uint8_t efm32_getpin(gpio_pinset_t cfgset)
{
return (uint8_t)((cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
}
/************************************************************************************
/****************************************************************************
* Name: efm32_gpio_interrupt
*
* Description:
* Common GPIO interrupt handling logic
*
************************************************************************************/
****************************************************************************/
static int efm32_gpio_interrupt(uint32_t mask, void *context)
{
@@ -110,47 +110,50 @@ static int efm32_gpio_interrupt(uint32_t mask, void *context)
return OK;
}
/************************************************************************************
/****************************************************************************
* Name: efm32_even_interrupt
*
* Description:
* Even GPIO interrupt handling logic
*
************************************************************************************/
****************************************************************************/
static int efm32_even_interrupt(int irq, void *context, FAR void *arg)
{
return efm32_gpio_interrupt(0x00005555, context);
}
/************************************************************************************
/****************************************************************************
* Name: efm32_even_interrupt
*
* Description:
* Even GPIO interrupt handling logic
*
************************************************************************************/
****************************************************************************/
static int efm32_odd_interrupt(int irq, void *context, FAR void *arg)
{
return efm32_gpio_interrupt(0x0000aaaa, context);
}
/************************************************************************************
/****************************************************************************
* Public Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: efm32_gpioirqinitialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for PIO pins.
* Initialize logic to support a second level of interrupt decoding for PIO
* pins.
*
************************************************************************************/
****************************************************************************/
void efm32_gpioirqinitialize(void)
{
/* Initialize GPIO interrupt registers, disabling GPIO interrupts at the source */
/* Initialize GPIO interrupt registers, disabling GPIO interrupts at the
* source
*/
putreg32(0, EFM32_GPIO_EXTIRISE);
putreg32(0, EFM32_GPIO_EXTIFALL);
@@ -167,13 +170,13 @@ void efm32_gpioirqinitialize(void)
up_enable_irq(EFM32_IRQ_GPIO_EVEN);
}
/************************************************************************************
/****************************************************************************
* Name: efm32_gpioirq
*
* Description:
* Configure an interrupt for the specified PIO pin.
*
************************************************************************************/
****************************************************************************/
void efm32_gpioirq(gpio_pinset_t pinset)
{
@@ -246,17 +249,16 @@ void efm32_gpioirq(gpio_pinset_t pinset)
leave_critical_section(flags);
}
/************************************************************************************
/****************************************************************************
* Name: efm32_gpioirqenable
*
* Description:
* Enable the interrupt for specified PIO IRQ
*
************************************************************************************/
****************************************************************************/
void efm32_gpioirqenable(int irq)
{
if (irq >= EFM32_IRQ_EXTI0 && irq <= EFM32_IRQ_EXTI15)
{
/* Enable the interrupt associated with the pin */
@@ -277,13 +279,13 @@ void efm32_gpioirqenable(int irq)
}
}
/************************************************************************************
/****************************************************************************
* Name: efm32_gpioirqdisable
*
* Description:
* Disable the interrupt for specified PIO IRQ
*
************************************************************************************/
****************************************************************************/
void efm32_gpioirqdisable(int irq)
{
@@ -308,13 +310,13 @@ void efm32_gpioirqdisable(int irq)
}
}
/************************************************************************************
/****************************************************************************
* Name: efm32_gpioirqclear
*
* Description:
* Disable the interrupt for specified PIO IRQ
*
************************************************************************************/
****************************************************************************/
void efm32_gpioirqclear(int irq)
{
arch/arm/src/efm32/efm32_lowputc.c
+18 -10
View File
@@ -181,7 +181,8 @@ static void efm32_uart_setbaud(uintptr_t base, uint32_t baud)
* CLKDIV = (256 * fHFPERCLK) / (oversample * baud) - 256
*/
clkdiv = ((uint64_t)BOARD_HFPERCLK_FREQUENCY << 8) / ((uint64_t)baud * oversample);
clkdiv = ((uint64_t)BOARD_HFPERCLK_FREQUENCY << 8) /
((uint64_t)baud * oversample);
if (clkdiv > 256)
{
clkdiv -= 256;
@@ -490,7 +491,8 @@ void efm32_lowputc(uint32_t ch)
* buffer is half-full or empty.
*/
while ((getreg32(CONSOLE_BASE + EFM32_USART_STATUS_OFFSET) & USART_STATUS_TXBL) == 0);
while ((getreg32(CONSOLE_BASE + EFM32_USART_STATUS_OFFSET) &
USART_STATUS_TXBL) == 0);
/* Then send the character */
@@ -505,7 +507,8 @@ void efm32_lowputc(uint32_t ch)
* buffer is half-full or empty.
*/
while ((getreg32(CONSOLE_BASE + EFM32_LEUART_STATUS_OFFSET) & LEUART_STATUS_TXBL) == 0);
while ((getreg32(CONSOLE_BASE + EFM32_LEUART_STATUS_OFFSET) &
LEUART_STATUS_TXBL) == 0);
/* Then send the character */
@@ -628,7 +631,8 @@ void efm32_uartconfigure(uintptr_t base, uint32_t baud, unsigned int parity,
/* Enable the U[S]ART */
putreg32(USART_CMD_RXEN | USART_CMD_TXEN, base + EFM32_USART_CMD_OFFSET);
putreg32(USART_CMD_RXEN | USART_CMD_TXEN,
base + EFM32_USART_CMD_OFFSET);
}
#endif
@@ -641,7 +645,8 @@ void efm32_uartconfigure(uintptr_t base, uint32_t baud, unsigned int parity,
****************************************************************************/
#ifdef HAVE_LEUART_DEVICE
void efm32_leuartconfigure(uintptr_t base, uint32_t baud, unsigned int parity,
void efm32_leuartconfigure(uintptr_t base,
uint32_t baud, unsigned int parity,
unsigned int nbits, bool stop2)
{
uint32_t regval = 0;
@@ -682,7 +687,6 @@ void efm32_leuartconfigure(uintptr_t base, uint32_t baud, unsigned int parity,
case 2:
regval |= LEUART_CTRL_PARITY_EVEN;
break;
}
/* Configure stop bits */
@@ -704,7 +708,8 @@ void efm32_leuartconfigure(uintptr_t base, uint32_t baud, unsigned int parity,
/* Enable the LEUART */
putreg32(LEUART_CMD_RXEN | LEUART_CMD_TXEN, base + EFM32_LEUART_CMD_OFFSET);
putreg32(LEUART_CMD_RXEN | LEUART_CMD_TXEN,
base + EFM32_LEUART_CMD_OFFSET);
}
#endif
@@ -759,11 +764,14 @@ void efm32_leuart_reset(uintptr_t base)
base + EFM32_LEUART_CMD_OFFSET);
putreg32(_LEUART_CTRL_RESETVALUE, base + EFM32_LEUART_CTRL_OFFSET);
putreg32(_LEUART_CLKDIV_RESETVALUE, base + EFM32_LEUART_CLKDIV_OFFSET);
putreg32(_LEUART_STARTFRAME_RESETVALUE, base + EFM32_LEUART_STARTFRAME_OFFSET);
putreg32(_LEUART_SIGFRAME_RESETVALUE, base + EFM32_LEUART_SIGFRAME_OFFSET);
putreg32(_LEUART_STARTFRAME_RESETVALUE,
base + EFM32_LEUART_STARTFRAME_OFFSET);
putreg32(_LEUART_SIGFRAME_RESETVALUE,
base + EFM32_LEUART_SIGFRAME_OFFSET);
putreg32(_LEUART_IEN_RESETVALUE, base + EFM32_LEUART_IEN_OFFSET);
putreg32(_LEUART_IFC_MASK, base + EFM32_LEUART_IFC_OFFSET);
putreg32(_LEUART_PULSECTRL_RESETVALUE, base + EFM32_LEUART_PULSECTRL_OFFSET);
putreg32(_LEUART_PULSECTRL_RESETVALUE,
base + EFM32_LEUART_PULSECTRL_OFFSET);
#if defined(EFM32_LEUART_INPUT_OFFSET)
putreg32(_LEUART_INPUT_RESETVALUE, base + EFM32_LEUART_INPUT_OFFSET);
#endif
arch/arm/src/efm32/efm32_lowputc.h
+3 -2
View File
@@ -32,7 +32,7 @@
#include "efm32_config.h"
/****************************************************************************
* Public Functions
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
@@ -82,7 +82,8 @@ void efm32_uartconfigure(uintptr_t base, uint32_t baud, unsigned int parity,
****************************************************************************/
#ifdef HAVE_LEUART_DEVICE
void efm32_leuartconfigure(uintptr_t base, uint32_t baud, unsigned int parity,
void efm32_leuartconfigure(uintptr_t base, uint32_t baud,
unsigned int parity,
unsigned int nbits, bool stop2);
#endif
arch/arm/src/efm32/efm32_pm.h
+4 -4
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/efm32_pm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,7 +16,7 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_EFM32_PM_H
#define __ARCH_ARM_SRC_EFM32_EFM32_PM_H
@@ -119,8 +119,8 @@ int efm32_pmstandby(void);
* sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is
* executed, the MCU enters Sleep mode as soon as it
* exits the lowest priority ISR.
* - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep mode
* as soon as WFI or WFE instruction is executed.
* - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep
* mode as soon as WFI or WFE instruction is executed.
* Returned Value:
* Zero means that the STOP was successfully entered and the system has
* been re-awakened. The internal voltage regulator is back to its
arch/arm/src/efm32/efm32_pwm.c
+17 -6
View File
@@ -71,7 +71,9 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* PWM/Timer Definitions ****************************************************/
/* The following definitions are used to identify the various time types */
/* Debug ********************************************************************/
@@ -85,6 +87,7 @@
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure represents the state of one PWM timer */
struct efm32_pwmtimer_s
@@ -111,6 +114,7 @@ struct efm32_pwmtimer_s
/****************************************************************************
* Static Function Prototypes
****************************************************************************/
/* Register access */
static uint32_t pwm_getreg(struct efm32_pwmtimer_s *priv, int offset);
@@ -159,7 +163,10 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev,
/****************************************************************************
* Private Data
****************************************************************************/
/* This is the list of lower half PWM driver methods used by the upper half driver */
/* This is the list of lower half PWM driver methods used by the upper half
* driver
*/
static const struct pwm_ops_s g_pwmops =
{
@@ -273,7 +280,8 @@ static uint32_t pwm_getreg(struct efm32_pwmtimer_s *priv, int offset)
*
****************************************************************************/
static void pwm_putreg(struct efm32_pwmtimer_s *priv, int offset, uint32_t value)
static void pwm_putreg(struct efm32_pwmtimer_s *priv,
int offset, uint32_t value)
{
putreg32(value, priv->base + offset);
}
@@ -412,7 +420,8 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
regval = (info->duty * pwm_getreg(priv, EFM32_TIMER_TOP_OFFSET)) >> 16;
pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CCV_OFFSET, regval);
//pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CCVB_OFFSET, regval);
/* pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CCVB_OFFSET, regval); */
regval = (_TIMER_CC_CTRL_MODE_PWM << _TIMER_CC_CTRL_MODE_SHIFT) | \
(_TIMER_CC_CTRL_CMOA_CLEAR << _TIMER_CC_CTRL_CMOA_SHIFT) | \
@@ -511,7 +520,9 @@ static int pwm_interrupt(int irq, void *context, FAR void *arg)
pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint32_t)priv->curr - 1);
}
/* Now all of the time critical stuff is done so we can do some debug output */
/* Now all of the time critical stuff is done so we can do some debug
* output
*/
pwminfo("Update interrupt SR: %04x prev: %d curr: %d count: %d\n",
regval, priv->prev, priv->curr, priv->count);
@@ -574,7 +585,6 @@ static uint8_t pwm_pulsecount(uint32_t count)
}
#endif
/****************************************************************************
* Name: pwm_setup
*
@@ -771,7 +781,8 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
*
****************************************************************************/
static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg)
static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev,
int cmd, unsigned long arg)
{
#ifdef CONFIG_DEBUG_PWM_INFO
FAR struct efm32_pwmtimer_s *priv = (FAR struct efm32_pwmtimer_s *)dev;
arch/arm/src/efm32/efm32_pwm.h
+19 -17
View File
@@ -53,12 +53,14 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration **************************************************************/
/* Configuration ************************************************************/
/* Timer devices may be used for different purposes. One special purpose is
* to generate modulated outputs for such things as motor control.
* If CONFIG_EFM32_TIMERn is defined then the CONFIG_EFM32_TIMERn_PWM must also
* be defined to indicate that timer "n" is intended to be used for pulsed
* output signal generation.
* If CONFIG_EFM32_TIMERn is defined then the CONFIG_EFM32_TIMERn_PWM must
* also be defined to indicate that timer "n" is intended to be used for
* pulsed output signal generation.
*/
#ifndef CONFIG_EFM32_TIMER0
@@ -84,8 +86,8 @@
#include <arch/board/board.h>
#include "hardware/efm32_timer.h"
/* For each timer that is enabled for PWM usage, we need the following additional
* configuration settings:
/* For each timer that is enabled for PWM usage, we need the following
* additional configuration settings:
*
* CONFIG_EFM32_TIMERx_CHANNEL - Specifies the timer output channel {0,1,3}
* BOARD_PWM_TIMERx_PINCFG - Specifies the timer output pin configuration.
@@ -94,21 +96,21 @@
* BOARD_PWM_TIMERx_PINLOC - Specifies the timer output pin location.
* example : _TIMER_ROUTE_LOCATION_LOC4
*
* BOARD_PWM_TIMERx_CLKIN - Specifies the timer input clock frequency (in Hz).
* example : 48e6 for 48MHz
* BOARD_PWM_TIMERx_CLKIN - Specifies the timer input clock frequency
* (in Hz). example : 48e6 for 48MHz
*
* NOTE: The EFM32 timers are each capable of generating different signals on
* each of the four channels with different duty cycles. That capability is
* not supported by this driver: Only one output channel per timer.
*/
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
@@ -121,11 +123,11 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: efm32_pwminitialize
*
* Description:
@@ -140,7 +142,7 @@ extern "C"
* On success, a pointer to the EFM32 lower half PWM driver is returned.
* NULL is returned on any failure.
*
************************************************************************************/
****************************************************************************/
FAR struct pwm_lowerhalf_s *efm32_pwminitialize(int timer);
arch/arm/src/efm32/efm32_rmu.c
+31 -29
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/efm32_rmu.c
*
* Copyright (C) 2015 Pierre-Noel Bouteville. All rights reserved.
@@ -31,11 +31,11 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -55,13 +55,13 @@
#include "efm32_rmu.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Private Types
************************************************************************************/
****************************************************************************/
#if defined(CONFIG_EFM32_RMU_DEBUG) && defined(CONFIG_DEBUG_WARN)
typedef struct
@@ -72,9 +72,9 @@ typedef struct
} efm32_reset_cause_list_t;
#endif
/************************************************************************************
/****************************************************************************
* Private Data
************************************************************************************/
****************************************************************************/
#if defined(CONFIG_EFM32_RMU_DEBUG) && defined(CONFIG_DEBUG_WARN)
static efm32_reset_cause_list_t efm32_reset_cause_list[] =
@@ -91,12 +91,12 @@ static efm32_reset_cause_list_t efm32_reset_cause_list[] =
},
{
0x0004, /* 0bXXXX XXXX XXX0 0100 */
0x001F, /* 0bXXXX XXXX XXX1 1111 */
0x001f, /* 0bXXXX XXXX XXX1 1111 */
"A Brown-out has been detected on the regulated power."
},
{
0x0008, /* 0bXXXX XXXX XXXX 1X00 */
0x000B, /* 0bXXXX XXXX XXXX 1X11 */
0x000b, /* 0bXXXX XXXX XXXX 1X11 */
"An external reset has been applied."
},
{
@@ -106,12 +106,12 @@ static efm32_reset_cause_list_t efm32_reset_cause_list[] =
},
{
0x0020, /* 0bXXXX X000 0010 0000 */
0x07FF, /* 0bXXXX X111 1111 1111 */
0x07ff, /* 0bXXXX X111 1111 1111 */
"A lockup reset has occurred."
},
{
0x0040, /* 0bXXXX X000 01X0 0000 */
0x07DF, /* 0bXXXX X111 11X1 1111 */
0x07df, /* 0bXXXX X111 11X1 1111 */
"A system request reset has occurred."
},
{
@@ -122,16 +122,16 @@ static efm32_reset_cause_list_t efm32_reset_cause_list[] =
{
0x0180, /* 0bXXXX X001 1XX0 0XX0 */
0x0799, /* 0bXXXX X111 1XX1 1XX1 */
"The system has woken up from EM4 on an EM4 wakeup reset request from pin."
"The system woke up from EM4 on an EM4 wakeup reset request from pin."
},
{
0x0200, /* 0bXXXX X01X XXX0 0000 */
0x061F, /* 0bXXXX X11X XXX1 1111 */
0x061f, /* 0bXXXX X11X XXX1 1111 */
"A Brown-out has been detected on Analog Power Domain 0 (AVDD0)."
},
{
0x0400, /* 0bXXXX X10X XXX0 0000 */
0x061F, /* 0bXXXX X11X XXX1 1111 */
0x061f, /* 0bXXXX X11X XXX1 1111 */
"A Brown-out has been detected on Analog Power Domain 1 (AVDD1)."
},
{
@@ -162,23 +162,23 @@ static efm32_reset_cause_list_t efm32_reset_cause_list[] =
};
#endif
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/* Variable old last reset cause of cpu. */
uint32_t g_efm32_rstcause;
/************************************************************************************
/****************************************************************************
* Private Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: efm32_reset_cause_list_str
*
* Description:
@@ -189,12 +189,13 @@ uint32_t g_efm32_rstcause;
* idx: Use to keep in maind reset cause decoding position.
* set *idx to zero before first call.
*
************************************************************************************/
****************************************************************************/
#if defined(CONFIG_EFM32_RMU_DEBUG) && defined(CONFIG_DEBUG_WARN)
const char *efm32_reset_cause_list_str(uint32_t reg, unsigned int *idx)
{
int len = sizeof(efm32_reset_cause_list)/sizeof(efm32_reset_cause_list[0]);
int len = sizeof(efm32_reset_cause_list) /
sizeof(efm32_reset_cause_list[0]);
efm32_reset_cause_list_t *ptr = NULL;
do
@@ -218,13 +219,14 @@ const char *efm32_reset_cause_list_str(uint32_t reg, unsigned int *idx)
}
#endif
/************************************************************************************
/****************************************************************************
* Name: efm32_rmu_initialize
*
* Description:
* Store reset cause into g_efm32_rstcause then clear reset cause register.
* Store reset cause into g_efm32_rstcause then clear reset cause
* register.
*
************************************************************************************/
****************************************************************************/
void efm32_rmu_initialize(void)
{
arch/arm/src/efm32/efm32_rmu.h
+9 -6
View File
@@ -48,6 +48,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#ifndef CONFIG_DEBUG_ERROR
@@ -73,18 +74,20 @@ extern uint32_t g_efm32_rstcause;
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: efm32_rmu_initialize
*
* Description:
* Store reset cause into g_efm32_rstcause then clear reset cause register.
* Store reset cause into g_efm32_rstcause then clear reset cause
* register.
*
************************************************************************************/
****************************************************************************/
void efm32_rmu_initialize(void);
const char* efm32_reset_cause_list_str(uint32_t reg, unsigned int *idx);
const char *efm32_reset_cause_list_str(uint32_t reg, unsigned int *idx);
/************************************************************************************
/****************************************************************************
* Name: efm32_reset_cause_list_str
*
* Description:
@@ -95,7 +98,7 @@ const char* efm32_reset_cause_list_str(uint32_t reg, unsigned int *idx);
* idx: Use to keep in maind reset cause decoding position.
* set *idx to zero before first call.
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_EFM32_RMU_DEBUG
const char *efm32_reset_cause_list_str(uint32_t reg, unsigned int *idx);
arch/arm/src/efm32/efm32_rtc.h
+4 -4
View File
@@ -39,7 +39,7 @@ typedef void (*alarmcb_t)(void);
* Pre-processor Definitions
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: efm32_rtc_setalarm
*
* Description:
@@ -52,14 +52,14 @@ typedef void (*alarmcb_t)(void);
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
struct timespec;
int efm32_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback);
#endif
/************************************************************************************
/****************************************************************************
* Name: efm32_rtc_cancelalarm
*
* Description:
@@ -71,7 +71,7 @@ int efm32_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback);
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
int efm32_rtc_cancelalarm(void);
arch/arm/src/efm32/efm32_rtc_burtc.c
+56 -50
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/efm32_rtc_burtc.c
*
* Copyright (C) 2015 Pierre-Noel Bouteville. All rights reserved.
@@ -31,11 +31,11 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -60,10 +60,11 @@
#include "efm32_bitband.h"
#include "clock/clock.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
****************************************************************************/
/* Configuration ************************************************************/
#ifdef CONFIG_RTC_HIRES
# ifndef CONFIG_RTC_FREQUENCY
@@ -130,9 +131,9 @@
#define __CNT_CARRY_REG EFM32_BURTC_RET_REG(0)
#define __CNT_ZERO_REG EFM32_BURTC_RET_REG(1)
/************************************************************************************
/****************************************************************************
* Private Data
************************************************************************************/
****************************************************************************/
/* Callback to use when the alarm expires */
@@ -140,9 +141,9 @@
static alarmcb_t g_alarmcb;
#endif
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/* Variable determines the state of the LSE oscillator.
* Possible errors:
@@ -156,11 +157,11 @@ bool g_efm32_burtc_reseted = false;
volatile bool g_rtc_enabled = false;
/************************************************************************************
/****************************************************************************
* Private Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: efm32_rtc_interrupt
*
* Description:
@@ -173,7 +174,7 @@ volatile bool g_rtc_enabled = false;
* Returned Value:
* Zero (OK) on success; A negated errno value on failure.
*
************************************************************************************/
****************************************************************************/
static int efm32_rtc_burtc_interrupt(int irq, void *context, FAR void *arg)
{
@@ -210,12 +211,13 @@ static int efm32_rtc_burtc_interrupt(int irq, void *context, FAR void *arg)
/* Clear pending flags, leave RSF high */
putreg32(BURTC_IFC_OF | BURTC_IFC_COMP0 | BURTC_IFC_LFXOFAIL, EFM32_BURTC_IFC);
putreg32(BURTC_IFC_OF | BURTC_IFC_COMP0 |
BURTC_IFC_LFXOFAIL, EFM32_BURTC_IFC);
return 0;
}
/************************************************************************************
/****************************************************************************
* Name: efm32_burtc_init
*
* Description:
@@ -225,7 +227,7 @@ static int efm32_rtc_burtc_interrupt(int irq, void *context, FAR void *arg)
* Note
* efm32_rmu_initialize should be called one since boot.
*
************************************************************************************/
****************************************************************************/
static void efm32_rtc_burtc_init(void)
{
@@ -268,9 +270,11 @@ static void efm32_rtc_burtc_init(void)
/* Restore all not set BURTC registers to default value */
// putreg32(_BURTC_LPMODE_RESETVALUE, EFM32_BURTC_LPMODE);
// putreg32(_BURTC_LFXOFDET_RESETVALUE, EFM32_BURTC_LFXOFDET);
// putreg32(_BURTC_COMP0_RESETVALUE, EFM32_BURTC_COMP0);
/* putreg32(_BURTC_LPMODE_RESETVALUE, EFM32_BURTC_LPMODE); */
/* putreg32(_BURTC_LFXOFDET_RESETVALUE, EFM32_BURTC_LFXOFDET); */
/* putreg32(_BURTC_COMP0_RESETVALUE, EFM32_BURTC_COMP0); */
/* New configuration */
@@ -284,7 +288,7 @@ static void efm32_rtc_burtc_init(void)
/* Clear interrupts */
putreg32(0xFFFFFFFF, EFM32_BURTC_IFC);
putreg32(0xffffffff, EFM32_BURTC_IFC);
/* Set new configuration */
@@ -348,21 +352,22 @@ static uint64_t efm32_get_burtc_tick(void)
val = (uint64_t)cnt_carry*__CNT_TOP + cnt + cnt_zero;
rtcinfo("Get Tick carry %u zero %u reg %u\n", cnt_carry, cnt_carry,cnt);
rtcinfo("Get Tick carry %u zero %u reg %u\n",
cnt_carry, cnt_carry, cnt);
return val;
}
/************************************************************************************
/****************************************************************************
* Public Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: up_rtc_initialize
*
* Description:
* Initialize the hardware RTC per the selected configuration. This function is
* called once during the OS initialization sequence
* Initialize the hardware RTC per the selected configuration.
* This function is called once during the OS initialization sequence
*
* Input Parameters:
* None
@@ -370,7 +375,7 @@ static uint64_t efm32_get_burtc_tick(void)
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
************************************************************************************/
****************************************************************************/
int up_rtc_initialize(void)
{
@@ -386,15 +391,15 @@ int up_rtc_initialize(void)
return OK;
}
/************************************************************************************
/****************************************************************************
* Name: up_rtc_time
*
* Description:
* Get the current time in seconds. This is similar to the standard time()
* function. This interface is only required if the low-resolution RTC/counter
* hardware implementation selected. It is only used by the RTOS during
* initialization to set up the system time when CONFIG_RTC is set but neither
* CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set.
* function. This interface is only required if the low-resolution
* RTC/counter hardware implementation selected. It is only used by the
* RTOS during initialization to set up the system time when CONFIG_RTC is
* set but neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set.
*
* Input Parameters:
* None
@@ -402,22 +407,22 @@ int up_rtc_initialize(void)
* Returned Value:
* The current time in seconds
*
************************************************************************************/
****************************************************************************/
#ifndef CONFIG_RTC_HIRES
time_t up_rtc_time(void)
{
return (time_t)efm32_get_burtc_tick()/CONFIG_RTC_FREQUENCY;
return (time_t)efm32_get_burtc_tick() / CONFIG_RTC_FREQUENCY;
}
#endif
/************************************************************************************
/****************************************************************************
* Name: up_rtc_gettime
*
* Description:
* Get the current time from the high resolution RTC clock/counter. This interface
* is only supported by the high-resolution RTC/counter hardware implementation.
* It is used to replace the system timer.
* Get the current time from the high resolution RTC clock/counter.
* This interface is only supported by the high-resolution RTC/counter
* hardware implementation. It is used to replace the system timer.
*
* Input Parameters:
* tp - The location to return the high resolution time value.
@@ -425,7 +430,7 @@ time_t up_rtc_time(void)
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_RTC_HIRES
int up_rtc_gettime(FAR struct timespec *tp)
@@ -437,7 +442,8 @@ int up_rtc_gettime(FAR struct timespec *tp)
/* Then we can save the time in seconds and fractional seconds. */
tp->tv_sec = val / CONFIG_RTC_FREQUENCY;
tp->tv_nsec = (val % CONFIG_RTC_FREQUENCY)*(NSEC_PER_SEC/CONFIG_RTC_FREQUENCY);
tp->tv_nsec = (val % CONFIG_RTC_FREQUENCY) *
(NSEC_PER_SEC / CONFIG_RTC_FREQUENCY);
rtcinfo("Get RTC %u.%09u\n", tp->tv_sec, tp->tv_nsec);
@@ -445,12 +451,12 @@ int up_rtc_gettime(FAR struct timespec *tp)
}
#endif
/************************************************************************************
/****************************************************************************
* Name: up_rtc_settime
*
* Description:
* Set the RTC to the provided time. All RTC implementations must be able to
* set their time based on a standard timespec.
* Set the RTC to the provided time. All RTC implementations must be
* able to set their time based on a standard timespec.
*
* Input Parameters:
* tp - the time to use
@@ -458,7 +464,7 @@ int up_rtc_gettime(FAR struct timespec *tp)
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
************************************************************************************/
****************************************************************************/
int up_rtc_settime(FAR const struct timespec *tp)
{
@@ -499,7 +505,7 @@ int up_rtc_settime(FAR const struct timespec *tp)
return OK;
}
/************************************************************************************
/****************************************************************************
* Name: efm32_rtc_setalarm
*
* Description:
@@ -512,7 +518,7 @@ int up_rtc_settime(FAR const struct timespec *tp)
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
#error "Sorry ! not yet implemented, just copied from STM32"
@@ -557,7 +563,7 @@ int efm32_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback)
}
#endif
/************************************************************************************
/****************************************************************************
* Name: efm32_rtc_cancelalarm
*
* Description:
@@ -569,7 +575,7 @@ int efm32_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback)
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
#error "Sorry ! not yet implemented, just copied from STM32"
arch/arm/src/efm32/efm32_serial.c
-1
View File
@@ -1,4 +1,3 @@
/****************************************************************************
* arch/arm/src/efm32/efm32_serial.c
*
arch/arm/src/efm32/efm32_timerisr.c
+1
View File
@@ -119,6 +119,7 @@ void up_timer_initialize(void)
putreg32(regval, NVIC_SYSH12_15_PRIORITY);
/* Make sure that the SYSTICK clock source is set correctly */
/* Configure SysTick to interrupt at the requested rate */
putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
arch/arm/src/efm32/efm32_usb.h
+25 -23
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/efm32_usb.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_EFM32_OTGFS_H
#define __ARCH_ARM_SRC_EFM32_EFM32_OTGFS_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -33,9 +33,9 @@
#if defined(CONFIG_EFM32_OTGFS)
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#if defined(HAVE_USBHOST_TRACE) && defined(CONFIG_EFM32_OTGFS)
enum usbhost_trace1codes_e
@@ -59,7 +59,7 @@ enum usbhost_trace1codes_e
USBHOST_VTRACE1_GINT_PTXFE, /* OTGFS Handle the periodic TxFIFO empty interrupt */
USBHOST_VTRACE1_GINT_HC, /* OTGFS Handle the host channels interrupt */
USBHOST_VTRACE1_GINT_HPRT, /* OTGFS Handle the host port interrupt */
USBHOST_VTRACE1_GINT_HPRT_POCCHNG, /* OTGFS HPRT: Port Over-Current Change*/
USBHOST_VTRACE1_GINT_HPRT_POCCHNG, /* OTGFS HPRT: Port Over-Current Change */
USBHOST_VTRACE1_GINT_HPRT_PCDET, /* OTGFS HPRT: Port Connect Detect */
USBHOST_VTRACE1_GINT_HPRT_PENCHNG, /* OTGFS HPRT: Port Enable Changed */
USBHOST_VTRACE1_GINT_HPRT_LSDEV, /* OTGFS HPRT: Low Speed Device Connected */
@@ -110,9 +110,9 @@ enum usbhost_trace1codes_e
#endif /* HAVE_USBHOST_TRACE && CONFIG_EFM32_OTGFS */
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
@@ -133,8 +133,8 @@ extern "C"
*
* Input Parameters:
* controller -- If the device supports more than USB host controller, then
* this identifies which controller is being initializeed. Normally, this
* is just zero.
* this identifies which controller is being initializeed.
* Normally, this is just zero.
*
* Returned Value:
* And instance of the USB host interface. The controlling task should
@@ -155,36 +155,38 @@ struct usbhost_connection_s;
FAR struct usbhost_connection_s *efm32_usbhost_initialize(int controller);
#endif
/***********************************************************************************
/****************************************************************************
* Name: efm32_usbhost_vbusdrive
*
* Description:
* Enable/disable driving of VBUS 5V output. This function must be provided be
* each platform that implements the EFM32 OTG FS host interface
* Enable/disable driving of VBUS 5V output. This function must be
* provided be each platform that implements the EFM32 OTG FS host
* interface
*
* Input Parameters:
* iface - For future growth to handle multiple USB host interface. Should be zero.
* iface - For future growth to handle multiple USB host interface.
* Should be zero.
* enable - true: enable VBUS power; false: disable VBUS power
*
* Returned Value:
* None
*
***********************************************************************************/
****************************************************************************/
#ifdef CONFIG_USBHOST
void efm32_usbhost_vbusdrive(int iface, bool enable);
#endif
/************************************************************************************
/****************************************************************************
* Name: efm32_usbsuspend
*
* Description:
* Board logic must provide the efm32_usbsuspend logic if the OTG FS device driver
* is used. This function is called whenever the USB enters or leaves suspend
* mode. This is an opportunity for the board logic to shutdown clocks, power,
* etc. while the USB is suspended.
* Board logic must provide the efm32_usbsuspend logic if the OTG FS
* device driver is used. This function is called whenever the USB enters
* or leaves suspend mode. This is an opportunity for the board logic to
* shutdown clocks, power, etc. while the USB is suspended.
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_USBDEV
struct usbdev_s;
arch/arm/src/efm32/efm32_usbdev.c
+408 -280
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/efm32/hardware/efm32_acmp.h
+14 -13
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_acmp.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ACMP_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ACMP_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,10 +72,11 @@
# warning This is the EFM32GG header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* ACMP Register Offsets *******************************************************************************************************/
****************************************************************************/
/* ACMP Register Offsets ****************************************************/
#define EFM32_ACMP_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_ACMP_INPUTSEL_OFFSET 0x0004 /* Input Selection Register */
@@ -86,7 +87,7 @@
#define EFM32_ACMP_IFC_OFFSET 0x0018 /* Interrupt Flag Clear Register */
#define EFM32_ACMP_ROUTE_OFFSET 0x001c /* I/O Routing Register */
/* ACMP Register Addresses *****************************************************************************************************/
/* ACMP Register Addresses **************************************************/
#define EFM32_ACMP0_CTRL (EFM32_ACMP0_BASE+EFM32_ACMP_CTRL_OFFSET)
#define EFM32_ACMP0_INPUTSEL (EFM32_ACMP0_BASE+EFM32_ACMP_INPUTSEL_OFFSET)
@@ -106,7 +107,7 @@
#define EFM32_ACMP1_IFC (EFM32_ACMP1_BASE+EFM32_ACMP_IFC_OFFSET)
#define EFM32_ACMP1_ROUTE (EFM32_ACMP1_BASE+EFM32_ACMP_ROUTE_OFFSET)
/* ACMP Register Bit Field Definitions *****************************************************************************************/
/* ACMP Register Bit Field Definitions **************************************/
/* Bit fields for ACMP CTRL */
arch/arm/src/efm32/hardware/efm32_adc.h
+14 -13
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_adc.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ADC_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ADC_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,10 +72,11 @@
# warning This is the EFM32GG header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* ADC Register Offsets ********************************************************************************************************/
****************************************************************************/
/* ADC Register Offsets *****************************************************/
#define EFM32_ADC_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_ADC_CMD_OFFSET 0x0004 /* Command Register */
@@ -93,7 +94,7 @@
#define EFM32_ADC_CAL_OFFSET 0x0034 /* Calibration Register */
#define EFM32_ADC_BIASPROG_OFFSET 0x003c /* Bias Programming Register */
/* ADC Register Addresses ******************************************************************************************************/
/* ADC Register Addresses ***************************************************/
#define EFM32_ADC0_CTRL (EFM32_ADC0_BASE+EFM32_ADC_CTRL_OFFSET)
#define EFM32_ADC0_CMD (EFM32_ADC0_BASE+EFM32_ADC_CMD_OFFSET)
@@ -111,7 +112,7 @@
#define EFM32_ADC0_CAL (EFM32_ADC0_BASE+EFM32_ADC_CAL_OFFSET)
#define EFM32_ADC0_BIASPROG (EFM32_ADC0_BASE+EFM32_ADC_BIASPROG_OFFSET)
/* ADC Register Bit Field Definitions ******************************************************************************************/
/* ADC Register Bit Field Definitions ***************************************/
/* Bit fields for ADC CTRL */
arch/arm/src/efm32/hardware/efm32_aes.h
+14 -13
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_aes.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_AES_H_
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_AES_H_
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,10 +72,11 @@
# warning This is the EFM32GG header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* AES Register Offsets ********************************************************************************************************/
****************************************************************************/
/* AES Register Offsets *****************************************************/
#define EFM32_AES_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_AES_CMD_OFFSET 0x0004 /* Command Register */
@@ -95,7 +96,7 @@
#define EFM32_AES_KEYHC_OFFSET 0x0048 /* KEY High Register */
#define EFM32_AES_KEYHD_OFFSET 0x004c /* KEY High Register */
/* AES Register Addresses ******************************************************************************************************/
/* AES Register Addresses ***************************************************/
#define EFM32_AES_CTRL (EFM32_AES_BASE+EFM32_AES_CTRL_OFFSET)
#define EFM32_AES_CMD (EFM32_AES_BASE+EFM32_AES_CMD_OFFSET)
@@ -115,7 +116,7 @@
#define EFM32_AES_KEYHC (EFM32_AES_BASE+EFM32_AES_KEYHC_OFFSET)
#define EFM32_AES_KEYHD (EFM32_AES_BASE+EFM32_AES_KEYHD_OFFSET)
/* AES Register Bit Field Definitions ******************************************************************************************/
/* AES Register Bit Field Definitions ***************************************/
/* Bit fields for AES CTRL */
arch/arm/src/efm32/hardware/efm32_burtc.h
+13 -13
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_burtc.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_BURTC_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_BURTC_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,13 +72,13 @@
# warning This is the EFM32GG header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
****************************************************************************/
#define EFM32_BURTC_NREGS 128 /* Number of backup retention registers */
/* BURTC Register Offsets ******************************************************************************************************/
/* BURTC Register Offsets ***************************************************/
#define EFM32_BURTC_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_BURTC_LPMODE_OFFSET 0x0004 /* Low power mode configuration */
@@ -101,7 +101,7 @@
#define EFM32_BURTC_RET_REG_OFFSET(n) (0x0100 + ((n) << 2))
/* BURTC Register Addresses ****************************************************************************************************/
/* BURTC Register Addresses *************************************************/
#define EFM32_BURTC_CTRL (EFM32_BCKRTC_BASE+EFM32_BURTC_CTRL_OFFSET)
#define EFM32_BURTC_LPMODE (EFM32_BCKRTC_BASE+EFM32_BURTC_LPMODE_OFFSET)
@@ -124,7 +124,7 @@
#define EFM32_BURTC_RET_REG(n) (EFM32_BCKRTC_BASE+EFM32_BURTC_RET_REG_OFFSET(n))
/* BURTC Register Bit Field Definitions ****************************************************************************************/
/* BURTC Register Bit Field Definitions *************************************/
/* Bit fields for BURTC CTRL */
arch/arm/src/efm32/hardware/efm32_calibrate.h
+12 -12
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_calibrate.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_CALIBRATE_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_CALIBRATE_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,17 +72,17 @@
# warning This is the EFM32GG header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
****************************************************************************/
#define CALIBRATE_MAX_REGISTERS 50 /* Max number of address/value pairs for calibration */
#define CALIBRATE ((const struct efm32_calibrate_s *)EFM32_CALIBRATE_BASE)
/*******************************************************************************************************************************
/****************************************************************************
* Public Type Definitions
*******************************************************************************************************************************/
****************************************************************************/
struct efm32_calibrate_s
{
arch/arm/src/efm32/hardware/efm32_cmu.h
+18 -15
View File
@@ -1,4 +1,4 @@
/********************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_cmu.h
*
* (C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_CMU_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_CMU_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,9 +72,10 @@
# warning This is the EFM32GG/G header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
****************************************************************************/
/* Maximum allowed core frequency when using 0 wait states on flash access */
#define CMU_MAX_FREQ_0WS 16000000
@@ -87,13 +88,15 @@
#define CMU_MAX_FREQ_2WS 48000000
/* Maximum frequency that HFLE needs to be enabled on Giant, Leopard and Wonder parts. */
/* Maximum frequency that HFLE needs to be enabled on Giant,
* Leopard and Wonder parts.
*/
#if defined(CONFIG_EFM32_EFM32GG)
# define CMU_MAX_FREQ_HFLE 32000000
#endif
/* CMU Register Offsets ********************************************************************************************************/
/* CMU Register Offsets *****************************************************/
#define EFM32_CMU_CTRL_OFFSET 0x0000 /* CMU Control Register */
#define EFM32_CMU_HFCORECLKDIV_OFFSET 0x0004 /* High Frequency Core Clock Division Register */
@@ -124,7 +127,7 @@
#define EFM32_CMU_ROUTE_OFFSET 0x0080 /* I/O Routing Register */
#define EFM32_CMU_LOCK_OFFSET 0x0084 /* Configuration Lock Register */
/* CMU Register Addresses ******************************************************************************************************/
/* CMU Register Addresses ***************************************************/
#define EFM32_CMU_CTRL (EFM32_CMU_BASE+EFM32_CMU_CTRL_OFFSET)
#define EFM32_CMU_HFCORECLKDIV (EFM32_CMU_BASE+EFM32_CMU_HFCORECLKDIV_OFFSET)
@@ -155,7 +158,7 @@
#define EFM32_CMU_ROUTE (EFM32_CMU_BASE+EFM32_CMU_ROUTE_OFFSET)
#define EFM32_CMU_LOCK (EFM32_CMU_BASE+EFM32_CMU_LOCK_OFFSET)
/* CMU Register Bit Definitions ************************************************************************************************/
/* CMU Register Bit Definitions *********************************************/
/* Bit fields for CMU CTRL */
@@ -1022,7 +1025,7 @@
# define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2) /* Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
# define CMU_HFCORECLKEN0_EBI (0x1UL << 3) /* External Bus Interface Clock Enable */
# define _CMU_HFCORECLKEN0_EBI_SHIFT 3 /* Shift value for CMU_EBI */
# define _CMU_HFCORECLKEN0_EBI_MASK 0x8UL /* Bit mask for CMU_EBI */
# define _CMU_HFCORECLKEN0_EBI_MASK 0x8UL /* Bit mask for CMU_EBI */
# define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /* Mode DEFAULT for CMU_HFCORECLKEN0 */
# define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 3) /* Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
#elif defined(CONFIG_EFM32_EFM32GG)
arch/arm/src/efm32/hardware/efm32_dac.h
+14 -13
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_dac.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DAC_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DAC_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,10 +72,11 @@
# warning This is the EFM32GG header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* DAC Register Offsets ********************************************************************************************************/
****************************************************************************/
/* DAC Register Offsets *****************************************************/
#define EFM32_DAC_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_DAC_STATUS_OFFSET 0x0004 /* Status Register */
@@ -96,7 +97,7 @@
#define EFM32_DAC_OPA1MUX_OFFSET 0x0060 /* Operational Amplifier Mux Configuration Register */
#define EFM32_DAC_OPA2MUX_OFFSET 0x0064 /* Operational Amplifier Mux Configuration Register */
/* DAC Register Addresses ******************************************************************************************************/
/* DAC Register Addresses ***************************************************/
#define EFM32_DAC0_CTRL (EFM32_DAC0_BASE+EFM32_DAC_CTRL_OFFSET)
#define EFM32_DAC0_STATUS (EFM32_DAC0_BASE+EFM32_DAC_STATUS_OFFSET)
@@ -117,7 +118,7 @@
#define EFM32_DAC0_OPA1MUX (EFM32_DAC0_BASE+EFM32_DAC_OPA1MUX_OFFSET)
#define EFM32_DAC0_OPA2MUX (EFM32_DAC0_BASE+EFM32_DAC_OPA2MUX_OFFSET)
/* DAC Register Bit Field Definitions ******************************************************************************************/
/* DAC Register Bit Field Definitions ***************************************/
/* Bit fields for DAC CTRL */
arch/arm/src/efm32/hardware/efm32_devinfo.h
+14 -16
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_devinfo.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DEVINFO_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DEVINFO_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,12 +72,11 @@
# warning This is the EFM32GG header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
****************************************************************************/
/* MSC Register Offsets ********************************************************************************************************/
/* MSC Register Offsets *****************************************************/
#define EFM32_DEVINFO_CAL_OFFSET 0x0000
#define EFM32_DEVINFO_ADC0CALn_OFFSET(n) (0x0004+(n)*4)
@@ -90,7 +89,7 @@
#define EFM32_DEVINFO_MEMINFO_SIZE_OFFSET 0x0048
#define EFM32_DEVINFO_PART_OFFSET 0x004c
/* MSC Register Addresses ******************************************************************************************************/
/* MSC Register Addresses ***************************************************/
#define EFM32_DEVINFO_CAL (EFM32_DEVINFO_BASE+EFM32_DEVINFO_CAL_OFFSET)
@@ -221,9 +220,8 @@
#define _DEVINFO_PART_DEVICE_NUMBER_MASK 0x0000FFFFUL /* Device number */
#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /* Bit position for device number */
/*******************************************************************************************************************************
/****************************************************************************
* Public Type Definitions
*******************************************************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DEVINFO_H */
arch/arm/src/efm32/hardware/efm32_dma.h
+18 -17
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_dma.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DMA_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DMA_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,9 +72,9 @@
# warning This is the EFM32GG/G header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
****************************************************************************/
#if defined(CONFIG_EFM32_EFM32GG)
# define EFM32_DMA_NCHANNELS 12
@@ -82,7 +82,7 @@
# define EFM32_DMA_NCHANNELS 8
#endif
/* DMA Register Offsets ********************************************************************************************************/
/* DMA Register Offsets *****************************************************/
#define EFM32_DMA_STATUS_OFFSET 0x0000 /* DMA Status Registers */
#define EFM32_DMA_CONFIG_OFFSET 0x0004 /* DMA Configuration Register */
@@ -116,6 +116,7 @@
#endif
#define EFM32_DMA_CHn_CTRL_OFFSET(n) (0x1100+((n)<<2)) /* Channel n Control Register */
#define EFM32_DMA_CH0_CTRL_OFFSET 0x1100 /* Channel 0 Control Register */
#define EFM32_DMA_CH1_CTRL_OFFSET 0x1104 /* Channel 1 Control Register */
#define EFM32_DMA_CH2_CTRL_OFFSET 0x1108 /* Channel 2 Control Register */
@@ -131,7 +132,7 @@
# define EFM32_DMA_CH11_CTRL_OFFSET 0x112c /* Channel 11 Control Register */
#endif
/* DMA Register Addresses ******************************************************************************************************/
/* DMA Register Addresses ***************************************************/
#define EFM32_DMA_STATUS (EFM32_DMA_BASE+EFM32_DMA_STATUS_OFFSET)
#define EFM32_DMA_CONFIG (EFM32_DMA_BASE+EFM32_DMA_CONFIG_OFFSET)
@@ -180,7 +181,7 @@
# define EFM32_DMA_CH11_CTRL (EFM32_DMA_BASE+EFM32_DMA_CH11_CTRL_OFFSET)
#endif
/* DMA Register Bit Field Definitions ******************************************************************************************/
/* DMA Register Bit Field Definitions ***************************************/
/* Bit fields for DMA STATUS */
@@ -2067,7 +2068,7 @@
#endif
/* DMA Descriptor Bit Field Definitions ****************************************************************************************/
/* DMA Descriptor Bit Field Definitions *************************************/
#define _DMA_CTRL_DST_INC_MASK 0xC0000000UL /* Data increment for destination, bit mask */
#define _DMA_CTRL_DST_INC_SHIFT 30 /* Data increment for destination, shift value */
@@ -2166,7 +2167,7 @@
#define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x000000006UL /* Peripheral scatter gather cycle type */
#define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x000000007UL /* Peripheral scatter gather cycle type using alternate structure */
/* DMA Request Bit Definitions *************************************************************************************************/
/* DMA Request Bit Definitions **********************************************/
#if defined(CONFIG_EFM32_EFM32GG)
# define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /* DMA channel select for ADC0_SINGLE */
@@ -2272,9 +2273,9 @@
# define DMAREQ_AES_KEYWR ((49 << 16) + 3) /* DMA channel select for AES_KEYWR */
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Public Types
*******************************************************************************************************************************/
****************************************************************************/
struct dma_descriptor_s
{
arch/arm/src/efm32/hardware/efm32_emu.h
+14 -13
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_emu.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_EMU_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_EMU_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,10 +72,11 @@
# warning This is the EFM32GG header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* EMU Register Offsets ********************************************************************************************************/
****************************************************************************/
/* EMU Register Offsets *****************************************************/
#define EFM32_EMU_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_EMU_MEMCTRL_OFFSET 0x0004 /* Memory Control Register */
@@ -95,7 +96,7 @@
#define EFM32_EMU_BUBODBUVINCAL_OFFSET 0x0058 /* BU_VIN Backup BOD calibration */
#define EFM32_EMU_BUBODUNREGCAL_OFFSET 0x005c /* Unregulated power Backup BOD calibration */
/* EMU Register Addresses ******************************************************************************************************/
/* EMU Register Addresses ***************************************************/
#define EFM32_EMU_CTRL (EFM32_EMU_BASE+EFM32_EMU_CTRL_OFFSET)
#define EFM32_EMU_MEMCTRL (EFM32_EMU_BASE+EFM32_EMU_MEMCTRL_OFFSET)
@@ -115,7 +116,7 @@
#define EFM32_EMU_BUBODBUVINCAL (EFM32_EMU_BASE+EFM32_EMU_BUBODBUVINCAL_OFFSET)
#define EFM32_EMU_BUBODUNREGCAL (EFM32_EMU_BASE+EFM32_EMU_BUBODUNREGCAL_OFFSET)
/* EMU Register Bit Field Definitions ******************************************************************************************/
/* EMU Register Bit Field Definitions ***************************************/
/* Bit fields for EMU CTRL */
arch/arm/src/efm32/hardware/efm32_flash.h
+4 -4
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_flash.h
*
* Copyright (C) 2015 Bouteville Pierre-Noel. All rights reserved.
@@ -31,14 +31,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_FLASH_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_FLASH_H
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
#if defined(CONFIG_EFM32_EFM32GG)
# define EFM32_FLASH_PAGESIZE 4096
arch/arm/src/efm32/hardware/efm32_gpio.h
+13 -13
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_gpio.h
*
* (C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_GPIO_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_GPIO_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,11 +72,11 @@
# warning This is the EFM32GG/G header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
****************************************************************************/
/* GPIO Register Offsets *******************************************************************************************************/
/* GPIO Register Offsets ****************************************************/
#define EFM32_GPIIO_PA 0
#define EFM32_GPIIO_PB 1
@@ -183,7 +183,7 @@
# define EFM32_GPIO_EM4WUCAUSE_OFFSET 0x13c /* EM4 Wake-up Cause Register */
#endif
/* GPIO Register Addresses *****************************************************************************************************/
/* GPIO Register Addresses **************************************************/
#define EFM32_GPIO_Pn_BASE(n) (EFM32_GPIO_BASE+EFM32_GPIO_Pn_OFFSET(n))
#define EFM32_GPIO_PA_BASE (EFM32_GPIO_BASE+EFM32_GPIO_PA_OFFSET)
@@ -283,7 +283,7 @@
# define EFM32_GPIO_EM4WUCAUSE (EFM32_GPIO_BASE+EFM32_GPIO_EM4WUCAUSE_OFFSET)
#endif
/* GPIO Register Bit Field Definitions *****************************************************************************************/
/* GPIO Register Bit Field Definitions **************************************/
/* Bit fields for GPIO P_CTRL */
arch/arm/src/efm32/hardware/efm32_i2c.h
+14 -13
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_i2c.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_I2C_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_I2C_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,10 +72,11 @@
# warning This is the EFM32GG header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* I2C Register Offsets ********************************************************************************************************/
****************************************************************************/
/* I2C Register Offsets *****************************************************/
#define EFM32_I2C_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_I2C_CMD_OFFSET 0x0004 /* Command Register */
@@ -93,7 +94,7 @@
#define EFM32_I2C_IEN_OFFSET 0x0034 /* Interrupt Enable Register */
#define EFM32_I2C_ROUTE_OFFSET 0x0038 /* I/O Routing Register */
/* I2C Register Addresses ******************************************************************************************************/
/* I2C Register Addresses ***************************************************/
#define EFM32_I2C0_CTRL (EFM32_I2C0_BASE+EFM32_I2C_CTRL_OFFSET)
#define EFM32_I2C0_CMD (EFM32_I2C0_BASE+EFM32_I2C_CMD_OFFSET)
@@ -127,7 +128,7 @@
#define EFM32_I2C1_IEN (EFM32_I2C1_BASE+EFM32_I2C_IEN_OFFSET)
#define EFM32_I2C1_ROUTE (EFM32_I2C1_BASE+EFM32_I2C_ROUTE_OFFSET)
/* I2C Register Bit Field Definitions ******************************************************************************************/
/* I2C Register Bit Field Definitions ***************************************/
/* Bit fields for I2C CTRL */
arch/arm/src/efm32/hardware/efm32_lcd.h
+14 -13
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_lcd.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LCD_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LCD_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,10 +72,11 @@
# warning This is the EFM32GG header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* LCD Register Offsets ********************************************************************************************************/
****************************************************************************/
/* LCD Register Offsets *****************************************************/
#define EFM32_LCD_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_LCD_DISPCTRL_OFFSET 0x0004 /* Display Control Register */
@@ -107,7 +108,7 @@
#define EFM32_LCD_SEGD6L_OFFSET 0x00d4 /* Segment Data Low Register 6 */
#define EFM32_LCD_SEGD7L_OFFSET 0x00d8 /* Segment Data Low Register 7 */
/* LCD Register Addresses ******************************************************************************************************/
/* LCD Register Addresses ***************************************************/
#define EFM32_LCD_CTRL (EFM32_LCD_BASE+EFM32_LCD_CTRL_OFFSET)
#define EFM32_LCD_DISPCTRL (EFM32_LCD_BASE+EFM32_LCD_DISPCTRL_OFFSET)
@@ -139,7 +140,7 @@
#define EFM32_LCD_SEGD6L (EFM32_LCD_BASE+EFM32_LCD_SEGD6L_OFFSET)
#define EFM32_LCD_SEGD7L (EFM32_LCD_BASE+EFM32_LCD_SEGD7L_OFFSET)
/* LCD Register Bit Field Definitions ******************************************************************************************/
/* LCD Register Bit Field Definitions ***************************************/
/* Bit fields for LCD CTRL */
arch/arm/src/efm32/hardware/efm32_lesense.h
+14 -13
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_lesense.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LESENSE_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LESENSE_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,10 +72,11 @@
# warning This is the EFM32GG header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* LESENSE Register Offsets ****************************************************************************************************/
****************************************************************************/
/* LESENSE Register Offsets *************************************************/
#define EFM32_LESENSE_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_LESENSE_TIMCTRL_OFFSET 0x0004 /* Timing Control Register */
@@ -162,7 +163,7 @@
#define EFM32_LESENSE_CHn_INTERACT_OFFSET 0x0004 /* Channel n Scan Configuration */
#define EFM32_LESENSE_CHn_EVAL_OFFSET 0x0008 /* Channel n Scan Configuration */
/* LESENSE Register Addresses **************************************************************************************************/
/* LESENSE Register Addresses ***********************************************/
#define EFM32_LESENSE_CTRL (EFM32_LESENSE_BASE+EFM32_LESENSE_CTRL_OFFSET)
#define EFM32_LESENSE_TIMCTRL (EFM32_LESENSE_BASE+EFM32_LESENSE_TIMCTRL_OFFSET)
@@ -249,7 +250,7 @@
#define EFM32_LESENSE_CH_INTERACT(n) (EFM32_LESENSE_CH_BASE(n)+EFM32_LESENSE_CHn_INTERACT_OFFSET)
#define EFM32_LESENSE_CH_EVAL(n) (EFM32_LESENSE_CH_BASE(n)+EFM32_LESENSE_CHb_EVAL_OFFSET)
/* LESENSE Register Bit Field Definitions **************************************************************************************/
/* LESENSE Register Bit Field Definitions ***********************************/
/* Bit fields for LESENSE CTRL */
arch/arm/src/efm32/hardware/efm32_letimer.h
+14 -13
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_letimer.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LETIMER_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LETIMER_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,10 +72,11 @@
# warning This is the EFM32GG header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* LETIMER Register Offsets ****************************************************************************************************/
****************************************************************************/
/* LETIMER Register Offsets *************************************************/
#define EFM32_LETIMER_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_LETIMER_CMD_OFFSET 0x0004 /* Command Register */
@@ -93,7 +94,7 @@
#define EFM32_LETIMER_SYNCBUSY_OFFSET 0x0034 /* Synchronization Busy Register */
#define EFM32_LETIMER_ROUTE_OFFSET 0x0040 /* I/O Routing Register */
/* LETIMER Register Addresses **************************************************************************************************/
/* LETIMER Register Addresses ***********************************************/
#define EFM32_LETIMER0_CTRL (EFM32_LETIMER0_BASE+EFM32_LETIMER0_CTRL_OFFSET)
#define EFM32_LETIMER0_CMD (EFM32_LETIMER0_BASE+EFM32_LETIMER0_CMD_OFFSET)
@@ -111,7 +112,7 @@
#define EFM32_LETIMER0_SYNCBUSY (EFM32_LETIMER0_BASE+EFM32_LETIMER0_SYNCBUSY_OFFSET)
#define EFM32_LETIMER0_ROUTE (EFM32_LETIMER0_BASE+EFM32_LETIMER0_ROUTE_OFFSET)
/* LETIMER Register Bit Field Definitions **************************************************************************************/
/* LETIMER Register Bit Field Definitions ***********************************/
/* Bit fields for LETIMER CTRL */
arch/arm/src/efm32/hardware/efm32_leuart.h
+14 -13
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_leuart.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LEUART_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LEUART_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,10 +72,11 @@
# warning This is the EFM32GG/G header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* LEUART Register Offsets *****************************************************************************************************/
****************************************************************************/
/* LEUART Register Offsets **************************************************/
#define EFM32_LEUART_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_LEUART_CMD_OFFSET 0x0004 /* Command Register */
@@ -101,7 +102,7 @@
# define EFM32_LEUART_INPUT_OFFSET 0x00ac /* LEUART Input Register */
#endif
/* LEUART Register Addresses ***************************************************************************************************/
/* LEUART Register Addresses ************************************************/
#define EFM32_LEUART0_CTRL (EFM32_LEUART0_BASE+EFM32_LEUART_CTRL_OFFSET)
#define EFM32_LEUART0_CMD (EFM32_LEUART0_BASE+EFM32_LEUART_CMD_OFFSET)
@@ -153,7 +154,7 @@
# endif
#endif
/* LEUART Register Bit Field Definitions ***************************************************************************************/
/* LEUART Register Bit Field Definitions ************************************/
/* Bit fields for LEUART CTRL */
arch/arm/src/efm32/hardware/efm32_memorymap.h
+4 -4
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_MEMORYMAP_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_MEMORYMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
arch/arm/src/efm32/hardware/efm32_msc.h
+13 -13
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_msc.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,22 +56,22 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_EFM32_EFM32_MSC_H
#define __ARCH_ARM_SRC_EFM32_EFM32_EFM32_MSC_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include "hardware/efm32_memorymap.h"
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
****************************************************************************/
/* MSC Register Offsets ********************************************************************************************************/
/* MSC Register Offsets *****************************************************/
#define EFM32_MSC_CTRL_OFFSET 0x0000 /* Memory System Control Register */
#define EFM32_MSC_READCTRL_OFFSET 0x0004 /* Read Control Register */
@@ -94,7 +94,7 @@
# define EFM32_MSC_MASSLOCK_OFFSET 0x0054 /* Mass Erase Lock Register */
#endif
/* MSC Register Addresses ******************************************************************************************************/
/* MSC Register Addresses ***************************************************/
#define EFM32_MSC_CTRL (EFM32_MSC_BASE+EFM32_MSC_CTRL_OFFSET)
#define EFM32_MSC_READCTRL (EFM32_MSC_BASE+EFM32_MSC_READCTRL_OFFSET)
@@ -117,7 +117,7 @@
# define EFM32_MSC_MASSLOCK (EFM32_MSC_BASE+EFM32_MSC_MASSLOCK_OFFSET)
#endif
/* MSC Register Bit Field Definitions ******************************************************************************************/
/* MSC Register Bit Field Definitions ***************************************/
/* Bit fields for MSC CTRL */
arch/arm/src/efm32/hardware/efm32_pcnt.h
+14 -13
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_pcnt.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_PCNT_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_PCNT_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,10 +72,11 @@
# warning This is the EFM32GG header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* PCNT Register Offsets *******************************************************************************************************/
****************************************************************************/
/* PCNT Register Offsets ****************************************************/
#define EFM32_PCNT_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_PCNT_CMD_OFFSET 0x0004 /* Command Register */
@@ -93,7 +94,7 @@
#define EFM32_PCNT_AUXCNT_OFFSET 0x0038 /* Auxiliary Counter Value Register */
#define EFM32_PCNT_INPUT_OFFSET 0x003c /* PCNT Input Register */
/* PCNT Register Addresses *****************************************************************************************************/
/* PCNT Register Addresses **************************************************/
#define EFM32_PCNT0_CTRL (EFM32_PCNT0_BASE+EFM32_PCNT_CTRL_OFFSET)
#define EFM32_PCNT0_CMD (EFM32_PCNT0_BASE+EFM32_PCNT_CMD_OFFSET)
@@ -143,7 +144,7 @@
#define EFM32_PCNT2_AUXCNT (EFM32_PCNT2_BASE+EFM32_PCNT_AUXCNT_OFFSET)
#define EFM32_PCNT2_INPUT (EFM32_PCNT2_BASE+EFM32_PCNT_INPUT_OFFSET)
/* PCNT Register Bit Field Definitions *****************************************************************************************/
/* PCNT Register Bit Field Definitions **************************************/
/* Bit fields for PCNT CTRL */
arch/arm/src/efm32/hardware/efm32_prs.h
+16 -15
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_prs.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_PRS_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_PRS_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,14 +72,15 @@
# warning This is the EFM32GG header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* PRS Register Offsets ********************************************************************************************************/
****************************************************************************/
/* PRS Register Offsets *****************************************************/
#define EFM32_PRS_SWPULSE_OFFSET 0x0000 /* Software Pulse Register */
#define EFM32_PRS_SWLEVEL_OFFSET 0x0004 /* Software Level Register */
#define EFM32_PRS_ROUTE_OFFSET 0x0008 /* I/O Routing Register
#define EFM32_PRS_ROUTE_OFFSET 0x0008 /* I/O Routing Register */
#define EFM32_PRS_CH_CTRL_OFFSET(n) (0x0010 + ((n) << 2))
#define EFM32_PRS_CH0_CTRL_OFFSET 0x0010 /* Channel 0 Control Register */
@@ -95,7 +96,7 @@
#define EFM32_PRS_CH10_CTRL_OFFSET 0x0018 /* Channel 10 Control Register */
#define EFM32_PRS_CH11_CTRL_OFFSET 0x003c /* Channel 11 Control Register */
/* PRS Register Addresses ******************************************************************************************************/
/* PRS Register Addresses ***************************************************/
#define EFM32_PRS_SWPULSE (EFM32_PRS_BASE+EFM32_PRS_SWPULSE_OFFSET)
#define EFM32_PRS_SWLEVEL (EFM32_PRS_BASE+EFM32_PRS_SWLEVEL_OFFSET)
@@ -115,7 +116,7 @@
#define EFM32_PRS_CH10_CTRL (EFM32_PRS_BASE+EFM32_PRS_CH10_CTRL_OFFSET)
#define EFM32_PRS_CH11_CTRL (EFM32_PRS_BASE+EFM32_PRS_CH11_CTRL_OFFSET)
/* PRS Register Bit Field Definitions ******************************************************************************************/
/* PRS Register Bit Field Definitions ***************************************/
/* Bit fields for PRS SWPULSE */
@@ -522,7 +523,7 @@
#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_CH_CTRL */
#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /* Shifted mode DEFAULT for PRS_CH_CTRL */
/* PRS Signals *****************************************************************************************************************/
/* PRS Signals **************************************************************/
#define PRS_VCMP_OUT ((1 << 16) + 0) /* PRS Voltage comparator output */
#define PRS_ACMP0_OUT ((2 << 16) + 0) /* PRS Analog comparator output */
arch/arm/src/efm32/hardware/efm32_rmu.h
+14 -13
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_rmu.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RMU_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RMU_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,22 +72,23 @@
# warning This is the EFM32GG header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* RMU Register Offsets ********************************************************************************************************/
****************************************************************************/
/* RMU Register Offsets *****************************************************/
#define EFM32_RMU_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_RMU_RSTCAUSE_OFFSET 0x0004 /* Reset Cause Register */
#define EFM32_RMU_CMD_OFFSET 0x0008 /* Command Register */
/* RMU Register Addresses ******************************************************************************************************/
/* RMU Register Addresses ***************************************************/
#define EFM32_RMU_CTRL (EFM32_RMU_BASE+EFM32_RMU_CTRL_OFFSET)
#define EFM32_RMU_RSTCAUSE (EFM32_RMU_BASE+EFM32_RMU_RSTCAUSE_OFFSET)
#define EFM32_RMU_CMD (EFM32_RMU_BASE+EFM32_RMU_CMD_OFFSET)
/* RMU Register Bit Field Definitions ******************************************************************************************/
/* RMU Register Bit Field Definitions ***************************************/
/* Bit fields for RMU CTRL */
arch/arm/src/efm32/hardware/efm32_romtable.h
+12 -12
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_romtable.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ROMTABLE_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ROMTABLE_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,9 +72,9 @@
# warning This is the EFM32GG header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
****************************************************************************/
#define ROMTABLE ((const struct efm32_romtable_s *)EFM32_ROMTABLE_BASE)
@@ -94,9 +94,9 @@
#define _ROMTABLE_PID3_REVMINORLSB_MASK 0x000000F0UL /* Least Significant Bits [3:0] of CHIP MINOR revision, mask */
#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /* Least Significant Bits [3:0] of CHIP MINOR revision, shift */
/*******************************************************************************************************************************
/****************************************************************************
* Public Type Definitions
*******************************************************************************************************************************/
****************************************************************************/
struct efm32_romtable_s
{
arch/arm/src/efm32/hardware/efm32_rtc.h
+14 -13
View File
@@ -1,4 +1,4 @@
/*******************************************************************************************************************************
/****************************************************************************
* arch/arm/src/efm32/hardware/efm32_rtc.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -15,10 +15,10 @@
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
* providing the Software "AS IS", with no express or implied warranties of
* any kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties
* against infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
@@ -56,14 +56,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RTC_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RTC_H
/*******************************************************************************************************************************
/****************************************************************************
* Included Files
*******************************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/efm32_memorymap.h"
@@ -72,10 +72,11 @@
# warning This is the EFM32GG header file; Review/modification needed for this architecture
#endif
/*******************************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* RTC Register Offsets ********************************************************************************************************/
****************************************************************************/
/* RTC Register Offsets *****************************************************/
#define EFM32_RTC_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_RTC_CNT_OFFSET 0x0004 /* Counter Value Register */
@@ -88,7 +89,7 @@
#define EFM32_RTC_FREEZE_OFFSET 0x0020 /* Freeze Register */
#define EFM32_RTC_SYNCBUSY_OFFSET 0x0024 /* Synchronization Busy Register */
/* RTC Register Addresses ******************************************************************************************************/
/* RTC Register Addresses ***************************************************/
#define EFM32_RTC_CTRL (EFM32_RTC_BASE+EFM32_RTC_CTRL_OFFSET)
#define EFM32_RTC_CNT (EFM32_RTC_BASE+EFM32_RTC_CNT_OFFSET)
@@ -101,7 +102,7 @@
#define EFM32_RTC_FREEZE (EFM32_RTC_BASE+EFM32_RTC_FREEZE_OFFSET)
#define EFM32_RTC_SYNCBUSY (EFM32_RTC_BASE+EFM32_RTC_SYNCBUSY_OFFSET)
/* RTC Register Bit Field Definitions ******************************************************************************************/
/* RTC Register Bit Field Definitions ***************************************/
/* Bit fields for RTC CTRL */

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