diff --git a/arch/arm/src/efm32/chip.h b/arch/arm/src/efm32/chip.h index b790d81b3e4..69d2659ef07 100644 --- a/arch/arm/src/efm32/chip.h +++ b/arch/arm/src/efm32/chip.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/efm32/chip.h * * Copyright (C) 2009, 2011-2014, 2018 Gregory Nutt. All rights reserved. @@ -33,14 +33,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_H #define __ARCH_ARM_SRC_EFM32_CHIP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -52,13 +52,13 @@ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Provide the required number of peripheral interrupt vector definitions as well. - * The definition EFM32_PERIPH_INTS simply comes from the chip-specific IRQ header - * file included by arch/efm32/irq.h. +/* Provide the required number of peripheral interrupt vector definitions as + * well. The definition EFM32_PERIPH_INTS simply comes from the chip-specific + * IRQ header file included by arch/efm32/irq.h. */ #define ARMV7M_PERIPHERAL_INTERRUPTS EFM32_PERIPH_INTS diff --git a/arch/arm/src/efm32/efm32_adc.c b/arch/arm/src/efm32/efm32_adc.c index c5bf988fb24..a164e560872 100644 --- a/arch/arm/src/efm32/efm32_adc.c +++ b/arch/arm/src/efm32/efm32_adc.c @@ -79,6 +79,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* ADC interrupts ***********************************************************/ /* The maximum number of channels that can be sampled. If dma support is @@ -117,12 +118,14 @@ struct efm32_dev_s /* ADC Register access */ static uint32_t adc_getreg(struct efm32_dev_s *priv, int offset); -static void adc_putreg(struct efm32_dev_s *priv, int offset, uint32_t value); +static void adc_putreg(struct efm32_dev_s *priv, int offset, + uint32_t value); static void adc_hw_reset(struct efm32_dev_s *priv, bool reset); /* ADC Interrupt Handler */ -static int adc_interrupt(int irq, FAR void *context, FAR struct adc_dev_s *dev); +static int adc_interrupt(int irq, + FAR void *context, FAR struct adc_dev_s *dev); /* ADC Driver Methods */ @@ -227,9 +230,9 @@ static void adc_putreg(struct efm32_dev_s *priv, int offset, uint32_t value) * reference. * * During production, calibration values are made and stored in the device - * information page for known references. Notice that for external references, - * calibration values must be determined explicitly, and this function - * will not modify the calibration register. + * information page for known references. Notice that for external + * references, calibration values must be determined explicitly, and this + * function will not modify the calibration register. * * Input Parameters: * adc - Pointer to ADC peripheral register block. @@ -254,7 +257,8 @@ static void ADC_CalibrateLoadScan(ADC_TypeDef *adc, ADC_Ref_TypeDef ref) cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_1V25_GAIN_MASK) >> _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT) << _ADC_CAL_SCANGAIN_SHIFT; cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK) >> - _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT) << _ADC_CAL_SCANOFFSET_SHIFT; + _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT) << + _ADC_CAL_SCANOFFSET_SHIFT; adc->CAL = cal; break; @@ -263,7 +267,8 @@ static void ADC_CalibrateLoadScan(ADC_TypeDef *adc, ADC_Ref_TypeDef ref) cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_2V5_GAIN_MASK) >> _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT) << _ADC_CAL_SCANGAIN_SHIFT; cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK) >> - _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT) << _ADC_CAL_SCANOFFSET_SHIFT; + _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT) << + _ADC_CAL_SCANOFFSET_SHIFT; adc->CAL = cal; break; @@ -272,7 +277,8 @@ static void ADC_CalibrateLoadScan(ADC_TypeDef *adc, ADC_Ref_TypeDef ref) cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_VDD_GAIN_MASK) >> _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT) << _ADC_CAL_SCANGAIN_SHIFT; cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK) >> - _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT) << _ADC_CAL_SCANOFFSET_SHIFT; + _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT) << + _ADC_CAL_SCANOFFSET_SHIFT; adc->CAL = cal; break; @@ -281,16 +287,19 @@ static void ADC_CalibrateLoadScan(ADC_TypeDef *adc, ADC_Ref_TypeDef ref) cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK) >> _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT) << _ADC_CAL_SCANGAIN_SHIFT; cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK) >> - _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT) << _ADC_CAL_SCANOFFSET_SHIFT; + _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT) << + _ADC_CAL_SCANOFFSET_SHIFT; adc->CAL = cal; break; case adcRef2xVDD: + /* Gain value not of relevance for this reference, leave as is */ cal = adc->CAL & ~_ADC_CAL_SCANOFFSET_MASK; cal |= ((DEVINFO->ADC0CAL2 & _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK) >> - _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT) << _ADC_CAL_SCANOFFSET_SHIFT; + _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT) << + _ADC_CAL_SCANOFFSET_SHIFT; adc->CAL = cal; break; @@ -311,9 +320,9 @@ static void ADC_CalibrateLoadScan(ADC_TypeDef *adc, ADC_Ref_TypeDef ref) * reference. * * During production, calibration values are made and stored in the device - * information page for known references. Notice that for external references, - * calibration values must be determined explicitly, and this function - * will not modify the calibration register. + * information page for known references. Notice that for external + * references, calibration values must be determined explicitly, and this + * function will not modify the calibration register. * * Input Parameters: * adc - Pointer to ADC peripheral register block. @@ -334,47 +343,58 @@ static void ADC_CalibrateLoadSingle(ADC_TypeDef *adc, ADC_Ref_TypeDef ref) switch (ref) { case adcRef1V25: - cal = adc->CAL & ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK); + cal = adc->CAL & + ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK); cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_1V25_GAIN_MASK) >> _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT) << _ADC_CAL_SINGLEGAIN_SHIFT; cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK) >> - _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT; + _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT) << + _ADC_CAL_SINGLEOFFSET_SHIFT; adc->CAL = cal; break; case adcRef2V5: - cal = adc->CAL & ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK); + cal = adc->CAL & + ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK); cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_2V5_GAIN_MASK) >> _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT) << _ADC_CAL_SINGLEGAIN_SHIFT; cal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK) >> - _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT; + _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT) << + _ADC_CAL_SINGLEOFFSET_SHIFT; adc->CAL = cal; break; case adcRefVDD: - cal = adc->CAL & ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK); + cal = adc->CAL & + ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK); cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_VDD_GAIN_MASK) >> _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT) << _ADC_CAL_SINGLEGAIN_SHIFT; cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK) >> - _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT; + _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT) << + _ADC_CAL_SINGLEOFFSET_SHIFT; adc->CAL = cal; break; case adcRef5VDIFF: - cal = adc->CAL & ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK); + cal = adc->CAL & + ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SINGLEGAIN_MASK); cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK) >> - _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT) << _ADC_CAL_SINGLEGAIN_SHIFT; + _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT) << + _ADC_CAL_SINGLEGAIN_SHIFT; cal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK) >> - _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT; + _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT) << + _ADC_CAL_SINGLEOFFSET_SHIFT; adc->CAL = cal; break; case adcRef2xVDD: + /* Gain value not of relevance for this reference, leave as is */ cal = adc->CAL & ~_ADC_CAL_SINGLEOFFSET_MASK; cal |= ((DEVINFO->ADC0CAL2 & _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK) >> - _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT) << _ADC_CAL_SINGLEOFFSET_SHIFT; + _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT) << + _ADC_CAL_SINGLEOFFSET_SHIFT; adc->CAL = cal; break; @@ -397,8 +417,8 @@ static void ADC_CalibrateLoadSingle(ADC_TypeDef *adc, ADC_Ref_TypeDef ref) * * Description: * Initializes common parts for both single conversion and scan sequence. - * In addition, single and/or scan control configuration must be done, please - * refer to ADC_InitSingle() and ADC_InitScan() respectively. + * In addition, single and/or scan control configuration must be done, + * please refer to ADC_InitSingle() and ADC_InitScan() respectively. * * NOTE: This function will stop any ongoing conversion. * @@ -419,8 +439,10 @@ void ADC_Init(ADC_TypeDef *adc, const ADC_Init_TypeDef *init) adc->CMD = ADC_CMD_SINGLESTOP | ADC_CMD_SCANSTOP; tmp = ((uint32_t)(init->ovsRateSel) << _ADC_CTRL_OVSRSEL_SHIFT) | - (((uint32_t)(init->timebase) << _ADC_CTRL_TIMEBASE_SHIFT) & _ADC_CTRL_TIMEBASE_MASK) | - (((uint32_t)(init->prescale) << _ADC_CTRL_PRESC_SHIFT) & _ADC_CTRL_PRESC_MASK) | + (((uint32_t)(init->timebase) << _ADC_CTRL_TIMEBASE_SHIFT) & + _ADC_CTRL_TIMEBASE_MASK) | + (((uint32_t)(init->prescale) << _ADC_CTRL_PRESC_SHIFT) & + _ADC_CTRL_PRESC_MASK) | ((uint32_t)(init->lpfMode) << _ADC_CTRL_LPFMODE_SHIFT) | ((uint32_t)(init->warmUpMode) << _ADC_CTRL_WARMUPMODE_SHIFT); @@ -568,7 +590,8 @@ void ADC_InitSingle(ADC_TypeDef *adc, const ADC_InitSingle_TypeDef *init) * * Input Parameters: * adcFreq ADC frequency wanted. The frequency will automatically - * be adjusted to be within valid range according to reference manual. + * be adjusted to be within valid range according to reference + * manual. * hfperFreq Frequency in Hz of reference HFPER clock. Set to 0 to * use currently defined HFPER clock setting. * @@ -648,7 +671,8 @@ void ADC_Reset(ADC_TypeDef *adc) * Name: ADC_TimebaseCalc * * Description: - * Calculate timebase value in order to get a timebase providing at least 1us. + * Calculate timebase value in order to get a timebase providing at least + * 1us. * * Input Parameters: * hfperFreq Frequency in Hz of reference HFPER clock. Set to 0 to @@ -696,6 +720,7 @@ uint8_t ADC_TimebaseCalc(uint32_t hfperFreq) return (uint8_t)(hfperFreq - 1); } + endif /* defined(ADC_COUNT) && (ADC_COUNT > 0) */ /**************************************************************************** @@ -882,8 +907,8 @@ static void adc_enable(FAR struct efm32_dev_s *priv, bool enable) * Name: adc_bind * * Description: - * Bind the upper-half driver callbacks to the lower-half implementation. This - * must be called early in order to receive ADC event notifications. + * Bind the upper-half driver callbacks to the lower-half implementation. + * This must be called early in order to receive ADC event notifications. * ****************************************************************************/ @@ -1015,16 +1040,18 @@ static void adc_reset(FAR struct adc_dev_s *dev) /* ADC CCR configuration */ regval = getreg32(EFM32_ADC_CCR); - regval &= ~(ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | ADC_CCR_DMA_MASK | + regval &= ~(ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | + ADC_CCR_DDS | ADC_CCR_DMA_MASK | ADC_CCR_ADCPRE_MASK | ADC_CCR_VBATE | ADC_CCR_TSVREFE); - regval |= (ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED | ADC_CCR_ADCPRE_DIV2); + regval |= (ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED | + ADC_CCR_ADCPRE_DIV2); putreg32(regval, EFM32_ADC_CCR); /* Set the number of conversions */ DEBUGASSERT(priv->nchannels <= ADC_MAX_SAMPLES); - regval |= (((uint32_t)priv->nchannels-1) << ADC_SQR1_L_SHIFT); + regval |= (((uint32_t)priv->nchannels - 1) << ADC_SQR1_L_SHIFT); adc_putreg(priv, EFM32_ADC_SQR1_OFFSET, regval); /* Set the channel index of the first conversion */ @@ -1055,8 +1082,8 @@ static void adc_reset(FAR struct adc_dev_s *dev) * Description: * Configure the ADC. This method is called the first time that the ADC * device is opened. This will occur when the port is first opened. - * This setup includes configuring and attaching ADC interrupts. Interrupts - * are all disabled upon return. + * This setup includes configuring and attaching ADC interrupts. + * Interrupts are all disabled upon return. * * Input Parameters: * @@ -1179,7 +1206,8 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) * ****************************************************************************/ -static int adc_interrupt(int irq, FAR void *context, FAR struct adc_dev_s *dev) +static int adc_interrupt(int irq, + FAR void *context, FAR struct adc_dev_s *dev) { FAR struct efm32_dev_s *priv = (FAR struct efm32_dev_s *)dev->ad_priv; uint32_t adcsr; @@ -1220,7 +1248,9 @@ static int adc_interrupt(int irq, FAR void *context, FAR struct adc_dev_s *dev) priv->cb->au_receive(dev, priv->chanlist[priv->current], value); } - /* Set the channel number of the next channel that will complete conversion */ + /* Set the channel number of the next channel that will complete + * conversion + */ priv->current++; @@ -1245,7 +1275,8 @@ static int adc_interrupt(int irq, FAR void *context, FAR struct adc_dev_s *dev) * Description: * Initialize the ADC. * - * The logic is, save nchannels : # of channels (conversions) in ADC_SQR1_L + * The logic is, save nchannels : + * # of channels (conversions) in ADC_SQR1_L * Then, take the chanlist array and store it in the SQR Regs, * chanlist[0] -> ADC_SQR3_SQ1 * chanlist[1] -> ADC_SQR3_SQ2 @@ -1265,7 +1296,8 @@ static int adc_interrupt(int irq, FAR void *context, FAR struct adc_dev_s *dev) * ****************************************************************************/ -struct adc_dev_s *efm32_adcinitialize(int intf, const uint8_t *chanlist, int nchannels) +struct adc_dev_s *efm32_adcinitialize(int intf, + const uint8_t *chanlist, int nchannels) { FAR struct adc_dev_s *dev; FAR struct efm32_dev_s *priv; diff --git a/arch/arm/src/efm32/efm32_adc.h b/arch/arm/src/efm32/efm32_adc.h index 48567174d73..88b9d7062f7 100644 --- a/arch/arm/src/efm32/efm32_adc.h +++ b/arch/arm/src/efm32/efm32_adc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/efm32/efm32_adc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_EFM32_ADC_H #define __ARCH_ARM_SRC_EFM32_EFM32_ADC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -33,18 +33,20 @@ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ -/* Timer devices may be used for different purposes. One special purpose is to - * control periodic ADC sampling. If CONFIG_EFM32_TIMn is defined then - * CONFIG_EFM32_TIMn_ADC must also be defined to indicate that timer "n" is intended - * to be used for that purpose. + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Timer devices may be used for different purposes. One special purpose is + * to control periodic ADC sampling. If CONFIG_EFM32_TIMn is defined then + * CONFIG_EFM32_TIMn_ADC must also be defined to indicate that timer "n" is + * intended to be used for that purpose. */ -/* For the EFM32 F1 line, timers 1-4 may be used. For EFM32 F4 line, timers 1-5 and - * 8 may be used. +/* For the EFM32 F1 line, timers 1-4 may be used. + * For EFM32 F4 line, timers 1-5 and 8 may be used. */ #ifndef CONFIG_EFM32_TIM1 @@ -84,7 +86,9 @@ # undef CONFIG_EFM32_TIM8_ADC3 #endif -/* Timers 6, 7, and 10-14 are not used with the ADC by any supported family */ +/* Timers 6, 7, + * and 10-14 are not used with the ADC by any supported family + */ #undef CONFIG_EFM32_TIM6_ADC #undef CONFIG_EFM32_TIM6_ADC1 @@ -141,8 +145,8 @@ # warning "DMA is not supported by the current driver" #endif -/* Timer configuration: If a timer trigger is specified, then get information - * about the timer. +/* Timer configuration: + * If a timer trigger is specified, then get information about the timer. */ #if defined(CONFIG_EFM32_TIM1_ADC1) @@ -268,11 +272,13 @@ # undef ADC_HAVE_TIMER #endif -/* NOTE: The following assumes that all possible combinations of timers and - * values are support EXTSEL. That is not so and it varies from one EFM32 to another. - * But this (wrong) assumptions keeps the logic as simple as possible. If un - * unsupported combination is used, an error will show up later during compilation - * although it may be difficult to track it back to this simplification. +/* NOTE: + * The following assumes that all possible combinations of timers and values + * are support EXTSEL. That is not so and it varies from one EFM32 to + * another. But this (wrong) assumptions keeps the logic as simple as + * possible. If un unsupported combination is used, an error will show + * up later during compilation although it may be difficult to track it back + * to this simplification. */ #if defined(CONFIG_EFM32_TIM1_ADC1) @@ -533,14 +539,15 @@ # endif #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ #ifdef __cplusplus #define EXTERN extern "C" -extern "C" { +extern "C" +{ #else #define EXTERN extern #endif diff --git a/arch/arm/src/efm32/efm32_bitband.c b/arch/arm/src/efm32/efm32_bitband.c index a4810705c35..97c22ac151d 100644 --- a/arch/arm/src/efm32/efm32_bitband.c +++ b/arch/arm/src/efm32/efm32_bitband.c @@ -93,10 +93,13 @@ * ****************************************************************************/ -inline void bitband_set_peripheral(uint32_t addr, uint32_t bit, uint32_t val) +inline void bitband_set_peripheral(uint32_t addr, + uint32_t bit, uint32_t val) { uint32_t regval; - regval = EFM32_BITBAND_PER_BASE + ((addr-EFM32_PER_MEM_BASE)*32) + (bit*4); + regval = EFM32_BITBAND_PER_BASE + + ((addr - EFM32_PER_MEM_BASE) * 32) + + (bit * 4); *((volatile uint32_t *)regval) = (uint32_t)val; } @@ -107,7 +110,8 @@ inline void bitband_set_peripheral(uint32_t addr, uint32_t bit, uint32_t val) * Description: * Perform bit-band operation on peripheral memory location. * - * This function reads a single bit from the peripheral bit-band alias region. + * This function reads a single bit from the peripheral bit-band alias + * region. * Bit-banding provides atomic read-modify-write cycle for single bit * modification. Please refer to the reference manual for further details * about bit-banding. @@ -127,7 +131,9 @@ inline void bitband_set_peripheral(uint32_t addr, uint32_t bit, uint32_t val) inline uint32_t bitband_get_peripheral(uint32_t addr, uint32_t bit) { uint32_t regval; - regval = EFM32_BITBAND_PER_BASE + ((addr-EFM32_PER_MEM_BASE)*32) + (bit*4); + regval = EFM32_BITBAND_PER_BASE + + ((addr - EFM32_PER_MEM_BASE) * 32) + + (bit * 4); return *((volatile uint32_t *)regval); } @@ -155,7 +161,9 @@ inline uint32_t bitband_get_peripheral(uint32_t addr, uint32_t bit) inline void bitband_set_sram(uint32_t addr, uint32_t bit, uint32_t val) { uint32_t regval; - regval = EFM32_BITBAND_RAM_BASE + ((addr-EFM32_RAM_MEM_BASE)*32) + (bit*4); + regval = EFM32_BITBAND_RAM_BASE + + ((addr - EFM32_RAM_MEM_BASE) * 32) + + (bit * 4); *((volatile uint32_t *)regval) = (uint32_t)val; } @@ -186,7 +194,9 @@ inline void bitband_set_sram(uint32_t addr, uint32_t bit, uint32_t val) inline uint32_t bitband_get_sram(uint32_t addr, uint32_t bit) { uint32_t regval; - regval = EFM32_BITBAND_RAM_BASE + ((addr-EFM32_RAM_MEM_BASE)*32) + (bit*4); + regval = EFM32_BITBAND_RAM_BASE + + ((addr - EFM32_RAM_MEM_BASE) * 32) + + (bit * 4); return *((volatile uint32_t *)regval); } diff --git a/arch/arm/src/efm32/efm32_bitband.h b/arch/arm/src/efm32/efm32_bitband.h index e84a7ff05d4..acaadb9f629 100644 --- a/arch/arm/src/efm32/efm32_bitband.h +++ b/arch/arm/src/efm32/efm32_bitband.h @@ -47,8 +47,8 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Configuration ************************************************************/ +/* Configuration ************************************************************/ /**************************************************************************** * Public Data @@ -59,7 +59,8 @@ ****************************************************************************/ #if defined(CONFIG_EFM32_BITBAND) -inline void bitband_set_peripheral(uint32_t addr, uint32_t bit, uint32_t val); +inline void bitband_set_peripheral(uint32_t addr, + uint32_t bit, uint32_t val); inline uint32_t bitband_get_peripheral(uint32_t addr, uint32_t bit); inline void bitband_set_sram(uint32_t addr, uint32_t bit, uint32_t val); inline uint32_t bitband_get_sram(uint32_t addr, uint32_t bit); diff --git a/arch/arm/src/efm32/efm32_clockconfig.c b/arch/arm/src/efm32/efm32_clockconfig.c index 89c0914c203..5f107090b3a 100644 --- a/arch/arm/src/efm32/efm32_clockconfig.c +++ b/arch/arm/src/efm32/efm32_clockconfig.c @@ -42,6 +42,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* BOARD Configuration ******************************************************/ /* Pre-scalers not currently implemented */ @@ -207,7 +208,6 @@ static void efm32_enable_leclocking(void) putreg32(regval, EFM32_CMU_HFCORECLKEN0); } - /**************************************************************************** * Name: efm32_maxwaitstates * @@ -241,7 +241,7 @@ static void efm32_maxwaitstates(void) regval |= MSC_READCTRL_MODE_WSMAXSCBTP; } - else + else { /* No.. select the mximum number of wait states without SCBTP */ @@ -353,7 +353,8 @@ static void efm32_setwaitstates(uint32_t hfcoreclk) * ****************************************************************************/ -static inline uint32_t efm32_hfclk_config(uint32_t hfclksel, uint32_t hfclkdiv) +static inline uint32_t efm32_hfclk_config(uint32_t hfclksel, + uint32_t hfclkdiv) { uint32_t frequency; #ifdef CMU_CTRL_HFLE @@ -399,10 +400,11 @@ static inline uint32_t efm32_hfclk_config(uint32_t hfclksel, uint32_t hfclkdiv) #ifdef CMU_CTRL_HFLE #if BOARD_HFXO_FREQUENCY > CMU_MAX_FREQ_HFLE - /* Adjust HFXO buffer current for high crystal frequencies, enable HFLE - * for frequencies above CMU_MAX_FREQ_HFLE. + /* Adjust HFXO buffer current for high crystal frequencies, + * enable HFLE for frequencies above CMU_MAX_FREQ_HFLE. * - * We must also have HFLE enabled to access some LE peripherals >= 32MHz. + * We must also have HFLE enabled to access some LE peripherals + * >= 32MHz. */ regval = getreg32(EFM32_CMU_CTRL); @@ -556,6 +558,7 @@ static inline uint32_t efm32_hfcoreclk_config(uint32_t hfcoreclkdiv, uint32_t hfclk) { /* REVISIT: Divider not currently used */ + return hfclk; } @@ -883,7 +886,8 @@ static inline void efm32_itm_syslog(void) regval = getreg32(EFM32_GPIO_ROUTE); regval &= ~_GPIO_ROUTE_SWLOCATION_MASK; regval |= GPIO_ROUTE_SWOPEN; - regval |= ((uint32_t)BOARD_SWOPORT_LOCATION << _GPIO_ROUTE_SWLOCATION_SHIFT); + regval |= ((uint32_t)BOARD_SWOPORT_LOCATION << + _GPIO_ROUTE_SWLOCATION_SHIFT); putreg32(regval, EFM32_GPIO_ROUTE); /* Enable output on pin */ @@ -893,7 +897,6 @@ static inline void efm32_itm_syslog(void) /* Enable debug clock AUXHFRCO */ efm32_enable_auxhfrco(); - } #else # define efm32_itm_syslog() @@ -922,14 +925,18 @@ void efm32_clockconfig(void) uint32_t lfaclk; uint32_t lfbclk; - /* Enable clocks and set dividers as determined by the board.h header file */ + /* Enable clocks and set dividers as determined by the board.h header + * file + */ hfclk = efm32_hfclk_config(BOARD_HFCLKSEL, BOARD_HFCLKDIV); hfcoreclk = efm32_hfcoreclk_config(BOARD_HFCORECLKDIV, hfclk); hfperclk = efm32_hfperclk_config(BOARD_HFPERCLKDIV, hfclk); coreleclk = efm32_coreleclk_config(hfclk); - lfaclk = efm32_lfaclk_config(BOARD_LFACLKSEL, BOARD_LFA_ULFCO_ENABLE, hfcoreclk); - lfbclk = efm32_lfbclk_config(BOARD_LFBCLKSEL, BOARD_LFB_ULFCO_ENABLE, hfcoreclk); + lfaclk = efm32_lfaclk_config(BOARD_LFACLKSEL, + BOARD_LFA_ULFCO_ENABLE, hfcoreclk); + lfbclk = efm32_lfbclk_config(BOARD_LFBCLKSEL, + BOARD_LFB_ULFCO_ENABLE, hfcoreclk); efm32_pcntclk_config(); efm32_wdogclk_config(); diff --git a/arch/arm/src/efm32/efm32_clockconfig.h b/arch/arm/src/efm32/efm32_clockconfig.h index 97558bb3b68..b0ec63d0a94 100644 --- a/arch/arm/src/efm32/efm32_clockconfig.h +++ b/arch/arm/src/efm32/efm32_clockconfig.h @@ -28,7 +28,7 @@ #include /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ /**************************************************************************** diff --git a/arch/arm/src/efm32/efm32_config.h b/arch/arm/src/efm32/efm32_config.h index fb7909f48da..c2331e9bd41 100644 --- a/arch/arm/src/efm32/efm32_config.h +++ b/arch/arm/src/efm32/efm32_config.h @@ -30,7 +30,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ + /* Make sure that the configuration does not enable UARTs that the MCU does * not have. */ diff --git a/arch/arm/src/efm32/efm32_dma.h b/arch/arm/src/efm32/efm32_dma.h index e53fe668726..14b97b3edc2 100644 --- a/arch/arm/src/efm32/efm32_dma.h +++ b/arch/arm/src/efm32/efm32_dma.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/efm32/efm32_dma.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_EFM32_DMA_H #define __ARCH_ARM_SRC_EFM32_EFM32_DMA_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -34,12 +34,12 @@ #include "chip.h" #include "hardware/efm32_dma.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Bit encoded input parameter to efm32_channel(). These encodings must fit in the - * an unsigned integer of type dma_config_t. +/* Bit encoded input parameter to efm32_channel(). + * These encodings must fit in the an unsigned integer of type dma_config_t. * * Current limitations/assumptions in the encoding: * @@ -70,12 +70,12 @@ # define EFM32_DMA_MEMINCR (1 << 13) /* 1=Increment memory address */ # define EFM32_DMA_NOINCR (0) /* 0=No memory address increment */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/* DMA_HANDLE provides an opaque reference that can be used to represent a DMA - * channel. +/* DMA_HANDLE provides an opaque reference that can be used to represent a + * DMA channel. */ typedef FAR void *DMA_HANDLE; @@ -122,16 +122,17 @@ struct efm32_dmaregs_s }; #endif -/* Type of 'config' argument passed to efm32_rxdmasetup() and efm32_txdmasetup. - * See EFM32_DMA_* encodings above. If these encodings exceed 16-bits, then this - * should be changed to a uint32_t. +/* Type of 'config' argument passed to efm32_rxdmasetup() and + * efm32_txdmasetup. See EFM32_DMA_* encodings above. + * If these encodings exceed 16-bits, then this should be changed to a + * uint32_t. */ typedef uint16_t dma_config_t; -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -144,19 +145,21 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: efm32_dmachannel * * Description: - * Allocate a DMA channel. This function gives the caller mutually exclusive - * access to a DMA channel. + * Allocate a DMA channel. + * This function gives the caller mutually exclusive access to a DMA + * channel. * - * If no DMA channel is available, then efm32_dmachannel() will wait until the - * holder of a channel relinquishes the channel by calling efm32_dmafree(). + * If no DMA channel is available, then efm32_dmachannel() will wait until + * the holder of a channel relinquishes the channel by calling + * efm32_dmafree(). * * Input Parameters: * None @@ -165,21 +168,23 @@ extern "C" * This function ALWAYS returns a non-NULL, void* DMA channel handle. * * Assumptions: - * - The caller can wait for a DMA channel to be freed if it is not available. + * - The caller can wait for a DMA channel to be freed if it is not + * available. * - ************************************************************************************/ + ****************************************************************************/ DMA_HANDLE efm32_dmachannel(void); -/************************************************************************************ +/**************************************************************************** * Name: efm32_dmafree * * Description: - * Release a DMA channel. If another thread is waiting for this DMA channel in a - * call to efm32_dmachannel, then this function will re-assign the DMA channel to - * that thread and wake it up. NOTE: The 'handle' used in this argument must - * NEVER be used again until efm32_dmachannel() is called again to re-gain access - * to the channel. + * Release a DMA channel. + * If another thread is waiting for this DMA channel in a call to + * efm32_dmachannel, then this function will re-assign the DMA channel to + * that thread and wake it up. NOTE: The 'handle' used in this argument + * must NEVER be used again until efm32_dmachannel() is called again to + * re-gain access to the channel. * * Returned Value: * None @@ -188,11 +193,11 @@ DMA_HANDLE efm32_dmachannel(void); * - The caller holds the DMA channel. * - There is no DMA in progress * - ************************************************************************************/ + ****************************************************************************/ void efm32_dmafree(DMA_HANDLE handle); -/************************************************************************************ +/**************************************************************************** * Name: efm32_rxdmasetup * * Description: @@ -205,12 +210,12 @@ void efm32_dmafree(DMA_HANDLE handle); * configured transfer size. * config - Channel configuration selections * - ************************************************************************************/ + ****************************************************************************/ void efm32_rxdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr, size_t nbytes, dma_config_t config); -/************************************************************************************ +/**************************************************************************** * Name: efm32_txdmasetup * * Description: @@ -223,12 +228,12 @@ void efm32_rxdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr, * configured transfer size. * config - Channel configuration selections * - ************************************************************************************/ + ****************************************************************************/ void efm32_txdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr, size_t nbytes, dma_config_t config); -/************************************************************************************ +/**************************************************************************** * Name: efm32_dmastart * * Description: @@ -238,25 +243,27 @@ void efm32_txdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr, * - DMA handle allocated by efm32_dmachannel() * - No DMA in progress * - ************************************************************************************/ + ****************************************************************************/ void efm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg); -/************************************************************************************ +/**************************************************************************** * Name: efm32_dmastop * * Description: - * Cancel the DMA. After efm32_dmastop() is called, the DMA channel is reset and - * efm32_dmasetup() must be called before efm32_dmastart() can be called again + * Cancel the DMA. + * After efm32_dmastop() is called, the DMA channel is reset and + * efm32_dmasetup() must be called before efm32_dmastart() can be called + * again * * Assumptions: * - DMA handle allocated by efm32_dmachannel() * - ************************************************************************************/ + ****************************************************************************/ void efm32_dmastop(DMA_HANDLE handle); -/************************************************************************************ +/**************************************************************************** * Name: efm32_dmasample * * Description: @@ -265,7 +272,7 @@ void efm32_dmastop(DMA_HANDLE handle); * Assumptions: * - DMA handle allocated by efm32_dmachannel() * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO void efm32_dmasample(DMA_HANDLE handle, struct efm32_dmaregs_s *regs); @@ -273,7 +280,7 @@ void efm32_dmasample(DMA_HANDLE handle, struct efm32_dmaregs_s *regs); # define efm32_dmasample(handle,regs) #endif -/************************************************************************************ +/**************************************************************************** * Name: efm32_dmadump * * Description: @@ -282,7 +289,7 @@ void efm32_dmasample(DMA_HANDLE handle, struct efm32_dmaregs_s *regs); * Assumptions: * - DMA handle allocated by efm32_dmachannel() * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO void efm32_dmadump(DMA_HANDLE handle, const struct efm32_dmaregs_s *regs, diff --git a/arch/arm/src/efm32/efm32_flash.c b/arch/arm/src/efm32/efm32_flash.c index 72a24cc6417..0ed5952d5ed 100644 --- a/arch/arm/src/efm32/efm32_flash.c +++ b/arch/arm/src/efm32/efm32_flash.c @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,17 +56,17 @@ * ****************************************************************************/ -/* Provides standard flash access functions, to be used by the flash mtd driver. - * The interface is defined in the include/nuttx/progmem.h +/* Provides standard flash access functions, to be used by the flash mtd + * driver. The interface is defined in the include/nuttx/progmem.h * * Requirements during write/erase operations on FLASH: * - HSI must be ON. * - Low Power Modes are not permitted during write/erase */ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -91,9 +91,9 @@ #if (defined(CONFIG_ARCH_CHIP_EFM32) && defined(CONFIG_EFM32_FLASHPROG)) -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_ARCH_RAMFUNCS # error "Flashing function should executed in ram" @@ -117,8 +117,8 @@ /* brief: * The timeout used while waiting for the flash to become ready after - * a write. This number indicates the number of iterations to perform before - * issuing a timeout. + * a write. This number indicates the number of iterations to perform + * before issuing a timeout. * note: * This timeout is set very large (in the order of 100x longer than * necessary). This is to avoid any corner cases. @@ -126,9 +126,9 @@ #define MSC_PROGRAM_TIMEOUT 10000000ul -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ void efm32_flash_unlock(void) { @@ -238,7 +238,6 @@ int __ramfunc__ msc_load_verify_address(uint32_t *address) status = getreg32(EFM32_MSC_STATUS); if (status & (MSC_STATUS_INVADDR | MSC_STATUS_LOCKED)) { - /* Check for invalid address */ if (status & MSC_STATUS_INVADDR) @@ -263,8 +262,8 @@ int __ramfunc__ msc_load_verify_address(uint32_t *address) * Description: * Perform data phase of FLASH write cycle. * - * This function performs the data phase of a Flash write operation by loading - * the given number of 32-bit words to the WDATA register. + * This function performs the data phase of a Flash write operation by + * loading the given number of 32-bit words to the WDATA register. * * note: * This function MUST be executed from RAM. Failure to execute this portion @@ -294,12 +293,14 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words, #if defined(_MSC_WRITECTRL_LPWRITE_MASK) && defined(_MSC_WRITECTRL_WDOUBLE_MASK) - /* If LPWRITE (Low Power Write) is NOT enabled, set WDOUBLE (Write Double word) */ + /* If LPWRITE (Low Power Write) is NOT enabled, + * set WDOUBLE (Write Double word) + */ if (!(getreg32(EFM32_MSC_WRITECTRL) & MSC_WRITECTRL_LPWRITE)) { - /* If the number of words to be written are odd, we need to align by writing - * a single word first, before setting the WDOUBLE bit. + /* If the number of words to be written are odd, we need to align by + * writing a single word first, before setting the WDOUBLE bit. */ if (num_words & 0x1) @@ -322,20 +323,22 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words, /* Clear double word option, in order to write one single word. */ - bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WDOUBLE_SHIFT, 0); + bitband_set_peripheral(EFM32_MSC_WRITECTRL, + _MSC_WRITECTRL_WDOUBLE_SHIFT, 0); /* Write first data word. */ putreg32(*data++, EFM32_MSC_WDATA); putreg32(MSC_WRITECMD_WRITEONCE, EFM32_MSC_WRITECMD); - /* Wait for the operation to finish. It may be required to change the - * WDOUBLE config after the initial write. It should not be changed - * while BUSY. + /* Wait for the operation to finish. It may be required to change + * the WDOUBLE config after the initial write. It should not be + * changed while BUSY. */ timeout = MSC_PROGRAM_TIMEOUT; - while ((getreg32(EFM32_MSC_STATUS) & MSC_STATUS_BUSY) && (timeout != 0)) + while ((getreg32(EFM32_MSC_STATUS) & MSC_STATUS_BUSY) && + (timeout != 0)) { timeout--; } @@ -353,11 +356,12 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words, ret = 0; } - /* Now we can set the double word option in order to write two words per - * data phase. + /* Now we can set the double word option in order to write two words + * per data phase. */ - bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WDOUBLE_SHIFT, 1); + bitband_set_peripheral(EFM32_MSC_WRITECTRL, + _MSC_WRITECTRL_WDOUBLE_SHIFT, 1); words_per_data_phase = 2; } else @@ -374,7 +378,6 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words, if (write_strategy_safe) { - /* Requires a system core clock at 1MHz or higher */ DEBUGASSERT(BOARD_SYSTEM_FREQUENCY >= 1000000); @@ -386,7 +389,8 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words, word_index++; if (words_per_data_phase == 2) { - while (!(getreg32(EFM32_MSC_STATUS) & MSC_STATUS_WDATAREADY)) + while (!(getreg32(EFM32_MSC_STATUS) & + MSC_STATUS_WDATAREADY)) { } @@ -439,7 +443,6 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words, while (word_index < num_words) { - /* Wait for the MSC to be ready for the next word. */ while (!(getreg32(EFM32_MSC_STATUS) & MSC_STATUS_WDATAREADY)) @@ -448,13 +451,13 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words, /* If the write to MSC->WDATA below missed the 30us timeout * and the following MSC_WRITECMD_WRITETRIG command arrived - * while MSC_STATUS_BUSY is 1, then the MSC_WRITECMD_WRITETRIG - * could be ignored by the MSC. In this case, - * MSC_STATUS_WORDTIMEOUT is set to 1 and MSC_STATUS_BUSY is - * 0. A new trigger is therefore needed here to complete write - * of data in MSC->WDATA. If WDATAREADY became high since - * entry into this loop, exit and continue to the next WDATA - * write. + * while MSC_STATUS_BUSY is 1, then the + * MSC_WRITECMD_WRITETRIG could be ignored by the MSC. + * In this case, MSC_STATUS_WORDTIMEOUT is set to 1 and + * MSC_STATUS_BUSY is 0. A new trigger is therefore needed + * here to complete write of data in MSC->WDATA. + * If WDATAREADY became high since entry into this loop, + * exit and continue to the next WDATA write. */ regval = getreg32(EFM32_MSC_STATUS); @@ -500,7 +503,8 @@ int __ramfunc__ msc_load_write_data(uint32_t *data, uint32_t num_words, /* Clear double word option, which should not be left on when returning. */ - bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WDOUBLE_SHIFT, 0); + bitband_set_peripheral(EFM32_MSC_WRITECTRL, + _MSC_WRITECTRL_WDOUBLE_SHIFT, 0); #endif @@ -511,7 +515,8 @@ void efm32_flash_lock(void) { /* Disable writing to the flash */ - bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 0); + bitband_set_peripheral(EFM32_MSC_WRITECTRL, + _MSC_WRITECTRL_WREN_SHIFT, 0); /* Unlock the EFM32_MSC */ @@ -527,7 +532,7 @@ uint32_t efm32_get_flash_size(void) regval = (regval & _DEVINFO_MEMINFO_SIZE_FLASH_MASK) \ >> _DEVINFO_MEMINFO_SIZE_FLASH_SHIFT; - return regval*1024; + return regval * 1024; } #endif @@ -544,7 +549,7 @@ uint32_t efm32_get_flash_page_size(void) return 512; } - return 1 << (regval+10); + return 1 << (regval + 10); } #endif @@ -552,13 +557,13 @@ uint32_t efm32_get_flash_page_size(void) #define EFM32_FLASH_NPAGES efm32_get_flash_page_nbr() uint32_t efm32_get_flash_page_nbr(void) { - return (EFM32_FLASH_SIZE/EFM32_FLASH_PAGESIZE); + return (EFM32_FLASH_SIZE / EFM32_FLASH_PAGESIZE); } #endif -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ size_t up_progmem_pagesize(size_t page) { @@ -586,7 +591,7 @@ ssize_t up_progmem_getpage(size_t addr) { #if (EFM32_FLASH_BASE != 0) if ((addr >= (EFM32_FLASH_BASE)) && \ - (addr < (EFM32_FLASH_BASE+EFM32_FLASH_SIZE))) + (addr < (EFM32_FLASH_BASE + EFM32_FLASH_SIZE))) { addr -= EFM32_FLASH_BASE; @@ -601,7 +606,7 @@ ssize_t up_progmem_getpage(size_t addr) #endif if ((addr >= (EFM32_USERDATA_BASE)) && \ - (addr < (EFM32_USERDATA_BASE+EFM32_USERDATA_SIZE))) + (addr < (EFM32_USERDATA_BASE + EFM32_USERDATA_SIZE))) { addr -= EFM32_USERDATA_BASE; @@ -630,7 +635,7 @@ size_t up_progmem_getaddress(size_t page) size_t up_progmem_neraseblocks(void) { - return EFM32_FLASH_NPAGES+EFM32_USERDATA_NPAGES; + return EFM32_FLASH_NPAGES + EFM32_USERDATA_NPAGES; } bool up_progmem_isuniform(void) @@ -645,7 +650,7 @@ ssize_t __ramfunc__ up_progmem_eraseblock(size_t block) uint32_t regval; irqstate_t flags; - if (block >= (EFM32_FLASH_NPAGES+EFM32_USERDATA_NPAGES)) + if (block >= (EFM32_FLASH_NPAGES + EFM32_USERDATA_NPAGES)) { return -EFAULT; } @@ -656,7 +661,8 @@ ssize_t __ramfunc__ up_progmem_eraseblock(size_t block) /* enable writing to the flash */ - bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 1); + bitband_set_peripheral(EFM32_MSC_WRITECTRL, + _MSC_WRITECTRL_WREN_SHIFT, 1); /* Load address */ @@ -688,7 +694,8 @@ ssize_t __ramfunc__ up_progmem_eraseblock(size_t block) /* Wait for the erase to complete */ timeout = MSC_PROGRAM_TIMEOUT; - while ((getreg32(EFM32_MSC_STATUS) & MSC_STATUS_BUSY) && (timeout != 0)) + while ((getreg32(EFM32_MSC_STATUS) & MSC_STATUS_BUSY) && + (timeout != 0)) { timeout--; } @@ -701,7 +708,8 @@ ssize_t __ramfunc__ up_progmem_eraseblock(size_t block) /* Disable writing to the MSC */ - bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 0); + bitband_set_peripheral(EFM32_MSC_WRITECTRL, + _MSC_WRITECTRL_WREN_SHIFT, 0); if (ret == 0) { @@ -731,14 +739,15 @@ ssize_t up_progmem_ispageerased(size_t page) size_t count; size_t bwritten = 0; - if (page >= (EFM32_FLASH_NPAGES+EFM32_USERDATA_NPAGES)) + if (page >= (EFM32_FLASH_NPAGES + EFM32_USERDATA_NPAGES)) { return -EFAULT; } /* Verify */ - for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page); + for (addr = up_progmem_getaddress(page), + count = up_progmem_pagesize(page); count; count--, addr++) { if (getreg8(addr) != 0xff) @@ -748,10 +757,10 @@ ssize_t up_progmem_ispageerased(size_t page) } return bwritten; - } -ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size) +ssize_t __ramfunc__ up_progmem_write(size_t addr, + const void *buf, size_t size) { int ret = 0; int word_count; @@ -779,18 +788,22 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size) /* enable writing to the flash */ - bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 1); + bitband_set_peripheral(EFM32_MSC_WRITECTRL, + _MSC_WRITECTRL_WREN_SHIFT, 1); /* Convert bytes to words */ num_words = num_bytes >> 2; - /* The following loop splits the data into chunks corresponding to flash pages. - * The address is loaded only once per page, because the hardware automatically - * increments the address internally for each data load inside a page. + /* The following loop splits the data into chunks corresponding to flash + * pages. The address is loaded only once per page, because the hardware + * automatically increments the address internally for each data load + * inside a page. */ - for (word_count = 0, p_data = (uint32_t *)buf; word_count < num_words; ) + for (word_count = 0, p_data = (uint32_t *)buf; + word_count < num_words; + ) { int page_bytes; ssize_t page_idx; @@ -798,7 +811,7 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size) /* Compute the number of words to write to the current page. */ - page_idx = up_progmem_getpage((size_t)address+(word_count << 2)); + page_idx = up_progmem_getpage((size_t)address + (word_count << 2)); if (page_idx < 0) { ret = -EINVAL; @@ -813,7 +826,7 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size) } page_words = (page_bytes - (((uint32_t) (address + word_count)) & \ - (page_bytes-1))) / sizeof(uint32_t); + (page_bytes - 1))) / sizeof(uint32_t); if (page_words > num_words - word_count) { @@ -822,7 +835,8 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size) flags = enter_critical_section(); - /* First we load address. The address is auto-incremented within a page. + /* First we load address. + * The address is auto-incremented within a page. * Therefore the address phase is only needed once for each page. */ @@ -854,7 +868,8 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size) /* Turn off double word write cycle support. */ - bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WDOUBLE_SHIFT, 0); + bitband_set_peripheral(EFM32_MSC_WRITECTRL, + _MSC_WRITECTRL_WDOUBLE_SHIFT, 0); #endif diff --git a/arch/arm/src/efm32/efm32_gpio.c b/arch/arm/src/efm32/efm32_gpio.c index 9d705900146..ff46abf14c7 100644 --- a/arch/arm/src/efm32/efm32_gpio.c +++ b/arch/arm/src/efm32/efm32_gpio.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/efm32/efm32_gpio.c * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -33,18 +33,18 @@ #include "hardware/efm32_gpio.h" #include "efm32_gpio.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #define __GPIO_INPUT (1 << 0) /* Bit 0: GPIO is an input */ #define __GPIO_OUTPUT (1 << 1) /* Bit 1: GPIO is an output */ #define __GPIO_DOUT (1 << 2) /* Bit 2: An input modified with DOUT setting */ #define __GPIO_DRIVE (1 << 3) /* Bit 3: An output with drive selection */ -/************************************************************************************ +/**************************************************************************** * Private Data - ************************************************************************************/ + ****************************************************************************/ static const uint8_t g_gpiomode[16] = { @@ -77,56 +77,56 @@ static const uint8_t g_gpiomode[16] = * by DRIVEMODE */ }; -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: efm32_getport * * Description: * Extract the encoded port number * - ************************************************************************************/ + ****************************************************************************/ static inline uint8_t efm32_getport(gpio_pinset_t cfgset) { return (uint8_t)((cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT); } -/************************************************************************************ +/**************************************************************************** * Name: efm32_getpin * * Description: * Extract the encoded pin number * - ************************************************************************************/ + ****************************************************************************/ static inline uint8_t efm32_getpin(gpio_pinset_t cfgset) { return (uint8_t)((cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT); } -/************************************************************************************ +/**************************************************************************** * Name: efm32_getmode * * Description: * Extract the encoded pin mode * - ************************************************************************************/ + ****************************************************************************/ static inline uint8_t efm32_getmode(gpio_pinset_t cfgset) { return (uint8_t)((cfgset & GPIO_MODE_MASK) >> GPIO_MODE_SHIFT); } -/************************************************************************************ +/**************************************************************************** * Name: efm32_getdrive * * Description: * Extract the output drive strength from the encoded configuration * - ************************************************************************************/ + ****************************************************************************/ static uint8_t efm32_getdrive(uint8_t mode, gpio_pinset_t cfgset) { @@ -140,22 +140,24 @@ static uint8_t efm32_getdrive(uint8_t mode, gpio_pinset_t cfgset) } } -/************************************************************************************ +/**************************************************************************** * Name: efm32_setdrive * * Description: * Set the GPIO output drive strength * - ************************************************************************************/ + ****************************************************************************/ static inline void efm32_setdrive(uintptr_t base, uint8_t pin, uint8_t drive) { /* Select drive mode for all pins on port configured with alternate drive * strength. * - * REVISIT: Is there any sane way to manage this for multiple pins in the port + * REVISIT: + * Is there any sane way to manage this for multiple pins in the port * with different drive values? */ + if (drive != _GPIO_DRIVE_STANDARD) { putreg32((uint32_t)drive << _GPIO_P_CTRL_DRIVEMODE_SHIFT, @@ -163,13 +165,13 @@ static inline void efm32_setdrive(uintptr_t base, uint8_t pin, uint8_t drive) } } -/************************************************************************************ +/**************************************************************************** * Name: efm32_getdout * * Description: * Extract the encoded port number * - ************************************************************************************/ + ****************************************************************************/ static inline bool efm32_getdout(uint8_t mode, gpio_pinset_t cfgset) { @@ -187,13 +189,13 @@ static inline bool efm32_getdout(uint8_t mode, gpio_pinset_t cfgset) } } -/************************************************************************************ +/**************************************************************************** * Name: efm32_setdout * * Description: * Set the GPIO output data value * - ************************************************************************************/ + ****************************************************************************/ static inline void efm32_setdout(uintptr_t base, uint8_t pin, bool dout) { @@ -209,26 +211,27 @@ static inline void efm32_setdout(uintptr_t base, uint8_t pin, bool dout) } } -/************************************************************************************ +/**************************************************************************** * Name: efm32_getdin * * Description: * Get the GPIO input value * - ************************************************************************************/ + ****************************************************************************/ static inline bool efm32_getdin(uintptr_t base, uint8_t pin) { - return ((getreg32(base + EFM32_GPIO_Pn_DIN_OFFSET) & ((uint32_t)1 << pin)) != 0); + return ((getreg32(base + EFM32_GPIO_Pn_DIN_OFFSET) & + ((uint32_t)1 << pin)) != 0); } -/************************************************************************************ +/**************************************************************************** * Name: efm32_setmode * * Description: * Set the GPIO mode * - ************************************************************************************/ + ****************************************************************************/ static inline void efm32_setmode(uintptr_t base, uint8_t pin, uint8_t mode) { @@ -257,17 +260,17 @@ static inline void efm32_setmode(uintptr_t base, uint8_t pin, uint8_t mode) putreg32(regval, regaddr); } -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: efm32_configgpio * * Description: * Configure a PIO pin based on bit-encoded description of the pin. * - ************************************************************************************/ + ****************************************************************************/ int efm32_configgpio(gpio_pinset_t cfgset) { @@ -301,13 +304,13 @@ int efm32_configgpio(gpio_pinset_t cfgset) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: efm32_unconfiggpio * * Description: * unConfigure a PIO pin based on bit-encoded description of the pin. * - ************************************************************************************/ + ****************************************************************************/ int efm32_unconfiggpio(gpio_pinset_t cfgset) { @@ -317,13 +320,13 @@ int efm32_unconfiggpio(gpio_pinset_t cfgset) return efm32_configgpio(cfgset); } -/************************************************************************************ +/**************************************************************************** * Name: efm32_gpiowrite * * Description: * Write one or zero to the selected PIO pin * - ************************************************************************************/ + ****************************************************************************/ void efm32_gpiowrite(gpio_pinset_t pinset, bool value) { @@ -342,13 +345,13 @@ void efm32_gpiowrite(gpio_pinset_t pinset, bool value) efm32_setdout(base, pin, value); } -/************************************************************************************ +/**************************************************************************** * Name: efm32_gpioread * * Description: * Read one or zero from the selected PIO pin * - ************************************************************************************/ + ****************************************************************************/ bool efm32_gpioread(gpio_pinset_t pinset) { @@ -367,13 +370,14 @@ bool efm32_gpioread(gpio_pinset_t pinset) return efm32_getdin(base, pin); } -/************************************************************************************ +/**************************************************************************** * Function: efm32_dumpgpio * * Description: - * Dump all PIO registers associated with the base address of the provided pinset. + * Dump all PIO registers associated with the base address of the provided + * pinset. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO int efm32_dumpgpio(uint32_t pinset, const char *msg) diff --git a/arch/arm/src/efm32/efm32_gpio.h b/arch/arm/src/efm32/efm32_gpio.h index 7edb56894f9..282ee99ff9a 100644 --- a/arch/arm/src/efm32/efm32_gpio.h +++ b/arch/arm/src/efm32/efm32_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/efm32/efm32_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,29 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_EFM32_GPIO_H #define __ARCH_ARM_SRC_EFM32_EFM32_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ #define EFM32_NGPIO 5 /* (5) GPIOA-F */ -/* Bit-encoded input to efm32_configgpio() *******************************************/ +/* Bit-encoded input to efm32_configgpio() **********************************/ /* 16-bit Encoding: * @@ -106,7 +107,8 @@ # define GPIO_OUTPUT_WIREDAND_DRIVE_PULLUP_FILTER \ (15 << GPIO_MODE_SHIFT) -/* If the pin is an PIO output, then this identifies the initial output value: +/* If the pin is an PIO output, then this identifies the initial output + * value: * * .... V... .... .... */ @@ -182,23 +184,23 @@ # define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) # define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ /* Must be big enough to hold the 16-bit encoding */ typedef uint16_t gpio_pinset_t; -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -209,17 +211,18 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: efm32_gpioirqinitialize * * Description: - * Initialize logic to support a second level of interrupt decoding for PIO pins. + * Initialize logic to support a second level of interrupt decoding for PIO + * pins. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_EFM32_GPIO_IRQ void efm32_gpioirqinitialize(void); @@ -227,53 +230,53 @@ void efm32_gpioirqinitialize(void); # define efm32_gpioirqinitialize() #endif -/************************************************************************************ +/**************************************************************************** * Name: efm32_configgpio * * Description: * Configure a PIO pin based on bit-encoded description of the pin. * - ************************************************************************************/ + ****************************************************************************/ int efm32_configgpio(gpio_pinset_t cfgset); -/************************************************************************************ +/**************************************************************************** * Name: efm32_unconfiggpio * * Description: * UnConfigure a PIO pin based on bit-encoded description of the pin. * - ************************************************************************************/ + ****************************************************************************/ int efm32_unconfiggpio(gpio_pinset_t cfgset); -/************************************************************************************ +/**************************************************************************** * Name: efm32_gpiowrite * * Description: * Write one or zero to the selected PIO pin * - ************************************************************************************/ + ****************************************************************************/ void efm32_gpiowrite(gpio_pinset_t pinset, bool value); -/************************************************************************************ +/**************************************************************************** * Name: efm32_gpioread * * Description: * Read one or zero from the selected PIO pin * - ************************************************************************************/ + ****************************************************************************/ bool efm32_gpioread(gpio_pinset_t pinset); -/************************************************************************************ +/**************************************************************************** * Name: efm32_gpioirq * * Description: * Configure an interrupt for the specified PIO pin. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_EFM32_GPIO_IRQ void efm32_gpioirq(gpio_pinset_t pinset); @@ -281,13 +284,13 @@ void efm32_gpioirq(gpio_pinset_t pinset); # define efm32_gpioirq(pinset) #endif -/************************************************************************************ +/**************************************************************************** * Name: efm32_gpioirqenable * * Description: * Enable the interrupt for specified PIO IRQ * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_EFM32_GPIO_IRQ void efm32_gpioirqenable(int irq); @@ -295,13 +298,13 @@ void efm32_gpioirqenable(int irq); # define efm32_gpioirqenable(irq) #endif -/************************************************************************************ +/**************************************************************************** * Name: efm32_gpioirqdisable * * Description: * Disable the interrupt for specified PIO IRQ * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_EFM32_GPIO_IRQ void efm32_gpioirqdisable(int irq); @@ -309,13 +312,13 @@ void efm32_gpioirqdisable(int irq); # define efm32_gpioirqdisable(irq) #endif -/************************************************************************************ +/**************************************************************************** * Name: efm32_gpioirqclear * * Description: * clear the interrupt for specified PIO IRQ * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_EFM32_GPIO_IRQ void efm32_gpioirqclear(int irq); @@ -323,13 +326,14 @@ void efm32_gpioirqclear(int irq); # define efm32_gpioirqclear(irq) #endif -/************************************************************************************ +/**************************************************************************** * Function: efm32_dumpgpio * * Description: - * Dump all PIO registers associated with the base address of the provided pinset. + * Dump all PIO registers associated with the base address of the provided + * pinset. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO int efm32_dumpgpio(uint32_t pinset, const char *msg); diff --git a/arch/arm/src/efm32/efm32_gpioirq.c b/arch/arm/src/efm32/efm32_gpioirq.c index fb31324cc25..53aaab3b390 100644 --- a/arch/arm/src/efm32/efm32_gpioirq.c +++ b/arch/arm/src/efm32/efm32_gpioirq.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/efm32/efm32_gpioirq.c * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -38,47 +38,47 @@ #ifdef CONFIG_EFM32_GPIO_IRQ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: efm32_getport * * Description: * Extract the encoded port number * - ************************************************************************************/ + ****************************************************************************/ static inline uint8_t efm32_getport(gpio_pinset_t cfgset) { return (uint8_t)((cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT); } -/************************************************************************************ +/**************************************************************************** * Name: efm32_getpin * * Description: * Extract the encoded pin number * - ************************************************************************************/ + ****************************************************************************/ static inline uint8_t efm32_getpin(gpio_pinset_t cfgset) { return (uint8_t)((cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT); } -/************************************************************************************ +/**************************************************************************** * Name: efm32_gpio_interrupt * * Description: * Common GPIO interrupt handling logic * - ************************************************************************************/ + ****************************************************************************/ static int efm32_gpio_interrupt(uint32_t mask, void *context) { @@ -110,47 +110,50 @@ static int efm32_gpio_interrupt(uint32_t mask, void *context) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: efm32_even_interrupt * * Description: * Even GPIO interrupt handling logic * - ************************************************************************************/ + ****************************************************************************/ static int efm32_even_interrupt(int irq, void *context, FAR void *arg) { return efm32_gpio_interrupt(0x00005555, context); } -/************************************************************************************ +/**************************************************************************** * Name: efm32_even_interrupt * * Description: * Even GPIO interrupt handling logic * - ************************************************************************************/ + ****************************************************************************/ static int efm32_odd_interrupt(int irq, void *context, FAR void *arg) { return efm32_gpio_interrupt(0x0000aaaa, context); } -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: efm32_gpioirqinitialize * * Description: - * Initialize logic to support a second level of interrupt decoding for PIO pins. + * Initialize logic to support a second level of interrupt decoding for PIO + * pins. * - ************************************************************************************/ + ****************************************************************************/ void efm32_gpioirqinitialize(void) { - /* Initialize GPIO interrupt registers, disabling GPIO interrupts at the source */ + /* Initialize GPIO interrupt registers, disabling GPIO interrupts at the + * source + */ putreg32(0, EFM32_GPIO_EXTIRISE); putreg32(0, EFM32_GPIO_EXTIFALL); @@ -167,13 +170,13 @@ void efm32_gpioirqinitialize(void) up_enable_irq(EFM32_IRQ_GPIO_EVEN); } -/************************************************************************************ +/**************************************************************************** * Name: efm32_gpioirq * * Description: * Configure an interrupt for the specified PIO pin. * - ************************************************************************************/ + ****************************************************************************/ void efm32_gpioirq(gpio_pinset_t pinset) { @@ -246,17 +249,16 @@ void efm32_gpioirq(gpio_pinset_t pinset) leave_critical_section(flags); } -/************************************************************************************ +/**************************************************************************** * Name: efm32_gpioirqenable * * Description: * Enable the interrupt for specified PIO IRQ * - ************************************************************************************/ + ****************************************************************************/ void efm32_gpioirqenable(int irq) { - if (irq >= EFM32_IRQ_EXTI0 && irq <= EFM32_IRQ_EXTI15) { /* Enable the interrupt associated with the pin */ @@ -277,13 +279,13 @@ void efm32_gpioirqenable(int irq) } } -/************************************************************************************ +/**************************************************************************** * Name: efm32_gpioirqdisable * * Description: * Disable the interrupt for specified PIO IRQ * - ************************************************************************************/ + ****************************************************************************/ void efm32_gpioirqdisable(int irq) { @@ -308,13 +310,13 @@ void efm32_gpioirqdisable(int irq) } } -/************************************************************************************ +/**************************************************************************** * Name: efm32_gpioirqclear * * Description: * Disable the interrupt for specified PIO IRQ * - ************************************************************************************/ + ****************************************************************************/ void efm32_gpioirqclear(int irq) { diff --git a/arch/arm/src/efm32/efm32_lowputc.c b/arch/arm/src/efm32/efm32_lowputc.c index ec52eea9a93..1cb4d3986c2 100644 --- a/arch/arm/src/efm32/efm32_lowputc.c +++ b/arch/arm/src/efm32/efm32_lowputc.c @@ -181,7 +181,8 @@ static void efm32_uart_setbaud(uintptr_t base, uint32_t baud) * CLKDIV = (256 * fHFPERCLK) / (oversample * baud) - 256 */ - clkdiv = ((uint64_t)BOARD_HFPERCLK_FREQUENCY << 8) / ((uint64_t)baud * oversample); + clkdiv = ((uint64_t)BOARD_HFPERCLK_FREQUENCY << 8) / + ((uint64_t)baud * oversample); if (clkdiv > 256) { clkdiv -= 256; @@ -490,7 +491,8 @@ void efm32_lowputc(uint32_t ch) * buffer is half-full or empty. */ - while ((getreg32(CONSOLE_BASE + EFM32_USART_STATUS_OFFSET) & USART_STATUS_TXBL) == 0); + while ((getreg32(CONSOLE_BASE + EFM32_USART_STATUS_OFFSET) & + USART_STATUS_TXBL) == 0); /* Then send the character */ @@ -505,7 +507,8 @@ void efm32_lowputc(uint32_t ch) * buffer is half-full or empty. */ - while ((getreg32(CONSOLE_BASE + EFM32_LEUART_STATUS_OFFSET) & LEUART_STATUS_TXBL) == 0); + while ((getreg32(CONSOLE_BASE + EFM32_LEUART_STATUS_OFFSET) & + LEUART_STATUS_TXBL) == 0); /* Then send the character */ @@ -628,7 +631,8 @@ void efm32_uartconfigure(uintptr_t base, uint32_t baud, unsigned int parity, /* Enable the U[S]ART */ - putreg32(USART_CMD_RXEN | USART_CMD_TXEN, base + EFM32_USART_CMD_OFFSET); + putreg32(USART_CMD_RXEN | USART_CMD_TXEN, + base + EFM32_USART_CMD_OFFSET); } #endif @@ -641,7 +645,8 @@ void efm32_uartconfigure(uintptr_t base, uint32_t baud, unsigned int parity, ****************************************************************************/ #ifdef HAVE_LEUART_DEVICE -void efm32_leuartconfigure(uintptr_t base, uint32_t baud, unsigned int parity, +void efm32_leuartconfigure(uintptr_t base, + uint32_t baud, unsigned int parity, unsigned int nbits, bool stop2) { uint32_t regval = 0; @@ -682,7 +687,6 @@ void efm32_leuartconfigure(uintptr_t base, uint32_t baud, unsigned int parity, case 2: regval |= LEUART_CTRL_PARITY_EVEN; break; - } /* Configure stop bits */ @@ -704,7 +708,8 @@ void efm32_leuartconfigure(uintptr_t base, uint32_t baud, unsigned int parity, /* Enable the LEUART */ - putreg32(LEUART_CMD_RXEN | LEUART_CMD_TXEN, base + EFM32_LEUART_CMD_OFFSET); + putreg32(LEUART_CMD_RXEN | LEUART_CMD_TXEN, + base + EFM32_LEUART_CMD_OFFSET); } #endif @@ -759,11 +764,14 @@ void efm32_leuart_reset(uintptr_t base) base + EFM32_LEUART_CMD_OFFSET); putreg32(_LEUART_CTRL_RESETVALUE, base + EFM32_LEUART_CTRL_OFFSET); putreg32(_LEUART_CLKDIV_RESETVALUE, base + EFM32_LEUART_CLKDIV_OFFSET); - putreg32(_LEUART_STARTFRAME_RESETVALUE, base + EFM32_LEUART_STARTFRAME_OFFSET); - putreg32(_LEUART_SIGFRAME_RESETVALUE, base + EFM32_LEUART_SIGFRAME_OFFSET); + putreg32(_LEUART_STARTFRAME_RESETVALUE, + base + EFM32_LEUART_STARTFRAME_OFFSET); + putreg32(_LEUART_SIGFRAME_RESETVALUE, + base + EFM32_LEUART_SIGFRAME_OFFSET); putreg32(_LEUART_IEN_RESETVALUE, base + EFM32_LEUART_IEN_OFFSET); putreg32(_LEUART_IFC_MASK, base + EFM32_LEUART_IFC_OFFSET); - putreg32(_LEUART_PULSECTRL_RESETVALUE, base + EFM32_LEUART_PULSECTRL_OFFSET); + putreg32(_LEUART_PULSECTRL_RESETVALUE, + base + EFM32_LEUART_PULSECTRL_OFFSET); #if defined(EFM32_LEUART_INPUT_OFFSET) putreg32(_LEUART_INPUT_RESETVALUE, base + EFM32_LEUART_INPUT_OFFSET); #endif diff --git a/arch/arm/src/efm32/efm32_lowputc.h b/arch/arm/src/efm32/efm32_lowputc.h index 5459f596248..6f0cbc3ef5c 100644 --- a/arch/arm/src/efm32/efm32_lowputc.h +++ b/arch/arm/src/efm32/efm32_lowputc.h @@ -32,7 +32,7 @@ #include "efm32_config.h" /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ /**************************************************************************** @@ -82,7 +82,8 @@ void efm32_uartconfigure(uintptr_t base, uint32_t baud, unsigned int parity, ****************************************************************************/ #ifdef HAVE_LEUART_DEVICE -void efm32_leuartconfigure(uintptr_t base, uint32_t baud, unsigned int parity, +void efm32_leuartconfigure(uintptr_t base, uint32_t baud, + unsigned int parity, unsigned int nbits, bool stop2); #endif diff --git a/arch/arm/src/efm32/efm32_pm.h b/arch/arm/src/efm32/efm32_pm.h index f62b3616238..c3dd20f4b7e 100644 --- a/arch/arm/src/efm32/efm32_pm.h +++ b/arch/arm/src/efm32/efm32_pm.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/efm32/efm32_pm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_EFM32_PM_H #define __ARCH_ARM_SRC_EFM32_EFM32_PM_H @@ -119,8 +119,8 @@ int efm32_pmstandby(void); * sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is * executed, the MCU enters Sleep mode as soon as it * exits the lowest priority ISR. - * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep mode - * as soon as WFI or WFE instruction is executed. + * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep + * mode as soon as WFI or WFE instruction is executed. * Returned Value: * Zero means that the STOP was successfully entered and the system has * been re-awakened. The internal voltage regulator is back to its diff --git a/arch/arm/src/efm32/efm32_pwm.c b/arch/arm/src/efm32/efm32_pwm.c index 8382fa6b9b4..be3b7189a33 100644 --- a/arch/arm/src/efm32/efm32_pwm.c +++ b/arch/arm/src/efm32/efm32_pwm.c @@ -71,7 +71,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* PWM/Timer Definitions ****************************************************/ + /* The following definitions are used to identify the various time types */ /* Debug ********************************************************************/ @@ -85,6 +87,7 @@ /**************************************************************************** * Private Types ****************************************************************************/ + /* This structure represents the state of one PWM timer */ struct efm32_pwmtimer_s @@ -111,6 +114,7 @@ struct efm32_pwmtimer_s /**************************************************************************** * Static Function Prototypes ****************************************************************************/ + /* Register access */ static uint32_t pwm_getreg(struct efm32_pwmtimer_s *priv, int offset); @@ -159,7 +163,10 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, /**************************************************************************** * Private Data ****************************************************************************/ -/* This is the list of lower half PWM driver methods used by the upper half driver */ + +/* This is the list of lower half PWM driver methods used by the upper half + * driver + */ static const struct pwm_ops_s g_pwmops = { @@ -273,7 +280,8 @@ static uint32_t pwm_getreg(struct efm32_pwmtimer_s *priv, int offset) * ****************************************************************************/ -static void pwm_putreg(struct efm32_pwmtimer_s *priv, int offset, uint32_t value) +static void pwm_putreg(struct efm32_pwmtimer_s *priv, + int offset, uint32_t value) { putreg32(value, priv->base + offset); } @@ -412,7 +420,8 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv, regval = (info->duty * pwm_getreg(priv, EFM32_TIMER_TOP_OFFSET)) >> 16; pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CCV_OFFSET, regval); - //pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CCVB_OFFSET, regval); + + /* pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CCVB_OFFSET, regval); */ regval = (_TIMER_CC_CTRL_MODE_PWM << _TIMER_CC_CTRL_MODE_SHIFT) | \ (_TIMER_CC_CTRL_CMOA_CLEAR << _TIMER_CC_CTRL_CMOA_SHIFT) | \ @@ -511,7 +520,9 @@ static int pwm_interrupt(int irq, void *context, FAR void *arg) pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint32_t)priv->curr - 1); } - /* Now all of the time critical stuff is done so we can do some debug output */ + /* Now all of the time critical stuff is done so we can do some debug + * output + */ pwminfo("Update interrupt SR: %04x prev: %d curr: %d count: %d\n", regval, priv->prev, priv->curr, priv->count); @@ -574,7 +585,6 @@ static uint8_t pwm_pulsecount(uint32_t count) } #endif - /**************************************************************************** * Name: pwm_setup * @@ -771,7 +781,8 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) * ****************************************************************************/ -static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg) +static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, + int cmd, unsigned long arg) { #ifdef CONFIG_DEBUG_PWM_INFO FAR struct efm32_pwmtimer_s *priv = (FAR struct efm32_pwmtimer_s *)dev; diff --git a/arch/arm/src/efm32/efm32_pwm.h b/arch/arm/src/efm32/efm32_pwm.h index 0b9c6c220a0..f94fd01d488 100644 --- a/arch/arm/src/efm32/efm32_pwm.h +++ b/arch/arm/src/efm32/efm32_pwm.h @@ -53,12 +53,14 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Configuration **************************************************************/ + +/* Configuration ************************************************************/ + /* Timer devices may be used for different purposes. One special purpose is * to generate modulated outputs for such things as motor control. - * If CONFIG_EFM32_TIMERn is defined then the CONFIG_EFM32_TIMERn_PWM must also - * be defined to indicate that timer "n" is intended to be used for pulsed - * output signal generation. + * If CONFIG_EFM32_TIMERn is defined then the CONFIG_EFM32_TIMERn_PWM must + * also be defined to indicate that timer "n" is intended to be used for + * pulsed output signal generation. */ #ifndef CONFIG_EFM32_TIMER0 @@ -84,8 +86,8 @@ #include #include "hardware/efm32_timer.h" -/* For each timer that is enabled for PWM usage, we need the following additional - * configuration settings: +/* For each timer that is enabled for PWM usage, we need the following + * additional configuration settings: * * CONFIG_EFM32_TIMERx_CHANNEL - Specifies the timer output channel {0,1,3} * BOARD_PWM_TIMERx_PINCFG - Specifies the timer output pin configuration. @@ -94,21 +96,21 @@ * BOARD_PWM_TIMERx_PINLOC - Specifies the timer output pin location. * example : _TIMER_ROUTE_LOCATION_LOC4 * - * BOARD_PWM_TIMERx_CLKIN - Specifies the timer input clock frequency (in Hz). - * example : 48e6 for 48MHz + * BOARD_PWM_TIMERx_CLKIN - Specifies the timer input clock frequency + * (in Hz). example : 48e6 for 48MHz * * NOTE: The EFM32 timers are each capable of generating different signals on * each of the four channels with different duty cycles. That capability is * not supported by this driver: Only one output channel per timer. */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -121,11 +123,11 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: efm32_pwminitialize * * Description: @@ -140,7 +142,7 @@ extern "C" * On success, a pointer to the EFM32 lower half PWM driver is returned. * NULL is returned on any failure. * - ************************************************************************************/ + ****************************************************************************/ FAR struct pwm_lowerhalf_s *efm32_pwminitialize(int timer); diff --git a/arch/arm/src/efm32/efm32_rmu.c b/arch/arm/src/efm32/efm32_rmu.c index 6413e9f0df3..da5697c8f19 100644 --- a/arch/arm/src/efm32/efm32_rmu.c +++ b/arch/arm/src/efm32/efm32_rmu.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/efm32/efm32_rmu.c * * Copyright (C) 2015 Pierre-Noel Bouteville. All rights reserved. @@ -31,11 +31,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -55,13 +55,13 @@ #include "efm32_rmu.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Private Types - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_EFM32_RMU_DEBUG) && defined(CONFIG_DEBUG_WARN) typedef struct @@ -72,9 +72,9 @@ typedef struct } efm32_reset_cause_list_t; #endif -/************************************************************************************ +/**************************************************************************** * Private Data - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_EFM32_RMU_DEBUG) && defined(CONFIG_DEBUG_WARN) static efm32_reset_cause_list_t efm32_reset_cause_list[] = @@ -91,12 +91,12 @@ static efm32_reset_cause_list_t efm32_reset_cause_list[] = }, { 0x0004, /* 0bXXXX XXXX XXX0 0100 */ - 0x001F, /* 0bXXXX XXXX XXX1 1111 */ + 0x001f, /* 0bXXXX XXXX XXX1 1111 */ "A Brown-out has been detected on the regulated power." }, { 0x0008, /* 0bXXXX XXXX XXXX 1X00 */ - 0x000B, /* 0bXXXX XXXX XXXX 1X11 */ + 0x000b, /* 0bXXXX XXXX XXXX 1X11 */ "An external reset has been applied." }, { @@ -106,12 +106,12 @@ static efm32_reset_cause_list_t efm32_reset_cause_list[] = }, { 0x0020, /* 0bXXXX X000 0010 0000 */ - 0x07FF, /* 0bXXXX X111 1111 1111 */ + 0x07ff, /* 0bXXXX X111 1111 1111 */ "A lockup reset has occurred." }, { 0x0040, /* 0bXXXX X000 01X0 0000 */ - 0x07DF, /* 0bXXXX X111 11X1 1111 */ + 0x07df, /* 0bXXXX X111 11X1 1111 */ "A system request reset has occurred." }, { @@ -122,16 +122,16 @@ static efm32_reset_cause_list_t efm32_reset_cause_list[] = { 0x0180, /* 0bXXXX X001 1XX0 0XX0 */ 0x0799, /* 0bXXXX X111 1XX1 1XX1 */ - "The system has woken up from EM4 on an EM4 wakeup reset request from pin." + "The system woke up from EM4 on an EM4 wakeup reset request from pin." }, { 0x0200, /* 0bXXXX X01X XXX0 0000 */ - 0x061F, /* 0bXXXX X11X XXX1 1111 */ + 0x061f, /* 0bXXXX X11X XXX1 1111 */ "A Brown-out has been detected on Analog Power Domain 0 (AVDD0)." }, { 0x0400, /* 0bXXXX X10X XXX0 0000 */ - 0x061F, /* 0bXXXX X11X XXX1 1111 */ + 0x061f, /* 0bXXXX X11X XXX1 1111 */ "A Brown-out has been detected on Analog Power Domain 1 (AVDD1)." }, { @@ -162,23 +162,23 @@ static efm32_reset_cause_list_t efm32_reset_cause_list[] = }; #endif -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ /* Variable old last reset cause of cpu. */ uint32_t g_efm32_rstcause; -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: efm32_reset_cause_list_str * * Description: @@ -189,12 +189,13 @@ uint32_t g_efm32_rstcause; * idx: Use to keep in maind reset cause decoding position. * set *idx to zero before first call. * - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_EFM32_RMU_DEBUG) && defined(CONFIG_DEBUG_WARN) const char *efm32_reset_cause_list_str(uint32_t reg, unsigned int *idx) { - int len = sizeof(efm32_reset_cause_list)/sizeof(efm32_reset_cause_list[0]); + int len = sizeof(efm32_reset_cause_list) / + sizeof(efm32_reset_cause_list[0]); efm32_reset_cause_list_t *ptr = NULL; do @@ -218,13 +219,14 @@ const char *efm32_reset_cause_list_str(uint32_t reg, unsigned int *idx) } #endif -/************************************************************************************ +/**************************************************************************** * Name: efm32_rmu_initialize * * Description: - * Store reset cause into g_efm32_rstcause then clear reset cause register. + * Store reset cause into g_efm32_rstcause then clear reset cause + * register. * - ************************************************************************************/ + ****************************************************************************/ void efm32_rmu_initialize(void) { diff --git a/arch/arm/src/efm32/efm32_rmu.h b/arch/arm/src/efm32/efm32_rmu.h index 7fb44beaa4b..2ab4206ce49 100644 --- a/arch/arm/src/efm32/efm32_rmu.h +++ b/arch/arm/src/efm32/efm32_rmu.h @@ -48,6 +48,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ #ifndef CONFIG_DEBUG_ERROR @@ -73,18 +74,20 @@ extern uint32_t g_efm32_rstcause; /**************************************************************************** * Public Function Prototypes ****************************************************************************/ -/************************************************************************************ + +/**************************************************************************** * Name: efm32_rmu_initialize * * Description: - * Store reset cause into g_efm32_rstcause then clear reset cause register. + * Store reset cause into g_efm32_rstcause then clear reset cause + * register. * - ************************************************************************************/ + ****************************************************************************/ void efm32_rmu_initialize(void); -const char* efm32_reset_cause_list_str(uint32_t reg, unsigned int *idx); +const char *efm32_reset_cause_list_str(uint32_t reg, unsigned int *idx); -/************************************************************************************ +/**************************************************************************** * Name: efm32_reset_cause_list_str * * Description: @@ -95,7 +98,7 @@ const char* efm32_reset_cause_list_str(uint32_t reg, unsigned int *idx); * idx: Use to keep in maind reset cause decoding position. * set *idx to zero before first call. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_EFM32_RMU_DEBUG const char *efm32_reset_cause_list_str(uint32_t reg, unsigned int *idx); diff --git a/arch/arm/src/efm32/efm32_rtc.h b/arch/arm/src/efm32/efm32_rtc.h index bc54f22a58d..6cb7a65bd4c 100644 --- a/arch/arm/src/efm32/efm32_rtc.h +++ b/arch/arm/src/efm32/efm32_rtc.h @@ -39,7 +39,7 @@ typedef void (*alarmcb_t)(void); * Pre-processor Definitions ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: efm32_rtc_setalarm * * Description: @@ -52,14 +52,14 @@ typedef void (*alarmcb_t)(void); * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_ALARM struct timespec; int efm32_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback); #endif -/************************************************************************************ +/**************************************************************************** * Name: efm32_rtc_cancelalarm * * Description: @@ -71,7 +71,7 @@ int efm32_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback); * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_ALARM int efm32_rtc_cancelalarm(void); diff --git a/arch/arm/src/efm32/efm32_rtc_burtc.c b/arch/arm/src/efm32/efm32_rtc_burtc.c index 207fd6e5d91..26b52a54bff 100644 --- a/arch/arm/src/efm32/efm32_rtc_burtc.c +++ b/arch/arm/src/efm32/efm32_rtc_burtc.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/efm32/efm32_rtc_burtc.c * * Copyright (C) 2015 Pierre-Noel Bouteville. All rights reserved. @@ -31,11 +31,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -60,10 +60,11 @@ #include "efm32_bitband.h" #include "clock/clock.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ #ifdef CONFIG_RTC_HIRES # ifndef CONFIG_RTC_FREQUENCY @@ -130,9 +131,9 @@ #define __CNT_CARRY_REG EFM32_BURTC_RET_REG(0) #define __CNT_ZERO_REG EFM32_BURTC_RET_REG(1) -/************************************************************************************ +/**************************************************************************** * Private Data - ************************************************************************************/ + ****************************************************************************/ /* Callback to use when the alarm expires */ @@ -140,9 +141,9 @@ static alarmcb_t g_alarmcb; #endif -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ /* Variable determines the state of the LSE oscillator. * Possible errors: @@ -156,11 +157,11 @@ bool g_efm32_burtc_reseted = false; volatile bool g_rtc_enabled = false; -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: efm32_rtc_interrupt * * Description: @@ -173,7 +174,7 @@ volatile bool g_rtc_enabled = false; * Returned Value: * Zero (OK) on success; A negated errno value on failure. * - ************************************************************************************/ + ****************************************************************************/ static int efm32_rtc_burtc_interrupt(int irq, void *context, FAR void *arg) { @@ -210,12 +211,13 @@ static int efm32_rtc_burtc_interrupt(int irq, void *context, FAR void *arg) /* Clear pending flags, leave RSF high */ - putreg32(BURTC_IFC_OF | BURTC_IFC_COMP0 | BURTC_IFC_LFXOFAIL, EFM32_BURTC_IFC); + putreg32(BURTC_IFC_OF | BURTC_IFC_COMP0 | + BURTC_IFC_LFXOFAIL, EFM32_BURTC_IFC); return 0; } -/************************************************************************************ +/**************************************************************************** * Name: efm32_burtc_init * * Description: @@ -225,7 +227,7 @@ static int efm32_rtc_burtc_interrupt(int irq, void *context, FAR void *arg) * Note * efm32_rmu_initialize should be called one since boot. * - ************************************************************************************/ + ****************************************************************************/ static void efm32_rtc_burtc_init(void) { @@ -268,9 +270,11 @@ static void efm32_rtc_burtc_init(void) /* Restore all not set BURTC registers to default value */ -// putreg32(_BURTC_LPMODE_RESETVALUE, EFM32_BURTC_LPMODE); -// putreg32(_BURTC_LFXOFDET_RESETVALUE, EFM32_BURTC_LFXOFDET); -// putreg32(_BURTC_COMP0_RESETVALUE, EFM32_BURTC_COMP0); + /* putreg32(_BURTC_LPMODE_RESETVALUE, EFM32_BURTC_LPMODE); */ + + /* putreg32(_BURTC_LFXOFDET_RESETVALUE, EFM32_BURTC_LFXOFDET); */ + + /* putreg32(_BURTC_COMP0_RESETVALUE, EFM32_BURTC_COMP0); */ /* New configuration */ @@ -284,7 +288,7 @@ static void efm32_rtc_burtc_init(void) /* Clear interrupts */ - putreg32(0xFFFFFFFF, EFM32_BURTC_IFC); + putreg32(0xffffffff, EFM32_BURTC_IFC); /* Set new configuration */ @@ -348,21 +352,22 @@ static uint64_t efm32_get_burtc_tick(void) val = (uint64_t)cnt_carry*__CNT_TOP + cnt + cnt_zero; - rtcinfo("Get Tick carry %u zero %u reg %u\n", cnt_carry, cnt_carry,cnt); + rtcinfo("Get Tick carry %u zero %u reg %u\n", + cnt_carry, cnt_carry, cnt); return val; } -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_initialize * * Description: - * Initialize the hardware RTC per the selected configuration. This function is - * called once during the OS initialization sequence + * Initialize the hardware RTC per the selected configuration. + * This function is called once during the OS initialization sequence * * Input Parameters: * None @@ -370,7 +375,7 @@ static uint64_t efm32_get_burtc_tick(void) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int up_rtc_initialize(void) { @@ -386,15 +391,15 @@ int up_rtc_initialize(void) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_time * * Description: * Get the current time in seconds. This is similar to the standard time() - * function. This interface is only required if the low-resolution RTC/counter - * hardware implementation selected. It is only used by the RTOS during - * initialization to set up the system time when CONFIG_RTC is set but neither - * CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set. + * function. This interface is only required if the low-resolution + * RTC/counter hardware implementation selected. It is only used by the + * RTOS during initialization to set up the system time when CONFIG_RTC is + * set but neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set. * * Input Parameters: * None @@ -402,22 +407,22 @@ int up_rtc_initialize(void) * Returned Value: * The current time in seconds * - ************************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_RTC_HIRES time_t up_rtc_time(void) { - return (time_t)efm32_get_burtc_tick()/CONFIG_RTC_FREQUENCY; + return (time_t)efm32_get_burtc_tick() / CONFIG_RTC_FREQUENCY; } #endif -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_gettime * * Description: - * Get the current time from the high resolution RTC clock/counter. This interface - * is only supported by the high-resolution RTC/counter hardware implementation. - * It is used to replace the system timer. + * Get the current time from the high resolution RTC clock/counter. + * This interface is only supported by the high-resolution RTC/counter + * hardware implementation. It is used to replace the system timer. * * Input Parameters: * tp - The location to return the high resolution time value. @@ -425,7 +430,7 @@ time_t up_rtc_time(void) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_HIRES int up_rtc_gettime(FAR struct timespec *tp) @@ -437,7 +442,8 @@ int up_rtc_gettime(FAR struct timespec *tp) /* Then we can save the time in seconds and fractional seconds. */ tp->tv_sec = val / CONFIG_RTC_FREQUENCY; - tp->tv_nsec = (val % CONFIG_RTC_FREQUENCY)*(NSEC_PER_SEC/CONFIG_RTC_FREQUENCY); + tp->tv_nsec = (val % CONFIG_RTC_FREQUENCY) * + (NSEC_PER_SEC / CONFIG_RTC_FREQUENCY); rtcinfo("Get RTC %u.%09u\n", tp->tv_sec, tp->tv_nsec); @@ -445,12 +451,12 @@ int up_rtc_gettime(FAR struct timespec *tp) } #endif -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_settime * * Description: - * Set the RTC to the provided time. All RTC implementations must be able to - * set their time based on a standard timespec. + * Set the RTC to the provided time. All RTC implementations must be + * able to set their time based on a standard timespec. * * Input Parameters: * tp - the time to use @@ -458,7 +464,7 @@ int up_rtc_gettime(FAR struct timespec *tp) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int up_rtc_settime(FAR const struct timespec *tp) { @@ -499,7 +505,7 @@ int up_rtc_settime(FAR const struct timespec *tp) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: efm32_rtc_setalarm * * Description: @@ -512,7 +518,7 @@ int up_rtc_settime(FAR const struct timespec *tp) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_ALARM #error "Sorry ! not yet implemented, just copied from STM32" @@ -557,7 +563,7 @@ int efm32_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback) } #endif -/************************************************************************************ +/**************************************************************************** * Name: efm32_rtc_cancelalarm * * Description: @@ -569,7 +575,7 @@ int efm32_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_ALARM #error "Sorry ! not yet implemented, just copied from STM32" diff --git a/arch/arm/src/efm32/efm32_serial.c b/arch/arm/src/efm32/efm32_serial.c index 753461c7470..ce0359fcdc3 100644 --- a/arch/arm/src/efm32/efm32_serial.c +++ b/arch/arm/src/efm32/efm32_serial.c @@ -1,4 +1,3 @@ - /**************************************************************************** * arch/arm/src/efm32/efm32_serial.c * diff --git a/arch/arm/src/efm32/efm32_timerisr.c b/arch/arm/src/efm32/efm32_timerisr.c index 547347e85bf..4f2b709aab0 100644 --- a/arch/arm/src/efm32/efm32_timerisr.c +++ b/arch/arm/src/efm32/efm32_timerisr.c @@ -119,6 +119,7 @@ void up_timer_initialize(void) putreg32(regval, NVIC_SYSH12_15_PRIORITY); /* Make sure that the SYSTICK clock source is set correctly */ + /* Configure SysTick to interrupt at the requested rate */ putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); diff --git a/arch/arm/src/efm32/efm32_usb.h b/arch/arm/src/efm32/efm32_usb.h index de4ce956541..63547df4df8 100644 --- a/arch/arm/src/efm32/efm32_usb.h +++ b/arch/arm/src/efm32/efm32_usb.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/efm32/efm32_usb.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_EFM32_OTGFS_H #define __ARCH_ARM_SRC_EFM32_EFM32_OTGFS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -33,9 +33,9 @@ #if defined(CONFIG_EFM32_OTGFS) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ #if defined(HAVE_USBHOST_TRACE) && defined(CONFIG_EFM32_OTGFS) enum usbhost_trace1codes_e @@ -59,7 +59,7 @@ enum usbhost_trace1codes_e USBHOST_VTRACE1_GINT_PTXFE, /* OTGFS Handle the periodic TxFIFO empty interrupt */ USBHOST_VTRACE1_GINT_HC, /* OTGFS Handle the host channels interrupt */ USBHOST_VTRACE1_GINT_HPRT, /* OTGFS Handle the host port interrupt */ - USBHOST_VTRACE1_GINT_HPRT_POCCHNG, /* OTGFS HPRT: Port Over-Current Change*/ + USBHOST_VTRACE1_GINT_HPRT_POCCHNG, /* OTGFS HPRT: Port Over-Current Change */ USBHOST_VTRACE1_GINT_HPRT_PCDET, /* OTGFS HPRT: Port Connect Detect */ USBHOST_VTRACE1_GINT_HPRT_PENCHNG, /* OTGFS HPRT: Port Enable Changed */ USBHOST_VTRACE1_GINT_HPRT_LSDEV, /* OTGFS HPRT: Low Speed Device Connected */ @@ -110,9 +110,9 @@ enum usbhost_trace1codes_e #endif /* HAVE_USBHOST_TRACE && CONFIG_EFM32_OTGFS */ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -133,8 +133,8 @@ extern "C" * * Input Parameters: * controller -- If the device supports more than USB host controller, then - * this identifies which controller is being initializeed. Normally, this - * is just zero. + * this identifies which controller is being initializeed. + * Normally, this is just zero. * * Returned Value: * And instance of the USB host interface. The controlling task should @@ -155,36 +155,38 @@ struct usbhost_connection_s; FAR struct usbhost_connection_s *efm32_usbhost_initialize(int controller); #endif -/*********************************************************************************** +/**************************************************************************** * Name: efm32_usbhost_vbusdrive * * Description: - * Enable/disable driving of VBUS 5V output. This function must be provided be - * each platform that implements the EFM32 OTG FS host interface + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the EFM32 OTG FS host + * interface * * Input Parameters: - * iface - For future growth to handle multiple USB host interface. Should be zero. + * iface - For future growth to handle multiple USB host interface. + * Should be zero. * enable - true: enable VBUS power; false: disable VBUS power * * Returned Value: * None * - ***********************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_USBHOST void efm32_usbhost_vbusdrive(int iface, bool enable); #endif -/************************************************************************************ +/**************************************************************************** * Name: efm32_usbsuspend * * Description: - * Board logic must provide the efm32_usbsuspend logic if the OTG FS device driver - * is used. This function is called whenever the USB enters or leaves suspend - * mode. This is an opportunity for the board logic to shutdown clocks, power, - * etc. while the USB is suspended. + * Board logic must provide the efm32_usbsuspend logic if the OTG FS + * device driver is used. This function is called whenever the USB enters + * or leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_USBDEV struct usbdev_s; diff --git a/arch/arm/src/efm32/efm32_usbdev.c b/arch/arm/src/efm32/efm32_usbdev.c index 447df00e390..5b29c9ca893 100644 --- a/arch/arm/src/efm32/efm32_usbdev.c +++ b/arch/arm/src/efm32/efm32_usbdev.c @@ -54,7 +54,8 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Configuration ***************************************************************/ + +/* Configuration ************************************************************/ #ifndef CONFIG_USBDEV_EP0_MAXSIZE # define CONFIG_USBDEV_EP0_MAXSIZE 64 @@ -103,8 +104,8 @@ # undef CONFIG_EFM32_USBDEV_REGDEBUG #endif -/* The actual FIFO addresses that we use must be aligned to 4-byte boundaries; - * FIFO sizes must be provided in units of 32-bit words. +/* The actual FIFO addresses that we use must be aligned to 4-byte + * boundaries; FIFO sizes must be provided in units of 32-bit words. */ #define EFM32_RXFIFO_BYTES ((CONFIG_USBDEV_RXFIFO_SIZE + 3) & ~3) @@ -138,7 +139,8 @@ # error "CONFIG_USBDEV_EP3_TXFIFO_SIZE is out of range" #endif -/* Debug ***********************************************************************/ +/* Debug ********************************************************************/ + /* Trace error codes */ #define EFM32_TRACEERR_ALLOCFAIL 0x01 @@ -224,7 +226,7 @@ #define EFM32_TRACEINTID_SETUPDONE (90 + 3) #define EFM32_TRACEINTID_SETUPRECVD (90 + 4) -/* Endpoints ******************************************************************/ +/* Endpoints ****************************************************************/ /* Number of endpoints */ @@ -247,17 +249,17 @@ #define EFM32_MAXPACKET (64) /* Max packet size (1-64) */ -/* Delays **********************************************************************/ +/* Delays *******************************************************************/ #define EFM32_READY_DELAY 200000 #define EFM32_FLUSH_DELAY 200000 -/* Request queue operations ****************************************************/ +/* Request queue operations *************************************************/ #define efm32_rqempty(ep) ((ep)->head == NULL) #define efm32_rqpeek(ep) ((ep)->head) -/* Standard stuff **************************************************************/ +/* Standard stuff ***********************************************************/ #ifndef MIN # define MIN(a,b) ((a) < (b) ? (a) : (b)) @@ -309,6 +311,7 @@ enum efm32_ep0state_e * SETUP processing. * TESTED: Never */ + EP0STATE_SETUP_OUT, /* OUT SETUP packet received. Waiting for the DATA * OUT phase of SETUP Packet to complete before * processing a SETUP command (without a USB request): @@ -316,6 +319,7 @@ enum efm32_ep0state_e * packet is received. * TESTED: In efm32_ep0out_receive() */ + EP0STATE_SETUP_READY, /* IN SETUP packet received -OR- OUT SETUP packet and * accompanying data have been received. Processing * of SETUP command will happen soon. @@ -330,21 +334,25 @@ enum efm32_ep0state_e * double-check that we have a SETUP request * and any accompanying data. */ + EP0STATE_SETUP_PROCESS, /* SETUP Packet is being processed by efm32_ep0out_setup(): * SET: When SETUP packet received in EP0 OUT * TESTED: Never */ + EP0STATE_SETUPRESPONSE, /* Short SETUP response write (without a USB request): * SET: When SETUP response is sent by * efm32_ep0in_setupresponse() * TESTED: Never */ + EP0STATE_DATA_IN, /* Waiting for data out stage (with a USB request): * SET: In efm32_epin_request() when a write * request is processed on EP0. * TESTED: In efm32_epin() to see if we should * revert to SETUP processing. */ + EP0STATE_DATA_OUT /* Waiting for data in phase to complete ( with a * USB request) * SET: In efm32_epout_request() when a read @@ -461,7 +469,7 @@ struct efm32_usbdev_s * Private Function Prototypes ****************************************************************************/ -/* Register operations ********************************************************/ +/* Register operations ******************************************************/ #ifdef CONFIG_EFM32_USBDEV_REGDEBUG static uint32_t efm32_getreg(uint32_t addr); @@ -471,13 +479,15 @@ static void efm32_putreg(uint32_t val, uint32_t addr); # define efm32_putreg(val,addr) putreg32(val,addr) #endif -/* Request queue operations ****************************************************/ +/* Request queue operations *************************************************/ -static FAR struct efm32_req_s *efm32_req_remfirst(FAR struct efm32_ep_s *privep); +static FAR struct +efm32_req_s *efm32_req_remfirst(FAR struct efm32_ep_s *privep); static bool efm32_req_addlast(FAR struct efm32_ep_s *privep, FAR struct efm32_req_s *req); -/* Low level data transfers and request operations *****************************/ +/* Low level data transfers and request operations **************************/ + /* Special endpoint 0 data transfer logic */ static void efm32_ep0in_setupresponse(FAR struct efm32_usbdev_s *priv, @@ -500,11 +510,13 @@ static void efm32_epin_request(FAR struct efm32_usbdev_s *priv, static void efm32_rxfifo_read(FAR struct efm32_ep_s *privep, FAR uint8_t *dest, uint16_t len); -static void efm32_rxfifo_discard(FAR struct efm32_ep_s *privep, int len); -static void efm32_epout_complete(FAR struct efm32_usbdev_s *priv, - FAR struct efm32_ep_s *privep); -static inline void efm32_ep0out_receive(FAR struct efm32_ep_s *privep, int bcnt); -static inline void efm32_epout_receive(FAR struct efm32_ep_s *privep, int bcnt); +static void efm32_rxfifo_discard(FAR struct efm32_ep_s *privep, int len); +static void efm32_epout_complete(FAR struct efm32_usbdev_s *priv, + FAR struct efm32_ep_s *privep); +static inline void +efm32_ep0out_receive(FAR struct efm32_ep_s *privep, int bcnt); +static inline void +efm32_epout_receive(FAR struct efm32_ep_s *privep, int bcnt); static void efm32_epout_request(FAR struct efm32_usbdev_s *priv, FAR struct efm32_ep_s *privep); @@ -516,9 +528,9 @@ static void efm32_req_complete(FAR struct efm32_ep_s *privep, static void efm32_req_cancel(FAR struct efm32_ep_s *privep, int16_t status); -/* Interrupt handling **********************************************************/ +/* Interrupt handling *******************************************************/ -static struct efm32_ep_s *efm32_ep_findbyaddr(struct efm32_usbdev_s *priv, +static struct efm32_ep_s *efm32_ep_findbyaddr(struct efm32_usbdev_s *priv, uint16_t eplog); static int efm32_req_dispatch(FAR struct efm32_usbdev_s *priv, FAR const struct usb_ctrlreq_s *ctrl); @@ -539,7 +551,8 @@ static inline void efm32_epout_interrupt(FAR struct efm32_usbdev_s *priv); static inline void efm32_epin_runtestmode(FAR struct efm32_usbdev_s *priv); static inline void efm32_epin(FAR struct efm32_usbdev_s *priv, uint8_t epno); -static inline void efm32_epin_txfifoempty(FAR struct efm32_usbdev_s *priv, int epno); +static inline void efm32_epin_txfifoempty(FAR struct efm32_usbdev_s *priv, + int epno); static inline void efm32_epin_interrupt(FAR struct efm32_usbdev_s *priv); /* Other second level interrupt processing */ @@ -559,9 +572,11 @@ static inline void efm32_otginterrupt(FAR struct efm32_usbdev_s *priv); /* First level interrupt processing */ -static int efm32_usbinterrupt(int irq, FAR void *context, FAR void *arg); +static int efm32_usbinterrupt(int irq, + FAR void *context, FAR void *arg); + +/* Endpoint operations ******************************************************/ -/* Endpoint operations *********************************************************/ /* Global OUT NAK controls */ static void efm32_enablegonak(FAR struct efm32_ep_s *privep); @@ -585,15 +600,18 @@ static int efm32_ep_disable(FAR struct usbdev_ep_s *ep); /* Endpoint request management */ -static FAR struct usbdev_req_s *efm32_ep_allocreq(FAR struct usbdev_ep_s *ep); +static FAR struct +usbdev_req_s *efm32_ep_allocreq(FAR struct usbdev_ep_s *ep); static void efm32_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *); /* Endpoint buffer management */ #ifdef CONFIG_USBDEV_DMA -static void *efm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes); -static void efm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf); +static void *efm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, + unsigned bytes); +static void efm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, + FAR void *buf); #endif /* Endpoint request submission */ @@ -622,7 +640,7 @@ static FAR struct usbdev_ep_s *efm32_ep_alloc(FAR struct usbdev_s *dev, static void efm32_ep_free(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep); -/* USB device controller operations ********************************************/ +/* USB device controller operations *****************************************/ static int efm32_getframe(struct usbdev_s *dev); static int efm32_wakeup(struct usbdev_s *dev); @@ -633,7 +651,7 @@ static void efm32_setaddress(struct efm32_usbdev_s *priv, static int efm32_txfifo_flush(uint32_t txfnum); static int efm32_rxfifo_flush(void); -/* Initialization **************************************************************/ +/* Initialization ***********************************************************/ static void efm32_swinitialize(FAR struct efm32_usbdev_s *priv); static void efm32_hwinitialize(FAR struct efm32_usbdev_s *priv); @@ -641,6 +659,7 @@ static void efm32_hwinitialize(FAR struct efm32_usbdev_s *priv); /**************************************************************************** * Private Data ****************************************************************************/ + /* Since there is only a single USB interface, all status information can be * be simply retained in a single global instance. */ @@ -679,37 +698,37 @@ static const struct usbdev_ops_s g_devops = #ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_deverror[] = { - TRACE_STR(EFM32_TRACEERR_ALLOCFAIL ), - TRACE_STR(EFM32_TRACEERR_BADCLEARFEATURE ), - TRACE_STR(EFM32_TRACEERR_BADDEVGETSTATUS ), - TRACE_STR(EFM32_TRACEERR_BADEPNO ), - TRACE_STR(EFM32_TRACEERR_BADEPGETSTATUS ), - TRACE_STR(EFM32_TRACEERR_BADGETCONFIG ), - TRACE_STR(EFM32_TRACEERR_BADGETSETDESC ), - TRACE_STR(EFM32_TRACEERR_BADGETSTATUS ), - TRACE_STR(EFM32_TRACEERR_BADSETADDRESS ), - TRACE_STR(EFM32_TRACEERR_BADSETCONFIG ), - TRACE_STR(EFM32_TRACEERR_BADSETFEATURE ), - TRACE_STR(EFM32_TRACEERR_BADTESTMODE ), - TRACE_STR(EFM32_TRACEERR_BINDFAILED ), - TRACE_STR(EFM32_TRACEERR_DISPATCHSTALL ), - TRACE_STR(EFM32_TRACEERR_DRIVER ), + TRACE_STR(EFM32_TRACEERR_ALLOCFAIL), + TRACE_STR(EFM32_TRACEERR_BADCLEARFEATURE), + TRACE_STR(EFM32_TRACEERR_BADDEVGETSTATUS), + TRACE_STR(EFM32_TRACEERR_BADEPNO), + TRACE_STR(EFM32_TRACEERR_BADEPGETSTATUS), + TRACE_STR(EFM32_TRACEERR_BADGETCONFIG), + TRACE_STR(EFM32_TRACEERR_BADGETSETDESC), + TRACE_STR(EFM32_TRACEERR_BADGETSTATUS), + TRACE_STR(EFM32_TRACEERR_BADSETADDRESS), + TRACE_STR(EFM32_TRACEERR_BADSETCONFIG), + TRACE_STR(EFM32_TRACEERR_BADSETFEATURE), + TRACE_STR(EFM32_TRACEERR_BADTESTMODE), + TRACE_STR(EFM32_TRACEERR_BINDFAILED), + TRACE_STR(EFM32_TRACEERR_DISPATCHSTALL), + TRACE_STR(EFM32_TRACEERR_DRIVER), TRACE_STR(EFM32_TRACEERR_DRIVERREGISTERED), - TRACE_STR(EFM32_TRACEERR_EP0NOSETUP ), - TRACE_STR(EFM32_TRACEERR_EP0SETUPSTALLED ), - TRACE_STR(EFM32_TRACEERR_EPINNULLPACKET ), - TRACE_STR(EFM32_TRACEERR_EPINUNEXPECTED ), - TRACE_STR(EFM32_TRACEERR_EPOUTNULLPACKET ), - TRACE_STR(EFM32_TRACEERR_EPOUTUNEXPECTED ), - TRACE_STR(EFM32_TRACEERR_INVALIDCTRLREQ ), - TRACE_STR(EFM32_TRACEERR_INVALIDPARMS ), - TRACE_STR(EFM32_TRACEERR_IRQREGISTRATION ), - TRACE_STR(EFM32_TRACEERR_NOEP ), - TRACE_STR(EFM32_TRACEERR_NOTCONFIGURED ), - TRACE_STR(EFM32_TRACEERR_EPOUTQEMPTY ), - TRACE_STR(EFM32_TRACEERR_EPINREQEMPTY ), - TRACE_STR(EFM32_TRACEERR_NOOUTSETUP ), - TRACE_STR(EFM32_TRACEERR_POLLTIMEOUT ), + TRACE_STR(EFM32_TRACEERR_EP0NOSETUP), + TRACE_STR(EFM32_TRACEERR_EP0SETUPSTALLED), + TRACE_STR(EFM32_TRACEERR_EPINNULLPACKET), + TRACE_STR(EFM32_TRACEERR_EPINUNEXPECTED), + TRACE_STR(EFM32_TRACEERR_EPOUTNULLPACKET), + TRACE_STR(EFM32_TRACEERR_EPOUTUNEXPECTED), + TRACE_STR(EFM32_TRACEERR_INVALIDCTRLREQ), + TRACE_STR(EFM32_TRACEERR_INVALIDPARMS), + TRACE_STR(EFM32_TRACEERR_IRQREGISTRATION), + TRACE_STR(EFM32_TRACEERR_NOEP), + TRACE_STR(EFM32_TRACEERR_NOTCONFIGURED), + TRACE_STR(EFM32_TRACEERR_EPOUTQEMPTY), + TRACE_STR(EFM32_TRACEERR_EPINREQEMPTY), + TRACE_STR(EFM32_TRACEERR_NOOUTSETUP), + TRACE_STR(EFM32_TRACEERR_POLLTIMEOUT), TRACE_STR_END }; #endif @@ -721,48 +740,48 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = #ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_intdecode[] = { - TRACE_STR(EFM32_TRACEINTID_USB ), - TRACE_STR(EFM32_TRACEINTID_INTPENDING ), - TRACE_STR(EFM32_TRACEINTID_EPOUT ), - TRACE_STR(EFM32_TRACEINTID_EPIN ), - TRACE_STR(EFM32_TRACEINTID_MISMATCH ), - TRACE_STR(EFM32_TRACEINTID_WAKEUP ), - TRACE_STR(EFM32_TRACEINTID_SUSPEND ), - TRACE_STR(EFM32_TRACEINTID_SOF ), - TRACE_STR(EFM32_TRACEINTID_RXFIFO ), - TRACE_STR(EFM32_TRACEINTID_DEVRESET ), - TRACE_STR(EFM32_TRACEINTID_ENUMDNE ), - TRACE_STR(EFM32_TRACEINTID_IISOIXFR ), - TRACE_STR(EFM32_TRACEINTID_IISOOXFR ), - TRACE_STR(EFM32_TRACEINTID_SRQ ), - TRACE_STR(EFM32_TRACEINTID_OTG ), - TRACE_STR(EFM32_TRACEINTID_EPOUT_XFRC ), + TRACE_STR(EFM32_TRACEINTID_USB), + TRACE_STR(EFM32_TRACEINTID_INTPENDING), + TRACE_STR(EFM32_TRACEINTID_EPOUT), + TRACE_STR(EFM32_TRACEINTID_EPIN), + TRACE_STR(EFM32_TRACEINTID_MISMATCH), + TRACE_STR(EFM32_TRACEINTID_WAKEUP), + TRACE_STR(EFM32_TRACEINTID_SUSPEND), + TRACE_STR(EFM32_TRACEINTID_SOF), + TRACE_STR(EFM32_TRACEINTID_RXFIFO), + TRACE_STR(EFM32_TRACEINTID_DEVRESET), + TRACE_STR(EFM32_TRACEINTID_ENUMDNE), + TRACE_STR(EFM32_TRACEINTID_IISOIXFR), + TRACE_STR(EFM32_TRACEINTID_IISOOXFR), + TRACE_STR(EFM32_TRACEINTID_SRQ), + TRACE_STR(EFM32_TRACEINTID_OTG), + TRACE_STR(EFM32_TRACEINTID_EPOUT_XFRC), TRACE_STR(EFM32_TRACEINTID_EPOUT_EPDISD), - TRACE_STR(EFM32_TRACEINTID_EPOUT_SETUP ), - TRACE_STR(EFM32_TRACEINTID_DISPATCH ), - TRACE_STR(EFM32_TRACEINTID_GETSTATUS ), - TRACE_STR(EFM32_TRACEINTID_EPGETSTATUS ), + TRACE_STR(EFM32_TRACEINTID_EPOUT_SETUP), + TRACE_STR(EFM32_TRACEINTID_DISPATCH), + TRACE_STR(EFM32_TRACEINTID_GETSTATUS), + TRACE_STR(EFM32_TRACEINTID_EPGETSTATUS), TRACE_STR(EFM32_TRACEINTID_DEVGETSTATUS), - TRACE_STR(EFM32_TRACEINTID_IFGETSTATUS ), + TRACE_STR(EFM32_TRACEINTID_IFGETSTATUS), TRACE_STR(EFM32_TRACEINTID_CLEARFEATURE), - TRACE_STR(EFM32_TRACEINTID_SETFEATURE ), - TRACE_STR(EFM32_TRACEINTID_SETADDRESS ), - TRACE_STR(EFM32_TRACEINTID_GETSETDESC ), - TRACE_STR(EFM32_TRACEINTID_GETCONFIG ), - TRACE_STR(EFM32_TRACEINTID_SETCONFIG ), - TRACE_STR(EFM32_TRACEINTID_GETSETIF ), - TRACE_STR(EFM32_TRACEINTID_SYNCHFRAME ), - TRACE_STR(EFM32_TRACEINTID_EPIN_XFRC ), - TRACE_STR(EFM32_TRACEINTID_EPIN_TOC ), - TRACE_STR(EFM32_TRACEINTID_EPIN_ITTXFE ), - TRACE_STR(EFM32_TRACEINTID_EPIN_EPDISD ), - TRACE_STR(EFM32_TRACEINTID_EPIN_TXFE ), + TRACE_STR(EFM32_TRACEINTID_SETFEATURE), + TRACE_STR(EFM32_TRACEINTID_SETADDRESS), + TRACE_STR(EFM32_TRACEINTID_GETSETDESC), + TRACE_STR(EFM32_TRACEINTID_GETCONFIG), + TRACE_STR(EFM32_TRACEINTID_SETCONFIG), + TRACE_STR(EFM32_TRACEINTID_GETSETIF), + TRACE_STR(EFM32_TRACEINTID_SYNCHFRAME), + TRACE_STR(EFM32_TRACEINTID_EPIN_XFRC), + TRACE_STR(EFM32_TRACEINTID_EPIN_TOC), + TRACE_STR(EFM32_TRACEINTID_EPIN_ITTXFE), + TRACE_STR(EFM32_TRACEINTID_EPIN_EPDISD), + TRACE_STR(EFM32_TRACEINTID_EPIN_TXFE), TRACE_STR(EFM32_TRACEINTID_EPIN_EMPWAIT), - TRACE_STR(EFM32_TRACEINTID_OUTNAK ), - TRACE_STR(EFM32_TRACEINTID_OUTRECVD ), - TRACE_STR(EFM32_TRACEINTID_OUTDONE ), - TRACE_STR(EFM32_TRACEINTID_SETUPDONE ), - TRACE_STR(EFM32_TRACEINTID_SETUPRECVD ), + TRACE_STR(EFM32_TRACEINTID_OUTNAK), + TRACE_STR(EFM32_TRACEINTID_OUTRECVD), + TRACE_STR(EFM32_TRACEINTID_OUTDONE), + TRACE_STR(EFM32_TRACEINTID_SETUPDONE), + TRACE_STR(EFM32_TRACEINTID_SETUPRECVD), TRACE_STR_END }; #endif @@ -794,8 +813,8 @@ static uint32_t efm32_getreg(uint32_t addr) uint32_t val = getreg32(addr); - /* Is this the same value that we read from the same register last time? Are - * we polling the register? If so, suppress some of the output. + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. */ if (addr == prevaddr && val == preval) @@ -821,7 +840,7 @@ static uint32_t efm32_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - uinfo("[repeats %d more times]\n", count-3); + uinfo("[repeats %d more times]\n", count - 3); } /* Save the new address, value, and count */ @@ -867,7 +886,8 @@ static void efm32_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -static FAR struct efm32_req_s *efm32_req_remfirst(FAR struct efm32_ep_s *privep) +static FAR struct +efm32_req_s *efm32_req_remfirst(FAR struct efm32_ep_s *privep) { FAR struct efm32_req_s *ret = privep->head; @@ -909,6 +929,7 @@ static bool efm32_req_addlast(FAR struct efm32_ep_s *privep, privep->tail->flink = req; privep->tail = req; } + return is_empty; } @@ -1075,7 +1096,9 @@ static void efm32_epin_transfer(FAR struct efm32_ep_s *privep, if (nbytes == 0) { - /* Yes.. leave the transfer size at zero and set the packet count to 1 */ + /* Yes.. + * leave the transfer size at zero and set the packet count to 1 + */ pktcnt = 1; } @@ -1088,7 +1111,8 @@ static void efm32_epin_transfer(FAR struct efm32_ep_s *privep, * perform the transfer. */ - pktcnt = ((uint32_t)nbytes + (privep->ep.maxpacket - 1)) / privep->ep.maxpacket; + pktcnt = ((uint32_t)nbytes + (privep->ep.maxpacket - 1)) / + privep->ep.maxpacket; } /* Set the XFERSIZE and PKTCNT */ @@ -1141,8 +1165,8 @@ static void efm32_epin_transfer(FAR struct efm32_ep_s *privep, efm32_putreg(regval, EFM32_USB_DIEPCTL(privep->epphy)); /* Transfer the data to the TxFIFO. At this point, the caller has already - * assured that there is sufficient space in the TxFIFO to hold the transfer - * we can just blindly continue. + * assured that there is sufficient space in the TxFIFO to hold the + * transfer we can just blindly continue. */ efm32_txfifo_write(privep, buf, nbytes); @@ -1213,9 +1237,9 @@ static void efm32_epin_request(FAR struct efm32_usbdev_s *priv, privep->epphy, privreq, privreq->req.len, privreq->req.xfrd, privep->zlp); - /* Check for a special case: If we are just starting a request (xfrd==0) and - * the class driver is trying to send a zero-length packet (len==0). Then set - * the ZLP flag so that the packet will be sent. + /* Check for a special case: If we are just starting a request (xfrd==0) + * and the class driver is trying to send a zero-length packet (len==0). + * Then set the ZLP flag so that the packet will be sent. */ if (privreq->req.len == 0) @@ -1311,7 +1335,8 @@ static void efm32_epin_request(FAR struct efm32_usbdev_s *priv, regval = efm32_getreg(regaddr); if ((int)(regval & _USB_DIEPTXFSTS_MASK) < nwords) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPIN_EMPWAIT), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPIN_EMPWAIT), + (uint16_t)regval); /* There is insufficient space in the TxFIFO. Wait for a TxFIFO * empty interrupt and try again. @@ -1351,9 +1376,10 @@ static void efm32_epin_request(FAR struct efm32_usbdev_s *priv, privreq->req.xfrd += nbytes; } - /* Note that the ZLP, if any, must be sent as a separate transfer. The need - * for a ZLP is indicated by privep->zlp. If all of the bytes were sent - * (including any final null packet) then we are finished with the transfer + /* Note that the ZLP, if any, must be sent as a separate transfer. The + * need for a ZLP is indicated by privep->zlp. If all of the bytes were + * sent (including any final null packet) then we are finished with the + * transfer */ if (privreq->req.xfrd >= privreq->req.len && !privep->zlp) @@ -1388,7 +1414,9 @@ static void efm32_rxfifo_read(FAR struct efm32_ep_s *privep, regaddr = EFM32_USB_FIFO_BASE(EP0); - /* Read 32-bits and write 4 x 8-bits at time (to avoid unaligned accesses) */ + /* Read 32-bits and write 4 x 8-bits at time + * (to avoid unaligned accesses) + */ for (i = 0; i < len; i += 4) { @@ -1457,8 +1485,8 @@ static void efm32_epout_complete(FAR struct efm32_usbdev_s *priv, { struct efm32_req_s *privreq; - /* Since a transfer just completed, there must be a read request at the head of - * the endpoint request queue. + /* Since a transfer just completed, there must be a read request at the + * head of the endpoint request queue. */ privreq = efm32_rqpeek(privep); @@ -1466,8 +1494,8 @@ static void efm32_epout_complete(FAR struct efm32_usbdev_s *priv, if (!privreq) { - /* An OUT transfer completed, but no packet to receive the data. This - * should not happen. + /* An OUT transfer completed, but no packet to receive the data. + * This should not happen. */ usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_EPOUTQEMPTY), privep->epphy); @@ -1495,13 +1523,14 @@ static void efm32_epout_complete(FAR struct efm32_usbdev_s *priv, * Name: efm32_ep0out_receive * * Description: - * This function is called from the RXFLVL interrupt handler when new incoming - * data is available in the endpoint's RxFIFO. This function will simply - * copy the incoming data into pending request's data buffer. + * This function is called from the RXFLVL interrupt handler when new + * incoming data is available in the endpoint's RxFIFO. This function will + * simply copy the incoming data into pending request's data buffer. * ****************************************************************************/ -static inline void efm32_ep0out_receive(FAR struct efm32_ep_s *privep, int bcnt) +static inline void efm32_ep0out_receive(FAR struct efm32_ep_s *privep, + int bcnt) { FAR struct efm32_usbdev_s *priv; @@ -1553,13 +1582,14 @@ static inline void efm32_ep0out_receive(FAR struct efm32_ep_s *privep, int bcnt) * Name: efm32_epout_receive * * Description: - * This function is called from the RXFLVL interrupt handler when new incoming - * data is available in the endpoint's RxFIFO. This function will simply - * copy the incoming data into pending request's data buffer. + * This function is called from the RXFLVL interrupt handler when new + * incoming data is available in the endpoint's RxFIFO. This function will + * simply copy the incoming data into pending request's data buffer. * ****************************************************************************/ -static inline void efm32_epout_receive(FAR struct efm32_ep_s *privep, int bcnt) +static inline void efm32_epout_receive(FAR struct efm32_ep_s *privep, + int bcnt) { struct efm32_req_s *privreq; uint8_t *dest; @@ -1575,7 +1605,8 @@ static inline void efm32_epout_receive(FAR struct efm32_ep_s *privep, int bcnt) { /* Incoming data is available in the RxFIFO, but there is no read setup * to receive the receive the data. This should not happen for data - * endpoints; those endpoints should have been NAKing any OUT data tokens. + * endpoints; those endpoints should have been NAKing any OUT data + * tokens. * * We should get here normally on OUT data phase following an OUT * SETUP command. EP0 data will still receive data in this case and it @@ -1592,7 +1623,8 @@ static inline void efm32_epout_receive(FAR struct efm32_ep_s *privep, int bcnt) * NAKing is working as expected. */ - usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_EPOUTQEMPTY), privep->epphy); + usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_EPOUTQEMPTY), + privep->epphy); /* Discard the data in the RxFIFO */ @@ -1636,9 +1668,9 @@ static inline void efm32_epout_receive(FAR struct efm32_ep_s *privep, int bcnt) * Name: efm32_epout_request * * Description: - * This function is called when either (1) new read request is received, or - * (2) a pending receive request completes. If there is no read in pending, - * then this function will initiate the next OUT (read) operation. + * This function is called when either (1) new read request is received, + * or (2) a pending receive request completes. If there is no read in + * pending, then this function will initiate the next OUT (read) operation. * ****************************************************************************/ @@ -1651,30 +1683,34 @@ static void efm32_epout_request(FAR struct efm32_usbdev_s *priv, uint32_t xfrsize; uint32_t pktcnt; - /* Make sure that there is not already a pending request request. If there is, - * just return, leaving the newly received request in the request queue. + /* Make sure that there is not already a pending request request. If there + * is, just return, leaving the newly received request in the request + * queue. */ if (!privep->active) { /* Loop until a valid request is found (or the request queue is empty). - * The loop is only need to look at the request queue again is an invalid - * read request is encountered. + * The loop is only need to look at the request queue again is an + * invalid read request is encountered. */ for (; ; ) { - /* Get a reference to the request at the head of the endpoint's request queue */ + /* Get a reference to the request at the head of the endpoint's + * request queue + */ privreq = efm32_rqpeek(privep); if (!privreq) { - usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_EPOUTQEMPTY), privep->epphy); + usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_EPOUTQEMPTY), + privep->epphy); - /* There are no read requests to be setup. Configure the hardware to - * NAK any incoming packets. (This should already be the case. I - * think that the hardware will automatically NAK after a transfer is - * completed until SNAK is cleared). + /* There are no read requests to be setup. Configure the + * hardware to NAK any incoming packets. (This should already + * be the case. I think that the hardware will automatically + * NAK after a transfer is completed until SNAK is cleared). */ regaddr = EFM32_USB_DOEPCTL(privep->epphy); @@ -1700,7 +1736,9 @@ static void efm32_epout_request(FAR struct efm32_usbdev_s *priv, efm32_req_complete(privep, OK); } - /* Otherwise, we have a usable read request... break out of the loop */ + /* Otherwise, we have a usable read request... + * break out of the loop + */ else { @@ -1716,7 +1754,8 @@ static void efm32_epout_request(FAR struct efm32_usbdev_s *priv, * maxpacket bytes). */ - pktcnt = (privreq->req.len + (privep->ep.maxpacket - 1)) / privep->ep.maxpacket; + pktcnt = (privreq->req.len + (privep->ep.maxpacket - 1)) / + privep->ep.maxpacket; xfrsize = pktcnt * privep->ep.maxpacket; /* Then setup the hardware to perform this transfer */ @@ -1795,7 +1834,8 @@ static void efm32_ep_flush(struct efm32_ep_s *privep) * Name: efm32_req_complete * * Description: - * Handle termination of the request at the head of the endpoint request queue. + * Handle termination of the request at the head of the endpoint request + * queue. * ****************************************************************************/ @@ -1895,8 +1935,8 @@ static struct efm32_ep_s *efm32_ep_findbyaddr(struct efm32_usbdev_s *priv, * Name: efm32_req_dispatch * * Description: - * Provide unhandled setup actions to the class driver. This is logically part - * of the USB interrupt handler. + * Provide unhandled setup actions to the class driver. This is logically + * part of the USB interrupt handler. * ****************************************************************************/ @@ -2076,13 +2116,14 @@ static inline void efm32_ep0out_testmode(FAR struct efm32_usbdev_s *priv, * Name: efm32_ep0out_stdrequest * * Description: - * Handle a stanard request on EP0. Pick off the things of interest to the - * USB device controller driver; pass what is left to the class driver. + * Handle a stanard request on EP0. Pick off the things of interest to + * the USB device controller driver; pass what is left to the class driver. * ****************************************************************************/ -static inline void efm32_ep0out_stdrequest(struct efm32_usbdev_s *priv, - FAR struct efm32_ctrlreq_s *ctrlreq) +static inline void +efm32_ep0out_stdrequest(struct efm32_usbdev_s *priv, + FAR struct efm32_ctrlreq_s *ctrlreq) { FAR struct efm32_ep_s *privep; @@ -2116,7 +2157,8 @@ static inline void efm32_ep0out_stdrequest(struct efm32_usbdev_s *priv, privep = efm32_ep_findbyaddr(priv, ctrlreq->index); if (!privep) { - usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_BADEPGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_BADEPGETSTATUS), + 0); priv->stalled = true; } else @@ -2140,19 +2182,23 @@ static inline void efm32_ep0out_stdrequest(struct efm32_usbdev_s *priv, { if (ctrlreq->index == 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_DEVGETSTATUS), 0); + usbtrace(TRACE_INTDECODE( + EFM32_TRACEINTID_DEVGETSTATUS), 0); /* Features: Remote Wakeup and selfpowered */ - priv->ep0data[0] = (priv->selfpowered << USB_FEATURE_SELFPOWERED); - priv->ep0data[0] |= (priv->wakeup << USB_FEATURE_REMOTEWAKEUP); + priv->ep0data[0] = (priv->selfpowered << + USB_FEATURE_SELFPOWERED); + priv->ep0data[0] |= (priv->wakeup << + USB_FEATURE_REMOTEWAKEUP); priv->ep0data[1] = 0; efm32_ep0in_setupresponse(priv, priv->ep0data, 2); } else { - usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_BADDEVGETSTATUS), 0); + usbtrace(TRACE_DEVERROR( + EFM32_TRACEERR_BADDEVGETSTATUS), 0); priv->stalled = true; } } @@ -2278,14 +2324,17 @@ static inline void efm32_ep0out_stdrequest(struct efm32_usbdev_s *priv, * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_SETADDRESS), ctrlreq->value); - if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_SETADDRESS), + ctrlreq->value); + if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && ctrlreq->index == 0 && ctrlreq->len == 0 && ctrlreq->value < 128 && priv->devstate != DEVSTATE_CONFIGURED) { - /* Save the address. We cannot actually change to the next address until + /* Save the address. + * We cannot actually change to the next address until * the completion of the status phase. */ @@ -2316,7 +2365,8 @@ static inline void efm32_ep0out_stdrequest(struct efm32_usbdev_s *priv, { usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_GETSETDESC), 0); - if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) + if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) { efm32_req_dispatch(priv, &priv->ctrlreq); } @@ -2338,7 +2388,8 @@ static inline void efm32_ep0out_stdrequest(struct efm32_usbdev_s *priv, { usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_GETCONFIG), 0); if (priv->addressed && - (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && + (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && ctrlreq->value == 0 && ctrlreq->index == 0 && ctrlreq->len == 1) @@ -2363,7 +2414,8 @@ static inline void efm32_ep0out_stdrequest(struct efm32_usbdev_s *priv, { usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_SETCONFIG), 0); if (priv->addressed && - (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && + (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && ctrlreq->index == 0 && ctrlreq->len == 0) { @@ -2485,7 +2537,8 @@ static inline void efm32_ep0out_setup(struct efm32_usbdev_s *priv) ctrlreq.len = GETUINT16(priv->ctrlreq.len); uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n", - ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len); + ctrlreq.type, ctrlreq.req, + ctrlreq.value, ctrlreq.index, ctrlreq.len); /* Check for a standard request */ @@ -2506,13 +2559,14 @@ static inline void efm32_ep0out_setup(struct efm32_usbdev_s *priv) if (priv->stalled) { - usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_EP0SETUPSTALLED), priv->ep0state); + usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_EP0SETUPSTALLED), + priv->ep0state); efm32_ep0_stall(priv); } /* Reset state/data associated with the SETUP request */ - priv->ep0datlen = 0; + priv->ep0datlen = 0; } /**************************************************************************** @@ -2524,7 +2578,8 @@ static inline void efm32_ep0out_setup(struct efm32_usbdev_s *priv) * ****************************************************************************/ -static inline void efm32_epout(FAR struct efm32_usbdev_s *priv, uint8_t epno) +static inline void efm32_epout(FAR struct efm32_usbdev_s *priv, + uint8_t epno) { FAR struct efm32_ep_s *privep; @@ -2571,12 +2626,12 @@ static inline void efm32_epout(FAR struct efm32_usbdev_s *priv, uint8_t epno) * Name: efm32_epout_interrupt * * Description: - * USB OUT endpoint interrupt handler. The core generates this interrupt when - * there is an interrupt is pending on one of the OUT endpoints of the core. - * The driver must read the OTGFS DAINT register to determine the exact number - * of the OUT endpoint on which the interrupt occurred, and then read the - * corresponding OTGFS DOEPINTx register to determine the exact cause of the - * interrupt. + * USB OUT endpoint interrupt handler. The core generates this interrupt + * when there is an interrupt is pending on one of the OUT endpoints of the + * core. The driver must read the OTGFS DAINT register to determine the + * exact number of the OUT endpoint on which the interrupt occurred, and + * then read the corresponding OTGFS DOEPINTx register to determine the + * exact cause of the interrupt. * ****************************************************************************/ @@ -2587,8 +2642,8 @@ static inline void efm32_epout_interrupt(FAR struct efm32_usbdev_s *priv) uint32_t doepint; int epno; - /* Get the pending, enabled interrupts for the OUT endpoint from the endpoint - * interrupt status register. + /* Get the pending, enabled interrupts for the OUT endpoint from the + * endpoint interrupt status register. */ regval = efm32_getreg(EFM32_USB_DAINT); @@ -2608,7 +2663,8 @@ static inline void efm32_epout_interrupt(FAR struct efm32_usbdev_s *priv) */ regval = efm32_getreg(EFM32_USB_DAINT); - daint = (regval & _USB_DAINT_OUTEPINT_MASK) >> _USB_DAINT_OUTEPINT_SHIFT; + daint = (regval & _USB_DAINT_OUTEPINT_MASK) >> + _USB_DAINT_OUTEPINT_SHIFT; usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_EPOUTUNEXPECTED), (uint16_t)regval); @@ -2620,7 +2676,7 @@ static inline void efm32_epout_interrupt(FAR struct efm32_usbdev_s *priv) { regval = efm32_getreg(EFM32_USB_DOEPINT(epno)); uinfo("DOEPINT(%d) = %08x\n", epno, regval); - efm32_putreg(0xFF, EFM32_USB_DOEPINT(epno)); + efm32_putreg(0xff, EFM32_USB_DOEPINT(epno)); } epno++; @@ -2645,14 +2701,15 @@ static inline void efm32_epout_interrupt(FAR struct efm32_usbdev_s *priv) doepint &= efm32_getreg(EFM32_USB_DOEPMSK); /* Transfer completed interrupt. This interrupt is triggered when - * efm32_rxinterrupt() removes the last packet data from the RxFIFO. - * In this case, core internally sets the NAK bit for this endpoint to - * prevent it from receiving any more packets. + * efm32_rxinterrupt() removes the last packet data from the + * RxFIFO. In this case, core internally sets the NAK bit for this + * endpoint to prevent it from receiving any more packets. */ if ((doepint & USB_DOEPINT_XFERCOMPL) != 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPOUT_XFRC), (uint16_t)doepint); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPOUT_XFRC), + (uint16_t)doepint); /* Clear the bit in DOEPINTn for this interrupt */ @@ -2668,20 +2725,24 @@ static inline void efm32_epout_interrupt(FAR struct efm32_usbdev_s *priv) */ #if 1 /* REVISIT: */ + if ((doepint & USB_DOEPINT_EPDISBLD) != 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPOUT_EPDISD), (uint16_t)doepint); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPOUT_EPDISD), + (uint16_t)doepint); /* Clear the bit in DOEPINTn for this interrupt */ efm32_putreg(USB_DOEPINT_EPDISBLD, EFM32_USB_DOEPINT(epno)); } #endif + /* Setup Phase Done (control EPs) */ if ((doepint & USB_DOEPINT_SETUP) != 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPOUT_SETUP), priv->ep0state); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPOUT_SETUP), + priv->ep0state); /* Handle the receipt of the IN SETUP packets now (OUT setup * packet processing may be delayed until the accompanying @@ -2692,6 +2753,7 @@ static inline void efm32_epout_interrupt(FAR struct efm32_usbdev_s *priv) { efm32_ep0out_setup(priv); } + efm32_putreg(USB_DOEPINT_SETUP, EFM32_USB_DOEPINT(epno)); } } @@ -2786,7 +2848,8 @@ static inline void efm32_epin(FAR struct efm32_usbdev_s *priv, uint8_t epno) * ****************************************************************************/ -static inline void efm32_epin_txfifoempty(FAR struct efm32_usbdev_s *priv, int epno) +static inline void efm32_epin_txfifoempty(FAR struct efm32_usbdev_s *priv, + int epno) { FAR struct efm32_ep_s *privep = &priv->epin[epno]; @@ -2802,11 +2865,12 @@ static inline void efm32_epin_txfifoempty(FAR struct efm32_usbdev_s *priv, int e * Name: efm32_epin_interrupt * * Description: - * USB IN endpoint interrupt handler. The core generates this interrupt when - * an interrupt is pending on one of the IN endpoints of the core. The driver - * must read the OTGFS DAINT register to determine the exact number of the IN - * endpoint on which the interrupt occurred, and then read the corresponding - * OTGFS DIEPINTx register to determine the exact cause of the interrupt. + * USB IN endpoint interrupt handler. The core generates this interrupt + * when an interrupt is pending on one of the IN endpoints of the core. + * The driver must read the OTGFS DAINT register to determine the exact + * number of the IN endpoint on which the interrupt occurred, and then + * read the corresponding OTGFS DIEPINTx register to determine the exact + * cause of the interrupt. * ****************************************************************************/ @@ -2818,8 +2882,8 @@ static inline void efm32_epin_interrupt(FAR struct efm32_usbdev_s *priv) uint32_t empty; int epno; - /* Get the pending, enabled interrupts for the IN endpoint from the endpoint - * interrupt status register. + /* Get the pending, enabled interrupts for the IN endpoint from the + * endpoint interrupt status register. */ daint = efm32_getreg(EFM32_USB_DAINT); @@ -2851,7 +2915,7 @@ static inline void efm32_epin_interrupt(FAR struct efm32_usbdev_s *priv) { uinfo("DIEPINT(%d) = %08x\n", epno, efm32_getreg(EFM32_USB_DIEPINT(epno))); - efm32_putreg(0xFF, EFM32_USB_DIEPINT(epno)); + efm32_putreg(0xff, EFM32_USB_DIEPINT(epno)); } epno++; @@ -2897,6 +2961,7 @@ static inline void efm32_epin_interrupt(FAR struct efm32_usbdev_s *priv) diepint = efm32_getreg(EFM32_USB_DIEPINT(epno)) & mask; /* Decode and process the enabled, pending interrupts */ + /* Transfer completed interrupt */ if ((diepint & USB_DIEPINT_XFERCOMPL) != 0) @@ -2923,20 +2988,23 @@ static inline void efm32_epin_interrupt(FAR struct efm32_usbdev_s *priv) if ((diepint & USB_DIEPINT_TIMEOUT) != 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPIN_TOC), (uint16_t)diepint); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPIN_TOC), + (uint16_t)diepint); efm32_putreg(USB_DIEPINT_TIMEOUT, EFM32_USB_DIEPINT(epno)); } - /* IN token received when TxFIFO is empty. Applies to non-periodic IN - * endpoints only. This interrupt indicates that an IN token was received - * when the associated TxFIFO (periodic/non-periodic) was empty. This - * interrupt is asserted on the endpoint for which the IN token was - * received. + /* IN token received when TxFIFO is empty. + * Applies to non-periodic IN endpoints only. + * This interrupt indicates that an IN token was received + * when the associated TxFIFO (periodic/non-periodic) was empty. + * This interrupt is asserted on the endpoint for which the IN + * token was received. */ if ((diepint & USB_DIEPINT_INTKNTXFEMP) != 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPIN_ITTXFE), (uint16_t)diepint); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPIN_ITTXFE), + (uint16_t)diepint); efm32_epin_request(priv, &priv->epin[epno]); efm32_putreg(USB_DIEPINT_INTKNTXFEMP, EFM32_USB_DIEPINT(epno)); } @@ -2947,35 +3015,41 @@ static inline void efm32_epin_interrupt(FAR struct efm32_usbdev_s *priv) #if 0 if ((diepint & USB_DIEPINT_INEPNAKEFF) != 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPIN_INEPNE), (uint16_t)diepint); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPIN_INEPNE), + (uint16_t)diepint); efm32_putreg(USB_DIEPINT_INEPNAKEFF, EFM32_USB_DIEPINT(epno)); } #endif + /* Endpoint disabled interrupt (ignored as this used only in polled * mode) */ #if 0 if ((diepint & USB_DIEPINT_EPDISBLD) != 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPIN_EPDISD), (uint16_t)diepint); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPIN_EPDISD), + (uint16_t)diepint); efm32_putreg(USB_DIEPINT_EPDISBLD, EFM32_USB_DIEPINT(epno)); } #endif + /* Transmit FIFO empty */ if ((diepint & USB_DIEPINT_TXFEMP) != 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPIN_TXFE), (uint16_t)diepint); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPIN_TXFE), + (uint16_t)diepint); - /* If we were waiting for TxFIFO to become empty, the we might have both - * XFRC and TXFE interrupts pending. Since we do the same thing for both - * cases, ignore the TXFE if we have already processed the XFRC. + /* If we were waiting for TxFIFO to become empty, the we might + * have both XFRC and TXFE interrupts pending. Since we do the + * same thing for both cases, ignore the TXFE if we have + * already processed the XFRC. */ if ((diepint & USB_DIEPINT_XFERCOMPL) == 0) { - /* Mask further FIFO empty interrupts. This will be re-enabled - * whenever we need to wait for a FIFO event. + /* Mask further FIFO empty interrupts. This will be + * re-enabled whenever we need to wait for a FIFO event. */ empty &= ~USB_DIEPEMPMSK(epno); @@ -3118,7 +3192,8 @@ static inline void efm32_rxinterrupt(FAR struct efm32_usbdev_s *priv) /* Decode status fields */ - epphy = (regval & _USB_GRXSTSP_CHEPNUM_MASK) >> _USB_GRXSTSP_CHEPNUM_SHIFT; + epphy = (regval & _USB_GRXSTSP_CHEPNUM_MASK) >> + _USB_GRXSTSP_CHEPNUM_SHIFT; privep = &priv->epout[epphy]; /* Handle the RX event according to the packet status field */ @@ -3141,7 +3216,8 @@ static inline void efm32_rxinterrupt(FAR struct efm32_usbdev_s *priv) /* OUT data packet received. * * PKTSTS = DataOUT, BCNT = size of the received data OUT packet, - * EPNUM = EPNUM on which the packet was received, DPID = Actual Data PID. + * EPNUM = EPNUM on which the packet was received, DPID = Actual Data + * PID. */ case USB_GRXSTSP_PKTSTS_PKTRCV: @@ -3186,8 +3262,9 @@ static inline void efm32_rxinterrupt(FAR struct efm32_usbdev_s *priv) } break; - /* SETUP data packet received. This indicates that a SETUP packet for the - * specified endpoint is now available for reading from the receive FIFO. + /* SETUP data packet received. + * This indicates that a SETUP packet for the specified endpoint + * is now available for reading from the receive FIFO. * * PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0. */ @@ -3198,7 +3275,8 @@ static inline void efm32_rxinterrupt(FAR struct efm32_usbdev_s *priv) usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_SETUPRECVD), epphy); - /* Read EP0 setup data. NOTE: If multiple SETUP packets are received, + /* Read EP0 setup data. + * NOTE: If multiple SETUP packets are received, * the last one overwrites the previous setup packets and only that * last SETUP packet will be processed. */ @@ -3242,7 +3320,8 @@ static inline void efm32_rxinterrupt(FAR struct efm32_usbdev_s *priv) default: { usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_INVALIDPARMS), - (regval & _USB_GRXSTSP_PKTSTS_MASK) >> _USB_GRXSTSP_PKTSTS_SHIFT); + (regval & _USB_GRXSTSP_PKTSTS_MASK) >> + _USB_GRXSTSP_PKTSTS_SHIFT); } break; } @@ -3270,7 +3349,9 @@ static inline void efm32_enuminterrupt(FAR struct efm32_usbdev_s *priv) efm32_ep0in_activate(); - /* Set USB turn-around time for the full speed device with internal PHY interface. */ + /* Set USB turn-around time for the full speed device with internal PHY + * interface. + */ regval = efm32_getreg(EFM32_USB_GUSBCFG); regval &= ~_USB_GUSBCFG_USBTRDTIM_MASK; @@ -3282,9 +3363,9 @@ static inline void efm32_enuminterrupt(FAR struct efm32_usbdev_s *priv) * Name: efm32_isocininterrupt * * Description: - * Incomplete isochronous IN transfer interrupt. Assertion of the incomplete - * isochronous IN transfer interrupt indicates an incomplete isochronous IN - * transfer on at least one of the isochronous IN endpoints. + * Incomplete isochronous IN transfer interrupt. Assertion of the + * incomplete isochronous IN transfer interrupt indicates an incomplete + * isochronous IN transfer on at least one of the isochronous IN endpoints. * ****************************************************************************/ @@ -3293,8 +3374,9 @@ static inline void efm32_isocininterrupt(FAR struct efm32_usbdev_s *priv) { int i; - /* The application must read the endpoint control register for all isochronous - * IN endpoints to detect endpoints with incomplete IN data transfers. + /* The application must read the endpoint control register for all + * isochronous IN endpoints to detect endpoints with incomplete IN data + * transfers. */ for (i = 0; i < EFM32_NENDPOINTS; i++) @@ -3373,7 +3455,8 @@ static inline void efm32_isocoutinterrupt(FAR struct efm32_usbdev_s *priv) /* When it receives an IISOOXFR interrupt, the application must read the * control registers of all isochronous OUT endpoints to determine which * endpoints had an incomplete transfer in the current microframe. An - * endpoint transfer is incomplete if both the following conditions are true: + * endpoint transfer is incomplete if both the following conditions are + * true: * * DOEPCTLx:EONUM = DSTS:SOFFN[0], and * DOEPCTLx:EPENA = 1 @@ -3488,7 +3571,8 @@ static int efm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) /* At present, there is only a single OTG FS device support. Hence it is * pre-allocated as g_otgfsdev. However, in most code, the private data * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple devices. + * global data) in order to simplify any future support for multiple + * devices. */ FAR struct efm32_usbdev_s *priv = &g_otgfsdev; @@ -3522,7 +3606,8 @@ static int efm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) break; } - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_INTPENDING), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_INTPENDING), + (uint16_t)regval); /* OUT endpoint interrupt. The core sets this bit to indicate that an * interrupt is pending on one of the OUT endpoints of the core. @@ -3530,7 +3615,8 @@ static int efm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & USB_GINTSTS_OEPINT) != 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPOUT), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPOUT), + (uint16_t)regval); efm32_epout_interrupt(priv); } @@ -3540,7 +3626,8 @@ static int efm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & USB_GINTSTS_IEPINT) != 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPIN), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPIN), + (uint16_t)regval); efm32_epin_interrupt(priv); } @@ -3549,7 +3636,8 @@ static int efm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) #ifdef CONFIG_DEBUG_USB if ((regval & USB_GINTSTS_MODEMIS) != 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_MISMATCH), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_MISMATCH), + (uint16_t)regval); efm32_putreg(USB_GINTSTS_MODEMIS, EFM32_USB_GINTSTS); } #endif @@ -3558,7 +3646,8 @@ static int efm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & USB_GINTSTS_WKUPINT) != 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_WAKEUP), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_WAKEUP), + (uint16_t)regval); efm32_resumeinterrupt(priv); efm32_putreg(USB_GINTSTS_WKUPINT, EFM32_USB_GINTSTS); } @@ -3567,7 +3656,8 @@ static int efm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & USB_GINTSTS_USBSUSP) != 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_SUSPEND), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_SUSPEND), + (uint16_t)regval); efm32_suspendinterrupt(priv); efm32_putreg(USB_GINTSTS_USBSUSP, EFM32_USB_GINTSTS); } @@ -3577,7 +3667,8 @@ static int efm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) #ifdef CONFIG_USBDEV_SOFINTERRUPT if ((regval & USB_GINTSTS_SOF) != 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_SOF), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_SOF), + (uint16_t)regval); efm32_putreg(USB_GINTSTS_SOF, EFM32_USB_GINTSTS); } #endif @@ -3588,7 +3679,8 @@ static int efm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & USB_GINTSTS_RXFLVL) != 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_RXFIFO), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_RXFIFO), + (uint16_t)regval); efm32_rxinterrupt(priv); } @@ -3596,7 +3688,8 @@ static int efm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & USB_GINTSTS_USBRST) != 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_DEVRESET), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_DEVRESET), + (uint16_t)regval); /* Perform the device reset */ @@ -3610,7 +3703,8 @@ static int efm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & USB_GINTSTS_ENUMDONE) != 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_ENUMDNE), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_ENUMDNE), + (uint16_t)regval); efm32_enuminterrupt(priv); efm32_putreg(USB_GINTSTS_ENUMDONE, EFM32_USB_GINTSTS); } @@ -3624,7 +3718,8 @@ static int efm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) #ifdef CONFIG_USBDEV_ISOCHRONOUS if ((regval & USB_GINTSTS_IISOIXFR) != 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_IISOIXFR), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_IISOIXFR), + (uint16_t)regval); efm32_isocininterrupt(priv); efm32_putreg(USB_GINTSTS_IISOIXFR, EFM32_USB_GINTSTS); } @@ -3641,7 +3736,8 @@ static int efm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & USB_GINTSTS_IISOOXFR) != 0) { - usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_IISOOXFR), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_IISOOXFR), + (uint16_t)regval); efm32_isocoutinterrupt(priv); efm32_putreg(USB_GINTSTS_IISOOXFR, EFM32_USB_GINTSTS); } @@ -3710,11 +3806,11 @@ static void efm32_enablegonak(FAR struct efm32_ep_s *privep) #else /* Since we are in the interrupt handler, we cannot wait inline for the - * GONAKEFF because it cannot occur until service th RXFLVL global interrupt - * and pop the OUTNAK word from the RxFIFO. + * GONAKEFF because it cannot occur until service th RXFLVL global + * interrupt and pop the OUTNAK word from the RxFIFO. * - * Perhaps it is sufficient to wait for Global OUT NAK status to be reported - * in OTGFS DCTL register? + * Perhaps it is sufficient to wait for Global OUT NAK status to be + * reported in OTGFS DCTL register? */ while ((efm32_getreg(EFM32_USB_DCTL) & USB_DCTL_GOUTNAKSTS) == 0); @@ -3753,7 +3849,8 @@ static void efm32_disablegonak(FAR struct efm32_ep_s *privep) * ****************************************************************************/ -static int efm32_epout_configure(FAR struct efm32_ep_s *privep, uint8_t eptype, +static int efm32_epout_configure(FAR struct efm32_ep_s *privep, + uint8_t eptype, uint16_t maxpacket) { uint32_t mpsiz; @@ -3848,7 +3945,8 @@ static int efm32_epout_configure(FAR struct efm32_ep_s *privep, uint8_t eptype, * ****************************************************************************/ -static int efm32_epin_configure(FAR struct efm32_ep_s *privep, uint8_t eptype, +static int efm32_epin_configure(FAR struct efm32_ep_s *privep, + uint8_t eptype, uint16_t maxpacket) { uint32_t mpsiz; @@ -3896,7 +3994,6 @@ static int efm32_epin_configure(FAR struct efm32_ep_s *privep, uint8_t eptype, mpsiz = (maxpacket << _USB_DIEPCTL_MPS_SHIFT); } - /* If the endpoint is already active don't change the endpoint control * register. */ @@ -4041,7 +4138,9 @@ static void efm32_epout_disable(FAR struct efm32_ep_s *privep) regaddr = EFM32_USB_DOEPINT(privep->epphy); while ((efm32_getreg(regaddr) & USB_DOEPINT_EPDISBLD) == 0); #else + /* REVISIT: */ + up_udelay(10); #endif @@ -4114,7 +4213,9 @@ static void efm32_epin_disable(FAR struct efm32_ep_s *privep) regval |= (USB_DIEPCTL_EPDIS | USB_DIEPCTL_SNAK); efm32_putreg(regval, regaddr); - /* Wait for the INEPNE interrupt that indicates that we are now in NAK mode */ + /* Wait for the INEPNE interrupt that indicates that we are now in NAK + * mode + */ regaddr = EFM32_USB_DIEPINT(privep->epphy); while ((efm32_getreg(regaddr) & USB_DIEPINT_INEPNAKEFF) == 0); @@ -4243,7 +4344,8 @@ static FAR struct usbdev_req_s *efm32_ep_allocreq(FAR struct usbdev_ep_s *ep) * ****************************************************************************/ -static void efm32_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) +static void efm32_ep_freereq(FAR struct usbdev_ep_s *ep, + FAR struct usbdev_req_s *req) { FAR struct efm32_req_s *privreq = (FAR struct efm32_req_s *)req; @@ -4309,7 +4411,8 @@ static void efm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf) * ****************************************************************************/ -static int efm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) +static int efm32_ep_submit(FAR struct usbdev_ep_s *ep, + FAR struct usbdev_req_s *req) { FAR struct efm32_req_s *privreq = (FAR struct efm32_req_s *)req; FAR struct efm32_ep_s *privep = (FAR struct efm32_ep_s *)ep; @@ -4335,7 +4438,8 @@ static int efm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s * #ifdef CONFIG_DEBUG_FEATURES if (!priv->driver) { - usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); + usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_NOTCONFIGURED), + priv->usbdev.speed); return -ESHUTDOWN; } #endif @@ -4404,7 +4508,8 @@ static int efm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s * * ****************************************************************************/ -static int efm32_ep_cancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) +static int efm32_ep_cancel(FAR struct usbdev_ep_s *ep, + FAR struct usbdev_req_s *req) { FAR struct efm32_ep_s *privep = (FAR struct efm32_ep_s *)ep; irqstate_t flags; @@ -4443,8 +4548,8 @@ static int efm32_ep_cancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s * static int efm32_epout_setstall(FAR struct efm32_ep_s *privep) { #if 1 - /* This implementation follows the requirements from the EFM32 F4 reference - * manual. + /* This implementation follows the requirements from the EFM32 F4 + * reference manual. */ uint32_t regaddr; @@ -4471,7 +4576,9 @@ static int efm32_epout_setstall(FAR struct efm32_ep_s *privep) regaddr = EFM32_USB_DOEPINT(privep->epphy); while ((efm32_getreg(regaddr) & USB_DOEPINT_EPDISBLD) == 0); #else + /* REVISIT: */ + up_udelay(10); #endif @@ -4484,13 +4591,17 @@ static int efm32_epout_setstall(FAR struct efm32_ep_s *privep) privep->stalled = true; return OK; #else + /* This implementation follows the STMicro code example. */ + /* REVISIT: */ uint32_t regaddr; uint32_t regval; - /* Stall the OUT endpoint by setting the STALL bit in the DOECPTL register. */ + /* Stall the OUT endpoint by setting the STALL bit in the DOECPTL + * register. + */ regaddr = EFM32_USB_DOEPCTL(privep->epphy); regval = efm32_getreg(regaddr); @@ -4641,6 +4752,7 @@ static int efm32_ep_stall(FAR struct usbdev_ep_s *ep, bool resume) { ret = efm32_ep_setstall(privep); } + leave_critical_section(flags); return ret; @@ -4673,12 +4785,13 @@ static void efm32_ep0_stall(FAR struct efm32_usbdev_s *priv) * Allocate an endpoint matching the parameters. * * Input Parameters: - * eplog - 7-bit logical endpoint number (direction bit ignored). Zero means - * that any endpoint matching the other requirements will suffice. The - * assigned endpoint can be found in the eplog field. + * eplog - 7-bit logical endpoint number (direction bit ignored). Zero + * means that any endpoint matching the other requirements will + * suffice. The assigned endpoint can be found in the eplog + * field. * in - true: IN (device-to-host) endpoint requested - * eptype - Endpoint type. One of {USB_EP_ATTR_XFER_ISOC, USB_EP_ATTR_XFER_BULK, - * USB_EP_ATTR_XFER_INT} + * eptype - Endpoint type. One of {USB_EP_ATTR_XFER_ISOC, + * USB_EP_ATTR_XFER_BULK, USB_EP_ATTR_XFER_INT} * ****************************************************************************/ @@ -4707,8 +4820,9 @@ static FAR struct usbdev_ep_s *efm32_ep_alloc(FAR struct usbdev_s *dev, if (epphy > 0) { - /* Otherwise, we will return the endpoint structure only for the requested - * 'logical' endpoint. All of the other checks will still be performed. + /* Otherwise, we will return the endpoint structure only for the + * requested 'logical' endpoint. All of the other checks will still be + * performed. * * First, verify that the logical endpoint is in the range supported by * by the hardware. @@ -4767,7 +4881,8 @@ static FAR struct usbdev_ep_s *efm32_ep_alloc(FAR struct usbdev_s *dev, * ****************************************************************************/ -static void efm32_ep_free(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep) +static void efm32_ep_free(FAR struct usbdev_s *dev, + FAR struct usbdev_ep_s *ep) { FAR struct efm32_usbdev_s *priv = (FAR struct efm32_usbdev_s *)dev; FAR struct efm32_ep_s *privep = (FAR struct efm32_ep_s *)ep; @@ -5118,8 +5233,9 @@ static void efm32_hwinitialize(FAR struct efm32_usbdev_s *priv) uint32_t address; int i; - /* "The application must perform the following steps to initialize the core - * at device on, power on, or after a mode change from Host to Device. + /* "The application must perform the following steps to initialize the + * core at device on, power on, or after a mode change from Host to + * Device. * 1. Program the following fields in USB_DCFG register. * - Device Speed * - NonZero Length Status OUT Handshake @@ -5133,11 +5249,11 @@ static void efm32_hwinitialize(FAR struct efm32_usbdev_s *priv) * has been detected on the USB and lasts for about 10 ms. On receiving * this interrupt, the application must perform the steps listed in * Initialization on USB Reset ... - * 4. Wait for the USB_GINTSTS.ENUMDONE interrupt. This interrupt indicates - * the end of reset on the USB. On receiving this interrupt, the - * application must read the USB_DSTS register to determine the - * enumeration speed and perform the steps listed in Initialization on - * Enumeration Completion ..." + * 4. Wait for the USB_GINTSTS.ENUMDONE interrupt. This interrupt + * indicates the end of reset on the USB. On receiving this interrupt, + * the application must read the USB_DSTS register to determine the + * enumeration speed and perform the steps listed in Initialization + * on Enumeration Completion ..." * * "Initialization on USB Reset * 1. Set the NAK bit for all OUT endpoints @@ -5154,8 +5270,8 @@ static void efm32_hwinitialize(FAR struct efm32_usbdev_s *priv) * 4. Set up the Data FIFO RAM for each of the FIFOs * - Program the USB_GRXFSIZ Register, to be able to receive control * OUT data and setup data. At a minimum, this must be equal to 1 max - * packet size of control endpoint 0 + 2 DWORDs (for the status of the - * control OUT data packet) + 10 DWORDs (for setup packets). + * packet size of control endpoint 0 + 2 DWORDs (for the status of + * the control OUT data packet) + 10 DWORDs (for setup packets). * - Program the Device IN Endpoint Transmit FIFO size register * (depending on the FIFO number chosen), to be able to transmit * control IN data. At a minimum, this must be equal to 1 max packet @@ -5187,23 +5303,26 @@ static void efm32_hwinitialize(FAR struct efm32_usbdev_s *priv) /* Disable global interrupts by clearing the GINTMASK bit in the GAHBCFG * register; Set the TXFELVL bit in the GAHBCFG register so that TxFIFO - * interrupts will occur when the TxFIFO is truly empty (not just half full). + * interrupts will occur when the TxFIFO is truly empty (not just half + * full). */ /* I never saw this in original EFM32 lib * and in reference manual I found: - * "Non-periodic TxFIFO Empty Level (can be enabled only when the core is - * operating in Slave mode as a host.)" + * "Non-periodic TxFIFO Empty Level (can be enabled only when the core + * is operating in Slave mode as a host.)" */ efm32_putreg(USB_GAHBCFG_NPTXFEMPLVL_EMPTY, EFM32_USB_GAHBCFG); - //efm32_putreg(0, EFM32_USB_GAHBCFG); + + /* efm32_putreg(0, EFM32_USB_GAHBCFG); */ /* Enable PHY USB */ efm32_putreg(USB_ROUTE_PHYPEN, EFM32_USB_ROUTE); /* Common USB OTG core initialization */ + /* Reset after a PHY select and set Host mode. First, wait for AHB master * IDLE state. */ @@ -5237,12 +5356,14 @@ static void efm32_hwinitialize(FAR struct efm32_usbdev_s *priv) /* Force Device Mode */ regval = efm32_getreg(EFM32_USB_GUSBCFG); - regval &= ~(_USB_GUSBCFG_FORCEHSTMODE_MASK | _USB_GUSBCFG_CORRUPTTXPKT_MASK); + regval &= ~(_USB_GUSBCFG_FORCEHSTMODE_MASK | + _USB_GUSBCFG_CORRUPTTXPKT_MASK); regval |= USB_GUSBCFG_FORCEDEVMODE; efm32_putreg(regval, EFM32_USB_GUSBCFG); up_mdelay(50); /* Initialize device mode */ + /* Restart the PHY Clock */ efm32_putreg(0, EFM32_USB_PCGCCTL); @@ -5363,8 +5484,9 @@ static void efm32_hwinitialize(FAR struct efm32_usbdev_s *priv) /* Enable the interrupts in the INTMSK */ - regval = (USB_GINTMSK_RXFLVLMSK | USB_GINTMSK_USBSUSPMSK | USB_GINTMSK_ENUMDONEMSK | - USB_GINTMSK_IEPINTMSK | USB_GINTMSK_OEPINTMSK | USB_GINTMSK_USBRSTMSK); + regval = (USB_GINTMSK_RXFLVLMSK | USB_GINTMSK_USBSUSPMSK | + USB_GINTMSK_ENUMDONEMSK | USB_GINTMSK_IEPINTMSK | + USB_GINTMSK_OEPINTMSK | USB_GINTMSK_USBRSTMSK); #ifdef CONFIG_USBDEV_ISOCHRONOUS regval |= (USB_GINTMSK_INCOMPISOINMSK | USB_GINTMSK_INCOMPLPMSK); @@ -5407,9 +5529,9 @@ static void efm32_hwinitialize(FAR struct efm32_usbdev_s *priv) * Assumptions: * - This function is called very early in the initialization sequence * - PLL and GIO pin initialization is not performed here but should been in - * the low-level boot logic: PLL1 must be configured for operation at 48MHz - * and P0.23 and PO.31 in PINSEL1 must be configured for Vbus and USB connect - * LED. + * the low-level boot logic: PLL1 must be configured for operation at + * 48MHz and P0.23 and PO.31 in PINSEL1 must be configured for Vbus and USB + * connect LED. * ****************************************************************************/ @@ -5418,7 +5540,8 @@ void arm_usbinitialize(void) /* At present, there is only a single OTG FS device support. Hence it is * pre-allocated as g_otgfsdev. However, in most code, the private data * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple devices. + * global data) in order to simplify any future support for multiple + * devices. */ FAR struct efm32_usbdev_s *priv = &g_otgfsdev; @@ -5460,7 +5583,8 @@ void arm_usbinitialize(void) */ /* Uninitialize the hardware so that we know that we are starting from a - * known state. */ + * known state. + */ arm_usbuninitialize(); @@ -5507,7 +5631,8 @@ void arm_usbuninitialize(void) /* At present, there is only a single OTG FS device support. Hence it is * pre-allocated as g_otgfsdev. However, in most code, the private data * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple devices. + * global data) in order to simplify any future support for multiple + * devices. */ FAR struct efm32_usbdev_s *priv = &g_otgfsdev; @@ -5572,8 +5697,8 @@ void arm_usbuninitialize(void) * Name: usbdev_register * * Description: - * Register a USB device class driver. The class driver's bind() method will be - * called to bind it to a USB device driver. + * Register a USB device class driver. The class driver's bind() method + * will be called to bind it to a USB device driver. * ****************************************************************************/ @@ -5582,7 +5707,8 @@ int usbdev_register(struct usbdevclass_driver_s *driver) /* At present, there is only a single OTG FS device support. Hence it is * pre-allocated as g_otgfsdev. However, in most code, the private data * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple devices. + * global data) in order to simplify any future support for multiple + * devices. */ FAR struct efm32_usbdev_s *priv = &g_otgfsdev; @@ -5642,9 +5768,10 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * Name: usbdev_unregister * * Description: - * Un-register usbdev class driver.If the USB device is connected to a USB host, - * it will first disconnect(). The driver is also requested to unbind() and clean - * up any device state, before this procedure finally returns. + * Un-register usbdev class driver.If the USB device is connected to a USB + * host, it will first disconnect(). The driver is also requested to + * unbind() and clean up any device state, before this procedure finally + * returns. * ****************************************************************************/ @@ -5653,7 +5780,8 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) /* At present, there is only a single OTG FS device support. Hence it is * pre-allocated as g_otgfsdev. However, in most code, the private data * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple devices. + * global data) in order to simplify any future support for multiple + * devices. */ FAR struct efm32_usbdev_s *priv = &g_otgfsdev; diff --git a/arch/arm/src/efm32/hardware/efm32_acmp.h b/arch/arm/src/efm32/hardware/efm32_acmp.h index 901a17e0846..c6083a0029e 100644 --- a/arch/arm/src/efm32/hardware/efm32_acmp.h +++ b/arch/arm/src/efm32/hardware/efm32_acmp.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_acmp.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ACMP_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ACMP_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,10 +72,11 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ -/* ACMP Register Offsets *******************************************************************************************************/ + ****************************************************************************/ + +/* ACMP Register Offsets ****************************************************/ #define EFM32_ACMP_CTRL_OFFSET 0x0000 /* Control Register */ #define EFM32_ACMP_INPUTSEL_OFFSET 0x0004 /* Input Selection Register */ @@ -86,7 +87,7 @@ #define EFM32_ACMP_IFC_OFFSET 0x0018 /* Interrupt Flag Clear Register */ #define EFM32_ACMP_ROUTE_OFFSET 0x001c /* I/O Routing Register */ -/* ACMP Register Addresses *****************************************************************************************************/ +/* ACMP Register Addresses **************************************************/ #define EFM32_ACMP0_CTRL (EFM32_ACMP0_BASE+EFM32_ACMP_CTRL_OFFSET) #define EFM32_ACMP0_INPUTSEL (EFM32_ACMP0_BASE+EFM32_ACMP_INPUTSEL_OFFSET) @@ -106,7 +107,7 @@ #define EFM32_ACMP1_IFC (EFM32_ACMP1_BASE+EFM32_ACMP_IFC_OFFSET) #define EFM32_ACMP1_ROUTE (EFM32_ACMP1_BASE+EFM32_ACMP_ROUTE_OFFSET) -/* ACMP Register Bit Field Definitions *****************************************************************************************/ +/* ACMP Register Bit Field Definitions **************************************/ /* Bit fields for ACMP CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_adc.h b/arch/arm/src/efm32/hardware/efm32_adc.h index 2f7c2418989..f12de7c29b3 100644 --- a/arch/arm/src/efm32/hardware/efm32_adc.h +++ b/arch/arm/src/efm32/hardware/efm32_adc.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_adc.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ADC_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ADC_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,10 +72,11 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ -/* ADC Register Offsets ********************************************************************************************************/ + ****************************************************************************/ + +/* ADC Register Offsets *****************************************************/ #define EFM32_ADC_CTRL_OFFSET 0x0000 /* Control Register */ #define EFM32_ADC_CMD_OFFSET 0x0004 /* Command Register */ @@ -93,7 +94,7 @@ #define EFM32_ADC_CAL_OFFSET 0x0034 /* Calibration Register */ #define EFM32_ADC_BIASPROG_OFFSET 0x003c /* Bias Programming Register */ -/* ADC Register Addresses ******************************************************************************************************/ +/* ADC Register Addresses ***************************************************/ #define EFM32_ADC0_CTRL (EFM32_ADC0_BASE+EFM32_ADC_CTRL_OFFSET) #define EFM32_ADC0_CMD (EFM32_ADC0_BASE+EFM32_ADC_CMD_OFFSET) @@ -111,7 +112,7 @@ #define EFM32_ADC0_CAL (EFM32_ADC0_BASE+EFM32_ADC_CAL_OFFSET) #define EFM32_ADC0_BIASPROG (EFM32_ADC0_BASE+EFM32_ADC_BIASPROG_OFFSET) -/* ADC Register Bit Field Definitions ******************************************************************************************/ +/* ADC Register Bit Field Definitions ***************************************/ /* Bit fields for ADC CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_aes.h b/arch/arm/src/efm32/hardware/efm32_aes.h index 572b8e7d04e..a21bc259307 100644 --- a/arch/arm/src/efm32/hardware/efm32_aes.h +++ b/arch/arm/src/efm32/hardware/efm32_aes.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_aes.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_AES_H_ #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_AES_H_ -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,10 +72,11 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ -/* AES Register Offsets ********************************************************************************************************/ + ****************************************************************************/ + +/* AES Register Offsets *****************************************************/ #define EFM32_AES_CTRL_OFFSET 0x0000 /* Control Register */ #define EFM32_AES_CMD_OFFSET 0x0004 /* Command Register */ @@ -95,7 +96,7 @@ #define EFM32_AES_KEYHC_OFFSET 0x0048 /* KEY High Register */ #define EFM32_AES_KEYHD_OFFSET 0x004c /* KEY High Register */ -/* AES Register Addresses ******************************************************************************************************/ +/* AES Register Addresses ***************************************************/ #define EFM32_AES_CTRL (EFM32_AES_BASE+EFM32_AES_CTRL_OFFSET) #define EFM32_AES_CMD (EFM32_AES_BASE+EFM32_AES_CMD_OFFSET) @@ -115,7 +116,7 @@ #define EFM32_AES_KEYHC (EFM32_AES_BASE+EFM32_AES_KEYHC_OFFSET) #define EFM32_AES_KEYHD (EFM32_AES_BASE+EFM32_AES_KEYHD_OFFSET) -/* AES Register Bit Field Definitions ******************************************************************************************/ +/* AES Register Bit Field Definitions ***************************************/ /* Bit fields for AES CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_burtc.h b/arch/arm/src/efm32/hardware/efm32_burtc.h index 08fe3d68ba7..22a7f1247d2 100644 --- a/arch/arm/src/efm32/hardware/efm32_burtc.h +++ b/arch/arm/src/efm32/hardware/efm32_burtc.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_burtc.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_BURTC_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_BURTC_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,13 +72,13 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ + ****************************************************************************/ #define EFM32_BURTC_NREGS 128 /* Number of backup retention registers */ -/* BURTC Register Offsets ******************************************************************************************************/ +/* BURTC Register Offsets ***************************************************/ #define EFM32_BURTC_CTRL_OFFSET 0x0000 /* Control Register */ #define EFM32_BURTC_LPMODE_OFFSET 0x0004 /* Low power mode configuration */ @@ -101,7 +101,7 @@ #define EFM32_BURTC_RET_REG_OFFSET(n) (0x0100 + ((n) << 2)) -/* BURTC Register Addresses ****************************************************************************************************/ +/* BURTC Register Addresses *************************************************/ #define EFM32_BURTC_CTRL (EFM32_BCKRTC_BASE+EFM32_BURTC_CTRL_OFFSET) #define EFM32_BURTC_LPMODE (EFM32_BCKRTC_BASE+EFM32_BURTC_LPMODE_OFFSET) @@ -124,7 +124,7 @@ #define EFM32_BURTC_RET_REG(n) (EFM32_BCKRTC_BASE+EFM32_BURTC_RET_REG_OFFSET(n)) -/* BURTC Register Bit Field Definitions ****************************************************************************************/ +/* BURTC Register Bit Field Definitions *************************************/ /* Bit fields for BURTC CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_calibrate.h b/arch/arm/src/efm32/hardware/efm32_calibrate.h index 1776611ed78..32026e0f57d 100644 --- a/arch/arm/src/efm32/hardware/efm32_calibrate.h +++ b/arch/arm/src/efm32/hardware/efm32_calibrate.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_calibrate.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_CALIBRATE_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_CALIBRATE_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,17 +72,17 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ + ****************************************************************************/ #define CALIBRATE_MAX_REGISTERS 50 /* Max number of address/value pairs for calibration */ #define CALIBRATE ((const struct efm32_calibrate_s *)EFM32_CALIBRATE_BASE) -/******************************************************************************************************************************* +/**************************************************************************** * Public Type Definitions - *******************************************************************************************************************************/ + ****************************************************************************/ struct efm32_calibrate_s { diff --git a/arch/arm/src/efm32/hardware/efm32_cmu.h b/arch/arm/src/efm32/hardware/efm32_cmu.h index f973156d0b3..2e5a4b075c9 100644 --- a/arch/arm/src/efm32/hardware/efm32_cmu.h +++ b/arch/arm/src/efm32/hardware/efm32_cmu.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************** +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_cmu.h * * (C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_CMU_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_CMU_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,9 +72,10 @@ # warning This is the EFM32GG/G header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ + ****************************************************************************/ + /* Maximum allowed core frequency when using 0 wait states on flash access */ #define CMU_MAX_FREQ_0WS 16000000 @@ -87,13 +88,15 @@ #define CMU_MAX_FREQ_2WS 48000000 -/* Maximum frequency that HFLE needs to be enabled on Giant, Leopard and Wonder parts. */ +/* Maximum frequency that HFLE needs to be enabled on Giant, + * Leopard and Wonder parts. + */ #if defined(CONFIG_EFM32_EFM32GG) # define CMU_MAX_FREQ_HFLE 32000000 #endif -/* CMU Register Offsets ********************************************************************************************************/ +/* CMU Register Offsets *****************************************************/ #define EFM32_CMU_CTRL_OFFSET 0x0000 /* CMU Control Register */ #define EFM32_CMU_HFCORECLKDIV_OFFSET 0x0004 /* High Frequency Core Clock Division Register */ @@ -124,7 +127,7 @@ #define EFM32_CMU_ROUTE_OFFSET 0x0080 /* I/O Routing Register */ #define EFM32_CMU_LOCK_OFFSET 0x0084 /* Configuration Lock Register */ -/* CMU Register Addresses ******************************************************************************************************/ +/* CMU Register Addresses ***************************************************/ #define EFM32_CMU_CTRL (EFM32_CMU_BASE+EFM32_CMU_CTRL_OFFSET) #define EFM32_CMU_HFCORECLKDIV (EFM32_CMU_BASE+EFM32_CMU_HFCORECLKDIV_OFFSET) @@ -155,7 +158,7 @@ #define EFM32_CMU_ROUTE (EFM32_CMU_BASE+EFM32_CMU_ROUTE_OFFSET) #define EFM32_CMU_LOCK (EFM32_CMU_BASE+EFM32_CMU_LOCK_OFFSET) -/* CMU Register Bit Definitions ************************************************************************************************/ +/* CMU Register Bit Definitions *********************************************/ /* Bit fields for CMU CTRL */ @@ -1022,7 +1025,7 @@ # define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2) /* Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ # define CMU_HFCORECLKEN0_EBI (0x1UL << 3) /* External Bus Interface Clock Enable */ # define _CMU_HFCORECLKEN0_EBI_SHIFT 3 /* Shift value for CMU_EBI */ -# define _CMU_HFCORECLKEN0_EBI_MASK 0x8UL /* Bit mask for CMU_EBI */ +# define _CMU_HFCORECLKEN0_EBI_MASK 0x8UL /* Bit mask for CMU_EBI */ # define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /* Mode DEFAULT for CMU_HFCORECLKEN0 */ # define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 3) /* Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ #elif defined(CONFIG_EFM32_EFM32GG) diff --git a/arch/arm/src/efm32/hardware/efm32_dac.h b/arch/arm/src/efm32/hardware/efm32_dac.h index 80a4b8dc488..efe4fc32c8f 100644 --- a/arch/arm/src/efm32/hardware/efm32_dac.h +++ b/arch/arm/src/efm32/hardware/efm32_dac.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_dac.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DAC_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DAC_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,10 +72,11 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ -/* DAC Register Offsets ********************************************************************************************************/ + ****************************************************************************/ + +/* DAC Register Offsets *****************************************************/ #define EFM32_DAC_CTRL_OFFSET 0x0000 /* Control Register */ #define EFM32_DAC_STATUS_OFFSET 0x0004 /* Status Register */ @@ -96,7 +97,7 @@ #define EFM32_DAC_OPA1MUX_OFFSET 0x0060 /* Operational Amplifier Mux Configuration Register */ #define EFM32_DAC_OPA2MUX_OFFSET 0x0064 /* Operational Amplifier Mux Configuration Register */ -/* DAC Register Addresses ******************************************************************************************************/ +/* DAC Register Addresses ***************************************************/ #define EFM32_DAC0_CTRL (EFM32_DAC0_BASE+EFM32_DAC_CTRL_OFFSET) #define EFM32_DAC0_STATUS (EFM32_DAC0_BASE+EFM32_DAC_STATUS_OFFSET) @@ -117,7 +118,7 @@ #define EFM32_DAC0_OPA1MUX (EFM32_DAC0_BASE+EFM32_DAC_OPA1MUX_OFFSET) #define EFM32_DAC0_OPA2MUX (EFM32_DAC0_BASE+EFM32_DAC_OPA2MUX_OFFSET) -/* DAC Register Bit Field Definitions ******************************************************************************************/ +/* DAC Register Bit Field Definitions ***************************************/ /* Bit fields for DAC CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_devinfo.h b/arch/arm/src/efm32/hardware/efm32_devinfo.h index d3279f02ff9..05472cdeaf9 100644 --- a/arch/arm/src/efm32/hardware/efm32_devinfo.h +++ b/arch/arm/src/efm32/hardware/efm32_devinfo.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_devinfo.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DEVINFO_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DEVINFO_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,12 +72,11 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ + ****************************************************************************/ - -/* MSC Register Offsets ********************************************************************************************************/ +/* MSC Register Offsets *****************************************************/ #define EFM32_DEVINFO_CAL_OFFSET 0x0000 #define EFM32_DEVINFO_ADC0CALn_OFFSET(n) (0x0004+(n)*4) @@ -90,7 +89,7 @@ #define EFM32_DEVINFO_MEMINFO_SIZE_OFFSET 0x0048 #define EFM32_DEVINFO_PART_OFFSET 0x004c -/* MSC Register Addresses ******************************************************************************************************/ +/* MSC Register Addresses ***************************************************/ #define EFM32_DEVINFO_CAL (EFM32_DEVINFO_BASE+EFM32_DEVINFO_CAL_OFFSET) @@ -221,9 +220,8 @@ #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0x0000FFFFUL /* Device number */ #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /* Bit position for device number */ -/******************************************************************************************************************************* +/**************************************************************************** * Public Type Definitions - *******************************************************************************************************************************/ - + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DEVINFO_H */ diff --git a/arch/arm/src/efm32/hardware/efm32_dma.h b/arch/arm/src/efm32/hardware/efm32_dma.h index 79342e8f24a..86ef8012d88 100644 --- a/arch/arm/src/efm32/hardware/efm32_dma.h +++ b/arch/arm/src/efm32/hardware/efm32_dma.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_dma.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DMA_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DMA_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,9 +72,9 @@ # warning This is the EFM32GG/G header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_EFM32_EFM32GG) # define EFM32_DMA_NCHANNELS 12 @@ -82,7 +82,7 @@ # define EFM32_DMA_NCHANNELS 8 #endif -/* DMA Register Offsets ********************************************************************************************************/ +/* DMA Register Offsets *****************************************************/ #define EFM32_DMA_STATUS_OFFSET 0x0000 /* DMA Status Registers */ #define EFM32_DMA_CONFIG_OFFSET 0x0004 /* DMA Configuration Register */ @@ -116,6 +116,7 @@ #endif #define EFM32_DMA_CHn_CTRL_OFFSET(n) (0x1100+((n)<<2)) /* Channel n Control Register */ + #define EFM32_DMA_CH0_CTRL_OFFSET 0x1100 /* Channel 0 Control Register */ #define EFM32_DMA_CH1_CTRL_OFFSET 0x1104 /* Channel 1 Control Register */ #define EFM32_DMA_CH2_CTRL_OFFSET 0x1108 /* Channel 2 Control Register */ @@ -131,7 +132,7 @@ # define EFM32_DMA_CH11_CTRL_OFFSET 0x112c /* Channel 11 Control Register */ #endif -/* DMA Register Addresses ******************************************************************************************************/ +/* DMA Register Addresses ***************************************************/ #define EFM32_DMA_STATUS (EFM32_DMA_BASE+EFM32_DMA_STATUS_OFFSET) #define EFM32_DMA_CONFIG (EFM32_DMA_BASE+EFM32_DMA_CONFIG_OFFSET) @@ -180,7 +181,7 @@ # define EFM32_DMA_CH11_CTRL (EFM32_DMA_BASE+EFM32_DMA_CH11_CTRL_OFFSET) #endif -/* DMA Register Bit Field Definitions ******************************************************************************************/ +/* DMA Register Bit Field Definitions ***************************************/ /* Bit fields for DMA STATUS */ @@ -2067,7 +2068,7 @@ #endif -/* DMA Descriptor Bit Field Definitions ****************************************************************************************/ +/* DMA Descriptor Bit Field Definitions *************************************/ #define _DMA_CTRL_DST_INC_MASK 0xC0000000UL /* Data increment for destination, bit mask */ #define _DMA_CTRL_DST_INC_SHIFT 30 /* Data increment for destination, shift value */ @@ -2166,7 +2167,7 @@ #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x000000006UL /* Peripheral scatter gather cycle type */ #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x000000007UL /* Peripheral scatter gather cycle type using alternate structure */ -/* DMA Request Bit Definitions *************************************************************************************************/ +/* DMA Request Bit Definitions **********************************************/ #if defined(CONFIG_EFM32_EFM32GG) # define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /* DMA channel select for ADC0_SINGLE */ @@ -2272,9 +2273,9 @@ # define DMAREQ_AES_KEYWR ((49 << 16) + 3) /* DMA channel select for AES_KEYWR */ #endif -/******************************************************************************************************************************* +/**************************************************************************** * Public Types - *******************************************************************************************************************************/ + ****************************************************************************/ struct dma_descriptor_s { diff --git a/arch/arm/src/efm32/hardware/efm32_emu.h b/arch/arm/src/efm32/hardware/efm32_emu.h index 675db59439e..f7b2db83673 100644 --- a/arch/arm/src/efm32/hardware/efm32_emu.h +++ b/arch/arm/src/efm32/hardware/efm32_emu.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_emu.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_EMU_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_EMU_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,10 +72,11 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ -/* EMU Register Offsets ********************************************************************************************************/ + ****************************************************************************/ + +/* EMU Register Offsets *****************************************************/ #define EFM32_EMU_CTRL_OFFSET 0x0000 /* Control Register */ #define EFM32_EMU_MEMCTRL_OFFSET 0x0004 /* Memory Control Register */ @@ -95,7 +96,7 @@ #define EFM32_EMU_BUBODBUVINCAL_OFFSET 0x0058 /* BU_VIN Backup BOD calibration */ #define EFM32_EMU_BUBODUNREGCAL_OFFSET 0x005c /* Unregulated power Backup BOD calibration */ -/* EMU Register Addresses ******************************************************************************************************/ +/* EMU Register Addresses ***************************************************/ #define EFM32_EMU_CTRL (EFM32_EMU_BASE+EFM32_EMU_CTRL_OFFSET) #define EFM32_EMU_MEMCTRL (EFM32_EMU_BASE+EFM32_EMU_MEMCTRL_OFFSET) @@ -115,7 +116,7 @@ #define EFM32_EMU_BUBODBUVINCAL (EFM32_EMU_BASE+EFM32_EMU_BUBODBUVINCAL_OFFSET) #define EFM32_EMU_BUBODUNREGCAL (EFM32_EMU_BASE+EFM32_EMU_BUBODUNREGCAL_OFFSET) -/* EMU Register Bit Field Definitions ******************************************************************************************/ +/* EMU Register Bit Field Definitions ***************************************/ /* Bit fields for EMU CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_flash.h b/arch/arm/src/efm32/hardware/efm32_flash.h index b2af16f773e..e2aa0f6e918 100644 --- a/arch/arm/src/efm32/hardware/efm32_flash.h +++ b/arch/arm/src/efm32/hardware/efm32_flash.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_flash.h * * Copyright (C) 2015 Bouteville Pierre-Noel. All rights reserved. @@ -31,14 +31,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_FLASH_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_FLASH_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_EFM32_EFM32GG) # define EFM32_FLASH_PAGESIZE 4096 diff --git a/arch/arm/src/efm32/hardware/efm32_gpio.h b/arch/arm/src/efm32/hardware/efm32_gpio.h index 7287c8e61d4..6c52f83d341 100644 --- a/arch/arm/src/efm32/hardware/efm32_gpio.h +++ b/arch/arm/src/efm32/hardware/efm32_gpio.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_gpio.h * * (C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_GPIO_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_GPIO_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,11 +72,11 @@ # warning This is the EFM32GG/G header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ + ****************************************************************************/ -/* GPIO Register Offsets *******************************************************************************************************/ +/* GPIO Register Offsets ****************************************************/ #define EFM32_GPIIO_PA 0 #define EFM32_GPIIO_PB 1 @@ -183,7 +183,7 @@ # define EFM32_GPIO_EM4WUCAUSE_OFFSET 0x13c /* EM4 Wake-up Cause Register */ #endif -/* GPIO Register Addresses *****************************************************************************************************/ +/* GPIO Register Addresses **************************************************/ #define EFM32_GPIO_Pn_BASE(n) (EFM32_GPIO_BASE+EFM32_GPIO_Pn_OFFSET(n)) #define EFM32_GPIO_PA_BASE (EFM32_GPIO_BASE+EFM32_GPIO_PA_OFFSET) @@ -283,7 +283,7 @@ # define EFM32_GPIO_EM4WUCAUSE (EFM32_GPIO_BASE+EFM32_GPIO_EM4WUCAUSE_OFFSET) #endif -/* GPIO Register Bit Field Definitions *****************************************************************************************/ +/* GPIO Register Bit Field Definitions **************************************/ /* Bit fields for GPIO P_CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_i2c.h b/arch/arm/src/efm32/hardware/efm32_i2c.h index 97eb5e09ce4..939c5f89cb7 100644 --- a/arch/arm/src/efm32/hardware/efm32_i2c.h +++ b/arch/arm/src/efm32/hardware/efm32_i2c.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_i2c.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_I2C_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_I2C_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,10 +72,11 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ -/* I2C Register Offsets ********************************************************************************************************/ + ****************************************************************************/ + +/* I2C Register Offsets *****************************************************/ #define EFM32_I2C_CTRL_OFFSET 0x0000 /* Control Register */ #define EFM32_I2C_CMD_OFFSET 0x0004 /* Command Register */ @@ -93,7 +94,7 @@ #define EFM32_I2C_IEN_OFFSET 0x0034 /* Interrupt Enable Register */ #define EFM32_I2C_ROUTE_OFFSET 0x0038 /* I/O Routing Register */ -/* I2C Register Addresses ******************************************************************************************************/ +/* I2C Register Addresses ***************************************************/ #define EFM32_I2C0_CTRL (EFM32_I2C0_BASE+EFM32_I2C_CTRL_OFFSET) #define EFM32_I2C0_CMD (EFM32_I2C0_BASE+EFM32_I2C_CMD_OFFSET) @@ -127,7 +128,7 @@ #define EFM32_I2C1_IEN (EFM32_I2C1_BASE+EFM32_I2C_IEN_OFFSET) #define EFM32_I2C1_ROUTE (EFM32_I2C1_BASE+EFM32_I2C_ROUTE_OFFSET) -/* I2C Register Bit Field Definitions ******************************************************************************************/ +/* I2C Register Bit Field Definitions ***************************************/ /* Bit fields for I2C CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_lcd.h b/arch/arm/src/efm32/hardware/efm32_lcd.h index ccc84640f6f..0f4dcb9f3ee 100644 --- a/arch/arm/src/efm32/hardware/efm32_lcd.h +++ b/arch/arm/src/efm32/hardware/efm32_lcd.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_lcd.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LCD_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LCD_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,10 +72,11 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ -/* LCD Register Offsets ********************************************************************************************************/ + ****************************************************************************/ + +/* LCD Register Offsets *****************************************************/ #define EFM32_LCD_CTRL_OFFSET 0x0000 /* Control Register */ #define EFM32_LCD_DISPCTRL_OFFSET 0x0004 /* Display Control Register */ @@ -107,7 +108,7 @@ #define EFM32_LCD_SEGD6L_OFFSET 0x00d4 /* Segment Data Low Register 6 */ #define EFM32_LCD_SEGD7L_OFFSET 0x00d8 /* Segment Data Low Register 7 */ -/* LCD Register Addresses ******************************************************************************************************/ +/* LCD Register Addresses ***************************************************/ #define EFM32_LCD_CTRL (EFM32_LCD_BASE+EFM32_LCD_CTRL_OFFSET) #define EFM32_LCD_DISPCTRL (EFM32_LCD_BASE+EFM32_LCD_DISPCTRL_OFFSET) @@ -139,7 +140,7 @@ #define EFM32_LCD_SEGD6L (EFM32_LCD_BASE+EFM32_LCD_SEGD6L_OFFSET) #define EFM32_LCD_SEGD7L (EFM32_LCD_BASE+EFM32_LCD_SEGD7L_OFFSET) -/* LCD Register Bit Field Definitions ******************************************************************************************/ +/* LCD Register Bit Field Definitions ***************************************/ /* Bit fields for LCD CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_lesense.h b/arch/arm/src/efm32/hardware/efm32_lesense.h index b933f7f0545..f1766789c45 100644 --- a/arch/arm/src/efm32/hardware/efm32_lesense.h +++ b/arch/arm/src/efm32/hardware/efm32_lesense.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_lesense.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LESENSE_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LESENSE_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,10 +72,11 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ -/* LESENSE Register Offsets ****************************************************************************************************/ + ****************************************************************************/ + +/* LESENSE Register Offsets *************************************************/ #define EFM32_LESENSE_CTRL_OFFSET 0x0000 /* Control Register */ #define EFM32_LESENSE_TIMCTRL_OFFSET 0x0004 /* Timing Control Register */ @@ -162,7 +163,7 @@ #define EFM32_LESENSE_CHn_INTERACT_OFFSET 0x0004 /* Channel n Scan Configuration */ #define EFM32_LESENSE_CHn_EVAL_OFFSET 0x0008 /* Channel n Scan Configuration */ -/* LESENSE Register Addresses **************************************************************************************************/ +/* LESENSE Register Addresses ***********************************************/ #define EFM32_LESENSE_CTRL (EFM32_LESENSE_BASE+EFM32_LESENSE_CTRL_OFFSET) #define EFM32_LESENSE_TIMCTRL (EFM32_LESENSE_BASE+EFM32_LESENSE_TIMCTRL_OFFSET) @@ -249,7 +250,7 @@ #define EFM32_LESENSE_CH_INTERACT(n) (EFM32_LESENSE_CH_BASE(n)+EFM32_LESENSE_CHn_INTERACT_OFFSET) #define EFM32_LESENSE_CH_EVAL(n) (EFM32_LESENSE_CH_BASE(n)+EFM32_LESENSE_CHb_EVAL_OFFSET) -/* LESENSE Register Bit Field Definitions **************************************************************************************/ +/* LESENSE Register Bit Field Definitions ***********************************/ /* Bit fields for LESENSE CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_letimer.h b/arch/arm/src/efm32/hardware/efm32_letimer.h index 526dfaaa7ef..25dff510916 100644 --- a/arch/arm/src/efm32/hardware/efm32_letimer.h +++ b/arch/arm/src/efm32/hardware/efm32_letimer.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_letimer.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LETIMER_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LETIMER_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,10 +72,11 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ -/* LETIMER Register Offsets ****************************************************************************************************/ + ****************************************************************************/ + +/* LETIMER Register Offsets *************************************************/ #define EFM32_LETIMER_CTRL_OFFSET 0x0000 /* Control Register */ #define EFM32_LETIMER_CMD_OFFSET 0x0004 /* Command Register */ @@ -93,7 +94,7 @@ #define EFM32_LETIMER_SYNCBUSY_OFFSET 0x0034 /* Synchronization Busy Register */ #define EFM32_LETIMER_ROUTE_OFFSET 0x0040 /* I/O Routing Register */ -/* LETIMER Register Addresses **************************************************************************************************/ +/* LETIMER Register Addresses ***********************************************/ #define EFM32_LETIMER0_CTRL (EFM32_LETIMER0_BASE+EFM32_LETIMER0_CTRL_OFFSET) #define EFM32_LETIMER0_CMD (EFM32_LETIMER0_BASE+EFM32_LETIMER0_CMD_OFFSET) @@ -111,7 +112,7 @@ #define EFM32_LETIMER0_SYNCBUSY (EFM32_LETIMER0_BASE+EFM32_LETIMER0_SYNCBUSY_OFFSET) #define EFM32_LETIMER0_ROUTE (EFM32_LETIMER0_BASE+EFM32_LETIMER0_ROUTE_OFFSET) -/* LETIMER Register Bit Field Definitions **************************************************************************************/ +/* LETIMER Register Bit Field Definitions ***********************************/ /* Bit fields for LETIMER CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_leuart.h b/arch/arm/src/efm32/hardware/efm32_leuart.h index 3df012c2086..b8ae69d42ba 100644 --- a/arch/arm/src/efm32/hardware/efm32_leuart.h +++ b/arch/arm/src/efm32/hardware/efm32_leuart.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_leuart.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LEUART_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LEUART_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,10 +72,11 @@ # warning This is the EFM32GG/G header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ -/* LEUART Register Offsets *****************************************************************************************************/ + ****************************************************************************/ + +/* LEUART Register Offsets **************************************************/ #define EFM32_LEUART_CTRL_OFFSET 0x0000 /* Control Register */ #define EFM32_LEUART_CMD_OFFSET 0x0004 /* Command Register */ @@ -101,7 +102,7 @@ # define EFM32_LEUART_INPUT_OFFSET 0x00ac /* LEUART Input Register */ #endif -/* LEUART Register Addresses ***************************************************************************************************/ +/* LEUART Register Addresses ************************************************/ #define EFM32_LEUART0_CTRL (EFM32_LEUART0_BASE+EFM32_LEUART_CTRL_OFFSET) #define EFM32_LEUART0_CMD (EFM32_LEUART0_BASE+EFM32_LEUART_CMD_OFFSET) @@ -153,7 +154,7 @@ # endif #endif -/* LEUART Register Bit Field Definitions ***************************************************************************************/ +/* LEUART Register Bit Field Definitions ************************************/ /* Bit fields for LEUART CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_memorymap.h b/arch/arm/src/efm32/hardware/efm32_memorymap.h index b1ad38cf6eb..42d94a76d56 100644 --- a/arch/arm/src/efm32/hardware/efm32_memorymap.h +++ b/arch/arm/src/efm32/hardware/efm32_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_MEMORYMAP_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" diff --git a/arch/arm/src/efm32/hardware/efm32_msc.h b/arch/arm/src/efm32/hardware/efm32_msc.h index 1391e1647a1..7ae8387ae35 100644 --- a/arch/arm/src/efm32/hardware/efm32_msc.h +++ b/arch/arm/src/efm32/hardware/efm32_msc.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_msc.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,22 +56,22 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_EFM32_EFM32_MSC_H #define __ARCH_ARM_SRC_EFM32_EFM32_EFM32_MSC_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include "hardware/efm32_memorymap.h" -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ + ****************************************************************************/ -/* MSC Register Offsets ********************************************************************************************************/ +/* MSC Register Offsets *****************************************************/ #define EFM32_MSC_CTRL_OFFSET 0x0000 /* Memory System Control Register */ #define EFM32_MSC_READCTRL_OFFSET 0x0004 /* Read Control Register */ @@ -94,7 +94,7 @@ # define EFM32_MSC_MASSLOCK_OFFSET 0x0054 /* Mass Erase Lock Register */ #endif -/* MSC Register Addresses ******************************************************************************************************/ +/* MSC Register Addresses ***************************************************/ #define EFM32_MSC_CTRL (EFM32_MSC_BASE+EFM32_MSC_CTRL_OFFSET) #define EFM32_MSC_READCTRL (EFM32_MSC_BASE+EFM32_MSC_READCTRL_OFFSET) @@ -117,7 +117,7 @@ # define EFM32_MSC_MASSLOCK (EFM32_MSC_BASE+EFM32_MSC_MASSLOCK_OFFSET) #endif -/* MSC Register Bit Field Definitions ******************************************************************************************/ +/* MSC Register Bit Field Definitions ***************************************/ /* Bit fields for MSC CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_pcnt.h b/arch/arm/src/efm32/hardware/efm32_pcnt.h index 650c69381a5..0462d8d46c3 100644 --- a/arch/arm/src/efm32/hardware/efm32_pcnt.h +++ b/arch/arm/src/efm32/hardware/efm32_pcnt.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_pcnt.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_PCNT_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_PCNT_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,10 +72,11 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ -/* PCNT Register Offsets *******************************************************************************************************/ + ****************************************************************************/ + +/* PCNT Register Offsets ****************************************************/ #define EFM32_PCNT_CTRL_OFFSET 0x0000 /* Control Register */ #define EFM32_PCNT_CMD_OFFSET 0x0004 /* Command Register */ @@ -93,7 +94,7 @@ #define EFM32_PCNT_AUXCNT_OFFSET 0x0038 /* Auxiliary Counter Value Register */ #define EFM32_PCNT_INPUT_OFFSET 0x003c /* PCNT Input Register */ -/* PCNT Register Addresses *****************************************************************************************************/ +/* PCNT Register Addresses **************************************************/ #define EFM32_PCNT0_CTRL (EFM32_PCNT0_BASE+EFM32_PCNT_CTRL_OFFSET) #define EFM32_PCNT0_CMD (EFM32_PCNT0_BASE+EFM32_PCNT_CMD_OFFSET) @@ -143,7 +144,7 @@ #define EFM32_PCNT2_AUXCNT (EFM32_PCNT2_BASE+EFM32_PCNT_AUXCNT_OFFSET) #define EFM32_PCNT2_INPUT (EFM32_PCNT2_BASE+EFM32_PCNT_INPUT_OFFSET) -/* PCNT Register Bit Field Definitions *****************************************************************************************/ +/* PCNT Register Bit Field Definitions **************************************/ /* Bit fields for PCNT CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_prs.h b/arch/arm/src/efm32/hardware/efm32_prs.h index 6076cf7d298..531ef0a37e4 100644 --- a/arch/arm/src/efm32/hardware/efm32_prs.h +++ b/arch/arm/src/efm32/hardware/efm32_prs.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_prs.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_PRS_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_PRS_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,14 +72,15 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ -/* PRS Register Offsets ********************************************************************************************************/ + ****************************************************************************/ + +/* PRS Register Offsets *****************************************************/ #define EFM32_PRS_SWPULSE_OFFSET 0x0000 /* Software Pulse Register */ #define EFM32_PRS_SWLEVEL_OFFSET 0x0004 /* Software Level Register */ -#define EFM32_PRS_ROUTE_OFFSET 0x0008 /* I/O Routing Register +#define EFM32_PRS_ROUTE_OFFSET 0x0008 /* I/O Routing Register */ #define EFM32_PRS_CH_CTRL_OFFSET(n) (0x0010 + ((n) << 2)) #define EFM32_PRS_CH0_CTRL_OFFSET 0x0010 /* Channel 0 Control Register */ @@ -95,7 +96,7 @@ #define EFM32_PRS_CH10_CTRL_OFFSET 0x0018 /* Channel 10 Control Register */ #define EFM32_PRS_CH11_CTRL_OFFSET 0x003c /* Channel 11 Control Register */ -/* PRS Register Addresses ******************************************************************************************************/ +/* PRS Register Addresses ***************************************************/ #define EFM32_PRS_SWPULSE (EFM32_PRS_BASE+EFM32_PRS_SWPULSE_OFFSET) #define EFM32_PRS_SWLEVEL (EFM32_PRS_BASE+EFM32_PRS_SWLEVEL_OFFSET) @@ -115,7 +116,7 @@ #define EFM32_PRS_CH10_CTRL (EFM32_PRS_BASE+EFM32_PRS_CH10_CTRL_OFFSET) #define EFM32_PRS_CH11_CTRL (EFM32_PRS_BASE+EFM32_PRS_CH11_CTRL_OFFSET) -/* PRS Register Bit Field Definitions ******************************************************************************************/ +/* PRS Register Bit Field Definitions ***************************************/ /* Bit fields for PRS SWPULSE */ @@ -522,7 +523,7 @@ #define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_CH_CTRL */ #define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /* Shifted mode DEFAULT for PRS_CH_CTRL */ -/* PRS Signals *****************************************************************************************************************/ +/* PRS Signals **************************************************************/ #define PRS_VCMP_OUT ((1 << 16) + 0) /* PRS Voltage comparator output */ #define PRS_ACMP0_OUT ((2 << 16) + 0) /* PRS Analog comparator output */ diff --git a/arch/arm/src/efm32/hardware/efm32_rmu.h b/arch/arm/src/efm32/hardware/efm32_rmu.h index 0ceb7b5973e..190f111b312 100644 --- a/arch/arm/src/efm32/hardware/efm32_rmu.h +++ b/arch/arm/src/efm32/hardware/efm32_rmu.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_rmu.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RMU_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RMU_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,22 +72,23 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ -/* RMU Register Offsets ********************************************************************************************************/ + ****************************************************************************/ + +/* RMU Register Offsets *****************************************************/ #define EFM32_RMU_CTRL_OFFSET 0x0000 /* Control Register */ #define EFM32_RMU_RSTCAUSE_OFFSET 0x0004 /* Reset Cause Register */ #define EFM32_RMU_CMD_OFFSET 0x0008 /* Command Register */ -/* RMU Register Addresses ******************************************************************************************************/ +/* RMU Register Addresses ***************************************************/ #define EFM32_RMU_CTRL (EFM32_RMU_BASE+EFM32_RMU_CTRL_OFFSET) #define EFM32_RMU_RSTCAUSE (EFM32_RMU_BASE+EFM32_RMU_RSTCAUSE_OFFSET) #define EFM32_RMU_CMD (EFM32_RMU_BASE+EFM32_RMU_CMD_OFFSET) -/* RMU Register Bit Field Definitions ******************************************************************************************/ +/* RMU Register Bit Field Definitions ***************************************/ /* Bit fields for RMU CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_romtable.h b/arch/arm/src/efm32/hardware/efm32_romtable.h index 6687eef52f5..ed223f478a3 100644 --- a/arch/arm/src/efm32/hardware/efm32_romtable.h +++ b/arch/arm/src/efm32/hardware/efm32_romtable.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_romtable.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ROMTABLE_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ROMTABLE_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,9 +72,9 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ + ****************************************************************************/ #define ROMTABLE ((const struct efm32_romtable_s *)EFM32_ROMTABLE_BASE) @@ -94,9 +94,9 @@ #define _ROMTABLE_PID3_REVMINORLSB_MASK 0x000000F0UL /* Least Significant Bits [3:0] of CHIP MINOR revision, mask */ #define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /* Least Significant Bits [3:0] of CHIP MINOR revision, shift */ -/******************************************************************************************************************************* +/**************************************************************************** * Public Type Definitions - *******************************************************************************************************************************/ + ****************************************************************************/ struct efm32_romtable_s { diff --git a/arch/arm/src/efm32/hardware/efm32_rtc.h b/arch/arm/src/efm32/hardware/efm32_rtc.h index 975e852bdc2..566b50b7264 100644 --- a/arch/arm/src/efm32/hardware/efm32_rtc.h +++ b/arch/arm/src/efm32/hardware/efm32_rtc.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_rtc.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RTC_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RTC_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,10 +72,11 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ -/* RTC Register Offsets ********************************************************************************************************/ + ****************************************************************************/ + +/* RTC Register Offsets *****************************************************/ #define EFM32_RTC_CTRL_OFFSET 0x0000 /* Control Register */ #define EFM32_RTC_CNT_OFFSET 0x0004 /* Counter Value Register */ @@ -88,7 +89,7 @@ #define EFM32_RTC_FREEZE_OFFSET 0x0020 /* Freeze Register */ #define EFM32_RTC_SYNCBUSY_OFFSET 0x0024 /* Synchronization Busy Register */ -/* RTC Register Addresses ******************************************************************************************************/ +/* RTC Register Addresses ***************************************************/ #define EFM32_RTC_CTRL (EFM32_RTC_BASE+EFM32_RTC_CTRL_OFFSET) #define EFM32_RTC_CNT (EFM32_RTC_BASE+EFM32_RTC_CNT_OFFSET) @@ -101,7 +102,7 @@ #define EFM32_RTC_FREEZE (EFM32_RTC_BASE+EFM32_RTC_FREEZE_OFFSET) #define EFM32_RTC_SYNCBUSY (EFM32_RTC_BASE+EFM32_RTC_SYNCBUSY_OFFSET) -/* RTC Register Bit Field Definitions ******************************************************************************************/ +/* RTC Register Bit Field Definitions ***************************************/ /* Bit fields for RTC CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_timer.h b/arch/arm/src/efm32/hardware/efm32_timer.h index 4d33d804897..aaf2d796fce 100644 --- a/arch/arm/src/efm32/hardware/efm32_timer.h +++ b/arch/arm/src/efm32/hardware/efm32_timer.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_timer.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_TIMER_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_TIMER_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,13 +72,13 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ + ****************************************************************************/ #define EFM32_TIMER_NCC 3 /* Three control channels */ -/* TIMER Register Offsets ******************************************************************************************************/ +/* TIMER Register Offsets ***************************************************/ #define EFM32_TIMER_CTRL_OFFSET 0x0000 /* Control Register */ #define EFM32_TIMER_CMD_OFFSET 0x0004 /* Command Register */ @@ -119,7 +119,7 @@ #define EFM32_TIMER_DTFAULTC_OFFSET 0x0084 /* DTI Fault Clear Register */ #define EFM32_TIMER_DTLOCK_OFFSET 0x0088 /* DTI Configuration Lock Register */ -/* TIMER Register Addresses ****************************************************************************************************/ +/* TIMER Register Addresses *************************************************/ #define EFM32_TIMER0_CTRL (EFM32_TIMER0_BASE+EFM32_TIMER_CTRL_OFFSET) #define EFM32_TIMER0_CMD_ (EFM32_TIMER0_BASE+EFM32_TIMER_CMD_OFFSET) @@ -277,7 +277,7 @@ #define EFM32_TIMER3_DTFAULTC (EFM32_TIMER3_BASE+EFM32_TIMER_DTFAULTC_OFFSET) #define EFM32_TIMER3_DTLOCK (EFM32_TIMER3_BASE+EFM32_TIMER_DTLOCK_OFFSET) -/* TIMER Register Bit Field Definitions ****************************************************************************************/ +/* TIMER Register Bit Field Definitions *************************************/ /* Bit fields for TIMER CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_usart.h b/arch/arm/src/efm32/hardware/efm32_usart.h index d5c9208aa01..53405eeb18b 100644 --- a/arch/arm/src/efm32/hardware/efm32_usart.h +++ b/arch/arm/src/efm32/hardware/efm32_usart.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************** +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_usart.h * * (C) Copyright 2014 Silicon Labs, http://www.silabs.com @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_USART_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_USART_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,22 +72,30 @@ # warning This is the EFM32GG/G header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ -/* The UART is functionally equivalent to the USART with the following exceptions. The register map and register descriptions - * are equal to those of the USART. + ****************************************************************************/ + +/* The UART is functionally equivalent to the USART with the following + * exceptions. The register map and register descriptions are equal to + * those of the USART. * - * - Synchronous operation Not available. SYNC, CSMA, CSINV, CPOL and CPHA in USARTn_CTRL, and MASTEREN in USARTn_STATUS - * are always 0. - * - Transmission direction Always LSB first. MSBF in USARTn_CTRL is always 0. - * - Chip-select Not available. AUTOCS in USARTn_CTRL is always 0. - * - SmartCard mode Not available. SCMODE in USARTn_CTRL is always 0. - * - Frame size Limited to 8-9 databits. Other configurations of DATABITS in USARTn_FRAME are not possible. + * - Synchronous operation Not available. SYNC, CSMA, CSINV, CPOL and + * CPHA in USARTn_CTRL, and MASTEREN in + * USARTn_STATUS are always 0. + * - Transmission direction Always LSB first. + * MSBF in USARTn_CTRL is always 0. + * - Chip-select Not available. + * AUTOCS in USARTn_CTRL is always 0. + * - SmartCard mode Not available. + * SCMODE in USARTn_CTRL is always 0. + * - Frame size Limited to 8-9 databits. + * Other configurations of DATABITS in + * USARTn_FRAME are not possible. * - IrDA Not available. IREN in USARTn_IRCTRL is always 0. */ -/* USART Register Offsets ******************************************************************************************************/ +/* USART Register Offsets ***************************************************/ #define EFM32_USART_CTRL_OFFSET 0x0000 /* Control Register */ #define EFM32_USART_FRAME_OFFSET 0x0004 /* USART Frame Format Register */ @@ -116,7 +124,7 @@ # define EFM32_USART_I2SCTRL_OFFSET 0x005c /* I2S Control Register */ #endif -/* USART Register Addresses ****************************************************************************************************/ +/* USART Register Addresses *************************************************/ #define EFM32_USART0_CTRL (EFM32_USART0_BASE+EFM32_USART_CTRL_OFFSET) #define EFM32_USART0_FRAME (EFM32_USART0_BASE+EFM32_USART_FRAME_OFFSET) @@ -253,7 +261,7 @@ # define EFM32_UART1_I2SCTRL (EFM32_UART1_BASE+EFM32_USART_I2SCTRL_OFFSET) #endif -/* USART Register Register Bit Definitions *************************************************************************************/ +/* USART Register Register Bit Definitions **********************************/ /* Bit fields for USART CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_usb.h b/arch/arm/src/efm32/hardware/efm32_usb.h index 4fcc35c4577..b12195daafb 100644 --- a/arch/arm/src/efm32/hardware/efm32_usb.h +++ b/arch/arm/src/efm32/hardware/efm32_usb.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_usb.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_USB_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_USB_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,9 +72,9 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ + ****************************************************************************/ /* General definitions */ @@ -89,7 +89,7 @@ #define EFM32_USB_PID_MDATA (3) /* Non-control */ #define EFM32_USB_PID_SETUP (3) /* Control */ -/* USB Register Offsets ********************************************************************************************************/ +/* USB Register Offsets *****************************************************/ #define EFM32_USB_CTRL_OFFSET 0x00000 /* System Control Register */ #define EFM32_USB_STATUS_OFFSET 0x00004 /* System Status Register */ @@ -293,7 +293,7 @@ #define EFM32_USB_FIFOD_OFFSET(n,d) (EFM32_USB_FIFO_OFFSET(n) + ((d) << 2)) #define EFM32_FIFORAM_OFFSET(d) (0x5c000 + ((d) << 2)) -/* USB Register Addresses ******************************************************************************************************/ +/* USB Register Addresses ***************************************************/ #define EFM32_USB_CTRL (EFM32_USB_BASE+EFM32_USB_CTRL_OFFSET) #define EFM32_USB_STATUS (EFM32_USB_BASE+EFM32_USB_STATUS_OFFSET) @@ -497,7 +497,7 @@ #define EFM32_USB_FIFOD(n,d) (EFM32_USB_BASE+EFM32_USB_FIFOD_OFFSET(n,d)) #define EFM32_FIFORAM(d) (EFM32_USB_BASE+EFM32_FIFORAM_OFFSET(d)) -/* USB Register Bit Field Definitions ******************************************************************************************/ +/* USB Register Bit Field Definitions ***************************************/ /* Bit fields for USB CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_vcmp.h b/arch/arm/src/efm32/hardware/efm32_vcmp.h index 996202aede6..268ba267db8 100644 --- a/arch/arm/src/efm32/hardware/efm32_vcmp.h +++ b/arch/arm/src/efm32/hardware/efm32_vcmp.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_vcmp.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_VCMP_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_VCMP_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,10 +72,11 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ -/* VCMP Register Offsets *******************************************************************************************************/ + ****************************************************************************/ + +/* VCMP Register Offsets ****************************************************/ #define EFM32_VCMP_CTRL_OFFSET 0x0000 /* Control Register */ #define EFM32_VCMP_INPUTSEL_OFFSET 0x0004 /* Input Selection Register */ @@ -85,7 +86,7 @@ #define EFM32_VCMP_IFS_OFFSET 0x0014 /* Interrupt Flag Set Register */ #define EFM32_VCMP_IFC_OFFSET 0x0018 /* Interrupt Flag Clear Register */ -/* VCMP Register Addresses *****************************************************************************************************/ +/* VCMP Register Addresses **************************************************/ #define EFM32_VCMP_CTRL (EFM32_VCMP_BASE+EFM32_VCMP_CTRL_OFFSET) #define EFM32_VCMP_INPUTSEL (EFM32_VCMP_BASE+EFM32_VCMP_INPUTSEL_OFFSET) @@ -95,7 +96,7 @@ #define EFM32_VCMP_IFS (EFM32_VCMP_BASE+EFM32_VCMP_IFS_OFFSET) #define EFM32_VCMP_IFC (EFM32_VCMP_BASE+EFM32_VCMP_IFC_OFFSET) -/* VCMP Register Bit Field Definitions *****************************************************************************************/ +/* VCMP Register Bit Field Definitions **************************************/ /* Bit fields for VCMP CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32_wdog.h b/arch/arm/src/efm32/hardware/efm32_wdog.h index 559dbef5fa0..b446d999d9d 100644 --- a/arch/arm/src/efm32/hardware/efm32_wdog.h +++ b/arch/arm/src/efm32/hardware/efm32_wdog.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************************* +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32_wdog.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -56,14 +56,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_WDOG_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_WDOG_H -/******************************************************************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/efm32_memorymap.h" @@ -72,22 +72,23 @@ # warning This is the EFM32GG header file; Review/modification needed for this architecture #endif -/******************************************************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************************************************************/ -/* WDOG Register Offsets *******************************************************************************************************/ + ****************************************************************************/ + +/* WDOG Register Offsets ****************************************************/ #define EFM32_WDOG_CTRL_OFFSET 0x0000 /* Control Register */ #define EFM32_WDOG_CMD_OFFSET 0x0004 /* Command Register */ #define EFM32_WDOG_SYNCBUSY_OFFSET 0x0008 /* Synchronization Busy Register */ -/* WDOG Register Addresses *****************************************************************************************************/ +/* WDOG Register Addresses **************************************************/ #define EFM32_WDOG_CTRL (EFM32_WDOG_BASE+EFM32_WDOG_CTRL_OFFSET) #define EFM32_WDOG_CMD (EFM32_WDOG_BASE+EFM32_WDOG_CMD_OFFSET) #define EFM32_WDOG_SYNCBUSY (EFM32_WDOG_BASE+EFM32_WDOG_SYNCBUSY_OFFSET) -/* WDOG Register Bit Field Definitions *****************************************************************************************/ +/* WDOG Register Bit Field Definitions **************************************/ /* Bit fields for WDOG CTRL */ diff --git a/arch/arm/src/efm32/hardware/efm32g_memorymap.h b/arch/arm/src/efm32/hardware/efm32g_memorymap.h index df35da9e073..699cdec6ac2 100644 --- a/arch/arm/src/efm32/hardware/efm32g_memorymap.h +++ b/arch/arm/src/efm32/hardware/efm32g_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32g_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,16 +16,16 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ /* Reference: "EFM32G Reference Manual, Gecko Series", Energy Micro */ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32G_MEMORYMAP_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32G_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Memory Base Addresses */ diff --git a/arch/arm/src/efm32/hardware/efm32gg_memorymap.h b/arch/arm/src/efm32/hardware/efm32gg_memorymap.h index f7362e19a1d..5b52a1ceace 100644 --- a/arch/arm/src/efm32/hardware/efm32gg_memorymap.h +++ b/arch/arm/src/efm32/hardware/efm32gg_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32gg_memorymap.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -54,14 +54,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32GG_MEMORYMAP_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM32GG_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Memory Base Addresses */ diff --git a/arch/arm/src/efm32/hardware/efm32tg_memorymap.h b/arch/arm/src/efm32/hardware/efm32tg_memorymap.h index 26474a53538..62d305f96f0 100644 --- a/arch/arm/src/efm32/hardware/efm32tg_memorymap.h +++ b/arch/arm/src/efm32/hardware/efm32tg_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/efm32/hardware/efm32tg_memorymap.h * * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by @@ -54,14 +54,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM3TG_MEMORYMAP_H #define __ARCH_ARM_SRC_EFM32_CHIP_EFM3TG_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Memory Base addresses */