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https://github.com/apache/nuttx.git
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Evaluate n in preprocessor before masking
This commit is contained in:
Peter van der Perk
committed by
Xiang Xiao
Xiang Xiao
parent
ec118743ea
commit
9e7e45df76
@@ -171,11 +171,11 @@
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#define QSPICR_IDATSZ_SHIFT (0) /* Bits 0-15: IP data transfer size (IDATSZ) */
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#define QSPICR_IDATSZ_MASK (0xffff << QSPICR_IDATSZ_SHIFT)
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#define QSPICR_IDATSZ(n) ((n << QSPICR_IDATSZ_SHIFT) & QSPICR_IDATSZ_MASK)
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#define QSPICR_IDATSZ(n) (((n) << QSPICR_IDATSZ_SHIFT) & QSPICR_IDATSZ_MASK)
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/* Bits 16-23: Reserved */
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#define QSPICR_SEQID_SHIFT (24) /* Bits 24-27: Points to a sequence in the LUT (SEQID) */
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#define QSPICR_SEQID_MASK (0x0f << QSPICR_SEQID_SHIFT)
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#define QSPICR_SEQID(n) ((n << QSPICR_SEQID_SHIFT) & QSPICR_SEQID_MASK)
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#define QSPICR_SEQID(n) (((n) << QSPICR_SEQID_SHIFT) & QSPICR_SEQID_MASK)
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/* Bits 28-31: Reserved */
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/* Flash Memory Configuration Register (FLSHCR) */
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@@ -185,18 +185,18 @@
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#define QSPI_FLSHCR_TCSS(n) (n & QSPI_FLSHCR_TCSS_MASK)
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#define QSPI_FLSHCR_TCSH_SHIFT (8) /* Bits 8-11: Serial flash memory CS hold time (TCSH) */
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#define QSPI_FLSHCR_TCSH_MASK (0x0f << QSPI_FLSHCR_TCSH_SHIFT)
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#define QSPI_FLSHCR_TCSH(n) ((n << QSPI_FLSHCR_TCSH_SHIFT) & QSPI_FLSHCR_TCSH_MASK)
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#define QSPI_FLSHCR_TCSH(n) (((n) << QSPI_FLSHCR_TCSH_SHIFT) & QSPI_FLSHCR_TCSH_MASK)
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/* Bits 12-31: Reserved */
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/* Buffer n Configuration Register (BUFnCR) */
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#define QSPI_BUFCR_MSTRID_SHIFT (0) /* Bits 0-3: Master ID (MSTRID) */
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#define QSPI_BUFCR_MSTRID_MASK (0x0f << QSPI_BUFCR_MSTRID_SHIFT)
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#define QSPI_BUFCR_MSTRID(n) ((n << QSPI_BUFCR_MSTRID_SHIFT) & QSPI_BUFCR_MSTRID_MASK)
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#define QSPI_BUFCR_MSTRID(n) (((n) << QSPI_BUFCR_MSTRID_SHIFT) & QSPI_BUFCR_MSTRID_MASK)
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/* Bits 4-7: Reserved */
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#define QSPI_BUFCR_ADATSZ_SHIFT (8) /* Bits 8-13: AHB data transfer size (ADATSZ) */
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#define QSPI_BUFCR_ADATSZ_MASK (0x3f << QSPI_BUFCR_ADATSZ_SHIFT)
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#define QSPI_BUFCR_ADATSZ(n) ((n << QSPI_BUFCR_ADATSZ_SHIFT) & QSPI_BUFCR_ADATSZ_MASK)
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#define QSPI_BUFCR_ADATSZ(n) (((n) << QSPI_BUFCR_ADATSZ_SHIFT) & QSPI_BUFCR_ADATSZ_MASK)
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/* Bits 14-31: Reserved */
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#define QSPI_BUF3CR_ALLMST (1 << 31) /* Bit 31: All master enable (ALLMST) */
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@@ -235,10 +235,10 @@
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#define QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT (8) /* Bits 8-11: Delay elements in each delay tap (SLV_DLY_COARSE) */
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#define QSPI_DLLCRA_SLV_DLY_COARSE_MASK (0x0f << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT)
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#define QSPI_DLLCRA_SLV_DLY_COARSE(n) ((n << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT) & QSPI_DLLCRA_SLV_DLY_COARSE_MASK)
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#define QSPI_DLLCRA_SLV_DLY_COARSE(n) (((n) << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT) & QSPI_DLLCRA_SLV_DLY_COARSE_MASK)
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#define QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT (12) /* Bits 12-14: T/16 offset delay elements in incoming DQS (SLV_DLY_OFFSET) */
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#define QSPI_DLLCRA_SLV_DLY_OFFSET_MASK (0x07 << QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT)
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#define QSPI_DLLCRA_SLV_DLY(n) ((n << QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT) & QSPI_DLLCRA_SLV_DLY_OFFSET_MASK)
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#define QSPI_DLLCRA_SLV_DLY(n) (((n) << QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT) & QSPI_DLLCRA_SLV_DLY_OFFSET_MASK)
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/* Bit 15: Reserved */
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#define QSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT (16) /* Bits 16-19: Fine offset delay elements in incoming DQS (SLV_FINE_OFFSET) */
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#define QSPI_DLLCRA_SLV_FINE_OFFSET_MASK (0x0f << QSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT)
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@@ -259,7 +259,7 @@
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/* Bits 7-23: Reserved */
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#define QSPI_SMPR_DLLFSMPFA_SHIFT (24) /* Bits 24-26: Selects the nth tap provided by slave delay chain for flash memory A (DLLFSMPFA) */
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#define QSPI_SMPR_DLLFSMPFA_MASK (0x07 << QSPI_SMPR_DLLFSMPFA_SHIFT)
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#define QSPI_SMPR_DLLFSMPFA(n) ((n << QSPI_SMPR_DLLFSMPFA_SHIFT) & QSPI_SMPR_DLLFSMPFA_MASK)
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#define QSPI_SMPR_DLLFSMPFA(n) (((n) << QSPI_SMPR_DLLFSMPFA_SHIFT) & QSPI_SMPR_DLLFSMPFA_MASK)
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/* Bits 27-31: Reserved */
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/* RX Buffer Status Register (RBSR) */
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@@ -274,7 +274,7 @@
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#define QSPI_RBCT_WMRK_SHIFT (0) /* Bits 0-6: RX buffer watermark (WMRK) */
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#define QSPI_RBCT_WMRK_MASK (0x7f << QSPI_RBCT_WMRK_SHIFT)
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#define QSPI_RBCT_WMRK(n) ((n << QSPI_RBCT_WMRK_SHIFT) & QSPI_RBCT_WMRK_MASK)
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#define QSPI_RBCT_WMRK(n) (((n) << QSPI_RBCT_WMRK_SHIFT) & QSPI_RBCT_WMRK_MASK)
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/* Bit 7: Reserved */
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#define QSPI_RBCT_RXBRD (1 << 8) /* Bit 8: RX buffer readout (RXBRD) */
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# define QSPI_RBCT_RXBRD_AHB (0 << 8) /* RX buffer content is read using the AHB bus registers */
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@@ -307,7 +307,7 @@
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#define QSPI_TBCT_WMRK_SHIFT (0) /* Bits 0-4: Watermark for TX buffer (WMRK) */
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#define QSPI_TBCT_WMRK_MASK (0x1f << QSPI_TBCT_WMRK_SHIFT)
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#define QSPI_TBCT_WMRK(n) ((n << QSPI_TBCT_WMRK_SHIFT) & QSPI_TBCT_WMRK_MASK)
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#define QSPI_TBCT_WMRK(n) (((n) << QSPI_TBCT_WMRK_SHIFT) & QSPI_TBCT_WMRK_MASK)
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/* Bits 5-31: Reserved */
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/* Status Register (SR) */
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@@ -392,7 +392,7 @@
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/* Bits 0-9: Reserved */
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#define QSPI_SFAD_TPAD_SHIFT (10) /* Bits 10-31: Top address for serial flash memory An/Bn (TPADAn/TPADBn) */
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#define QSPI_SFAD_TPAD_MASK (0x3fffff << QSPI_SFAD_TPAD_SHIFT)
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#define QSPI_SFAD_TPAD(n) ((n << QSPI_SFAD_TPAD_SHIFT) & QSPI_SFAD_TPAD_MASK)
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#define QSPI_SFAD_TPAD(n) (((n) << QSPI_SFAD_TPAD_SHIFT) & QSPI_SFAD_TPAD_MASK)
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/* RX Buffer Data Register (RBDRn, n=0,...,63) */
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@@ -415,7 +415,7 @@
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#define QSPI_LUT_OPRND0_SHIFT (0) /* Bits 0-7: Operand for INSTR0 (OPRND0) */
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#define QSPI_LUT_OPRND0_MASK (0xff << QSPI_LUT_OPRND0_SHIFT)
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#define QSPI_LUT_OPRND0(n) ((n << QSPI_LUT_OPRND0_SHIFT) & QSPI_LUT_OPRND0_MASK)
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#define QSPI_LUT_OPRND0(n) (((n) << QSPI_LUT_OPRND0_SHIFT) & QSPI_LUT_OPRND0_MASK)
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#define QSPI_LUT_PAD0_SHIFT (8) /* Bits 8-9: Pad information for INSTR0 (PAD0) */
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#define QSPI_LUT_PAD0_MASK (0x03 << QSPI_LUT_PAD0_SHIFT)
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# define QSPI_LUT_PAD0_1 (0x00 << QSPI_LUT_PAD0_SHIFT) /* 1 Pad */
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@@ -424,11 +424,11 @@
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#define QSPI_LUT_INSTR0_SHIFT (10) /* Bits 10-15: Instruction 0 (INSTR0) */
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#define QSPI_LUT_INSTR0_MASK (0x3f << QSPI_LUT_INSTR0_SHIFT)
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#define QSPI_LUT_INSTR0(n) ((n << QSPI_LUT_INSTR0_SHIFT) & QSPI_LUT_INSTR0_MASK)
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#define QSPI_LUT_INSTR0(n) (((n) << QSPI_LUT_INSTR0_SHIFT) & QSPI_LUT_INSTR0_MASK)
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#define QSPI_LUT_OPRND1_SHIFT (16) /* Bits 16-23: Operand for INSTR1 (OPRND1) */
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#define QSPI_LUT_OPRND1_MASK (0xff << QSPI_LUT_OPRND1_SHIFT)
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#define QSPI_LUT_OPRND1(n) ((n << QSPI_LUT_OPRND1_SHIFT) & QSPI_LUT_OPRND1_MASK)
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#define QSPI_LUT_OPRND1(n) (((n) << QSPI_LUT_OPRND1_SHIFT) & QSPI_LUT_OPRND1_MASK)
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#define QSPI_LUT_PAD1_SHIFT (24) /* Bits 24-25: Pad information for INSTR1 (PAD1) */
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#define QSPI_LUT_PAD1_MASK (0x03 << QSPI_LUT_PAD1_SHIFT)
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# define QSPI_LUT_PAD1_1 (0x00 << QSPI_LUT_PAD1_SHIFT) /* 1 Pad */
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@@ -437,7 +437,7 @@
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#define QSPI_LUT_INSTR1_SHIFT (26) /* Bits 26-31: Instruction 1 (INSTR1) */
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#define QSPI_LUT_INSTR1_MASK (0x3f << QSPI_LUT_INSTR1_SHIFT)
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#define QSPI_LUT_INSTR1(n) ((n << QSPI_LUT_INSTR1_SHIFT) & QSPI_LUT_INSTR1_MASK)
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#define QSPI_LUT_INSTR1(n) (((n) << QSPI_LUT_INSTR1_SHIFT) & QSPI_LUT_INSTR1_MASK)
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/* External Memory Base Address */
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@@ -91,7 +91,7 @@
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/* Bits 2-7: Reserved */
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#define STM_CR_CPS_SHIFT (8) /* Bits 8-15: Counter Prescaler (CPS) */
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#define STM_CR_CPS_MASK (0xff << STM_CR_CPS_SHIFT)
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#define STM_CR_CPS(n) ((n << STM_CR_CPS_SHIFT) & STM_CR_CPS_MASK)
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#define STM_CR_CPS(n) (((n) << STM_CR_CPS_SHIFT) & STM_CR_CPS_MASK)
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/* Bits 16-31: Reserved */
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/* Count Register (CNT) */
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