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arch/stm32h7: Extend support to all STM32H7x3xx
All parts in the STM32H7x3xx family have the same pinmap, etc.,
so extending support to all members of the family required only
minimal changes: Adding them to Kconfig, extending some
preprocessor logic, and minor code changes.
arch/arm/src/stm32h7/Kconfig:
* Add explicit support for all microcontrollers in the
STM32H7x3xx family by adding support for:
- STM32H743AG
- STM32H743AI
- STM32H743BG
- STM32H743BI
- STM32H743IG
- STM32H743II
- STM32H743VG
- STM32H743VI
- STM32H743XG
- STM32H743XI
- STM32H743ZG
- STM32H753AI
- STM32H753BI
- STM32H753VI
- STM32H753XI
- STM32H753ZI
* Fix TODO items for IO_CONFIG (all STM32H7X3XX).
* Because 100-pin parts lack GPIO ports F and G, but have
port H, create the new hidden configs STM32H7_HAVE_GPIOF
and STM32H7_HAVE_GPIOG.
* STM32H7_STM32H7X3XX:
- Select STM32H7_HAVE_GPIOF and STM32H7_HAVE_GPIOG only
when not STM32H7_IO_CONFIG_V (100-pin part).
- STM32H7_STM32H7X3XX: select STM32H7_HAVE_SPI5 for all
IO configs except V (100-pin part), which doesn't expose
SPI5 due to pin count.
* STM32H7_STM32H7X7XX: Always select STM32H7_HAVE_GPIOF and
STM32H7_HAVE_GPIOG because we aren't adding more part
numbers in this family.
* Remove extraneous (duplicate) "bool" and "default n"
lines.
* config STM32H7_FMC: Fix indent (contents were indented
with spaces while rest of file uses tabs).
arch/arm/include/stm32h7/chip.h:
* Extend preprocessor logic to add support for the new
MCU part numbers.
* Expand table of differences between family members.
* Define STM32H7_NGPIO based on IO_CONFIGs decided in Kconfig.
* If IO config is not known, issue compile-time #error
with grep-friendly "CONFIG_STM32H7_IO_CONFIG_x Not Set."
Suggested by davids5.
arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h:
arch/arm/src/stm32h7/stm32h7x3xx_rcc.c:
arch/arm/src/stm32h7/stm32h7x7xx_rcc.c:
* When checking STM32H7_NGPIO > 5 or 6, check also
CONFIG_STM32H7_HAVE_GPIOF or CONFIG_STM32H7_HAVE_GPIOG.
arch/arm/src/stm32h7/stm32_gpio.c:
* stm32_configgpio(): When applicable, make sure we're not
trying to configure one of the missing ports.
* Fix nxstyle complains (wrong end of line comment position
and several long lines). No functional changes.
* g_gpiobase[]: Init base address for ports F and G according to
CONFIG_STM32H7_HAVE_GPIOF and CONFIG_STM32H7_HAVE_GPIOG.
* stm32_configgpio(): Replace complicated check with g_gpiobase[]
null check. Suggested by davids5.
* stm32_gpiowrite() and stm32_gpioread(): Add previously missing
null check of g_gpiobase[].
arch/arm/src/stm32h7/stm32_gpio.h:
* Wrap the defines GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD,
GPIO_PORTE, GPIO_PORTF, GPIO_PORTG, GPIO_PORTH, GPIO_PORTI,
GPIO_PORTJ, and GPIO_PORTK in conditional logic so that the
compiler will prevent use of ports that do not exist on the
target MCU.
* Fix nxstyle complaints.
Documentation/NuttX.html:
* Remove copy-and-pasted anchor for stm32f76xx77xx.
* Correct link to README.txt for Nucleo-H743ZI board,
formerly on BitBucket, now on GitHub.
* Add list item for STMicro STM32H747I-DISCO board.
Co-Authored-By: David Sidrane <David.Sidrane@Nscdg.com>
This commit is contained in:
Nathan Hartman
committed by
patacongo
patacongo
parent
0668a1552d
commit
9b9d1fc7ca
@@ -5991,7 +5991,6 @@ Mem: 29232 5920 23312 23312
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<td>
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<p>
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<a name="stm32h7x3">STMicro STM32 H7x3</a>
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<a name="stm32f76xx77xx"><b>STMicro STM32 F76xx/F77xx</b>.</a>
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Architecture support for the STM32 H7x3 was added through efforts of several people in NuttX-7.26. Support is available for one board from this family:
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</p>
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<ul>
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@@ -5999,12 +5998,22 @@ Mem: 29232 5920 23312 23312
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<p>
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<b>Nucleo-H743ZI</b>.
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This is a member of the Nucleo-144 board family.
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Support for this board was also added NuttX-7.26.
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See the board <a href="https://bitbucket.org/nuttx/nuttx/src/master/boards/arm/stm32f7/nucleo-h743zi/README.txt">README.txt</a> file for further information.
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Support for this board was added in NuttX-7.26.
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See the board <a href="https://github.com/apache/incubator-nuttx/blob/master/boards/arm/stm32h7/nucleo-h743zi/README.txt">README.txt</a> file for further information.
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</p>
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<p>
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The basic NSH configuration is fully, thanks to the bring-up efforts of Mateusz Szafoni.
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This port is port is still a work in progress and additional drivers are being ported from the F7 family.
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This port is still a work in progress and additional drivers are being ported from the F7 family.
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</p>
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</li>
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<li>
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<p>
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<b>STMicro STM32H747I-DISCO</b>.
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Support for this board was added in NuttX-9.0.
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See the board <a href="https://github.com/apache/incubator-nuttx/blob/master/boards/arm/stm32h7/stm32h747i-disco/README.txt">README.txt</a> file for further information.
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</p>
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<p>
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This port is still a work in progress.
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</p>
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</li>
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</ul>
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@@ -49,12 +49,19 @@
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/* STM32H7x3xx Differences between family members:
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*
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* ----------- ----------------
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* ----------- ---------------- ----- ----
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* SPI
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* PART PACKAGE GPIOs I2S
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* ----------- ---------------- ----- ----
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* STM32H7x3Ax UFBGA169 132 6/3
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* STM32H7x3Bx LQFP208 168 6/3
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* STM32H7x3Ix LQFP176/UFBGA176 140 6/3
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* STM32H7x3Vx LQFP100/TFBGA100 82 5/3
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* STM32H7x3Xx TFBGA240 168 6/3
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* STM32H7x3Zx LQFP144 114 6/3
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* ----------- ---------------- ----- ----
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*
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* PART PACKAGE
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* ----------- ----------------
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* STM32H7x3Zx LQFP144
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* ----------- ----------------
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* Parts STM32H7xxxG have 1024Kb of FLASH
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*
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* Parts STM32H7xxxI have 2048Kb of FLASH
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*
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@@ -62,7 +69,24 @@
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* with CONFIG_STM32H7_FLASH_OVERRIDE_x
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*/
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#if defined(CONFIG_ARCH_CHIP_STM32H743ZI) || defined(CONFIG_ARCH_CHIP_STM32H753II)
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#if defined (CONFIG_ARCH_CHIP_STM32H743AG) || \
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defined (CONFIG_ARCH_CHIP_STM32H743AI) || \
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defined (CONFIG_ARCH_CHIP_STM32H743BG) || \
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defined (CONFIG_ARCH_CHIP_STM32H743BI) || \
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defined (CONFIG_ARCH_CHIP_STM32H743IG) || \
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defined (CONFIG_ARCH_CHIP_STM32H743II) || \
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defined (CONFIG_ARCH_CHIP_STM32H743VG) || \
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defined (CONFIG_ARCH_CHIP_STM32H743VI) || \
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defined (CONFIG_ARCH_CHIP_STM32H743XG) || \
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defined (CONFIG_ARCH_CHIP_STM32H743XI) || \
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defined (CONFIG_ARCH_CHIP_STM32H743ZG) || \
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defined (CONFIG_ARCH_CHIP_STM32H743ZI) || \
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defined (CONFIG_ARCH_CHIP_STM32H753AI) || \
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defined (CONFIG_ARCH_CHIP_STM32H753BI) || \
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defined (CONFIG_ARCH_CHIP_STM32H753II) || \
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defined (CONFIG_ARCH_CHIP_STM32H753VI) || \
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defined (CONFIG_ARCH_CHIP_STM32H753XI) || \
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defined (CONFIG_ARCH_CHIP_STM32H753ZI)
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#elif defined(CONFIG_ARCH_CHIP_STM32H747XI)
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#else
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# error STM32 H7 chip not identified
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@@ -92,7 +116,22 @@
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/* Peripherals */
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# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */
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# if defined(CONFIG_STM32H7_IO_CONFIG_A)
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# define STM32H7_NGPIO (10) /* GPIOA-GPIOJ */
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# elif defined(CONFIG_STM32H7_IO_CONFIG_B)
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# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */
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# elif defined(CONFIG_STM32H7_IO_CONFIG_I)
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# define STM32H7_NGPIO (9) /* GPIOA-GPIOI */
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# elif defined(CONFIG_STM32H7_IO_CONFIG_V)
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# define STM32H7_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */
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# elif defined(CONFIG_STM32H7_IO_CONFIG_X)
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# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */
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# elif defined(CONFIG_STM32H7_IO_CONFIG_Z)
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# define STM32H7_NGPIO (8) /* GPIOA-GPIOH */
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# else
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# error CONFIG_STM32H7_IO_CONFIG_x Not Set
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# endif
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# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */
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# define STM32H7_NADC (3) /* (3) ADC1-3*/
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# define STM32H7_NDAC (2) /* (2) DAC1-2*/
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@@ -172,7 +211,7 @@
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# define STM32H7_NFMC 0 /* No FMC memory controller */
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#endif
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/* NVIC priority levels **************************************************************/
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/* NVIC priority levels *************************************************************/
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/* 16 Programmable interrupt levels */
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+198
-19
@@ -12,13 +12,113 @@ choice
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default ARCH_CHIP_STM32H743ZI
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depends on ARCH_CHIP_STM32H7
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config ARCH_CHIP_STM32H743AG
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bool "STM32H743AG"
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_G
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select STM32H7_IO_CONFIG_A
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---help---
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STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
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UFBGA169
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config ARCH_CHIP_STM32H743AI
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bool "STM32H743AI"
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_A
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---help---
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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UFBGA169
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config ARCH_CHIP_STM32H743BG
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bool "STM32H743BG"
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_G
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select STM32H7_IO_CONFIG_B
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---help---
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STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
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LQFP208
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config ARCH_CHIP_STM32H743BI
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bool "STM32H743BI"
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_B
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---help---
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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LQFP208
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config ARCH_CHIP_STM32H743IG
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bool "STM32H743IG"
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_G
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select STM32H7_IO_CONFIG_I
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---help---
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STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
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LQFP176 or UFBGA176
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config ARCH_CHIP_STM32H743II
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bool "STM32H743II"
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_I
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---help---
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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LQFP176 or UFBGA176
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config ARCH_CHIP_STM32H743VG
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bool "STM32H743VG"
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_G
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select STM32H7_IO_CONFIG_V
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---help---
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STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
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LQFP100 or TFBGA100
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config ARCH_CHIP_STM32H743VI
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bool "STM32H743VI"
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_V
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---help---
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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LQFP100 or TFBGA100
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config ARCH_CHIP_STM32H743XG
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bool "STM32H743XG"
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_G
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select STM32H7_IO_CONFIG_X
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---help---
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STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
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TFBGA240
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config ARCH_CHIP_STM32H743XI
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bool "STM32H743XI"
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_X
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---help---
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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TFBGA240
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config ARCH_CHIP_STM32H743ZG
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bool "STM32H743ZG"
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_G
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select STM32H7_IO_CONFIG_Z
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---help---
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STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
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LQFP144
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config ARCH_CHIP_STM32H743ZI
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bool "STM32H743ZI"
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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# TODO: IO_CONFIG
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select STM32H7_IO_CONFIG_Z
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---help---
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STM32 H7 Cortex M7, 2048 FLASH, 1024K Kb SRAM
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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LQFP144
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config ARCH_CHIP_STM32H747XI
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bool "STM32H747XI"
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@@ -26,18 +126,89 @@ config ARCH_CHIP_STM32H747XI
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select STM32H7_FLASH_CONFIG_I
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# TODO: IO_CONFIG
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---help---
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Dual core STM32 H7 Cortex M7+M4, 2048 FLASH, 1024K Kb SRAM
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Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM
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config ARCH_CHIP_STM32H753AI
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bool "STM32H753AI"
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_A
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---help---
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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with cryptographic accelerator, UFBGA169
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config ARCH_CHIP_STM32H753BI
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bool "STM32H753BI"
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_B
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---help---
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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with cryptographic accelerator, LQFP208
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config ARCH_CHIP_STM32H753II
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bool "STM32H753II"
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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# TODO: IO_CONFIG
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select STM32H7_IO_CONFIG_I
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---help---
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STM32 H7 Cortex M7, 2048 FLASH, 1024K Kb SRAM
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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with cryptographic accelerator, LQFP176/UFBGA176
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config ARCH_CHIP_STM32H753VI
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bool "STM32H753VI"
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_V
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---help---
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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with cryptographic accelerator, LQFP100/TFBGA100
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config ARCH_CHIP_STM32H753XI
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bool "STM32H753XI"
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_X
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---help---
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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with cryptographic accelerator, TFBGA240
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config ARCH_CHIP_STM32H753ZI
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bool "STM32H753ZI"
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_Z
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---help---
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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with cryptographic accelerator, LQFP144
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endchoice # STM32 H7 Chip Selection
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config STM32H7_IO_CONFIG_A
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bool
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default n
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config STM32H7_IO_CONFIG_B
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bool
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default n
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config STM32H7_IO_CONFIG_I
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bool
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default n
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config STM32H7_IO_CONFIG_V
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bool
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default n
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config STM32H7_IO_CONFIG_X
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bool
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default n
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config STM32H7_IO_CONFIG_Z
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bool
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default n
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config STM32H7_STM32H7X3XX
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bool
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default n
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@@ -50,11 +221,11 @@ config STM32H7_STM32H7X3XX
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select ARMV7M_HAVE_DTCM
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select STM32H7_HAVE_ETHERNET
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select STM32H7_HAVE_FMC
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select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V
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select STM32H7_HAVE_GPIOG if !STM32H7_IO_CONFIG_V
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select STM32H7_HAVE_SPI4
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select STM32H7_HAVE_SPI5
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select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V
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select STM32H7_HAVE_SPI6
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bool
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default n
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config STM32H7_STM32H7X7XX
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bool
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@@ -68,11 +239,11 @@ config STM32H7_STM32H7X7XX
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select ARMV7M_HAVE_DTCM
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select STM32H7_HAVE_ETHERNET
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select STM32H7_HAVE_FMC
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select STM32H7_HAVE_GPIOF
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select STM32H7_HAVE_GPIOG
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select STM32H7_HAVE_SPI4
|
||||
select STM32H7_HAVE_SPI5
|
||||
select STM32H7_HAVE_SPI6
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32H7_FLASH_CONFIG_B
|
||||
bool
|
||||
@@ -159,8 +330,16 @@ config STM32H7_HAVE_ETHERNET
|
||||
default n
|
||||
|
||||
config STM32H7_HAVE_FMC
|
||||
bool
|
||||
default n
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32H7_HAVE_GPIOF
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32H7_HAVE_GPIOG
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32H7_HAVE_SPI4
|
||||
bool
|
||||
@@ -289,13 +468,13 @@ config STM32H7_ETHMAC
|
||||
select ARCH_HAVE_PHY
|
||||
|
||||
config STM32H7_FMC
|
||||
bool "FMC"
|
||||
default n
|
||||
depends on STM32H7_HAVE_FMC
|
||||
---help---
|
||||
Enable Flexible Memory Controller.
|
||||
To correctly configure FMC for your hardware, you will have to define
|
||||
a number of macros in your board.h file. See stm32_fmc.c for directions.
|
||||
bool "FMC"
|
||||
default n
|
||||
depends on STM32H7_HAVE_FMC
|
||||
---help---
|
||||
Enable Flexible Memory Controller.
|
||||
To correctly configure FMC for your hardware, you will have to define
|
||||
a number of macros in your board.h file. See stm32_fmc.c for directions.
|
||||
|
||||
config STM32H7_OTGFS
|
||||
bool "OTG FS"
|
||||
|
||||
@@ -129,7 +129,7 @@
|
||||
# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32H7_NGPIO > 5
|
||||
#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF))
|
||||
# define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
@@ -142,7 +142,7 @@
|
||||
# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32H7_NGPIO > 6
|
||||
#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG))
|
||||
# define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
|
||||
@@ -83,10 +83,18 @@ const uint32_t g_gpiobase[STM32H7_NGPIO] =
|
||||
STM32_GPIOE_BASE,
|
||||
#endif
|
||||
#if STM32H7_NGPIO > 5
|
||||
# if defined(CONFIG_STM32H7_HAVE_GPIOF)
|
||||
STM32_GPIOF_BASE,
|
||||
# else
|
||||
0,
|
||||
# endif
|
||||
#endif
|
||||
#if STM32H7_NGPIO > 6
|
||||
# if defined(CONFIG_STM32H7_HAVE_GPIOG)
|
||||
STM32_GPIOG_BASE,
|
||||
# else
|
||||
0,
|
||||
# endif
|
||||
#endif
|
||||
#if STM32H7_NGPIO > 7
|
||||
STM32_GPIOH_BASE,
|
||||
@@ -165,6 +173,10 @@ int stm32_configgpio(uint32_t cfgset)
|
||||
/* Get the port base address */
|
||||
|
||||
base = g_gpiobase[port];
|
||||
if (base == 0)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Get the pin number and select the port configuration register for that
|
||||
* pin
|
||||
@@ -182,7 +194,10 @@ int stm32_configgpio(uint32_t cfgset)
|
||||
break;
|
||||
|
||||
case GPIO_OUTPUT: /* General purpose output mode */
|
||||
stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */
|
||||
|
||||
/* Set the initial output value */
|
||||
|
||||
stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0);
|
||||
pinmode = GPIO_MODER_OUTPUT;
|
||||
break;
|
||||
|
||||
@@ -312,7 +327,9 @@ int stm32_configgpio(uint32_t cfgset)
|
||||
|
||||
putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET);
|
||||
|
||||
/* Otherwise, it is an input pin. Should it configured as an EXTI interrupt? */
|
||||
/* Otherwise, it is an input pin. Should it configured as an EXTI
|
||||
* interrupt?
|
||||
*/
|
||||
|
||||
if (pinmode != GPIO_MODER_OUTPUT && (cfgset & GPIO_EXTI) != 0)
|
||||
{
|
||||
@@ -342,14 +359,15 @@ int stm32_configgpio(uint32_t cfgset)
|
||||
* Name: stm32_unconfiggpio
|
||||
*
|
||||
* Description:
|
||||
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set it
|
||||
* into default HiZ state (and possibly mark it's unused) and unlock it whether
|
||||
* it was previously selected as alternative function (GPIO_ALT|GPIO_CNF_AFPP|...).
|
||||
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set
|
||||
* it into default HiZ state (and possibly mark it's unused) and unlock it
|
||||
* whether it was previously selected as alternative function
|
||||
* (GPIO_ALT|GPIO_CNF_AFPP|...).
|
||||
*
|
||||
* This is a safety function and prevents hardware from schocks, as unexpected
|
||||
* write to the Timer Channel Output GPIO to fixed '1' or '0' while it should
|
||||
* operate in PWM mode could produce excessive on-board currents and trigger
|
||||
* over-current/alarm function.
|
||||
* This is a safety function and prevents hardware from shocks, as
|
||||
* unexpected write to the Timer Channel Output GPIO to fixed '1' or '0'
|
||||
* while it should operate in PWM mode could produce excessive on-board
|
||||
* currents and trigger over-current/alarm function.
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success
|
||||
@@ -391,23 +409,25 @@ void stm32_gpiowrite(uint32_t pinset, bool value)
|
||||
/* Get the port base address */
|
||||
|
||||
base = g_gpiobase[port];
|
||||
|
||||
/* Get the pin number */
|
||||
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
|
||||
/* Set or clear the output on the pin */
|
||||
|
||||
if (value)
|
||||
if (base != 0)
|
||||
{
|
||||
bit = GPIO_BSRR_SET(pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
bit = GPIO_BSRR_RESET(pin);
|
||||
}
|
||||
/* Get the pin number */
|
||||
|
||||
putreg32(bit, base + STM32_GPIO_BSRR_OFFSET);
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
|
||||
/* Set or clear the output on the pin */
|
||||
|
||||
if (value)
|
||||
{
|
||||
bit = GPIO_BSRR_SET(pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
bit = GPIO_BSRR_RESET(pin);
|
||||
}
|
||||
|
||||
putreg32(bit, base + STM32_GPIO_BSRR_OFFSET);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -431,11 +451,14 @@ bool stm32_gpioread(uint32_t pinset)
|
||||
/* Get the port base address */
|
||||
|
||||
base = g_gpiobase[port];
|
||||
if (base != 0)
|
||||
{
|
||||
/* Get the pin number and return the input state of that pin */
|
||||
|
||||
/* Get the pin number and return the input state of that pin */
|
||||
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0);
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
return ((getreg32(base + STM32_GPIO_IDR_OFFSET) &
|
||||
(1 << pin)) != 0);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
@@ -58,8 +58,8 @@
|
||||
|
||||
/* Bit-encoded input to stm32_configgpio() */
|
||||
|
||||
/* Each port bit of the general-purpose I/O (GPIO) ports can be individually configured
|
||||
* by software in several modes:
|
||||
/* Each port bit of the general-purpose I/O (GPIO) ports can be individually
|
||||
* configured by software in several modes:
|
||||
*
|
||||
* - Input floating
|
||||
* - Input pull-up
|
||||
@@ -162,7 +162,9 @@
|
||||
#define GPIO_OPENDRAIN (1 << 9) /* Bit9: 1=Open-drain output */
|
||||
#define GPIO_PUSHPULL (0) /* Bit9: 0=Push-pull output */
|
||||
|
||||
/* If the pin is a GPIO digital output, then this identifies the initial output value.
|
||||
/* If the pin is a GPIO digital output, then this identifies the initial output
|
||||
* value.
|
||||
*
|
||||
* If the pin is an input, this bit is overloaded to provide the qualifier to
|
||||
* distinguish input pull-up and -down:
|
||||
*
|
||||
@@ -195,17 +197,39 @@
|
||||
|
||||
#define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */
|
||||
#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT)
|
||||
#if STM32H7_NGPIO > 0
|
||||
# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */
|
||||
#endif
|
||||
#if STM32H7_NGPIO > 1
|
||||
# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */
|
||||
#endif
|
||||
#if STM32H7_NGPIO > 2
|
||||
# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */
|
||||
#endif
|
||||
#if STM32H7_NGPIO > 3
|
||||
# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */
|
||||
#endif
|
||||
#if STM32H7_NGPIO > 4
|
||||
# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */
|
||||
#endif
|
||||
#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF))
|
||||
# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */
|
||||
#endif
|
||||
#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG))
|
||||
# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
|
||||
#endif
|
||||
#if STM32H7_NGPIO > 7
|
||||
# define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */
|
||||
#endif
|
||||
#if STM32H7_NGPIO > 8
|
||||
# define GPIO_PORTI (8 << GPIO_PORT_SHIFT) /* GPIOI */
|
||||
#endif
|
||||
#if STM32H7_NGPIO > 9
|
||||
# define GPIO_PORTJ (9 << GPIO_PORT_SHIFT) /* GPIOJ */
|
||||
#endif
|
||||
#if STM32H7_NGPIO > 10
|
||||
# define GPIO_PORTK (10 << GPIO_PORT_SHIFT) /* GPIOK */
|
||||
#endif
|
||||
|
||||
/* This identifies the bit in the port:
|
||||
*
|
||||
@@ -315,7 +339,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value);
|
||||
|
||||
bool stm32_gpioread(uint32_t pinset);
|
||||
|
||||
/****************************************************************************
|
||||
/************************************************************************************
|
||||
* Name: stm32_gpiosetevent
|
||||
*
|
||||
* Description:
|
||||
|
||||
@@ -349,10 +349,10 @@ static inline void rcc_enableahb4(void)
|
||||
#if STM32H7_NGPIO > 4
|
||||
| RCC_AHB4ENR_GPIOEEN
|
||||
#endif
|
||||
#if STM32H7_NGPIO > 5
|
||||
#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF))
|
||||
| RCC_AHB4ENR_GPIOFEN
|
||||
#endif
|
||||
#if STM32H7_NGPIO > 6
|
||||
#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG))
|
||||
| RCC_AHB4ENR_GPIOGEN
|
||||
#endif
|
||||
#if STM32H7_NGPIO > 7
|
||||
|
||||
@@ -349,10 +349,10 @@ static inline void rcc_enableahb4(void)
|
||||
#if STM32H7_NGPIO > 4
|
||||
| RCC_AHB4ENR_GPIOEEN
|
||||
#endif
|
||||
#if STM32H7_NGPIO > 5
|
||||
#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF))
|
||||
| RCC_AHB4ENR_GPIOFEN
|
||||
#endif
|
||||
#if STM32H7_NGPIO > 6
|
||||
#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG))
|
||||
| RCC_AHB4ENR_GPIOGEN
|
||||
#endif
|
||||
#if STM32H7_NGPIO > 7
|
||||
|
||||
Reference in New Issue
Block a user