diff --git a/Documentation/NuttX.html b/Documentation/NuttX.html index 166c0ce5221..83ecadd8fc0 100644 --- a/Documentation/NuttX.html +++ b/Documentation/NuttX.html @@ -5991,7 +5991,6 @@ Mem: 29232 5920 23312 23312

STMicro STM32 H7x3 - STMicro STM32 F76xx/F77xx. Architecture support for the STM32 H7x3 was added through efforts of several people in NuttX-7.26. Support is available for one board from this family:

diff --git a/arch/arm/include/stm32h7/chip.h b/arch/arm/include/stm32h7/chip.h index 8deccf0df4c..eed4ab88797 100644 --- a/arch/arm/include/stm32h7/chip.h +++ b/arch/arm/include/stm32h7/chip.h @@ -49,12 +49,19 @@ /* STM32H7x3xx Differences between family members: * - * ----------- ---------------- + * ----------- ---------------- ----- ---- + * SPI + * PART PACKAGE GPIOs I2S + * ----------- ---------------- ----- ---- + * STM32H7x3Ax UFBGA169 132 6/3 + * STM32H7x3Bx LQFP208 168 6/3 + * STM32H7x3Ix LQFP176/UFBGA176 140 6/3 + * STM32H7x3Vx LQFP100/TFBGA100 82 5/3 + * STM32H7x3Xx TFBGA240 168 6/3 + * STM32H7x3Zx LQFP144 114 6/3 + * ----------- ---------------- ----- ---- * - * PART PACKAGE - * ----------- ---------------- - * STM32H7x3Zx LQFP144 - * ----------- ---------------- + * Parts STM32H7xxxG have 1024Kb of FLASH * * Parts STM32H7xxxI have 2048Kb of FLASH * @@ -62,7 +69,24 @@ * with CONFIG_STM32H7_FLASH_OVERRIDE_x */ -#if defined(CONFIG_ARCH_CHIP_STM32H743ZI) || defined(CONFIG_ARCH_CHIP_STM32H753II) +#if defined (CONFIG_ARCH_CHIP_STM32H743AG) || \ + defined (CONFIG_ARCH_CHIP_STM32H743AI) || \ + defined (CONFIG_ARCH_CHIP_STM32H743BG) || \ + defined (CONFIG_ARCH_CHIP_STM32H743BI) || \ + defined (CONFIG_ARCH_CHIP_STM32H743IG) || \ + defined (CONFIG_ARCH_CHIP_STM32H743II) || \ + defined (CONFIG_ARCH_CHIP_STM32H743VG) || \ + defined (CONFIG_ARCH_CHIP_STM32H743VI) || \ + defined (CONFIG_ARCH_CHIP_STM32H743XG) || \ + defined (CONFIG_ARCH_CHIP_STM32H743XI) || \ + defined (CONFIG_ARCH_CHIP_STM32H743ZG) || \ + defined (CONFIG_ARCH_CHIP_STM32H743ZI) || \ + defined (CONFIG_ARCH_CHIP_STM32H753AI) || \ + defined (CONFIG_ARCH_CHIP_STM32H753BI) || \ + defined (CONFIG_ARCH_CHIP_STM32H753II) || \ + defined (CONFIG_ARCH_CHIP_STM32H753VI) || \ + defined (CONFIG_ARCH_CHIP_STM32H753XI) || \ + defined (CONFIG_ARCH_CHIP_STM32H753ZI) #elif defined(CONFIG_ARCH_CHIP_STM32H747XI) #else # error STM32 H7 chip not identified @@ -92,7 +116,22 @@ /* Peripherals */ -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# if defined(CONFIG_STM32H7_IO_CONFIG_A) +# define STM32H7_NGPIO (10) /* GPIOA-GPIOJ */ +# elif defined(CONFIG_STM32H7_IO_CONFIG_B) +# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# elif defined(CONFIG_STM32H7_IO_CONFIG_I) +# define STM32H7_NGPIO (9) /* GPIOA-GPIOI */ +# elif defined(CONFIG_STM32H7_IO_CONFIG_V) +# define STM32H7_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ +# elif defined(CONFIG_STM32H7_IO_CONFIG_X) +# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# elif defined(CONFIG_STM32H7_IO_CONFIG_Z) +# define STM32H7_NGPIO (8) /* GPIOA-GPIOH */ +# else +# error CONFIG_STM32H7_IO_CONFIG_x Not Set +# endif + # define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ # define STM32H7_NADC (3) /* (3) ADC1-3*/ # define STM32H7_NDAC (2) /* (2) DAC1-2*/ @@ -172,7 +211,7 @@ # define STM32H7_NFMC 0 /* No FMC memory controller */ #endif -/* NVIC priority levels **************************************************************/ +/* NVIC priority levels *************************************************************/ /* 16 Programmable interrupt levels */ diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index bf1018ee293..c1a7e1510f4 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -12,13 +12,113 @@ choice default ARCH_CHIP_STM32H743ZI depends on ARCH_CHIP_STM32H7 +config ARCH_CHIP_STM32H743AG + bool "STM32H743AG" + select STM32H7_STM32H7X3XX + select STM32H7_FLASH_CONFIG_G + select STM32H7_IO_CONFIG_A + ---help--- + STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, + UFBGA169 + +config ARCH_CHIP_STM32H743AI + bool "STM32H743AI" + select STM32H7_STM32H7X3XX + select STM32H7_FLASH_CONFIG_I + select STM32H7_IO_CONFIG_A + ---help--- + STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, + UFBGA169 + +config ARCH_CHIP_STM32H743BG + bool "STM32H743BG" + select STM32H7_STM32H7X3XX + select STM32H7_FLASH_CONFIG_G + select STM32H7_IO_CONFIG_B + ---help--- + STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, + LQFP208 + +config ARCH_CHIP_STM32H743BI + bool "STM32H743BI" + select STM32H7_STM32H7X3XX + select STM32H7_FLASH_CONFIG_I + select STM32H7_IO_CONFIG_B + ---help--- + STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, + LQFP208 + +config ARCH_CHIP_STM32H743IG + bool "STM32H743IG" + select STM32H7_STM32H7X3XX + select STM32H7_FLASH_CONFIG_G + select STM32H7_IO_CONFIG_I + ---help--- + STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, + LQFP176 or UFBGA176 + +config ARCH_CHIP_STM32H743II + bool "STM32H743II" + select STM32H7_STM32H7X3XX + select STM32H7_FLASH_CONFIG_I + select STM32H7_IO_CONFIG_I + ---help--- + STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, + LQFP176 or UFBGA176 + +config ARCH_CHIP_STM32H743VG + bool "STM32H743VG" + select STM32H7_STM32H7X3XX + select STM32H7_FLASH_CONFIG_G + select STM32H7_IO_CONFIG_V + ---help--- + STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, + LQFP100 or TFBGA100 + +config ARCH_CHIP_STM32H743VI + bool "STM32H743VI" + select STM32H7_STM32H7X3XX + select STM32H7_FLASH_CONFIG_I + select STM32H7_IO_CONFIG_V + ---help--- + STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, + LQFP100 or TFBGA100 + +config ARCH_CHIP_STM32H743XG + bool "STM32H743XG" + select STM32H7_STM32H7X3XX + select STM32H7_FLASH_CONFIG_G + select STM32H7_IO_CONFIG_X + ---help--- + STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, + TFBGA240 + +config ARCH_CHIP_STM32H743XI + bool "STM32H743XI" + select STM32H7_STM32H7X3XX + select STM32H7_FLASH_CONFIG_I + select STM32H7_IO_CONFIG_X + ---help--- + STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, + TFBGA240 + +config ARCH_CHIP_STM32H743ZG + bool "STM32H743ZG" + select STM32H7_STM32H7X3XX + select STM32H7_FLASH_CONFIG_G + select STM32H7_IO_CONFIG_Z + ---help--- + STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, + LQFP144 + config ARCH_CHIP_STM32H743ZI bool "STM32H743ZI" select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I -# TODO: IO_CONFIG + select STM32H7_IO_CONFIG_Z ---help--- - STM32 H7 Cortex M7, 2048 FLASH, 1024K Kb SRAM + STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, + LQFP144 config ARCH_CHIP_STM32H747XI bool "STM32H747XI" @@ -26,18 +126,89 @@ config ARCH_CHIP_STM32H747XI select STM32H7_FLASH_CONFIG_I # TODO: IO_CONFIG ---help--- - Dual core STM32 H7 Cortex M7+M4, 2048 FLASH, 1024K Kb SRAM + Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM + +config ARCH_CHIP_STM32H753AI + bool "STM32H753AI" + select STM32H7_STM32H7X3XX + select STM32H7_FLASH_CONFIG_I + select STM32H7_IO_CONFIG_A + ---help--- + STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, + with cryptographic accelerator, UFBGA169 + + +config ARCH_CHIP_STM32H753BI + bool "STM32H753BI" + select STM32H7_STM32H7X3XX + select STM32H7_FLASH_CONFIG_I + select STM32H7_IO_CONFIG_B + ---help--- + STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, + with cryptographic accelerator, LQFP208 config ARCH_CHIP_STM32H753II bool "STM32H753II" select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I -# TODO: IO_CONFIG + select STM32H7_IO_CONFIG_I ---help--- - STM32 H7 Cortex M7, 2048 FLASH, 1024K Kb SRAM + STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, + with cryptographic accelerator, LQFP176/UFBGA176 + +config ARCH_CHIP_STM32H753VI + bool "STM32H753VI" + select STM32H7_STM32H7X3XX + select STM32H7_FLASH_CONFIG_I + select STM32H7_IO_CONFIG_V + ---help--- + STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, + with cryptographic accelerator, LQFP100/TFBGA100 + +config ARCH_CHIP_STM32H753XI + bool "STM32H753XI" + select STM32H7_STM32H7X3XX + select STM32H7_FLASH_CONFIG_I + select STM32H7_IO_CONFIG_X + ---help--- + STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, + with cryptographic accelerator, TFBGA240 + +config ARCH_CHIP_STM32H753ZI + bool "STM32H753ZI" + select STM32H7_STM32H7X3XX + select STM32H7_FLASH_CONFIG_I + select STM32H7_IO_CONFIG_Z + ---help--- + STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, + with cryptographic accelerator, LQFP144 endchoice # STM32 H7 Chip Selection +config STM32H7_IO_CONFIG_A + bool + default n + +config STM32H7_IO_CONFIG_B + bool + default n + +config STM32H7_IO_CONFIG_I + bool + default n + +config STM32H7_IO_CONFIG_V + bool + default n + +config STM32H7_IO_CONFIG_X + bool + default n + +config STM32H7_IO_CONFIG_Z + bool + default n + config STM32H7_STM32H7X3XX bool default n @@ -50,11 +221,11 @@ config STM32H7_STM32H7X3XX select ARMV7M_HAVE_DTCM select STM32H7_HAVE_ETHERNET select STM32H7_HAVE_FMC + select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V + select STM32H7_HAVE_GPIOG if !STM32H7_IO_CONFIG_V select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 + select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V select STM32H7_HAVE_SPI6 - bool - default n config STM32H7_STM32H7X7XX bool @@ -68,11 +239,11 @@ config STM32H7_STM32H7X7XX select ARMV7M_HAVE_DTCM select STM32H7_HAVE_ETHERNET select STM32H7_HAVE_FMC + select STM32H7_HAVE_GPIOF + select STM32H7_HAVE_GPIOG select STM32H7_HAVE_SPI4 select STM32H7_HAVE_SPI5 select STM32H7_HAVE_SPI6 - bool - default n config STM32H7_FLASH_CONFIG_B bool @@ -159,8 +330,16 @@ config STM32H7_HAVE_ETHERNET default n config STM32H7_HAVE_FMC - bool - default n + bool + default n + +config STM32H7_HAVE_GPIOF + bool + default n + +config STM32H7_HAVE_GPIOG + bool + default n config STM32H7_HAVE_SPI4 bool @@ -289,13 +468,13 @@ config STM32H7_ETHMAC select ARCH_HAVE_PHY config STM32H7_FMC - bool "FMC" - default n - depends on STM32H7_HAVE_FMC - ---help--- - Enable Flexible Memory Controller. - To correctly configure FMC for your hardware, you will have to define - a number of macros in your board.h file. See stm32_fmc.c for directions. + bool "FMC" + default n + depends on STM32H7_HAVE_FMC + ---help--- + Enable Flexible Memory Controller. + To correctly configure FMC for your hardware, you will have to define + a number of macros in your board.h file. See stm32_fmc.c for directions. config STM32H7_OTGFS bool "OTG FS" diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h index 20980009295..3c7c9068a84 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h @@ -129,7 +129,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 5 +#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -142,7 +142,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 6 +#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32h7/stm32_gpio.c b/arch/arm/src/stm32h7/stm32_gpio.c index 6f56e76f2f2..0db84636be9 100644 --- a/arch/arm/src/stm32h7/stm32_gpio.c +++ b/arch/arm/src/stm32h7/stm32_gpio.c @@ -83,10 +83,18 @@ const uint32_t g_gpiobase[STM32H7_NGPIO] = STM32_GPIOE_BASE, #endif #if STM32H7_NGPIO > 5 +# if defined(CONFIG_STM32H7_HAVE_GPIOF) STM32_GPIOF_BASE, +# else + 0, +# endif #endif #if STM32H7_NGPIO > 6 +# if defined(CONFIG_STM32H7_HAVE_GPIOG) STM32_GPIOG_BASE, +# else + 0, +# endif #endif #if STM32H7_NGPIO > 7 STM32_GPIOH_BASE, @@ -165,6 +173,10 @@ int stm32_configgpio(uint32_t cfgset) /* Get the port base address */ base = g_gpiobase[port]; + if (base == 0) + { + return -EINVAL; + } /* Get the pin number and select the port configuration register for that * pin @@ -182,7 +194,10 @@ int stm32_configgpio(uint32_t cfgset) break; case GPIO_OUTPUT: /* General purpose output mode */ - stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */ + + /* Set the initial output value */ + + stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); pinmode = GPIO_MODER_OUTPUT; break; @@ -312,7 +327,9 @@ int stm32_configgpio(uint32_t cfgset) putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); - /* Otherwise, it is an input pin. Should it configured as an EXTI interrupt? */ + /* Otherwise, it is an input pin. Should it configured as an EXTI + * interrupt? + */ if (pinmode != GPIO_MODER_OUTPUT && (cfgset & GPIO_EXTI) != 0) { @@ -342,14 +359,15 @@ int stm32_configgpio(uint32_t cfgset) * Name: stm32_unconfiggpio * * Description: - * Unconfigure a GPIO pin based on bit-encoded description of the pin, set it - * into default HiZ state (and possibly mark it's unused) and unlock it whether - * it was previously selected as alternative function (GPIO_ALT|GPIO_CNF_AFPP|...). + * Unconfigure a GPIO pin based on bit-encoded description of the pin, set + * it into default HiZ state (and possibly mark it's unused) and unlock it + * whether it was previously selected as alternative function + * (GPIO_ALT|GPIO_CNF_AFPP|...). * - * This is a safety function and prevents hardware from schocks, as unexpected - * write to the Timer Channel Output GPIO to fixed '1' or '0' while it should - * operate in PWM mode could produce excessive on-board currents and trigger - * over-current/alarm function. + * This is a safety function and prevents hardware from shocks, as + * unexpected write to the Timer Channel Output GPIO to fixed '1' or '0' + * while it should operate in PWM mode could produce excessive on-board + * currents and trigger over-current/alarm function. * * Returned Value: * OK on success @@ -391,23 +409,25 @@ void stm32_gpiowrite(uint32_t pinset, bool value) /* Get the port base address */ base = g_gpiobase[port]; - - /* Get the pin number */ - - pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - - /* Set or clear the output on the pin */ - - if (value) + if (base != 0) { - bit = GPIO_BSRR_SET(pin); - } - else - { - bit = GPIO_BSRR_RESET(pin); - } + /* Get the pin number */ - putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); + pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Set or clear the output on the pin */ + + if (value) + { + bit = GPIO_BSRR_SET(pin); + } + else + { + bit = GPIO_BSRR_RESET(pin); + } + + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); + } } } @@ -431,11 +451,14 @@ bool stm32_gpioread(uint32_t pinset) /* Get the port base address */ base = g_gpiobase[port]; + if (base != 0) + { + /* Get the pin number and return the input state of that pin */ - /* Get the pin number and return the input state of that pin */ - - pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & + (1 << pin)) != 0); + } } return 0; diff --git a/arch/arm/src/stm32h7/stm32_gpio.h b/arch/arm/src/stm32h7/stm32_gpio.h index 3eca1e8f3b7..fb70e6545f0 100644 --- a/arch/arm/src/stm32h7/stm32_gpio.h +++ b/arch/arm/src/stm32h7/stm32_gpio.h @@ -58,8 +58,8 @@ /* Bit-encoded input to stm32_configgpio() */ -/* Each port bit of the general-purpose I/O (GPIO) ports can be individually configured - * by software in several modes: +/* Each port bit of the general-purpose I/O (GPIO) ports can be individually + * configured by software in several modes: * * - Input floating * - Input pull-up @@ -162,7 +162,9 @@ #define GPIO_OPENDRAIN (1 << 9) /* Bit9: 1=Open-drain output */ #define GPIO_PUSHPULL (0) /* Bit9: 0=Push-pull output */ -/* If the pin is a GPIO digital output, then this identifies the initial output value. +/* If the pin is a GPIO digital output, then this identifies the initial output + * value. + * * If the pin is an input, this bit is overloaded to provide the qualifier to * distinguish input pull-up and -down: * @@ -195,17 +197,39 @@ #define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */ #define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) +#if STM32H7_NGPIO > 0 # define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ +#endif +#if STM32H7_NGPIO > 1 # define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ +#endif +#if STM32H7_NGPIO > 2 # define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ +#endif +#if STM32H7_NGPIO > 3 # define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ +#endif +#if STM32H7_NGPIO > 4 # define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ +#endif +#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) # define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ +#endif +#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) # define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */ +#endif +#if STM32H7_NGPIO > 7 # define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */ +#endif +#if STM32H7_NGPIO > 8 # define GPIO_PORTI (8 << GPIO_PORT_SHIFT) /* GPIOI */ +#endif +#if STM32H7_NGPIO > 9 # define GPIO_PORTJ (9 << GPIO_PORT_SHIFT) /* GPIOJ */ +#endif +#if STM32H7_NGPIO > 10 # define GPIO_PORTK (10 << GPIO_PORT_SHIFT) /* GPIOK */ +#endif /* This identifies the bit in the port: * @@ -315,7 +339,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value); bool stm32_gpioread(uint32_t pinset); -/**************************************************************************** +/************************************************************************************ * Name: stm32_gpiosetevent * * Description: diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c index 770607be446..fa5555d439c 100644 --- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c @@ -349,10 +349,10 @@ static inline void rcc_enableahb4(void) #if STM32H7_NGPIO > 4 | RCC_AHB4ENR_GPIOEEN #endif -#if STM32H7_NGPIO > 5 +#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) | RCC_AHB4ENR_GPIOFEN #endif -#if STM32H7_NGPIO > 6 +#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) | RCC_AHB4ENR_GPIOGEN #endif #if STM32H7_NGPIO > 7 diff --git a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c index 2b6a1c82fa9..859997c6b1d 100644 --- a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c @@ -349,10 +349,10 @@ static inline void rcc_enableahb4(void) #if STM32H7_NGPIO > 4 | RCC_AHB4ENR_GPIOEEN #endif -#if STM32H7_NGPIO > 5 +#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) | RCC_AHB4ENR_GPIOFEN #endif -#if STM32H7_NGPIO > 6 +#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) | RCC_AHB4ENR_GPIOGEN #endif #if STM32H7_NGPIO > 7