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Merged nuttx/nuttx into master

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jjlange
2019-07-17 10:05:38 -05:00
parent 00ddedbcd2 3ac3451404
commit 9ae6140b5a
483 changed files with 33926 additions and 30113 deletions
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Documentation/NuttX.html
+10 -3
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@@ -104,7 +104,7 @@
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
<p>Last Updated: May 19, 2019</p>
<p>Last Updated: July 11, 2019</p>
</td>
</tr>
</table>
@@ -2771,14 +2771,21 @@ nsh>
<p>
<a name="nxplpc11xx"><b>NXP LPC11xx</b>.</a>
Support is provided for the NXP LPC11xx family of processors.
In particular, support is provided for LPCXpression LPC1115 board.
In particular, support is provided for LPCXpresso LPC1115 board.
This port was contributed by Alan Carvalho de Assis.
</p>
<ul>
<p>
<b>STATUS:</b>
The first released version was provided in NuttX 7.10.
Refer to the board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/lpcxpresso-lpc1115/README.txt" target="_blank">README.txt</a> file for further information.
Refer to the board <a href="https://bitbucket.org/nuttx/obsoleted/src/master/nuttx/configs/lpcxpresso-lpc1115/README.txt" target="_blank">README.txt</a> file for further information.
</p>
<p>
<b>Obsoleted:</b>
Support for the LPCXpresso-LPC1115 and for the LPC1115 architecture in general was removed after NuttX-7.30.
The LPC11 port was never really used (to my knowledge) and was no longer supported.
A snapshot of the port is still available in the <a href="https://bitbucket.org/nuttx/obsoleted/src/master/ChangeLog" target="_blank">Obsoleted</a> repository.
It can be brought back into the main repository at any time if anyone is willing to provide support for the architecture.
</p>
</ul>
</td>
Documentation/NuttxPortingGuide.html
+3 -3
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@@ -6273,7 +6273,7 @@ int kbd_decode(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *sta
</p>
<p>
<b>Examples</b>:
<code>arch/arm/src/lpc17xx/lpc17_usbhost.c</code>,
<code>arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c</code>,
<code>arch/arm/src/stm32/stm32_otgfshost.c</code>,
<code>arch/arm/src/sama5/sam_ohci.c</code>, and
<code>arch/arm/src/sama5/sam_ehci.c</code>.
@@ -6366,7 +6366,7 @@ int kbd_decode(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *sta
</p>
<p>
<b>Examples</b>:
The function <code>nsh_waiter()</code> in the file <code>configs/olimex-lpc1766stk/src/lpc17_appinit.c</code>.
The function <code>nsh_waiter()</code> in the file <code>configs/olimex-lpc1766stk/src/lpc17_40_appinit.c</code>.
</p>
</li>
<li>
@@ -6409,7 +6409,7 @@ int kbd_decode(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *sta
</p>
<p>
<b>Examples</b>:
<code>arch/arm/src/dm320/dm320_usbdev.c</code>, <code>arch/arm/src/lpc17xx/lpc17_usbdev.c</code>,
<code>arch/arm/src/dm320/dm320_usbdev.c</code>, <code>arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c</code>,
<code>arch/arm/src/lpc214x/lpc214x_usbdev.c</code>, <code>arch/arm/src/lpc313x/lpc313x_usbdev.c</code>, and
<code>arch/arm/src/stm32/stm32_usbdev.c</code>.
</p>
Documentation/README.html
-2
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@@ -153,8 +153,6 @@ nuttx/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/llpc4357-evb/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- lpc4370-link2/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/llpc4370-link2/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- lpcxpresso-lpc1115/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/lpcxpresso-lpc1115/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- lpcxpresso-lpc1768/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/lpcxpresso-lpc1768/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- lpcxpresso-lpc54628/
Documentation/UsbTrace.html
+7 -7
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@@ -112,7 +112,7 @@
</li>
<li>
For the USB device driver, that 8-bit event data is provided within the USB device driver itself.
So, for example, the 8-bit event data for the LPC1768 USB device driver is found in <code>arch/arm/src/lpc17xx/lpc17_usbdev.c</code>.
So, for example, the 8-bit event data for the LPC1768 USB device driver is found in <code>arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c</code>.
</li>
</ul>
<p><b>16-bit Trace Data</b>.
@@ -237,28 +237,28 @@
<td align="center">3</td>
<td align="left"><code>TRACE_INTENTRY_ID</code><sup>1</sup></td>
<td align="right">1</td>
<td align="left"><code>LPC17_TRACEINTID_USB</code><sup>2</sup></td>
<td align="left"><code>LPC17_40_TRACEINTID_USB</code><sup>2</sup></td>
<td align="left">0039</td>
</tr>
<tr>
<td align="center">4</td>
<td align="left"><code>TRACE_INTDECODE_ID</code><sup>2</sup></td>
<td align="right">7</td>
<td align="left"><code>LPC17_TRACEINTID_DEVSTAT</code><sup>2</sup></td>
<td align="left"><code>LPC17_40_TRACEINTID_DEVSTAT</code><sup>2</sup></td>
<td align="left">0019</td>
</tr>
<tr>
<td align="center">5</td>
<td align="left"><code>TRACE_INTDECODE_ID</code><sup>2</sup></td>
<td align="right">32</td>
<td align="left"><code>LPC17_TRACEINTID_SUSPENDCHG</code><sup>2</sup></td>
<td align="left"><code>LPC17_40_TRACEINTID_SUSPENDCHG</code><sup>2</sup></td>
<td align="left">0019</td>
</tr>
<tr>
<td align="center">6</td>
<td align="left"><code>TRACE_INTDECODE_ID</code><sup>2</sup></td>
<td align="right">6</td>
<td align="left"><code>LPC17_TRACEINTID_DEVRESET</code><sup>2</sup></td>
<td align="left"><code>LPC17_40_TRACEINTID_DEVRESET</code><sup>2</sup></td>
<td align="left">0019</td>
</tr>
<tr>
@@ -279,13 +279,13 @@
<td align="center">9</td>
<td align="left"><code>TRACE_INTEXIT_ID</code><sup>1</sup></td>
<td align="right">1</td>
<td align="left"><code>LPC17_TRACEINTID_USB</code><sup>2</sup></td>
<td align="left"><code>LPC17_40_TRACEINTID_USB</code><sup>2</sup></td>
<td align="left">0000</td>
</tr>
</table>
<p><small><b>NOTES</b>:<br>
<sup>1</sup>See <code>include/nuttx/usb/usbdev_trace.h</code><br>
<sup>2</sup><code>See arch/arm/src/lpc17xx/lpc17_usbdev.c</code>
<sup>2</sup><code>See arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c</code>
</small></p>
</ul>
<p>
README.txt
-2
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@@ -1848,8 +1848,6 @@ nuttx/
| | `- README.txt
| |- lpc4370-link2/
| | `- README.txt
| |- lpcxpresso-lpc1115/
| | `- README.txt
| |- lpcxpresso-lpc1768/
| | `- README.txt
| |- lpcxpresso-lpc54628/
arch/README.txt
+2 -3
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@@ -166,9 +166,8 @@ arch/arm - ARM-based micro-controllers
arch/arm/include/imx6 and arch/arm/src/imrt
arch/arm/include/kinetis and arch/arm/src/kinetis
arch/arm/include/kl and arch/arm/src/kl
arch/arm/include/lpc11xx and arch/arm/src/lc823450
arch/arm/include/lpc11xx and arch/arm/src/lpc11xx
arch/arm/include/lpc17xx and arch/arm/src/lpc17xx
arch/arm/include/lc823450 and arch/arm/src/lc823450
arch/arm/include/lpc17xx_40xx and arch/arm/src/lpc17xx_40xx
arch/arm/include/lpc214x and arch/arm/src/lpc214x
arch/arm/include/lpc2378 and arch/arm/src/lpc2378.
arch/arm/include/lpc31xx and arch/arm/src/lpc31xx
arch/arm/Kconfig
+7 -18
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@@ -133,21 +133,14 @@ config ARCH_CHIP_LM
---help---
TI/Luminary Stellaris LMS3 and LM4F architectures (ARM Cortex-M3/4)
config ARCH_CHIP_LPC11XX
bool "NXP LPC11xx"
select ARCH_CORTEXM0
---help---
NXP LPC11xx architectures (ARM Cortex-M0)
config ARCH_CHIP_LPC17XX
bool "NXP LPC17xx"
select ARCH_CORTEXM3
config ARCH_CHIP_LPC17XX_40XX
bool "NXP LPC17xx/LPC40xx"
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_FETCHADD
select ARMV7M_HAVE_STACKCHECK
---help---
NXP LPC17xx architectures (ARM Cortex-M3)
NXP LPC17xx & LPC40xx architectures (ARM Cortex-M3/4)
config ARCH_CHIP_LPC214X
bool "NXP LPC214x"
@@ -665,9 +658,8 @@ config ARCH_CHIP
default "kinetis" if ARCH_CHIP_KINETIS
default "kl" if ARCH_CHIP_KL
default "lc823450" if ARCH_CHIP_LC823450
default "tiva" if ARCH_CHIP_LM || ARCH_CHIP_TIVA ||ARCH_CHIP_SIMPLELINK
default "lpc11xx" if ARCH_CHIP_LPC11XX
default "lpc17xx" if ARCH_CHIP_LPC17XX
default "tiva" if ARCH_CHIP_LM || ARCH_CHIP_TIVA || ARCH_CHIP_SIMPLELINK
default "lpc17xx_40xx" if ARCH_CHIP_LPC17XX_40XX
default "lpc214x" if ARCH_CHIP_LPC214X
default "lpc2378" if ARCH_CHIP_LPC2378
default "lpc31xx" if ARCH_CHIP_LPC31XX
@@ -877,11 +869,8 @@ endif
if ARCH_CHIP_LM || ARCH_CHIP_TIVA || ARCH_CHIP_SIMPLELINK
source arch/arm/src/tiva/Kconfig
endif
if ARCH_CHIP_LPC11XX
source arch/arm/src/lpc11xx/Kconfig
endif
if ARCH_CHIP_LPC17XX
source arch/arm/src/lpc17xx/Kconfig
if ARCH_CHIP_LPC17XX_40XX
source arch/arm/src/lpc17xx_40xx/Kconfig
endif
if ARCH_CHIP_LPC214X
source arch/arm/src/lpc214x/Kconfig
arch/arm/include/cxd56xx/geofence.h
+233
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@@ -0,0 +1,233 @@
/****************************************************************************
* arch/arm/include/cxd56xx/geofence.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_CXD56XX_GEOFENCE_H
#define __ARCH_ARM_INCLUDE_CXD56XX_GEOFENCE_H
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* Start geofence monitoring.
* This command is used to start the geofence monitoring.
*
* param arg
* Parameter is Unnecessary. Set Zero.
*/
#define CXD56_GEOFENCE_IOCTL_START 1
/* Stop geofence monitoring.
* This command is used to stop the geofence monitoring.
*
* param arg
* Parameter is Unnecessary. Set Zero.
*/
#define CXD56_GEOFENCE_IOCTL_STOP 2
/* Add region.
* This command is used to add the region.
*
* param arg
* Parameter is struct cxd56_geofence_region_s.
*/
#define CXD56_GEOFENCE_IOCTL_ADD 3
/* Modify region.
* This command is used to modify the region.
*
* param arg
* Parameter is struct cxd56_geofence_region_s.
*/
#define CXD56_GEOFENCE_IOCTL_MODIFY 4
/* Delete region.
* This command is used to delete the region.
*
* param arg
* Parameter is region id.
*/
#define CXD56_GEOFENCE_IOCTL_DELETE 5
/* Delete all region.
* This command is used to delete all region.
*
* param arg
* Parameter is Unnecessary. Set Zero.
*/
#define CXD56_GEOFENCE_IOCTL_ALL_DELETE 6
/* Get region data.
* This command is used to get region data.
*
* param arg
* Parameter is struct cxd56_geofence_region_s pointer
* Latitude and longitude and radius data of specified id is stored.
*/
#define CXD56_GEOFENCE_IOCTL_GET_REGION_DATA 7
/* Get used id.
* This command is used to get used region id.
*
* param arg
* Parameter is uint32_t data pointer.
* The used id is represented by bit field.
* For example, when ID0 and ID19 are used,
* since bit0 and bit19 are set, the return value is 0x00080001.
*/
#define CXD56_GEOFENCE_IOCTL_GET_USED_ID 8
/* Get all status.
* This command is used to get all region status.
*
* param arg
* Parameter is Unnecessary. Set Zero.
* All region status will stored in next read data.
*/
#define CXD56_GEOFENCE_IOCTL_GET_ALL_STATUS 9
/* Set goefence operation mode
* This command is used to set operation mode.
*
* param arg
* Parameter is struct cxd56_geofence_mode_s.
*/
#define CXD56_GEOFENCE_IOCTL_SET_MODE 10
/* check macros for GNSS commands */
#define CXD56_GEOFENCE_IOCTL_INVAL 0
#define CXD56_GEOFENCE_IOCTL_MAX 11
/* The transition type indicating that the user exits the region. */
#define CXD56_GEOFENCE_TRANSITION_EXIT 0
/* The transition type indicating that the user enters the region. */
#define CXD56_GEOFENCE_TRANSITION_ENTER 1
/* The transition type indicating that the user enters and
* dwells in region for a given period of time.
*/
#define CXD56_GEOFENCE_TRANSITION_DWELL 2
/* MAX number of region on the CXD56xx. */
#define CXD56_GEOFENCE_REGION_CAPACITY 20
/* Region center point and radius data
*
* The latitude and longtitude data format is
* integer value multiplied by 1000000.
* Example: When latitude is 35.123456, specify 35123456.
*/
struct cxd56_geofence_region_s
{
/* Region ID The range of ID is 0 to 19. */
uint8_t id;
/* Latitude (degree) of the center position of the region. */
long latitude;
/* Longitude (degree) of the center position of the region. */
long longitude;
/* Radius (m) of the region. */
uint16_t radius;
};
/* Geofence mode setting parameter */
struct cxd56_geofence_mode_s
{
uint16_t deadzone; /* dead zone [meter] */
uint16_t dwell_detecttime; /* Dewlling period time [sec] */
};
/* The transition data */
struct cxd56_geofence_trans_s
{
/* Region ID */
uint8_t id;
/* Transition status.
* The status is #CXD56_GEOFENCE_TRANSITION_EXIT or
* #CXD56_GEOFENCE_TRANSITION_ENTER or #CXD56_GEOFENCE_TRANSITION_DWELL.
*/
uint8_t status;
};
/* Geofence output data structer. */
struct cxd56_geofence_status_s
{
/* Updated region ID count */
uint8_t update;
/* The detail data od updated region ID */
struct cxd56_geofence_trans_s status[CXD56_GEOFENCE_REGION_CAPACITY];
};
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ARCH_ARM_INCLUDE_ARCH_CXD56XX_GEOFENCE_H */
arch/arm/include/cxd56xx/gnss.h
+869
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File diff suppressed because it is too large Load Diff
arch/arm/include/cxd56xx/gnss_type.h
+710
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File diff suppressed because it is too large Load Diff
arch/arm/src/lpc11xx/lpc11_wdt.h → arch/arm/include/cxd56xx/uart0.h
+36 -30
View File
@@ -1,8 +1,7 @@
/************************************************************************************
* arch/arm/src/lpc11xx/lpc11_wdt.h
/****************************************************************************
* arch/arm/include/cxd56xx/cxd56_uart0.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -14,9 +13,10 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
@@ -31,32 +31,38 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_WDT_H
#define __ARCH_ARM_SRC_LPC11XX_LPC11_WDT_H
#ifndef __ARM_ARCH_INCLUDE_CXD56XX_CXD56_UART0_H
#define __ARM_ARCH_INCLUDE_CXD56XX_CXD56_UART0_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "hardware/lpc11_wdt.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Functions
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_WDT_H */
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
int cxd56_uart0initialize(FAR const char *devname);
void cxd56_uart0uninitialize(FAR const char *devname);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARM_ARCH_INCLUDE_CXD56XX_CXD56_UART0_H */
arch/arm/include/lpc11xx/chip.h
-92
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@@ -1,92 +0,0 @@
/************************************************************************************
* arch/arm/include/lpc11xx/chip.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H
#define __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Get customizations for each supported chip */
#if defined(CONFIG_ARCH_CHIP_LPC1115)
# define LPC111x 1 /* LPC111x family */
# define LPC11_FLASH_SIZE (64*1024) /* 64Kb */
# define LPC11_SRAM_SIZE (8*1024) /* 8Kb */
# define LPC11_CPUSRAM_SIZE (8*1024)
# undef LPC11_HAVE_BANK0 /* No AHB SRAM bank 0 */
# undef LPC11_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC11_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC11_NUSBHOST 0 /* No USB host controller */
# define LPC11_NUSBOTG 0 /* No USB OTG controller */
# define LPC11_NUSBDEV 1 /* One USB device controller */
# define LPC11_NCAN 1 /* One CAN controller */
# define LPC11_NI2S 0 /* No I2S modules */
# define LPC11_NDAC 0 /* No DAC module */
#else
# error "Unsupported LPC11xx chip"
#endif
/* NVIC priority levels *************************************************************/
/* Each priority field holds a priority value, 0-31. The lower the value, the greater
* the priority of the corresponding interrupt. The processor implements only
* bits[7:6] of each field, bits[5:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H */
arch/arm/include/lpc11xx/irq.h
-143
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@@ -1,143 +0,0 @@
/****************************************************************************
* arch/arm/include/lpc11xxx/irq.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
#include <arch/lpc11xx/chip.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*/
/* Common Processor Exceptions (vectors 0-15) */
#define LPC11_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define LPC11_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define LPC11_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
/* Vectors 4-10: Reserved */
#define LPC11_IRQ_SVCALL (11) /* Vector 11: SVC call */
/* Vector 12-13: Reserved */
#define LPC11_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define LPC11_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16) */
#define LPC11_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_ARCH_CHIP_LPC1115)
#define LPC11_IRQ_PIO0_0 (16) /* Vector 16: PIO0_0 */
#define LPC11_IRQ_PIO0_1 (17) /* Vector 17: PIO0_1 */
#define LPC11_IRQ_PIO0_2 (18) /* Vector 18: PIO0_2 */
#define LPC11_IRQ_PIO0_3 (19) /* Vector 19: PIO0_3 */
#define LPC11_IRQ_PIO0_4 (20) /* Vector 20: PIO0_4 */
#define LPC11_IRQ_PIO0_5 (21) /* Vector 21: PIO0_5 */
#define LPC11_IRQ_PIO0_6 (22) /* Vector 22: PIO0_6 */
#define LPC11_IRQ_PIO0_7 (23) /* Vector 23: PIO0_7 */
#define LPC11_IRQ_PIO0_8 (24) /* Vector 24: PIO0_8 */
#define LPC11_IRQ_PIO0_9 (25) /* Vector 25: PIO0_9 */
#define LPC11_IRQ_PIO0_10 (26) /* Vector 26: PIO0_10 */
#define LPC11_IRQ_PIO0_11 (27) /* Vector 27: PIO0_11 */
#define LPC11_IRQ_PIO1_0 (28) /* Vector 28: PIO1_0 */
#define LPC11_IRQ_CCAN (29) /* Vector 29: C_CAN controller for LPC11Cxx */
#define LPC11_IRQ_SSP1 (30) /* Vector 30: SPI1/SSP1 */
#define LPC11_IRQ_I2C0 (31) /* Vector 31: I2C0 */
#define LPC11_IRQ_CT16B0 (32) /* Vector 32: Clock/Timer0 16 bits */
#define LPC11_IRQ_CT16B1 (33) /* Vector 33: Clock/Timer1 16 bits */
#define LPC11_IRQ_CT32B0 (34) /* Vector 34: Clock/Timer0 32 bits */
#define LPC11_IRQ_CT32B1 (35) /* Vector 35: Clock/Timer1 32 bits */
#define LPC11_IRQ_SSP0 (36) /* Vector 36: SPI0/SSP0 */
#define LPC11_IRQ_UART (37) /* Vector 37: UART */
/* Vector 38: Reserved */
/* Vector 39: Reserved */
#define LPC11_IRQ_ADC (40) /* Vector 40: Analog/Digital Converter */
#define LPC11_IRQ_WDT (41) /* Vector 41: Watchdog timer */
#define LPC11_IRQ_BOD (42) /* Vector 42: Brownout Detection */
/* Vector 43: Reserved */
#define LPC11_IRQ_PIO3 (44) /* Vector 44: PIO3 */
#define LPC11_IRQ_PIO2 (45) /* Vector 45: PIO2 */
#define LPC11_IRQ_PIO1 (46) /* Vector 46: PIO1 */
#define LPC11_IRQ_PIO0 (47) /* Vector 47: PIO0 */
#endif
#define NR_IRQS (48) /* 32 interrupts plus 16 exceptions */
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
typedef void (*vic_vector_t)(uint32_t *regs);
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
extern "C"
{
#endif
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H */
arch/arm/include/lpc17xx/chip.h
-388
View File
@@ -1,388 +0,0 @@
/************************************************************************************
* arch/arm/include/lpc17xx/chip.h
*
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* with LPC178x support from Rommel Marcelo
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H
#define __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Get customizations for each supported chip */
#if defined(CONFIG_ARCH_CHIP_LPC1751)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (32*1024) /* 32Kb */
# define LPC17_SRAM_SIZE (8*1024) /* 8Kb */
# define LPC17_CPUSRAM_SIZE (8*1024)
# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 0 /* No USB host controller */
# define LPC17_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 1 /* One CAN controller */
# define LPC17_NI2S 0 /* No I2S modules */
# define LPC17_NDAC 0 /* No DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1752)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (64*1024) /* 65Kb */
# define LPC17_SRAM_SIZE (16*1024) /* 16Kb */
# define LPC17_CPUSRAM_SIZE (16*1024)
# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 0 /* No USB host controller */
# define LPC17_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 1 /* One CAN controller */
# define LPC17_NI2S 0 /* No I2S modules */
# define LPC17_NDAC 0 /* No DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1754)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */
# define LPC17_CPUSRAM_SIZE (16*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 1 /* One CAN controller */
# define LPC17_NI2S 0 /* No I2S modules */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1756)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */
# define LPC17_CPUSRAM_SIZE (16*1024)
# define LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1758)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1759)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1764)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */
# define LPC17_CPUSRAM_SIZE (16*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 0 /* No USB host controller */
# define LPC17_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 0 /* No I2S modules */
# define LPC17_NDAC 0 /* No DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1765)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1766)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1767)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 0 /* No USB host controller */
# define LPC17_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_NUSBDEV 0 /* No USB device controller */
# define LPC17_NCAN 0 /* No CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1773)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_SRAM_SIZE (40*1024) /* 40Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* No Peripheral SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LPC17_NUSBHOST /* No USB host controller */
# undef LPC17_NUSBOTG /* No USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_HAVE_SPIFI 1 /* Have SPIFI interface */
# undef LPC17_HAVE_LCD /* No LCD controller */
# undef LPC17_HAVE_QEI /* No QEI interface */
# undef LPC17_HAVE_SD /* No SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1774)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_SRAM_SIZE (40*1024) /* 40Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0*/
# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LPC17_NUSBHOST /* One USB host controller */
# undef LPC17_NUSBOTG /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_HAVE_LCD /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1776)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_HAVE_LCD /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1777)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_HAVE_LCD /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1778)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (96*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_HAVE_LCD /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1785)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_HAVE_LCD 1 /* One LCD controller */
# undef LPC17_HAVE_QEI /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1786)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_HAVE_LCD 1 /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1787)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_HAVE_LCD 1 /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1788)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_HAVE_LCD 1 /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#else
# error "Unsupported LPC17xx chip"
#endif
/* NVIC priority levels *************************************************************/
/* Each priority field holds a priority value, 0-31. The lower the value, the greater
* the priority of the corresponding interrupt. The processor implements only
* bits[7:3] of each field, bits[2:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x08 /* Five bits of interrupt priority used */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H */
arch/arm/include/lpc17xx/lpc176x_irq.h
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/****************************************************************************
* arch/lpc17xx/lpc176x_irq.h
*
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*/
/* External interrupts (vectors >= 16) */
#define LPC17_IRQ_WDT (LPC17_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */
#define LPC17_IRQ_TMR0 (LPC17_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_IRQ_TMR1 (LPC17_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_IRQ_TMR2 (LPC17_IRQ_EXTINT+3) /* Timer 2 Match 0-3
* Capture 0-1 */
#define LPC17_IRQ_TMR3 (LPC17_IRQ_EXTINT+4) /* Timer 3 Match 0-3
* Capture 0-1 */
#define LPC17_IRQ_UART0 (LPC17_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART1 (LPC17_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* Modem Control Change
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART2 (LPC17_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART3 (LPC17_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_PWM1 (LPC17_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1
* Capture 0-1 of PWM1 */
#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */
#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */
#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */
#define LPC17_IRQ_SPIF (LPC17_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF)
* Mode Fault (MODF) */
#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
* Rx FIFO half full of SSP0
* Rx Timeout of SSP0
* Rx Overrun of SSP0 */
#define LPC17_IRQ_SSP1 (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
* Rx FIFO half full
* Rx Timeout
* Rx Overrun */
#define LPC17_IRQ_PLL0 (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
#define LPC17_IRQ_RTC (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
* Alarm (RTCALF) */
#define LPC17_IRQ_EINT0 (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
#define LPC17_IRQ_EINT1 (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
#define LPC17_IRQ_EINT2 (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
#define LPC17_IRQ_EINT3 (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
* Note: EINT3 channel is shared with GPIO interrupts */
#define LPC17_IRQ_ADC (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
#define LPC17_IRQ_BOD (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */
#define LPC17_IRQ_USB (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
* USB_INT_REQ_DMA */
#define LPC17_IRQ_CAN (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
* CAN 1 Tx, CAN 1 Rx */
#define LPC17_IRQ_GPDMA (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
* IntStatus of DMA channel 1 */
#define LPC17_IRQ_I2S (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
#define LPC17_IRQ_ETH (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
* TxFinishedInt, TxErrorInt,* TxUnderrunInt,
* RxDoneInt, RxFinishedInt, RxErrorInt,
* RxOverrunInt */
#define LPC17_IRQ_RITINT (LPC17_IRQ_EXTINT+29) /* Repetitive Interrupt Timer (RITINT) */
#define LPC17_IRQ_MCPWM (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
* ICAP[2:0], FES */
#define LPC17_IRQ_QEI (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
* DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
* POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
* POS2REV_Int */
#define LPC17_IRQ_PLL1 (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
#define LPC17_IRQ_USBACT (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
#define LPC17_IRQ_CANACT (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
#define LPC17_IRQ_NEXTINT (35)
#define LPC17_IRQ_NIRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
/* GPIO interrupts. The LPC17xx supports several interrupts on ports 0 and
* 2 (only). We go through some special efforts to keep the number of IRQs
* to a minimum in this sparse interrupt case.
*
* 28 interrupts on Port 0: p0.0 - p0.11, p0.15-p0.30
* 14 interrupts on Port 2: p2.0 - p2.13
* --
* 42
*/
#ifdef CONFIG_LPC17_GPIOIRQ
# define LPC17_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrupt set */
# define LPC17_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */
/* Set 1: 12 interrupts p0.0-p0.11 */
# define LPC17_VALID_GPIOINT0L (0x00000ffful)
# define LPC17_VALID_SHIFT0L (0)
# define LPC17_VALID_FIRST0L (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
# define LPC17_IRQ_P0p0 (LPC17_VALID_FIRST0L+0)
# define LPC17_IRQ_P0p1 (LPC17_VALID_FIRST0L+1)
# define LPC17_IRQ_P0p2 (LPC17_VALID_FIRST0L+2)
# define LPC17_IRQ_P0p3 (LPC17_VALID_FIRST0L+3)
# define LPC17_IRQ_P0p4 (LPC17_VALID_FIRST0L+4)
# define LPC17_IRQ_P0p5 (LPC17_VALID_FIRST0L+5)
# define LPC17_IRQ_P0p6 (LPC17_VALID_FIRST0L+6)
# define LPC17_IRQ_P0p7 (LPC17_VALID_FIRST0L+7)
# define LPC17_IRQ_P0p8 (LPC17_VALID_FIRST0L+8)
# define LPC17_IRQ_P0p9 (LPC17_VALID_FIRST0L+9)
# define LPC17_IRQ_P0p10 (LPC17_VALID_FIRST0L+10)
# define LPC17_IRQ_P0p11 (LPC17_VALID_FIRST0L+11)
# define LPC17_VALID_NIRQS0L (12)
/* Set 2: 16 interrupts p0.15-p0.30 */
# define LPC17_VALID_GPIOINT0H (0x7fff8000ull)
# define LPC17_VALID_SHIFT0H (15)
# define LPC17_VALID_FIRST0H (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L)
# define LPC17_IRQ_P0p15 (LPC17_VALID_FIRST0H+0)
# define LPC17_IRQ_P0p16 (LPC17_VALID_FIRST0H+1)
# define LPC17_IRQ_P0p17 (LPC17_VALID_FIRST0H+2)
# define LPC17_IRQ_P0p18 (LPC17_VALID_FIRST0H+3)
# define LPC17_IRQ_P0p19 (LPC17_VALID_FIRST0H+4)
# define LPC17_IRQ_P0p20 (LPC17_VALID_FIRST0H+5)
# define LPC17_IRQ_P0p21 (LPC17_VALID_FIRST0H+6)
# define LPC17_IRQ_P0p22 (LPC17_VALID_FIRST0H+7)
# define LPC17_IRQ_P0p23 (LPC17_VALID_FIRST0H+8)
# define LPC17_IRQ_P0p24 (LPC17_VALID_FIRST0H+9)
# define LPC17_IRQ_P0p25 (LPC17_VALID_FIRST0H+10)
# define LPC17_IRQ_P0p26 (LPC17_VALID_FIRST0H+11)
# define LPC17_IRQ_P0p27 (LPC17_VALID_FIRST0H+12)
# define LPC17_IRQ_P0p28 (LPC17_VALID_FIRST0H+13)
# define LPC17_IRQ_P0p29 (LPC17_VALID_FIRST0H+14)
# define LPC17_IRQ_P0p30 (LPC17_VALID_FIRST0H+15)
# define LPC17_VALID_NIRQS0H (16)
/* Set 3: 14 interrupts p2.0-p2.13 */
# define LPC17_VALID_GPIOINT2 (0x00003ffful)
# define LPC17_VALID_SHIFT2 (0)
# define LPC17_VALID_FIRST2 (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H)
# define LPC17_IRQ_P2p0 (LPC17_VALID_FIRST2+0)
# define LPC17_IRQ_P2p1 (LPC17_VALID_FIRST2+1)
# define LPC17_IRQ_P2p2 (LPC17_VALID_FIRST2+2)
# define LPC17_IRQ_P2p3 (LPC17_VALID_FIRST2+3)
# define LPC17_IRQ_P2p4 (LPC17_VALID_FIRST2+4)
# define LPC17_IRQ_P2p5 (LPC17_VALID_FIRST2+5)
# define LPC17_IRQ_P2p6 (LPC17_VALID_FIRST2+6)
# define LPC17_IRQ_P2p7 (LPC17_VALID_FIRST2+7)
# define LPC17_IRQ_P2p8 (LPC17_VALID_FIRST2+8)
# define LPC17_IRQ_P2p9 (LPC17_VALID_FIRST2+9)
# define LPC17_IRQ_P2p10 (LPC17_VALID_FIRST2+10)
# define LPC17_IRQ_P2p11 (LPC17_VALID_FIRST2+11)
# define LPC17_IRQ_P2p12 (LPC17_VALID_FIRST2+12)
# define LPC17_IRQ_P2p13 (LPC17_VALID_FIRST2+13)
# define LPC17_VALID_NIRQS2 (14)
# define LPC17_NGPIOAIRQS (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2)
#else
# define LPC17_NGPIOAIRQS (0)
#endif
/* Total number of IRQ numbers */
#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H */
arch/arm/include/lpc17xx/lpc178x_irq.h
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/****************************************************************************
* arch/arm/include/lpc17xxx/lpc178x_irq.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Authors: Rommel Marcelo
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*/
/* External interrupts (vectors >= 16) */
#define LPC17_IRQ_WDT (LPC17_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */
#define LPC17_IRQ_TMR0 (LPC17_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_IRQ_TMR1 (LPC17_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_IRQ_TMR2 (LPC17_IRQ_EXTINT+3) /* Timer 2 Match 0-3
* Capture 0-1 */
#define LPC17_IRQ_TMR3 (LPC17_IRQ_EXTINT+4) /* Timer 3 Match 0-3
* Capture 0-1 */
#define LPC17_IRQ_UART0 (LPC17_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART1 (LPC17_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* Modem Control Change
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART2 (LPC17_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART3 (LPC17_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_PWM1 (LPC17_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1
* Capture 0-1 of PWM1 */
#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */
#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */
#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */
#define LPC17_IRQ_RESERVED29 (LPC17_IRQ_EXTINT+13) /* Unused */
#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
* Rx FIFO half full of SSP0
* Rx Timeout of SSP0
* Rx Overrun of SSP0 */
#define LPC17_IRQ_SSP1 (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
* Rx FIFO half full
* Rx Timeout
* Rx Overrun */
#define LPC17_IRQ_PLL0 (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
#define LPC17_IRQ_RTC (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
* Alarm (RTCALF) */
#define LPC17_IRQ_EINT0 (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
#define LPC17_IRQ_EINT1 (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
#define LPC17_IRQ_EINT2 (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
#define LPC17_IRQ_EINT3 (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
* Note: EINT3 channel is shared with GPIO interrupts */
#define LPC17_IRQ_ADC (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
#define LPC17_IRQ_BOD (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */
#define LPC17_IRQ_USB (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
* USB_INT_REQ_DMA */
#define LPC17_IRQ_CAN (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
* CAN 1 Tx, CAN 1 Rx */
#define LPC17_IRQ_GPDMA (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
* IntStatus of DMA channel 1 */
#define LPC17_IRQ_I2S (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
#define LPC17_IRQ_ETH (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
* TxFinishedInt, TxErrorInt,* TxUnderrunInt,
* RxDoneInt, RxFinishedInt, RxErrorInt,
* RxOverrunInt */
#define LPC17_IRQ_MCI (LPC17_IRQ_EXTINT+29) /* MCI SD Card Interface */
#define LPC17_IRQ_MCPWM (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
* ICAP[2:0], FES */
#define LPC17_IRQ_QEI (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
* DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
* POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
* POS2REV_Int */
#define LPC17_IRQ_PLL1 (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
#define LPC17_IRQ_USBACT (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
#define LPC17_IRQ_CANACT (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
#define LPC17_IRQ_UART4 (LPC17_IRQ_EXTINT+35) /* UART 4 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_SSP2 (LPC17_IRQ_EXTINT+36) /* SSP2 Tx FIFO half empty of SSP2
* Rx FIFO half full of SSP2
* Rx Timeout of SSP2
* Rx Overrun of SSP2 */
#define LPC17_IRQ_LCD (LPC17_IRQ_EXTINT+37) /* LCD interrupt
* BER, VCompI, LNBUI, FUFI, CrsrI */
#define LPC17_IRQ_GPIO (LPC17_IRQ_EXTINT+38) /* GPIO Interrupt
* P0xREI, P2xREI, P0xFEI, P2xFEI */
#define LPC17_IRQ_PWM0 (LPC17_IRQ_EXTINT+39) /* PWM0 Match 0 - 6 of PWM0
* Capture 0-1 of PWM0 */
#define LPC17_IRQ_EEPROM (LPC17_IRQ_EXTINT+40) /* EEPROM Interrupt
* EE_PROG_DONE, EE_RW_DONE */
#define LPC17_IRQ_NEXTINT (41)
#define LPC17_IRQ_NIRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
/* GPIO interrupts. The LPC177x_8x supports several interrupts on ports 0 and
* 2 (only). We go through some special efforts to keep the number of IRQs
* to a minimum in this sparse interrupt case.
*
* 31 interrupts on Port 0: p0.0 - p0.30
* 31 interrupts on Port 2: p2.0 - p2.30
* --
* 42
*/
#ifdef CONFIG_LPC17_GPIOIRQ
# define LPC17_VALID_GPIOINT0 (0xfffffffful) /* GPIO port 0 interrupt set */
# define LPC17_VALID_GPIOINT2 (0xfffffffful) /* GPIO port 2 interrupt set */
/* Set 1: 16 interrupts p0.0-p0.15 */
# define LPC17_VALID_SHIFT0L (0)
# define LPC17_VALID_FIRST0L (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
# define LPC17_IRQ_P0p0 (LPC17_VALID_FIRST0L+0)
# define LPC17_IRQ_P0p1 (LPC17_VALID_FIRST0L+1)
# define LPC17_IRQ_P0p2 (LPC17_VALID_FIRST0L+2)
# define LPC17_IRQ_P0p3 (LPC17_VALID_FIRST0L+3)
# define LPC17_IRQ_P0p4 (LPC17_VALID_FIRST0L+4)
# define LPC17_IRQ_P0p5 (LPC17_VALID_FIRST0L+5)
# define LPC17_IRQ_P0p6 (LPC17_VALID_FIRST0L+6)
# define LPC17_IRQ_P0p7 (LPC17_VALID_FIRST0L+7)
# define LPC17_IRQ_P0p8 (LPC17_VALID_FIRST0L+8)
# define LPC17_IRQ_P0p9 (LPC17_VALID_FIRST0L+9)
# define LPC17_IRQ_P0p10 (LPC17_VALID_FIRST0L+10)
# define LPC17_IRQ_P0p11 (LPC17_VALID_FIRST0L+11)
# define LPC17_IRQ_P0p12 (LPC17_VALID_FIRST0L+12)
# define LPC17_IRQ_P0p13 (LPC17_VALID_FIRST0L+13)
# define LPC17_IRQ_P0p14 (LPC17_VALID_FIRST0L+14)
# define LPC17_IRQ_P0p15 (LPC17_VALID_FIRST0L+15)
# define LPC17_VALID_NIRQS0L (16)
/* Set 2: 16 interrupts p0.16-p0.31 */
# define LPC17_VALID_SHIFT0H (16)
# define LPC17_VALID_FIRST0H (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L)
# define LPC17_IRQ_P0p16 (LPC17_VALID_FIRST0H+0)
# define LPC17_IRQ_P0p17 (LPC17_VALID_FIRST0H+1)
# define LPC17_IRQ_P0p18 (LPC17_VALID_FIRST0H+2)
# define LPC17_IRQ_P0p19 (LPC17_VALID_FIRST0H+3)
# define LPC17_IRQ_P0p20 (LPC17_VALID_FIRST0H+4)
# define LPC17_IRQ_P0p21 (LPC17_VALID_FIRST0H+5)
# define LPC17_IRQ_P0p22 (LPC17_VALID_FIRST0H+6)
# define LPC17_IRQ_P0p23 (LPC17_VALID_FIRST0H+7)
# define LPC17_IRQ_P0p24 (LPC17_VALID_FIRST0H+8)
# define LPC17_IRQ_P0p25 (LPC17_VALID_FIRST0H+9)
# define LPC17_IRQ_P0p26 (LPC17_VALID_FIRST0H+10)
# define LPC17_IRQ_P0p27 (LPC17_VALID_FIRST0H+11)
# define LPC17_IRQ_P0p28 (LPC17_VALID_FIRST0H+12)
# define LPC17_IRQ_P0p29 (LPC17_VALID_FIRST0H+13)
# define LPC17_IRQ_P0p30 (LPC17_VALID_FIRST0H+14)
# define LPC17_IRQ_P0p31 (LPC17_VALID_FIRST0H+15)
# define LPC17_VALID_NIRQS0H (16)
/* Set 3: 16 interrupts p2.0-p2.15 */
# define LPC17_VALID_SHIFT2L (0)
# define LPC17_VALID_FIRST2L (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H)
# define LPC17_IRQ_P2p0 (LPC17_VALID_FIRST2L+0)
# define LPC17_IRQ_P2p1 (LPC17_VALID_FIRST2L+1)
# define LPC17_IRQ_P2p2 (LPC17_VALID_FIRST2L+2)
# define LPC17_IRQ_P2p3 (LPC17_VALID_FIRST2L+3)
# define LPC17_IRQ_P2p4 (LPC17_VALID_FIRST2L+4)
# define LPC17_IRQ_P2p5 (LPC17_VALID_FIRST2L+5)
# define LPC17_IRQ_P2p6 (LPC17_VALID_FIRST2L+6)
# define LPC17_IRQ_P2p7 (LPC17_VALID_FIRST2L+7)
# define LPC17_IRQ_P2p8 (LPC17_VALID_FIRST2L+8)
# define LPC17_IRQ_P2p9 (LPC17_VALID_FIRST2L+9)
# define LPC17_IRQ_P2p10 (LPC17_VALID_FIRST2L+10)
# define LPC17_IRQ_P2p11 (LPC17_VALID_FIRST2L+11)
# define LPC17_IRQ_P2p12 (LPC17_VALID_FIRST2L+12)
# define LPC17_IRQ_P2p13 (LPC17_VALID_FIRST2L+13)
# define LPC17_IRQ_P2p14 (LPC17_VALID_FIRST2L+14)
# define LPC17_IRQ_P2p15 (LPC17_VALID_FIRST2L+15)
# define LPC17_VALID_NIRQS2L (16)
/* Set 4: 16 interrupts p2.16 - p2.31 */
# define LPC17_VALID_SHIFT2H (16)
# define LPC17_VALID_FIRST2H (LPC17_VALID_FIRST2L+LPC17_VALID_NIRQS2L)
# define LPC17_IRQ_P2p16 (LPC17_VALID_FIRST2H+0)
# define LPC17_IRQ_P2p17 (LPC17_VALID_FIRST2H+1)
# define LPC17_IRQ_P2p18 (LPC17_VALID_FIRST2H+2)
# define LPC17_IRQ_P2p19 (LPC17_VALID_FIRST2H+3)
# define LPC17_IRQ_P2p20 (LPC17_VALID_FIRST2H+4)
# define LPC17_IRQ_P2p21 (LPC17_VALID_FIRST2H+5)
# define LPC17_IRQ_P2p22 (LPC17_VALID_FIRST2H+6)
# define LPC17_IRQ_P2p23 (LPC17_VALID_FIRST2H+7)
# define LPC17_IRQ_P2p24 (LPC17_VALID_FIRST2H+8)
# define LPC17_IRQ_P2p25 (LPC17_VALID_FIRST2H+9)
# define LPC17_IRQ_P2p26 (LPC17_VALID_FIRST2H+10)
# define LPC17_IRQ_P2p27 (LPC17_VALID_FIRST2H+11)
# define LPC17_IRQ_P2p28 (LPC17_VALID_FIRST2H+12)
# define LPC17_IRQ_P2p29 (LPC17_VALID_FIRST2H+13)
# define LPC17_IRQ_P2p30 (LPC17_VALID_FIRST2H+14)
# define LPC17_IRQ_P2p31 (LPC17_VALID_FIRST2H+15)
# define LPC17_VALID_NIRQS2H (16)
# define LPC17_NGPIOAIRQS (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2L+LPC17_VALID_NIRQS2H)
#else
# define LPC17_NGPIOAIRQS (0)
#endif
/* Total number of IRQ numbers */
#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H */
arch/arm/include/lpc17xx_40xx/chip.h
+468
View File
@@ -0,0 +1,468 @@
/************************************************************************************
* arch/arm/include/lpc17xx_40xx/chip.h
*
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* with LPC178x support from Rommel Marcelo
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_40XX_CHIP_H
#define __ARCH_ARM_INCLUDE_LPC17XX_40XX_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Get customizations for each supported chip */
#if defined(CONFIG_ARCH_CHIP_LPC1751)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (32*1024) /* 32Kb */
# define LPC17_40_SRAM_SIZE (8*1024) /* 8Kb */
# define LPC17_40_CPUSRAM_SIZE (8*1024)
# undef LPC17_40_HAVE_BANK0 /* No AHB SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_40_NUSBHOST 0 /* No USB host controller */
# define LPC17_40_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 1 /* One CAN controller */
# define LPC17_40_NI2S 0 /* No I2S modules */
# define LPC17_40_NDAC 0 /* No DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1752)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (64*1024) /* 65Kb */
# define LPC17_40_SRAM_SIZE (16*1024) /* 16Kb */
# define LPC17_40_CPUSRAM_SIZE (16*1024)
# undef LPC17_40_HAVE_BANK0 /* No AHB SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_40_NUSBHOST 0 /* No USB host controller */
# define LPC17_40_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 1 /* One CAN controller */
# define LPC17_40_NI2S 0 /* No I2S modules */
# define LPC17_40_NDAC 0 /* No DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1754)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_40_SRAM_SIZE (32*1024) /* 32Kb */
# define LPC17_40_CPUSRAM_SIZE (16*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 1 /* One CAN controller */
# define LPC17_40_NI2S 0 /* No I2S modules */
# define LPC17_40_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1756)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_40_SRAM_SIZE (32*1024) /* 32Kb */
# define LPC17_40_CPUSRAM_SIZE (16*1024)
# define LPC17_40_HAVE_BANK0 1 /* No AHB SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 2 /* Two CAN controllers */
# define LPC17_40_NI2S 1 /* One I2S module */
# define LPC17_40_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1758)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_40_CPUSRAM_SIZE (32*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 2 /* Two CAN controllers */
# define LPC17_40_NI2S 1 /* One I2S module */
# define LPC17_40_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1759)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_40_CPUSRAM_SIZE (32*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 2 /* Two CAN controllers */
# define LPC17_40_NI2S 1 /* One I2S module */
# define LPC17_40_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1764)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_40_SRAM_SIZE (32*1024) /* 32Kb */
# define LPC17_40_CPUSRAM_SIZE (16*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 0 /* No USB host controller */
# define LPC17_40_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 2 /* Two CAN controllers */
# define LPC17_40_NI2S 0 /* No I2S modules */
# define LPC17_40_NDAC 0 /* No DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1765)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_40_CPUSRAM_SIZE (32*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 2 /* Two CAN controllers */
# define LPC17_40_NI2S 1 /* One I2S module */
# define LPC17_40_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1766)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_40_CPUSRAM_SIZE (32*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 2 /* Two CAN controllers */
# define LPC17_40_NI2S 1 /* One I2S module */
# define LPC17_40_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1767)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_40_CPUSRAM_SIZE (32*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 0 /* No USB host controller */
# define LPC17_40_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_40_NUSBDEV 0 /* No USB device controller */
# define LPC17_40_NCAN 0 /* No CAN controllers */
# define LPC17_40_NI2S 1 /* One I2S module */
# define LPC17_40_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_40_CPUSRAM_SIZE (32*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 2 /* Two CAN controllers */
# define LPC17_40_NI2S 1 /* One I2S module */
# define LPC17_40_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1773)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_40_SRAM_SIZE (40*1024) /* 40Kb */
# define LPC17_40_CPUSRAM_SIZE (32*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* No Peripheral SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LPC17_40_NUSBHOST /* No USB host controller */
# undef LPC17_40_NUSBOTG /* No USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */
# undef LPC17_40_HAVE_LCD /* No LCD controller */
# undef LPC17_40_HAVE_QEI /* No QEI interface */
# undef LPC17_40_HAVE_SD /* No SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1774)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_40_SRAM_SIZE (40*1024) /* 40Kb */
# define LPC17_40_CPUSRAM_SIZE (32*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0*/
# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LPC17_40_NUSBHOST /* One USB host controller */
# undef LPC17_40_NUSBOTG /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_40_HAVE_LCD /* No LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1776)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_40_SRAM_SIZE (80*1024) /* 80Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_40_HAVE_LCD /* No LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1777)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (96*1024) /* 96Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# undef LPC17_40_NETHCONTROLLERS /* No Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_40_HAVE_LCD /* No LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1778)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (96*1024) /* 64Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_40_HAVE_LCD /* No LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1785)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_40_SRAM_SIZE (80*1024) /* 80Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# undef LPC17_40_NETHCONTROLLERS /* No Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_40_HAVE_LCD 1 /* One LCD controller */
# undef LPC17_40_HAVE_QEI /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1786)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_40_SRAM_SIZE (80*1024) /* 80Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_40_HAVE_LCD 1 /* One LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1787)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (96*1024) /* 96Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# undef LPC17_40_NETHCONTROLLERS /* No Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_40_HAVE_LCD 1 /* One LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1788)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (96*1024) /* 96Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_40_HAVE_LCD 1 /* One LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC4072)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (64*1024) /* 64Kb */
# define LPC17_40_SRAM_SIZE (24*1024) /* 24Kb */
# define LPC17_40_CPUSRAM_SIZE (16*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* No Peripheral SRAM bank 1 */
# undef LPC17_40_NETHCONTROLLERS /* No Ethernet controller */
# undef LPC17_40_NUSBHOST /* No USB host controller */
# undef LPC17_40_NUSBOTG /* No USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */
# undef LPC17_40_HAVE_LCD /* No LCD controller */
# undef LPC17_40_HAVE_QEI /* No QEI interface */
# undef LPC17_40_HAVE_SD /* No SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC4074)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_40_SRAM_SIZE (40*1024) /* 40Kb */
# define LPC17_40_CPUSRAM_SIZE (32*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0*/
# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# undef LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
# undef LPC17_40_NUSBHOST /* No USB host controller */
# undef LPC17_40_NUSBOTG /* No USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */
# undef LPC17_40_HAVE_LCD /* One LCD controller */
# undef LPC17_40_HAVE_QEI /* No QEI interface */
# undef LPC17_40_HAVE_SD /* No SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC4076)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_40_SRAM_SIZE (80*1024) /* 80Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */
# undef LPC17_40_HAVE_LCD /* No LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC4078)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (96*1024) /* 96Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */
# undef LPC17_40_HAVE_LCD /* No LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC4088)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (96*1024) /* 64Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */
# define LPC17_40_HAVE_LCD 1 /* One LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#else
# error "Unsupported LPC17xx/LPC40xx chip"
#endif
/* NVIC priority levels *************************************************************/
/* Each priority field holds a priority value, 0-31. The lower the value, the greater
* the priority of the corresponding interrupt. The processor implements only
* bits[7:3] of each field, bits[2:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x08 /* Five bits of interrupt priority used */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_40XX_CHIP_H */
arch/arm/include/lpc17xx/irq.h → arch/arm/include/lpc17xx_40xx/irq.h
+23 -23
View File
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/include/lpc17xxx/irq.h
* arch/arm/include/lpc17xx_40xxx/irq.h
*
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -37,8 +37,8 @@
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_40XX_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC17XX_40XX_IRQ_H
/****************************************************************************
* Included Files
@@ -47,7 +47,7 @@
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
#include <arch/lpc17xx/chip.h>
#include <arch/lpc17xx_40xx/chip.h>
/****************************************************************************
* Pre-processor Definitions
@@ -59,32 +59,32 @@
/* Common Processor Exceptions (vectors 0-15) */
#define LPC17_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define LPC17_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define LPC17_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define LPC17_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define LPC17_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define LPC17_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define LPC17_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define LPC17_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define LPC17_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define LPC17_IRQ_SYSTICK (15) /* Vector 15: System tick */
#define LPC17_40_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define LPC17_40_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define LPC17_40_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define LPC17_40_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define LPC17_40_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define LPC17_40_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define LPC17_40_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define LPC17_40_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define LPC17_40_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define LPC17_40_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16) */
#define LPC17_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
#define LPC17_40_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
/* Family Specfic Interrupts */
#if defined(LPC176x) /* LPC175/6 family */
# include <arch/lpc17xx/lpc176x_irq.h>
#elif defined(LPC178x) /* LPC177/8 family */
# include <arch/lpc17xx/lpc178x_irq.h>
# include <arch/lpc17xx_40xx/lpc176x_irq.h>
#elif defined(LPC178x_40xx) /* LPC177/8 or LPC40xx family */
# include <arch/lpc17xx_40xx/lpc178x_40xx_irq.h>
#else
# error "Unknown LPC17xx family"
# error "Unknown LPC17xx/LPC40xx family"
#endif
/****************************************************************************
@@ -116,4 +116,4 @@ extern "C"
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_40XX_IRQ_H */
arch/arm/include/lpc17xx_40xx/lpc176x_irq.h
+245
View File
@@ -0,0 +1,245 @@
/****************************************************************************
* arch/lpc17xx_40xx/lpc176x_irq.h
*
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC176X_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC176X_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*/
/* External interrupts (vectors >= 16) */
#define LPC17_40_IRQ_WDT (LPC17_40_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */
#define LPC17_40_IRQ_TMR0 (LPC17_40_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_40_IRQ_TMR1 (LPC17_40_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_40_IRQ_TMR2 (LPC17_40_IRQ_EXTINT+3) /* Timer 2 Match 0-3
* Capture 0-1 */
#define LPC17_40_IRQ_TMR3 (LPC17_40_IRQ_EXTINT+4) /* Timer 3 Match 0-3
* Capture 0-1 */
#define LPC17_40_IRQ_UART0 (LPC17_40_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_40_IRQ_UART1 (LPC17_40_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* Modem Control Change
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_40_IRQ_UART2 (LPC17_40_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_40_IRQ_UART3 (LPC17_40_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_40_IRQ_PWM1 (LPC17_40_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1
* Capture 0-1 of PWM1 */
#define LPC17_40_IRQ_I2C0 (LPC17_40_IRQ_EXTINT+10) /* I2C0 SI (state change) */
#define LPC17_40_IRQ_I2C1 (LPC17_40_IRQ_EXTINT+11) /* I2C1 SI (state change) */
#define LPC17_40_IRQ_I2C2 (LPC17_40_IRQ_EXTINT+12) /* I2C2 SI (state change) */
#define LPC17_40_IRQ_SPIF (LPC17_40_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF)
* Mode Fault (MODF) */
#define LPC17_40_IRQ_SSP0 (LPC17_40_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
* Rx FIFO half full of SSP0
* Rx Timeout of SSP0
* Rx Overrun of SSP0 */
#define LPC17_40_IRQ_SSP1 (LPC17_40_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
* Rx FIFO half full
* Rx Timeout
* Rx Overrun */
#define LPC17_40_IRQ_PLL0 (LPC17_40_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
#define LPC17_40_IRQ_RTC (LPC17_40_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
* Alarm (RTCALF) */
#define LPC17_40_IRQ_EINT0 (LPC17_40_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
#define LPC17_40_IRQ_EINT1 (LPC17_40_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
#define LPC17_40_IRQ_EINT2 (LPC17_40_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
#define LPC17_40_IRQ_EINT3 (LPC17_40_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
* Note: EINT3 channel is shared with GPIO interrupts */
#define LPC17_40_IRQ_ADC (LPC17_40_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
#define LPC17_40_IRQ_BOD (LPC17_40_IRQ_EXTINT+23) /* BOD Brown Out detect */
#define LPC17_40_IRQ_USB (LPC17_40_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
* USB_INT_REQ_DMA */
#define LPC17_40_IRQ_CAN (LPC17_40_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
* CAN 1 Tx, CAN 1 Rx */
#define LPC17_40_IRQ_GPDMA (LPC17_40_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
* IntStatus of DMA channel 1 */
#define LPC17_40_IRQ_I2S (LPC17_40_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
#define LPC17_40_IRQ_ETH (LPC17_40_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
* TxFinishedInt, TxErrorInt,* TxUnderrunInt,
* RxDoneInt, RxFinishedInt, RxErrorInt,
* RxOverrunInt */
#define LPC17_40_IRQ_RITINT (LPC17_40_IRQ_EXTINT+29) /* Repetitive Interrupt Timer (RITINT) */
#define LPC17_40_IRQ_MCPWM (LPC17_40_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
* ICAP[2:0], FES */
#define LPC17_40_IRQ_QEI (LPC17_40_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
* DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
* POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
* POS2REV_Int */
#define LPC17_40_IRQ_PLL1 (LPC17_40_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
#define LPC17_40_IRQ_USBACT (LPC17_40_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
#define LPC17_40_IRQ_CANACT (LPC17_40_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
#define LPC17_40_IRQ_NEXTINT (35)
#define LPC17_40_IRQ_NIRQS (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT)
/* GPIO interrupts. The LPC17xx/LPC40xx supports several interrupts on ports 0 and
* 2 (only). We go through some special efforts to keep the number of IRQs
* to a minimum in this sparse interrupt case.
*
* 28 interrupts on Port 0: p0.0 - p0.11, p0.15-p0.30
* 14 interrupts on Port 2: p2.0 - p2.13
* --
* 42
*/
#ifdef CONFIG_LPC17_40_GPIOIRQ
# define LPC17_40_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrupt set */
# define LPC17_40_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */
/* Set 1: 12 interrupts p0.0-p0.11 */
# define LPC17_40_VALID_GPIOINT0L (0x00000ffful)
# define LPC17_40_VALID_SHIFT0L (0)
# define LPC17_40_VALID_FIRST0L (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT)
# define LPC17_40_IRQ_P0p0 (LPC17_40_VALID_FIRST0L+0)
# define LPC17_40_IRQ_P0p1 (LPC17_40_VALID_FIRST0L+1)
# define LPC17_40_IRQ_P0p2 (LPC17_40_VALID_FIRST0L+2)
# define LPC17_40_IRQ_P0p3 (LPC17_40_VALID_FIRST0L+3)
# define LPC17_40_IRQ_P0p4 (LPC17_40_VALID_FIRST0L+4)
# define LPC17_40_IRQ_P0p5 (LPC17_40_VALID_FIRST0L+5)
# define LPC17_40_IRQ_P0p6 (LPC17_40_VALID_FIRST0L+6)
# define LPC17_40_IRQ_P0p7 (LPC17_40_VALID_FIRST0L+7)
# define LPC17_40_IRQ_P0p8 (LPC17_40_VALID_FIRST0L+8)
# define LPC17_40_IRQ_P0p9 (LPC17_40_VALID_FIRST0L+9)
# define LPC17_40_IRQ_P0p10 (LPC17_40_VALID_FIRST0L+10)
# define LPC17_40_IRQ_P0p11 (LPC17_40_VALID_FIRST0L+11)
# define LPC17_40_VALID_NIRQS0L (12)
/* Set 2: 16 interrupts p0.15-p0.30 */
# define LPC17_40_VALID_GPIOINT0H (0x7fff8000ull)
# define LPC17_40_VALID_SHIFT0H (15)
# define LPC17_40_VALID_FIRST0H (LPC17_40_VALID_FIRST0L+LPC17_40_VALID_NIRQS0L)
# define LPC17_40_IRQ_P0p15 (LPC17_40_VALID_FIRST0H+0)
# define LPC17_40_IRQ_P0p16 (LPC17_40_VALID_FIRST0H+1)
# define LPC17_40_IRQ_P0p17 (LPC17_40_VALID_FIRST0H+2)
# define LPC17_40_IRQ_P0p18 (LPC17_40_VALID_FIRST0H+3)
# define LPC17_40_IRQ_P0p19 (LPC17_40_VALID_FIRST0H+4)
# define LPC17_40_IRQ_P0p20 (LPC17_40_VALID_FIRST0H+5)
# define LPC17_40_IRQ_P0p21 (LPC17_40_VALID_FIRST0H+6)
# define LPC17_40_IRQ_P0p22 (LPC17_40_VALID_FIRST0H+7)
# define LPC17_40_IRQ_P0p23 (LPC17_40_VALID_FIRST0H+8)
# define LPC17_40_IRQ_P0p24 (LPC17_40_VALID_FIRST0H+9)
# define LPC17_40_IRQ_P0p25 (LPC17_40_VALID_FIRST0H+10)
# define LPC17_40_IRQ_P0p26 (LPC17_40_VALID_FIRST0H+11)
# define LPC17_40_IRQ_P0p27 (LPC17_40_VALID_FIRST0H+12)
# define LPC17_40_IRQ_P0p28 (LPC17_40_VALID_FIRST0H+13)
# define LPC17_40_IRQ_P0p29 (LPC17_40_VALID_FIRST0H+14)
# define LPC17_40_IRQ_P0p30 (LPC17_40_VALID_FIRST0H+15)
# define LPC17_40_VALID_NIRQS0H (16)
/* Set 3: 14 interrupts p2.0-p2.13 */
# define LPC17_40_VALID_GPIOINT2 (0x00003ffful)
# define LPC17_40_VALID_SHIFT2 (0)
# define LPC17_40_VALID_FIRST2 (LPC17_40_VALID_FIRST0H+LPC17_40_VALID_NIRQS0H)
# define LPC17_40_IRQ_P2p0 (LPC17_40_VALID_FIRST2+0)
# define LPC17_40_IRQ_P2p1 (LPC17_40_VALID_FIRST2+1)
# define LPC17_40_IRQ_P2p2 (LPC17_40_VALID_FIRST2+2)
# define LPC17_40_IRQ_P2p3 (LPC17_40_VALID_FIRST2+3)
# define LPC17_40_IRQ_P2p4 (LPC17_40_VALID_FIRST2+4)
# define LPC17_40_IRQ_P2p5 (LPC17_40_VALID_FIRST2+5)
# define LPC17_40_IRQ_P2p6 (LPC17_40_VALID_FIRST2+6)
# define LPC17_40_IRQ_P2p7 (LPC17_40_VALID_FIRST2+7)
# define LPC17_40_IRQ_P2p8 (LPC17_40_VALID_FIRST2+8)
# define LPC17_40_IRQ_P2p9 (LPC17_40_VALID_FIRST2+9)
# define LPC17_40_IRQ_P2p10 (LPC17_40_VALID_FIRST2+10)
# define LPC17_40_IRQ_P2p11 (LPC17_40_VALID_FIRST2+11)
# define LPC17_40_IRQ_P2p12 (LPC17_40_VALID_FIRST2+12)
# define LPC17_40_IRQ_P2p13 (LPC17_40_VALID_FIRST2+13)
# define LPC17_40_VALID_NIRQS2 (14)
# define LPC17_40_NGPIOAIRQS (LPC17_40_VALID_NIRQS0L+LPC17_40_VALID_NIRQS0H+LPC17_40_VALID_NIRQS2)
#else
# define LPC17_40_NGPIOAIRQS (0)
#endif
/* Total number of IRQ numbers */
#define NR_IRQS (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT+LPC17_40_NGPIOAIRQS)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC176X_IRQ_H */
arch/arm/include/lpc17xx_40xx/lpc178x_40xx_irq.h
+291
View File
@@ -0,0 +1,291 @@
/****************************************************************************
* arch/arm/include/lpc17xx_40xxx/lpc178x_40xx_irq.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Authors: Rommel Marcelo
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC178X_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC178X_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*/
/* External interrupts (vectors >= 16) */
#define LPC17_40_IRQ_WDT (LPC17_40_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */
#define LPC17_40_IRQ_TMR0 (LPC17_40_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_40_IRQ_TMR1 (LPC17_40_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_40_IRQ_TMR2 (LPC17_40_IRQ_EXTINT+3) /* Timer 2 Match 0-3
* Capture 0-1 */
#define LPC17_40_IRQ_TMR3 (LPC17_40_IRQ_EXTINT+4) /* Timer 3 Match 0-3
* Capture 0-1 */
#define LPC17_40_IRQ_UART0 (LPC17_40_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_40_IRQ_UART1 (LPC17_40_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* Modem Control Change
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_40_IRQ_UART2 (LPC17_40_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_40_IRQ_UART3 (LPC17_40_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_40_IRQ_PWM1 (LPC17_40_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1
* Capture 0-1 of PWM1 */
#define LPC17_40_IRQ_I2C0 (LPC17_40_IRQ_EXTINT+10) /* I2C0 SI (state change) */
#define LPC17_40_IRQ_I2C1 (LPC17_40_IRQ_EXTINT+11) /* I2C1 SI (state change) */
#define LPC17_40_IRQ_I2C2 (LPC17_40_IRQ_EXTINT+12) /* I2C2 SI (state change) */
#define LPC17_40_IRQ_RESERVED29 (LPC17_40_IRQ_EXTINT+13) /* Unused */
#define LPC17_40_IRQ_SSP0 (LPC17_40_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
* Rx FIFO half full of SSP0
* Rx Timeout of SSP0
* Rx Overrun of SSP0 */
#define LPC17_40_IRQ_SSP1 (LPC17_40_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
* Rx FIFO half full
* Rx Timeout
* Rx Overrun */
#define LPC17_40_IRQ_PLL0 (LPC17_40_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
#define LPC17_40_IRQ_RTC (LPC17_40_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
* Alarm (RTCALF) */
#define LPC17_40_IRQ_EINT0 (LPC17_40_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
#define LPC17_40_IRQ_EINT1 (LPC17_40_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
#define LPC17_40_IRQ_EINT2 (LPC17_40_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
#define LPC17_40_IRQ_EINT3 (LPC17_40_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
* Note: EINT3 channel is shared with GPIO interrupts */
#define LPC17_40_IRQ_ADC (LPC17_40_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
#define LPC17_40_IRQ_BOD (LPC17_40_IRQ_EXTINT+23) /* BOD Brown Out detect */
#define LPC17_40_IRQ_USB (LPC17_40_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
* USB_INT_REQ_DMA */
#define LPC17_40_IRQ_CAN (LPC17_40_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
* CAN 1 Tx, CAN 1 Rx */
#define LPC17_40_IRQ_GPDMA (LPC17_40_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
* IntStatus of DMA channel 1 */
#define LPC17_40_IRQ_I2S (LPC17_40_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
#define LPC17_40_IRQ_ETH (LPC17_40_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
* TxFinishedInt, TxErrorInt,* TxUnderrunInt,
* RxDoneInt, RxFinishedInt, RxErrorInt,
* RxOverrunInt */
#define LPC17_40_IRQ_MCI (LPC17_40_IRQ_EXTINT+29) /* MCI SD Card Interface */
#define LPC17_40_IRQ_MCPWM (LPC17_40_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
* ICAP[2:0], FES */
#define LPC17_40_IRQ_QEI (LPC17_40_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
* DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
* POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
* POS2REV_Int */
#define LPC17_40_IRQ_PLL1 (LPC17_40_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
#define LPC17_40_IRQ_USBACT (LPC17_40_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
#define LPC17_40_IRQ_CANACT (LPC17_40_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
#define LPC17_40_IRQ_UART4 (LPC17_40_IRQ_EXTINT+35) /* UART 4 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_40_IRQ_SSP2 (LPC17_40_IRQ_EXTINT+36) /* SSP2 Tx FIFO half empty of SSP2
* Rx FIFO half full of SSP2
* Rx Timeout of SSP2
* Rx Overrun of SSP2 */
#define LPC17_40_IRQ_LCD (LPC17_40_IRQ_EXTINT+37) /* LCD interrupt
* BER, VCompI, LNBUI, FUFI, CrsrI */
#define LPC17_40_IRQ_GPIO (LPC17_40_IRQ_EXTINT+38) /* GPIO Interrupt
* P0xREI, P2xREI, P0xFEI, P2xFEI */
#define LPC17_40_IRQ_PWM0 (LPC17_40_IRQ_EXTINT+39) /* PWM0 Match 0 - 6 of PWM0
* Capture 0-1 of PWM0 */
#define LPC17_40_IRQ_EEPROM (LPC17_40_IRQ_EXTINT+40) /* EEPROM Interrupt
* EE_PROG_DONE, EE_RW_DONE */
#define LPC17_40_IRQ_NEXTINT (41)
#define LPC17_40_IRQ_NIRQS (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT)
/* GPIO interrupts. The LPC177x_8x supports several interrupts on ports 0 and
* 2 (only). We go through some special efforts to keep the number of IRQs
* to a minimum in this sparse interrupt case.
*
* 31 interrupts on Port 0: p0.0 - p0.30
* 31 interrupts on Port 2: p2.0 - p2.30
* --
* 42
*/
#ifdef CONFIG_LPC17_40_GPIOIRQ
# define LPC17_40_VALID_GPIOINT0 (0xfffffffful) /* GPIO port 0 interrupt set */
# define LPC17_40_VALID_GPIOINT2 (0xfffffffful) /* GPIO port 2 interrupt set */
/* Set 1: 16 interrupts p0.0-p0.15 */
# define LPC17_40_VALID_SHIFT0L (0)
# define LPC17_40_VALID_FIRST0L (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT)
# define LPC17_40_IRQ_P0p0 (LPC17_40_VALID_FIRST0L+0)
# define LPC17_40_IRQ_P0p1 (LPC17_40_VALID_FIRST0L+1)
# define LPC17_40_IRQ_P0p2 (LPC17_40_VALID_FIRST0L+2)
# define LPC17_40_IRQ_P0p3 (LPC17_40_VALID_FIRST0L+3)
# define LPC17_40_IRQ_P0p4 (LPC17_40_VALID_FIRST0L+4)
# define LPC17_40_IRQ_P0p5 (LPC17_40_VALID_FIRST0L+5)
# define LPC17_40_IRQ_P0p6 (LPC17_40_VALID_FIRST0L+6)
# define LPC17_40_IRQ_P0p7 (LPC17_40_VALID_FIRST0L+7)
# define LPC17_40_IRQ_P0p8 (LPC17_40_VALID_FIRST0L+8)
# define LPC17_40_IRQ_P0p9 (LPC17_40_VALID_FIRST0L+9)
# define LPC17_40_IRQ_P0p10 (LPC17_40_VALID_FIRST0L+10)
# define LPC17_40_IRQ_P0p11 (LPC17_40_VALID_FIRST0L+11)
# define LPC17_40_IRQ_P0p12 (LPC17_40_VALID_FIRST0L+12)
# define LPC17_40_IRQ_P0p13 (LPC17_40_VALID_FIRST0L+13)
# define LPC17_40_IRQ_P0p14 (LPC17_40_VALID_FIRST0L+14)
# define LPC17_40_IRQ_P0p15 (LPC17_40_VALID_FIRST0L+15)
# define LPC17_40_VALID_NIRQS0L (16)
/* Set 2: 16 interrupts p0.16-p0.31 */
# define LPC17_40_VALID_SHIFT0H (16)
# define LPC17_40_VALID_FIRST0H (LPC17_40_VALID_FIRST0L+LPC17_40_VALID_NIRQS0L)
# define LPC17_40_IRQ_P0p16 (LPC17_40_VALID_FIRST0H+0)
# define LPC17_40_IRQ_P0p17 (LPC17_40_VALID_FIRST0H+1)
# define LPC17_40_IRQ_P0p18 (LPC17_40_VALID_FIRST0H+2)
# define LPC17_40_IRQ_P0p19 (LPC17_40_VALID_FIRST0H+3)
# define LPC17_40_IRQ_P0p20 (LPC17_40_VALID_FIRST0H+4)
# define LPC17_40_IRQ_P0p21 (LPC17_40_VALID_FIRST0H+5)
# define LPC17_40_IRQ_P0p22 (LPC17_40_VALID_FIRST0H+6)
# define LPC17_40_IRQ_P0p23 (LPC17_40_VALID_FIRST0H+7)
# define LPC17_40_IRQ_P0p24 (LPC17_40_VALID_FIRST0H+8)
# define LPC17_40_IRQ_P0p25 (LPC17_40_VALID_FIRST0H+9)
# define LPC17_40_IRQ_P0p26 (LPC17_40_VALID_FIRST0H+10)
# define LPC17_40_IRQ_P0p27 (LPC17_40_VALID_FIRST0H+11)
# define LPC17_40_IRQ_P0p28 (LPC17_40_VALID_FIRST0H+12)
# define LPC17_40_IRQ_P0p29 (LPC17_40_VALID_FIRST0H+13)
# define LPC17_40_IRQ_P0p30 (LPC17_40_VALID_FIRST0H+14)
# define LPC17_40_IRQ_P0p31 (LPC17_40_VALID_FIRST0H+15)
# define LPC17_40_VALID_NIRQS0H (16)
/* Set 3: 16 interrupts p2.0-p2.15 */
# define LPC17_40_VALID_SHIFT2L (0)
# define LPC17_40_VALID_FIRST2L (LPC17_40_VALID_FIRST0H+LPC17_40_VALID_NIRQS0H)
# define LPC17_40_IRQ_P2p0 (LPC17_40_VALID_FIRST2L+0)
# define LPC17_40_IRQ_P2p1 (LPC17_40_VALID_FIRST2L+1)
# define LPC17_40_IRQ_P2p2 (LPC17_40_VALID_FIRST2L+2)
# define LPC17_40_IRQ_P2p3 (LPC17_40_VALID_FIRST2L+3)
# define LPC17_40_IRQ_P2p4 (LPC17_40_VALID_FIRST2L+4)
# define LPC17_40_IRQ_P2p5 (LPC17_40_VALID_FIRST2L+5)
# define LPC17_40_IRQ_P2p6 (LPC17_40_VALID_FIRST2L+6)
# define LPC17_40_IRQ_P2p7 (LPC17_40_VALID_FIRST2L+7)
# define LPC17_40_IRQ_P2p8 (LPC17_40_VALID_FIRST2L+8)
# define LPC17_40_IRQ_P2p9 (LPC17_40_VALID_FIRST2L+9)
# define LPC17_40_IRQ_P2p10 (LPC17_40_VALID_FIRST2L+10)
# define LPC17_40_IRQ_P2p11 (LPC17_40_VALID_FIRST2L+11)
# define LPC17_40_IRQ_P2p12 (LPC17_40_VALID_FIRST2L+12)
# define LPC17_40_IRQ_P2p13 (LPC17_40_VALID_FIRST2L+13)
# define LPC17_40_IRQ_P2p14 (LPC17_40_VALID_FIRST2L+14)
# define LPC17_40_IRQ_P2p15 (LPC17_40_VALID_FIRST2L+15)
# define LPC17_40_VALID_NIRQS2L (16)
/* Set 4: 16 interrupts p2.16 - p2.31 */
# define LPC17_40_VALID_SHIFT2H (16)
# define LPC17_40_VALID_FIRST2H (LPC17_40_VALID_FIRST2L+LPC17_40_VALID_NIRQS2L)
# define LPC17_40_IRQ_P2p16 (LPC17_40_VALID_FIRST2H+0)
# define LPC17_40_IRQ_P2p17 (LPC17_40_VALID_FIRST2H+1)
# define LPC17_40_IRQ_P2p18 (LPC17_40_VALID_FIRST2H+2)
# define LPC17_40_IRQ_P2p19 (LPC17_40_VALID_FIRST2H+3)
# define LPC17_40_IRQ_P2p20 (LPC17_40_VALID_FIRST2H+4)
# define LPC17_40_IRQ_P2p21 (LPC17_40_VALID_FIRST2H+5)
# define LPC17_40_IRQ_P2p22 (LPC17_40_VALID_FIRST2H+6)
# define LPC17_40_IRQ_P2p23 (LPC17_40_VALID_FIRST2H+7)
# define LPC17_40_IRQ_P2p24 (LPC17_40_VALID_FIRST2H+8)
# define LPC17_40_IRQ_P2p25 (LPC17_40_VALID_FIRST2H+9)
# define LPC17_40_IRQ_P2p26 (LPC17_40_VALID_FIRST2H+10)
# define LPC17_40_IRQ_P2p27 (LPC17_40_VALID_FIRST2H+11)
# define LPC17_40_IRQ_P2p28 (LPC17_40_VALID_FIRST2H+12)
# define LPC17_40_IRQ_P2p29 (LPC17_40_VALID_FIRST2H+13)
# define LPC17_40_IRQ_P2p30 (LPC17_40_VALID_FIRST2H+14)
# define LPC17_40_IRQ_P2p31 (LPC17_40_VALID_FIRST2H+15)
# define LPC17_40_VALID_NIRQS2H (16)
# define LPC17_40_NGPIOAIRQS (LPC17_40_VALID_NIRQS0L+LPC17_40_VALID_NIRQS0H+LPC17_40_VALID_NIRQS2L+LPC17_40_VALID_NIRQS2H)
#else
# define LPC17_40_NGPIOAIRQS (0)
#endif
/* Total number of IRQ numbers */
#define NR_IRQS (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT+LPC17_40_NGPIOAIRQS)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC178X_IRQ_H */
arch/arm/src/armv7-m/up_ramvec_initialize.c
+1 -1
View File
@@ -86,7 +86,7 @@
* vector table must be zero). In this case alignment to a 128 byte address
* boundary is sufficient.
*
* Some parts, such as the LPC17xx family, require alignment to a 256 byte
* Some parts, such as the LPC17xx/LPC40xx family, require alignment to a 256 byte
* address boundary. Any other unusual alignment requirements for the vector
* can be specified for a given architecture be redefining
* NVIC_VECTAB_TBLOFF_MASK in the chip-specific chip.h header file for the
arch/arm/src/cxd56xx/Kconfig
+107
View File
@@ -224,6 +224,46 @@ config CXD56_GPIO_IRQ
---help---
Enable support for GPIO interrupts
config CXD56_UART0
bool "UART0"
default n
---help---
UART interface with hardware flow control in the application subsystem.
if CXD56_UART0
config CXD56_UART0_BAUD
int "CXD56 UART0 BAUD"
default 921600
config CXD56_UART0_PARITY
int "CXd56 UART0 parity"
default 0
range 0 2
---help---
CXD56 UART0 parity. 0=None, 1=Odd, 2=Even. Default: None
config CXD56_UART0_BITS
int "CXD56 UART0 number of bits"
default 8
range 5 8
---help---
CXD56 UART0 number of bits. Default: 8
config CXD56_UART0_2STOP
int "CXD56 UART0 two stop bits"
default 0
---help---
0=1 stop bit, 1=Two stop bits. Default: 1 stop bit
config CXD56_UART0_FLOWCONTROL
bool "CXD56 UART0 flow control"
default n
---help---
Enable CXD56 UART0 RTS flow control
endif
config CXD56_UART1
bool "UART1"
default y
@@ -1183,4 +1223,71 @@ config CXD56_GE2D
default n
---help---
A hardware image processor device.
config CXD56_GNSS
bool "GNSS device"
default n
if CXD56_GNSS
menu "GNSS settings"
config CXD56_GNSS_NPOLLWAITERS
int "GNSS max poll waiters"
default 4
config CXD56_GNSS_NSIGNALRECEIVERS
int "GNSS max signal receivers"
default 4
config CXD56_GNSS_WORKER_STACKSIZE
int "GNSS worker thread stack size"
default 128
config CXD56_GNSS_WORKER_THREAD_PRIORITY
int "GNSS worker thread priority"
default 255
config CXD56_GNSS_BACKUP_FILENAME
string "GNSS backup file name"
default "/mnt/spif/gnss_backup.bin"
---help---
Specify the path and file name of backup data.
config CXD56_GNSS_CEP_FILENAME
string "GNSS CEP file name"
default "/mnt/sd0/gnss_cep.bin"
---help---
Specify the path and file name of cep data.
config CXD56_GNSS_FW_RTK
bool "Support carrier-phase data output for Real-Time Kinematic"
default n
---help---
This is experimental function.
config CXD56_GNSS_DEBUG_FEATURE
bool "GNSS debug feature"
if CXD56_GNSS_DEBUG_FEATURE
config CXD56_GNSS_DEBUG_ERROR
bool "GNSS debug error"
config CXD56_GNSS_DEBUG_WARN
bool "GNSS debug warn"
config CXD56_GNSS_DEBUG_INFO
bool "GNSS debug info"
endif # CXD56_GNSS_DEBUG_FEATURE
endmenu
config CXD56_GEOFENCE
bool "Geofence Support"
default y
depends on CXD56_GNSS
endif
endmenu
arch/arm/src/cxd56xx/Make.defs
+13
View File
@@ -101,6 +101,10 @@ CHIP_CSRCS += cxd56_powermgr.c
CHIP_CSRCS += cxd56_farapi.c
CHIP_CSRCS += cxd56_sysctl.c
ifeq ($(CONFIG_CXD56_UART0),y)
CHIP_CSRCS += cxd56_uart0.c
endif
ifeq ($(CONFIG_CXD56_PM_PROCFS),y)
CHIP_CSRCS += cxd56_powermgr_procfs.c
endif
@@ -181,3 +185,12 @@ endif
ifeq ($(CONFIG_CXD56_WDT),y)
CHIP_CSRCS += cxd56_wdt.c
endif
ifeq ($(CONFIG_CXD56_GNSS),y)
CHIP_CSRCS += cxd56_gnss.c
CHIP_CSRCS += cxd56_cpu1signal.c
endif
ifeq ($(CONFIG_CXD56_GEOFENCE),y)
CHIP_CSRCS += cxd56_geofence.c
endif
arch/arm/src/cxd56xx/cxd56_cpu1signal.c
+281
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/****************************************************************************
* arch/arm/src/cxd56xx/cxd56_cpu1signal.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdlib.h>
#include <errno.h>
#include <sched.h>
#include <pthread.h>
#include <debug.h>
#include "cxd56_icc.h"
#include "cxd56_cpu1signal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef CONFIG_CXD56CPU1_WORKER_STACKSIZE
# define CONFIG_CXD56CPU1_WORKER_STACKSIZE 1024
#endif
#ifndef CONFIG_CXD56CPU1_WORKER_THREAD_PRIORITY
# define CONFIG_CXD56CPU1_WORKER_THREAD_PRIORITY (SCHED_PRIORITY_MAX)
#endif
#define CXD56CPU1_CPUID 1
/****************************************************************************
* Private Type
****************************************************************************/
struct cxd56_sigtype_s
{
int use;
cxd56_cpu1sighandler_t handler;
FAR void * data;
};
struct cxd56cpu1_info_s
{
pthread_t workertid;
int ndev;
struct cxd56_sigtype_s sigtype[CXD56_CPU1_DATA_TYPE_MAX];
};
/****************************************************************************
* Private Data
****************************************************************************/
static struct cxd56cpu1_info_s g_cpu1_info = {0};
/****************************************************************************
* Private Functions
****************************************************************************/
static FAR void *cxd56cpu1_worker(FAR void *arg)
{
struct cxd56cpu1_info_s *priv = (struct cxd56cpu1_info_s *)arg;
iccmsg_t msg;
uint8_t sigtype;
int ret;
msg.cpuid = CXD56CPU1_CPUID;
while (1)
{
ret = cxd56_iccrecvmsg(&msg, 0);
if (ret < 0)
{
continue;
}
sigtype = (uint8_t)CXD56_CPU1_GET_DEV(msg.data);
if (sigtype >= CXD56_CPU1_DATA_TYPE_MAX)
{
_info("Caught invalid sigtype %d.\n", sigtype);
continue;
}
if (priv->sigtype[sigtype].handler)
{
priv->sigtype[sigtype].handler(msg.data,
priv->sigtype[sigtype].data);
}
}
return arg;
}
/****************************************************************************
* Public Functions
****************************************************************************/
int cxd56_cpu1sigsend(uint8_t sigtype, uint32_t data)
{
iccmsg_t msg;
msg.cpuid = CXD56CPU1_CPUID;
msg.msgid = sigtype;
msg.data = data;
return cxd56_iccsend(CXD56_PROTO_GNSS, &msg, 0);
}
void cxd56_cpu1sigregisterhandler(uint8_t sigtype,
cxd56_cpu1sighandler_t handler)
{
struct cxd56cpu1_info_s *priv = &g_cpu1_info;
if (sigtype >= CXD56_CPU1_DATA_TYPE_MAX)
{
return;
}
priv->sigtype[sigtype].handler = handler;
}
void cxd56_cpu1sigunregisterhandler(uint8_t sigtype)
{
struct cxd56cpu1_info_s *priv = &g_cpu1_info;
if (sigtype >= CXD56_CPU1_DATA_TYPE_MAX)
{
return;
}
priv->sigtype[sigtype].handler = NULL;
}
int cxd56_cpu1siginit(uint8_t sigtype, FAR void *data)
{
struct cxd56cpu1_info_s *priv = &g_cpu1_info;
pthread_attr_t tattr;
struct sched_param param;
pthread_t tid;
int ret;
if (sigtype >= CXD56_CPU1_DATA_TYPE_MAX)
{
return -ENODEV;
}
sched_lock();
if (priv->sigtype[sigtype].use)
{
ret = -EBUSY;
goto _err1;
}
priv->sigtype[sigtype].use = true;
priv->sigtype[sigtype].data = data;
if (priv->ndev > 0)
{
ret = OK;
goto _err1;
}
priv->ndev++;
sched_unlock();
cxd56_iccinit(CXD56_PROTO_GNSS);
ret = cxd56_iccinitmsg(CXD56CPU1_CPUID);
if (ret < 0)
{
_err("Failed to initialize ICC for GPS CPU: %d\n", ret);
goto _err0;
}
pthread_attr_init(&tattr);
tattr.stacksize = CONFIG_CXD56CPU1_WORKER_STACKSIZE;
param.sched_priority = CONFIG_CXD56CPU1_WORKER_THREAD_PRIORITY;
pthread_attr_setschedparam(&tattr, &param);
ret = pthread_create(&tid, &tattr, cxd56cpu1_worker,
(pthread_addr_t)priv);
if (ret != 0)
{
cxd56_iccuninitmsg(CXD56CPU1_CPUID);
ret = -ret; /* pthread_create does not modify errno. */
goto _err0;
}
priv->workertid = tid;
return ret;
_err0:
priv->sigtype[sigtype].use = false;
priv->sigtype[sigtype].data = NULL;
return ret;
_err1:
sched_unlock();
return ret;
}
int cxd56_cpu1siguninit(uint8_t sigtype)
{
struct cxd56cpu1_info_s *priv = &g_cpu1_info;
pthread_t tid;
int ret;
if (sigtype >= CXD56_CPU1_DATA_TYPE_MAX)
{
return -ENODEV;
}
sched_lock();
if (!priv->sigtype[sigtype].use)
{
ret = -EBUSY;
goto _err1;
}
priv->ndev--;
priv->sigtype[sigtype].use = false;
priv->sigtype[sigtype].data = NULL;
if (priv->ndev > 0)
{
ret = OK;
goto _err0;
}
tid = priv->workertid;
priv->workertid = 0;
sched_unlock();
pthread_cancel(tid);
pthread_join(tid, NULL);
cxd56_iccuninit(CXD56CPU1_CPUID);
return 0;
_err1:
sched_unlock();
_err0:
return ret;
}
arch/arm/src/cxd56xx/cxd56_cpu1signal.h
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/****************************************************************************
* arch/arm/src/cxd56xx/cxd56_cpu1signal.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_CPU1SIGNAL_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_CPU1SIGNAL_H
/* CPU1 Notifyable functions */
#define CXD56_CPU1_DATA_TYPE_GNSS 0
#define CXD56_CPU1_DATA_TYPE_GEOFENCE 1
#define CXD56_CPU1_DATA_TYPE_PVTLOG 2
#define CXD56_CPU1_DATA_TYPE_AGPS 3
#define CXD56_CPU1_DATA_TYPE_RTK 4
#define CXD56_CPU1_DATA_TYPE_SPECTRUM 5
#define CXD56_CPU1_DATA_TYPE_INFO 6
#define CXD56_CPU1_DATA_TYPE_BACKUP 7
#define CXD56_CPU1_DATA_TYPE_CEP 8
#define CXD56_CPU1_DATA_TYPE_CEPFILE 9
#define CXD56_CPU1_DATA_TYPE_BKUPFILE 10
#define CXD56_CPU1_DATA_TYPE_GPSEPHEMERIS 11
#define CXD56_CPU1_DATA_TYPE_GLNEPHEMERIS 12
#define CXD56_CPU1_DATA_TYPE_CPUFIFOAPI 13
#define CXD56_CPU1_DATA_TYPE_SBAS 14
#define CXD56_CPU1_DATA_TYPE_DCREPORT 15
#define CXD56_CPU1_DATA_TYPE_MAX 16
/* CPU1 devices */
#define CXD56_CPU1_DEV_GNSS (CXD56_CPU1_DATA_TYPE_GNSS)
#define CXD56_CPU1_DEV_GEOFENCE (CXD56_CPU1_DATA_TYPE_GEOFENCE)
#define CXD56_CPU1_DEV_MASK 0xff
#define CXD56_CPU1_GET_DEV(DATA) ((DATA) & CXD56_CPU1_DEV_MASK)
#define CXD56_CPU1_GET_DATA(DATA) ((DATA) >> 8)
#if CXD56_CPU1_DATA_TYPE_MAX > (CXD56_CPU1_DEV_MASK + 1)
#error "CXD56_CPU1_DEV must be smaller than 0xf"
#endif
typedef void (*cxd56_cpu1sighandler_t)(uint32_t data, FAR void *userdata);
extern int cxd56_cpu1siginit(uint8_t cpu1dev, FAR void *data);
extern int cxd56_cpu1siguninit(uint8_t cpu1dev);
extern void cxd56_cpu1sigregisterhandler(uint8_t cpu1dev,
cxd56_cpu1sighandler_t handler);
extern void cxd56_cpu1sigunregisterhandler(uint8_t cpu1dev);
extern int cxd56_cpu1sigsend(uint8_t sigtype, uint32_t data);
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_CPU1SIGNAL_H */
arch/arm/src/cxd56xx/cxd56_geofence.c
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arch/arm/src/cxd56xx/cxd56_geofence.h
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/****************************************************************************
* arch/arm/src/cxd56xx/cxd56_geofence.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_GEOFENCE_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_GEOFENCE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: cxd56_geofenceinitialize
*
* Description:
* Initialize GEOFENCE device
*
* Input Parameters:
* devpath - The full path to the driver to register. E.g., "/dev/geofence"
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
****************************************************************************/
int cxd56_geofenceinitialize(FAR const char *devpath);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_GEOFENCE_H */
arch/arm/src/cxd56xx/cxd56_gnss.c
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arch/arm/src/cxd56xx/cxd56_gnss.h
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/****************************************************************************
* arch/arm/src/cxd56xx/cxd56_gnss.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_GNSS_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_GNSS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* GNSS specific debug */
#ifdef CONFIG_CXD56_GNSS_DEBUG_ERROR
# define gnsserr(fmt, ...) logerr(fmt, ## __VA_ARGS__)
#else
# define gnsserr(fmt, ...)
#endif
#ifdef CONFIG_CXD56_GNSS_DEBUG_WARN
# define gnsswarn(fmt, ...) logwarn(fmt, ## __VA_ARGS__)
#else
# define gnsswarn(fmt, ...)
#endif
#ifdef CONFIG_CXD56_GNSS_DEBUG_INFO
# define gnssinfo(fmt, ...) loginfo(fmt, ## __VA_ARGS__)
#else
# define gnssinfo(fmt, ...)
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: cxd56_gnssinitialize
*
* Description:
* Initialize GNSS device
*
* Input Parameters:
* devpath - The full path to the driver to register. E.g., "/dev/gps"
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
****************************************************************************/
int cxd56_gnssinitialize(FAR const char *devpath);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_GNSS_H */
arch/arm/src/cxd56xx/cxd56_gnss_api.h
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/****************************************************************************
* arch/arm/src/cxd56xx/cxd56_gnss_api.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_GNSS_API_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_GNSS_API_H
#include <arch/chip/gnss_type.h>
#include <arch/chip/gnss.h>
/* GD Start mode */
#define CXD56_GNSS_STMOD_COLD 0
#define CXD56_GNSS_STMOD_WARM 1
#define CXD56_GNSS_STMOD_WARMACC2 2
#define CXD56_GNSS_STMOD_HOT 3
#define CXD56_GNSS_STMOD_HOTACC 4
#define CXD56_GNSS_STMOD_HOTACC2 5
#define CXD56_GNSS_STMOD_HOTACC3 6
#define CXD56_GNSS_STMOD_XTC1 7
#define CXD56_GNSS_STMOD_XTC2 8
/* GD operation mode */
/* GD_SetOperationMode, GD_GetOperationMode */
#define CXD56_GNSS_OPMOD_NORMAL 1
#define CXD56_GNSS_OPMOD_LOWPOWER 2
#define CXD56_GNSS_OPMOD_BALANCE 4
#define CXD56_GNSS_OPMOD_1PSS 5
/* Start a positioning
* begining to search the satellites and measure the receiver position
*/
int GD_Start(uint8_t startMode);
/* Stop a positioning */
int GD_Stop(void);
/* Select GNSSs to positioning
* These are able to specified by CXD56_GNSS_B_SAT_XXX defines.
*/
int GD_SelectSatelliteSystem(uint32_t system);
/* Get current using GNSSs to positioning
* A argument 'satellite' indicates current GNSSs by bit fields defined
* by CXD56_GNSS_B_SAT_XXX.
*/
int GD_GetSatelliteSystem(FAR uint32_t *system);
/* Set the rough receiver position */
int GD_SetReceiverPositionEllipsoidal(FAR double *dLat, FAR double *dLon,
FAR double *dHeight);
/* Set the rough receiver position as orgothonal */
int GD_SetReceiverPositionOrthogonal(int32_t dX, int32_t dY, int32_t dZ);
/* Set enable or disable the 1PPS output. */
int GD_Set1ppsOutput(uint32_t enable);
/* Get the current 1PPS output setting. */
int GD_Get1ppsOutput(FAR uint32_t *enable);
/* Set the receiver operation mode
* 1st argument 'mode' is a operation mode defined by CXD56_GNSS_OPMOD_XXX.
* 2nd argument 'cycle' is a positioning period[ms], default is 1000[ms].
*/
int GD_SetOperationMode(uint32_t mode, uint32_t cycle);
/* Get the receiver operation mode */
int GD_GetOperationMode(FAR uint32_t *mode, FAR uint32_t *cycle);
/* Set the TCXO offset */
int GD_SetTcxoOffset(int32_t offset);
/* Get the TCXO offset */
int GD_GetTcxoOffset(FAR int32_t *offset);
/* Set the estimated current time of the receiver.
* 1st argument date & time are in UTC.
*/
int GD_SetTime(FAR struct cxd56_gnss_date_s *date,
FAR struct cxd56_gnss_time_s *time);
/* Set the network time */
int GD_SetFrameTime(uint16_t sec, uint32_t fracSec);
/* Get the almanac data */
int GD_GetAlmanac(uint32_t satellite, FAR uint32_t* almanac,
FAR uint32_t *almanacSize);
/* Set the almanac data */
int GD_SetAlmanac(uint32_t satellite, FAR uint32_t *almanac);
/* Get the Ephemeris data */
int GD_GetEphemeris(uint32_t satellite, FAR uint32_t* ephemeris,
FAR uint32_t *ephemerisSize);
/* Set the Ephemeris data */
int GD_SetEphemeris(uint32_t satellite, FAR uint32_t *ephemeris);
/* Select to use or not use the initial position calculation supporting
* information of the QZSS L1-SAIF.
*/
int GD_SetQzssPosAssist(uint32_t enable);
/* Get a setting of the initial position calculation supporting
* information of the QZSS L1-SAIF.
*/
int GD_GetQzssPosAssist(FAR uint32_t *enable);
/* Set IMES bitrates. */
int GD_SetImesBitrate(uint32_t bitrate);
/* Get IMES bitrates. */
int GD_GetImesBitrate(FAR uint32_t *bitrate);
/* Set IMES center frequency offset. */
int GD_SetImesCenterFreqOffset(uint32_t offset);
/* Set IMES preamble. */
int GD_SetImesPreamble(uint32_t preamble);
/* Start GPS test */
void GD_StartGpsTest(uint32_t satellite, uint32_t reserve1,
uint32_t reserve2, uint32_t reserve3);
/* Stop GPS test */
int GD_StopGpsTest(void);
/* Get GPS test result */
int GD_GetGpsTestResult(FAR float* cn, FAR float* doppler);
/* Control Spectrum output */
int GD_SpectrumControl(unsigned long time, unsigned int enable,
unsigned char moniPoint1, unsigned char step1,
unsigned char moniPoint2, unsigned char step2);
/* Save the backup data to a Flash memory. */
int GD_SaveBackupdata(void);
/* CEP Check Assist Data Valid */
int GD_CepCheckAssistData(void);
/* CEP Get Age Data */
int GD_CepGetAgeData(FAR float *age, FAR float *cepi);
/* CEP Reset Assist Data init flag & valid flag */
int GD_CepInitAssistData(void);
/* AGPS Set tau */
int GD_SetTauGps(FAR double *tau);
/* AGPS Set Acquist */
int GD_SetAcquist(FAR uint8_t *pAcquistData, uint16_t acquistSize);
/* Set the estimated current time of the receiver.
* 1st argument date & time are in GPS time.
*/
int GD_SetTimeGps(FAR struct cxd56_gnss_date_s *date,
FAR struct cxd56_gnss_time_s *time);
/* Clear Receiver Infomation */
int GD_ClearReceiverInfo(uint32_t type);
/* AGPS Set Tow Assist */
int GD_SetTowAssist(FAR uint8_t *pAssistData, uint16_t dataSize);
/* AGPS Set UTC Model */
int GD_SetUtcModel(FAR uint8_t *pModelData, uint16_t dataSize);
/* Read GNSS data to specified buffer */
int GD_ReadBuffer(uint8_t type, int32_t offset, FAR void *buf,
uint32_t length);
/* Write GNSS data from specified buffer */
int GD_WriteBuffer(uint8_t type, int32_t offset, FAR void *buf,
uint32_t length);
/* Set notify mask, this mask flag is cleared when notified(poll/signal) */
int GD_SetNotifyMask(uint8_t type, uint8_t clear);
/* Geofence Add Region */
int GD_GeoAddRegion(uint8_t id, long lat, long lon, uint16_t rad);
/* Geofence Modify Region */
int GD_GeoModifyRegion(uint8_t id, long lat, long lon, uint16_t rad);
/* Geofence Delete Region */
int GD_GeoDeleteRegione(uint8_t id);
/* Geofence All delete Region */
int GD_GeoDeleteAllRegion(void);
/* Geofence Region check */
int GD_GeoGetRegionData(uint8_t id, FAR long *lat, FAR long *lon,
FAR uint16_t *rad);
/* Geofence Get Used Region ID */
uint32_t GD_GeoGetUsedRegionId(void);
/* Geofence Set mode */
int GD_GeoSetOpMode(uint16_t deadzone, uint16_t dwell_detecttime);
/* Geofence Request All region notify */
int GD_GeoSetAllRgionNotifyRequest(void);
/* Geofence Register to gnss_provider */
int GD_RegisterGeofence(void);
/* Geofence Release from gnss_provider */
int GD_ReleaseGeofence(void);
/* Pvtlog Register to gnss_provider */
int GD_RegisterPvtlog(uint32_t cycle, uint32_t threshold);
/* Pvtlog Release */
int GD_ReleasePvtlog(void);
/* Pvtlog Delete log data */
int GD_PvtlogDeleteLog(void);
/* Pvtlog Get Log status */
int GD_PvtlogGetLogStatus(FAR struct cxd56_gnss_status_s *pLogStatus);
/* Start outputting carrier phase info. */
int GD_RtkStart(FAR struct cxd56_rtk_setting_s *pParam);
/* Stop outputting carrier phase info. */
int GD_RtkStop(void);
/* Set output interval of carrier phase info.
*
* interval : CXD56_GNSS_RTK_INTERVAL_XXX (gd_type.h)
*/
int GD_RtkSetOutputInterval(int interval);
/* Get output interval of carrier phase info. [ms] */
int GD_RtkGetOutputInterval(FAR int* interval);
/* Set GNSS of outputting carrier phase info. */
int GD_RtkSetGnss(uint32_t gnss);
/* Get GNSS of outputting carrier phase info. */
int GD_RtkGetGnss(FAR uint32_t* pGnss);
/* Set enable/disable GD to notify updating ephemeris */
int GD_RtkSetEphNotify(int enable);
/* Get enable/disable GD to notify updating ephemeris */
int GD_RtkGetEphNotify(FAR int* enable);
/* Set the Ephemeris data Ephemeris data size is variable. */
int GD_SetVarEphemeris(uint32_t *ephemeris, uint32_t ephemerisSize);
/* Get the Ephemeris data Ephemeris data size is variable. */
int GD_GetVarEphemeris(uint32_t satellite, uint32_t* ephemeris,
uint32_t ephemerisSize);
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_GNSS_API_H */
arch/arm/src/cxd56xx/cxd56_uart0.c
+325
View File
@@ -0,0 +1,325 @@
/****************************************************************************
* arch/arm/src/cxd56xx/cxd56_uart0.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/kmalloc.h>
#include <nuttx/fs/fs.h>
#include <nuttx/irq.h>
#include <queue.h>
#include <semaphore.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <debug.h>
#include <errno.h>
#include "up_arch.h"
#include "chip.h"
#include "cxd56_pinconfig.h"
#ifdef CONFIG_CXD56_UART0
#include <arch/chip/uart0.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef CONFIG_CXD56_UART0_BAUD
# define CONFIG_CXD56_UART0_BAUD 921600
#endif
#ifndef CONFIG_CXD56_UART0_BITS
# define CONFIG_CXD56_UART0_BITS 8
#endif
#ifndef CONFIG_CXD56_UART0_PARITY
# define CONFIG_CXD56_UART0_PARITY 0
#endif
#ifndef CONFIG_CXD56_UART0_2STOP
# define CONFIG_CXD56_UART0_2STOP 0
#endif
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static int uart0_open(FAR struct file *filep);
static int uart0_close(FAR struct file *filep);
static ssize_t uart0_read(FAR struct file *filep,
FAR char *buffer, size_t len);
static ssize_t uart0_write(FAR struct file *filep,
FAR const char *buffer, size_t len);
static int uart0_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
static int uart0_semtake(sem_t *id);
static void uart0_semgive(sem_t *id);
/****************************************************************************
* FarAPI prototypes
****************************************************************************/
int PD_UartInit(int ch);
int PD_UartUninit(int ch);
int PD_UartConfiguration(int ch, int baudrate, int databits,
int parity, int stopbit, int flowctrl);
int PD_UartEnable(int ch);
int PD_UartDisable(int ch);
int PD_UartReceive(int ch, void *buf, int size, int leave);
int PD_UartSend(int ch, void *buf, int size, int leave);
/****************************************************************************
* Private Data
****************************************************************************/
static const struct file_operations g_uart0fops =
{
.open = uart0_open,
.close = uart0_close,
.read = uart0_read,
.write = uart0_write,
.seek = 0,
.ioctl = uart0_ioctl,
};
static sem_t g_lock;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: uart0_semtake
****************************************************************************/
static int uart0_semtake(sem_t *id)
{
while (sem_wait(id) != 0)
{
ASSERT(errno == EINTR);
}
return OK;
}
/****************************************************************************
* Name: uart0_semgive
****************************************************************************/
static void uart0_semgive(sem_t *id)
{
sem_post(id);
}
/****************************************************************************
* Name: uart0_open
****************************************************************************/
static int uart0_open(FAR struct file *filep)
{
FAR struct inode *inode = filep->f_inode;
int flowctl;
int bits;
int stop;
int ret;
if (inode->i_crefs > 1)
{
return OK;
}
ret = PD_UartInit(0);
if (ret < 0)
{
set_errno(EFAULT);
return ERROR;
}
/* 0 = 5bit, 1 = 6bit, 2 = 7bit, 3 = 8bit */
bits = CONFIG_CXD56_UART0_BITS - 5;
/* 1 = 1 stop, 2 = 2 stop bit */
stop = CONFIG_CXD56_UART0_2STOP + 1;
/* Enable UART0 pin configuration */
#ifdef CONFIG_UART0_FLOWCONTROL
flowctl = 1;
CXD56_PIN_CONFIGS(PINCONFS_SPI2_UART0);
#else
flowctl = 0;
CXD56_PIN_CONFIGS(PINCONFS_SPI2A_UART0);
#endif
ret = PD_UartConfiguration(0, CONFIG_CXD56_UART0_BAUD,
bits,
CONFIG_CXD56_UART0_PARITY,
stop, flowctl);
if (ret < 0)
{
PD_UartUninit(0);
set_errno(EINVAL);
return ERROR;
}
ret = PD_UartEnable(0);
if (ret < 0)
{
PD_UartUninit(0);
set_errno(EFAULT);
return ERROR;
}
return OK;
}
/****************************************************************************
* Name: uart0_close
****************************************************************************/
static int uart0_close(FAR struct file *filep)
{
FAR struct inode *inode = filep->f_inode;
if (inode->i_crefs == 1)
{
PD_UartDisable(0);
PD_UartUninit(0);
/* Disable UART0 pin by changing Hi-Z GPIO */
#ifdef CONFIG_UART0_FLOWCONTROL
CXD56_PIN_CONFIGS(PINCONFS_SPI2_GPIO);
#else
CXD56_PIN_CONFIGS(PINCONFS_SPI2A_GPIO);
#endif
}
return 0;
}
/****************************************************************************
* Name: uart0_read
****************************************************************************/
static ssize_t uart0_read(FAR struct file *filep,
FAR char *buffer, size_t len)
{
int ret;
uart0_semtake(&g_lock);
/* Always blocking */
ret = PD_UartReceive(0, buffer, len, 0);
uart0_semgive(&g_lock);
if (ret < 0)
{
set_errno(-ret);
ret = 0; /* Receive no data */
}
return (ssize_t)ret;
}
/****************************************************************************
* Name: uart0_write
****************************************************************************/
static ssize_t uart0_write(FAR struct file *filep,
FAR const char *buffer, size_t len)
{
int ret;
uart0_semtake(&g_lock);
/* Always blocking */
ret = PD_UartSend(0, (FAR void *)buffer, len, 0);
uart0_semgive(&g_lock);
if (ret < 0)
{
set_errno(-ret);
ret = 0;
}
return (ssize_t)ret;
}
/****************************************************************************
* Name: uart0_ioctl
****************************************************************************/
static int uart0_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
{
return -ENOTTY;
}
/****************************************************************************
* Name: cxd56_uart0initialize
****************************************************************************/
int cxd56_uart0initialize(FAR const char *devname)
{
int ret;
sem_init(&g_lock, 0, 1);
ret = register_driver(devname, &g_uart0fops, 0666, NULL);
if (ret != 0)
{
return ERROR;
}
return OK;
}
/****************************************************************************
* Name: cxd56_uart0uninitialize
****************************************************************************/
void cxd56_uart0uninitialize(FAR const char *devname)
{
unregister_driver(devname);
sem_destroy(&g_lock);
}
#endif /* CONFIG_CXD56_UART0 */
arch/arm/src/imxrt/imxrt_usdhc.c
+2 -2
View File
@@ -3017,7 +3017,7 @@ FAR struct sdio_dev_s *imxrt_usdhc_initialize(int slotno)
imxrt_clockall_usdhc1();
break;
#if defined(CONFIG_IMXRT_USDHC2)
case IMXRT_USDHC2_BASE:
(void)imxrt_config_gpio(PIN_USDHC2_D0);
(void)imxrt_config_gpio(PIN_USDHC2_D1);
@@ -3027,7 +3027,7 @@ FAR struct sdio_dev_s *imxrt_usdhc_initialize(int slotno)
(void)imxrt_config_gpio(PIN_USDHC2_CMD);
imxrt_clockall_usdhc2();
break;
#endif
default:
return NULL;
}
arch/arm/src/lpc11xx/Kconfig
-241
View File
@@ -1,241 +0,0 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
comment "LPC11xx Configuration Options"
choice
prompt "NXP LPC11XX Chip Selection"
default ARCH_CHIP_LPC1115
depends on ARCH_CHIP_LPC11XX
config ARCH_CHIP_LPC1114
bool "LPC1114"
select ARCH_FAMILY_LPC111X
config ARCH_CHIP_LPC1115
bool "LPC1115"
select ARCH_FAMILY_LPC111X
endchoice
config ARCH_FAMILY_LPC111X
bool
menu "LPC11xx Peripheral Support"
choice
prompt "System Clock:"
default LPC11_INTRCOSC
config LPC11_INTRCOSC
bool "Internal RC"
config LPC11_MAINOSC
bool "External Crystal"
endchoice
choice
prompt "SysTick clock source"
default LPC11_SYSTICK_CORECLK
config LPC11_SYSTICK_CORECLK
bool "Cortex-M0 core clock"
config LPC11_SYSTICK_CORECLK_DIV16
bool "Cortex-M0 core clock divided by 16"
endchoice
config LPC11_PLL
bool "PLL"
default y
config LPC11_UART0
bool "UART0"
select UART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
default y
config LPC11_CAN0
bool "CAN0"
default n
config LPC11_SPI
bool "SPI"
default n
config LPC11_SSP0
bool "SSP0"
default n
config LPC11_SSP1
bool "SSP1"
default n
config LPC11_I2C0
bool "I2C0"
default n
config LPC11_TMR0
bool "Timer 0"
default n
config LPC11_TMR1
bool "Timer 1"
default n
config LPC11_WDT
bool "WDT"
default n
config LPC11_ADC
bool "ADC"
default n
config LPC11_FLASH
bool "FLASH"
default n
endmenu
menu "ADC driver options"
depends on LPC11_ADC
config LPC11_ADC0_AVERAGE
int "ADC0 average"
default 200
config LPC11_ADC0_MASK
hex "ADC0 mask"
default 0x01
config LPC11_ADC0_SPS
int "ADC0 SPS"
default 1000
config LPC11_ADC_CHANLIST
bool "Use ADC channel list"
default n
---help---
The errata that states: "A/D Global Data register should not be used
with burst mode or hardware triggering". If this option is selected,
then the ADC driver will grab from the individual channel registers
rather than from the global data register as this is the stated
workaround in the errata.
The ADC interrupt will trigger on conversion complete on the last
channel listed in the array g_adc_chanlist[] (as opposed to
triggering interrupt from the global DONE flag).
If this option is enabled, then the platform specific code must do
two things: (1) define LPC11_ADC_NCHANNELS in the configuration file
and (2) provide an array g_adc_chanlist[] with the channel numbers
matching the LPC11_ADC0_MASK within the board-specific library.
config LPC11_ADC_BURSTMODE
bool "One interrupt at the end of all ADC conversions"
default n
---help---
Select this if you want to generate only one interrupt once all
selected channels has been converted by the ADC
config LPC11_ADC_NCHANNELS
int "ADC0 number of channels"
depends on LPC11_ADC_CHANLIST
default 0
---help---
If LPC11_ADC_CHANLIST is enabled, then the platform specific code
must do two things: (1) define LPC11_ADC_NCHANNELS in the configuration
file and (2) provide an array g_adc_chanlist[] with the channel
numbers matching the LPC11_ADC0_MASK within the board-specific
library.
endmenu
menu "CAN driver options"
depends on LPC11_CAN1 || LPC11_CAN2
config LPC11_CAN1_BAUD
int "CAN1 BAUD"
depends on LPC11_CAN1
---help---
CAN1 BAUD rate. Required if LPC11_CAN1 is defined.
config LPC11_CAN2_BAUD
int "CAN2 BAUD"
depends on LPC11_CAN2
---help---
CAN2 BAUD rate. Required if LPC11_CAN2 is defined.
config LPC11_CAN1_DIVISOR
int "CAN1 CCLK divisor"
depends on LPC11_CAN1
default 4
---help---
CAN1 is clocked at CCLK divided by this number. (the CCLK frequency is divided
by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4.
config LPC11_CAN2_DIVISOR
int "CAN2 CCLK divisor"
depends on LPC11_CAN2
default 4
---help---
CAN2 is clocked at CCLK divided by this number. (the CCLK frequency is divided
by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4.
config LPC11_CAN_TSEG1
int "TSEG1 quanta"
default 6
---help---
The number of CAN time quanta in segment 1. Default: 6
config LPC11_CAN_TSEG2
int "TSEG2 quanta"
default 4
---help---
The number of CAN time quanta in segment 2. Default: 7
config LPC11_CAN_SAM
bool "CAN sampling"
default n
---help---
The bus is sampled 3 times (recommended for low to medium speed buses to spikes on the bus-line).
config CAN_REGDEBUG
bool "Register level debug"
depends on DEBUG_CAN_INFO
default n
---help---
Output detailed register-level CAN debug information. Requires also
CONFIG_DEBUG_CAN_INFO.
endmenu
config LPC11_GPIOIRQ
bool "GPIO interrupt support"
default n
---help---
Enable support for GPIO interrupts
menu "I2C driver options"
depends on LPC11_I2C0 || LPC11_I2C1 || LPC11_I2C2
config LPC11_I2C0_FREQUENCY
int "I2C0 frequency"
depends on LPC11_I2C0
default 100000
config LPC11_I2C1_FREQUENCY
int "I2C1 frequency"
depends on LPC11_I2C1
default 100000
config LPC11_I2C2_FREQUENCY
int "I2C2 frequency"
depends on LPC11_I2C2
default 100000
endmenu
arch/arm/src/lpc11xx/Make.defs
-101
View File
@@ -1,101 +0,0 @@
############################################################################
# arch/arm/src/lpc11xx/Make.defs
#
# Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
HEAD_ASRC =
CMN_ASRCS = up_exception.S up_saveusercontext.S up_fullcontextrestore.S
CMN_ASRCS += up_switchcontext.S vfork.S
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copyfullstate.c
CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c
CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c
CMN_CSRCS += up_puts.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c
CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_stackframe.c
CMN_CSRCS += up_systemreset.c up_unblocktask.c up_usestack.c up_doirq.c
CMN_CSRCS += up_hardfault.c up_svcall.c up_vectors.c up_vfork.c
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += up_task_start.c up_pthread_start.c
CMN_CSRCS += up_signal_dispatch.c
CMN_UASRCS += up_signal_handler.S
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c
endif
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += up_dumpnvic.c
endif
CHIP_ASRCS =
CHIP_CSRCS = lpc11_clockconfig.c lpc11_gpio.c lpc11_i2c.c lpc11_irq.c
CHIP_CSRCS += lpc11_lowputc.c lpc11_serial.c lpc11_spi.c lpc11_ssp.c
CHIP_CSRCS += lpc11_start.c
# Configuration-dependent LPC11xx files
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += lpc11_idle.c
endif
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += lpc11_timerisr.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += lpc11_userspace.c
endif
ifeq ($(CONFIG_LPC11_GPIOIRQ),y)
CHIP_CSRCS += lpc11_gpioint.c
endif
ifeq ($(CONFIG_ARCH_IRQPRIO),y)
CHIP_CSRCS += lpc11_irqprio.c
endif
ifeq ($(CONFIG_LPC11_SPI0),y)
CHIP_CSRCS += lpc11_spi.c
else
ifeq ($(CONFIG_LPC11_SPI1),y)
CHIP_CSRCS += lpc11_spi.c
endif
endif
ifeq ($(CONFIG_PWM),y)
CHIP_CSRCS += lpc11_pwm.c
endif
arch/arm/src/lpc11xx/chip.h
-74
View File
@@ -1,74 +0,0 @@
/************************************************************************************
* arch/arm/src/lpc11xx/chip.h
*
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_H
#define __ARCH_ARM_SRC_LPC11XX_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "nvic.h"
/* Include the chip capabilities file */
#include <arch/lpc11xx/chip.h>
#define ARMV6M_PERIPHERAL_INTERRUPTS 32
/* Include the memory map file. Other chip hardware files should then include
* this file for the proper setup.
*/
#include "hardware/lpc11_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_H */
arch/arm/src/lpc11xx/hardware/lpc111x_iocon.h
-269
View File
@@ -1,269 +0,0 @@
/************************************************************************************
* arch/arm/src/lpc11xx/hardware/lpc111x_iocon.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Rommel Marcelo
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC111X_IOCON_H
#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC111X_IOCON_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/lpc11_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#define IOCON_NPINS 12
/* Register offsets *****************************************************************/
/* Note: The IOCON offset is not linear. See User manual UM10398 Page 74 */
#define LPC11_IOCON_P0_0_OFFSET 0x00c
#define LPC11_IOCON_P0_1_OFFSET 0x010
#define LPC11_IOCON_P0_2_OFFSET 0x01c
#define LPC11_IOCON_P0_3_OFFSET 0x02C
#define LPC11_IOCON_P0_4_OFFSET 0x030
#define LPC11_IOCON_P0_5_OFFSET 0x034
#define LPC11_IOCON_P0_6_OFFSET 0x04c
#define LPC11_IOCON_P0_7_OFFSET 0x050
#define LPC11_IOCON_P0_8_OFFSET 0x060
#define LPC11_IOCON_P0_9_OFFSET 0x064
#define LPC11_IOCON_P0_10_OFFSET 0x068
#define LPC11_IOCON_P0_11_OFFSET 0x074
#define LPC11_IOCON_P1_0_OFFSET 0x078
#define LPC11_IOCON_P1_1_OFFSET 0x07c
#define LPC11_IOCON_P1_2_OFFSET 0x080
#define LPC11_IOCON_P1_3_OFFSET 0x090
#define LPC11_IOCON_P1_4_OFFSET 0x094
#define LPC11_IOCON_P1_5_OFFSET 0x0a0
#define LPC11_IOCON_P1_6_OFFSET 0x0a4
#define LPC11_IOCON_P1_7_OFFSET 0x0a8
#define LPC11_IOCON_P1_8_OFFSET 0x014
#define LPC11_IOCON_P1_9_OFFSET 0x038
#define LPC11_IOCON_P1_10_OFFSET 0x06c
#define LPC11_IOCON_P1_11_OFFSET 0x098
#define LPC11_IOCON_P2_0_OFFSET 0x008
#define LPC11_IOCON_P2_1_OFFSET 0x028
#define LPC11_IOCON_P2_2_OFFSET 0x05c
#define LPC11_IOCON_P2_3_OFFSET 0x08c
#define LPC11_IOCON_P2_4_OFFSET 0x040
#define LPC11_IOCON_P2_5_OFFSET 0x044
#define LPC11_IOCON_P2_6_OFFSET 0x000
#define LPC11_IOCON_P2_7_OFFSET 0x020
#define LPC11_IOCON_P2_8_OFFSET 0x024
#define LPC11_IOCON_P2_9_OFFSET 0x054
#define LPC11_IOCON_P2_10_OFFSET 0x058
#define LPC11_IOCON_P2_11_OFFSET 0x070
#define LPC11_IOCON_P3_0_OFFSET 0x084
#define LPC11_IOCON_P3_1_OFFSET 0x088
#define LPC11_IOCON_P3_2_OFFSET 0x09C
#define LPC11_IOCON_P3_3_OFFSET 0x0ac
#define LPC11_IOCON_P3_4_OFFSET 0x03c
#define LPC11_IOCON_P3_5_OFFSET 0x048
#define LPC11_IOCON_SCK_LOC_OFFSET 0x0b0
#define LPC11_IOCON_DSR_LOC_OFFSET 0x0b4
#define LPC11_IOCON_DCD_LOC_OFFSET 0x0b8
#define LPC11_IOCON_RI_LOC_OFFSET 0x0bc
/* Register addresses ***************************************************************/
/* Note: The IOCON base is not linear. See User manual UM10398 Page 74 */
#define LPC11_IOCON_P0_0 (LPC11_IOCON_BASE + LPC11_IOCON_P0_0_OFFSET)
#define LPC11_IOCON_P0_1 (LPC11_IOCON_BASE + LPC11_IOCON_P0_1_OFFSET)
#define LPC11_IOCON_P0_2 (LPC11_IOCON_BASE + LPC11_IOCON_P0_2_OFFSET)
#define LPC11_IOCON_P0_3 (LPC11_IOCON_BASE + LPC11_IOCON_P0_3_OFFSET)
#define LPC11_IOCON_P0_4 (LPC11_IOCON_BASE + LPC11_IOCON_P0_4_OFFSET)
#define LPC11_IOCON_P0_5 (LPC11_IOCON_BASE + LPC11_IOCON_P0_5_OFFSET)
#define LPC11_IOCON_P0_6 (LPC11_IOCON_BASE + LPC11_IOCON_P0_6_OFFSET)
#define LPC11_IOCON_P0_7 (LPC11_IOCON_BASE + LPC11_IOCON_P0_7_OFFSET)
#define LPC11_IOCON_P0_8 (LPC11_IOCON_BASE + LPC11_IOCON_P0_8_OFFSET)
#define LPC11_IOCON_P0_9 (LPC11_IOCON_BASE + LPC11_IOCON_P0_9_OFFSET)
#define LPC11_IOCON_P0_10 (LPC11_IOCON_BASE + LPC11_IOCON_P0_10_OFFSET)
#define LPC11_IOCON_P0_11 (LPC11_IOCON_BASE + LPC11_IOCON_P0_11_OFFSET)
#define LPC11_IOCON_P1_0 (LPC11_IOCON_BASE + LPC11_IOCON_P1_0_OFFSET)
#define LPC11_IOCON_P1_1 (LPC11_IOCON_BASE + LPC11_IOCON_P1_1_OFFSET)
#define LPC11_IOCON_P1_2 (LPC11_IOCON_BASE + LPC11_IOCON_P1_2_OFFSET)
#define LPC11_IOCON_P1_3 (LPC11_IOCON_BASE + LPC11_IOCON_P1_3_OFFSET)
#define LPC11_IOCON_P1_4 (LPC11_IOCON_BASE + LPC11_IOCON_P1_4_OFFSET)
#define LPC11_IOCON_P1_5 (LPC11_IOCON_BASE + LPC11_IOCON_P1_5_OFFSET)
#define LPC11_IOCON_P1_6 (LPC11_IOCON_BASE + LPC11_IOCON_P1_6_OFFSET)
#define LPC11_IOCON_P1_7 (LPC11_IOCON_BASE + LPC11_IOCON_P1_7_OFFSET)
#define LPC11_IOCON_P1_8 (LPC11_IOCON_BASE + LPC11_IOCON_P1_8_OFFSET)
#define LPC11_IOCON_P1_9 (LPC11_IOCON_BASE + LPC11_IOCON_P1_9_OFFSET)
#define LPC11_IOCON_P1_10 (LPC11_IOCON_BASE + LPC11_IOCON_P1_10_OFFSET)
#define LPC11_IOCON_P1_11 (LPC11_IOCON_BASE + LPC11_IOCON_P1_11_OFFSET)
#define LPC11_IOCON_P2_0 (LPC11_IOCON_BASE + LPC11_IOCON_P2_0_OFFSET)
#define LPC11_IOCON_P2_1 (LPC11_IOCON_BASE + LPC11_IOCON_P2_1_OFFSET)
#define LPC11_IOCON_P2_2 (LPC11_IOCON_BASE + LPC11_IOCON_P2_2_OFFSET)
#define LPC11_IOCON_P2_3 (LPC11_IOCON_BASE + LPC11_IOCON_P2_3_OFFSET)
#define LPC11_IOCON_P2_4 (LPC11_IOCON_BASE + LPC11_IOCON_P2_4_OFFSET)
#define LPC11_IOCON_P2_5 (LPC11_IOCON_BASE + LPC11_IOCON_P2_5_OFFSET)
#define LPC11_IOCON_P2_6 (LPC11_IOCON_BASE + LPC11_IOCON_P2_6_OFFSET)
#define LPC11_IOCON_P2_7 (LPC11_IOCON_BASE + LPC11_IOCON_P2_7_OFFSET)
#define LPC11_IOCON_P2_8 (LPC11_IOCON_BASE + LPC11_IOCON_P2_8_OFFSET)
#define LPC11_IOCON_P2_9 (LPC11_IOCON_BASE + LPC11_IOCON_P2_9_OFFSET)
#define LPC11_IOCON_P2_10 (LPC11_IOCON_BASE + LPC11_IOCON_P2_10_OFFSET)
#define LPC11_IOCON_P2_11 (LPC11_IOCON_BASE + LPC11_IOCON_P2_11_OFFSET)
#define LPC11_IOCON_P3_0 (LPC11_IOCON_BASE + LPC11_IOCON_P3_0_OFFSET)
#define LPC11_IOCON_P3_1 (LPC11_IOCON_BASE + LPC11_IOCON_P3_1_OFFSET)
#define LPC11_IOCON_P3_2 (LPC11_IOCON_BASE + LPC11_IOCON_P3_2_OFFSET)
#define LPC11_IOCON_P3_3 (LPC11_IOCON_BASE + LPC11_IOCON_P3_3_OFFSET)
#define LPC11_IOCON_P3_4 (LPC11_IOCON_BASE + LPC11_IOCON_P3_4_OFFSET)
#define LPC11_IOCON_P3_5 (LPC11_IOCON_BASE + LPC11_IOCON_P3_5_OFFSET)
#define LPC11_IOCON_SCK_LOC (LPC11_IOCON_BASE + LPC11_IOCON_SCK_LOC_OFFSET)
#define LPC11_IOCON_DSR_LOC (LPC11_IOCON_BASE + LPC11_IOCON_DSR_LOC_OFFSET)
#define LPC11_IOCON_DCD_LOC (LPC11_IOCON_BASE + LPC11_IOCON_DCD_LOC_OFFSET)
#define LPC11_IOCON_RI_LOC (LPC11_IOCON_BASE + LPC11_IOCON_RI_LOC_OFFSET)
/* Register bit definitions *********************************************************/
/* IOCON pin function select */
#define IOCON_FUNC_GPIO (0)
#define IOCON_FUNC_ALT1 (1)
#define IOCON_FUNC_ALT2 (2)
#define IOCON_FUNC_ALT3 (3)
#define IOCON_FUNC_ALT4 (4)
#define IOCON_FUNC_ALT5 (5)
#define IOCON_FUNC_ALT6 (6)
#define IOCON_FUNC_ALT7 (7)
#define IOCON_FUNC_SHIFT (0) /* Bits 0-2: All types */
#define IOCON_FUNC_MASK (7 << IOCON_FUNC_SHIFT)
#define IOCON_MODE_SHIFT (3) /* Bits 3-4: Type D,A,W */
#define IOCON_MODE_MASK (3 << IOCON_MODE_SHIFT )
#define IOCON_HYS_SHIFT (5) /* Bit 5: Type D,W */
#define IOCON_HYS_MASK (1 << IOCON_HYS_SHIFT)
/* Bit 6-9: Reserved */
#define IOCON_OD_SHIFT (10) /* Bit 10: Type D,A,W */
#define IOCON_OD_MASK (1 << IOCON_OD_SHIFT)
/* Bit 11-31: Reserved */
/* Pin modes */
#define IOCON_MODE_FLOAT (0) /* 00: pin has neither pull-up nor pull-down */
#define IOCON_MODE_PD (1) /* 01: pin has a pull-down resistor enabled */
#define IOCON_MODE_PU (2) /* 10: pin has a pull-up resistor enabled */
#define IOCON_MODE_RM (3) /* 11: pin has repeater mode enabled */
/* Pin types */
#define IOCON_TYPE_D_MASK (0x0000067f) /* All ports except where ADC/DAC, USB, I2C is present */
#define IOCON_TYPE_A_MASK (0x000105df) /* USB/ADC/DAC P0:12-13, P0:23-26, P1:30-31 */
#define IOCON_TYPE_U_MASK (0x00000007) /* USB P0:29 to 31 */
#define IOCON_TYPE_I_MASK (0x00000347) /* I2C/USB P0:27-28, P5:2-3 */
#define IOCON_TYPE_W_MASK (0x000007ff) /* I2S P0:7-9 */
/* Analog/Digital mode */
#define IOCON_ADMODE_SHIFT (7)
#define IOCON_ADMODE_ANALOG (0 << IOCON_ADMODE_SHIFT)
#define IOCON_ADMODE_DIGITAL (1 << IOCON_ADMODE_SHIFT)
/* I2C modes */
#define IOCON_I2CMODE_SHIFT (8)
#define IOCON_I2CMODE_MASK (3 << IOCON_I2CMODE_SHIFT)
# define IOCON_I2CMODE_STANDARD (0 << IOCON_I2CMODE_SHIFT)
# define IOCON_I2CMODE_STANDIO (1 << IOCON_I2CMODE_SHIFT)
# define IOCON_I2CMODE_FASTPLUS (2 << IOCON_I2CMODE_SHIFT)
/*(3 << IOCON_I2CMODE_SHIFT) Reserved */
/* Bits 10-31: Reserved */
/* SCK location register */
#define IOCON_SCK_LOC_SHIFT (0)
#define IOCON_SCK_LOC_MASK (3 << IOCON_SCK_LOC_SHIFT)
# define IOCON_SCK_LOC_SWCLK (0 << IOCON_SCK_LOC_SHIFT)
# define IOCON_SCK_LOC_PIO2_11 (1 << IOCON_SCK_LOC_SHIFT)
# define IOCON_SCK_LOC_PIO0_6 (2 << IOCON_SCK_LOC_SHIFT)
/*(3 << IOCON_SCK_LOC_SHIFT) Reserved */
/* Bits 2-31: Reserved */
/* DSR location register */
#define IOCON_DSR_LOC_SHIFT (0)
#define IOCON_DSR_LOC_MASK (3 << IOCON_DSR_LOC_SHIFT)
# define IOCON_DSR_LOC_PIO2_1 (0 << IOCON_DSR_LOC_SHIFT)
# define IOCON_DSR_LOC_PIO3_1 (1 << IOCON_DSR_LOC_SHIFT)
/*(2 << IOCON_DSR_LOC_SHIFT) Reserved */
/*(3 << IOCON_DSR_LOC_SHIFT) Reserved */
/* Bits 2-31: Reserved */
/* DCD location register */
#define IOCON_DCD_LOC_SHIFT (0)
#define IOCON_DCD_LOC_MASK (3 << IOCON_DCD_LOC_SHIFT)
# define IOCON_DCD_LOC_PIO2_2 (0 << IOCON_DCD_LOC_SHIFT)
# define IOCON_DCD_LOC_PIO3_2 (1 << IOCON_DCD_LOC_SHIFT)
/*(2 << IOCON_DCD_LOC_SHIFT) Reserved */
/*(3 << IOCON_DCD_LOC_SHIFT) Reserved */
/* Bits 2-31: Reserved */
/* RI location register */
#define IOCON_RI_LOC_SHIFT (0)
#define IOCON_RI_LOC_MASK (3 << IOCON_RI_LOC_SHIFT)
# define IOCON_RI_LOC_PIO2_3 (0 << IOCON_RI_LOC_SHIFT)
# define IOCON_RI_LOC_PIO3_3 (1 << IOCON_RI_LOC_SHIFT)
/*(2 << IOCON_RI_LOC_SHIFT) Reserved */
/*(3 << IOCON_RI_LOC_SHIFT) Reserved */
/* Bits 2-31: Reserved */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC118X_IOCON_H */
arch/arm/src/lpc11xx/hardware/lpc111x_memorymap.h
-107
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/************************************************************************************
* arch/arm/src/lpc11xx/hardware/lpc111x_memorymap.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC111X_MEMORYMAP_H
#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC111X_MEMORYMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Memory Map ***********************************************************************/
#define LPC11_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatile memory */
#define LPC11_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=16Kb) */
#define LPC11_ROM_BASE 0x1fff0000 /* -0x1fffffff: 16Kb Boot ROM with flash services */
#define LPC11_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */
#define LPC11_GPIO_BASE 0x50000000 /* -0x2009ffff: GPIO at AHB Peripherals */
#define LPC11_APB_BASE 0x40000000 /* -0x4007ffff: APB Peripherals */
#define LPC11_AHB_BASE 0x50000000 /* -0x501fffff: AHB Peripherals */
#define LPC11_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */
#define LPC11_SCS_BASE 0xe000e000
#define LPC11_DEBUGMCU_BASE 0xe0042000
/* APB Peripherals *****************************************************************/
#define LPC11_I2C0_BASE 0x40000000 /* -0x40003fff: I2C-bus */
#define LPC11_WDT_BASE 0x40004000 /* -0x40007fff: Watchdog timer */
#define LPC11_UART0_BASE 0x40008000 /* -0x4000bfff: UART 0 */
#define LPC11_TMR0_BASE 0x4000c000 /* -0x4000ffff: Timer 0 */
#define LPC11_TMR1_BASE 0x40010000 /* -0x40013fff: Timer 1 */
#define LPC11_TMR2_BASE 0x40014000 /* -0x40017fff: Timer 0 */
#define LPC11_TMR3_BASE 0x40018000 /* -0x4001bfff: Timer 1 */
#define LPC11_ADC_BASE 0x4001c000 /* -0x4001ffff: ADC */
/* -0x40037fff: Reserved */
#define LPC11_PMU_BASE 0x40038000 /* -0x4003bfff: PMU */
/* -0x40017fff: Reserved */
#define LPC11_FLASHC_BASE 0x4003c000 /* -0x4003ffff: Flash Controller */
#define LPC11_SPI0_BASE 0x40040000 /* -0x40043fff: SPI0 */
#define LPC11_IOCON_BASE 0x40044000 /* -0x40047fff: IOCONFIG */
#define LPC11_SYSCON_BASE 0x40048000 /* -0x4004bfff: System Control */
/* -0x4004ffff: Reserved */
#define LPC11_CAN0_BASE 0x40050000 /* -0x40053fff: CAN0 */
/* -0x40057ffff: Reserved */
#define LPC11_SPI1_BASE 0x40058000 /* -0x4005bffff: SPI1 */
/* -0x4007fffff: Reserved */
/* AHB Peripherals ******************************************************************/
#define LPC11_GPIO_PIO0 (LPC11_GPIO_BASE + 0) /* -0x5000ffff: GPIO PIO0 */
#define LPC11_GPIO_PIO1 (LPC11_GPIO_BASE + 0x10000) /* -0x5001ffff: GPIO PIO1 */
#define LPC11_GPIO_PIO2 (LPC11_GPIO_BASE + 0x20000) /* -0x5002ffff: GPIO PIO1 */
#define LPC11_GPIO_PIO3 (LPC11_GPIO_BASE + 0x30000) /* -0x5003ffff: GPIO PIO1 */
/* -0x501fffff: Reserved */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC116X_MEMORYMAP_H */
arch/arm/src/lpc11xx/hardware/lpc111x_pinconfig.h
-122
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@@ -1,122 +0,0 @@
/************************************************************************************
* arch/arm/src/lpc11xx/hardware/lpc111x_pinconfig.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC111X_PINCONFIG_H
#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC111X_PINCONFIG_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* GPIO pin definitions *************************************************************/
/* NOTE that functions have a alternate pins that can be selected. These alternates
* are identified with a numeric suffix like _1, _2, or _3. Your board.h file
* should select the correct alternative for your board by including definitions
* such as:
*
* #define GPIO_UART1_RXD GPIO_UART1_RXD_1
*
* (without the suffix)
*/
#ifdef CONFIG_ARCH_CHIP_LPC1115
#define GPIO_CLKOUT (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1)
#define GPIO_CT32B0_MAT2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1)
#define GPIO_SPI0_SSEL (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2)
#define GPIO_CT16B0_CAP0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2)
#define GPIO_I2C0_SCL (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4)
#define GPIO_I2C0_SDA (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5)
#define GPIO_SPI0_SCK_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6)
#define GPIO_UART0_CTS (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7)
#define GPIO_SPI0_MISO (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8)
#define GPIO_CT16B0_MAT0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8)
#define GPIO_SPI0_MOSI (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9)
#define GPIO_CT16B0_MAT1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9)
#define GPIO_JTAG_SWCLK (GPIO_ALT0 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10)
#define GPIO_PIO0_10 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10)
#define GPIO_SPI0_SCK (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10)
#define GPIO_CT16B0_MAT2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10)
#define GPIO_PIO0_11 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11)
#define GPIO_AD_inp0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11)
#define GPIO_CT32B0_MAT3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11)
#define GPIO_PIO1_0 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0)
#define GPIO_AD_inp1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0)
#define GPIO_CT32B1_CAP0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0)
#define GPIO_PIO1_1 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1)
#define GPIO_AD_inp2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1)
#define GPIO_CT32B1_MAT0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1)
#define GPIO_PIO1_2 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN2)
#define GPIO_AD_inp3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN2)
#define GPIO_CT32B1_MAT1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN2)
#define GPIO_JTAG_SWDIO (GPIO_ALT0 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3)
#define GPIO_PIO1_3 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3)
#define GPIO_AD_inp4 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3)
#define GPIO_CT32B1_MAT2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3)
#define GPIO_AD_inp5 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN4)
#define GPIO_CT32B1_MAT3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN4)
#define GPIO_UART0_RTS (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN5)
#define GPIO_CT32B0_CAP0 (GPIO_ALT2 | GPIO_PULLDN | GPIO_PORT1 | GPIO_PIN5)
#define GPIO_UART0_RXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN6)
#define GPIO_CT32B0_MAT0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN6)
#define GPIO_UART0_TXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN7)
#define GPIO_CT32B0_MAT1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN7)
#define GPIO_CT16B1_CAP0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN8)
#define GPIO_CT16B1_MAT0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN9)
#define GPIO_AD_inp6 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN10)
#define GPIO_CT16B1_MAT1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN10)
#define GPIO_AD_inp7 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN11)
#define GPIO_UART0_DTR (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN0)
#endif /* CONFIG_ARCH_CHIP_LPC1115 */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC116X_PINCONFIG_H */
arch/arm/src/lpc11xx/hardware/lpc11_adc.h
-171
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@@ -1,171 +0,0 @@
/************************************************************************************
* arch/arm/src/lpc11xx/hardware/lpc11_adc.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_CHIP_ADC_H
#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_CHIP_ADC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/lpc11_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register offsets *****************************************************************/
#define LPC11_ADC_CR_OFFSET 0x0000 /* A/D Control Register */
#define LPC11_ADC_GDR_OFFSET 0x0004 /* A/D Global Data Register */
#define LPC11_ADC_INTEN_OFFSET 0x000c /* A/D Interrupt Enable Register */
#define LPC11_ADC_DR_OFFSET(n) (0x0010+((n) << 2))
#define LPC11_ADC_DR0_OFFSET 0x0010 /* A/D Channel 0 Data Register */
#define LPC11_ADC_DR1_OFFSET 0x0014 /* A/D Channel 1 Data Register */
#define LPC11_ADC_DR2_OFFSET 0x0018 /* A/D Channel 2 Data Register */
#define LPC11_ADC_DR3_OFFSET 0x001c /* A/D Channel 3 Data Register */
#define LPC11_ADC_DR4_OFFSET 0x0020 /* A/D Channel 4 Data Register */
#define LPC11_ADC_DR5_OFFSET 0x0024 /* A/D Channel 5 Data Register */
#define LPC11_ADC_DR6_OFFSET 0x0028 /* A/D Channel 6 Data Register */
#define LPC11_ADC_DR7_OFFSET 0x002c /* A/D Channel 7 Data Register */
#define LPC11_ADC_STAT_OFFSET 0x0030 /* A/D Status Register */
/* Register addresses ***************************************************************/
#define LPC11_ADC_CR (LPC11_ADC_BASE+LPC11_ADC_CR_OFFSET)
#define LPC11_ADC_GDR (LPC11_ADC_BASE+LPC11_ADC_GDR_OFFSET)
#define LPC11_ADC_INTEN (LPC11_ADC_BASE+LPC11_ADC_INTEN_OFFSET)
#define LPC11_ADC_DR(n) (LPC11_ADC_BASE+LPC11_ADC_DR_OFFSET(n))
#define LPC11_ADC_DR0 (LPC11_ADC_BASE+LPC11_ADC_DR0_OFFSET)
#define LPC11_ADC_DR1 (LPC11_ADC_BASE+LPC11_ADC_DR1_OFFSET)
#define LPC11_ADC_DR2 (LPC11_ADC_BASE+LPC11_ADC_DR2_OFFSET)
#define LPC11_ADC_DR3 (LPC11_ADC_BASE+LPC11_ADC_DR3_OFFSET)
#define LPC11_ADC_DR4 (LPC11_ADC_BASE+LPC11_ADC_DR4_OFFSET)
#define LPC11_ADC_DR5 (LPC11_ADC_BASE+LPC11_ADC_DR5_OFFSET)
#define LPC11_ADC_DR6 (LPC11_ADC_BASE+LPC11_ADC_DR6_OFFSET)
#define LPC11_ADC_DR7 (LPC11_ADC_BASE+LPC11_ADC_DR7_OFFSET)
#define LPC11_ADC_STAT (LPC11_ADC_BASE+LPC11_ADC_STAT_OFFSET)
/* Register bit definitions *********************************************************/
/* A/D Control Register */
#define ADC_CR_SEL_SHIFT (0) /* Bits 0-7: Selects pins to be sampled */
#define ADC_CR_SEL_MASK (0xff << ADC_CR_SEL_MASK)
#define ADC_CR_CLKDIV_SHIFT (8) /* Bits 8-15: APB clock (PCLK_ADC0) divisor */
#define ADC_CR_CLKDIV_MASK (0xff << ADC_CR_CLKDIV_SHIFT)
#define ADC_CR_BURST (1 << 16) /* Bit 16: A/D Repeated conversions */
#define ADC_CR_CLKS_SHIFT (17) /* Bits 17-19: Clocks used on burst mode conv. */
#define ADC_CR_CLKS_MASK (3 << ADC_CR_CLKS_SHIFT)
/* Bits 20-23: Reserved */
#define ADC_CR_START_SHIFT (24) /* Bits 24-26: Control A/D conversion start */
#define ADC_CR_START_MASK (7 << ADC_CR_START_SHIFT)
# define ADC_CR_START_NOSTART (0 << ADC_CR_START_SHIFT) /* No start */
# define ADC_CR_START_NOW (1 << ADC_CR_START_SHIFT) /* Start now */
# define ADC_CR_START_P0p2 (2 << ADC_CR_START_SHIFT) /* Start edge on P0.2/SSEL/CT16B0_CAP0 */
# define ADC_CR_START_P1p5 (3 << ADC_CR_START_SHIFT) /* Start edge on P1.5/DIR/CT32B0_CAP0 */
# define ADC_CR_START_CT32B0MAT0 (4 << ADC_CR_START_SHIFT) /* Start edge on Counter/Timer32 MAT0 */
# define ADC_CR_START_CT32B0MAT1 (5 << ADC_CR_START_SHIFT) /* Start edge on Counter/Timer32 MAT1 */
# define ADC_CR_START_CT16B0MAT0 (6 << ADC_CR_START_SHIFT) /* Start edge on Counter/Timer16 MAT0 */
# define ADC_CR_START_CT16B0MAT1 (7 << ADC_CR_START_SHIFT) /* Start edge on Counter/Timer16 MAT1 */
#define ADC_CR_EDGE (1 << 27) /* Bit 27: Start on falling edge */
/* Bits 28-31: Reserved */
/* A/D Global Data Register AND Channel 0-7 Data Register */
/* Bits 0-5: Reserved */
#define ADC_DR_RESULT_SHIFT (5) /* Bits 6-15: Result of conversion (DONE==1) */
#define ADC_DR_RESULT_MASK (0x3ff << ADC_DR_RESULT_SHIFT)
/* Bits 16-23: Reserved */
#define ADC_DR_CHAN_SHIFT (24) /* Bits 24-26: Channel converted */
#define ADC_DR_CHAN_MASK (3 << ADC_DR_CHN_SHIFT)
/* Bits 27-29: Reserved */
#define ADC_DR_OVERRUN (1 << 30) /* Bit 30: Conversion(s) lost/overwritten*/
#define ADC_DR_DONE (1 << 31) /* Bit 31: A/D conversion complete*/
/* A/D Interrupt Enable Register */
#define ADC_INTEN_CHAN(n) (1 << (n))
#define ADC_INTEN_CHAN0 (1 << 0) /* Bit 0: Enable ADC chan 0 complete intterrupt */
#define ADC_INTEN_CHAN1 (1 << 1) /* Bit 1: Enable ADC chan 1 complete interrupt */
#define ADC_INTEN_CHAN2 (1 << 2) /* Bit 2: Enable ADC chan 2 complete interrupt */
#define ADC_INTEN_CHAN3 (1 << 3) /* Bit 3: Enable ADC chan 3 complete interrupt */
#define ADC_INTEN_CHAN4 (1 << 4) /* Bit 4: Enable ADC chan 4 complete interrupt */
#define ADC_INTEN_CHAN5 (1 << 5) /* Bit 5: Enable ADC chan 5 complete interrupt */
#define ADC_INTEN_CHAN6 (1 << 6) /* Bit 6: Enable ADC chan 6 complete interrupt */
#define ADC_INTEN_CHAN7 (1 << 7) /* Bit 7: Enable ADC chan 7 complete interrupt */
#define ADC_INTEN_GLOBAL (1 << 8) /* Bit 8: Only the global DONE generates interrupt */
/* Bits 9-31: Reserved */
/* A/D Status Register */
#define ADC_STAT_DONE(n) (1 << (n))
#define ADC_STAT_DONE0 (1 << 0) /* Bit 0: A/D chan 0 DONE */
#define ADC_STAT_DONE1 (1 << 1) /* Bit 1: A/D chan 1 DONE */
#define ADC_STAT_DONE2 (1 << 2) /* Bit 2: A/D chan 2 DONE */
#define ADC_STAT_DONE3 (1 << 3) /* Bit 3: A/D chan 3 DONE */
#define ADC_STAT_DONE4 (1 << 4) /* Bit 4: A/D chan 4 DONE */
#define ADC_STAT_DONE5 (1 << 5) /* Bit 5: A/D chan 5 DONE */
#define ADC_STAT_DONE6 (1 << 6) /* Bit 6: A/D chan 6 DONE */
#define ADC_STAT_DONE7 (1 << 7) /* Bit 7: A/D chan 7 DONE */
#define ADC_STAT_OVERRUN(n) ((1 << (n)) + 8)
#define ADC_STAT_OVERRUN0 (1 << 8) /* Bit 8: A/D chan 0 OVERRUN */
#define ADC_STAT_OVERRUN1 (1 << 9) /* Bit 9: A/D chan 1 OVERRUN */
#define ADC_STAT_OVERRUN2 (1 << 10) /* Bit 10: A/D chan 2 OVERRUN */
#define ADC_STAT_OVERRUN3 (1 << 11) /* Bit 11: A/D chan 3 OVERRUN */
#define ADC_STAT_OVERRUN4 (1 << 12) /* Bit 12: A/D chan 4 OVERRUN */
#define ADC_STAT_OVERRUN5 (1 << 13) /* Bit 13: A/D chan 5 OVERRUN */
#define ADC_STAT_OVERRUN6 (1 << 14) /* Bit 14: A/D chan 6 OVERRUN */
#define ADC_STAT_OVERRUN7 (1 << 15) /* Bit 15: A/D chan 7 OVERRUN */
#define ADC_STAT_INT (1 << 16) /* Bit 15: A/D interrupt */
/* Bits 17-31: Reserved */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_CHIP_ADC_H */
arch/arm/src/lpc11xx/hardware/lpc11_gpio.h
-146
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@@ -1,146 +0,0 @@
/************************************************************************************
* arch/arm/src/lpc11xx/hardware/lpc11_gpio.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_CHIP_GPIO_H
#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_CHIP_GPIO_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/lpc11_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register offsets *****************************************************************/
/* GPIO block register offsets ******************************************************/
#define LPC11_GPIO0_OFFSET 0x00000
#define LPC11_GPIO1_OFFSET 0x10000
#define LPC11_GPIO2_OFFSET 0x20000
#define LPC11_GPIO3_OFFSET 0x30000
#define LPC11_GPIO_OFFSET(n) (0x10000*(n))
#define LPC11_GPIO_DATA_OFFSET 0x3FFC
#define LPC11_GPIO_DIR_OFFSET 0x8000 /* GPIO Port Direction control */
#define LPC11_GPIO_IS_OFFSET 0x8004 /* Interrupt Sense register */
#define LPC11_GPIO_IBE_OFFSET 0x8008 /* Interrupt Both Edges register */
#define LPC11_GPIO_IEV_OFFSET 0x800c /* Interrupt Event register */
#define LPC11_GPIO_IE_OFFSET 0x8010 /* Interrupt Mask register */
#define LPC11_GPIO_RIS_OFFSET 0x8014 /* Raw interrupt status register */
#define LPC11_GPIO_MIS_OFFSET 0x8018 /* Masked interrupt status register */
#define LPC11_GPIO_IC_OFFSET 0x801c /* Interrupt clear register */
/* Register addresses ***************************************************************/
/* GPIO block register addresses ****************************************************/
#define LPC11_GPIOn_BASE(n) (LPC11_GPIO_BASE+LPC11_GPIO_OFFSET(n))
#define LPC11_GPIO0_BASE (LPC11_GPIO_BASE+LPC11_GPIO0_OFFSET)
#define LPC11_GPIO1_BASE (LPC11_GPIO_BASE+LPC11_GPIO1_OFFSET)
#define LPC11_GPIO2_BASE (LPC11_GPIO_BASE+LPC11_GPIO2_OFFSET)
#define LPC11_GPIO3_BASE (LPC11_GPIO_BASE+LPC11_GPIO3_OFFSET)
#define LPC11_GPIO_DIR(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_DIR_OFFSET) /* GPIO Port Direction register */
#define LPC11_GPIO_IS(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IS_OFFSET) /* GPIO Interrupt Sense register */
#define LPC11_GPIO_IBE(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IBE_OFFSET) /* GPIO Interrupt Both Edges sense register */
#define LPC11_GPIO_IEV(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IVE_OFFSET) /* GPIO Interrupt Event register */
#define LPC11_GPIO_IE(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IE_OFFSET) /* GPIO Interrupt Mask register */
#define LPC11_GPIO_RIS(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_RIS_OFFSET) /* GPIO Raw Interrupt Status register */
#define LPC11_GPIO_MIS(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_MIS_OFFSET) /* GPIO Masked Interrupt Status register */
#define LPC11_GPIO_IC(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IC_OFFSET) /* GPIO Interrupt Clear register */
#define LPC11_GPIO0_DATA (LPC11_GPIO0_BASE+LPC11_GPIO_DATA_OFFSET)
#define LPC11_GPIO0_DIR (LPC11_GPIO0_BASE+LPC11_GPIO_DIR_OFFSET)
#define LPC11_GPIO0_IS (LPC11_GPIO0_BASE+LPC11_GPIO_IS_OFFSET)
#define LPC11_GPIO0_IBE (LPC11_GPIO0_BASE+LPC11_GPIO_IBE_OFFSET)
#define LPC11_GPIO0_IEV (LPC11_GPIO0_BASE+LPC11_GPIO_IVE_OFFSET)
#define LPC11_GPIO0_IE (LPC11_GPIO0_BASE+LPC11_GPIO_IE_OFFSET)
#define LPC11_GPIO0_RIS (LPC11_GPIO0_BASE+LPC11_GPIO_RIS_OFFSET)
#define LPC11_GPIO0_MIS (LPC11_GPIO0_BASE+LPC11_GPIO_MIS_OFFSET)
#define LPC11_GPIO0_IC (LPC11_GPIO0_BASE+LPC11_GPIO_IC_OFFSET)
#define LPC11_GPIO1_DATA (LPC11_GPIO1_BASE+LPC11_GPIO_DATA_OFFSET)
#define LPC11_GPIO1_DIR (LPC11_GPIO1_BASE+LPC11_GPIO_DIR_OFFSET)
#define LPC11_GPIO1_IS (LPC11_GPIO1_BASE+LPC11_GPIO_IS_OFFSET)
#define LPC11_GPIO1_IBE (LPC11_GPIO1_BASE+LPC11_GPIO_IBE_OFFSET)
#define LPC11_GPIO1_IEV (LPC11_GPIO1_BASE+LPC11_GPIO_IVE_OFFSET)
#define LPC11_GPIO1_IE (LPC11_GPIO1_BASE+LPC11_GPIO_IE_OFFSET)
#define LPC11_GPIO1_RIS (LPC11_GPIO1_BASE+LPC11_GPIO_RIS_OFFSET)
#define LPC11_GPIO1_MIS (LPC11_GPIO1_BASE+LPC11_GPIO_MIS_OFFSET)
#define LPC11_GPIO1_IC (LPC11_GPIO1_BASE+LPC11_GPIO_IC_OFFSET)
#define LPC11_GPIO2_DATA (LPC11_GPIO2_BASE+LPC11_GPIO_DATA_OFFSET)
#define LPC11_GPIO2_DIR (LPC11_GPIO2_BASE+LPC11_GPIO_DIR_OFFSET)
#define LPC11_GPIO2_IS (LPC11_GPIO2_BASE+LPC11_GPIO_IS_OFFSET)
#define LPC11_GPIO2_IBE (LPC11_GPIO2_BASE+LPC11_GPIO_IBE_OFFSET)
#define LPC11_GPIO2_IEV (LPC11_GPIO2_BASE+LPC11_GPIO_IVE_OFFSET)
#define LPC11_GPIO2_IE (LPC11_GPIO2_BASE+LPC11_GPIO_IE_OFFSET)
#define LPC11_GPIO2_RIS (LPC11_GPIO2_BASE+LPC11_GPIO_RIS_OFFSET)
#define LPC11_GPIO2_MIS (LPC11_GPIO2_BASE+LPC11_GPIO_MIS_OFFSET)
#define LPC11_GPIO2_IC (LPC11_GPIO2_BASE+LPC11_GPIO_IC_OFFSET)
#define LPC11_GPIO3_DATA (LPC11_GPIO3_BASE+LPC11_GPIO_DATA_OFFSET)
#define LPC11_GPIO3_DIR (LPC11_GPIO3_BASE+LPC11_GPIO_DIR_OFFSET)
#define LPC11_GPIO3_IS (LPC11_GPIO3_BASE+LPC11_GPIO_IS_OFFSET)
#define LPC11_GPIO3_IBE (LPC11_GPIO3_BASE+LPC11_GPIO_IBE_OFFSET)
#define LPC11_GPIO3_IEV (LPC11_GPIO3_BASE+LPC11_GPIO_IVE_OFFSET)
#define LPC11_GPIO3_IE (LPC11_GPIO3_BASE+LPC11_GPIO_IE_OFFSET)
#define LPC11_GPIO3_RIS (LPC11_GPIO3_BASE+LPC11_GPIO_RIS_OFFSET)
#define LPC11_GPIO3_MIS (LPC11_GPIO3_BASE+LPC11_GPIO_MIS_OFFSET)
#define LPC11_GPIO3_IC (LPC11_GPIO3_BASE+LPC11_GPIO_IC_OFFSET)
/* Register bit definitions *********************************************************/
/* GPIO block register bit definitions **********************************************/
#define GPIO(n) (1 << (n)) /* n=0,1,..11 */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_CHIP_GPIO_H */
arch/arm/src/lpc11xx/hardware/lpc11_i2c.h
-208
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@@ -1,208 +0,0 @@
/************************************************************************************
* arch/arm/src/lpc11xx/hardware/lpc11_i2c.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_I2C_H
#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_I2C_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/lpc11_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register offsets *****************************************************************/
#define LPC11_I2C_CONSET_OFFSET 0x0000 /* I2C Control Set Register */
#define LPC11_I2C_STAT_OFFSET 0x0004 /* I2C Status Register */
#define LPC11_I2C_DAT_OFFSET 0x0008 /* I2C Data Register */
#define LPC11_I2C_ADR0_OFFSET 0x000c /* I2C Slave Address Register 0 */
#define LPC11_I2C_SCLH_OFFSET 0x0010 /* SCH Duty Cycle Register High Half Word */
#define LPC11_I2C_SCLL_OFFSET 0x0014 /* SCL Duty Cycle Register Low Half Word */
#define LPC11_I2C_CONCLR_OFFSET 0x0018 /* I2C Control Clear Register */
#define LPC11_I2C_MMCTRL_OFFSET 0x001c /* Monitor mode control register */
#define LPC11_I2C_ADR1_OFFSET 0x0020 /* I2C Slave Address Register 1 */
#define LPC11_I2C_ADR2_OFFSET 0x0024 /* I2C Slave Address Register 2 */
#define LPC11_I2C_ADR3_OFFSET 0x0028 /* I2C Slave Address Register 3 */
#define LPC11_I2C_BUFR_OFFSET 0x002c /* Data buffer register */
#define LPC11_I2C_MASK0_OFFSET 0x0030 /* I2C Slave address mask register 0 */
#define LPC11_I2C_MASK1_OFFSET 0x0034 /* I2C Slave address mask register 1 */
#define LPC11_I2C_MASK2_OFFSET 0x0038 /* I2C Slave address mask register 2 */
#define LPC11_I2C_MASK3_OFFSET 0x003c /* I2C Slave address mask register */
/* Register addresses ***************************************************************/
#define LPC11_I2C0_CONSET (LPC11_I2C0_BASE+LPC11_I2C_CONSET_OFFSET)
#define LPC11_I2C0_STAT (LPC11_I2C0_BASE+LPC11_I2C_STAT_OFFSET)
#define LPC11_I2C0_DAT (LPC11_I2C0_BASE+LPC11_I2C_DAT_OFFSET)
#define LPC11_I2C0_ADR0 (LPC11_I2C0_BASE+LPC11_I2C_ADR0_OFFSET)
#define LPC11_I2C0_SCLH (LPC11_I2C0_BASE+LPC11_I2C_SCLH_OFFSET)
#define LPC11_I2C0_SCLL (LPC11_I2C0_BASE+LPC11_I2C_SCLL_OFFSET)
#define LPC11_I2C0_CONCLR (LPC11_I2C0_BASE+LPC11_I2C_CONCLR_OFFSET)
#define LPC11_I2C0_MMCTRL (LPC11_I2C0_BASE+LPC11_I2C_MMCTRL_OFFSET)
#define LPC11_I2C0_ADR1 (LPC11_I2C0_BASE+LPC11_I2C_ADR1_OFFSET)
#define LPC11_I2C0_ADR2 (LPC11_I2C0_BASE+LPC11_I2C_ADR2_OFFSET)
#define LPC11_I2C0_ADR3 (LPC11_I2C0_BASE+LPC11_I2C_ADR3_OFFSET)
#define LPC11_I2C0_BUFR (LPC11_I2C0_BASE+LPC11_I2C_BUFR_OFFSET)
#define LPC11_I2C0_MASK0 (LPC11_I2C0_BASE+LPC11_I2C_MASK0_OFFSET)
#define LPC11_I2C0_MASK1 (LPC11_I2C0_BASE+LPC11_I2C_MASK1_OFFSET)
#define LPC11_I2C0_MASK2 (LPC11_I2C0_BASE+LPC11_I2C_MASK2_OFFSET)
#define LPC11_I2C0_MASK3 (LPC11_I2C0_BASE+LPC11_I2C_MASK3_OFFSET)
#define LPC11_I2C1_CONSET (LPC11_I2C1_BASE+LPC11_I2C_CONSET_OFFSET)
#define LPC11_I2C1_STAT (LPC11_I2C1_BASE+LPC11_I2C_STAT_OFFSET)
#define LPC11_I2C1_DAT (LPC11_I2C1_BASE+LPC11_I2C_DAT_OFFSET)
#define LPC11_I2C1_ADR0 (LPC11_I2C1_BASE+LPC11_I2C_ADR0_OFFSET)
#define LPC11_I2C1_SCLH (LPC11_I2C1_BASE+LPC11_I2C_SCLH_OFFSET)
#define LPC11_I2C1_SCLL (LPC11_I2C1_BASE+LPC11_I2C_SCLL_OFFSET)
#define LPC11_I2C1_CONCLR (LPC11_I2C1_BASE+LPC11_I2C_CONCLR_OFFSET)
#define LPC11_I2C1_MMCTRL (LPC11_I2C1_BASE+LPC11_I2C_MMCTRL_OFFSET)
#define LPC11_I2C1_ADR1 (LPC11_I2C1_BASE+LPC11_I2C_ADR1_OFFSET)
#define LPC11_I2C1_ADR2 (LPC11_I2C1_BASE+LPC11_I2C_ADR2_OFFSET)
#define LPC11_I2C1_ADR3 (LPC11_I2C1_BASE+LPC11_I2C_ADR3_OFFSET)
#define LPC11_I2C1_BUFR (LPC11_I2C1_BASE+LPC11_I2C_BUFR_OFFSET)
#define LPC11_I2C1_MASK0 (LPC11_I2C1_BASE+LPC11_I2C_MASK0_OFFSET)
#define LPC11_I2C1_MASK1 (LPC11_I2C1_BASE+LPC11_I2C_MASK1_OFFSET)
#define LPC11_I2C1_MASK2 (LPC11_I2C1_BASE+LPC11_I2C_MASK2_OFFSET)
#define LPC11_I2C1_MASK3 (LPC11_I2C1_BASE+LPC11_I2C_MASK3_OFFSET)
#define LPC11_I2C2_CONSET (LPC11_I2C2_BASE+LPC11_I2C_CONSET_OFFSET)
#define LPC11_I2C2_STAT (LPC11_I2C2_BASE+LPC11_I2C_STAT_OFFSET)
#define LPC11_I2C2_DAT (LPC11_I2C2_BASE+LPC11_I2C_DAT_OFFSET)
#define LPC11_I2C2_ADR0 (LPC11_I2C2_BASE+LPC11_I2C_ADR0_OFFSET)
#define LPC11_I2C2_SCLH (LPC11_I2C2_BASE+LPC11_I2C_SCLH_OFFSET)
#define LPC11_I2C2_SCLL (LPC11_I2C2_BASE+LPC11_I2C_SCLL_OFFSET)
#define LPC11_I2C2_CONCLR (LPC11_I2C2_BASE+LPC11_I2C_CONCLR_OFFSET)
#define LPC11_I2C2_MMCTRL (LPC11_I2C2_BASE+LPC11_I2C_MMCTRL_OFFSET)
#define LPC11_I2C2_ADR1 (LPC11_I2C2_BASE+LPC11_I2C_ADR1_OFFSET)
#define LPC11_I2C2_ADR2 (LPC11_I2C2_BASE+LPC11_I2C_ADR2_OFFSET)
#define LPC11_I2C2_ADR3 (LPC11_I2C2_BASE+LPC11_I2C_ADR3_OFFSET)
#define LPC11_I2C2_BUFR (LPC11_I2C2_BASE+LPC11_I2C_BUFR_OFFSET)
#define LPC11_I2C2_MASK0 (LPC11_I2C2_BASE+LPC11_I2C_MASK0_OFFSET)
#define LPC11_I2C2_MASK1 (LPC11_I2C2_BASE+LPC11_I2C_MASK1_OFFSET)
#define LPC11_I2C2_MASK2 (LPC11_I2C2_BASE+LPC11_I2C_MASK2_OFFSET)
#define LPC11_I2C2_MASK3 (LPC11_I2C2_BASE+LPC11_I2C_MASK3_OFFSET)
/* Register bit definitions *********************************************************/
/* I2C Control Set Register */
/* Bits 0-1: Reserved */
#define I2C_CONSET_AA (1 << 2) /* Bit 2: Assert acknowledge flag */
#define I2C_CONSET_SI (1 << 3) /* Bit 3: I2C interrupt flag */
#define I2C_CONSET_STO (1 << 4) /* Bit 4: STOP flag */
#define I2C_CONSET_STA (1 << 5) /* Bit 5: START flag */
#define I2C_CONSET_I2EN (1 << 6) /* Bit 6: I2C interface enable */
/* Bits 7-31: Reserved */
/* I2C Control Clear Register */
/* Bits 0-1: Reserved */
#define I2C_CONCLR_AAC (1 << 2) /* Bit 2: Assert acknowledge Clear bit */
#define I2C_CONCLR_SIC (1 << 3) /* Bit 3: I2C interrupt Clear bit */
/* Bit 4: Reserved */
#define I2C_CONCLR_STAC (1 << 5) /* Bit 5: START flag Clear bit */
#define I2C_CONCLRT_I2ENC (1 << 6) /* Bit 6: I2C interface Disable bit */
/* Bits 7-31: Reserved */
/* I2C Status Register
*
* See tables 399-402 in the "LPC11xx User Manual" (UM10398), Rev. 01, 4 January
* 2010, NXP for definitions of status codes.
*/
#define I2C_STAT_MASK (0xff) /* Bits 0-7: I2C interface status
* Bits 0-1 always zero */
/* Bits 8-31: Reserved */
/* I2C Data Register */
#define I2C_DAT_MASK (0xff) /* Bits 0-7: I2C data */
/* Bits 8-31: Reserved */
/* Monitor mode control register */
#define I2C_MMCTRL_MMENA (1 << 0) /* Bit 0: Monitor mode enable */
#define I2C_MMCTRL_ENASCL (1 << 1) /* Bit 1: SCL output enable */
#define I2C_MMCTRL_MATCHALL (1 << 2) /* Bit 2: Select interrupt register match */
/* Bits 3-31: Reserved */
/* Data buffer register */
#define I2C_BUFR_MASK (0xff) /* Bits 0-7: 8 MSBs of the I2DAT shift register */
/* Bits 8-31: Reserved */
/* I2C Slave address registers:
*
* I2C Slave Address Register 0
* I2C Slave Address Register 1
* I2C Slave Address Register 2
* I2C Slave Address Register 3
*/
#define I2C_ADR_GC (1 << 0) /* Bit 0: GC General Call enable bit */
#define I2C_ADR_ADDR_SHIFT (1) /* Bits 1-7: I2C slave address */
#define I2C_ADR_ADDR_MASK (0x7f << I2C_ADR_ADDR_SHIFT)
/* Bits 8-31: Reserved */
/* I2C Slave address mask registers:
*
* I2C Slave address mask register 0
* I2C Slave address mask register 1
* I2C Slave address mask register 2
* I2C Slave address mask register 3
*/
/* Bit 0: Reserved */
#define I2C_MASK_SHIFT (1) /* Bits 1-7: I2C mask bits */
#define I2C_MASK_MASK (0x7f << I2C_ADR_ADDR_SHIFT)
/* Bits 8-31: Reserved */
/* SCH Duty Cycle Register High Half Word */
#define I2C_SCLH_MASK (0xffff) /* Bit 0-15: Count for SCL HIGH time period selection */
/* Bits 16-31: Reserved */
/* SCL Duty Cycle Register Low Half Word */
#define I2C_SCLL_MASK (0xffff) /* Bit 0-15: Count for SCL LOW time period selection */
/* Bits 16-31: Reserved */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_I2C_H */
arch/arm/src/lpc11xx/hardware/lpc11_memorymap.h
-73
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@@ -1,73 +0,0 @@
/************************************************************************************
* arch/arm/src/lpc11xx/hardware/lpc11_memorymap.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_MEMORYMAP_H
#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_MEMORYMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/* This file is only a thin shell that includes the correct memory map definitions
* for the selected LPC11xx family.
*/
#include <arch/lpc11xx/chip.h>
#if defined(LPC111x)
# include "hardware/lpc111x_memorymap.h"
#else
# error "Unrecognized LPC11xx family"
#endif
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_MEMORYMAP_H */
arch/arm/src/lpc11xx/hardware/lpc11_pinconfig.h
-73
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@@ -1,73 +0,0 @@
/************************************************************************************
* arch/arm/src/lpc11xx/hardware/lpc11_pinconfig.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_PINCONFIG_H
#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_PINCONFIG_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/* This file is only a thin shell that includes the correct pin configuration
* definitions for the selected LPC11xx family.
*/
#include <arch/lpc11xx/chip.h>
#if defined(LPC111x)
# include "hardware/lpc111x_pinconfig.h"
#else
# error "Unrecognized LPC11xx family"
#endif
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_PINCONFIG_H */
arch/arm/src/lpc11xx/hardware/lpc11_pmu.h
-106
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@@ -1,106 +0,0 @@
/************************************************************************************
* arch/arm/src/lpc11xx/hardware/lpc11_pmu.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_PMU_H
#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_PMU_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/lpc11_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register offsets *****************************************************************/
#define LPC11_PMU_PCON_OFFSET 0x0000 /* Power control register */
#define LPC11_PMU_GPREG0 0x0004 /* General purpose register 0 */
#define LPC11_PMU_GPREG1 0x0008 /* General purpose register 1 */
#define LPC11_PMU_GPREG2 0x000C /* General purpose register 2 */
#define LPC11_PMU_GPREG3 0x0010 /* General purpose register 3 */
#define LPC11_PMU_GPREG4 0x0014 /* General purpose register 0 */
/* Register addresses ***************************************************************/
#define LPC11_PMU_PCON (LPC11_PMU_BASE+LPC11_PMU_PCON_OFFSET)
#define LPC11_PMU_GPREG0 (LPC11_PMU_BASE+LPC11_PMU_GPREG0)
#define LPC11_PMU_GPREG1 (LPC11_PMU_BASE+LPC11_PMU_GPREG1)
#define LPC11_PMU_GPREG2 (LPC11_PMU_BASE+LPC11_PMU_GPREG2)
#define LPC11_PMU_GPREG3 (LPC11_PMU_BASE+LPC11_PMU_GPREG3)
#define LPC11_PMU_GPREG4 (LPC11_PMU_BASE+LPC11_PMU_GPREG4)
/* Register bit definitions *********************************************************/
/* Power control register */
/* Bit 0: Reserved. Do not write 1 to this bit */
#define PMU_PCON_DPDEN (1 << 1) /* Deep power-down mode enable */
/* Bits 2-7: Reserved. Do not write ones to this bit */
#define PMU_PCON_SLEEPFLAG (1 << 8) /* Sleep mode flag */
/* Bits 9-10: Reserved. Do not write ones to this bit */
#define PMU_PCON_DPDFLAG (1 << 11) /* Deep power-down flag. */
/* Bits 12-31: Reserved. Do not write ones to this bit */
/* General Purpose REG */
#define PMU_GPREG03_GPDATA_MASK (0xffffffff) /* Bits 0-31: Data retained during Deep power-down mode */
/* General Purpose REG4 Register */
/* Bits 0-9: Reserved. Do not write ones to this bit */
#define PMU_GPREG4_WAKEUPHYS (1 << 10) /* WAKEUP pin hysteresis enable */
#define PMU_GPREG4_GPDATA_SHIFT 11 /* Data retained during Deep power-down mode. */
#define PMU_GPREG4_GPDATA_MASK (0x1fffff << PMU_GPREG4_GPDATA_SHIFT)
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_PMU_H */
arch/arm/src/lpc11xx/hardware/lpc11_ssp.h
-182
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@@ -1,182 +0,0 @@
/************************************************************************************
* arch/arm/src/lpc11xx/hardware/lpc11_ssp.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_SSP_H
#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_SSP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/lpc11_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register offsets *****************************************************************/
#define LPC11_SSP_CR0_OFFSET 0x0000 /* Control Register 0 */
#define LPC11_SSP_CR1_OFFSET 0x0004 /* Control Register 1 */
#define LPC11_SSP_DR_OFFSET 0x0008 /* Data Register */
#define LPC11_SSP_SR_OFFSET 0x000c /* Status Register */
#define LPC11_SSP_CPSR_OFFSET 0x0010 /* Clock Prescale Register */
#define LPC11_SSP_IMSC_OFFSET 0x0014 /* Interrupt Mask Set/Clear Register */
#define LPC11_SSP_RIS_OFFSET 0x0018 /* Raw Interrupt Status Register */
#define LPC11_SSP_MIS_OFFSET 0x001c /* Masked Interrupt Status Register */
#define LPC11_SSP_ICR_OFFSET 0x0020 /* Interrupt Clear Register */
/* Register addresses ***************************************************************/
/* SPI 0 */
#define LPC11_SSP0_CR0 (LPC11_SPI0_BASE+LPC11_SSP_CR0_OFFSET)
#define LPC11_SSP0_CR1 (LPC11_SPI0_BASE+LPC11_SSP_CR1_OFFSET)
#define LPC11_SSP0_DR (LPC11_SPI0_BASE+LPC11_SSP_DR_OFFSET)
#define LPC11_SSP0_SR (LPC11_SPI0_BASE+LPC11_SSP_SR_OFFSET)
#define LPC11_SSP0_CPSR (LPC11_SPI0_BASE+LPC11_SSP_CPSR_OFFSET)
#define LPC11_SSP0_IMSC (LPC11_SPI0_BASE+LPC11_SSP_IMSC_OFFSET)
#define LPC11_SSP0_RIS (LPC11_SPI0_BASE+LPC11_SSP_RIS_OFFSET)
#define LPC11_SSP0_MIS (LPC11_SPI0_BASE+LPC11_SSP_MIS_OFFSET)
#define LPC11_SSP0_ICR (LPC11_SPI0_BASE+LPC11_SSP_ICR_OFFSET)
/* SPI 1 */
#define LPC11_SSP1_CR0 (LPC11_SPI1_BASE+LPC11_SSP_CR0_OFFSET)
#define LPC11_SSP1_CR1 (LPC11_SPI1_BASE+LPC11_SSP_CR1_OFFSET)
#define LPC11_SSP1_DR (LPC11_SPI1_BASE+LPC11_SSP_DR_OFFSET)
#define LPC11_SSP1_SR (LPC11_SPI1_BASE+LPC11_SSP_SR_OFFSET)
#define LPC11_SSP1_CPSR (LPC11_SPI1_BASE+LPC11_SSP_CPSR_OFFSET)
#define LPC11_SSP1_IMSC (LPC11_SPI1_BASE+LPC11_SSP_IMSC_OFFSET)
#define LPC11_SSP1_RIS (LPC11_SPI1_BASE+LPC11_SSP_RIS_OFFSET)
#define LPC11_SSP1_MIS (LPC11_SPI1_BASE+LPC11_SSP_MIS_OFFSET)
#define LPC11_SSP1_ICR (LPC11_SPI1_BASE+LPC11_SSP_ICR_OFFSET)
/* Register bit definitions *********************************************************/
/* SPI/SSP Control Register 0 */
#define SSP_CR0_DSS_SHIFT (0) /* Data Size Select */
#define SSP_CR0_DSS_MASK (15 << SSP_CR0_SHIFT)
# define SSP_CR0_DSS_4BITS (3 << SSP_CR0_DSS_SHIFT) /* 4 bits per transfer */
# define SSP_CR0_DSS_5BITS (4 << SSP_CR0_DSS_SHIFT) /* 5 bits per transfer */
# define SSP_CR0_DSS_6BITS (5 << SSP_CR0_DSS_SHIFT) /* 6 bits per transfer */
# define SSP_CR0_DSS_7BITS (6 << SSP_CR0_DSS_SHIFT) /* 7 bits per transfer */
# define SSP_CR0_DSS_8BITS (7 << SSP_CR0_DSS_SHIFT) /* 8 bits per transfer */
# define SSP_CR0_DSS_9BITS (8 << SSP_CR0_DSS_SHIFT) /* 9 bits per transfer */
# define SSP_CR0_DSS_10BITS (9 << SSP_CR0_DSS_SHIFT) /* 10 bits per transfer */
# define SSP_CR0_DSS_11BITS (10 << SSP_CR0_DSS_SHIFT) /* 11 bits per transfer */
# define SSP_CR0_DSS_12BITS (11 << SSP_CR0_DSS_SHIFT) /* 12 bits per transfer */
# define SSP_CR0_DSS_13BITS (12 << SSP_CR0_DSS_SHIFT) /* 13 bits per transfer */
# define SSP_CR0_DSS_14BITS (13 << SSP_CR0_DSS_SHIFT) /* 14 bits per transfer */
# define SSP_CR0_DSS_15BITS (14 << SSP_CR0_DSS_SHIFT) /* 15 bits per transfer */
# define SSP_CR0_DSS_16BITS (15 << SSP_CR0_DSS_SHIFT) /* 16 bits per transfer */
#define SSP_CR0_FRF_SHIFT (4) /* Frame Format */
#define SSP_CR0_FRF_MASK (3 << SSP_CR0_FRF_SHIFT)
# define SSP_CR0_FRF_SPI (0 << SSP_CR0_FRF_SHIFT) /* SPI Frame Format */
# define SSP_CR0_FRF_TI (1 << SSP_CR0_FRF_SHIFT) /* TI Frame Format */
# define SSP_CR0_FRF_MWIRE (2 << SSP_CR0_FRF_SHIFT) /* Microwire Frame Format */
/* (3 << SSP_CR0_FRF_SHIFT) format is not supported */
#define SSP_CR0_CPOL (1 << 6) /* Bit 6: Clock polarity control */
#define SSP_CR0_CPHA (1 << 7) /* Bit 7: Clock phase control */
#define SSP_CR0_SCR_SHIFT (8) /* Bit 8-15: Serial Clock Rate. PCLK/(CPSDVSR x [SCR + 1] */
#define SSP_CR0_SCR_MASK (255 << SSP_CR0_SCR_SHIFT)
/* SPI/SSP Control Register 1 */
#define SSP_CR1_LBM (1 << 0) /* Bit 0: Loop Back Mode */
#define SSP_CR1_SSE (1 << 1) /* Bit 1: SPI Enable */
#define SSP_CR1_MS (1 << 2) /* Bit 2: Master/Slave Mode */
#define SSP_CR1_SOD (1 << 3) /* Bit 3: Slave Output Disable */
/* Bits 4-31: Reserved */
/* SPI/SSP Data Register */
#define SSP_DR_MASK (0xffff) /* Bits 0-15: Data */
/* Bits 16-31: Reserved */
/* SPI/SSP Status Register */
#define SSP_SR_TFE (1 << 0) /* Bit 0: Transmit FIFO Empty */
#define SSP_SR_TNF (1 << 1) /* Bit 1: Transmit FIFO Not Full */
#define SSP_SR_RNE (1 << 2) /* Bit 2: Receive FIFO Not Empty */
#define SSP_SR_RFF (1 << 3) /* Bit 3: Receive FIFO Full */
#define SSP_SR_BSY (1 << 4) /* Bit 4: Busy */
/* Bits 5-31: Reserved */
/* SPI/SSP Clock Prescale Register */
#define SSP_CPSR_DVSR_MASK (0xff) /* Even values between 2 and 254 */
/* SPI/SSP Interrupt Mask Set/Clear Register */
#define SSP_IMSC_RORIM (1 << 0) /* Bit 0: Enable Receive Overrun Interrupt */
#define SSP_IMSC_RTIM (1 << 1) /* Bit 1: Enable Receive Timeout Interrupt */
#define SSP_IMSC_RXIM (1 << 2) /* Bit 2: Enable Rx FIFO half full Interrupt */
#define SSP_IMSC_TXIM (1 << 3) /* Bit 3: Enable Tx FIFO halt empty */
/* Bits 4-31: Reserved */
/* SPI/SSP Raw Interrupt Status */
#define SSP_RIS_RORIS (1 << 0) /* Bit 0: An Overrun event occurred */
#define SSP_RIS_RTRIS (1 << 1) /* Bit 1: Rx FIFO has data and MCU didn't read it */
#define SSP_RIS_RXRIS (1 << 2) /* Bit 2: The Rx FIFO is at least half full */
#define SSP_RIS_TXRIS (1 << 3) /* Bit 3: Tx FIFO is at least halt empty */
/* Bits 4-31: Reserved */
/* SPI/SSP Masked Interrupt Status Register */
#define SSP_MIS_RORMIS (1 << 0) /* Bit 0: An Overrun occurred and this interrupt is enabled */
#define SSP_MIS_RTMIS (1 << 1) /* Bit 1: An Rx FIFO timeout happened and this int is enabled */
#define SSP_MIS_RXMIS (1 << 2) /* Bit 2: Rx FIFO is at least half empty and this int is enabled */
#define SSP_MIS_TXMIS (1 << 3) /* Bit 3: Tx FIFO is at least halt full and this int is enabled */
/* Bits 4-31: Reserved */
/* SPI/SSP Interrupt Clear Register */
#define SSP_ICR_RORIC (1 << 0) /* Bit 0: Clear Rx FIFO Overrun Interrupt */
#define SSP_ICR_RTIC (1 << 1) /* Bit 1: Clear Rx FIFO read timeout Interrupt */
/* Bits 2-31: Reserved */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_SPI_H */
arch/arm/src/lpc11xx/hardware/lpc11_syscon.h
-449
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@@ -1,449 +0,0 @@
/********************************************************************************************
* arch/arm/src/lpc11xx/hardware/lpc11_syscon.h
*
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_SYSCON_H
#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_SYSCON_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/lpc11_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* Register offsets *************************************************************************/
#define LPC11_SYSCON_SYSMEMREMAP_OFFSET 0x0000 /* System memory remap */
#define LPC11_SYSCON_PRESETCTRL_OFFSET 0x0004 /* Pefipheral reset control */
#define LPC11_SYSCON_SYSPLLCTRL_OFFSET 0x0008 /* System PLL control */
#define LPC11_SYSCON_SYSPLLSTAT_OFFSET 0x000C /* System PLL status */
/* 0x010 - 0x01c: Reserved */
#define LPC11_SYSCON_SYSOSCCTRL_OFFSET 0x0020 /* System oscillator control */
#define LPC11_SYSCON_WDTOSCCTRL_OFFSET 0x0024 /* Watchdog oscillator control */
#define LPC11_SYSCON_IRCCTRL_OFFSET 0x0028 /* IRC control */
/* 0x02c: Reserved */
#define LPC11_SYSCON_SYSRSTSTAT_OFFSET 0x0030 /* System reset status register */
/* 0x034 - 0x03c: Reserved */
#define LPC11_SYSCON_SYSPLLCLKSEL_OFFSET 0x0040 /* System PLL clock source select */
#define LPC11_SYSCON_SYSPLLCLKUEN_OFFSET 0x0044 /* System PLL clock source update enable */
/* 0x048 - 0x06c: Reserved */
#define LPC11_SYSCON_MAINCLKSEL_OFFSET 0x0070 /* Main clock source select */
#define LPC11_SYSCON_MAINCLKUEN_OFFSET 0x0074 /* Main clock source update enable */
#define LPC11_SYSCON_SYSAHBCLKDIV_OFFSET 0x0078 /* System AHB clock divider */
/* 0x07c: Reserved */
#define LPC11_SYSCON_SYSAHBCLKCTRL_OFFSET 0x0080 /* System AHB clock control */
/* 0x084 - 0x090: Reserved */
#define LPC11_SYSCON_SSP0CLKDIV_OFFSET 0x0094 /* SPI0 clock divider */
#define LPC11_SYSCON_UARTCLKDIV_OFFSET 0x0098 /* UART clock divider */
#define LPC11_SYSCON_SSP1CLKDIV_OFFSET 0x009c /* SPI1 clock divider */
/* 0x0a0 - 0x0cc: Reserved */
#define LPC11_SYSCON_WDTCLKSEL_OFFSET 0x00d0 /* WDT clock source select */
#define LPC11_SYSCON_WDTCLKUEN_OFFSET 0x00d4 /* WDT clock source update enable */
#define LPC11_SYSCON_WDTCLKDIV_OFFSET 0x00d8 /* WDT clock divider */
/* 0x0dc: Reserved */
#define LPC11_SYSCON_CLKOUTCLKSEL_OFFSET 0x00e0 /* CLKOUT clock source select */
#define LPC11_SYSCON_CLKOUTUEN_OFFSET 0x00e4 /* CLKOUT clock source update enable */
#define LPC11_SYSCON_CLKOUTCLKDIV_OFFSET 0x00e8 /* CLKOUT clock divider */
/* 0x0ec - 0x0fc: Reserved */
#define LPC11_SYSCON_PIOPORCAP0_OFFSET 0x0100 /* POR captured PIO status 0 */
#define LPC11_SYSCON_PIOPORCAP1_OFFSET 0x0104 /* POR captured PIO status 1 */
/* 0x108 - 0x14c: Reserved */
#define LPC11_SYSCON_BODCTRL_OFFSET 0x0150 /* BOD control */
#define LPC11_SYSCON_SYSTCKCAL_OFFSET 0x0154 /* System tick counter calibration */
/* 0x158 - 0x16c: Reserved */
#define LPC11_SYSCON_IRQLATENCY_OFFSET 0x0170 /* IRQ delay */
#define LPC11_SYSCON_NMISRC_OFFSET 0x0174 /* NMI source selection */
/* 0x178 - 0x1fc: Reserved */
#define LPC11_SYSCON_STARTAPRP0_OFFSET 0x0200 /* Start logic edge control register 0 */
#define LPC11_SYSCON_STARTERP0_OFFSET 0x0204 /* Start logic signal enable register 0 */
#define LPC11_SYSCON_STARTRSRP0CLR_OFFSET 0x0208 /* Start logic reset register 0 */
#define LPC11_SYSCON_STARTSRP0_OFFSET 0x020c /* Start logic status register 0 */
/* 0x210 - 0x22c: Reserved */
#define LPC11_SYSCON_PDSLEEPCFG_OFFSET 0x0230 /* Power-down states in Deep-sleep mode */
#define LPC11_SYSCON_PDAWAKECFG_OFFSET 0x0234 /* Power-down states after wake-up from Deep-sleep mode */
#define LPC11_SYSCON_PDRUNCFG_OFFSET 0x0238 /* Power-down configuration register */
/* 0x023c - 0x3f0: Reserved */
#define LPC11_SYSCON_DEVICE_ID_OFFSET 0x03f4 /* Device ID register 0 for parts LPC1100, LPC1100C, LPC1100L */
/* Register addresses ***********************************************************************/
#define LPC11_SYSCON_SYSMEMREMAP (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSMEMREMAP_OFFSET)
#define LPC11_SYSCON_PRESETCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_PRESETCTRL_OFFSET)
#define LPC11_SYSCON_SYSPLLCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSPLLCTRL_OFFSET)
#define LPC11_SYSCON_SYSPLLSTAT (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSPLLSTAT_OFFSET)
#define LPC11_SYSCON_SYSOSCCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSOSCCTRL_OFFSET)
#define LPC11_SYSCON_WDTOSCCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_WDTOSCCTRL_OFFSET)
#define LPC11_SYSCON_IRCCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_IRCCTRL_OFFSET)
#define LPC11_SYSCON_SYSRSTSTAT (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSRSTSTAT_OFFSET)
#define LPC11_SYSCON_SYSPLLCLKSEL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSPLLCLKSEL_OFFSET)
#define LPC11_SYSCON_SYSPLLCLKUEN (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSPLLCLKUEN_OFFSET)
#define LPC11_SYSCON_MAINCLKSEL (LPC11_SYSCON_BASE + LPC11_SYSCON_MAINCLKSEL_OFFSET)
#define LPC11_SYSCON_MAINCLKUEN (LPC11_SYSCON_BASE + LPC11_SYSCON_MAINCLKUEN_OFFSET)
#define LPC11_SYSCON_SYSAHBCLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSAHBCLKDIV_OFFSET)
#define LPC11_SYSCON_SYSAHBCLKCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSAHBCLKCTRL_OFFSET)
#define LPC11_SYSCON_SSP0CLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_SSP0CLKDIV_OFFSET)
#define LPC11_SYSCON_UARTCLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_UARTCLKDIV_OFFSET)
#define LPC11_SYSCON_SSP1CLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_SSP1CLKDIV_OFFSET)
#define LPC11_SYSCON_WDTCLKSEL (LPC11_SYSCON_BASE + LPC11_SYSCON_WDTCLKSEL_OFFSET)
#define LPC11_SYSCON_WDTCLKUEN (LPC11_SYSCON_BASE + LPC11_SYSCON_WDTCLKUEN_OFFSET)
#define LPC11_SYSCON_WDTCLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_WDTCLKDIV_OFFSET)
#define LPC11_SYSCON_CLKOUTCLKSEL (LPC11_SYSCON_BASE + LPC11_SYSCON_CLKOUTCLKSEL_OFFSET)
#define LPC11_SYSCON_CLKOUTUEN (LPC11_SYSCON_BASE + LPC11_SYSCON_CLKOUTUEN_OFFSET_OFFSET)
#define LPC11_SYSCON_CLKOUTCLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_CLKOUTCLKDIV_OFFSET)
#define LPC11_SYSCON_PIOPORCAP0 (LPC11_SYSCON_BASE + LPC11_SYSCON_PIOPORCAP0_OFFSET)
#define LPC11_SYSCON_PIOPORCAP1 (LPC11_SYSCON_BASE + LPC11_SYSCON_PIOPORCAP1_OFFSET)
#define LPC11_SYSCON_BODCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_BODCTRL_OFFSET)
#define LPC11_SYSCON_SYSTCKCAL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSTCKCAL_OFFSET)
#define LPC11_SYSCON_IRQLATENCY (LPC11_SYSCON_BASE + LPC11_SYSCON_IRQLATENCY_OFFSET)
#define LPC11_SYSCON_NMISRC (LPC11_SYSCON_BASE + LPC11_SYSCON_NMISRC_OFFSET)
#define LPC11_SYSCON_STARTAPRP0 (LPC11_SYSCON_BASE + LPC11_SYSCON_STARTAPRP0_OFFSET)
#define LPC11_SYSCON_STARTERP0 (LPC11_SYSCON_BASE + LPC11_SYSCON_STARTERP0_OFFSET)
#define LPC11_SYSCON_STARTRSRP0CLR (LPC11_SYSCON_BASE + LPC11_SYSCON_STARTRSRP0CLR_OFFSET)
#define LPC11_SYSCON_STARTSRP0 (LPC11_SYSCON_BASE + LPC11_SYSCON_STARTSRP0_OFFSET)
#define LPC11_SYSCON_PDSLEEPCFG (LPC11_SYSCON_BASE + LPC11_SYSCON_PDSLEEPCFG_OFFSET)
#define LPC11_SYSCON_PDAWAKECFG (LPC11_SYSCON_BASE + LPC11_SYSCON_PDAWAKECFG_OFFSET)
#define LPC11_SYSCON_PDRUNCFG (LPC11_SYSCON_BASE + LPC11_SYSCON_PDRUNCFG_OFFSET)
#define LPC11_SYSCON_DEVICE_ID (LPC11_SYSCON_BASE + LPC11_SYSCON_DEVICE_ID_OFFSET)
/* Register bit definitions *****************************************************************/
#define SYSCON_SYSMEMREMAP_MAP_SHIFT (0) /* Bits 0-1: System memory remap register */
#define SYSCON_SYSMEMREMAP_MAP_MASK (3 << SYSCON_SYSMEMREMAP_MAP_SHIFT)
# define SYSCON_SYSMEMREMAP_MAP_BOOTLOADER (0 << SYSCON_SYSMEMREMAP_MAP_SHIFT) /* Interrupt vectors are re-mapped to Boot ROM */
# define SYSCON_SYSMEMREMAP_MAP_RAM (1 << SYSCON_SYSMEMREMAP_MAP_SHIFT) /* Interrupt vectors are re-mapped to Static RAM */
# define SYSCON_SYSMEMREMAP_MAP_FLASH (2 << SYSCON_SYSMEMREMAP_MAP_SHIFT) /* Interrupt vectors are keeped in flash */
/* Bits 2-31: Reserved */
#define SYSCON_PRESETCTRL_SSP0_RST_N (1 << 0) /* SPI0 reset control */
#define SYSCON_PRESETCTRL_I2C0_RST_N (1 << 1) /* I2C0 reset control */
#define SYSCON_PRESETCTRL_SSP1_RST_N (1 << 2) /* SPI1 reset control */
#define SYSCON_PRESETCTRL_CAN_RST_N (1 << 3) /* C_CAN reset control */
/* Bits 4-31: Reserved */
#define SYSCON_SYSPLLCTRL_MSEL_SHIFT (0) /* Bits 0-4: Feedback divider value. */
#define SYSCON_SYSPLLCTRL_MSEL_MASK (0x1f << SYSCON_SYSPLLCTRL_MSEL_SHIFT)
# define SYSCON_SYSPLLCTRL_MSEL_DIV(n) ((n-1) << SYSCON_SYSPLLCTRL_MSEL_SHIFT) /* n=1,2,3,..32 */
#define SYSCON_SYSPLLCTRL_PSEL_SHIFT (5) /* Bits 5-6: Post divider ratio P. The division ratio is 2 x P */
#define SYSCON_SYSPLLCTRL_PSEL_MASK (3 << SYSCON_SYSPLLCTRL_PSEL_SHIFT)
# define SYSCON_SYSPLLCTRL_PSEL_DIV1 (0 << SYSCON_SYSPLLCTRL_PSEL_SHIFT)
# define SYSCON_SYSPLLCTRL_PSEL_DIV2 (1 << SYSCON_SYSPLLCTRL_PSEL_SHIFT)
# define SYSCON_SYSPLLCTRL_PSEL_DIV4 (2 << SYSCON_SYSPLLCTRL_PSEL_SHIFT)
# define SYSCON_SYSPLLCTRL_PSEL_DIV8 (3 << SYSCON_SYSPLLCTRL_PSEL_SHIFT)
/* Bits 7-31: Reserved */
#define SYSCON_SYSPLLSTAT_LOCK (1 << 0) /* PLL lock status. 0 = PLL not locked, 1 = PLL locked */
/* Bits 1-31: Reserved */
#define SYSCON_SYSOSCCTRL_BYPASS (1 << 0) /* Bypass system oscillator */
#define SYSCON_SYSOSCCTRL_FREQRANGE (1 << 1) /* Determines freq. range for low-power oscillator */
/* Bits 2-31: Reserved */
#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0) /* Bits 0-4: Select divider for Fclkana. wdt_osc_clk = Fclkana/(2x(1+DIVSEL)) */
#define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1f << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)
# define SYSCON_WDTOSCCTRL_DIVSEL(n) (((n-2)/2) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT) /* n = 2,4,8,..64 */
#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5) /* Bits 5-8: Select watchdog oscillator analog output frequency */
#define SYSCON_WDTOSCCTRL_FREQSEL_MASK (15 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)
# define SYSCON_WDTOSCCTRL_FREQSEL_0p6Mhz (1 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 0.6 MHz */
# define SYSCON_WDTOSCCTRL_FREQSEL_1p05Mhz (2 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 1.05 MHz */
# define SYSCON_WDTOSCCTRL_FREQSEL_1p4Mhz (3 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 1.4 MHz */
# define SYSCON_WDTOSCCTRL_FREQSEL_1p75Mhz (4 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 1.75 MHz */
# define SYSCON_WDTOSCCTRL_FREQSEL_2p1Mhz (5 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 2.1 MHz */
# define SYSCON_WDTOSCCTRL_FREQSEL_2p4Mhz (6 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 2.4 MHz */
# define SYSCON_WDTOSCCTRL_FREQSEL_2p7Mhz (7 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 2.7 MHz */
# define SYSCON_WDTOSCCTRL_FREQSEL_3Mhz (8 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 3.0 MHz */
# define SYSCON_WDTOSCCTRL_FREQSEL_3p25Mhz (9 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 3.25 MHz */
# define SYSCON_WDTOSCCTRL_FREQSEL_3p5Mhz (10 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 3.5 MHz */
# define SYSCON_WDTOSCCTRL_FREQSEL_3p75Mhz (11 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 3.75 MHz */
# define SYSCON_WDTOSCCTRL_FREQSEL_4Mhz (12 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 4 MHz */
# define SYSCON_WDTOSCCTRL_FREQSEL_4p2Mhz (13 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 4.2 MHz */
# define SYSCON_WDTOSCCTRL_FREQSEL_4p4Mhz (14 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 4.4 MHz */
# define SYSCON_WDTOSCCTRL_FREQSEL_4p6Mhz (15 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 4.6 MHz */
/* Bits 9-31: Reserved */
#define SYSCON_IRCCTRL_TRIM_MASK (0xff) /* Bits 0-7: Trim value used to adjust on-chip 12 MHz oscillator */
/* Bits 8-31: Reserved */
#define SYSCON_SYSRSTSTAT_POR (1 << 0) /* POR reset status */
#define SYSCON_SYSRSTSTAT_EXTRST (1 << 1) /* Status of the external /RESET pin */
#define SYSCON_SYSRSTSTAT_WDT (1 << 2) /* Status of the Watchdog reset */
#define SYSCON_SYSRSTSTAT_BOD (1 << 3) /* Status of Brown-out detect reset */
#define SYSCON_SYSRSTSTAT_SYSRST (1 << 4) /* Status of the software system reset */
/* Bits 5-31: Reserved */
#define SYSCON_SYSPLLCLKSEL_SHIFT (0) /* Bits 0-1: System PLL clock source */
#define SYSCON_SYSPLLCLKSEL_MASK (3 << SYSCON_SYSPLLCLKSEL_SHIFT)
# define SYSCON_SYSPLLCLKSEL_IRCOSC (0 << SYSCON_SYSPLLCLKSEL_SHIFT)
# define SYSCON_SYSPLLCLKSEL_SYSOSC (1 << SYSCON_SYSPLLCLKSEL_SHIFT)
/* Bits 2-31: Reserved */
#define SYSCON_SYSPLLCLKUEN_ENA (1 << 0) /* Bit 0: Enable system PLL clock source update */
/* Bits 1-31: Reserved */
#define SYSCON_MAINCLKSEL_SHIFT (0) /* Bits 0-1: Clock source for main clock */
#define SYSCON_MAINCLKSEL_MASK (3 << SYSCON_MAINCLKSEL_SHIFT)
# define SYSCON_MAINCLKSEL_IRCOSC (0 << SYSCON_MAINCLKSEL_SHIFT) /* IRC oscillator */
# define SYSCON_MAINCLKSEL_PLLOSC (1 << SYSCON_MAINCLKSEL_SHIFT) /* Input clock to system PLL */
# define SYSCON_MAINCLKSEL_WDTOSC (2 << SYSCON_MAINCLKSEL_SHIFT) /* WDT oscillator */
# define SYSCON_MAINCLKSEL_SYSPLLCLKOUT (3 << SYSCON_MAINCLKSEL_SHIFT) /* System PLL clock out */
/* Bits 2-31: Reserved */
#define SYSCON_MAINCLKUEN_ENA (1 << 0) /* Bit 0: Enable main clock source update */
/* Bits 1-31: Reserved */
#define SYSCON_SYSAHBCLKDIV_SHIFT (0) /* Bits 0-7: 0=System clock disabled, 1=Divide by 1 ... 255 = Divide by 255 */
#define SYSCON_SYSAHBCLKDIV_MASK (0xff << SYSCON_SYSAHBCLKDIV_SHIFT)
/* Bits 8-31: Reserved */
//# define SYSCON_CCLKCFG_DIV(n) ((n-1) << SYSCON_CCLKCFG_SHIFT) /* n=2,3,..255 */
#define SYSCON_SYSAHBCLKCTRL_SYS (1 << 0) /* Bit 0: Enables clock for AHB to APB bridge */
#define SYSCON_SYSAHBCLKCTRL_ROM (1 << 1) /* Bit 1: Enables clock for ROM */
#define SYSCON_SYSAHBCLKCTRL_RAM (1 << 2) /* Bit 2: Enables clock for RAM */
#define SYSCON_SYSAHBCLKCTRL_FLASHREG (1 << 3) /* Bit 3: Enables clock for flash register interface */
#define SYSCON_SYSAHBCLKCTRL_FLASHARRAY (1 << 4) /* Bit 4: Enables clock for flash array access */
#define SYSCON_SYSAHBCLKCTRL_I2C0 (1 << 5) /* Bit 5: Enables clock for I2C0 */
#define SYSCON_SYSAHBCLKCTRL_GPIO (1 << 6) /* Bit 6: Enables clock for GPIO */
#define SYSCON_SYSAHBCLKCTRL_CT16B0 (1 << 7) /* Bit 7: Enables clock for 16-bit counter/timer 0 */
#define SYSCON_SYSAHBCLKCTRL_CT16B1 (1 << 8) /* Bit 8: Enables clock for 16-bit counter/timer 1 */
#define SYSCON_SYSAHBCLKCTRL_CT32B0 (1 << 9) /* Bit 9: Enables clock for 32-bit counter/timer 0 */
#define SYSCON_SYSAHBCLKCTRL_CT32B1 (1 << 10) /* Bit 10: Enables clock for 32-bit counter/timer 1 */
#define SYSCON_SYSAHBCLKCTRL_SSP0 (1 << 11) /* Bit 11: Enables clock for SPI0 */
#define SYSCON_SYSAHBCLKCTRL_UART (1 << 12) /* Bit 12: Enables clock for UART */
#define SYSCON_SYSAHBCLKCTRL_ADC (1 << 13) /* Bit 13: Enables clock for ADC */
/* Bit 14: Reserved */
#define SYSCON_SYSAHBCLKCTRL_WDT (1 << 15) /* Bit 15: Enables clock for WDT */
#define SYSCON_SYSAHBCLKCTRL_IOCON (1 << 16) /* Bit 16: Enables clock for I/O configuration block */
#define SYSCON_SYSAHBCLKCTRL_CAN (1 << 17) /* Bit 17: Enables clock for C_CAN */
#define SYSCON_SYSAHBCLKCTRL_SSP1 (1 << 18) /* Bit 18: Enables clock for SPI1 */
/* Bits 19-31: Reserved */
#define SYSCON_SSP0CLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable SPI0_PCLK, 1=Divide by 1 ... 255 = Divide by 255 */
/* Bits 8-31: Reserved */
#define SYSCON_UARTCLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable UART_PCLK, 1=Divide by 1 ... 255 = Divide by 255 */
/* Bits 8-31: Reserved */
#define SYSCON_SSP1CLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable SPI1_PCLK, 1=Divide by 1 ... 255 = Divide by 255 */
/* Bits 8-31: Reserved */
#define SYSCON_WDTCLKSEL_SHIFT (0) /* Bits 0-1: WDT clock source */
#define SYSCON_WDTCLKSEL_MASK (3 << SYSCON_WDTCLKSEL_SHIFT)
# define SYSCON_WDTCLKSEL_IRCOSC (0 << SYSCON_WDTCLKSEL_SHIFT) /* IRC oscillator */
# define SYSCON_WDTCLKSEL_MAINCLK (1 << SYSCON_WDTCLKSEL_SHIFT) /* Main clock */
# define SYSCON_WDTCLKSEL_WDTOSC (2 << SYSCON_WDTCLKSEL_SHIFT) /* Watchdog oscillator */
/* Bits 2-31: reserved */
#define SYSCON_WDTCLKUEN_ENA (1 << 0) /* Bit 0: Enable WDT clock source update */
/* Bits 1-31: Reserved */
#define SYSCON_WDTCLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable WDCLK, 1=Divide by 1 ... 255 = Divide by 255 */
/* Bits 8-31: Reserved */
#define SYSCON_CLKOUTCLKSEL_SHIFT (0) /* Bits 0-1: CLKOUT clock source */
#define SYSCON_CLKOUTCLKSEL_MASK (3 << SYSCON_CLKOUTCLKSEL_SHIFT)
# define SYSCON_CLKOUTCLKSEL_IRCOSC (0 << SYSCON_CLKOUTCLKSEL_SHIFT) /* IRC oscillator */
# define SYSCON_CLKOUTCLKSEL_SYSOSC (1 << SYSCON_CLKOUTCLKSEL_SHIFT) /* System oscillator */
# define SYSCON_CLKOUTCLKSEL_WDTOSC (2 << SYSCON_CLKOUTCLKSEL_SHIFT) /* Watchdog oscillator */
# define SYSCON_CLKOUTCLKSEL_MAINCLK (3 << SYSCON_CLKOUTCLKSEL_SHIFT) /* Main clock */
/* Bits 2-31: Reserved */
#define SYSCON_CLKOUTUEN_ENA (1 << 0) /* Bit 0: Enable CLKOUT clock source update */
/* Bits 1-31: Reserved */
#define SYSCON_CLKOUTCLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable CLKOUT, 1=Divide by 1 ... 255 = Divide by 255 */
/* Bits 1-31: Reserved */
#define SYSCON_PIOPORCAP0_CAPPIO0_SHIFT (0) /* Bits 0-11: Raw reset stats input PIO0_n: PIO0_11 to PIO0_0 */
#define SYSCON_PIOPORCAP0_CAPPIO0_MASK (0xfff << SYSCON_PIOPORCAP0_CAPPIO0_SHIFT)
# define SYSCON_PIOPORCAP0_CAPPIO0_BIT(n) ((1 << n) << SYSCON_PIOPORCAP0_CAPPIO0_SHIFT) /* n = 0 to 11 */
#define SYSCON_PIOPORCAP0_CAPPIO1_SHIFT (12) /* Bits 12-23: Raw reset stats input PIO0_n: PIO1_11 to PIO1_0 */
#define SYSCON_PIOPORCAP0_CAPPIO1_MASK (0xfff << SYSCON_PIOPORCAP0_CAPPIO1_SHIFT)
# define SYSCON_PIOPORCAP0_CAPPIO1_BIT(n) ((1 << n) << SYSCON_PIOPORCAP0_CAPPIO1_SHIFT) /* n = 0 to 11 */
#define SYSCON_PIOPORCAP0_CAPPIO2_SHIFT (24) /* Bits 24-31: Raw reset stats input PIO0_n: PIO2_11 to PIO2_0 */
#define SYSCON_PIOPORCAP0_CAPPIO2_MASK (0xfff << SYSCON_PIOPORCAP0_CAPPIO2_SHIFT)
# define SYSCON_PIOPORCAP0_CAPPIO2_BIT(n) ((1 << n) << SYSCON_PIOPORCAP0_CAPPIO2_SHIFT) /* n = 0 to 11 */
#define SYSCON_PIOPORCAP1_CAPPIO2_8 (1 << 0) /* Bit 0: Raw reset status input PIO2_8 */
#define SYSCON_PIOPORCAP1_CAPPIO2_9 (1 << 1) /* Bit 1: Raw reset status input PIO2_9 */
#define SYSCON_PIOPORCAP1_CAPPIO2_10 (1 << 2) /* Bit 2: Raw reset status input PIO2_10 */
#define SYSCON_PIOPORCAP1_CAPPIO2_11 (1 << 3) /* Bit 3: Raw reset status input PIO2_11 */
#define SYSCON_PIOPORCAP1_CAPPIO3_0 (1 << 4) /* Bit 4: Raw reset status input PIO3_0 */
#define SYSCON_PIOPORCAP1_CAPPIO3_1 (1 << 5) /* Bit 5: Raw reset status input PIO3_1 */
#define SYSCON_PIOPORCAP1_CAPPIO3_2 (1 << 6) /* Bit 6: Raw reset status input PIO3_2 */
#define SYSCON_PIOPORCAP1_CAPPIO3_3 (1 << 7) /* Bit 7: Raw reset status input PIO3_3 */
#define SYSCON_PIOPORCAP1_CAPPIO3_4 (1 << 8) /* Bit 8: Raw reset status input PIO3_4 */
#define SYSCON_PIOPORCAP1_CAPPIO3_5 (1 << 9) /* Bit 9: Raw reset status input PIO3_5 */
/* Bits 10-31: Reserved */
#define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0) /* Bits 0-1: BOD reset level */
#define SYSCON_BODCTRL_BODRSTLEV_MASK (3 << SYSCON_BODCTRL_BODRSTLEV_SHIFT)
# define SYSCON_BODCTRL_BODRSTLEV_LEVEL0 (0 << SYSCON_BODCTRL_BODRSTLEV_SHIFT) /* Level 0: assert 1.46V, de-assert 1.63V */
# define SYSCON_BODCTRL_BODRSTLEV_LEVEL1 (1 << SYSCON_BODCTRL_BODRSTLEV_SHIFT) /* Level 1: assert 2.06V, de-assert 2.15V */
# define SYSCON_BODCTRL_BODRSTLEV_LEVEL2 (2 << SYSCON_BODCTRL_BODRSTLEV_SHIFT) /* Level 2: assert 2.35V, de-assert 2.43V */
# define SYSCON_BODCTRL_BODRSTLEV_LEVEL3 (3 << SYSCON_BODCTRL_BODRSTLEV_SHIFT) /* Level 3: assert 2.63V, de-assert 2.71V */
#define SYSCON_BODCTRL_BODINTVAL_SHIFT (2) /* Bits 2-3: BOD interrupt level */
#define SYSCON_BODCTRL_BODINTVAL_MASK (3 << SYSCON_BODCTRL_BODRSTLEV_BODINTVAL_SHIFT)
# define SYSCON_BODCTRL_BODINTVAL_LEVEL0 (0 << SYSCON_BODCTRL_BODINTVAL_SHIFT) /* Level 0: Reserved */
# define SYSCON_BODCTRL_BODINTVAL_LEVEL1 (1 << SYSCON_BODCTRL_BODINTVAL_SHIFT) /* Level 1: int. assert 2.22V,de-a. 2.35V */
# define SYSCON_BODCTRL_BODINTVAL_LEVEL2 (2 << SYSCON_BODCTRL_BODINTVAL_SHIFT) /* Level 2: int. assert 2.52V,de-a. 2.66V */
# define SYSCON_BODCTRL_BODINTVAL_LEVEL3 (3 << SYSCON_BODCTRL_BODINTVAL_SHIFT) /* Level 3: int. assert 2.80V,de-a. 2.90V */
#define SYSCON_BODCTRL_BODRSTENA (1 << 4) /* BOD reset enable */
/* Bits 5-31: Reserved */
#define SYSCON_SYSTCKCAL_CAL 0x3ffffff /* Bits 0-25: System tick timer calibration value */
/* Bits 26-31: Reserved */
#define SYSCON_IRQLATENCY_LATENCY_MASK (0xff) /* Bits 0-7: 8-bit latency value */
/* Bits 8-31: Reserved */
#define SYSCON_NMISRC_IRQNO_SHIFT (0) /* Bits 0-4: The IRQ number of interrupt that acts as NMI if bit 31 is 1 */
#define SYSCON_NMISRC_IRQNO_MASK (31 << SYSCON_NMISRC_IRQNO_SHIFT)
/* Bits 5-30: Reserved */
#define SYSCON_NMISRC_NMIEN (1 << 31) /* Write 1 to this bit to enable NMI source selected by bits 4:0 */
#define SYSCON_STARTAPRP0_APRPIO0_SHIFT (0) /* Bits 0-11: Edge select for start logic input PIO0_[0-11], 0=fall/1=rise */
#define SYSCON_STARTAPRP0_APRPIO0_MASK (0xfff << SYSCON_STARTAPRP0_APRPIO0_SHIFT)
# define SYSCON_STARTAPRP0_APRPIO0_BIT(n) ((1 << n) << SYSCON_STARTAPRP0_APRPIO0_SHIFT) /* n = 0 to 11 */
#define SYSCON_STARTAPRP0_APRPIO1_0 (1 << 12) /* Bit 12: Edge select start logic input PIO1_0, 0=falling/1=rising */
/* Bits 13-31: Reserved */
#define SYSCON_STARTERP0_ERPIO0_SHIFT (0) /* Bits 0-11: Enable start signal for start logic input PIO0[0-11] */
#define SYSCON_STARTERP0_ERPIO0_MASK (0xfff << SYSCON_STARTERP0_ERPIO0_SHIFT)
# define SYSCON_STARTERP0_ERPIO0_BIT(n) ((1 << n) << SYSCON_STARTERP0_ERPIO0_SHIFT) /* n = 0 to 11 */
#define SYSCON_STARTERP0_ERPIO1_0 (1 << 12) /* Bit 12: Enable start signal for start logic input PIO1_0 */
/* Bits 13-31: Reserved */
#define SYSCON_STARTRSRP0CLR_RSRPIO0_SHIFT (0) /* Bits 0-11: Start logic reset register 0 */
#define SYSCON_STARTRSRP0CLR_RSRPIO0_MASK (0xfff << SYSCON_STARTRSRP0CLR_RSRPIO0_SHIFT)
# define SYSCON_STARTRSRP0CLR_RSRPIO0_BIT(n) ((1 << n) << SYSCON_STARTRSRP0CLR_RSRPIO0_SHIFT) /* n = 0 to 11 */
#define SYSCON_STARTRSRP0CLR_RSRPIO1_0 (1 << 12) /* Bit 12: Start signal reset for start logic input PIO1_0 */
/* Bits 13-31: Reserved */
#define SYSCON_STARTSRP0_SRPIO0_SHIFT (0) /* Bits 0-11: Start logic status register 0 */
#define SYSCON_STARTSRP0_SRPIO0_MASK (0xfff << SYSCON_STARTSRP0_SRPIO0_SHIFT)
# define SYSCON_STARTSRP0_SRPIO0_BIT(n) ((1 << n) << SYSCON_STARTSRP0_SRPIO0_SHIFT) /* n = 0 to 11 */
#define SYSCON_STARTSRP0_SRPIO1_0 (1 << 12) /* Bit 12: Start signal status for start logic input PIO1_0 */
/* Bits 13-31: Reserved */
/* Bits 0-2: Reserved. NOTE: Always write these bits as 111 */
#define SYSCON_PDSLEEPCFG_BOD_PD (1 << 3) /* BOD power-down control in Deep-sleep mode */
/* Bits 4-5: Reserved. NOTE: Always write these bits as 11 */
#define SYSCON_PDSLEEPCFG_WDTOSC_PD (1 << 6) /* Watchdog oscillator power control in Deep-sleep mode */
/* Bit 7: Reserved. NOTE: Always write this bit as 1 */
/* Bits 8-10: Reserved NOTE: Always write these bits as 000 */
/* Bits 11-12: Reserved. NOTE: Always write these bits as 11 */
/* Bits 13-31: Reserved */
#define SYSCON_PDAWAKECFG_IRCOUT_PD (1 << 0) /* Bit 0: IRC oscillator output wake-up configuration */
#define SYSCON_PDAWAKECFG_IRC_PD (1 << 1) /* Bit 1: IRC oscillator wake-up configuration */
#define SYSCON_PDAWAKECFG_FLASH_PD (1 << 2) /* Bit 2: Flash wake-up configuration */
#define SYSCON_PDAWAKECFG_BOD_PD (1 << 3) /* Bit 3: Brownout Detection wake-up configuration */
#define SYSCON_PDAWAKECFG_ADC_PD (1 << 4) /* Bit 4: ADC wake-up configuration */
#define SYSCON_PDAWAKECFG_SYSOSC_PD (1 << 5) /* Bit 5: System oscillator wake-up configuration */
#define SYSCON_PDAWAKECFG_WDTOSC_PD (1 << 6) /* Bit 6: Watchdog oscillator wake-up configuration */
#define SYSCON_PDAWAKECFG_SYSPLL_PD (1 << 7) /* Bit 7: System PLL wake-up configuration */
/* Bit 8: Reserved. NOTE: Always write this bit as 1 */
/* Bit 9: Reserved. NOTE: Always write this bit as 0 */
/* Bit 10: Reserved. NOTE: Always write this bit as 1 */
/* Bit 11: Reserved. NOTE: Always write this bit as 1 */
/* Bit 12: Reserved. NOTE: Always write this bit as 0 */
/* Bits 13-15: Reserved. NOTE: Always write these bits as 111 */
/* Bits 16-31: Reserved */
#define SYSCON_PDRUNCFG_IRCOUT_PD (1 << 0) /* Bit 0: IRC oscillator output power-down */
#define SYSCON_PDRUNCFG_IRC_PD (1 << 1) /* Bit 1: IRC oscillator power-down */
#define SYSCON_PDRUNCFG_FLASH_PD (1 << 2) /* Bit 2: Flash power-down */
#define SYSCON_PDRUNCFG_BOD_PD (1 << 3) /* Bit 3: Brownout Detection power-down */
#define SYSCON_PDRUNCFG_ADC_PD (1 << 4) /* Bit 4: ADC power-down */
#define SYSCON_PDRUNCFG_SYSOSC_PD (1 << 5) /* Bit 5: System oscillator power-down */
#define SYSCON_PDRUNCFG_WDTOSC_PD (1 << 6) /* Bit 6: Watchdog oscillator power-down */
#define SYSCON_PDRUNCFG_SYSPLL_PD (1 << 7) /* Bit 7: System PLL power-down */
/* Bit 8: Reserved. NOTE: Always write this bit as 1 */
/* Bit 9: Reserved. NOTE: Always write this bit as 0 */
/* Bit 10: Reserved. NOTE: Always write this bit as 1 */
/* Bit 11: Reserved. NOTE: Always write this bit as 1 */
/* Bit 12: Reserved. NOTE: Always write this bit as 0 */
/* Bits 13-15: Reserved. NOTE: Always write these bits as 111 */
/* Bits 16-31: Reserved */
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_SYSCON_H */
arch/arm/src/lpc11xx/hardware/lpc11_timer.h
-271
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@@ -1,271 +0,0 @@
/************************************************************************************
* arch/arm/src/lpc11xx/hardware/lpc11_timer.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_TIMER_H
#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_TIMER_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/lpc11_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register offsets *****************************************************************/
#define LPC11_TMR_IR_OFFSET 0x0000 /* Interrupt Register */
#define LPC11_TMR_TCR_OFFSET 0x0004 /* Timer Control Register */
#define LPC11_TMR_TC_OFFSET 0x0008 /* Timer Counter */
#define LPC11_TMR_PR_OFFSET 0x000c /* Prescale Register */
#define LPC11_TMR_PC_OFFSET 0x0010 /* Prescale Counter */
#define LPC11_TMR_MCR_OFFSET 0x0014 /* Match Control Register */
#define LPC11_TMR_MR0_OFFSET 0x0018 /* Match Register 0 */
#define LPC11_TMR_MR1_OFFSET 0x001c /* Match Register 1 */
#define LPC11_TMR_MR2_OFFSET 0x0020 /* Match Register 2 */
#define LPC11_TMR_MR3_OFFSET 0x0024 /* Match Register 3 */
#define LPC11_TMR_CCR_OFFSET 0x0028 /* Capture Control Register */
#define LPC11_TMR_CR0_OFFSET 0x002c /* Capture Register 0 */
#define LPC11_TMR_CR1_OFFSET 0x0030 /* Capture Register 1 */
#define LPC11_TMR_EMR_OFFSET 0x003c /* External Match Register */
#define LPC11_TMR_CTCR_OFFSET 0x0070 /* Count Control Register */
#define LPC11_TMR_PWMC_OFFSET 0x0074 /* PWM Control Register */
/* Register addresses ***************************************************************/
#define LPC11_TMR16B0IR (LPC11_TMR16B0_BASE+LPC11_TMR_IR_OFFSET)
#define LPC11_TMR16B0TCR (LPC11_TMR16B0_BASE+LPC11_TMR_TCR_OFFSET)
#define LPC11_TMR16B0TC (LPC11_TMR16B0_BASE+LPC11_TMR_TC_OFFSET)
#define LPC11_TMR16B0PR (LPC11_TMR16B0_BASE+LPC11_TMR_PR_OFFSET)
#define LPC11_TMR16B0PC (LPC11_TMR16B0_BASE+LPC11_TMR_PC_OFFSET)
#define LPC11_TMR16B0MCR (LPC11_TMR16B0_BASE+LPC11_TMR_MCR_OFFSET)
#define LPC11_TMR16B0MR0 (LPC11_TMR16B0_BASE+LPC11_TMR_MR0_OFFSET)
#define LPC11_TMR16B0MR1 (LPC11_TMR16B0_BASE+LPC11_TMR_MR1_OFFSET)
#define LPC11_TMR16B0MR2 (LPC11_TMR16B0_BASE+LPC11_TMR_MR2_OFFSET)
#define LPC11_TMR16B0MR3 (LPC11_TMR16B0_BASE+LPC11_TMR_MR3_OFFSET)
#define LPC11_TMR16B0CCR (LPC11_TMR16B0_BASE+LPC11_TMR_CCR_OFFSET)
#define LPC11_TMR16B0CR0 (LPC11_TMR16B0_BASE+LPC11_TMR_CR0_OFFSET)
#define LPC11_TMR16B0CR1 (LPC11_TMR16B0_BASE+LPC11_TMR_CR1_OFFSET)
#define LPC11_TMR16B0EMR (LPC11_TMR16B0_BASE+LPC11_TMR_EMR_OFFSET)
#define LPC11_TMR16B0CTCR (LPC11_TMR16B0_BASE+LPC11_TMR_CTCR_OFFSET)
#define LPC11_TMR16B0PWMC (LPC11_TMR16B0_BASE+LPC11_TMR_PWMC_OFFSET)
#define LPC11_TMR16B1IR (LPC11_TMR16B1_BASE+LPC11_TMR_IR_OFFSET)
#define LPC11_TMR16B1TCR (LPC11_TMR16B1_BASE+LPC11_TMR_TCR_OFFSET)
#define LPC11_TMR16B1TC (LPC11_TMR16B1_BASE+LPC11_TMR_TC_OFFSET)
#define LPC11_TMR16B1PR (LPC11_TMR16B1_BASE+LPC11_TMR_PR_OFFSET)
#define LPC11_TMR16B1PC (LPC11_TMR16B1_BASE+LPC11_TMR_PC_OFFSET)
#define LPC11_TMR16B1MCR (LPC11_TMR16B1_BASE+LPC11_TMR_MCR_OFFSET)
#define LPC11_TMR16B1MR0 (LPC11_TMR16B1_BASE+LPC11_TMR_MR0_OFFSET)
#define LPC11_TMR16B1MR1 (LPC11_TMR16B1_BASE+LPC11_TMR_MR1_OFFSET)
#define LPC11_TMR16B1MR2 (LPC11_TMR16B1_BASE+LPC11_TMR_MR2_OFFSET)
#define LPC11_TMR16B1MR3 (LPC11_TMR16B1_BASE+LPC11_TMR_MR3_OFFSET)
#define LPC11_TMR16B1CCR (LPC11_TMR16B1_BASE+LPC11_TMR_CCR_OFFSET)
#define LPC11_TMR16B1CR0 (LPC11_TMR16B1_BASE+LPC11_TMR_CR0_OFFSET)
#define LPC11_TMR16B1CR1 (LPC11_TMR16B1_BASE+LPC11_TMR_CR1_OFFSET)
#define LPC11_TMR16B1EMR (LPC11_TMR16B1_BASE+LPC11_TMR_EMR_OFFSET)
#define LPC11_TMR16B1CTCR (LPC11_TMR16B1_BASE+LPC11_TMR_CTCR_OFFSET)
#define LPC11_TMR16B1PWMC (LPC11_TMR16B1_BASE+LPC11_TMR_PWMC_OFFSET)
#define LPC11_TMR32B0IR (LPC11_TMR32B0_BASE+LPC11_TMR_IR_OFFSET)
#define LPC11_TMR32B0TCR (LPC11_TMR32B0_BASE+LPC11_TMR_TCR_OFFSET)
#define LPC11_TMR32B0TC (LPC11_TMR32B0_BASE+LPC11_TMR_TC_OFFSET)
#define LPC11_TMR32B0PR (LPC11_TMR32B0_BASE+LPC11_TMR_PR_OFFSET)
#define LPC11_TMR32B0PC (LPC11_TMR32B0_BASE+LPC11_TMR_PC_OFFSET)
#define LPC11_TMR32B0MCR (LPC11_TMR32B0_BASE+LPC11_TMR_MCR_OFFSET)
#define LPC11_TMR32B0MR0 (LPC11_TMR32B0_BASE+LPC11_TMR_MR0_OFFSET)
#define LPC11_TMR32B0MR1 (LPC11_TMR32B0_BASE+LPC11_TMR_MR1_OFFSET)
#define LPC11_TMR32B0MR2 (LPC11_TMR32B0_BASE+LPC11_TMR_MR2_OFFSET)
#define LPC11_TMR32B0MR3 (LPC11_TMR32B0_BASE+LPC11_TMR_MR3_OFFSET)
#define LPC11_TMR32B0CCR (LPC11_TMR32B0_BASE+LPC11_TMR_CCR_OFFSET)
#define LPC11_TMR32B0CR0 (LPC11_TMR32B0_BASE+LPC11_TMR_CR0_OFFSET)
#define LPC11_TMR32B0CR1 (LPC11_TMR32B0_BASE+LPC11_TMR_CR1_OFFSET)
#define LPC11_TMR32B0EMR (LPC11_TMR32B0_BASE+LPC11_TMR_EMR_OFFSET)
#define LPC11_TMR32B0CTCR (LPC11_TMR32B0_BASE+LPC11_TMR_CTCR_OFFSET)
#define LPC11_TMR32B0PWMC (LPC11_TMR32B0_BASE+LPC11_TMR_PWMC_OFFSET)
#define LPC11_TMR32B1IR (LPC11_TMR32B1_BASE+LPC11_TMR_IR_OFFSET)
#define LPC11_TMR32B1TCR (LPC11_TMR32B1_BASE+LPC11_TMR_TCR_OFFSET)
#define LPC11_TMR32B1TC (LPC11_TMR32B1_BASE+LPC11_TMR_TC_OFFSET)
#define LPC11_TMR32B1PR (LPC11_TMR32B1_BASE+LPC11_TMR_PR_OFFSET)
#define LPC11_TMR32B1PC (LPC11_TMR32B1_BASE+LPC11_TMR_PC_OFFSET)
#define LPC11_TMR32B1MCR (LPC11_TMR32B1_BASE+LPC11_TMR_MCR_OFFSET)
#define LPC11_TMR32B1MR0 (LPC11_TMR32B1_BASE+LPC11_TMR_MR0_OFFSET)
#define LPC11_TMR32B1MR1 (LPC11_TMR32B1_BASE+LPC11_TMR_MR1_OFFSET)
#define LPC11_TMR32B1MR2 (LPC11_TMR32B1_BASE+LPC11_TMR_MR2_OFFSET)
#define LPC11_TMR32B1MR3 (LPC11_TMR32B1_BASE+LPC11_TMR_MR3_OFFSET)
#define LPC11_TMR32B1CCR (LPC11_TMR32B1_BASE+LPC11_TMR_CCR_OFFSET)
#define LPC11_TMR32B1CR0 (LPC11_TMR32B1_BASE+LPC11_TMR_CR0_OFFSET)
#define LPC11_TMR32B1CR1 (LPC11_TMR32B1_BASE+LPC11_TMR_CR1_OFFSET)
#define LPC11_TMR32B1EMR (LPC11_TMR32B1_BASE+LPC11_TMR_EMR_OFFSET)
#define LPC11_TMR32B1CTCR (LPC11_TMR32B1_BASE+LPC11_TMR_CTCR_OFFSET)
#define LPC11_TMR32B1PWMC (LPC11_TMR32B1_BASE+LPC11_TMR_PWMC_OFFSET)
/* Register bit definitions *********************************************************/
/* Registers holding 32-bit numeric values (no bit field definitions):
*
* Timer Counter (TC)
* Prescale Register (PR)
* Prescale Counter (PC)
* Match Register 0 (MR0)
* Match Register 1 (MR1)
* Match Register 2 (MR2)
* Match Register 3 (MR3)
* Capture Register 0 (CR0)
* Capture Register 1 (CR1)
*/
/* Interrupt Register */
#define TMR_MR0INT (1 << 0) /* Bit 0: Match channel 0 interrupt */
#define TMR_MR1INT (1 << 1) /* Bit 1: Match channel 1 interrupt */
#define TMR_MR2INT (1 << 2) /* Bit 2: Match channel 2 interrupt */
#define TMR_MR3INT (1 << 3) /* Bit 3: Match channel 3 interrupt */
#define TMR_CR0INT (1 << 4) /* Bit 4: Capture channel 0 interrupt */
#define TMR_CR1INT (1 << 5) /* Bit 5: Capture channel 1 interrupt */
/* Bits 6-31: Reserved */
/* Timer Control Register */
#define TMR_TCR_CEN (1 << 0) /* Bit 0: Counter Enable */
#define TMR_TCR_CRST (1 << 1) /* Bit 1: Counter Reset */
/* Bits 2-31: Reserved */
/* Match Control Register */
#define TMR_MCR_MR0I (1 << 0) /* Bit 0: Interrupt on MR0 */
#define TMR_MCR_MR0R (1 << 1) /* Bit 1: Reset on MR0 */
#define TMR_MCR_MR0S (1 << 2) /* Bit 2: Stop on MR0 */
#define TMR_MCR_MR1I (1 << 3) /* Bit 3: Interrupt on MR1 */
#define TMR_MCR_MR1R (1 << 4) /* Bit 4: Reset on MR1 */
#define TMR_MCR_MR1S (1 << 5) /* Bit 5: Stop on MR1 */
#define TMR_MCR_MR2I (1 << 6) /* Bit 6: Interrupt on MR2 */
#define TMR_MCR_MR2R (1 << 7) /* Bit 7: Reset on MR2 */
#define TMR_MCR_MR2S (1 << 8) /* Bit 8: Stop on MR2 */
#define TMR_MCR_MR3I (1 << 9) /* Bit 9: Interrupt on MR3 */
#define TMR_MCR_MR3R (1 << 10) /* Bit 10: Reset on MR3 */
#define TMR_MCR_MR3S (1 << 11) /* Bit 11: Stop on MR3 */
/* Bits 12-31: Reserved */
/* Capture Control Register */
#define TMR_CCR_CAP0RE (1 << 0) /* Bit 0: Capture on CAPn.0 rising edge */
#define TMR_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edge */
#define TMR_CCR_CAP0I (1 << 2) /* Bit 2: Interrupt on CAPn.0 */
#define TMR_CCR_CAP1RE (1 << 3) /* Bit 3: Capture on CAPn.1 rising edge */
#define TMR_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edge */
#define TMR_CCR_CAP1I (1 << 5) /* Bit 5: Interrupt on CAPn.1 */
/* Bits 6-31: Reserved */
/* External Match Register */
#define TMR_EMR_NOTHING (0) /* Do Nothing */
#define TMR_EMR_CLEAR (1) /* Clear external match bit MATn.m */
#define TMR_EMR_SET (2) /* Set external match bit MATn.m */
#define TMR_EMR_TOGGLE (3) /* Toggle external match bit MATn.m */
#define TMR_EMR_EM0 (1 << 0) /* Bit 0: External Match 0 */
#define TMR_EMR_EM1 (1 << 1) /* Bit 1: External Match 1 */
#define TMR_EMR_EM2 (1 << 2) /* Bit 2: External Match 2 */
#define TMR_EMR_EM3 (1 << 3) /* Bit 3: External Match 3 */
#define TMR_EMR_EMC0_SHIFT (4) /* Bits 4-5: External Match Control 0 */
#define TMR_EMR_EMC0_MASK (3 << TMR_EMR_EMC0_SHIFTy)
# define TMR_EMR_EMC0_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC0_SHIFT)
# define TMR_EMR_EMC0_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC0_SHIFT)
# define TMR_EMR_EMC0_SET (TMR_EMR_SET << TMR_EMR_EMC0_SHIFT)
# define TMR_EMR_EMC0_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC0_SHIFT)
#define TMR_EMR_EMC1_SHIFT (6) /* Bits 6-7: External Match Control 1 */
#define TMR_EMR_EMC1_MASK (3 << TMR_EMR_EMC1_SHIFT)
# define TMR_EMR_EMC1_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC1_SHIFT)
# define TMR_EMR_EMC1_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC1_SHIFT)
# define TMR_EMR_EMC1_SET (TMR_EMR_SET << TMR_EMR_EMC1_SHIFT)
# define TMR_EMR_EMC1_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC1_SHIFT)
#define TMR_EMR_EMC2_SHIFT (8) /* Bits 8-9: External Match Control 2 */
#define TMR_EMR_EMC2_MASK (3 << TMR_EMR_EMC2_SHIFT)
# define TMR_EMR_EMC2_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC2_SHIFT)
# define TMR_EMR_EMC2_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC2_SHIFT)
# define TMR_EMR_EMC2_SET (TMR_EMR_SET << TMR_EMR_EMC2_SHIFT)
# define TMR_EMR_EMC2_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC2_SHIFT)
#define TMR_EMR_EMC3_SHIFT (10) /* Bits 10-11: External Match Control 3 */
#define TMR_EMR_EMC3_MASK (3 << TMR_EMR_EMC3_SHIFT)
# define TMR_EMR_EMC3_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC3_SHIFT)
# define TMR_EMR_EMC3_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC3_SHIFT)
# define TMR_EMR_EMC3_SET (TMR_EMR_SET << TMR_EMR_EMC3_SHIFT)
# define TMR_EMR_EMC3_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC3_SHIFT)
/* Bits 12-31: Reserved */
/* Count Control Register */
#define TMR_CTCR_MODE_SHIFT (0) /* Bits 0-1: Counter/Timer Mode */
#define TMR_CTCR_MODE_MASK (3 << TMR_CTCR_MODE_SHIFT)
# define TMR_CTCR_MODE_TIMER (0 << TMR_CTCR_MODE_SHIFT) /* Timer Mode, prescale match */
# define TMR_CTCR_MODE_CNTRRE (1 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */
# define TMR_CTCR_MODE_CNTRFE (2 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */
# define TMR_CTCR_MODE_CNTRBE (3 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */
#define TMR_CTCR_INPSEL_SHIFT (2) /* Bits 2-3: Count Input Select */
#define TMR_CTCR_INPSEL_MASK (3 << TMR_CTCR_INPSEL_SHIFT)
# define TMR_CTCR_INPSEL_CAPNp0 (0 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */
# define TMR_CTCR_INPSEL_CAPNp1 (1 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.1 for TIMERn */
#define TMR_CTCR_ENCC (1 << 4) /* Enable Clear Timer/Prescale when capture event happens */
#define TMR_CTCR_SELCC_SHIFT (5) /* Bits 5-7: Selects which capture event will clear Timer/Prescale */
#define TMR_CTCR_SELCC_MASK (3 << TMR_CTCR_SELCC_SHIFT)
# define TMR_CTCR_SELCC_RECAP0 (0 << TMR_CTCR_SELCC_SHIFT) /* Rising edge CAP0 clears timer (if bit 4 is set) */
# define TMR_CTCR_SELCC_FECAP0 (1 << TMR_CTCR_SELCC_SHIFT) /* Falling edge CAP0 clears timer (if bit 4 is set) */
# define TMR_CTCR_SELCC_RECAP1 (2 << TMR_CTCR_SELCC_SHIFT) /* Rising edge CAP1 clears timer (if bit 4 is set) */
# define TMR_CTCR_SELCC_FECAP1 (3 << TMR_CTCR_SELCC_SHIFT) /* Falling edge CAP1 clears timer (if bit 4 is set) */
/* Bits 8-31: Reserved */
/* PWM Control register */
#define TMR_PWMC_PWMEN0 (1 << 0) /* PWM channel0 enable */
#define TMR_PWMC_PWMEN1 (1 << 1) /* PWM channel1 enable */
#define TMR_PWMC_PWMEN2 (1 << 2) /* PWM channel2 enable */
#define TMR_PWMC_PWMEN3 (1 << 3) /* PWM channel3 enable */
/* Bits 4-31: Reserved */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_TIMER_H */
arch/arm/src/lpc11xx/hardware/lpc11_uart.h
-261
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@@ -1,261 +0,0 @@
/************************************************************************************
* arch/arm/src/lpc11xx/hardware/lpc11_uart.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_UART_H
#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_UART_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/lpc11_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register offsets *****************************************************************/
#define LPC11_UART_RBR_OFFSET 0x0000 /* (DLAB =0) Receiver Buffer Register (all) */
#define LPC11_UART_THR_OFFSET 0x0000 /* (DLAB =0) Transmit Holding Register (all) */
#define LPC11_UART_DLL_OFFSET 0x0000 /* (DLAB =1) Divisor Latch LSB (all) */
#define LPC11_UART_DLM_OFFSET 0x0004 /* (DLAB =1) Divisor Latch MSB (all) */
#define LPC11_UART_IER_OFFSET 0x0004 /* (DLAB =0) Interrupt Enable Register (all) */
#define LPC11_UART_IIR_OFFSET 0x0008 /* Interrupt ID Register (all) */
#define LPC11_UART_FCR_OFFSET 0x0008 /* FIFO Control Register (all) */
#define LPC11_UART_LCR_OFFSET 0x000c /* Line Control Register (all) */
#define LPC11_UART_MCR_OFFSET 0x0010 /* Modem Control Register (UART1 only) */
#define LPC11_UART_LSR_OFFSET 0x0014 /* Line Status Register (all) */
#define LPC11_UART_MSR_OFFSET 0x0018 /* Modem Status Register (UART1 only) */
#define LPC11_UART_SCR_OFFSET 0x001c /* Scratch Pad Register (all) */
#define LPC11_UART_ACR_OFFSET 0x0020 /* Auto-baud Control Register (all) */
#define LPC11_UART_FDR_OFFSET 0x0028 /* Fractional Divider Register (all) */
#define LPC11_UART_TER_OFFSET 0x0030 /* Transmit Enable Register (all) */
#define LPC11_UART_RS485CTRL_OFFSET 0x004c /* RS-485/EIA-485 Control (UART1 only) */
#define LPC11_UART_ADRMATCH_OFFSET 0x0050 /* RS-485/EIA-485 address match (UART1 only) */
#define LPC11_UART_RS485DLY_OFFSET 0x0054 /* RS-485/EIA-485 direction control delay (UART1 only) */
/* Register addresses ***************************************************************/
#define LPC11_UART0_RBR (LPC11_UART0_BASE+LPC11_UART_RBR_OFFSET)
#define LPC11_UART0_THR (LPC11_UART0_BASE+LPC11_UART_THR_OFFSET)
#define LPC11_UART0_DLL (LPC11_UART0_BASE+LPC11_UART_DLL_OFFSET)
#define LPC11_UART0_DLM (LPC11_UART0_BASE+LPC11_UART_DLM_OFFSET)
#define LPC11_UART0_IER (LPC11_UART0_BASE+LPC11_UART_IER_OFFSET)
#define LPC11_UART0_IIR (LPC11_UART0_BASE+LPC11_UART_IIR_OFFSET)
#define LPC11_UART0_FCR (LPC11_UART0_BASE+LPC11_UART_FCR_OFFSET)
#define LPC11_UART0_LCR (LPC11_UART0_BASE+LPC11_UART_LCR_OFFSET)
#define LPC11_UART0_MCR (LPC11_UART0_BASE+LPC11_UART_MCR_OFFSET)
#define LPC11_UART0_LSR (LPC11_UART0_BASE+LPC11_UART_LSR_OFFSET)
#define LPC11_UART0_SCR (LPC11_UART0_BASE+LPC11_UART_SCR_OFFSET)
#define LPC11_UART0_ACR (LPC11_UART0_BASE+LPC11_UART_ACR_OFFSET)
#define LPC11_UART0_ICR (LPC11_UART0_BASE+LPC11_UART_ICR_OFFSET)
#define LPC11_UART0_FDR (LPC11_UART0_BASE+LPC11_UART_FDR_OFFSET)
#define LPC11_UART0_TER (LPC11_UART0_BASE+LPC11_UART_TER_OFFSET)
#define LPC11_UART0_RS485CTRL (LPC11_UART0_BASE+LPC11_UART_RS485CTRL_OFFSET)
#define LPC11_UART0_ADRMATCH (LPC11_UART0_BASE+LPC11_UART_ADRMATCH_OFFSET)
#define LPC11_UART0_RS485DLY (LPC11_UART0_BASE+LPC11_UART_RS485DLY_OFFSET)
/* Register bit definitions *********************************************************/
/* RBR (DLAB =0) Receiver Buffer Register (all) */
#define UART_RBR_MASK (0xff) /* Bits 0-7: Oldest received byte in RX FIFO */
/* Bits 8-31: Reserved */
/* THR (DLAB =0) Transmit Holding Register (all) */
#define UART_THR_MASK (0xff) /* Bits 0-7: Adds byte to TX FIFO */
/* Bits 8-31: Reserved */
/* DLL (DLAB =1) Divisor Latch LSB (all) */
#define UART_DLL_MASK (0xff) /* Bits 0-7: DLL */
/* Bits 8-31: Reserved */
/* DLM (DLAB =1) Divisor Latch MSB (all) */
#define UART_DLM_MASK (0xff) /* Bits 0-7: DLM */
/* Bits 8-31: Reserved */
/* IER (DLAB =0) Interrupt Enable Register (all) */
#define UART_IER_RBRIE (1 << 0) /* Bit 0: RBR Interrupt Enable */
#define UART_IER_THREIE (1 << 1) /* Bit 1: THRE Interrupt Enable */
#define UART_IER_RXLIE (1 << 2) /* Bit 2: RX Line Interrupt Enable */
/* Bits 3-7: Reserved */
#define UART_IER_ABEOINTEN (1 << 8) /* Bit 8: Enables the end of auto-baud interrupt */
#define UART_IER_ABTOINTEN (1 << 9) /* Bit 9: Enables the auto-baud time-out interrupt */
/* Bits 10-31: Reserved */
#define UART_IER_ALLIE (0x038f)
/* IIR Interrupt ID Register (all) */
#define UART_IIR_INTSTATUS (1 << 0) /* Bit 0: Interrupt status (active low) */
#define UART_IIR_INTID_SHIFT (1) /* Bits 1-3: Interrupt identification */
#define UART_IIR_INTID_MASK (7 << UART_IIR_INTID_SHIFT)
# define UART_IIR_INTID_MSI (0 << UART_IIR_INTID_SHIFT) /* Modem Interrupt */
# define UART_IIR_INTID_THRE (1 << UART_IIR_INTID_SHIFT) /* THRE Interrupt */
# define UART_IIR_INTID_RDA (2 << UART_IIR_INTID_SHIFT) /* 2a - Receive Data Available (RDA) */
# define UART_IIR_INTID_RLS (3 << UART_IIR_INTID_SHIFT) /* 1 - Receive Line Status (RLS) */
# define UART_IIR_INTID_CTI (6 << UART_IIR_INTID_SHIFT) /* 2b - Character Time-out Indicator (CTI) */
/* Bits 4-5: Reserved */
#define UART_IIR_FIFOEN_SHIFT (6) /* Bits 6-7: Copies of FCR bit 0 */
#define UART_IIR_FIFOEN_MASK (3 << UART_IIR_FIFOEN_SHIFT)
#define UART_IIR_ABEOINT (1 << 8) /* Bit 8: End of auto-baud interrupt */
#define UART_IIR_ABTOINT (1 << 9) /* Bit 9: Auto-baud time-out interrupt */
/* Bits 10-31: Reserved */
/* FCR FIFO Control Register (all) */
#define UART_FCR_FIFOEN (1 << 0) /* Bit 0: Enable FIFOs */
#define UART_FCR_RXRST (1 << 1) /* Bit 1: RX FIFO Reset */
#define UART_FCR_TXRST (1 << 2) /* Bit 2: TX FIFO Reset */
/* Bits 3-5: Reserved */
#define UART_FCR_RXTRIGGER_SHIFT (6) /* Bits 6-7: RX Trigger Level */
#define UART_FCR_RXTRIGGER_MASK (3 << UART_FCR_RXTRIGGER_SHIFT)
# define UART_FCR_RXTRIGGER_0 (0 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 0 (1 character) */
# define UART_FCR_RXTRIGGER_4 (1 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 1 (4 characters) */
# define UART_FCR_RXTRIGGER_8 (2 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 2 (8 characters) */
# define UART_FCR_RXTRIGGER_14 (3 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 3 (14 characters) */
/* Bits 8-31: Reserved */
/* LCR Line Control Register (all) */
#define UART_LCR_WLS_SHIFT (0) /* Bit 0-1: Word Length Select */
#define UART_LCR_WLS_MASK (3 << UART_LCR_WLS_SHIFT)
# define UART_LCR_WLS_5BIT (0 << UART_LCR_WLS_SHIFT)
# define UART_LCR_WLS_6BIT (1 << UART_LCR_WLS_SHIFT)
# define UART_LCR_WLS_7BIT (2 << UART_LCR_WLS_SHIFT)
# define UART_LCR_WLS_8BIT (3 << UART_LCR_WLS_SHIFT)
#define UART_LCR_STOP (1 << 2) /* Bit 2: Stop Bit Select */
#define UART_LCR_PE (1 << 3) /* Bit 3: Parity Enable */
#define UART_LCR_PS_SHIFT (4) /* Bits 4-5: Parity Select */
#define UART_LCR_PS_MASK (3 << UART_LCR_PS_SHIFT)
# define UART_LCR_PS_ODD (0 << UART_LCR_PS_SHIFT) /* Odd parity */
# define UART_LCR_PS_EVEN (1 << UART_LCR_PS_SHIFT) /* Even Parity */
# define UART_LCR_PS_STICK1 (2 << UART_LCR_PS_SHIFT) /* Forced "1" stick parity */
# define UART_LCR_PS_STICK0 (3 << UART_LCR_PS_SHIFT) /* Forced "0" stick parity */
#define UART_LCR_BRK (1 << 6) /* Bit 6: Break Control */
#define UART_LCR_DLAB (1 << 7) /* Bit 7: Divisor Latch Access Bit (DLAB) */
/* Bits 8-31: Reserved */
/* MCR Modem Control Register (UART1 only) */
#define UART_MCR_DTR (1 << 0) /* Bit 0: DTR Control Source for DTR output */
#define UART_MCR_RTS (1 << 1) /* Bit 1: Control Source for RTS output */
/* Bits 2-3: Reserved */
#define UART_MCR_LPBK (1 << 4) /* Bit 4: Loopback Mode Select */
/* Bit 5: Reserved */
#define UART_MCR_RTSEN (1 << 6) /* Bit 6: Enable auto-rts flow control */
#define UART_MCR_CTSEN (1 << 7) /* Bit 7: Enable auto-cts flow control */
/* Bits 8-31: Reserved */
/* LSR Line Status Register (all) */
#define UART_LSR_RDR (1 << 0) /* Bit 0: Receiver Data Ready */
#define UART_LSR_OE (1 << 1) /* Bit 1: Overrun Error */
#define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */
#define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */
#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */
#define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */
#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */
#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */
/* Bits 8-31: Reserved */
/* MSR Modem Status Register (UART1 only) */
#define UART_MSR_DELTACTS (1 << 0) /* Bit 0: CTS state change */
#define UART_MSR_DELTADSR (1 << 1) /* Bit 1: DSR state change */
#define UART_MSR_RIEDGE (1 << 2) /* Bit 2: RI ow to high transition */
#define UART_MSR_DELTADCD (1 << 3) /* Bit 3: DCD state change */
#define UART_MSR_CTS (1 << 4) /* Bit 4: CTS State */
#define UART_MSR_DSR (1 << 5) /* Bit 5: DSR State */
#define UART_MSR_RI (1 << 6) /* Bit 6: Ring Indicator State */
#define UART_MSR_DCD (1 << 7) /* Bit 7: Data Carrier Detect State */
/* Bits 8-31: Reserved */
/* SCR Scratch Pad Register (all) */
#define UART_SCR_MASK (0xff) /* Bits 0-7: SCR data */
/* Bits 8-31: Reserved */
/* ACR Auto-baud Control Register (all) */
#define UART_ACR_START (1 << 0) /* Bit 0: Auto-baud start/running*/
#define UART_ACR_MODE (1 << 1) /* Bit 1: Auto-baud mode select*/
#define UART_ACR_AUTORESTART (1 << 2) /* Bit 2: Restart in case of time-out*/
/* Bits 3-7: Reserved */
#define UART_ACR_ABEOINTCLR (1 << 8) /* Bit 8: End of auto-baud interrupt clear */
#define UART_ACR_ABTOINTCLRT (1 << 9) /* Bit 9: Auto-baud time-out interrupt clear */
/* Bits 10-31: Reserved */
/* FDR Fractional Divider Register (all) */
#define UART_FDR_DIVADDVAL_SHIFT (0) /* Bits 0-3: Baud-rate generation pre-scaler divisor value */
#define UART_FDR_DIVADDVAL_MASK (15 << UART_FDR_DIVADDVAL_SHIFT)
#define UART_FDR_MULVAL_SHIFT (4) /* Bits 4-7 Baud-rate pre-scaler multiplier value */
#define UART_FDR_MULVAL_MASK (15 << UART_FDR_MULVAL_SHIFT)
/* Bits 8-31: Reserved */
/* TER Transmit Enable Register (all) */
/* Bits 0-6: Reserved */
#define UART_TER_TXEN (1 << 7) /* Bit 7: TX Enable */
/* Bits 8-31: Reserved */
/* RS-485/EIA-485 Control */
#define UART_RS485CTRL_NMMEN (1 << 0) /* Bit 0: RS-485/EIA-485 Normal Multidrop Mode (NMM) enabled */
#define UART_RS485CTRL_RXDIS (1 << 1) /* Bit 1: Receiver is disabled */
#define UART_RS485CTRL_AADEN (1 << 2) /* Bit 2: Auto Address Detect (AAD) is enabled */
#define UART_RS485CTRL_SEL (1 << 3) /* Bit 3: RTS/DTR used for direction control (DCTRL=1) */
#define UART_RS485CTRL_DCTRL (1 << 4) /* Bit 4: Enable Auto Direction Control */
#define UART_RS485CTRL_OINV (1 << 5) /* Bit 5: Polarity of the direction control signal on RTS/DTR */
/* Bits 6-31: Reserved */
/* RS-485/EIA-485 address match */
#define UART_ADRMATCH_MASK (0xff) /* Bits 0-7: Address match value */
/* Bits 8-31: Reserved */
/* RS-485/EIA-485 direction control delay (UART1 only) */
#define UART_RS485DLY_MASK (0xff) /* Bits 0-7: Direction control (RTS/DTR) delay */
/* Bits 8-31: Reserved */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_UART_H */
arch/arm/src/lpc11xx/hardware/lpc11_wdt.h
-102
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@@ -1,102 +0,0 @@
/************************************************************************************
* arch/arm/src/lpc11xx/hardware/lpc11_wdt.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_WDT_H
#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_WDT_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/lpc11_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register offsets *****************************************************************/
#define LPC11_WDT_MOD_OFFSET 0x0000 /* Watchdog mode register */
#define LPC11_WDT_TC_OFFSET 0x0004 /* Watchdog timer constant register */
#define LPC11_WDT_FEED_OFFSET 0x0008 /* Watchdog feed sequence register */
#define LPC11_WDT_TV_OFFSET 0x000c /* Watchdog timer value register */
/* Register addresses ***************************************************************/
#define LPC11_WDT_MOD (LPC11_WDT_BASE+LPC11_WDT_MOD_OFFSET)
#define LPC11_WDT_TC (LPC11_WDT_BASE+LPC11_WDT_TC_OFFSET)
#define LPC11_WDT_FEED (LPC11_WDT_BASE+LPC11_WDT_FEED_OFFSET)
#define LPC11_WDT_TV (LPC11_WDT_BASE+LPC11_WDT_TV_OFFSET)
/* Register bit definitions *********************************************************/
/* Watchdog mode register */
#define WDT_MOD_WDEN (1 << 0) /* Bit 0: Watchdog enable */
#define WDT_MOD_WDRESET (1 << 1) /* Bit 1: Watchdog reset enable */
#define WDT_MOD_WDTOF (1 << 2) /* Bit 2: Watchdog time-out */
#define WDT_MOD_WDINT (1 << 3) /* Bit 3: Watchdog interrupt */
/* Bits 4-31: Reserved */
/* Watchdog timer constant register */
#define WDT_TC (0x00ffffff) /* Bits 0-23: Watchdog time-out interval */
/* Bits 24-31: Reserved */
/* Watchdog feed sequence register */
#define WDT_FEED_MASK (0xff) /* Bits 0-7: Feed value should be 0xaa
* followed by 0x55 */
/* Bits 14-31: Reserved */
/* Watchdog timer value register */
#define WDT_TV (0x00ffffff) /* Bits 0-23: Watchdog timer value */
/* Bits 24-31: Reserved */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_WDT_H */
arch/arm/src/lpc11xx/lpc111x_gpio.c
-725
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